A method (100) of determining a doping concentration of a semiconductor material (101) includes the steps of moving carriers (102) in the material, wherein a number of carriers is a function of the doping concentration of the material (101). The carriers are deflected (130) toward a surface (110) of the material (101) and an accumulated charge profile on the surface of the material, due to the deflected carriers, is detected (140) and used to calculate (180) the doping concentration across a surface (110) of the material (101).

The fabrication of semiconductor integrated circuits begins with a semiconductor wafer (e.g., silicon) which is often referred to as the "starting material." Typically the starting material is a lightly doped p-type wafer (with an approximate dose of about 5.times.10.sup.14 -1.times.10.sup.15 atoms/cm.sup.2) having a <100> crystal orientation. It is desirable that the doping concentration (atoms/cm.sup.3) be relatively uniform across a single wafer (e.g., within about 1%) and be within a range of about 10.sup.14 to 10.sup.16 atoms/cm.sup.3 and be uniform from wafer to wafer to provide a resistivity of about 2 to 100 .OMEGA.-cm. One of the reasons that the doping level uniformity is important is that the doping level of the wafer (i.e., the substrate for various semiconductor devices) impacts the resultant threshold voltage for transistors built on and in the substrate as well as other transistor device parameters.
When the source and substrate of a transistor are shorted together (V.sub.SB =0), the transistor threshold voltage (V.sub.T) can be characterized by the following equation: EQU V.sub.T =V.sub.TO =.phi..sub.ms -2.phi..sub.f -Q.sub.tot /C.sub.OX -Q.sub.BO /C.sub.OX,
wherein .phi..sub.ms is the work function difference between the gate material and the bulk silicon in the transistor channel, .phi..sub.f is the equilibrium electrostatic potential, Q.sub.BO is the charge stored per unit area (C/cm.sup.2) in the depletion region, C.sub.OX is the gate oxide capacitance per unit area (F/cm.sup.2), and Q.sub.tot is the total positive oxide charge per unit area present at the oxide/bulk interface. .phi..sub.ms, .phi..sub.f and Q.sub.BO are each dependent upon the doping concentration of the starting material, wherein an increase in the doping concentration of the substrate changes the above parameters and results in an increase in the threshold voltage (V.sub.T). Consequently, nonuniform doping concentrations within a wafer and between wafers is undesirable since it results in variations in the resulting transistor threshold voltages for various semiconductor devices.
In addition to it being desirable to provide starting material which provides uniform transistor threshold voltages within a wafer and between wafers, it is also desirable for the starting material to provide a low source/drain-to-substrate capacitance, a high source/drain-to-substrate breakdown voltage, high current mobility and a low sensitivity to source-substrate bias effects. A deviation in the desired doping concentration, however, impacts the above characteristics. For example, an increase in the wafer doping concentration undesirably results in a decrease in the junction breakdown voltage, increases the junction capacitance and lowers the carrier mobility.
Because the wafer doping concentration level and uniformity is an important characteristic, electrical specifications are provided for the starting material which include, for example: the conductivity type of the wafer, the average resistivity or resistivity range (.OMEGA.-cm), the radial resistivity gradient (% variation) and resistivity variations. The conductivity type information includes whether the wafer is an n-type or a p-type wafer and indicates what element was used to dope the wafer (e.g., arsenic, phosphorous, boron, etc.). The wafer resistivity relates to the doping density of the wafer (atoms/cm.sup.3) and is measured using a four-point probe technique. The radial resistivity gradient provides a measure of the variation of the resistivity between the center and selected outer regions of the wafer, and the resistivity variations represent local variations of the resistivity on the wafer. Both the radial resistivity and the resistivity variations are also measured using a four-point probe technique.
The four-point probe technique is used to measure the sheet resistance Rs of a film. The sheet resistance Rs of a film (which in this instance is the wafer) is determined as follows in conjunction with prior art FIG. 1. The resistance (R) of a rectangular shaped film of length (L), width (W) and thickness (t) is given by the equation: EQU R=.rho.L/tW,
wherein .rho. equals the resistivity of the film, which is unique for a given material, and is measured in .OMEGA.-cm. If the length L is equal to the width W, then the rectangle is a square and the equation reduces to:
R=.rho./t=Rs,
wherein Rs is the sheet resistance in .OMEGA./square and is independent of the size of the square (but does depend on the resistivity of the material and the thickness of the film). Therefore the resistivity .rho. and the sheet resistance Rs are distinct parameters that are related by the above equation.
The four-point probe method is illustrated in prior art FIG. 2. If the sample film may be approximated as semi-infinite with respect to the spacings (s) between the four probes (which are spaced apart substantially equally from one another), the current (I) is driven as shown and the voltage drop (V.sub.1 -V.sub.2) is measured across the remaining probes as illustrated in prior art FIG. 2. The sheet resistance may then be calculated according to the following equation: EQU Rs=(V.sub.1 -V.sub.2)(2.pi.s)/It.
To prevent erroneous readings using the four point technique (e.g., due to thermoelectric heating and cooling) the measurement is often performed with current forced in both directions and the two readings are averaged. Further, the test is often performed at several current levels (i.e., I.sub.1, I.sub.2, etc.), until the proper current level is found. For example, if the current is too low, the forward and reverse current readings will substantially differ and if the current is too high, I.sup.2 R heating will result in the measured reading drifting over time. Although the American Society for Testing and Materials (ASTM) provides standards which recommend current levels for a given resistivity range, one may still need to vary the current about the recommended value to achieve the optimum current for an accurate measurement which undesirably takes extra time.
The sheet resistance Rs and the resistivity .rho. are found using the measured results and the equation V/I(2.pi.s), wherein s is the probe spacing. The above equation, however, is only accurate if the sample is semi-infinite with respect to the probe spacings, which is often not an accurate assumption. Thus, the sheet resistance is typically calculated by the relation: EQU Rs=(V/I)F.sub.1,
wherein F.sub.1 is a correction factor which is a function of the average probe distance s and the wafer diameter D (i.e., F.sub.1 =f(s/D)).
Since the four-point probe technique uses a correction factor and occupies a space of at least 3s due to the four probes, the readings are not totally accurate and further represent merely an average resistivity within the region of 3s. Consequently, it would bee desirable to have a method of determining the resistivity of the starting material that provides a more accurate and convenient resistivity reading and a higher resolution mapping of the resistivity across the wafer to thereby determine whether the doping level concentration is sufficiently uniform.

Method of determining the doping concentration across a surface of a semiconductor material


A screening apparatus includes a conveyor (14) pivotally mounted on a wheeled chassis (2) for movement between an extended operational position and a folded transporting position. The conveyor (14) includes an endless belt (16) and a boom frame (20) supporting the belt (16). The boom frame (20) consists of a rear section (24) pivotally mounted on the chassis (2), and a forward section (26) pivotally mounted to the rear section (24). A screen device (54) is pivotally coupled to the conveyor forward section (26), and a hopper (12) is mounted at the rear of the chassis (2).. To erect the apparatus, the conveyor section (26) is swung down to straighten the conveyor (14), and hydraulic rams (30) are operated to raise the conveyor (14) sufficiently to move the screen device (54) by means of a hydraulic ram (66). The rams (30) then raise the conveyor (14) to a desired operational position, and locating pins are inserted through aligned box members in box member assemblies (34) to retain the conveyor (14) in its operational position. The ram (66) is then operated to swing the screen device (54) into its operational position. After use, the screening apparatus is returned to its transporting position by carrying out the aforementioned operations in reverse order.

In a previously proposed screening apparatus, the material to be screened is fed onto the input stage of an elongate conveyor which conveys the material to a screen device for separating the material into particles of different sizes. The separated materials are then either deposited at different locations on the ground, or passed onto associated separate conveyors which convey the particles of different sizes to locations which are remote from one another.
In order to prevent the separated material from becoming inadvertently mixed with the initial unseparated material it is desirable for the separated material to be deposited a reasonable distance from the input stage of the conveyor. Consequently, it is necessary for the conveyor to be of a considerable length, and for this reason difficulties can arise in transporting the screening apparatus on a public highway or for any appreciable distance on site.


When the clock is stopped during a power-down mode, a clock duty-cycle detector asserts a power-down signal. The clock input is filtered to produce an average clock voltage over several clock periods. The average clock voltage is compared to an upper reference voltage to determine when the clock""s duty cycle (high pulse-width percent) is above an upper limit. The average clock voltage is also compared to a lower reference voltage to determine when the clock""s duty cycle is below a lower limit. When the clock""s duty cycle is above the upper limit or below the lower limit the power-down signal is activated by logic. The logic disables the power-down signal when the clock""s duty cycle is between the upper and lower limits. High-frequency clock glitches do not falsely trigger a power-up, since glitches are usually narrow and not sufficiently wide to reach the lower limit.

This invention relates to integrated circuits (IC""s), and more particularly to clock power-down detection.
Low-power and battery-operated electronic systems often are able to power down all or parts of the system to reduce power consumption. Subsystems can be partially powered down by stopping a clock input to the subsystem, or more fully powered down by asserting a power-down or enable input to the subsystem.
FIG. 1 shows a prior-art chip with separate clock and power-down inputs. Chip 10 could be a subsystem such as a memory, or part of a subsystem such as one memory chip on a memory module, or a network controller on a network card. A clock is input to chip 10, and a separate power-down signal is applied to an enable input (xcx9cEN) of chip 10. When the power-down signal is active (high), chip 10 is disabled and its power consumption is reduced. The clock to chip 10 may or may not be stopped.
Oftentimes the number of pins on a chip is limited, and using one of the few available pins for a power-down signal is undesirable. Sometimes the power-down condition can be detected by examining other pins. FIG. 2A shows detecting a stopped clock to power down a chip. Chip 10xe2x80x2 includes frequency detector 12 which receives a clock input to chip 10xe2x80x2, such as a general clock that is used elsewhere in chip 10xe2x80x2.
When the clock input to chip 10xe2x80x2 is stopped, such as when the system wishes to reduce power for the subsystem containing chip 10xe2x80x2, frequency detector 12 detects that the clock has stopped and activates an internal power-down signal. This internal power-down signal disables or shuts off various circuits in chip 10xe2x80x2, reducing its power consumption. Frequency detector 12 may activate the internal power-down signal when the frequency of the clock input falls below a threshold frequency such as 1 kHz, 1 MHz, 10 Hz, or some other value.
A problem can occur when using a frequency detector to detect a slowed or stopped clock. Another nearby clock (NB_CLK) may have a metal trace or wire parallel to the clock input to chip 10xe2x80x2 for a distance on a circuit board. When NB_CLK pulses and CLK_IN is off, a small voltage pulse may be capacitivly coupled into the clock input CLK_IN to chip 10xe2x80x2. FIG. 2B is a waveform showing capacitive coupling of a nearby clock trace that can cause false power-ups. When the nearby clock NB_CLK has a fast rising edge, a pulse can be coupled onto CLK_IN. If this pulse is sufficiently large, it can appear to the frequency detector as a clock pulse. When the frequency of the nearby clock is above the frequency detect threshold, chip 10xe2x80x2 is falsely powered back up by these clock glitches.
To avoid having such small, brief glitches falsely triggering power-up, some filtering can be added to the detector. The frequency detector then requires a certain high pulse width before triggering power-up. FIG. 3A shows a filtered clock detector. Chip 16 receives a clock input CLK_IN, which is applied to the gate of transistor 22 in detector 12xe2x80x2. When the high pulse time of CLK_IN is sufficiently large, transistor 22 discharges capacitor 20 more rapidly than resistor 24 charges it back up. Then node PS falls below the threshold of buffer 18, causing buffer 18 to drive the internal power-down signal low (inactive). When the clock stops, transistor 22 remains off and resistor 24 charges capacitor 20 above the threshold of buffer 18, which then drives the power-down signal high (active).
FIG. 3B is a waveform showing power-down detection when the high pulse is too narrow. When CLK_IN has a high time greater than the minimum, TH greater than TH(min), then the power-down signal remains low as the transistor discharges the capacitor on node PS. However, as the high pulse width decreases further, it falls below the minimum width, and PS is not sufficiently discharged by the transistor. Node PS rises in voltage above the threshold of the buffer, VT, so that the buffer drives the power-down signal PD high to initiate power-down.
Some systems may power-down the clock by leaving it in the high state rather than the low state. In that case transistor 22 remains on, keeping node PS low and preventing buffer 18 from driving the power-down signal high. FIG. 3C is a waveform showing a failure to power down when the clock is held high. The clock input CLK_IN is slowed down or stopped in the high state rather than the low state. The high pulse width is nearly or all of the entire clock period, causing TH greater than TH(min) and meeting the requirement for detecting an active (running) clock. Node PS is discharged by the transistor during the clock-high time, and stays below threshold VT. The power-down signal remains inactive, and the chip does not power down as expected.
What is desired is a clock detector that detects when the clock stops in the high or low state. A clock detector is desired that detects when the clock""s duty cycle is too high or too low and activates a power-down signal. A clock detector that does not falsely power-up a chip when glitches occur on a stopped clock line is desirable, regardless of whether the clock is stopped in the high or low state.

Power down circuit detecting duty cycle of input signal


A magnetostrictive linear displacement detector includes a dual pole magnet assembly. The displacement detector includes a magnetostrictive wire, a return wire and a magnet disposed for displacement along the magnetostrictive wire. A torsional strain sensor at the head end generates an electrical indication of the torsional strain within the magnetostrictive wire induced by passage of an electrical excitation by the position of the magnet. The magnet of this invention is a cylindrical magnetic bipole. The magnet includes two toroidal magnet sections. The first toroidal magnet section has radially disposed magnetic poles with the South pole directed inwardly and the North pole directed outwardly. The second toroidal magnet is a similar radial magnet except that it has its North pole directly inwardly and its South pole directly outwardly. The magnet assembly has a length preferably no more than one half inch. This length should be short in relation to the total length of the measurement range. This dual pole magnet assembly may also be used in a reciprocal system by producing a torsional strain at the head end and detecting an electrical response when the torsional strain passes the dual pole magnet assembly.

The usefulness of the phenomenon of magnetostrictivity in linear distance or position measuring devices is recognized by the prior art; for example, see Redding, U.S. Pat. No. 4,305,283; McCrea et al, U.S. Pat. No. 4,158,964; Krisst, U.S. Pat. No. 4,071,818; Edwards, U.S. Pat. No. 4,028,619; and Tellerman, U.S. Pat. No. 3,898,555. Common to several of these devices are a magnetostrictive wire that runs in a straight line path through the measurement field, means for inducing a torsional strain at a given position along the wire, and a magnet that is displaceable along the wire, either by connection to a movable body such as a machine tool or by reason of association with a float device. Generally speaking, the position of the magnet represents the position of the monitored quantity and is determined as a function of the time required for a torsional strain to propagate from one end of the wire through the area of influence of the magnet or from the position of the magnet to a sensing apparatus located at one end of the wire.
It is known in the art to provide increased position detection sensitivity and cancellation of differential circuit delays using a reflection technique. The magnetostrictive wire has a reflection termination at its foot end and a reflection damping termination at its head end. The position detection is made from the time between the receipt of the direct torsional strain and the receipt of the torsional strain reflected from the foot end. Position resolution is doubled because of the increased propagation path with this technique. In addition, circuit delays in detection of the direct and reflected responses are the same and are effectively canceled out.
There is a problem with this prior art technique. Prior art magnetostrictive position detectors employ a magnet with a single radially disposed pole. The single radially disposed pole magnet of the prior art produces identical torsional strain pulses traveling in both directions. The torsional strain generally has the form of a damped sine wave. The reflection of the torsional strain from the reflection termination inverts its phase. The electrical detector coupled to the transducer thus must detect different portions of the direct and reflected waveforms. It is difficult to provide reliable detection at the same location of the two damped sine waves due to their differing shape. It is possible to provide an electrical phase inversion of the reflected response before detection. However, this negates the advantage of the reflection technique in canceling out delays in the electrical system. This is because the two waveforms must be processed differently and thus could encounter differing delays under differing conditions resulting in potentially unreliable position detection. Therefore there is a need in the art to provide a manner of obtaining the full benefits of the reflection technique.

Magnetostrictive linear position detector and a dual pole position magnet therefor


A server comprises an electronic data item receiving unit, an identification code receiving unit, an identification code storing unit, and an electronic data item transmitting unit. The electronic data item receiving unit receives an electronic data item. When a person exists within a predetermined range from an output terminal, the identification code receiving unit receives a first identification code concerning any one of the person and a device used by the person and a second identification code for identifying the output terminal. The identification code storing unit stores therein the first and second identification codes received by the identification code receiving unit, in association with each other. The electronic data item transmitting unit transmits the electronic data item received by the electronic data item receiving unit to a corresponding output terminal based on the first and second identification codes stored in the identification code storing unit.

1. Field of the Invention
The present invention relates to a server that transmits electronic data to an output terminal, a data output system that includes the server and output terminals, a data output method for outputting electronic data to an output terminal, and an output terminal.
2. Description of Related Art
An increasing number of companies are introducing a free-space office in which each staff member does not have his/her own seat and is allowed to freely sit in any empty seat to work thereat. In the free-space office, however, when a staff member wants to communicate with another staff member, he/she has to find where another staff member stays, because staff members do not have his/her own seats. A possible way to solve this problem is, for example, introduction of a system that uses an IC tag for obtaining information about where a person is, as disclosed in Japanese Patent Unexamined Publication No. 2003-323490.
The system disclosed in the above-mentioned publication is adopted for example in a hospital in order to always know where a patient is. Each patient carries an IC tag which emits an identification code at predetermined intervals, and IC tag readers disposed at various places receive the identification code, to thereby grasp where each patient is.

Server, data output system, data output method, and output terminal


Embodiments of the subject technology provide for predicting seismic impedance. The subject technology generates a corridor stack based on vertical seismic profile (VSP) data of a wellbore in a subterranean formation. The subject technology generates an initial estimate of a velocity model for the subterranean formation below the wellbore. The subject technology generating a density model for the subterranean formation below the wellbore based on information from nearby wells. The subject technology inverts, based on a global inversion algorithm and the initial estimate of the velocity model, the generated corridor stack to determine a set of velocity models. The subject technology generates impedance models in a depth domain based on the generated density model and the set of velocity models. Further, the subject technology stores the generated impedance models.

Vertical Seismic Profile (VSP) analysis is a technique used to conduct geophysical surveys of subterranean features. For example, VSP analysis can be used to image the earth's subsurface in the proximity of a wellbore during the drilling or operation of a well. In an example, one or more seismic energy sources are located at the surface and one or more seismic detectors are located within a wellbore. A seismic profile based on information regarding the subsurface can be determined based on the detection of reflected seismic energy that originates from the seismic energy sources at the surface.
In one or more implementations, not all of the depicted components in each figure may be required, and one or more implementations may include additional components not shown in a figure. Variations in the arrangement and type of the components may be made without departing from the scope of the subject disclosure. Additional components, different components, or fewer components may be utilized within the scope of the subject disclosure.

Prediction ahead of bit using vertical seismic profile data and global inversion


Integrated circuit devices utilizes on-chip power down control circuitry to control the timing of application of at least one external power signal to the device when a functional logic circuit within the device is switching in and out of an inactive mode of operation, such as a sleep mode. During a respective inactive mode, the leakage current characteristics of the respective functional logic circuit are improved by removal of the external power signal. The at least one external power signal may be provided by one or more power transistors operating in response to signals generated by external power transistor control circuitry. These power transistors may provide power to respective power supply pins that are coupled on-chip to the device and the external power transistor control circuitry may be responsive to one or more signals generated by the device.

The present invention relates to integrated circuit devices and, more particularly, to integrated circuit devices having functional logic circuits therein that can be selectively disposed in active and power saving sleep modes of operation.
Integrated circuit devices that are fabricated using deep sub-micron (DSM) process technologies typically include MOS transistors having thinner gate oxides and lower threshold voltages (Vth). The use of DSM process technologies also typically increase device integration. Unfortunately, the achievement of higher integration levels and lower threshold voltages typically results in higher leakage currents because the magnitude of total leakage current is typically directly proportional to integration density and inversely proportional to threshold voltage. Thus, a simultaneous increase in integration density and decrease in threshold voltage can result in significant increases in leakage currents. One conventional technique for reducing total leakage current within an integrated circuit device is to provide MOS transistors having relatively high threshold voltages (xe2x80x9chigh-Vthxe2x80x9d) for some circuits within the device and MOS transistors having relatively low threshold voltages (low-Vth) for other circuits within the device. For example, high-Vth MOS transistors may be used for circuits that are not critical to timing and low-Vth MOS transistors, which typically have greater leakage, may be used for circuits that are critical for timing. Another conventional technique for reducing total leakage current includes use of a body voltage(s) on an integrated circuit chip as a way to increase effective threshold voltages for certain devices therein.
A technique for reducing leakage current is also described in U.S. Pat. No. 6,064,223 to Lu et al., entitled xe2x80x9cLow Leakage Circuit Configuration for Mosfet Circuits.xe2x80x9d In this patent, at least one switchable pathway is provided between an active circuit and a power or ground node. This switchable pathway, which is provided by PMOS transistor 102 and/or NMOS transistor 108 in FIG. 2 of the ""223 patent, is operable to reduce leakage current through the circuit by essentially disconnecting a power supply path from the circuit. One of many limitations with this technique is the requirement 120 that the switchable pathway be sufficiently large to provide a sufficiently low resistance path to the circuit when the circuit is operating in a high current active mode. However, the use of one or more large switchable pathways may, among other things, reduce integrated densities and complicate efficient layout of the circuit. U.S. Pat. No. 6,081,135 to Goodnow et al., entitled xe2x80x9cDevice and Method to Reduce Power Consumption in Integrated Semiconductor Devices,xe2x80x9d reduces power by eliminating unnecessary node toggling. Unneeded Node toggling is reduced by utilizing either a PMOS pull-up transistor or an NMOS pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which a circuit is inactive. In an illustrated embodiment, the inputs to a circuit are all pulled high after a time of inactivity. This time of inactivity is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption may be reduced without excessive power caused by the pulling itself. Unfortunately, this node toggling technique may reduce integration density by requiring significant on-chip timing and node pulling circuitry.
Thus, notwithstanding these conventional techniques to reduce leakage currents in highly integrated circuits, there continues to be a need for improved techniques that provide efficient current leakage control and do not require extensive on-chip circuitry.
An integrated circuit device according to one embodiment of the present invention utilizes on-chip power down control circuitry to control the timing of application of at least one external power signal to the device when a functional logic circuit within the device is switching in and out of an inactive mode of operation, such as a sleep mode. The at least one external power signal may be provided by one or more power transistors operating in response to signals generated by external power transistor control circuitry. These power transistors may provide power to respective power supply pins that are coupled on-chip to the device and the external power transistor control circuitry may be responsive to one or more signals generated by the device.
In particular, an integrated circuit device is preferably provided having at least one internal (e.g., on-chip) functional logic circuit therein. This internal functional logic circuit may be configurable in a respective active mode of operation or a power-saving sleep mode of operation. The internal functional logic circuit may also include an output at which a respective sleep mode request can be generated. In this case, the internal functional logic circuit may include circuitry that enables the functional logic circuit to generate its own sleep mode request. Functional logic circuits that are capable of generating their own sleep mode request include microprocessor, cache and LCD controller. According to other embodiments, a sleep mode request for a respective internal functional logic circuit may be generated external to the functional logic circuit. Such requests may be generated by other on-chip circuitry or circuitry located external to the device. The device is also preferably provided with an internal (i.e., on-chip) power control logic circuit that generates one or more power down signals. The power down signals may be provided to the external power transistor control circuitry and may be generated in direct response to the sleep mode request.
According to another embodiment of the present invention, an integrated circuit device comprises a plurality of internal functional logic circuits having respective active and power-saving sleep modes of operation. These internal functional logic circuits have first outputs at which respective sleep mode requests are generated. An internal power control logic circuit is also provided. This internal power control logic circuit generates respective power down signals in response to the sleep mode requests generated at the first outputs. These power down signals are provided external to the device. The device may also include a plurality of power supply pads that receive a respective plurality of external power supply signals, with each of the plurality of external power supply signals being provided to a respective one (or more) of the plurality of internal functional logic circuits. In particular, the power down signals generated by the internal power control logic circuit are preferably provided to external power switching circuitry that is electrically coupled to the plurality of power supply pads. The logic value of each of the power down signal can be used to influence whether the external power switching circuitry provides power to or withholds power from respective power supply pads.
According to a preferred aspect of this embodiment, the external power switching circuitry includes a power transistor control circuit that is responsive to the power down signals and a plurality of power transistors that are coupled to the power transistor control circuit and generate the external power supply signals. Moreover, the internal power control logic circuit may comprise an active mode restart control circuit having an output at which respective active restart signals are generated. Each of the plurality of internal functional logic circuits may be responsive to a respective active restart signal generated by the active mode restart control circuit. The logic value of the active restart signal can be used to control whether a respective functional logic circuit is switched from an active mode of operation to a sleep mode of operation and vice versa.
An additional embodiment of the present invention may include a system of integrated circuits. This system may include an integrated circuit chip and power switching circuitry that is located external to the integrated circuit chip. In this embodiment, a device on the chip preferably includes an internal functional logic circuit and an internal power control logic circuit. The internal functional logic circuit has two modes of operation. These two modes of operation include a normal active mode of operation and a power-saving sleep mode of operation, which can be initiated in response to a sleep mode request. The sleep mode request may be generated by the internal functional logic circuit or another circuit internal to the device. The sleep mode request may also be generated external to the device. The internal power control logic circuit performs operations to generate a power down signal in response to the sleep mode request. An active/sleep mode power supply pad is also preferably provided on the integrated circuit chip and this pad is preferably electrically coupled to the internal functional logic circuit. External power switching circuitry is also provided. The power switching circuitry selectively provides power to or withholds power from the active/sleep mode power supply pad in response to the power down signal generated by the internal power control logic circuit. The power switching circuitry may comprise a power transistor control circuit that is responsive to the power down signal and a power transistor that is electrically coupled to the power transistor control circuit and electrically coupled to the active/sleep mode power supply pad.

Integrated circuit devices having power control logic that inhibits internal leakage current loss during sleep mode operation and method of operating same


A boot having a shoe shaped shell member and a cuff member having a section overlapping the shell member. The cuff and shell members are pivotally connected together for pivoting movement in response to pivoting of the individual's leg relative to the individual's foot. An elastomeric material is disposed between said shell member to pivotally connect the two members together.

Plastic footwear such as ski boots and boots for skates, collectively referred to herein as boots, are usually comprised of two, three or four parts necessary to permit flexing of the ankle forward and backwards while retaining lateral support for performance. These plastic parts are normally connected with metal rivets, permitting swiveling or rotation around the location of the rivets. Plastic is commonly used and the parts are formed by such methods as injection molding. The boot provides protection to the foot and lower leg and adds sufficient stiffness to permit good performance such as in ski boots where lateral support is necessary for various ski maneuvers.
It is necessary when skiing or skating to permit the skier or skater to bend his or her knees in the forward direction and to encounter various resistance as the knee is bent further forward, eventually coming to a stop, before damage occurs to the Achilles tendon. This requires fairly precise fit of the plastic pieces and careful placement of rivets or other pivoting means to provide for comfort and performance at the same time.
Normally a boot of the above described type has a lower shell having a heel, middle and front section for receiving and supporting an individual's foot along the heel, bottom, sides and top front portion of the foot. The boot may also include a cuff which covers the upper portion of the foot or lower leg. The cuff is the part which rotates forward when the knee is bent. Additionally, many boots have tongues or rear portions which permit exit and entry in the case of front-entry or rear-entry boots.
Conventionally constructed boots utilizing rivets are limited in that the cuff or other plastic parts attached to the lower shell must rotate around a fixed point. This is not necessarily compatible with the human foot, which has a semi-sliding joint in the ankle rather than one which pivots from a point between the ankle bones.

Elastometric connecting means for footwear


A single poly electrical erasable programmable read only memory (EEPROM) includes a source, a drain, a dielectric layer and an electrode layer. The source and the drain are located in a substrate, wherein the source and the drain have a first conductive type. The dielectric layer is disposed on the substrate and between the source and the drain, wherein the dielectric layer includes a first dielectric layer having two tunnel dielectric parts separating from each other, and thicknesses of the two tunnel dielectric parts are thinner than thicknesses of the other parts of the first dielectric layer. The electrode layer is disposed on the dielectric layer, wherein the electrode layer includes a first electrode disposed on the first dielectric layer, thereby the first electrode being a floating gate.

1. Field of the Invention
The present invention relates generally to a single poly electrical erasable programmable read only memory (EEPROM), and more specifically to a single poly electrical erasable programmable read only memory (EEPROM) including two tunnel dielectric parts.
2. Description of the Prior Art
An EEPROM (electrically erasable programmable read only memory) provides excellent performance. Thanks to voltages required for programming and erasing being self-generated, only an external source is required for operation. Programming and erasing is carried out in each memory cell for recording a bit data. Charges can be trapped in a floating gate and thus the characteristic of each memory cell can be changed to store data bit "0" or data bit "1". Each memory cell consists of two MOS transistors, wherein one storage transistor having a floating gate is used for trapping charges while the other access transistor is used for operation. Proper bias voltages are applied while programming and erasing the EEPROM (electrically erasable programmable read only memory). For instance, while the EEPROM (electrically erasable programmable read only memory) is erased, charges are injected into the floating gate, and the transistor stores a data bit "1"; while the EEPROM (electrically erasable programmable read only memory) is programmed, charges are removed from the floating gate, and the transistor stores a data bit "0".
For programming and erasing the EEPROM (electrically erasable programmable read only memory), a tunneling dielectric layer must be disposed between a substrate and the floating gate, thereby charges being trapped in or removed from the floating gate through the tunneling dielectric layer while applying proper bias voltages. Thus, the structure, the material and the charge tunneling frequency of the tunneling dielectric layer affect life time of the EEPROM (electrically erasable programmable read only memory). Specifically, these properties affect life time of the EEPROM (electrically erasable programmable read only memory) in a high temperature atmosphere.

Single poly electrical erasable programmable read only memory (EEPROM)


A bearing assembly for a rotary shaft machine, the assembly comprising a ball or rotary bearing mounted between a bearing support and the shaft, the bearing comprising an outer ring and an inner ring between which rolling elements are interposed, the outer ring being held rigidly to the support, the inner ring and the shaft being slidable relative to each other, the bearing assembly further comprising at least one washer mounted between the inner ring and a shoulder of the shaft and exerting force between the inner ring and the shoulder tending to move them apart to take up operating slack, wherein the washer presents a flat annulus and a plurality of trapezium-shaped resilient tabs extending radially from the annulus, each presenting a portion that is inclined relative to the plane of the annulus and each being terminated by an end flat parallel to the plane of the annulus.

A particularly advantageous application lies in the back bearing assemblies of alternators for motor vehicles.
Generally, the bearing proper of a bearing assembly is held against a support by means of capsules or washers made of plastic or of additional elements made of steel (e.g. a stop ring). Throughout the present specification, the term "alternator back bearing assembly" is used to mean the bearing assembly situated on an alternator at its end remote from the drive thereto.
Various solutions attempt to reconcile operating stiffness (axial support for the shaft) and ease of installation.
Nevertheless, the slack necessary during assembly and for operation without applying stress on the bearing is itself damaging and can lead to several types of defect under the effect of vibration at high speed.
In particular, the outer ring of the bearing can be subjected to rotation that causes the bearing assembly to be destroyed.
Also, axial slack in the bearing and vibration at high speed can cause the rolling paths on the rings to be destroyed.
The vibration and hammering due to such slack can also give rise to premature wear of the bearing and its housing in the bearing support.
Document FR-A-1 135 722 describes a bearing assembly for a rotary shaft machine, which assembly includes a ball or roller bearing mounted between a support and the shaft. The outer ring of the bearing is rigidly fixed to the support while the inner ring is capable of sliding relative to the shaft. A column made up of two plate-springs is interposed between the inner ring and a shoulder on the shaft for the purpose of exerting a force tending to move them apart so as to take up the operating axial slack. Nevertheless, plate-springs are very stiff in that they exhibit significant resilience only when subjected to high stresses. As a result, the axial slack is taken up only at the price of applying large axial stresses on the parts, and that is harmful to good operation of the bearing assembly.

Ball or roller bearing assembly, in particular a back bearing assembly for a motor vehicle alternator


An information handling system particularly suitable for motor vehicle use. A master station is arranged to transmit information to, and to receive and display information from, a plurality of sequentially-addressed peripheral stations. Synchronization and clock signals, as well as information control signals, are transmitted by the master station to the various peripheral stations, each of which responds to a particular information frame. An address code determines the information frame to which a given peripheral station responds. The peripheral station may control devices actuated by connection to a power bus or sensors from which information is obtained and transmitted to the master station for display.

This invention relates to a multiplex communication system and is particularly, but not exclusively, intended for use in motor vehicles.
Conventional practice in motor vehicles has been to provide each powered device (light, horn, windscreen wiper motor, etc.) with its own power lead and associated driver's control switch, and to provide a number of warning and indicating instruments (fuel gauge, tachometer, oil pressure warning, etc.) each connected to an appropriate sensor by separate wiring. This gives rise to wiring looms of considerable complexity and cost. It is also necessary to fabricate and stock different wiring harnesses for each model of vehicle.
There have hitherto been a considerable number of proposals to overcome these problems by using a common channel interconnecting all electrically powered devices and monitoring devices with a central control station, information being passed along the channel by multiplexing techniques. None of these proposals has yet been put into practice in volume vehicle production, principally for reasons of cost, and/or complexity. The factors which can be identified as necessary for a commercially viable system are:
(a) the system must be mechanically simple and robust;
(b) the number of different components required must be kept to a minimum;
(c) the system must be sufficiently fast to maintain information such as road and engine speed sufficiently up to date in real time for the purposes of the driver;
(d) it must be possible to control at least 50 functions and to receive information from a similar number of sensors; and
(e) there must be signal security which prevents spurious signals caused by interference effecting erroneous operation of controlled devices.
Of the systems previously proposed, some have been too slow or have too small a channel capacity to be suitable for use in vehicles, while others have achieved the required speed and channel capacity by using long trains of pulses at high repetition rates which requires the use of high frequency components with attendant expense. Other systems are unsuitable because they require a number of signal-carrying conductors, which increases cost and the risk of incorrect connection.


A fabricating method of organic electronic device is provided. The method comprises: providing a flexible substrate; fabricating a plurality of organic elements on the flexible substrate; fabricating a patterned spacing layer on the flexible substrate; and arranging a cover substrate on the patterned spacing layer, and sealing the edges of the flexible substrate and the cover substrate with a sealant, wherein the patterned spacing layer is used to maintain a space between the flexible substrate and the cover substrate.

1. Field of Invention
The present invention relates to a method of fabricating an electronic device. More particularly, the present invention relates to a method of fabricating an organic electronic device.
2. Description of Related Art
With the improvement of semiconductor processing techniques, many electronic devices are now fabricated on silicon substrates with semiconductor processes. In terms of flat displays, the required elements are fabricated on glass substrates with semiconductor processes. However, silicon substrates and glass substrates are both hard substrates, thus the electronic devices produced cannot be bent. To make electronic devices lighter, thinner, and flexible, flexible substrates such as plastic substrates have been used in the fabrication of electronic devices.
Besides, as for the material selection of electronic devices, now some electronic devices can be fabricated with organic materials, for example, organic thin film transistors (OTFTs). In comparison with traditional inorganic transistors, OTFTs can be fabricated at a low temperature, so lighter, thinner, and cheaper plastic can substitute glass to function as the substrate. Meanwhile, plastic substrates are advantageous as they are flexible. Furthermore, the OTFT process is simple. By directly patterning organic thin films with printing techniques, the number of required masks and vacuum evaporation apparatus can be reduced. In addition, the manufacturing cost can be greatly reduced because OTFT process is suitable for plastic substrates and is highly compatible with the roll-to-roll process.
However, in a traditional flat display employing OTFTs and plastic substrates, the electronic elements are sealed between two plastic substrates with a sealant at their edges. In this case, when the flat display is flexed, electronic elements will be easily in contact with the plastic substrates, and problems of scratching, wear, and even damage will be occurred since a fixed space cannot be maintained between the two plastic substrates.

Method of fabricating organic electronic device

Industrial Technology Research Institute


An in-line skating device of a roller skate has a base which is fastened to the sole of a boot of the roller skate is fastened pivotally with a wheel carrier. The wheel carrier is provided with a plurality of wheels pivoted thereto in sequence. The carrier is formed of at least two pairs of carrying plates. Two carrying plates of each pair are connected in a parallel manner and are pivoted in the longitudinal direction. The wheels are respectively pivoted between the two carrying plates. The pivoting point of two adjoining carrying plates is located on the axle of one of the wheels. When the base turns in relation to the carrier, the carrying plates of one pair displace in relation to the carrying plates of other pair, thereby enabling the wheels pivoted to the carrying plates of one of the pairs to remain in contact with the ground surface so as to enable the roller skate to be started swiftly at a fast pace.

The present invention relates generally to a roller skate, and more particularly to an in-line skating device enabling the roller skate to start swiftly at a fast pace and having means for braking the roller skate in motion in a smooth and gentle manner.
The conventional in-line skating device of the roller skate comprises a plurality of wheels, which are uniformly pivoted to a sole plate. The device is defective in design in that it prevents the roller skate from being started promptly or suddenly at a fast pace in view of the fact that some wheels can not be maneuvered to remain in contact with the ground while other wheels have left the ground. As a result, a roller skater must resort to all wheels or the front wheel to start the roller skate. It is conceivably difficult to start the roller skate swiftly by means of all wheels because of a considerable friction force that has to be overcome. On the other hand, it is also difficult to start the roller skate rapidly by the front wheel which does not afford a sufficient impetus.
An improved in-line skating device is disclosed by the WO 96136408 patent and is used to fasten pivotally the base of the boot with the carrier of the wheels. The base is provided with a brake shoe, which is put into action at the time when the base turns in relation to the carrier. The device is defective in design in that the braking action is apt to jam the wheels in motion.
The primary objective of the present invention is to provide a roller skate with an in-line skating device which is free from the deficiencies of the prior art devices described above.
The device of the present invention comprises a base and a wheel carrier fastened pivotally with the base. The base is fastened to the sole of a boot. The wheel carrier is formed of two pairs of carrying plates. Two carrying plates of each pair are connected with each other in a parallel fashion. Each wheel is pivoted between the two carrying plates. The carrying plates of each pair are pivoted together in sequence lengthwise. The pivoting point of two adjoining pairs of the carrying plates is located on the axle of one of the wheels. When the base turns in relation to the wheel carrier, one pair of the carrying plates displace in relation to other pair of the carrying plates, thereby enabling the wheel which is pivoted to one pair of the carrying plates to make contact with the ground.
The base of the device of the present invention is provided at one end with a braking mechanism comprising an arresting wheel which is capable of arresting the corresponding wheel at such time when the base turns in relation to the wheel carrier. As a result, the roller skate in a gliding motion can be slowed down or stopped stably and gently by the braking mechanism.


A dental laser assembly having a housing with a first and second laser cavity. The housing also includes an optical output port and a dental optical delivery system optically connected to the port. A first laser is contained within a first laser cavity which, when activated, generates a first laser beam while, similarly, a second laser is contained within a second laser cavity which, when activated, generates a second laser beam. Only one laser, however, is activated at a given time and the output beam from the activated laser is directed to the optical output port in the housing for use in dental applications. The first laser has optical qualities sufficient to perform a first set of dental procedures while the second laser has optical qualities sufficient to perform a second and different set of dental procedures.

I. Field of the Invention
The present invention relates generally to medical laser systems and, more particularly, to a dental laser assembly having two lasers for use in different dental applications.
II. Description of the Prior Art
There are numerous previously known lasers which have been used in a number of different medical applications. For example, a YAG laser has been previously used in cataract surgery for opening opacified lenses or capsules in the eye. Similarly, other lasers have been used in various surgical applications, such as brain surgery.
The use of lasers in dentistry is a presently evolving field in which the inventors are intimately involved. Dental applications using lasers include not only the removal of incipient carious lesions and/or stains on the outer surface of the tooth, but also the removal of dentin, enamel as well as diseased mouth tissue. This diseased mouth tissue includes, for example, diseased gum tissue as well as diseased nerve tissue in endontic procedures.
It has been found that lasers having different optical qualities are best suited for different medical applications. For example, YAG lasers having certain energy levels, pulse durations, wave lengths and the like are used in cataract surgery Conversely, continuous wave CO.sub.2 lasers having different wave lengths and different power levels are used in different types of medical applications, such as surgical applications. Furthermore, the use of a CO.sub.2 continuous laser would be completely inappropriate for use in cataract surgery and, similarly, a YAG laser is not as effective for use in certain surgical medical procedures.
Consequently, it has been the previous practice to design a separate and independent laser for each type of medical procedure desired. This practice, however, disadvantageously increases the overall cost of medical equipment when two or more lasers are necessary in order to perform different medical procedures. In addition, if a complex procedure requires two different lasers for sequential steps in the procedure, the convenience of not having to move two laser systems would be valuable.
For example, one type of laser having certain optical qualities is sufficient for certain medical procedures, such as removing incipient carious lesions and/or stain from the surface of teeth. Conversely, a laser having different optical qualities is necessary in order to perform other medical procedures, such as eradicating enamel and dentin. For soft gum tissue as well as diseased nerve tissue in endontic applications, one or the other of the lasers may be appropriate. Consequently, in order for a dental office to be fully laser equipped, it would be necessary to have two independent lasers, one laser for certain procedures and a separate laser for other procedures.


An optical time-domain reflectometer (OTDR) having a light-emitting element, a branching section, a light-receiving section, and a processing section. The light-emitting element emits pulsating measuring light when driven. The branching section applies the measuring light emitted from the light-emitting element, to an optical fiber to be measured, and branches the light supplied from the optical fiber. The light-receiving section receives the light branched by the branching section and detects a level of the light received. The processing section detects a level of the light supplied from the optical fiber after the OTDR is connected to the optical fiber, while not driving the light-emitting element. The processing section drives the light-emitting element only when the level of the light received is equal to or lower than a preset value.

This application is a U.S. National Phase Application under 35 USC 371 of International Application PCT/JP00/06025 (not published in English) filed Sep. 6, 2000.
This invention relates to an optical time-domain reflectometer (hereinafter referred to as xe2x80x9cOTDRxe2x80x9d) that is use search for defective points in an optical fiber. More particularly, the invention relates to an OTDR that does not influence the communication via the line during measuring.
As is known, an OTDR is connected to one end of an optical fiber and applies a pulsed light beam into the optical fiber from the end thereof. The OTDR measures the time that lapses until reflected light (backscattered light) arrives from the optical fiber, the level of the reflected light and the like. The losses in the optical fiber, the positions where the losses occur (e.g., connection points), the positions of far ends, and the like are thereby determined.
FIG. 6 is a diagram showing how optical fibers are laid and how the various characteristics of the optical fibers are measured by a conventional technique.
On a panel 30 a port is provided for a plurality of optical fibers F. Of the fibers F, one line is used to achieve communication (i.e., an active line) is connected to a transmitter 32a and a receiver 32b.
For convenience, only one core line of the optical fiber F, or active line, is illustrated in FIG. 6. In practice, many lines of the optical fiber F serve as active lines.
An OTDR 31 is connected to one of the optical fibers F that are not used, that is, those other than the active lines, in order to perform various measurements on that optical fiber F.
The core line that is used as an active line is known and identified with the core-line number and the like. The OTDR 31 is therefore connected to a port of a core-line number not assigned to the active line.
The core-line number may be mistaken for another and the measuring may be started. In this case, measuring light (pulsed light) is applied into the core of the active line through which communication is being achieved. This may influence the communication.
Also, the waveform of the measuring signal changes to an abnormal one. Consequently, normal measuring of characteristics may not be accomplished.
The panel 30 has hundreds of ports or thousands of ports. Almost all ports are in connected state, no matter whether they are used for active lines. To initiate measuring, the ports are disconnected and connected to the OTDR. Hence, one core-line number may be mistaken for another, as mentioned above.
Once the port of any active line is disconnected, the light being used is no longer applied, inevitably causing a problem. In this condition, any port that is not of any active line can be identified, only by the core-line number allocated to the port. This may cause a mistake.
In some cases, a measuring port 33 is provided at a position different from the position where the panel 30 is arranged.
The measuring port 33 is connected to each core line of the fiber F by means of a coupler (not shown) or the like. The port 33 is used during the measuring only; it is usually opened.
Once the OTDR 31 is connected to the measuring port 33 to effect measuring, the core line of the fiber F, which is connected to the transmitter 32a and receiver 32b, cannot be visually detected.
When light is applied to the core line of a wrong number, thereby starting the measuring, the measuring signal will immediately enter the communication line, adversely influencing the communication. In addition, the measuring side will be affected, resulting in an abnormal waveform and the like.
The present invention has been made in order to solve the problems described above. The object of the invention is to provide an OTDR which prevents various measuring of an active line effecting communication, which influences neither the communication line nor the measuring and which can therefore perform measuring in safety.
According to one aspect of the invention, there is provided an OTDR having:
a light-emitting element (2b) for emitting pulsating measuring light when driven;
branching means (3) for applying the measuring light emitted from the light-emitting element, to an optical fiber to be measured, and branching light supplied from the optical fiber; and
light-receiving means (11) for receiving the light branched by the branching means and detecting a level of the light received.
The OTDR further comprises processing means for detecting a level of the light supplied from the optical fiber after the OTDR is connected to the optical fiber, while not driving the light-emitting element, and for driving the light-emitting element only when the level of the light received is equal to or lower than a preset value.
According to another aspect of this invention, there is provided an OTDR comprising:
light source driving means;
a light source for emitting pulsating measuring light when driven by the light source driving means;
branching means for applying the measuring light emitted from the light source, to an optical fiber to be measured, and branching light supplied from the optical fiber;
light-receiving means for receiving the light branched by the branching means and detecting a level of the light received;
determining means for causing the light-receiving means to detect the level of light received while the light source is not emitting light and for determining that the optical fiber is not serving as a communication line, only when the level of light received is equal to or lower than a preset value; and
processing means for causing the light source driving means to drive the light source, thereby to start the measuring of the optical fiber, when the determining means determines that the optical fiber is not serving as a communication line.
According to a further aspect of the invention, there is provided a method of measuring an optical fiber by use of an optical time-domain reflectometer, the method comprising the steps of:
providing a light source that emits pulsating measuring light when driven by light source driving means;
providing branching means for applying the measuring light emitted from the light source, to an optical fiber to be measured, and branching light supplied from the optical fiber;
providing light-receiving means for receiving the light branched by the branching means and detecting a level of the light received;
causing the light-receiving means to detect the level of light received while the light source is not emitting light and determining that the optical fiber is not serving as a communication line, only when the level of light received is equal to or lower than a preset value; and
causing the light source driving means to drive the light source, thereby to start the measuring of the optical fiber, when it is determined that the optical fiber is not serving as a communication line.

Optical time-domain reflectometer capable of determining when a test of an optical fiber should be conducted


Disclosed herein is a method of fabricating a capacitor. The method includes the steps of: forming a Ti1xe2x88x92xHfxN layer on a substrate, wherein x is in a range from 0 to 0.5; forming an electrode layer on the Ti1xe2x88x92xHfxN layer; and forming a HfO2 layer on an interface between the electrode layer and the Ti1xe2x88x92xHfxN layer by performing a thermal treatment in an oxygen gas-containing atmosphere.

1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the invention relates to a method for fabricating a capacitor thereof.
2. Brief Description of Related Technology
As an integration of a semiconductor device becomes higher recently, studies are conducted to increase the charge storage area by forming a capacitor in a complicated structure such as a cylinder, fin, stack or hemispheric silicon (HSG) to secure sufficient capacitance. In addition, a dielectric layer of capacitor is formed of materials HfO2, Al2O3, Ta2O5, SrTiO3, (Ba,Sr)TiO3, BLT, etc., of which dielectric constants are higher than SiO2 or Si3N4. In particular, a hafnium oxide (HfO2) layer is a high dielectric layer currently studied for a gate insulation layer and a dielectric layer of a capacitor.
FIGS. 1A to 1C are cross-sectional views illustrating a conventional method for fabricating a capacitor.
Referring to FIG. 1A, an inter-layer dielectric layer (ILD) 12 is formed on a surface of a semiconductor substrate 11 having transistors and bit lines, and a storage node contact mask (not shown) is formed on inter-layer dielectric layer (ILD) 12. After that, a storage node contact hole is formed to expose a predetermined area of the surface of the semiconductor substrate 11 by etching the inter-layer dielectric layer 12 with the storage node contact mask.
Subsequently, a polysilicon layer is formed on the entire surface including the storage node contact hole, and then an etch-back process is carried out in order to form a polysilicon plug 13 in the contact hole to a predetermined depth.
After that, a titanium silicide (TiSi2) 14 and a titanium nitride (TiN) layer 15 are formed on the polysilicon plug 13. The TiSi2 layer 14 forms an ohmic contact with a following bottom electrode, and the TiN layer 15 serves as an anti-diffusion layer that prevents oxygen remaining inside the bottom electrode from diffusing into the polysilicon plug 13, the storage node contact plug, or into the semiconductor substrate 11.
Referring to FIG. 1B, a sacrificial oxide layer 16 that determines the height of the bottom electrode is formed on the inter-layer dielectric layer 12 and the TiN layer 15, and then a storage node mask (not shown) using a photoresist is formed on the sacrificial oxide layer 16.
Subsequently, the sacrificial oxide layer 16 is selectively etched with the storage node mask to form an opening in which a bottom electrode is aligned on the polysilicon plug 13 to be formed.
Thereafter, a bottom electrode 17 is formed of metal over the surface of the sacrificial oxide layer 16 including the opening. After that, the bottom electrode is made to remain in the opening only through the process of etch-back or chemical mechanical polishing method so that the bottom electrode in the concavity is isolated from the neighboring bottom electrodes.
Referring to FIG. 1C, on the entire surface including the bottom electrode 17, a dielectric layer 18 and a top electrode 19 are formed successively. Here, the bottom electrode 17, dielectric layer 18 and top electrode 19 are formed by the chemical vapor deposition (CVD) method, and the dielectric layer 18 is mostly made of a high dielectric layer, such as HfO2.
In the conventional method described above, a capacitor is formed connected to a plug by using a storage node contact mask.
However, in a dynamic RAM (DRAM) over 4 Gbits that a fine design rule should be applied to, the storage node contact plug and the bottom electrode should not be misaligned. Also, to secure a sufficient capacitance, the height of the bottom electrode should be increased. This is a difficult because the plug height for interconnection becomes higher as the height of the bottom electrode gets higher. In addition, because the isolation gap from the neighboring bottom electrode is reduced, the current technology forming a bottom electrode, dielectric layer and top electrode by the CVD method has reached its limitation, so an atomic layer deposition (ALD) method is under development recently.
However, the ALD method has a shortcoming that an extra thermal treatment, or plasma treatment should be performed in every step to improve the quality of the layers. This is because the ALD method conducts depositions at a low temperature to improve the step coverage. Due to such complicated processes and investment for new equipments, the production costs are high for the ALD method.
It would be desirable to provide a method for fabricating a capacitor that avoids a rise in the production cost and complexity in production processes caused by performing a deposition and a subsequent treatment thereof whenever a layer is formed.
It also would be desirable to provide a method for fabricating a capacitor that avoids a misalignment in masking or etching processes for connecting transistors and the capacitor.
Accordingly, disclosed herein is a method of fabricating a capacitor, comprising the steps of: (a) forming a Ti1xe2x88x92xHfxN layer on a substrate, wherein x is in a range from 0 to 0.5; (b) forming an electrode layer on the Ti1xe2x88x92xHfxN layer; and, (c) forming a HfO2 layer on an interface between the electrode layer and the Ti1xe2x88x92xHfxN layer by performing a thermal treatment in an oxygen gas-containing atmosphere. Such a capacitor will include a bottom electrode formed from the Ti1xe2x88x92xHfxN layer, a dielectric layer formed from the HfO2 layer, and a top electrode formed from the electrode layer.
Also disclosed herein is a method for fabricating a capacitor, comprising the steps of: (a) forming an inter-layer dielectric layer on a silicon semiconductor substrate; (b) forming a contact hole that exposes a surface of the semiconductor substrate by selectively etching the inter-layer dielectric layer; (c) forming a Ti1xe2x88x92xHfxN layer in the contact hole, wherein x is in a range from 0 to about 0.5; (d) forming an electrode layer on the Ti1xe2x88x92xHfxN layer; and forming a HfO2 layer on an interface between the electrode layer and the Ti1xe2x88x92xHfxN layer by performing a thermal treatment in an oxygen atmosphere. Such a capacitor will include a bottom electrode formed from the Ti1xe2x88x92xHfxN layer, a dielectric layer formed from the HfO2 layer, and a top electrode formed from the electrode layer.

Method of fabricating capacitor having hafnium oxide


Systems, devices, and methods for producing a three-dimensional visualization of a drill plan and drilling motor with a toolface are provided for drill steering purposes. A drilling motor with a toolface in communication with a sensor system is provided. A controller in communication with the sensor system is operable to generate a depiction of the drill plan and a depiction of the drilling motor, and to combine these depictions in a three-dimensional visualization of the downhole environment. This visualization is used by a user to steer the drill.

At the outset of a drilling operation, drillers typically establish a drilling plan that includes a target location and a drilling path to the target location. Once drilling commences, the bottom hole assembly (BHA) may be directed or "steered" from a vertical drilling path in any number of directions, to follow the proposed drilling plan. For example, to recover an underground hydrocarbon deposit, a drilling plan might include a vertical bore to a point above the reservoir, then a directional or horizontal bore that penetrates the deposit. The operator may then follow the plan by steering the BHA through the vertical and horizontal aspects in accordance with the plan.
In slide drilling implementations, such directional drilling requires accurate orientation of a bent housing of the downhole motor. The bent housing is set on surface to a predetermined angle of bend. The high side of this bend is referred to as the toolface of the BHA. In such slide drilling implementations, rotating the drill string changes the orientation of the bent housing and the BHA, and thus the toolface. To effectively steer the assembly, the operator must first determine the current toolface orientation, such as via measurement-while-drilling (MWD) apparatus. Thereafter, if the drilling direction needs adjustment, the operator must rotate the drill string to change the toolface orientation. In rotary steerable system implementations, the operator still must determine the current toolface orientation.
During drilling, a "survey" identifying locational and directional data of a BHA in a well is obtained at various intervals. Each survey yields a measurement of the inclination angle from vertical and azimuth (or compass heading) of the survey probe in a well (typically 40-50 feet behind the total depth at the time of measurement). In directional wellbores, particularly, the position of the wellbore must be known with reasonable accuracy to ensure the correct steering of the wellbore path. The measurements themselves include inclination from vertical and the azimuth of the well bore. In addition to the toolface data, and inclination, and azimuth, the data obtained during each survey may also include hole depth data, pipe rotational data, hook load data, delta pressure data (across the downhole drilling motor), and modeled dogleg data, for example.
These measurements may be taken at discrete points in the well, and the approximate path of the wellbore may be computed from the data obtained at these discrete points. Conventionally, a standard survey is conducted at each drill pipe connection, at approximately every 90 feet, to obtain an accurate measurement of inclination and azimuth for the new survey position.
When deviation from the planned drilling path occurs, drillers must consider the information available to them and then direct the drill back to the original path. This typically requires the operator to manipulate the drawworks brake and rotate the rotary table or top drive quill to find the precise combinations of hook load, mud motor differential pressure, and drill string torque, to properly position the toolface. This can be difficult, time consuming, and complex. Each adjustment has different effects on the toolface orientation, and each must be considered in combination with other drilling requirements to drill the hole. Thus, reorienting the toolface in a bore is very complex, labor intensive, and often inaccurate. Furthermore, information required to steer the drilling BHA is generally transmitted to the operator in a textual format in conventional systems. An operator must consider the implications of this textual information, formulate a visual mental impression of the overall orientation of the drilling BHA, and try to formulate a steering plan based on this mental impression, before steering the system. A more efficient, reliable, and intuitive method for steering a BHA is needed.

3D toolface wellbore steering visualization


A linear actuator having an actuator member driven in a linear direction by a lever mechanism pivotally coupled thereto which is in turn driven by a plurality of on/off linear drivers. Driving the linear drivers through varying stroke distances provides a sequence of discrete actuator steps. By providing an interconnected simple lever mechanism a discrete set of 2.sup.n steps may be provided for n drive positions and n on/off linear drivers. The linear actuator thus provides simple integration with a digital control system and precise positive discrete steps of linear actuation.

The present invention relates to actuator mechanisms. More particularly, the present invention relates to systems for providing accurate mechanical control of a movable member in a linear direction.
In a wide variety of applications, it is important to provide precise linear motion of an actuator member in response to a control signal. For example, in many industrial and robotics applications such precise control of linear motion is very important.
For example, one industrial application where such linear control is important is in valve systems for controlling the flow of steam or other fluids which need to be controllably released. In such applications, a piston or some other type of value stem is moved linearly under the control of a linear actuator to open a valve opening by an amount corresponding to the amount of linear motion. Linear actuators commonly employed for such applications include pneumatic and hydraulic driven pistons, worm gears and cam driven rods. Such prior art linear actuators used in control valves have several disadvantages, however. In particular, in applications requiring control of high temperature fluids such as steam, or low temperature fluids such as refrigerants, the temperature variations in the valve system can result in variations in the response of the linear actuator. For example, stiction in the actuator may occur such that when a control signal is applied, the actuator may move in a discontinuous manner or not at all. Such variations are uncontrollable and unpredictable thereby creating inaccuracies in the operation of the valve. The resulting variations in the amount of fluid controlled by the valve may have serious consequences for industrial process control. Additionally, such problems will be important in applications where a relatively short linear stroke for the actuator must be controlled accurately and/or under substantial load, or when substantial variations in operating conditions arise.
Another problem experienced in many applications of the aforementioned linear actuators relates to the inherently analog nature of such actuators. In order to provide more than two linear positions, such actuators require an analog control signal provided from a control system to drive the linear actuator by the desired amount. The control electronics employed in industrial and robotics is becoming predominantly digital in nature, however, frequently being under microprocessor or larger computer control. This requires interface electronics to allow the digital control system to control the inherently analog linear actuator. Alternatively, an on/off approach has been employed, for example, using on/off electrical solenoids, to provide a simple two-way linear actuation system suitable for digital control. However, such a two-way system cannot provide the more detailed adjustments necessary for many applications. Therefore, for example, to obtain a range of fluid flow through a two-way valve a plurality of valves must be employed, each driven on or off by an on/off linear valve actuator, to give a desired range of control. Additionally, many applications other than valve control require more than the simple on/off linear actuation provided by such solenoid type actuators.
Additionally, prior art linear actuators providing continuous linear motion, such as worm gear, pneumatic or hydraulic actuators, generally lack any positive mechanical calibration of the actuation distance. Rather, such actuators depend on the control electronics to ensure the correct amount of linear actuation. Alternatively, complicated and expensive sensors and feedback control systems are needed to ensure the mechanical actuator has correctly responded to the analog control signal to provide the desired amount of linear travel. For many applications requiring very compact systems or operating in extreme or demanding environments, such sensors and feedback control systems can involve extremely difficult design problems and considerable expense. For example, this is especially true in the harsh, corrosive environment of paper making which requires extremely high reliability coupled with continuous production schedules.
Accordingly, a need presently exists for a linear actuator providing precise and positive linear motion compatible with digital control systems and not requiring complex feedback control.


A battery cell having a positive terminal, a negative terminal and a power producing core section (e.g., electrolyte) for systems, such as computer systems, cellular phones, etc. The battery cell also includes an internal circuit to monitor the state of the battery cell. The state that is monitored may include the temperature, charge level of the battery core section, the discharge/charge rate. The circuit may control the battery cell (e.g., cause charging of the battery cell). This internal circuit may be an integrated circuit, such as a microprocessor.

Today, batteries are used to provide power to many devices. These devices are more often portable or mobile devices. More recently, batteries have been a primary power source used for laptop and notebook computers, cellular phones, hand-held/mobile video recorders and many other electronic devices. Current battery cells include nickel cadmium, nickel metal hydride, lithium-ion, alkaline, acid, zinc, etc.
Typically, a group of batteries are strung together and encased in a plastic-molded pack. The cells in a pack are strung together by electrically coupling the positive terminal of one battery to the negative terminal of the next battery, with the negative terminal of the first battery in the string being the negative contact of the battery pack and the positive terminal of the last battery in the string being the positive contact of the battery pack. The plastic battery pack may also contain a logic board (e,g., PCB) that contains a integrated circuit (IC), an analog-to-digital (A/D) converter and/or a serial communication device to monitor the state of the battery pack and provide access to the state by a unit external to the battery pack. However, this logic board does not monitor each cell independently, only the group of battery cells as a whole. A temperature sensor may also be included in the battery pack to determine the temperature within the battery pack. The temperature reading obtained using the temperature sensor is output from the battery pack along with the positive and negative contacts of the first and last batteries in the string respectively.
One problem with current battery packs of the prior art is their expense. Specifically, approximately 20% of the cost of a battery pack is due to the molded plastic used to encase the battery cells. The plastic is normally custom molded for use in a specific application, such that there is no interchangeability between the various battery packs. For example, a battery pack designed for use in a specific laptop or notebook computer, normally cannot be used in other computers. This is due in part to the necessary functionality that is included within the battery packs to monitor and control the batteries as a whole. It is desirable to add some interchangeability to the battery packs. By integrating monitoring and control functionality into the battery cells themselves, the circuit board within a battery pack may be eliminated, thereby leaving only the battery cells in the battery pack. With cells of a particular type being approximately the same size, the battery packs can be the same size and interchangeable for different applications.
Another problem with the battery packs of the prior art is that they do not provide charging of individual cells. The entire string of batteries in the battery pack is coupled up to a charger in order to charge the battery pack as a whole. Cells within the inner portion of a string of batteries are not monitored individually, such that there is no method of guaranteeing that these inner cells are fully changed without always overcharging.
The battery packs of the prior art do not provide for monitoring of individual cells. Because individual cells are not monitored, the user has no way of knowing the current charge level of individual cells in the pack or that a battery cell in the pack is damaged. Charging a damaged cell may be dangerous because the cell may vent, become very hot, do nothing, or explode. Thus, without the ability to monitor, the user may be put in danger when attempting to charge the battery pack. Moreover, without monitoring, difficulty exists in maintaining a cell's charging within its optimum operating range. For instance, certain cells, such as lithium-ion cells, operate when they are charged to a particular range. If they are over-charged, they explode. If they are discharged too low, then they cannot be charged again. Because there is no monitoring in the prior art of individual cells, one cannot determine if one of the cells in the pack has become over-charged, such that it may explode, or has become discharged too low, such that it cannot be charged again. Therefore, it is desirable to be able to monitor individual battery cells in a battery pack.
Furthermore, because individual cells are not monitored, cells may become unbalanced. When cells become unbalanced, it is possible that a reverse cell voltage could occur. That is, as cells are normally coupled together with the positive terminal connected to the negative terminal of a subsequent battery cell in the string, if a cell becomes discharged too low, a cell reversal may occur. In cell reversal, if the charge in the cell becomes zero volts, the positive and negative designations lose their meaning and terminals of an individual battery cell may switch designations such that the positive terminal and the negative terminal of a zero volt battery cell switch to become negative and positive respectively. In such a situation, the other battery cells start to charge the zero volt cell and place energy into it due to its terminals being connected to the same terminals of its neighboring battery cells. In the prior art, this may occur unknown to the user since there is no monitoring of individual cells in the battery pack. Thus, it is desirable to provide monitoring of individual cells to avoid cell reversal.
The present invention provides a mechanism to monitor and charge each cell independently. In doing so, the present invention eliminates unbalanced cells, reversed cell voltages and provides a mechanism to determine if a cell is damaged to prevent damaged cells from being charged.

Battery cell having an internal circuit for controlling its operation


Methods for identifying and isolating CD8 T cells that produce interleukin-13 upon activation are provided. The present methods leverage one or more newly-identified biomarkers to identify such CD8 T cells and, in certain cases, sort the same. Certain methods comprise obtaining a sample from a mammal, quantifying a level of expression of one or more biomarkers therein, and determining if the level of expression is elevated as compared, wherein an elevated expression level is indicative of an active disease state. Antisera and antibodies are also provided. In particular, an anti-C10orf128 antiserum formulated against a particular peptide is provided, such anti-C10orf128 antiserum characterized in that it identifies a subset of CD8 T cells that produce interleukin-13 upon activation.

Systemic Sclerosis
Systemic sclerosis (also known as SSc or scleroderma) is a severe rheumatologic illness with inflammation of small and medium sized vessels throughout the body that causes cycles of ischemic injury, neovascularization, and progressive scarring in the skin and visceral organs. Current diagnostic criteria are dependent on physical findings combined with autoantibodies (ANA combined with Scl-70 and anti-centromere B) that are not believed to be directly involved in the pathogenesis of the disease. In addition to suboptimal diagnostic tests for systemic sclerosis, there is no effective therapy currently available for this disease.
Investigations into systemic sclerosis have not identified the cause of a presumed autoimmune attack on small and medium sized vessels, but have identified the effector cell type responsible for the immune-mediated damage. In 2009, investigators showed that systemic sclerosis patients have a unique CD8 T cell population in peripheral blood and skin that produce the protein interleukin 13 (IL-13) when activated (hereafter referred to as CD8IL-13 T cells). In addition, studies have shown that dermal fibroblasts exposed to culture supernatants from scleroderma CD8 T cells produce collagen (which results in scarring) through a mechanism dependent on IL-13 and tumor necrosis factor beta (TGF-beta), which is the master cytokine involved in collagen production and scarring. Others investigating mechanisms of scarring in other experimental systems have shown that the combination of tumor necrosis factor alpha (TNF-alpha) and IL-13 causes stromal cells to make TGF-beta. Unfortunately, however, the IL-13 producing CD8 T cells in human studies could only be identified by activation, fixation/permeabilization/intracellular cytokine staining for IL-13. That processing requirement has conventionally rendered the accessible CD8IL-13 T cell population unusable for advanced investigations such as gene expression micro array analyses.
Chlamydia Infection
Chlamydia infection is the most common sexually transmitted disease, responsible for about 2.8 million cases a year in the US. Untreated Chlamydia infections can ascend into the upper reproductive tract causing scarring and fibrosis that result in infertility and ectopic pregnancies. Fibrosis is a major contributor to scarring (the shared biologic trait shared with scleroderma) caused by Chlamydia infection.
Working in the mouse model for Chlamydia trachomatis infections, the inventor of the present application developed unique methodologies for cloning antigen-specific T cell clones based on unconventional antigen preparations and antigen presenting cells. Chlamydia infections of the genital tract are clinically important because the infection-promoted scarring of the genital tract that leads to infertility and ectopic pregnancy.
It is conventionally known that T cells, and specifically CD8 T cells, are the predominant inflammatory infiltrate in affected tissue thought to produce cytokines that drive the synthesis of extracellular matrix proteins by fibroblasts that results in excess fibrosis. Research in the mouse model for Chlamydia genital tract infections has shown unambiguously that scarring and infertility are mediated by CD8 T cells. Perhaps more specifically, the inventor hereof has shown in the mouse model that the CD8 T cell response to Chlamydia genital tract infections is atypical and includes the antigen-specific CD8IL-13 T cells that also produce TNF-alpha when activated.
As previously noted, although human CD8+ T cells expressing IL-13 have been described in humans, they unfortunately are not currently a usable tool to study the biology, protein, and gene expression in these cells, nor to screen prospective therapeutics. This is in large part because convention human CD8IL-13 T cell subset biomarkers do not allow for the practicable purification of viable CD8IL-13 T cells required to perform the genomic and functional studies needed to develop improved diagnostic tests, test therapeutic drugs, and identify new therapeutic targets.
Accordingly, and especially given the huge impact that both Chlamydia infections and scleroderma have on human health and the problems that exist with currently available treatments for both conditions, there is a pressing need for an increased understanding of the role of CD8 T cells in the human immune system and, more specifically, for a useful tool to study CD8IL-13 T cells. Similarly, a need exists to identify biomarkers for human CD8IL-13 T cells, with such biomarkers capable of facilitating viable cell purification protocols such that genomic and functional studies may be performed thereon. In this manner, meaningful diagnostic testing and therapeutic interventions could be screened for the purposes of (a) vaccine development, (b) diagnosing and treating pathological scarring during Chlamydia infections, and (c) diagnosing and treating pathological scarring in patients with scleroderma. As provided herein, gene expression microarray experiments utilizing murine CD8IL-13 and conventional CD8 T cell clones have been used to identify biomarkers for human CD8IL-13 T cells. The inventor of this application has identified that the human homolog (C10orf128) of the murine cell surface biomarker for CD8IL-13 T cells (1810011H11Rik) is expressed in the circulating CD8 T cell pool of patients with scleroderma, and can be practicably used to purify the desired CD8IL-13 T cell subset from the peripheral blood of human subjects.

Methods and antisera for isolating and identifying subsets of CD8 T cells