Method for ordering nodes within hierarchical data. The concept of isolated ordered regions to maintain coordinates of nodes is used by associating each node with coordinates relative to a containing region. Modifications to nodes within a region only affect the nodes in that region, and not nodes in other regions. Traversals that retrieve information from the nodes can rebase the coordinates from their containing region and return with a total order.

1. Field of Invention
The present invention relates generally to the field of ordering nodes. More specifically, the present invention is related to ordering nodes within hierarchical data.
2. Discussion of Prior Art
A tree structure comprising nodes is a type of data structure in which each element is attached to one or more elements directly beneath it. The connections among elements in a tree structure are called branches. Trees are often called inverted trees because they are normally drawn with the root at the top. Inverted trees are the data structures used to represent hierarchical file structures. In this case, the leaves are files and the other elements above the leaves are directories.
Tree structures have been used in prior art data processing systems to organize data. But, such prior art fails to provide for a system for ordering nodes within hierarchical data in a mark-up language-based document. Additionally, such prior art systems fail to teach a method or system for ordering nodes into a plurality of regions, wherein each of the regions defines an area within a two-dimensional space.
The following references provide for a general teaching with regard to hierarchical structures, but they fail to provide for the claimed invention's method and system.
U.S. Pat. No. 5,970,489 discloses a method for using region-sets to focus searches in hierarchical structures. The method improves a search in a hierarchical structure by focusing the search to selected regions within the structure. The method defines one or more region-set(s) and uses the region-set(s) as either a filter for the results of a key-word search or an integrated part of a search engine to increase the efficiency of the search engine. The method also provides for dynamic creation of new region-set(s) from existing region-set(s) using a prescribed set of operators.
U.S. patent application publication 2002/0118214 A1 provides a system and method for browsing node-link structures based on an estimated degree of interest. The disclosed invention enables a user to view large collections of linked information on a computer-based display. A visualization is created which presents a representation of the complete collection of information on the display. The visualization fits completely within a fixed area of the computer-based display, negating the need to scroll information into the display area. The visualization is based on identified focus nodes and through calculation of a Degree of Interest (DOI) for each of the nodes based in the structure. Layout and presentation of the visualization structure are based on the DOI values in combination with considerations of available display space. A user may dynamically manipulate views of the structure by selecting one or more focus nodes, thus causing a recalculation of the degree of interest.
U.S. Pat. No. 6,359,635 provides for methods, articles, and an apparatus for visibly representing information and for providing an input interface. Display and/or input regions to represent a plurality of tree-related elements include: a region to represent a root element; at least two concave regions to represent at least two non-root, internal elements; and at least two regions to represent at least two leaf elements. In a particular embodiment, a first concave region is radially adjacent to both a second concave region and a third concave region, the second concave region angularly adjacent to the third concave region, and a radial width of the second concave region differing from a radial width of the third concave region.
Whatever the precise merits, features, and advantages of the above cited references, none of them achieves or fulfills the purposes of the present invention.

This patent is subject to a terminal disclaimer.

Isolated ordered regions (IOR) node order

International Business Machines Corporation


Embodiments of an orthopedic apparatus and method for using the orthopedic apparatus to correct rotational bone deformities are disclosed. Embodiments of the orthopedic apparatus include a stationary segment having a fixed portion engaged to a first bone portion and a track portion engaged to a mobile segment that is engaged to a second bone portion separated by the first bone portion by a growth plate such that the mobile segment migrates over time from a first position along the stationary segment to a second position along the stationary segment in such a way that torsional growth and correction of an angular deformity are promoted.

In orthopedics, rotational deformities of the bone along the lower portions of an individual can change the planar orientation of various respective reference planes for the hip, knee and ankle. For example, abnormal angulation of the femoral neck with respect to the transcondylar axis of the knee is referred to as femoral anteversion. In general, rotational deformities as discussed above may be defined as an abnormal angulation of a bone relative to a longitudinal axis.
It is very common in infants to be born with femoral anteversion due to the position of the fetus inside the womb during pregnancy and can occur in up to 10% of children. In fact, femoral anteversion is the most common cause of children walking with their toes inward (in-toeing) in children older than 3 years of age. Although most rotational bone abnormalities, such as femoral anteversion, are resolved under normal growth and development, a small percentage of cases will continue to suffer from a residual rotational deformity that may later require surgical correction.
One common method of surgical bone realignment to address femoral anteversion is by performing an osteotomy procedure which requires cutting of the bone followed by its realignment to the correct bone orientation. However, osteotomy procedures require making a large incision to create access to the bone for the surgeon to perform the bone cutting and realignment, thereby making the procedure substantially invasive. In addition, the procedure can cause disruption of the adjacent musculature surrounding the bone as well as possibly damaging the neurovascular structures. Procedures to cut and realign bones are associated with a long and painful rehabilitation period that can last several months. The cut bone ends may not heal adequately and in such cases, further surgery may be necessary. Implant failure is also a well documented complication of osteotomies. Another concern is the accidental damage to the growth plate that can occur during the surgical realignment procedure, which can later inhibit healthy and normal limb growth. As such, current surgical bone realignment apparatuses and methods require a relatively invasive procedure be performed to correct rotational bone deformities. An alternative to invasive osteotomies is the use of guided growth through a minimally invasive device.

Orthopedic apparatus for correcting rotational bone deformities and method for using the orthopedic apparatus


A brushless motor drive device switches energization modes for supplying power to two phases of a three-phase brushless motor, based on an induced voltage induced in a non-energized phase. In a case in which a target duty ratio Dt, which is a duty ratio of a PWM signal according to a manipulated variable of the brushless motor becomes less than a detection limit value Dlim, which is the lower limit of a duty ratio capable of detecting an induced voltage, there is set a detection timing (1/N) for detecting an induced voltage according to the cycle of a PWM signal, and a detection time duty ratio D1, which is a duty ratio of the PWM signal at the detection timing, is restricted to Dlim.

1. Field of the Invention
The present invention relates to a brushless motor drive device, and, in particular, to a drive device which sensorlessly determines energization mode switching of a three-phase brushless motor.
2. Description of Related Art
Japanese Laid-open (Kokai) Patent Application Publication No. 2009-189176 discloses a drive system of a synchronous motor that: in a three-phase synchronous motor, detects an induced voltage (pulse induced voltage) of a non-energized phase induced by a pulse voltage; compares the level of this induced voltage with that of a reference voltage; and sequentially switches energization modes according to the result of this level comparison.
Incidentally, a pulse induced voltage of a non-energized phase is detected while a pulse-shaped voltage is being applied to two phases. However, since the pulse induced voltage oscillates immediately after the start of a voltage application, if the duty ratio of the pulse voltage is small (if the voltage application time is short), there is a possibility that the pulse induced voltage may be sampled within the oscillation period, and consequently the pulse induced voltage may be detected falsely, and the timing of switching energization modes may be misjudged.
Moreover, the magnitude of the pulse induced voltage of the non-energized phase changes according to the duty ratio of the pulse voltage, and if the duty ratio is small, the pulse induced voltage becomes below the reference voltage, resulting in a possibility that determination of the switching timing of energization modes may become impossible.


The invention relates to a process for the production of a ceramic/fiber composite.. The process comprises impregnating fibers with a molten polysilazane in a first step, converting the polysilazane in the fibers into the infusible state in a second step and, in a third step, heating the impregnated fibers to 800.degree. to 2000.degree. C. in an atmosphere of nitrogen, noble gas, or ammonia.

1. Field of the Invention
The present invention relates to a ceramic/fiber composite and a process for its production.
Because of its high breaking strength, dimensional stability, resistance to high temperature and to corrosion, ceramic/fiber composite is gaining a continuously growing importance. The good properties of the ceramic/fiber composite are based on the combination of a matrix and built-in fibers.
2. Description of the Related Art
A ceramic/fiber composite in which the fibers are fist impregnated with polysilazane and the polysilazane is then thermally decomposed to silicon nitride is described in EP-0,125,772 A1. A disadvantage with this process is that, for the impregnation of the fibers, the polysilazane must be dissolved in solvent.
After the impregnation, the solvent must be removed. Cavities form as a result of the removal of the solvent from the fiber composite, resulting in a ceramic fiber composite possessing properties which are not always satisfactory. It has been found that ceramic fiber composites have an increasing breaking strength and dimensional stability if there are only a few cavities in the ceramic fiber composite.

Process of producing a ceramic/fiber composite using a molten polysilazone


An operational condition of an outboard motor 1 is detected by an ECU 29, and transmitted via a communication unit 228, from a communication apparatus 283 to a base station 30. Antennas 32 and a cable 33 are arranged along an inner surface of an engine cover 12. The cable 33 is provided with a connector 34 for connecting the antenna 32 to a communication unit 28 and a GPS receiving circuit 31. The communication apparatus and the antennas are held floating in a case 351 which is filled with a gel, and the case 351 is fixed to the engine cover 12. A communication unit 28 is provided inside an engine cover 12. A housing portion 41 for a portable phone PH is provided pivoted about the cover 12 in such a manner that the portable phone is removable from the housing portion 41.

1. Field of the Invention
The present invention relates to an outboard motor, and particularly, to an outboard motor which comprises a radio communication apparatus capable of transmitting data such as an operational condition of the outboard motor and the like to the outside.
2. Description of the Related Art
For a vehicle such as an automobile, it is known to monitor an operational condition of the vehicle at a location away from the vehicle. For example, there is described in the Japanese Patent Application Laid-Open No. 9-315272 a vehicle which has a fault diagnosis device mounted thereon with a transmitter so as to transmit a diagnosis result to a base station. A vehicle with a transmitter mounted thereon transmits data to a base station by utilizing a radio-receiving antenna or a dedicated antenna that is jutted out from the vehicle.
For an outboard motor used for a boat, since it operates for a long time under severe conditions, it should be considered that information for appropriate maintenance is transmitted to a maintenance facility. For a small board, that is, a boat which utilizes an outboard motor, since the outboard motor is prepared independent of a boat and is attached to the boat hull, antennas and the like for transmission/reception are positioned at a location near the steering position, for example, in a cabin.
If a communication apparatus is mounted in an outboard motor itself, since the outboard motor is away from antennas and the like in a cabin, there occur many problems such as laborsome cable wiring, necessity to take measures against noise due to long cable wiring and the like. Particularly, since the outboard motor is used in combination with various kinds of hulls, they are required to be separately handled in view of the differences of cable wiring, routing, or the like, which results in expense of much time.
In addition, a rear portion of the boat is susceptible not only to vibrations of the outboard motor, but also to impact of the boat beaten by waves. Therefore, when a radio communication apparatus is mounted on an outboard motor positioned at the rear portion of the boat, due consideration must be given to these vibration and impact. Further, since the outboard motor is relatively small, it is not easy to obtain therein a space for the radio communication apparatus, the antenna, and the controller such as a CPU to be connected thereto.


The flow sensor comprises a heater arranged between two sensing thermopiles. In addition, at least one monitoring thermocouple is provided for measuring the temperature of the heater. The signal from the monitoring thermocouple can be used to improve the accuracy of the device in several ways. In particular, the signal from the monitoring thermocouple depends on changes of the Seeback constant and other inherent properties of the thermopiles in the same way as the signal from the sensing thermopiles, which allows a compensation of such effects. The signal from the monitoring thermocouple can also be used as a reference voltage to an A/D converter for converting the signals from the sensing thermopiles.

The invention relates to a device for measuring the flow of a fluid that has a heater and at least two sensing thermopiles integrated on a substrate, in particular a semiconductor substrate. The device is adapted to measure the flow of the fluid from the signal measured by the sensing thermopiles. This type of flow sensor is e.g. described in US 2003/0115952.


A prosthetic heart valve comprises a biological tissue valve and a collapsible and expandable support frame comprising a longitudinal axis. The frame comprises an outflow circumferential structure defining an outflow end of the frame and defining a similar row of expandable cells, and a circumferential undulating strut structure spaced apart from the outflow circumferential structure. The frame also comprises three struts longitudinally aligned with the longitudinal axis, configured to facilitate mounting the biological tissue valve to the frame, and interconnecting the outflow circumferential structure to the circumferential undulating structure. Each strut comprises a first end terminating at a respective junction between two adjacent expandable cells of the outflow circumferential structure, and a second end terminating at the circumferential undulating strut structure. The prosthetic heart valve is configured to be collapsed for introduction into a patient using a catheter and to be expanded for deployment at an implantation site.

Currently, the replacement of a deficient cardiac valve is often performed by opening the thorax, placing the patient under extracorporeal circulation or peripheral aorto-venous heart assistance, temporarily stopping the heart, surgically opening the heart, excising the deficient valve, and then implanting a prosthetic valve in its place. U.S. Pat. No. 4,106,129 to Carpentier describes a bioprosthetic heart valve with compliant orifice ring for surgical implantation. This procedure generally requires prolonged patient hospitalization, as well as extensive and often painful recovery. It also presents advanced complexities and significant costs.
To address the risks associated with open heart implantation, devices and methods for replacing a cardiac valve by a less invasive means have been contemplated. For example, French Patent Application No. 99 14462 illustrates a technique and a device for the ablation of a deficient heart valve by percutaneous route, with a peripheral valvular approach. International Application (PCT) Nos. WO 93/01768 and WO 97/28807, as well as U.S. Pat. No. 5,814,097 to Sterman et al., U.S. Pat. No. 5,370,685 to Stevens, and U.S. Pat. No. 5,545,214 to Stevens illustrate techniques that are not very invasive as well as instruments for implementation of these techniques.
U.S. Pat. No. 3,671,979 to Moulopoulos and U.S. Pat. No. 4,056,854 to Boretos describe a catheter-mounted artificial heart valve for implantation in close proximity to a defective heart valve. Both of these prostheses are temporary in nature and require continued connection to the catheter for subsequent repositioning or removal of the valve prosthesis, or for subsequent valve activation.
With regard to the positioning of a replacement heart valve, attaching this valve on a support with a structure in the form of a wire or network of wires, currently called a stent, has been proposed. This stent support can be contracted radially in such a way that it can be introduced into the body of the patient percutaneously by means of a catheter, and it can be deployed so as to be radially expanded once it is positioned at the desired target site. U.S. Pat. No. 3,657,744 to Ersek discloses a cylindrical, stent-supported, tri-leaflet, tissue, heart valve that can be delivered through a portion of the vasculature using an elongate tool. The stent is mounted onto the expansion tool prior to delivery to the target location where the stent and valve are expanded into place. More recently, U.S. Pat. No. 5,411,552 to Andersen also illustrates a technique of this type. In the Andersen patent, a stent-supported tissue valve is deliverable percutaneously to the native heart valve site for deployment using a balloon or other expanding device. Efforts have been made to develop a stent-supported valve that is self-expandable, using memory materials such as Nitinol.
The stent-supported systems designed for the positioning of a heart valve introduce uncertainties of varying degree with regard to minimizing migration from the target valve site. A cardiac valve that is not adequately anchored in place to resist the forces of the constantly changing vessel wall diameter, and turbulent blood flow therethrough, may dislodge itself, or otherwise become ineffective. In particular, the known stents do not appear to be suited to sites in which the cardiac wall widens on either proximally and/or distally of the valve annulus situs. Furthermore, the native cardiac ring remaining after ablation of the native valve can hinder the positioning of these stents. These known systems also in certain cases create problems related to the sealing quality of the replacement valve. In effect, the existing cardiac ring can have a surface that is to varying degrees irregular and calcified, which not only lessens the quality of the support of the stent against this ring but also acts as the source of leaks between the valve and this ring. Also, these systems can no longer be moved at all after deployment of the support, even if their position is not optimal. Furthermore, inflating a balloon on a stented valve as described by Andersen may traumatize the valve, especially if the valve is made from a fragile material as a living or former living tissue.
Also, the existing techniques are however considered not completely satisfactory and capable of being improved. In particular, some of these techniques have the problem of involving in any case putting the patient under extracorporeal circulation or peripheral aorto-venous heart assistance and temporary stopping of the heart; they are difficult to put into practice; they do not allow precise control of the diameter according to which the natural valve is cut, in view of the later calibration of the prosthetic valve; they lead to risks of diffusion of natural valve fragments, often calcified, into the organism, which can lead to an embolism, as well as to risks of perforation of the aortic or cardiac wall; they moreover induce risks of acute reflux of blood during ablation of the natural valve and risk of obstruction of blood flow during implantation of the device with a balloon expandable stent for example.


A method, terminal, cache server and system for displaying multimedia content in a browser, comprising receiving a webpage identifier in a browser window for a webpage comprising multimedia content, generating a multimedia content display request corresponding to the multimedia content, and sending the multimedia content display request to server, receiving multimedia content returned from the server, activating a multimedia display plug-in of the browser to display a multimedia display window, and displaying the received multimedia content in the multimedia display window, wherein the multimedia display window in an initial state is smaller than the browser window.

In the prior art, a user can view videos on a mobile browser through the following steps: the user accesses a video link in a mobile browser, and the mobile browser identifies the video server, downloads the video from the video server, and invokes a video player locally-installed on the mobile device to play the video.
There are issues in the prior art methods for playing a video on a mobile device using a video player: the video player of the mobile device shares the same user interface as other content on the browser, and the video player typically plays the video in full screen mode, which prevents the user from conducting other browser operations, such as browsing the news, while viewing the video.

Method and apparatus for displaying multimedia content in browser

TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED


In an antenna assembly (10) including a whip antenna (1, 9) provided with a stopper (5) of a conductive material at a lower end of the whip antenna, a helical antenna (2) provided with a conductive sleeve (6) mounted on a top end of the whip antenna, and a holder (4) of a conductive material for slidably holding the whip antenna, each of the stopper, the conductive sleeve, and the holder is of a light metal having a specific gravity not greater than 3 g/cm.sup.3. The holder is electrically connected to the stopper when the whip antenna is in an extended position. The holder is electrically connected to the conductive sleeve when the whip antenna is in a retracted position. The light metal may includes at least one of aluminum and magnesium. Alternatively, the light metal essentially consists of 0.4% or less Si, 0.7% or less Fe, 5.0-6.0% Cu, 0.30% or less Zn, 0.2-0.6% Bi, 0.2-0.6% Pb, and the balance Al in weight.

This invention relates to an antenna assembly comprising a whip antenna and a helical antenna mounted on a top end of the whip antenna.
An antenna assembly of the type described has been used in a radio communication device such as a portable communication terminal set, especially a mobile telephone terminal set. The antenna assembly is usually extendably and retractably mounted to a housing (or a casing) of the terminal set as disclosed in JP-A-3 245603 (Reference I).
In Reference I, the terminal set has a housing or enclosure enclosing transmitting and receiving electrical circuitry. The antenna assembly comprises the whip antenna (or an antenna rod) and a holder (or a support) attached to the housing for slidably holding (or supporting) the whip antenna. The holder (or the support) is made of a conductor and is connected to the electrical circuitry. The whip antenna is provided with a stopper (or a conductive ring) fixedly mounted on a lower or an inner end. When the whip antenna is in an extended position, the stopper is brought into contact with the holder (or the support) so that the whip antenna is connected to the electrical circuitry through the stopper and the holder (or the support). The whip antenna comprises a conductive rod covered with a dielectric sleeve or tube. The whip antenna or the conductive rod has an electrical length of a quarter wavelength of a predetermined frequency.
The helical antenna (or an antenna coil) is enclosed in a dielectric cap and is carried on a top end of the whip antenna. The dielectric cap is provided with a conductive sleeve at a lower end electrically connected to the helical antenna. The conductive sleeve is fitted onto the top end of the whip antenna and fixed thereto by caulking or deforming the conducive sleeve together with the dielectric sleeve of the whip antenna. The helical antenna is connected to the conductive rod of the whip antenna and has also an electrical length of a quarter wavelength of the predetermined frequency. Therefore, the antenna assembly has a half wavelength of the predetermined frequency.
When the antenna assembly is in a retracted position where the whip antenna is retracted in the housing, the helical antenna is connected to the electrical circuitry through the conductive sleeve and the holder (or the support). Thus, the helical antenna is used for short-range operation of the terminal set. At the retracted position, the whip antenna is in the housing and, therefore, does not serve for receiving the radio signal.
For a long-range operation, the antenna assembly is pulled out by manually handling the cap into the extended position where the stopper is brought into contact with the holder (or the support). Thus, the antenna assembly serves as a half-wavelength antenna. This structure of the antenna assembly will be referred to as a "non-separate type" because the whip antenna is not electrically separated from the helical antenna.
An assembly of the helical antenna and the dielectric cap with the conductive sleeve will be referred to as an antenna top.
Use is made of a special support of a coaxial structure as the holder (or the support) in order to insure that the whip antenna is disabled when the antenna assembly is in the retracted position. This is disclosed in GB 2,257,836 A (Reference II) and JP-A-5 243829 corresponding thereto.
In U.S. Pat. No. 5,204,687 (Reference III) and JP-B-2646505 (Reference IV), another structure of the antenna assembly is disclosed in which the conductor rod of the whip antenna is not electrically connected to the helical antenna but is insulated from the helical antenna. In the structure, the whip antenna is reliably disabled in the retracted position without use of the special support of the coaxial structure. The whip antenna only serves for receiving the radio signal in the extended position because the helical antenna is no longer connected to the holder (or the support). This structure of the antenna assembly will be referred to as a "separate type" because the whip antenna is electrically separated from the helical antenna.
In detail, Reference IV discloses a dielectric joint member of a generally rod shape which is secured at one end thereof to the top end of the conductor rod of the whip antenna. The dielectric joint member is partially covered with the conductive sleeve and is fitted at the other end portion with a coil bobbin. A helical coil or the helical antenna is wound on the coil bobbin and is connected to the conductive sleeve. The dielectric cap covers the coil bobbin, the helical coil, and the top end portion of the conductive sleeve together by, for example, the plastic molding to form the antenna top.
In the above, the conductive sleeve and the top end of the conductive rod of the whip antenna are fixed to the dielectric joint member by the insulation molding of the dielectric joint member when the conductive sleeve and the top end of the conductive rod are inserted into a mold.
In any one of the non-separate type antenna assembly and the separate type antenna assembly, it is essential that each of the holder, the conductive sleeve, and the stopper is electrically conductive. Generally, these conductive portions (namely, the holder, the conductive sleeve, and the stopper) are formed by the use of brass or zinc because of availability, machinability, and platability. As the mobile telephone terminal set becomes smaller in size and lighter in weight, the antenna assembly is also required to be light in size.
However, brass or zinc used as a material of each of the conductive portions of the antenna assembly has a large specific gravity. For example, 70-30 brass has a specific gravity of 8.6 g/cm.sup.2 and zinc has a specific gravity of 7.18 g/cm.sup.2. This makes it difficult to achieve a light weight.

Lightweight antenna assembly comprising a whip antenna and a helical antenna mounted on a top end of the whip antenna


In a fixing apparatus of an embodiment of the invention, a heat roller forwardly and reversely rotated by a drive motor capable of forwardly and reversely rotating is heated by an induction heating coil also when it is reversely rotated. Further, the roller control temperature of the heat roller by a control system is adjusted according to a time of forward rotation of the heat roller and a time of reverse rotation, or a time when the heat roller and a press roller are separated from each other and a time when they are in contact with each other. Besides, after a specified time has passed since an instruction of reverse rotation or forward rotation by a drive signal, output of the induction heating coil is tuned on.

1. Field of the Invention
The present invention relates to a fixing apparatus mounted in an image forming apparatus such as a copier, a printer or a facsimile, and particularly to a fixing apparatus of an image forming apparatus, which uses an induction heating system.
2. Description of the Background
Among induction heating fixing apparatuses used in image forming apparatuses such as electrophotographic copiers or printers, there is an apparatus which prevents a part of a fixing member from being excessively heated. For example, JP-A-2005-321511 discloses a fixing apparatus in which separation between a first fixing member and a second fixing member is detected, and power supply to a heat generating part is cut off. Besides, for example, JP-A-2002-82549 discloses a fixing apparatus in which after a heat generating roller in contact with a fixing belt starts a rotation operation, the heat generating roller is excited to generate heat.
However, as in the related art fixing apparatus, when the temperature control of the heat generating part is performed only by the timing of contact and separation of the fixing member, in the case where the fixing member having a small heat capacity is used, when the fixing members at the heating side and the pressure side come in contact with each other, a temperature drop in the fixing member becomes large. Thus, there is a fear that defective quality of fixing image occurs at the time of first copying.
Thus, in the induction heating fixing apparatus, it is desired that a fixing apparatus of an image forming apparatus is developed in which defective quality of fixing image due to a temperature drop in a heat generating member caused at the time of contact with an opposite member is prevented and a stable fixing property is obtained.

Temperature control of a fixing apparatus using an induction heating system


A robot configured for mini-invasive surgery through a single parietal incision and/or natural orifice includes at least one articulated support, a stiffening component, and at least one maneuvering element. The articulated support includes a plurality of rigid bodies that are mutually associated. The stiffening component is associated with the articulated support and adapted for the transition of the articulated support from an inactive configuration, in which the rigid bodies can move with respect to each other, to an active configuration, in which the rigid bodies are mutually aligned so as to form a guide, and vice versa. The least one maneuvering element can be associated slidingly with the guide of the articulated body in its active configuration and can engage selectively a plurality of operating instruments accommodated in at least one container body that can be associated with the articulated support in its active configuration.

The use of mini-invasive techniques has become the standard for many routine surgical procedures. However, among mini-invasive surgical techniques, laparoscopy procedures have great drawbacks, which include difficulties in accessing the surgical target and the technical limitations of working with coaxial surgical instruments. These limitations are particularly clear when one operates through a single parietal access opening (single incision) and/or natural orifice in the patient. This surgical technique imposes constrains on the possibility of triangulating the instruments, applying offset forces, and on the dimensions of the instruments themselves. Moreover, collisions often occur among instruments both inside and outside the operating surgical area. However, the use of additional surgical openings, which would allow better operability of the instruments in the surgical area, is associated with an increased risk of bleeding, for example at the level of the abdominal wall in the case of abdominal surgery, and of accidental damage of the viscera, as well as consequent increases in postoperative pain and risks of infection and formation of incisional hernias.
Conventional robotic systems for laparoscopic surgery are particularly bulky, complicated to assemble and difficult to insert and remove from the surgical area. Moreover, these robotic systems have highly limited functionalities when used in the configuration with single parietal access, and it is moreover impossible to use them through natural orifices.

Robot, particularly for mini-invasive surgery through a single parietal incision or natural orifice


A ballistic body armor damage sensing system having a body armor ballistic plate including at least one ballistic layer and at least one damage sensing layer coupled to the at least one ballistic layer and including a plurality of electrically conductive members which are positioned throughout said damage sensing layer, wherein when a fired projectile impacts the body armor ballistic plate and damages one or more of the electrically conductive members, the damaged electrically conductive members exhibit a measurable change in electrical resistance.

Conventional ballistic body armor implements one or more ballistic plates strategically positioned to overlie a corresponding body region to be protected. For example, a conventional ballistic body armor vest includes a fabric shell that houses at least a ballistic chest plate. The chest plate is supported within the fabric shell such that when a user wears the vest, the chest plate overlies and protects a chest region of the user.
When a fired projectile strikes a body armor ballistic plate, the projectile exerts a force on the ballistic plate. Ideally, the ballistic plate prevents a ballistic penetration and absorbs enough of the ballistic force to prevent serious blunt force trauma to the individual wearing the ballistic plate. However, in various circumstances certain degrees of ballistic force may still be transmitted to the individual and cause bodily injury. The degree of bodily injury suffered is generally directly proportional to the amount of ballistic force exerted on the individual.
In military operations, there is a need to provide efficient medical assistance to soldiers injured in the field. In this regard, it is imperative to quickly assess the extent of bodily injury suffered by a solider impacted by a fired projectile so that appropriate treatment actions may be taken quickly, particularly when there are multiple critically injured soldiers in need of treatment and limited medical resources are available. Accordingly, there is a need for improvements to conventional ballistic body armor to assist in enabling swift assessment of bodily injury experienced by an individual struck by a fired projectile, and thereby enable efficient provision of medical treatment.

Ballistic body armor damage sensing system and related methods


Disclosed is a bipolar SRAM including, in each memory cell, two NPN multiemitter transistors, with a base of one transistor being cross-connected to a collector of the other transistor. The respective collectors of these two multiemitter transistors in an arbitrary memory cell are connected to the same positive word line through a load. The first emitter of one of these two multiemitter transistors and the first emitter of the other transistor are connected to the same negative word line. Only when the positive word line corresponding to this negative word line is not selected, a data holding current flows to the negative word line from the first emitter of the transistor having a H level collector potential out of these two multiemitter transistors, and when the corresponding positive word line is selected, the negative word line is controlled not to allow the data holding current to flow. Furthermore, in a data writing, when the arbitrary memory cell is selected in order to reduce or eliminate a current flowing between a second emitter of one transistor of these two multiemitter transistors in the selected memory cell and a bit line connected thereto, the bit line is controlled.

1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to static semiconductor memory devices (referred to as SRAM hereinafter) using bipolar transistors.
2. Description of the Background Art
Semiconductor memory devices include SRAM write data which is held unless a power supply is turned off. SRAMs are classified into a MOSSRAM including MOS transistors as components and a bipolar SRAM including bipolar transistors as components. A bipolar SRAM is used as a part of which a high speed operation is required such as a central portion of a CPU (central processing unit) because the bipolar SRAM operates at a higher speed than a MOSSRAM. FIG. 7 is a schematic block diagram showing an entire arrangement of a chip of a bipolar SRAM.
Referring to FIG. 7, a bipolar SRAM 100 comprises a memory array 1, a row address buffer.multidot.decoder 2, a column address buffer.multidot.decoder 3, read/write circuit 4, a sense amplifier 5, an output buffer 6, a word line discharging circuit.multidot.holding current control circuit 7 and a read/write control circuit 8. Bipolar SRAM 100 further comprises a row address terminal T.sub.AX receiving an externally applied row address signal, a column address terminal T.sub.AY receiving an externally applied column address signal, an input data terminal T.sub.DI receiving an externally applied write data, a control terminal T.sub.CTL receiving an externally applied write control signal and a data output terminal T.sub.DO externally outputting read data.
Memory array 1 includes memory cells MCs arranged in a matrix of rows and columns, two word lines WP and WN provided for each row, and a bit line pair BP provided for each column. Each bit line pair BP includes two bit lines, BTL and BTR. The word line WN is connected to word line discharging circuit.multidot.holding current control circuit 7. Only the word line WP is connected to row address buffer.multidot.decoder 2.
The internal arrangement and a basic operation principle of the memory cell MC will be described. FIG. 8 is a circuit diagram showing the basic arrangement of a memory cell of a bipolar SRAM. With reference to FIG. 8, the memory cell MC includes two NPN type multiemitter transistors QML and QMR connected crossing with each other and loads RML and RMR. Load RML is provided between the collector of transistor QML and the word line WP corresponding to the memory cell MC. Similarly, load RMR is provided between the collector of transistor QMR and said corresponding word line WP. One emitter of transistor QML and one emitter of transistor QMR are connected in common to the other word line WN corresponding to the memory cell MC. The other emitter of transistor QML is connected to the bit line BTL corresponding to the memory cell MC. The other emitter of transistor QMR is connected to the other bit line BTR corresponding to the memory cell MC. In the following description, the word line WP is referred to as a positive word line and the word line WN is referred to as a negative word line.
Complementary potentials corresponding to data held at a node between load RML and transistor QML and a node between load RMR and transistor QMR. The node between load RML and transistor QML and that between load RMR and transistor QMR are referred to as storage nodes NL and NR, respectively, in the following.
It is assumed that a potential V.sub.NH on the positive word line WP corresponding to a logical "H" level and a potential V.sub.NL corresponding to a logical level "L" are held at storage nodes NL and NR, respectively. In reading data from the memory cell MC, the potential on the positive word line WP corresponding to the memory cell MC is raised to a high potential V.sub.H (for example -1.0 V). The bit lines BTL and BTR are connected to constant current sources IRWL and IRWR, respectively. In response to the potential rise of the word line WP, the potential at storage node NL is raised to approximately the same potential V.sub.H on the positive word line WP. At the same time, the potential at storage node NR is also raised to a fixed potential V.sub.L (for example -2.0 V) lower than the potential V.sub.H at the node NL. Bit line BTL is connected to a power supply Vcc through an NPN type transistor QRWL for reading and writing. Similarly, the other bit line BTR is connected to power supply Vcc through an NPN transistor QRWR. In a data reading, a read reference potential V.sub.RD is applied to the bases of transistors QRWL and QRWR. Read reference potential V.sub.RD is a potential close to the intermediate value (for example, about -1.6 V) between the potential V.sub.H corresponding to a H level and the potential V.sub.L corresponding to a L level. The potential V.sub.L at storage node NR and the potential V.sub. H at storage node NL are applied to the bases of transistors QML and QMR, respectively.
Since transistor QML and transistor QRWL constitute an ECL (emitter coupled logic) with respect to constant current source IRWL, transistor QRWL is rendered conductive which receives at its base the potential V.sub.RD higher than the base potential V.sub.L of transistor QML. As a result, the current flows to bit line BTL from power supply Vcc through transistor QRWL, whereby the potential on bit line BTL becomes the potential (-1.6 V-0.8 V=-2.4 V) lower than the base potential V.sub.RD of transistor QRWL by a base-emitter voltage V.sub.BE (.apprxeq.0.8 V) of the transistor. Similarly, transistors QMR and QRWR constitute an ECL with respect to constant current source IRWR. Transistor QMR receives a potential V.sub.H higher than that of storage node NL at its base. As a result transistor QMR is rendered conductive in this ECL, whereby a current flows to bit line BTR from positive word line WP at a H level potential through load RMR and transistor QMR, causing the bit line BTR to attain a low potential (-1.0 V-0.8 =-1.8 V) lower than the base potential V.sub.H of transistor QMR by the base-emitter voltage V.sub.BE of the transistor.
Conversely, when the potentials held at storage nodes NL and NR are at a L level and a H level, respectively, transistor QML is rendered conductive at bit line BTL side of the memory cell MC and transistor QRWR is rendered conductive at bit line BTR side. In this case, the potential on bit line BTL becomes -1.8 V and the potential on bit line BTR becomes -2.4 V. That is, the series-connection circuit of load RML and transistor QML constitutes an inverter IL inverting the potential at storage node NR and outputting the inversion to bit line BTL. Similarly, the series-connection circuit of load RMR and transistor QMR constitutes an inverter IR inverting the potential at storage node NL and outputting the inversion to bit line BTR. As a result, a potential difference is generated between BTL and BTR in a data reading. The potential difference is sensed by sense amplifier 5 in FIG. 7 to obtain the storage data of the selected memory cell MC.
In writing data to the memory cell MC, the potential on positive word line WP is raised to a high potential V.sub.H and complementary potentials corresponding to data to be written are applied to the bases of transistors QRWL and QRWR. It is assumed that data is already written in the memory cell MC so that the potentials at storage nodes NL and NR are at a H level and a L level, respectively. In this case, since transistors QML and QMR constitute the ECL, transistor QML is turned off and the other transistor QMR is turned on. In writing the reverse data to presently written data to the memory cell MC, that is, when the potentials at storage nodes NL and NR are inverted to a L level and a H level, respectively, the potential V.sub.WL (ordinarily -2.4 V) lower than the potential V.sub.L held at storage node NR is applied to the base of transistor QRWL and the potential V.sub.WH (ordinarily -0.8 V) higher than the potential V.sub.H held at storage node NL is applied to the base of transistor QRWR. As a result, transistor QML is switched from off to on state and transistor QRWL enters an off state. Meanwhile, transistor QMR is switched from on to off state and transistor QRWR enters an on state.
Turning-on of transistor QML causes a current to flow from positive word line WP through load RML and transistor QML to bit line BTL, thereby lowering the potential at storage node NL. Conversely, the turning-off of transistor QMR causes no current to flow from word line WP to load RMR, thereby raising the potential at storage node NR to the same potential as the potential V.sub.H on positive word line WP. At this time, a current flows to bit line BTR from power supply Vcc through transistor QRWR. As the foregoing, storage node NR is charged in response to the high potential on positive word line WP and storage node NL is discharged. The potential at storage node NR eventually becomes approximately equal to the potential V.sub.H on positive word line WP and the potential at storage node NL becomes a low level potential V.sub.L.
Conversely, in a data writing wherein storage nodes NL and NR are forced to "H" and "L" potentials, respectively, the potential V.sub.WH and the potential V.sub.WL are applied to the base of transistor QRWL and the base of the transistor QRWR, respectively. In this case, transistor QRWL receiving a high potential at its base is turned on and transistor QML is turned off. At the same time, transistor QMR receiving a high potential at its base is turned on and transistor QRWR is turned off. Therefore in this case, no change is caused in the conduction state of transistors QML and QMR, whereby the potentials held at storage nodes NL and NR remain unchanged. The data thus written (the potentials at storage nodes NL and NR) should be held even after the end of the writing. When the potentials at storage nodes NL and NR attain respectively "L" and "H" in this writing, in order to maintain the logical levels of the potentials at storage nodes NL and NR, the on state of transistor QML and the off state of transistor QMR should be maintained even after the end of the writing. Conversely, when the potentials at storage nodes NL and NR attain "H" and "L" in the writing, the off state of transistor QML and the on state of QMR should be maintained even after the end of the writing. However, since the potential on positive word line WP is lowered to the original potential V.sub.NH after the end of the writing, the base potentials of transistors QML and QMR are lowered to the original potential V.sub.NH and V.sub.NL, respectively, thereby preventing the conduction states of transistors QML and QMR from remaining the same as that in the data writing. The potentials at storage nodes NL and NR cannot be maintained when the conduction states of transistors QML and QMR change. That is, the data of the memory cell MC is damaged. Such data damage is prevented by flowing a small current all the time through negative word line WN from the memory cell MC. Negative word line WN is connected to one emitter unconnected to bit line BTL out of the two emitters of transistor QML and to one emitter unconnected to bit line BTR out of the two emitters of transistor QMR. In this method, current flows all the time from a storage node attaining a low level potential V.sub.L as a result of the writing to negative word line WN through a transistor turning on as a result of the writing out of transistors QML and QMR. Therefore, the potential at the storage node attaining a L level in the writing is maintained even after the end of the data writing. With inverters IL and IR cross-connected to each other, a maintained potential of the storage node of one inverter results in a maintained potential of the storage node of the other inverter. As a result, no storage data is damaged in the memory cell MC. As the foregoing, the current constantly flowed through negative word line WN to maintain the storage data of the memory cell MC is referred to as a data holding current. The potential on positive word line WP is raised to a H level only in the case of data writing and data reading of a memory cell connected thereto and the potential is lowered to the original level at the end of the data reading and data writing. In order to enhance the rate of a potential drop of positive word line WP, the electric charge stored in positive word line WP is extracted at a high speed through a memory cell and negative word line WN connected to the word line when the data writing and the data reading finish.
Back to FIG. 7, a row address signal applied to row address terminal T.sub.AX designates one of the positive word lines WPs in memory cell array 1, which one word line is connected to a memory cell to or from which line data is written or read. Similarly, a column address signal applied to column address terminal T.sub.AY designates one of the bit line pairs BPs in memory cell array 1, which pair is connected to a memory cell to or from which pair data is written or read. In response to the row address signal applied to row address terminal T.sub.AY, row address buffer.multidot.decoder 2 supplies a high potential V.sub.H only to the word line WP designated by the row address signal among the positive word lines WPs in memory cell array 1. In response to the column address signal applied to column address terminal T.sub.AY, column address buffer.multidot.decoder 3 selects the column designated by the column address signal among the columns corresponding to the respective bit line pairs BPs in memory array 1.
In response to a write enable signal WE applied to write control terminal T.sub.CTL, read/write control circuit 8 controls read/write circuit 4 and word line discharging circuit.multidot.holding current source 7. Write enable signal WE designates whether a data writing or a data reading should be performed for memory array 1. When write enable signal WE designates a "data writing", read/write control circuit 8 applies the input data signal D.sub.IN applied to input data terminal T.sub.DI to read/write circuit 4. Read/write circuit 4 includes write/read transistors QRWL and QRWR (see FIG. 8) provided for each bit line pair BP in memory array 1. In response to the applied input data signal D.sub.IN, read/write circuit 4 supplies such a complementary base voltage as described above to only the transistors QRWL and QRWR corresponding to the column selected by column address buffer.multidot.decoder 3 among the read/write transistors QRWL and QRWR provided corresponding to the respective bit line pairs BPs. As a result, the data is written on such a principle as described above in the memory cell (selected memory cell) provided at a crossing point between the row designated by the row address signal and the column designated by the column address signal.
When write enable signal WE designates a "data reading", read/write control circuit 8 does not accept input data signal D.sub.IN applied to input data terminal T.sub.DI. At this time, read/write circuit 4 applies, as a gate potential, the potential V.sub.RD which is the intermediate potential between the high level potential V.sub.H and the low level potential V.sub.L only to the write/read transistors QRWL and QRWR in the column selected by column address buffer.multidot.decoder 3. As a result, a potential difference is produced between the two bit lines constituting the bit line pair corresponding to the selected memory cell according to the storage data of the selected memory cell. Sense amplifier 5 senses and amplifies the potential difference to be output. Output buffer 6 buffers the signal output from sense amplifier 5, which buffered signal is provided to output data terminal T.sub.DO as the read data D.sub.OUT from the selected memory cell.
Word line discharging circuit.multidot.holding current control circuit 7 causes the holding current to flow through all the negative word lines WNs in memory array 1, while promoting the discharging of the selected word line in response to the stop of the high potential supply to the selected word line among the positive word lines WPs in memory array 1 in the data reading and the data writing.
A positive word line receiving a potential V.sub.H in a data reading or a data writing is referred to as a word line in a selected state or a selected word line hereinafter. Similarly, a bit line pair corresponding to a column selected by column address buffer.multidot.decoder 3 in a data writing and a data reading is referred to as a bit line pair in a selected state or a selected bit line pair.
FIG. 9 is a partial circuit diagram showing a specific circuit arrangement of a bipolar SRAM. The circuit system and the reading and writing method of the bipolar SRAM are disclosed in Japanese Patent Laying Open No. 60-242584, for example. FIG. 10 is a timing chart showing the operations in the data reading and the data writing of the bipolar SRAM having the arrangement shown in FIG. 9. With reference to FIGS. 9 and 10, a specific circuit operation of the bipolar SRAM will be described in detail in the following. While memory array 1 is illustrated in FIG. 9 as having four memory cells arranged in a matrix of two rows and two columns for the purpose of simplicity, it has an arrangement having more memory cells arranged in a matrix in practice.
With reference to FIG. 9, memory cells M11, M12, M21 and M22 are arranged in a matrix of two rows and two columns in memory array 1. The arrangement of each memory cell is as shown in FIG. 8. Memory cells M11 and M12 are connected in common to a positive word line WP1 and a negative word line WN1. Memory cells M21 and M22 are connected in common to a positive word line WP2 and a negative word line WN2 different from the positive word line WP1 and the negative word line WN1.
A row decoder XD includes a selection circuit XD.sub.1 for selecting/non-selecting positive word line WP1 and a selection circuit XD.sub.2 for selecting/non-selecting the other positive word line WP2.
Selection circuit XD.sub.1 includes NPN type transistors Q1 and T1 constituting an ECL, and an NPN type transistor QWD1 having a base connected to the collector of transistor Q1. The collector of transistor Q1 is connected to a power supply Vcc through a resistor RXD.sub.1 and the collectors of transistors T1 and QWD1 are directly connected to power supply Vcc. The emitter of transistor QWD1 is connected to positive word line WP1. The emitters of transistors Q1 and T1 are connected to a constant current source IXD1.
The other selection circuit XD.sub.2 has the same arrangement as that of the selection circuit XD.sub.1.
In response to an externally applied address signal, row decoder XD sets to a high potential one of a signal X1 to be applied to the base of transistor Q1 and a signal X2 to be applied to the base of transistor Q2 and sets the other signal to a low potential to select either positive word lines WP1 or WP2. A circuit operation of row decoder XD will be described.
The base potentials of transistors T1 and T2 are set to an intermediate potential VR between the high potential and the low potential. Thus, when the input signal X1 to the base of transistor Q1 attains a high potential and input signal X2 to the base of transistor Q2 attains a low potential, transistor Q1 is rendered conductive out of transistors Q1 and T1 in selection circuit XD.sub.1. Conversely, in selection circuit XD.sub.2, transistor T2 becomes conductive and transistor Q2 becomes non-conductive. The conduction of transistor Q1 causes a current to flow from power supply Vcc through resistor RXD1 and transistor Q1 to constant current source IXD1, whereby the collector potential of transistor X1 (the base potential of transistor QWD1) falls. Non-conduction of transistor Q2 prevents the current from flowing from power supply Vcc through a resistor RXD2 and transistor Q2 to a constant current source IXD2, whereby the collector potential of transistor Q2 (a base potential of a transistor QWD2) is raised in response to the output voltage of power supply Vcc, thereby rendering transistor QWD2 conductive. As a result, the potential on the other positive word line WP2 is raised to the high potential V.sub.H (-1.0 V) in response to the output voltage of power supply Vcc. Conversely, when input signal X1 attains a low potential and input signal X2 attains a high potential, transistor Q1 becomes non-conductive in selection circuit XD.sub.1, thereby raising the potential on positive word line WP1 to a high level contrary to the former case.
In memory array 1, memory cells M11 and M21 are connected in common to a pair of two bit lines BTL1 and BTR1 constituting a bit line pair BP1. Memory cells M12 and M22 are connected in common to a pair of two bit lines BTL2 and BTR2 constituting a bit line pair BP2. Provided between the bit lines BTL1 and BTR1 are two diodes DBDL1 and DBDR1 connected in anti-series. Similarly, provided between bit lines BTL2 and BTR2 are two diodes DBDL2 and DBDR2 connected in anti-series. The node between diodes DBDL1 and DBDR1 and that between diodes DBDL2 and DBDR2 are connected in common to a constant current source BTDSCS.
Bit line pairs BP1 and BP2 are connected to a bit line clamp circuit BTCL. Bit line clamp circuit BTCL fixes the potentials on the two bit lines constituting the non-selected bit line pair to the same potential.
Bit line clamp circuit BTCL includes a clamp circuit BTCL1 provided corresponding to bit line pair BP1 and a clamp circuit BTCL2 provided corresponding to bit line pair BP2.
Clamp circuit BTCL includes an NPN type transistor QBCL1 having an emitter connected to bit line BTL1 and a collector connected to power supply Vcc and an NPN type transistor QBCR1 having an emitter connected to bit line BTR1 and a collector connected to power supply Vcc. The base of transistor QBCL1 and the base of transistor QBCR1 are connected to power supply Vcc through a common resistor RBC1 and diode D.
Clamp circuit BTCL2 has the same arrangement as that of the clamp circuit BTCL1.
A read/write circuit RWb includes NPN type transistors STa1, STc1, STa2 and STc2 provided corresponding to all the bit lines BTL1, BTR1, BTL2 and BTR2, respectively in memory array 1. Read/write circuit RWb further includes NPN type transistors STb1 and STb2 respectively provided corresponding to a base node NBC1 between transistors QBCL1 and QBCR1 and a base node NBC2 between transistors QBCL2 and QBCR2. Respective transistors STa1 and STa2 are connected in series between the corresponding bit lines BTL1 and BTL2, and a constant current source IRWL. Respective transistors STc1 and STc2 are connected in series between the corresponding bit lines BTR1 and BTR2, and constant current source IRWR. Respective transistors STb1 and STb2 are connected in series between the corresponding base nodes NBC1 and NBC2 in bit line clamp circuit BTCL and a constant current source IBTCL. The base voltages of these transistors STa1, STb1, STc1, STa2, STb2 and STc2 are controlled by a column decoder YD.
Column decoder YD includes a selection circuit YD1 for selecting/non-selecting bit line pair BP1 and a selection circuit YD2 for selecting/non-selecting bit line pair BP2.
Selection circuit YD1 includes two NPN type transistors Q3 and T3 constituting an ECL and an NPN type transistor QBD1 having a base connected to the collector of transistor Q3. The collector of transistor Q3 is connected to power supply Vcc through a resistor RYDa1 and a diode DYa1. The collector of transistor T3 is connected to the diode DYa1 through a resistor RYDb1. The emitters of transistors Q3 and T3 are connected in common to a constant current source IYDa1. The collector of transistor QBD1 is directly connected to power supply Vcc. The emitter of transistor QBD1 is connected to the bases of transistors STa1, STb1 and STc1 in read/write circuit RW.sub.b and a constant current source IYDb1 through a diode DYb1.
A selection circuit YD2 has the same arrangement as that of the selection circuit YD1.
A description will be made of column decoder YD, read/write circuit RWb and bit line clamp circuit BTCL.
Column decoder YD causes one of a signal Y1 to be applied to the base of transistor Q3 and a signal Y2 to be applied to a base of a transistor Q4 to have a high potential and causes the other signal to have a lower potential, in response to an external column address signal, to select one of the bit line pairs BP1 and BP2. It is assumed, for example, that signal Y1 applied to the base of transistor Q3 is raised to a high potential and signal Y2 applied to the base of transistor Q4 is dropped to a low potential. In this case, in a selection circuit YD1, transistor Q3 out of transistors Q3 and T3 becomes conductive to generate a current flowing from power supply Vcc to diode DYa1, resistor RYDa1 and transistor Q3. As a result, the collector potential of transistor Q3 is lowered, whereby an output signal YS1 (hereinafter referred to as a bit line selecting signal) of selection circuit YD1 is lowered to turn off transistors STa1, STb1 and STc1. Consequently, the connections are electrically cut off between bit line BTL1 and constant current source IRWL, between bit line BTR1 and constant current source IRWR and between the base node NBC1 in bit line clamp circuit BTCL and constant current source IBTCL. At the same time, in selection circuit YD2, input signal Y2 is lowered to turn on transistor T4 and turn off transistor Q4, whereby the collector potential of transistor Q4 is raised in response to the output voltage of power supply Vcc to render a transistor QBD2 conductive contrary to the case of selection circuit YD1. As a result, the current is generated which flows from a diode DYb2 to the bases of transistors STa2, STb2 and STc2 provided corresponding to bit line pair BP2 in a read/write circuit RWb. That is, a bit line selecting signal YS2 from selection circuit YD2 is raised to render transistors STa2, STb2 and STc2 conductive, thereby electrically connecting bit line BTL1 to constant current source IRWL, bit line BTR2 to constant current source IRWR and base node NBC2 in bit line clamp circuit BTCL to constant current source IBTCL.
As the foregoing, when input signal Y2 to selection circuit YD2 is at a low potential, bit line pair BP2 is selectively electrically connected to constant current sources IRWL, IRWR and IBTCL. As a result, the current flows from power supply Vcc to constant current source IBTCL through diode D, a resistor RBC2 and transistor STb2, whereby the potential at base node NBC2 falls. Therefore, transistors QBCL2 and QBCR2 become nonconductive. Conversely, since no current is generated which flows to resistor RBC1, the potential at the base node NBC1 between QBCL1 and QBCR1 rises in response to the output voltage of power supply Vcc, thereby rendering transistors QBCL1 and QBCR1 conductive to supply a high potential to bit lines BTL1 and BTR1. As a result, diodes DBDL1 and DBDR1 are forward biased to become conductive, thereby short-circuiting bit line BTL1 and bit line BTR1. With the current flowing from the cathodes of diodes DBDL1 and DBDR1 maintained constant by constant current source BTDSCS, bit lines BTL1 and BTR1 are held to the same fixed potential. That is, in this case bit line pair BP1 is not selected and bit line pair BP2 is selected.
Conversely, when input signal Y1 to selection circuit YD1 attains a low potential and input signal Y2 to selection circuit YD2 attains a high potential, signal YS1 applied to the bases of transistors STa1, STb1 and STc1 provided corresponding to bit line pair BP1 attains a high potential. At the same time, signal YS2 applied to the bases of transistors STa2, STb2 and STc2 provided corresponding to bit line pair BP2 attains a low potential. Consequently, in this case, bit line pair BP1 is selected and bit line pair BP2 is not selected.
Read/write circuit RWb further includes reading and writing transistors QRWL1 and QRWR1 provided corresponding to bit line pair BP1 and reading and writing transistors QRWL2 and QRWR2 provided corresponding to bit line pair BP2. Transistors QRWL1 and QRWR1 are provided between power supply Vcc and, bit line BTL1 and bit line BTR1, respectively, which bit lines constituting bit line pair BP1. Similarly, transistors QRWL2 and QRWR2 are provided between power supply Vcc and, bit line BTL2 and bit line BTR2, respectively, which bit lines constituting bit line pair BP2. A base potential TRB of transistors QRWL1 and QRWL2 and a base potential TRA of transistors QRWR1 and QRWR2 are controlled by a read/write control circuit RWC.
Read/write control circuit RWC controls the base potentials of transistors QRWL1 and QRWL2 and transistors QRWR1 and QRWR2 in response to an external write enable signal WE and input data signal D.sub.IN such that transistors QRWL1 and QRWL2 and transistors QRWR1 and QRWR2 operate in the data reading and data writing as described above.
A data holding current control circuit 7a includes constant current sources IH1 and IH2 connected to negative word lines WN1 and WN2, respectively. Constant current source IH1 holds the storage data of memory cells M11 and M12 by causing a small current to flow to negative word line WN1 at any time. Similarly, constant current source IH2 causes a small current to flow to the other negative word line WN2 at any time to hold the storage data of memory cells M21 and M22.
A word line discharging circuit 7b includes a diode QDD1 having an anode connected to negative word line WN1, a diode QDD2 having an anode connected to the other negative word line WN2, and a constant current source IWDCS. Constant current source IWDCS is connected in common to the cathodes of diodes QDD1 and QDD2. The potentials on negative word lines WN1 and WN2 rise/fall in response to the potential rise/fall of the corresponding positive word lines WP1 and WP2, respectively. Therefore, the change of positive word line WP1 from a selected state to a non-selected state causes the electric charges to be discharged through diode QDD1, whereby the current defined by constant current source IWDCS flows from positive word line WP1 through memory cells M11 and M12 and negative word line WN1 to constant current source IWDCS. As a result, the electric charges stored in positive word line WP1 are extracted at a high speed to rapidly render positive word line WP1 non-selected. The change of positive word line WP2 from a selected state to a non-selected state causes the electric charges to be discharged through diode QDD2. In this case, the electric charges stored in positive word line WP2 are accordingly extracted by constant current source IWDCS at a high speed to rapidly return positive word line WP2 to a non-selected state. As the foregoing, the current flowing for rapidly returning a positive word line to a non-selected state is referred to as a word line discharging current. The arrangement and the operation of word line discharging circuit 7b shown in FIG. 9 is disclosed in more detail in Japanese publication No. 57-17316, for example.
Referring to FIGS. 8 to 10, the data reading operation of the bipolar SRAM will be described. It is assumed in this description that memory cell M11 is selected and storage nodes NR and NL of memory cell M11 are held at a H level and a L level, respectively.
With reference to FIG. 9, when the data is read from memory cell M11, signal X1 in row decoder XT shifts from a H level to a L level in response to an external row address signal at a time t.sub.0. As a result, positive word line WP1 rises to a high potential V.sub.H from a low potential V.sub.NH. Consequently, the potential on negative word line WN1 rises to the potential lower than the potential V.sub.H on positive word line WP1 by a base-to-emitter voltage V.sub.BE of on state transistors QML or QMR in memory cells M11 or M12. In this way, negative word line WN1 enters a selected state out of a non-selected state. As a result, the potential as storage node NR of memory cell M11 rises from the level V.sub.NH of a non-selected state to a level V.sub.H of a selected state as indicated by 1 in FIG. 10. Similarly, the potential at the other storage node NL of memory cell M11 rises from the level V.sub.NL at non-selected state to the level V.sub.L at a selected state as indicated by 2 in FIG. 10.
On the other hand, signals Y1 and Y2 in column decoder YD attain a L level and a H level, respectively, in response to the external column address signal. As a result, bit line selecting signal YS1 attains a H level to select bit line pair BP1, whereby bit line BTL1 is electrically connected to constant current source IRWL and bit line BTR1 is electrically connected to constant current source IRWR. Furthermore, resistor RBC1 is electrically connected to constant current source IBTCL. In this way, bit line pair BP1 enters a selected state out of a non-selected state.
The resistance value of resistor RBC1 is set such that the potential at base node NBC1 is lower than the potential V.sub.L when the current defined by constant current source IBTCL flows to resistor RBC1. Similarly, the resistance value of resistor RBC2 is set to allow the potential at base node NBC2 to be lower than the potential V.sub.L when the current defined by constant current source IBTCL flows to the resistors RBC2. The reason for these resistance values of resistors RBC1 and RBC2 will be explained in the following and therefore no description thereof will be made here.
At the same time, the external write enable signal WE attains a H level.multidot.designating "data reading mode" in the data reading. In response to the H level write enable signal WE, read/write control circuit RWC controls base potentials TRA and TRB of read/write transistors QRWL1 and QRWR1 to become the intermediate potential V.sub.RD between potentials V.sub.L and V.sub.H of storage nodes NL and NR, respectively, of the selected memory cell M11.
The respective transistors of the four transistors each having the emitter connected to bit line BTL1, that is, transistors QRWL1 and QBCL1 and transistors QMLs of memory cells M11 and M21 constitute an ECL for constant current source IRWL. The transistor QML of memory cell M11 having the highest base potential V.sub.H among these four transistors conducts, thereby supplying current to constant current source IRWL. Similarly, transistors QRWR1 and QBCR1 and the respective transistors QMRs of memory cells M11 and M21 constitute an ECL for constant current source IRWR. Therefore, transistor QRWR1 having the highest base potential V.sub.RD among these four transistors conducts, thereby supplying current to constant current source IRWR.
The potential on bit line BTL1 is determined by the base potential of the conducting transistor among the transistors each having the emitter connected to bit line BTL1. Thus, bit line BTL1 attains the potential V.sub.H -V.sub.BE lower than the base potential V.sub.H of transistor QML in memory cell M11 by the base-to-emitter voltage V.sub.BE of the transistor. Similarly, the potential on bit line BTR1 is determined by the base current of the conducting transistor among the transistors connected to BTR1. Thus, bit line BTR1 attains the potential V.sub.RD -V.sub.BE lower than the base potential V.sub.RD of transistor QRWR1 by the base-to-emitter voltage V.sub.BE. As a result, the potential difference V.sub.H -V.sub.RD is produced between the selected bit lines BTL1 and BTR1. The potential difference V.sub.H -V.sub.RD is the potential difference to be sensed by a sense amplifier (not shown).
A writing operation of the bipolar SRAM will be described taking data writing in memory cell M11 as an example. In this description, it is assumed that a L level potential and a H level potential are already held at storage nodes NL and NR of memory cell M11.
Consideration is given to a rewriting of data of memory cell M11, that is, the inversion of the potentials at storage nodes NL and NR of memory cell M11 to a H level and a L level, respectively. In this case, input data terminal T.sub.DI of FIG. 7 receives as an input signal D.sub.IN a data signal corresponding to the data opposite to the data already stored in memory cell M11. The external write enable signal WE is set to a L level designating a "writing mode". Read/write control circuit RWC sets the base potential TRA of read/write transistor QRWR1 (FIG. 10 (4)) to a predetermined potential V.sub.WL lower than the potential V.sub.L, and sets the base potential TRB of read/write transistor QRWL1 (FIG. 10 (3)) to a predetermined potential V.sub.WH higher than the potential V.sub.H in response to the L level write enable signal WE and the input data signal D.sub.IN.
Row decoder XD operates similarly to select positive word line WP1 as in the data reading. As a result, the potential on positive word line WP1 rises to a H level potential V.sub.H. At the same time, column decoder YD operates similarly to select bit line pair BP1 as in the data reading. As a result, bit lines BTL1 and BTR1 constituting bit line pair BP1 are electrically connected to constant current sources IRWL and IRWR, respectively. Then, the base node NBC1 in bit line clamp circuit BTCL is electrically connected to constant current source IBTCL. Just as in the data reading, the potentials as storage nodes NL and NR in memory cell M11 become the potentials V.sub.L and V.sub.H higher than the potentials V.sub.NL and V.sub.NH in the non-selected state, respectively. It is assumed herein that the potential V.sub.L at storage node NL maintaining a L level potential in the selected memory cell M11 is set to be higher than the potential V.sub.NH at the storage node maintaining a H level in the non-selected memory cell M21. In this case, such a relation as follows is established among potentials V.sub.H and V.sub.L of a storage node of a selected memory cell, potentials V.sub.NH and V.sub.NL of a storage node of a non-selected memory cell and the base potentials V.sub.WH and V.sub.WL of reading/writing transistors QRWL1 and QRWR1. EQU V.sub.WH >V.sub.H >(V.sub.RD)>V.sub.L >V.sub.WL >V.sub.NH >V.sub.NL
At this time, irrespective of the held data of memory cell M21, transistor QMR of memory cell M11 has the highest base potential among the transistors each having the emitter connected to bit line BTR1 to constitute the ECL with respect to constant current source IRWR. On the other hand, irrespective of the held data of memory cell M21, reading/writing transistor QRWL1 has the highest base potential among the transistors each having the emitter connected to bit line BTL1 to constitute the ECL with respect to constant current source IRWL. Transistor QMR accordingly conducts in memory cell M11 and transistor QML becomes non-conductive. As a result, the current flows through RMR, thereby lowering the potential at storage node NR after the time t.sub.1 to FIG. 10. Conversely, the electric charge supplied from positive word line WP1 to storage node NL raises the potential at storage node NL after the time t.sub.1 of FIG. 10. Ultimately, the potential at storage node NL rises to the potential V.sub.H on the selected positive word line WP1 which is higher than the potential at storage node NR. In this way, the data of memory cell M11 is rewritten.
As the foregoing, in a conventional bipolar SRAM, the base potentials of transistors QMR and QML of the selected memory cell in a data reading are set to be higher than the base potentials of transistors QMR and QML of the non-selected memory cell having the emitter connected to the same bit line connected to this memory cell. That is, the potential V.sub.L at the storage node maintaining the L level of the selected memory cell is set to be higher than the potential V.sub.NH of the storage node maintaining the H level of the non-selected memory cell. Thus, a margin of a potential difference V.sub.M between the potential V.sub.L and the potential V.sub.NH is required as shown in FIG. 10.
The inversion of the relation between the potential V.sub.L and the potential V.sub.NH (V.sub.L <V.sub.NH is established) causes such a phenomenon as follows.
In writing data different from that already held in an arbitrary memory cell, for example, in writing data to memory cell M11 as described above, transistor QMR of non-selected memory cell M21 has the highest base potential among the transistors constituting the ECL with respect to constant current source IRWL (in a case where memory cell M21 stores the opposite data to the held data in memory cell M11 so that the storage node NL of memory cell M11 has the potential V.sub.NH). Transistor QMR of the non-selected memory cell M21 accordingly conducts and transistor QMR in memory cell M11 which is supposed to conduct becomes non-conductive. As a result, the potential at storage node NR in the selected memory cell M11 does not fall, so that the storage data of the selected memory cell M11 cannot be inverted. In order to avoid such problem, circuit factors should be settled to establish the relation V.sub.L >V.sub.NH between the potentials V.sub.L and V.sub.NH in a data writing. That is, the potential V.sub.NH cannot take the value between the potentials V.sub.N and V.sub.H. It is therefore not possible to set a potential difference V.sub.H -V.sub.NH between a potential on a selected word line and a potential on a non-selected word line to be smaller than a potential difference (referred to as a logical amplitude of a memory cell) V.sub.H -V.sub.L between storage nodes NL and NR of the selected memory cell.
Conversely, correct data reading from a selected memory cell requires one of transistors QML and QMR to be rendered conductive having a base receiving a potential V.sub.H at a storage node NL or NR maintaining a H level of the selected memory cell and of the other to be rendered non-conductive. This requires the potential V.sub.H at the storage node maintaining the H level of the selected memory cell to be higher than the potential V.sub.NH at the storage node maintaining the H level of the non-selected memory cell. This restriction is not so severe as in a data writing. As a result, a difference between the potential at the storage node of the selected memory cell and that at the storage node of the non-selected memory cell is larger than is required in a data reading.
The recent increased capacity of a semiconductor memory device has been followed by an increase in the number of memory cells of the semiconductor memory device. The increase in the number of memory cells means an increase of a total load amount coupled to positive word lines WP1 and WP2 driven by transistors QWD1 and QWD2, respectively in row decoder XD shown in FIG. 9. That is, the parasitic capacitances of the positive word lines WP1 and WP2 with respect to transistors QWD1 and QWD2 are increased. As a result, more time is required of transistors QWD1 and QWD2, respectively. That is more charging time of positive word lines WP1 and WP2 is required. Positive word lines WP1 and WP2 are raised by transistors QWD1 and QWD2, respectively, from the low potential V.sub.NH to the high potential V.sub.H to change from a non-selected state to a selected state. Such an increase in the charging time therefore increases a time period required of positive word lines WP1 and WP2 to change from a non-selected state to a selected state. The charging time of positive word lines WP1 and WP2 also depends on a difference .vertline.V.sub. NH -V.sub.H .vertline. (word line amplitude) between the potential V.sub.NH on positive word lines WP1 and WP2 at a non-selected state and the potential V.sub.H on the same at a selected state. In other words, the larger the word line amplitude is, the longer becomes a time period required of transistors QWD1 and QWD2 to raise the potentials on positive word lines WP1 and WP2 to a predetermined selected potential V.sub.H.
Consideration will be given of a circuit operation in data reading, for example, in reading data from memory cell M11. When the potential at storage nodes NL or NR maintaining the H level in memory cell M11 exceeds the base potential V.sub.RD of reading and writing transistors QRWL1 or QRWR1 in response to the potential rise of the selected positive word line WP1, the transistor conducts which receives, at its base, the potential of the storage node maintaining the H level out of transistors QML and QMR in memory cell M11. As a result, a potential difference is produced between bit lines BTL1 and BTR1, thereby enabling a data reading. A time (access time) required of data to be read from the actually designated memory cell after a memory cell to be selected is designated is accordingly proportional to a time tA1 required of the potential V.sub.NH at the storage node maintaining the H level of the selected memory cell to exceed the reading reference voltage V.sub.RD. The rate of the potential rise of the storage node of the selected memory cell is proportional to the rate of the potential rise of the selected word line. Thus, the longer the time required of positive word lines WP1 and WP2 to enter a selected state from a non-selected state, the more is increased the time tA1, thereby increasing an access time in the data reading.
Therefore, in order to prevent increase of an access time of a bipolar SRAM in consideration of the recent increase in the number of memory cells, a word line amplitude should be reduced. One of prior art for avoiding such an increase in an access time is the technique disclosed in U.S. Pat. No. 4,536,860.

Static semiconductor memory device using bipolar transistor


Methods for coupling aryl halides or aryl sulfonates to produce biaryls or polyaryls using novel nickel phosphite catalysts are provided.

The coupling of aryl compounds to form biaryl compounds or polyaryl compounds via carbon-carbon bonds is of great synthetic importance. A large number of methods are known to effect such couplings, including Ullman couplings of aryl iodides and bromides (see P. E. Fanta, "The Ullman Synthesis of Biaryls," Synthesis, 9, 9-21, 1974), coupling of aryl bromides and iodides with aryl boronic acids and esters using palladium catalysts (A. Suzuki, Acc. Chem. Res., 15, 178, 1982), reductive coupling of aryl halides with magnesium via Grignard reagents using nickel catalysts (T. Yamamoto and A. Yamamoto, Chem. Left., 353-356, 1977), reductive coupling of aryl chlorides with zinc using nickel triphenylphosphine catalysts (I. Colon and D. R. Kelsey, J. Org. Chem., 51, 2627-2637, 1986; and U.S. Pat. No. 4,326,989) and oxidative coupling of phenols using iron (III) or air and copper catalysts (L. F. Fieser and M. Fieser, Reagents for Organic Synthesis, Vol. 1, 390, 1967).
Each of the above-referenced prior art methods for the coupling of aryl compounds has certain limitations. The Ullman coupling generally results in low yields and, for best results, requires aryl iodides, which are expensive. Although coupling of aryl chlorides, which are less expensive than aryl iodides and aryl bromides, has been accomplished by Yamamoto et al via Grignard reagents, the generally more expensive aryl bromides and iodides are preferred. In addition, in the Yamamoto et al coupling reactions, groups such as ketones and esters, which are not stable to Grignard conditions, must be avoided, thereby limiting the scope of useful reactions. While the Suzuki coupling is the method of choice for cross-coupling to form asymmetric biaryls, it uses expensive palladium catalysts and boronic acid substrates, which makes the process more expensive and, hence, less desirable.
Because aryl chlorides cost substantially less than aryl bromides and aryl iodides, the nickel phosphine catalyzed couplings disclosed by Colon et al are widely used. In the Colon et al method, a nickel compound, salt, or complex is reduced in situ with zinc powder in the presence of a phosphine (specifically a triaryl phosphine) to form an active nickel (O) phosphine catalyst. It is theorized that in the triarylphosphine process, each of the nickel species in the catalytic cycle is capable of losing one or more of its phosphine ligands (L) to form coordinatively unsaturated complexes. These equilibria have been studied by Tolman (C. A. Tolman, W. C. Seidel, and L. W. Gosser, J. Am. Chem., 96, 53 (1974)). The formation f unsaturated complexes is said to be essential at certain parts of the cycle, so that the aryl halide may react. However, during other parts of the cycle, unsaturated nickel complexes may cause the formation of unwanted by-products or may react to form inert complexes unable to catalyze further coupling. It has been found in using the Colon et al process that the concentration of phosphine ligand must be kept between certain limits to prevent the formation of unsaturated nickel complexes which are too reactive and which lead to unwanted side reactions. The typical range of concentrations is approximately 0.2 to 0.5 M triphenylphosphine, 0.5 to 1 M aryl halide, and 0.01 to 0.05 M nickel.
In view of the foregoing, it can be seen that in the Colon et al. process relatively large amounts of triphenylphosphine must be used in coupling reactions compared to the amount of aryl halide substrate. Since such large amounts of triphenylphosphine must be used, recovery and purification of triphenylphosphine is required to enhance process economics. Because of the inefficiencies involved in the recovery, the cost of the process is substantially increased.
In addition to the increased cost of the Colon et al process due to the loss of triphenylphosphine, such processes also result in unwanted by-products due to abstraction of an aryl group (Ar') from the phosphine P(Ar').sub.3. The abstracted aryl group can couple to aryl halide (ArX), giving an undesired by-product Ar--Ar', for example. While increasing the concentration of phosphine ligand can suppress (but not eliminate) this undesired side reaction, increasing the phosphine concentration further increases the loss of triphenylphosphine, thereby increasing the overall process cost.
Aryl sulfonates react in a fashion similar to aryl halides and may be coupled using nickel phosphine catalysts such as that of Colon et al., for example, see the work of Percec et al. (V. Percec, J-Y. Bae, M. Zhao, and D. H. Hill, J. Org. Chem., 1995, 60, 176-185; and U.S. Pat. No. 5,241,044, issued Aug. 31, 1993.)
There is a need in the art for economical catalyst systems which can be used in reactions which couple aryl halides or aryl sulfonates to form either biaryl or polyaryl compounds and which enhance the economics of the process while reducing or substantially eliminating by-product formation.


A wireless device (12) is configured to transmit a signal simultaneously from a group (104) of physical antenna ports (106), based on associating disjoint frequency sub-bands with respective ones of the physical antenna ports (106). The frequency sub-bands collectively span a frequency bandwidth and each physical antenna port (106) supports transmission over the frequency bandwidth and has a per-port transmit power associated therewith. The wireless device (12) is configured to transmit the signal further based on allocating the per-port transmit power of each physical antenna port (106) in the group (104) only to frequency elements of the signal that fall within the frequency sub-band associated with the physical antenna port (106). A radio network node (10) in a network (16) is configured to perform channel estimation based on receiving a reference signal from the wireless device (12) and its channel estimation accounts for channel changes that may appear at the border between two frequency sub-bands.

A general problem with multi-antenna uplink transmissions by a User Equipment (UE) or another type of wireless communication device to a radio network is the limited total transmit power over all simultaneously used physical antenna ports, as well as the limited transmit power of each physical antenna port. In case several physical antenna ports are simultaneously active to transmit reference signals, such as Sounding Reference Signals (SRSs), the power per physical antenna port is limited by the overall and per-port power limits. There is thus a risk that the received power spectral density per signal may be too weak, at least under adverse channel conditions. For details regarding SRS, see, for example, Section 5.5.3 of the Third Generation Partnership Project (3GPP) Technical Specification, TS 36.211 V141.1.0 (2016-12).
To overcome the above problem, the wireless device may, in some cases, beamform its reference signal transmission over multiple physical antenna ports to improve link gain by potentially both beamforming gain and increased output power for the transmission. Most likely the number of reference signals will be less than the number of antenna ports in such cases, because the reference signals are likely to not share the same power amplifiers, for the sake of peak-to-average-power-ratio (PAPR) when transmitting data.
However, beamforming over antenna ports is not always an option, or at least may not be desirable. For example, consider a case where the involved antennas are located far away from each other, i.e., typically >0.5 wavelengths of separation. Because of the large separation between antennas, the resulting beams will have many and narrow lobes (grating lobes), which may make it difficult to transmit reference signals in the desired direction. Other beamforming complications may arise from unknown phase relations between the different antennas used for the transmission.

Methods and apparatus for signal transmission and reception in a wireless communication network