A schedule for a complex activity is obtained by a scheduling system using a method of constraint-based iterative repair. A predetermined initial schedule is iteratively repaired, repairs being made during each iteration only to portions of the schedule that produce a constraint violation, until an acceptable schedule is obtained. Since repairs are made to the schedule only to repair violated constraints, rather than to the entire schedule, schedule perturbations are minimized, thereby reducing problems with the dynamic performance of the scheduling system and minimizing disruption to the smooth operation of the activity. All constraints on the scheduling activity can be evaluated simultaneously to produce a solution that is near optimal with respect to all constraints. In particular, consumable resource constraints can be evaluated simultaneously with other constraints such as, for example, reusable resource constraints, temporal constraints, state constraints, milestone constraints and preemptive constraints. The scheduling system of the invention is much quicker than previous scheduling systems that use, for example, constructive scheduling method. The system of the invention can also be easily modified to add, delete or modify constraints. Because of the minimization of schedule perturbation, coupling of all constraints, speed of operation, and ease of modification, the scheduling system of the invention is particularly useful for scheduling applications that require frequent and rapid rescheduling.

1. Field of the Invention
This invention relates to a system and method for scheduling a complex activity that includes performance of a multiplicity of tasks, the completion of which necessitates the use of a multiplicity of resources and adherence to state requirements of a multiplicity of attributes. The tasks, resources and attributes are related by a multiplicity of constraints. At least some of the resources are consumable resources. In particular, the invention relates to such a system and method that combine the techniques of constraint-based iterative repair with the techniques of material requirements planning.
2. Related Art
Management of a complex activity, such as operation of a manufacturing facility, or maintenance and repair of a complex system such as the Space Shuttle, necessitates scheduling of many tasks, the completion of which may conflict with each other for a variety of reasons. Further, each of the tasks uses resources (which can be either consumable or reusable) of finite extent. Development of a schedule that resolves the many possible conflicts that may arise during conduct of the activity is a complex problem. The problem is further compounded by the probability that unforeseen events will, from time to time, necessitate modification of any determined schedule.
"Scheduling" is the process of assigning times and resources to the tasks of an operation. Scheduling assignments must satisfy a set of constraints. Constraints include, for example, temporal constraints, milestone constraints, resource constraints, state constraints and preemptive constraints.
Constructive scheduling is one method that has been used to develop schedules for complex activities. In constructive scheduling, a partial schedule is developed from scratch so that the partial schedule does not violate any of the constraints (or violates the constraints to a predefined acceptable degree). The partial schedule is then incrementally extended through a series of successive partial schedules, each successive partial schedule conforming to the constraints (again, to a predefined degree), until a final, complete schedule is developed. In some constructive scheduling methods, failure of any of the partial schedules to adequately satisfy the constraints necessitates backtracking to an earlier partial schedule and reconstructing a series of partial schedules from that point. Construction of partial schedules and backtracking continue until an acceptable final schedule is developed. In other constructive scheduling methods, when a partial schedule fails to satisfy a constraint, the schedule meets the constraint as best it can, and the constraint is relaxed to the degree necessary to eliminate the constraint violation.
Constraint-based iterative repair is another method that has been used to develop schedules for complex activities. In constraint-based iterative repair, a complete schedule that does not adequately satisfy the constraints is iteratively modified to obtain a series of complete schedules until one of the modified schedules adequately satisfies the constraints. Unlike constructive methods, only constraints that have been violated are repaired during each iteration.
The above-described techniques have been used to solve "scheduling problems." A "scheduling problem" is a problem in which all of the items, e.g., tasks and resources, to be scheduled to accomplish an operation are known at the beginning of development of the schedule. Establishment of a schedule consists of assigning a time and allocating resources to each task such that the constraints are satisfied to the degree desired. An example of a scheduling problem is the assignment of classrooms, teachers and students for all of the courses offered at a university during a semester.
In contrast to a scheduling problem, with its pre-established set of tasks and resources, a "planning problem" is more open-ended. In a planning problem, any of a number of sets of tasks and resources can be chosen to accomplish an operation, subject only to the satisfaction of certain conditions during the scheduled set of activities. Thus, typically, while scheduling for a planning problem will begin with a defined set of tasks and resources, additional tasks and resources are added to the schedule as the final schedule is developed. (It is also possible to delete some tasks and resources during development of the final schedule.) Therefore, scheduling for "planning problems" is generally more complex than scheduling for "scheduling problems." Scheduling a manufacturing operation is a good example of a planning problem.
There are two primary types of planning problems: i) consumable resource planning, e.g., inventory planning such as planning for finished goods, raw material, and/or work-in-progress in a manufacturing operation, and ii) reusable resource planning, e.g., capacity planning such as planning for machine and labor usage in a manufacturing operation. Previously, these two planning problems have been addressed separately. Below, previous methods of addressing these problems are discussed in the manufacturing context.
In manufacturing, master production scheduling (MPS) has been used to address the inventory planning problem. MPS operates at a macrocosmic level and is used to develop a build schedule for the supply of finished goods, e.g., goods sold directly to a consumer. MPS accepts demand requirements as input, i.e., the quantity of finished goods needed at particular times. The demand requirements are forecasted and/or actual needs netted against existing inventory. MPS develops a schedule for the replenishment of the finished goods inventory by scheduling the production and/or procurement of batches of finished goods to meet the demand requirements. For example, MPS could be used to develop a build schedule for a particular model of computer made by a manufacturer.
Rough cut capacity planning has been used in the manufacturing context to address the capacity planning problem at the macrocosmic level. Typically, rough cut capacity planning evaluates capacity constraints at some level between the factory and machine levels, e.g., at the production line level. A build schedule, as developed by a MPS system for example, is input into the rough cut capacity planning system and a determination is made as to whether sufficient resources exist to implement the build schedule. If not, a planner must either direct that additional capacity be added, or develop a new build schedule using MPS techniques. For example, rough cut capacity planning can determine whether there are an adequate number of assembly lines and workers to produce a sufficient number of computers according to a build schedule established by an MPS system.
Typically, MPS and rough cut capacity scheduling are successively performed at least several times before a satisfactory build schedule is developed, one that accommodates both demand (inventory) requirements and capacity constraints. Inventory planning and capacity planning are not coupled, other than to supply the inventory planning (i.e., MPS) output as the capacity planning (i.e., rough cut capacity planning) input, and to use the capacity planning output to evaluate the efficacy of the inventory planning output. Solution of the combined inventory and capacity problem in this manner frequently takes a rather long time and does not lend itself to easy rescheduling once an acceptable build schedule has been established.
Once MPS and rough cut capacity planning have been used to develop a satisfactory build schedule for the supply of finished goods, the production requirements of the build schedule are supplied to a material requirements planning (MRP) system. MRP operates at a microcosmic level and is used to develop a schedule for the production of finished goods. As input, the MRP system accepts the production requirements of the build schedule, subassembly and raw materials inventory levels (to net production requirements against existing inventory), bills of materials (BOMs) associated with the production of the finished goods and subassemblies, and information regarding production and material ordering lead times. The MRP system outputs schedules for the ordering of raw materials and component parts, assembly of raw materials and component parts into sub-assemblies, and assembly of sub-assemblies into finished goods. MRP could be used, for example, to schedule the assembly of circuit boards and disk drives from raw materials and/or component parts, as well as the subsequent assembly of the circuit boards and disk drives (and other necessary components) to produce computers.
The schedule developed by an MRP system assumes infinite capacity. Since, in the real world, this is not so, the schedule developed by the MRP system can be input to a capacity resources planning (CRP) system to evaluate whether sufficient capacity resources are available at the times necessary to fulfill the MRP schedule. If not, then either additional capacity must be added, or the MRP system must produce a new schedule. However, like MPS and rough cut capacity planning, MRP and CRP are not coupled processes, so that development of a new schedule by the MRP system does not occur automatically, but rather must be initiated by a planner who makes changes to the demand requirements placed on the MRP system using knowledge not available to the planning systems, such as the ability of one part to be substituted for another.
Another approach used with MRP to solve the capacity problem is finite capacity scheduling (FCS). FCS systems may have a limited ability to perform some automatic rescheduling. However, they do not extensively couple capacity constraints to inventory requirements and so do not adequately optimize a schedule based upon consideration of capacity constraints. Several types of FCS have been tried, each type enabling consideration of only a small subset of schedules out of the entire realm of possible schedules that can satisfy the inventory and capacity constraints.
One type of FCS uses mathematical programming techniques, such as linear programming or integer programming (e.g., a branch and bound method), to develop an acceptable schedule. Mathematical programming techniques can ensure that the best possible schedule is found. However, evaluation of alternative schedules requires reformulation of the schedule from scratch, i.e., these techniques are constructive methods, making this approach very slow in producing the final schedule. Further, mathematical programming necessitates complex mathematical formulations and a large number of variables to define the scheduling problem, thus necessitating a large information storage capacity and a lengthy time for execution of the scheduling procedure. Thus, mathematical programming is not suitable for use in situations where frequent and rapid rescheduling is required, as is frequently the case. Additionally, linear programming requires a linear optimization function and real-valued variables, conditions that are too restrictive for many scheduling problems.
Another type of FCS, "dispatching and simulation," uses a set of rules to produce a schedule that satisfies both inventory and capacity constraints. Dispatching and simulation systems can include only very simple rules, or they can be implemented as rule-based expert systems and implement a more complex set of rules. However, this approach can only be used to produce a single solution--the method does not iterate through a series of solutions--so that the best schedule is usually not found. Further, once a scheduling problem has been defined, it is an arduous task to modify the problem definition to accommodate additions, revisions and deletions to the problem constraints, making dispatching and simulation a relatively inflexible approach to scheduling.
There are a number of other FCS methods, including case-based reasoning, genetic algorithms, and neural nets. All of these methods use some variation of iterative repair. Case-based reasoning is a method that matches a scheduling problem to a library of previously solved scheduling problems. When an analogous problem is found, the solution to that problem is repaired so as to make the solution applicable to the new problem. Since, in order to be useful, case-based reasoning methods require the acquisition of a voluminous amount of cases to be useful, they are overly time consuming. Even after training, case-based methods are typically slow because of the matching process.
Genetic algorithms and neural network algorithms are iterative repair methods that generally rely on very weak repairs such as random modifications or repairs that are analogous to biological gene mutations and crossovers. Because these algorithms have weak repairs, they typically require many iterations to converge to an acceptable schedule and, therefore, are slow. Further, since these methods rely on random repairs, they also tend to significantly alter schedules, making them undesirable for rescheduling applications. Standard applications of simulated annealing and tabu search also rely on random repairs rather than the exploitation of constraint knowledge, so they also suffer from the same problems--slowness and large schedule perturbation--as genetic and neural network algorithms.
None of the above-described approaches considers both inventory and capacity constraints simultaneously to a significant degree, and most do not consider the two together at all. As a result, those methods typically do not produce a schedule that is optimal with respect to both capacity and inventory constraints.
Further, those methods that do consider inventory and capacity together to a limited degree (FCS methods), suffer from other deficiencies. Integer programming requires complex modeling and is slow. Dispatching and simulation, and rule-based expert systems do not iterate through a series of solutions in order to obtain increasingly better solutions and are difficult to modify to change constraint definitions.
Additionally, all of the above-described methods produce revised schedules by reworking all or a large part of the schedule without regard for the extent of the changes between the old and new schedules. In other words, these methods do not attempt to minimize scheduling perturbations when a schedule must be revised. Such extensive scheduling changes can be disruptive to the smooth operation of a complex activity. Further, reworking the entire schedule causes these methods to take an undesirably long time to produce a schedule. Thus, none of the above-described methods work well for frequent rescheduling of a complex activity. Since, in the real world, rescheduling must typically be done often to respond to changing conditions, a better scheduling approach is needed, one that integrates the resolution of capacity and inventory constraints, that minimizes the disturbances caused by rescheduling and that produces a revised schedule quickly. Further, such a system should be easily modified to accommodate changes in constraint definition.

Iterative repair optimization with particular application to scheduling for integrated capacity and inventory planning


A dental strainer unit includes a plastic strainer, a plastic strainer cap, and a transparent, non-rigid plastic housing. The strainer unit can be cost-effectively manufactured and easily disassembled and cleaned. The strainer cap can be manufactured in a variety of sizes to permit different aspirator devices to be attached thereto, and the housing can be snap-fit over the enlarged head of a saliva ejector valve. The dental strainer unit can be used in a modularized dental aspiration system.

The invention relates to aspirator apparatus, and more particularly relates to aspirator apparatus of the vacuum-operated type. In its most immediate sense, the invention relates to dental aspiration devices such as are used to aspirate body fluids and solids from a patient's mouth, and to methods for using such devices.
Dental procedures can cause solid matter (e.g. bone chips, tooth particles, tissue fragments, pieces of amalgam etc.) to enter fluids (e.g. saliva, blood, and cooling water) that are present in the patient's mouth. The solid matter is removed from the mouth to prevent the patient from swallowing or aspirating it, and removal of the solid matter necessarily entails removal of the fluids as well. When such fluids are withdrawn from the patient's mouth (as by a vacuum-powered saliva ejector or a high-speed saliva aspirator) this solid matter can cause difficulties for the dentist and even for the patient. One such difficulty is that the solid matter can clog the vacuum system. Another such difficulty is that the solid matter can build up upon the inside surfaces of the vacuum lines, thereby forming a base for the growth of biofilm that in turn promotes the growth of bacteria. For these reasons, it is known to provide a strainer unit behind the ejector or aspirator. The strainer unit separates the solid matter from the body fluids, protecting the vacuum system and making it more difficult for a biofilm to build up. Conventionally, the ejector or aspirator is disposable, but the strainer unit is not.
Existing strainer units have a number of disadvantages. First, existing FDA regulations do not require that strainer units be sterile; they need only be clean. And, even if a particular dentist is motivated to sterilize a strainer unit before connecting it to the vacuum system, existing strainer units can neither be easily emptied nor easily cleaned and sterilized. Hence, a strainer unit used during a dental procedure on a patient will likely be unsterile at the beginning of the procedure. In the worst case, the strainer unit will contain solid matter and/or body fluids from a prior patient. This poses the danger that bodily substances from a dental procedure performed earlier in a day may cross-contaminate (as by backflowing fluid into the patient's mouth) a patient undergoing a dental procedure later on that day. Second, existing strainer units are not versatile. (The saliva ejector shown in U.S. Pat. No. 3,890,712 is an example of such a non-versatile device.) They are designed to work only with a particular type of saliva ejector or aspirator, and cannot easily be used with another type. Third, existing strainer units are relatively expensive. (The Osseous Coagulum Trap now being sold through Quality Aspirators, Duncanville Tex., is an example of an expensive strainer unit.) Hence, if a dentist is motivated to use a sterile strainer unit for each patient, the dentist must make a considerable investment in strainer units and must incur increased operating expenses to clean and to sterilize them.
It would be advantageous to provide an improved strainer unit that would overcome these disadvantages.
Existing saliva ejectors and high-speed saliva aspirators also have disadvantages. One conventional saliva ejector, which has a strainer tip at its distal end, can become painfully embedded in the soft tissue of the patient's mouth. This is because the patient's flesh can seal off the holes in the strainer tip. When this happens, the vacuum to the saliva ejector causes the strainer tip and the patient's flesh to be tightly urged against each other. Similarly, a conventional high-speed saliva aspirator can likewise become wedged against the patient's flesh and cause damage to the tissue.
Finally, although conventional saliva ejectors, saliva extractors and similar dental tools are supplied in a "clean" state, they necessarily become less clean when contacted by the hand of the dentist or dental hygienist.
It would be advantageous to provide a saliva ejector and a saliva extractor, and a method for using such dental tools, that would overcome these disadvantages.
In accordance with the invention, a modularized aspiration system is provided. One component of the system is an all-plastic strainer unit. This strainer unit has three parts: a plastic strainer, a plastic strainer cap, and a plastic housing. The strainer has an open inlet end and an outlet end and a multiplicity of openings sized to permit fluids to pass out of the strainer and to retain solids within the strainer. The retainer cap is attached to the strainer and covers its inlet end, and has an inlet port where an aspirator device (such as a saliva ejector or a high-speed saliva aspirator) can be attached. The housing has an inlet end and an outlet end. The inlet end is shaped to receive the strainer so that the inlet end of the strainer faces the inlet end of the housing and the outlet end of the strainer faces the outlet end of the housing. The outlet end has an outlet port sized to fit onto a distal end of a conventional vacuum valve.
In preferred embodiments, the strainer unit is a dental strainer unit, the vacuum valve is a saliva ejector valve, the openings are sized to permit saliva, blood, and water to pass out of the strainer, and the strainer cap and strainer are removably secured within the housing. This makes it possible to adapt the strainer unit for attachment to almost any saliva removal device by mounting the strainer unit with a cap having an appropriately-sized male or female element. This also makes it possible to manufacture the strainer unit economically, since the number of parts required is small; the same strainer and housing can be used in all instances and only the cap (which is a comparatively small and inexpensive part) need be made in a variety of sizes.
Advantageously, and in preferred embodiments, the housing is transparent and non-rigid; transparency allows the dentist or dental hygienist to know if the strainer is becoming overfull, and non-rigidity allows the strainer unit to be positively snap-fit over the enlarged head of a conventional saliva ejector valve (and to thereby positively notify the dentist or hygienist that the attachment between the valve and the housing is proper). To make the strainer unit more generally useful, it is possible to provide an elongated adaptor having one end with the shape of a saliva ejector valve head and the other end shaped to mate with a high-volume valve. The preferred embodiment of a strainer unit in accordance with the invention forms the basis for a versatile modular system and can be used to connect virtually any type of saliva removal device with any conventional vacuum source. Further advantageously, and in preferred embodiments, the strainer is generally frustum-shaped, with its inlet end at the base of the frustum.
Further advantageously, in accordance with the invention an improved saliva ejector and an improved high-speed saliva aspirator are provided. In a flexible saliva ejector in accordance with the invention, a protective flange is provided adjacent to, and spaced apart from, the strainer tip that is conventionally provided. This prevents the patient's flesh from blocking all the holes through which fluids are removed from the patient's mouth, and thereby prevents the saliva ejector and the patient's flesh from being tightly and painfully urged together by the vacuum. In a saliva extractor in accordance with the invention, a protective flexible tip is secured at the distal end. This cushions the patient's flesh at the point where it is contacted by the distal end of the saliva extractor, making it less likely that the distal end of the extractor will injure the patient.
In preferred embodiments, a saliva ejector and a saliva extractor in accordance with the invention are pleated, as with locking bellows. This makes it easier for the device to maintain the shape desired without the use of stiffening wire in the wall of the device.
Still further advantageously, in accordance with the invention a new method of operating a hand-operated dental instrument (such as a high volume valve or a saliva ejector valve) is provided. In accordance with this method, a dental tool (such as a saliva ejector or a high-speed saliva aspirator in accordance with the invention, with or without a strainer unit in accordance with the invention) is packaged within a pouch, advantageously a conventional sterilizing pouch. If the dentist so desires, he can sterilize the tool and the strainer unit inside the pouch before using them. One end of the pouch is then opened to permit the instrument to be introduced into the pouch and connected with the tool. Then, the other end of the pouch is opened so the tool can be pushed out of the pouch and used in a dental operation. The tool is pushed out until the instrument is sheathed within the pouch, where it can be operated through the pouch without being physically touched by the dentist or dental hygienist. In this way

East Coast Medical and Dental Devices, Inc.


Preforms for precision press molding made of optical glass, optical elements, and methods of manufacturing the same are provided. The preforms are suited to precision press molding having a broad range of dispersion characteristics, a low glass transition temperature, a low sag point, and good resistance to devitrification while containing no PbO. The optical element is obtained by precision press molding the preform. One example of the preform has a refractive index (nd) of greater than or equal to 1.7 and an Abbé number (vd) of less than or equal to 32. The other example of the preform has an Abbé number (vd) exceeding 32.

Since precision press-molded aspherical lenses and the like that are made with optical glass having broad dispersion characteristics (for example, an Abbé number, vd, of 17 to 72) are extremely useful in optical design, the demand for the optical glass used in such precision press molding is increasing. However, large quantities of lead oxide have been incorporated into the optical glass compositions of many of the glasses and the pressing temperature has been reduced to increase the service life of the pressing mold employed in precision press molding. For example, Japanese Unexamined Patent Publication (KOKAI) Heisei No. 1-308843 discloses an optical glass for precision pressing comprised of (denoted as weight percentages): SiO2: 15 to 50 percent, PbO: 30 to 58 percent, Li2O: 0.1 to 7 percent, Na2O: 0 to 15 percent, K2O: 0 to 15 percent where Li2O+Na2O+K2O: 3 to 25 percent; La2O3: 0 to 15 percent, MgO: 0 to 10 percent, TiO2: 0 to 10 percent, where La2O3+MgO+TiO2: 0.1 to 20 percent, ZrO2: 0 to 5 percent, Al2O3: 0 to 10 percent, where ZrO2+Al2O3: 0.1 to 10 percent; ZnO: 0 to 20 percent, B2O3: 0 to 15 percent, Y2O3: 0 to 5 percent, Gd2O3: 0 to 5 percent, CaO: 0 to 10 percent, SrO: 0 to 15 percent, BaO: 0 to 9 percent; Nb2O5: 0 to 15 percent, Ta2O5: 0 to 5 percent, WO3: 0 to 5 percent, P205: 0 to 5 percent, As2O3: 0 to 1 percent, Sb2O3: 0 to 5 percent.
However, precision press molding is normally conducted in a nonreactive or weakly reducing atmosphere to prevent oxidation of the pressing mold. When precision press molding the above-described glass containing a large amount of lead oxide among the glass components, lead oxide at the surface of the glass is reduced, precipitating out as metallic lead on the surface of the lens. This then adheres to the mold material used to mold precision press-molded lenses, compromising the precision of the transfer surface of lenses that are precision press molded and requiring maintenance to remove the metallic lead adhering to the mold, which is not suited to mass production. Further, the melting of the glasses containing large quantities of lead oxide disclosed in the above-cited patent publication presents major problems in terms of environmental pollution. Thus, the glass disclosed in above-cited patent publication is unsuited to precision press molding.
The present invention, devised to solve the above-stated problems, has for its object to provide preforms for precision press molding comprised of optical glass imparting broad dispersion characteristics, permitting a low pressing temperature suited to precision press molding, and affording high stability; a method of manufacturing such preforms; optical elements obtained by precision press molding this preform; and a method of manufacturing such optical elements.

This patent is subject to a terminal disclaimer.

Preforms for precision press molding, optical elements, and methods of manufacturing the same


Lead-free copper-tin, low friction, castable bearing bronze alloy for industrial applications as bearing, bushing, and guide parts as well as threaded cast parts, with the following weight percentage range.. Sn=3-9 PA0 Bi=2.5-9 PA0 P=0-0.3 PA0 Zn=0-1 PA0 Ni=0-2 PA0 Pb=0-0.35 PA0 Cu=Balance

This invention relates to a lead-free continuously-cast copper-base alloy suited for use as a bearing, bushing, or guide material.
Currently there are different specifications covering many bearing bronzes, the most popular of them being those of Copper Development Association (CDA). Some of these bearing bronzes are lead-free, for example, C903 or C954. Others are leaded, for example, C932 and C936. Lead-free bronzes like C903 and C954 have high coefficient of friction in metal to metal rubbing contact and also have lower machinability compared to leaded bronzes.
Leaded bronzes have good machinability and have low coefficient of friction. However, they contain anywhere from 5 to over 15 percent lead in them. During the past two decades it has been established that ingestion of even a few parts per billion of lead into human body causes severe health problem. As a consequence strong efforts are being made to eliminate lead from materials which ultimately might end up in human beings. Recently considerable efforts have been made to remove or at least reduce the lead content from plumbing brasses that come in contact with potable water. U.S. Pat. No. 4,879,094 is an example.
In bearing and bushing bronzes lead is used primarily as a lubricating agent which also helps machinability. Currently there are many pump installations handling water that contain leaded bearings. Lead from them can possibly contaminate water being pumped. Furthermore, many machine shops buy lead containing bars and tube stocks to machine them into bushings and bearings. This might expose machinists to lead-bearing dusts if not fully protected. Additionally, lead-bearing scrap requires proper handling and recycling to prevent lead from entering the environment.
This establishes the need for a low friction bearing alloy which does not contain any highly toxic material like lead. In fact, there are already are some lead-free alloys with low friction. Examples are nickel-base alloys of Thomas and Williams (U.S. Pat. No. 2,743,176) and of Larson (U.S. Pat. No. 4,702,887) and copper-nickel alloy of Sahu (U.S. Pat. No. 5,242,657). However, these alloys are many times more expensive than common bearing alloys like C932 and C936.


The present invention is directed to a process of detecting a target nucleic acid using labeled oligonucleotides. This process uses the 5' to 3' nuclease activity of a nucleic acid polymerase to cleave annealed labeled oligonucleotide from hybridized duplexes and release labeled oligonucleotide fragments for detection. This process is easily incorporated into a PCR amplification assay.

Investigational microbiological techniques are routinely being applied to diagnostic assays. For example, Falkow et al., U.S. Pat. No. 4,358,535 disclose a method for detecting pathogens by spotting a sample e.g., blood, cells, saliva, etc. on a filter (e.g., nitrocellulose), lysing the cells, and fixing the DNA through chemical denaturation and heating. Then, labeled DNA probes are added and allowed to hybridize with the fixed sample DNA, hybridization indicating the presence of the pathogen's DNA. The sample DNA in this case may be amplified by culturing the cells or organisms in place on the filter.
A significant improvement in DNA amplification, the polymerase chain reaction (PCR) technique, is disclosed in U.S. Pat. Nos. 4,683,202, 4,683,195 and 4,800,159. In its simplest form, PCR is an in vitro method for the enzymatic synthesis of specific DNA sequences, using two oligonucleotide primers that hybridize to opposite strands and flank the region of interest in the target DNA. A repetitive series of reaction steps involving template denaturation, primer annealing, and the extension of the annealed primers by DNA polymerase results in the exponential accumulation of a specific fragment whose termini are defined by the 5' ends of the primers. PCR is reported to be capable of producing a selective enrichment of a specific DNA sequence by a factor of 10.sup.9. The PCR method is also described in Saiki et al., (1985) Science 230:1350.
Detection methods generally employed in standard PCR techniques use a labeled probe with the amplified DNA in a hybridization assay. For example, commonly-owned copending patent application U.S. Ser. Nos. 899,344 and 178,276 to Erlich et al., disclose assay methods wherein the PCR-amplified DNA is first fixed to a filter and then a specific oligonucleotide probe is added and allowed to hybridize. Preferably, the probe is labeled, e.g., with .sup.32 P, biotin, horseradish peroxidase (HRP), etc., to allow for detection of hybridization. The reverse is also suggested, that is, the probe is instead bound to the membrane and the PCR amplified sample DNA is added.
Other means of detection include the use of fragment length polymorphism (PCR FLP), hybridization to allele-specific oligonucleotide (ASO) probes (Saiki et al., (1986) Nature 324:163), or direct sequencing via the dideoxy method (using amplified DNA rather than cloned DNA). The standard PCR technique operates (essentially) by replicating a DNA sequence positioned between two primers, providing as the major product of the reaction a DNA sequence of discrete length terminating with the primer at the 5' end of each strand. Thus, insertions and deletions between the primers result in product sequences of different lengths, which can be detected by sizing the product in PCR-FLP. In an example of ASO hybridization, the amplified DNA is fixed to a nylon filter (by, for example, UV irradiation) in a series of "dot blots", then allowed to hybridize with an oligonucleotide probe labeled with HRP under stringent conditions. After washing, tetramethylbenzidine (TMB) and hydrogen peroxide are added: HRP oxidizes the hydrogen peroxide which in turn oxidizes the TMB to a blue precipitate, indicating hybridized probe.
While the PCR technique as presently practiced is an extremely powerful method for amplifying nucleic acid sequences, the detection of the amplified material requires additional manipulation and subsequent handling of the PCR products to determine whether the target DNA is present. It would be desirable to decrease the number of subsequent handling steps currently required for the detection of amplified material. A "homogeneous" assay system, that is, one which generates signal while the target sequence is amplified, requiring minimal post amplification handling, would be ideal.

Homogeneous assay system using the nuclease activity of a nucleic acid polymerase


An environmentally sealed electrical connector comprises a plug connector and a complimentary socket connector. The plug connector includes a plug body, a plug shell, a plug boot, a backshell and an interfacial seal. The socket connector includes a socket body, a socket shell, a socket boot and a backshell. The plug boot and the socket boot each have a plurality of rupturable features, each feature in register with a corresponding aperture through the corresponding connector body. The interfacial seal seats between the plug connector and socket connector when the plug connector is mated to the socket connector. The interfacial seal also has a plurality of rupturable features corresponding to a predetermined contact layout. Thus, when the socket connector is mated with the plug connector, a connector is provided, which prevents contaminants from penetrating the connection.

The present invention relates to electrical connectors, and in particular, to electrical connectors that interconnect a plurality of wires so as to provide environmentally sealed electrical connections.
It is often necessary to interconnect wires to form an electrical connection. In this regard, an electrical connector is often utilized to electrically join wires together or to otherwise electrically interconnect a wire or bundle of wires to additional circuitry. In practice, a connector typically comprises complimentary male and female connector components. Each connector component may be coupled to a terminal end of one or more wires in a corresponding wire bundle, or to a circuit or other arrangement. In use, a plurality of simultaneous electrical connections may be readily made by plugging the complimentary male and female connector components together. Correspondingly, an electrical connection between the connector components may be broken by disconnecting the male connector component from the female connector component.

Environmentally sealed electrical connector


A seat belt retractor (40) associated with a seat (10) includes a spool (106) about which seat belt webbing (42) is wound. The spool (106) is supported for rotation in a belt withdrawal direction and in an opposite belt retraction direction. A vehicle sensitive sensor (190) is responsive to at least one sensed vehicle condition for preventing rotation of the spool (106) in the belt withdrawal direction. A first mechanism (206) is responsive to a first condition for disabling the vehicle sensitive sensor (190). A second mechanism (294) is responsive to a second, different condition for preventing rotation of the spool (106) in the belt withdrawal direction. The second condition is a condition of the associated seat (10). In one embodiment, a third mechanism (400) is responsive to the first condition for allowing rotation of the spool (106) in the belt withdrawal direction.

Many vehicle seat belt retractors include a vehicle sensitive sensor. The vehicle sensitive sensor is responsive to certain vehicle conditions, such as vehicle deceleration and tilt, for preventing rotation of a spool of the retractor in a belt withdrawal direction.
It is common in some types of vehicles to locate the seat belt retractor in the backrest portion of the seat. When a seat belt retractor that is mounted in the backrest portion of the seat includes a vehicle sensitive sensor, the reclining or folding of the backrest portion of the seat may result in the vehicle sensitive sensor preventing rotation of the spool in a belt withdrawal direction. The spool of the retractor, however, may still rotate in the belt retraction direction to retract seat belt webbing. If the seat belt webbing retracts into the retractor when the backrest portion of the seat is in a folded condition and the vehicle sensitive sensor prevents rotation of the spool in the belt withdrawal direction, the seat belt webbing is prevented from being withdrawn from the retractor. As a result, the seat belt webbing may prevent the backrest portion of the seat from being returned to an upright position.
In some known seat belt systems, a button is sewn onto the seat belt webbing at a predetermined location. When the backrest portion of the seat is in an upright position and the seat belt webbing is fully retracted, the button on the seat belt webbing engages a structure within the retractor for preventing further retraction of the seat belt webbing. When the backrest portion of the seat is folded, no further seat belt webbing may be retracted into the retractor. Since the distance between the retractor and the anchor for the seat belt webbing is shortened when the backrest portion of the seat is folded, a loose portion of the seat belt webbing is formed when the backrest portion of the seat is folded. This loose portion of the seat belt webbing may hang to the side of the seat and is subject to damage from events such as being closed in the vehicle door.
A mechanism for disabling the vehicle sensitive sensor under certain conditions, such as a folded condition of the backrest portion of the seat, is desired. Such a mechanism, however, should not hinder the proper operation of the vehicle sensitive sensor when the seat belt webbing is being used for restraining an occupant in a vehicle seat.
A vehicle seat generally includes a seat back latch mechanism that must be moved to an unlatched condition for enabling the backrest portion of the seat to be folded or reclined relative to the seat cushion. When the seat back latch mechanism is in the latched condition, the backrest portion of the seat is fixed relative to the cushion portion of the seat. When the seat belt retractor is located in the backrest portion of the seat, the seat back latch mechanism must be in the latched condition for the seat belt webbing to help restrain the forward movement of the torso of the occupant of the seat. If the seat back latch mechanism is in the unlatched condition during the occurrence of a vehicle crash event, the backrest portion of the seat will move with the torso of the occupant and the seat belt webbing will not restrain movement of the torso.
It is desirable to prevent an occupant from withdrawing seat belt webbing from the seat belt retractor until the seat back latch mechanism is in the latched condition. By preventing the withdrawal of the seat belt webbing until the seat back latch mechanism is in the latched condition, the occupant will be forced to place the seat back latch mechanism in the latched condition prior to withdrawing and buckling the seat belt webbing. As a result of the seat back latch mechanism being placed in the latched condition to fix the backrest portion of the seat relative to the cushion portion, the seat belt webbing may help to restrain movement of the torso of the occupant.

Retractor having mechanisms for disabling a vehicle sensitive sensor and for preventing webbing withdrawal


In some examples, a system receives, from a sender, an access control value generated based on information of a plurality of recipients. The system sends, to the sender, a signed version of the access control value for sending by the sender to the plurality of recipients with an encrypted message. The system receives, from a first recipient a request for a key to decrypt the encrypted message, a signed access control value and recipient information for deriving the access control value. The system determines whether the first recipient is one of the plurality of recipients using the signed access control value and the recipient information.

Communications between different entities (where entities can refer to users, programs, and/or machines) can contain sensitive information that is to be protected. Examples of sensitive information include personal information of a user, confidential information, information pertaining to a system, a program, or a machine that an enterprise may not wish to be exposed, and so forth. Encryption techniques can be applied to protect communications.
Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements. The figures are not necessarily to scale, and the size of some parts may be exaggerated to more clearly illustrate the example shown. Moreover, the drawings provide examples and/or implementations consistent with the description; however, the description is not limited to the examples and/or implementations provided in the drawings.


A single stage side key disposed on a side surface of an operation unit, which is configured to control an image forming apparatus, includes an arm on the rear of an operation surface of the single stage side key (in a direction perpendicular to the operation surface). This configuration enables the operation unit to have a small thickness.

Field of the Invention
The present invention relates to an operation apparatus including a push button, which is to be mounted in an image forming apparatus such as a copier, printer, and facsimile, and an image forming apparatus including the operation apparatus.
Description of the Related Art
Image forming apparatuses such as a copier, printer, and facsimile each typically include an operation panel on an operation surface of a main body. The operation panel includes a display configured to display an operational state of the image forming apparatus. In addition to the display, the operation panel includes an input display allowing an operator to directly enter a command therethrough to start a function of the image forming apparatus, for example, and a plurality of push buttons allowing an operator to directly enter a command to start a function of the image forming apparatus, for example.
Japanese Patent Laid-Open No. 9-269860 describes a configuration of an operation panel including push buttons. The push buttons are integrally formed with a common supporting bar with arms therebetween, and the common supporting bar is screwed or welded to a case of an operation unit. The push buttons and the arms form a hinge structure having the common supporting bar as a shaft. The arms are formed of an elastic material. The operation panel further includes, at positions below the push buttons, switches configured to move together with the push buttons for key input and a printed board having the switches and an electrical circuit thereon.
However, the arm of the operation panel known in the art extends in a planar direction along a pressing surface of the push button. To reduce force required to push the push button, the arm is required to have lower elastic force by having a longer length or a smaller thickness, for example. This requires a space extending along the pressing surface of the push button in a planar direction to be larger. The thickness of the operation panel increases if the above-described push button is disposed at a side surface of the operation panel.

Image forming apparatus including an operation apparatus with a button disposed on the side


Embodiments provide a cargo basket including a frame, the frame including a base, the base including a pair of elongated first and second lower side members, the base including a pair of elongated first and second lower end members, the frame including a floor supported by the base, the frame including four corner posts extending from the base at respective of the four base corners, the frame including an elongated primary side wall supported by the base, the frame including a spaced pair of first and second end walls supported by the base, the frame including a spaced pair of first and second terminal side walls supported by the base, an access portal defined between the pair of terminal side posts, and a pair of gates supported for pivotal movement relative to respective of the terminal side posts.

Cargo baskets are used to transport cargo to facilities such as offshore oil exploration rigs. Cargo is grouped and loaded into the cargo baskets at a suitable location, such as a loading dock at a port facility. The loaded cargo baskets are transported by a suitable mode of transportation such as, for example, an ocean-going supply boat. The cargo baskets are transferred to a recipient, such as an offshore oil rig, in a suitable manner. For example, cargo baskets can be hoisted from a supply boat onto a receiving platform of an offshore oil rig by a single point hoist. The hoist is connected to raise each loaded cargo basket in a suitable manner, such as by a set of wire rope slings extending from a hoist hook to lifting eyes on the cargo basket.
Cargo baskets can be used to transport a variety of cargo. For example, a cargo basket can be used to transport large drilling tool components. The drilling tool components are loaded into the cargo basket in a suitable manner, such as by hand over a side of the cargo basket, or by hoist. A cargo basket can also be used to transport palletized cargo loads. In the specific context of offshore petroleum exploration, for example, the palletized cargo loads can be palletized containers of drilling supplies. Each palletized cargo load is connected to a suitable hoist, such as a single point hoist having a hook, with the use of hoist rigging such as flexible wire rope slings connected from the hoist hook and around the pallet, raised from the dock, positioned over the empty cargo basket, lowered into the cargo basket, and then the wire rope slings are removed for use with another load.
For reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved cargo baskets.


A front end module for an optical receiver is disclosed. The module includes a PD, a trans-impedance amplifier (TIA), an insulating carrier for mounting the PD, and a conductive base for mounting the carrier. The carrier provides first and second metal films thereon. The first metal film carries a photocurrent from the PD to the TIA, while, the second metal film carries the bias supply to the PD. The PD is mounted on the first and second metal films by the flip-chip arrangement. The second metal film surrounds the first metal film to suppress resonances appeared in the trans-impedance spectrum of the front end module.

1. Field of the Invention
The present invention relates to a front end module for an optical receiver, in particular, the present invention relates to a module including a photodiode (hereafter denoted as PD) mounted on a carrier.
2. Related Background Art
A front end module for an optical receiver generally includes a PD that receives an optical signal to generate a photocurrent and a trans-impedance amplifier (hereafter denoted as TIA) that converts the photocurrent into a voltage signal. A Japanese Patent Application published as JP-2007-274032A has disclosed such a front end module. The transmission speed of the optical communication has increased and exceeded over 10 GHz in some applications. The front end module is necessary to operate stably even in such high transmission speeds.


A switching power supply apparatus according to an embodiment includes a switching element, an inductor, a drive circuit, a mounting substrate, and an insulating substrate. The switching element is connected between a power supply and a lighting load. The inductor is connected in series to the switching element. The drive circuit controls the switching element, converts a voltage supplied from the power supply, and is mounted on the mounting substrate. The insulating substrate is thermally connected to the switching element, and has thermal conductivity higher than the mounting substrate.

A switching power supply employing a switching element is widely used in various fields as a power supply suitable for power saving and downsizing. As an example, the switching power supply is used also as a power supply for illumination. In recent years, replacement of lighting sources from incandescent lamps or fluorescent lamp to energy saving and long life light sources such as a light-emitting diode (LED) is in progress. Also, for example, new lighting sources such as Organic light-emitting diode (OLED) are also developed.
However, heat generation density of the switching element or the like is increased if the switching power supply is increased in frequency and downsized.

Switching power supply apparatus and luminaire

Toshiba Lighting & Technology Corporation


A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.

1. Field of the Invention
The present invention relates in general to microprocessors and, more particularly, to a system, method, and microprocessor architecture providing precise state updates in an out-of-order machine.
2. Relevant Background
Early computer processors (also called microprocessors) included a central processing unit or instruction execution unit that executed only one instruction at a time. As used herein the term processor includes complex instruction set computers (CISC), reduced instruction set computers (RISC) and hybrids. In response to the need for improved performance several techniques have been used to extend the capabilities of these early processors including pipelining, superpipelining, superscaling, speculative instruction execution, and out-of-order instruction execution.
Pipelined architectures break the execution of instructions into a number of stages where each stage corresponds to one step in the execution of the instruction. Pipelined designs increase the rate at which instructions can be executed by allowing a new instruction to begin execution before a previous instruction is finished executing. Pipelined architectures have been extended to "superpipelined" or "extended pipeline" architectures where each execution pipeline is broken down into even smaller stages (i.e., microinstruction granularity is increased). Superpipelining increases the number of instructions that can be executed in the pipeline at any given time.
"Superscalar" processors generally refer to a class of microprocessor architectures that include multiple pipelines that process instructions in parallel. Superscalar processors typically execute more than one instruction per clock cycle, on average. Superscalar processors allow parallel instruction execution in two or more instruction execution pipelines. The number of instructions that may be processed is increased due to parallel execution. Each of the execution pipelines may have differing number of stages. Some of the pipelines may be optimized for specialized functions such as integer operations or floating point operations, and in some cases execution pipelines are optimized for processing graphic, multimedia, or complex math instructions.
The goal of superscalar and superpipeline processors is to execute multiple instructions per cycle (IPC). Instruction-level parallelism (ILP) available in programs can be exploited to realize this goal, however, this potential parallelism requires that instructions be dispatched for execution at a sufficient rate. Conditional branching instructions create a problem for instruction fetching because the instruction fetch unit (IFU) cannot know with certainty which instructions to fetch until the conditional branch instruction is resolved. Also, when a branch is detected, the target address of the instructions following the branch must be predicted to supply those instructions for execution.
Recent processor architectures use a branch prediction unit to predict the outcome of branch instructions allowing the fetch unit to fetch subsequent instructions according to the predicted outcome. Branch prediction techniques are known that can predict branch outcomes with greater than 95% accuracy. These instructions are "speculatively executed" to allow the processor to make forward progress during the time the branch instruction is resolved. When the prediction is correct, the results of the speculative execution can be used as correct results, greatly improving processor speed and efficiency. When the prediction is incorrect, the completely or partially executed instructions must be flushed from the processor and execution of the correct branch initiated.
Early processors executed instructions in an order determined by the compiled machine-language program running on the processor and so are referred to as "in-order" or "sequential" processors. In superscalar processors multiple pipelines can simultaneously process instructions only when there are no data dependencies between the instructions in each pipeline. Data dependencies cause one or more pipelines to "stall" waiting for the dependent data to become available. This is further complicated in superpipelined processors where, because many instructions exist simultaneously in each pipeline, the potential quantity of data dependencies is large. Hence, greater parallelism and higher performance are achieved by "out-of-order" processors that include multiple pipelines in which instructions are processed in parallel in any efficient order that takes advantage of opportunities for parallel processing that may be provided by the instruction code.
Although out-of-order processing greatly improves throughput, it also increases complexity as compared to simple sequential processors. One area of increased complexity relates to state recovery following an unpredicted change of instruction flow. At any time during execution many instructions may be in the execution stage, some awaiting scheduling, some being executed, and some having completed execution but awaiting retirement. In the event that a change of instruction flow is detected during execution of an instruction, the instructions preceding that instruction must proceed to retirement, but the instructions following should be discarded. In other words, the state of the processor at the time of the change in instruction flow must be recovered in order for execution to continue properly. State recovery restores the pipeline to a state that it would have existed had the mispredicted instructions not been processed. Hence, one particular problem with superscalar processors is state recovery following an unexpected change of instruction flow caused by internal or external events such as interrupts, exceptions, and branch instructions.
Out-of-order execution can result in conflicts between instructions attempting to use the same registers even though these instructions are otherwise independent. Instructions may produce two general types of actions when executed: storing results that are directed to an architectural register location and setting condition codes (CCs) that are directed to one or more architectural condition code registers (CCRs). The results and CC's for any instruction that is speculatively executed cannot be stored in the architectural registers until all conditions prior to the instruction are resolved. To overcome this problem in prior processors, new register locations called "rename registers" are allocated for every new result produced (i.e., for every instruction that loads data into a register) in a process called "register renaming". A similar technique is used to store the CC set by a speculatively executed instruction. One difficulty with this technique is that because the speculative CC is stored separately from the speculative result, the bookkeeping logic necessary to handle the results and CC sets with precision is cumbersome and can slow processor throughput.
Using register renaming, an instruction identifying the original register for the purpose of reading its value obtains instead the value of the newly allocated rename register. Thus, the hardware renames the original register identifier in the instruction to identify the new register and the correct stored value. The same register identifier in several different instructions may access different hardware registers depending on the locations of the register references with respect to the register assignments. Although widely used, register renaming requires use of a tracking table having entries for each register in the processor indicating, among other things, the instruction identification and the particular instruction assigned to that register. This method of register renaming becomes unwieldy for larger designs with hundreds or thousands of registers. Also, because tracking tables become slower to access as they increase in size, large tracking tables may become a clock frequency limitation.
When an error occurs in the execution of a microinstruction an "exception" is generated. Typical exceptions include "faults", "traps" and "interrupts". These events cause updates of the macroarchitectural or microarchitectural state of the processor in response to the condition detected by invoking software or hardware instruction routines called "exception handlers". Exception handling is complicated in a multiple pipeline machine. Exceptions may be handled in either a precise or imprecise manner. Precise exception handling allows the programmer to know exactly where an error occurred and continue processing without having to abort the program because the appearance of sequential execution of instructions is preserved. In contrast, imprecise exception handling provides minimal information to the programmer, none of which is guaranteed to be correct, and may require aborting execution of the program. Thus, in most applications, precise exception handling is preferred.

Apparatus for generating out-of-order results and out-of-order condition codes in a processor


A flexible self-regulating heating pad apparatus (10) in combination with a compressed gas cylinder (50); wherein, the flexible self-regulating heating pad apparatus )10) consists of a flexible self-regulating heating unit (34); an insulation unit (36); a jacketing unit (38); and a releasable attachment system (40) for installing the flexible self-regulating heating pad apparatus (10) in a circumferential fashion around the compressed gas cylinder (50) to increase the temperature and concurrently the pressure of the contents (54) of the cylinder (50).

Compressed gas cylinders incorporate one or more fusible plugs embedded in the wall of the cylinder, or cylinder outlet valve, to prevent overpressurization of the cylinder due to overheating. When excessive heat is applied to the compressed gas cylinder, the fusible plug(s) melt before overpressurization can occur and cause the cylinder to rupture. Should a fusible plug melt, or a compressed gas cylinder rupture, potentially harmful gas and liquid in the cylinder will be released to the atmosphere.
As can be seen by reference to U.S. Pat. Nos.: 4,633,061; 4,695,703; 4,695,712; and 4,833,299, the prior art is replete with myriad and diverse patented constructions which provide flexible heating pads.
While the prior art constructions are adequate for the purpose and function for which they were specifically designed, they fall far short of providing the safety and economy of a flexible self-regulating heating pad that is suited to conform to and be removeable from a compressed gas cylinder.
For instance, in the U.S. Pat. No. 4,833,299 of Estes (1989), there is described a flexible heating wrap which includes a plurality of heating elements controlled by individual temperature responsive control devices which are used to regulate the quantity of heat output by the heating wrap.
This present invention utilizes the thermal characteristics of a self-regulating heating element in combination with the physical dimensions of the heating pad, and the heat retaining characteristics of the insulating material to regulate the quantity of heat output to a cylinder. The advantages of using a self-regulating heating element without other separate temperature responsive control devices include safety, as the heating pad can never exceed the melt temperature of the fusible plug(s) in the compressed gas cylinder or cylinder outlet valve; and economy of operation, by virtue of the electrical and thermal operating characteristics of the self-regulating heating element.

Flexible self-regulating heating pad for compressed gas cylinders


A look ahead column redundancy circuit provides high speed memory access to both regular memory arrays and redundant memory arrays. In the preferred embodiment of the present invention, the information on both the address bus and the information on the next address bus are decoded by redundant column decoders in parallel. The decoded information from the redundant column decoders is then provided to a redundancy column pathway as the addressing information from the address bus and the next address bus is provided to a main column pathway. The information on the address bus is latched when beginning at a new column address. The information on the next address bus is latched for the next column address when operating in a burst cycle mode. The main column pathway preferably includes a latch, a main column decoder and a main column select circuit. A disable signal is also activated by the redundant column decoders if the addressing information for a current memory access operation corresponds to an address within the redundant memory array. When activated, the disable signal disables the main column select circuit within the main column pathway. If the addressing information for a current memory access operation does not correspond to an address within the redundant memory array, then the memory access operation is performed within the main memory array without any delays. Since the decoding is performed before the information is latched onto the column address bus, the proper pathway is selected without the need for any additional delay.

The present invention generally relates to semiconductor memory devices. More particularly, the present invention relates to redundancy circuits within semiconductor memory devices.
Random access memory (RAM) is a component used within electronic systems to store data for use by other components within the system. Dynamic RAM (DRAM) is a type of RAM which uses a capacitor-type storage and requires periodic refreshing in order to maintain the data stored within the DRAM. Static RAM (SRAM) is another type of RAM which retains the information stored within the SRAM as long as power is applied. SRAM does not require periodic refreshing in order to maintain the stored data. Synchronous DRAM (SDRAM) operates within a synchronous memory system such that input and output signals are synchronized to an active edge of a system clock.
RAM is generally organized within the system into addressable blocks, each containing a predetermined number of memory cells. Each memory cell within a RAM represents a bit of information. The memory cells are organized into rows and columns. Each row of memory cells forms a word. Each memory cell within a row is coupled to the same wordline which is used to activate the memory cells within the row. The memory cells within each column of a block of memory are also each coupled to a pair of bitlines. These bitlines are also coupled to local input/output (LIO) lines. These local input/output lines are used to read data from an activated memory array or write data to an activated memory array. The pair of bitlines includes a bitline and an inverse bitline. A memory cell is therefore accessed by activating the appropriate wordline and pair of bitlines.
An address bus and next address bus are used to access specified memory cells within a memory array. The information on the address bus or next address bus is latched onto the wordline and bitline used for accessing data within the memory array. The next address bus is used when operating in a burst cycle mode to transfer large blocks of data. Addressing information is split into row and column address information which is decoded by individual row and address decoders to decrease access time. Burst cycle mode is used to transfer large blocks of data. Typically, in a burst cycle mode the memory array is divided into even and odd blocks with the address bus used to access the even block and the next address bus used to access the odd block. The next address is typically generated by automatically incrementing the address from the address bus. In this way, data may be transferred more rapidly.
Memory circuits are fabricated on wafers. Wafer yield is defined as the ratio of non-defective chips to the number of total chips fabricated on a given wafer. In general, as integration density in semiconductor memory devices increases, the likelihood of defective cells in any one memory array also increases. Therefore, the higher the integration density of chips fabricated on a given wafer, the lower the wafer yield.
It has been determined that an effective method for increasing wafer yield is to use redundant memory to replace defective memory. Redundant memory includes redundant memory cells which are configured in rows and/or columns and are used to replace rows and/or columns of the main memory array which are found to have one or more defective memory cells.
One problem which exists with the use of redundant memory circuits as substitutes for main memory circuits is access time. The column address is typically provided simultaneously to both a regular column address decoder and a redundant column address decoder. The redundant column address decoder is programmed with the addresses of defective columns. The redundant column address decoder decodes the column address and determines if the column address is programmed within the redundant memory array. If the column address corresponds to an address programmed into the redundant column address decoder, then the redundant column address decoder disables the regular column address decoder and initiates access to the redundant memory array. Otherwise, if the column address is not included within the redundant memory array, then the regular column address decoder is not disabled and the memory access is performed in the main memory array. The regular column address decoder must wait for the output of the redundant column address decoder to be valid before proceeding with the memory access. This waiting causes delays and extends the time necessary for each memory access operation.
A block diagram of a conventional redundancy address decoding circuit which requires a delay in the decoding scheme is illustrated in FIG. 1. Initially, either the information on the address bus 10 or the information on the next address bus 20 is latched by a latch 30 onto the column address bus 40. The information on the address bus 10 is latched by the latch 30 when beginning at a new column address. When the column address enable signal (CAEN) 15 is activated to a logical high voltage level, the information on the address bus 10 is passed through the transistor 13 and latched by the latch 30 onto the column address bus 40. The information on the next address bus 20 is latched by the latch 30 onto the column address bus 40 for the next address in a burst cycle mode. When the next address in a burst cycle is needed, the column address counter signal (CACTR) 25 is activated to a logical high voltage level, enabling the next address information from the next address bus 20 to be passed through the transistor 12 and latched by the latch 30 onto the column address bus 40.
The information latched by the latch 30 onto the column address bus 40 is provided as an input to both a regular column decoder 50 and a redundant column decoder 60. The regular column decoder 50 and the redundant column decoder 60 are arranged in parallel to decode the address information on the column address bus 40. If the redundant column decoder 60 detects an address within a corresponding redundant column memory array 100, then the redundant column decoder 60 sends a disabling signal to the regular column decoder 50 which disables the regular column pathway. If the redundant column decoder 60 detects an address within the redundant column memory array 100, then the redundant column decoder 60 also provides the decoded redundancy address information to a redundancy column select circuit 90. The redundancy column select circuit 90 then provides this information to circuitry (not shown) to complete the memory access operation, either read or write, within the redundancy column memory array 100. If the redundant column decoder 60 does not decode an address within the redundancy column array 100, then the regular column pathway is not disabled and the regular column decoder 50 then provides the decoded address information to a regular column select circuit 80. The regular column select circuit 80 then provides this information to circuitry (not shown) to complete the memory access operation, either read or write, within the corresponding regular column memory array 110.
Accordingly, in such a configuration, in order to ensure that the regular column pathway is properly disabled when the column address is within the redundant memory array 100, the output from the regular column decoder 50 is delayed until the disable output 70 from the redundant column decoder 60 is valid. This delay is included within each memory access operation. One previous method for resolving this delay was to load both regular and redundant column activate information and data onto both the regular local I/O signal lines and the redundant local I/O signal lines and then select the appropriate local I/O signal lines using the disable output of the redundant column decoder.
A block diagram of a prior art technique for avoiding delay during memory access operations is illustrated in FIG. 2. Initially, either the information on the address bus 200 or the information on the next address bus 210 is latched by a latch 230 onto the column address bus 240. The information on the address bus 200 is latched by the latch 230 when beginning at a new column address. The column address enable signal (CAEN) 215 is activated to a logical high voltage level, enabling the information on the address bus 200 to pass through the transistor 212 and to be latched by the latch 230 onto the column address bus 240. The information on the next address bus 210 is latched by the latch 230 for the next address in a burst cycle mode. When the next address in a burst cycle is needed, the column address counter signal (CACTR) 225 is activated to a logical high voltage level, enabling the next address information from the next address bus 210 to pass through the transistor 213 to the latch 230. The next address information is then latched by the latch 230 onto the column address bus 240.
A regular column decoder 250 and a redundant column decoder 260 are arranged in parallel to decode the address information on the column address bus 240. The regular column decoder 250 is coupled to a regular column address select circuit 280 and the redundant column decoder is coupled to a redundant column address select circuit 290. The regular column decoder outputs the regular column address corresponding to the current addressing information to the regular column address select circuit 280 which instructs drivers (not shown) to perform the memory access operation within the regular memory array 300 utilizing the local I/O signal lines 310. If the redundant column decoder 260 detects an address within the redundant column memory array 320, then the redundant column decoder 260 outputs the decoded redundancy address information to the redundancy column address select circuit 290 which instructs memory drivers (not shown) to perform the memory access operation within the redundancy column memory array 320 utilizing the redundant local I/O signal lines 325. Both the local I/O signal lines 310 and the redundant local I/O signal lines 325 are coupled to a multiplexer 330. The local I/O signal lines 310 are coupled to an input A of the multiplexer 330, while the redundant local I/O signal lines 325 are coupled to an input B of the multiplexer 330. The signal REDUN 350 is output from the redundant column decoder 260 and provided as the control input to the multiplexer 330, to control which of the I/O signal lines 310 or the redundant local I/O signal lines 325 are selected by the multiplexer 330. If the redundant column decoder 260 detects an address within the redundancy column array 320, the REDUN signal 350 is raised to a logical high voltage level by the redundant column decoder 260 and the data on the redundancy local I/O signal lines 325 at the input B to is selected by the multiplexer 330. Otherwise, if the redundant column decoder 260 does not detect an address within the redundancy column array 320, the signal REDUN is pulled to a logical low voltage level and the data on the local I/O signal lines 310 at the input A is selected by the multiplexer 330. This solution will speed up access time during memory access operations but requires significant additional layout at the cost of additional space and complexity. What is needed is an improved circuit for decoding a column address and controlling access to regular and redundancy column memory cells.
A look ahead column redundancy circuit provides high speed memory access to both regular memory arrays and redundant memory arrays. In the preferred embodiment of the present invention, the information on both the address bus and the information on the next address bus are decoded by redundant column decoders in parallel. The decoded information from the redundant column decoders is then provided to a redundancy column pathway as the addressing information from the address bus and the next address bus is provided to a main column pathway through a latch. The information on the address bus is latched when beginning at a new column address. The information on the next address bus is latched for the next column address when operating in a burst cycle mode. The main column pathway preferably includes a main column decoder and a main column select circuit. A disable signal is also activated by the redundant column decoders if the addressing information for a current memory access operation corresponds to an address within the redundant memory array. When activated, the disable signal disables the main column select circuit within the main column pathway. If the addressing information for a current memory access operation does not correspond to an address within the redundant memory array, then the memory access operation is performed within the main memory array without any additional delays. Since the decoding is performed before the information is latched onto the column address bus, the proper pathway is selected without the need for any additional delay.
In one aspect of the present invention, an apparatus for accessing a memory structure including a main memory array and a redundant memory array comprises an address bus for carrying addressing information for a current memory access operation, a main column pathway including a main column decoder for decoding addressing information and a main select circuit for selecting appropriate groups of memory cells within the main memory array for a current memory access operation and a redundant column pathway including a redundant column decoder for decoding addressing information and a redundant select circuit for selecting appropriate groups of memory cells within the redundant memory array for a current memory access operation if the current memory access operation is accessing memory cells within the redundant memory array, wherein the redundant column pathway is selected if the current memory access operation is accessing memory cells within the redundant memory array. The redundant column decoder disables the main select circuit if the current memory access operation is accessing memory cells within the redundant memory array. The redundant column decoder is provided the addressing information before the main column pathway. The main column pathway is provided the addressing information and the redundant select circuit is provided decoded redundant addressing information from the redundant column decoder in response to a control signal. The groups of memory cells are columns.
In another aspect of the present invention, a method of completing memory access operations within a memory structure including a main memory array and a redundant memory array, comprises the steps of determining from addressing information for a current memory access operation if the addressing information represents an address included within the redundant memory array, decoding a redundant address within the redundant memory array, if the addressing information represents an address included within the redundant memory array, providing the addressing information for the current memory access operation to a main column pathway and providing the redundant address to a redundant column pathway in response to a first control signal, decoding a main address within the main memory array corresponding to the addressing information; activating a group of main memory cells within the main memory array corresponding to the main address and selecting the redundant column pathway if the addressing information represents an address included within the redundant memory array. The method further includes the step of disabling the step of activating a group of main memory cells, if the addressing information represents an address included within the redundant memory array. The method further includes the step of activating a group of redundant memory cells within the redundant memory array, if the addressing information represents an address included within the redundant memory array. The step of decoding a redundant address is completed before the step of providing the addressing information. The groups of main memory cells are columns within the main memory array. The groups of redundant memory cells are columns within the redundant memory array.
In yet another aspect of the present invention, an apparatus for controlling access to a memory structure including a regular memory array and a redundancy memory array comprises an address bus for carrying addressing information for a current memory access operation, a first redundancy column decoder coupled to the address bus for decoding the addressing information, the first redundancy column decoder including a first output for providing a first decoded redundancy address and a second output for providing a disable signal, a first pass through circuit coupled to the address bus for passing through the addressing information in response to a first control signal, a first latching circuit coupled to the first pass through circuit for latching the addressing information which has passed through the first pass through circuit, a regular column decoder circuit coupled to the first latching circuit for decoding the addressing information and providing a decoded regular address, a second pass through circuit coupled to the first output of the first redundancy column decoder for passing through the first decoded redundancy address in response to the first control signal, a second latching circuit coupled to the second pass through circuit for latching the first decoded redundancy address from the first output of the first redundancy column decoder which has passed through the second pass through circuit, a regular column select circuit coupled to the regular column decoder to receive the decoded regular address and to select a corresponding regular column address within the regular memory array, wherein the regular column select circuit is also coupled to receive the disable signal from the second output of the first redundancy column decoder for disabling the regular column select circuit if the addressing information corresponds to an address within the redundancy memory array and a redundancy column select circuit coupled to the second latching circuit to receive the first decoded redundancy address and to select a corresponding redundant column address within the redundancy memory array, if the addressing information corresponds to an address within the redundancy memory array. The first redundancy column decoder is provided the addressing information before the first latching circuit. The first control signal is a column address enable signal. The apparatus further includes a next address bus for carrying next addressing information for a next memory access operation, a second redundancy column decoder coupled to the next address bus for decoding the next addressing information, the second redundancy column decoder including a third output for providing a second decoded redundancy address and a fourth output for providing the disable signal, a third pass through circuit coupled to the next address bus for passing through the next addressing information in response to a second control signal, wherein the third pass through circuit is also coupled to pass the next addressing information through to the first latching circuit and a fourth pass through circuit coupled to the third output of the second redundancy column decoder for passing through the second decoded redundancy address in response to the second control signal, wherein the fourth pass through circuit is also coupled to pass the second decoded redundancy address through to the second latching circuit. The first and second column decoders are provided the addressing information and the next addressing information before the first latching circuit. The second control signal is a column address counter signal.

Method of and apparatus for providing look ahead column redundancy access within a memory


A protective garment for use as overalls or trousers or as a pullover or jacket is made of a rectangular blank having two overlapping panels which are connected to each other along the two longitudinally extending marginal portions of the blank and, if necessary, along one transversely extending marginal portion. A first row of perforations is provided to form an elongated tongue starting at the one transversely extending marginal portion and extending midway between the longitudinally extending marginal portions toward but well short of the other transversely extending marginal portion. The perforations are surrounded by a welded or otherwise formed seam which converts the blank portions flanking the tongue into two tubes to constitute the leggins or the sleeves of a garment. The tongue is provided with one or more rows of perforations to form at least one strip which can be detached to be used as a sash or to form three strips, one to be used as a sash and the other two to be used to tie the leggins or sleeves to the legs or arms of the wearer. The blank has two weakened portions which are adjacent the other transversely extending marginal portion and can be destroyed to form two straps which are placed over the shoulders or are received in the crotch of the wearer.

The invention relates to improvements in garments, particularly for use as rainwear or as protective garments in hospitals, chemical plants, nursing homes, convalescent homes, beauty salons, homes or apartments and many other establishments. Still more particularly, the invention relates to improvements in garments which can be obtained by conversion of blanks having two panels or layers of flexible sheet material, such as metallic or plastic foil, textile material, paper or the like.
Commonly owned European Pat. No. 0 235 556 granted Jan. 16, 1991 to Edith Bachor discloses a protective garment which can be obtained by converting a twin-layer or twin-panel blank of foil or non-woven textile material. As a rule, the material is a metallic or a plastic foil which can be welded by the application of heat and/or pressure. However, the patented garment can also consist of any one of a plurality of different textile materials, particularly those made of plastic filaments and/or spunbonded materials. The blank which is to be converted into the patented garment constitutes a length of flattened hose or tube and has two tubular portions which can constitute the leggins of a garment to be used as overalls or trousers, or the sleeves of an article of clothing to be used as a pullover, jacket or vest. By sealing a transversely extending marginal portion of the blank which is adjacent the free ends of the tubular portions, the blank can be converted into a garment with sleeves or leggins which are closed at their free ends. If the blank is converted into overalls with leggins having closed free ends, the material of the overalls is stretched when the wearer is in motion, i.e., the length of the leggins increases and the crotch of the overalls descends so that it is ultimately likely to interfere with movements of the legs. This can be defined as a so-called sleeper or bunny pajamas effect. Attempts to reduce the likelihood of undesirable downward migration of the crotch include the utilization of a belt or sash. However, a belt or sash must be produced in a separate operation which contributes to the cost of the protective garment.
Swiss Pat. No. 540 019 granted Aug. 15, 1973 to Wolfgang Patzold et al. discloses an apron made of a blank having a lower marginal portion which can be separated to form a sash or belt which is applied around the waist of the wearer of the apron.
Disposable protective garments of plastic foil or the like are often obtained by converting rectangular blanks which adhere to each other end-to-end along rows or lines of weakened portions which must be destroyed in order to separate a blank from the neighboring blank. The blanks form a long row or strip which is normally convoluted onto a core to form a roll containing a large number of blanks and occupying a relatively small amount of space in storage or during transport. If the blanks are converted into aprons of the type disclosed in the Swiss patent to Patzold et al., the separable marginal portions are located between neighboring blanks and are likely to be separated with wrong blanks, i.e., a blank which is separated from the neighboring blank can be detached in such a way that its marginal portion (which is intended to be converted into a sash) continues to adhere to the neighboring blank. Thus, it can happen that a particular blank does not carry a separable sash but the neighboring blank is provided with two sashes. Moreover, the length of the sash which is to be formed in accordance with the teaching of the Swiss patent does not suffice to form a sash or belt of requisite length. This can create problems when the protective garment is to be applied over a regular garment or if the protective garment is to be worn by a corpulent person.


An actuator as a piezoelectric device has a bonding layer including titanium, a lower electrode including platinum, a piezoelectric thin film, and an upper electrode formed in this order on a substrate. Ti particles precipitate from the bonding layer onto the lower electrode. Pt that forms the lower electrode has a crystal grain size of 75 nm to 150 nm.

Piezoelectric materials such as PZT (lead zirconate titanate) have been used to form piezoelectric devices for use in actuators and sensors. Traditionally, bulk piezoelectric materials have been used. In recent years, thin film piezoelectric materials (piezoelectric thin films) have been studied and used to meet the need for a reduction in size and thickness. Particularly when a piezoelectric device is used as an actuator for an inkjet head, it is important to make the piezoelectric device smaller for each nozzle, because nozzles must be arranged at high density for high-definition image printing.
Methods for depositing piezoelectric thin films include sputtering and sol-gel techniques. Piezoelectric thin films are deposited on a substrate layer and therefore strongly influenced by the material, orientation, and other properties of the substrate layer. In order to improve the properties of piezoelectric thin films, therefore, various methods are used, such as control of the orientation of a lower electrode used as the substrate and placement of an orientation control layer between a lower electrode and a piezoelectric thin film.
A precious metal such as Pt, Au (gold), or Ir (iridium) is often used to form the lower electrode. In addition, a bonding layer including Ti or TiOx (titanium oxide) is often provided between the lower electrode and the substrate (such as an oxidized silicon substrate) in order to increase the bonding between them. For example, Patent Literature 1 discloses a piezoelectric device having a silicon oxide film, a titanium oxide film (bonding layer), a lower electrode including Pt, a PZT film (piezoelectric thin film), and an upper electrode, which are stacked in this order on a silicon substrate.
According to Patent Literature 1, Ti is deposited in the form of islands on the lower electrode by sputtering, and the PZT film is deposited on the Ti islands. It is suggested that when Ti is deposited in the form of islands on the lower electrode, the Ti islands can serve as crystal nuclei to control the orientation of PZT during the deposition of the PZT film on the lower electrode, so that the resulting PZT can have improved crystallinity (orientation) and thus improved piezoelectric properties.
For example, Patent Literature 2 also discloses such a method including depositing seed crystals (for serving as crystal nuclei) in the form of islands on a lower electrode and then depositing a piezoelectric thin film thereon. According to Patent Literature 2, after a bonding layer including Ti and a lower electrode including Pt are formed in this order on a substrate, the substrate is annealed in an oxygen atmosphere so that Ti is diffused into Pt and TiOx seeds are distributed in the form of islands on the lower electrode.
Actually, in this regard, even without annealing in the oxygen atmosphere, seed crystals (Ti) can precipitate on the lower electrode depending on the settings of the deposition conditions such as the substrate temperature during Pt deposition, because a sufficient amount of oxygen exists for the amount of the atoms on the thin film surface even when the pressure is around the back pressure of the vacuum system (10−3 Pa to 10−5 Pa).
Unfortunately, it is difficult to control the necessary amount of Ti by sputtering in the method of forming seed crystals (Ti) on the lower electrode by sputtering as disclosed in Patent Literature 1.
In this regard, Patent Literature 2 discloses that the ratio of seed crystals (TiOx) to Pt on the lower electrode surface is about 1.5% by atom. It is difficult to control the amount of Ti to a level of around 1.5% by atom by sputtering although the crystallinity of a perovskite crystal, such as PZT, deposited on the lower electrode significantly depends on the ratio of the seed crystals. Even when one atom thick layer of seed crystals are deposited, the deposition time is about few seconds although it depends on the supplied power and other conditions. Therefore, the deposition time would be shorter when the deposition on the surface is performed at a ratio of 1.5% by atom. Using sputtering, it is very difficult to form a uniform film on a substrate in such a short deposition time. If the resulting film is not uniform, the productivity will significantly decrease.
Alternatively, Ti can be precipitated from the bonding layer onto the lower electrode. In this method, appropriate control of the amount of Ti precipitation can be more easily achieved by the control of the Pt deposition temperature than in the method of forming seed crystals by sputtering. Therefore, this method is advantageous in that it can easily deposit Ti uniformly on the substrate.

Piezoelectric device, inkjet head, inkjet printer, and method of manufacturing piezoelectric device