The present invention relates to a cartridge, system, and methods that can be used for automated handling of fluids, such as blood. The cartridge can be configured to obtain a fluid sample from a sealed container, e.g., a septum sealed container. The system can be configured to handle the cartridge for operations such as obtaining a sample and/or dispensing the sample from the cartridge into, for example, a microtiter plate. The method of the invention can employ the cartridge or system of the invention.

Liquid sample processing is an everyday activity of a typical clinical, diagnostic, or research laboratory. Although the sample may include a toxic chemical or a biohazard, many conventional sample processing steps are conducted manually. Such manual processing of hazardous liquids can expose the laboratory worker to aerosols or puncture wounds. For example, sample tubes are often under either positive or negative internal pressure due to the method employed to collect the sample, changing temperature, or agitation. Opening such a tube can release an aerosol of the biohazard. Laboratories typically require employees to move samples into a large and expensive isolation hoods for opening and other steps that might release a hazardous aerosol.
Manual sample handling can compromise sample integrity. Handling dozens or hundreds of individual samples inevitably leads to human error. Human error can compromise the sample chain of custody and require costly or redundant testing and quality-control. Further, human handling of open sample tubes can lead to cross-contamination of samples.
In addition, manual sample handling can be labor intensive. Each worker can open and remove liquid from only one tube at a time. An increase in sample processing throughput is usually achieved by putting several technicians on the task in parallel. It is estimated that such manual sample processing can account for 65% of all laboratory hands-on labor costs.
In high throughput sample processing, such as whole blood or plasma analyses for infectious agents or genetic testing, large numbers of liquid samples come into the laboratories in capped and bar-coded glass or plastic vessels, e.g., VACUTAINER® tubes. Manual procedures for processing such samples can include checking the sample for clotting, scanning the barcode, verifying correspondence of sample with proper subject, placing a new number or barcode on the tube, removing the tube from a carrier, inverting the tube, uncapping the tube, disposing of the tube cap, placing the same new number or barcode on a different tube, pouring the sample into the different tube, placing the tube into a machine rack, orienting the tube for barcode reading, removing the tube from the machine rack, recapping the tube, and placing the tube into a carrier. Error in any of a variety of these labor-intensive procedures can expose a worker to hazardous substances or compromise the sample.
There remains a need for improved fluid handling systems that can rapidly and safely remove potentially harmful fluids from containers.

This patent is subject to a terminal disclaimer.

Automated fluid handling cartridge, fluid processing system, and methods


A method for treating pancreatic cancer is provided. The method comprises administering to a subject in need thereof a therapeutically effective amount of a pharmaceutical formulation, wherein the pharmaceutical formulation comprises (Z)-butylidenephthalide and is substantially free of (E)-butylidenephthalide.

Field of the Invention
The present invention relates to the uses of a pharmaceutical formulation, which comprises (Z)-butylidenephthalide, especially to the uses of the pharmaceutical formulation in treating pancreatic cancer.
Descriptions of the Related Art
The pancreas is a soft, elongated gland located in the back of the abdominal cavity of a living body. In general, the pancreas of a human has a length ranging from about 15 cm to 20 cm, a width of about 2.5 cm, and a weight ranging from about 75 grams to 100 grams. "Pancreatic cancer" refers to a malignant tumor that is generated from pancreatic cells. Ductal adenocarcinomas accounts for 90% of pancreatic cancers, wherein about 80% occurs within the head of the pancreas gland.
Pancreatic cancer tends to occur in the elderly, and the incidence rate in males is twice as high as that in females. Early pancreatic cancer usually does not show obvious symptoms, but along with the gradual growth of pancreatic tumors, patients may show symptoms of abdominal pain, back pain, jaundice, weight loss, and diarrhea. In addition, typical pancreatic cancer appears fibrosis and adhesion to surrounding tissue. Because pancreatic cancer cells often penetrate into peripheral nerves and/or invade blood vessels, almost 90% of pancreatic cancer is not treatable through surgery. Pancreatic cancer has a poor prognosis, and the five-year survival rate is less than 5%.
Current clinical therapy for pancreatic cancer includes surgery, chemotherapy and irradiation therapy, etc. In general, when the condition of a patient of pancreatic cancer allows, surgery is the first line treatment in increasing the survival rate. As for the chemotherapy, a single medicament, such as the anti-metabolites medicaments of 5-fluorouracil (5-FU) and gemcitabine, or a combination of various medicaments can be chosen based on the clinical stage of pancreatic cancer. However, the therapeutic efficacy of chemotherapy is low. Traditional chemotherapy is almost ineffective in the case of pancreatic cancer recurrence. Irradiation therapy is usually used as an adjuvant therapy during the treatment for pancreatic cancer because this therapy cannot cure unresectable pancreatic tumor. Therefore, there is still a need for a medicament for treating pancreatic cancer.
The inventors of the present invention found that Z-butylidenephthalide (Z-BP) can inhibit the growth of pancreatic cancer cells, and thus, can be used to treat pancreatic cancer. In particular, a controlled release dosage form containing Z-butylidenephthalide can be implanted into the area with pancreatic cancer cells after surgery, to achieve a locally stable high dose of Z-butylidenephthalide. As a result, Z-butylidenephthalide can penetrate into surrounding pancreatic tissue to kill "invasive residual cancer cells," to achieve the desired therapeutic effect.


Examples of refreshing a photoconductive layer in an image forming apparatus are described. In one example, a method includes performing a first refreshing cycle comprising applying, at a first refresh unit, a first refresh voltage to the photoconductive layer and applying, at a second refresh unit, a second refresh voltage to the photoconductive layer. A second refreshing cycle is performed including applying, at the first refresh unit, a third refresh voltage to the photoconductive layer, the third refresh voltage being higher than the first refresh voltage and higher than the second refresh voltage. Each of the first and second refreshing cycles electrically bias the photoconductive layer to a refresh polarity opposite to a print polarity applied during a print routine of the image forming apparatus.

Electrophotography is commonly used in digital printers or presses. Digital printing may use a variety of print material to reproduce a variety of digital sources on a variety of media. Digital printers or presses may utilize a photoconductor to apply print material to a print medium. The photoconductor may be charged and exposed to light. Charged print material, such as toner, may be attracted to areas of the photoconductor. The print material may be transferred to from the photoconductor to the print medium directly or to an offset unit. Heat and/or pressure may fuse the toner to the medium.


A front surface of a front cowl and the windscreen are disposed so as to form a gap therebetween, and a screen cover is fixed over the front surface in an engaged state. An upper portion of the screen cover covers a lower portion of the windscreen so that the gap is invisible externally. In addition, an intake port substantially in the shape of a slit elongated in the front-rear direction is provided between each side part of the screen cover and the front surface, in an obliquely rising outwardly opening shape. Traveling wind is laterally taken in through the intake ports, to be led through the gap to the inner side of the windscreen.

1. Field of the Invention
The present invention relates to a saddle type vehicle, such as motorcycle, provided with a front cowl on the front side of a driver and with a windscreen extending to the upper side of the front cowl. Particularly, the invention relates to such a vehicle in which traveling wind can be effectively introduced to the inner side of a windscreen.
2. Description of Related Art
Incidentally, in the present application, directions such as front, rear, up, down, left and right, are made with reference to a vehicle. Also, the inner surface or inner side of a windscreen refers to the windscreen's surface or side facing the driver.
In motorcycles, it is a well-known practice to cover a front surface of the vehicle with a front cowl, thereby straightening the traveling wind, and to provide on the upper side of the front cowl a transparent windscreen for covering the front side of the driver.
It is also a well-known practice to overlap a windscreen and a front cowl with each other, with a gap left therebetween, to form the overlapping part with an air intake port, and to guide the traveling wind through the intake port to the inner side of the windscreen, thereby dispelling a negative pressure inside the windscreen and preventing the inner surface of the windscreen from being fogged (see Japanese Patent No. 4090717).
Meanwhile, in the case where a windscreen and a front cowl are overlapped over each other with a gap left therebetween to form an air intake port, like in the above-mentioned related art, an overlapping part of the windscreen and the front cowl should have a certain degree of length for achieving stable intake of the traveling wind to the inner surface of the windscreen.
Since the windscreen should be formed from a comparatively heavy material, however, an increase in the size of the overlapping part leads to increases in the size and weight of the vehicle body. In addition, since a material comparatively difficult to mold is used for the windscreen, it becomes difficult for the shape of the overlapping part to be high in the degree of freedom for realizing an enhanced design. Furthermore, since the windscreen is transparent, the front cowl and the gap on the lower side are visible in the area of the overlapping part, whereby the external appearance quality may be lowered. Consequently, restrictions are imposed on design.


A firing control device for use in a pneumatic tool includes a flow path unit, a conditioning valve and a switch valve. The flow path unit is connected to a main. chamber and an operating chamber of the pneumatic tool. The conditioning valve blocks fluid communication between the main chamber and the operating chamber via the flow path unit. When the switch valve is activated, the pressure in the casing is permitted to move the conditioning valve. The conditioning valve is moved to permit the fluid communication between the main chamber and the operating chamber via the flow path unit when the switch valve is continuously activated by a predetermined time period.

A conventional pneumatic tool disclosed in U.S. Patent Application Publication 20140231485 includes a trigger, a force transmission element, a first control valve, a second control valve, a control piston that is associated with the first control valve, and a locking piston that is associated with the second control valve and that is movable within a housing cap. The second control valve is activated to drive movement of the locking piston upon depression of the trigger. The first control valve is activated to drive movement of the control piston when both of the trigger and the force transmission element are depressed. A fastener can be fired by the conventional pneumatic tool by continuously depressing the trigger and subsequently depressing the force transmission element. After the trigger is continuously depressed by a predetermined time period, the locking piston is moved onto a moving path of the control piston upon the activation of the second control valve, so as to prevent the movement of the control piston. As such, when a time delay between the depression of the trigger and the depression of the force transmission element is less than the predetermined time period, the first control valve is activated to drive movement of the control piston upon the depression of the force transmission element, so as to fire the fastener. When a time delay between the depression of the trigger and the depression of the force transmission element is greater than the predetermined time period, the control piston cannot be moved for firing the fastener upon the activation of the first control valve by virtue of the depression of the force transmission element since the control piston is locked by the locking piston.
However, since the locking piston serves as a latch for preventing the movement of the control piston, the locking piston and the control piston may easily be worn, and the air-tightness between the locking piston and the housing cap may be affected by the control piston.

Firing control device for a pneumatic tool


A control circuit for controlling multiple power supplies having their outputs coupled in series is configured to in response to an output current reaching a defined current threshold of a power supply of the power supplies, control the power supply to operate in its constant current mode so that the output current is regulated at the defined current threshold as the remaining power supplies operate in their constant voltage mode, and in response to the output voltage of the power supply reaching a defined voltage threshold, control the power supply to operate in its constant voltage mode so that the power supply provides a first regulated output voltage to its output as the remaining power supplies provide a second regulated output voltage different than the first regulated output voltage to their output. Various other systems, power supplies, control circuit and methods are also disclosed.

This section provides background information related to the present disclosure which is not necessarily prior art.
Power supplies having outputs coupled in series each commonly include an overcurrent protection (OCP) scheme. Some typical OCP schemes include a latching overcurrent protection scheme and a foldback current limiting scheme. For example, FIG. 1A illustrates a voltage-current (V-I) characteristics curve 100 of two series coupled power supplies each employing a latching OCP scheme in which an output current increases until it reaches an OCP threshold (e.g., 130% of a rated output current). At that time, the output current and voltage terminate to zero.
FIG. 1B illustrates a V-I characteristics curve 102 of two series coupled power supplies each employing a foldback current limiting scheme. In this case, one of the power supplies enters its foldback mode when an output current reaches its OCP threshold thereby causing the output current and an output voltage to decrease linearly. The output current then increases again until the other power supply enters its foldback mode causing the output current and the output voltage to decrease linearly again.
FIG. 1C illustrates a V-I characteristics curve 104 of two series coupled power supplies each employing a constant current limiting scheme and a foldback current limiting scheme in which an output current is held steady at a particular level until an output voltage reaches a defined threshold. At which time, the power supplies enter their foldback mode as explained above.

Constant current limiting protection for series coupled power supplies


An IC tester includes a test pattern storage circuit that stores a test pattern, a delay amount storage table that stores a test condition, an offset address generation circuit that divides the delay amount storage table into a plurality of regions and selects a region from the plurality of divided regions, a reference signal delay circuit that delays a reference signal according to a test condition stored in a region of the delay amount storage table selected by the offset address generation circuit, and a test waveform formation circuit that generates a test waveform according to the test pattern stored in the test pattern storage circuit and the reference signal delayed by the reference signal delay circuit.

1. Field of the Invention
The present invention relates to IC testers for testing the electrical characteristics of an IC (Integrated Circuit), and more particularly to an IC tester that can set a plurality of test conditions.
2. Description of the Background Art
In accordance with increase in the integration density and incorporation of multifunctions in an IC, the circuit complexity and the number of input and output terminals have been increased. The time required for testing the electrical characteristics of such an IC is getting longer since measurement covering a great number of items must be taken. In general, an IC tester is widely used for testing an IC. The performance of the IC tester will greatly contribute to reduce the time required for testing.
FIG. 1 is a block diagram showing a schematic structure of a conventional IC tester. The IC tester includes an CPU (Central Processing Unit) 1 for providing the overall control of the IC tester, a reference signal generation circuit 2 for generating a reference signal used in forming a test waveform, a control circuit 3 for controlling each circuit in testing an IC 12 of interest, a reference signal delay circuit 4 for delaying the reference signal generated by reference signal generation circuit 2, a test pattern storage circuit 5 for storing a test pattern of under-testing IC 12, a delay amount storage circuit for storing the amount of delay by reference signal delay circuit 4, a test waveform formation circuit 7 for forming a test waveform according to signals output from reference signal delay circuit 4 and test pattern storage circuit 5, a voltage amplify circuit 8 for amplifying the voltage of the signal output from test waveform formation circuit 7, a voltage supply circuit 9 for supplying a voltage to voltage amplify circuit 8, a D/A (digital/analog) conversion data storage circuit 10 for holding input data and providing the data to voltage supply circuit 9, and a control signal transmission bus 13 that is used by CPU 1 in providing data to respective circuits. In testing IC 12, control circuit 13 provides an address 14 to test pattern storage circuit 5 and delay amount storage circuit 6.
FIG. 1 depicts the schematic structure of one channel for the IC tester. The IC tester includes a plurality of the circuitry shown in FIG. 1. In testing IC 12, CPU 1 sets the data for test pattern storage circuit 5, delay amount storage circuit 6 and D/A conversion data storage circuit 10 for each channel.
The process of forming a test waveform input to under-testing IC 12 will be described hereinafter. CPU 1 includes an internal memory for storing a test program according to the test specification of under-testing IC 12 and test conditions. CPU 1 executes the test program to generate a test waveform according to a plurality of test items. The generated test waveform is provided to under-testing IC 12. For example, CPU 1 has all the test patterns required for testing prestored in test pattern storage circuit 5 when testing is to be carried out. In executing the first test item, CPU 1 has the amount of delay corresponding to the time from the transition of the reference signal until the transition of the test waveform stored for each test pattern in delay amount storage circuit 6. The voltage value of that output waveform is stored in D/A conversion data storage circuit 10. Then, the test is initiated. In general, CPU 1 has the data for executing the next test item stored in delay amount storage circuit 6 and D/A conversion data storage circuit 10 after the test of the previous test item is completed.
Reference signal generation circuit 2 generates a reference signal for testing IC 12. The cycle of a reference signal corresponds to the cycle of the test waveform generated by test waveform formation circuit 7.
Test pattern storage circuit 5 holds the test pattern of the test item stored by CPU 1. When IC 12 is tested, a test pattern is sequentially provided to test waveform formation circuit 7 in synchronization with the change of address signal 14 applied from control circuit 3.
Delay amount storage circuit 6 holds the amount of delay stored by CPU 1. When IC 12 is tested, the amount of delay is provided to reference signal delay circuit 4 in synchronization with the change in address signal 14 output from control circuit 3. The details of delay amount storage circuit 6 will be described afterwards. Reference signal delay circuit 4 delays the reference signal output from reference signal generation circuit 2 in a programmable manner according to the amount of delay from delay amount storage circuit 6. The delayed signal is provided to test waveform formation circuit 7.
Test waveform formation circuit 7 holds the test pattern output from test pattern storage circuit 5 in synchronization with the delayed reference signal output from reference signal delay circuit 4. The output of test waveform formation circuit 7 is provided to voltage amplify circuit 8.
D/A conversion data storage circuit 10 holds and provides to voltage supply circuit 9 the digital data stored by CPU 1. Voltage supply circuit 9 converts the digital data into an analog voltage value, which is provided to voltage amplify circuit 8. Voltage amplify circuit 8 amplifies the voltage of the test waveform output from test waveform formation circuit 7 according to the analog voltage value from voltage supply circuit 9. The amplified voltage is provided to under-testing IC 12.
When the IC tester is executing one test item, CPU 1 issues a control signal via transmission bus 13 to store data into test pattern storage circuit 5, delay amount storage circuit 6, and D/A conversion data storage circuit 10. Then, CPU 1 sends to control circuit 3 an instruction to initiate testing of IC 12. Control circuit 3 responds to this instruction from CPU 1 to increment address signal 14 provided to test pattern storage circuit 5 and delay amount storage circuit 6 in synchronization with a reference signal output from reference signal generation circuit 2. Test pattern storage circuit 5 and delay amount storage circuit 6 sequentially provide the test pattern and delay amount corresponding to address signal 14, respectively. Test waveform formation circuit 7 produces a test waveform according to the delayed reference signal from reference signal delay circuit 4 and the test pattern from test pattern storage circuit 5. The test waveform is provided to voltage amplify circuit 8. Here, delay amount storage circuit 6 and D/A conversion data storage circuit 10 are referred to as "test condition storage circuit", and test waveform formation circuit 7 and voltage amplify circuit 8 are referred to as "waveform formation circuit".
By sequentially carrying out the above process for each test item, the testing operation on IC 12 is carried out. In general, D/A conversion data storage circuit 10 continuously outputs the data set by CPU 1 prior to the test until the entire test is completed.
FIG. 2 is a block diagram showing a specific structure of delay amount storage circuit 6 of FIG. 1. Delay amount storage circuit 6 includes a pointer storage circuit 20 storing the pointer used in selecting an amount of delay, and a delay amount storage table 21 for storing the amount of data that is provided to reference signal delay circuit 4 and three-state buffers 22 and 23.
Delay amount storage circuit 6 is taken as an example to be described hereinafter of the storage circuits such as delay amount storage circuit 6 and D/A conversion data storage circuit 10 that has data updated rather frequently.
A plurality of delay amount data that will be used by reference signal delay circuit 4 are stored in delay amount storage table 21 by CPU 1. The pointer of the delay amount data stored in delay amount storage table 21 is stored in pointer storage circuit 20 by CPU 1. Pointer storage circuit 20 has a capacity that can store data identical to the number of test patterns stored in test pattern storage circuit 5. Data corresponding to address signal 14 output from control circuit 3 is provided to delay amount storage table 21 as the pointer.
In storing data into pointer storage circuit 20, CPU 1 renders the output of three-state buffer 22 to a high impedance state. Three-state buffer 23 is turned on. In response, the data from CPU 1 is provided to pointer storage circuit 20. CPU 1 stores data into pointer storage circuit 20 by sequentially changing the address of pointer storage circuit 20 via control circuit 3.
In storing data into delay amount storage table 21, CPU 1 renders three-state buffer 23 to a high impedance state. Three-state buffer 22 is turned on. In response, the address from control circuit 3 is provided to delay amount storage table 21. CPU 1 sequentially stores data by applying the address to delay amount storage table 21 via control circuit 3.
In testing IC 12, the pointer corresponding to address signal 14 output from control circuit 3 is provided from pointer storage circuit 20. The amount of delay selected by that pointer in delay amount storage table 21 is provided to reference signal delay circuit 4. Delay amount storage table 21 accommodates a plurality of types of ICs such as an IC 1 that requires four delay amount data and an IC 2 that requires N delay amount data as shown in FIG. 2 since the number of the delay amount to be set depends upon the type of the IC to be tested.
FIGS. 3A-3D are diagrams for describing the procedure of forming a waveform in a conventional IC tester. According to the delay amount output from delay amount storage circuit 6 shown in FIG. 3A, reference signal delay circuit 4 delays the reference signal of FIG. 3B to the signal shown in FIG. 3C. Test waveform formation circuit 7 holds the test pattern output from test pattern storage circuit 5 with the delayed reference signal, which is output as a test waveform shown in FIG. 3D.
The IC tester must carry out a test item corresponding to various test conditions for the purpose of testing the electrical properties of an IC of interest. These test conditions are reset for each test item. The time required for resetting the test conditions is great for an IC that has a complex function. In practice, an IC tester has a plurality of the circuitry shown in FIG. 1 corresponding to one channel. Since it is necessary to reset the test conditions for each circuitry, the amount of data for the reset operation is great. There was a problem that the time required for resetting the test conditions occupied a major portion of the IC testing time.

IC tester having region in which various test conditions are stored

Ryoden Semiconductor System Engineering Corporation


A surface acoustic wave device including a substrate and an electrode structure formed on the substrate, said substrate being made of a doubly rotated Y-cut (.alpha.X-.theta.Y cut) Langasite (La.sub.3 Ga.sub.5 SiO.sub.14), a rotation angle .alpha. from the X axis being substantially 50.degree..+-.5.degree. and a rotation angle .theta. from the Y axis being substantially 19.degree.-30.degree.. The device further includes a normal type electrode structure which reveals a natural single-phase unidirectional transducer property together with an anisotropy of the substrate. The device further has a double electrode type electrode structure which cancels the directionality, or a floating type electrode structure which reverses the directionality. The electrode structure is formed to constitute a surface acoustic wave filter having a low insertion loss and an excellent phase property.

1. Field of the Invention
The present invention relates to a surface acoustic wave device such as surface acoustic wave (SAW) filter, surface acoustic wave resonator and surface acoustic wave guide, and more particularly relates to a surface acoustic filter with low loss utilizing a natural single-phase unidirectional transducer (NSPUDT) property.
2. Description of the Related Art
Heretofore, surface acoustic wave devices have been desired to have large electro-mechanical coupling coefficient K.sup.2, small power flow angle PFA, small temperature coefficient of delay time TCD and so on. Furthermore, recent electronic devices are required to be small in size, light in weight and economical in power consumption.
There has been widely used a transversal type surface acoustic wave filter including a substrate having a piezoelectric property, a transmitter side transducer having interdigitally arranged positive and negative electrode fingers, which are connected to two opposite phase output terminals of a single-phase signal source, and a receiver side transducer having interdigitally arranged positive and negative electrode fingers. Such a transversal type surface acoustic wave filter has been used for extracting a desired signal component within a given frequency range.
In such a surface acoustic wave filter, it has been required to reduce an insertion loss and to suppress undesired ripple components within a given frequency range. Since usual interdigital type electrode structures have a bidirectional property, the insertion loss could not be reduced smaller than a theoretical insertion loss of 6 dB. This insertion loss of 6 dB is too large to realize a SAW filter having a desired property.
In order to mitigate such a drawback, there has been proposed a multi-transducer system, in which on both sides of each of a plurality of transmitter side transducers, there is arranged a pair of receiver side transducers. In a surface acoustic wave filter of such a multi-transducer system, it is possible to reduce the insertion loss to about 1.5-2.0 dB. However, in the multi-transducer system, the control of a plurality of transducers is very difficult and good phase and frequency properties could not be attained. Moreover, it is quite difficult to manufacture such a multi-transducer system device. In order to improve the performance of the surface acoustic wave device, it is also very important to flatten a phase characteristic, to suppress pass band ripples and to reduce a suppression band.
In order to meet the above mentioned requirements, it has been proposed to use a unidirectional transducer that can realize a very small insertion loss which is theoretically lower than 1 dB and has excellent phase and frequency characteristics. There have been proposed various types of the unidirectional transducers. They may be roughly classified into:
(a) multi-phase type unidirectional transducer, and PA1 (b) single-phase type unidirectional transducer. PA1 a substrate made of a single crystal of doubly rotated Y-cut (.alpha.Y-.theta.X cut) Langasite (La.sub.3 Ga.sub.5 SiO.sub.14) and having a surface, a rotation angle .alpha. from the Y axis being substantially 50.degree..+-.5.degree. and a rotation angle .theta. from the X axis being substantially 19.degree.-+.degree.; PA1 a first electrode structure formed on said surface of the substrate such that a natural single-phase unidirectional transducer property is revealed together with an anisotropy of the substrate; and PA1 a second electrode structure formed on said surface of the substrate such that the natural single-phase unidirectional transducer property due to the anisotropy of the substrate is cancelled. PA1 a substrate made of a single crystal of doubly rotated Y-cut (.alpha.Y-.theta.X cut) Langasite (La.sub.3 Ga.sub.5 SiO.sub.14) and having a surface, a rotation angle .alpha. from the Y axis being substantially 50.degree..+-.5.degree. and a rotation angle .theta. from the X axis being substantially 19.degree.-30.degree.; PA1 a first electrode structure formed on said surface of the substrate such that a natural single-phase unidirectional transducer property is revealed together with an anisotropy of the substrate; and PA1 a second electrode structure formed on said surface of the substrate such that a directionality of the natural single-phase unidirectional transducer property due to the anisotropy of the substrate is reversed.
As the latter single-phase type unidirectional transducer, there have been proposed various types. For instance, there has been proposed a single-phase unidirectional transducer utilizing an asymmetry of electrode structure and an internal reflection due to the mass load effect, a reflection bank type unidirectional transducer having a reflection bank between exiting electrodes, a single-phase unidirectional transducer utilizing a reflection by floating electrodes, and a natural single-phase unidirectional transducer utilizing anisotropic property of a substrate. In surface acoustic wave devices including these unidirectional transducers, the directionality is realized by making an exciting wave and a reflected wave to be in-phase in a wave propagating direction and to be in opposite phase in an opposite direction.
Heretofore, substrates of surface acoustic wave devices are made of single crystals of quartz, lithium tantalate (LiTaO.sub.3) and lithium niobate (LiNbO.sub.3). In U.S. Pat. No. 5,698,927, there is proposed the use of lithium tetraborate (LiB.sub.4 O.sub.7) single crystal as a substrate revealing the natural single-phase unidirectional transducer operation. However, the known single crystals are not optimal for the surface acoustic wave device, and it is particularly difficult to obtain a surface acoustic wave filter having desired characteristics.
For instance, in order to realize a surface acoustic wave resonator, it is required that the electro-mechanical coupling coefficient K.sup.2 be large, the reflection be large, the power flow angle PFA be small and the temperature coefficient of delay time TCD be small. However, the electro-mechanical coupling coefficient K.sup.2 of quartz is about 0.2 and the reflection of quartz is small. Therefore, it is rather difficult to realize a surface acoustic wave resonator having desired characteristics by using the quartz substrate.
A substrate for the surface acoustic wave filter is required to have a large electro-mechanical coupling coefficient K.sup.2, a small reflection, a small power flow angle PFA and a small temperature coefficient of delay time TCD. However, the use of a piezoelectric substrate having such characteristics has not been proposed.
In the above mentioned known single-phase unidirectional transducer, except for the natural single-phase unidirectional transducer, the electrode structure has become very complicated. Particularly, the distance between adjacent electrode edges and the width of an electrode have to be smaller than .lambda./4. Upon increasing the operation frequency, the distance and width should be much smaller, and it is quite difficult to manufacture electrodes of such small distance and width.
In order to mitigate the above mentioned drawbacks, there has been proposed a natural single-phase unidirectional transducer (NSPUDT), in which the unidirectionality is realized by utilizing the anisotropy of the piezoelectric substrate although the normal type electrode structure having an electrode edge distance of .lambda./4 and an electrode width of .lambda./4 is used. It is known that quartz substrate, LiNbO.sub.3 substrate and LiTaO.sub.3 substrate, show the NSPUDT operation due to anisotropy. However, in these known piezo-electric substrates, the electro-mechanical coupling coefficient K.sup.2 is small, the temperature coefficient of delay time TCD is not zero, the power flow angle PFA is not zero, and a directionality reversed electrode structure could not be realized easily. Due to these problems, it is very difficult to realize an ideal surface acoustic wave device.
Furthermore, in order to obtain a surface acoustic wave device which is small in size, light in weight and low in electric power consumption, it is advantageous to decrease the propagating velocity of a surface acoustic wave. However, the above-mentioned piezoelectric substrates have a relatively high propagating velocity which is not lower than 3000 m/sec. Therefore, the known piezoelectric substrates cannot produce a surface acoustic wave device which is small in size, light in weight and low in electric power consumption.
Recently, a piezoelectric substrate made of Langasite (La.sub.3 Ga.sub.5 SiO.sub.14) single crystal has been proposed for the surface acoustic wave device. It has been reported that the Langasite single crystal belongs to the trigonal system to which the quartz crystal also belongs, and has a higher electro-chemical coupling coefficient K.sup.2 and a higher phase transition temperature than the quartz crystal ("The 17.sup.th ULTRASONIC SYMPOSIUM Preliminary Theses", page 305, 1996). In the same publication, page 306, there is also described that in an X-cut Langasite single crystal, the temperature dependency becomes almost zero when a rotation angle .theta. from the Y axis is set to a value within a range of 10.degree.-20.degree.. Further, in "1996 IEEE INTERNATIONAL FREQUENCY CONTROL SYMPOSIUM, FILTER AND RESONATOR USING LANGASITE", pp. 379-382, 1996, it has been reported that a Langasite single crystal is used as a substrate for a bulk resonator. It should be noted that the bulk resonator is quite different from the surface acoustic wave device. Moreover, in "Japan Journal of Applied Physics", Vol. 37, part 1, No. 5B, page 2909, 1998 as well as in "27.sup.th EM SYMPOSIUM Preliminary Theses", 1998, page 125, it has been reported that a doubly rotated Y-cut (.alpha.X-.theta.Y cut) Langasite single crystal substrate having a rotation angle .alpha. from the X axis of 50.degree. and a rotation angle .theta. from the Y axis of 22.5.degree.-24.degree. has a superior temperature property which is compatible with the ST-X cut quartz crystal substrate.
As stated above, several reports have been issued about the velocity of the surface acoustic wave, electro-mechanical coupling coefficient K.sup.2 and temperature dependency for the Langasite single crystal substrates. However, no one has reported the electrode reflection property. Particularly, the above publications do not mention at all that the Langasite single crystal has the unidirectionality due to the anisotropy, i.e. NSPUDT property.
The inventors have reported in "Lecture Theses of The Acoustical Society of Japan", 1-8-22, page 997, 1997 that the Langasite single crystal substrate can be advantageously used for surface acoustic wave devices. In this publication, it is reported that the doubly rotated Y-cut Langasite single crystal substrate having a rotation angle .alpha.=0.degree.-30.degree. and a rotation angle .theta.=0.degree.-20.degree., shows a good NSPUDT property. After various experiments and analyses, the inventors have found that the power flow angle PFA of such a Langasite single crystal substrate is not zero, and therefore this known Langasite single crystal substrate could not produce a surface acoustic wave device having an optimal performance.

Surface acoustic wave device comprising langasite single crystal substrate


A five stage treatment system for treating oily wastewater to fit it for discharge to surface waters comprising a coalescer for separating free oil, an ultrafiltration unit for separating emulsified oil, an activated carbon filter for separating residual light organic compounds, a cation exchanger for removing heavy metal ions, a pH adjusting unit for adjusting the treated water to substantially neutral pH prior to discharge, and a controller for regulating the operation of the system. An optional gravity separation stage and/or a clarifier stage may also be included, if desired. Flow of permeate from the ultrafiltration stage is monitored and control valves admitting feed solution to the ultrafiltration unit or discharging retentate from the ultrafiltration unit are adjusted in response to the measured values to maintain a desired rate of permeate flow.

The present invention relates to a method and apparatus for processing oily wastewaters, such as bilge water from ships, boats and the like.
Numerous processes and activities produce wastewater which is contaminated with oil. For example, the bilge water which leaks into ships or boats frequently becomes contaminated with oil leaked or spilled from machinery or tanks on the vessels. Many industrial processes, such as machining of metal, also produce wastewater contaminated with oil.
Current environmental laws encourage both waste minimization and resource recovery while current economic conditions require them. The rapid consumption of inherently limited petroleum deposits by modern industrial societies makes it economically desirable to recover and reuse oil. Ecological considerations also have led governments to promulgate environmental regulations which prohibit disposing of oily wastes in such a way as to contaminate the environment. Yet currently available technologies for recovery or disposal tend to be expensive or less than fully effective. Thus, while both economic and environmental considerations make it desirable to recover oil from wastewater, considerable difficulty may be encountered in attempting to separate and recover oil from oily wastewaters.
Oily wastewaters generally contain oil in two forms. The first is free oil which is simply intermixed with the aqueous phase. The second form is emulsified oil in which tiny particles of oil are stably dispersed throughout the aqueous phase. Although oil and water are generally immiscible, it is often costly and time consuming to separate them, and in some cases it is so difficult as to be considered impractical. The difficulties are compounded when the proportion of oil in a wastewater is small, e.g., less than about 10 percent. Despite the great deal of effort which has been expended in this field, there remains a need for improved methods and apparatus for treating oily wastewater to separate the oil from the water.

Method and apparatus for processing oily wastewater


A manual braking mechanism is adapted for manually overridable remote conl. The mechanism is disposed in a generally planar region forward of a vehicle's handle bar that does not interfere with the vehicle body or a human vehicle driver. The mechanism includes a base plate releasably clamped to the vehicle's handle bar and a housing fixed on the base plate. A brake cylinder in the housing connects to a control lever swingable on the base plate about a lever axis, and the cylinder's reaction force biases the lever toward a brake releasing position. A link pivots on the plate at the lever axis, has a hinge connection remote from the lever axis and has a carrier closer to the lever axis to the hinge connection. The carrier cammingly rotates the lever as the link swings on the lever axis. The mechanism has a frame whose first leg connects to the base plate at the lever axis and the frame's second leg is releasably clamped to the handle bar. The clamps for the base plate and second leg can be loosened to turn the modified braking mechanism on the handle bar. A third leg of the frame pivotally supports one end of a motor unit while the motor unit's opposite end engages the link's hinge connection. An extensor translates into and from the motor unit to swing the link so that the lever may release or apply the vehicle brake. The hinged connection utilizes a manually removable quick release pin that allows rapid decoupling of the motor unit from the link, after which the motor unit can be swung free of the link.

Currently the US Army is investigating methods to remove unexploded shells from artillery ranges and secured battle zones. One promising method is the use of remotely controlled vehicles having robotic accessories for shell removal. Since the vehicles will perform highly risky operations, it is likely that they will be damaged or destroyed with some regularity. It is therefore preferred that such vehicles be as cheap and expendable as possible. One practical and relatively inexpensive way to obtain such vehicles is to modify small commercially available off-road vehicles. It is preferred that these modified vehicles be capable of both manual and robotic operation.
To meet part of the above requirements, we have uniquely converted an existing manual brake actuator into a manually overridable, remotely controllable device. The converted actuator has a base and a clamp releasably fixing the base to the handle bar of a vehicle. A brake cylinder biases a lever swingable on the base toward a brake releasing position. A link having a common swing axis with lever has a hinge connection remote from this common axis, and the link includes a carrier closer to the common axis than to the hinge connection. The carrier cams upon the lever as the link swings the lever in a brake applying direction.
The converted actuator has a one-piece frame easily made from flat metal stock, and a first leg of the frame connects to the base at the common axis. A second frame leg is releasably clamped to the handle bar, whereby clamps for the base plate and second leg can be loosened to turn the actuator to a new angular position on the handle bar. A third frame leg swingably mounts one end of a motor unit which drives the link. The opposing end of the motor unit is releasably pivoted to the link by a quick release pin at the link's hinge connection. The motor's back drive force is greater than the biassing force of the cylinder, so that if the motor unit loses power during remote brake actuation, the motor unit will keep the actuator in a brake applying mode. Removal of the release pin decouples the motor unit so that the motor unit can not pivot the link or maintain brake actuation.

The United States of America as represented by the Secretary of the Army


A dynamic pointing accuracy evaluation system is used in conjunction with a weapon system that includes a gun that fires a projectile from a barrel toward a target. The firing of the projectile occurs upon receipt of a shoot command from an automated fire control system that is activated by a firing command generated by a gunner viewing the target through a gun sight. The dynamic pointing accuracy evaluation system includes a firing-image camera mounted to a barrel of the gun and aimed parallel to a boresight of the gun. A photo trigger command line transmits a photo trigger command from the fire control system to the firing-image camera. The firing-image camera produces a firing image upon receipt of the photo trigger command. A computer receives the firing image and determines a calculated strike location from the firing image and from a range of the gun to the target.

The main weapon system of a modern military tank such as the M60A3 tank is a gun that fires projectiles responsive to the firing command of a human gunner. However, the firing command does not go directly from the gunner to the gun. The firing command is supplied to a fire control system, typically a director-type fire control system, that coordinates the firing command with other information, such as the motion of the gun, the motion of the vehicle, the motion of the target, the range of the target, the type of projectile, environmental conditions, and other information. The fire control system constantly performs and updates the ballistic solution for the potential target. The fire control system typically calculates a desired gun-sight offset in elevation (i.e., how much of an angle above the target the gun should be pointed to hit the target) and the desired gun-sight offset in azimuth (i.e., how much of an angle left or right of the target the gun should be pointed to hit the target). With this information and the constant measurements of the actual gun-to-sight offsets in elevation and azimuth, the fire control system constantly calculates the error values between the desired offsets and the actual offsets. These error values are used to reposition the gun and to determine when the error values are sufficiently close to zero that a shot would be of sufficiently high probability for a hit (alternatively stated, is inside the "coincidence window").
After receiving the firing command from the gunner and performing the fire-control calculations, the fire control system produces a shoot command that actually fires the gun at the appropriate moment. Thus, the fire control system takes into account many factors that cannot be readily evaluated quickly by the human gunner, while the gunner makes the decisions on target selection and the time at which the firing sequence is started.
In order to evaluate the performance of the fire control system and to train the gunner to work with the fire control system under a wide variety of conditions, the conventional practice is to perform a series of live-fire tests. In these tests, the tank and its crew, including the gunner, are transported to a live-fire range. A statistically significant number of rounds are fired under various conditions, such as the tank standing still, and the tank moving over various surfaces and at various speeds, and under a variety of weather conditions and using a variety of types of ammunition. These live-fire tests are expensive to perform, as the transportation costs and operating costs are high, and the cost of each round fired is typically about $500.
Additionally, the live-fire tests have shortcomings in regard to the results. The accuracy in hitting the target with the projectile depends upon variations in extraneous factors other than the gunner and the tank system, such as the variations in the propulsive and flight properties from projectile to projectile ("ammunition dispersion"), and the wind and the weather ("environmental dispersion"). These factors cannot be maintained constant in a live-fire test series, so that there is always some uncertainty as to whether the statistical results of the live-fire test series reflect the performance of the gunner and the weapon system, or whether the extraneous dispersion factors are the dominant effect.
Various attempts have been made to improve upon the present approach. Motion tracking techniques are used to determine the positions of the gun and the site used by the gunner, but this approach cannot determine the pointing accuracy of the weapon system. Smaller caliber, inexpensive test projectiles may be used, but they are even more subject to the extraneous factors. Tank simulators are employed in early training of tank crews, but do not provide a sufficiently realistic simulation in advanced training of the actual field conditions that the tank crew will experience, such as bouncing, vibration, and noise for the particular tank that the gun crew will use.
There is a need for an approach to evaluating and training gunners, and evaluating the tank weapon system, which is less expensive than the current approach and also is not affected by the extraneous factors. The present invention fulfills this need, and further provides related advantages.

Dynamic pointing accuracy evaluation system and method used with a gun that fires a projectile under control of an automated fire control system


A method of preparing for polishing the end face of a fiber optic connector having an optical fiber held by a ferrule. A laser beam removes the portion of the optical fiber tip projecting beyond a predetermined distance. The beam has a spot size selected so as to also remove excess epoxy.

Various grinding and polishing machines have been proposed to prepare connectors having a desired end face surface. Examples are shown in Saito et al., U.S. Pat. No. 5,007,209: Moulin, U.S. Pat. No. 4,905,415, and others. A coupler end face having an optical fiber distal end projecting from a surrounding ferrule is ground, normally on a pad of some sort. A time-consuming preparatory step involves preparation of the projecting fiber tip. If the tip is too short, it may not be polishable; if too long, it can perforate the grinding pad.
The optical fiber distal ends are often secured in their ferrules by an adhesive such as epoxy. In practice, excess epoxy must also be ground off, increasing the time necessary for the grinding process. A fast and accurate method for preparing the coupler end faces would be an improvement in the art.

Laser removal of excess optical fiber prior to connector polishing


A phase-lock loop circuit in a demodulator includes a timing recovery block and a carrier recovery block. The demodulator for demodulates a digital signal including symbols. The phase-lock loop includes an integrator processing a block of N samples to produce an average of the N symbols, and means for supplying the average of the N symbols to the timing recovery block and the carrier recovery block every NT period, where T is a sample time interval.

This invention relates generally to demodulators for digital television receivers, and more particularly to phase-lock loop units in demodulator front-ends.
The era of digital television broadcasting in the United States began officially with the introduction of terrestrial services in November, 1998. It is expected that cable and satellite digital TV broadcasting will soon become available as well. In all three transmission media, i.e., terrestrial, cable, and satellite, MPEG-2 is the common standard for video coding at the source of television signals. Because of the similarity in video coding in the three transmission media, it is possible to share signal processing functional blocks in receivers for the three media. This is the so-called multi-mode digital television receiver.
In the multi-mode digital TV receiver, the conventional approach for implementing demodulators dictates a hardware solution. This is due to the high symbol rates, i.e., 10.76 MHz for 8VSB, 5.38 MHz for 256QAM, and up to 45 MHz for QPSK. Symbols can be, for example, six or eight bits. Hardware offers computational speed not attainable by software. However, specialized hardware is very difficult to change for future upgrades, the size of the chip is large, and the cost is relatively high when compared with implementation that use software and common digital signal processors.
Therefore, it is desired to provide an alternatives to hardware implemented demodulators. These alternatives would provide flexibility, low cost, without degradation of performance while demodulating symbols at a very high rate.
The invention provides means for updating timing and error recovery blocks of a demodulator front-end of a digital television receiver. A phase-lock loop circuit in a demodulator including a timing recovery block and a carrier recovery block. The demodulator for demodulating a digital signal including symbols. The symbols are sampled at a time interval equal to or a fraction of the symbol rate. The phase-lock loop includes an integrator processing a block of N samples to produce an average of the N samples, and means for supplying the average to the timing recovery block and the carrier recovery block every NT period, where T is a sample interval. As a feature, the phase-lock loop is under software control and can operate in any one of three block-based modes as determined by a frequency offset.

Programmable digital signal processor for demodulating digital television signals

Mitsubishi Electric Research Laboratories, Inc.


A digital automatic gain control device for use in a communication terminal of a mobile radio communication system employing a time-division duplex (TDD) transmission. A transmission power amplifier and a reception amplifier, which constitute the communication terminal, are fully composed of digital elements. In a transmission mode, a reception data latch is cleared to turn off the reception amplifier, so as to prevent a distortion of a modulated transmission signal due to regeneration and coupling of a modulated transmission waveform generated from a receiver. On the contrary, in a reception mode, a transmission data latch is cleared to prevent the carrier generated from the transmitter from being leaked toward a receiver, thereby preventing deterioration of a reception sensitivity of the receiver. Therefore, the transmission and reception gain can be accurately controlled based on the accurate timing control by the control processor.

1. Field of the Invention
The present invention relates to a band spread radio communication system, and more particularly to an automatic gain control method and device for use in a communication terminal of a mobile radio communication system employing a time-division duplex (TDD) transmission.
2. Description of the Related Art
In a conventional mobile radio communication system employing a time-division duplex (TDD) transmission, a mobile station automatically controls a gain of a transmitter/receiver in a communication terminal, in order to prevent a deterioration of the system performances due to a mutual interference with another mobile station. The time-division duplex transmission refers to a bidirectional transmission for periodically (e.g., 1msec) switching a channel to a transmission mode and a reception mode. A mobile station controls a gain of a transmission power amplifier disposed in a transmitter based on a mobile station transmission power control command included in a received frame from a base station, in order to maintain an appropriate transmission power during a transmission mode. Further, the mobile station appropriately controls a gain of a reception amplifier in order to compensate for an attenuation of a reception power according to a distance from the base station, during a reception mode.
Conventionally, the gains of the transmission power amplifier and the reception amplifier are controlled by an analog automatic gain control method in which the gain is controlled according to an intensity of a received signal. Such a prior art method is well disclosed in U.S. Pat. No. 5,257,283, issued on Oct. 26, 1993, by Klein S. Gilhousen, el al., entitled Spread Spectrilm Transismitter Power Control Method And System.
Referring to FIG. 1, which is described in the U.S. Pat. No. 5,257,283 patent, there is illustrated a block diagram of an analog automatic gain control system for use in a mobile radio communication system. As illustrated, a signal received from an antenna is transferred to an intermediate frequency amplifier (IF AMP) 6 via a down-converter 2 and a band pass filter (BPF) 4. An output of intermediate frequency amplifier 6 is applied to a base band processor 10 via an analog-to-digital (A/D) converter 8, and also applied to an automatic gain control (AGC) detector 12. Automatic gain control detector 12 has a double function. First, in the reception mode, automatic gain control detector 12 generates a control voltage for controlling a gain of intermediate frequency amplifier 6 to maintain a constant level of the received signal. Second, in the transmission mode, an output of automatic gain control detector 12 is compared with a reference power level value generated from a control processor 18, in order to control a transmission power based on a value set by a transmission signal from the base station. A comparator 14 compares the output of the automatic gain control detector 12 with the reference power level value received from control processor 18 via a digital-to-analog (D/A) converter 20. An output of comparator 14 is applied to a nonlinear filter 16 which has a nonlinear output characteristic with respect to a variation of the output of comparator 14. The output characteristic of nonlinear filter 16 sets an increasing rate of the transmission power control voltage to a value lower than a decreasing rate thereof, in order to prevent the deterioration of the system performances due to a rapid increase of the transmission power. In the meantime, an intermediate frequency amplifier 24 controls a signal generated from a transmission modulator (not shown) based on a control signal generated from control processor 18 via a digital-to-analog converter 22, in the transmission mode of the mobile station. Digital-to-analog converter 22 generates the control signal for controlling a gain of intermediate frequency amplifier 24. An output signal from intermediate frequency amplifier 24 is applied to an intermediate frequency amplifier 26. Since a gain of intermediate frequency amplifier 26 is controlled by an output of nonlinear filter 16, a transmission is signal output of intermediate frequency amplifier 26 is automatically controlled.
It is noted from the foregoing description that the prior art analog automatic gain control system includes the automatic gain control detector 12 for detecting an intensity of the received signal. However, it is difficult to form automatic gain control detector 12 at a broad variation range of a reception power level. Further, there is needed an additional means for converting an output level of automatic gain control detector 12 into a proper control voltage range for controlling the gain of intermediate frequency amplifier 6. Moreover, the prior art analog automatic gain control system needs comparator 14 for comparing the control signal output from control processor 18 with the output value of automatic gain control detector 12 in order to control the transmission power during the transmission and reception modes. However, as being composed of analog elements, comparator 14 is sensitive to noise so that a response time may be limitative. Therefore, it is not easy to accurately control the output of comparator 14. Besides, the prior art analog automatic gain control system needs digital-to-analog converter 20 for converting the digital signal output from control processor 18 into the analog value to supply the analog value to comparator 14. However, a low conversion speed of digital-to-analog converter 20 becomes a main cause that delays the response time of the automatic gain control system. In particular, in case that the signal that the mobile station has received is a burst signal, it is difficult to control the gain in order to maintain a constant received signal level through one data frame interval. Further, it is not easy to realize nonlinear filter 16 in the light of its features. In order for nonlinear filter 16 to control the gain of intermediate frequency amplifier 26, there is needed an additional circuit, i.e., a level converter for converting an output level of nonlinear filter 16 within a gain variable control voltage range of intermediate frequency amplifier 26. However, although the level converter is additionally used, it is still not easy to constitute nonlinear filter 16 in the light of its nonlinear output characteristic. It should be noted that all the problems mentioned above are mainly caused because the prior art system employs the analog automatic gain control method.

Digital automatic gain control method and device for use in communication terminal of mobile radio communication system


A microcomputer according to the present invention includes: collecting unit for generating and collecting a series of trace information for each execution process of a program to be evaluated in a preset sampling period for a predetermined number of repetitions; outputting circuit for outputting the series of the trace information for each repetition; and decimating circuit for deleting any of the trace information collected at each repetition so that the outputting circuit can output all of the trace information to be collected within the sampling period when the collecting circuit has finished repetitive collection process.

1. Field of the Invention
The present invention relates to a microcomputer that is effective for debugging in a real working environment, and more particularly, it relates to a microcomputer that collects trace information at a plurality of times in a debugging operation while decimating it at a predetermined time period as well as a debugging system for controlling the debugging by the microcomputer and a method for collecting such trace information.
2. Description of Related Art
Upon development of a microcomputer system, verification of its operation and debugging of its software may be commonly performed by a so-called debugger, which is a development support device using any debugging tool such as an ICE (In-Circuit Emulator). The ICE comprises features for substituting for a CPU or a program memory to be developed and for debugging programs and hardware efficiently. For example, such features may include a real-time trace feature that verifies executing conditions in real time, a break feature that stops running at a given address, a single-step feature, a feature for setting data in a register, and the like.
Further, the ICE has a memory mapping feature that stores a program under development on its own memory instead of memory on the microcomputer system to verify the operation of the program. It allows debugging of the program and hardware while executing the developed program both on the ICE main unit and on the system to be evaluated, enabling efficient debugging work.
However, there have been appeared various problems with using the debugger comprising the above ICE, as a result of the fact that working frequencies of microcomputers have increased and that, at present, a CPU, a memory element and peripheral feature blocks may be often contained in one chip with advancement of LSI higher integration technology.
More specifically, for example, increase of a working frequency of a microcomputer may cause delay in signal transmission between the ICE main unit and the microcomputer to be evaluated, which may interfere with real-time trace. In particular, signal delay in a path between the ICE main unit and the microcomputer to be evaluated or in a buffer that stores trace information read out from the microcomputer by the ICE may significantly affect the real-time trace. Consequently, it becomes more difficult to perform the real-time trace that monitors access by the CPU to an external bus at the clock frequency at which the actual microcomputer runs.
In addition, miniaturization and diversification of microcomputers with advancement of LSI higher integration technology affect prices of probes that connects the ICE main unit to a printed circuit board on which the microcomputer to be evaluated is installed. For example, even a microcomputer having same architecture may have different number of pins and different circuit arrangement if its peripheral features are implemented by different circuits, thereby necessitating development of corresponding probes. Further, by miniaturization of microcomputers, it becomes necessary to use expensive adaptors to connect the above probes, which may cause cost-related problems.
As means for solving the above problems, a debugging system has been developed, wherein a debugging feature is incorporated in a microcomputer itself and exchanges debugging information with a debugger via pins dedicated for debugging. An example of such debugger is a microcomputer that is compliant with JTAG (Joint Test Action Group) in which a debugging feature is incorporated.
In the microcomputer compliant with JTAG, shift registers called cells are arranged between an internal logic circuit and each pin, which can monitor signals passing there or inject any data into the signals. Thus, the cells have features equivalent to those of the test probes in conventional testing methods.
FIG. 14 is a diagram schematically showing a configuration of a conventional debugging system as mentioned above, wherein the debugging features are incorporated in the microcomputer compliant with JTAG. In this figure, there is shown a host computer 100 for controlling a debugging tool 101, which can perform various configuration settings for debugging and which sends setting information to the debugging tool 101. The debugging tool 101 exchanges debugging information and trace information with a microcomputer with built-in debugging features 103 via pins that are dedicated for debugging and compliant with JTAG. The pins dedicated for debugging include five JTAG interface pins consisting of a TCK pin (a clock input pin) specified by IEEE 1149.1, a TDI pin (a pin for serially inputting test instruction code or test data), a TDO pin (a pin for serially outputting test instruction code or test data), a TMS pin (a pin for inputting selection of a test mode that controls state transition in a logic circuit to be evaluated in the microcomputer 103), and a TRST pin (a pin for inputting test reset that asynchronously initializes the logic circuit to be evaluated in the microcomputer 103).
Besides, there are pins to output signals from a debugging features block 106 to the debugging tool 101 including a TRCLK pin (a trace clock pin for outputting trace clock signals from the debugging features block 106 to a debugger 102), a TRSYNC pin (a trace synchronization pin for outputting a signal that indicates a leading location of a packet constituting trace information), and a TRDATA pin (a trace outputting pin for outputting the trace information). The debugger 102 equates to a configuration consisting of the host computer 100 and the debugging tool 101. The microcomputer with built-in debugging features 103 comprises the debugging features block 106 that provides the debugging features as well as a CPU 104 and a memory-peripheral features block 105 in one chip. Further, there are shown the CPU 104 for the microcomputer 103, the memory-peripheral features block 105 for the microcomputer 103, and the debugging features block 106 that performs debugging under control of the debugger 102.
FIG. 15 is a block diagram showing a configuration of the microcomputer with built-in debugging features 103 in FIG. 14. In this figure, a jump requesting signal 104a is output from the CPU 104 to a trace controlling section 109 to specify a branch-target address according to a branch instruction executed by the CPU 104. An executed instruction size signal 104b is output from the CPU 104 to the trace controlling section 109 to specify size of an instruction executed from the previous branch. A JTAG controlling section 107 that controls the debugging features by communicating with the debugging tool 101 via the JTAG interface is comprised of control registers that is related to debugging and accessible via the JTAG interface, a TAP (Test Access Port) controller that controls access via the JTAG interface, and the like. Trace trigger generating unit 108 generate a trace start signal 108a, a trace end signal 108b and data access detection signal 108c for controlling trace operation of the trace controlling section 109. The trace start signal 108a instructs the trace controlling section 109 to start outputting trace information, the trace end signal 108b instructs the trace controlling section 109 to finish outputting the trace information, and the data access detection signal 108c specifies the address that the CPU 104 has accessed and the data read therefrom or written thereto. The trace controlling section 109 generates the trace information that traces an internal state of the microcomputer 103 and outputs it to the debugging tool 101, and an address bus 110a and a data bus 110b transfer address signals and data in the microcomputer 103, respectively. It is to be noted that elements similar to those in FIG. 14 are given like reference numerals and description of these elements is thus omitted.
FIG. 16 is a block diagram showing a configuration of the trace controlling section in FIG. 15. In this drawing, a trace controlling circuit 111 receives trace-related information from outside and controls trace operation. A latch signal 111a is generated by the trace controlling circuit 111 to allow a buffer 113 to latch the address on the address bus 110a and data on the data bus 110b. An output controlling section 112 controls outputs from the trace controlling section 109 and outputs the trace clock signal TRCLK, the trace synchronization signal TRSYNC and the trace output TRDATA to the debugging tool 101. The buffer 113 latches information from the address bus 110a and the data bus 110b to create the trace information. A FIFO buffer 114 constitutes the output controlling section 112 and outputs the trace information in a predetermined bit unit from the buffer 113 to the debugging tool 101. Here, it is also to be noted that elements similar to those in FIG. 14 and FIG. 15 are given like reference numerals and description of these elements is omitted.
Next, the operation of the conventional debugging system will be described.
Here, a case will be described wherein execution of a program by the CPU 104 in the microcomputer with built-in debugging features 103 is traced in real time. First, as shown in FIG. 14, the microcomputer 103 is connected to the debugging tool 101 via the pins dedicated for debugging and compliant with JTAG. Then, the user uses the debugger 102 to download the program to be evaluated, which is stored on the memory-peripheral features block 105 in the microcomputer 103. It allows the user to determine trace conditions for the above program to be evaluated and make settings of the trace-related information according to the above conditions using the host computer 100. For example, when the CPU 104 executes the program to be evaluated, address information, which is stored in the memory space of the microcomputer 103 and acts as a trigger to start or end collection of the trace information and so on, is configured. This information is sent to the debugging tool 101 by the host computer 100.
The debugging tool 101 sets the above information via the pins dedicated for debugging and compliant with JTAG on a trace register (not shown) that is one of cells in the JTAG controlling section 107. The CPU 104 in the microcomputer 103 executes the program to be evaluated in response to an instruction from the debugger 102. At this time, the CPU 104 outputs the above information set in the trace register to the trace trigger generating unit 108 via the buses 110a, 110b. Using this information, the trace trigger generating unit 108 generates the trace start signal 108a, the trace end signal 108b and the data access detection signal 108c and outputs them to the trace controlling section 109.
In the trace controlling section 109, the trace controlling circuit 111 therein asserts the above trace start signal 108a to start outputting the trace information. More specifically, for example, when the CPU 104 executes a branch instruction in the above program to be evaluated, it generates the jump requesting signal 104a that specifies the branch-target address and the executed instruction size signal 104b that specifies the size of the instruction executed from the previous branch and outputs them to the trace controlling circuit 111. The trace controlling circuit 111 asserts the jump requesting signal 104a to output the latch signal 111a to the buffer 113. It allows the branch-target address to be taken in the buffer 113 via the address bus 110a. At this time, the trace controlling circuit 111 outputs the executed instruction size signal 104b to the buffer 113.
From the executed instruction size signal 104b, the trace controlling circuit 111 acquires the size of the instruction executed from the previous branch and sets it in the buffer 113. It allows the branch-target address to be taken in the buffer 113 from the address bus 110a sequentially, and therefore the branch trace information that traces each branch-target address and the size of the instruction executed from the previous branch in execution process of the program to be evaluated in the CPU 104 is generated. By outputting the branch-target address and the size of the instruction executed from the previous branch, the branch-source address and the branch-target address of the program can be notified. The branch trace information is output from the buffer 113 to the FIFO buffer 114. Then, the output controlling section 112 outputs the branch trace information in the FIFO buffer 114 by 8 bits at a time to the debugging tool 101 via the TRDATA pin. The output controlling section 112 also outputs the trace clock signal (TRCLK) as well as the trace synchronization signal (TRSYNC) that indicates a leading location of a packet constituting the branch trace information to the debugging tool 101 via respective pins.
On the other hand, when the trace controlling circuit 111 asserts the above data access detection signal 108c, it outputs the latch signal 111a to the buffer 113. At this time, via the address bus 110a and the data bus 110b, the address accessed by the CPU 104 as well as the data read therefrom and written thereto is acquired by the buffer 113 and then the data trace information comprised of the accessed address and the corresponding data is created. The data trace information is output from the buffer 113 to the FIFO buffer 114.
After that, the output controlling section 112 outputs the data trace information in the FIFO buffer 114 by 8 bits at a time to the debugging tool 101 via the TRDATA pin. The output controlling section 112 also outputs the trace clock signal (TRCLK) as well as the trace synchronization signal (TRSYNC) that indicates a leading location of a packet constituting the branch trace information to the debugging tool 101 via respective pins.
Finally, when the trace controlling circuit 111 asserts the above trace end signal 108b, it stops outputting the latch signal 111a to the buffer 113 to stop outputting the trace information.
As described above, the debugger 102 can acquire execution sequence and data access sequence of the evaluated program by the CPU 104 in the microcomputer 103 in real time from the branch trace information and the data trace information. By utilizing such information, the debugger 102 can debug the microcomputer in real time.
The conventional microcomputer of the above-described construction has such a problem that the trace information may not be output fully in case of successive branches and the like, in other words, a so-called overflow of the trace information may occur, thereby adversely affecting the real-time trace of the program.
The above problem will be described more specifically. For example, assuming that one unit of the trace information is comprised of 72 bits and the debugging features block 106 outputs the above trace information by 8 bits at a time from the TRDATA pin, it takes 9 clocks to output the one unit of the trace information. Here, if new branch occurs within 9 clocks after the immediately proceeding branch, the branch-target address of the newly created branch trace information is output from the buffer 113 to the FIFO buffer 114 while the previous branch trace information including the immediately proceeding branch-target address is still output from the FIFO buffer. Consequently, the immediately proceeding branch-target address is overwritten by the new branch-target address of the next created branch, and as a result, both of the address information can not be output in a complete form.
In this regard, it may be contemplated to solve this problem by increasing the outputting speed of the trace information by the debugging features block 106. However, it is difficult to increase the trace clock (TRCLK) frequency in comparison with acceleration of access of the CPU 104 to the memory-peripheral features block 105, because the trace information is output via the external pin (TRDATA pin).
Further, it may be also contemplated to output the trace information in parallel by using multiple external pins (TRDATA pins), but it is not appropriate because it may increase a cost of the microcomputer 103 and moreover restrict miniaturization of its size.


A circularity measuring apparatus includes: a rotary table on which a measured object is loaded; a contact-type stylus configured to contact a substantially circular measured surface of the measured object with an inclination; a holder configured to hold the stylus within a predetermined stroke range so that an inclination angle of the stylus is changeable; a displacement detector configured to detect a displacement of the inclination angle of the stylus, which is caused due to a contact between the stylus and the measured surface; and a controller configured to: estimate a position of a top end of the stylus based on an output of the displacement detector; and instruct the holder in an optimal stroke range in the position.

1. Field of the Invention
The present invention relates to a circularity measuring apparatus and, more particularly, an improvement in a protecting mechanism of a detector with a contact type stylus.
2. Description of the Related Art
In order to collect various data about a deviation from circular form such as circularity, concentricity, coaxiality, or the like, of a measured object such as a circular column, a circular cylinder, or the like, the circularity measuring apparatus is well known. In the circularity measuring apparatus, the measured object is loaded on a rotary table, and then the rotary table is turned while detecting a surface position of a measured rotating body with a contact type stylus, or the like, so that data of surface positions of the measured rotating body are collected and thus the circularity is measured/calculated, as disclosed in JP-A-1-259211, JP-A-6-300505, JP-A-2003-302218, JP-A-2004-108787, JP-A-2007-71726, WO2006/008891 and Japanese Patent No. 2701141.
However, when a notch, especially an edged notch, or the like exists on an outer periphery of the measured object, the stylus falls into the notched portion, and the stylus is caught by an edge portion of the notch. When the rotary table continues to turn as it is, the stylus may be broken down.
Therefore, in the prior art, when the stylus comes up to the notched portion, a measuring program is suspended once, and then the stylus is fixed such that this stylus does not fall into the notched portion. Then, the stylus is caused by turning the rotary table to pass through the notched portion, and then the measuring program is started once again.
Similarly, when a measurement of an inner surface of a bore is performed, the breakage of the stylus may also be caused. More particularly, normally a holder for holding the stylus is considerably larger in diameter than the stylus. Therefore, the stylus is positioned to have an inclination such that an outer diameter portion of the holder does not contact the measured object. For this reason, a top end of the stylus is not always positioned on a center line of the holder. Upon inserting the stylus into the bore, the top end of the stylus being held obliquely is caught by an outer periphery of the bore even though the holder is positioned just over the bore, and thus the stylus may also be broken down.
Therefore, in this case, the measuring program is also suspended once upon inserting the stylus into the bore, then the stylus is fixed, then the stylus is inserted into the bore, and then the fixation of the stylus is released.


A system of interconnectable construction elements created from molded plastic, wood or metal, and which include four basic construction elements, wherein a first and second construction element include a hemispherical segment and a planar connecting segment and complementary male and female connectors, and third and fourth construction elements that include a hemispherical segment with complementary male and female connectors, wherein the first and second construction elements can be coupled together, the third and fourth construction elements can be coupled together, or one of the first and second construction elements can be coupled to a complementary one of the third or fourth construction elements.

1. Field of the Invention
This invention relates generally to construction and model building toys. Specifically, the invention is a system of construction elements that are coupled together to form various shapes and models. The construction elements are capable of being interconnected and configured to form interesting, educational, and entertaining designs, models, and construction projects. The nature of the construction elements also enables movement of some construction elements relative to other construction elements when coupled together.
2. Description of Related Art
The state of the prior art is replete with building blocks and other similar types of toys that enable construction elements to be coupled together to build models, shapes, patterns or designs in three dimensions. While these construction elements are referred to as toys, it should not be assumed that they are simplistic devices. The construction elements are capable of building complex shapes and models. Furthermore, they often include the ability to incorporate actuable elements such that they can be powered by mechanical or electrical devices, or even by manual manipulation. The result is that the construction elements are often minor engineering feats in and of themselves.
Given this introduction to so-called toy construction elements, it should not be surprising to realize that construction elements are capable of rather amazing and even ingenious ways of interlocking to thereby form rather complex models, shapes, patterns and designs.
However, given the fact that there are many different types of construction elements, and that there are many different types of connection schemes that can be used to connect them, it should also not be surprising that new and advantageous construction elements and ways of connecting them together are still possible.
Accordingly, it would be advantageous to provide a plurality of building elements that include new and advantageous means of building construction projects, models, shapes, patterns or designs, wherein only a small number of construction elements are capable of being combined in a variety of ways to enable an imaginative user to build both simple and complex projects. Finally, it would be advantageous to provide a plurality of construction elements that can be actuated so as to pivot, rotate, and otherwise move relative to each other by application of mechanical force to thereby animate the construction projects, models, shapes, patterns or designs.

Interconnectable model construction elements