Methods are provided for testing a honeycomb body comprised of a core portion comprising honeycomb cell walls and a circumferential skin portion overlying at least some outer honeycomb cell walls. The circumferential skin portion includes a cement mixture layer. The method comprises the step of directing a fluid stream from a pressurized fluid source at the honeycomb body. The fluid stream is capable of separating at least part of the skin portion from the outer honeycomb cell walls when the adherence between at least part of the skin portion and the outer honeycomb cell walls is below a minimum threshold. In one example, the method further comprises the step of inspecting at least part of the interface between the honeycomb body and the skin portion during or after directing the fluid stream at the honeycomb body. In further examples, an apparatus is provided for testing the honeycomb body.

Conventional honeycomb bodies are known to include a core portion with honeycomb cell walls and a circumferential skin portion overlying outer honeycomb cell walls of the core portion. The honeycomb bodies are extruded from a batch material, dried to remove excess moisture and then fired to complete the processing of the honeycomb bodies. Unfortunately, it sometimes happens that during the firing process at least partial separation of the skin portion from the core portion can occur. When the skin separates from the core portion of the honeycomb after firing the honeycomb may either be discarded or additional processing steps must be taken to mend the skin.

Methods for using a fluid stream to test a honeycomb body


The present invention relates to flavor or fragrance composition comprising at least one compound of the formula 1

Swiss patent 557 423 describes 3-mercapto carboxylic esters of the general formula I
wherein R1 represents an alkyl or alkenyl or alkadienyl group with 1 to 6 carbon atoms, and R2 represents an alkyl or alkenyl group containing 3 to 9 carbon atoms. These 3-mercapto carboxylic esters are known as flavor or fragrance compounds, and possess either green organoleptic properties, e.g. leaf green (3-mercapto-4-methylhexanoic acid ethyl ester), green fruity (3-mercapto-4-methylhexanoic acid hex-3-enyl ester), green and pungent (3-mercapto-4-methylhexanoic acid 2-hexenyl ester), or fatty organoleptic properties (e.g. 3-mercaptooctanoic acid ethyl ester, 3-mercaptononanoic acid methyl ester, 3-mercaptodecanoic acid ethyl ester or 3-mercapto-4-ethylhexanoic acid ethyl ester). An exception is 3-mercapto-4-methylhexanoic acid hexa-2,4-dienyl ester with a sulfurous, onion and garlic-like note. The latter-mentioned compound demonstrates that a small change in the structure of the compound can cause a dramatic change of the odor properties; e.g. a hexa-2,4-dienyl group instead of a hex-3-enyl group changes the organoleptic character from green-fruity to onion, garlic-like.
The flavor and fragrance industry is further interested in new ingredients with a clear fruity character. Thus, the above mentioned compounds would be of interest if they do not have the disadvantage that the fruity note is always combined with green and/or fatty notes.

Organoleptic compositions: use of 3-mercapto alkanoic acid esters as flavor ingredients

Abstract: or a precursor thereof, wherein R1 represents a branched or unbranched alkyl, alkenyl or alkadienyl group containing 1 to 8 carbon atoms and R2 represents a methyl or an ethyl group and to a method of flavoring a food, a beverage or a consumer healthcare or household product using at least one of these compounds.


A detection device and method for detecting the presence of an agent in a fluid. The device includes a membrane having first and second sides. The membrane allows a stimulus, e.g. ultraviolet light, to dissolve in response to presence of the agent. A source is positioned on a first side of the membrane. The source sources the stimulus toward the membrane. A detection structure is disposed on the second side of the membrane for detecting the stimulus. The detection structure generates an output voltage in response to the intensity of the stimulus detected. As the membrane dissolves, the intensity of the stimulus detected changes.

Potential biological attacks against large scale civilian populations have become an important issue in homeland security. By way of example, the anthrax cases in the United States in 2001 and the ricin case on Capitol Hill in 2004 have proven that the threat of a biological attack is real. In order to thwart any potential biological attack, the development of a civilian biodefense plan is crucial. Consequently, there has been an enormous effort to develop practical and efficient biosensors in recent years.
Most present biosensors take advantage of biologically active materials for high sensitivity and selectivity. In general, the biosensor includes a biorecognition structure (e.g., a membrane) in contact with or interrogated by a transducer. The biologically active material recognizes a particular biological molecule through a reaction, specific adsorption, or other physical or chemical process, and the transducer converts the output of this recognition into a usable signal, usually electrical or optical. Many approaches have been explored to achieve ultra-sensitive detection of bio-species. These biodetection approaches can be categorized as either an engineering-oriented approach or a biological-oriented approach. In other words, most biodetection schemes are either based on relatively complex electronic, photonic and/or electrochemical methods or more elegant biomolecular methods (e.g. enzyme linked immunosorbent assay, or ELISA) typically with an optical or spectrometry-based readout.
By way of example, one process utilizes photonics integrated on a microchip to study the interaction between the optical field and the target bio-analyte. Because most biorecognition processes occur in an aqueous ambient, this approach requires the integration of photonics, highly sensitive microelectronics and microfluidic systems on a single microchip. The use of ion-channel switches as biosensors has also been explored, but the bioelectronic interface is a delicate one. Often, when an approach promises very high sensitivity, the output signal from the biorecognition is very small, thus requiring extremely highly-sensitive on-chip microelectronics for signal amplification, processing and wireless transmission. The high demand of these approaches on system integration and high sensitivity photonics and electronics circuitry presents a big challenge to the biosensors in terms of cost, reliability and power consumption. The more biomolecular based approaches, like ELISA, are simple, but typically require a macro scale spectrometry system to quantify the output.
Therefore, it is a primary object and feature of the present invention to provide a bioagent detection device that is highly sensitive and selective.
It is a further object and feature of the present invention to provide a bioagent detection device that is small in size and weight and is inexpensive to manufacture.
It is a still further object and feature of the present invention to provide a bioagent detection device that provides continuous monitoring of a user selected environment.
In accordance with the present invention, a detection device is provided for detecting the presence of an agent in a fluid. The device includes a membrane having first and second sides. The membrane allows passage of a stimulus therethrough in response to presence of the agent. A source is positioned on a first side of the membrane. The source sources the stimulus toward the membrane. A detection structure is disposed on the second side of the membrane for detecting the stimulus.
The detection device includes a body that defines a first chamber for accommodating the membrane therein. The membrane is fabricated from a polymeric material that dissolves in response to exposure to the agent. The source includes an ultraviolet light emitting diode for generating ultraviolet light having an intensity. The ultraviolet light is the stimulus. The detection structure includes an ultraviolet light detector. The ultraviolet light detector generates an output voltage in response to the intensity of the ultraviolet light detected. A mask is positioned between the source and the detection structure. The mask prevents passage of the stimuli therethrough.
In accordance with a further aspect of the present invention, a detection device is provided for detecting the presence of an agent in a fluid. The detection device includes a body defining a chamber. The chamber accommodates the flow of fluid therein. A membrane is disposed in the chamber of the body. The membrane allows for the passage of a stimulus therethrough in response to presence of the agent in the chamber. A source is positioned on a first side of the body. The source directs the stimulus toward the membrane. A detection structure is disposed on the second side of the body for detecting the stimulus.
The stimulus is ultraviolet light and the source includes an ultraviolet light emitting diode for generating the ultraviolet light. The detection structure includes an ultraviolet light detector. The ultraviolet light detector generates an output voltage in response to the intensity of the ultraviolet light detected. The membrane is fabricated from a polymeric material that dissolves in response to exposure to the agent. A mask is positioned between the source and the detection structure. The mask prevents passage of the stimulus therethrough. The body includes an upper surface and lower surface. The chamber extends through the body and the mask is coated on the lower surface of the body. It is contemplated for the ultraviolet light to be at a predetermined wavelength and for the membrane to have a different absorption of light than the fluid at the predetermined wavelength.
In accordance with a further aspect of the present invention, a method of detecting the presence of an agent in a fluid is provided. The method includes the steps of engaging a membrane with the fluid and generating a signal in response to detection of a stimulus directed at the membrane.
The membrane is formed from a polymeric material that dissolves in response to exposure to the agent. The step of generating a signal includes the additional steps of directing the stimulus having an intensity at the membrane and detecting the stimulus. An output voltage is generated in response to the intensity of the stimulus detected. The stimulus is directed toward a first side of the membrane and the stimulus is detected on a second side of the membrane.
The method may also include the additional steps of positioning the membrane in a chamber of a microfluidic device and flowing the fluid through the chamber. The stimulus is ultraviolet light at a predetermined wavelength. The membrane has a different absorption of light than the fluid at the predetermined wavelength.


A spare data terminal for inputting/outputting spare memory cell data to the outside of a semiconductor memory device and a terminal for inputting/outputting normal memory cell data are provided separately from each other. In a test mode, the data terminals are coupled in parallel to internal data line pairs and, simultaneously, a spare data line pair is coupled to the spare data terminal. Thus, test time for detecting a defective bit in the semiconductor memory device can be shortened.

1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a redundancy circuit for repairing a failure in normal memory cells by replacement. More particularly, the invention relates to a configuration for shortening a test time of a semiconductor memory device having a defect repaired by performing a replacement on an internal data line (IO line) basis.
2. Description of the Background Art
FIG. 18 is a diagram schematically showing the configuration of an array portion of a conventional semiconductor memory device. In FIG. 18, the semiconductor memory device includes a memory mat MM divided into a plurality of IO unit blocks IBO to IBn along the row direction, a row/column decoder band RCB for selecting a memory cell in memory mat MM, and a data path DPH for transmitting/receiving data to/from the selected memory cell in memory mat MM. In each of IO unit blocks IBO to IBn, memory cells of 32 bits are simultaneously selected at the time of column selection. For the memory cells (32IO) of 32 bits simultaneously selected, a spare memory array and a spare IO line pair SIO for repairing a defective memory cell column are provided. To the spare IO line pair, spare memory cells in the spare memory array are coupled. In each of the IO unit blocks IBO to IBn, in defective column repairing, a defective column is repaired by replacing the corresponding internal data line pair (IO line pair) with the spare IO line pair.
In row/column decoder band RCB, a row decoder for selecting a row of memory cells in memory mat MM, and a column decoder for selecting a column of the memory cells in memory mat MM are aligned. As will be described in detail later, a word line for transmitting a row selection signal from the row decoder and a column selection line for transmitting a column selection signal from the column decoder are disposed in parallel with each other in the row direction.
Data path DPH includes a circuit for inputting/outputting data between the semiconductor memory device and an outside of the semiconductor, an input buffer and a write driver for writing data, a preamplifier and an output buffer for reading data, and a spare replacement circuit for replacing a defective column with an IO line pair to repair the defective column.
In the semiconductor memory device shown in FIG. 18, replacement with a spare IO line for repairing a defective column is executed on the IO unit block basis (IBO to IBn). Specifically, in each of IO unit blocks IB0 to IBn, normal memory cells and spare memory cells for repairing a defective normal memory cell are disposed.
FIG. 19 is a diagram schematically showing the configuration of IO unit block IB0 illustrated in FIG. 18. Since IO unit blocks IB0 to IBn have the same configuration, in FIG. 19, IO unit block IB0 is representatively shown. In FIG. 19, IO unit block IB0 is divided into a plurality of row blocks RB#0 to RB#15 along the column direction. Each of row blocks RB#0 to RB#15 is divided into a plurality of unit memory arrays UMA along the row direction. By unit memory arrays UMA aligned in the column direction, a column block CB# is formed. In FIG. 19, each of row blocks RB#0 to RB#15 is divided into 33 unit memory arrays UMAs. As column blocks CB#, therefore, 32 column blocks CB#0 to CB#31 and a spare column block SCB#0 are disposed.
In correspondence with column blocks CB#0 to CB#31, internal data line pairs (global data line pairs) GIO0 to GIO31 are disposed, respectively. For spare column block SCB#0, a spare internal data line pair (spare global data line pair) SGIO0 is disposed. In unit memory array UMA, memory cells are arranged in rows and columns. A row block RB# is selected by the row decoder in the row/column decoder band, and column selection is performed on the unit memory array in the selected row block by the column decoder disposed for the selected row block.
Global data line pairs GIO0 to GIO31 and spare global data line pair SGIO0 are shared by the unit memory arrays UMA included in column blocks CB#0 to CB#31 and spare column block SCB#0, respectively. One row block is selected, column selection is performed in the selected row block, and data in the memory cells of 33 bits including a spare memory cell data is transferred. In a row block RB#, the normal and spare memory cells are simultaneously selected and coupled to global data line pairs GIO0 to GIO31 and spare global data line pair SGIO0.
FIG. 20 is a diagram showing the configuration of IO unit block IBO more specifically. Each of the other IO unit blocks IB1 to IBn has a similar configuration. In FIG. 20, in IO unit block IBO, unit memory arrays UMA are arranged in 16 rows and 33 columns. Unit memory array UMA has memory cells arranged in 256 rows and 16 columns. In row blocks RB#0 to RB#15, spare word lines SWL0 to SWL15 are disposed, respectively. A defective memory cell row is repaired on a row block basis.
In row block RB#0, word lines WL0 to WL255 and spare word line SWL0 are disposed being shared by corresponding 33 unit memory arrays UMA. Column selection lines CSL0 to CSL15 are disposed being shared by 33 unit memory arrays UMA.
In row block RB#1, word lines WL256 to WL511 and spare word line SWL1 are disposed, and column selection lines CSL16 to CSL31 are disposed in the row direction.
In row block RB#15, word lines WL3840 to WL4095, spare word line SWL15, and column selection lines CSL240 to CSL255 are provided in the row direction and shared by unit memory arrays UMA in row block RB#15.
In each of row blocks RB#0 to RB#15, word lines, spare word line, and column selection lines CSL are provided being shared by corresponding unit memory arrays UMA. In memory cell selection, consequently, selection of memory cell row and column is executed also in spare column block SCB#0. In each of unit memory arrays UMA, according to a 1/16 decoding operation, one of 16 columns is selected and coupled to the corresponding global data line GIO (in GIO0 to GI031). Simultaneously, in spare column block SB#0 as well, a spare memory cell column is selected and coupled to spare global data line pair SGIO0.
Spare column block SCB#0 is used to repair a defective column on the row block basis in IO unit block IB0 or replace a defective global data line pair GIO. Without waiting for a result of determination whether a defective column address is designated or not, normal memory cells and spare memory cells are simultaneously selected. After the spare determination, when a defective column address is designated, the corresponding defective global data line pair GIO is replaced by the spare global data line pair SGIO0. By performing a column selecting operation before the spare determination, time for accessing a column (writing/reading of data) is shortened.
FIG. 21 is a diagram schematically showing an example of the configuration of a unit memory array UMA. In FIG. 21, unit memory array UMA includes normal memory cells NMC disposed in plural rows and plural columns (256 rows and 16 columns) and spare memory cells SMC aligned in a row. Normal memory cells NMC and spare memory cells SMC are aligned in the column direction.
Word lines WL are disposed in correspondence with the rows of normal memory cells NMC. In unit memory array UMA, 256 word lines are disposed. In FIG. 21, word lines WL0 to WL255 are disposed. To each of normal word lines WL0 to WL255, memory cells in the corresponding row are connected. To spare word line SW0, spare memory cells SMC are coupled. Normal memory cells NMC and spare memory cell SMC are aligned in each column, and bit line pairs BLP0 to BLP15 are disposed in correspondence with the memory cell columns. Each of bit line pairs BLP0 to BLP15 consists of bit lines BL and ZBL (not shown). Corresponding to crossings between word lines WL and spare word line SWL0, and bit line BL or ZBL, memory cells NMC and SMC are disposed.
For bit line pairs BLP0 to BLP15, sense amplifiers SA0 to SA15 are disposed, respectively. When activated, sense amplifiers SA0 to SA15 differentially amplify potentials of corresponding ones of bit line pairs BLP0 to BLP15 and latch the amplified potential.
Sense amplifiers SA0 to SA15 are coupled to a global data line pair GIO via column selection gates CS0 to CS15 receiving column selection signals CSL0 to CSL15. Column selection signals CSL0 to CSL15 are commonly transmitted to unit memory arrays UMA included in corresponding row block RB# as shown in FIG. 20. In unit memory array UMA, one of column selection gates CG is made conductive in accordance with column selection signals CSL0 to CSL15, and corresponding bit line pair BLP (one of BLP0 to BLP15) is coupled to global data line pair GIO via sense amplifier SA (one of SA0 to SA15).
Therefore, the memory cells of 32 bits in IO unit block IB and a memory cell of one bit in the unit memory array in the spare column block are simultaneously selected. In one memory mat, memory cells of 32xc2x7(n+1) bits and memory cells of (n+1) bits in spare column block are simultaneously selected.
FIG. 22 is a diagram schematically showing an example of the configuration of a read data path for outputting data included in data path DPH illustrated in FIG. 18. FIG. 22 shows the configuration for output data Dout0 to Dout31 of 32 bits. The read data path shown in FIG. 22 is provided for each of IO unit blocks IBO to IBn.
In FIG. 22, the read data path includes: preamplifiers PK0 to PK31 provided for global data line pairs GIO0 to GIO31, respectively, for ampliying memory cell data on global data line pairs GIO0 to GIO31 when activated; a spare pre-amplifier SPK provided for spare global data line pair SGIO, for amplifying memory cell data on spare global data line pair SGIO when activated; multiplexers MX0 to MX31 provided for preamplifiers PK0 to PK31, respectively, each for selecting either an output signal of corresponding one of preamplifiers PK0 to PK31 or an output signal of spare preamplifier SPK; latch circuits RLFK0 to RLFK31 provided for multiplexers MX0 to MX31, respectively, and each made conductive when clock signal CLK is at the L level, to pass an output signal of corresponding one of multiplexers MX0 to MX31; and latch circuits RLK0 to RLK31 provided in correspondence with latch circuits RLFK0 to RLFK31, respectively, and entering a through state when clock signal CLK is at the H level, to pass output signals of latch circuits RLFK0 to RLFK31, for outputting output data bits Dout0 to Dout31.
Latch circuits RLFK0 to RLFK31 enter a latching state when clock signal CLK goes high. On the other hand, latch circuits RLK0 to RLK31 enter a latching state when clock signal CLK goes low.
In order to set a selection path of multiplexers MX0 to MX31, the read data path includes: a spare determination circuit 500 for generating spare address signals SPADD1 to SPADD31 for designating a defective global data line pair to be replaced by spare global data line pair SGI; an OR circuit 502 for receiving a test mode spare control signal TMSPCC and a spare address signal SPADD0 and generating a spare selection signal SPSEL0 to multiplexer MX0; and an AND circuit 504 for receiving spare address signals SPADD1 to SPADD31 and a complementary test mode spare control signal ZTMSPCC, generating spare selection signals SPSEL1 to SPSEL31, and supplying the generated spare selection signals SPSEL1 to SPSEL31 to multiplexers MX0 to MX31, respectively.
Spare determination circuit 500 stores addresses each for specifying a global data line pair to be replaced on a row block basis, takes in a row block specifying address BLADD supplied when a row active command instructing row selection is applied. When a column access command R/W for instructing reading/writing of data is supplied, spare determination circuit 500 generates spare address signals SPADD1 to SPADD31 in accordance with row block specifying address BLADD. In the configuration of spare determining circuit 500, a unit memory array corresponding to a defective column or defective global data line pair is replaced by a unit memory array including a memory cell for repairing the defect, that is, a unit memory array in the spare column block.
When test mode spare control signal TMSPCC is at the H level, a mode of testing a spare memory cell is designated. In the following description, xe2x80x9cspare memory cellxe2x80x9d indicates a memory cell in the spare column block. When a spare memory cell connected to the spare word line is used in a column block other than the spare column block, the memory cell will be referred to as a normal memory cell.
In this state of spare test mode, spare selection signal SPSEL0 from OR circuit 502 is forcedly set to the H level in accordance with test mode spare control signal TMSPCC, and multiplexer MX0 selects an output signal of spare preamplifier SPK. At this time, complementary test mode spare control signal ZTMSPCC is at the L level, all spare selection signals SPSEL1 to SPSEL31 are at the L level, and multiplexers MX1 to MX31 select output signals of corresponding preamplifiers PK1 to PK31.
On the other hand, when test mode spare control signal TMSPCC is at the L level, complementary test mode spare control signal ZTMSPCC is at the H level, and spare selection signals SPSEL0 to SPSEL31 are generated according to spare address signals SPADD0 to SPADD31. When a defective bit exists, in any of multiplexers MX0 to MX31, the corresponding global data line pair is replaced by the spare global data line pair. When no defective bit exits, all spare addresses SPADD0 to SPADD31 are at the L level, and multiplexers MX0 to MX31 select output signals of preamplifiers PK0 to PK31.
FIG. 23 is a diagram schematically showing an example of the configuration of a write data path for writing data in the data path illustrated in FIG. 18. FIG. 23 also shows the configuration for one IO unit block. In FIG. 23, the write data path includes: latch circuits WLFKO to WLFK31 for latching externally applied write data bits Din0 to Din31 synchronously with clock signal CLK; a multiplexer MUX for selecting one of output signals of latch circuits WLFK0 to WLFK31 in accordance with spare address signals SPADD0 to SPADD31; latch circuits WLK0 to WLK31 for taking in and latching output signals of latch circuits WLFK0 to WLFK31 synchronously with clock signal CLK; a spare latch circuit SWLK for latching an output signal of multiplexer MUX; write drivers WDK0 to WDK31 provided in correspondence with latch circuits WLK0 to WLK31, respectively, for driving global data line pairs GIO0 to GIO31 in accordance with output signals of latch circuits WLK0 to WLK31 to generate internal write data when activated; and a spare write driver SWDK for driving spare global data line pair SGIO0 in accordance with an output signal of spare latch circuit SWLK when activated.
Latch circuits WLFK0 to WLFK31 enter a through state when clock signal CLK goes low, and enter a latch state when clock signal CLK goes high. Latch circuits WLK0 to WLK31 and SWLK enter a through state when clock signal CLK goes high, and enter a latch state when clock signal CLK goes low.
Multiplexer MUX further receives test mode spare control signal TMSPCC and selects and supplies an output signal of latch circuit WLFK0 to latch circuit SWLK in writing data to a spare memory cell,. Spare write driver SWDK is activated when a spare is hit (when a defective bit is accessed), and drives a spare global data line pair SGIO0 in accordance with an output signal of spare latch circuit SWLK.
FIG. 24 is a diagram showing an example of the configuration of multiplexer MUX illustrated in FIG. 23. In FIG. 24, multiplexer MUX includes: an OR circuit 506 for receiving test mode spare control signal ATMSPCC and spare address SPADD0; a selection circuit SX0 for passing internal data Data0 from a corresponding latch circuit (WLFK0) when an output signal of OR circuit 506 is at the H level; and selection circuits SX1 to SX31 provided in correspondence with latch circuits WLFK1 to WLFK31, respectively, and made conductive when corresponding spare address signals SPADD1 to SPADD31 are at the H level to pass internal data bits Data1 to Data31 from the corresponding latch circuits.
Selection circuits SX0 to SX31 have the same configuration and each include an inverter IV for receiving an output signal of OR circuit 506 or a transfer control signal being a spare address, and a transmission gate TM selectively made conductive according to the transfer control signal and an output signal of inverter IV to pass a corresponding internal data bit Data. An output signal of OR circuit 506 is supplied as a transfer control signal to selection circuit SX0, and spare address signals SPADD1 to SPADD31 are supplied as transfer control signals to selection circuits SX1 to SX31, respectively.
In the configuration of the multiplexer shown in FIG. 24, when test mode spare control signal TMSPCC is at the L level, OR circuit 506 operates as a buffer circuit. Therefore, according to spare address signals SPADD0 to SPADD31, internal data bits Data0 to Data31 from latch circuits WLFK0 to WLFK31 shown in FIG. 23 are selectively passed, and an output signal Out is generated and supplied to spare latch circuit SWLK (refer to FIG. 23). When no defective bit exits, all spare address signals SPADD0 to SPADD31 are at the L level, and all selection circuits SX0 to SX31 enter an output high impedance state, so that internal write data is not transmitted to spare global data line pair SGIO. When a defective bit exits, a corresponding spare address SPADDi goes high, a corresponding selection circuit SXi is made conductive, internal data bit Datai from a corresponding latch circuit WLFKi is selected, and the output signal Out is generated and supplied to spare latch circuit SWLK.
When test mode spare control signal TMSPCC is at the H level, irrespective of a logic level of spare address signal SPADD0, an output signal of OR circuit 506 goes high, an internal data bit Data0 from latch circuit WLFK0 shown in FIG. 23 is selected, and output signal Out is generated and supplied to spare latch circuit SWLK. When test mode spare control signal TMSPCC is at the H level, data can be written into a spare memory cell in accordance with write data bit Din0 from an outside of the device. By using test mode spare control signal TMSPCC, whether normal memory cell and spare memory cell are normal or not can be determined with respect to all bits, and a defective normal memory cell can be repaired by using a normal spare memory cell. In this description, the normal memory cell indicates a memory cell coupled to global data line pair GIO, and the spare memory cell indicates a memory cell coupled to the spare global data line pair. In the following description as well, similar definition of memory cells will be used.
In a semiconductor memory device having a redundant bit, in order to replace a defective normal memory cell by a spare memory cell, a test as described below is performed. First, test mode spare control signal TMSPCC is set to the L level. Since the defect address designating a defective normal memory cell is not programmed yet, all spare address signals SPADD0 to SADD0-31 are at the L level. In this state, a test is performed on all bits of the normal memory cells. Subsequently, test mode spare control signal TMSPCC is set to the H level and a test is performed on all bits of the spare memory cells. Specifically, by selection circuit SX0 and multiplexer MX0, the spare global data line pair is selected in place of global data line pair GIO0 to make the spare global data line pair to be accessed from the outside of the device, thereby writing and reading data to and from the spare memory cell.
In the case where it is found, from the test performed on all the memory cells of normal and spare memory cells, that a defective normal memory cell exists, when the spare memory cell for replacing the defective memory cell is not defective, the defective normal memory cell is replaced by the spare memory cell (that is, the defect address is programmed in the spare determining circuit). In the replacement by the spare memory cell, in the above-described configuration, redundancy replacement is performed on a global data line pair GIO basis. Redundancy replacement for repairing a defect may be performed on a column selection line unit. As shown in FIG. 19, spare word line SWL is used, and defect repairing is executed on a word line by word line basis. In the redundancy replacement, therefore, a predetermined number of normal memory cells related to the defective normal memory cell are simultaneously replaced with the spare memory cells for repairing defect.
In the case of the configuration of performing spare replacement on a global data line pair unit, based on defect address information programmed by blowing a fuse element or the like in the spare determining circuit shown in FIG. 22, whether redundancy replacement is performed or not is determined. When an address of a memory cell to be replaced is input, write data bits input to the normal global data line pair to be replaced are transmitted to the spare global data line pair (in data writing mode). In data reading mode, the data bits of the normal global data line pair to be replaced are replaced with read data bits output from the spare global data line pair, and the defective normal memory cell and normal memory cells related to the defective normal memory cell are replaced by the spare memory cells. Equivalently, the global data line pair is replaced by the spare global data line pair.
In order to perform the repair by redundancy replacement of a defective normal memory cell, as described above, all the normal and spare memory cells have to be tested. For this purpose, test mode spare control signal TMSPCC is used. In the memory array, however, although the spare and normal memory cells are simultaneously selected in column selection, after performing the test on the normal memory cells, a test is performed on only the spare memory cells. Consequently, test mode spare control signal TMSPCC has to be switched. For the switch of the test mode, a test mode sequence requiring a predetermined time is necessary.
Specifically, for example, in order to switch the test mode for the normal memory cells to that for the spare memory cells, first, whether the test on all bits of the normal memory cells has been completed or not is determined, and after that, the test on the normal memory cells is completed. After completion of the test on the normal memory cells, a test mode for the spare memory cells is newly set, row and column addresses of the spare memory cell are generated, and a test is performed on the spare memory cells. Therefore, a certain time is required to switch the test mode, and a problem that the long test time for detecting a defective bit is necessary occurs.
Since the different tests for the normal and spare memory cells are performed in different modes, there is a problem that the test time is long. Particularly, in the case of using the unit memory array having the same configuration as that having the normal memory cells is used as a spare memory array, the number of bits of the spare memory cells increases, so that the test time on the spare memory cells increases.
An object of the invention is to provide a semiconductor memory device capable of efficiently performing a test on a memory cell.
Another object of the invention is to provide a semiconductor memory device having shortened test time for repairing an defective bit.
Further object of the invention is to provide a logic merged memory in which a logic and a memory are formed on the same chip, capable of efficiently performing a test for repairing an defective bit in a short time.
Further another object of the invention is to provide a semiconductor memory device of a type of repairing an defective bit by IO replacement, capable of performing a test for repairing an defective bit in a short time.
A semiconductor memory device according to the invention includes a normal array having normal memory cells arranged in a matrix of rows and columns, and a spare array having spare memory cells arranged in a matrix of rows and columns, for repairing a defective cell in the normal memory cells by replacement. The normal array is divided into column blocks in unit of a predetermined number of columns.
The semiconductor memory device according to the invention further includes: a plurality of normal internal data lines disposed in correspondence with the column blocks and each coupled to a selected column of a corresponding column block; a spare internal data line disposed in correspondence with the spare array and to be coupled to a selected column of the spare array; a plurality of normal data terminals for receiving external data, disposed in correspondence with the plurality of normal internal data lines; a spare data terminal for receiving external data, disposed in correspondence with the spare internal data line; and a test control circuit for electrically coupling the plurality of normal data terminals and the plurality of normal internal data lines and for electrically coupling the spare internal data line and the spare data terminal in response to a test mode instruction signal.
According to another aspect of the invention, in a semiconductor memory device for repairing a defect in a unit of an IO line disposed commonly to memory cells in a plurality of columns and coupled to a selected column, a data terminal dedicated to spare data is provided separately from a normal data terminal, and a spare IO line and a spare data terminal are coupled to each other in a test mode, so that a normal memory cell and a spare memory cell can be accessed in parallel from an outside of the device.
By providing the spare data terminal for inputting and outputting spare data, the normal and spare memory cells can be accessed in parallel, and a test can be performed simultaneously on the normal and spare memory cells. Consequently, it is unnecessary to perform tests by separate sequences for the spare memory cell and for the normal memory cells. The time for switching the sequences also becomes unnecessary. Since the spare and normal memory cells are simultaneously tested in one test sequence, the time for the test on memory cells to repair a defective bit can be greatly reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Mitsubishi Electric Engineering Company Limited


A method of detecting a flow blockage in a pipe includes: arranging a fluid flow along the pipe, the pipe in fluid communication with a pressure sensor; configuring the pressure sensor to measure a pressure within the pipe; recording plurality of measurements of pressure within the pipe; sampling ‘n’ successive values of pressure within the pipe; performing an analytical test on the ‘n’ successive values, the analytical test producing an output value, the output value representative of a variation in the individual ones of the ‘n’ successive values; comparing the output value to a pre-defined threshold value, the threshold value indicative of a lack of variation in the individual ones of the ‘n’ successive values; and if the output value is less than the threshold value, generating an alert to provide a user with an indication of the presence of flow blockage in the pipe.

With reference to FIG. 1, a conventional high bypass ratio turbofan engine generally indicated at 10 has a principal and rotational axis 11. This turbofan engine comprises a three-shaft gas turbine engine having high, intermediate and low pressure spools. Such engines are typically provided with a single rotating stage in both the high and intermediate turbines. The low pressure turbine however, usually comprises many stages.
The engine 10 comprises, in axial flow series, an air intake 12, a propulsive fan 13, an intermediate pressure compressor 14, a high pressure compressor 15, combustion equipment 16, a high-pressure turbine 17, an intermediate pressure turbine 18, a low-pressure turbine 19 and a core engine exhaust nozzle 20. A nacelle 21 generally surrounds the engine 10 and defines the intake 12, a bypass duct 22 and a bypass exhaust nozzle 23. The fan 13 is circumferentially surrounded by a fan casing 30, which is supported by an annular array of outlet guide vanes 27.
The gas turbine engine 10 works in a conventional manner so that air entering the intake 11 is accelerated by the fan 13 to produce two air flows: a first air flow into the intermediate pressure compressor 14 and a second air flow which passes through a bypass duct 22 to provide propulsive thrust. The intermediate pressure compressor 14 compresses the air flow directed into it before delivering that air to the high pressure compressor 15 where further compression takes place. The compressed air exhausted from the high pressure compressor 15 is directed into the combustion equipment 16 where it is mixed with fuel and the mixture combusted. The resultant hot combustion products then expand through, and thereby drive the high, intermediate and low pressure turbines 17, 18, 19 before being exhausted through the nozzle 20 to provide additional propulsive thrust. The high, intermediate and low pressure turbines 17, 18, 19 respectively drive the high and intermediate pressure compressors 15, 14 and the fan 13 by interconnecting shafts 24, 25, 26 respectively thereby making up high, intermediate and low pressure spools.
Control of the gas turbine engine requires analysis of various data consisting of measured engine parameters converted into electrical signals by sensors sited on the engine. These parameters include shaft speeds, temperatures, pressures and fuel flow rate.
The measured pressures include the inlet pressure at the fan face (P20), the pressure at the exit of the intermediate compressor (P25), the high pressure compressor delivery pressure (P30), the hot nozzle pressure (P50), and the by-pass pressure (P160). The location of each of these pressure variables within a typical three-shaft high bypass ratio turbofan engine is shown in FIG. 1.
Of these pressures, P30 being the pressure at the exit from the high pressure compressor is the highest pressure in the engine. Due to the hostile environment at the exit from the high pressure compressor, the associated pressure sensor is remotely located with a pipe connecting it to the exit region.
The connecting pipe is known to fill with moist air and in icing conditions this can freeze such that the pipe is blocked. This has the effect of 'freezing' the static pressure measurement because all variation in the measured pressure ceases until the pipe unfreezes.
A known technique for detecting the freezing of the P30 signal pipe relies on comparing a P30 value modelled from other engine parameters (such as, for example, fuel flow rate or high pressure compressor delivery temperature) with the actual measured P30 value. When a significant difference appears between the modelled and measured values then a freezing of the P30 signal pipe may be indicated.
On detection of the freezing of the P30 signal pipe, the control strategies of the engine change from using the measured P30 value to using the modelled P30 value.
In such circumstances, if there is little or no change in engine conditions (for example during cruise of the aircraft) then a P30 pipe freeze event may remain undetected until the pilot requires a change in engine thrust. The frozen P30 signal pipe may then cause the engine to produce an incorrect thrust level (i.e. higher or lower than requested) which would represent a safety risk during this critical event.
In effect, it is a dormant failure waiting for a demanded change in engine conditions to make it evident.
A disadvantage of the prior art system is that while it would detect the frozen P30 signal pipe and activate a different control regime for the engine using the modelled P30, there remains the possibility that a significantly incorrect thrust level may exist for a short period of time but at a potentially critical one.
A further disadvantage of the prior art system is that an error message, highlighting the frozen P30 signal pipe, is provided to the pilot. This adds to the pilot's workload during a critical time and may distract the pilot from potentially more important issues.

Method and system for detecting a flow blockage in a pipe


In one embodiment, the present invention relates to a method of treating metal foil including sequentially contacting the metal foil with a first solution containing a metal foil oxidizer and less than about 5 g/l of a hydroxide compound, contacting the metal foil with a chromium containing electrolytic bath and electrolyzing the bath, wherein the bath contains about 0.1 to about 5 g/l of a chromium compound, and contacting the metal foil with a second solution containing from about 0.1 to about 10% v/v of a silane compound, with the proviso that the metal foil is not contacted with a reducing agent after contact with the first solution.

Metal foil, for example copper foil, is often laminated to a dielectric substrate. Resultant laminates are subjected to numerous processing techniques as well as inevitable wear and tear. In this connection, it is desirable to provide a laminate having high peel strength. High peel strength enables a laminate to maintain its structural integrity during processing (exposure to chemicals and various etchants, such as hydrochloric acid) and over the course of normal wear and tear (heat degradation, physical agitation, and so forth).
Metal foils are typically treated to increase surface roughness and thereby increase the peel strength of resultant laminates. However, metal foils having increasingly high levels of surface roughness are subject to "treatment transfer", which is the undesirable migration of metal material from the metal foil to the dielectric substrate. Treatment transfer lowers the peel strength as well as degrading the insulating properties of the dielectric substrate. Treatment transfer also leads to unsightly yellow staining after the metal foil is etched. Accordingly, it is desirable to provide metal foil which not only exhibits high peel strength when incorporated into a laminate, but also does not affect the insulating properties of the dielectric substrate.
When metal foils are treated to increase surface roughness, an electrolytic process is typically utilized. For example, a nodular or dendritic layer of copper or zinc is electrodeposited on metal foil to increase the surface roughness. This process is not only time consuming, but also expensive because of the enormous amount of electricity needed to applying a nodular layer of copper or zinc. Accordingly, it is desirable to increase the efficiency and cost-effectiveness of treating metal foils.


A suspension system for a motor of a combustion-powered hand tool includes a motor retaining ring defining a space for accepting the motor, an outer ring radially spaced from the retaining ring and configured for attachment to a cylinder head of a combustion chamber, and at least one resilient suspension element configured for dampening vibrations between a motor support and a tool frame, and having a plurality of resilient beams connecting the retaining ring and the outer ring.

The present invention relates generally to improvements in portable combustion-powered fastener driving tools, and specifically to improvements relating to the suspension of a motor for a combustion chamber fan for decreasing the operationally induced acceleration forces experienced by the motor, and for decreasing wear and tear on the motor.
Portable combustion-powered tools for use in driving fasteners into workpieces are described in commonly assigned patents to Nikolich U.S. Pat. Re. No. 32,452, U.S. Pat. Nos. 4,522,162; 4,483,474; 4,403,722; 5,197,646; 5,263,439 and U.S. Pat. No. 6,520,397, all of which are incorporated herein by reference. Similar combustion-powered nail and staple driving tools are available commercially from ITW-Paslode of Vernon Hills, Ill.
Such tools incorporate a generally pistol-shaped tool housing enclosing a small internal combustion engine that is powered by a fuel cell. A battery-powered electronic power distribution unit produces a spark for ignition, and a fan located in the combustion chamber provides for an efficient combustion within the chamber and facilitates scavenging, including the exhaust of combustion by-products. The engine includes a reciprocating piston with an elongated, rigid driver blade disposed within a cylindrical body.
A valve sleeve is axially reciprocable about the cylinder and, through a linkage, moves to close the combustion chamber when a workpiece contact element at the end of the linkage is pressed against a workpiece. This pressing action also triggers a fuel-metering valve to introduce a specified volume of fuel into the closed combustion chamber.
Upon the pulling of a trigger switch, which causes the ignition of a charge of gas in the combustion chamber of the engine, the piston and driver blade are shot downward to impact a positioned fastener and drive it into the workpiece. The piston then returns to its original, "ready" position, through differential gas pressures within the cylinder. Fasteners are fed into the nosepiece through a magazine, where they are held in a properly positioned orientation for receiving the impact of the driver blade.
Upon ignition of the combustible fuel/air mixture, the combustion in the chamber causes the acceleration of the piston/driver blade assembly and the penetration of the fastener into the workpiece if the fastener is present. This combined downward movement causes a reactive force or recoil of the tool body. Therefore, the fan motor, which is suspended in the tool body, is subjected to an acceleration opposite the power stroke of the piston/driver blade and fastener.
Almost immediately thereafter, a bumper at the opposite end of the cylinder stops the momentum of the piston/driver blade assembly, and the tool body is accelerated toward the workpiece. The motor and shaft are thus subjected to an acceleration force which is opposite the direction of the first acceleration. After experiencing these reciprocal accelerations, the motor oscillates with respect to the tool.
Conventional combustion powered tools require specially designed motors to withstand these reciprocal accelerations of the shaft and motor, and the resulting motor oscillations. The motors are equipped with custom modifications which result in expensive motors that increase the production cost of the tools.
Although prior suspension systems exist that are designed to stabilize the motors and prevent them from experiencing excessive acceleration forces, they are prior art systems with a larger mass or a higher level of rigidity, increasing the final manufacturing costs of the combustion-powered tools to which they pertain.
Therefore, there is a need for a motor suspension system for a combustion-powered tool with an increased resiliency that reduces operationally induced acceleration forces experienced by the tool during operation. There is also a need for a motor suspension system that accommodates the use of a more standard, cost-effective motor.

Beam system membrane suspension for a motor mount


The present invention allows a modem to operate in both the voice band, from 300 to 3400 Hz, and also in the ADSL band, which extends above 3400 Hz. Unlike conventional ADSL modems, the present invention avoids the computationally-intensive operations required to extract all the available band of a telephone subscriber loop. Consequently, the present invention can be implemented with low-cost modifications to existing voice band modems. The present invention thereby offers higher data transfer rates at a fraction of the cost of more complicated ADSL modems. The present invention also provides bypassing functions, which allow communications through a modem located at the telephone central office side of a subscriber loop to be switched through a packet-switched network, which is capable of accommodating high data transfer rates, instead of a central office switching system, which generally imposes unnecessary limitations on data transfer rates.

1. Field of the Invention
The present invention relates to systems for connecting remote computer systems to computer networks through telephone lines, and more particularly to a modem which operates at a voice band frequency below 4000 Hz as well as a higher broad band frequency above 4000 Hz.
2. Related Art
With the advent of computer networking and personal computers, public switched telephone networks (PSTNs) are increasingly used to connect computer systems to other computer systems, and to connect computer systems to computer networks, such as the Internet. As computer systems begin to support data-intensive applications, which transfer sounds, images and video between computer systems, the connections between computer systems are subject to increasing demands for larger amounts of bandwidth. Although the subscriber loops, which connect telephones to central office switching systems, are capable of accommodating transfers of data between computer systems, the available bandwidth of data transfers through PSTNs is severely constrained by inherent limitations of the switching equipment located in central office switching systems. Most of this switching equipment digitizes analog signals on subscriber loops by sampling the analog signals at a frequency of 8 kHz. Because of the Nyquist limit, this sampling rate imposes an artificial maximum frequency of 4 kHz on signals that can be passed from a subscriber loop through a PSTN.
Fortunately, the majority of capital investment in the telephone system is in the subscriber loops, which are pairs of wires running to homes and business from telephone central office switching systems. With new asymmetric digital subscriber loop (ADSL) modems, a typical subscriber loop can send 8,000,000 bits per second. The main difference between ADSL modems and older V.34 type modems is that in ADSL a distant modem is located in a telephone central office, and it receives a signal across a subscriber loop before the bandwidth is artificially reduced by equipment in the central office switching system. (In the following disclosure, the term "ADSL" is used as a generic description of all modems operating over direct telephone wire at frequencies above 4,000 Hz. The actual method used to modulate the line at the high band rate may or may not actually be asymmetric.)
ADSL technology was largely started by Dr. Joseph W. Lechleider at Bell Communications Research (Bellcore) during the mid-1980's, and has culminated in American National Standards Institute (ANSI) standard T1.413. The same standard has been adopted by the European Telecommunications Standard Institute (ETSI). The T1.413 standard is based upon discrete multitone (DMT) modulation. There are other related techniques, which are not standardized, such as Carrierless Amplitude modulation/Phase modulation (CAP), and another older method known as Quadrature Amplitude Modulation (QAM). The three above-mentioned methods can be grouped together has efficient line codes. This means that they are capable of approaching the Shannon-Hartley limit for the maximum amount of information which can be sent through a given channel. In addition to these three methods, there are many older modulation techniques such as AMI (Alternate Mark Inversion) and 2B1Q, which operate at levels below the maximum possible rate. All of these codes can be used to send high speed data over ordinary telephone lines.
While the theoretical capabilities for ADSL technology are quite promising, there exist large numbers of barriers to making the required changes to implement ADSL technology on a wide scale. First, the technology required to implement ADSL modems is considerably more expensive than for existing V.34 modems. For example, an ADSL modem at this time costs about $2,000, compared to about $100 for a V.34 modem. ADSL modems can be expected to decline in price to somewhere in the range of $500 to $1,000 within the next year because of volume shipments. However, there will nevertheless exist an approximately 5 to 1 ratio in cost of ADSL over V.34 modems for the foreseeable future. Second, there is currently no infrastructure to support ADSL modems in telephone central offices. A large number of ADSL modems, all requiring 8 Mbits per second of data, will quickly overwhelm any conceivable data switch of today's technology. Because of this bandwidth bottleneck, it is unlikely that the benefits of ADSL technology will actually be realized on a broad scale any time soon. Unfortunately, the tremendous additional cost for ADSL modems must be paid even though much of the additional data rate will not be immediately useable.
Another problem with ADSL is that there is no known content which requires such bandwidth. Video on demand (VOD) could theoretically utilize the bandwidth available through ADSL technology however, VOD requires a complex and expensive system of video servers to distribute the material. This infrastructure presently does not exist. Internet access is a rapidly evolving content area which could theoretically utilize the additional bandwidth of ADSL technology, but at present, Internet applications are designed for transmission facilities comprising 33 Kbit links and T1 trunks.
What is needed is a modem which is capable of providing the increased bandwidth from ADSL technology at a fraction of the cost.


An aromatic dihydroxy compound conforming to formula 1

The present invention provides polycarbonates and copolycarbonates of reduced water uptake and improved flowability, processes for their preparation and their use for the production of particular products and the products obtainable therefrom. The invention furthermore provides new bisphenols and processes for their preparation and their use.
Aromatic polycarbonates belong to the group of industrial thermoplastics. They are distinguished by the combination of the technologically important properties of transparency, heat resistance and toughness.
To obtain high molecular weight polycarbonates by the phase boundary process, the alkali metal salts of bisphenols are reacted with phosgene in the two-phase mixture. The molecular weight may be controlled by the amount of monophenols, such as e.g. phenol or tert-butylphenol. Practically exclusively linear polymers are formed in these reactions. This may be demonstrated by end group analysis. Branched polycarbonates are also obtained in this reaction by the controlled use of so-called branching agents, as a rule polyhydroxylated compounds.
For the preparation of polycarbonates by the phase boundary process, reference may be made by way of example to H. Schnell, Chemistry and Physics of Polycarbonates, Polymer Reviews, vol. 9, Interscience Publishers, New York 1964 p. 33 et seq. and to Polymer Reviews, vol. 10, "Condensation Polymers by Interfacial and Solution Methods", Paul W. Morgan, Interscience Publishers, New York 1965, chap. VIII, p. 325.
For the preparation of polycarbonates by the melt transesterification process, the bisphenols are reacted with diaryl carbonates, usually diphenyl carbonate, in the presence of catalysts, such as alkali metal salts or ammonium or phosphonium compounds, in the melt.
The melt transesterification process is described, for example, in the Encyclopedia of Polymer Science, vol. 10 (1969), Chemistry and Physics of Polycarbonates, Polymer Reviews, H. Schnell, vol. 9, John Wiley and Sons, Inc. (1964) and DE-C 10 31 512.
However, the polycarbonates and copolycarbonates already described in the prior art are unsatisfactory due to their water uptake and the limited dimensional stability thereby caused, or have the disadvantage that when used as data carrier materials they may be of limited or non-optimum suitability at reading wavelengths in the blue or blue-green range.

Aromatic dihydroxy compound useful for the preparation of (CO)polycarbonates

Abstract: is disclosed. Also disclosed are (co)polycarbonates derived from the compound. The novel (co)polycarbonates are characterized by their reduced water uptake and improved flowability.


A method of interface registration for a network device to join in a cluster system, comprises: when the network device joins in the cluster system, the network device's local interconnection board sends its board number to the network device's local main control board, the network device's local non-interconnection board receives the board number sent by the local main control board, wherein the local interconnection board is a board on which interfaces for interconnecting the network device to network devices in the cluster system are located; after the cluster interface registration of the local non-interconnection board and local interconnection board on the cluster main control board, the local non-interconnection board and the local interconnection board receive and store a mapping relationship between local interface information of the network device and global interface information of the network device sent by the cluster main control board respectively.

A clustered network interconnects multiple physically independent network devices to form a logically integrated system. All independent network devices in a clustered network are invisible to the outside and are managed in a centralized manner. These network devices are operated as a single device, which greatly simplifies device operation and maintenance.
The existing clustered network interconnects multiple physically independent network devices in a star topology through an additional central switching frame. A main control board of the cluster is also located on a certain board of the central switching frame. Intra-frame interconnection and inter-frame interconnection are realized in the same manner, and the interface registration for a network device to join in a cluster system and the management flow after joining in the cluster are the same as those for non-clustered devices. Such clustered network formed through interconnecting special hardware is efficient in communication, has large throughput for both intra-frame forwarding and inter-frame forwarding, low latency, and is transparent to upper level software system.
However, the above clustered network employs special hardware to interconnect network devices. After having joined in a cluster system, such network devices can only operate in a cluster mode, and cannot select operation modes, e.g., select to operate in a stand-alone mode or a cluster mode. Therefore, network devices are unable to on-line switch between stand-alone operation and joining in a cluster.

Method and device of interface registration for a network device to join in a cluster system


An earthquake sensor in which a weight falls from a support surface and activates a switch in the event of an earthquake. The support surface is preferably a bell with its opened end downward and the weight resting on a concave, recessed region at the closed end of the bell. The bell is preferably supported by a shaft along the axis of the bell, the tip of which the bell pivots about like a pendulum. A conductive cylinder encircles the bell near its bottom. When the earth moves, the weight falls down the inclined surface of the bell, wedging between the bell and the cylinder, forcing the bell to pivot over to electrically connect the bell to the cylinder. In an alternative embodiment, the weight electrically connects the bell and the cylinder, and the bell does not pivot.

When an earthquake occurs, the more time people have to respond, the fewer will be the number of people who are injured. Earthquake alarms serve the purpose of sensing motion of the earth's surface and warning those nearby of that motion. Many elaborate and sophisticated seismic measuring devices exist, but are unfortunately not affordable for most people.
There has been a need for an inexpensive earthquake alarm that is effective. Many of the proposed solutions to this need are machines which must remain ready over long periods of time without sounding but need to be reliably functional when an earthquake occurs. The alarms are needed by a wide variety of people who all must be able to install, operate and maintain the alarm. Therefore, the alarm should require the least amount of attention and when maintenance is necessary, it should be simple.
Alarms which have been described in U.S. Pat. Nos. 4,689,997, 4,364,033, 3,990,039 and 1,625,625, have a pendulum body which is moved by the motion of the earth's surface. The pendulum's motion results in producing a signal warning people of the earthquake. These types of alarms suffer from being too insensitive to the earth's motion. Alarms which are sensitive enough are too difficult to set up and maintain due to their sensitivity. Another alarm, which is disclosed in U.S. Pat. No. 4,086,807, has a ball that is magnetically held in place which is moved out of place by the earthquake, sounding an alarm.
There is a need for a simply functioning earthquake alarm that is sensitive to earthquakes and yet is easy to install, operate and maintain. The alarm should also remain Operable after being dormant for long periods of time, and should require a minimum of attention and maintenance.


Severely contaminated white mineral oils which fail the RCS specification are treated using an acid-treated bentonite clay, such as TONSIL CO 630G. The white oil products produced in the treatment may be a USP grade white oil.

The present invention relates to a process for preparing a USP grade white oil by filtering through a specified clay sorbent.
A white oil produced in the present process meets the requirements of regulation 21 CFR 172.878, 21 CFR 178.3620(a), 21 CFR 178.3620(b) or 21 CFR 178.3620(c) for USP and technical grade white oils. White mineral oil is prepared from a distillate of petroleum crude oil which has a viscosity in the lubricating oil range and a normal boiling point above 350.degree. F. Preparation of the white oil generally includes one or more upgrading steps for purifying the oil and for removing the contaminants which degrade the properties of the oil as a white oil. Common upgrading steps include refining processing such as hydrotreating, hydrogenation, filtering, solvent refining and/or dewaxing. A final step for removing the last traces of contaminants may include one or more hydrogenation reaction steps, an acid treatment step and/or a final filtering step. The traditional method for making white mineral oil has been treatment of the distillate with acid. Traditionally, the distillate was treated with acid, and purified by clay treatment to remove by-products that have been created by the acid treatment. U.S. Pat. No. 4,024,026 and U.S. Pat. No. 4,053,367 disclose removing impurities, such as olefinic materials, from hydrocarbons by clay treating. Common contact materials for clay treating are acidic aluminosilicates, either naturally occurring materials, such as bauxite or mordenite clay, or a synthetic material and may comprise alumina, silica, magnesia or zirconia or some other compound which exhibits similar properties. Typical clays which are taught as being suitable include Filtrol 24, Filtrol 25, Filtrol 62, Attapulgus clay and TONSIL clay.
White mineral oils have also been prepared using hydrogenation processes. U.S. Pat. No. 3,459,656 to Rausch discloses a process for preparing technical grade and food grade white mineral oils by catalytic hydrogenation in two steps. The catalyst of the first hydrogenation operation is taught as being any of the sulfur resistant non-precious metal hydrogenation catalysts. The catalyst of the second hydrogenation is a platinum group metal-promoted catalyst. U.S. Pat. No. 5,294,327 discloses three stages of hydroprocessing without any solvent extraction or acid treatment prior steps to produce a desired food grade quality white mineral oil.
While a hydrogenation process may produce acceptable white oil during normal operation, it may produce "off-spec" product as a result of, for example, a process upset or a feed change. Such off-spec product may then require a second treatment in order to pass all of the requirements of a USP grade white oil, at additional expense and process complexity. U.S. Pat. No. 5,098,556 partly addresses the issue of off-spec oil by disclosing a process for removing the RCS present in off-spec white oil produced by catalytic hydrogenation by contacting the off-spec oil with a bleaching clay, such as a smectite clay, particularly an acid-treated montmorillonite clay, such as bentonite or attapulgite. According to the '556 patent, a white oil having an RCS value of approximately 2.5-3.5 is considered off specification, but treatable by clay purification. A white oil with an RCS value of 4 or over generally was found to be untreatable. Clay treatment of the white oil reduced the RCS value to under 2.5. The '556 patent does not clearly explain the number value attributed to the RCS test.
The determination of readily carbonizable substances (RCS) in a white mineral oil is described in ASTM D565-88 (Reapproved 1993). The test includes extracting a white oil sample with H.sub.2 SO.sub.4, and evaluating the color of the oil layer and acid layer following extraction. A white oil sample is considered as having passed the RCS test when the oil layer shows no change in color and when the acid extract layer is no darker than the reference standard colorimetric solution. However, while not required by the test, the acid extract layer may be further analyzed for color, using, for example, the ASTM Color Scale (ASTM D1500-96) or the Gardner Color Scale (ASTM D1544-80: reapproved 1989). As used herein, the term "RCS value" refers to the color of the acid extract from the acid extract layer. Unless otherwise indicated, the color is referenced to the ASTM color scale, and is indicated by a number per the ASTM color scale.
The '556 process is limited to white oils having an RCS value of 2.5-3.5. However, conditions beyond the control of the refiner may result in production of a more severely contaminated white oil. It is desirable to have an inexpensive and efficient process for upgrading such more severely contaminated off-spec oils without having to resort to additional hydrogenation or to other more costly and difficult methods.

Clay treatment process for white mineral oil


To achieve a first object of the present invention, a starting time limit vehicle speed which preferentially permits a torque distribution to front and rear wheels at the time of starting of a vehicle is switched in accordance with a degree of a diameter difference. To achieve a second object of the present invention, when the vehicle makes a normal running with different-diameter tires mounted thereon, a front/rear wheel distribution torque caused by a front/rear wheel rotation speed difference owing to the different-diameter tires is limited by switching a torque gain depending on a degree of a diameter difference.

1. Field of the Invention
The present invention relates to a front/rear wheel torque distribution control apparatus applied to a four-wheel drive vehicle, which variably controls a driving torque distribution to a front wheel and a rear wheel by controlling a tightening torque of an electronic control clutch.
2. Description of the Related Art
A technology has been heretofore known, in which in the case where a four-wheel drive vehicle having an electronic control clutch for controlling a torque distribution transmitted to front and rear wheels is mounted with a tire having a diameter different from that of a tire originally mounted thereon (hereinafter the tire having the diameter different from that of the tire originally mounted is referred to as a different-diameter tire, and the tire originally mounted is a normal-diameter tire), after the different-diameter tires are detected, a front/rear wheel distributed torque is not controlled (an alarm alone is raised) or the front/rear distributed torque is made close to a two-wheel drive side (see Japanese Patent Application Laid-Open No. 4(1992)-103433).
However, the conventional front/rear wheel torque distribution control apparatus of the four-wheel drive vehicle has the following problems.
When the distribution torque is large despite of an increase of a vehicle speed (a clutch tightening state), a difference of a rotation speed between the front wheel and the rear wheel, which is produced by the different-diameter tires, cannot be absorbed by a relative rotation of a plate of the electronic control clutch. A drive train may be adversely affected as long as a driver does not cope with such a situation with replacement of the tire with new one and the like.
When the torque distribution is made to be a sufficiently small constant value (two-wheel drive side), four-wheel drive performance in which a good starting characteristic is to be obtained in starting a vehicle is deteriorated.
The first object of the present invention is to provide a front/rear wheel torque distribution control apparatus of a four-wheel drive vehicle capable of reducing bad influence of different-diameter tires on a drive train without damaging inherent four-wheel drive performance enhancing a starting property at the time of a start of the vehicle at which large front/rear wheel distribution torque is required.
The second object of the present invention is to provide a front/rear wheel torque distribution control apparatus of a four-wheel vehicle capable of securing the lowest four-wheel drive performance in a normal running state of a vehicle by allowing a front/rear wheel distribution torque to approach to a torque at the time normal tires are mounted thereon.
To achieve the first object of the present invention, a first aspect of the present invention provides a front/rear wheel torque distribution control apparatus of a four-wheel drive vehicle having an electronic control clutch for controlling a torque distribution to front and rear wheels, in which one of the front and rear wheels is a main drive wheel and the other is a subsidiary drive wheel,
the front/rear wheel torque distribution control apparatus comprising:
a tire diameter difference degree detector for detecting a degree of a diameter difference between a different-diameter tire and a normal-diameter tire (hereinafter referred to as a degree of a diameter difference) when any of the front and rear wheels mounts the different-diameter tires;
a driver request torque calculator for calculating a driver request torque transmitted from the main drive wheel to the subsidiary drive wheel via the electronic control clutch in response to an operation of a driver;
a vehicle speed detector for detecting a vehicle speed;
a starting time limit speed determiner for making a starting time limit speed in which a torque at the time of starting the vehicle is limited by a vehicle speed lower as the degree of the tire diameter difference detected by the tire diameter difference degree detector is larger; and
a starting time torque distribution controller for outputting an instruction to obtain the driver request torque calculated by the driver request torque calculator to the electronic control clutch until the vehicle speed becomes equal to a starting time limit vehicle speed determined by the starting time limit speed determiner when the vehicle mounts the different-diameter tires.
In the first aspect of the present invention, the tire diameter difference degree detector detects the degree of the diameter difference when the vehicle mounts the different-diameter tires on any of the front and rear wheels. In response to the operation of the driver, the driver request torque calculator calculates the driver request torque transmitted via the electronic control clutch. The vehicle speed detector detects the vehicle speed.
When the detected degree of the tire diameter difference is higher than a setting value, the starting time limit speed determiner determines the limit torque so as to be smaller as the degree of the diameter difference is lager.
When the vehicle mounted with the different-diameter tires starts, the starting time torque distribution controller outputs an instruction to obtain the driver request torque calculated by the driver request torque calculator to the electronic control clutch until the detected vehicle speed becomes equal to the starting time limit vehicle speed. The torque distribution transmitted to the front and rear wheels is control to a four-wheel drive side.
Specifically, at the time of starting of the vehicle when the front/rear wheel rotation speed difference occurs due to a large drive slip, a distribution of the drive torque to the four wheels as evenly as possible and acquisition of a starting property suppressing the drive slip are wished. However, when a torque distribution control is performed for the vehicle mounted with the different-diameter tire just in the same manner for the vehicle mounted with the normal-diameter tire and a perfect clutch tightening state is maintained because of a large front/rear wheel distribution torque in spite of an increased vehicle speed, the front/rear wheel rotation speed difference caused by the different-diameter tire cannot be absorbed by the electronic control clutch, and a twist torque occurs in a drive train (drive system). Furthermore, when a clutch tightening force is not sufficiently high, the front/rear wheel rotation speed difference caused by the different-diameter tire can be absorbed by a relative rotation of a clutch plate. However, a high friction heat is generated because of the relative rotation in the state where the clutch tightening force is applied, so that deterioration of the clutch due to heat is promoted. In any case, if a driver does not cope with such a situation by some countermeasures such as replacement of the tire with new one, a drive train including the electronic control clutch is adversely affected.
On the other hand, when the torque distribution to the front and rear wheels is made to be close to a two-wheel drive side in starting of the vehicle mounted with the different-diameter tires, the adverse influence on the drive train is removed. However, a high starting property utilizing a four-wheel drive performance cannot be obtained at the time of starting of the vehicle.
Accordingly, a vehicle speed (starting time limit vehicle speed) which preferentially permits the torque distribution to the front and rear wheels at the time of starting of the vehicle is switched in accordance with the degree of the tire diameter difference.
Thus, under the restricted condition that the driver request torque is output until the vehicle speed becomes equal to the starting time limit vehicle speed, the four-wheel drive performance can be displayed by the driver request torque.
Accordingly, at the time of starting of the vehicle where a large front/rear wheel distribution torque is necessary, it is possible to reduce the adverse influence on the drive train owing to the different-diameter tire without damaging the inherent four-wheel drive performance enhancing the starting property.
To achieve the second object of the present invention, a second aspect of the present invention provides a front/rear wheel torque distribution control apparatus of a four-wheel drive vehicle having an electronic control clutch for controlling a torque distribution to front and rear wheels,
the front/rear wheel torque distribution control apparatus comprising:
a tire diameter difference degree detector for detecting a degree of a diameter difference when any of front and rear wheels mounts different-diameter tires;
a normal running time detector for detecting a normal running time of the vehicle;
a normal running torque gain determiner for determining a normal running torque gain to be a torque gain smaller than a torque gain at the time when normal-diameter tires are mounted as the degree of the diameter difference detected by the tire diameter difference degree detector is larger, when any of the front and rear wheels mounts the different-diameter tires;
a normal running torque calculator for calculating a normal running torque by multiplying a front/rear wheel rotation speed difference by the torque gain determined by the normal running torque gain determiner; and
a normal running time torque distribution controller for outputting an instruction to obtain the normal running torque calculated by the normal running torque calculator to the electronic control clutch, when the vehicle makes normal running with the different-diameter tires mounted on any of the front and rear wheels thereof.
In the second aspect of the present invention, the tire diameter difference degree detector detects the degree of the diameter difference when any of the front and rear wheels mounts the different-diameter tires. The normal running time detector detects the normal running time of the vehicle. The normal running torque gain determiner determines the normal running torque gain to be the torque gain smaller than the torque gain at the time when the normal-diameter tires are mounted as the degree of the diameter difference detected by the tire diameter difference degree detector is larger, when any of the front and rear wheels mounts the different-diameter tires. The normal running torque calculator calculates the normal running torque by multiplying the front/rear wheel rotation speed difference by the torque gain determined by the normal running torque gain determiner.
The normal running time torque distribution controller outputs the instruction to obtain the calculated normal running torque to the electronic control clutch, when the vehicle makes the normal running with the different-diameter tires mounted on any of the front and rear wheels thereof, and the torque distribution transmitted to the front and rear wheels is controlled.
Specifically, when the torque distribution control corresponding to the front/rear wheel rotation speed difference is performed for the vehicle mounted with the different-diameter tire just in the same manner for the vehicle mounted with the normal-diameter tire, the front/rear wheel distribution torque becomes larger in accordance with an amount of the front/rear wheel rotation speed difference caused due to the different-diameter tire.
Accordingly, when the vehicle makes the normal running with the different-diameter tires mounted thereon, the front/rear wheel distribution torque caused by the front/rear wheel rotation speed difference due to the different-diameter tire is suppressed by switching the torque gain in accordance with the degree of the diameter difference.
With such an operation, by switching the torque gain, it is possible to remove or reduce an influence of an increase in the front/rear wheel distribution torque owing to the different-diameter tire, and hence the front/rear wheel distribution torque becomes close to a torque of a vehicle mounted with normal-diameter tires.
Thus, in the normal running of the vehicle mounted with the different-diameter tires, the minimum four-wheel drive performance can be secured by allowing the front/rear wheel distribution torque to be close to a torque at the time the vehicle mounts the normal-diameter tires.

Front/rear wheel torque distribution control apparatus for four wheel drive vehicle


The present invention provides a process for the production of perfluoroalkylsulphonyl fluorides of the formula C.sub.n F.sub.2n+1 SO.sub.2 F with n=6-10 by electrochemical fluorination of alkylsulphonyl halides of the general formula C.sub.n H.sub.2n+1 SO.sub.2 X with n=6-10 and X=F, Cl, Br or I in hydrogen fluoride, which process is characterised in that electrodes are used which consist of nickel with a columnar structure or which are coated with nickel with a columnar structure as shown in FIG. 1.. The invention also provides electrodes for the production of perfluoroalkylsulphonyl fluorides from the corresponding alkylsulphonyl halides by electrochemical fluorination in hydrogen fluoride, which electrodes are characterised in that they consist of nickel with a columnar structure or are coated with nickel with a columnar structure.

1. Field of the Invention
The invention relates to a process for the production of perfluoroalkylsulphonyl fluorides by electrochemical fluorination of the corresponding alkylsulphonyl halides and to electrodes for the performance of the process.
2. Description of the Prior Art
The production of fluorinated compounds by electrochemical fluorination proceeds according to E. Hollitzer and P. Satori, Chem.-Ing.-Tech. 58 (1986), no. 1, 31-38 by anodic oxidation in a solvent containing fluoride. Anode materials used in the process are nickel, carbon and platinum. If hydrogen fluoride is used as the solvent, nickel anodes are preferably used. Perfluorinated compounds are obtained from the process.
If alkylsulphonyl halides of the formula C.sub.n H.sub.2n+1 SO.sub.2 X with n=6-10 and X=F, Cl, Br, I are electrochemically fluorinated in hydrogen fluoride on nickel electrodes, perfluoroalkylsulphonyl fluorides, C.sub.n F.sub.2n+1 SO.sub.2 F, are produced. A disadvantage of this process for the production of perfluoroalkylsulphonyl fluorides is considerable anode corrosion. This corrosion gives rise to problems from nickel corrosion products when operating the electrolysis cells, which corrosion products clog the electrode interstices and block valves and pipework. For this reason, prolonged, continuous electrochemical fluorination is not possible, which greatly diminishes the economic viability of the process.
The object of the invention was, therefore, to provide a process for the production of perfluoroalkylsulphonyl fluorides by electrochemical fluorination in which the stated disadvantages do not arise.
It was surprisingly found that the stated disadvantages do not arise if the anodes consist of nickel with a columnar structure or are coated with nickel with such a structure.

Process for the production of perfluoroalkylsulphonyl fluorides and electrodes for performance of the process


Disclosed herein is a magnetron. The magnetron comprises an anode cylinder, upper and lower magnets provided to upper and lower portions of the anode cylinder, and upper and lower magnetic poles connected to the magnets, respectively. Each of the magnets has an inner diameter of 19˜21 mm, a thickness of 11.5˜12.5 mm, and an outer diameter of 50˜54 mm.

1. Field of the Invention
The present invention relates to a magnetron, and more particularly, to a miniaturized magnetron.
2. Discussion of the Related Art
Generally, a magnetron is an oscillation source of microwaves for heating foods, and is utilized for microwave ovens and the like due to its simple construction and highly efficient stable behavior.
Meanwhile, since magnets mounted in the magnetron are made of a permanent magnetic material, material costs for the magnetron are increased. In particular, a conventional magnetron has a problem in that, as the magnets and upper/lower magnetic poles are excessively large, the material costs are significantly increased. Additionally, the excessively large volumes of the magnet and the poles also cause an excessive increase in size of the magnetron.
Meanwhile, since a significantly reduced magnetron possibly causes a sharp reduction in an output of the magnetron, it is difficult to miniaturize the magnetron without decreasing the output of the magnetron.
Thus, the present invention is directed to a magnetron, which has a reduced size without being lowered in output performance.


A power conversion method of a power conversion apparatus including plural primary side ports disposed in a primary side circuit and a secondary side port disposed in a secondary side circuit magnetically coupled to the primary side circuit through a transformer, the method adjusting transmission power transmitted between the primary and secondary side circuits by changing a phase difference between switching of the primary and secondary side circuits, and changing a first duty ratio of the switching of the primary side circuit or a second duty ratio of the switching of the secondary side circuit, the method including: determining whether a value obtained by dividing the phase difference by 360° is greater than a third duty ratio; and setting the second duty ratio to be equal to or greater than the value obtained by dividing the phase difference by 360° when the value is greater than the third duty ratio.

1. Field of the Invention
The present invention relates to a power conversion apparatus and a power conversion method.
2. Description of Related Art
A power conversion apparatus is known which adjusts transmission power transmitted between a primary side conversion circuit including a plurality of primary side ports and a secondary side conversion circuit including a plurality of secondary side ports and being magnetically coupled to the primary side conversion circuit through a transformer according to a phase difference φ (for example, see Japanese Patent Application Publication No. 2011-193713 (JP 2011-193713 A)).
The transmission power that is adjusted according to the phase difference φ is affected by a value of a duty ratio D of switching of the primary conversion circuit or the secondary conversion circuit.
However, since the phase difference φ and the duty ratio D are independently controlled, if there is no period during which ON time of a switching element of the primary side conversion circuit and ON time of a switching element of the secondary side conversion circuit overlap, the transmission power may decrease even the phase difference φ increases.

Power conversion with controlled phase difference and duty ratio


A firewall configured to be interfaced between an internal and an external networks. The firewall includes a VoIP processor for detecting an outgoing VoIP packet sent from the internal network, for changing data in a header of the VoIP packet and also changing data contents in the VoIP packet corresponding to data changed in the header to enable bi-directional VoIP communication. In one embodiment, the VoIP processor changes a source IP address and a port number in the header of the VoIP packet and also changes the data contents in the VoIP packet corresponding to the source IP address and the port number changed in the header to enable bi-directional VoIP communication. In another embodiment, the firewall further includes an external VoIP interface comprising multiple VoIP ports for receiving multiple incoming VoIP packets each designated with one of the VoIP ports. And, the VoIP processor further includes a VoIP port versus internal address table for identifying an internal address in the internal network for directing each of the incoming VoIP packets to the internal address identified.

1. Field of the Invention
Embodiments of the present invention generally relate to the management and processes of the network communication packet implemented with a firewall. More particularly, this embodiments of the present invention relate to a new interface configuration and processing scheme for enhancing bi-directional VoIP communication traversing the firewall without degrading the level of protections provided by the firewall.
2. Descriptions of the Reference Art
A technical difficulty is still faced by those who apply Internet Protocol (IP) for voice communication by sending voice messages as digitized data packets on Internet, commonly known as Voice over IP (VoIP) technologies, when the sender or the receiver are protected by a firewall protection system. Specifically, several popular VoIP signaling protocols such as MGCP, SIP and H323 are commonly implemented. All these different types of protocols are implemented with the data relating to the end point address embedded as part of the data content transmitted in the Internet Protocol packets. Referring to FIG. 1 for a typical firewall setup where the firewall is installed as a protection interface between the internal and external networks for preventing invasions of undesirable transmission between the internal and external networks. A conventional firewall employs a network address translation (NAT) technique to change the IP packet header such that all outgoing packets from the internal network are presented to the external network as if there are sent out from the firewall. However, once the sender's identification, i.e., the source IP address and port number of the sender, is translated and changed by the firewall, a return packet in response to the sender's VoIP packets can only return to the firewall and would be unable to reach the sender. The communication loop is broken due to the operation of the firewall in changing the source IP and the source port numbers. For a packet sent from the internal network to the external network through the firewall, it would typically include the header information of source IP address, protocol type, source port number, destination IP address and destination port number. An exemplary header is shown below:    Source IP: 192.168.100.1    Protocol: UDP    Source port: 1025    Destination IP: 10.1.2.3    Destination port: 2727After the packet is processed by the firewall, the header data is changed and an example of the changed header is shown below:    Source IP: firewall's external IP address    Protocol: UDP    Source port: allocated by the firewall (for example 3330)    Destination IP: 10.1.2.3    Destination port: 2727
For the security of the network user protected by the firewall, the Sender's IP address is therefore changed and hidden from the external network. It is noticed that the destination IP and port number are not changed. The same IP address and port number maybe included in the content of the IP packets too. Specifically, a valid SIP request must contain the following header fields: To, From, CSeq, Call-ID, Max-Forwards, and Via; all of these header fields are mandatory in all SIP requests. Call-ID in this case includes a port number and IP address (or domain name) of an end point. For the outbound traffic, i.e., IP packets transmitted from the internal private network to an external public network, because the conventional firewall only changes the packet header, the end point address embedded in the packet content still points to the original IP addresses and the embedded IP address will be mismatched with the header now changed by the firewall. Due to the mismatches, the VoIP communication cannot be successful. Furthermore, for the inbound VoIP communications, because the internal host's IP addressees are hidden from the public network, VoIP traffic when designate the IP address and the port number of an internal IP address cannot reach individual end point by their IP address, thus an incoming call cannot be made. Additionally, even a special assignment is made to correlate a port number with an end point of an internal user, since for each specific protocol, the port number is fixed, for example port 2427 is for MGCP, and 2543 is for SIP. So in a conventional firewall for the management of incoming traffic, if a packet is targeting port 2427, it usually is a call. However, since only one port is used, a call can only be made to one end point inside firewall using the conventional method.
In summary, VoIP is a major enabler of high-value, converged voice/data applications. However, widespread use of VoIP is at odds with conventional security technology: Network-level devices, such as NAT gateways, lack the intelligence to recognize and properly process the critical signaling protocols that enable VoIP calls to be established and managed. Until now, extreme compromises have been required to enable flexible VoIP applications: Companies have been forced to either compromise their security, by opening holes in their perimeter security to allow VoIP signaling to pass, or have been forced to purchase expensive, single-function call-proxy systems that focus on solving the NAT traversal problem. Another approach—using VoIP only in conjunction with VPN tunnels—greatly limits the reach of Internet telephony. None of these so-called solutions achieves the goal of enabling widespread, secure use of VoIP technology.
Since there is an increase in adopting voice over IP technology in the enterprise environment spawning from renewed interest in converged voice/data application, there is an urgent need to resolve the difficulties. Particularly, as most conventional network security technologies employ the network address translation (NAT) technique as a universal standard to prevent unauthorized access to a private network from the Internet, these difficulties often force organizations to either comprise security or forsake the voice/data convergence because such applications have become impractical.
Therefore, a need still exits in the art to provide improved firewall systems with more intelligent operations capable of managing both VoIP and non-VoIP network communications in order to resolve these difficulties.

Firewall interface configuration and processes to enable bi-directional VoIP traversal communications


A co-ordinate-measuring instrument is provided with a translumination device which includes at least one illumination body and an image processing sensor system which is provided with a lens measuring along an optical axis. In order to perform high-accuracy measurement without the necessity of placing and removing the illumination body and the sensor image processing system, the illumination body is constructed in such a way that it emits diffused light and a filter which is embodied, for example in the form of a comb, provided with through holes and arranged between the illumination body and a measured object is transparent for beams forming with the axis an angle which is less than a defined limiting angle α.

The invention relates to a coordinate measuring device with a backlighting arrangement, especially for measuring a large area object, including at least one illumination element as well as an image processing sensor unit comprising a lens measuring along an optical axis.
In order to measure large area objects with a coordinate measuring device comprising an image processing sensor, it is necessary to illuminate large areas with as parallel light as possible to obtain reproducible measuring results of high accuracy.
Here exists the possibility of positioning moving illumination units together with the camera. The mechanical components necessary for this are, however, expensive and reduce the dynamic quality of the overall measuring device due to the moved masses.
A light flow regulator for a microscope is known from DE-A 27 01 764, which has a support with a set of light-permeable channels running parallel to one another. The support is rotatable about an axis in order to allow light to penetrate through the channels to the desired extent.
A backlighting configuration for a coordinate measuring device can be inferred from DE-A 198 05 040. A measured object can be subjected to diffuse or directed light by arrangements of fiber light guides, fluorescent tubes and/or light diodes.
A water-tight illumination arrangement according to DE-U 202 05 631, which is determined for manufacturing apparatuses, has a large number of light diodes whose rays are guided by a honey-comb light guide.