A discharge accelerating unit which accelerates a discharge of a capacitive load (floating capacitor C1) of a signal line when a positive polarity input gradation voltage DAC(P) decreases is provided for a positive polarity operating circuit. A charge accelerating unit which accelerates a charge of a capacitive load (floating capacitor C2) of a signal line when a negative polarity input gradation voltage DAC(N) decreases is provided for a negative polarity operating circuit. Good characteristics can be obtained irrespective of a switching period of the positive polarity operating circuit and the negative polarity operating circuit and luminance levels of adjacent dots. The number of devices which are added by the invention can be minimized.

1. Field of the Invention
The invention relates to a driving circuit for a liquid crystal display.
2. Related Background Art
FIG. 5 is a circuit diagram of a conventional liquid crystal driving circuit.
From the top of the diagram, (a) shows a positive polarity operating circuit, (b) shows a negative polarity operating circuit, and (c) and (d) show time charts for the operations of those operating circuits in order.
Referring to the diagram, the conventional driving circuit for a liquid crystal display has a positive polarity feedback amplifier AMP(P) and a negative polarity feedback amplifier AMP(N). A positive polarity input gradation voltage DAC(P) is inputted to a (+) terminal of the positive polarity feedback amplifier AMP(P). A positive polarity output gradation voltage OUT(P) is supplied to a parasitic capacitor C1 such as a signal line via a control switch SW3.
Further, a negative polarity input gradation voltage DAC(N) is inputted to a (+) terminal of the negative polarity feedback amplifier AMP(N). A negative polarity output gradation voltage OUT(N) is supplied to a parasitic capacitor C2 such as a signal line via the control switch SW3. The positive polarity feedback amplifier AMP(P) and the negative polarity feedback amplifier AMP(N) are connected as a pair to the two signal lines. Ordinarily, in many cases, those two signal lines are connected to two liquid crystal dots adjacently arranged on a liquid crystal display apparatus. Further, the connection of the positive polarity feedback amplifier AMP(P) and the connection of the negative polarity feedback amplifier AMP(N) are alternately switched between the signal lines at a predetermined time interval. Such a switching operation is performed in order to prolong a life span of the liquid crystal display apparatus.
The positive polarity feedback amplifier AMP(P) and the negative polarity feedback amplifier AMP(N) are voltage followers for outputting a voltage which is equal to an input voltage irrespective of magnitude of loads (parasitic capacitors C1 and C2 of the signal lines here). The voltage which becomes equal to ½ of a power voltage VDD is defined to be an intermediate voltage VM here.
An input voltage which is increased/decreased in the direction of the power voltage VDD in the case where the intermediate voltage VM is set to a reference voltage is defined as a positive polarity input gradation voltage DAC(P). An input voltage which is increased/decreased in the direction of a ground voltage VSS in the case where the intermediate voltage VM is set to the reference voltage is defined as a negative polarity input gradation voltage DAC(N). Similarly, an output voltage which is increased/decreased in the direction of the power voltage VDD in the case where the intermediate voltage VM is set to the reference voltage is defined as a positive polarity output gradation voltage OUT(P). An output voltage which is increased/decreased in the direction of the ground voltage VSS in the case where the intermediate voltage VM is set to the reference voltage is defined as a negative polarity output gradation voltage OUT(N).
That is, the positive polarity gradation voltage is a gradation voltage which increases like VU1, VU2, and VU3 toward the power voltage VDD in the case where the intermediate voltage VM is set to the reference. The negative polarity gradation voltage is a gradation voltage which increases like VD1, VD2, and VD3 toward the ground voltage VSS in the case where the intermediate voltage VM is set to the reference.
Ordinarily, for example, in the case of using a nematic liquid crystal, intensity of an electric field which is applied to the liquid crystal at the intermediate voltage VM becomes equal to 0 by another construction (not shown), so that the liquid crystal enters a state where it is difficult to transmit the light. On the other hand, the larger the positive polarity output gradation voltage OUT(P) or the negative polarity output gradation voltage OUT(N) is, the larger the intensity of the electric field which is applied to the liquid crystal is and the liquid crystal enters a state where it is easy to transmit the light. Therefore, even if the switching operation of the connection of the positive polarity feedback amplifier AMP(P) and the connection of the negative polarity feedback amplifier AMP(N) is executed between the two signal lines every predetermined elapse of time as mentioned above, a reproduced image is not influenced.
For example, a case where the positive polarity input gradation voltage DAC(P) and the negative polarity input gradation voltage DAC(N) which are line-symmetrical with respect to the intermediate voltage VM as a center are inputted to the positive polarity feedback amplifier AMP(P) and the negative polarity feedback amplifier AMP(N), respectively, will be described. Usually, since luminance levels of the adjacent dots are equal in many cases, such a state often occurs. FIGS. 5(c) and 5(d) show changes in each voltage in such a state.
FIG. 5(c) shows the time chart in the case where, for example, the positive polarity input gradation voltage DAC(P) which increases from VU1 to VU3 at time P1, decreases from VU3 to VU2 at time P2, and increases from VU2 to VU3 at time P5 is inputted to the positive polarity feedback amplifier AMP(P), respectively, and the negative polarity input gradation voltage DAC(N) which increases from VD1 to VD3 at time P1, decreases from VD3 to VD2 at time P2, and increases from VD2 to VD3 at time P5 is inputted to the negative polarity feedback amplifier AMP(N), respectively.
At this time, in the positive polarity feedback amplifier AMP(P), when the positive polarity input gradation voltage DAC(P) increases from VU1 to VU3 at time P1, the positive polarity output gradation voltage OUT(P) promptly traces VU3. However, when the positive polarity input gradation voltage DAC(P) decreases from VU3 to VU2 at time P2, although the positive polarity output gradation voltage OUT(P) is supposed to decrease to VU2 at time P3, it cannot trace such a voltage but decreases to reach VU2 at time P4. In the negative polarity feedback amplifier AMP(N), when the negative polarity input gradation voltage DAC(N) increases from VD1 to VD3 at time P1, the negative polarity output gradation voltage OUT(N) promptly traces VD3. However, when the negative polarity input gradation voltage DAC(N) decreases from VD3 to VD2 at time P2, although the negative polarity input gradation voltage OUT(N) is supposed to decrease to VD2 at time P3, it cannot trace such a voltage but decreases to reach VD2 at time P4.
Such a phenomenon is common to the voltage followers which are used as a positive polarity feedback amplifier AMP(P) and a negative polarity feedback amplifier AMP(N) to which a capacitive load is connected. That is, in the positive polarity feedback amplifier AMP(P), although the operation to increase the positive polarity output gradation voltage OUT(P) is fast, the operation to decrease the positive polarity output gradation voltage OUT(P) is slow. Such a fact is generally known. Also in the negative polarity feedback amplifier AMP(N), although the operation to increase the negative polarity output gradation voltage OUT(N) is fast, the operation to decrease the negative polarity output gradation voltage OUT(N) is slow. Such a fact is also generally known. In such a state, an image cannot be accurately reproduced onto a display screen of the liquid crystal display apparatus.
Therefore, when the switching operation of the connection of the positive polarity feedback amplifier AMP(P) and the connection of the negative polarity feedback amplifier AMP(N) is executed between the two signal lines at a predetermined time interval as mentioned above, the control switch SW3 is short-circuited, charges charged in the parasitic capacitors C1 and C2 are once returned to the intermediate voltage VM, and thereafter, the operation is started. A peripheral construction of the control switch SW3 will be described in detail hereinlater in the description of a preferred embodiment.
Meanwhile, constructions to prevent the occurrence of such a problem have also been laid open (for example, refer to JP-A-11-95729 (Page 5, FIG. 1) and JP-A-2002-229525 (Summary)).
The method whereby the control switch SW3 is short-circuited each time the connection switching of the positive polarity feedback amplifier AMP(P) and the negative polarity feedback amplifier AMP(N) is executed at a predetermined time interval, the charges charged in the parasitic capacitors C1 and C2 are once returned to the intermediate voltage VM, and thereafter, the operation is started as mentioned above, has the following problems to be solved. That is, when the connection switching is executed at a predetermined time interval, the operation is performed effectively. However, if a switching period becomes long, for example, twice as long as the predetermined time interval, three times as long as the predetermined time interval, . . . , a case where a signal level decreases in the same period occurs. In such a case, since the connection switching is not executed even if the signal level decreases, an inconvenience as mentioned above occurs. Therefore, the effect is small. This is because the voltages of the parasitic capacitors C1 and C2 are not returned to the intermediate voltage VM unless the connection switching is executed.
Even if the connection switching is executed at a predetermined time interval, when the luminance levels of the adjacent dots are different, such amounts of the charges charged in the parasitic capacitors C1 and C2 are not equal, so that the voltages are difficult to be returned to the intermediate voltage VM. Further, in the cases of JP-A-11-95729 and JP-A-2002-229525, since a circuit scale increases, there are problems to be solved such as increase in area of a chip and increase in costs.

Driving circuit for liquid crystal display


A vehicle steering apparatus (10) includes a steering gear assembly (20) which is connected with a steerable vehicle wheel (12). A first sensor (26) has an output signal which is a function of steering wheel position. A second sensor (28) has an output signal which is a function of steerable wheel position. A controller (30) is operable to provide an output signal when the steerable vehicle wheel position does not correspond to the steering wheel position. A motor (34) is connected with a differential gear mechanism (36). The motor (34) is operable in response to the output signal from the controller (30) to effect operation of the differential gear mechanism (36) to actuate the steering gear assembly (20) and change the position of the steerable vehicle wheel (12).

The present invention relates to a steering apparatus for use in turning steerable vehicle wheels.
During operation of a vehicle having steerable wheels, the position of a manually rotatable steering wheel for the vehicle may not agree with the position of a steerable wheel of the vehicle. This may be caused by lash in the steering apparatus, joint phasing, and/or elastic yielding of components of the steering apparatus. The resulting difference between the desired position of the steerable vehicle wheel and the position of the steering wheel may be objectionable to a driver of the vehicle.


The present invention is related to compounds of formula (I),

Stimulation of food intake is important in connection with patients suffering from anorexia due to chronic medical conditions, eating disorders, and other conditions in which excessive weight loss has produced a detrimental effect on the patients' health.
Obesity is a common and very serious public health problem as it increases a person's risk for a number of serious conditions, including diabetes, heart disease, stroke, high blood pressure, and some types of cancers. Considerable increase in the number of obese individuals over the past two decades has created profound public health implications. Although studies have demonstrated that reduction in obesity by diet and exercise reduces the associated risk factors dramatically, these treatments are largely unsuccessful considering obesity is strongly associated with genetically inherited factors that contribute to increased appetite, preferences for highly caloric foods, reduced physical activity, and increased lipogenic metabolism.
Growth hormone (GH) is not only of importance for linear body growth but is also of major importance for the maintenance of body composition, metabolism and heart function in adult life. GH release from the anterior pituitary is regulated by the stimulatory peptide GH-releasing hormone (GHRH) and the inhibitory peptide somatostatin (Frohman, L; Jansson, J.-O. Endocr. Rev. (1986) 7:223–253). Early research identified small GH-releasing peptides (GHRPs) derived from the pentapeptide met-enkephalin (Momany, F; Browers, C, et al: Endocrinology (1981) 108:31–39). Further efforts led to the development of a number of peptidyl and non-peptidyl growth hormone secrectgogues (GHSs), including the orally-active, non-peptidyl GH secretagogue MK677 (Svensson, J; Lohn, L; Jansson, J.-O. et al: J. Clin. Endocrinol. Metab. (1998) 83:362–369). Later efforts cloned a seven-transmembrane GPCR that was a target for the GHSs (Howard, A; Feighner, S.; Cully, D. et al: Science (1996) 273:974–977).
This GHS-receptor (GHS-R) is localized in the hypothalamus and in the pituitary, but also in other brain areas such as the hippocampus as well as the pancreas. Recently, an endogenous ligand for the GHS-R, ghrelin, an acylated peptide consisting of 28 amino acids was isolated (Kojima, M; Hosoda, H; Date, Y; Nakazoto, M.; Matsuo, H; Kangawa, K: Nature (1999), 402:656–660). Since then, ghrelin has been found to be localized in the hypothalamic-pituitary area where it stimulates the release of GH to the circulation, but is also found in the highest concentration in the stomach.
Biological evidence indicates that ghrelin has an important role in the regulation of metabolism and energy expenditure. Ghrelin was found to stimulate food intake and weight gain when administered either systemically or intraventricularly in rodents (Nakazato M, Murakami N, Date Y, Kojima M, Matsuo H, Kangawa K, et al. Nature 2001;409:194–198) (Asakawa A, Inui A, Kaga T, Yuzuriha H, Nagata T, Ueno N, et al. Gastroenterology 2001;120:337–345). Ghrelin was also found to be more potent than any other orexigenic peptide except neuropeptide Y (NPY). The orexigenic activity of centrally administered ghrelin is thought to be mediated by brain NPY and AGRP, two neuropeptides with potent orexigenic actions (Kamegai J, Tamura H, Shimizu T, Ishii S, Sugihara H, Wakabayashi I. Endocrinology 2000;141:4797–4800). It was also recognized that the appetite activity of centrally administered ghrelin can be blocked by co administration of a NPY-Y1 receptor antagonist. In addition, ghrelin was found to reverse leptin-induced inhibition of food intake (Shintani M, Ogawa Y, Ebihara K, Aizawa-Abe M, Miyanaga F, Takaya K, et al. Diabetes 2001;50:227–232). Ghrelin exerts its actions in the arcuate nucleus and paraventricular nucleus to influence the interplay of NPY, AGRP and a-MSH circuits. Ghrelin may also act via afferent vagal pathways that terminate in the hypothalamus. In obese patients, the increase in the plasma ghrelin level with diet-induced weight loss is consistent with the hypothesis that ghrelin has a role in the long-term regulation of body weight. Gastric bypass in obese patients is associated with markedly suppressed ghrelin levels, possibly contributing to the weight-reducing effect of the procedure (Cummings, D. E. et al: N Engl J Med 2002;346:1623–30).
Intracerebroventricular treatment with the anti-ghrelin antiserum against the N-terminal region twice a day for 5 days in rats decreased significantly both daily food intake and body weight (Murakami, N; T Hayashida, T; T Kuroiwa, T; K Nakahara, K; Ida, T; Mondal, M S; Nakazato, M; Kojima M; Kangawa, K. Journal of Endocrinology (2002) 174, 283–288). Transgenic (Tg) rats expressing an antisense ghrelin receptor mRNA under the control of the promoter for tyrosine hydroxylase (TH) selectively attenuated ghrelin receptor protein expression in the arcuate nucleus (Arc). Tg rats had lower body weight and less adipose tissue than did control rats. Daily food intake was reduced, and the stimulatory effect of GHS treatment on feeding was abolished in Tg rats (Shuto, Y; Shibasaki, T; Otagiri, A; et al: J. Clin. Invest. 109:1429–1436 (2002)). These data suggest that ghrelin receptor modulators may be beneficial in the treatment of anorexia, cancer cachexia, eating disorders, age-related decline in body composition, weight gain, obesity and disorders associated with obesity such as diabetes mellitus.

Tetraline derivatives as ghrelin receptor modulators

Abstract: or a therapeutically suitable salt or prodrug thereof, the preparation of the compounds, compositions containing the compounds and the use of the compounds in the prevention or treatment of disorders regulated by ghrelin including anorexia, cancer cachexia, eating disorders, age-related decline in body composition, weight gain, obesity, and diabetes mellitus.


A method of braking a vehicle includes determining via a controller a desired braking power for braking the vehicle. Under the method, a bypass valve that controls exhaust gas flow through the exhaust heat recovery device is moved via the controller to a relatively restrictive position to provide at least some of the desired braking power.

Hybrid vehicles that have an electric motor-generator are often configured to implement regenerative braking to slow the vehicle by operating the motor-generator as a generator. The motor-generator converts rotational torque of the vehicle axle into electrical energy stored in an energy storage device, such as a battery. The availability of regenerative braking is variable as it depends upon the charge power limit of the energy storage device. For example, if the charge power limit of the energy storage device is less than the required braking power, then regenerative braking will not be able to provide all of the desired braking power, and the friction brakes of the vehicle will be required to absorb at least some energy. If, during a braking event, the energy storage device reaches a predetermined maximum state of charge, the regenerative braking is ceased and the system must increase the level of friction braking to meet the braking demand. Although suitable for meeting the level of braking demand, these systems can have an uneven feel when such a transition from regenerative to full friction braking occurs. Additionally, because the availability of the second form of braking (i.e., the regenerative braking) is variable, the friction braking system must be able to bear a substantial amount of load, adding cost to the system. For example, an additional hydraulic pump is often required on such braking systems to increase the braking capacity.
Some vehicles have a dedicated exhaust valve in the exhaust system that can be moved to restrict exhaust flow, adding torque on the engine to slow the engine, providing an additional source of braking power. The dedicated exhaust valve is used only for this purpose on such vehicles, adding expense to the vehicle.

Hybrid vehicle and method of braking by controlling an exhaust heat recovery device bypass valve on a hybrid vehicle


A freewheeling DC/DC step-down converter includes a high-side MOSFET, an inductor and an output capacitor connected between the input voltage and ground. A freewheeling clamp, which includes a freewheeling MOSFET and diode, is connected across the inductor. When the high-side MOSFET is turned off, a current circulates through the inductor and freewheeling clamp rather than to ground, improving the efficiency of the converter. The converter has softer diode recovery and less voltage overshoot and noise than conventional Buck converters and features unique benefits during light-load conditions.

Voltage regulation is commonly required to prevent variation in the supply voltage powering various microelectronic components, such as digital ICs, semiconductor memories, display modules, hard disk drives, RF circuitry, microprocessors, digital signal processors and analog ICs, especially in battery-powered applications such as cell phones, notebook computers and consumer products.
Since the battery or DC input voltage of a product often must be stepped-up to a higher DC voltage, or stepped-down to a lower DC voltage, such regulators are referred to as DC-to-DC converters. Step-down converters, commonly referred to as Buck converters, are used whenever a battery's voltage is greater than the desired load voltage. Step-down converters may comprise inductive switching regulators, capacitive charge pumps, and linear regulators. Conversely, step-up converters, commonly referred to boost converters, are needed whenever a battery's voltage is lower than the voltage needed to power its load. Step-up converters may comprise inductive switching regulators or capacitive charge pumps.
Of the aforementioned voltage regulators, the inductive switching converter can achieve superior performance over the widest range of currents, input voltages and output voltages. The operation of a DC/DC inductive switching converter is based on the simple principle that the current in an inductor (coil or transformer) cannot be changed instantly, and that an inductor will produce an opposing voltage to resist any change in its current.
The basic principle of an inductor-based DC/DC switching converter is to switch or "chop" a DC supply voltage into pulses or bursts, and to filter those bursts using a low-pass filter comprising an inductor and a capacitor to produce a well-behaved time-varying voltage, i.e. to change a DC voltage into an AC voltage. By using one or more transistors switching at a high frequency to repeatedly magnetize and de-magnetize an inductor, the inductor can be used to step-up or step-down the converter's input voltage, producing an output voltage different from its input voltage. After changing the AC voltage up or down using magnetics, the output voltage is then rectified back into a DC voltage, and filtered to remove any ripples.
The DC/DC converter is typically implemented using MOSFETs with a low on-state resistance, commonly referred to as "power MOSFETs". Using feedback from the converter's output voltage to control the switching conditions, a constant well-regulated output voltage can be maintained despite rapid changes in the converter's input voltage or its output current.
To remove any AC noise or ripple generated by the switching action of the MOSFETs, an output capacitor is placed across the output terminal of the switching regulator circuit. Together the inductor and the output capacitor form a "low-pass" filter able to prevent most of the MOSFETs' switching noise before it reaches the load. The switching frequency, typically 1 MHz or more, must be "high" relative to the resonant frequency of the filter's "LC" tank. Averaged across multiple switching cycles, the switched inductor behaves like a programmable current source with a slow-changing average current.
Since the average inductor current is controlled by MOSFETs that are either biased as "on" or "off" switches, the power dissipation in the MOSFETs is theoretically small, and high converter efficiencies, in the 80% to 90% range, can be realized. Specifically when a power MOSFET is biased as an on-state switch using a "high" gate bias, it exhibits a linear I-V drain characteristic with a low RDS(on) resistance typically 200 milliohms or less. At 0.5 A for example, such a device will exhibit a maximum voltage drop ID·RDS(on) of only 100 mV despite its high drain current. Its power dissipation during its on-state conduction time is ID2·RDS(on). In the example given, the power dissipated while the transistor is conducting is (0.5 A)2·(0.2Ω)=50 mW.
Thus a power MOSFET has its gate biased to its source, i.e. so that VGS=0. Even with an applied drain voltage VDS equal to a converter's battery input voltage Vbatt, a power MOSFET's drain current IDSS is very small, generally well below one microampere and more generally in the range of nanoamperes. The current IDSS primarily comprises junction leakage.
For these reasons, a power MOSFET used as a switch in a DC/DC converter is efficient, since in its off-condition it exhibits low currents at high voltages, and in its on-state it exhibits high currents at a low voltage drop. Excepting switching transients, the ID·VDS product in the power MOSFET remains small, and power dissipation in the switch remains low.
A critical component in switching regulation is the rectifier function needed to convert, or "rectify", the synthesized AC output of the chopper back into a DC voltage. To ensure that the load never sees a reversal of polarity in voltage, a rectifier diode is placed in the series path of the switched inductor and the load, thereby blocking large AC signals from the load. The rectifier may be located topologically either in the high-side path, i.e., between the positive terminal of the power or battery input and the positive terminal of the output, or on the low-side path, i.e. in the "ground" return path. Another function of the rectifier is to control the direction of energy flow so that current only flows from the converter to the load and does not reverse direction.
In one class of switching regulators, the rectifier function employs a P-N junction diode or a Schottky diode. The Schottky diode is preferred over the P-N junction because it exhibits a lower forward voltage drop than P-N junctions, typically 400 mV instead of 700 mV, and therefore dissipates less power. During forward conduction, a P-N diode stores charge in the form of minority carriers. These minority carriers must be removed, i.e. extracted, or recombine naturally before the diode is able to block current in its reverse-biased polarity.
Because a Schottky diode contains a metal-semiconductor interface rather than a P-N junction, ideally it does not utilize minority carriers to conduct and therefore stores less charge than a P-N junction diode. With less stored charge, the Schottky diode is able to respond more quickly to changes in the polarity of the voltage across its terminals and to operate at higher frequencies. Unfortunately Schottky diodes have several major disadvantages, one of which is that it exhibits significant and unwanted off-state leakage current, especially at high temperatures. As a result, there is unfortunately a fundamental tradeoff between a Schottky diode's relatively high off-state leakage current and its relatively low forward-biased voltage drop.
Moreover, the lower its voltage drop during conduction, the leakier it becomes in its off state. The leakage current also exhibits a positive voltage coefficient of current, so that as the leakage current increases, power dissipation also increases, causing the Schottky diode to leak more and dissipate more power, causing even more heating. With such positive feedback, localized heating can cause a hot spot to get hotter and "hog" more of the leakage until the spot reaches such a high current density that the device fails, a process known as thermal runaway.
Another disadvantage of a Schottky diode is the difficulty of integrating it into an IC using conventional wafer fabrication processes and manufacturing. Metals with the best properties for Schottky diodes are not commonly available in IC processes. Some commonly available metals exhibit too high a voltage barrier, i.e. too high a voltage drop, while other commonly available metals exhibit too low a barrier potential, i.e. they allow too much leakage current.
Despite these limitations, many switching regulators today use P-N diodes or Schottky diodes for rectification. As a two-terminal device, a rectifier does not require a gate signal to control when it conducts. Aside from current resulting from the transient charge storage, the rectifier naturally prevents reverse currents, so that energy cannot flow from the output capacitor and electrical load back into the converter and its inductor.
To reduce voltage drops and conduction losses, power MOSFETs are sometimes used in place of Schottky rectifier diodes in switching regulators. Operation of a MOSFET as a rectifier is often accomplished by placing the MOSFET in parallel with a Schottky diode and turning on the MOSFET whenever the diode conducts, i.e. synchronous to the diode's conduction. In such an application, the MOSFET is sometimes referred to as a "synchronous rectifier."
Since a synchronous rectifier MOSFET can be sized to have a low on-resistance and a lower voltage drop than a Schottky diode, when the Schottky diode is conducting current is diverted from the diode to the MOSFET channel, and the overall power dissipation in the "rectifier" is reduced. Most power MOSFETs includes a parasitic source-to-drain diode. In a switching regulator, the orientation of this intrinsic P-N diode must be the same polarity as the Schottky diode, i.e. cathode to cathode, anode to anode. Since the parallel combination of the silicon P-N diode and Schottky diode carries current only for brief intervals, known as "break-before-make" intervals, before the synchronous rectifier MOSFET turns on, the average power dissipation in the diodes is low, and the Schottky diode is often eliminated altogether.
Assuming that the transistor switching events are relatively fast compared to the oscillating period of the regulator, the power losses during switching can be considered negligible or alternatively treated as a fixed power loss. Overall, the power lost in a low-voltage switching regulator can be estimated by considering the conduction and gate drive losses. At multi-megahertz switching frequencies, however, the switching waveform analysis becomes more significant and the MOSFET's drain voltage, drain current, and gate voltage must be analyzed as a function of time.
A synchronous rectifier MOSFET, however, unlike a Schottky or P-N junction diode, allows current to flow bi-directionally and must be operated with precise timing on its gate signal to prevent a reverse current flow, an unwanted type of conduction that lowers efficiency, increases power dissipation and heating, and may damage the device. By slowing down the switching rates and increasing the turn-on delays, efficiency can often be traded for improved robustness in DC/DC switching regulators.
Applying the above principles, present inductor-based DC/DC switching regulators are implemented in a wide range of circuits, inductors, and converter topologies. Broadly, they can be divided into two major topologies, non-isolated and isolated converters.
The most common isolated converters include the flyback converter and the forward converter, and require a transformer or coupled inductor. At higher power, full-bridge converters are also used. Isolated converters are able to step up or step down the input voltages depending on the primary to secondary winding ratio of the transformer. Transformers with multiple windings can produce multiple outputs simultaneously, including voltages both higher and lower than the input. The disadvantage of transformers is they are large compared to single-winding inductors and suffer from unwanted stray inductances.
Non-isolated converters include step-down. Buck converters, step-up boost converters, and Buck-boost converters. Buck and boost converters are efficient and compact in size, particularly when operating in the megahertz frequency range, where inductors of 2.2 μH or less may be used. Such topologies produce a single regulated output voltage per coil, and require a dedicated control loop and a separate PWM controller for each output to constantly adjust the on-times of the MOSFET switches so as to regulate the output voltage.
In portable and battery powered applications, synchronous rectification is commonly employed to improve efficiency. A step-up boost converter employing synchronous rectification is known as a synchronous boost converter. A step-down Buck converter employing synchronous rectification is known as a synchronous Buck regulator.
Non-Synchronous Versus Synchronous Buck Converter Operation
As illustrated in FIG. 1A, a prior art Buck converter 1 includes a P-channel or N-channel power MOSFET 2, an inductor 3, an output capacitor 4, a Schottky rectifier diode 5, and a pulse-width modulation (PWM) controller 6. Inductor 3, MOSFET 2 and rectifier 5 share a common node referred to here as the "Vx" node (sometimes referred to as the "Lx" node), which exhibits a voltage Vx. A diode 7 is parasitic to MOSFET 2 and remains reverse-biased and off throughout regular operation of Buck converter 1.
Through the switching action of power MOSFET 2, the Vx node switches "rail-to-rail," exhibiting a potential alternating between approximately Vbatt when MOSFET 2 is on (and conducting a current IL(on)) to slightly below ground when MOSFET 2 is off (when a current IL(off) recirculates through rectifier diode 5). The waveform of Vx is illustrated in graph 10 of FIG. 1B, where Vx when MOSFET 2 is conducting (curve 11) is given by the expression (Vbatt−I·RDS(on)) and Vx when MOSFET 2 is off (curve 14) is given by −Vf.
At time t=12, after a duration ton, inductor 3 drives voltage Vx negative, and depending on the design and layout of converter 1 at this point Vx may experience some voltage overshoot and unwanted oscillations or ringing 13. After an interval toff, at time 15, MOSFET 2 turns on, and after diode 5 recovers from any stored charge, Vx exhibits a positive transition 15 and the entire cycle repeats.
In a synchronous Buck converter, rectifier diode 5 is replaced by a second power MOSFET. As shown in FIG. 2A, a synchronous Buck converter 20 includes a high-side power MOSFET switch 22, an inductor 23, an output capacitor 24, and a low-side synchronous rectifier MOSFET 21 with anintrinsic parallel diode 25. The gates of MOSFETs 22 and 21 are driven by break-before-make (BBM) circuitry 27 and controlled by a PWM controller 26 in response to a feedback voltage VFB from the converter's output present across output capacitor 24. BBM operation is needed to prevent a short between Vbatt and ground through MOSFETs 21 and 22.
The waveform for Vx in synchronous regulator 20 is illustrated in graph 30 of FIG. 2B, where through the switching action of high-side power MOSFET 22, the Vx node switches rail-to-rail, exhibiting a potential alternating between approximately Vbatt when said MOSFET is on (and conducting current IL(on)) and to slightly below ground when MOSFET 22 is off (when a current IL(off) recirculates through MOSFET 21). Vx is illustrated in graph 30 as being equal to Vbatt−I·RDS1(on) when MOSFET 22 is conducting (curve 31).
At time t=32, after a duration ton, inductor 23 drives Vx negative, and depending on the design and layout of converter 20 may experience some voltage overshoot and unwanted oscillations or ringing 33 before settling to a voltage −Vf. At time t=34 after a break-before-make time interval tBBM (as determined by BBM circuitry 27), Vx is reduced by conducting synchronous rectifier MOSFET 21 to a magnitude (−I·RDS2(on)), reducing the power loss compared to dissipation in P-N diode 25.
At a time t=35, just before high-side MOSFET 22 is turned on, synchronous rectifier MOSFET 21 is shut off and Vx returns to −Vf, (curve 36), the forward voltage drop across diode 25. After an interval toff, MOSFET 22 turns on, and after P-N diode 25 recovers from any charge storage, Vx exhibits a positive transition 37. Depending on the recovery of P-N diode 25 Vx may exhibit an over-voltage spike 38. Following spike 38 and subsequent ringing Vx stabilizes at (Vbatt−I·RDS1(on)) and the entire cycle repeats.
High-side MOSFET 22 may be an N-channel or P-channel MOSFET. The grounded synchronous rectifier MOSFET 21 is more conveniently implemented as an N-channel MOSFET. Diode 28, which remains off and reverse-biased during the normal operation of converter 22, is a P-N diode intrinsic to high-side MOSFET 22. Since diode 28 does not conduct under normal operation, it is shown with dotted lines. Diode 25, intrinsic to synchronous rectifier MOSFET 21, becomes forward-biased whenever high-side MOSFET 22 is off but carries a substantial current only when MOSFET 21 is off. A Schottky diode may be included in parallel with MOSFET 21 but with series inductance may not operate fast enough to divert current from the forward-biased diode 25.
If the percentage of the time that energy flows from the battery or power source into the DC/DC converter (i.e. the percentage of time when high-side MOSFET switch 22 is on and inductor 23 is being magnetized) is defined as the duty factor D of the converter, the output-to-input voltage ratio of the converter is proportionate to the duty factor, i.e.
            V      out              V              i                                                  n              =      D    ≡                  t        on            T
While this equation describes a wide range of conversion ratios, a Buck converter cannot smoothly approach a voltage ratio of zero or unity without requiring extremely fast devices and circuit response times. Considering these factors, the duty factor of a Buck converter is limited in practice to the range of 5% to 95%.
Forced Diode Recovery Operation and Impact
Diode recovery is a major source of power loss and electrical noise in switching regulators. In graph 30 of FIG. 2B, the high dV/dt voltage transient 37 and voltage overshoot 38 occur because of stored charge in diode 25. This phenomenon is better explained in graph 40 of FIG. 2C, wherein the rectifier current Irect and the voltage Vx are plotted against time. Prior to time t1, as shown in inset 41, high-side MOSFET 22 is off and the low-side synchronous rectifier MOSFET 21 is on, carrying a current Irect that is the same as the current IL flowing through inductor 23, i.e. Irect=IL (curve 50). During this interval Vx (the voltage across synchronous rectifier MOSFET 21) is equal to Irect·RDS2(on) (curve 60).
At time t1 MOSFET 21 turns off and P-N junction diode 25 must carry the inductor current IL by itself. As a result, Vx increases in absolute magnitude to −Vf (curve 61). During this break-before-make interval, charge is stored in P-N junction diode 25. This condition, illustrated in inset 42, persists until time t2, when high-side MOSFET 22 once again turns on.
As shown in inset 43, the instant MOSFET 22 turns on it is biased with a large drain voltage and a small gate voltage operating in its saturated region as a controlled current source, ramping up in current. As the current in MOSFET 22 ramps up, it supplies an increasing percentage of current in inductor 23, diminishing the current burden in rectifier diode 25 as evidenced by the linear drop in Irect current (curve 51). During this ramp-up, the absolute value of the voltage across reverse-biased diode 25 declines gradually by an amount ΔVx (curve 62), but diode 25 remains reverse-biased and Vx is still below ground.
If no charge were present in P-N diode 25, at time t2 when current Irect reaches zero, diode 25 would turn off and Irect would never go negative. But because of stored charge in P-N diode 25, the current ramp (curve 51) in diode 25 reverses polarity and actually goes negative, with current flowing into the cathode of diode 25. As the charge in the diode depletes and recombines, the voltage across diode 25 approaches zero (curve 63).
At time t6 the voltage across rectifier diode 25 reverses polarity and the diode reverse recovery current reaches its peak (point 52). Vx then rises rapidly with a high dV/dt slew rate (curve 64), powered by a high side MOSFET 22 which is now biased into a full-on condition with an on-state resistance RDS1(on) as represented schematically in inset 44. During this interval, high-side MOSFET 22 must supply both the current through inductor 23 and the reverse-recovery current in diode 25. A reverse current in diode 25 means current is flowing into the cathode of the P-N junction diode even though the diode is reverse-biased and theoretically should be off. By temporarily conducting a negative current while being reverse-biased (curve 53), diode 25 produces an energy loss Err during the interval Δtrr=t9−t6 and given by
      E    rr    ≈            ∫              t        6                    t        9                                          I                                (            t            )                          ·                  V                                (            t            )                                            ⅆ        t
Err can be substantial. Reverse currents of 1 A or more may occur with instantaneous power (Irr(peak)·Vbatt) losses of over 4W. Since this reverse current is supplied through Vbatt-connected high-side MOSFET 22, the energy loss is similar to shoot-through current losses, and using a triangular approximation contributes an average power loss of (2W)·Δtrr/T.
Moreover, because of the high dV/dt in the region of curve 63, Vx over-shoots the battery input voltage Vbatt. The cause for this overshoot is represented schematically in equivalent circuit 100 of FIG. 2D, where the battery is represented by voltage source 101, the inductor by current source 103, the charged output capacitor by voltage source 104, the high side MOSFET with drain current I1 represented by controlled current source 102, and the recovery diode 105 by a junction capacitance 107 and a minority carrier diffusion capacitance by P-N junction diode 106.
Inset 108 traces the change in I1 with the drain voltage VDS1 of high-side MOSFET 102 over time, where VDS1=(Vbatt−Vx). For example, at time t2 the high-side MOSFET is off and current I1 is zero. As the gate voltage of the high-side MOSFET operating in its saturated region increases (bracket 109) in magnitude from VG(t3) to VG(t7), the magnitude of current I1 increases without significant changes in drain voltage VDS1. For example, at time t6, Vx=0 and the drain voltage has a voltage VDS1=Vbatt (point 112). The voltage during this time period is nearly constant because diode 105 still contains stored charge and will not let Vx change. Beyond time t7, however, the diode "let's go" and the voltage changes rapidly (curve 111).
Referring again to FIG. 2C, at time t8 the voltage overshoot may reach a peak voltage Vpeak (point 65). If the magnitude of Vpeak is 600 mV or more greater than Vbatt, it will momentarily forward-bias the high-side diode 28, storing charge and causing noise and further oscillations (curve 66).
Finally, at time t9, as shown in inset 67 in FIG. 2C, the Vx voltage stabilizes at Vbatt (curve 67), the rectifier current Irect is zero (curve 54), and the reverse recovery of diode 25 is complete. Referring again to inset 108 of FIG. 2D, at point 113 the gate of high-side MOSFET 102 reaches a bias VG(t8) and MOSFET 102 enters its linear region (curve 110), no longer behaving as a controlled current source. In the linear region 110, the drain current I1 and drain voltage VDS1 do not change substantially.
In conclusion, diode recovery occurs in a synchronous Buck converter as a consequence of break-before-make operation, where both high-side and low-side MOSFETs are momentarily off. The charge stored in the diode leads to current spikes between the battery input and ground, i.e. across the converter's power input. It also causes increased power dissipation, loss of efficiency, high dV/dt slew rates, voltage overshoot, noise, and unwanted ringing and oscillations. Such oscillations may also limit the maximum operating frequency of the switching regulator.
Gate Drive Losses
Another source of power loss in a Buck converter results from the charging and discharging of the MOSFET gate capacitances. The origin of gate drive loss is represented schematically in the Buck converter 120 of FIG. 3A, where a P-channel MOSFET 122 includes a drain-to-gate capacitance CDG (capacitor 126), gate-to-source capacitance CGS (capacitor 128), and drain-to-source capacitance CDS (capacitor 127). To turn MOSFET 122 on and off, gate driver 125 must supply transient gate drive currents iG(t) to charge and discharge the gate connected CDG and CGS capacitors 126 and 128 at the desired frequency. All of the MOSFET's capacitors shown are voltage variable.
The magnitude of drain-to-gate capacitor 126 is especially important since it appears larger in actual operation than its small signal equivalent value. This amplifying effect on input capacitance, originally known as the "Miller" effect in bipolar amplifiers, is a consequence of voltage gain in converter 120. This voltage gain Av(t) occurs during operating conditions when MOSFET 122 is saturated and behaves like a programmable current source. The CDG input capacitance is scaled in proportion to this gain, which varies during a switching transient.
Even though the parasitic capacitance in MOSFET 122 gives rise to gate drive and switching losses, the power required to drive the MOSFET's capacitance is manifested in gate driver 125, not in the MOSFET itself and must be supplied by the battery input source Vbatt. Changing the high-side MOSFET from a common-source configured P-channel device to a source-follower N-channel device does not eliminate the Miller feedback effect.
In Buck converter 140 of FIG. 3B, for example, a high-side N-channel MOSFET 142 includes a drain-to-gate capacitance CDG (capacitor 146), a gate-to-source capacitance CGS (capacitor 148), and a drain-to-source capacitance CDS (capacitor 147). To turn MOSFET 142 on and off, a source-referenced gate driver 145 must supply transient gate drive currents iG(t) to charge and discharge the gate connected CDG and CGS (capacitors 146 and 148) at the desired frequency. All of the MOSFET's capacitors shown are voltage variable.
Even though the drain of N-channel MOSFET 142 is biased at a fixed potential Vbatt, gate driver 145 must float with the voltage Vx, so that the gate potential VG changes with respect to the drain potential VD during a switching transient. As a consequence the magnitude of input capacitance is still amplified by the Miller effect and must be driven by gate driver 145. The power needed to drive the extra capacitance is delivered from bootstrap capacitor 149, which is ultimately is supplied from Vbatt through forward-biased bootstrap diode 150 whenever Vx is at ground.
Gate drive loss therefore occurs driving the high-side MOSFET in a Buck converter regardless of whether the device is an N-channel source-follower device or a P-channel common-source configured device. Rather than calculate the power loss in a voltage variable capacitor, a more accurate measurement of gate drive requirements of a power MOSFET is the gate charge curve 160 shown in FIG. 3C. The graph illustrates a plot of the gate-to-source voltage VGS of the MOSFET versus the total gate charge QG needed to drive the gate to that voltage. Taking into account changing bias conditions, the aforementioned Miller effect, and non-linear capacitances, the gate charge measurement method is more useful than capacitance calculations in determining gate drive loss.
The gate charge curve is generated using a power MOSFET with its gate driven by a constant current source IG. To properly model the effect of gate to drain feedback, the MOSFET drives a load comprising a resistor or current-source powered from Vbatt. The device is characterized by starting with an off MOSFET and zero gate bias (point 161) and at a start time, but switching on the current source driving the MOSFET's gate. As the gate VGS voltage rises to its threshold and beyond, then at VGS(on) the transistor has adequate transconductance to carry the load current and the drain voltage begins to drop (curve 163).
During the dVDS/dt transition, the gate-to-drain capacitance CDG must be charged by equal and opposite charges coming from the drain and gate terminals. Since the constant gate current is charging CGD no charge is left over to charge the gate-to-source capacitor CGS, and as a result the gate potential becomes constant (curve 164). This plateau in gate voltage represents the charge needed to satisfy charge neutrality and quantitatively measures drain-to-gate feedback, i.e. the Miller effect over the entire transient. Once the drain voltage drops to semi-constant value, the MOSFET enters its linear region where VDS=ID·RDS1 and the gate voltage VGS resumes its upward transition.
Since the gate current in the measurement is a constant magnitude IG, the abscissa of graph 160 can be changed from time "t" to gate-charge QG by the linear relationship QG=IG·t. As shown in graph 160, the drain voltage VDS(t) and gate voltage VGS(t) can then be plotted against gate charge. As illustrated there is a unique and specific amount of gate charge QG needed to drive the gate to a specific gate voltage 162 and drain voltage 165. Since charge is conserved, the shape of the graph doesn't depend on the speed by which the measurement was made. If the IG is increased, the time t is decreased by in proportion and graph 160 remains unchanged.
The effective input capacitance of the power MOSFET switching between "off" with gate voltage VGSα=0 and "fully-on" with the gate at potential VGSβ is given by
      C    eq    =                    Δ                                                  Q                    Δ                                                  V              =                  Q                  G                                                              β                            V                  GS                                                              β                    where QGβ is the sum of all the charges required for the MOSFET to transition from off to on, i.e. QG(on), then through its saturation region ΔQDG and into its linear region by an amount ΔQD(lin), or as
      C    eq    =                    Q                  G                                                              β                            V                  GS                                                              β                      =                                        Q            G                                          (            on            )                          +                  Δ                                                                          Q            DG                          +                  Δ                                                                                Q              G                                                  (              lin              )                                                  V                  GS                                                              β
Since charge is conserved, the equivalent capacitance Ceq to drive the MOSFET's gate to a voltage VGSβ is path independent, meaning that the power needed to bias the device to a fully on condition is independent of the drive technique. Gate-drive power loss is however dependent on the drain bias Vbatt, which determines the width of the plateau ΔQDG. The higher the Vbatt voltage is, the larger the magnitude of VDS and the wider the gate plateau ΔQDG.
In essence, ΔQDG plateau (curve 164) in graph 160 represents the small-signal Miller feedback effect on input capacitance as measured in a large scale MOSFET switching transient, and accurately accounts for the total energy lost in the transient. Even if a voltage source is used to power the gate during switching, the energy and power losses remain the same. Only by minimizing the drain voltage transition causing the ΔQDG can the losses be reduced in any given power MOSFET. Unfortunately since Vbatt is the input to a DC/DC converter, it is not available as a variable to control gate drive losses.
Actual power loss depends on the relative relationship of the interval of switching losses with respect to the overall period. The primary losses, however, comprise I2·RDS conduction losses and QG·VG gate drive losses as given byPloss≈Pconduction+Pgate-drive=I2RDS1D+QG·VG·f
In a DC/DC converter, the duty factor D is controlled by feedback to maintain a fixed output-to-input conversion ratio. For a fixed voltage input voltage, output voltage and load current, only frequency determines the weighting of these two loss components. At low frequencies gate drive losses dominate. At high frequencies switching losses dominate.
Worse yet, MOSFET device operation requires an unavoidable tradeoff between these losses. This intrinsic tradeoff can best be understood by converting graph 160 into graph 170 by swapping the ordinate and abscissa axes as shown in FIG. 3D. As shown, the QG gate charge curve includes off portion 161, saturation portion 164, and linear region 162 just as in graph 160 where QG increases proportionally with increasing VGS. On the same graph 170, RDS on-resistance curve exhibits a hyperbolic dependence on gate drive, declining with increasing bias. At the edge of saturation, the on-resistance RDS declines rapidly (curve 171) into linear operation (curve 172) and reaches a minimum value (curve 173) at approximately a gate bias of VGSβ.
The tradeoff of on-resistance and gate-charge is illustrated by their product QG·RDS, shown by the dashed curve in graph 160. Since both terms contribute to loss, minimizing the QG·RDS product represents the maximum converter efficiency and minimum power loss. In region 174, the QG·RDS product declines because on-resistance 171 is dropping. In region 176 the QG·RDS product increases because QG is increasing. In between an optimum bias condition 175 exists where the QG·RDS product is minimized. In a real converter, the VGS cannot be maintained at this optimum condition since VGS varies with the battery input voltage. In essence, the QG·RDS product is a figure-of-merit for a given technology and device design.
Without redesigning the device and process, the only means to reduce the gate drive loss in its operation is to limit the maximum VDS during device operation. Unfortunately, the Buck and synchronous Buck converters impose the full battery input voltage Vbatt across the high-side MOSFET during switching, maximizing ΔQDG and the associated gate drive losses.
In contrast, the synchronous rectifier MOSFET does not change between conducting and non-conducting states with any significant drain bias, so its gate drives losses are not aggravated by the Miller effect and an excessive ΔQDG plateau.
Problems with Buck Converters
As shown above, a Buck converter exhibits poor efficiencies and excessive heating because of power dissipation in its rectifier. Schottky diodes suffer from excessive leakage and the risk of thermal runaway. Synchronous rectification eliminates the rectifier conduction losses and heating problems in conventional non-synchronous Buck converters, but cannot eliminate all the problems of a Buck converter.
Break-before-make operation, for example, needed to prevent shoot-through conduction in the high-side and low-side power MOSFETs, requires a dead time when both devices are momentarily off. During that interval, a P-N diode parallel to the synchronous rectifier MOSFET must carry the full inductor current and in so doing store charge. This stored charge leads to forced diode recovery causing a current path across the converter's input, and causes high dV/dt slew rates, voltage over-shoot, oscillations and noise—the same as in a non-synchronous Buck converter.
Moreover, eliminating the diode is not an option. Circuit 200 of FIG. 4A illustrates a Buck converter with the rectifier diode removed, comprising a high-side MOSFET 202 with an intrinsic parallel diode 205, an inductor 203 and an output capacitor 204. Unlike in a Buck or synchronous Buck converter, no diode is present between the node Vx and ground. The resulting switching waveforms of operating circuit 200 are shown in graph 210 of FIG. 4B where once MOSFET 202 is turned on, the drain and inductor currents ramp linearly 211 while the voltage across MOSFET 202 is only IL(t)·RDS(on), meaning Vx≈Vbatt, as shown by curve 215.
At a time t1, when MOSFET 202 is turned off, VX immediately exhibits a negative going voltage transient (curve 216) in order to maintain a constant inductor current (point 212). With no rectifier, the voltage at node Vx goes negative, below ground, without limitation until the VDS1 across off-state MOSFET 202 exceeds the avalanche breakdown BVDSS1 of diode 205, driving it into breakdown. The negative Vx voltage overshoots and rings slightly (curve 217) until it settles at a voltage Vx=(Vbatt−BVDSS1). If MOSFET 202 is fragile, i.e. not robust, it will immediately exhibit snapback I-V characteristics and destroy itself. If MOSFET 202 is robust, it will sustain the breakdown voltage BVDSS1 until the current ramps down to zero (curve 213) at time t2, when MOSFET 202 ceases conduction At that time, inductor 203 behaves like a wire, not a current source and Vx jumps up from point 218 to the capacitor voltage Vout as shown by curve 219.
Such a device is referred to as a rugged power MOSFET. Rugged MOSFETs are rated by the magnitude of energy Ej they can absorb before the silicon semiconductor or conductor materials in the MOSFET melt from overheating. A thermal failure is not considered a failure of ruggedness. Power device operation in this manner is known as unclamped inductive switching, or UIS, and is common in many solenoid and motor drives used in automotive applications. Because energy is dumped from inductor 203 into diode 205, UIS operation has very poor energy efficiency. So removing the rectifier diode from Buck converter is not a viable option.
Unfortunately leaving the rectifier diode in also creates problems, especially under light load conditions where it causes the inductor current to become intermittent. This phenomenon is illustrated in graph 225 of FIG. 5A. For a Buck converter operating at a high currents IL(high) the inductor current alternates in successive upward and downward ramps reaching a maximum current (point 227) and a minimum (point 226) both well above zero. At lower inductor currents IL(mid) the peak current (point 229) is well above zero but the minimum value (point 228) approaches zero.
Any inductor current IL below this minimum value causes the inductor current to become discontinuous. In such cases the inductor current has a positive peak current (point 231) but has a minimum value truncated to zero at points 230 and 232, the diode conduction time now being limited to a small percentage of the total period T and essentially conducting at a different frequency and duty factor than the off-time of MOSFET 236. Discontinuous conduction increases ripple and noise in the converter's output.
In a synchronous Buck converter operating in light load such as circuit 235 of FIG. 5B, care must also be taken to turn off low-side MOSFET 237 before the current reaches zero and IL reverses polarity. If the synchronous rectifier MOSFET remains on too long, the inductor current will reverse direction as shown by curve 233. A current reversal means current in inductor 239 will flow backwards from the load 242 and into the regulator, moving energy in the wrong direction away from load 241 and output capacitor 240 and into converter circuitry, during which efficiency suffers.
Circuit 235 will therefore oscillate with current IL(forward) flowing in part of the cycle and IL(reverse) flowing for the rest. Some electrical loads 241 do not operate properly under AC conditions. But sensing and shutting of synchronous rectifier MOSFET 237 is problematic because of noise on Vx and because there is no easy way to accurately measure low magnitude currents in inductor 239. If MOSFET 237 is shut off too late, the inductor current reverses and energy is lost. If it is shut off prematurely, diode 238 has to carry current for a longer time and stores more charge. It also exhibits oscillations at the time the synchronous rectifier is shut off, lowering efficiency and generating noise.
Moreover, at very light loads the high side MOSFET's on-time becomes so short the entire converter is forced to operate at a variable frequency with almost no inductor current flowing, i.e. nearly off. Being nearly off makes it difficult to react to sudden changes in the load current and can lead to poor transient regulation, especially in light load operation.

Step-down switching regulator with freewheeling diode


A battery includes a housing having a plurality of cell vessels and a plurality of positive and negative electrode plates provided within the cell vessels. The battery also includes a lower cover configured to close the cell vessels with a seal, the lower cover having openings for the cell vessels. The battery further includes a degassing channel system which is coupled to the lower cover by at least one member, the openings of the lower cover opening into the degassing channel system. Annular projections are integrally formed on each of the openings of the lower cover adjacent to the lower cover, and the at least one member is configured to couple the degassing channel system to the lower cover such that the projections seal the openings to the degassing channel system by surface pressure.

The present invention relates to accumulators or batteries (i.e., lead-acid starting, lighting, and ignition batteries), and more particularly to the construction of such accumulators or batteries. For purposes of the present disclosure, the term "accumulator" and "battery" will be used interchangeably.
Gas is developed during operation of accumulators, and must be dissipated in the cell vessels. Upward openings are provided in the cell vessels for this purpose, and open into a degassing chamber system. The degassing chamber system branches off by means of a multiplicity of deflection webs so as to form a labyrinth for electrolyte liquid which can slosh into the cavity through the openings from the cell vessels. Electrolyte is also torn away in the gas flow and can strike the deflection webs, where it condenses. In this case, the degassing channel system is inclined such that the electrolyte liquid can flow back again into the cell vessel.
DE 1 901 356 discloses a multicell accumulator having a continuous covering strip which closes the filling openings and, when fitted, releases degassing openings for the individual cells. A movable tubular part is arranged in each filling opening, is moved in the direction of the cell interior when the covering strip is fitted, and releases at least one degassing opening. The movable tubular part latches in an upper limit position when the covering strip is lifted off, and in the process seals the degassing opening. The seal is in this case provided on conical sealing surfaces on the tubular section.
EP 1 017 119 A1 discloses an accumulator in which filling openings in a lower cover of a battery cell vessel are sealed by a degassing channel element which is fitted to the lower cover and has tubular pieces with degassing valves for insertion into the openings. The tubular pieces are locked by means of spring latching hooks, which lock with the opening wall in the cell interior. The opening is in this case sealed radially with the aid of a push fit of the tubular pieces which project into the openings.
U.S. Pat. No. 4,348,466 discloses an accumulator in which a gassing channel system is fitted to the lower cover, which has openings to the cell vessels. Once again, the tubular degassing valves which project into the opening are sealed radially, but with the aid of sealing rings which are circumferential on the outer wall of the tubular pieces.
U.S. Pat. No. 3,597,280 also discloses an accumulator with a degassing channel system fitted, in which the degassing channel system is plugged onto the cell vessels with the aid of valve plugs which project into the opening. The degassing channel system is sealed and fixed to the cell vessels by a push fit between the valve plugs and the openings. One problem with these conventional accumulators is the sealing of the openings in the lower cover to the degassing channel system, as a result of manufacturing tolerances.

Battery having a cover and a degassing channel system sealed with annular projections and sealing elements


This method for installing avionics software applications on a platform with a multi-core processor and intended to be on board an aircraft is implemented by an electronic installation device. Each avionics software application includes one or several software processing operations to be executed over a predefined time period including one or several successive time clusters.

Using multi-core processors creates substantial difficulty for the qualification of the platforms. Indeed, running several software applications at the same time on one multi-core processor creates risks of contention due to the sharing of common resources (bus, memory) with different cores, the behavior of the multi-core processor not being able to be controlled easily.
The term "contention" refers to any situation in which at least one activity carried out by at least one core of a multi-core processor experiences delays in its performance due to the temporal parallelism allowed by said multi-core processor.
The origin of the contentions is generally the use of shared resources of the processor or the operating system, also called OS, resulting in waits causing these delays. A contention then causes a delay in the execution of a software application hosted in a core.
A first example of contention is the bus (often called "interconnect") connecting the cores to one another, which does not always allow simultaneous transactions between cores or between the cores and the peripherals, such as certain integrated cache memories or the external memory.
Another example of contention is the use of common software modules of the OS installed on one of the cores and called by all of the cores, potentially at the same time. Simultaneous calls for such shared software modules lead to arbitration and the placement of some requests in standby in order to serialize the software processing operations on the core where the shared software module is installed.
Another example of contention is a temporary interruption of all of the cores on a particular event on one of the cores in order to manage a coherent status among all of the cores.
When the processor is further a processor purchased from a supplier, or a COTS (Commercial Off-The-Shelf) processor, it is generally impossible to access the design details of the internal members of such a multi-core processor, and it is therefore very difficult, if not impossible, to guarantee a deterministic behavior of the processor.
According to a first known type of software architecture for a platform with a multi-core processor, also called SMP (Symmetrical Multi-Processing) architecture, an operating system decides at each moment which software processing operation is executed on which core.
According to a second known type of software architecture for a platform with a multi-core processor, also called AMP (Asymmetrical Multi-Processing) architecture, each core sequences the execution of a set of software applications, independently from one core to the next, with one operating system per core.
However, such architectures are not robust enough to obtain the qualification of platforms with multi-core processors, in particular in the avionics field according to standard DO297.

Method and electronic device for installing avionics software applications on a platform comprising a multi-core processor, related computer program and electronic system

Abstract: It comprises determining an installation plan for the software processing operations according to a first installation rule and/or a second installation rule, the installation plan defining, for each software processing operation, at least one core and at least one time cluster that are associated with said software processing operation, the first rule consisting of predetermining a list of authorized combinations of criticality levels for applications intended to be executed during a same time cluster, and the second rule consisting of prohibiting installation of critical software application(s) on one or several cores of the plurality of cores.


An arteriosclerosis-degree evaluating apparatus, including a blood-pressure measuring device which iteratively measures a blood pressure value of a living subject, a pulse-wave-propagation-velocity-related-information obtaining device which iteratively obtains, at substantially a same time as a time when the blood-pressure measuring device measures each blood pressure value of the living subject, a piece of pulse-wave-propagation-velocity-related information that is related to a velocity at which a pulse wave propagates through an artery of the subject, and an output device which outputs a change of the pieces of pulse-wave-propagation-velocity-related information iteratively obtained by the pulse-wave-propagation-velocity-related-information obtaining device, relative to a change of the blood pressure values iteratively measured by the blood-pressure measuring device.

1. Field of the Invention
The present invention relates to an arteriosclerosis-degree evaluating apparatus for evaluating an arteriosclerosis degree of a living subject, based on pulse-wave-propagation-velocity-related information that is related to a velocity at which a pulse wave propagates through an artery of the subject; such as a pulse-wave propagation velocity itself, or a pulse-wave propagation time, and particularly relates to an arteriosclerosis-degree evaluating apparatus for evaluating an arteriosclerosis degree based on a change of pulse-wave-propagation-velocity-related information relative to a change of blood pressure.
2. Related Art Statement
The harder a blood vessel is, the faster a pulse wave propagates through the blood vessel. It is therefore known that arteriosclerosis can be diagnosed based on information related to a velocity at which a pulse wave propagates through an artery. It is also known that pulse-wave-propagation-velocity-related information is influenced by blood pressure. For example, it is known that the higher the blood pressure is, the higher the pulse wave propagation velocity is, that is, the lower the blood pressure is, the lower the pulse wave propagation velocity is. Thus, Japanese Patent Document No. 2001-190506 discloses an arteriosclerosis evaluating device which obtains pulse-wave-propagation-velocity-related information, measures blood pressure, and can diagnose an arteriosclerosis degree based on both the obtained information and the measured blood pressure.
However, recently, it has been elucidated that there are cases where though blood pressure changes, pulse-wave propagation velocity does not change so much and, in those very cases, arteriosclerosis has advanced and patents"" life expectancy is short. In those cases where pulse-wave propagation velocity does not change so much with blood pressure, it can be said that pulse-wave propagation velocity is so strongly influenced by arteriosclerosis. Thus, it can be said that even if pulse-wave propagation velocity is high and blood pressure is also high, arteriosclerosis has not advanced so much if the velocity lowers as the blood pressure lowers, and that it has advanced if the velocity does not lower so much as the blood pressure lowers.
However, conventionally, the cases where change of pulse-wave propagation velocity relative to change of blood pressure is known have been limited to few cases, e.g., cases where when antihypertensive drug is administered to patients, blood pressure and pulse-wave propagation velocity are measured before and after the administration so as to observe the therapeutic effect of the drug. Even in those cases, a long time is needed before the therapeutic effect appears. Thus, detecting change of pulse-wave propagation velocity relative to change of blood pressure needs a long time.
It is therefore an object of the present invention to provide an arteriosclerosis-degree evaluating apparatus which can quickly detect change of pulse-wave propagation velocity relative to change of blood pressure.
The above object has been achieved by the present invention. According to the present invention, there is provided an arteriosclerosis-degree evaluating apparatus, comprising a blood-pressure measuring device which iteratively measures a blood pressure value of a living subject; a pulse-wave-propagation-velocity-related-information obtaining device which iteratively obtains, at substantially a same time as a time when the blood-pressure measuring device measures each blood pressure value of the living subject, a piece of pulse-wave-propagation-velocity-related information that is related to a velocity at which a pulse wave propagates through an artery of the subject; and an output device which outputs a change of the pieces of pulse-wave-propagation-velocity-related information iteratively obtained by the pulse-wave-propagation-velocity-related-information obtaining device, relative to a change of the blood pressure values iteratively measured by the blood-pressure measuring device.
The arteriosclerosis-degree evaluating apparatus according to the present invention may be used with a patient whose blood pressure is increasing, e.g., because a physical load is being applied to the patient, or a patient whose blood pressure is decreasing, e.g., because the patient is resting after a physical load has been applied. The blood-pressure measuring device iteratively measures a blood pressure value of the patient, the pulse-wave-propagation-velocity-related-information obtaining device iteratively obtains, at substantially the same time as the time when the blood-pressure measuring device measures each blood pressure value of the patient, a piece of pulse-wave-propagation-velocity-related information, and the output device outputs a change of the pieces of pulse-wave-propagation-velocity-related information iteratively obtained, relative to a change of the blood pressure values iteratively measured. Thus, the present apparatus can quickly detect the change of the pieces of pulse-wave-propagation-velocity-related information, relative to the change of the blood pressure values.
Preferably, the blood-pressure measuring device comprises an inflatable cuff which is adapted to be worn on a portion of the subject; a blood-pressure-value determining means for determining the blood pressure value of the subject based on a signal obtained while a pressure in the cuff is changed; a pressure-pulse-wave detecting device which includes a pressure-pulse-wave sensor that is adapted to be pressed against a prescribed artery of the subject, and which continuously detects, through the pressure-pulse-wave sensor, a pressure pulse wave produced from the prescribed artery; a relationship determining means for determining a relationship between magnitude of pressure pulse wave, and blood pressure, based on at least one blood pressure value measured by the blood-pressure-value determining means and at least one magnitude of the pressure pulse wave detected by the pressure-pulse-wave detecting device; and a blood-pressure monitoring means for iteratively determining, according to the determined relationship, a monitor blood pressure value of the subject, based on a magnitude of each of heartbeat-synchronous pulses of the pressure pulse wave continuously detected by the pressure-pulse-wave detecting device, wherein the pulse-wave-propagation-velocity-related-information obtaining device iteratively obtains a piece of pulse-wave-propagation-velocity-related information at substantially a same time as a time when the blood-pressure monitoring means determines each monitor blood pressure value of the living subject, and wherein the output device outputs a change of the pieces of pulse-wave-propagation-velocity-related information iteratively obtained by the pulse-wave-propagation-velocity-related-information obtaining device, relative to a change of the monitor blood pressure values iteratively determined by the blood-pressure monitoring device.
When the present arteriosclerosis-degree evaluating apparatus is used with a patient whose blood pressure is increasing, or a patient whose blood pressure is decreasing, the blood-pressure monitoring means iteratively determines a monitor blood pressure value of the patient, the pulse-wave-propagation-velocity-related-information obtaining device iteratively obtains a piece of pulse-wave-propagation-velocity-related information at substantially a same time as a time when the blood-pressure monitoring means determines each monitor blood pressure value of the patient, and the output device outputs a change of the pieces of pulse-wave-propagation-velocity-related information iteratively obtained relative to a change of the monitor blood pressure values iteratively determined. Thus, the present apparatus can detect, in more detail, the change of the pieces of pulse-wave-propagation-velocity-related information relative to the change of the monitor blood pressure values, as compared with the case where blood pressure values are iteratively measured using a cuff.
Preferably, the output device displays, in a two-dimensional graph defined by an axis indicative of blood pressure and an axis of pulse-wave propagation velocity, a symbol at a position corresponding to each of the blood pressure values iteratively measured by the blood-pressure measuring device and a corresponding one of the pieces of pulse-wave-propagation-velocity-related information iteratively obtained by the pulse-wave-propagation-velocity-related-information obtaining device.
According to this feature, a medical person such as a doctor or a nurse can visually and easily recognize a change of pulse-wave-propagation-velocity-related information relative to a change of blood pressure, in each of a plurality of time periods; such as a change of pulse-wave-propagation-velocity-related information relative to an initial change of blood pressure, an overall tendency of change of pulse-wave-propagation-velocity-related information relative to change of blood pressure, or a change of pulse-wave-propagation-velocity-related information relative to a terminal change of blood pressure.
Preferably, the pulse-wave-propagation-velocity-related-information obtaining device iteratively obtains the piece of pulse-wave-propagation-velocity-related information that is related to the velocity at which the pulse wave propagates through the artery including an aorta of the subject.
According to this feature, the output device outputs a change of the pieces of pulse-wave-propagation-velocity-related information related to the artery including the aorta, relative to a change of the blood pressure values iteratively measured. The pulse-wave-propagation-velocity-related information related to the artery including the aorta provides an excellent predictive indicator about cardiovascular diseases. Thus, based on the change of pulse-wave-propagation-velocity-related information related to the artery including the aorta, relative to the change of blood pressure values, a medical person can make an accurate diagnosis about the risk of cardiovascular disease.
It is another object of the present invention to provide an arteriosclerosis-degree diagnosing method comprising the step of iteratively obtaining a piece of pulse-wave-propagation-velocity-related information from a patient whose blood pressure is increasing because a prescribed physical load is being applied to the patient, or a patient whose blood pressure is decreasing because the patient is resting after a prescribed physical load has been applied, and the step of diagnosing an arteriosclerosis degree of the patient based on a change of the pieces of pulse-wave-propagation-velocity-related information iteratively obtained.
According to this method, the blood pressure of the patient is changed by applying the physical load to the patient, and the pieces of pulse-wave-propagation-velocity-related information are iteratively obtained from the patient whose blood pressure is increasing because of the physical load, or the patient whose blood pressure is decreasing after the physical load. Thus, a change of the pieces of pulse-wave-propagation-velocity-related information relative to a change of blood pressure can be quickly detected.


There is provided an electric power applying circuit for applying a direct current power to a load. The electric power applying circuit includes an output buffer that (i) is supplied with, as power source voltages, positive and negative high voltages which are determined in accordance with a range of an applied voltage which is to be applied to the load, (ii) generates a voltage in accordance with an input voltage, within a range defined by the power source voltages, and (iii) applies the generated voltage to the load, a main amplifier that amplifies a voltage input thereto to generate the input voltage, and inputs the generated input voltage into the output buffer, wherein the main amplifier exhibits a higher accuracy in terms of voltage generation than the output buffer, and a floating power source that generates positive and negative floating voltages by using, as a reference, a voltage determined in accordance with a voltage output from the output buffer, and supplies the generated positive and negative floating voltages to the main amplifier as power source voltages thereof, wherein a difference in voltage between the positive and negative floating voltages is smaller than a difference in voltage between the positive and negative high voltages.

1. Technical Field
The present invention relates to an electric power applying circuit for supplying power to a load, and a test apparatus for testing a device under test (DUT). More particularly, the present invention relates to an electric power applying circuit for supplying a direct current (DC) power to a load and a test apparatus for conducting a DC test on a DUT.
2. Related Art
It is known that a device under test (DUT) such as a semiconductor circuit is tested by way of direct current (DC) tests according to which, for example, a voltage is applied and a resultant current is measured, and a current is applied and a resultant voltage is measured. In the case of a test in which a voltage is applied and a resultant current is measured, for example, while applying a predetermined DC voltage to the DUT, a test apparatus detects a DC current flowing within the DUT when the DUT is operating or not operating. When the detected DC current does not fall within a predetermined range, the test apparatus judges the DUT to be defective.
A conventionally known circuit for supplying a DC power to a DUT is constituted by using an amplifier, for example, as disclosed in Unexamined Japanese Patent Application Publication No. H05-119110. The amplifier amplifies an input voltage, and applies the amplified voltage to the DUT.
To apply, to the DUT, a voltage whose voltage value is high and highly accurately controlled, the circuit needs to be constituted by using a high-accuracy and high-voltage amplifier. Such an amplifier is expensive, thereby increasing the cost of the circuit.
As disclosed in Patent Document 1, for example, a voltage-applying/current-measuring circuit is known which applies a constant voltage to a DUT and measures a current supplied to the DUT. When the voltage-applying/current-measuring circuit applies a high voltage to the DUT, each of the elements constituting the circuit needs to be formed by using a high-accuracy and high-voltage element.
Even when a floating power source is used to supply power source voltages to some of the elements constituting the circuit as disclosed in FIG. 1 of Patent Document 1, constituents such as a main amplifier 13, a differential amplifier 21, and a resistor 25 need to be configured by using high-accuracy and high-voltage elements. This increases the cost of the circuit. Furthermore, since the floating power source is used for some of the elements constituting the circuit, the circuit has a complex configuration, which also contributes to an increase in the cost of the circuit.
In view of the above, an advantage of some embodiments of the present invention is to provide an electric power applying circuit and a test apparatus which can solve the above-described problems. This advantage is achieved by combining the features recited in the independent claims. The dependent claims define further effective specific example of the present invention.

Electric power applying circuit and test apparatus


The present invention relates to modifying agents for melamine-formaldehyde resins and highly reactive thermosetting resins which are prepared with this agent and consist of 1 mol of melamine, 1.5 to 3.5 mol of formaldehyde, 0.5 to 5% by weight of a polyhydric alcohol, based on the melamine plus formaldehyde, and 0.5 to 10% by weight of the modifying agent, based on the liquid resin. The modifying agent can be added to the melamine-formaldehyde resin as a pulverulent mixture before or during the condensation reaction or in the liquid state in the form of a condensation product prepared in a known manner. The modifying agent consists of 10 to 75% by weight of dicyandiamide, 5 to 70% by weight of cold water-soluble starch (soluble between about 18.degree. and about 25.degree. C.) and 20 to 85% by weight of a guanamine. The highly reactive resins modified in this way are preferably used for coating chipboard and hardboard by a short cycle process.

1. Field of the Invention
The invention relates to modifying agents for melamine-formaldehyde resins, a highly reactive, modified thermosetting resin based on a melamine-formaldehyde condensation product and the use of the modifying agent for the preparation of thermosetting resins, laminates, and coated sheets.
2. Relevance of the Prior Art
Precondensed, aqueous or aqueous-alcoholic solutions of melamine-formaldehyde resins are known in the art to be outstandingly suitable for impregnation of absorbent carrier materials, such as, for example, paper webs or non-woven materials or fabrics, which are dried after the impregnation and finally processed to laminates (layered material) by hot pressing, or for improving the surface of derived timber products, for example hardboard or wood chipboard. Suitable resins are taught, for example, in U.S. Pat. No. 2,197,357 to Widmer et al issued Apr. 16, 1940.
Hard, scratch-resistant surface coatings which are resistant to water and chemicals are obtained using such melamine impregnating resins. Such properties are required, above all, in furniture construction.
The use of pure melamine resin for impregnating carrier materials meets with certain difficulties inasmuch as the pressing pressures must be very high and the pressing times must be relatively long. Resin films finished with such resins and pressed, for example, onto chipboard are moreover susceptible to cracking, especially after a relatively long storage time, which is why improvements have been sought in this respect. Possibilities for avoiding such difficulties are known in the art and resins suitable for particularly rapid curing and processing, known as short cycle resins, have been developed. These advancements may include the modification of melamine resins by replacing some of the melamine by other condensable products, such as urea or glycols. For example, GB 1 464 014 claims an impregnating resin based on an aqueous condensation product of melamine and formaldehyde that is characterized by the melamine replacing addition of saccharose or .alpha.-methylglycoside and 0.5 up to 7% by weight of the resin part in the solution of a diol with 2 to 4 carbon atoms, such as ethylenglycol, 1,3- and 1,2-propylenglycol or 1,2-, 1,3- or 1,4-butandiol.
Such modified resins have improved flow properties, but although useful surfaces have already been obtained with them under lower pressure and over shorter reaction times, their properties were not satisfactory in all respects. In particular, a more pronounced tendency to yellow at higher temperatures which are recommended if short reaction times are applied and a reduced gloss of the surfaces produced with such resins was apparent.

Modifying agents for thermosetting resins and thermosetting resins prepared using these agents


A method, a device, and a storage medium for certificate identification. The method may comprise: instructing a user to move a certificate according to a designated movement method within an imaging region of a camera of a terminal device; imaging the certificate in the imaging region to obtain a movement video of the certificate; extracting at least one key frame in the movement video; analyzing an image content of the at least one key frame according to a certificate identification method that corresponds to the designated movement method, to generate an analysis result of the image content; and determining, based on the analysis result, whether the certificate is a forged certificate.

Optical character recognition (OCR) of certificate characters is used extensively in identity verification scenarios, such as internet finance. OCR of certificate characters refers to processing, by the OCR technology, an image of a certificate provided by a user, in order to extract and identify the user information contained in the certificate, such as a user name, a date of birth, and an expiration date of the certificate. In a finance scenario, it is vitally important to identify any identity thefts or forgeries due to forged certificates. Behaviors of forging certificates by users in the black industry can be divided into two types, physical certificate forgery and electronic certificate forgery. Physical certificate forgery refers to alteration of certificate information directly on the physical entity of a certificate, including alteration of user identity information physically, for example, alteration of a name or date of birth by smearing, applying a physical patch, etc., direct fabrication of a certificate. Electronic certificate forgery refers to, forging information on the digitized image of the certificate obtained by digitization of a physical certificate by imaging, scanning, etc., for example, forging by Adobe Photoshop (PS) or any other image processing tool. Compared with physical certificate forgery, electronic certificate forgery has characteristics including easy access to forgery target since a certificate may be imaged directly without the need of a physical certificate, a low forgery cost, easy access to a forgery tool (i.e., Adobe Photoshop or any other image processing software), highly authentic, and prone to provoke batch attacks. Electronic services, such as internet finance, should focus on prevention from such forgeries.

Method and apparatus for certificate identification


A method is provided for reprocessing a petroleum-based waste oil feedstock into diesel fuel. The method includes forming a treated feedstock by (a) filtering the feedstock, thereby removing solids and metals from the feedstock, and (b) dehydrating the feedstock; vaporizing the treated feedstock to produce an oil vapor; passing the oil vapor through at least one catalyst bed and subsequently through a cooler, thereby converting the oil vapor to a hydrocarbon liquid product with a diesel product boiling point range; and removing contaminants from the hydrocarbon liquid product, wherein the contaminants are selected from the group consisting of particulates and color precursors.

Lubricating oil (or lube oil) is the highest value component of crude oil. More than half of the global supply of lubricating oil is consumed in the automotive industry, with a large portion of that being consumed as motor oil.
Conventional motor oil comprises nearly 80-90% base oils, with the balance being specialty additives. Oil additives are vital for the proper lubrication and prolonged use of motor oil in modern internal combustion engines. Without suitable additives, oil can become contaminated, break down, leak out, or provide insufficient protection to engine parts over some or all operating temperature ranges. Some of the more important motor oil additives are those which provide proper viscosity and lubricity, contaminant control, resistance to (or control of) chemical breakdown, and seal conditioning. Some additives are specifically designed to permit lubricants to perform better under severe conditions, such as those encountered at extreme pressures and temperatures or high levels of contamination.
The lubricating component in motor oil reduces friction and cools engine moving parts. It typically has a carbon content ranging from C20 to nearly C40, with an initial and end boiling point of approximately 350° C. and 500° C., respectively. During use in an engine, a portion of the motor oil may undergo deterioration due to oxidation and decomposition. Motor oil may also become 'spent' as it accumulates contaminants that interfere with the ability of the oil to adequately lubricate engine parts. Such contaminants may include, for example, sediments, sludge, dirt, shavings, heavy metals, water and engine combustion products.

Low-pressure catalytic conversion of used motor oil to diesel fuel


Methods and media for pre-mastering in preparation for recording data files to optical media are provided. In one example, a method for pre-mastering includes receiving a selection of data files to be recorded to an optical media and generating a database in which to list the selection. The database is populated with the selection of data files which are identified by file node and listed in alphabetical order by directory. The method provides for accessing a file in the database, verifying a source location of the accessed file, verifying an integrity of the accessed file, and determining a destination location for the accessed file. The determining of the destination location includes determining a logical block to which at least a portion of the accessed file is to be recorded on the optical media.

1. Field of the Invention
The present invention relates generally to the recording of data to optical media, and more particularly to a method for determining the target layout and which files to cache during the pre-mastering stage of optical media recording.
2. Description of the Related Art
When recording data to optical media, a user typically selects a plurality of files from a source or plurality of sources, identifies a target or destination optical media, and executes a recording function. The selected files can be of any type including audio files, video files, photographic files, data files, and the like. The recording function is typically executed by use of an optical media recording program which accomplishes such tasks as mapping out precise locations of source files, determining size of source files, mapping out a precise target destination for the selected files, calculating a theoretical transfer rate for reading the file from a source and recording the file to a destination, identifying those files that will be cached and those files that will be recorded directly from source to destination, performing necessary formatting as required, and burning the selected files to a destination optical media. Data can be recorded in one or more sessions to a single optical media.
During the pre-mastering stage in preparation for recording data files to optical media, selected files are typically sorted a plurality of times to achieve an optimum recording order that avoids buffer under-run, and that minimizes recording time when the actual burn operation is accomplished. The plurality of file sorts is usually intended to maximize efficient use of available resources by establishing a writing order that matches system resources and specifications such as transfer rate, buffer size, read speed for source location, target optical media device write speed, available system cache, and the like.
While the plurality of file sorts remains a viable and efficient use of system resources for a user wishing to record a relatively small or limited number of data files to optical media, as the number of files selected for recording increases, the system processing time required to accomplish the plurality of sorts for an increasing number of files, as well as for an increasing number of file sorts as a result of the increasing number of files, increases significantly. A large number of files, e.g., 20,000–50,000 files, depending on size, can take up to four minutes of processing time, plus an additional approximately five minutes to perform a system test used to calculate an average file transfer rate. For users recording large numbers of data files, it is desirable that the processing time prior to recording be minimized, as should the recording time to record the selected files.
As is known, when files are recorded to optical media, the files are read from a source location, from a plurality of source locations, or a system cache into a buffer of a recording device. A file system for the destination optical media is created, and the files are then written to the destination or target optical media from the optical media recording device buffer, along with required file system and other data structures in order to comply with accepted data formats and specifications. In typical prior art programs, the filling and depletion of the buffer, file size, optical media device read and write speeds, and other factors were all considered during the plurality of file sorts to maximize efficient utilization of system resources and avoid buffer under-run. Typical optical media recording devices now have sufficient buffer under-run protection resident in the recording device to make much of the plurality of file sorts unnecessary.
In view of the foregoing, what is needed is a method of recording data to optical media that avoids excessive consumption of system processing time, and maximizes efficient use of available recording resources while avoiding the problems of the prior art.

Pre-mastering for optical media recording