The invention relates to a method for protecting data during a self-test of a microcontrollers, in which all of the circuit elements within the microcontroller can be tested, where the course of the self-test cannot be altered via the external pins, and no intermediate results are passed to the outside via the pins. The invention also relates to an configuration in the form of an integrated circuit which can be used to implement the method, and to correspondingly equipped microcontrollers.

The invention relates to a method and a configuration for protecting data during a self-test of a microcontroller. The configuration is in the form of an integrated circuit.
For the manufacture of integrated circuits (ICs), the production test is an aspect that plays a crucial part in the overall determination of the quality. Normally, the production test is performed by stimulating the integrated circuits on a test system using a multiplicity of test patterns on the input pins of the ICs, measuring the test responses on the output pins of the ICs, and comparing them with the nominal values stored in the test system.
This presents a problem for a particular class of ICs, the xe2x80x9csecurity ICsxe2x80x9d, as are used for data encryption or for the hardware-based protection of transfer protocols, for example. In the case of these ICs, configuration and operation are subject to certain security requirements thatxe2x80x94couched in simple termsxe2x80x94require that the internal circuit elements of the IC must not be able to be accessed by unauthorized parties via the pins of the IC. For this reason, the test method outlined cannot be applied in this instance, since knowledge and storage of input data and of the associated nominal output data in a test system or a PC, for example, would allow the configuration and operation of the IC to be inferred. Nevertheless, a suitable production test needs to be conducted for this class of ICs too.
To solve this problem, self-tests (BIST, Built-In Self-Test) have been developed. A self-test normally requires only a start signal to be specified; after a prescribed time, the test response conditioned in the IC can then be read out. Since this test response contains the compression of a large number of individual test results to form a single data record, it is generally not possible for the configuration and operation of the IC to be inferred from this test response.
To implement a self-test, two different approaches can be distinguished for microcontrollers: A self-test containing the execution of a test program stored in the microcontroller itself; and a self-test such as described in IEEE standard 1149.1 xe2x80x9cStandard Test Access Port and Boundary-Scan Architecturexe2x80x9d under the term xe2x80x9cRUNBISTxe2x80x9d as an optional function.
The fundamental advantage of a self-test using a test program stored in the microcontroller itself is that the test program can check the authorization to perform the self-test in a variety of ways before the actual test is performed. This can be done, inter alia, by the external input of a password that is compared with a nominal value stored in the microcontroller, the self-test being started only if the result of the check is positive.
However, the approach using a test program stored in the microcontroller itself generally has substantial drawbacks. One drawback is that software cannot stimulate or observe all of the circuit elements within the microcontroller. The result of this is that the quality of the production test is not sufficiently high. Also, the additionally integrated memory required for the test instructions increases the chip area. Another drawback is that the execution of a test programxe2x80x94as compared with a normal test using a test machinexe2x80x94is generally at least ten times slower.
The approach via the self-test using the boundary scan described in IEEE standard 1149.1, for example, generally solves the problem of the accessibility of internal circuit nodes, since in this case all of the inputs and outputs of the IC are involved in the generation of test patterns and test responses. However, this self-test satisfies only minor security requirements, because the generation of test patterns takes place internally but the test responses are emitted serially by the boundary scan, and the flow control of the self-test by the standardized TAP controller can be altered from the outside at any time. Thus, a xe2x80x9chackerxe2x80x9d could misuse this self-test in order to access secrets in the chip. To do so, he would repeat the self-test as often as desired, but would constantly and systematically vary the duration of the self-test by the number of clock cycles which keeps the system in the xe2x80x9cRun-Test/Idlexe2x80x9d state and would infer the chip content from the results which are then read out in each case. The control signals needed for this are freely accessible externally in line with the IEEE standard, and there is no kind of protection against such xe2x80x9cspyingxe2x80x9d.
It is accordingly an object of the invention to provide a method and configuration for protecting data during a self-test of a microcontroller that overcomes the hereinaforementioned disadvantages of the heretofore-known devices of this general type and that allow a full and fast self-test that is protected against hacking attempts.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for protecting data while self-testing a microcontroller and testing circuit elements within the microcontroller, a course of the self-test not being alterable via an external pin, and no intermediate results being passed to the outside. The method includes the step of providing the microcontroller with a boundary scan having registers. The next step is storing a built-in self-test (BIST) in the microcontroller. The next step is generating test patterns within the microcontroller with the BIST by using the registers of the boundary scan.
With the objects of the invention in view, there is also provided an integrated circuit configuration for protecting data during a self-test for a microcontroller including devices for starting the self-test and for performing the self-test internally. The self-test covers all fundamental elements of the microcontroller and outputs a corresponding test response. The configuration includes devices for storing a self-test program. In addition, the configuration includes devices for isolating external input and output devices from the devices for performing the self-test throughout execution of the self-test.
Accordingly, the microcontroller has a boundary scan, preferably in line with IEEE standard 1149.1. However, only the obligatory test instructions listed in the IEEE standard are implemented, as are provided for the production test on a printed circuit board (and not on the IC), in line with the intention of the boundary scan.
The BIST now uses the registers of the boundary scan in order to generate pseudo-random test patterns within the chip and to compress test responses. Since the boundary scan register encompasses the entire logic of the chip as far as the input and output cells, it is optimally suited to reaching a maximum number of internal circuit nodes using the self-test, which is in turn a prerequisite for the greatest possible fault coverage and hence quality of the production test.
In accordance with the invention, this BIST is not started directly from the outside (e.g. by the instruction xe2x80x9cRUNBISTxe2x80x9d, as indicated in the IEEE standard), however, but rather with the microcontroller. Beforehand, the microcontroller checks the authorization to perform the self-test. During the self-test, the microcontroller monitors correct execution of the self-test, which includes not allowing the self-test to be interrupted. This also includes not accepting any test instructions during the BIST using the boundary scan (in line with the IEEE standard), that is to say the TAP controller indicated in the IEEE standard is thus decoupled from the boundary scan cells by using logic. At the end of the test, the compressed test response can either be output by the microcontroller or can be compared with a nominal response stored in a read only memory in the microcontroller.
Thus, in principle, the invention combines the two known approaches and the associated logic sequence while preserving the advantages. First, the test program integrated in the microcontroller checks the authorization to execute the self-test. If this condition is satisfied, the test program starts the self-test by decoupling the TAP controller""s control signals from the boundary scan register by using logic, putting the test logic into a defined initial state and starting the self-test. At the end of the test, the test program reads the test response stored in the boundary scan register into an internal memory and then erases the test response in the boundary scan register. The TAP controller is then enabled again. The test response stored in the microcontroller can now be compared with a nominal response stored in the test program or can be output to the outside, depending on implementation.
This procedure ensures that only authorized parties can execute the self-test, that the course of the self-test cannot be altered via the external pins, and that no intermediate results are passed to the outside via the pins. Despite this, a fast full self-test covering all of the elements of the microprocessor is made possible.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and a configuration for protecting data during a self-test of a microcontroller, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

Method and configuration for protecting data during a self-test of a microcontroller


A circuit recloser that limits current through a power line when a fault condition occurs. The recloser includes a circuit interrupter that is switchable between a closed state, in which current is permitted to flow through the power line, and an open state, in which the current is interrupted. The interrupter switches to its open state in response to a fault condition, such as a current surge. The recloser also has a movable member that is operatively coupled to the interrupter for resetting the interrupter to the closed state from the open state when the movable member is moved. The movable member is configured for being remotely movable to close the interrupter. Preferably the recloser includes an electric drive to remotely move the movable member from a remote station, and a projection extends from the movable member to enable manual movement thereof. The movable member includes a shaft which the electric drive rotates by turning a slotted hub coaxially about the shaft. When hub rotates, ends of slots in the hub contact a drive pin that extends radially from the shaft. The slots allow manual rotation of the shaft without damaging the electric drive. Microswitches sense the position of the hub during its rotation.

Electric power distribution lines are occasionally subjected to lightning strikes or grounding. Lightning strikes and groundings result in a sudden surge of electric current through the power lines. These sudden current surges may damage transformers, power lines and other related equipment in the electric power distribution grid. Since sudden surges of current, caused by lightning strikes or grounded power lines, usually last for only a fraction of a second, standard circuit breakers cannot be used to limit the current on the distribution lines because they shall keep the circuit open even though the fault condition has passed. Automatic circuit breakers, referred to as reclosers, are used in place of standard circuit breakers for protecting transmission lines against current surges.
Reclosers are designed to open a circuit when a current surge is sensed and then reclose the circuit within a few moments. When a recloser device is used to limit current flow through electric power lines, sudden current flows resulting from a lightning strike or a downed power line causes contacts within the recloser to separate, thereby opening the circuit and limiting the current flow. After opening the circuit, the recloser is designed to wait an interval of time, approximately one second in most cases, before bringing the internal contacts back together to close the circuit. If the current is still too high, the recloser opens the circuit again, thereby limiting the current through the lines. Again, the recloser closes the circuit after a few moments. Reclosers are designed to successively reclose only a few times, typically three times, before going into an open circuit configuration. In the open circuit configuration, the recloser remains open and can only be closed by physically turning a lever located on its surface.
In many cases, a fault condition may place several reclosers along an electric power line in their open circuit configuration This requires workers to travel to each of the reclosers to reset them back into their closed circuit configuration. The time and effort required to reset all of the reclosers along the distribution lines can add significantly to the cost and delay of restoring electrical power after a failure.


A power tool includes a housing having a handle configured for a user, the handle defining a first axis, a motor supported by the housing, the motor defining a second axis along a length of the motor, a tool element movably supported by the housing and drivingly coupled to the motor, the tool element defining a third axis along a length of the tool element. Each of the first, second, and third axes are oblique with respect to each of the other axes.

The present invention relates to a reciprocating saw, and, more particularly, to a portable, battery powered reciprocating saw.
Reciprocating saws are used to cut a variety of objects made from a variety of materials, such as metal pipes, wood and dry wall. A cordless, compact reciprocating saw allows for cutting operations in tight spaces or awkward angles for plumbing, electrical, remodeling and HVAC applications.

Portable battery-powered reciprocating saw


An aircraft (50) with a variable cargo bay (52) includes a frame (60). A pair of fairing assemblies (54, 56) is coupled to the frame (60). Each of the pair of fairing assemblies (54, 56) has a ramp (100) connected to the frame (60) by a front sliding pivoting mechanism (106). A door assembly (58) is between the pair of fairing assemblies (54, 56) and is coupled to the frame (60).

Aircraft are generally designed to carry their maximum load in the fuselage and/or wings of the aircraft. A prior art aircraft 10, is shown in FIGS. 1 and 2. The fuselage 12 of the aircraft 10 is where any loads are stored in flight. In modern military aircraft, it is common for the aircraft to have ample thrust to carry larger loads than can fit within its fuselage. One way to take advantage of this extra thrust is to place these oversized loads externally. These external loads are attached to mounts on the wings or fuselage. An example of an aircraft 20 with a plurality of oversized loads 22, is shown in FIGS. 3 and 4. While this allows the aircraft to carry oversized loads, the oversized loads now have to be designed to withstand a severe acoustic environment and carrying the loads externally increases the aerodynamic drag on the aircraft.
Another solution to increasing the payload capacity has been to redesign the aircraft with a larger fuselage so that it can carry larger loads internally. Carrying the loads internally protects the loads from environmental exposure, but increases the size and weight of the aircraft as well as the cost of the aircraft. This is illustrated by FIGS. 5 and 6. FIG. 5 shows an aircraft 30 externally carrying an oversized load 32. FIG. 6 shows a redesigned aircraft 40 capable of carrying the oversized load 32 internally. The redesigned larger aircraft 40 is longer 42 than the aircraft 30 with the external load. In many aircraft, this extra load capacity is only needed for a small percentage of its missions however the size, weight and cost penalties are incurred for all missions.
Thus, there exists a need for an aircraft that can carry oversized loads internally, without incurring the weight, cost and size penalties imposed by designing a larger aircraft.


The present invention monitors a user's activities to determine how much attention he is paying to one or more devices. Based on the information gathered about the user's current “attention profile,” a “user-interaction parameter” is set that reflects where the user's attention is focused and, ideally, how much of his attention is given to each device. Then, based on the user-interaction parameter, the user interface of at least one of the user's devices is configured to optimize the user's interactions, given the amount of attention he is currently giving to this user interface. If the user is giving the majority of his attention to the television, for example, then the user interface of a companion device can be configured to emphasize the types of interactions available to a user who is not actively watching the companion device.

As personal communications devices (e.g., cell phones) are developed to support greater and greater functionality, people are using them to do much more than talk. As is well known, these devices now usually allow their users to create media files (e.g., by taking a picture or by recording a video using a camera on the device), to download media files from remote servers (via a web interface supported by the device), and to access interactive applications.
However, even as people spend more time online, traditional media remain very important. Indeed, rather than simply replacing traditional media time with online time, many people are beginning to "multi-task," that is, to combine traditional and new media. For example, while they watch television, their personal communications device becomes a "companion device" displaying content often, but not always, related to the content shown on their television. Similarly, while they are engaged in an interactive application on their companion device, they remain at least peripherally aware of the content that the television is displaying.
Televisions and companion devices are not designed to optimize the same type of user interactions. Terminology reflects this distinction: Television programming is aimed at "viewers," while companion devices invite "users." That is, television programming is designed, for the most part, to be passively watched while the viewer "leans back" on his couch. Companion devices, supporting fully interactive applications, invite users who "lean forward" to more actively interact with the applications.

Supporting multiple attention-based, user-interaction modes


Disclosed is an improved field effect transistor (FET) employing both a metal-semiconductor (MES) gate and a metal-insulator-semiconductor (MIS) gate, which FET is particularly useful to provide amplification at microwave frequencies. The use of the MIS gate with appropriate biasing allows the carrier density within a selected portion of the device's channel region to be controlled. The carrier density control increases the breakdown voltage of the FET and enables the FET to be operated with higher maximum channel current and a higher drain to source voltage. As a result, higher output power is provided as compared to prior art MESFET devices of a similar size. Also disclosed is an amplifier circuit including the MES/MIS FET of the present invention, which amplifier circuit further includes means coupled to the MES/MIS FET for dividing a high frequency input signal to provide a first divided portion and a second divided portion. The first divided portion is applied to the MES gate while the second divided portion is applied to the MIS gate. The second portion operates as a time varying bias voltage to control carrier density within the channel portion of the MES/MIS FET and thereby control performance parameters such as breakdown voltage and maximum available channel current.

GaAs MESFETS are well known devices for providing amplification at microwave frequencies, high speed digital switching, and various other functions. The use of microwave frequencies in satellite and wireless communications has been growing exponentially over recent years, thereby providing a vast market for GaAs transistors. As the power output capability of MESFETs continues to improve, a single transistor can provide the power once provided by several, thereby saving considerable costs and drastically reducing the size of the amplifier modules. GaAs transistors are increasingly being used in high power transmitters to replace old designs which employed traveling wave tubes or klystrons. The higher the power handling capability and efficiency that can be achieved, the greater the number of potential applications for MESFET amplifiers. Accordingly, there has been a tremendous effort in the commercial and military industry over recent years to improve the performance capability of these GaAs devices.
The conventional MESFET employs a metal gate electrode in direct contact with a GaAs substrate to form what is known as a Schottky barrier. A voltage applied to the gate electrode influences a current carrying region beneath the gate, thereby controlling the flow of current between the drain and source electrodes and thus providing amplification or switching.
Illustrated in FIG. 1 is a cross-sectional view of a conventional n-channel MESFET 10. An n+ source region 14, n+ drain region 12, and an n doped channel region 15 are formed within a GaAs substrate 11. Gate, source and drain electrodes s, g and d, respectfully, are then formed atop the respective doped regions, with the gate electrode g typically offset towards the source electrode s for reduced parasitic source resistance. When a voltage is applied between the gate and source electrodes g and s, it controls a surface depletion region 16 formed within the channel 15, through which current flows from drain to source upon the application of a bias voltage between the drain and source electrodes.
A basic circuit arrangement for which the MESFET 10 provides amplification of an RF input signal is shown in FIG. 2. The circuit 20 amplifies the RF input signal applied to input terminal 18 to provide an amplified RF output across a load resistor R.sub.L. Inductors L1 and L2 act as AC chokes to bring the DC bias voltages Vgg and Vdd to the respective gate and drain terminals of the device 10. Capacitors C1 and C2 function as DC blocks, while input and output matching structures 17 and 19 are employed to transform the relatively high input and output system impedances to generally lower device impedances, to optimize the performance of the MESFET 10.
The load line characteristics of the circuit 20 superimposed on the MESFET 10 I-V characteristics is shown in FIG. 3. As the RF input signal swings up and down during one RF cycle, so does the gate to source voltage V.sub.GS which causes the drain to source current i.sub.DS to increase and decrease, respectively. This results in the drain to source voltage v.sub.DS being large when the current is small, and vice versa. The load line 21 indicates that the v.sub.DS swing is from a "knee" voltage Vk to (2VDD-Vk), as i.sub.DS swings from a maximum current i.sub.P to a minimum current imin. Basically, the slope and excursion of the load line is governed by the choice of the DC bias voltages VDD and VGG, the value of the load resistance R.sub.L in conjunction with the output matching network 19, and the magnitude of the input voltage swing (i.e., the RF input power level). In any event, these parameters must be selected to prevent the voltage v.sub.DS from swinging too high and penetrating the breakdown region 19.
To maximize output power, it is desirable to have both a large current swing and a large voltage swing. The maximum current is limited by the channel doping and thickness, while the maximum voltage swing is set by the gate-drain breakdown voltage. One way to increase the gate-drain breakdown voltage is to increase the spacing D1 between the gate electrode g and the drain n+ region 12 (FIG. 1). This approach was the subject of an article entitled "A Novel High-Voltage High Speed MESFET using a Standard GaAs Digital IC Process", by P. Mok et al., IEEE Transactions on Electron Devices, Vol. 41, No. 2, February, 1994. In that article, breakdown voltages above 80V were reported; however, the higher the breakdown voltage which was achieved, the higher the "on-resistance" of the device, a parameter which reduces device efficiency.
A major shortcoming of either of the above approaches to increasing output power--i.e., increasing breakdown voltage or increasing maximum channel current--is that they compete directly with one another. That is, for a given geometry, increasing the channel thickness and/or doping level of the channel to increase the maximum channel current will decrease the gate to drain breakdown voltage. Moreover, increasing the spacing between the gate electrode and the drain n+ region 12 to increase the breakdown voltage actually decreases the maximum channel current. (This latter effect has been measured using a technique of applying short duration voltage pulses between the gate and source in the absence of RF input power, and then measuring the peak i.sub.DS current. This technique is believed to be more representative of the FET's behavior under RF drive than the conventional method of applying DC voltages to the device to measure the maximum current).
Accordingly, there is a need for a GaAs transistor which has both higher gate-drain breakdown voltage and higher current handling capability to yield higher RF power output performance. It is an object of the present invention to provide such a transistor.


A new Pentas plant named ‘PEZZ0004’ particularly distinguished by the large sized inflorescences with red colored flowers, dark yellow-green foliage, vigorous and upright habit with strong branches, and tolerates hot summer conditions.

The present invention comprises a new Pentas, botanically known as Pentas lanceolata, and hereinafter referred to by the variety name 'PEZZ0004'.
'PEZZ0004' is a product of a planned breeding program. The new cultivar 'PEZZ0004' has large sized inflorescences with red colored flowers, dark yellow-green foliage, vigorous and upright habit with strong branches, and tolerates hot summer conditions.
'PEZZ0004'originates from a hybrid cross in a breeding program made in July 2006 in a greenhouse in Gilroy, Calif. The female parent was an unpatented, proprietary plant, identified as 'T50H-4' with violet colored flowers.
The male parent of 'PEZZ0004'was an unpatented, proprietary plant identified as 'T37H-1' with red colored flowers. The resultant seed was sown in January 2007 in a greenhouse in Gilroy, Calif.
'PEZZ0004' was selected as one flowering plant within the progeny of the stated cross in May 2007 in a greenhouse in Gilroy, Calif.
The first act of asexual reproduction of 'PEZZ0004' was accomplished when vegetative cuttings were propagated from the initial selection in May 2007 in a greenhouse in Gilroy, Calif.


An article of furniture includes a structure having a surface that supports a weight. The surface may be tiltable from a first position in which the surface is flat or substantially horizontal and a second position in which the surface is substantially vertical. At least one leg rotating mechanism may attach at least one leg of the article of furniture to the surface so that the at least one leg is rotatable about a vertical axis when the surface is tilted. In some embodiments, the article may be a table and the surface may be a tabletop. In other embodiments, the article may be a chair and the surface may be a seating surface of a seat.

Tables and other articles of furniture are often configured to have a number of legs that support a surface. For instance, tables may have legs or a stand that supports a tabletop. As another example, a chair may have a pedestal base or legs that support a seat. Examples of such articles of furniture may be appreciated from U.S. Pat. Nos. D686,856, 1,240,390, 2,796,307, 2,903,312, 3,166,029, 3,382,820, 3,408,965, 6,389,988, 6,550,402, 7,066,098, 7,765,938, 7,845,290, 8,091,488, 8,342,462, 8,347,796, 8,505,186, and U.S. Pat. App. Pub. Nos. 2010/0044541, 2011/0304183, 2012/0304902, 2012/0306240, and 2013/0118387.
Tables, chairs and other furniture may be nested, or stacked when stored to preserve space. For instance, chairs may be configured to be stacked on top of each other. As another example, tables may be configured to be stacked on top of each other or nested beside other tables.
We have determined that a new arrangement for an article of furniture is needed to improve the ability of furniture to be easily nested, or stacked.

Article of furniture and method of stacking the same


To allow for optimum arrangement of the rows of seats for any individual flight, the distance between rows is adjusted in the longitudinal direction of the passenger plane, optionally according to sections, by storing in a control device an actually desired arrangement of rows, and automatically displacing (via the control device) every row whose position has to be changed to achieve the actually desired arrangement of rows on its fastening rails to the position determined by the actually desired arrangement of rows. In this way, it is possible to provide a passenger plane, preferably prior to landing, with the data of the actual passenger distribution and the resulting optimum arrangement of rows for the next flight so that it can be prepared after landing for the next flight in the shortest possible time.

The present invention relates to a method and apparatus for adapting the seat row arrangement in passenger planes according to need.
In passenger planes, the seat rows are mounted fixedly on fastening rails, which run in the floor in the longitudinal direction of the plane. The plane operator selects a seat row arrangement which is most favorable for the desired intended purpose. Seat row arrangement is understood here as being the number of seat rows and their distances from one another, which may be different in different sections in the longitudinal direction of the plane. As a rule, at the front of the plane there is a Business Class section having larger seat row distances, followed by a generally larger section in Economy Class having smaller seat row distances. Occasionally, continuously uniform seat row distances are also used.
Up to now, the planes have been operated over the long term with a seat row arrangement prescribed once, and the seat row arrangement is changed only under exceptional circumstances if the plane is to be set up, for example, for a new intended purpose and a change in the number of seat rows in Business Class and in Economy Class is to be brought about. Up to now, such changes in the seat row arrangement have been brought about only under exceptional circumstances, since they require a high expenditure in terms of personnel and time because each seat row whose position is to be changed has to be mechanically released from its fastening on the fastening rails, manually displaced and re-fastened by the ground staff. At the same time, if the ratio of seat rows in Economy Class to seat rows in Business Class is changed, seat rows are generally brought into the plane or removed therefrom. It is clear that such conversions entail such high expenditure in terms of personnel and time that they are carried out only in exceptional circumstances.
On the other hand, in the case of the air traffic conditions nowadays when a passenger plane lands at an airport and, after the shortest possible standing time on the ground, sets off again on the return flight to the initial airport or to another airport, situations often arise in which the seat row arrangements with their rigid division into Business Class and Economy Class cannot be used in an economically favorable manner. For example, flights in the early morning or in the evening are often occupied by a high proportion of business travelers in Business Class, while flights on the same routes in the day are more heavily used by Economy Class passengers. In this case, if a relatively large section of seat rows is held ready for Business Class, under flight conditions with a high proportion of economy passengers, the conveying capacity of the plane is not optimally used; on the other hand, at the peak times of Business Class use sufficient seat rows are not available in Business Class.
Accordingly, a need has developed in the art to address one or more problems noted above in the air plane seating industry.

Method and device for adapting the seat row arrangement in passenger planes according to need


In a computer network, processing modules exchange data with a peripheral device using managers at the processing module having different management protocols and one or more different management protocol agents in a network interface at the managed device. Data descriptive of the characteristics of the managed device is generated in the network interface in response to a request from a processing module manager. The generated descriptive data is sent to the requesting manager by the agent having the same management protocol as the requesting manager and a managed device description file is formed from the generated descriptive data by the processing module manager to control the managed device.

1. Field of the Invention
The invention relates to networking processing modules and peripheral devices in a network connected computer system and more particularly to arrangements for providing information on the specifications of peripheral devices to processing modules using the peripheral devices in a network.
2. Description of the Related Art
In networked computer systems, processing modules and peripheral devices serving the processing modules are connected at different points of a network. The network couples the processing modules with other processing modules and the peripheral devices required to service the processing modules. Each processing module includes a manager that manages one or more peripheral devices servicing processing module applications by sending request messages to an agent at the managed device and receiving data returned from the managed device on status and attributes of the managed device. The messaging through the network may be performed using one of several available protocols. In exchanging data, the processing module application may use one of several different protocol models. If the OSI protocol model is employed, the CMIP management protocol is used for device management. Alternatively, the application may use the TCP/IP protocol model which includes the SNMP management protocol for device management.
U.S. Pat. No. 5,367,635 issued to Neal Bauer et al. on Nov. 22, 1994 discloses a computer network management system in which a user editable text file defining object identifications, object types and the path and name of associated executable software is generated and sent to a managed node. The user can then invoke user defined executable software by sending a network command and a user defined object identifier to the agent in a managed node. Data can then be sent between the user and the user defined executable software at the managed node. In order to manage a network peripheral device, however, the user processing module manager must store information on the characteristics of the device. The managed device characteristics information embedded in the processing module manager by the processing module supplier, however, may not correspond to the current characteristics of the managed device. As a result, the user executable software may not perform the desired functions in the managed device.
U.S. Pat. No. 5,404,532 issued to Wade C. Allen et al. on Apr. 4, 1994 discloses a networked computer system having communication between managers and agents in which an event forwarding discriminator in the agent program discriminates among events at the managed device to notify the manager only of significant events defined by the manager. The event forwarding discriminators are monitored so that if an event forwarding discriminator fails, the agent rebuilds or restores it with all its attributes and the manager is notified. The reconstruction of important portions of an agent, however, does not address the problem of providing a processing module manager with the characteristics of the agent of the managed device.
U.S. Pat. No. 5,278,978 issued to Richard A. Demers et al. on Jan. 11, 1994 discloses an arrangement for exchanging data between heterogeneous database systems by converting data in a receiving database system in which descriptive information exchanged between a sending database system and the receiving database system. In the event that the sending and receiving database systems are dissimilar, the data received in the format of the sending database system is converted to the format of the receiving database system. While the Demers et al. patent permits conversion of data between dissimilar machines, it does not relate to maintaining a managed device description file for the purpose of sending commands and controlling the device with respect to its status and attributes in a network.
Managed device characteristics are generally stored at the processing module manager in the form of a device description file specifying the characteristics of the managed peripheral device.
The description file, generally denoted as an MIB (Management Information Base), for each management protocol is written in a different format. In the SNMP management protocol, the MIB of the manager uses a syntax ASN.1. The CMIP management protocol uses a GDMO having the ASN.1 syntax but having a different format than the ASN.1 syntax for SNMP. In the event that the processing module manager operates under a different management protocol than the managed device, access to the data on the characteristics of the managed device may not be properly parsed by the processing module manager so that generation of a managed device description file at the manager would not be possible.
A description file for a peripheral device is generally supplied with the processing module manager for the application and is of the type corresponding the management protocol of the manager. A peripheral device in the network system, however, may utilize another management protocol so that the description file at the manager is not appropriate for the peripheral device. As a result, request messages from the manager based on the format of the management protocol thereat cannot be parsed by the agent in the managed peripheral device. Further, changes in the peripheral device may not be reflected in the description file supplied to the processing module manager from an outside source and a new peripheral device may be added for which there is no description file in the processing module manager.
If the management protocol of the processing module manager is different than the management protocol of a peripheral device managed by the processing module, data packets between the processing module manager and the agent of the managed device may not be sent with compatible management protocols and the description file at the processing module manager may not be in the required syntax. As a result, it is a problem in networked computer systems that description files of managed devices residing in processing module managers may not be useful in making queries on the status and the attributes of the managed device. Neither of the aforementioned patents address the problem of exchanging management data between processing module managers and managed device agents in a networked computer system having various management protocols.

Apparatus for generating and transferring managed device description file


A method and system are used to control a characteristic of a beam. The system comprises an illumination system, at least one optical element, a fluid source, and a pressure and/or fluid concentration controller. The illumination system produces a beam of radiation. The at least one optical element has at least one fluid path therethrough through which the beam passes and is capable of changing a characteristic of one or more portions of the beam. The fluid source supplies fluid to the at least one fluid path. The pressure and/or fluid concentration controller controls pressure and/or fluid concentration of the fluid to change the characteristic of the beam, which is positioned between the fluid source and the optical element.

1. Field of the Invention
The present invention is related to illumination intensity uniformity, ellipticity and telecentricity control using radiation absorbing fluids.
2. Background Art
In a pattern generating environment that patterns an impinging beam of radiation, which is later projected onto an object, controlling characteristics of the beam and/or the patterned beam is critical. This is because the beam and/or the patterned beam have to be precisely controlled in order to form accurate patterns on the object.
Generally, patterning generating systems use static optical systems, which are typically designed and manufactured for each application of the patterning system in order to produce the light beams with desired characteristics. In the static optical system example, when a change in illumination characteristics is desired or needed, a new optical system must be designed and manufactured. Also, changing of an output of an illumination source with time cannot normally be accounted for in a static optical system, which can result in less than desirable patterns being formed on the object.
In other illumination control methods, corrections are made by throwing away light in areas with unwanted light characteristics and/or corrections are being performed by relatively slow mechanical devices, which can substantially reduce throughput.
Further, in some examples, by correcting for one optical characteristic, e.g., light intensity uniformity, other characteristics become undesirable, e.g., ellipticity and/or telecentricity.
Therefore, what is needed is a system and method utilizing a dynamic optical system that is adjustable in response to measured or detected characteristics of an illumination beam and/or patterned illumination beam.

System and method utilizing an illumination beam adjusting system


Tin-based alloys that include micro-additions of certain elements avoid the discoloration that otherwise afflict those alloys when they are melted. The discoloration, which results from tin oxidation, correlates with poor performance of the alloys in filler metal applications. A preferred method of preparing the alloys of the invention is by rapid solidification from the melt.

1. Field of the Invention
This invention relates to tin alloys and, more particularly, to tin alloys that contain small amounts of certain elements.
2. Description of the Prior Art
It has long been known that the oxidation resistance of tin can be improved by the addition of small amounts (about 0.1 at. %) of certain alloying elements that exhibit appreciable solid solubility in tin (W. E. Boggs et al., J. Electrochem. Soc. 110, 4 (1963)). More recently, the effect of certain impurity elements on the wetting properties of tin-lead solders was reported (M. L. Ackroyd et al., Metals Technology, February, 1975, p. 73).
A tin-based solder system for attaching semiconductor devices to a metal package was discussed in U.S. Pat. No. 4,170,472, issued Oct. 9, 1979, to Olsen et al.
During the past decade, several publications have appeared that describe progress in the development of rapidly solidified filler metal alloy foils (See, e.g., N.J DeCristofaro et al., Welding Journal 57(7), 33 (1978); D. Bose et al., Welding Journal 60(10), 29 (1981); and A. Datta et al., Welding Journal 63(10), 14 (1984)).
Nevertheless, tin-based alloys generally suffer discoloration on melting. This discoloration results from oxidation of the tin and, for filler metal alloys, is associated with poor performance (e.g., dewetting of substrates by molten solder and premature failure of devices).


A memory array includes a plurality of memory banks, each having a plurality of sectors and a plurality of sector decoders, each sector decoder operatively associated with a sector. A first plurality of lines provides first signals, and a second plurality of lines provides second signals. A first decoder apparatus is operatively associated with the first plurality of lines for receiving the first signals and for providing a first address signal by means of a first single line to a sector decoder of a memory bank. A second decoder apparatus is operatively associated with the second plurality of lines for receiving the second signals and for providing a second address signal by means of a second single line to a sector decoder of a memory bank.

1. Technical Field
This invention relates generally to memory arrays, and more particularly, to sector decoding in such an array.
2. Background Art
FIG. 1 illustrates a flash memory array 50 of the prior art. This memory array 50 includes a plurality of memory banks (shown are banks BA and BB of a large number of memory banks). Each memory bank includes a plurality of sectors arranged in a column. For example memory bank BA includes sectors SA1-SA8 arranged in a column, memory bank BB includes sectors SB1-SB8 arranged in a column, and so forth. These columns of sectors are in parallel relation as illustrated FIG. 1. Each sector is operatively associated with a sector decoder as shown. For example, in memory bank BA, sector decoder SA1D is operatively associated with sector SA1, etc., while in memory bank BB, sector decoder SB1D is operatively associated with sector SB1, etc.
At the bottom of the array 50 are a plurality of read address lines R (including lines R1, R2, R3) and a plurality of write address lines W (including lines W1, W2, W3). The read address lines R1, R2, R3 communicate respectively with lines R1A, R2A, R3A, (which make up the plurality of lines RA), and the lines R1A, R2A, R3A in turn communicate with each of the sector decoders SA1D-SA8D. The read address lines R1, R2, R3 also communicate respectively with lines R1B, R2B, R3B (which make up the plurality of lines RB), and the lines R1A, R2A, R3A in turn communicate with each of the sector decoders SB1D-SB8D. The write address lines W1, W2, W3 communicate respectively with lines W1A, W2A, W3A (which make up the plurality of lines WA), and the lines W1A, W2A, W3A in turn communicate with each of the sector decoders SA1D-SA8D. The write address lines W1, W2, W3 also communicate respectively with lines W1B, W2B, W3B (which make up the plurality of lines WB), and the lines W1A, W2A, W3A in turn communicate with each of the sector decoders SB1D-SB8D. In addition, select decoders are included for selecting a particular memory bank. As illustrated, select decoder BAD has extending therefrom lines WSELA, RSELA which communicate with each of the sector decoders SA1D-SA8D, select BBD has extending therefrom lines WSELB, RSELB which communicate with each of the sector decoders SB1D-SB8D, etc.
It will be understood that while the present embodiment illustrates eight sectors in each bank, along with three read address lines R1, R2, R3 (capable of providing eight digital addresses) and three write address lines W1, W2, W3 (capable providing eight digital addresses), these numbers are chosen for illustrative purposes only and, for example, each bank may include more than eight sectors, for example 16 sectors which would be associated with four read address lines (for providing 16 digital addresses) and four write address lines (for providing 16 digital addresses).
Each of the select decoders BAD, BBD is identical in configuration, and the select decoder BAD is illustrated in FIG. 2. In selecting a bank, an external address EA is provided to a NAND gate 100 of the bank to be selected, for example, the bank BA. The signal from the NAND gate 100 is inverted by means of inverter 102, the output of which is provided to the gate of N channel transistor 104 and input to a NAND gate 106. The transistor 104 is in series with N channel transistor 108 and P channel transistor 109, with transistor 109 connected to Vcc and transistor 104 connected to ground. The node A between the transistors 108, 110 is connected to a latch 112 and also to an input to the NAND gate 106. With the signal to the gate of the transistor 108 low, and with the signal RSTB to the gate of the transistor 109 low, an address signal to the NAND gate 100 provides a low output therefrom which is inverted to a high output applied to the gate of the transistor 104 and input to the NAND gate 106. The node A is high, causing the output on line WSELA of the latch 112 to be low. At the same time, the node A provides a high signal to the NAND gate 106, providing a low output from the NAND gate 106 which is inverted by inverter 114 to provide a high output on line RSELA. To reverse these outputs, so that line WSELA is high and line RSELA is low, the input to the gate of transistor 108 is pulsed while the input signal RSTB is taken high so that node A is driven low, causing line WSELA to go high and line RSELA to go low. Each of the signals on lines WSELA, RSELA is provided to each of the select decoders SA1D-SA8D, each of the signals on lines WSELB, RSELB, is provided to each of the select decoders SB1D, SB8D, etc. The select decoders SA1D-SA8D, SB1D-SB8D are similar in configuration and will be described with reference to FIGS. 4 and 5.
FIG. 3 illustrates the array 50 of FIG. 1 with line RSELA high and line WSELA low, selecting bank BA and providing a read select signal to each of the sector decoders SA1D-SA8D (it is understood that the term "write" may include writing and erasing). Meanwhile, the signals on the lines R1, R2, R3 (read address), are provided as 111 respectively while the signals on the lines W1, W2, W3 (write address) are provided as 000 respectively. The select decoder SA8D includes AND gate 8120 and AND gate 8122 in parallel. The lines RSELA, R1A, R2A and R3A provide input signals to the AND gate 8120, while lines WSELA, W1A, W2A and W3A provide input signals to the AND gate 8122. The outputs of the AND gates 8120, 8122 are provided as inputs to NOR gate 8124, the output of which in turn is provided to inverter 8126. The output from the inverter 8126 is provided to the sector SA8. In the present example, and as illustrated also in FIG. 4, lines RSELA, R1A, R2A and R3A are high, providing a high output from AND gate 8120, while lines WSELA, W1A, W2A and W3A are low, providing a low output from AND gate 8122. This provides a low output from NOR gate 8124 and a high output from inverter 8126, so that a high (read address) signal is provided to sector SA8. Meanwhile, and with reference to FIG. 5, the high signal on line RSELA is provided to AND gate 7120 of sector decoder SA7B, while high signals on lines R1A, R2A are provided to AND gate 7120. As shown, the signal on line R3A is inverted by inverter 7128, and the output from inverter 7128 is input to AND gate 7120. The outputs of both AND gates 7120, 7122 are low, so the output from NOR gate 7124 is high and the output from inverter 7126 is low, so that a read address signal is not provided to sector SA7.
FIG. 6 illustrates the array of FIG. 3 again with line RSELA high and line WSELA low, selecting bank BA and providing a read select signal to each of the sector decoders SA1D-SA8D. Meanwhile, the signals on the lines R1, R2, R3 (read address), are provided as 110 respectively while the signals on the lines W1, W2, W3 (write address) are provided as 000 respectively. As described above, the lines RSELA, R1A, R2A and R3A provide input signals to the AND gate 8120, while lines WSELA, W1A, W2A and W3A provide input signals to the AND gate 8120. In this example, and as illustrated also in FIG. 7, lines RSELA, R1A, and R2A are high, while line R3A is low, providing a low output from AND gate 8120, while lines WSELA, W1A, W2A and W3A are low, providing a low output from AND gate 8122. This provides a high output from NOR gate 8124 and a low output from inverter 8126, so that a read address signal is not provided to sector SA8. Meanwhile, and with reference to FIG. 8, the high signal on line RSELA is provided to AND gate 7120 of sector decoder SA7B, while high signals on lines R1A, R2A are provided to AND gate 7120. The low signal on line R3A is inverted by inverter 7128, and the output from inverter 7128 is input to AND gate 7120. The output of AND gate 7120 is high, while the output of AND gate 7122 is low, so the output from NOR gate 7124 is low and the output from inverter 7126 is high, so that a read address signal is provided to sector SA7.
It will be understood that the other sector decoders include appropriately placed inverters (similar to inverter 7128) so that only one sector at a time is provided with a read or write address signal.
As will be seen with reference to FIGS. 1, 3 and 6, the pluralities of lines RA and WA, RB and WB, etc. extend and lie within the area of the memory banks between adjacent columns of sectors (for example, plurality of lines RA and plurality of lines WA lie between the column of sectors SA1-SA8 and the column of sectors SB1-SB8. These lines, included across the device between each pair of adjacent columns of sectors, take up substantial area of the finally produced die, causing the die to be large in area. As is well understood, reduction in die size for a given devices highly desirable. The problem is increased when the number of sectors in a column is increased. For example, has pointed out above, a column of 16 sectors would require four read address lines and four write address lines rather than the three read address lines and three write address lines as shown in the present example.
Therefore, what is needed is an approach wherein proper addressing up sectors in a memory array may be undertaken, meanwhile using an approach which reduces die size as compared to the prior art.


The present invention relates to primers for diagnosis of one or more kinds of cancers and a diagnosis kit comprising said primers. The primers are made from highly homologous areas of twelve MAGE subtypes and eight GAGE subtypes. The diagnostic kit comprising the said primers can detect six MAGE subtypes and eight GAGE subtypes respectively. The invention also includes methods for using the primers to diagnose the onset of cancer, to monitor the progression of disease, and to correlate the gene expression to the prognosis of disease.

1. Field of the Invention
The present invention is related to primers for diagnosis of one or more kinds of cancers expressing the MAGE or GAGE genes or their subtypes, and a diagnostic kit containing the above primers. In a particular embodiment, the invention relates to common primers that can simultaneously detect six MAGE sub-types from MAGE 1 to MAGE 6 (MAGE 1–6) or eight GAGE sub-types from GAGE 1 to GAGE 8 (GAGE 1–8), a diagnostic kit containing the above common primers, and methods for use of these primers to detect cancer. Additionally, the invention includes methods for use of primers for detection of MAGE or GAGE expression in a clinical methodology to detect the expression of multiple MAGE and GAGE genes in biological samples, including patient samples for screening, diagnosis, or prognosis in cancer patients. The methodology may also include qualitative correlation of expression of the MAGE or GAGE genes to disease or quantitative measurement of expression of one or more genes to standard or control values, and the use of this comparison in the methodologies listed above.
2. Description of the Prior Art
The diagnosis of cancers has been accomplished through the medical physical examination, X-ray and CT, histological examination, etc. However, these methods have not been appropriate for detection of cancers at the initial stage, for discrimination between a malignant cancer and a benign tumor. It is believed that the initial stages of cancer development cannot be detected by direct physical observation, but occur at the genetic level where a number of genes that are involved in the onset or progression of the cancer are differentially expressed in the very earliest stages of the disease. In some cases, the initial stages of cancer may be marked by the expression of specific genes that either accompany the onset of the disease, or that are the actual causative agent in the onset or progression of cancer. Unfortunately, the ability to detect these events is complicated by the fact that hundreds or thousands of genes may be expressed during the onset of the disease and it is extremely difficult to detect and to separate normal gene expression from the expression of the specific genes that indicate or are responsible for, the onset or progression of disease.
However, recently developed molecular biological diagnostic methods have contributed greatly to the development of cancer diagnostics that are both specific and highly sensitive. The most widely used method among many molecular biological diagnostic methods is the polymerase chain reaction (PCR) or the reverse transcriptase-polymerase chain reaction (RT-PCR). In these techniques, abnormal genes, such as cancerous antigen genes expressed in a sample, are amplified and detected.
Particularly, RT-PCR is a method of detecting mRNA which is expressed by a particular gene. This method may be used for the diagnosis of a cancer by examining the property of expression of cancerous antigen genes. The most important matter in the diagnosis of a cancer in the RT-PCR method is the selection of the target gene for detection (hereinafter referred to as a "cancer diagnosis marker"). Usually, only one cancer diagnosis marker is selected and detected by this method.
The requirements for a cancer diagnosis marker are that it should be selectively expressed in cancerous tissue and should be expressed in large amounts in as many cancer types as possible. MAGE (melanoma antigen gene) and GAGE ('G' antigen gene) are two kinds of cancer-associated testis antigens. Selected subtypes or subfamilies of these genes are expressed in many kinds of cancer tissues, but are not expressed in most normal tissues, except for the testis. It has been clarified that MAGE has been expressed in many cancers such as the stomach cancer (1, 2), esophagus cancer (3), colon cancer (4), lung cancer (5), breast cancer (6, 7), liver cancer (8), leukemia (9), neuroblastoma (10), ovary cancer (11), etc. in many studies since it was discovered in the melanoma. And it has been reported that GAGE has been expressed in the melanoma, sarcoma, small-cell carcinoma, head and neck cancer, bladder cancer, ovary cancer, etc. (11, 12). MAGE or GAGE genes may be identified with distinct nomenclature as subtypes or subfamilies, such as MAGE A–L, and specifically such as MAGE A1–A15, MAGE B1–17, MAGE C1–7, MAGE D1–4, MAGE E1–3, MAGE F, MAGE G, MAGE H, MAGE 11–12, MAGE J1, MAGE K1, MAGE L2 and NECDIN.
Therefore, selected MAGE and GAGE genes are very extensively utilized as cancer diagnostic markers because detection of MAGE and/or GAGE expression detects many kinds of cancers and has a high specificity for expression in cancer tissues compared to other cancer-associated antigens such as the carcinoembryonic antigen, etc. Also, MAGE and GAGE have a high homogeneity of gene sequence among gene subtypes. About 12 kinds of sub-types of MAGE have the homogeneity ranging from about 56% to 99%, and 8 kinds of sub-types of GAGE have the homogeneity ranging from about 82% to 99%. Therefore, it is possible to increase the cancer diagnosis rate by using such same DNA sequence part as a primer since many sub-types of MAGE or GAGE may be detected simultaneously during RT-PCR. De Plaen et al., "Structure, chromosomal localization, and expression of 12 genes of the MAGE family, Immunogenetics 1994;405(5):360–9; Chomez, Patrick et al., "An Overview of the MAGE Gene Family with the Identification of all Human Members of the Family," Cancer Research 61, 5544–5551, Jul. 15, 2001; Barker, P A, et al., "The MAGE proteins: emerging roles in cell cycle progression, apoptosis, and neurogenetic disease," J. Neurosci Res 2002 March 15:67(6):705–12; Van den Eynde, B., et al., "A new family of genes coding for an antigen recognized by autologous cytolytic T lymphocytes on a human melanoma," J. Exp. Med. 1995 September 1,;182(3):689–98; and De Backer, Olivier, "Characterization of the GAGE Genes That Are Expressed in Various Human Cancers and in Normal Testis," Cancer Research 59, 3157–3165, Jul. 1, 1999).
Accordingly, the highly conserved, high homogeneity of sequences among MAGE and GAGE subtypes allows the design of common primers of the invention having a high selectivity and specificity for cancer detection and diagnosis. Moreover, the primers of the invention exhibit high specificity for cancer detection and diagnosis through simultaneous detection of many MAGE or GAGE gene subtypes.

Selected primers for detection of MAGE or GAGE genes for diagnosis of cancer and methods of use


The edge protector of the present invention is made of a plurality of sheets of inexpensive cardboard or linerboard cut into sections and laminated in a flat configuration. The laminations include at least one sheet which is continuous and provides a hinge portion, at least one sheet which is flexible and provides a stop--similar to a leaf spring. Protective laminates are disposed between the continuous member and the spring-like member and include a central portion and at least one leg portion. The leg portion can be pivoted about an axis in the continuous member, away from and at an angle to the central portion, thereafter to be held in angular disposition (that could vary in angular disposition restricted only to products' natural restrictions) with regard to the central portion by the spring-like portion. The edge protector of the present invention is particularly suited for protecting the edges of a large range of equipment such as furniture, desk-tops during the shipment or movement of such equipment or furniture. The channel of the present invention, when constructed, is flat, but when "set up", would be primarily an "L"-shape or "U"- shape configuration. But certainly not restricted to these configurations. They could be box-shaped, hexagonal, etc., limited only to a practical application of the spring hinge and hold concept.

For the protection of furniture during shipment or movement thereof, many devices have been suggested and provided as packaging supports or pads or corner protectors or the like, and I refer particularly to U.S. Pat. Nos.: 4,784,270; 4,399,915; 4,375,852; 4,360,145; 3,337,111; 974,844; 2,950,038; 2,914,232; 2,896,833; 2,783,930; 692,720; and 2,196,157.
Such devices, for economy purposes, have often been made of fiber board, liner board, or simlar flat cardboard, but may also be made of sheets of polystyrene or rubber or other similar flexible packaging material.
Most of these devices have been provided for the protection of corners such as Suess U.S. Pat. No. 2,692,720, but others have included edge-protectors such as shown in White U.S. Pat. No. 2,196,157 and Petriekis U.S. Pat. No. 3,337,111.
Although the devices of the prior art have been effective to protect the furniture, they have, in the past, required either an external carton or box to hold them in place against the furniture or some sort of belting or strapping to hold them in place. In some cases the channels may still require banding or boxing depending on the application, but the new channel would be self-gripping during the banding operation, making it much easier to use, and would reduce the banding required.

Foldable multi-ply shock-absorbing edge protector


Provided herein is technology relating to treating and/or ameliorating TNFα cytotoxicity and particularly, but not exclusively, to compositions, methods, and kits for specifically modulating BCL-2-associated death promoter (BAD) activity, for example, by modulating the activity of Src and/or p190GAP.

The pro-inflammatory cytokine TNFα has a crucial role in inflammation, immune responses, and apoptosis (1-4). TNFα alone does not typically induce apoptosis under physiological or developmental conditions unless IKK-mediated activation of NF-κB is also impaired (5) because the target gene products of NF-κB inhibit caspases and prevent prolonged JNK1 activation (6, 7). Inactivation of the BH3-only family protein BAD by IKK is also required for suppression of TNFα-induced apoptosis (8). Like other BH3-only family member proteins, BAD is a potent inducer of apoptosis (9). Hypo-phosphorylated BAD translocates from the cytosol to mitochondria to inactivate the anti-apoptotic BCL-2 family members BCL-2 and BCL-xL, which results in the increased activity of the pro-apoptotic BCL-2 family members BAK and BAX to induce apoptosis (10, 11). Phosphorylation of BAD by IKK at Ser26 primes BAD to be further phosphorylated at Ser112, Ser136, and Ser155 by other protein kinases (e.g., Akt and PKA), which results in the sequestration of BAD in cytosol by association with the phospho-Ser/Thr anchoring protein 14-3-3 (8, 10-12).
TNFα cytotoxicity has long been recognized to have a crucial role in the pathologies of inflammatory disease, infectious disease, autoimmune disease, and cancer (13, 14). However, the mechanism underlying TNFα cytotoxicity is not known. Furthermore, little is known about the genetics and chemical perturbations of TNFα cytotoxicity and IKK signaling pathways in diseases associated with TNFα-induced tissue or organ damage.


A memory test circuit receives test pattern data from a processing unit having a first data width, expands the test pattern to a second data width greater than the first data width, and writes the expanded test pattern data into a memory having the second data width, thereby avoiding the need for extra write cycles when a processing unit tests a memory having a greater data width. The test pattern data may be expanded by, for example, copying a specific bit to multiple bit positions, inverting a specific bit and copying the inverted bit to multiple bit positions, or performing arithmetic operations that generate a test pattern similar to the test pattern received from the processing unit.

1. Field of the Invention
The present invention relates to a memory test circuit enabling a central processing unit (CPU) to test a memory having a data width greater than the data width of the data bus linking the memory to the CPU.
2. Description of the Related Art
So-called system-on-a-chip devices, for example, are often structured to transfer data directly between memory and peripheral computational circuits on a wide data bus, without the intervention of the CPU. One example of such a device is described in Japanese Patent Application Publication No. 2000-357372. When the device is fabricated, it is tested by having the CPU execute a self-test program. As part of the self-test, the CPU must write test patterns in the memory, so a memory test circuit, which is a type of switching circuit that connects the memory to the CPU, is provided. If the width of the CPU data bus is less than the data width of the memory, the memory test circuit must also convert the data width.
FIG. 1 schematically shows a conventional memory test circuit. This memory test circuit tests a memory (MEM) 1 having an m-bit data width by using a CPU 2 having an n-bit data bus (m>n). To convert between m-bit and n-bit data, the circuit includes an m-bit register (REG) 3, L n-bit registers 41, 42, . . . , 4L (where L is the least integer equal to or greater than m/n), and a selector (SEL) 5. Register 3 is coupled between the data input-output terminals of the memory 1 and registers 41-4L. Registers 41-4L are coupled in parallel to the data bus of the CPU 2. Selector 5 selects n-bit portions of the data stored in register 3 and supplies the selected data to the CPU 2.
In this type of memory test circuit, an m-bit word of data written into the memory 1 is first written from the CPU 2 into registers 41-4L as separate n-bit portions of write data WDT, requiring L write cycles; then the n-bit portions of write data are transferred all at once through register 3 into the memory 1. Similarly, m-bit data read from one word in the memory 1 are stored in register 3 temporarily, and the stored data are divided into n-bit portions in selector 5 and sequentially supplied to the CPU 2 as read data RDT. Accordingly, even though the memory 1 can input or output m bits per cycle, each reading or writing operation requires (L+1) cycles.
In, for example, a memory test using the marching cubes algorithm (a specific procedure for which will be given later), a total of ten test cycles, including six write cycles and four read cycles, are inherently necessary for each word in the memory 1. In the memory test circuit described above, (L+1) times as many cycles are required; that is, 10(L+1) cycles are required. Even in a simpler memory test using a checker pattern or the like, that inherently requires only four cycles (two write cycles and two read cycles) per word, 4(L+1) cycles are needed, and in a memory test using a diagonal pattern, 2(L+1) cycles are required for writing and reading.
The conventional memory test circuit described above is problematic because the test data must be written from the CPU 2 into registers 41-4L in multiple separate portions, greatly increasing the necessary number of test cycles.

Oki Electric Electric Industry Co., Ltd.


A system and method using ANT and/or ANT+ protocols for one or more ANT and/or ANT+ applications. The system can include a Bluetooth interface and a Host Controller Interface (HCI) that are configured to process incoming and outgoing ANT and/or ANT+ messages from/to one or more ANT and/or ANT+ enabled devices. The ANT and/or ANT+ messages can be communicated to one or more ANT and/or ANT+ enabled devices utilizing a Bluetooth transceiver. The Bluetooth interface and the HCI can be configured to wrap one or more ANT and/or ANT+ messages with a header and/or to remove a header from one or more wrapped ANT and/or ANT+ messages. The header can be an HCI compatible header.

1. Field
This application relates generally to wireless communications, including wireless communications utilizing ANT and/or ANT+ protocols.
2. Related Art
The Bluetooth (IEEE 802.15.1 and Bluetooth Special Interest Group (SIG)) specification defines the Bluetooth communication protocol for radio frequency (RF) communications between two more communication devices utilizing a short-range radio link. Bluetooth operates in a globally unlicensed 2.4 GHz Industrial, Scientific, and Medical (ISM) band. Due to low power requirements, Bluetooth integrated circuits (ICs) are designed to consume very low power to operate.
Similar to the Bluetooth protocol, the ANT communication protocol represents an ultra-low-power, short range wireless technology operating on the 2.4 GHz ISM band. The ANT communication protocol can be used to establish a sensor network having one or more sensors that wirelessly communicate with one or more communication devices. For example, the ANT communication protocol can be that used in sports and fitness fields to implement personal area networks (PANs) for performance and health monitoring. ANT+ is an interoperability function that can be added to the base ANT communication protocol to allow for one or more ANT+ enabled devices to interface with one or more other ANT+ enabled devices.
The embodiments of the present disclosure will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.

Host controller interface and messaging method for ANT applications


An apparatus for generating data for use in determining a property of a gemstone, such as a cut diamond with a support structure for supporting a gemstone placed at an observation position, the support structure being arranged such that, if the gemstone has an axis of symmetry, the gemstone is supportable such that the axis of symmetry is parallel to an axis X passing through the observation position; an illuminator arranged to illuminate a gemstone so placed with a spatially varied light pattern; a rotator arranged to cause relative rotation between the light pattern and the support structure generally about the axis X; and a camera arranged to capture, at each of a plurality of rotational positions, an image of light returned by the gemstone and to output said images as image data.

The beauty of a gemstone, such as a cut diamond, derives from its light handling ability. What attracts the eye is the "game of light" played by a well-cut diamond as incident light is reflected and refracted off its many facets. Diamonds and other gemstones may be cut according to many different standardised cut patterns such as the standard round brilliant cut, oval, pear, marquise, radiant, princess, heart, emerald cut etc. The most popular cut is the standard round brilliant (SRB) cut as shown in FIG. 1. Diamond cutting and polishing is a highly skilled art and a well-cut diamond, having superior optical performance, will command a significant price premium over a poorly cut diamond having inferior optical performance.
When showing a cut diamond to an untrained observer, one frequently refers to the four C's of a gemstone, being its carat weight, its clarity, its cut and its colour. Carat weight, clarity and colour can be relatively easily measured objectively and are therefore generally useful. Cut may also be specified or measured in terms of the geometry of the various facets. However, what really matters is the light handling ability of the gemstone and reference is often made to more subjective parameters of a cut diamond, such as its brilliance (the intensity of light returned), scintillation (fast and local fluctuations in the light returned as the diamond moves relative to the lighting conditions), fire (the dispersion of white light into spectral colours) and symmetry (the symmetry of light patterns such as the so-called "hearts and arrows"). It can be difficult, particularly for an untrained observer, to make a personal appraisal of these subjective parameters. It can also be difficult to compare the light handling abilities of two diamonds with the same carat weight, clarity and colour, and therefore to appreciate why one is more valuable than the other.
It is recognised that properties such as brilliance, fire and symmetry should be derived, whether by experimental observation or theoretical computer modelling, under a variety of lighting conditions. Moreover, with the property of scintillation it is clearly essential to observe or model the diamond under a variety of lighting conditions. Electronic apparatus for capturing images of gemstones under varying lighting conditions for analysis are known.

Apparatus for generating data for determining a property of a gemstone and methods and computer programs for determining a property of a gemstone


A vehicle diagnostic information storage system includes a volatile storage device such as a backup RAM and a nonvolatile storage device such as EEPROM. If a fault occurs, a control section stores data on fault items, and input and output conditions of sensors of a vehicle control system, in the volatile storage device and updates the data in the volatile storage device during a vehicle operation. In response to a switching operation of a vehicle main switch such as a turn-on operation of an ignition switch, the control section transfers the most recent version of updated data from the volatile storage device to the nonvolatile storage device.

The present invention relates to a diagnostic system for a vehicle, and more specifically to a system for storing diagnostic information.
Complicated vehicle control systems increase the need for onboard diagnostics (self diagnosis) for diagnosing faults and malfunctions in the systems.
Japanese Patent Provisional Publication No. 61-169332 shows a conventional diagnostic system for an automatic transmission.
In some conventional examples, diagnostic information is lost when the driver turns off the ignition switch. The diagnostic system of the above-mentioned Japanese document employs a nonvolatile memory for saving information on detected faults. However, this system is not arranged to use the nonvolatile memory effectively in consideration of the characteristics of the memory.


Optical transmission being performed by frequency modulating frequency-division-multiplexed multi-channel signals as a single unit, distortion that is caused by a ripple-shaped group delay deviation in a transmitter 2, a receiver 4 and an optical link 3 is reduced by providing a level adjuster 2a for adjusting the level of frequency-division-multiplexed multi-channel signals input to the FM modulator 2b, and by increasing the input level of multi-channel signals to the FM modulator 2b by level adjusting means 2a to enlarge the bandwidth of FM signal, in the case where the number of channels is small.

1. Field of the Invention
The present invention relates to an optical transmission system for frequency modulating frequency-division-multiplexed multiplexed-channel signals as a single unit for optical transmission and optical transmission apparatus used for the system.
2. Description of the Related Art
Conventionally, there is known a system for frequency modulating frequency-division-multiplexed multiplexed-channel signals as a single unit for transmission. FIG. 10 is a block diagram showing the configuration of such a conventional optical transmission system. In FIG. 10, an optical transmission system 50 has a configuration in which a transmitter 51 connects to a receiver 53 through an optical transmission link, such as an optical fiber 52.
The transmitter 51 is composed of a general FM modulator 54 for frequency modulating a carrier signal as a single unit by frequency-division-multiplexed multiplexed-channel signals and an optical modulator 55 for modulating the intensity state of a signal light by the resulting frequency-modulated signals. The receiver 53 is composed of an optical receiver for performing photoelectric conversion of transmitted optical signals and an FM demodulator 57 for frequency demodulating the frequency-modulated signal to output frequency-division-multiplexed multiplexed-channel signals.
Next, the operation of a conventional optical transmission system is described below. Frequency-division-multiplexed multiplexed-channel signals input to the FM modulator 54 are frequency modulated as a single unit. The resulting frequency-modulated signal is applied to the optical modulator, which changes the intensity state of the signal light, and is transmitted through the optical fiber line 52. Optical signal transmitted to the receiver 53 undergo photoelectric conversion, and the resulting frequency-modulated signals is frequency demodulated by the FM demodulator 57 to restore frequency-division-multiplexed multiplexed-channel signals.
An optical transmitter used for this type of optical transmission systems is disclosed, for example, in JP-A-8-274714 (optical signal transmitter). This optical signal transmitter can transmit multiplexed-channel signals (video signals) by converting amplitude modulated broadband electrical signals to frequency-modulated electrical signals, and thus can provide an optical transmitter having good signal quality.
However, in this type of conventional optical transmission system and an optical transmitter used for the optical transmission system, there occurs a ripple-shaped group delay deviation which periodically varies from the specific frequency shown in FIG. 3. This group delay deviation raises the problems such that the number of channels for frequency-division-multiplexed multiplexed-channel signals input to the transmitter becomes small, that is to say, bandwidth of FM signal frequency modulated as a single unit is reduced so that distortion caused by the ripple-shaped group delay deviation comes to be larger distortion in case of the signals being transmitted from the transmitter to the receiver.
The object of the invention is to provide an optical transmission system for increasing the level per waveform of multiplexed-channel signals and increasing the bandwidth of FM signal to reduce the distortion caused by a ripple-shaped group delay deviation in a transmitter, a receiver and optical transmission link, even in the case where the number of channels for frequency-division-multiplexed (FDM) multiplexed-channel signal input to the transmitter is small, and the bandwidth of FM signal frequency modulated as a single unit is reduced.
An optical transmission system according to the invention comprises a transmitter for transmitting optical signals based on the input frequency-division-multiplexed multiplexed-channel signals and a receiver for receiving optical signals transmitted from the transmitter through optical transmission link, the transmitter having signal level adjusting means for reducing the distortion caused by a ripple-shaped group delay deviation in a transmitter a receiver and the optical transmission link in transmitting optical signals from a transmitter or a receiver. Through such a system configuration, the bandwidth of FM signal can be enlarged and the distortion caused by a ripple-shaped group delay deviation in a transmitter, a receiver and optical transmission link can be reduced by adjusting to increase the level per waveform of multiplexed-channel signals through signal level adjusting means, even in the case where the number of channels for the frequency-division-multiplexed multiplexed-channel signals input to the transmitter is small, and the bandwidth of FM signal frequency modulated as a single unit is reduced.
In an optical transmission system according to the invention, the transmitter is equipped with a general FM modulator for frequency modulating multiplexed-channel signals as a single unit and the receiver is equipped with optical modulation means for adjusting the intensity state of the signal light through frequency modulated signals obtained by frequency modulating multiplexed-channel signals as a single unit. Further equipped is an optical receiver for performing photoelectric conversion of the optical signal transmitted to the receiver through the optical transmission link on a general FM demodulation for frequency demodulating FM signal obtained thereby. Through such a system configuration, the bandwidth of FM signal can be enlarged and the distortion caused by a ripple-shaped group delay deviation in a transmitter, a receiver and optical transmission link can be reduced by increasing the level per waveform of multiplexed-channel signals through signal level adjusting means when signals are transmitted from the transmitter to the receiver through an optical channel, even in the case where the number of channels for frequency-division-multiplexed multiplexed-channel signals input to the transmitter is small, and the bandwidth of FM signal frequency modulated as a single unit is reduced.
In an optical transmission system according to the invention, the signal level adjusting means is equipped with an amplifier for amplifying multiplexed-channel signals and an attenuator for attenuating while adjusting the output of the amplifier. Through such a system configuration, the bandwidth of FM signal can be enlarged and the distortion caused by a ripple-shaped group delay deviation in a transmitter, a receiver and optical transmission link can be reduced by increasing the level per waveform of multiplexed-channel signals based on the output of the amplifier when FDM multiplexed-channel signals are transmitted from the transmitter to the receiver through an optical link, even in the case where the number of channels for frequency-division-multiplexed multiplexed-channel signals input to the transmitter is small, and the bandwidth of FM signal frequency modulated as a single unit is reduced.
In an optical transmission system according to the invention, the signal level adjusting means is used to manually adjust the input level of the FDM multiplexed-channel signals based on the number of channels for the FDM multiplexed-channel signals. Through such a system configuration, the bandwidth of FM signal can be enlarged and the distortion caused by a ripple-shaped group delay deviation of a transmitter, a receiver and optical transmission link can be reduced by manually adjusting the level in waveform of FDM multiplexed-channel signals when they are transmitted from the transmitter to the receiver through the optical link, even in the case where the number of channels for frequency-division-multiplexed multiplexed-channel signals input to the transmitter is small, and the bandwidth of FM signal frequency modulated as a single unit is reduced.
In an optical transmission system according to the invention, the transmitter comprises a bandwidth detector for detecting the bandwidth of the FM signal. Through such a system configuration, the bandwidth of FM signal can be enlarged and the distortion caused by a ripple-shaped group delay deviation of signals transmitted from a transmitter, a receiver and optical transmission link can be reduced by detecting the bandwidth of FM signal whose input level is adjusted to enlarge the bandwidth of the FM signal when signals are transmitted from the transmitter to the receiver through an optical channel, even in the case where the number of channels for frequency-division-multiplexed multiplexed-channel signals input to the transmitter is small, and the bandwidth of FM signal frequency modulated as a single unit is reduced.
An optical transmitter according to the invention comprises a transmitter for transmitting optical signals based on the input frequency-division-multiplexed multiplexed-channel signals, the transmitter comprising signal level adjusting means for reducing the distortion caused by a ripple-shaped group delay deviation in the transmitter, the receiver and the optical transmission link in transmitting optical signals from the transmitter to the receiver, and for adjusting the level of transmit signals depending on the increase/decrease in the number of channels for FDM multiplexed-channel signals to keep constant of the bandwidth of the FM signal. Through such a system configuration, the bandwidth of FM signal can be enlarged and the distortion caused by a ripple-shaped group delay deviation of signals transmitted from a transmitter to a receiver can be reduced to transmit the multiplexed-channel signals with good signal quality, by adjusting to increase the level per waveform of multiplexed-channel signals through signal level adjusting means, even in the case where the number of channels for frequency-division-multiplexed multiplexed-channel signals input to the transmitter is small, and the bandwidth of FM signal frequency modulated as a single unit is reduced.
In an optical transmitter according to the invention, the transmitter is equipped with a general FM modulator for frequency modulating the multiplexed-channel signals as a single unit. Through such a system configuration, the bandwidth of FM signal can be enlarged and the distortion caused by a ripple-shaped group delay deviation of signals transmitted from a transmitter to a receiver can be reduced to transmit multiplexed-channel signals with good signal quality, by increasing the level per waveform of multiplexed-channel signals when signals are transmitted from the transmitter to the receiver through an optical channel, even in the case where the number of channels for frequency-division-multiplexed multiplexed-channel signals input to the transmitter is small, and the bandwidth of FM signal frequency modulated as a single unit is reduced.
In an optical transmitter according to the invention, the signal level adjusting means is equipped with an amplifier for amplifying the multiplexed-channel signals and an attenuator for attenuating while adjusting the output of the amplifier. Through such a system configuration, the bandwidth of FM signal can be enlarged and the distortion caused by a ripple-shaped group delay deviation of signals transmitted from a transmitter to a receiver can be reduced by increasing the level per waveform of multiplexed-channel signals based on the output of the amplifier when signals are transmitted from the transmitter to the receiver through an optical channel, even in the case where the number of channels for frequency-division-multiplexed multiplexed-channel signals input to the transmitter is small, and the bandwidth of FM signal frequency modulated as a single unit is reduced.
In an optical transmitter according to the invention, the signal level adjusting means is used to manually adjust the input level of multiplexed-channel signals based on the number of channels for the multiplexed-channel signals. Through such a system configuration, the bandwidth of the FM signal can be enlarged and the distortion caused by a ripple-shaped group delay deviation of signals transmitted from a transmitter to a receiver can be reduced by manually adjusting the level per waveform of FDM multiplexed-channel signals when they are transmitted from the transmitter to the receiver through an optical transmission link, even in the case where the number of channels for frequency-division-multiplexed FDM multiplexed-channel signals input to the transmitter is small, and the bandwidth of FM signal frequency modulated as a single unit is reduced.
In an optical transmitter according to the invention, the transmitter comprises a bandwidth detector for detecting the bandwidth of FM signal. Through such a system configuration, the bandwidth of FM signal can be enlarged and the distortion caused by a ripple-shaped group delay deviation in a transmitter, a receiver and the optical transmission link can be reduced by detecting the bandwidth of FM signal whose input level is adjusted to enlarge the bandwidth of the FM signal when FDM signals are transmitted from the transmitter to the receiver through an optical transmission link, even in the case where the number of channels for frequency-division-multiplexed multiplexed-channel signals input to the transmitter is small, and the bandwidth of FM signal frequency modulated as a single unit is reduced.

Optical transmission system and optical transmission apparatus used therefor

Matsushita Electric Industrial Co., Ltd.


An aircraft energy management system including a cabin air compressor adapted to be coupled to a source of fan discharge air at a first pressure during an inflight operating mode and adapted to be coupled to a ram intake air during a ground operating mode. The system further including an environmental control system mechanically coupled to a compressor exit of the cabin air compressor. The aircraft energy management system configured to provide a conditioned fluid flow to an aircraft cabin, cockpit or de-icing system.

Embodiments disclosed herein relate generally to aircraft energy management systems including environmental control systems and more particularly to methods and apparatus for extracting fan discharge air to boost an aircraft environmental control system.
Turbine-powered aircraft conventionally incorporate environmental control systems (ECS) which control aircraft cabin temperature by the amount and temperature of a bleed air extracted from an engine. Historically, ECS have used engine bleed air that is extracted from a high pressure compressor (HPC) or is generated by means of a compressor that is driven by an auxiliary gas turbine ("APU"), throttled (pressure reduced), and cooled by a heat exchanger ("precooler") using fan bleed air. Bleed air is also used to provide anti-icing to the aircraft, and must be at high temperature for this purpose—typically about 204° C. (400° F.).
Aircraft weight is a current concern in the current industry, with a decrease in aircraft weight resulting in an efficiency increase. In light of the concern, future aircraft will replace some or all of their metallic structures with composite materials to reduce weight and improve overall efficiency. These structures have limited temperature capability compared to metal alloys. For example, a typical carbon-fiber composite material may have a temperature limit substantially below 93° C. (200° F.). Conventional ECS interfaces, utilizing engine bleed air cannot meet this requirement without significantly increasing the size of an included precooler. Furthermore, composite aircraft will often use electrically powered anti-ice systems and therefore do not require high temperature bleed air.
One way ECS requirements have been met in composite aircraft, is by using electrically driven ECS to pressurize and condition ambient air. While effective to provide low-pressure, low-temperature bleed air, this requires a separate air inlet to efficiently entrain ambient fresh air, an additional air intake for cooling and considerable electrical power to drive the ECS compressors. The electrical power requirements can require an undesirable increase in the size of the engine mounted generators. In addition, the air intakes will produce drag on the aircraft, translating to an increase in fuel burn and therefore cost of operation. These weight and drag penalties of electrically driven ECS are also of concern in smaller aircraft.
Accordingly, there is a need for an improved environmental control system and method for extracting engine discharge air that will reduce aircraft weight and minimize drag air penalties.

Aircraft energy management system including engine fan discharge air boosted environmental control system


An energy storage module in which a plurality of energy storage cells including electrode terminals are stacked, includes a bus bar that electrically connects a plurality of electrode terminals, a conductive member that is secured on the bus bar, a detection section that detects a voltage of each of the energy storage cells, and a wiring board, a wire that is electrically connected to the detection section, and a pad that is connected to the wire being formed on the wiring board, the conductive member coming in contact with the pad.

A stacked (laminated) assembled battery has been known in which a plurality of battery cells are connected in series to achieve a high output (see JP-A-2011-23179).
A plurality of battery cells included in such a stacked assembled battery may differ in output voltage during discharge due to the difference in temperature or the like between the battery cells. Therefore, a detection section that detects the output voltage of each battery cell is provided in an assembled battery. The detection section is electrically connected to the electrode terminals of the battery cells through a wire harness, for example.

Energy storage module including conductive member secured on bus bar and in contact with pad of wiring board


A preparation for topical treatment of infections caused by virus, bacteria and fungi, said preparation contains pentane diol or hexane diol as active substance.

The present invention refers to a preparation for topical treatment of infections caused by virus, bacteria and fungi.
Diols or glycols are used as solvents, as anti-freezing agents or as vehicles in pharmaceutical preparations and some of them have an antimicrobial effect. A laboratory study of certain diols showed that the antimycotic activity was increased with an increasing length of the carbon chain.
So far propane-1,2-diol is the only diol widely used in dermatology. It is used in the treatment of Pityriasis versicolor, Pityrosporum folliculitis and Seborrhoeic dermatitis. It has even been active against Influenza A virus in vitro.
Certain laboratory tests indicate that pentane-1-5-diol has a higher activity against both fungi and bacteria than propane-1,2-diol (Faergemann et al: The antimycotic activity of five diols. Saubouradia 18:287-293, 1980). Nothing is however known about its effect in clinical treatment of infections caused by fungi and bacteria and nothing is known about its activity against virus, as far as we know. further has a low oral toxicity and is non-irritating to the skin.
There is today no effective topical treatment available for the treatment of recurrent herpes labialis. Acyclovir given orally is effective but no effective topical formulation has been found so far.

Preparation of topical treatment of infections caused by virus, bacteria and fungi