The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity. While the present disclosure is directed to a complex system which includes a number of features, the present application is particularly directed to the structure and linking of a plurality of almost identical processing elements.

The present application is directed to a method and apparatus for performing encryption and decryption. The application discloses several inventions relating to an overall system for the use of exponentiation modulo N as a mechanism for carrying out the desired cryptological goals and functions in a rapid, efficient, accurate and reliable manner. A first part of the disclosure is related to the construction of a method and its associated apparatus for carrying out modular multiplication. A second part of the disclosure is directed to an improved apparatus for carrying out modular multiplication through the partitioning of the problem into more manageable pieces and thus results in the construction of individual identical (if so desired) Processing Elements. A third part of the disclosure is directed to the utilization of the resulting series of Processing Elements in a pipelined fashion for increased speed and throughput. A fourth part of the disclosure is directed to an apparatus and method for calculating a unique inverse operation that is desirable as an input step or stage to the modular multiplication operation. A fifth part of the disclosure is directed to the use of the modular multiplication system described herein in its originally intended function of performing an exponentiation operation. A sixth part of the disclosure is directed to the use of the Chinese Remainder Theorem in conjunction with the exponentiation operation. A seventh part of the this disclosure is directed to the construction and utilization of checksum circuitry which is employed to insure reliable and accurate operation of the entire system. The present application is particularly directed the invention described in the second part of the disclosure.
More particularly, the present invention is directed to circuits, systems and methods for multiplying two binary numbers having up to n bits each with the multiplication being modulo, N an odd number. In particular, the present invention partitions one of the factors into m blocks with k bits in each block with the natural constraint that mkxe2x89xa7n+2. Even more particularly, the present invention is directed to multiplication modulo N when the factors being multiplied have a large number of bits. The present invention is also particularly directed to the use of the modular multiplication function hardware described herein in the calculation of a modular exponentiation function for use in cryptography. Ancillary functions, such as the calculation of a convenient inverse and a checksum mechanism for the entire apparatus are also provided herein. The partitioning employed herein also results in the construction of Processing Elements which can be cascaded to provide significant expansion capabilities for larger values of N. This, in turn, leads to a modality of Processor Element use in a pipelined fashion. The cascade of Processor Elements is also advantageously controllable so as to effectively partition the Processor Element chain into separate pieces which independently work on distinct and separate factors of N.
Those wishing an optimal understanding from this disclosure should appreciate at the outset that the purpose of the methods and circuits shown herein is the performance of certain arithmetic functions needed in modem cryptography and that these operations are not standard multiplication, inversion and/or exponentiation, but rather are modulo N operations. The fact that the present application is directed to modular arithmetic circuits and methods, as opposed to standard arithmetic operations, is a fact which would be best to keep firmly in mind, particularly since modular arithmetic, with it implied division operations, is much more difficult to perform and to calculate, particularly where exponentiation modulo N is involved.
In a preferred system for implementation which takes advantage of certain aspects of the present invention, this application is also directed to a circuit and method of practice in which an adder array and a multiplier array are effectively partitioned into in a series of nearly identical processor elements with each processor element (PE) in the series operating on a sub-block of data. The multiplier array and adder array are thus partitioned. Thus, having recognized the ability to reconfigure the generic structure into a plurality of serially connected processor elements, the present invention is also directed to a method of operation in which each processor element operates as part of a pipeline over a plurality of operational cycles. The pipelining mode of operation is even further extended to the multiplication of a series of numbers in a fashion in which all of the processor elements are continuously actively generating results.
The multiplication of binary numbers module N is an important operation in modem, public-key cryptography. The security of any cryptographic system which is based upon the multiplication and subsequent factoring of large integers is directly related to the size of the numbers employed, that is, the number of bits or digits in the number. For example, each of the two multiplying factors may have up to 1,024 bits. However, for cryptographic purposes, it is necessary to carry out this multiplication modulo a number N. Accordingly, it should be understood that the multiplication considered herein multiplies two n bit numbers to produce a result with n bits or less rather than the usual 2 n bits in conventional multiplication.
However, even though there is a desire for inclusion of a large number of bits in each factor, the speed of calculation becomes significantly slower as the number of digits or bits increase. However, for real-time cryptographic purposes, speed of encryption and decryption are important concerns. In particular, real-time cryptographic processing is a desirable result.
Different methods have been proposed for carrying out modular multiplication. In particular, in an article appearing in xe2x80x9cThe Mathematics of Computation,xe2x80x9d Vol. 44, No. 170, April 1985, pp. 519-521, Peter L. Montgomery describes an algorithm for xe2x80x9cModular Multiplication without Trial Division.xe2x80x9d However, this article describes operations that are impractical to implement in hardware for a large value of N. Furthermore, the method described by Montgomery operates only in a single phase. In contrast, the system and method presented herein partitions operational cycles into two phases. From a hardware perspective, the partitioning provides a mechanism for hardware sharing which provides significant advantages.
In accordance with a preferred embodiment of the present invention, an initial zero value is stored in a result register Z0. The integers A and B which are to be multiplied using the present process are partitioned into m blocks with k bits in each block. The multiplication is carried out modulo N. Additionally, the value R is set equal to 2k. In this way, the integer A is representable as A=Amxe2x88x921Rmxe2x88x921+ . . . +A2R2+A1R2+A0. This is the partitioning of the integer A into m blocks.
In one embodiment of the present invention, a method and circuit are shown for computing a function Z=f(Ai B)=AB 2xe2x88x92mk mod N. Later, it will be shown how this function is used to calculate AB mod N itself.
The system, methods, and circuits of the present invention are best understood in the context of the underlying algorithm employed. Furthermore, for purposes of understanding this algorithm, it is noted that modular computation is carried out modulo N, which is an odd number and n is the number of bits in the binary representation of N. Additionally, N0 represents the least significant k bits of N. Also, a constant s is employed which is equal to xe2x88x921/N0 mod R=1(Rxe2x88x92N0) mod R. With this convention, the algorithm is expressed in pseudo code as follows:
Z0=0
for i=0 to mxe2x88x921
Xi=Zi+AiB
yi=s xi, 0 mod R (x i, 0 is the least significant k bits of Xi)
Zi+1=(Xi+yiN)/R
end.
There are two items to note in particular about this method for carrying out modulo N multiplication. The first thing to note is that the multiplication is based upon a partitioning of one of the factors into sub-blocks with k bits in each block. This greatly simplifies the size of multiplier arrays which need to be constructed. It furthermore creates a significant degree of parallelism which permits the multiplication operation be carried out in a much shorter period of time. The second item to note is that the partitioning also results in the splitting of the process not only into a plurality of m cycles, but also, splits the method into two phases that occur in each cycle. In the first phase (X-phase), the values Xi and yi are computed. In the second phase (Z-phase), the intermediate result value Zi+1 is calculated. It should be noted that, in the calculation of Xiand in the calculation of Zi+1, there is an addition operation and a multiplication operation. This fact allows the same hardware which performs the multiplication and addition in each of these steps to be shared rather than duplicated. With respect to the division by R in the formation of Zi+1, it is noted that this is accomplishable by simply discarding the low order k bits. Other advantages of this structure will also become apparent.
The output of the above hardware and method produces the product AB 2xe2x88x92mk mod N. To produce the more desirable result AB mod N, the method and circuit employed above is used a second time. In particular, the original output from this circuit is supplied to one of its input registers with the other register containing the factor 22mk mod N. This factor eliminates the first factor of 2xe2x88x92mk added during the first calculation and also cancels the additional factor of 2xe2x88x92mk included when the circuit is run the second time. This produces the result AB mod N.
For those who wish to practice the processes of the present invention via software, it is noted that the algorithm for multiplication provided above is readily implementable in any standard procedure-based programming language with the resulting code, in either source or object form, being readily storable on any convenient storage medium, including, but certainly not limited to, magnetic or optical disks. This process is also eminently exploitable along with the use of the exponentiation processes described below, including processes for exponentiation based on the Chinese Remainder Theorem.
In the process described above it is noted that one of the process inputs is the variable xe2x80x9csxe2x80x9d. This value is calculated as a negative inverse modulo R. In order to facilitate the generation of this input signal, a special circuit for its generation is described herein. This circuit also takes advantage of existing hardware used in other parts of a processing element. In particular, it forms a part of the rightmost processor element in a chain.
Note that, in the calculation shown above for Xi and Zi, these are more than n bit numbers. Accordingly, the multiplication and addition operations are carried out in relatively large circuits which are referred to herein as multiplier and adder arrays. In accordance with a preferred method of practicing the present invention, the adder array and multiplier array are split into sub-blocks. While this partitioning of hardware may be done using any convenient number of blocks, partitioning into blocks capable of processing k bits at a time is convenient. Thus, in the preferred embodiment, instead of employing one large multiplier array for processing two numbers having n+1 bits and k bits; with n being much greater than k, a plurality of separate k bit by k bit multipliers are employed. Additionally, it is noted that partitioning into processor element sub-blocks, while useful in and of itself particularly for circuit layout efficiency, also ultimately makes it possible to operate the circuit in several pipelined modes.
In a first pipelined mode, the circuit is operated through a plurality of cycles, m, in which adjacent processor elements are operated in alternate phases. That is, in a first pipelined mode, if a processor element is in the X-phase, its immediate neighbors are operating in the Z-phase, and vice versa. In a second pipelined mode, the pipelined operation is continued but with new entries in the input registers (A and B) which now are also preferably partitioned in the same manner as the multiplier and adder arrays.
Since n is generally much greater than k (1,024 as compared to 32, for example) and since carry propagation through adder stages can contribute significantly to processing delays, the partitioning and pipelining together eliminate this source of circuit delay and the corresponding dependence of circuit operation times on the significant parameter n whose size, in cryptographic contexts, determines the difficulty of unwarranted code deciphering.
The pipelined circuit of the present invention is also particularly useful in carrying out exponentiation modulo N, an operation that is also very useful in cryptographic applications. Such an operation involves repeated multiplication operations. Accordingly, even though pipelining may introduce an initial delay, significant improvements in performance of exponentiation operations are produced.
In one embodiment found within the disclosure herein it has been noted that the chaining together of individually operating Processing Elements introduces an addition operation in a critical timing path, that is, into a path whose delayed execution delays the whole process. The present invention provides an improvement in the design of the individual Processing Elements through the placement of this addition operation in an earlier portion of the Processing Element""s operation. In doing so, however, new control signals are also provided to make up for the fact that some signals in some of the Processing Elements are not yet available at this earlier stage and accordingly are, where convenient, provided from operations occurring or which have already occurred in adjacent Processing Elements.
The Processing Elements used herein are also specifically designed so that they may function in different capacities. In particular, it is noted that the rightmost Processing Element performs some operations that are unique to its position as the lower order Processing Element in the chain. Likewise the leftmost element has a unique role and can assume a simpler form. However, the Processing Elements employed herein are also specially designed and constructed so as to be able to adapt to different roles in the chain. In particular, the middle Processing Element is controllable so that it takes on the functional and operational characteristics of a rightmost Processing Element. In this way the entire chain is partitionable so that it forms two (or more, if needed) separate and independent chains operating (in preferred modalities) on factors of the large odd integer N.
While an intermediate object of the present invention is the construction of a modular multiplication engine, a more final goal is providing an apparatus for modular exponentiation. In the present invention this is carried out using the disclosed modular multiplier in a repeated fashion based on the binary representation of the exponent. A further improvement on this process involves use of the Chinese Remainder Theorem for those parts of the exponentiation operation in which the factors of N are known. The capability of the Processing Element chain of the present invention to be partitioned into two portions is particularly useful here since each portion of the controllably partitioned chain is able to work on each of the factors of N in an independent and parallel manner.
Since one wishes to operate computational circuits at as high a speed as possible and since this can some times lead to erroneous operations, there is provided a challenge in how to detect errors when the operations being performed are not based on standard arithmetic, but are rather based on modular arithmetic (addition, subtraction, inversion and multiplication and exponentiation). However, the present invention solves this problem through the use of circuits and methods which are not only consonant with the complicating requirements of modular arithmetic operations but which are also capable of being generated on the fly with the addition of only a very small amount of additional hardware and with no penalty in time of execution or throughput.
Accordingly, it is seen that it is an object of the present invention to produce a multiplier for multiplying two large integers modulo N.
It is yet another object of the present invention to improve the performance and capabilities of cryptographic circuits and systems.
It is a still further object of the present invention to create a multiplier circuit which operates at high speed.
It is yet another object of the present invention to create a multiplier circuit which performs multiplication modulo N without having to perform division operations.
It is also an object of the present invention to provide a multiplier which is scaleable for various values of N and n.
It is also another object of the present invention to provide a method for computing a product of two integers modulo N in a multi-phase process which permits sharing of hardware circuitry across the two phases.
It is yet another object of the present invention to provide a system and method in which the factors are partitioned into a plurality of m sub-blocks with each sub-block having k bits, whereby values for m and k are selectable so as to provide additional flexibility in hardware structure.
It is also another object of the present invention to increase the speed of multiplication calculations in cryptographic processes.
It is also an object of the present invention to provide an implementation for a multiplier circuit which uses macro components as building blocks so as to avoid the costs associated with custom design.
It is also an object of the present invention to provide a design which is flexible and scaleable.
It is also an object of the present invention to provide a word-oriented, as opposed to a bit-oriented, multiplication system and circuit.
It is a still further object of the present invention to construct a circuit for multiplication modulo N which comprises a plurality of nearly identical processor elements.
It is yet another object of the present invention to partition the multiplication of an n bit number into a plurality of pieces for quasi-independent calculation.
It is still another object of the present invention to operate the circuit herein in a pipelined mode.
It is an even further object of the present invention to operate the circuit herein so as to process sequences of distinct operands (factors) in a pipelined mode.
It is yet another object of the present invention to improve the performance of a sequence of chained Processing Elements by removing addition functions from critical paths.
It is a still further object of the present invention to operate the circuit herein so as to process sequences of identical or repeated operands in a pipelined mode, as for example, in the calculation of the exponential function modulo N.
It is yet another object of the present invention to increase the speed of exponentiation operations in cryptographic processes.
It is a still further object of the present invention to provide Processing Elements whose character as beginning, middle or end units in the chain may be controlled so as to enable the partitioning of the chain into a plurality of sub-chains each of which is capable of independent parallel processing based on a factor of N.
It is also an object of the present invention to provide a mechanism for calculating an inverse operation which is useful as an input to the method of modular multiplication employed herein.
It is yet another object of the present innovation to provide an apparatus and method for generating useful checksums which are useful for indicating that the system has operated in a proper fashion and has produced no errors.
It is a still further object of the present invention to provide a checksum circuit and method which is consonant with modular arithmetic.
It is also an object of the present invention to provide an engine which is capable of data encryption through the use of exponentiation modulo N, a large prime or the product of two large primes.
It is a further object of the present invention to provide an engine which is capable of data decryption through the use of exponentiation modulo N.
It is yet another object of the present invention to employ the Chinese Remainder Theorem to facilitate the exponentiation operation modulo N when factors for N are known.
It is also an object of the present invention to provide an encryption/decryption engine which is capable of operating in the mode of public key cryptographic systems.
It is also an object of the present invention to provide an engine which is capable of generating and receiving documents having coded digital signatures.
It is also an object of the present invention to provide an engine which is capable of generating keys to be exchanged between any two users for data encryption and decryption.
It is also an object of the present invention to produce a high-speed, high-performance cryptographic engine.
Lastly, but not limited hereto, it is an object of the present invention to provide a cryptographic engine for encryption and for decryption which can be included as part of a larger processing system and therefore possesses communication capabilities for the transfer of data and command information from other parts of a larger scale data processing system with which the present engine is coupled.
The recitation herein of a list of desirable objects which are met by various embodiments of the present invention is not meant to imply or suggest that any or all of these objects are present as essential features, either individually or collectively, in the most general embodiment of the present invention or in any of its more specific embodiments.

Hardware implementation for modular multiplication using a plurality of almost entirely identical processor elements

International Business Machines Corporation


There is provided a process for producing alkylaromatics, especially ethylbenzene and cumene, wherein a feedstock is first fed to a transalkylation zone and the entire effluent from the transalkylation zone is then cascaded directly into an alkylation zone along with an olefin alkylating agent, especially ethylene or propylene.

There is provided a process for producing alkylaromatics, especially ethylbenzene and cumene, wherein a feedstock is first fed to a transalkylation zone and the entire effluent from the transalkylation zone is then cascaded directly into an alkylation zone along with an olefin alkylating agent, especially ethylene or propylene.
Ethylbenzene is a valuable commodity chemical which is currently used on a large scale industrially for the production of styrene monomer. Ethylbenzene may be produced by a number of different chemical processes but one process which has achieved a significant degree of commercial success is the vapor phase alkylation of benzene with ethylene in the presence of a solid, acidic ZSM-5 zeolite catalyst. In the commercial operation of this process, the polyalkylated benzenes, including both polymethylated and polyethylated benzenes are recycled to the alkylation reactor in which the reaction between the benzene and the ethylene takes place. By recycling the by-products to the alkylation reaction, increased conversion is obtained as the polyethylated benzenes (PEB) are converted to ethylbenzene (EB). In addition, the presence of the PEB during the alkylation reaction reduces formation of these species through equilibration of the components because at a given feed composition and under specific operating conditions, the PEB recycle will reach equilibrium at a certain level. This commercial process is known as the Mobil/Badger process and is described in more detail in an article by Francis G. Dwyer, entitled "Mobil/Badger Ethylbenzene Process-Chemistry and Catalytic Implications", appearing on pages 39-50 of a book entitled Catalysis of Organic Reactions, edited by William R. Moser, Marcel Dekker, Inc., 1981.
Ethylbenzene production processes are described in U.S. Pat. Nos. 3,751,504 (Keown), 4,547,605 (Kresge), and 4,016,218 (Haag); reference is made to these patents for a detailed description of such processes. The process described in U.S. Pat. No. 3,751,504 is of particular note since it includes a separate transalkylation step in the recycle loop which is effective for converting a significant proportion of the more highly alkylated products to the desired ethylbenzene product. Other processes for the production of ethylbenzene are disclosed in U.S. Pat. Nos. 4,169,111 (Wight) and 4,459,426 (Inwood), in both of which a preference for large-pore size zeolites such as zeolite Y is expressed, in distinction to the intermediate-pore size zeolites used in the processes described in the Keown, Kresge and Haag patents. U.S. Pat. No. 3,755,483 (Burress) describes a process for the production of ethylbenzene using zeolite ZSM-12 as the alkylation catalyst.
Ethylbenzene (EB) can be synthesized from benzene and ethylene (C.sub.2 =) over a variety of zeolitic catalysts in either the liquid phase or in the vapor phase. An advantage of a liquid phase process is its low operating temperature and the resulting low content of by-products. For example, U.S. Pat. No. 4,891,458 describes the liquid phase synthesis of ethylbenzene with zeolite Beta.
To minimize polyalkylation and other undesirable side reactions, production of such alkylaromatics as ethylbenzene and cumene typically operates with high ratios of aromatic (e.g., benzene) to alkylating agent (e.g., ethene) in the feed to the alkylation reactor. Zeolite-catalyzed processes generally operate at aromatic/olefin (A/O) molar feed ratios of three or above, while processes catalyzed by AlCl.sub.3 or supported phosphoric acid often operate at A/O's of three and below. However, in both cases polyalkylated aromatics (e.g., diethylbenzenes) are produced at levels that prohibit simply disposing of them as waste. These polyalkylated aromatics are instead reacted further with feed aromatic to form additional monoalkylate via transalkylation reactions. In the case of zeolite-catalyzed alkylaromatic processes, this transalkylation may take place in the alkylation reactor (as in the case of the Mobil/Badger process discussed above) or may take place in a separate transalkylation reactor, with the effluent from the transalkylation reactor being combined with the alkylation reactor effluent and sent to product recovery.


A method of fabricating an ultrasonic coupler to a specified configuration such that the ultrasonic coupler is fabricated by freezing and defrosting an aqueous solution containing a polymer. A surface of the fabricated ultrasonic coupler is made to be smooth. The ultrasonic coupler is fabricated using an ultrasonic coupler fabricating die including members each made of silicone rubber which varies in compliance with the expansion and the contraction of the aqueous solution. To fabricate the ultrasonic coupler, the aqueous solution containing a polyvinyl alcohol (PVA) is poured into the die. Then, the die is subjected to the process of cooling to below the freezing point and the process of recovery to room temperature so as to progress a bridging of the PVA, thereby progressing a gelling of the aqueous solution.

1. Field of the Invention
The present invention relates to a method of fabricating an ultrasonic coupler which is interposed between an ultrasonic probe and an object to be observed with the use of an ultrasonic diagnostic system.
2. Description of the Related Art
There has been generally used an ultrasonic diagnostic system for displaying a tomographic image of the human body utilizing ultrasounds. Now, referring to the drawings, there will be explained a case where such an ultrasonic diagnostic system is used to observe diagnostic portions of the human body, for example, a thyroid gland, a carotid artery, and a mammary gland, which all exist near the body surface.
FIG. 7 is a view schematically showing a state in which an ultrasonic probe for transmission and reception of ultrasounds directly contacts with the body surface. FIG. 8 is a view schematically showing a state wherein an ultrasonic coupler, which is sufficiently conductive in ultrasound, is placed between an ultrasonic probe and the body surface.
As shown in FIG. 7, in a case where an ultrasonic probe 10 directly contacts the body surface 12, a convergent point of an ultrasonic beam 14 is given by a position 16 which is placed at a distance from the body surface 12. Consequently, when a diagnostic portion 18, which exists near the body surface 12, is observed, a resolving power will degrade. Thus, in such a case, in order to contribute to an enhancement of the resolving power, it is so designed, as shown in FIG. 8, that an ultrasonic coupler 20 is placed between the ultrasonic probe 10 and the body surface 12, so that the ultrasonic beam 14 can be converged on the neighborhood of the diagnostic portion 18.
Such an ultrasonic coupler is made of a non-hydrous gel substance consisting of a urethane rubber, a silicone rubber or the like, and alternatively, a polymer hydrous gel substance such as a polyvinyl alcohol (PVA), a polyvinyl pyrrolidone (PVP), a polyethylene oxide (PEO) and the like.
In case of the use of the non-hydrous gel substance for the ultrasonic coupler, the ultrasounds transmitted from an ultrasonic probe will be attenuated during passing through the ultrasonic coupler made of the non-hydrous gel substance, since the attenuation of the ultrasounds is generally large (approximately, 2 dB/cm/MHz) within the non-hydrous gel substance. Consequently, the ultrasounds hardly enter the object to be monitored. Similarly, the ultrasounds reflected by the inner observed object will be also attenuated during passing through the ultrasonic coupler. Thus, it will be a cause of deterioration of the ultrasound signal to noise ratio (S/N).
On the other hand, in case of the use of the ultrasonic coupler made of the polymer hydrous gel substance, it is possible to implement a high S/N, since the attenuation of the ultrasounds is extremely small (approximately, 0.1 db/cm/MHz) within the polymer hydrous gel substance. However, if such an ultrasonic coupler is left in an atmosphere, water evaporates and it will spoil the function of the ultrasonic coupler. Therefore, it is necessary to preserve the ultrasonic coupler in a sealed vessel when it is not used. Further, such an ultrasonic coupler easily slips and it is difficult to hold by hand. In view of the foregoing, there is used an ultrasonic coupler 24, as shown in FIG. 9, on which connection members 22 for connecting the coupler with the ultrasonic probe 10 are fixed. An aqueous solution containing a PVA among the polymer hydrous gel substance has such a characteristic that when the aqueous solution is frozen below the freezing point and defrosted at the room temperature, a bridging between molecules progresses thereby, gelling. A repetition of freezing and defrosting advances an additional bridging (refer to Japanese Patent Publication No. Sho. 47-12854). The gelling substance (PVA gel) has an excellent mechanical characteristic in points of a high tearing strength, and a full elasticity. Thus, the gelling substance is suitable for the ultrasonic coupler.
Next , referring to the drawings, there will be explained a method of fabricating an ultrasonic coupler, which is made of an aqueous solution containing the PVA, among methods of fabricating an ultrasonic coupler.
FIGS. 10A-10F are sectional views showing steps of fabricating an ultrasonic coupler.
First, as shown in FIG. 10A, a specified configuration of die 30 is prepared. Next, as shown in FIG. 10B, an aqueous solution 34 containing the PVA is poured from an inlet 32 of the die 30 into the die 30. After pouring the aqueous solution 34, it is frozen below the freezing point. The aqueous solution 34 will increase in volume about 10% when frozen. Consequently, as shown in FIG. 10C, for example, it will happen that a parting segment 36 of the die 30 is destroyed, or expanded portions are formed. As a result, as shown in FIG. 10D, a gel 38 having a projection 40 is made up. The steps of FIGS. 10C and 10D are repeatedly performed. Thereafter, as shown in FIG. 10E, the gel 38 is separated from the die. Finally, as shown in FIG. 10F, the expanded portion or the projection 40 is excised so as to reshape into a specified configuration of ultrasonic coupler 44.
As described above, since the aqueous solution containing the PVA will increase in volume about 10% when frozen, according to the above described fabrication method, there will be formed the projections due to gelling. Thus, it is necessary to excise or remove the projections and it will be troublesome. Further, a surface, which is formed by removal of projections, will be poor in smoothness. If such a surface is in contact with a body surface or an ultrasonic probe, it will be a cause of a large attenuation of the ultrasounds.

Method of fabricating ultrasonic coupler


Contents of a text processing job is not pre-traced, and at a stage of processing a drawing object, a CLUT combination relating thereto is determined to be ON/OFF. A plurality of drawing objects are associated with a set of CLUT combination, and a CLUT combination which has been once ON is maintained as is ON.

1. Field of the Invention
The present invention relates to an image processing apparatus and an image processing method which can shorten a processing time required when a color conversion is carried out for outputting an input image.
2. Description of the Related Art
When text data including a color image is printed out, color conversion from original data (an input image) into CMYK data for a printer is executed by referring to a look-up table in a color profile (CLUT).
For example, in Jpn. Pat. Appln. KOKAI Publication No. 2003-219193, there is shown an example in which first color conversion means for carrying out color conversion from medium data thereof into data for another medium, and second color conversion means for carrying out color conversion data from another medium into data for the apparatus thereof are provided, and the both have a reversible relationship.
However, there is no description relating to the reduction in the time needed for the color conversion itself.

Method and apparatus for color transformation (conversion)


A type of a request that is currently being processed at a system is determined. A distribution is selected from a set of processing time distributions, the distribution forming a model that is applicable to the type. A threshold point is computed for the model. A processing time that exceeds a threshold point processing time is regarded as exhibiting tail latency. Tail latency includes a delay in processing of the request due to a reason other than a utilization of a resource of the system exceeding a threshold utilization and a size of a queue in the system exceeding a threshold size. An evaluation is made that the request will experience tail latency during processing at the system and the processing of the request at the system is aborted. The request is offloaded for processing at a peer system in a load-balanced group of systems.

In a load-balanced configuration, a load-balancer system receives requests for service from numerous client systems. Depending on the load-balancing algorithm used therein, the load-balancer sends a received request to one of the systems participating in the load-balanced group of systems serviced by the load-balancer. The system that receives the request from the load-balancer processes the request, or queues the request for processing, depending on the conditions and configuration of the system.
Presently, if a system in a load-balanced group has excessive utilization of the processor, the memory, the network bandwidth, the electrical power, or some other computing resource, the system can offload the request to another peer system in the group. Such presently available offloading is dependent only upon the utilization-related conditions of one or more computing resources in system.
Some other presently available offloading algorithms look at the number of requests pending in a queue in the system. When that queue-size exceeds a threshold, the presently available offloading algorithm offloads one or more requests from the queue to shorten the queue. A request is interchangeably referred to herein as a "job" unless expressly distinguished where used.

Tail latency-based job offloading in load-balanced groups

INTERNATIONAL BUSINESS MACHINES CORPORATION


A multipoint control unit (MCU) or other digital video-processing apparatus operates to manipulate compressed digital video from several compressed digital video sources. The apparatus has a plurality of video input modules and a plurality of video output module. Each of the video input modules receives a compressed video signal from one of the sources and generally decodes the data into a primary data stream and a secondary data stream. The video output module receives the primary and secondary data streams, from at least one of the input module for generally encoding to a compressed output stream for transmission.

In video communication, e.g., video conferencing, Multipoint Control Units (xe2x80x9cMCU""sxe2x80x9d) serve as switches and conference builders for the network. The MCU""s receive multiple audio/video streams from the various users"" terminals, or codecs, and transmit to the various users"" terminals audio/video streams that correspond to the desired signal at the users"" stations. In some cases, where the MCU serves as a switchboard, the transmitted stream to the end terminal is a simple stream from a single other user. In other cases, it is a combined xe2x80x9cconferencexe2x80x9d stream composed of a combination of several users"" streams.
An important function of the MCU is to translate or manipulate the input streams into the desired output streams from all and to all codecs. One aspect of this xe2x80x9ctranslationxe2x80x9d is a modification of the bit-rate between the original stream and the output stream. This rate matching modification can be achieved, for example, by changing the frame rate, the spatial resolution, or the quantization accuracy of the corresponding video. The output bit-rate, and thus the modified factor used to achieve the output bit rate, can be different for different users, even for the same input stream. For instance, in a four party conference, one of the parties may be operating at 128 Kbps, another at 256 Kbps, and two others at T1. Each party needs to receive the transmission at the appropriate bit rate. The same principles apply to xe2x80x9ctranslation,xe2x80x9d or transcoding, between parameters that vary between codecs, e.g., different coding standards like H.261/H263; different input resolutions; and different maximal frame rates in the input streams.
Another use of the MCU can be to construct an output stream that combines several input streams. This option, sometimes called xe2x80x9ccompositingxe2x80x9d or xe2x80x9ccontinuous presence,xe2x80x9d allows a user at a remote terminal to observe, simultaneously, several other participants in the conference. The choice of these participants can vary among different users at different remote terminals of the conference. In this situation, the amount of bits allocated to each participant can also vary, and may depend on the on screen activity of the users, on the specific resolution given to the participant, or some other criterion.
All of this elaborate processing, e.g., transcoding and continuous presence processing, must be done under the constraint that the input streams are already compressed by a known compression method, usually based on a standard like ITU""s H.261 or H.263. These standards, as well as other video compression standards like MPEG, are generally based on a Discrete Cosine Transform (xe2x80x9cDCTxe2x80x9d) process wherein the blocks of the image (video frame) are transformed, and the resulting transform coefficients are quantized and coded.
One prior art method first decompresses the video streams; performs the required combination, bridging and image construction; and finally re-compresses the video streams for transmission. This method requires high computation power, leads to degradation in the resulting video quality and suffers from large propagation delay. One of the most computation intensive portions of the prior art methods is the encoding portion of the operation where such things as motion vectors and DCT coefficients have to be generated so as to take advantage of spatial and temporal redundacies. For instance, to take advantage of spatial redundancies in the video picture, the DCT function can be perfomed. To generate DCT coefficients, each frame of the picture is broken into blocks and the discrete cosine transform function is performed upon each block. In order to take advantage of temporal redundancies, motion vectors can be generated. To generate motion vectors, consecutive frames are compared to each other in an attempt to discern pattern movement from one frame to the next. As would be expected, these computations require a great deal of computing power.
In order to reduce computation complexity and increase quality, others have searched for methods of performing such operations in a more efficient manner. Proposals have included operating in the transform domain on motion compensated, DCT compressed video signals by removing the motion compensation portion and compositing in the DCT transform domain.
Therefore, a method is needed for performing the xe2x80x9ctranslationxe2x80x9d operations of an MCU, such as modifying bit rates, frame rates, and compression algorithms in an efficient manner that reduces propagation delays, degradation in signal quality, video bandwidth use within the MCU and computational complexity.
The present invention relates to an improved method of processing multimedia/video data in an MCU or other digital video processing device (VPD). By reusing information embedded in a compressed video stream received from a video source, the VPD can improve the quality and reduce the total computations needed to process the video data before sending it to the destination. More specifically, the present invention operates to manipulate compressed digital video from several compressed digital video sources. A video input module receives compressed video input data from a video source. A generalized decoder within the video input module decodes the compressed video input data and generates a primary video data stream. The generalized decoder also processes the compressed video input data and the primary video data stream to generate a secondary data stream. A video output module, which includes a rate control unit and a generalized encoder, receives the primary video data stream and the secondary data stream from at least one input module. The generalized encoder, in communication with the rate control unit, receives the primary video data from one or more input modules and encodes the primary video data into combined compressed video output data. The use of the secondary data stream by the output module improves the speed of encoding and the quality of the compressed video data.

Method and system for multimedia communication control


Disclosed are immunological methods and materials for detection of antigens associated with breast or prostate cancer disease states. Presently preferred antibody preparations (e.g., PR92 monoclonal antibodies produced by hybridoma cell line ATCC HB 9390) are employed in immunoassays performed on patient body fluids and for purification of tumor-associated antigen compositions.

Immunological technologies have provided for major advances in therapeutic and diagnostic techniques in cancer diagnosis and both in vitro and in vivo cancer therapy. Numerous tumor-associated antigens have been characterized and polyclonal and monoclonal antibodies specifically immunoreactive with such have been proposed for use as diagnostic and prognostic aids in the clinical management of tumor disease states.
Of interest to the background of the invention are references generally relating to useful monoclonal antibodies raised against human tumor cells (see, e.g., Chen, U.S. Pat. No. 4,618,585) and especially the following references generally relating to monoclonal antibodies immunoreactive with various tumor-associated antigens such as CA 19-9, CA 125 and carcinoembryonic antigen (CEA) and to diagnostic tests based on the use of one or more of such antibodies: Del Villano, WO 84/00758 (CA 19-9); Safi, et al., Cancer, 5, 779-782 (1986) (CA 19-9); Brochure published by Centocor, "Carbohydrate Antigen 19-9 Radioimmunoassay", (1983) (CA 19-9); Del Villano, et al., Clin. Chem., 29 3, 549-552 (1983) (CA 19-9); De Favero, et al., Cancer, 57, 1576-1579 (1986) (CA 19-9); Gupta, et al., Cancer, 56, 277-283 (1985) (CA 19-9); Brochure published by Centocor relating to CA 125, (1983); Bergmann, et al., Cancer, 59, 213-217 (1987) (CA 125); Pinto, et al., Cancer, 59, 218-222 (1987) (CA 125); Brochure published by Centocor relating to CA 19-9 and CEA (1984); and Bast, et al., New Eng. J. Med., 309/15, 883-920 (1983) (CA 125); Brochure published by Centocor, "Centocor Cancer Antigen 125.TM.) Radioimmunoassay" (1983) (CA 125); Bast, et al., Am. J. Obstet. Gynecol., 149/5, 553-559 (1984) (CA 19-9, CA 125, and CEA).
Of interest to the background of the present invention are the following references relating to the diagnosis of prostate cancer disease states on the basis of elevated levels of marker substances such as "prostate specific antigen" (PA) and prostatic acid phosphatase (PAP) which are present in low levels in normal human serum and the serum of patients with benign prostatic hyperplasia, but present at higher levels in sera of prostatic carcinoma patients, especially those in an advanced disease state: Lin, et al., U.S. Pat. No. 4,298,592; Lee, et al., U.S. Pat. No. 4,267,272; Miller, et al., U.S. Pat. No. 4,510,239; and, European Patent Application No. 160228 published Nov. 6, 1985.
Of substantial interest to the background of the invention with respect to immunological methods for diagnosis of prostate cancer are the following references relating to monoclonal antibodies raised against human prostate tumor cell lines PC-3 and DU145: Ware, et al., Cancer Research, 42, 1215-1222 (April 1982) (PC-3); Raynor, et al., J.N.C.I., 73, 617-625 (1984) (PC-3); Carroll, et al., Clinical Immunology and Immunopathology, 33, 268-281 (1984) (PC-3); Starlinq, et al., Cancer Research, 42, 3084-3089 (1982) (DU-145); Starling and Wright, Cancer Research, 45, 804-808 (1985) (DU-145); and Wright, et al., Cancer Research, 43, 5509-5516 (1983) (PC-3 and DU-145).
Also of interest to the background of the invention are the following references relating to the diagnosis of breast cancer disease states on the basis of monoclonal antibodies raised against various breast tumor cell lines and breast tissues: Schlom, et al., U.S. Pat. No. 4,612,282; Hilkens, et al., Prot. Bio Fluids. 29, 813-816 (1981); Hilkens, et al., Prot. Bio. Fluids, 31, 1013-1016 (1984); Dempsey, et al., J.N.C.I., 77, 1-9 (1986); Papsidero, et al., Cancer Research, 43, 1741-1747 (1983); Brochure published by Centocor, "Centocor CA 15-3 Radioimmunoassay" (1985); Brochure published by Centocor, "Radioimmunoassay for the Detection of CA 15-3 in Serum or Plasma" (1986) and the further references cited therein; Hilkens, et al., Int. J. Cancer, 34, 197-206 (1984); Kofe, et al., Hybridoma, 3, 223-232 (1984); Sekine, et al., J. Immunology, 135 3610-3615 (1985); and, Schmidt-Rhode, et al., International Society for Oncodevelopmental Biology and Medicine, Sept. 10-13, Paris, 1985.
Despite the above noted advances in the art, there continues to exist a need for methods and materials useful in accurately detecting and monitoring prostate or breast tumor disease states.

Immunological methods and materials for detection of tumor associated antigens


Provided are an IC and a method for automatically tuning process and temperature variations. The IC includes: a test circuit unit including test circuit elements having identical element values and variations to a tuning-targeted circuit element and at least one reference circuit element having a smaller variation than the tuning-targeted circuit element; a comparator that obtains a difference between intensities of first and second signals detected from the test circuit unit; and a tuning unit that tunes the variation of the tuning-targeted circuit element according to the difference between the intensities of the first and second signals. Thus, process and temperature variations of a circuit element can be detected and accurately tuned with respect to the circuit element itself. Also, the process and temperature variations can be tuned inside an IC. Thus, the time required for tuning the process and temperature variations can be reduced.

1. Field of the Invention
The present invention relates to an integrated circuit (IC) and a method for automatically tuning process and temperature variations.
2. Description of the Related Art
In general, a process variation occurring in the manufacture of an IC must be tuned to accurately operate the IC. A conventional method of tuning a process variation will be described in brief with reference to FIG. 1.
FIG. 1 is a circuit diagram illustrating a conventional method of tuning a process variation. A case where circuit elements of which process variations are to be tuned for low pass filters (LPFs) 12 will be described with reference to FIG. 1. To tune the process variations of the LPFs 12 in a conventional IC 10, a test signal is input to an input node 11 when power is applied to the conventional IC 10 to perform an initialization, passes through the LPFs 12, and is output to a final rode 13. The test signal is transmitted to a process variation tuning circuit (not shown) installed outside through a modem (not shown). A tuning control signal is input from a tuning circuit installed outside to an input node 14 so as to tune the process variations of the LPFs 12. The above-described conventional method is achieved using a signal output from the final node 13 of the conventional IC 10. Thus, process variations occurring in circuit elements constituting the LPFs 12 are not directly considered.
The signal output from the final node 13 is transmitted to the tuning circuit installed outside, and a control signal is received from an external source with respect to a process variation. Thus, a relatively long time is required for tuning a process variation in the conventional method.
In addition, a modem or the like must be installed to communicate with an external tuning circuit. Thus, an IC has a complicated structure.
Only when the power is applied to the IC to perform the initialization, the tuning circuit operates to tune the process variation. Thus, temperature variations of the circuit elements occurring due to heat during the operation of the IC cannot be considered.

Integrated circuit and method for automatically tuning process and temperature variations


There is provided mechanisms for calibration of an eye tracking system. An eye tracking system comprises a pupil centre corneal reflection (PCCR) based eye tracker and a non-PCCR based eye tracker. A method comprises obtaining at least one first eye position of a subject by applying the PCCR based eye tracker on an image set depicting the subject. The method comprises calibrating a head model of the non-PCCR based eye tracker, as applied on the image set, for the subject using the obtained at least one first eye position from the PCCR based eye tracker as ground truth. The head model comprises facial features that include at least one second eye position. The calibrating involves positioning the head model in order for its at least one second eye position to be consistent with the at least one first eye position given by the PCCR based eye tracker.

Eye tracking is a sensor technology that makes it possible for a computer or other device to know where a subject, such as a person, is looking. An eye tracker can detect the presence, attention and focus of the user. Eye tracking need not necessarily involve tracking of the user's gaze (for example in the form of a gaze direction or a gaze point). Eye tracking may for example relate to tracking of the position of an eye of the subject in space, without actually tracking a gaze direction or gaze point of the eye.
Different techniques have been developed for monitoring in which direction (or at which point on a display) a subject, such as person, is looking. This is often referred to as gaze tracking. Such techniques often involve detection of certain features in images of the eye, and a gaze direction or gaze point is then computed based on positions of these detected features. An example of such a gaze tracking technique is pupil center corneal reflection (PCCR). PCCR based gaze tracking employs the position of the pupil center and the position of glints (reflections of illuminators at the cornea) to compute a gaze direction of the eye or a gaze point at a display.
As an alternative (or complement) to conventional techniques such as PCCR-based eye tracking, machine learning may be employed to train an algorithm to perform eye tracking. For example, the machine learning may employ training data in the form of images of the eye and associated known gaze points to train the algorithm, so that the trained algorithm can perform eye tracking in real time based on images of the eye. Plenty of training data is typically needed for such machine learning to work properly. The training data may take quite some time and/or resources to collect. In many cases, certain requirements may be put on the training data. The training data should for example preferably reflect all those types of cases/scenarios that the eye tracking algorithm is supposed to be able to handle. If only certain types of cases/scenarios are represented in the training data (for example only small gaze angles, or only well-illuminated images), then the eye tracking algorithm may perform well for such cases/scenarios, but may not perform that well for other cases/scenarios not dealt with during the training phase.
Hence, each type of eye tracker comes with its own advantages and disadvantages. However, regardless of which type of eye tracker is used, there is a risk that the performance of the eye tracker will be inaccurate, for example due to insufficient calibration.
It would be desirable to provide new ways to address one or more of the abovementioned issues.


Methods for interpretation of mass spectrometric tests for clinical biomarkers in which the amounts of internal standards are set to equal clinical evaluation thresholds, and preparations for adding stable isotope labeled peptide species to sample digests while minimizing losses and alterations in peptide stoichiometry.

Methods of using mass spectrometry for the measurement of established and candidate biomarker proteins could benefit from improvements in methods for the preparation, handling and quantitative performance of stable isotope labeled peptides. Such labeled peptides are used as internal standards in the analysis of peptides samples, including protein sample digests, by mass spectrometry. In a specific case, the art could benefit from improvements to the performance of the technology called "SISCAPA" that was disclosed in one or more of the patent filings referenced above, and a number of recent publications including, for instance: An effective and rapid method for functional characterization of immunoadsorbents using POROS® beads and flow cytometry, N. Leigh Anderson et al., Journal of Proteome Research 3:228-34 (2004); Mass Spectrometric Quantitation of Peptides and Proteins Using Stable Isotope Standards and Capture by Anti-Peptide Antibodies (SISCAPA), Anderson, N. L. et al., Journal of Proteome Research 3: 235-44 (2004); Anti-peptide antibody screening: selection of high affinity monoclonal reagents by a refined surface plasmon resonance technique, Matthew E. Pope et al., J. Immunol. Methods, 341(1-2):86-96 (2009); A Human Proteome Detection and Quantitation Project: hPDQ, N. Leigh Anderson, et al., Mol. Cell. Proteomics 8:883-886 (2009); SISCAPA Peptide Enrichment on Magnetic Beads Using an Inline Beadtrap Device, N. Leigh Anderson, et al., Mol. Cell. Proteomics 8:995-1005 (2009); An automated and multiplexed method for high throughput peptide immunoaffinity enrichment and multiple reaction monitoring mass spectrometry-based quantification of protein biomarkers, Jeffrey R. Whiteaker, et al., Mol. Cell. Proteomics 9:184-196 (2010); Proteomic-Based Multiplex Assay Mock Submissions: Supplementary Material to A Workshop Report by the NCI-FDA Interagency Oncology Task Force on Molecular Diagnostics, Fred E. Regnier, et al., Clin. Chem. 56:2 165-171 (2010); MALDI Immunoscreening (MiSCREEN): A Method for Selection of Anti-peptide Monoclonal Antibodies for Use in Immunoproteomics, Morteza Razavi, Matthew E. Pope, Martin V. Soste, Brett A. Eyford, N. Leigh Anderson and Terry W. Pearson, Journal of Immunological Methods 364:50-64 (2011).


In a method of managing access codes, a product is provided with an access restricting mechanism configured to permit operation of the product in response to entry of either one of first and second access codes using a code interface. The first access code is displayed on the product without displaying the second access code on the product. The second access code is identified to a user in response to user input of at least one of the first access code and a serial number into a terminal in communication with an electronically accessible code storage unit associating the second access code with the at least one of the first access code and the serial number.

Combination locks are used in commercial, residential, and institutional environments to provide lockable access to personal items and/or enclosures. The combination lock may be a separate device, such as a combination padlock, which may be shackled to a door, bracket, cable, or other item to restrict access. Alternatively, the combination lock may be integral to an enclosure, such as a safe or a storage locker. Combination locks include mechanical (e.g., single-dial, multiple-dial, and mechanical keypad) and electromechanical (e.g., electronic keypad) designs. These designs allow for authorized access without possession of a mechanical or electronic key (e.g., bitted mechanical key, RFID card, wireless transceiver/fob, etc.).
While the use of a combination lock, as compared to a key-based lock, may eliminate the risk of lost, stolen, or copied keys, an authorized access code (e.g., dial or keypad sequence or combination) may be forgotten, preventing access to the locked item by the authorized user. Further, in a situation where an administrator or other such individual needs access to the locked item or items, it may be difficult or impossible to keep track of the authorized combinations, particularly where the combination code is changeable by the user.


The present invention provides a solid of pitavastatin tert-butyl ester and process for its preparation. The present invention also provides a novel crystalline form of pitavastatin calcium, process for its preparation and pharmaceutical compositions comprising it.

Pitavastatin is chemically, (3R,5S,6E)-7-[2-cyclopropyl-4-(4-fluorophenyl)-3-quinolinyl]-3,5-dihydroxy-6-heptenoic acid and has the structural formula:

Pitavastatin calcium is a novel member of the medication class of statins. Marketed in the United States under the trade name Livalo, it is like other statin drugs an inhibitor of HMG-CoA reductase, the enzyme that catalyses the first step of cholesterol synthesis. It is likely that pitavastatin will be approved for use in hypercholesterolaemia (elevated levels of cholesterol in the blood) and for the prevention of cardiovascular disease outside South and Southeast Asia as well.
Polymorphism is defined as "the ability of a substance to exist as two or more crystalline phases that have different arrangement and/or conformations of the molecules in the crystal Lattice. Thus, in the strict sense, polymorphs are different crystalline structures of the same pure substance in which the molecules have different arrangements and/or different configurations of the molecules". Different polymorphs may differ in their physical properties such as melting point, solubility, X-ray diffraction patterns, etc. Although those differences disappear once the compound is dissolved, they can appreciably influence pharmaceutically relevant properties of the solid form, such as handling properties, dissolution rate and stability. Such properties can significantly influence the processing, shelf life, and commercial acceptance of a polymorph. It is therefore important to investigate all solid forms of a drug, including all polymorphic forms, and to determine the stability, dissolution and flow properties of each polymorphic form. Polymorphic forms of a compound can be distinguished in the laboratory by analytical methods such as X-ray diffraction (XRD), Differential Scanning calorimetry (DSC) and Infrared spectrometry (IR).
Solvent medium and mode of crystallization play very important role in obtaining one polymorphic Form over the other.
Pitavastatin and its calcium salt can exist in different polymorphic Forms, which may differ from each other in terms of stability, physical properties, spectral data and methods of preparation.
Pitavastatin and its process were disclosed in U.S. Pat. No. 5,753,675.
Pitavastatin calcium and its process were disclosed in U.S. Pat. No. 5,856,336.
PCT publication no. WO 2004/072040 (herein after referred to '040 patent) disclosed crystalline polymorph A, polymorph B, polymorph C, polymorph D, polymorph E, polymorph F and amorphous form of pitavastatin calcium.
According to the '040 patent, crystalline polymorph A of pitavastatin calcium was characterized by an X-ray powder diffraction pattern having peaks expressed as 2θ at about 5.0, 6.8, 9.1, 10.0, 10.5, 11.0, 13.3, 13.7, 14.0, 14.7, 15.9, 16.9, 17.1, 18.4, 19.1, 20.8, 21.1, 21.6, 22.9, 23.7, 24.2, 25.2, 27.1, 29.6, 30.2 and 30.2 degrees.
According to the '040 patent, crystalline polymorph B of pitavastatin calcium was characterized by an X-ray powder diffraction pattern having peaks expressed as 2θ at about 4.6, 5.3, 6.2, 7.7, 9.2, 9.6, 10.3, 11.3, 11.7, 12.6, 13.0, 13.9, 14.7, 14.9, 15.6, 16.3, 17.0, 17.4, 18.0, 18.7, 19.3, 20.0, 20.5, 20.8, 21.2, 21.5, 22.4, 23.2, 23.8, 24.4, 25.2, 26.0, 26.4, 27.0, 27.9 and 28.9 degrees.
According to the '040 patent, crystalline polymorph C of pitavastatin calcium was characterized by an X-ray powder diffraction pattern having peaks expressed as 2θ at about 4.1, 5.6, 7.8, 8.3, 10.3, 11.6, 17.5, 17.9, 18.7, 19.5, 20.6, 21.5, 21.9, 23.1, 24.0 and 24.8 degrees.
According to the '040 patent, crystalline polymorph D of pitavastatin calcium was characterized by an X-ray powder diffraction pattern having peaks expressed as 2θ at about 5.0, 6.5, 6.8, 8.7, 10.0, 10.2, 10.8, 13.1, 13.5, 14.3, 15.3, 16.1, 16.8, 18.2, 18.5, 19.0, 19.9, 20.5, 21.0, 21.7, 22.3, 23.4, 24.0, 25.6 and 26.2 degrees.
According to the '040 patent, crystalline polymorph E of pitavastatin calcium was characterized by an X-ray powder diffraction pattern having peaks expressed as 2θ at about 4.4, 5.0, 6.6, 6.8, 8.9, 10.0, 10.3, 10.8, 13.3, 13.6, 14.0, 15.2, 15.9, 16.4, 16.9, 17.8, 18.3, 18.9, 20.2, 20.4, 20.7, 20.9, 21.1, 21.6, 21.7, 22.3, 23.5, 23.8, 24.1, 24.7, 25.4, 26.6, 30.2 and 34.0 degrees.
According to the '040 patent, crystalline polymorph F of pitavastatin calcium was characterized by an X-ray powder diffraction pattern having peaks expressed as 2θ at about 5.1, 5.6, 7.0, 8.8, 9.6, 10.2, 10.9, 11.3, 11.9, 12.5, 13.0, 13.7, 14.4, 14.7, 15.3, 15.5, 16.8, 17.6, 18.3, 19.3, 19.7, 20.6, 21.2, 21.8, 22.8, 23.1, 23.8, 24.1, 24.8, 25.7, 26.2, 26.6, 26.9, 28.4, 29.5, 29.8 and 30.9 degrees.
PCT publication no. WO 2005/063711 disclosed crystal form A of pitavastatin calcium which contains from 5 to 15% of water.
PCT publication no. WO 2007/132482 disclosed a process for the preparation of pitavastatin calcium. According to this process, pitavastatin calcium can be prepared by reacting the (4R,6S)-(E)-6-[2-(2-cyclopropyl-4-(4-fluorophenyl)quinoline-3-yl)-vinyl]-2,2-dimethyl-1,3-dioxane-4-yl}acetic acid tertiary butyl ester in acetonitrile with hydrochloric acid and then treating with sodium hydroxide. The reaction mixture obtained was further treated with methyl amine to form pitavastatin methyl amine salt and then converted to pitavastatin calcium.
PCT publication no. WO 2010/077062 described a process for the preparation of pitavastatin calcium. According to this process, pitavastatin calcium can be prepared by reacting the tert-butyl (3R,5S,6E)-7-[2-cyclopropyl-4-(4-fluorophenyl)quinolin-3-yl]-3,5-O-isopropylidene-3,5-dihydroxy-6-heptenoate in acetonitrile with hydrochloric acid and then treating with sodium hydroxide. The reaction mixture obtained was further treated with calcium chloride dihydrate to form pitavastatin calcium.
Tert-butyl-(3R,5S,E)-7-(2-chloropropyl-4-(4-fluorophenyl)quinolin-3-yl)-3,5-dihydroxyhept-6-enoate (pitavastatin tert-butyl ester) is a key intermediate for the preparation of pitavastatin calcium. The chemical formula of pitavastatin tert-butyl ester may be represented as:

The process for the preparation of solid of pitavastatin tert-butyl ester was not disclosed in the prior art. We have discovered that pitavastatin tert-butyl ester can be obtained as a solid. It has been found that the pitavastatin or pharmaceutical acceptable salt of it can be obtained with good chromatographic purity and good yields when the crystalline solid of pitavastatin tert-butyl ester is used for the preparation of the said compounds.
We have also discovered novel crystalline form of pitavastatin calcium. The novel form has been found to be stable over the time and reproducible and so, suitable for pharmaceutical preparations.
Thus, one object of the present invention is to provide a solid of pitavastatin tert-butyl ester and process for its preparation.
Another object of the present invention is to provide a novel crystalline form of pitavastatin calcium, process for its preparation and pharmaceutical compositions comprising it.


An enclosed connection system for connecting first and second elongate electrical conductors includes a transverse wedge connector and an enclosure. The transverse wedge connector includes an electrically conductive first connector member, an electrically conductive second connector member, and a clamping mechanism. The first connector member includes: a first body having inner and outer opposed ends; a first hook portion on the outer end of the first body, the first hook portion defining a first channel to receive the first conductor; and a first abutment portion on the inner end of the first body. The second connector member includes: a second body having inner and outer opposed ends; a second hook portion on the outer end of the second body, the second hook portion defining a second channel to receive the second conductor; and a second abutment portion on the inner end of the second body. The clamping mechanism is selectively operable to displace the first and second connector members relative to one another from an open position to a clamping position to clamp the first conductor in the first channel and between the first hook portion and the second abutment portion and to clamp the second conductor in the second channel and between the second hook portion and the first abutment portion to thereby form a connection. The enclosure is configured to receive and cover the connection and to protect the transverse wedge connector.

Electrical conductors often must be terminated or joined in various environments, such as underground or overhead. Such conductors may be, for example, high voltage electrical distribution or transmission lines. In order to form such connections, a connector may be employed. For example, in electrical power systems, it is occasionally necessary to tap into an electrical power line. One known system for tapping into an electrical power line is to use a tap connector for electrically connecting a main line electrical cable to an end of a tap line electrical conductor.
One such tap connector, typically referred to as a wedge connector, includes an electrically conductive C-shaped member or sleeve and a wedge. The two conductors are positioned at opposite sides of the C-shaped sleeve and the wedge is driven between the two conductors. This forces the two conductors against the C-shaped sleeve such that they are captured between the wedge and the C-shaped sleeve. Wedge connectors are commonly installed using an explosively driven connecting tool (sometimes referred to as a powder actuated tool). The C-shaped sleeve is held in place on a tool head connected to a tool body including a cartridge chamber. The cartridge chamber accepts a gunpowder shell casing with a powder charge that is activated by striking the casing with a hammer. The explosion drives a ram that forces the wedge portion of the connector between the two conductors.

Connection enclosure assemblies, connector systems and methods for forming an enclosed connection between conductors