An armature for a solenoid actuator is disclosed. The armature comprises a first face comprising a recess suitable for receiving a biasing spring in use of the armature; a second face opposite the first face; and fluid communication passages for providing a fluid flow path through the armature between the recess and the second face in use of the armature. The first face is uninterrupted by the fluid communication passages. The invention reduces the risk of cavitation damage during operation of the actuator. In one application, the actuator is used in a fluid pump for a selective catalytic reduction system.

One strategy for reducing nitrogen oxide exhaust gas emissions in an internal combustion engine involves the introduction of a reagent comprising a reducing agent, typically a liquid ammonia source such as an aqueous urea solution, into the exhaust gas stream. This method is known as selective catalytic reduction or SCR. The reducing agent is injected into the exhaust gas upstream of an exhaust gas catalyst, known as an SCR catalyst. Nitrogen oxides in the exhaust gas undergo a catalysed reduction reaction with the ammonia source on the SCR catalyst, forming gaseous nitrogen and water.
Typically, in a selective catalytic reduction (SCR) system, injection of the reagent into the exhaust gas stream is achieved by pumping the reagent from a supply tank to an injection nozzle disposed within the exhaust gas stream using a suitable pump, such as described in the present applicant's co-pending European Patent Application Publication No. EP-A-1878920.
FIG. 1 shows, schematically and in simplified form, a known pump 20 suitable for pumping reagent in an SCR system. The pump 20 comprises a solenoid actuator 22 disposed within a generally cylindrical housing 24. The actuator 22 comprises a tubular pole member 26, formed integrally with the housing 24, and a wire winding or coil 28 disposed around the pole member 26. One end of the pole member 26 forms an annular pole face 30 of the actuator 22.
An armature 32 is provided in an armature chamber 34 adjacent to the pole face 30. The armature 32 is connected to a pumping plunger 36. The plunger 36 is slidably received in a central bore 38 of a sleeve 40 disposed centrally within the pole member 26. An end face 42 of the sleeve 40 is spaced from the pole face 30, so as to form a spring chamber 44 adjacent to the pole face 30. A biasing spring 46 is partially received in the spring chamber 44 to bias the armature 32 away from the pole face 30. One end of the biasing spring 46 abuts the end face 42 of the sleeve 40, and the other end of the biasing spring 46 abuts a central region 48 of the armature 30.
The pump 20 further comprises, at an upstream end, an inlet 50, which receives fluid from a source such as a tank (not shown) and, at a downstream end, an outlet 52 that is in communication with a delivery nozzle (not shown). In use of the pump 20 in an SCR system for an internal combustion engine, the fluid is a reagent and the delivery nozzle is disposed within an exhaust pipe of the engine.
A supply passage 54 is provided within the pump 20 to convey fluid from the inlet 50 to the outlet 52. In this example, the supply passage 54 comprises an annular space 56 between the pole member 26 and the coil 28, and further comprises radial passages 58 that extend through the pole member 26 and the sleeve 40 to communicate with the bore 38 of the sleeve 40. When the pumping plunger 36 is in the position shown in FIG. 1, with the armature 32 biased away from the pole face 30, the radial passages 58 communicate with a delivery chamber 60 formed at a downstream end of the bore 38 of the sleeve 40.
Fluid flow from the delivery chamber 60 to the outlet 52 is controlled by an outlet valve 62, which is arranged to open when the pressure of fluid in the delivery chamber 60 exceeds a threshold level.
In operation, in a pumping stroke of the pump, the coil 28 is energized to generate a toroidal magnetic field around the coil 28. As a result, the armature 32 moves towards the pole face 30, against the force of the biasing spring 46, such that the downstream end of the plunger 36 interrupts fluid flow between the radial passages 58 and the delivery chamber 60. The downstream end of the plunger 36 reduces the volume of the delivery chamber 60, so that the pressure of fluid in the delivery chamber 60 increases. Once the threshold pressure is reached, the outlet valve 62 opens to cause delivery of fluid from the outlet 52 of the pump 20.
The coil 28 is then de-energized, whereupon the magnetic forces acting on the armature 32 diminish. The force of the biasing spring 46 causes the armature 32 to move away from the pole face 30, so as to increase the volume of the pumping chamber 60 and re-open fluid communication between the radial passages 58 and the delivery chamber 60. Fluid can then re-fill the delivery chamber 60, ready for the next pumping stroke.
In an SCR system, it is desirable to provide rapid, frequent injections of fluid into the exhaust pipe. For example, to ensure sufficient atomization of the fluid as it leaves the delivery nozzle, the velocity of the pumping plunger 36 must be relatively high, typically of the order of 2 meters per second. As will be appreciated from FIG. 1, the armature 32 must move through fluid within the armature chamber 34. Since the diameter of the armature 32 is relatively large, a significant quantity of fluid is displaced when the armature 32 moves. The displacement of this fluid tends to slow the movement of the armature 32 and therefore the pumping plunger 36.
To allow the armature 32, and hence the plunger 36, to move fast enough in the armature chamber 34, it is known to provide vent holes 64 in the armature 32. The vent holes 64 extend axially through the armature 32 from the face of the armature 32 nearest the pole face 30 to the opposite face, furthest from the pole face 30. During movement of the armature 32, fluid can flow through the vent holes 64 as well as around the periphery of the armature 32, thereby reducing the fluid drag on the armature 32.
It has been found that, when the coil 28 is de-energized and the armature 32 moves away from the pole face 30, the pressure in the spring chamber 44 is caused to drop rapidly. This can lead to cavitation damage to the actuator 20, caused by the collapse of cavities in the fluid in the spring chamber 44 that form as a result of the pressure drop.
Accordingly, it would be desirable to provide an armature for an actuator that overcomes or mitigates this problem.

Delphi International Operations Luxembourg, S.A.R.L.


An external read sense amplifier for reading out a data to an outside and an internal verify sense amplifier for reading out a data for an internal operation are provided, separately from each other, to a plurality of banks. Preferably, an internal verify sense amplifier is provided for each prescribed number of memory blocks. There is provided a nonvolatile semiconductor memory device with a background operation function, having a reduced chip occupancy area.

1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and particularly, to a nonvolatile semiconductor memory device capable of operating in the background operation mode in which a data is externally read out in an erasure/programming operation in the interior thereof.
2. Description of the Background Art
FIG. 17 is a block diagram schematically showing a configuration of a conventional nonvolatile semiconductor memory device. In FIG. 17, the conventional nonvolatile semiconductor memory device includes a plurality of banks B#1 to B#4. Each of the banks B#1 to B#4 includes: a memory array MA having a plurality of nonvolatile memory cells arranged in rows and columns; a predecoder PD for predecoding a supplied address signal; a row decoder RD for decoding a row predecode signal supplied from the predecoder PD to select an addressed row of the memory array MA; a column decoder CD for decoding a column predecode signal supplied from the predecoder PD to generate a column select signal selecting an addressed column of the memory array MA; and a Y gate YG for selecting a corresponding column of the memory array MA according to the column select signal supplied from the column decoder CD. The banks B#1 to B#4 can be addressed independently and individually.
The nonvolatile semiconductor memory device further includes: an address buffer 1 taking in an address signal AD supplied externally therein according to a control signal CTL and generating an internal address signal to supply it to the banks B#1 to B#4; a data buffer 2 for inputting and outputting a data between the data buffer 2 and an external device; a write data buffer 4 receiving an internal write data from the data buffer 2 to store the data therein; write circuit and sense amplifier blocks 5a to 5d, provided corresponding to the respective banks B#1 to B#4, each transmitting a write data to a selected memory cell of a corresponding bank and reading a data from a selected memory cell of a corresponding bank; a bank pointer 3 for activating a bank specified by a bank address signal supplied from the address buffer 1; an erasure/programming verification circuit 6 receiving a verify data read out from the write circuit and sense amplifier blocks 5a to 5d and a write data stored in the write data buffer 4 in a write operation, and for verifying whether or not, in a selected bank, erasing has been correctly performed and whether or not, in a selected bank, data programming has been correctly performed; and internal control circuit 7 receiving a control signal CTL supplied externally, a command CMD specifying an operating mode supplied externally and a bank address signal supplied from the bank pointer 3, and controlling operations of the data buffer 2 and the bank pointer 3 but as well as setting an internal address signal generated from the address buffer 1 in an internal operation.
The control signal includes a chip enable signal /CE, a write enable signal /WE and an output enable signal /OE. The command CMD specifies a data erase mode, a data write mode and the like, and is supplied through a data bus.
The nonvolatile semiconductor memory device shown in FIG. 17 is a flash memory in which one memory cell is formed of one floating gate field effect transistor. Data storage in a memory cell is achieved by injection/extraction of electric charges to/from the floating gate of a floating gate field effect transistor to change a threshold voltage thereof.
It has been established that an access time for a data read operation ranges from 50 nsec (nanoseconds) to 200 nsec and on the other hand, an erasure/programming operation requires to change a threshold voltage of a memory cell transistor (in a unit of a memory block) and therefore, it takes a relatively long time ranging from 2 xcexcs (microseconds) to 5 s (seconds). In the prior art, it is impossible to read out a data in the chip during an internal operation in which the erasure/programming operation is performed. In a case where a plurality of banks B#1 to B#4 are provided as shown in FIG. 17, however, while an internal operation for programming/erasing is performed on a bank, can be accessed for data reading from another bank. An operation in which while an internal operation is actually performed in one bank, a data can be read out from another bank, is called a BGO (background operation) function. In order to realize this BGO function, an external operation address signal and an internal operation address signal are generated from the address buffer and further, the write circuit and sense amplifier blocks 5a to 5d are provided corresponding to the respective banks B#1 to B#4. According to an operating mode, the write circuit and sense amplifier blocks 5a to 5d are coupled to either the erasure/programming verification circuit 6 or the data buffer 2. The selective connection is performed under control of the internal control circuit 7 according to a bank specifying signal supplied from the bank pointer 3.
FIG. 18 is a circuit diagram representing a construction of a sense amplifier included in each of the write circuit and sense amplifier blocks 5a to 5d shown FIG. 17. In FIG. 18, the sense amplifier includes: a current sense circuit 901, activated when a sense amplifier enable signal ZSE is activated, for amplifying a data transmitted through an internal data transmission line 900 from the Y gate YG; an N channel MOS transistor 902, made conductive when the sense amplifier enable signal ZSE is deactivated, for precharging a node 907 to the ground voltage level; two cascaded CMOS inverters 903 and 904 amplifying a signal on the node 907; an internal output circuit 905, activated when an external read output enable signal EXRDE is activated, for buffering (amplifying) a signal supplied from the CMOS inverter 904 to transmit the buffered signal to the data buffer 2; and an internal output circuit 906, activated when a verify output enable signal VFRDE is activated, for buffering (amplifying) an output signal of the CMOS inverter 904 to supply the output signal to the erasure/programming verification circuit 6.
The current sense circuit 901 includes: a P channel MOS transistor PQ1, made conductive when the sense amplifier enable signal ZSE is activated, for supplying a current to the node 907; a P channel MOS transistor PQ2 made conductive when the sense amplifier enable signal ZSE is activated and transmitting a power supply voltage when made conductive; an N channel MOS transistor NQ3 connected between the MOS transistor PQ2 and the ground node, and receiving the sense amplifier enable signal ZSE at a gate thereof; an N channel MOS transistor NQ 1 connected between the node 907 and the internal data line 900, and coupled with drains of the MOS transistors PQ2 and PQ3 at a gate thereof; and an N channel MOS transistor NQ2 connected in parallel to the MOS transistor NQ3, and connected to the internal data transmission line 900 at a gate thereof.
The first internal output circuit 905 includes: P channel MOS transistors PQ3 and PQ4 connected serially between a power supply node and a first output node; and N channel MOS transistors NQ4 and NQ5 connected serially between the first output node and a ground node. An output signal of the CMOS inverter 904 is supplied to the gates of the MOS transistors PQ3 and NQ5, and the external read output enable signal EXRDE is supplied to the gate of the MOS transistor PQ4 through an inverter. Further, the external read output enable signal EXRDE is supplied to the gate of the MOS transistor NQ4.
The second internal output circuit 906 includes: P channel MOS transistors PQ5 and PQ6 connected serially between a power supply node and a second output node; and N channel MOS transistors NQ6 and NQ7 connected serially between the second output node and a ground node. An output signal of the CMOS inverter 904 is supplied to the gates of the MOS transistors PQ5 and NQ7. The verify output enable signal VFRDE is supplied to the gate of the MOS transistor PQ6 through an inverter and further, the verify output enable signal VFRDE is supplied to the gate of the MOS transistor NQ6.
The internal data transmission line 900 is coupled to a selected column of a corresponding memory array through the Y gate YG. When the sense amplifier enable signal ZSE is inactive at H level, the MOS transistor PQ1 and PQ2 are turned off, while the MOS transistor NQ3 is turned on in the current sense circuit 901. Therefore, the gate of the MOS transistor NQ1 is coupled to a ground node through the MOS transistor NQ3, and the MOS transistor NQ1 is turned off to disconnect the node 907 and the internal data transmission line 900 from each other. Further, the MOS transistor 902 is turned on and the node 907 is fixed at the ground voltage level.
When the sense amplifier enable signal ZSE goes to L level of the active state, the MOS transistors PQ1 and PQ2 are turned on, while the MOS transistor NQ3 is turned off. Further, the MOS transistor 902 is turned off. Therefore, the node 907 is charged by the MOS transistor PQ1 toward the power supply voltage level. Further, the MOS transistor NQ1 receives the power supply voltage at the gate thereof through the MOS transistor PQ2, to turn on for coupling the node 907 with the internal data transmission line 900. Therefore, a voltage lower than the power supply voltage by a threshold voltage of the MOS transistor NQ1 is transmitted to the internal data transmission line 905 through the MOS transistor NQ1. When a threshold voltage of a memory cell on a column selected by the Y gate YG is low, a current flows through the memory cell and a voltage level on the internal transmission line 900 decreases and the MOS transistor NQ2 is turned off, a current flows from the MOS transistors PQ1 and NQ1 to the internal data transmission line 900 to reduce a voltage level of the node 907.
On the other hand, when a threshold voltage of a memory cell selected by the Y gate YG is high, no current flows through the selected memory cell and the internal data transmission line 900 goes to a voltage level charged by the MOS transistors PQ1 and NQ1. Accordingly, the MOS transistor NQ2 is turned on to discharge the gate of the MOS transistor NQ1 to the ground voltage level. Therefore, the MOS transistor NQ1 is turned off and the node 907 maintains H level charged by the MOS transistor PQ1. A voltage level of the node 907 is amplified by the CMOS inverters 903 and 904 and the amplified voltage is transmitted to the internal output circuits 905 and 906.
In the internal output circuit 905, when the external read output enable signal EXRDE is inactive at L level, the MOS transistors PQ4 and NQ4 are off and the internal output circuit 905 is in an output high impedance state. On the other hand, when the external read output signal EXRDE is activated at H level, the MOS transistors PQ4 and NQ4 are turned on and the internal output circuit 905 inverts the signal supplied from the CMOS inverter 904 and transmits the inverted signal to the data buffer 2. The data buffer 2 is activated under control of the internal control circuit 7 shown in FIG. 17 and buffers a data supplied from the internal output circuit 905 to output the buffered data to an outside.
When the verify output enable signal VFRDE is inactive at L level, the MOS transistors PQ6 and NQ6 in the internal output circuits 906 are off and the internal output circuit 906 is in the output high impedance state. When the verify output enable signal VFRED is activated at H level, the MOS transistors PQ6 and NQ6 are turned on and a signal from the CMOS inverter 904 is buffered and supplied to the erasure/programming verification circuit 6.
The erasure/programming verification circuit 6 identify, in an erasure operating mode, whether or not a signal supplied from the internal output circuit 906 is at a logical level corresponding to the erased state and determines whether or not erasing has been correctly effected. On the other hand, the erasure/programming verification circuit 6 identifies, in a program mode, whether or not a data supplied from the internal output circuit 906 is at a logic level corresponding a write data and determines whether or not data writing has been correctly effected. The output enable signals EXRDE and VFRDE are selectively activated by the internal control circuit 7 according to whether an internal operation or an external operation is effected, based on a signal generated from the bank pointer.
FIG. 19 is a circuit diagram representing a configuration of a Y gate shown in FIG. 17. FIG. 19 shows a portion including the Y gate for selecting a memory cell of one bit from memory cells of 8 bits. In FIG. 19, the Y gate YG includes: column select gates TR0 to TR3 each formed of an N channel MOS transistor, and provided corresponding to respective internal data lines DL0 to DL3, and made conductive when column select signals CAL0 to CAL3 are selected, respectively, and column select gates TR4 to TR7 formed of N channel MOS transistors, provided corresponding to respective internal data lines DL4 to DL7, and made conductive when column select signals CAL0 to CAL3 are selected, respectively.
The internal data lines DL0 to DL7 are, for example, bit lines in the memory array MA and a column of memory cells are connected to each of the lines DL0 to DL7. A column (an internal data line) is selected according to a column address in a set of the internal data lines DL0 to DL3 and in a set of the internal data lines DL4 to DL7 by the column select gates TR0 to TR 3 and TR4 to TR7, and the selected columns are coupled to respective global data lines GDL0 and GDL1.
The Y gate YG further includes block select gates TR8 and TR9 formed of N channel MOS transistors, provided corresponding to the global data lines GDL0 and GDL1, and made conductive when respective column block select signals CAU0 and CAU1 are activated to couple the corresponding global data lines GDL0 and GDL1 to the internal transmission line 900.
In the Y gate YG shown in FIG. 19, a total of 2 bits composed of one bit from the internal data line DL0 to DL3 and one bit from the internal data line DL4 to DL7 are selected according to the column select signal CAL0 to CAL3 and the two bits are transmitted to the respective global data lines GDL0 to GDL1. Then, one of the global lines GDL0 and GDL1 is coupled to the sense amplifier circuit through the internal transmission line 900 according to the column block select signals CAU0 and CAU1. The internal transmission line 900 is also coupled to the write circuit included in a corresponding write circuit and sense amplifier block 5 (5a to 5d), and data reading and data writing are effected through the Y gate YG.
It should be appreciated that the memory array MA is divided into a plurality of blocks and a plurality of bits are read out in parallel. In FIG. 19, although a configuration is shown in which a memory cell of 1 bit is simply selected from memory cells of 8 bits, a scale of the Y gate YG is expanded, proportional to the number of internal data lines included in one column block and the number of column blocks.
FIG. 20 is a circuit diagram representing an example of configuration of a column decoder shown in FIG. 17. In FIG. 20, the column decoder CD includes: an OR circuit 910 receiving an external read bank specifying signal EBP_X and an internal operation bank specifying signal IBP_X to generate a bank specifying signal BP_X; inverters 911 to 913 inverting predecode signals (or address signal bits) A0 to A2 to generate complimentary predecode signal /A0 to /A2; and column decode circuits 914 to 919, enabled when the bank specifying signal BP_X is activated, for performing a decode operation.
The column decode circuit 914 receives the predecode signal /A0 and the bank specifying signal BP_X to generate the column select signal CAL0. The column decode circuit 915 receives the predecode signals A0 and /A1, and the bank specifying signal BP_X to generate the column signal CAL1. The column decode circuit 916 receives the predecode signals /A0 and A1, and the bank specifying signal BP_X to generate the column select signal CAL2. The column decode circuit 917 receives the predecode signals A0 and A1, and the bank specifying signal BP_X to generate the column select signal CAL3. The column decode circuit 918 receives the predecode signal /A2 and the bank specifying signal BP_X to generate the column block select signal CAU0. The column decode circuit 919 receives the predecode signal A2 and the bank specifying signal BP_X to generate the column block select signal CAU1.
Level converters 920 are provided corresponding to the respective column select signals CAL0 to CAL3, and to the respective column block select signals CAU0 to CAU1. The level converters 920 each receive a high voltage VP as one operating power supply voltage and converts a voltage level of a corresponding signal from a normal operation power supply voltage to a high voltage VP while maintaining a logical level thereof. When a programming operation is performed, a level conversion of a selected column select signal is performed using level converter 920 in order that a high programming voltage is transmitted onto a selected column through a column select gate formed of an N channel MOS transistor as shown in FIG. 19.
The predecode signals A0 to A2 are supplied from the predecoder PD shown in FIG. 17. The column decode circuits 914 to 919 each are an AND type decode circuit and enabled when the bank specifying signal BP_X is activated at H level, to perform a decode operation. One of the column select signals CAL0 to CAL3 and one of the column block select signals CAU0 to CAU1 are driven to a selected state (H level) according to the predecode signals A0 to A2. With such driving to the selected state, one column (of memory cells) is selected in the memory array MA.
It should be appreciated that the predecode signals A0 to A2, and /A0 to /A2 may be address signal bits.
In the nonvolatile semiconductor memory device as shown in FIG. 17, a data can be read out from a bank through accessing that bank while an internal operation for erasing/programming is performed on another bank. It is necessary, however, to provide a write circuit and a sense amplifier circuit for each bank in order to realize the background operation (BGO) function. Especially, in a sense amplifier as shown in FIG. 18, output circuits are required to be provided for external data outputting and for an internal operation (for verifying), separately, and there arises a problem that an occupying area of a sense amplifier is larger. Specifically, when the number of banks is increased in order to improve an operating efficiency of the nonvolatile semiconductor memory device, the number of sense amplifiers increases proportionally, thereby resulting in great increase in chip occupied area.
It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of suppressing increase in chip area with degradation of a background operation function even when the number of banks increases.
It is another object of the present invention to provide a flash memory with a background operation function being capable of increasing the number of banks while suppressing increase in number of internal data read circuits.
A nonvolatile semiconductor memory device according to one aspect of the present invention includes: a plurality of memory banks each having a plurality of nonvolatile memory cells; at least one sense amplifier for read operation, provided corresponding to a prescribed number of memory banks of the plurality of memory banks, for outputting externally a data read out from a corresponding bank through a buffer circuit; and an sense amplifier for internal operation, provided corresponding to the plurality of memory banks and separately from the sense amplifier for read operation, for reading out a memory cell data from a corresponding memory bank for a prescribed internal operation.
A nonvolatile semiconductor memory device according to another aspect of the present invention includes: a memory array having a plurality of nonvolatile memory cells arranged in a matrix of rows and columns; an external sense amplifier circuit for reading out a data on a selected memory cell of the memory array to an outside; an sense amplifier for internal operation, provided separately from the external sense amplifier circuit, for reading out a data from a selected memory cell of the memory array for a prescribed internal operation; and a select circuit for coupling the selected memory cell of the memory array to the external sense amplifier circuit and the sense amplifier for internal operation through different paths.
A nonvolatile semiconductor memory device according to still another aspect of the present invention is a nonvolatile semiconductor memory device with a background operation function, in which a plurality of internal data read paths are provided extending from one memory cell array.
By providing a sense read circuit for external reading corresponding to a prescribed number of memory banks, it is unnecessary to provide external read sense amplifiers corresponding to respective memory banks, thereby enabling a chip area to decrease.
By connecting a sense read circuit for external reading and a sense read circuit for an internal operation to a bank through different paths, efficient placement of the sense read circuit for an internal operation can be realized, thereby improving a layout efficiency and reducing a chip area.
Further, by providing a plurality of output paths for a memory array, an internal operation amplifier and an external read sense amplifier can be separately disposed in an efficient way and therefore, a chip area can be efficiently utilized to decrease a chip area.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Nonvolatile memory with background operation function


The disclosed embodiments are related to a method and system for creating a digital image album implementable on a computing device. The method includes receiving a plurality of digital images. The method further includes creating a first signature corresponding to each of the plurality of digital images. The method further includes comparing the first signature corresponding to each of the plurality of digital images with one or more second signatures. Each of the second signatures corresponds to each of one or more prototype digital albums. The method further includes selecting one or more digital images from the plurality of digital images based on the comparison to create the digital image album.

Over the years, an individual collects hundreds of photographs, which subsequently have to be organized for storage and viewing purposes. The most common manner of organizing these photographs is to place them in albums. Although many people collect photographs, only a few invest time on a regular basis to organize and maintain the photographs. Moreover, with time, the number of unorganized photographs increase, making it difficult to keep the collection organized. Therefore, there is a need to provide efficient techniques for organizing a collection of photographs.

Method and system for creating a digital image album


Process and apparatus for producing a turbine component, turbine component and use of the apparatus

U.S. Pat. No. 6,024,792 shows the build-up welding used for single crystal structures, in which new layers are produced on a substrate by means of powder being supplied.
Turbines are used in many sectors to drive generators or turbo machines. The energy content of a working medium which is under a high pressure and at a high temperature is used to generate a rotary motion of a turbine shaft by the working medium being passed over the turbine, where it expands in such a manner as to perform work. To generate the rotary motion of the turbine shaft, a number of rotor blades, which are usually combined in ring form to form groups or rows of blades, are arranged over the outer circumference of the shaft, which rotor blades drive the turbine shaft by transfer of momentum from the working medium flowing in. Moreover, rows of guide vanes which are connected to the turbine casing are usually arranged between the adjacent rows of rotor blades in order to guide the flowing working medium in the turbine. The turbine blades and vanes have a main blade or vane section which is profiled in a manner which is advantageous for appropriate guidance of the working medium, is configured appropriately for the working medium parameters, such as pressure and temperature, and extends along a blade or vane axis. A platform, which extends transversely with respect to the blade or vane axis and is formed as a hook pedestal at least in an end region, is formed integrally on the end side of the main blade or vane part in order to attach the turbine blade or vane to its corresponding support, i.e. the shaft or casing.
To achieve a particularly high level of efficiency, gas or steam turbines for driving generators are for thermodynamic reasons designed for particularly high parameters of the working medium flowing into the turbine unit. In the case of steam turbines, this may quite easily mean pressures of over 200 bar and temperatures of over 500° C.
In the case of gas turbines, the temperatures of the working medium flowing into the turbine unit may lie in the range from approximately 1200° C. to approximately 1300° C.
To ensure a high level of reliability and a long service life of a turbine component, in particular a blade or vane, even at very high working medium parameters and correspondingly high thermal loads, turbine components which are exposed to particularly high levels of loading are designed to be coolable.
Furthermore, rotating turbine components are exposed to particularly high mechanical loads in the radial direction. For example, turbine blades or vanes generally have their axis orientated in the radial direction and have to withstand considerable tensile stresses in this direction. The mechanical loads are increased still further since, in modern turbines, the turbine blades or vanes are usually designed as what are known as hollow profiles, in order to ensure cooling of a turbine blade or vane in the inner region by acting on cavities in regions which are exposed to particularly high thermal loads. It has proven expedient to produce a turbine component from a material which has a preferred crystal orientation. For this purpose, the turbine component may be designed as a single crystal component, i.e. the preferred crystal orientation is given by the single crystal structure. A component of this type is also known as an "SX component". Alternatively, however, the preferred crystal orientation may also be produced by the turbine component being designed with a directionally solidified structure. A component of this type is also known as a "DS component". The preferred crystal orientation of the material of the turbine component makes it possible to achieve a particularly good, specifically directed and rapid, dissipation of heat and an ability to withstand tensile loads along the preferred crystal orientation which is considerably higher than with a turbine component made from a material which is isotropic. In the case of a turbine blade or vane, the preferred crystal orientation is expediently arranged along the blade or vane axis. The heat conduction properties of a turbine blade or vane of this type and its ability to withstand tensile loads are therefore particularly expedient along this preferred crystal orientation for operation of the turbine blade or vane in a turbine. Similar measures can also be provided in a similar way for other turbine components.
Turbine components which are exposed to considerable mechanical and thermal loads, in particular turbine blades or vanes, are usually produced entirely or in part, as described in EP 0 815 993 A1, using a casting process which enables the turbine component to be provided with a directionally solidified and/or single crystal structure as a preferred crystal orientation. Therefore, SX or DS blades or vanes are usually cast in a single operation. The casting process means that undercuts, as are used in particular in the case of the turbine blades or vanes with an anchoring platform or cavities as explained above, cannot be achieved or can only be achieved with difficulty. In any event, complex geometries generally lead to high scrap rates, which reduces the economic viability of the casting operation, which has to produce a turbine component of this type as a single component. Hitherto, these high scrap rates have been accepted. One attempt to lower scrap rates in a turbine component with a preferred crystal orientation, in particular in an SX and/or DS turbine component, consists in designing a turbine component of this type such that it is "suitable for casting", i.e. generally with simpler design than was originally desired. This is often to the detriment of the use properties of a turbine component of this type.
To summarize, therefore, it can be concluded that turbine components, in particular rotating components, which are exposed to high thermal and mechanical loads and at the same time have a design which is complex with regard to the casting operation can only be produced with difficulty with a preferred crystal orientation in the casting process. Either high scrap rates have to be accepted or a turbine component design which has been unnecessarily simplified purely for the casting operation has to be accepted. These problems are all the more serious since hitherto a single-crystal or directionally solidified turbine component has had to be cast as a single part using a casting process.

Abstract: Turbine components have to withstand high thermal and mechanical loads. It therefore proves advantageous for them to be made from a material with a preferred crystal orientation. Hitherto, the turbine components with a preferred crystal orientation have been produced as a single piece, with relatively high scrap rates. The proposed concept makes it possible to produce a preferred turbine component (9, 10) in a particularly simple way by assembling a turbine component (9, 10) at least from a first base part (1) and a build-up material (8), the subregion (7) of the joining zone having a preferred crystal orientation (2), so that disadvantageous properties of a joining zone without a preferred crystal orientation (2) which have hitherto been encountered are avoided.


Monaural inputs are accepted for presentation to a pair of speakers. The output sound image from that pair of speakers is such that a listener will perceive that the sound is stereo and that certain sounds come from a non-existent center speaker and that other sounds come from locations beyond the physical boundaries of the two speakers. The system operates to preserve full tone range at both speakers and does not split the sound from a particular instrument between both speakers. The system can be used to provide sound signals to the rear speakers of a multiple speaker system when the sound input to the rear speakers is either monaural or stereo.

1. Technical Field of the Invention
This invention relates to a system and method for expanding sound. More particularly, the invention relates to a system that expands sound images from monaural inputs and/or stereo inputs for presentation to left and right output transducers without loss of information content and without altering the tone or stereo balance while maintaining speech centered in the resultant sound image.
2. Description of Related Art
It is now well known that sound images that would normally be directed to two speakers can be manipulated so that the resulting sound output, as perceived by a listener positioned in front of the speakers, will appear to that listener as coming from a location other than from the physical location of the speaker sets, including locations to the left of the left loudspeaker and to the right of the right loudspeaker.
U.S. Pat. Nos. 5,105,462 and 5,208,860, issued to Lowe, et al. on Apr. 14, 1992, and May 4, 1993, respectively, which patents are hereby incorporated by reference herein, are illustrations of systems for positioning monaural sound images at any desired location around a listener. The Lowe patents take a monaural sound image input and position that sound image at a selected location. The systems discussed in the '462 and '860 patents are herein referred to as the Q1 system.
FIG. 4A is an illustration of a filter based upon the disclosure contained in the '462 and '860 patents. The Q1 filter 40 of FIG. 4A will produce a left virtual image. Q1 filter 40 is comprised of an input for a sound signal 410, circuitry for adjusting the phase and amplitude of the input signal 90, and outputs for the altered signal 413 and the unaltered input signal 412.
FIG. 4B illustrates the effect of positioning of a monaural input signal as is accomplished, for example, by the systems disclosed in the '462 and '860 patents. When a monaural input signal is positioned, a listener 453 located in front of a pair of transducers 450, 451 will perceive the sound as coming from a location 452 other than from the physical location of the speakers.
U.S. Pat. No. 5,440,638, issued to Lowe, et al. on Aug. 8, 1995, which patent is hereby incorporated herein by reference, shows a system for enhancing the stereo sound image by removing the common audio information and adding that common information back so that it is preserved in the output sound image heard by the listener. The system described in the '638 patent is referred to as the QX process.
For example, FIG. 5B illustrates the effect of expansion of a stereo input signal. When a stereo input signal is expanded, a listener 553 Apositioned in front of a pair of transducers 550, 551 will perceive an expanded sound field 552 extending beyond the location of the transducers.
Copending U.S. patent application Ser. No. 08/511,788, filed Aug. 7, 1995, discloses a system for enhancing stereo sound images by removing at least a portion of common audio information. An embodiment of the system described in the copending application is shown in FIG. 5A. The systems described in this copending application are also referred to as QX processes.
Prior art sound expansion systems utilize differences between two input signals to expand the input sound. When two input signals are the same, as in a monaural input signal, there is no significant difference between the two input signals for prior art systems to utilize for expansion purposes. Thus, prior art sound expansion systems cannot satisfactorily expand monaural input signals.
Another major problem when attempting to expand sound from a monaural source is that the resultant sound image must sound "real" and not be overly colored.
Thus, an object of this invention is to give a listener the perception that he/she is hearing stereo sound with a full range of highs and lows spread throughout the hearing pattern when the input signals are monaural.
It is further desired to produce a distributed hearing pattern such that the sound image does not appear to come from any one single position.
A further problem in the prior art when attempting to convert monaural sound signals to pseudo stereo is that certain sounds, such as speech, should appear to come from the center as opposed to from one side. Also, in some situations, the character of an input signal will alternate from monaural to true stereo.
Therefore, it is desired to design a system which can accept such an input without changing the position of various instruments when the character of the input is stereo. For example, if the sounds from the horns arrive on the right input, the system should not change the relative position of the horns within the listening field. Further, the system should not split the horn sounds so that part of the sound range comes from the right speaker and part of the sound range comes from the left speaker.
Thus, there is a need in the art for a system and method for accepting a monaural sound image and for creating from that sound image a stereo sound image available for presentation to left and right transducers without coloring the sound output.
A further need exists for such a system that can work on either digital and analog input signals.
A still further need exists in the art for such a system which can accept both monaural as well as stereo inputs without affecting the stereo output image.


A method and system for configuring a cache memory system in order to efficiently process processor requests. A group of cache elements, which include a Region Cache, a Region Coherence Array, and a lowest level cache, is configured based on a tradeoff of latency and power consumption requirements. A selected cache configuration differs from other feasible configurations in the order in which cache elements are accessed relative to each other. The Region Cache is employed in a number of configurations to reduce the power consumption, latency, and bandwidth requirements of the Region Coherence Array. The Region Cache is accessed by processor requests before (or in parallel with) the larger Region Coherence Array, providing the region coherence state and power efficiently to requests that hit in the Region Cache.

1. Technical Field
The present invention generally relates to data processing systems and in particular to clustered shared-memory multiprocessors. More particularly, the present invention relates to ordering cache accesses in clustered shared-memory multiprocessor systems.
2. Description of the Related Art
To reduce global bandwidth requirements within a computer system, many modern shared-memory multiprocessor systems are clustered. The processors are divided into groups called symmetric multiprocessing nodes (SMP nodes), such that processors within the same SMP node may share a physical cabinet, a circuit board, a multi-chip module, or a chip, thereby enabling low-latency, high-bandwidth communication between processors in the same SMP node. Two-level cache coherence protocols exploit this clustering configuration to conserve global bandwidth by first broadcasting memory requests for a line of data from a processor to the local SMP node, and only sending memory requests to other SMP nodes if necessary (e.g., if it is determined from the responses to the first broadcast that the requested line is not cached on the local SMP node). While this type of two-level cache coherence protocol reduces the computer system global bandwidth requirements, memory requests that must eventually be broadcast to other SMP nodes are delayed by the checking of the local SMP node first for the requested line, causing the computer system to consume more SMP node bandwidth and power. It is important for performance, scalability, and power consumption to first send memory requests to the appropriate portion of the shared-memory computer system where the cached data is most likely to be found.
Coarse-Grain Coherence Tracking with the aid of Region Coherence Arrays is a technique that can improve the performance, scalability, and power consumption of broadcast-based, shared-memory multiprocessor systems. Region Coherence Arrays track coherence status at a coarse granularity, and use this information to route memory requests in order to minimize request latency, conserve interconnect bandwidth and reduce power consumption.
There are three implementation considerations with Coarse-Grain Coherence Tracking facilitated by Region Coherence Arrays: area, latency, and power consumption. First, Region Coherence Arrays need to be somewhat large to be effective, such that the Region Coherence Arrays map several times the data contained in the processor's cache hierarchy. Empirical results show that Region Coherence Arrays with 4 KB regions need at least one-fourth the number of locations of the processor's cache hierarchy to be effective (assuming a 128-byte cache line). Thus, Region Coherence Arrays consume a significant area in facilitating Coarse-Grain Coherence Tracking. Second, and in part due to their size, Region Coherence Arrays may need to be accessed in parallel with the lowest-level cache to minimize the latency added to external requests. The region coherence state is used when a cache miss is detected to route the external request. Third, Region Coherence Arrays can be power-hungry. The non-trivial size of Region Coherence Arrays and a need to be accessed in parallel with the lowest-level cache can lead to considerable power consumption. Thus, power is wasted accessing the Region Coherence Array on lowest-level cache hits.

Efficient processing of data requests with the aid of a region cache

International Business Machines Corporation


An image forming device includes an image support object, a charging unit, an exposure unit, and a developing unit. The image forming device further includes a monitoring unit that sequentially updates a count value to a new count value according to a rotation state and a stop state of the image support object, and an intermittent driving unit that intermittently rotates the image support object according to the new count value generated by the monitoring unit after an image formation operation to form the toner image on the image support object surface is completed.

1. Field of the Invention
This invention relates to an image forming device and a computer-readable recording medium.
2. Description of the Related Art
An image forming device of electrophoto-graphic type according to the related art is known. The image forming device of this type includes a charging part, an exposure part, a developing part, a transfer part, and a cleaning part, which are disposed around the periphery of a cylindrical photoconductor drum. During operation of the image forming device, a toner image is formed on the surface of the photoconductor drum when the photoconductor drum is rotated, and the toner image is transferred from the photoconductor drum to a printing medium, such as a copy sheet.
In the image forming device of this type, a toner charging process is performed with the developing part for frictional charging of a toner in the developing part. The amount of charge of the toner generated by performing the toner charging process varies depending on the temperature and the humidity of the atmosphere in which the toner exists.
There is almost no influence on the amount of charge of the toner by the atmosphere during a normal image formation operation (or a printing operation). However, if the image forming device restarts a printing operation after an end of a standby state being continued over a certain period of time, a significant influence on the amount of charge of the toner by the atmosphere may appear during an image formation operation immediately after the restart due to the humidity change.
Normally, a developing part for supplying a toner to a photoconductor drum is arranged to store the toner in a closed space in order to prevent scattering of the toner. FIG. 1 is a diagram for explaining a movement of toner in a vicinity of a developing device. As illustrated in FIG. 1, a toner 6, a developing roller 3, and a supplying roller 4 are accommodated in a toner container part 2a of a developing device 2. An opening of the developing device 2 is substantially closed by a developing blade 5, the developing roller 3, and a toner return part 2b that constitutes a part of a side wall of the developing device 2.
When the image forming device is in an image formation operation and in a standby state, the gap between the developing blade 5 and the developing roller 3 and the gap between the developing roller 3 and the toner return part 2b are in a closed state with the toner 6.
During the image formation operation, a part of a toner 6b that is delivered from the developing device 2 by the developing roller 3 adheres to a surface 1a of a photoconductor drum 1 to form a toner image (an image formation toner 6c) on the surface 1a of the photoconductor drum 1, and the remainder of the toner 6b is returned through the toner return part 2b to the inside of the developing device 2 (a return toner 6d).
However, if the image forming device is set in a standby state of image formation, the toner 6b outside the developing device 2 remains adhering to the developing roller 3 and is not returned back to the inside of the developing device 2 which is formed as the closed space. As long as the standby state continues, the toner 6b outside the developing device 2 is easily influenced by a change of the environmental temperature or humidity outside the developing device 2.
Generally, during an image formation operation of the image forming device, the portion in the vicinity of the photoconductor drum is subjected to a high-temperature, low-humidity condition (the relative humidity is lowered by a temperature rise). During a standby state of image formation, the high-temperature, low-humidity condition of the portion is gradually changed to be equal to the external environmental temperature and humidity. The toner 6a inside the developing device 2 is not easily influenced by a change of the external environment because it is stored in the closed space of the developing device 2. In contrast, the toner 6b outside the developing device 2 is easily influenced by a change of the environmental temperature and humidity during the standby state, which results in a deterioration of the toner charging performance.
The formation of a toner image on the photoconductor drum 1 during image formation operation is performed using the action of an electric charge of the toner, and a deterioration of the toner charging performance directly affects the image formation state on the photoconductor drum, namely, affecting the image quality. Subsequently, at a next time of image formation, a toner image is formed on the photoconductor drum 1 by using the toner 6b outside the developing device (which has been affected by the surrounding environment during the standby state) and the toner 6a inside the developing device (which is not affected in the closed space). In such a case, belt-like image density irregularities may occur in the toner image due to the difference in the toner charging performance between the toner 6a and the toner 6b.
Conventionally, several approaches to eliminating the problem of image density irregularities due to the change of the toner charging performance have been proposed.
For example, Japanese Laid-Open Patent Publication No. 2004-109980 discloses an image forming device which is arranged to perform a rotating operation to rotate the developing roller each time the image formation stopping time reaches a given period, in order to optimize the image density controlling factors.
Japanese Laid-Open Patent Publication No. 2007-065581 discloses a developing device in which an environmental sensor is disposed in a developing part of each color. This developing device is arranged to optimize the toner charging state in accordance with changes of the humidity of the developing part detected by the sensor.
Japanese Laid-Open Patent Publication No. 2004-264647 discloses an image forming device in which a sensor is disposed in the vicinity of a photoconductor drum to detect a change of the environmental humidity during a standby state of the image forming device. When the humidity change detected by the sensor is large, the photoconductor drum is rotated by a given amount of rotation in order to prevent the image density irregularities which easily take place immediately when the standby state is switched to an active state of image formation operation.
In the image forming device of Japanese Laid-Open Patent Publication No. 2004-109980, the rotating operation to rotate the developing roller is performed at intervals of a fixed time during a standby state, and the influence by the outside environment on the toner adhering to the developing roller can be eliminated. However, in this image forming device, the power consumption during the standby state is increased by the rotating operation of the developing roller performed during the standby state.
In the image forming device of Japanese Laid-Open Patent Publication No. 2007-065581, the change of the environmental state of the toner inside the developing device is detected, but the change of the environmental state of the toner adhering to the portion exposed to the outside of the developing device cannot be detected. It is difficult for this image forming device to eliminate the problem of image density irregularities which easily take place at a time of restarting of an image formation operation immediately after an end of a standby state.
In the image forming device of Japanese Laid-Open Patent Publication No. 2004-264647, the sensor has to be disposed in the vicinity of the photoconductor drum to detect a change of the humidity in the vicinity of the photoconductor drum, which increases the manufacture cost and may put the restrictions on the layout of the image forming device.

Image forming device with an intermittent driving unit and computer-readable recording medium executed by the image forming device


An inspection system for inspecting an object, the system comprising an illuminator including at least one pulsed light source, a detector assembly, and a relative motion provider operative to provide motion of the object relative to the detector assembly, alone an axis of motion, the detector assembly comprising a plurality of 2-dimensional detector units whose active areas are arranged at intervals.

State of the art methods and apparatus for inspection of an article such as a semiconductor wafer or reticle or printed circuit board (PCB) are described in the following patent documents: U.S. Pat. No. 6,816,249; U.S. Pat. No. 6,288,780; U.S. Pat. No. 5,216,479; published US Application No. 2004/0027688. The disclosures of all publications mentioned in the specification and of the publications cited therein are hereby incorporated by reference.

Multi mode inspection method and apparatus


A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which resistance characteristics are enhanced.

1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a mask ROM and fabrication method thereof. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for forming a bit line of a conductive material such as polysilicon to minimize device size and to enhance resistance characteristics.
2. Discussion of the Related Art
Typically, a flat ROM device is named after its structure. The name of the device is attributed to a fact that a step difference of a shape of bit and word lines is smaller than that of another memory device. A mask ROM is the name for specific coding selectively performed to set a specific cell to 0 or 1 through a mask process. Yet, it does not matter that the flat form is used together with the mask ROM.
A mask ROM and fabrication method thereof are explained with reference to the attached drawings as follows.
FIG. 1A is a cross-sectional diagram of a bit line of a mask ROM according to a related art, and FIG. 1B is a cross-sectional diagram of a word line of a mask ROM according to a related art.
Referring to FIG. 1A, in observing a mask ROM according to a related art in a bit line direction, a plurality of word lines are patterned over a substrate 10 having a gate oxide layer 12 formed thereon to leave a prescribed width from one another. Each of the word lines consists of a stack of polysilicon 13a and silicide 14a.
Referring to FIG. 1B, in observing a mask ROM according to a related art in a word line direction, a gate oxide layer 12 is formed on a substrate 10 having a BN (buried N-doped) junction region 11 defined on a prescribed area. A polysilicon layer 13 and silicide 14 are sequentially stacked on the gate oxide layer 12. The gate oxide layer 12 over the BN junction region 11 is formed relatively thicker than the other portion. The BN junction region 11 buried in the substrate 10 plays the role of a bit line.
The above-explained mask ROM of the related art is fabricated in a following manner.
First, a device isolation area (not shown in the drawing) is formed on a semiconductor substrate 10 by LOCOS (local oxidation of silicon) or STI (shallow trench isolation). An area of the semiconductor substrate 10 excluding the device isolation area is defined as an active area.
Subsequently, a well is formed in the active area. A nitride layer (not shown in the drawing) is deposited on the semiconductor substrate 10. A photoresist pattern is formed on the nitride layer. The nitride layer is patterned to correspond to a width of the photoresist pattern. Ion implantation is then carried out on a prescribed portion of the semiconductor substrate 10 to define an impurity region using the patterned nitride layer as a mask. The defined impurity region corresponds to a BN (buried N doped) junction region 11.
After the patterned nitride layer has been removed, the semiconductor substrate 10 is cleaned. A gate oxide layer 12 is formed on the semiconductor substrate 10. In doing so, a portion of the gate oxide layer 12 formed on the BN junction region 11 is formed thicker than the other portion of the gate oxide layer 12.
A polysilicon layer 13 is formed on the gate oxide layer 12. A silicide 14 is formed by performing silicidation on the polysilicon layer 13. The silicide 14 and the polysilicon layer 13 are then selectively removed to form a silicide layer 14a and a gate electrode layer 13a, respectively. The silicide layer 14a is formed on the gate electrode layer 13a to form a stack. The stack consisting of the silicide stack 14a and the gate electrode layer 13a functions as a word line.
Subsequently, a gap between a pair of the stacks is filed up with an insulating layer 15.
Ion implantation is performed to form an LDD region and a heavily doped junction region.
In fabricating the flat cell type mask ROM according to the related art, the BN junction region 11 used as a bit line is formed by implanting ions into a pure active area and by annealing the ion-implanted region.
A region between a pair of the BN junction regions 11 functioning as bit lines, respectively corresponds to a channel of a cell transistor. A pair of the BN junction regions 11 are operative as source and drain, respectively.
The BN junction region 11 is formed relatively long in the flat cell type mask ROM. Inter-line resistance of the BN junction region 11 has considerable bad influence on driving a cell. To maintain the appropriate resistance, a junction depth and a line width need to be appropriately adjusted. Yet, as a cell size is reduced, it is difficult to appropriately implement the junction depth and line width in aspect of channel margin.


A threaded connection for a conduit includes a pin member and a box member. The pin member includes a pin thread having a pin thread crest, a pin thread root, a pin load flank oriented at a pin load flank angle, and a pin stab flank oriented at a pin stab flank angle. The box member includes a box thread having a box thread crest, a box thread root, a box load flank oriented at a box load flank angle, and a box stab flank oriented at a box stab flank angle. At least one of the pin load flank angle, the pin stab flank angle, the box load flank angle, and the box stab flank angle varies over at least part of the threaded connection.

Casing joints, liners, and other oilfield tubulars are often used in drilling, completing, and producing a well. Casing joints, for example, may be placed in a wellbore to stabilize a formation and protect a formation against high wellbore pressures (e.g., wellbore pressures that exceed a formation pressure) that could damage the formation. Casing joints are sections of steel pipe, which may be coupled in an end-to-end manner by threaded connections, welded connections, and other connections known in the art. The connections are usually designed so that a seal is formed between an interior of the coupled casing joints and an annular space formed between exterior walls of the casing joints and walls of the wellbore. The seal may be, for example, an elastomer seal (e.g., an o-ring seal), a thread seal, a metal-to-metal seal formed proximate the connection, or similar seals known in the art.
One type of threaded connection commonly used to form a thread seal in oilfield tubulars is a wedge thread. In FIGS. 1A and 1B, a prior art connection having a wedge thread is shown. "Wedge threads" are characterized by threads, regardless of a particular thread form, that increase in width in opposite directions on a pin member 101 and a box member 102. The rate at which the threads change in width along the connection is defined by a variable commonly known as a "wedge ratio." As used herein, "wedge ratio," although technically not a ratio, refers to the difference between the stab flank lead and the load flank lead, which causes the threads to vary in width along the connection. A detailed discussion of wedge ratios is provided in U.S. Pat. No. 6,206,436 issued to Mallis, and assigned to the assignee of the present invention. That patent is incorporated herein by reference in its entirety.
Wedge threads are extensively disclosed in U.S. Pat. No. RE 30,647 issued to Blose, U.S. Pat. No. RE 34,467 issued to Reeves, U.S. Pat. No. 4,703,954 issued to Ortloff, and U.S. Pat. No. 5,454,605 issued to Mott, all assigned to the assignee of the present invention and incorporated herein by reference. Continuing with FIGS. 1A and 1B, on the pin member 101, a pin thread crest 222 is narrow towards the distal end of the pin member 101 while a box thread crest 291 is wide. Moving along an axis 105 (from right to left), the pin thread crest 222 widens while the box thread crest 291 narrows. Referring still to FIGS. 1A and 1B, the threads are tapered, meaning that a pin thread 106 increases in diameter from beginning to end while a box thread 107 decreases in diameter in a complimentary manner. Having a thread taper can improve the ability to stab the pin member 101 into the box member 102 and distributes stress in the connection.
Generally, thread seals are difficult to achieve with non-wedge threads having broad crests and roots, however, the same thread forms may have thread seals when used for wedge threads. Wedge threads do not have any particular thread form. One example of a suitable thread form is a semi-dovetailed thread form disclosed in U.S. Pat. No. 5,360,239 issued to Klementich, and incorporated herein by reference. Another thread form includes a multi-faceted load flank or stab flank, as disclosed in U.S. Pat. No. 6,722,706 issued to Church, and incorporated herein by reference. Each of the above thread forms is considered to be a "trapped" thread form, meaning that at least a portion of the corresponding load flanks and/or corresponding stab flanks axially overlap. An open (i.e. not trapped) thread form with a generally rectangular shape is disclosed in U.S. Pat. No. 6,578,880 issued to Watts. The above thread forms are examples of thread forms that may be used for embodiments of the invention. Generally, open thread forms such as buttress or stub are not suitable for wedge threads because they would impart a large radial force on the box member. A generally square thread form, such as that disclosed by Watts, or a trapped thread form does not impart an outward radial force on the box member. Those having ordinary skill in the art will appreciate that the teachings contained herein are not limited to particular thread forms.
For wedge threads, a thread seal may be accomplished as a result of the contact pressure caused by interference over at least a portion of the connection between the pin load flank 226 and the box toad flank 225 and between the pin stab flank 232 and the box stab flank 231, which occurs when the connection is made-up. Close proximity or interference between the roots 292 and 221 and crests 222 and 291 completes the thread seal when it occurs over at least a portion of where the flank interference occurs. Generally, higher pressure may be contained wit increased interference between the roots and crests ("root/crest interference") on the pin member 101 and the box member 102 and by increasing flank interference. The particular connection shown in FIG. 1A also includes a metal-to-metal seal that is accomplished by contact pressure between corresponding seal surfaces 103 and 104, respectively located on the pin member 101 and box member 102.
Wedge threads typically do not have a positive stop torque shoulder on the connection. For wedge threads that do not have a positive stop torque shoulder, the make-up is "indeterminate," and, as a result, the relative position of the pin member and box member varies more during make-up for a given torque range to be applied than for connections having a positive stop torque shoulder. As used herein, "make-up" refers to threading a pin member and a box member together. "Selected make-up" refers to threading the pin member and the box member together with a desired amount of torque, or based on a relative position (axial or circumferential) of the pin member with the box member. For wedge threads that are designed to have both flank interference and root/crest interference at a selected make-up, both the flank interference and root/crest interference increase as the connection is made-up (i.e. increase in torque increases flank interference and root/crest interference). For tapered wedge threads that are designed to have root/crest clearance, the clearance decreases as the connection is made-up. Regardless of the design of the wedge thread, corresponding flanks come closer to each other (i.e. clearance decreases or interference increases) during make-up. Indeterminate make-up allows for the flank interference and root/crest interference to be increased by increasing the make-up torque on the connection. Thus, a wedge thread may be able to thread-seal higher pressures of gas and/or liquid by designing the connection to have more flank interference and/or root/crest interference or by increasing the make-up torque on the connection, however, this also increases stress on the connection during make-up, which could lead to failure during use.
Free-running threads used for oilfield tubular connections typically do not form thread seals when the connection is made-up. FIG. 2 shows a prior art connection having free-running threads. The free-running threads include load flanks 154 and 155, stab flanks 157 and 158, crests 159 and 162, and roots 160 and 161. As is typical of a connection with free-running threads, this connection relies on a positive stop torque shoulder formed by the contact of surfaces 151 and 152 disposed on the pin member 101 and the box member 102, respectively. The positive stop torque shoulder shown in FIG. 2 is commonly referred to as a "pin nose shoulder." In other connections, the positive stop torque shoulder may instead be formed by the box face 163 and a mating shoulder (not shown) on the pin member 101. The positive stop torque shoulder also provides a seal. Unlike wedge threads, which make-up by the wedging of the pin thread 106 and the box thread 107, free-running threads rely on the positive stop torque shoulder to load the connection during make-up. To make-up the connection shown in FIG. 2, the pin member 101 and the box member 102 are screwed together until the surfaces 151 and 152 are brought into abutment, at which point the pin load flank 154 and box load flank 155 are also in abutment. Additional torque is applied to the pin member 101 and the box member 102 to load the surfaces 151 and 152 and the pin load flank 154 and box load flank 155 until the desired amount of make-up torque has been applied to the connection.
The connection shown in FIG. 2 does not accomplish a thread seal because of the large gap 153 that exists between the pin stab flank 157 and box stab flank 158. The gap 153 occurs because of how free-running threads with positive stop torque shoulders are loaded. Applying torque to the connection during make-up against the positive stop torque shoulder causes the pin member 101 to be compressed while the box member 102 is stretched in tension. Note that when a box face shoulder is used, the box member 102 is compressed while the pin member 101 is stretched in tension. The force between the pin member 101 and the box member 102 is applied through the pin load flank 154 and box load flank 155. The pin stab flank 157 and the box stab flank 158 are not loaded during make-up. This results in contact pressure between the load flanks 154 and 155 and a gap between stab flanks 157 and 158. As discussed above, a wedge thread (as shown in FIGS. 1A and 1B) is able to form a thread seal in part because of the interference between the load flanks 225 and 226 and the stab flanks 232 and 231. For wedge threads, this occurs near the end of the make-up of the connection because of the varying width of the pin thread 106 and the box thread 107. To have similar interference between the load flanks 154 and 155 and stab flanks 157 and 158 on a cylindrical (i.e. non-tapered) free-running thread and the thread heights are continuous, the interference would exist substantially throughout the make-up of the connection because the pin thread 106 and the box thread 107 have a continuous width. Because the particular connection shown in FIG. 2 is cylindrical (i.e. not tapered), root/crest interference, if any, would exist substantially throughout the make-up of the connection. This could lead to galling of the threads and difficulty in making up the connection.
In the prior art, the angles at which the load flank and the stab flank are disposed relative to the central axis of the threaded connection are constant. As a result, a thread either has an open or trapped thread form for its entire length. Each thread form has advantages depending on its application. For example, a buttress thread form can be advantageous for a shouldered non-wedge connection that will experience a large amount of axial tension and relatively little axial compression. For wedge threads, a dovetailed thread form is often used because it pulls the pin member and the box member together during make-up. Also, an open thread form with positive flank angles can impart large radial forces as a result of the wedging force between the pin thread and the box thread.
In some connections, more than one thread form may be advantageous; however, one thread form must be selected over the other. The advantage of multiple thread forms in a connection was recognized in U.S. Pat. No. 6,767,035 issued to Hashem. The '035 patent discloses a shouldered connection having multiple threads formed on both the pin member and the box member. The cutting of multiple threads, sometimes referred to as a "multi-start" thread, results in a threaded connection that has an alternating open and closed thread form in a two-dimensional cross-section. Embodiments disclosed in the '035 patent have two threads formed on the pin member and the box member. One thread has an open thread form, such as a stub acme. The other thread has a trapped thread form, such as dovetailed or hooked. Such a combination of thread forms results in advantages of both thread forms existing uniformly over the length of the connection.
The stresses experienced by a threaded connection are not uniform over the length of a thread, for example, during bending of the distal ends and the middle portion of the threaded connection. As a result, a particular thread form can be the best for one part of the connection, but not for another. Thus, what is still needed is a threaded connection that allows for the thread form to be selected over different portions of the connection to distribute stresses.

Threaded connection with variable flank angles


Disclosed is a high field asymmetric waveform ion mobility spectrometer (FAIMS) having a side-to-side electrode geometry. The FAIMS includes an inner electrode (102) having a length and an outer surface that is curved in a direction transverse to the length. The FAIMS also includes an outer electrode (104) having a length, a channel extending therethrough along at least a portion of the length, and a curved inner surface, a portion of the length of the outer electrode overlapping a portion of the length of the inner electrode so as to provide an analyzer region therebetween. The outer electrode has an ion inlet (114) for introducing ions from a source of ions into the analyzer region and an ion outlet (112) for extracting ions from the analyzer region, the ion inlet and the ion outlet being disposed on opposing sides of the outer electrode. The FAIMS is characterized in that at least one of the inner and outer electrodes is shaped such that a width of the analyzer region in the vicinity of the ion outlet is other than a width of the analyzer region in at least one other region.

High sensitivity and amenability to miniaturization for field-portable applications have helped to make ion mobility spectrometry (IMS) an important technique for the detection of many compounds, including narcotics, explosives, and chemical warfare agents as described, for example, by G. Eiceman and Z. Karpas in their book entitled "Ion Mobility Spectrometry" (CRC Boca Raton, 1994). In IMS, gas-phase ion mobilities are determined using a drift tube with a constant electric field. Ions are separated in the drift tube on the basis of differences in their drift velocities. At low electric field strength, for example 200 V/cm, the drift velocity of an ion is proportional to the applied electric field strength, and the mobility, K, which is determined from experimentation, is independent of the applied electric field. Additionally, in IMS the ions travel through a bath gas that is at sufficiently high pressure that the ions rapidly reach constant velocity when driven by the force of an electric field that is constant both in time and location. This is to be clearly distinguished from those techniques, most of which are related to mass spectrometry, in which the gas pressure is sufficiently low that, if under the influence of a constant electric field, the ions continue to accelerate.
E. A. Mason and E. W. McDaniel in their book entitled "Transport Properties of Ions in Gases" (Wiley, N.Y., 1988) teach that at high electric field strength, for instance fields stronger than approximately 5,000 V/cm, the ion drift velocity is no longer directly proportional to the applied electric field, and K is better represented by KH, a non-constant high field mobility term. The dependence of KH on the applied electric field has been the basis for the development of high field asymmetric waveform ion mobility spectrometry (FAIMS). Ions are separation in FAIMS on the basis of a difference in the mobility of an ion at high field strength, KH, relative to the mobility of the ion at low field strength, K. In other words, the ions are separated due to the compound dependent behavior of KH as a function of the applied electric field strength.
In general, a device for separating ions according to the FAIMS principle has an analyzer region that is defined by a space between first and second spaced-apart electrodes. The first electrode is maintained at a selected dc voltage, often at ground potential, while the second electrode has an asymmetric waveform V(t) applied to it. The asymmetric waveform V(t) is composed of a repeating pattern including a high voltage component, VH, lasting for a short period of time tH and a lower voltage component, VL, of opposite polarity, lasting a longer period of time tL. The waveform is synthesized such that the integrated voltage-time product, and thus the field-time product, applied to the second electrode during each complete cycle of the waveform is zero, for instance VHtH+VLtL=0; for example +2000 V for 10 μs followed by −1000 V for 20 μs. The peak voltage during the shorter, high voltage portion of the waveform is called the "dispersion voltage." or DV, which is identically referred to as the applied asymmetric waveform voltage.
Generally, the ions that are to be separated are entrained in a stream of gas flowing through the FAIMS analyzer region, for example between a pair of horizontally oriented, spaced-apart electrodes. Accordingly, the net motion of an ion within the analyzer region is the sum of a horizontal x-axis component due to the stream of gas and a transverse y-axis component due to the applied electric field. During the high voltage portion of the waveform an ion moves with a y-axis velocity component given by vH=KHEH, where EH is the applied field, and KH is the high field ion mobility under operating electric field, pressure and temperature conditions. The distance traveled by the ion during the high voltage portion of the waveform is given by dH=vHtH=KHEHtH, where tH is the time period of the applied high voltage. During the longer duration, opposite polarity, low voltage portion of the asymmetric waveform, the y-axis velocity component of the ion is vL=KEL, where K is the low field ion mobility under operating pressure and temperature conditions. The distance traveled is dL=vLtL=KELtL. Since the asymmetric waveform ensures that (VHtH)+(VLtL)=0, the field-time products EHtH and ELtL are equal in magnitude. Thus, if KH and K are identical, dH and dL are equal, and the ion is returned to its original position along the y-axis during the negative cycle of the waveform. If at EH the mobility KH>K, the ion experiences a net displacement from its original position relative to the y-axis. For example, if a positive ion travels farther during the positive portion of the waveform, for instance dH>dL, then the ion migrates away from the second electrode and eventually will be neutralized at the first electrode.
In order to reverse the transverse drift of the positive ion in the above example, a constant negative dc voltage is applied to the second electrode. The difference between the dc voltage that is applied to the first electrode and the dc voltage that is applied to the second electrode is called the "compensation voltage" (CV). The CV voltage prevents the ion from migrating toward either the second or the first electrode. If ions derived from two compounds respond different to the applied high strength electric fields, the ratio of KH to K may be different for each compound. Consequently, the magnitude of the CV that is necessary to prevent the drift of the ion toward either electrode is also different for each compound. Thus, when a mixture including several species of ions, each with a unique KK/K ratio, is being analyzed by FAIMS, only one species of ion is selectively transmitted to a detector for a given combination of CV and DV. In one type of FAIMS experiment, the applied CV is scanned with time, for instance the CV is slowly ramped or optionally the CV is stepped from one voltage to a next voltage, and a resulting intensity of transmitted ions is measured. In this way a CV spectrum showing the total ion current as a function of CV, is obtained.
Guevremont et al. have described the use of curved electrode bodies for instance inner and outer cylindrical electrodes, for producing a two-dimensional atmospheric pressure ion focusing effect that results in higher ion transmission efficiencies than can be obtained using, for example, a FAIMS device having parallel plate electrodes. In particular, with the application of an appropriate combination of DV and CV an ion of interest is focused into a band-like region in the annular gap between the cylindrical electrodes as a result of the electric fields which change with radial distance. Focusing the ions of interest has the effect of reducing the number of ions of interest that are lost as a result of the ion suffering a collision with one of the inner and outer electrodes. FAIMS devices with cylindrical electrode geometry have been described in the prior art, as for example in U.S. Pat. No. 5,420,424, the contents of which are incorporated herein by reference.
In WO 00/08455, the contents of which are incorporated herein by reference. Guevremont and Purves describe a domed-FAIMS analyzer. In particular, the domed-FAIMS analyzer includes a cylindrical inner electrode having a curved surface terminus proximate an ion outlet orifice of the FAIMS analyzer region. The curved surface terminus is substantially continuous with the cylindrical shape of the inner electrode and is aligned co-axially with the ion outlet orifice. During use, the application of an asymmetric waveform to the inner electrode results in the normal ion-focusing behavior as described above, and in addition the ion-focusing action extends around the generally spherically shaped terminus of the inner electrode. This causes the selectively transmitted ions to be directed generally radially inwardly within the region that is proximate the terminus of the inner electrode. Several contradictory forces are acting on the ions in thus region near the terminus of the inner electrode. The force of the carrier gas flow tends to influence the ions to travel towards the ion-outlet orifice, which advantageously also prevents the ions from migrating in a reverse direction, back towards the ion source. Additionally, the ions that get too close to the inner electrode are pushed back away from the inner electrode, and those near the outer electrode migrate back towards the inner electrode, due to the focusing action of the applied electric fields. When all forces acting upon the ions are balanced, the ions are effectively captured in every direction, either by forces of the flowing gas, or by the focusing effect of the electric fields of the FAIMS mechanism. This is an example of a three-dimensional atmospheric pressure ion trap, as described in greater detail by Guevremont and Purves in WO 00/08457, the contents of which are incorporated herein by reference.
Guevremont and Purves further disclose a near-trapping mode of operation for the above-mentioned domed-FAIMS analyzer, which achieves ion transmission from the domed-FAIMS to a mass spectrometer with high efficiency. Under near-trapping conditions, the ions that accumulate in the three-dimensional region of space near the spherical terminus of the inner electrode are caused to leak from this region, being pulled by a flow of gas towards the ion-outlet orifice. The ions that are extracted from this region do so as a narrow, approximately collimated beam, which is pulled by the gas flow through the ion-outlet orifice and into a smaller orifice leading into the vacuum system of the mass spectrometer. Accordingly, a tandem domed-FAIMS/MS device is a highly sensitive instrument that is capable of detecting and identifying ions of interest at part-per-billion levels.
More recently, in WO 01/69216 the contents of which is incorporated herein by reference, Guevremont and Purves describe a so-called "perpendicular-gas-flow-FAIMS", which is identically referred to as a side-to-side FAIMS. The analyzer region of the side-to-side FAIMS is defined by an annular space between inner and outer cylindrical electrodes. In particular, ions that are introduced into the analyzer region of the side-to-side FAIMS are selectively transmitted in a direction that is generally around the circumference of the inner electrode. For instance, the ion inlet and the ion outlet of a side-to-side FAIMS device are disposed, one opposing the other, within a surface of the outer electrode such that ions are selectively transmitted through the curved analyzer region between the ion inlet and the ion outlet along a continuously curving ion flow path absent a portion having a substantially linear component. In particular, the ions travel from the ion inlet to the ion outlet by flowing around the inner electrode in one of a "clock-wise" and a "counter clock-wise" direction. This is in contrast to the above-mentioned FAIMS devices in which the ions are selectively transmitted along the length of the inner electrode.
Advantageously, the side-to-side FAIMS device reduces the minimum distance that must be traveled by the ions within the analyzer region to approximately fifty per cent of the circumference of the inner electrode. Since the ions split into two streams traveling in opposite directions around the inner electrode after they are introduced through the ion inlet, the effective ion density within the analyzer region is reduced, and so too is the ion-ion repulsion space charge effect reduced. Furthermore, the reduction of the minimum ion travel distance has the added benefit of improving the ion transmission efficiency. For example, by keeping the time for travel short, the effect of diffusion and ion-ion repulsion forces are minimized. In keeping distances short, the transit time of the ions through the analyzer region is also short, which supports more rapid analysis of ion mixtures.
The side-to-side electrode geometry is readily adapted for use with a conventional electrospray ionization source. It has been determined experimentally that the analysis of peptides and proteins using mode P2, that is fir positive ions using a negative DV, gave results comparable to those obtained using a domed-FAIMS device. It is a limitation of the side-to-side FAIMS, however, that the analysis of several low molecular weight species, that is a molecular weight of less than approximately 200–300 Da, using mode N1, that is for negative ions using a negative DV, resulted in a lower signal intensity compared to the results that were obtained using the domed-FAIMS device. This result was not entirely unexpected, in view of the specific steps that are performed for optimizing the performance of a domed-FAIMS device. In particular, the distance between the hemispherical tip of the inner electrode and the ion outlet, referred to as the extraction region, is adjusted so as to optimize signal intensity. For the domed-device, in general, the distance is slightly larger for peptides and proteins than it is for the low molecular weight species. Furthermore, when using mode N1, optimal results are obtained when the distance between the inner and outer electrodes is less in the extraction region than it is in the remainder of the analyzer region.
Of course, it is relatively straightforward to vary the inter-electrode spacing in extraction region of the domed-FAIMS devices. For example, this optimization is easily achieved in the domed-FAIMS devices by relatively moving the inner electrode toward the ion outlet in the outer electrode, which affects only the spacing near the ion outlet. In particular, the analyzer region of a domed-FAIMS device is defined between the cylindrical inner surface of the outer electrode and the cylindrical outer surface of the inner electrode. Accordingly, the inter-electrode spacing, and therefore the conditions for selectively transmitting ions, does not change within the analyzer region of a domed-FAIMS device when the inner electrode is moved in a longitudinal direction relative to the outer electrode. As will be obvious to one of skill in the art, such is not the case for a FAIMS having a side-to-side electrode geometry. In particular, relatively moving the inner electrode toward the ion outlet in the outer electrode of a side-to-side FAIMS results not only in changes to the inter-electrode spacing proximate the ion outlet, but also elsewhere in the analyzer region. By making such an adjustment, the overall ion transmission efficiency through the side-to-side FAIMS device is likely to be lower, since the resulting changes in electric fields within the analyzer region are likely to cause a disproportionate increase in ion losses.
It would be advantageous to provide a FAIMS apparatus including a detection system that overcomes the limitations of the prior art.

Side-to-side FAIMS apparatus having an analyzer region with non-uniform spacing and method therefore


A subscriber or other user is provided with access to a subscription service of a signal distribution system at a roaming location remote from a home location of the user. The home and remote locations are serviced by respective first and second head ends of the system. The subscription service comprises a plurality of selectable channels available to the user at the home location. The second head end obtains content for at least one channel of the subscription service available to the user at the home location, and inserts the content into a program stream utilizable for delivery of content to an interface device at the remote location to thereby make the channel accessible to the user at the remote location. In one embodiment, responsive to a channel change command initiated by the user via an interface device at the remote location, the second head end first determines if content for the newly-selected channel is already available in the second head end as a result of subscription services provided to any other user serviced by the second head end. If the content for the newly-selected channel is already available in the second head end, the second head end immediately makes that content accessible to the user at the remote location without obtaining it from the first head end.

Conventional signal distribution systems include, by way of example, cable television systems, satellite television systems, and systems providing IPTV over digital subscriber line (DSL) or fiber. Such systems are configured to distribute media streams associated with subscription television services to system subscribers or other users. Subscription television services are usually tied to a particular household or other predetermined subscriber location. Typically, a given subscriber is provided with an interface device, such as a set-top box or receiver, for communicating with system head end equipment. The interface device is configured to permit the subscriber to receive, on a television or other presentation device coupled to the interface device at a home location, the particular subscription television services to which that subscriber is entitled by virtue of the subscription. A given subscription may encompass, by way of example, a number of basic broadcast channels, as well as one or more premium programming channels, such as movie channels, sports channels, specialty channels, pay-per-view channels, on-demand video channels, etc.
A serious drawback of conventional cable, satellite and IPTV systems is that there is typically no roaming capability provided for subscribers. That is, subscribers generally must be at their respective home locations in order to receive the television services to which they have subscribed. By way of example, if a first subscriber leaves his or her home location and visits a remote location that also serves as a home location for a second subscriber, there is no mechanism provided for allowing the first subscriber to access his or her subscription television services at the second subscriber location. Thus, if the first subscriber has paid for access to a premium programming channel at his or her home location, that subscriber has no ability to access the premium programming channel at the remote location. This is the case even if the remote location, that is, the home location of the second subscriber, has the same television service provider and type of interface device as the home location of the first subscriber.
The above-cited U.S. patent application Ser. No. 11/130,329 discloses techniques which address and solve the remote accessibility problem. In one embodiment disclosed therein, an arrangement is provided whereby subscribers can access their usual home location subscription television services when at remote locations, without the need for carrying media devices, communications devices or other equipment to the remote locations.
Further advances in remote accessibility are described in the above-cited U.S. patent application Ser. No. 11/145,832. As disclosed therein, users of a cable, satellite or IPTV system, or other type of signal distribution system, may be provided with access to user-defined content that is obtained by a service provider from one or more external networks. A user-defined channel, comprising content specified by a system user, is provided as one of a plurality of channels of a subscription service in a signal distribution system. The user-defined channel may comprise, for example, a tracking channel that identifies a current location of at least one entity, such as a particular family member, specified by the system user. As another example, the user-defined channel may comprise a video monitoring channel, with the video signals being sourced from video cameras at one or more monitored locations.
Despite the considerable advances provided by the techniques described in U.S. patent application Ser. Nos. 11/130,329 and 11/145,832, a need remains for additional improvements in providing user accessibility to subscription television services or other content via cable, satellite and IPTV systems, as well as other types of signal distribution systems.

Method and apparatus for delivering subscription service content to roaming users


Embodiments of the present invention provide systems, methods, and computer storage media directed to generating training image data for a convolutional neural network, encoding parameters into a convolutional neural network, and employing a convolutional neural network that estimates camera calibration parameters of a camera responsible for capturing a given digital image. A plurality of different digital images can be extracted from a single panoramic image given a range of camera calibration parameters that correspond to a determined range of plausible camera calibration parameters. With each digital image in the plurality of extracted different digital images having a corresponding set of known camera calibration parameters, the digital images can be provided to the convolutional neural network to establish high-confidence correlations between detectable characteristics of a digital image and its corresponding set of camera calibration parameters. Once trained, the convolutional neural network can receive a new digital image, and based on detected image characteristics thereof, estimate a corresponding set of camera calibration parameters with a calculated level of confidence.

There are a variety of use cases where one may find utility in being able to determine or estimate parameters of a camera that had previously captured an image. For instance, compositing visual elements or virtual objects into a photograph would require a skillful rendering of a virtual object into a scene with accurate perspective, scale, rotation, and the like, such that the object appears as if it belonged therein. Even the slightest errors in the rendering process can throw off realism of a composition. To render the virtual object with precise detail, one would require an accurate estimation or determination of the camera calibration parameters that were employed when the photograph was taken. While various techniques of camera parameter estimation have been generally known to those skilled in the art, such techniques require tedious and error-prone measurements and calculations.

This patent is subject to a terminal disclaimer.