A method and system for ascertaining warranty issues associated with transportation products is provided. Transportation products are manufactured at a factory, and as the products are made, historical information concerning significant events related to the manufacturing process may be stored. As the transportation product is delivered to a retail outlet, other significant event information may be stored. Locations are determined within a region for warranty claims related to the servicing of selected transportation products. Product history information for the selected transportation products may be retrieved from one or more databases. Data mining algorithms may be employed to generate input data for forming a set of spatial relationships. The locations of products within the region are then associated with the product history information to form a set of spatial relationships. Product history information may include such information as purchaser address information, information related to manufacture of the selected transportation products, information related to transportation of the selected transportation products from a manufacturing site to a retail outlet, etc.

1. Technical Field
The present invention relates to an improved data processing system and, in particular, to a method and system for a specific business application of database processing.
2. Description of Related Art
As businesses become more productive and profit margins seem to be reduced, relationships between businesses and its customers become more valuable. Businesses are more willing to protect those relationships by spending more money on information technology. Because an enterprise may collect significant amounts of data concerning their operations and the flow of goods to and from the enterprise, some of the expenditures on information technology are used to xe2x80x9cminexe2x80x9d these collections of data to discover customer relationships that are useful to the enterprise.
Data mining allows a user to search large databases and to discover hidden patterns in that data. Data mining is thus the efficient discovery of valuable, non-obvious information from a large collection of data and centers on the automated discovery of new facts and underlying relationships in the data. The term xe2x80x9cdata miningxe2x80x9d comes from the idea that the raw material is the business data, and the data mining algorithm is the excavator, shifting through the vast quantities of raw data looking for the valuable nuggets of business information.
Certain businesses desire a better understanding of customers and purchased products, and data mining has been used in an attempt to discover relationships between customers and purchases. One class of relationships for which some businesses desire guidance is the relationship between failure of transportation products, such as cars, trucks, minivans, etc., and the appearance of warranty claims for the products. Business may own several databases from which such relationships could be extracted if the proper methodologies could be applied. However, data mining analysis heretofore has been concerned primarily with relationships between customer characteristics and product characteristics. However, one of the aspects of the customer-retailer relationship that is not assessed by data mining is the geographic relationship between the customer and the retailer. Spatial analysis using a Geographic Information System (GIS) is used to delineate those geographic relationships. For example, much of a relationship between a customer and retail relationship or a manufacturer and its retail distribution points can be related to the way that customer product complaints are handled. The spatial relationships between the locations of product failures and the location of their repairs cannot be assessed without the use of GIS. Therefore, if there were geographic factors that bear upon the reason for the failure, they would not be considered.
Therefore, it would be advantageous to provide a method and system for data analysis that discovers relationships between the cause for transportation product failures and the locations of other entities or events which may contribute to the cause of the product failures. These may include data such as the retail outlets at which the transportation products were purchased, the manner in which the transportation products were shipped to the retail outlets as well as the manner in which the transportation product is used and the location of the area of its primary use in comparison to the repair facility that undertakes repairs of the damaged product when it is under warranty. Much of the respective geographic relationships between these data can contribute to the validity of warranty claims that are filed against the manufacturer""s warranty by the retailer who repairs the transportation product. The validity or non-validity of these claims effect the well being of the relationship between the retailer who sold and/or who repaired the damaged transportation product as well as the continued good relationship between the manufacturer, the retailer, and their ultimate transportation product customer.
A method and system for ascertaining warranty issues associated with transportation products is provided. Transportation products are manufactured at a factory, and as the products are made, historical information concerning significant events related to the manufacturing process may be stored. As the transportation product is delivered to a retail outlet, other significant event information may be stored. Locations for the repair of the products under warranty may be related to the servicing of selected transportation products as well as their use. Product history information for the selected transportation products may be retrieved from one or more databases. Data mining algorithms may be employed to generate input data into a GIS for an analysis that will allow the formulation of a set of spatial relationships.
In this process, the locations of products within a region are associated with the product history information to form a set of spatial relationships between events that have led up to the repair of the product as well as the location of that repair with respect to the original retailer selling the product. Product history information may include such information as purchaser address information, information related to manufacture of the selected transportation products, information related to transportation of the selected transportation products from a manufacturing site to a retail outlet, primary use of the transportation product, etc. To understand the validity of a warranty claim filed against the manufacturer warranty by the repairer of a damaged transportation product, one must not only consider the attributes related to the cause for the damage but the spatial relationships between those attributes.

Method and system for integrating spatial analysis and data mining analysis to ascertain warranty issues associated with transportation products

International Business Machines Corporation


An integrated circuit including a serial interface (12) having a nonvolatile memory (30) coupled to a and configuration of circuit boards and entire systems. A configurable circuits (10) containing switches, resistors, capacitors or digital logic devices has an unique identification code and is electrically configured by connection to a nonvolatile memory (30). An interrogation shift register (38) and a configuration data shift register (36) are serially connected to receive a serial bit stream (50) containing an interrogation code section and a configuration data section. The interrogation code, which is identical to the identification code of a selected one of the configurable circuits, is compared with the circuit. identification code to provide a match pulse (42) that enables a program signal to initiate transfer of data from the data shift register (36) to the nonvolatile memory (30).

1. Field of the Invention
The present invention relates to configurable circuits and more particularly concerns circuits that can be electrically configured and re-configured.
2. Description of Related Art
Many electronic circuits, including circuit boards and entire electronic systems, must be trimmed and configured either upon completion of manufacture, at installation or after some time of use. Often circuit components will drift due to aging or environmental factors, and thus need be adjusted for proper operation. Other circuits require such adjustments in order to alter operation and function of the circuit. Thus it is frequently desirable to selectively vary or adjust such circuit operations and parameters as frequency, resistance, capacitance, switch selection and data line selections. Presently trimming and configuration or reconfiguration of such circuits and system is accomplished by use of mechanical DIP switches and potentiometers, or sometimes by laser trimming of circuit components. These methods are slow or may require expensive equipment. Mechanical trimming switches, potentiometers and the like are expensive, relatively difficult to build and assemble, require physical access to the device and are inherently less reliable than electronic components. Laser trimming equipment is expensive and is generally available only upon manufacture of circuitry, and cannot be accomplished in the field.
Circuits have been programmed by use of EEPROM memories, but such prior art is able to handle configuration of several circuits only with great complexity and increased numbers of control lines. Prior arrangements, furthermore, make no provisions for digital readout of the actual configuration of the device, and, moreover, have been available only for a configurable potentiometer or an array of resistors.
Where circuit boards or systems operate in environments or packages that make access difficult, or where such circuits or devices are encapsulated, the circuit boards and systems may require trimming, adjustment or other reconfiguration which cannot be accomplished in presently available mechanical systems.
Accordingly, it is an object of the present invention to provide configurable circuits that avoid or minimize above mentioned problems.

Nonvolatile serially programmable devices


In an example embodiment a sender report containing multiple rows and/or columns of information drawn from a data table may be displayed to a user of a machine. A user may select a portion of the displayed information. A sender adaptor may extract report-to-report selection criteria from the selected information. A receiver adaptor may identify other data tables where information related to the report-to-report selection criteria resides. If such information resides in multiple data tables, the receiver adaptor may join the multiple data tables into one or more data tables. The receiver adaptor may convert the report-to-report selection criteria into selection criteria for the identified data table(s) or joined data table(s). The selection criteria may be passed to a generic receiver report adapted to retrieve any information from any data table(s). The generic receiver report may retrieve information according to the selection criteria and display the information to the user.

Report-to-report functionality may be used to connect reports within a system. This functionality, however, requires custom tailored sender and receiver reports to make sure that they "fit together" in their definition, selection criteria and database tables. No general way exists that allows general information from one report to be used to select information that may reside in other places in the system.

System and method for report to report generation


An improved, walled-emitter, bipolar transistor and a method for fabricating such a transistor is disclosed. The method includes the step of separately doping the edges of the active base that are adjacent to the isolation oxide in order to increase the doping level at the edges and thus counteract base narrowing that would otherwise be present.

1. Field of the Invention
This invention relates generally to bipolar transistors, and relates more particularly to a walled-emitter, polysilicon-contact, bipolar transistor having improved base characteristics, and a method for fabricating such a transistor.
2. Description of the Relevant Art
A walled-emitter, bipolar transistor has an emitter and active base that extend to an isolation oxide at one or more places. FIG. 1 depicts a plan view of a vertical, walled-emitter, bipolar transistor 10. The dashed lines 12 define boundaries between the doped regions of the transistor 10 and a surrounding isolation oxide 14. A collector contact 16, a base contact 18, and an emitter contact 20 form electrical connections with the collector, base, and emitter, respectively, of the transistor. The emitter of transistor 10 is in the doped region below the emitter contact 20. The emitter extends to the isolation oxide 14 at two locations 22 and 24. The active base of transistor 10 is below the emitter region and also extends to the isolation oxide 14 at locations 22 and 24. One advantage of walled-emitter transistor design is that it makes effective use of the active base area while minimizing the parasitic collector-base capacitance for a given emitter area.
Connections or contacts to the doped regions of a bipolar transistor can be made with polysilicon, which effectively adds one level of interconnection among devices. Polysilicon contacts for bipolar transistors are common for integrated circuits having both bipolar and MOS (or CMOS) devices on the same chip.
A process for fabricating polysilicon-contact, bipolar NPN transistors typically includes the following steps. After n+ buried layers and an epitaxial layer are formed on the substrate, isolation oxide is formed to isolate regions of the substrate into n-type wells for separate transistors. Then, a layer of polysilicon is deposited on top of the substrate. The polysilicon is implanted with a p-type dopant, like boron, and diffused into the substrate to form the base of a bipolar transistor. Then, portions of the substrate are masked and the polysilicon is implanted with an n-type dopant, like arsenic, to form the emitter and emitter contacts of the bipolar transistor. The substrate is masked again and the polysilicon is implanted with a p-type dopant to form the base contacts of the transistor. During this last step, the emitter region is masked so that the p-type dopants do not enter the emitter region. After implantation, the substrate is annealed to diffuse the dopants into the silicon substrate. The three implantation steps described above may be referred to as a base implant, an n+ polysilicon implant, and a p+ polysilicon implant, respectively. The order of the n+ and p+ polysilicon implant steps is interchangeable.
One constraint to fabricating high performance, polysilicon-contact transistors with walled-emitters is the effect that device isolation can have on key parameters like leakage current (Iceo) and breakdown voltage (BVceo). As shown in FIG. 2, the problem is that a typical walled-emitter transistor has an active base region 26 that is thinner at the isolation edges 22 and 24. Note that the emitter region 28 extends to the isolation oxide 14, making it a "walled-emitter" at locations 22 and 24. Also shown in FIG. 2 are a buried layer 30 and a substrate 32. The buried layer 30 is part of the collector region of the transistor 10.
The active base 26 is thinner at the isolation edges 22 and 24 because the base implantation is less effective at those locations. When the base is formed during the base implant, an angled edge or "bird's beak" of the isolation oxide overlaps and shields the edge of the base. During the base implant, the bird's beak absorbs some of the implanted atoms, so that fewer dopant atoms are implanted at the edge of the base. Also, some of the base dopant atoms that are implanted at the edges of the base will diffuse laterally from the base into the oxide during subsequent annealing steps. The combined result of shielding by the oxide bird's beak and lateral diffusion into the oxide is that the active base 26 is thinner at the isolation edges 22 and 24 that it is away from the edges.
The thinner base 26 at the isolation edges 22 and 24 provides a site for current leakage between the emitter 28 and collector 30 and also decreases breakdown voltage. Breakdown voltage can be so low that the transistor cannot operate at maximum supply voltages. Vertical scaling of such a transistor is severely constrained, compromising device parameters such as beta and unity gain cutoff frequency, which are determined by base thickness.
One approach to overcoming the above-described problem is to laterally extend the oxide well region and open up a gap between the oxide and the edge of the emitter region. Such a transistor is not a "walled-emitter" transistor because the emitter does not extend to the oxide wall. The transistor would have an active base under the emitter of relatively uniform thickness, unaffected by the edge of the isolation oxide. A disadvantage of this approach is that more surface area is needed to fabricate a transistor having comparable performance to that of a wall-emitter transistor.

Making walled emitter bipolar transistor with reduced base narrowing


The present invention is an integral magnetic head suspension and method for making the same. The integral suspension, with or without the head, contains integrated conductive circuits that have multiple cross overs for noise reduction. The suspension is fabricated completely on silicon (Si) wafers using semiconductor processes. A N+ silicon layer is disposed over a P- silicon wafer. The N+ silicon layer and the P- silicon water are thermally oxidized to generate a bottom silicon oxide layer opposite the N+ layer side of the wafer and a top silicon oxide layer on the N+ side of the wafer, and to drive the N+ silicon into the P- silicon wafer. A layer of polysilicon is disposed over the silicon oxide layer on top of the N+ silicon layer. One or more pairs of conductive traces having multiple cross-overs are fabricated on the layer of polysilicon. Optimally, a magnetic head is simultaneously fabricated on the suspension. The polysilicon layer is then patterned to define the head structure and suspension structure as one piece. Finally, the magnetic head and suspension are separated from the wafer by removing the first silicon oxide layer by a chemical etchant and the P- silicon wafer by selective etching. The head and suspension are released from the silicon wafer as a single structure using the above-described semiconductor processes. Accordingly, no grinding or cutting is used to define the dimensions of the head. Further, no processes are required to attach the head to the suspension and the suspension can be made from low mass materials such as silicon (Si) or Al.sub.2 O.sub.3.

1. Field of the Invention
This invention relates in general to integral recording head suspensions, and more particularly, to a low noise integrated conductor magnetic recording head suspension fabricated as one single structure using semiconductor processes and a method for making the same.
2. Description of Related Art
Moving magnetic storage devices, especially magnetic disk drives, are the memory device of choice. This is due to their expanded non-volatile memory storage capability together with a relatively low cost. Accurate retrieval of the stored information from these devices becomes critical, requiring the magnetic transducer to be positioned as close to the storage media as possible. Optimally, the transducer may actually contact the media.
Magnetic disk drives are information storage devices which utilize at least one rotatable magnetic media disk having concentric data tracks defined for storing data, a read/write transducer for reading data from and/or writing data to the various data tracks, a slider for supporting the transducer adjacent the data tracks typically in a flying mode above the storage media, a suspension assembly for resiliently supporting the slider and the transducer over the data tracks, and a positioning actuator coupled to the transducer/slider/suspension combination for moving the transducer across the media to the desired data track and maintaining the transducer over the data track center line during a read or a write operation. The transducer is attached to or is formed integrally with the slider which supports the transducer above the data surface of the storage disk by a cushion of air, referred to as an air bearing, generated by the rotating disk.
Alternatively, the transducer may operate in contact with the surface of the disk. Thus the suspension provides desired slider loading and dimensional stability between the slider and an actuator arm which couples the transducer/slider/suspension assembly to the actuator. The suspension is required to maintain the transducer and the slider adjacent the data surface of the disk with as low a loading force as possible. The actuator positions the transducer over the correct track according to the data desired on a read operation or to the correct track for placement of the data during a write operation. The actuator is controlled to position the transducer over the desired data track by shifting the combination assembly across the surface of the disk in a direction generally transverse to the data tracks.
The development of thin film magnetic recording heads and suspensions have become the subject of increased interest, especially in the area of high speed, high density recording and retrieval of digital computer information on magnetic media.
Conventional thin film magnetic recording heads are produced using suitable material know in the art such as alumina-titanium-carbide (AlTiC) or silicon for example, and are suspended on stainless steel flexures using physical and mechanical methods. Twisted pairs of copper wire or parallel, single-layer integrated circuits, often referred to as copper traces, are used to electrically connect the magnetic recording head to the recording channel.
Known methods for fabricating single-layer integrated circuits on suspensions typically consist of sequentially depositing thin film layers of conductive, and insulative materials on a rigid substrate. The delineated layer of conductive thin films provides electrical interconnection between the heads and the power supply/addressing network which is used to activate the drive. Finally, insulator thin film layers (polyimides, SiO.sub.2) are used to electrically isolate the various thin film conductor layers. The various thin film layers are typically deposited by a variety of techniques including vacuum deposition (sputtering, evaporation), electroplating, and spin-coating (e.g., for spin-on insulator materials).
Although it is known that twisted pairs of copper wire will suppress common mode noise, electrostatic and magnetic, by approximately 30 to 40 db, the current integrated circuit suspension designs do not permit cross-over of the integrated copper circuits or traces for noise reduction. The resulting integrated head/suspension assemblies are subjected to undesirable common mode noise.
Furthermore, conventional heads also require attachment to the suspensions and the wires for electrical contact must be bonded to the head assembly. These processes increase the size of the head/suspension assembly as well as contribute significantly to the cost.
It can be seen then that there is a need for a low noise magnetic recording head suspension fabricated as one single structure using semiconductor processes.
It can also be seen that there is a need for a low noise, low mass-recording head and suspension fabricated as one single structure using the semiconductor processes.

Integrated conductor magnetic recording head and suspension having cross-over integrated circuits for noise reduction

International Business Machines Corporation


Integrated circuit test systems include an input driver having an output terminal that is connected to a test system port and a biasing device that is connected between the test system port and a reference voltage. The biasing device comprises a Thxc3xa9venin equivalent circuit that is represented by an impedance element and a nonzero power source. The impedance element may be used to match the impedance of a device under test, which can reduce distortion in signals passed between the device under test and the test system. Furthermore, the power source may be used to provide direct current (DC) signals at the pins of a device under test, which can allow the swing height (e.g., amplitude or magnitude) of the test signals to be reduced. That is, the test signals are superimposed upon the DC voltages to allow xe2x80x9chighxe2x80x9d and xe2x80x9clowxe2x80x9d logic levels to be manifested via relatively minor swings in the test signals. By reducing the swing height of the test signals, transmission speed can be improved thereby reducing round trip signal delay.

This application claims the benefit of Korean Patent Application No. 98-36934, filed Sep. 8, 1998, the disclosure of which is hereby incorporated herein by reference.
The present invention relates generally to the field of integrated circuit testing, and, more particularly, to systems for testing integrated circuit memory modules and devices.
Improvements in both speed and functionality of central processing units (CPUs) have generally resulted in accompanying improvements in memory devices to support the operation of these improved CPUs. These memory devices may comprise a plurality of integrated circuit memory elements. That is, a single memory module may include a plurality of conventional or xe2x80x9cnormalxe2x80x9d memory elements. Unfortunately, the fabrication process may damage one or more of the conventional memory elements that comprise the memory module. Therefore, it may be desirable to test the various memory elements within a memory module to identify any elements that are inoperable.
FIG. 1 is a high-level block diagram that depicts a conventional testing system for verifying the operation of a memory module. A test unit 100 includes both the hardware and software for controlling the testing operation. The test unit 100 interfaces with a load board 120 that is used for transmitting signals output from the test unit 100. A socket printed circuit board 140 and socket 160 are used to interface the load board 120 to a memory module 180.
Broadly stated, the test unit 100 is used to test the memory module 180 as follows: The test unit 100 provides a read instruction and/or a write instruction to one or more memory elements within the memory module 180 through the load board 120, printed circuit board 140, and socket 160. The test unit 100 can then determine whether a particular memory element within the memory module 180 is operating properly by comparing data written into a memory cell with data read from the memory cell to determine if they are identical.
FIG. 2 is a schematic of a conventional test configuration using independent channel signaling that illustrates the test unit 100, load board 120, and memory module 180 in more detail. The test unit 100 includes a plurality of data input drivers 12-1, 12-3, . . . , and 12-(2n-1) that receive control signals and address data through the input terminals 10-1, 10-5, . . . , and 10-(4n-3). The test unit 100 further includes a plurality of data input drivers 12-2, 12-4, . . . , and 12-2n that receive write data through the input terminals 10-2, 10-6, . . . , and 10-(4n-2). Finally, the test unit 100 includes a plurality of comparators 14-1, 14-2, . . . , and 14-n that are used to compare read data from the memory module 180 with expected data provided through the input terminals 10-4, 10-8, . . . , and 10-4n and to generate a comparison result at the output terminals 10-3, 10-7, and 10-(4n-1).
The load board 120 includes a plurality of transmission lines 20-1, 20-3, . . . , and 20-(2n-1) that are connected to the output terminals of the data input drivers 12-1, 12-3, . . . , and 12-(2n-1). In addition, the load board 120 includes a plurality of transmission lines 20-2, 20-4, . . . , and 20-2n that are connected to the output terminals of the data input drivers 12-2, 12-4, . . . , and 12-2n and one of the input terminals of the comparators 14-1, 14-2, . . . , and 14-n as illustrated.
The memory module 180 includes a plurality of memory devices or elements 32-1, 32-2, . . . , and 32-n that include input pins 30-1, 30-3, . . . , and 30-(2n-1) and input/output pins 30-2, 30-4, . . . , and 30-2n. The input pins 30-1, 30-3, . . . , and 30-(2n-1) are connected to the transmission lines 20-1, 20-3, . . . , and 20-(2n-1) and the input/output pins 30-2, 30-4, . . . , and 30-2n are connected to the transmission lines 202, 20-4, . . . , and 20-2n. For purposes of illustration, the memory devices 32-1, 32-2, . . . , and 32-n are each depicted with a single input pin and a single input/output pin. It is nevertheless understood to those skilled in the art that the memory devices 32-1, 32-2, . . . , and 32-n typically include both a plurality of input pins and input/output pins.
A method that may be used for testing the memory module 180 is described hereafter. A typical test cycle involves the following steps: 1) input the write instruction and the write address, 2) perform a data write operation, 3) input the read instruction and read address, and 4) perform a data read operation. This cycle may be repeatedly performed until the operability of all memory devices 32-1, 32-2, . . . , and 32-n in the memory module 180 is verified. This test cycle will be discussed hereafter with reference to the independent channel test configuration of FIG. 2.
The test unit 100 receives the write instruction and write address through the input terminals 10-1, 10-5, . . . , and 10-(4n-3). The write instruction and write address are then provided to the input pins 30-1, 30-3, . . . , and 30-(2n-1) of the memory devices 32-1, 32-2, . . . , and 32-n through the data input drivers 12-1, 12-3, . . . , and 12(2n-1) and the transmission lines 20-1, 20-3, . . . , and 20-(2n-1). Next, the memory devices 32-1, 32-2, . . . , and 32-n prepare for the write operation.
The data to be written into the selected memory cell is received through the input terminals 10-2, 10-6, . . . , and 10-(4n-2) and is provided to the input/output pins 30-2, 30-4, . . . , and 30-2n of the memory devices 32-1, 32-2, . . . , and 32-n through the data input drivers 12-2, 12-4, . . . , and 12-2n and the transmission lines 20-2, 20-4, . . . , and 20-2n. The memory devices 32-1, 32-2, . . . , and 32-n then enable the data to be written into the selected memory cell.
After completing the data write operation, the test unit 100 receives the read instruction and read address through the input terminals 10-1, 10-5, . . . , and 10-(4n-3) and, simultaneously, the data that has been previously written into the memory cell corresponding to the read address is received at the input terminals 10-4, 10-8, . . . , and 10-4n. The read instruction and read address are provided to the input pins 30-1, 30-3, . . . , and 30-(2n-1) of the memory devices 32-1, 32-2, . . . , and 32-n through the data input drivers 12-1, 12-3, . . . , and 12-(2n-1) and the transmission lines 20-1, 20-3, . . . , and 20-(2n-1). Next, the memory devices 32-1, 32-2, . . . , and 32-n prepare for the read operation.
The data are then read through the input/output pins 30-2, 30-4, . . . , and 30-2n and transmission lines 20-2, 20-4, . . . , and 20-2n traversing the same path that was used to write data to the memory devices 32-1, 32-2, . . . , and 32-n. The data that are read from the memory devices 32-1, 32-2, . . . , and 32-n are compared by the comparators 14-1, 14-2, . . . , and 14-n with the expected data provided at the input terminals 10-4, 10-8, . . . , and 10-4n. The results of the comparison are provided through the output terminals 10-3, 10-7, and 10-(4n-1).
The test unit 100 uses the results of the comparison operation to determine whether the memory devices 32-1, 32-2, . . . , and 32-n are operating properly. More specifically, if a comparison result indicates that the read data and the expected data are identical, then the test unit 100 concludes that a particular memory device 32-1, 32-2, . . . , and 32-n is operating properly. On the other hand, if a comparison result indicates that the read data and expected data are not identical, then the test unit 100 identifies the particular memory device 32-1, 32-2, . . . , and 32-n as being inoperable or damaged.
Because each memory device 32-1, 32-2, . . . , and 32-n is accessed through independent signaling channels (i.e., transmission lines 20-1, 20-3, . . . , and 20-(2n-1) and transmission lines 20-2, 20-4, . . . , and 20-2n), all of the memory devices 32-1, 32-2, . . . , and 32-n contained in the memory module 180 can be tested simultaneously. Note that if the memory devices 32-1, 32-2, . . . , and 32-n that comprise the memory module 180 operate at a relatively low speed, then the testing method described in the foregoing may not be affected by the round trip delay of signals between the test unit 100 and the memory module 180. If, however, the memory devices 32-1, 32-2, . . . , and 32-n that comprise the memory module 180 operate at a relatively high speed, then the memory devices 32-1, 32-2, . . . , and 32-n may transition rapidly from a read mode to a write mode, which can cause the read and the write operations to interfere with each other unless the testing procedure accounts for the round trip delay of signals between the test unit 100 and the memory module 180.
Furthermore, if the memory devices 32-1, 32-2, . . . , and 32-n that comprise the memory module 180 operate at a relatively low speed, then the signals transferred between the memory module 180 and the test unit 100 and/or load board 120 are typically unaffected by impedance mismatches between the components. If, however, the memory devices 32-1, 32-2, . . . , and 32-n that comprise the memory module 180 operate at a relatively high speed, then impedance mismatches between the memory module 180 and the test unit 100 and/or load board 120 may cause signal distortion. Typically, the impedances of the test unit 100 and the load board 120 are predetermined or adjusted to match so as to reduce distortion in signals transferred therebetween. Nevertheless, the impedances of the test unit 100 and/or the load board 120 may be different than the impedances of the memory module 180 and/or the transmission lines (i.e., transmission lines 20-1, 20-3, . . . , and 20-(2n-1) and transmission lines 20-2, 20-4, . . . , and 20-2n), which can result in signal distortion, especially when the memory devices 32-1, 32-2, . . . , and 32-n operate at a relatively high speed.
Thus, in summary, the conventional test configuration of FIG. 2 may be useful for testing memory devices that operate at a relatively low speed. When testing memory devices that operate at a relatively high speed, however, the test configuration may be adversely affected by round trip signal delays and signal distortion due to impedance mismatches as discussed hereinabove.
FIG. 3 is a schematic of a conventional test configuration that uses common channel signaling. The test unit 100 includes a data input driver 12-1 that receives control signals and address data through an input terminal 10-1. The test unit 100 further includes a data input driver 12-2 that receives write data through an input terminal 10-2. Finally, the test unit 100 includes a comparator 14 that is used to compare read data from the memory module 180 with expected data provided through an input terminal 10-4 and to generate a comparison result at the output terminal 10-3.
The load board 120 includes a transmission line 20-1 that is connected to the output terminal of the data input driver 12-1. In addition, the load board 120 includes a transmission line 20-2 that is connected to the output terminal of the data input driver 12-2 and one of the input terminals of the comparator 14 as illustrated.
The memory module 180 includes a plurality of memory devices or elements 32-1, 32-2, . . . , and 32-n that include input pins 30-1, 30-3, . . . , and 30-(2n-1) and input/output pins 30-2, 30-4, . . . , and 30-2n. The input pins 30-1, 30-3, . . . , and 30-(2n-1) are connected to the transmission line 20-1 and the input/output pins 30-2, 30-4, . . . , and 30-2n are connected to the transmission line 20-2. For purposes of illustration, the memory devices 32-1, 32-2, . . . , and 32-n are each depicted with a single input pin and a single input/output pin. It is nevertheless understood to those skilled in the art that the memory devices 32-1, 32-2, . . . , and 32-n typically include both a plurality of input pins and input/output pins. Moreover, the input pins 30-1, 30-3, . . . , and 30-(2n-1) for all of the memory devices 32-1, 32-2, . . . , and 32-n are shown connected to a single channel (i.e., transmission line 20-1) and the input/output pins 30-2, 30-4, . . . , and 30-2n for all of the memory devices 32-1, 32-2, . . . , and 32-n are shown connected to a single channel (i.e., transmission line 20-2). Alternatively, it should be understood that the memory devices 32-1, 32-2, . . . , and 32-n could be divided into groups of n units such that all n units in a single group are connected via common channels while memory devices in separate groups remain independent. As illustrated in FIG. 3, because the input pins 30-1, 30-3, . . . , and 30-(2n-1) of the memory devices 32-1, 32-2, . . . , and 32-n are commonly connected to a single data input driver 12-1 and the input/output pins 30-2, 30-4, . . . , and 30-2n of the memory devices 32-1, 32-2, . . . , and 32-n are connected to a single data input driver 12-2, the memory devices 32-1, 32-2, . . . , and 32-n cannot be tested in parallel, but instead are tested serially.
Although the test configuration of FIG. 3 may be different than that of FIG. 2, it nevertheless may suffer from the same disadvantages. That is, the test configuration of FIG. 3 may be adversely affected by round trip signal delays and signal distortion due to impedance mismatches when testing memory devices that operate at a relatively high speed.
It is therefore an object of the present invention to provide improved test systems for testing integrated circuit memory modules and devices.
It is another object of the present invention to provide improved test systems that can be used for testing high-speed integrated circuit memory modules and devices.
It is yet another object of the present invention to provide improved test systems for testing integrated circuit memory modules and devices that can reduce signal distortion that may occur as signals are passed between a test system and a memory module or device under test.
These and other objects, advantages, and features of the present invention may be provided by integrated circuit test systems that include a first input driver having an output terminal that is connected to a first test system port and a first biasing device that is connected between the first test system port and a reference voltage. The first biasing device comprises a Thxc3xa9venin equivalent circuit that is represented by an impedance element and a non-zero power source. The impedance element may be used to match the impedance of a device under test, which can reduce distortion in signals passed between the device under test and the test system. Furthermore, the power source may be used to provide direct current (DC) signals at the pins of the device under test, which can allow the swing height (e.g., amplitude or magnitude) of the test signals to be reduced. That is, the test signals are superimposed upon the DC voltages to allow xe2x80x9chighxe2x80x9d and xe2x80x9clowxe2x80x9d logic levels to be manifested via relatively minor swings in the test signals. By reducing the swing height of the test signals, transmission speed can be improved thereby reducing round trip signal delay.
In accordance with an aspect of the invention, a second input driver has an output terminal that is connected to a second test system port and a second biasing device is connected between the second test system port and a reference voltage. The second biasing device comprising a Thxc3xa9venin equivalent circuit that is represented by an impedance element and a non-zero power source.
In accordance with another aspect of the invention, a third input driver has an output terminal that is connected to the first test system port and a fourth input driver has an output terminal that is connected to the second test system port.
In accordance with still another aspect of the present invention, first and second transmission lines are used to connect the first and third input drivers to the first test system port and third and fourth transmission lines are used to connect the second and fourth input drivers to the second test system port.
In accordance with yet another aspect of the present invention, one of the first and third input drivers generates a DC signal when the other input driver in the pair transmits a control signal, e.g., an instruction and/or address signal.
In accordance with still another aspect of the present invention, the second and fourth input drivers both generate a DC signal when data is read from the memory device through the second test system port.
In accordance with still another aspect of the present invention, one of the second and fourth input drivers generates a DC signal when the other input driver in the pair transmits write data.
The DC signals generated by the input drivers are used conjunction with the DC signals provided by the power sources to ensure that a desired DC offset voltage is maintained on the signal transmission paths.
Test systems in accordance with the present invention can also be used to test a memory module having a plurality of memory devices with each device having an input pin and an input/output pin. In accordance with an illustrative embodiment, a test system includes a first signal channel that connects the input pins of the plurality of memory devices to each other and a second signal channel that connects the input/output pins of the plurality of memory devices to each other. A first pair of input drivers is connected to the first signal channel and a second pair of input drivers is connected to the second signal channel. In addition, a first impedance element and first power source are connected in series between the first signal channel and ground and a second impedance element and second power source are connected in series between the second signal channel and ground.
In accordance with yet another illustrative embodiment of the present invention, a test system for a memory module includes a first signal channel that connects the input pins of a plurality of memory devices to each other and a second signal channel that connects the input/output pins of the plurality of memory devices to each other. First and second input drivers are connected to the first signal channel at first and second nodes respectively. Similarly, third and fourth input drivers are connected to the second signal channel at first and second nodes respectively. In addition, a first impedance element and first power source are connected in series between first node of the first signal channel and ground, a second impedance element and second power source are connected in series between the second node of the first signal channel and ground, a third impedance element and third power source are connected in series between the first node of the second signal channel and ground, and a fourth impedance element and a fourth power source are connected in series between the second node of the second signal channel and ground.
The test systems according to the present invention, which include impedance elements and power sources for maintaining a DC signal on the test signal transmission paths, can thus be used to test high-speed memory devices where signal distortion and round trip signal delay may be problematic.

Integrated circuit test systems that use direct current signals and impedance elements to improve test signal transmission speed and reduce test signal distortion


The invention relates to mechanical watch oscillators comprising an assembly consisting of a spiral and a temperature compensated balance. The spiral is embodied in a quartz substrate whose section is selected in such a way that the drifts of the spiral and of the balance associated therewith are thermally compensated. The substrate section can be embodied in the form of a section of single or double rotation.

The mechanical oscillators, also called regulators, of timepieces are composed of a flywheel, called a balance wheel, and a spiral spring, called a hairspring, which is fixed, on the one hand, to the balance wheel staff and, on the other hand, to a pallet bridge in which the balance wheel staff pivots. The balance wheel/hairspring oscillates about its equilibrium position at a frequency that must be kept as constant as possible, as it determines the operation of the timepiece. For a homogeneous and uniform hairspring, the period of oscillation of such oscillators is given by the expression:
  T  =      2        π                                            J            b                    ·                      L            s                                                E            s                    ·                      I            s                              in which:                Jb is the total moment of inertia of the balance wheel/hairspring;        Ls represents the active length of the hairspring;        Es is the elastic modulus of the hairspring; and        Is is the second moment of section of the hairspring.
A temperature variation results in a variation in the oscillation period such that, to the first order:
            Δ                                      T        T    =            1      2                  {                                    Δ                                                                                J              b                                            J            b                          +                              Δ                                                                                L              s                                            L            s                          -                              Δ                                                                                E              s                                            E            s                          -                              Δ                                                                                I              s                                            I            s                              }      i.e. an expansion effect on Jb, Ls and Is and a thermoelasticity effect on Es. With an increase in temperature, the first three terms are generally positive (expansion of the balance wheel, elongation of the hairspring and reduction in Young's modules) and bring about a loss, whereas the last term is negative (increase in the cross section of the hairspring) and brings about a gain.
In the past, several methods for compensating for the temperature drift of the frequency have been proposed in order to alleviate this problem. Mention may in particular be made of methods of compensation by thermal modification of the moment of inertia of the balance wheel (for example a bimetallic balance wheel made of steel and brass) or by the use of a special alloy (for example invar) for hairsprings having a very low thermoelastic coefficient. These methods remain complicated, difficult to implement and consequently expensive.
More recently, in its European patent application EP 02026147.5 the Applicant described a method for the thermal compensation of the spring constant of a spiral spring, consisting in thermally oxidizing a hairspring produced in a silicon substrate. In the case of hairsprings made of steel of the invar type (for example the house alloy Nivarox-Far S.A.), spiral springs made of oxidized silicon make it possible to regulate the thermal behavior of the spring itself, possibly with a slight overcompensation by a few ppm/° C. This overcompensation limitation is due to the maximum oxide thickness that can be produced in practice (currently less than 4 μm) and to the minimum tolerable width of the cross section of the silicon hairspring (greater than 40 μm). Consequently, the balance wheel must also be thermally compensated. This can be obtained, for example, using an alloy of the "glucydur" type (a copper-beryllium alloy, also called "glucinium") or else other alloys having a very low thermal expansion coefficient. This method is also complicated and, no more than the other more conventional methods, does not make it possible to correct for other isochronism defects, such as those due for example to various frictional effects in the oscillator, to the balance wheel being out of balance, to the center of mass of the hairspring being off-center, etc.

Temperature-compensated balance wheel/hairspring oscillator

CSEM Centre Suisse d'Electronique et de Microtechniques SA - Recherche et Développement


A method and system in a wireless communications network for restricting certain communication transactions to specific geographic areas in order to reduce the risk of communications fraud are presented. Initially, a list of communication transactions is stored such that the list includes communication transactions permitted to occur at each of a number of geographic locations. Thereafter, a communications transaction is initiated. In response to an initiation of the communications transaction, a geographic location of an originator of the communications transaction is determined. Next, the list of communication transactions is automatically scanned for communication transactions permitted to occur at the geographic location. If the communications transaction is not found among the list, the initiation of the communications transaction is thereafter terminated. Alternatively, if the communications transaction is found among the list, the communications transaction is thereafter permitted to continue. The geographic location can include a cell or cells maintained within the communications network.

1. Technical Field
The present invention relates, in general, to an improved wireless communications system. In particular, the present invention relates to an improved wireless communications system in which the risk of illicitly intercepted communications service is reduced.
2. Description of the Related Art
Cordless telephone systems are well-known in the prior art. A cordless telephone system generally includes a portable cordless handset and a cordless base station which is connected to a telephone company phone system by a landline. The cordless base station has an assigned landline telephone number that allows users to place and receive calls utilizing the cordless portable handset within a limited range of the cordless portable base station, such as within a home or office. However, due to the limited range present within such systems, a cordless portable handset provides the user with only relatively local radio-telephone communication.
Radio-telephone communication outside the range of a cordless telephone system also can be provided to users via cellular telephone systems. Cellular radio is a radiotelephone communications system that began to develop rapidly in the early 1980s. Basically, cellular radio is a small-scale, "cellular" version of the communication linkage provided by large radio-broadcasting systems. In a cellular telephone system, a geographical area is divided into smaller units, called cells. Each cell can have a radius of about 13 to 19 km (8 to 12 mi). In addition, each cell contains its own small radio transceiver. If necessary, each cell can be further subdivided into smaller cells. In this way, a honeycomb pattern of cells is formed such that each cell can repeatedly utilize the same range of radio frequencies without interfering with one another, so long as neighboring cells do not utilize precisely the same radio channels. Persons equipped with mobile communication devices such as small mobile cellular telephones can utilize this cellular telephone system in the same way that telephone calls are performed utilizing standard carriers.
Computerized switching is essential to the operation of cellular radio, so that when mobile-unit calls are switched from one cell to the next, the transfer in channels can take place without interruption, or at most a brief delay. The growth of electronic switching systems and the development of microprocessors have made such computerized switching possible. For each area to be covered by cellular radio, the U.S. Federal Communications Commission (FCC) licenses different types of organizations. For example, one type organization must be a telephone company, while another, a business that agrees to construct the necessary radio system. In recent years, the FCC has awarded newer frequency bands that also utilize cellular technology.
A cellular telephone system typically includes cellular subscriber units that may be mobile or portable, and cellular base stations that are connected to the public telephone company via one or more cellular switching networks. Each cellular subscriber has an assigned cellular telephone number that allows the user to place and receive calls within a widespread range of the cellular base stations, such as throughout a metropolitan area. Cellular telephone systems are thus based on a structure of associated cells. Each cell constitutes a specified geographic area that (a) is defined for a specific mobile communications system; and (b) has its own base station and a single controller interconnected with a public telephone network. Cellular telephone systems are particularly advantageous in providing cellular mobile service, a communications service that allow users to access a telephone network from a stationary or moving vehicle, via a combination of radio transmission and telephone switching. Cellular mobile services typically provide communications links to the user by segmenting a large geographic area into many smaller areas (i.e., cells). As a user passes from cell to cell, the cellular mobile service allows calls in progress to be handed over without interruption to adjacent base stations.
Users often desire to make toll calls via mobile communication devices, such as cellular telephones. In public switched telephone systems, including those that incorporate mobile cellular telephone systems, a toll is a charge for a connection to a central office or a user end instrument that is beyond a call originator exchange boundary. The amount of a toll (i.e., toll call) is usually based on various factors, such as distance, the number of exchanges utilized, duration of the call, time of day, locations of call originator and call receiver, type or class of service, and extent of utilization. Although a user may desire to make a toll call to a cellular telephone, the carrier (i.e., the company handling the cellular telephone call) may be exposed to fraud if it allows a toll call to proceed, particularly in long-distance dialing cases. Cellular signals can be easily intercepted because of the availability of cellular networks over wide geographic areas.
Several solutions have been proposed to handle the potential illicit interception of cellular telephone service and resulting fraudulent actions by unscrupulous intermediaries. The first solution is simply to permit no toll calls at all. This solution is limited because it does not allow flexibility for users or subscribers of mobile cellular telephone services. This solution is thus unrealistic and unprofitable for cellular carriers to implement. Another solution is to allow a mobile user to make local toll calls only, but not international toll calls. This solution reduces the exposure to fraud somewhat. However, the carrier and the user are still exposed to fraud derived from local phone calls. Such a method does not allow a carrier to generate revenue from legitimate mobile customers who desire to make toll calls.
Another solution is to allow a mobile cellular telephone user to make toll calls, but require some sort of an identification number, such as a PIN number, when placing a toll call. Again, exposure to the risk of fraud is reduced somewhat, but exposure remains, because the PIN number can be recorded by a fraudulent user anytime the real user of a mobile communications device places a toll call. Such a solution also requires an extra undesirable effort on the part of the user of the mobile communications device to avoid illicit interception of the PIN number.
It can be appreciated from the foregoing that a need exists for a method and system in a cellular network that allows cellular telephone users to be able to make toll calls, while reducing the risk of exposure to fraudulent cellular network interceptors. Such a method and system, if implemented successfully, would limit the ability of individuals to illicitly steal the cellular telephone service of an originating cellular telephone user. For example, when an originating cellular telephone user makes a cellular telephone call, the user may be prompted, depending on the requirements of a particular cellular telephone company, to input an account number or password. The cost of the cellular communications transaction is then credited to this account number, to which the user must later pay funds.
If, however, the cellular telephone call is intercepted illicitly at the moment the user punches the account number into the cellular telephone keypad, the account number may then be in effect "stolen," and the user or cellular telephone company forced to recoup the cost of any losses suffered as a result of this theft. Such an illicit operation is often referred to in the art of cellular telephone technology as "cloning." In this situation, the illicit interceptor (i.e., cloner) utilizes illicitly accessed mobile cellular telephone identification information in an effort to fool the cellular telephone system into the belief that the cloner is the "real" mobile cellular telephone, when in fact the cloner is not. The fraud perpetrated on the mobile cellular telephone user or cellular carrier is that the cloner pretends to be the mobile cellular telephone user placing the toll call. Either the mobile cellular telephone user or the cellular carrier will have to pay the charges related to the toll call made by the cloner.
Thus, it can be seen that a need exists for a method and system that would prevent or at the very least, lessen the chances of such an unfortunate event occurring. With respect to the foregoing need, the inventor is aware of no attempts to date which have been directed toward satisfying the foregoing identified need.

Method and system in a wireless communications network for providing toll restrictions based on the geographic location of an originator


A computer instruction is provided which replicates a bit sequence to generate a data string consisting only of a plurality of the replicated bit sequences. The computer instruction allows this to be done in a register store having a predetermined bit capacity addressable by a single address. The computer instruction is useful in the context of packed arithmetic instructions, where it is often desirable to combine each of a set of objects arithmetically or logically with a common object. A computer and a method of operating a computer using the instruction are described.

For the execution of packed arithmetic instructions, a computer provides a packed arithmetic unit which operates on two source operands, at least one of which is packed, to generate a packed result. A packed operand comprises a bit string consisting of a plurality of sub-strings, each defining a particular data value and referred to herein as "objects". Thus, an operand comprises a plurality of objects. Each operand is stored in a register store which has a predetermined bit capacity addressable by a single address and in which individual bit locations cannot be individually addressed. Thus, it is not possible to address and handle individual objects within each operand.
"Packed instructions" allow a common operation to be carried out on all of the objects within an operand without individually identifying them. A simple common operation is to load the operand into and out of memory.
Another "packed instruction" is an arithmetic instruction which performs the same arithmetic operation on pairs of objects from respective operands in parallel to provide a packed result operand comprising a plurality of result objects.
It is often desirable in this context to combine each of a set of objects arithmetically or logically with a common object: for example, to multiply each of the column values in one row of a matrix by the same value. There are numerous other applications where an operation of this nature must be carried out.
An operation of this nature cannot currently readily be carried out in a packed environment, because each object within the set cannot be individually addressed if they constitute a single operand. This operation must therefore be done using non-packed instructions requiring the loading to and from memory of individual objects and a waste of register capacity. Moreover, a long sequence of instructions is required, which take up space in the memory holding instruction sequences for the processor. It is desirable to reduce where possible the length of instruction sequences.


An image sensor has multiple light shields of conductive material, the light shields being formed with respective openings. A matrix array of unit cells are formed on a semiconductor body so that they respectively correspond to the light shields. Each unit cell includes a photosensitive region for receiving imagewise radiation through the opening of the corresponding light shield for producing photo-generated electrons, a floating diffusion region, and a transfer gate for transferring the photo-generated electrons from the photosensitive region to the floating diffusion region. An amplifying transistor is provided having a controlling terminal connected to the floating diffusion region for amplifying a potential developed in the floating diffusion region and a controlled terminal connected to the corresponding light shield. As a result, each light shield is biased at a potential that substantially varies with the potential of the floating diffusion region.

1. Field of the Invention
The present invention relates generally to image sensors, and more specifically to a CMOS-based image sensor.
2. Description of the Related Art
CMOS (complementary metal oxide semiconductor) based image sensors are characterized by low power consumption, operability on a single voltage source (5 or 3.3 volts) and amenability to integration with peripheral circuitry on a common chip, as described in a paper titled xe2x80x9cA 128xc3x97128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systemsxe2x80x9d, Sunetra K. Mendis et al., IEDM 93, pages 583 to 586.
However, one disadvantage of the current CMOS-based image sensor is that the output voltage it generates is not of sufficient value.
It is therefore an object of the present invention to provide a CMOS-based image sensor capable of producing a high voltage output.
The present invention is based on a recognition that there is a stray capacitance between a grounded conductive light shield covering portions of the image sensor other than photosensitive areas and a conductor extending parallel with the light shield. It is found that the presence of this stray capacitance is the source of the stated problem.
The problem is solved by segmenting the conventional light shield into a plurality of unit light shields respectively corresponding to unit cells of the image sensor and biasing each unit light shield at a potential which varies with the output voltage of the corresponding unit cell.
According to the present invention, there is provided an image sensor comprising a plurality of light shields of conductive material, the light shields being formed with respective openings. A matrix array of unit cells are formed on a semiconductor body so that they respectively correspond to the light shields. Each of the unit cells includes a photosensitive region for receiving light through the opening of the corresponding light shield for producing photo-generated electrons, a floating diffusion region, a transfer gate for transferring the photo-generated electrons from the photosensitive region to the floating diffusion region, and an amplifying transistor having a controlling terminal connected to the floating diffusion region for amplifying a potential developed in the floating diffusion region and a controlled terminal connected to the corresponding light shield, so that the light shield is ii biased at a potential that substantially varies with the potential of the floating diffusion region.


A valve device includes a base, and a faucet and a spray gun coupled to the base. A valve member is engaged in the base and has a chamber, and includes two valve seats disposed between the chamber and the faucet and between the chamber and the opening. A valve stem is slidably engaged in the valve member and has two plugs for engaging with the valve seats. A spring may bias one plug to engage with one valve seat and for preventing the water from flowing into the spray gun. The water is allowed to flow into the spray gun when the spray gun is actuated.

1. Field of the Invention
The present invention relates to a valve, and more particularly to a valve device for faucet and spray gun.
2. Description of the Prior Art
Typical faucets include a valve device for controlling the outward flow of cold water and hot water. The typical faucets do not provide any mechanism for controlling the water flow to the spray gun when the spray gun is secured to the faucet.
The present invention has arisen to mitigate and/or obviate the afore-described disadvantages of the conventional faucets.


A communication system includes a synchronizing signal generator that generates a synchronizing signal based on a timing of an alternating waveform in a power line, a data communicating circuit that performs the data communication, and a communication controller that controls to acquire a transmitting right utilizing a timing of the synchronizing signal and to control the communication circuit in accordance with whether or not the communication apparatus acquires the transmitting right.

1. Field of the Invention
The present invention generally relates to power line communication (PLC) systems and methods for data communications over a power distribution system, and more particularly, to a device for facilitating communications through power lines and a method of using the same.
2. Related Art
In general, when a terminal (for example, a computer terminal) performs wired data communication in a home, office or factory environment, a great deal of preparatory engineering work must be performed before a communication system including the terminal is able to begin operations. This is because the communication system needs to install connectors and cables as transmission lines to appropriate positions.
However, with respect to power line communications, the preparatory engineering work in such environments is reduced in comparison with other communication technologies, because almost all of such environments already have in place many commercial power supply lines located in virtually every nook and cranny, while using a commercial power supply, for example, alternating current 100V (50 Hz/60 Hz) in Japan or 120V in the U.S. More particularly, in the case of PLC, it will be possible to establish a data communication line by just connecting a communication apparatus plug to an outlet of the commercial power supply.
JP2000-165304A describes an example of PLC technology utilizing a power line as a data communication line.
In Japan, the frequency band from 2 MHz to 30 MHz is planned to be opened to PLC. At present, many companies are in the process of research and development of PLC technology. However, at this time, there is no PLC standard in Japan, and each company has different specifications for PLC communications relating to protocol, modulating method, and frequency band.
In view of the above, there is high possibility, during actual use, of mixing different PLC communication methods in a same environment. For example, assuming that people who live in an apartment or condominium complex use PLC apparatuses therein, they may use different communication apparatuses made by different manufacturers. In such situation, these different communication apparatuses may be simultaneously connected to a common power line.
In such situation, each communication apparatus may not demodulate signals from the other apparatuses that use different types of PLC communication methods, and may recognize these signals as noise. Because each apparatus may not recognize the existence of the others on the common power line, signals output from different communication apparatuses may collide with each other. Under these conditions, it may become almost impossible to effect a communication. That is, it may become almost impossible for these different PLC apparatuses to coexist on a common power line. In order to facilitate such coexistence, these different apparatuses would need to undergo significant changes to their circuits and controllers.
On the other hand, a plurality of the same kind of PLC apparatuses are able to communicate with each other using a common power line because the signal multiplexing is performed based on time division multiplexing.

Communication apparatus and communication method

Matsushita Electric Industrial Co., Ltd.


A liquid crystal display device is disclosed. The liquid crystal display device includes: a liquid crystal display panel configured to include color filters arranged to have different color arrangement in odd and even horizontal lines, and to display an image; an input portion configured to input data for pixels opposite to the color filters of the odd and even numbered horizontal lines; a data converter configured to compensate for the input data from the input portion using rendering filter values which are differently set according to the odd and even horizontal lines; a controller configured to re-arrange the compensated data from the data converter into a suitable format for the liquid crystal display panel; and a data driver configured to apply the re-arranged data from the controller to the liquid crystal display panel and drive the liquid crystal display panel.

1. Field of the Disclosure
The present application relates to a liquid crystal display device and a driving method thereof, and more particularly to a liquid crystal display device and a driving method that are adapted to enhance picture quality.
2. Description of the Related Art
The liquid crystal display device includes a liquid crystal panel which is configured with a thin film transistor substrate provided with a plurality of thin film transistors and a color filter substrate provided with a color filter layer. The liquid crystal panel further includes a liquid crystal layer interposed between the two substrates.
In general, almost all the liquid crystal display devices include the color filter layer, which is formed on the color filter substrate and configured with three primary colored filters such as red, green and blue filter. The liquid crystal display devices control the quantity of light transmitted through the color filter layer and display a desired color.
Recently, a display technology of red, green, blue and white (hereinafter, "RGBW") mode has been developed which further includes white besides red, green and blue, in order to enhance brightness. As such, a method of deriving four color voltages from three color data, rendering methods and so on are applied to the driving of the liquid crystal panel.
The rendering methods individually drive pixels and simultaneously drive pixels adjacent to the pixel to be driven. In other words, the rendering method disperses brightness to the adjacent pixels and displays a single dot.
Among the rendering methods, a sub-pixel rendering method is being used as a technology capable of realize a high definition display using the small number of display pixels. The sub-pixel rendering method enables a gray signal applied to a sub-pixel of a display pixel with an arbitrary color to be overlapped with other sub-pixels adjacent to the display pixel, in order to display an image.
Such a sub-pixel rendering method can reduce the number of sub-pixels within a red, green and blue stripe arrangement to 3/2. In this case, the sub-pixel rendering method can provide the same definition as that of the red, green and blue stripe arrangement according to the related art. As the number of sub-pixels decreases, the area of each sub-pixel can be expanded to 3/2 times. Therefore, the sub-pixel rendering method can allow each sub-pixel to have a high aperture ratio.
The sub-pixel rendering method is also applied to a liquid crystal display device which has a red, green, blue and white stripe arrangement instead of the red, green and blue stripe arrangement. In the liquid crystal display device with the red, green, blue and white stripe arrangement, red, green, blue and white sub-pixels or color filters are arranged in stripe shapes.
The liquid crystal display device with the red, green, blue and white stripe arrangement converts received red, green and blue data into red, green, blue and white data and applies the above-mentioned sub-pixel rendering method to the red, green, blue and white data, in order to display an image. In this case, the sub-pixel rendering method enhances the definition of the liquid crystal display device.
However, the distance between the same color sub-pixels being physically alternated in the red, green, blue and white stripe arrangement is lengthened by ¾ compared to the red, green and blue stripe arrangement of the related art. Also, the same color sub-pixels are arranged adjacently to one another in a vertical direction. As such, not only the definition deteriorates but also a line dim appears on the screen, even though the sub-pixel rendering method is applied to the liquid crystal display device with the red, green, blue and white stripe arrangement. Due to this, picture quality can deteriorate.

Converting color in liquid crystal display device having different color filter arrangements for odd and even horizontal lines


A foil stock comprising at least one AlFeSi-based layer. The foil stock according to the invention comprises an AlMg-based core layer and an AlFeSi-based cladding layer of not more than 0.05% by weight, in particular of not more than 0.03% by weight magnesium (Mg), thereby ensuring high strength and good deformation and coating properties of a carrier foil produced from said foil stock.

In the prior art, there are known foils based on AlFeSi and ones based on an aluminum alloy of the 8xxx series (DE60024806T2). To manufacture them, an AlFeSi-based foil stock (for example defined in the standard DIN EN 12482-1 or DIN EN 12482-2) is cold rolled to a desired foil thickness in several rolling steps and is then soft-annealed in order to reduce manufacturing-induced cold work hardening phenomena.
Such AlFeSi foils are used, for example, in composite foils for packaging materials, in order, as a diffusion-resistant carrier foil, to meet the requirements for a coating by means of priming, painting, or lamination (EP2492089A1), Manufacturing foil from an AlFeSi foil stock has the disadvantage that ensuring both a sufficient mechanical strength and a sufficient cold formability of the foil produced is comparatively labor-intensive. Furthermore, an AlFeSi foil stock requires a relatively high purity content of alloying elements such foil stocks are therefore usually made of primary aluminum, which has a negative impact on the manufacturing costs.


A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

In the semiconductor industry, minimization of the feature size of MOS transistors in integrated circuits is a common goal. This goal is essentially driven by the need to produce integrated circuits at ever-lower costs, while improving circuit functionality and speed. Such downscaling can be achieved by reducing the characteristic dimensions of the transistors, i.e. reducing the gate lengths, the gate oxide thickness, and the junction depths, and by increasing the channel doping levels. However, scaled-down MOS transistors generally suffer from a phenomenon referred to as the "short-channel effect". The short-channel effect has an adverse impact on the switching performance of the transistors, because such switching is inefficiently controlled by the gate electrode, which leads to an undesired decrease in the threshold voltage. Mechanically, the depletion regions around the source and the drain occupy an increasingly large fraction of the channel region, so that a lower potential on the gate is needed to achieve inversion in the channel.
Referring to the FIG. 1, a conventional scaled-down MOS transistor 100, which is fabricated within a semiconductor substrate 102, includes a source extension region 106a and a drain extension region 106b. The source extension region 106a and the drain extension region 106b have shallow junctions in order to minimize the short-channel effect that occurs in MOS transistors having sub-micron or nanometer dimensions. The MOS transistor 100 further includes a source region 108a and a drain region 108b that have deeper junctions, relative to the source extension region 106a and the drain extension region 106b, to provide lower resistance. The MOS transistor 100 also includes a gate structure 110, which is comprised of a gate dielectric 112 and a gate electrode 114. An insulative spacer 118, which is typically comprised of silicon nitride (SiN), is disposed on the sidewalls of the gate structure 110. The MOS transistor 100 further includes silicide regions 120a, 120b, and 120c to provide low-resistance electrical contact with the source/drain 106a/106b and the gate electrode 114. The MOS transistor is electrically isolated from other devices by shallow trench isolation structures 104.
A problem lies in that impurities in the source/drain extension regions 106a/106b tend to diffuse to the region immediately under the gate 110. The portions of the source/drain extension regions 106a/106b formed immediately under the gate 110 have a higher electric resistance relative to the portions of the extension regions 106a/106b located immediately under the sidewall spacers 118. For this reason, the transistor 100 has effective resistances R that are connected in series to the source and the drain. This inhibits the flow of electric current, thus decreasing operation speed.
A second problem concerns the rise of channel dopant concentration, which in turn causes a rise in threshold voltage in the field effect transistor. In order to meet miniaturization requirements in MOS transistors, the impurity concentration of the channel impurity region is necessarily raised. At the same time, contemporary semiconductor devices are designed to operate with a lower power supply voltage, such as ranging from 5V to 3.3V. For operation with such a low power supply voltage, the threshold voltage of the field effect transistor needs to be lower. For this reason, any rise in the threshold voltage of MOS transistor due to the rise in channel dopant concentration is undesirable. On the other hand, a channel doping level that is too high in scaled-down devices gives rise to superfluous leakage current and junction breakdown.
In an attempt to overcome the stated disadvantages, elevated source and drain structures have been suggested. Referring to FIG. 2, a gate structure 210 comprised of a gate dielectric 212 and a gate electrode 214 is formed on the surface of the semiconductor substrate 202. A source extension region 206a and a drain extension region 206b are then formed in the semiconductor substrate. A spacer 218, typically comprised of silicon nitride (SiN), is formed on the sidewalls of the gate structure 210. An epitaxial layer 205, typically comprised of silicon, is grown on the exposed portions of the source/drain extension regions 206a/206b, typically using selective epitaxial growth. Following the growth of the epitaxial layer 205, dopants are implanted and activated to form an elevated source 208a and an elevated drain 208b. The MOS transistor 200 further includes silicide regions 220a, 220b, and 220c to provide electrical contacts to the elevated source/drain regions 208a/208b and the gate electrode 214.
A MOS transistor having an elevated source/drain produced according to the structure of FIG. 2 is effective for reducing the resistance of the source and drain regions by increasing the thickness and the doping level by elevating the source/drain regions 208a/208b. However, it is inevitable that the dopants of the source/drain extension regions 206a/206b diffuse into the region immediately under the gate 210, which result in junction leakage current through the source/drain extension regions 206a/206b.

MOS transistor with elevated source and drain structures and method of fabrication thereof


A vacuum valve comprising a valve body with a valve opening, a valve plate which is movable between an open position in which it lies next to the valve opening and releases the valve opening and a closed position in which the valve opening is covered and a diaphragm plate which is movable between a passive position, in which it lies next to the valve opening and releases the valve opening, and an active position in which it partially covers the valve opening. The vacuum valve has a completely open state in which the valve plate is in its open position and the diaphragm plate is in its passive position, a completely closed state in which the valve plate is in its closed position and is sealed relative to the valve body, and a partially closed state in which the valve plate is in its open position and the diaphragm plate is in its active position, wherein the vacuum valve has a reduced cross section compared to the completely open state.

a) Field of the Invention
The invention is directed to a vacuum valve comprising a valve body with a valve opening, a valve plate which is movable between an open position in which it lies next to the valve opening and releases the valve opening and a closed position in which the valve opening is covered, wherein the vacuum valve has a completely open state in which the valve plate is in its open position and a completely closed state in which the valve plate is in its closed position and is sealed relative to the valve body.
b) Description of the Related Art
There are different known embodiment forms of valves in which the valve plate is laterally adjacent to the valve opening in the open state and is displaceable into a position in which the valve opening is covered for closing the valve. Valves of this type are known as slide valves.
In a conventional embodiment form of valves of the type mentioned above, the valve plate is initially displaced from its open position into a position in which the valve opening is completely covered but the valve plate is raised from the valve seats arranged at the valve body. This displacement is carried out in the plane of the valve plate. The valve plate is subsequently set against the valve seat so that sealing is achieved relative to the valve body.
Slide valves of the type mentioned above are known, for example, from U.S. Pat. No. 4,052,036, U.S. Pat. No. 4,470,576, and U.S. Pat. No. 4,660,141. After the valve plate has achieved the state in which the valve opening is completely covered when closing the valve, the valve plate is spread apart for advancing the valve plate toward the valve body and for sealing relative to the latter. The contents of these patents are hereby adopted through reference.
Aside from valves in which the valve plate is displaceable in a straight line between its open position and its position in which the valve opening is covered, there are also known valves of this type in which the valve plate is swiveled around a swiveling axis extending perpendicular to the plane of the valve plate. Valves of this type are also known as pendulum slides or pendulum valves. In one embodiment form of a valve of this kind, the valve plate is spread apart in a manner analogous to valves that are displaceable in a straight line.
Further, there are known vacuum valves of the kind mentioned above in which L-shaped movements of the valve plate are carried out when closing the valve. In this connection, a displacement of the valve plate is initially carried out again in its plane (between the open position and the position in which the valve opening is completely covered) and, after reaching the position in which the valve opening is covered, a displacement is carried out vertical thereto. A valve of this type is known from U.S. Pat. No. 6,431,518B1, for example. Apart from valves with valve plates which are displaceable in a straight line proceeding from their open position, there are other valves in which the valve plate is swiveled around a swiveling axis extending perpendicular to its plane. In addition to L-movements, grinding movements (with movement components diagonal to the plane of the valve plate, particularly shortly before closure of the valve), also referred to as J-movements, are known.
Further, there are known slide valves in which the displacement of the valve plate and sealing of the valve are carried out only by a straight-line movement (in the principal plane of the valve plate), wherein the sealing surface and the sealing ring have a three-dimensional orientation or alignment. A design of this type is described, for example, in the British Patent Application GB 2 205 926 A whose contents are hereby likewise adopted through reference.
U.S. Pat. No. 5,577,707 discloses a slide valve in which an annular seal connection piece is provided for sealing the valve plate relative to the valve body in the completely closed state of the valve. The seal connection piece is mounted in the through-channel of the valve body forming the valve opening so as to be displaceable vertical to the plane of the valve plate and is accordingly sealed relative to the valve body. In the completely closed and sealed state of the valve, the seal connection piece is advanced toward the valve plate and is likewise sealed relative to it. The contents of this patent are hereby adopted through reference.
In slide valves which are constructed as regulating valves, the valve plate can be moved into various intermediate positions between its initial position and its end position by means of the correspondingly constructed drive of the valve plate, so that the cross section of the valve opening is adjustable in order to configure the conductivity of the valve in a controllable manner. Stepping motors, for example, can be used to drive the valve plate.
In some applications, however, the ability to fully regulate the cross section of the valve opening is not required and not even desirable. In this case, in addition to the completely open state and the sealed state of the valve, there is only a predetermined partially closed state in which the valve plate can be moved into an intermediate position determined by the drive between its open position and its closed position. Valves of this kind are also known as three-position valves and the drives used in this case, particularly pneumatic drives, are known as three-position drives. A disadvantage in these three-position valves consists in that the orifice opened in the intermediate position of the valve plate is not symmetric to the axis of the valve opening so that the gas flow through the valve is asymmetric, which is undesirable in various applications, for example, in semiconductor technology.


A compound bow comprises at least one limb that extends continuously between opposed rotatable members. In some embodiments, the bow comprises a second limb that extends continuously between the opposed rotatable members. In some embodiments, the limbs are parallel to one another.

Bows have been used for thousands of years as a tool for rapidly propelling an arrow. The simplest bow designs have included a body made of a single piece of material—usually wood. The body is shaped to include flexible limbs at each end. A bow string is securely fastened between the flexible limbs. When the bow string is pulled, the force causes the limbs to bend. When the string is released, the reduced force causes the limbs to spring back to their original position, thereby propelling an arrow.
In recent years major advances in bow technology have occurred. One major advance is the development of the compound bow. A compound bow typically includes pulleys and cams that provide added mechanical advantage. As a result, a compound bow may be both easier to draw and also more powerful than prior bow technology.


The invention relates to a crane comprising                a base for attaching the crane to a harvester or similar work machine,        a main boom having two ends, one end pivoted to the base,        an articulated boom having two ends, one end pivoted to the said main boom ,        an actuator cylinder for moving the main boom relative to the base having a cylinder part,        a second actuator cylinder for moving the articulated boom relative to the main boom,        a pressure cylinder in connection with one actuator cylinder, arranged to follow this actuator cylinder in order to produce pressure for the second actuator cylinder,

In known harvesters, two crane types, with a different main principle, are generally used, which are a path-of-motion crane and a sliding-boom crane. In harvesters, path-of-motion cranes are the most generally used and are manufactured in several different implementations by several different manufacturers. The basic idea of a path-of-motion crane is to implement an essentially horizontal, approximately linear movement of the outer end of the crane's boom, and simultaneously the load being carried by it, by guiding a single operating device, for example a hydraulic cylinder. This property is regarded as being advantageous and desirable in harvester machines, the task of the boom of which is mainly to use the boom to lift trees from around the machine for processing in the harvester head.
U.S. Pat. No. 7,523,834 B2, which discloses one form of implementation for a path-of-motion crane, is known from the prior art. The path-of-motion crane consists of a base, to which is pivoted a main boom, an articulated boom being pivoted in turn to the main boom. Between the base and the main boom is a lifting cylinder for lifting the main boom and in connection with the main boom is an actuator cylinder for operating the articulated boom. The folding movement of the articulated boom is created with the aid of the actuator cylinder and an arm mechanism connected to it. Drawbacks with the solution are the additional weight brought by the arm mechanism, as well as the complexity of the design of the arm mechanism. In addition, the complicated arm mechanism, located far from the lifting boom, can obscure visibility from the operator.
According to a second solution according to the prior art, the lifting cylinder and the actuator cylinder are synchronized with the aid of a pressure cylinder, which replaces the arm mechanism. The piston rods of the pressure cylinder and the actuator cylinder are permanently connected to each other, so that, when the actuator cylinder moves, the pressure cylinder follows the movement of the actuator cylinder, producing pressure and volume flow for the lifting cylinder.
The pressure cylinder and the actuator cylinder are pivoted in parallel between the main boom and the articulated boom. The feed pressure is directed only to the actuator cylinder, which creates an uneven loading in the attachment of the actuator cylinder and the pressure cylinder. This uneven loading tends to twist the booms and the pivots, creating asymmetrical stresses in the structure of the path-of-motion crane. In order to ensure the working life of the structures, the booms and pivots must be reinforced and made sturdier than usual. In addition, the strokes of the parallel cylinders must be made very precisely the same length, otherwise the difference in the length of stroke will also create serious additional stresses in the structures.

Abstract: wherein the pressure cylinder is arranged to form an essentially coaxial multi-chamber cylinder with the actuator cylinder to be followed.