A non-volatile semiconductor memory device includes: a non-volatile memory area including gate electrodes, each including stack of a floating gate, an inter-electrode insulating film and a control gate, and having first insulating side walls formed on side walls of the gate electrode; a peripheral circuit area including single-layer gate electrodes made of the same layer as the control gate; and a first border area including: a first isolation region formed in the semiconductor substrate for isolating the non-volatile memory area and peripheral circuit area; a first conductive pattern including a portion made of the same layer as the control gate and formed above the isolation region; and a first redundant insulating side wall made of the same layer as the first insulating side wall and formed on the side wall of the first conductive pattern on the side of the non-volatile memory area.

A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having a non-volatile memory of a stacked gate electrode structure formed on a gate insulating film (a tunneling insulating film) on the surface of a semiconductor substrate and to its manufacture method. The stacked gate electrode structure is constituted of a floating gate electrode (typically a polysilicon layer), an inter-electrode insulating film (typically an ONO stacked insulating film of an oxide film/a nitride film/an oxide film) and a control gate (typically a polysilicon layer).
B) Description of the Related Art
Many non-volatile semiconductor memories such as flash memories are used which utilize two-layer polysilicon layers. A flash memory is formed by forming a tunneling oxide film on a silicon substrate, forming a floating gate of a first polysilicon layer on the tunneling oxide film, and forming a control gate of a second polysilicon layer with an inter-electrode insulating film being interposed therebetween. An ONO film of a lamination of an oxide film/a nitride film/an oxide film is used as the inter-electrode insulating film. By applying a voltage between the control gate and substrate, it is possible to inject (write) charges from the substrate to the floating gate and to drain (erase) charges in the floating gate to the substrate.
The floating gate is formed independently in each memory cell. A control gate is used in common by a plurality of memory cells. For electric insulation between the control gate and floating gate, the ONO film covers the upper surface and side wall of the floating gate covered with the control gate.
In an integrated peripheral circuit area, the first polysilicon layer is removed and a single-layer gate electrode is formed by the second polysilicon layer. In a flash memory, unique processes such as side wall oxidation are executed after the laminated gate electrodes are formed. If these unique processes are executed after the gate electrodes of transistors in the peripheral circuit area are patterned, undesired issues occur such as generation of bird's beaks due to side wall oxidation so that the performance of transistors is degraded. To avoid this, during a process of forming laminated gate electrodes of flash memories, the second polysilicon layer is not patterned but left.
A flash memory can function as a MOS transistor by connecting a wiring to the floating gate of a flash memory. A transistor can be formed by using flash memory manufacture processes. This transistor is called first polysilicon transistor.
In order to form an electrically insulated floating gate of a flash memory, first, first polysilicon layers covering the active regions are formed in a parallel stripe shape and covered with an ONO film. After the ONO film is patterned, a second polysilicon layer is deposited on the whole substrate surface. By disposing a control gate mask pattern crossing parallel stripes of the first polysilicon layers, the second polysilicon layers, ONO films and first polysilicon layers are etched to form laminated electrodes.
Most of manufacture processes are used in common in the flash memory area and first polysilicon transistor area, separately from the peripheral circuit area using single-layer gate electrodes. Although the second polysilicon layer is formed secondarily in a first polysilicon transistor area, this layer is not necessary in terms of electric sense. The first and second polysilicon layers may be patterned in the same shape. The first polysilicon layer is left in the first polysilicon transistor area and removed in its peripheral area. The peripheral edge of the first polysilicon layer extends outside the first polysilicon transistor area. The ONO film is formed on the upper surface and peripheral side wall of the first polysilicon layer.
The second polysilicon layer is formed thereafter. By masking out the peripheral circuit area, the second polysilicon layer, ONO film and first polysilicon layer in the flash memory area and first polysilicon transistor area are etched to form laminated gate electrodes. It is difficult to completely remove the ONO film on the peripheral side wall of the first polysilicon layer.
After the side walls of the laminated gate electrodes are thermally oxidized, a silicon nitride film is deposited on the whole substrate surface, and side wall spacers are formed on the side walls of the laminated gate electrodes by reactive ion etching (RIE). Side walls are also formed on the peripheral side walls of the second polysilicon layer covering the peripheral circuit area. Thereafter, the second polysilicon layer in the peripheral circuit area is etched. It is not easy to completely remove the peripheral side wall of the second polysilicon layer.
The second polysilicon layer is patterned by different processes for the laminated gate electrode area (flash memory area+first polysilicon transistor area) and for the peripheral circuit area. As described above, residues are likely to be formed in the border area between the laminated gate electrode area and single-layer gate electrode layer. Residues are easy to be peeled off, forming dusts.
Description will be made by referring to the accompanying drawings. FIGS. 10A and 10B are a partial plan view of a flash memory area adjacent to a peripheral circuit area and a partial plan view of a first polysilicon transistor area adjacent to the peripheral circuit area. FIGS. 11A1 to 11A4 and FIGS. 11B1 to 11B4 are cross sectional views showing the structures of the flash memory area and first polysilicon transistor area during manufacture processes.
As shown in FIGS. 10A and 10B, in the flash memory area and first polysilicon transistor area, a plurality of active regions AR long in vertical direction are defined in parallel and surrounded by an isolation region ISO. In the flash memory area, a plurality of first polysilicon layers p1s are patterned in stripe shape, being mutually separated and covering each active region AR. In the first polysilicon transistor area, the first polysilicon layer p1s is patterned in a single plain shape covering the whole area as shown by a broken line p1p. A laminated insulating layer ONO of an oxide film/a nitride film/an oxide film is formed covering the first polysilicon layer p1 (p1s and p1p are collectively represented by p1). The laminated insulating layer ONO has a large height on the side wall of the first polysilicon layer p1.
A second polysilicon layer p2p is formed above the whole substrate surface, covering the first polysilicon layer p1 and upper laminated insulating layer ONO. In the area inner than a border line DSG, the second polysilicon layer p2p, and the underlying laminated insulating layer ONO and first polysilicon layer p1 are etched in a shape of the control gate electrode CG and gate electrode G by using the same mask. In the area outer than the border line DSG, the whole polysilicon layer is left. Since the laminated insulating layer ONO has a large height at the peripheral side wall of the first polysilicon layer, etching residues are formed.
FIG. 11A1 is a cross sectional view along a direction of the active region AR in the flash memory area shown in FIG. 10A. FIG. 11B1 is a cross sectional view along a direction of the laminated gate electrode G in the first polysilicon transistor area shown in FIG. 10B. Although the flat second polysilicon layer p2, laminated insulating layer ONO and first polysilicon layer p1 are etched, the laminated insulating layer ONO on the peripheral side wall of the first polysilicon layer p1 is left, forming an ONO fence OF. The ONO fence OF between the control gate electrodes CG is hard to be peeled off because the distance between the control gate electrodes CG is short as shown in FIG. 10A. In the lower area of FIG. 10A, an elongated U-character shaped ONO fence OF is formed and is easy to be peeled off. The ONO fence at the peripheral side wall of the first polysilicon transistor area has no support as shown in FIG. 10B and is extremely long so that it is very easy to be peeled off.
FIGS. 11A2 and 11B2 are cross sectional views along the direction of the laminated gate electrodes CG and G in the flash memory area and first polysilicon transistor area. The side wall of the laminated gate electrode (including a region of only the second polysilicon layer p2 in the flash memory area) is oxidized, and after ion implantation, the side wall of the laminated gate electrode is oxidized again. The oxide film ox is shown in FIGS. 11A2 and 11B2, but will be omitted for simplicity in other figures. Thereafter, a silicon nitride layer is deposited and anisotropic etching is performed to form a side wall SW1 of silicon nitride on the side wall of the laminated gate electrode. A side wall SW1 is also formed on the side wall of the second polysilicon layer in the peripheral circuit area. Side walls SW3 are formed on the side walls of the ONO fence OF. Even in this state, it cannot be said that the strength of the ONO fence is sufficient. After the laminated gate electrode structure is formed in the laminated gate area, single-layer gate electrodes are formed in the peripheral circuit area.
With reference to FIGS. 10A and 10B, the area inner than a border line DP2 is covered with a resist mask, and the second polysilicon layer p2 in the peripheral circuit area outer than the border line DP2 is patterned to form gate electrodes of the peripheral circuit. An unnecessary second polysilicon layer p2 is etched and removed.
As shown in FIGS. 11A3 and 11B3, the side wall SW1 of silicon nitride formed on the peripheral side wall of the second polysilicon layer p2 in the peripheral circuit area loses the support of the second polysilicon layer, forming a silicon nitride pillar SNP in a wall shape (a pillar shape in cross section).
By using a resist mask, contact holes are formed thorough the second polysilicon layer and laminated insulating layer ONO of the first polysilicon transistor to expose the first polysilicon layer. In the peripheral circuit area, impurity ion implantation is performed on both side of the gate electrode, a silicon oxide layer is deposited, and RIE is performed to form side walls of silicon oxide.
As shown in FIGS. 11A4 and 11B4, also in the border area between the flash memory area and first polysilicon transistor area, oxide film side walls SW2 are formed on the already formed nitride film side wall SW1 and side walls of the SiN pillar SNP. Side walls SW2 are formed also on the side walls of the ONO fence OF. Even if the side walls SW2 are formed, the ONO fence OF and SiN pillar SNP are easy to be peeled off, forming dusts and lowering a yield.
Japanese Patent Laid-open Publication No. HEI-10-163456 proposes that while a first polysilicon film is patterned, a peripheral circuit area is covered with the first polysilicon layer, and after an ONO film is formed, the ONO film and first polysilicon film are etched to leave the first polysilicon film in the peripheral area of the peripheral circuit area. The ONO film on the side wall of the first polysilicon film is left together with the first polysilicon film to prevent generation of ONO fence of thin fence shape.
Japanese Patent Laid-open Publication No. 2000-286350 proposes that the end portion of a first polysilicon film is covered with a dummy pattern second polysilicon film to prevent an ONO film on the side wall of the first polysilicon film from being exposed by etching and dusts from being generated.
By covering the end portion of the striped first polysilicon film above the active region in the memory area, with the dummy pattern second polysilicon film, generation of a long ONO fence without support can be prevented, to prevent peeling-off.

Semiconductor device with integrated flash memory and peripheral circuit and its manufacture method


There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-154983, filed May 25, 2000, the entire contents of which are incorporated herein by reference.
This invention relates to a boosted voltage generating circuit for boosting power supply voltage and a semiconductor memory device having the same and more particularly to a semiconductor memory device having memory cells and a boosted voltage generating circuit for generating high voltage used at the data erasing or programming time of the memory cell.
A flash memory is provided as one type of a semiconductor memory device. FIG. 1 shows the cross sectional construction of one memory cell element of the flash memory. In FIG. 1, an N-type well region (N-well) 72 is formed in a P-type semiconductor substrate (P-substrate) 71. Further, a P-type well region (P-well) 73 is formed in the N-type well region 72. In the P-type well region 73, source and drain regions 74, 75 of a memory cell which are formed of n+-type regions are separately formed. A floating gate electrode 76 is formed above the channel region between the source and drain regions 74 and 75 with an insulating film disposed therebetween and a control gate electrode 77 is formed above the floating gate electrode 76 with an insulating film disposed therebetween.
Further, a contact region 78 formed of a p+-type region is formed on the P-substrate 71, a contact region 79 formed of an n+-type region is formed on the N-type well region 72 and a contact region 80 formed of a p+-type region is formed on the P-type well region 73.
At the operating time, gate voltage Vg, drain voltage Vd and source voltage Vs are respectively applied to the control gate electrode 77, drain region 75 and source region 74. Further, the same voltage as the source voltage Vs is applied to the contact regions 79 and 80 and a ground voltage of 0V is applied to the contact region 78.
The above memory cell stores data of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d level according to the amount of electrons accumulated in the floating gate electrode 76. The threshold voltage as viewed from the control gate electrode 77 is changed according to the level of the stored data.
A memory cell array is constructed by use of a plurality of memory cells which have the same construction as the above memory cell. FIG. 2 shows an example of a circuit of the memory cell array of a NOR type flash memory. A plurality of memory cells MC are arranged in a matrix form and the control gate electrodes of the memory cells MC arranged on the same row are commonly connected to a corresponding one of a plurality of word lines WL0 to WLn. Further, the drains of the memory cells MC arranged on the same column are commonly connected to a corresponding one of a plurality of bit lines BL0 to BLm. Generally, the memory cells are divided into a plurality of blocks and the sources of the memory cells MC in the same block are commonly connected to a corresponding one of a plurality of source lines SLi which is provided for the block.
FIG. 3 shows the relation between the gate voltage (Vg) applied to the control gate electrode and a drain current flowing in the memory cell at the operating time. In this example, the state in which the amount of electrons accumulated in the floating gate electrode is relatively large, that is, the state in which the threshold voltage Vt of the memory cell is high is defined as xe2x80x9c0xe2x80x9d data (the memory cell storing xe2x80x9c0xe2x80x9d data is referred to as a xe2x80x9c0xe2x80x9d cell) and the state in which the amount of accumulated electrons is relatively small, that is, the state in which the threshold voltage Vt of the memory cell is low is defined as xe2x80x9c1xe2x80x9d data (the memory cell storing xe2x80x9c1xe2x80x9d data is referred to as a xe2x80x9c1xe2x80x9d cell).
One example of the voltage bias condition at the data readout time, program time and erase time is shown in the following table 1.
That is, the table 1 shows one example of values of the voltages Vg, Vd, Vs supplied to the memory cell. At the data readout time, Vg, Vd, Vs are respectively set at 5V, 1V, 0V. At the data program time, Vg, Vs are respectively set at 9V, 0V and Vd is set at 5V for the memory cell into which data is programmed and at 0V for the other memory cells (in which original xe2x80x9c1xe2x80x9d data is kept). Further, at the data erase time, Vg, Vs are respectively set at xe2x88x927V, 10V and Vd is set in the electrically floating state.
Readout data is determined according to whether a cell current flows or not when voltage Vread (in this example, 5V) is applied to the control gate electrode while preset voltage (in this example, 1V) is being applied to the drain. The above determination is made by comparing the cell current with a reference current (Iref) flowing in a reference cell by use of a sense amplifier (not shown).
The erase operation is simultaneously effected for a plurality of memory cells which commonly have the P-well 73 (shown in FIG. 1). At the erase time, all of the memory cells subjected to the erase process are set into xe2x80x9c1xe2x80x9d cells by causing electrons to flow from the floating gate electrodes 76 thereof into the P-type well region 73 according to the Fowler-Nordheim (Fxe2x80xa2N) tunneling phenomenon.
The program operation is effected for each memory cell. The bit line connected to the memory cell in which xe2x80x9c0xe2x80x9d data is programmed is biased to 5V so as to inject electrons of high energy generated by the channel hot electron phenomenon into the floating gate electrode 76 of the memory cell. The bit line connected to the xe2x80x9c1xe2x80x9d cells in which original xe2x80x9c1xe2x80x9d data is maintained is set at 0V. As a result, no electrons are injected into the floating gate electrode 76 and the threshold voltage Vt is kept unchanged in the non-programmed memory cell.
Further, in the flash memory, the program verify operation and erase verify operation are effected at the program time and erase time to confirm the extent to which data is programmed and erased. In the program verify operation, the xe2x80x9c0xe2x80x9d readout operation is effected by setting the voltage of the control gate electrode at high voltage Vpv (for example, 7V) in comparison with the voltage Vread (in this example, 5V) set at the readout time. Then, the program operations and program verify operations are repeatedly and alternately effected and the program operation is terminated when data items of the memory cells to be programmed are all set to xe2x80x9c0xe2x80x9d.
At the erase time, the xe2x80x9c1xe2x80x9d readout operation is effected by setting the voltage of the control gate electrode 77 at low voltage Vev (for example, 3.5V) in comparison with the voltage Vread set at the readout time. Then, the erase operations and erase verify operations are repeatedly and alternately effected and the erase operation is terminated when data items of the memory cells subjected to the erase process are all set to xe2x80x9c1xe2x80x9d. As a result, a sufficiently large cell current Icell can be attained.
Thus, the voltage applied to the control gate electrode of the memory cell is set to various values such as 9V, 7V, 5V, 3.5v according to the various operation modes. Among the above voltages, 9V, 7V, 5V are higher than the power supply voltage supplied from the exterior.
Conventionally, in order to generate various voltages such as 9V, 7V, 5V which are higher than the power supply voltage supplied from the exterior, a required number of booster circuits for boosting the power supply voltage are provided and one of the outputs of the plurality of booster circuits is adequately selected by use of a switch and the selected output is applied to the control gate electrode of the memory cell.
However, since the booster circuit necessitates elements such as capacitors which occupy a large area on the chip, there occurs a problem that the chip area becomes large if a plurality of booster circuits are provided. Further, since the consumption current in the booster circuit is relatively large, a problem that the consumption current in the whole portion of the chip becomes large occurs.
As described above, since a plurality of booster circuits are provided in the conventional semiconductor memory device which requires various voltages higher than the power supply voltage supplied from the exterior, problems that the chip area becomes large at the time of integrating the device and the consumption current becomes large occur.
Accordingly, an object of this invention is to provide a boosted voltage generating circuit capable of generating various voltages higher than the power supply voltage supplied from the exterior without making the chip area larger at the time of integration and increasing the consumption current.
Further, another object of this invention is to provide a semiconductor memory device capable of generating various voltages higher than the power supply voltage supplied from the exterior without making the chip area larger at the time of integration and increasing the consumption current.
According to this invention, there is provided a boosted voltage generating circuit comprising a first voltage output circuit for receiving first voltage and outputting second voltage obtained by boosting the first voltage; a second voltage output circuit coupled with the first voltage output circuit, for generating third voltage whose voltage value is smaller than the value of the second voltage and which is variably set to at least two values based on the second voltage; and an equalizer circuit coupled with the first and second voltage output circuits, for short-circuiting an output node of the second voltage and an output node of the third voltage in response to a first control signal.
Further, according to this invention, there is provided a semiconductor memory device comprising a memory cell array having a plurality of data-erasable memory cells having gate electrodes, for storing data; a plurality of word lines coupled with the gate electrodes of the plurality of memory cells; a first voltage output circuit for receiving first voltage and outputting second voltage obtained by boosting the first voltage; a second voltage output circuit coupled with the first voltage output circuit, for generating third voltage whose voltage value is smaller than the value of the second voltage and which is variably set to at least two values based on the second voltage; a equalizer circuit coupled with the first and second voltage output circuits, for short-circuiting an output node of the second voltage and an output node of the third voltage in response to a first control signal; and a row decoder circuit coupled with the second voltage output circuit, for setting potentials of the plurality of word lines based on the third voltage.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
FIG. 1 is a view showing the cross sectional structure of one memory cell in a flash memory;
FIG. 2 is a diagram showing an example of the circuit of a memory cell array of a NOR type flash memory;
FIG. 3 is a characteristic diagram showing the relation between gate voltage applied to the control gate electrode of a memory cell and a drain current of the memory cell;
FIG. 4 is a block diagram showing a general boosted voltage generating circuit;
FIG. 5 is a timing chart showing one example of the operation of the circuit shown in FIG. 4;
FIG. 6 is a block diagram showing a boosted voltage generating circuit according to a first embodiment of this invention;
FIG. 7 is a timing chart for illustrating one example of the operation of the circuit shown in FIG. 6;
FIG. 8 is a circuit diagram showing one example of the concrete construction of a booster circuit shown in FIG. 6;
FIG. 9 is a circuit diagram showing one example of the concrete construction of a regulator circuit shown in FIG. 6;
FIG. 10 is a circuit diagram showing one example of the concrete construction of a comparator shown in FIG. 9;
FIG. 11 is a circuit diagram showing one example of the concrete construction of a equalizer circuit shown in FIG. 6;
FIG. 12 is a timing chart for illustrating one example of the operation which is different from the operation shown in FIG. 7;
FIG. 13 is a circuit diagram showing the concrete construction of the regulator circuit shown in FIG. 6 according to a modification of the first embodiment of this invention together with another circuit including a control signal generating circuit;
FIG. 14 is a timing chart for illustrating one example of the operation of the circuit shown in FIG. 13;
FIG. 15 is a block diagram showing a boosted voltage generating circuit according to a second embodiment of this invention;
FIG. 16 is a block diagram showing the whole construction of a memory formed when this invention is applied to a flash memory;
FIG. 17 is a waveform diagram showing the relation between the word line voltage and a equalizing control signal EQLE in the memory shown in FIG. 16;
FIG. 18 is a diagram showing the state of distribution of the threshold voltage of the memory cell after data erasing;
FIG. 19 is a cross sectional view showing the structure of part of the flash memory shown in FIG. 16; and
FIG. 20 is a timing chart at the time of erase operation of the flash memory shown in FIG. 16.

Boosted voltage generating circuit and semiconductor memory device having the same


A micro-endoscope and method of making the same includes a mounting housing, a camera module received within the mounting housing, and an encapsulation material interposed between the camera module and the mounting housing for fixedly mounting the camera module within the mounting housing and/or inhibiting the passage of light between the camera module and the mounting housing. The micro-endoscope further includes a light guide having the mounting housing received therein.

The present disclosure generally relates to medical devices, and more particularly relates to a micro-endoscope and a method of making the same. Micro-endoscopes are a type of endoscope having a very small cross-sectional dimension. This can present unique manufacturing challenges for the micro-endoscope. By way of example, a micro-endoscope can have an outside diameter that is less than about 4.0 mm. This small size inhibits easy manufacture of the micro-endoscope and makes it difficult to position an image capturing device, such as a camera, near the distal end of the micro-endoscope.
In one known micro-endoscope, a camera module is painted with a black paint and installed within an optical light guide near the distal end of the micro-endoscope. In particular, lateral sides of the camera module are painted with a thin coat of black paint and the camera module is fit via an interference fit within the light guide. Then, both the camera module and the light guide are received with in a steel outer sheath.
There are a number of potential drawbacks with this arrangement. For example, the dimensions of the camera module alone and/or the camera module with the black paint thereon can be too inconsistent resulting in problems when inserting the camera in the light guide tube. Also, the attachment of a ribbon cable to the back of the camera module can be susceptible to failure due to the connection being maintained by only relatively weak solder connections. Additionally, the micro-endoscope can suffer from decreased optical output due to stray light passing by the camera module. Further, the black paint can sometimes interfere with the optics of the camera module and it is possible for parasitic paint particles to develop due to local detachment of the black paint.

Micro-endoscope and method of making same


Compounds, pharmaceutical compositions, and methods for reversing fosfomycin resistance are disclosed. Embodiments of the disclosed compounds inhibit fosfomycin-inhibiting enzymes. Some embodiments of the compounds are FosA inhibitors. The disclosed pharmaceutical compositions include (i) fosfomycin or a pharmaceutically acceptable salt thereof and (ii) a compound, or a pharmaceutically acceptable salt thereof, which inhibits a fosfomycin-inhibiting enzyme. A method of inhibiting growth of a fosfomycin-resistant bacterium includes contacting the bacterium with (i) fosfomycin or a pharmaceutically acceptable salt thereof and (ii) an effective amount of a disclosed compound or a pharmaceutically acceptable salt thereof.

Fosfomycin (also known as phosphomycin or phosphonomycin) is a broad-spectrum antibiotic produced by some Streptomyces species (e.g., S. fradiae, S. lividans) or by synthetic means. Fosfomycin covalently binds to the active site of UDP-N-acetylglucosamine enolpyruvyl transferase (MurA) of both Gram-negative and Gram-positive bacteria, and inhibits synthesis of the bacterial peptidoglycan precursor UDP N-acetylmuramic acid.

Fosfomycin, which was discovered over four decades ago, has drawn renewed interest as an agent active against multidrug-resistant (MDR) and extensively drug-resistant (XDR) pathogens. In a review of 17 studies that evaluated the antimicrobial activity and clinical effectiveness of fosfomycin for infections caused by MDR Enterobacteriaceae, including ESBL producing organisms, 11 studies reported that at least 90% of the isolates were susceptible to fosfomycin. There is also a growing interest in potential use of fosfomycin for the treatment of infections caused by carbapenem-resistant Enterobacteriaceae, such as KPC-producing Klebsiella pneumoniae. In the U.S., fosfomycin tromethamine is approved as a single-dose, orally administered treatment for cystitis. In several European and Asian countries, an intravenous fosfomycin disodium formulation is available, and is used to treat bacteremia, pneumonia, urinary tract infection, osteomyelitis and central nervous system infections, usually in combination with another active agent. A clinical trial evaluating the safety and efficacy of intravenous FOM for the treatment of complicated urinary tract infection and acute pyelonephritis has been completed in the U.S. (NCT02753946; clinicaltrials.gov), with likely FDA approval in early 2018. However, with increased use of fosfomycin, there is increased risk of fosfomycin resistance. Thus, there is a need for compounds and methods to reverse fosfomycin resistance.

University of Pittsburgh—of the Commonwealth System of Higher Education


The invention provided relates to the use of polyvinylpyrrolidone-iodine complexes in combination with gelling agents to produce strong disinfectants which not only physically stabilize biohazardous and infectious wastes but also kill pathogens contained in the wastes. The gelling agents include polyacyrlates that are superabsorbents.

Wastes, particularly infectious human wastes, present a vast array of health problems for humans. For example, wastes may contain viral, bacterial, and fungal contaminants that may be spread to human and animal populations through such pests as mosquitoes and flies. One area of concern to humans is the spread of infectious diseases when such diseases are generated in medical environments such as hospitals and clinics. Blood borne pathogens such as hepatitis B and HIV viruses may be found in blood, urine, and other bodily fluids found in medical environments. Theses fluids, although ultimately disposed of, present dangers not only to those who may come into direct contact with the wastes during generation of the waste, such as hospital personnel and patients, but also workers involved with the disposal of the waste.
Various methods have been devised to treat medical wastes including the use of disinfectants and antimicrobial agents. However, even with the use of these agents, prior to and even after treatment, workers may still be exposed when wastes spill, leak or aerosolize from their containers. Accordingly, in order to prevent such mishaps workers have developed methods to contain the wastes by using solidifying and gelling agents.
One problem encountered by workers who handle contaminated liquid wastes is that these wastes are generally treated and disposed of using disinfectants. For example, phenol has been used in combination with gelling agents. Specifically ortho-benzyl-para-chlorophenol is used in combination with a gelling agent such as starch grafted polyacrylate. This composition is poured into canisters containing liquid wastes and the liquid turns into a highly viscous gelatin-like substance. Of course, many of these agents pose general questions and concerns regarding their toxicity and potential of environmental harm.
Iodine has been used as a biocide for many years. Iodine has several properties that make it difficult to use alone as a biocide. For example, iodine is insoluble in water. Also, when placed in volatile solutions such as in alcohols, the concentration of the iodine varies due to evaporation of the alcohol. High concentrations of iodine can lead to severe irritation of the skin.
In an effort to overcome these problems, workers developed an anti-microbial composition comprising polyvinyl pyrrolidone polymer, in combination with iodine ("PVP-I). Polyvinyl pyrrolidone and iodine, when combined in an aqueous solution, form a complex. The major complex formed is a triiodide. Some of the iodine reacts with water and is reduced to iodide. Some of the iodine also becomes covalently linked to the carbon atoms of the polyvinyl pyrrilidone. It is generally accepted that the antimicrobial activity of PVP-I arises from the release of elemental iodine (free iodine) in solution. In solution, the triiodide species is in equilibrium with iodine and Iodide. Accordingly, pH, concentration, and temperature play an important role in antimicrobial properties of any PVP-I solution.
PVP-I solutions have been used in the medical industry as a disinfectant and is provided in topical cleaners. It is also used as a scrub and with swabs. Crosspovidone-iodine has also been impregnated onto cellulose filters.
One noted drawback to the use of PVP-I is that it is known to be unstable at low pH. Heretofore, attempts to combine gelling agents with disinfecting agents have not produced a superior product having good gelling properties while maintaining an effective disinfectant qualities.
Accordingly, it is an object of the present invention to not only provide a composition that disinfects wastes which contain a high organic (e.g., proteins) load but one that also provides adequate gelling or solidifying properties.


An elevator handtruck having four wheels for allowing loads to be moved like an elevator and raised and lowered out from the raised rear edges of a truck such as a pickup truck, moving van, and the like. Safety straps can attach the handtruck to flanges mounted on the wheel wells within a flat bed of the truck vehicle. A motorized carriage having a set of wheels can be slidably mounted on shafts on the rear of a two wheeled handtruck. The carriage wheels can be folded downward when not in use. During use, the carriage wheels sit on the edge of the truck bed such as the tailgate. A user holding a hand control can press buttons causing the carriage to slide up and down causing the entire handtruck to raise upward to the flat bed or downward to the ground. Power can be supplied by attaching jumper cable clip ends connected to the carriage motor on the handtruck to the terminals on the standard vehicle battery.

The common two-wheel hand truck is used extensively to handle heavy, rigid, box-like loads, especially on a one man job. The body of such a truck consists of a pair of upright rails which are spaced apart by cross bars which are tipped to hold a load at their front faces. A lip stands out from the bottom edge of the front faces of the rails to reach underneath a load to pick it up and to place it upon the rails when the truck is tipped. Two spaced apart wheels are mounted upon a shaft at the back side of the rails and at the bottom of the truck so that when the truck is tilted, it will be upon these wheels. Finally, a handle is provided at the top and at the back side of each rail to enable an operator to hold the truck. In picking up a load, the operator pushes the truck against the side of the box-like load and pushes the lip underneath it. He then tips the truck and the load rearwardly to place the load upon the truck. So positioned, an operator can balance the load over the wheels and move the loaded truck to its destination. Such hand trucks are useful for moving loads across smooth level surfaces but do not help the operator to lift or lower a load from the bed of a pickup truck. Because of this problem, a job such as moving a stove or refrigerator necessitates the use of two or more people to lift or lower the load onto a typical flat bed truck. This need also arises for package handlers such as U.P.S. drivers who have to handle extra heavy boxes from time to time and cannot single-handedly manage to lift or lower a box-like package from the ground to the truck bed. An attempt to solve this problem is shown in U.S. Pat. No. 3,896,904 by Bruce Walker. However, there is a serious problem with Walker's design. Walker describes a two wheeled hand truck in which a pair of legs is cranked down, in a telescoping fashion, from hollow openings formed by tubular vertical members at either side of the back of the hand truck. The proposed mechanism does indeed raise a load from ground level to the height of a truck bed. However, once the load is lifted the user must attempt to lift and lower the hand truck and its contents onto the truck bed. Lowering the legs while the Walker hand truck is fully loaded could also prove problematical. The legs must be extended while the user holds onto the handles of the hand truck, creating a rather precarious situation. Needless to say, this product never made it to the marketplace.
Other patent attempts have been made but still fail to solve the above problems. See for example, U.S. Pat. Nos. 2,493,824 to Noros; 2,714,462 to Butler, 2,904,201 to Rhodes; 3,052,323 to Hopfeld; 3,199,692 to Lebre; 3,873,118 to Takagi; 4,049,083 to Garvey; 4,728,245 to Shelton; 4,737,065 to Ju; 5,195,762 to Pressly; 5,290,051 to Olson and 5,419,672 to Poe.


A bandage configured to be administered from a continuous roll, comprising: (I) a first layer of flexible webbed material, the first layer including a self-adhesive disposed on a top surface; and (II) a second layer of flexible padded material adhered to the first layer along a longitudinal axis by the self-adhesive, the second layer having a width less than a width of the first layer so that a portion of the self-adhesive is exposed on each longitudinal side of the second layer; wherein the self-adhesive may releasably adhere to a bottom surface of the first layer in a rolled form so that, when unrolled, an adhesive bond is broken free of damaging the first layer; and wherein, when the self-adhesive is bonded to itself and opposing adhesive portions, the resulting peel strength is greater than a peel strength when the self-adhesive is bonded to skin.

Conventional self-adhesive bandages are typically packaged individually in a wrapper to avoid contamination of the bandage prior to application. The individual bandages are pre-cut to specific lengths, requiring a user to search for an appropriately sized bandage for a wound. Continuous rolls for self-adhesive bandages have been proposed to improve the convenience and customization of the bandages for users addressing wounds. However, continuous rolls often require special medical cutting tools (i.e., medical scissors) to cut a desired length of the bandage. Furthermore, continuous rolls are often difficult to cut, difficult to unroll manually, or both.
Additionally, a release paper adhered to the self-adhesive side of the bandage is often required so that the bandage can be rolled on itself without being contaminated. Further, without a release paper the bandage will adhere to itself, resulting in damage that renders the bandage unusable. Thus, a user is required to unroll a desired portion of the bandage, cut a desired length, and remove the release paper prior to application. Typically, a user will have difficulty removing the release paper without damaging the bandage piece or accidently adhering the bandage piece to itself.
Examples of such rolls may be found in the following potentially related documents: Published U.S. Patent Application 2007/0179466; U.S. Pat. Nos. 5,843,011; 6,362,388; 6,756,519; 8,851,284; and PCT Publication No. WO 97/17045, all of which are incorporated by reference herein for all purposes. It would be attractive to have a continuous bandage roll that is free of a release paper. What is needed is a bandage roll that may adhere to a portion of itself without damaging the bandage. It would be attractive to have a continuous bandage roll that easily unrolls and is cut to a desired length without damaging the bandage. What is needed is a bandage roll dispenser that is configured to unroll the bandage and cut the bandage to a desired length. It would be attractive to have a continuous bandage roll dispenser that protects the continuous bandage roll after cutting a portion of the bandage roll. What is needed is a bandage roll dispenser that secures a continuous bandage roll within the dispenser and remains enclosed while not in use. It would be attractive to have an alternative bandage roll assembly, particularly those in which the bandage can removably adhere to a portion of itself without damage, yet still have sufficient peel strength to remain in place when applied to a wound. What is needed is a continuous bandage roll configured to removably adhere to itself without damage, yet also remain in place when applied to a wound. It would be attractive to have a more advantageous bandage dispenser to meet one or more of the above needs.

Dispenser for a sterile bandage on a continuous roll


A method of producing a fluorine-containing compound, which contains the step of: fluorinating a substrate in a solvent with fluorine gas, wherein as said substrate, a substrate that cannot substantially undergo fluorinating reaction independently, is allowed to react, in the presence of a substrate that rapidly undergoes fluorinating reaction independently.

Perfluoro compounds are excellent in chemical stability, dielectric constant lowness, refractive index lowness, viscosity lowness, lubricity, water repellency and oil repellency, non-adhesiveness, and the like, and they are applied to various materials, such as fluorocarbon rubbers, materials for plenum cables, optical fibers, antireflective films, pellicles, and the like. In recent years, therefore, methods of synthesizing a perfluoro compound effectively have actively been developed.
One method of synthesizing a perfluoro compound effectively is a direct fluorination method using fluorine gas. This method is very attractive from the viewpoint of energy-saving and high selectivity of a product, since, for example, this method is different from electrolytic fluorination, which requires vast energy and may generate a compound composed of mixed isomers. However, the direct fluorination method has a problem that the following occasionally advance: cleavage of carbon-carbon chains, oligomerization, generation of high heat, and explosive reaction.
Known methods of solving such a problem are to inject a substrate into an inert solvent, together with an excessive amount of fluorine (see, for example, U.S. Pat. Nos. 5,322,904 and 5,399,718, and International Publication No. WO 00/56694 pamphlet). In this method, fluorine is saturated into a solvent inert to fluorine, which will be referred to as an inert solvent hereinafter, and examples thereof include flon-series solvents and perfluoro alkane-series solvents. A substrate and fluorine are then introduced into the inert solvent such that the amount of fluorine would be excessive, i.e. the mol number of fluorine is not less than the amount necessary to fluorinate the substrate completely, thereby restraining coupling reaction between molecules of the substrate, decomposition reaction of the substrate, and explosive reaction. However, if the substrate accumulates in a reaction container without being effectively fluorinated and the reaction proceeds all at once at some point of time, it is expected that there is risk due to much heat generation and explosion is possible.
To avoid such risk, it is indispensable to cause the fluorination to proceed effectively from the early stage of the reaction. For this purpose, it is necessary to set conditions for causing the substrate to react effectively with fluorine.
One condition for causing the substrate to react effectively with fluorine is that "the substrate is soluble in a solvent and has a bond that reacts easily with fluorine." Of inert solvents, flon-series solvents are excellent in dissolving power. Thus, fluorinating reaction using a flon solvent is known (see, for example, U.S. Pat. Nos. 5,322,904 and 5,399,718). However, flon-series solvents have the problems that they are not easily available and that they are environmentally harmful compounds that deplete the ozone layer. Consequently, it would be difficult to use the flon-series solvents for the production of a perfluoro compound. Further, even in the case of using a flon-series solvent, there is the problem of explosion, depending on a structure of the substrate to be used (see, for example, Journal of Synthetic Organic Chemistry, Japan, 2003, vol. 61, No. 2, p. 164).
In another known example, a solvent other than flon-series solvents, such as Fluorinert FC-72 (trade name, manufactured by 3M Co.), is used to conduct fluorination (see, for example, U.S. Pat. No. 5,399,718). This solvent is inferior to flon-series solvents in power for dissolving hydrocarbon compounds. When this solvent is used to perform fluorination, the reaction proceeds as in the example described in U.S. Pat. No. 5,399,718, if a substrate may be dissolved in the solvent even in a small amount thereof, and the substrate has a bond that reacts easily with fluorine. However, if the substrate is hardly dissolved in the solvent, and further the substrate has a bond that does not react easily with fluorine, it is observed that the reaction thereof does not proceed at all, and the substrate floats in the reaction system.
When the solubility of a substrate in inert solvent is poor, another known method is to perform fluorination using a compound in which fluorine is partially introduced into the substrate in advance (see, for example, International Publication No. WO 00/56694 pamphlet, and Journal of Synthetic Organic Chemistry, Japan, 2003, vol. 61, No. 2, p. 164). However, in this case, the substrate is restricted to a substrate into which fluorine can be introduced in advance, thereby causing a problem that the range of compounds that can be fluorinated becomes narrow. Further, there is caused a problem that the cost for the substrate's raw material increases, since fluorine is beforehand introduced into the material.

Method of producing a fluorine-containing compound


Determining which edge nodes should be used for data feed preprocessing based on response time between the edge nodes and the sources and network bandwidth usage. Edge node determination does not rely on which edge node is closest in physical proximity to the source, but rather makes a determination that minimizes transmission time and ensures network bandwidth usage is minimized. Machine learning models associated with source and edge node are trained over time based on observed response times and/or network bandwidth utilization, subsequently the models are executed with bandwidth network set to zero and the model outputting the lowest response time is deemed to be the edge node that is used.

Data lakes are storage repositories that store a vast amount of raw data in its native format. In this regard, the raw data may be structured data (e.g., specified rows and columns) transmitted from data warehouses or the like, unstructured data (e.g., data transmitted from Internet of Things (IoT) devices, application logs or the like) or semi-structured data (e.g., XML data or the like in which key value pairs are present). While a hierarchical data warehouse stores data in files or folders, a data lake uses a flat architecture to accommodate the storage of the various different types of data. Moreover, a data lake may utilize cloud storage, in whole or in part, or more conventional object storage, such as Hadoop-oriented object storage or the like.
In large entities/enterprises, data lakes may be used to support various different analytical use cases. However, a sizeable portion of the data destined for a data lake is data that serves no purpose and/or value in the analytical use cases. For example, data from IOT devices that shows normal device behavior is generally irrelevant to the analytical use cases. As a result, data lakes may implement preprocessing, in which received data is filtered to remove irrelevant data prior to storing the data in the data lake. However, since all of the preprocessing occurs locally at the data lake, unnecessary network bandwidth is consumed by transmitting the entirety of the data to the data lake. This problem is exasperated when the entity/enterprise is a global entity/enterprise and, thus, the data lake receives data feeds from various world-wide locations.
When preprocessing is occurs upstream of the data lake, such as at an edge node, the physical distance between the source of the data feed (i.e., application server) and the edge node is not as important as the need to minimize response time and ensure minimal network bandwidth utilization.
Therefore, a need exists to develop systems, methods, computer program products and the like that intelligently determining which edge node from amongst a plurality of edge nodes should be selected for preprocessing a data feed destined for a target, such as a data lake. The selection process should minimize response time between the data source and the edge node, while ensuring minimal network bandwidth utilization.

Determining which edge node to utilize based on response time and network bandwidth


The present disclosure provides clamps used to assemble photovoltaic (PV) arrays with frameless PV modules. The clamp includes a clamp cover configured to fit within a clamp grip such that when the clamp cover is fitted to the clamp grip pockets are formed to receive portions of PV modules. A base of the clamp cover may include one or more legs that act as a stop to prevent over tightening the clamp.

Field
The present disclosure relates generally to clamps for assembling solar arrays, and more particularly to mid-clamps used to secure frameless photovoltaic modules to rail systems.
Description of the Related Art
Photovoltaic arrays are typically composed of a number of photovoltaic modules set within a metallic frame, and a rail system that supports the photovoltaic modules. When installing a photovoltaic array, a number of photovoltaic modules are assembled onto the rail system, which is sometimes called rails or racking structures. The metallic frames of the individual photovoltaic modules, and the structural pieces, e.g., the rails, on which the modules mount are generally made out of aluminum, which is typically anodized to resist corrosion.
One obstacle to the general adoption of solar energy for power generation is the cost to fabricate and install photovoltaic arrays. The metallic frames supporting the photovoltaic modules are a contributor to the higher costs of using solar energy for power generation. Recently, frameless photovoltaic modules, e.g., thin-film and crystalline photovoltaic modules, have been developed. Frameless photovoltaic modules eliminate the metal framing supporting the photovoltaic modules, which reduces the manufacturing costs to build the photovoltaic modules and thus the photovoltaic arrays. Further, the metal framing supporting the photovoltaic modules has been found to be less aesthetic pleasing than frameless photovoltaic modules.


An image processing device performs a color process to a color image signal. The image processing device includes a profile designating section that designates a profile describing color reproducibility of a standard recording medium that is a target of color conversion, a recording medium designating section that designates a recording medium that is to be actually used, and color conversion section that performs color conversion according to the recording medium designated by the recording medium designating section and the profile designated by the profile designating section.

1. Field of the Invention
The present invention relates to an image processing technique for performing a color process to a color image signal upon forming an image on a recording medium in a digital copying machine, printer and the like.
2. Description of the Related Arts
There has been known a technique for performing a color matching process by utilizing a profile that describes a color characteristic of each device when a color management process is executed among different input and output devices, i.e., when a process is executed for reproducing almost the same color even by use of any input device or output device. The profile specified by the ICC is normally and popularly used as the standard of a profile for every device. The ICC profile is used for a color calibration, color proof and the like. In the conventional color calibration, it is used for a color conversion process from a printing machine, in which a color is desired to be matched, into a color printer for calibration.
In general, a color image signal given in the color calibration is a signal of a color space according to a printing machine to which the signal is outputted, so that CMYK color space is used, for example. Therefore, in the case of performing the color calibration, the color image signal of CMYK color space is once converted into a color image signal of a color space that is not dependent on the device, with the profile of the printing machine, and thereafter, it is converted into a color image signal of a CMYK color space that is dependent on the color printer, with the profile of the color printer for calibration.
Many of the profiles prepared for every device correspond to the case where a standard recording medium is used. An output device such as a printer is assumed, for example. Even when the same recording materials are used, a color reproducibility greatly differs depending upon a recording medium on which an image is formed. FIG. 15 is a graph showing a CMYK tone performance in a typical paper quality, while FIG. 16 is a graph similarly showing a color reproduction area. FIG. 15 shows a tone characteristic when tone representation is performed with a single color of each primary color C, M, Y and K, wherein the horizontal axis represents a color material amount (%) and the vertical axis represents a color difference ΔE from a white section of a sheet. As understood by referring to FIG. 15, it is found that a desired color development can not be obtained at a middle and high density area in the case of using uncoated paper compared to the case of using an art paper or coated paper. Further, as shown in FIG. 16, the reproducible color area is narrow in the uncoated paper, compared to the art paper, so that it is found that a bright color cannot be reproduced.
As described above, the tone characteristic and color reproduction area are different depending upon a paper quality. Therefore, there arises a problem that, even when color conversion is performed by use of a profile of a standard printing condition for forming an image, the reproduced color is different depending upon the used recording medium.
In order to perform a color conversion process considering a color reproducibility that is different per recording medium, it is necessary to use a profile that is established by considering the color reproducibility of the recording medium to be used. Accordingly, there arises a problem that a profile should be newly generated for performing color conversion when a printed matter printed on a recording medium other than a standard recording medium is desired to be color-matched to the other printed matters. The generation of a profile requires a profile creating application or an expensive measuring device, thereby entailing a problem that a color-matching cannot easily be executed.
Further, even if profiles each corresponding to each recording medium are prepared, plural profiles should be prepared corresponding to many recording mediums as for each profile according to each device or printing characteristic, so that the number thereof becomes enormous. Moreover, it is not easy to select a desired profile among such enormous profiles upon using profiles, thereby entailing a problem of being difficult to use these profiles.

Image processing device, for performing color conversion, image processing method for color conversion image processing program for color conversion and recording medium


An interconnection structure suitable for use as an IC package, probe head or other electrical termination of high density where uninterrupted controlled impedance is desired is described.

High speed electronic signals circuits place significant demands on the circuits and interconnections employed in their point-to-point transmission. This is becoming increasingly important as signal speeds enter the multi-gigahertz range. The challenge begins at the chip and from there the problems cascade through the entire electronic interconnection chain. Ultimately the transmission of electronic signals through signal paths of uniform impedance is critical to the performance of advanced systems. This being so, interconnecting devices and structures that provide such capability are vitally important to the production of viable electronic products. Unfortunately, properly controlling the characteristic impedance, while changing the feature sizes and spacing of the conductors and changing location to redistribute signals exiting the chip, is extremely challenging using current design practices.
Typically, traditional interconnection schemes, beginning at the chip, create small discontinuities at each interconnection transition. For example, while the chip design provides for internal control of the myriad of signal generating circuits within it, the next level interconnections, such as the wire bonds used to interconnect the chip to the package, typically begin the signal degradation process by creating both a small amount capacitance at the point of interconnection and excessive inductance which can cause cross talk. The length of the wire bond, at which point the concerns of inductance becomes critical, is determined by the frequency of the signals being transmitted. As signal speeds rise, the acceptable lead length must be shorter so as not to interfere with the signal. Further down the interconnection pathway, the circuit paths within the package may also contribute to the degradation as those signals are redistributed to make their escape from the package. From there, interconnections to the printed circuit board or next level interconnection devices may include sockets, connectors and other circuit boards. With signal integrity a key objective at high speed, any disruption of the signal in transmission goes counter to that objective and can result in signal degradation, loss and reflections. While a number of solutions are available for low pin counts ICs, owing to the short electrical path and the degrees of freedom associated with such low pin counts, as the pin counts rise, the number of solutions drops off rapidly.
Overcoming the problem for higher pin count applications in a cost effect way is an area of need for innovative solutions. More specifically, there is need for IC packaging and probe head solutions which provide an uninterrupted, controlled impedance path from the terminations on the IC die to the terminations either on a package or to a probe card which will serve to interconnect to the next level interconnection substrate or electrical test system.
Thus it is desirable to have an interconnecting structure that provides a substantially seamless transition from one signal pitch to another without disturbing signal quality. Structures and methods for accomplishing these objectives and other objectives are disclosed herein.

Controlled impedance structures for high density interconnections


A method for evaluating a sensor array includes providing software having the sensor array topology, relating array elements to hardware components. Data from the array elements is collected and evaluated to determine operative components. Displays of the determinations are generated allowing a user to diagnose sensor array failures. Other aspects of the invention provide for automatic array failure diagnosis and improvement of sensor array directivity. An additional aspect provides a system for evaluating a sensor array incorporating a computer with a database and a display.

(1) Field of Invention
The present invention generally relates to methods of maintaining acoustic sensor arrays.
(2) Description of the Prior Art
Diagnosing failures in marine sonar systems is difficult for many reasons. One issue is that these systems operate in a noisy environment where the signal is difficult to separate from other noise. It can be difficult to determine if a sensor is inoperative and causing noise or merely receiving noise. Thus, it is often difficult to know if a sensor is inoperative.
Another issue is created by the complexity of these systems. Some systems feature long lines of fiber optic sensors. These sensors have a plurality of Bragg arrays made into them to reflect light at different frequencies. A plurality of lasers provides light at different frequencies to the sensors. Light reflecting from the sensors is interfered with light provided to a reference loop to give sensor information. This sensor information is converted from optical information to electronic information. The electronic sensor information is often processed in parallel in multiple processing boards. This sensor information can also be provided to a telemetry system to combine multiple streams of information on fewer cables. Many of these components are subject to mechanical deterioration because the system relies on transmission through a fiber optic line deployed from a marine vessel that operates in a harsh environment.
In any case, diagnosing the failing component or components in these types of systems is difficult because failure of one component may appear as failure of multiple components throughout the system.

The United States of America as represented by the Secretary of the Navy


A product exchange system comprising a controller and a memory coupled to the controller. The controller is configured to: provide an application programing interface configured to receive a delivery request from a first user for delivery of an item, wherein the delivery request includes an identifier of a second user, and wherein the API is configured not to receive a physical address of the second user; in response to receiving the delivery request, access a data storage system that stores an association between the identifier and the second user, and further stores one or more permission settings associated with the second user defining delivery requests to allow in response to receipt of the identifier from the first user or in response to receipt of one of the item and product characteristic; and, in response to receipt of the delivery request, tests the permission settings.

The present subject matter relates generally to systems and methods for an online identification to a physical address exchange platform.
In today's society, people are identified by a plethora of identifiers including their name, social security number, bank account number, residential address, password, birth date, and email address, among others. These forms of identity management are often "validated" by various regulated government organizations. As a result, these forms of identity management are reliable and useful for "real-life" offline transactions. By contrast, in the digital/online world, most online identities are based on unregulated and self-controlled parameters such as email address, mobile phone number, social media identities (e.g., Facebook identity, LinkedIn identity), etc. There is a need for a system that connects these two worlds in a meaningful way.
Because many identifiers are confidential information, most people prefer to keep their information private. However, individuals are continually asked to share their identifiers with third parties, for example, by providing a mailing address to a third party or by providing a billing address when purchasing an item online. However, it may be unsafe to share identifiers, such as a physical address, with unknown individuals. Moreover, the more confidential information an individual discloses, the more likely the person will be subjected to privacy challenges.
During a typical transaction, a sender selects an item from a retailer's website to send to a receiver. During checkout, the sender must input his or her name, the billing address of the buyer, gift options, the name of the receiver, the address of the receiver, and the phone number of the receiver. Based on the large amount of required information, many senders decide not to complete the purchase owing to either not having the time to complete the checkout process or because the sender may not have all of the receiver's personal information. For example, the sender may not have the physical address of the recipient and, perhaps, does not feel comfortable asking for such personal information from the receiver. In addition, physical addresses change often such that it is difficult for senders to track the changes in address in order to determine the most current address to use as the mailing address.
From a recipient's perspective, providing his or her residential address is not safe. In addition, updating a change of address is often a time consuming and laborious process. Typically, a recipient must update their address information in each organization. For example, a recipient must update their address with the post office, department of motor vehicle, internal revenue service, energy company, magazine subscriptions, place of employment, among a multitude of others.
In addition, conventional systems do not take into account the recipient's preference in shipping location. For example, a recipient may want certain packages sent from friends to be mailed to his or her home address, whereas the recipient may want to gifts from colleagues to be mailed to his or her work address.
Further, the rise of online shopping has led to an increase in shipping and logistics-related issues of delivery of online purchases. It has also led to an increased cost of digital and direct marketing, and a significant decrease in brick and mortar retail as well as store operations costs. There has also been a loss in commission charges on transactions accrued by brokers and agents, which are avoided through online purchasing. Product discovery has become easier, product reviews have become important, and competition has grown. In some instances, consumers have seen lower prices over time, and, with so many options available, sellers are under pressure to provide the best price. Every best price guarantee comes with multiple terms and conditions, making it difficult to compare offers on equal footing. Every consumer wants best price, but it has become increasingly difficult to find.
Often direct marketing companies send random offers or coupons or samples to their database list. However, many of these samples don't reach right recipient because of the use of a wrong or old address. Further, sometimes these samples or offers may not be relevant for consumers who receive them but could be very relevant to some of the consumer's connections (friends, relatives, or other relationships), but are unable to refer to them as they may not have their addresses at the time of referral. Conventional systems also fail to take advantage of social media connections, therefore, missing a valuable market opportunity. Further, the brands must absorb the costs associated with failed direct marketing attempts, increasing the end cost to the consumer. Traditional direct marketing also creates hurdles for brands by requiring brand to track consumer behavior, location, frequently visited locations, frequently purchased items, and other details using GPS-based mobile applications, digital cookies, discount offers, location-based offers, and other data.
Further, consumers are typically nervous to broadcast their needs, demands, and requirements online or otherwise in public for the fear of losing privacy and also because such broadcasting may result in overwhelming unsolicited contact (e.g., calls, mail, email, etc.). With better targeted connections between sellers and buyers, there are opportunities to eliminate middle men to more efficiently reduce the cost of the product to consumers.
Additionally, the use of a physical mailing address requires consumers to update residential addresses with businesses and government entities, including ecommerce stores, physical stores, credit card companies, gyms, club memberships, coffee shops, airlines, magazine subscriptions, hospitals, banks, and the United States Postal Service. This process of updating a mailing address with each entity separately becomes complex and time-consuming. Further, with the growth of international transactions, many parties have difficulty with inconsistent address formatting and language barriers, requiring a lot of effort and creating unnecessary delays. Local governments of growing cities and towns also experience challenges with defining addresses in terms of street number, street name, unit number, province or district, county, zip codes, and other address details, requiring community members to update records upon local changes to the system. In some cases, those updates are required frequently.
Accordingly, there is a need for systems and methods directed to an address system that does not jeopardize an individual's privacy information while considering a recipient's preferences.


Exemplary external medical devices are configurable to communicate with an implantable medical device (IMD). One medical device includes multiple IMD telemetry ports operable to connect IMD telemetry mechanisms to the medical device. The medical device also includes a control unit configured to control the IMD telemetry mechanisms.

Implantable medical devices (IMDs) exist in the marketplace to treat a range of patient conditions. For example, various IMDs are utilized to address cardiac-related conditions. External medical devices, such as programmers, are utilized to communicate with the IMDs. For instance, during an implantation procedure data can be transferred between the external medical device and the IMD. In some cases, operational data (i.e., instructions) can be transmitted from the external medical device to the IMD and data gathered by the IMD can be transmitted to the external medical device.
External medical devices are often manifested as a housing that protects a control or processing unit for processing the IMD related data. The external medical device can also include a telemetry mechanism for facilitating data transfer with the IMD or alternatively the external medical device can include a telemetry mechanism port for connecting to the telemetry mechanism. In various scenarios having a capacity to connect to only a single telemetry mechanism diminishes the performance of the external medical device and/or unnecessarily increases the time required to perform a procedure with the external medical device.

External medical device configurations for communicating with implantable medical devices


A method for estimating and/or reducing uncertainty in reservoir models of potential petroleum reservoirs comprises receiving the results of a stochastic seismic inversion, and transforming the inversion data into a form suitable for reservoir modelling and flow simulations, while honoring inter-property and inter-layer correlations in the inversion data as well as measured well data and other geological constraints.

At the time an oil or gas field is being appraised or developed, the development of a reservoir model usually centers on the task of building computer models suitable for forward flow simulation. Prior to this, much of the work will have focused on data acquisition and interpretation, and the construction of models suitable for simple volumetric calculations or drilling decisions. In particular, much of the interpretative work will be based on surface seismic data, and this is routinely fed into various inversion routines which produce pointwise (trace-local) estimates of the properties of direct interest, such as surface positions, layer thicknesses, hydrocarbon content, net-to-gross (NG or NG), etc.
In previous publications (Gunning and Glinsky, 2004, 2005; Gunning, 2003), the inventors have introduced an open source tool Delivery that enables users to perform a fully probabilistic seismic inversion for a layer-based model of the reservoir. This is a trace-based inversion, so it produces an ensemble of realisations of the relevant reservoir parameters at each point in the imaged seismic grid over a field. The 'meso-scale' layer resolution is usually around 5-20 m. At each 'common mid-point' (CMP) location, the inversion provides a full joint-probability distribution of quantities like the layer thicknesses, fluid content, NG, layer times, and velocities. The seismic inversion data produced by Delivery is an array of trace-local stochastic samples from a Bayesian posterior distribution of reservoir layer parameters, which contains complex correlations between layers boundaries, rock properties and fluid information, but no transverse correlations. This inversion data produced by the program is suitable for answering the simple kind of questions mentioned above, such as pointwise histograms of layer thickness, maps of hydrocarbon probability etc, but is not directly suitable for flow calculations per se.
In the past, trend maps have been formed from the results of seismic inversion for properties such as porosity and net sand. These trend maps have then been used to control the geostatistical population of properties and/or objects into the reservoir simulation model. However, none of the rich inter-property and inter-layer correlations were respected. The models have also tended to be built at extremely fine scale (less then a few meters) then upscaled to a coarser scale for reservoir simulation (less than tens of meters).
It would therefore be desirable to provide a method for converting seismic inversion data into a form suitable for use in reservoir models for flow simulation and/or volumetric calculations, while preserving the correlations available from the seismic inversion, and also honouring measured well data and preferably other geological constraints. In particular, it would be desirable to provide such a method which makes it possible to estimate and/or reduce uncertainty in the reservoir model.

Method for estimating and/or reducing uncertainty in reservoir models of potential petroleum reservoirs


A riser disconnect and support mechanism for flexible risers and umbilicals on an offshore structure with low under keel clearance. A main body portion includes an inverted and truncated conical or convex section substantially at the center of the main body portion. The main body portion and conical section receive risers therethrough by means of a plurality of conduits through the main body portion and conical section. A plurality of projections extend radially outward from the main body portion. A plurality of arch-shaped riser supports are provided on each projection to support risers and/or umbilical lines and control their bending radii. The projections extend out from the main body portion at a distance that allows the portions of the risers below the main body portion to hang at an angle and bend radius in accordance with the design tolerances of the risers to prevent buckling or damage due to excessive bending while keeping the risers from contacting the sea floor.

The invention is related to the use of flexible production and water injection risers and control umbilicals with offshore structures and more particularly to a riser disconnect and support mechanism.
Floating offshore structures used in drilling for and production of hydrocarbons (natural gas and oil) use drilling and production risers that typically extend from the sea floor to the keel of the structure and then to the topside of floating structures.
A potential hazard in offshore operations is the escape of hydrocarbons and other products from the production risers and control umbilicals into enclosed locations in and around the facility structure. These hazards may be caused by damaged risers or failures in mechanical connectors in the flow lines inside the facility.
In some situations the riser arrangements may have to be disconnected from the supporting facility and this facility returned for reconnect at a later time. For example, offshore structure designs for deployment in arctic regions have to consider ice forces that can be the governing design load. Unlike bottom founded structures such as compliant towers and jackets and gravity base structures (GBS), floating structures are challenged by mooring and riser designs that make resistance to maximum expected ice loads impractical and thus require disconnection from the risers and moorings as part of the ice management scheme. Also the floating support hull may be returned to port for refitting or reconfiguration of the topsides.
Moored floating structures such as the ship-shaped Floating Production Unit (FPU), the Spar, and the Single Column Floater are practical designs for support facilities. Even in shallower water where earthquakes are a threat, the moored floater can be the better option because of its ability to avoid seismic effects of an earthquake on the structure since it is suspended in the water above the sea floor.
Several designs to disconnect and support riser arrangements from the floating support facilities presently exist.
The FPSO/PPS (Floating Production Storage and Offloading/Floating Production and Storage) generally has a weather-vaning mooring turret attached inboard at the keel. Risers and umbilicals pass through the turret up to the onboard production facilities. For disconnect between the risers and hull, the risers are disconnected at the turret and released to separate from the hull. After release the buoy is suspended in the water column with the aid of mooring lines and supports the risers. To reconnect, the buoy is recovered by the hull and pulled back into position. The risers are reconnected at the turret. The draft of the ship-shaped hull is generally in the order of 30 meters. At this draft it is practical to provide one atmosphere dry access to the assembly around the turret to make it accessible for inspection, maintenance, and repair.
Other designs based on deeper draft facilities such as the Spar and Single Column Floater have drafts in the order of 100 meters to 200 meters. These hull types offer the advantage of reduced motions, thus improving conditions for general operations and have a significant reduction in fatigue damage to the risers as compared to the shallower draft ship-shaped hulls. Spar based designs such as U.S. Pat. Nos. 7,377,225 and 7,197,999 describe disconnectable buoys at the keel similar to the FPSO/FPU with riser disconnect at the keel. The disadvantage of these designs is the depth of the disconnect buoy. Due to the in-situ pressure and space constraints inspection, maintenance, and repair are difficult and complicated. There is also risk that hazardous product escaping from the risers due to faulty connections at the buoy can collect inside the hull.
Floating offshore structures with relatively low clearance between the bottom of the structure and the sea floor also present special challenges for the connection and disconnection of risers at the bottom or sides of the structures. The flexible risers typically used with floating offshore structures have a minimum allowable bend radius beyond which will cause breakage of the riser. Also, the flexible risers must not touch the sea floor during connection to or disconnection from the structure and during the time that the risers are supported when not connected to a structure. These two challenges are not satisfactorily addressed in the current art.


Some embodiments of the invention provides a media editing application that includes tools to perform a variety of different editing operations based on roles assigned to media content. In some embodiments, the media editing application includes focus-editing tools to emphasize or de-emphasize different sets of clips based on the assigned roles. In some embodiments, the media editing application allows one or more sets of clips to be disabled or enabled during playback based on the assigned roles.

To date, many media editing applications exist for creating media presentations by compositing several pieces of media content such as video, audio, animation, still image, etc. Such applications give users the ability to edit, combine, transition, overlay, and piece together different media content in a variety of manners to create and output a resulting composite presentation.
Some media content producers (e.g., movie studios, broadcast stations) require a particular type of content in a composite media presentation to be separate from other types of content. For instance, a movie studio may require the video content to be separate from the dialogue or music content. This content separation allows the movie studio to easily replace the dialogue content in a first language with dialogue content in a second different language.
To output separate content, several media editing applications allow their users to create multiple tracks and specify different output channels for these tracks. FIG. 1 provides an example of such a media editing application 100. The media application 100 includes a composite display area 105 that includes different tracks 110-125. As shown, the application's user has created several tracks with the media editing application, and arranged one set of clips (e.g., "Dialogue" clips) along one track, another set of clips (e.g., "Music" clips) along another track, etc. The user has also specified whether these tracks should be output to separate channels. In the example illustrated in FIG. 1, the user has specified that the track 115 (e.g., with three "Dialogue" clips) should be output to a first channel, while the track 125 (e.g., with two "Music" clips) should be output to a second channel.
There are a number of shortcomings with such media editing applications as described above. For instance, the media editing application requires its user to create multiple tracks for different output channels and arrange clips along these different tracks. This constrains the application's user as the tracks are used for outputting the composite presentation when they could be used for other purposes. For instance, each particular track can be used to edit clips, create transitions between clips (e.g., keyframing), define compositing order, etc.
As another example, in the track-based system as described above, the editing operations are intrinsically tied to output operations. That is, if a composite presentation was edited without initially considering different output channels, then the user may have to re-edit the composite presentation by creating additional tracks and rearranging the media clips along the additional tracks. Such re-editing can be time consuming, especially when there are many clips that are part of the same composite presentation.
In addition to the different output channels, the media editing application requires its user to know what type of content is included in each clip. The application's user may have to input descriptive names for different clips so that it is clear what types of content are contained in those clips. For example, the user may have to input a particular clip name that indicates whether the clip contains dialogue, effect, music, etc. Otherwise, one or more clips could be placed on a wrong track if the user does not know what type of content is included in each clip.


Process and apparatus for precision scoring a workpiece of variable thickness and/or shape in which the thickness of the workpiece at points along a trace pattern is first determined, and a variable depth groove is thereafter formed by laser scoring which is controlled in correspondence with the previously determined thickness values. These values can be determined by scanning opposite surfaces on the surface of a locating fixture and a surface of the workpiece. Robot manipulators are used for scanning and scoring, and the power of the laser and/or the trace velocity are controlled to vary the degree of scoring. The scoring is used to special advantage for precision preweakening of auto trim pieces for creating an air bag deployment opening.

This invention concerns laser scoring of an automotive interior trim piece in which a laser beam is used to score the surface of material, as to create a line of preweakening.
It has previously been proposed to create a preweakening of a trim piece to allow a deployment "door" to be formed by the pressure of an inflating air bag causing an outer covering as a layer of vinyl plastic to rupture in a desired pattern to form an opening allowing the air bag to deploy into the passenger compartment from a storage canister mounted behind the trim piece.
This construction is useful for so-called invisible seam construction installations particularly for the passenger side, in which the location of the air bag is concealed by the absence of any externally perceptible suggestion of a deployment opening door.
The use of the pressure generated by the inflating air bag to rupture the covering skin requires that a precisely controlled preweakening of the covering be carried out.
The air bag must perform reliably over a wide range of ambient temperature conditions. The strength and elongation characteristics of the covering layer, typically of a tough plastic such as vinyl or leather, JPO, TPE, or TPU, varies considerably with ambient temperature. If the covering layer presents too much resistance to rupture, proper deployment of the air bag may not occur due to the resulting delay in overcoming resistance of the covering layer.
At the same time, the preweakened covering must retain sufficient strength so as to not crack or show the line of preweakening on the passenger side.
Covering layers, particularly when made of cast plastic, typically are of irregular thickness due to the inherent lack of precision of the manufacturing process. This variation in thickness makes it difficult to execute preweakening by scoring, as a scored groove of constant depth will result in an erratic preweakening at points along the door pattern since the thickness of the remaining material will vary.
This in turn causes erratic air bag performance due to variations in the precise moment when the air bag will burst through the covering layer.
Production in the automotive field involves large numbers of parts and such air bag system components should desirably have a very low defect rate, i.e., one part per million or less so as to be consistent with current standards.
The object of the present invention is to provide processes and apparatus for precision laser scoring of workpieces which are of varying thickness.


A reciprocating ejector mechanism for an electric bed comprising an aperture formed on a bed board. An ejector mechanism is mounted in the aperture. The ejector mechanism includes an ejected part, which is arranged parallel to the bed board. At least one first connecting rod with one end is connected with the ejected part and another end is hinged with a slider. The slider may slide along the guide bar fixed on the bed board. A second connecting rod with one end can be hinged with the middle part of the first connecting rod and another end hinged with the bed board. The ejector mechanism may have a driving device fixed on the bed board and connected with the linkage to drive the first connecting rod to rotate, so that the ejected part is driven to move parallel to the bed board.

The electric bed is a new type of bed, where the shape of its bed surface is changeable according to user needs. In order to improve the comfort of the electric bed and further satisfy the user's comfort requirements, relevant manufacturers researched and developed many additional functions. One of these functions includes an ejector mechanism for head and waist positioning such as neck or lumbar support. Ejector mechanisms may allow neck support, lumbar support.
Chinese patent publication CN 201220387006 discloses an electric bed with head and waist ejector functions where a head ejector mechanism uses a composite structure of a hinge and a push rod. The ejected part has one end hinged with a bed board (frame) and another end driven by a linear motor so that the ejected part is ejected during rotation around the hinge joint. The bed board is a bed board frame from which the ejector mechanism protrudes. Thus, the bed board is referred to as the bed board (frame).
The lumbar or waist ejector mechanism uses a lifting pole driven by the motor and can rotate around a fixed point below the bed board (frame) to raise/drop the mattress for the waist, playing a role of supporting or massage.
Curvilinear movement achieves the above-mentioned ejector mechanism used in the prior art. The ejected part is not parallel to the original bed board (frame), so user experience can be poor in case of pinching. Additionally, the head ejector mechanism does not have massage function. The waist ejector mechanism also scrapes with the mattress due to its movement in a curve, thereby shortening the service life of the mattress.


A data entry system comprising of: an input surface, a limited number of input elements of any shape and positions at the input surface, and a processing device (for detecting a continuous sweeps of an input object over the input surface, for tracking a sequence of the input elements interacted with the input object during such sweeps, and for generating a function associated with the sequence after the sweep is completed). A system characterized in that the processing device is adapted for time independent and reliable detecting a sequence of input elements, even if an input object could interact with several input elements simultaneously. A system also characterized in that the sweeps may represent strokes of handwritten symbols. The invention can be utilized in new designs of compact data input systems for electronic devices.

As the functionality of electronic devices continues to increase, most such devices require alphanumeric input and extended controls. Several solutions for data entry for such devices exist like compact keyboards, handwriting recognition, and voice recognition.
Among the possible solutions, handwriting recognition is one of the more popular solutions because it is intuitive, fast, and requires a small footprint on a device. However, handwriting recognition is typically restrictive, requiring sophisticated processing and hardware as well as being less accurate and less flexible than keyboard input.
A primary problem of handwriting recognition is that processing algorithms are quite sophisticated and require considerable processing power. Moreover, even the best algorithms have less than a 100% recognition ratio. Another problem is that handwriting recognition systems are difficult to customize to individual writing styles. All systems are language (alphabet) dependent and require separate, additional modules for every new language. In addition, handwriting recognition requires a high-resolution, sensitive display for symbol input.
Different methods have been proposed to solve the aforementioned problems. Many approaches, such as Unistroke™ from the Xerox Corporation and Graffiti™ from Palm, Inc., require inputting only special, simplified strokes. In these approaches, symbols are typically represented by only one stroke. Using only one stroke simplifies the processing algorithms, but necessitates memorization of the default set of strokes, which precludes easy implementation of these methods by new users.
Due to the complexity of symbol description for traditional handwriting recognition systems and the nature of recognition algorithms, no existing system has 100% recognition ratio, and most typical handwriting recognition systems have much lower recognition ratios that makes these systems unappealing to users.
Some systems provide limited customization of symbols and functions, but that typically increases the complexity of both the system and the hardware requirements.
Some approaches are based on recognition of symbol shapes at a low-resolution rectangular sensitive matrix. Additional restrictions are added on symbol shapes as well as requiring user-memorization of symbol shapes. Due to input limitations, these solutions have simpler processing algorithms and a higher recognition ratio but are usually time-dependent upon the input by the user. As such, these systems typically are not considered to be highly user-friendly in a manner that would appeal to typical users.
Other approaches are based on processing sequences of elements of low-resolution rectangular sensitive matrix. These approaches do not provide natural multi-stroke recognition and customization. These approaches require adjacency of sensitive elements, but do not work correctly with wide input objects like fingers which could activate several elements of the matrix simultaneously.
Further, typical methods for handwriting recognition require the use of a stylus or pen as an input device and a high resolution input device such as a pressure sensitive or resistive touchpad. By using a stylus on a high resolution input device, a processing algorithm may be defined by curve approximations for the symbols represented by single strokes. The need for a stylus is a problem for users of devices such as mobile phones which are typically not used with a stylus and may typically be used with one hand for single-hand entry and operation. For example, a user typically can hold a mobile phone in one hand and operate the device or enter information using the same hand, typically with the thumb of the hand holding the device.
Accordingly, improved data entry systems and associated methods are desired to provide data entry for small electronic devices such mobile phones.

Stroke-based data entry device, system, and method