The invention is a system and method for conveying information, job skills, academic courses, and/or other forms of learning (collectively “education”). The subject matter being taught is organized into small modular units called content modules. Content modules can be invoked in a highly flexible manner and order, based on interactions with the user. A learning matrix selectively identifies which content module is to be subsequently invoked, on the basis of user goals, test results, prerequisites relating to the subject matter, empirical evidence relating to how persons typically learn the particular subject, prior content modules invoked by the user, and/or any other potentially relevant characteristic. By incorporating information relating to the user, the user's performance, the subject matter, and/or empirical data relating to how people learn the specific subject matter, subsequent content modules can be selected to specifically tailor the learning process to the specific context of the user.

This invention relates generally to systems and methods for the providing of teaching and/or training. More specifically, the invention relates to a teaching and/or training approach that utilizes highly compartmentalized content modules, frequent individualized feedback, and a highly flexible, configurable, and targeted learning matrix for navigating the various content modules on an individualized basis using relevant data tracked by the system.
In a world of increasing technology, complexity, and specialization, the importance of education has never been greater. The increased demand for education is not limited to traditional academic environments such as colleges, universities, k-12 schooling, and other more traditional academic environments. Businesses, government entities at all levels, non-profit organizations, and other organizations increasingly provide job-related training, in addition to other forms of education, skill acquisition, and knowledge conveyance.
New academic subjects, job skills, and other forms of knowledge, information, analysis, techniques, and skills (collectively "knowledge" or "education") are being created every day. Some of the subject matter thought to be of crucial importance in the present is only a short number of years old. The impact of the every increasing aggregate knowledge base should not be underestimated. However, improvements with respect to education tools and methodologies to convey knowledge have been substantially more modest.
Many technology advances have spilled over into education systems. New technologies such as computers, the Internet, and other technological advancements (collectively "new technologies") have a significant presence in both academic and non-academic education environments. However, education systems have not been designed, implemented, or configured to take advantage of the iterative processing, database capabilities, and other advantages of the new technologies that would allow information to be taught in a fundamentally different way. Instead, new technologies are being used to simply automate old education processes that used to be manual processes. The improved opportunities for communication brought about by such new technologies is not to be underestimated. However, the new technologies have not been configured to adjust with the core issue of how people actually learn, and how technology can bring about fundamental improvements to the learning process. Whether the particular learner is a fast learner, a slow learner, or an average learner with respect to a particular subject matter, all learners can benefit from a more targeted, interactive, and modular approach.
Modern information conveyance techniques are not fundamentally different from those used in United States in the 1800's, and by other civilizations and cultures at even earlier times. The education process, including the knowledge and skill conveyance provided in non-academic environments, is highly linear. All students in the class are presented essentially the same material, in essentially the same fashion and order. This is despite the fact that each student brings a different knowledge base, a different past education history, different education goals, and different methods of learning. The existing linear system is thus less individualized than it should be. Quick, slow, and average learners alike are needlessly hampered by such linear and non-interactive education processes.
Even when taught on an individual basis, students and others to whom information, knowledge, and skills are to be conveyed (collectively "students" or "learners") are traditionally taught in a linear manner, with infrequent feedback relating to the student's acquisition of the desired skills, knowledge, and information. The characteristics of low interactivity and high linearity are particularly pronounced in formal academic environments, although non-academic environments suffer from similar limitations.
Semesters that typically span across a number of months constitute the primary building block of time in the education process. For example, a student's performance during the first few weeks of a semester-long course does not typically impact the materials taught during the last few weeks of that same semester-long course. In such a traditional environment, a student's failure to grasp critical material is not identified in a manner that impacts the student's curriculum until an inadequate grade for the course prevents satisfaction of a particular perquisite for a subsequent course or a graduation requirement. Moreover, if a student has a fundamentally inadequate or flawed understanding of a subset of the materials in a particular semester course, the student could pass the class, only to encounter trouble in subsequent courses due to a lack of understanding of the particular subset of materials. For example, an engineering student can "get by" in a particular mathematics course because a particular type of problem was merely one of many, only to find that the same particular type of problem is the basis for an entire advanced class of physics or engineering a year or two later.
The existing art does not identify the strengths and weaknesses of a student's performance in units that are small enough to optimize the learning opportunities of the student. Semester-long time frames are much longer than the "bandwidth" with which students learn. It would be desirable for the education process to be broken down into smaller modular learning units. This would facilitate the ability of a system to truly target the teaching process to the particular student or user.
The syllabus of a semester-long course is generally predetermined from start to finish in a very linear manner. In prior art systems and methodologies, subject matter is taught in a predetermined order that fails to take into account the specific difficulties and strengths of the students in the course. Similarly, the particular goals of the students are also ignored. For example, different "story problems" using differential equations or integral calculus should be used if a particular student is pre-med than if the student wants to be a mathematician.
It would be desirable to integrate all potentially relevant information relating to a student, including the student's learning goals, the subject matter(s) being studied, past performance on tests with regards to specific content, etc. into a single learning matrix that could manage the learning process for a student.


A data dictionary is provided that specifies the entities and corresponding attributes for the application program interface developers to use. An extensible markup language interface is provided for customers to perform operations on the data. Application program interfaces receive extensible markup language requests and generate extensible markup language response documents that may return data from the database. A set of classes is also provided that correspond to the entities that are defined in the data dictionary. These classes define utility methods for use in retrieving data. The application program interface then appends the returned response object at the depth necessary in order to generate an extensible markup language document.

1. Technical Field
The present invention relates to data processing systems and, in particular, to building application program interfaces for extensible markup language documents.
2. Description of Related Art
Database architectures, such as E-business infrastructures, include large numbers of data entities. These entities may be stored as objects in a data store. The data entities also include large numbers of attributes, which may also be entities. An application program interface (API) may be programmed to access the entities and their attributes.
However, entities may share common attributes. For example, status may be an attribute of several entities, such as customer, user, server, etc. Thus, developers may need to provide code for accessing entities and their attributes redundantly.
Furthermore, the database architecture may change. For example, database column names may change or be removed from previous versions. Therefore, a developer may also need to update the API code for every change in the database architecture. The code must-also be changed for each entity being affected.
Therefore, it would be advantageous to provide an improved mechanism for code reusability and maintainability in application program interfaces.

Method, apparatus, and program for code reusability and maintainability in XML-driven projects

International Business Machines Corporation


A rear steer mower having a front steering assembly is provided. The front steering assembly includes a steering wheel, a steering shaft, a pair of toed out negatively castered front wheels and a linking element configured to receive rotational input from the steering wheel to the pair of front wheels.

(1) Field of the Invention
The present invention relates generally to riding mowers, and in particular, to a hydrostatically controlled rear steer mower with a front steering mechanism.
(2) Description of the Prior Art
Lawnmowers are well known in the art and have been used for decades to maintain a lawn's appearance. In the prior art, the lawnmower design has typically been of the form of a riding mower that is propelled by the use of a gasoline or diesel engine. A mowing deck is located beneath the mower, and in some circumstances in front or behind of mower. The mowing deck is usually powered by the same gasoline or diesel mower that propels the vehicle. The mowing deck may contain a series of pulleys connected with mowing blades that operate in a rotational pattern to cut a lawn.
Many problems have plagued the riding lawnmower. In the past, riding lawnmowers were incapable of cornering in an acceptable turn radius. In order to correct this problem, the prior art implemented a rear steer mowing system, commonly called a zero turn mower. This rear steer mechanism made each rear wheel independently controllable by the operator and turning was facilitated by slowing the inner turn radius wheel while accelerating the outer turn radius wheel. However, these zero turn mowers were deficient in the regards that they were susceptible to loss of tire grip while cornering and on steep terrain. When the rider was operating the vehicle on a steep terrain, the higher elevated tire would lose contact with the terrain surface and thereby cause the mower to sway out of control from the operator. This created a dangerous and inefficient method of mowing.
Thus, there remains a need for a new and improved hydrostatically controlled rear steer mower that is capable of maintaining tire grip while traversing rough, uneven or highly sloped terrain.

Rear steer lawn mowing vehicle with front steering means


A temperature compensated CMOS RC oscillator circuit changes the source-bulk voltage to stabilize the MOSFET's threshold voltage variation over temperature using a resistor and temperature-correlated bias current. The MOSFET's source is connected to ground through a resistor. This temperature-correlated bias current also runs through this resistor. When temperature increases, the bias current also increases, which increases the MOSFET's source-bulk voltage. The increased source-bulk voltage helps to stabilize the threshold voltage of MOSFET at high temperature. A power saving logic is also embedded in this oscillator to achieve higher frequency at lower power consumption. In the present invention, there is no high gain op amp or high speed comparator, which makes the resultant oscillator to be low power design and which can be integrated into a single chip with other system.

An accurate clock generator is very important for signal-conditioning in a variety of applications. An application specific integrated circuit (ASIC) operating that utilizes such a generator in an environment is subject to substantial variations in temperature. One example of such an environment is an automotive application, in which the temperature range could be from −50 C to 150 C. An unstable clock frequency reduces the performance of the internal circuits, especially the switched-cap circuits, baud rate generator and handshake circuits.
To provide a stable reference clock, many oscillator circuits have been studied. A common one is the crystal oscillator, an example of which is disclosed, for example in U.S. Pat. No. 6,377,130. However, a crystal cannot be integrated into a single chip and its usage is limited by its size.
RC oscillators have been studied for a long time. Conventional RC oscillators are limited to low-frequency, low-precision applications sources such as tone generators, alarms or flashing indicators. Also, the temperature coefficient (TC) parameters of those resistors and capacitors are hard to control.
Many other RC circuits, like canonic RC-active frequency oscillator, require an operational amplifier as disclosed, for example in U.S. Pat. No. 5,870,345 or a comparator as disclosed in US Patent Publication No. 2005/0134393, to stabilize the oscillating frequency. To provide whether to build a high gain operational amplifier or a high speed comparator is complicated and expensive in the hardware and power consumption. This is particularly true if the frequency of the application is up to megahertz range. Also the offset voltage of the operational amplifier and comparator is temperature dependent, which gives a temperature dependent clock signal. To correct this offset, a complicated circuitry is required.
Due to the aforementioned drawbacks, conventional approaches cannot provide a stabilized oscillator circuit integrated into ASIC with a high performance. Therefore a new approach is necessary. The present invention addresses such a need.

Temperature compensated RC oscillator for signal conditioning ASIC using source bulk voltage of MOSFET


A liquid crystal display device (LCD) is provided, in which a first alignment layer is formed to have at least a pair of domains having alignment directions that are perpendicular to each other on a unit pixel, a second alignment layer is formed in the same direction as the first alignment layer, and an optically compensated bend (OCB) mode liquid crystal layer is disposed between the first and second alignment layers to have at least a pair of domains having alignment directions that are perpendicular to each other, so that horizontal and vertical viewing angles can be improved and phase transition voltage can be lowered.

1. Field of the Invention
The present invention relates to a liquid crystal display device (LCD) and, more particularly, to an LCD having wide vertical and horizontal viewing angles and including first and second alignment layers for forming a liquid crystal layer that easily makes a transition to an initial bend phase.
2. Description of the Related Art
Nowadays, in order to overcome the shortcomings of conventional display devices such as cathode ray tubes (CRTs) that are heavy and large-sized, much attention is being paid to flat panel display devices (FPDs), for example, LCDs, organic light emitting display devices (OLEDs), and plasma display panels (PDPs).
In a typical LCD, liquid crystals are injected between two substrates including electrodes for generating an electric field. The electric field is generated between the substrates by the application of different electric potentials to the electrodes, so that the arrangement of liquid crystal (LC) molecules is changed. Thus, optical transmittance is controlled so as to display an image on a screen.
FIGS. 1A and 1B are perspective views illustrating an operating principle of a twisted nematic (TN) mode LCD, which is the most representative type of LCD. Referring to FIG. 1A, the TN mode LCD includes a first substrate 101, a second substrate 103, a light source (not shown), and a liquid crystal layer 106. A first electrode (not shown) and a first alignment layer (not shown) are formed on one surface of the first substrate 101, and a first polarizer 102 is formed on the other surface thereof. A second electrode (not shown) and a second alignment layer (not shown) are formed on one surface of the second substrate 103, and a second polarizer 104 is formed on the other surface thereof. The light source supplies light 105 from above the other surface of the second substrate 103. The liquid crystal layer 106 is filled between the first and second substrates 101 and 103.
A polarization axis of the first polarizer 102 is located in the same direction as a direction 107 in which the first alignment layer formed on one surface of the first substrate 101 is rubbed. A direction 108 in which the second alignment layer formed on one surface of the second substrate 103 is rubbed is perpendicular to the direction 107 in which the first alignment layer is rubbed. A polarization axis of the second polarizer 104 is located in the same direction as the direction 108 in which the second alignment layer is rubbed.
Referring to FIG. 1A, in an inactivated state where no voltage is applied between the first and second electrodes, it can be seen that the major axes (i.e., local optical axes) of LC molecules of the liquid crystal layer 106 filled between the first and second substrates 101 and 103 are gradually twisted due to the directions 107 and 108 in which the first and second alignment layers are rubbed. Thus, an LC molecule 106a close to one surface of the first substrate 101 is twisted at an angle of 90° to an LC molecule 106b close to one surface of the second substrate 103. As a result, the light 105 emitted from the light source is linearly polarized by the second polarizer 104 (refer to 105a), rotated by the LC molecules of the liquid crystal layer 106 (refer to 105b), and then externally emitted through the first polarizer 102 having the polarization axis perpendicular to that of the second polarizer 104 (refer to 105c). Referring to FIG. 1B, in an activated state where a voltage is applied between the first and second electrodes, LC molecules of the liquid crystal layer 106 are not twisted any more and become parallel to each other due to an electric field generated by the voltage. Thus, light 105a obtained by linearly polarizing the incident light 105 is not rotated any more and is wholly absorbed in the first polarizer 102.
However, the TN mode LCD has narrow horizontal and vertical viewing angles and a slow response speed. Thus, optically compensated bend (OCB) mode LCDs have been proposed to solve the problems of the TN mode LCD, but it is still necessary to improve horizontal and vertical viewing angles.


A two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate transistor, has a drain coupled to the write bit line, a gate coupled to the word line, and a source coupled to the source line. The merged transistor effectively consists of a floating gate transistor in series with a NMOS enhancement transistor. The series NMOS transistor has a voltage threshold of about 1 to 2 volts, thus preventing cell activation caused by overerasure (negative voltage threshold) of the floating gate transistor.

This invention relates generally to memory and programmable logic devices having electrically programmable memory cells, and more specifically, to an improved two-transistor flash EPROM cell which prevents negative voltage thresholds after cell erasure and prevents conduction paths through the cell during programming subsequent to an erasure.
It is often desirable in digital systems to include memory which may be programmed in the field by the customer and later reprogrammed if necessary. It is also desirable to provide such programmable memory in a form where the information is stored in a nonvolatile manner, that is, in a manner where power is not required to maintain the stored information. Previously, fusible programmable logic devices were used to provide this on-site programmability. Because these devices relied on the physical destruction of fuses, however, reprogramming the memory device was impossible.
A family of devices, known as EPROMs, dependent upon avalanche charge injection or "hot" injection onto a floating-gate has evolved. In EPROMs, under the influence of a high applied drain voltage, charge collects on the floating gate where it is trapped by surrounding oxide insulation. The cell is erased by ultraviolet light which increases the energy of the floating gate electrons enabling them to jump the energy barrier and dissipate.
Another family of devices, known as EEPROMs or E.sup.2 PROMs can be electrically programmed and electrically erased. The basic technologies used to make E.sup.2 PROMs today typically rely on Fowler-Nordheim tunnelling, which is cold electron tunnelling through the energy barrier at a silicon-silicon dioxide interface. A thin oxide layer is required for this process. Flash EPROMs can be electrically programmed and electrically erased, yet typically allow a smaller memory cell size compared to the E.sup.2 PROM cell.
Programming flash EPROMs relies on charge injection. FIG. 1 is a schematic drawing of a small portion (4 cells) of a flash EPROM array such as in products sold by Intel Corporation. To program a flash EPROM cell 110, a high voltage is applied to the word line 112 to thereby raise the potential of gate 115. A high voltage is also applied to drain 114 of the cell to be programmed. This places a charge on the floating gate 118, adjusting the threshold voltage of the cell. Unlike the conventional EPROM cell which is erased by ultraviolet light, however, erasure of the cell 110 is dependent on Fowler-Nordheim tunneling. During erasure, the gate 115 of the flash EPROM cell is grounded, the source 116 is raised to a high voltage, and the drain 114 is allowed to float. These conditions allow charge on the floating gate to tunnel through the floating gate oxide and dissipate, leaving the floating gate unprogrammed.
Unfortunately, one of the problems associated with E.sup.2 PROM cells not found in conventional EPROM cells is the tendency for the voltage threshold of the device to become negative after erasure. This phenomenon does not occur in conventional EPROMs, where the floating gates return to the original voltage (zero volts) after erasure. In the flash EPROM cell, overerasure can leave the floating gate charged, resulting in a negative voltage threshold. A negative voltage threshold can prevent later accurate reading of the cell by the sense amplifier (coupled to drain 114). Typically when reading a particular cell 110 in a memory array, a logical "one" level is applied to the cell word line 112 for the row in which a cell is to be read and a logical zero level is applied to all other cell word lines, i.e., word lines not having the cell to be read. If the voltage threshold of the cell 110 which is to be read, however, is negative after the erasure, application of a low or zero voltage to the word line 112 will result in the overerased cell in word line 112 being turned on, which can prevent the sense amplifier from sensing a voltage differential. Thus, the sense amplifier may not be able to recognize the programming of which cell is on and may not be able to read a correct voltage.
Different flash EPROMs combat the problem of negative threshold voltage in a variety of ways. At the 1989 IEEE International Solid State Circuit Conference Session of Non-volatile Memory, a paper entitled "Nonvolatile Memories," by Kynett, et al., described a flash memory which controls the memory array erase threshold voltage by using an erase algorithm. Instead of using a single fixed pulse erase voltage, the described device changes the voltage pulse according to an erase algorithm to prevent overerasure.
A flash E.sup.2 PROM memory cell developed by Seeq Technology is shown in FIG. 2 and was described in the 1987 IEEE International Solid State Circuit Conference, Session VII of Non-volatile Memory. See "A 128K Flash EEPROM Using Double Polysilicon Technology," by Samachisa, et al. The flash E.sup.2 PROM transistor cell 210 is an integrated circuit structure which merges a floating gate transistor 212 in series with a NMOS transistor 214. If the erase voltage threshold of the floating gate transistor 212 becomes negative, the application of zero volts to the control gate of transistor 212 typically would turn on the transistor. Because of the NMOS transistor 214 in series with the floating gate transistor 212, however, the cell 210 has a voltage threshold of about +1 volt, and the cell 210 will not be turned on.
Although the Seeq flash E.sup.2 PROM solves the negative threshold voltage problem, there are problems associated with such a cell. Programming the Seeq flash E.sup.2 PROM device relies upon hot electron injection which is strongly dependent on the effective channel length. Dependency on the channel length is problematic because the channel in the Seeq transistor is not self-aligned, increasing the probability of punchthrough or longer programming times. Furthermore, the series NMOS transistor 214 adds to the cell resistance. This increased resistance makes hot electron programming more difficult, increasing the time needed to program the device.
Accordingly, a flash EPROM cell which decreases the time needed to program the cell, and which prevents a negative voltage threshold is needed.


A body channel communication method is disclosed including the following steps. Whether or not a body channel is established is detected. When that a body channel is established is detected, a check packet is received from an electrical device, which is at another end of the body channel, through the body channel. A current interference power of the body channel is estimated according to the received check packet. A current transmission mode for the body channel is obtained according to the current interference power. Data is transmitted through the body channel, which is set to the current transmission mode. Further, a body channel communication device is also disclosed.

1. Technical Field
The present invention relates to a body channel communication method and device.
2. Description of Related Art
Body channel communication (BCC) is a technology applying the human body as the signal transmission medium for data transmission. In particular, in that the human channel features good conductivity, signals transmitted through the human skin is subject to lower path loss. Compared with the wireless channel transmission, more power can be utilized for modulation during transmission through the body channel. Accordingly, data can be transmitted through the low frequency domain utilizing the BCC technology, which can omit the high-frequency radio frequency (RF) circuit and is suitable for low power systems. In addition, the interference caused by other high-frequency RF products can also be avoided.
At present, the BCC technology is apt to be interfered by external noises coupled to the various body channels, which limits data transmission rate. Hence, BCC technology is insufficient to provide boarder bandwidth for transmitting higher video/audio data stream. In some researches of the BCC technology, high-level modulation is utilized to provide high bandwidth, which, however, consumes large amount of energy and is not suitable for mobile devices.
Therefore, there is a need to provide high data transmission rate utilizing the BCC technology with less power consumption.

Body channel communication method and device using a transmission mode according to interefence estimate


A data printer wherein a slip is dropped in a guide chute and a serially operable print head is moved along the length of the slip to print a line of characters. A line feed device comprises a drive gear meshing with a driven gear carrying a feed roller for frictionally advancing the slip from one print line position, extending parallel to the length of the slip, to the next. The driven gear is moveable about the axis of the drive gear and is forced into frictional engagement with the slip by the rotational force imparted to the driven gear by the drive gear.

I. Field of the Invention
This invention relates to data printers and has particular reference to a printer for printing a plurality of lines of print lengthwise on slips or forms.
II. Description of the Prior Art
In many business applications, records are made of transactions on slips which are given to a customer as a record of such transactions. For example, in banking transactions such a printed slip may be given to a depositor as a record of his deposit.
The U.S. Pat. Nos. 4,944,620, issued on Jul. 31, 1990 and 5,080,513, issued on Jan. 14, 1992, disclose and claim slip printers, each utilizing a serial printer head, preferably of the inkjet type. When a slip is dropped into a receiving chute, the print head is moved along the length of the slip to print a line of type characters. In some cases, the printer is also capable of printing a similar line of characters on a journal tape.
Such printers are compact, inexpensive and highly reliable. However, such printers are generally capable of printing only a single line of characters on each slip. This is of a disadvantage in cases where additional desirable data cannot be included in a single line of print.

Multi-line printer for slips or the like


The invention relates to an article of manufacture which includes a substrate, and on at least one surface thereof, a porous coating which has a total thickness in the range of up to about 50 microns and which consists of a plurality of discrete adjacent strata, wherein each discrete stratum is porous, inclusive of porous interfaces, and is fabricated from at least one substance selected from the group consisting of metals and metal oxides. The article is made by vaporizing a metal under vacuum conditions, optionally in an oxidizing atmosphere, at predetermined intervals of time, such that a deposit of a desired total thickness is formed on the substrate as a coating consisting of a plurality of discrete adjacent strata.

A capacitor is an electronic device which consists of two plates of electrically conductive material separated by an insulator. When introduced in an electrical circuit the plates are connected to a negative and a positive terminal of the current source, and therefore are called cathode and anode respectively.
An electrolytic capacitor is a capacitor in which one plate is metallic and the other plate is an electrolyte. Intervening between the two plates is a dielectric consisting of a surface oxide coating on the metal plate. Conventionally, the metal plate on which the dielectric coating is formed is referred to as the anode. The term "anode" is used herein to refer both to the metal plate itself and to a combination of the metal plate with the dielectric coating. It will be clear from the context which meaning of "anode" is intended. A transition between ionic conduction in the electrolyte and electronic conduction in an external circuit is provided by a second metal plate which is referred to herein as cathode. The anode and the cathode are referred to herein collectively as electrodes. Typically, the anode and the cathode are thin foils.
Typically also, the metal of the anode is a valve metal, i.e. a metal which, when oxidized, allows current to pass if used as cathode but opposes the flow of current when used as anode. Examples of valve metals include magnesium, thorium, cadmium, tungsten, tin, iron, silver, silicon, tantalum, titanium, aluminum, zirconium and niobium.
As is the case with capacitors generally, the capacitance of an electrolytic capacitor is proportional to the surface areas of its two plates. Conventionally, the surface areas of the foils are increased by etching. High purity valve metal foils are etched electrochemically in a chloride solution with DC, AC, or an alteration of DC and AC, or a concurring AC and DC. A disadvantage of electrochemical etching is that in the case of thin foils, it weakens the foil mechanically, making it difficult to fabricate electrolytic capacitors by high speed winding. Furthermore, the electrochemical etching results in acid waste and therefore is not environmentally friendly. Recently, vacuum deposition process has been proposed for increasing the surface areas of foil electrodes.
Kakinoki et al., in U.S. Pat. No. 4,970,626, disclose a method for producing an electrolytic capacitor comprising deposition of titanium onto an aluminum substrate in an atmosphere of argon, wherein the deposition occurs at a constant or gradually varied deposition angle. The disclosed method allows producing a coating with a rough column-like structure deposited onto the substrate, which can be used as a cathode of an electrolytic capacitor. In another embodiment, a two-stage deposition process is employed at different angles at each stage. The disadvantages of the disclosed method of increasing the surface area of a foil electrode include the additional cost of working with two metals and the decrease in stability associated with an intermetallic potential.
U.S. Pat. No. 4,309,810 (Drake) teaches vacuum deposition of a metal vapor, e.g. tantalum, at a low angle onto a foil substrate, e.g. aluminum, so as to produce a column-like structure. The deposition is carried out in presence of oxygen at a partial pressure not exceeding 10−4 Torr. In an embodiment, a small quantity of an inert gas is added to the oxygen. Drake's foil has been found to be too brittle for use in electrolytic capacitors: it breaks when it is rolled into a cylindrical roll, the standard shape of an electrolytic capacitor. A similar process for producing a column-like surface structure is disclosed in DE 4,127,743 (Neumann et al). Unlike the Drake process the deposition occurs at angles greater than 30°.
Allegret et al., in U.S. Pat. Nos. 5,431,971 and 5,482,743, disclose a process of evaporating aluminum in an oxidizing atmosphere under a pressure of 0.8 to 2.3 Pa, thereby depositing a mixture of aluminum and aluminum oxide. The deposited layer consists of grain agglomerates, forming a porous matrix of aluminum oxide containing metallic aluminum crystallites embedded randomly inside these grains. Such mixed Al/Al2O3 surfaces are more robust mechanically compared to pure aluminum surfaces; however electrolytic capacitors incorporating them are known to have relatively high resistive losses and relatively low stability over time. In addition, the presence of both aluminum and large quantities of aluminum oxide in the surface of the foil makes difficult and less effective both stabilization by subsequent conventional chemical or electrochemical treatments and structure coarsening by subsequent annealing.
U.S. Pat. No. 6,764,712 (Katsir, et al.) discloses a process for increasing the surface area of a metal substrate, comprising a reactive vacuum vapor deposition of valve metal onto a metal foil in an atmosphere mainly containing oxygen and an inert gas. The process can produce high surface area coatings with a fractal-like structure characterizing by cauliflower-like morphology, which may constitute a component of integrated electrolytic capacitors described in U.S. Pat. No. 6,865,071 (Katsir, et al.)
If the foil is intended to serve as an anode of an electrolytic capacitor, the step of increasing the surface must be followed by a step of oxidizing the surface to produce a thin oxide layer, conventionally by anodization. Patents in this art include U.S. Pat. No. 4,537,665 and U.S. Pat. No. 4,582,574 (Nguyen et al.), and U.S. Pat. No. 5,643,432 (Qiu). For cathode foils, in order to maintain capacity over time, the oxidizing step is necessary, and is also termed stabilizing passivation.
A printing page which comprises a substantially planar substrate and a porous vacuum deposited ungrained coating thereon is described and claimed in U.S. Publication No. 2006-0086273 A1 published on Apr. 27, 2006 (corresponding with the GB priority application No. 0421810.3) which has inventorship in common with the present patent application.
The entire contents of the above-mentioned US patents and published US patent application are incorporated herein by reference.

Electrodes, printing plate precursors and other articles including multi-strata porous coatings, and method for their manufacture


An optical imaging system includes a first lens, a second lens, a third lens including a concave object side surface, a fourth lens, a fifth lens, and a sixth lens sequentially disposed from an object side toward an image side. The optical imaging system satisfies 0.7<TL/f<1.0 and F No.<2.1, where TL is a distance from an object side of the first lens to an imaging plane, f is a total focal length of the optical imaging system, and F No. is the F No. of the optical imaging system.

The present disclosure relates to a telephoto optical imaging system comprised of six lenses.
A telephoto optical system capable of long-distance imaging has a considerable size. For example, a telephoto optical system has a ratio TL/f, of a total focal length f to a total length TL of the optical system, of 1 or more. Therefore, a telephoto optical system is difficult to mount in small electronic devices such as portable terminals, or the like. Further, with a telephoto optical system, it may be difficult to secure a sufficient amount of light incident on an imaging plane, such that it may be difficult to realize a low F No.


There is disclosed a phase locked loop comprising: a phase frequency detector for receiving as a first input a reference signal and for generating a control signal; a voltage controlled oscillator for receiving the control signal and for generating a signal defining an output frequency, a feedback path connecting the output signal to a second input of the phase frequency detector; and a digital accumulator for generating the reference signal under the control of an accumulator reference clock.

Frequency synthesisers are an integral part of any modern communications system, especially any coherent system dependent upon a steady phase difference between each element in the communication network.
Advancing technology has made possible the use of adaptive beam steering using multiple antennas to provide a focused beam between transmitter and receiver systems, allowing the dual benefits of increased cell capacity with increased rejection of interfering signals. The ability to adjust the output phase of the frequency under digital base-band control is particularly useful as it can reduce the component count used in a transmitter system. Similarly a system which can accurately provide a phase modulated radio frequency signal offers the potential for higher levels of component integration.
Reference is made to FIG. 1, which shows a known synthesiser generally designated by reference numeral 10.
The synthesiser 10 comprises a phase detector 2, a low-pass filter 4, voltage controlled oscillator (VCO) 6, a divider 8, and an optional integer "R" divider 12. A signal having a required output frequency is generated at the output of the VOC 6.
Essentially there are two variants to this type of synthesiser, employing either fixed integer dividers or modulated dividers, by a suitably adjusted data stream, which constantly adjusts the integer divider value in the divider 8. Modulated dividers are also known as fractional-N dividers. The parasitic modulation of the divider output signal is itself modulated by this modulated data stream to ensure the remainder of the phase locked loop can remove this parasitic modulation, whilst preserving the advantages it offers.
Both types of phase locked loops use a phase frequency detector 2, which is commonly a digital element, to compare a fed back voltage controlled oscillator output with an incoming reference signal, to which the system is phase locked. The output of the phase frequency detector 2 can be a series of either current or voltage pulses, which are filtered by the loop filter 4 to give a small error voltage. This small error voltage complements the voltage pedestal at the output of the loop filter, ensuring the VCO remains phase locked. The error voltage is the correction voltage supplied to the VCO, to suppress the excess phase noise of this device to levels determined by the phase locked loop dynamic characteristics. The VCO is the device controlled by this negative feed back closed loop system. To provide a frequency translation back to the phase frequency detector 2, for comparison with the reference signal, the series divider circuit is used. If fractional-n dividers are used, as shown in FIG. 1, their mean division value can be adjusted to give an effective multiplication of the reference signal, hence allowing the phase locked system to change to different frequencies with respect to the reference signal.
Digital dividers have the net effect of raising the phase noise of the system because their dividing action in the feed back path of the system translates to a multiplication of PFD related noise in the through transfer characteristic of the phase locked loop.
Arrangements using digital dividers in their feed-back path offer limited noise performance preventing their simple implementation in new, more demanding, communication system applications.
Single loop fractional-N techniques, described earlier, have been adapted to improve on divider limitations by raising the sampling frequency seen at the digital phase frequency detector input to reduce these division values. However, a point is reached where the sampling frequency approaches half the synthesiser's output frequency (for a minimum division value of 2). Beyond this point only another 3 dB of improvement might be possible, although this still does not guarantee that the resulting in-band phase noise becomes acceptable.
Also known is the use of phase locked loops employing a mixer as a frequency translation element, in order to improve the in-band phase noise using a combination of analogue phase locked loops and direct digital synthesisers. In an alternative PLL arrangement, a mixer arrangement is used in place of the divider 8. When mixers are used, additional signal sources are required to provide this frequency translation. Mixers do not raise the in-band phase noise levels, because their action is to subtract two signals in the feed back path, giving no change in phase at the mixer output, and hence no adverse effect to a system which tracks only phase. A phase locked loop using a mixer has a minimal multiplication of any spurious energy injected into the reference input.
The direct digital synthesisers provide the necessary frequency interpolation required for attaining the specified frequency steps at the phase locked loop output. Reference is made to the Qualcom application note AN2334-4, (1990) and U.S. Pat. Nos. 4,965,533, and 5,184,093 on the subject.
Alternatively the direct digital synthesiser is applied to the phase frequency detector input, with a consequent spurious degradation seen at the phase locked loop output.
A phase locked loop possesses a typical transfer characteristic of a band-pass system. This band-pass is filter characteristic is centred about the output VCO's signal, which at high frequencies (given the low loop bandwidths of the phase locked loop) represents a very high "Q" factor that cannot be achieved any other way.
The alternative to analogue phase locked loops, as described herein above, are direct digital synthesisers. Direct digital synthesisers are not phase locked systems, as they do not possess a feedback path between their output and inputs. They are capable of open loop operation because their all-digital nature guarantees repeatable outputs under all conditions. They do not suffer from the vagrancies of analogue systems. The basic concept of direct digital synthesisers remains unchanged from the original paper presenting the idea given in 1971. As shown in FIG. 2, a direct digital synthesiser 20 is built up of three components; a digital (phase) accumulator 14, a sine (or cosine) look-up table 16, and a digital to analogue converter (DAC) 18. External to the direct digital synthesiser 20 is an analogue low pass or band pass filter 22. A reference clock 24 clocks the digital accumulator 14 and the DAC 18.
The purpose of the digital accumulator 14 is to digitally integrate the digital input word provided on an input thereto, resulting in a ramp output at the required frequency. This defines the digital input word as a phase value equivalent to the phase difference over one accumulator clock period to give the required output frequency. Every time the accumulator overflows the "carry out" bit is ignored and the accumulator output re-starts it's integration sequence, giving an output word pattern resembling a ramp. The length of the digital accumulator 14 determines the phase resolution available for each accumulator clock cycle and hence the accuracy of the output frequency. Using this concept of phase increments, the required digital input word for a given output frequency can be calculated using the expression:
      Input                          Accumulator                          Word    =                    F        Required            ×              2                  Accumulator                                                              Length                            F              Accumulator                                                  Clock
In a practical system the length of the accumulator data word exceeds the resolution of the following sine look up table, therefore only the "P" most significant bits are fed into the sine look up table. The value of "P" depends upon the combined width of the sine look up table and any compression circuitry used to mirror and invert the output of the sine look-up table output. It is the function of the sine look-up table 16 to convert the truncated accumulator equivalent phase value to a digital equivalent amplitude value, using a sine or cosine transfer characteristic. This digital amplitude is converted into an analogue signal level using a digital to analogue converter 18 clocked at the same frequency as the digital accumulator 14. In some direct digital synthesiser designs additional pipelining circuitry may be added to overcome circuit settling times allowing higher frequencies of operation. There is no effect on the quality of the output signal, with such pipelining only a slight phase delay is incurred between a change in digital input to analogue output.
Direct digital synthesisers are comprised of all digital elements making them suitable for integration into a chip. However one major performance limitation is the digital-to-analogue converter at the output. This digital-to-analogue converter generates problems; reducing the spurious free dynamic range and raising the noise floor. To minimise these effects caused by sampling and aliasing during the digital-to-analogue converter operation, the passive reconstruction filter 22 is normally used to "clean-up" the signal before it is used in the remainder of the system it is employed to drive.
Direct digital synthesisers cannot operate at the required local oscillator frequencies of contemporary mobile communication systems with the necessary noise and spurious performance. Therefore in current known solutions direct digital synthesisers are combined with analogue or digital phase locked loop techniques, to perform the necessary up-conversion of their lower frequency signals.
As described hereinabove, any phase locked loop employing a digital divider in its feedback path possesses gain. Therefore any small direct digital synthesiser related spurious products would be subject to this gain, usually raising their level to unacceptable levels. Analogue loops using only a mixer in the feedback path have no such gain, giving a unity translation of input DDS spurious levels.
It is an aim of the present invention to provide a solution which overcomes the above-stated problems.


The present invention relates to a self-service gasoline pump system with game functions in which a plurality of gasoline dispensers or pumps are respectively provided with a game device, and the game devices are connected in parallel to each other and to a controller. While a dispenses gasoline, the game device performs a game automatically whenever a predetermined certain amount of gasoline or charge is reached, or manually whenever the user pushes a button for starting games, so as to offer premiums to the user according to game points. The game results are displayed under the control of the controller.

Conventionally, gasoline is pumped into automobiles by employees of gas stations in many countries and self-service has not been accepted yet due to rejection symptoms of users who are not familiar with operating the machines and due to the face-saving trends of users.
However, such self-service is has already widespread in many European countries and the need of acceptance of self-service increasing in many other countries in view of increase personnel expenses.
Therefore, motivation for users to pump gasoline themselves is increasing. The above-described conventional self-service gasoline dispenser will now be described in more detail with reference to FIG. 1.
FIG. 1 is an elevational view of a conventional self-service machine gasoline dispenser. As shown therein, the conventional self-lubricating gasoline dispenser includes a machine part 1 having a pump and a motor simply for the dispensing function, a hose and nozzle part 2, and a display part 3, so that only pumping of gasoline and metering dispensed amount and its cost are possible, which does not particularly interest users.

Self-service gasoline pump system with game function

108-202 Parktown, 52 Sunae-dong, Bundang-gu


A liquid crystal display apparatus includes a liquid crystal modulation element having a liquid crystal layer and first and second electrodes, and a controller performs control for an electric potential difference applied between the electrodes such that an electric field applied to the liquid crystal layer is inverted between positive and negative. The controller switches the control between first control and second control. The first control controls the electric potential difference such that one of an absolute value of a time-integrated value of the positive electric field applied to the liquid crystal layer and an absolute value of a time-integrated value of the negative electric field applied thereto is larger than the other, and the second control controls the electric potential difference such that the other absolute value of the time-integrated value is larger than the one absolute value of the time-integrated value.

The present invention relates to a liquid crystal display apparatus using a liquid crystal modulation element such as a liquid crystal projector and performing liquid crystal drive control such as overdrive for improving moving image display performance.
Some of the liquid crystal modulation elements (also called as liquid crystal display elements) are realized by sealing nematic liquid crystal having positive dielectric anisotropy between a first transparent substrate having a transparent electrode (common electrode) formed thereon and a second transparent substrate having a transparent electrode (pixel electrode) forming pixels, wiring, switching elements and the like formed thereon.
The liquid crystal modulation element is referred to as a Twisted Nematic (TN) liquid crystal modulation element in which the major axes of liquid crystal molecules are twisted by 90 degrees continuously between the two glass substrates. This liquid crystal modulation element is used as a transmissive liquid crystal modulation element. Some of the liquid crystal modulation elements utilize a circuit substrate having reflecting mirrors, wiring, switching elements and the like formed thereon instead of the abovementioned second transparent substrate. This is called a Vertical Aligned Nematic (VAN) liquid crystal modulation element in which the major axes of liquid crystal molecules are alignment in homeotropic alignment substantially perpendicularly to two substrates. The liquid crystal modulation element is used as a reflective liquid crystal modulation element.
In these liquid crystal modulation elements, typically, Electrically Controlled Birefringence (ECB) effect is used to provide retardation for a light wave passing through a liquid crystal layer to control the change of polarization of the light wave, thereby forming an image from the light.
In the liquid crystal modulation element, which utilizes the ECB effect to modulate the light intensity, application of an electric field to the liquid crystal layer moves ionic materials present in the liquid crystal layer. When a DC electric field is continuously applied to the liquid crystal layer, the ionic materials are pulled toward one of two opposite electrodes. Even when a constant voltage is applied to the electrodes, the electric field applied to the liquid crystal layer is cancelled out by the charged ions to substantially attenuate the electric field applied to the liquid crystal layer.
To avoid such a phenomenon, a line inversion drive method is typically employed in which the polarity of an applied electric field is reversed between positive and negative for each line of arranged pixels and is changed in a predetermined cycle such as 60 Hz or the like. In addition, a field inversion drive method is used in which the polarity of an applied electric field to all of arranged pixels is reversed between positive and negative in a predetermined cycle. Those drive methods can avoid the application of the electric field of only one polarity to the liquid crystal layer to prevent the unbalanced ions. This corresponds to controlling the effective electric field to be applied to the liquid crystal layer such that it always has the same value as the voltage to be applied to the electrodes.
So-called overdrive has been known as a drive method for the purpose of improving the display quality of the liquid crystal modulation element. In the overdrive, when the liquid crystal modulation element is driven so as to display a moving image whose tone (or tone value) changes with time, the tone values of two field images that are temporally continuous are compared. When the tone value increases, the liquid crystal modulation element is driven with an increased tone value that is higher than an original display tone value. When the tone value decreases on the other hand, the liquid crystal modulation element is driven with a decreased tone value that is lower than the original display tone value. The use of such overdrive as described above improves the response speed of the liquid crystal in a halftone (middle tone) display state, and thereby blur of a displayed moving image is reduced.
The overdrive of the liquid crystal modulation element has been disclosed in, for example, Japanese Patent Laid-Open No. 2001-034238 (Japanese Patent No. 3407698).
However, the overdrive to display the moving image on the liquid crystal modulation element for a long time results in application of a DC voltage component to a liquid crystal layer thereof in average. This is because the absolute values of liquid crystal applied electric fields (hereinafter also simply referred to as voltages) corresponding to positive and negative overdrive amounts in a certain tone are unbalanced.
For example, a case is assumed where a black display state and a certain halftone display state are cyclically switched. In this case, the voltage corresponding to a certain overdrive amount is applied to the liquid crystal layer in the switching from the black display state in which no voltage is applied to the liquid crystal layer to the halftone display state. On the other hand, the voltage corresponding to the overdrive amount is zero in the switching from the halftone display state to the black display state. When such unbalanced voltages applied to the liquid crystal layer are frequently caused in, for example, moving image display performed by continuously scanning a stripe pattern image, and then the voltage component corresponding to the difference of the unbalanced voltages is accumulated, the DC voltage component is applied to the liquid crystal layer.
In a conventional direct-view-type liquid crystal panel, line inversion drive is employed in which voltages having opposite polarities to each other are applied to each of adjacent lines of display electrodes formed in the liquid crystal modulation element as a countermeasure against the application of the DC voltage component to the liquid crystal layer. Alternatively, dot inversion drive is also employed where voltages having opposite polarities to each other are applied to each of adjacent pixels.
These drive methods can balance out the DC voltage components in the adjacent lines or pixels.
In a liquid crystal display apparatus such as an image projection apparatus using a micro display, however, the line inversion drive and the dot inversion drive cause an abnormal alignment of the liquid crystal which provides an adverse influence on a displayed image. To prevent this, the field inversion drive is recently used in which one field is driven with a single polarity. However, the field inversion drive cannot suppress the application of the DC voltage component to the liquid crystal layer in the overdrive.
Japanese Patent No. 3407698 has disclosed a method that appropriate selection of the material of the electrodes can solve a problem in which a so-called "stain" caused due to the application of the DC voltage component to the liquid crystal layer in the overdrive.
However, the problem caused by the application of the DC voltage component to the liquid crystal layer is not limited to the "stain" described in Japanese Patent No. 3407698. Specifically, burn-in or flicker is also caused. Thus, the application of the DC voltage component to the liquid crystal layer must be prevented essentially.


A programmable logic device (PLD) data transfer cable includes a parallel interface, a programming interface, and a logic control circuit. The parallel interface is used for connecting to PLDs. The logic control circuit includes a first group of transmission channels, a second group of transmission channels, a first group of switches, and a second group of switches. The first and second group of switches control the working status of the first and second group of transmission channels respectively. The electrical connections between pins of the parallel interface and the programming interface when first group of transmission channels are activated are different with those when second group of transmission channels are activated.

1. Field of the Invention
The present invention relates to a data transfer cable and, particularly, to a data transfer cable for programmable logic devices.
2. Description of the Related Art
When a programmable logic device (PLD) is programmed in-system, a data transfer cable is used for connecting a computer parallel interface with a programming interface of the PLD. The specifications of different PLDs are not the same. Thus, the data transfer cable must be changed for programming different PLDs, which increases cost and is inconvenient.
What is needed, therefore, is to provide a data transfer cable for PLDs which can amend the aforementioned deficiencies.

Data transfer cable for programmable logic devices

Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd.


A negative pressure air bearing slider includes a slider body for flying above a surface of a recording disc during relative rotation of the recording disc. First and second projections extend from a lead portion of a principal surface of the slider body to define first and second air bearing surfaces, respectively, the first and second air bearing surfaces being spaced apart from each other in the lateral direction of said slider body. A third U-shaped projection extends from the principal surface and includes a curved front wall portion at least partially located between the first and second projections and first and second side wall portions extending from opposite ends of the curved front wall portion to a rear portion of the principal surface so as to define a rounded negative pressure cavity therein.

1. Field of the Invention
The present invention relates to a magnetic disk drive device, and in particular, to a flying-type negative pressure air bearing slider for a transducer head assembly of a magnetic disk drive device.
2. Description of the Related Art
Transducer head assemblies have been designed to literally fly over a rapidly rotating disc, and include an air bearing slider for carrying a magnetic transducer proximate a rapidly rotating disc. The transducer, in the case of flying-type sliders, is a thin-film head or a magneto-resistive head.
In magnetic disk technologies, it is generally desired to achieve higher data recording densities without a substantial change in form factor. In the context of the air bearing slider, increased recording densities are obtainable by maintaining the flying height, pitch angle and roll angle constant over the whole disk surface, to thereby enhance floating stability and contact start stop (CSS) reliability.
On the one hand, the magnetic head must fly at a sufficient height to avoid frictionally related problems caused by physical contact during data communication between the magnetic head and the rapidly rotating disk. On the other hand, the head should be made to fly as low as possible to obtain the highest possible recording densities. As the magnetic head is fixed to the slider mechanism, the disk recording density increases as the flying height of the slider decreases. Accordingly, it is preferred that the slider fly as close as possible to the disk surface without actually contacting the disc surface. A constant flying height is preferably maintained, regardless of variations in tangential velocity during flying, cross movements of the slider during data search operations, and changes in skew angle in the case of rotary type actuators.
To achieve stable flying characteristics, the slider should also fly at a pitch angle that falls within a safe range of a predetermined value. The pitch angle is defined as the tilt angle between the principal plane of the slider in the tangential direction of the rotating disc and the principal plane of the disc surface. The pitch angle is positive in the normal case in which the flying height of the rear portion of the slider is lower than that of the front portion of the slider. A transducer is generally situated at the lowest position of the rear portion of the slider for maximizing recording data capacity. If the designed pitch angle is too small, the possibility exists that a disturbance will cause the front end of the slider dip down such that a negative pitch ensues resulting in a collision with the rapidly rotating disk. On the other hand, if the designed pitch angle is too large, the air stiffness needed for stable flying can be disadvantagously reduced. Therefore, to maintain stability while avoiding the situation of a negative pitch angle, the slider should be configured such that the pitch angle can be controlled to fall within an optimum value range. Another factor to consider regarding pitch angle is the general tendency for the pitch angle to increase with skew angle increases as the slider is positioned in a radially outward direction over the disc surface. Thus, the pitch angle should fall within the safe range regardless of skew angle variations.
Differing hydrodynamic forces support the inner and outer air bearing surface (ABS) rails of the slider, and resulting variations in side leakage air flow with skew angle changes can generate roll angle variations. Here, the inner and outer rails refer to those ABS rails of the slider positioned toward the inner periphery and outer periphery of the disc, respectively. Also, roll angle is defined as the tilt angle between the principal plane of the slider in the radial direction of the disc and the principal plane of the disc surface. The roll angle is positive in the normal case where the transducer is positioned closest to the rail which travels closest to the disc surface. During data read/write processing, the read/write transducer should be located at the lowest point of slider body relative to the radial direction of the disc surface, i.e., the roll angle should be positive, to thus maximize recording density. A positive and constant roll angle over the entire disk surface area is a key factor in maintaining a stable flying condition.
FIG. 1 is a schematic perspective view of a conventional tapered flat slider. In FIG. 1, two rails 11 a are formed in parallel at a predetermined height on a surface of a slim hexahedron body 10a to thus form lengthwise extending ABS's. A tapered or sloped portion 12a is formed at each leading edge portion of the ABS rails 11a. In such a structure, air within a very thin boundary layer rotates together with the rotation of the disk due to surface friction. When passing between the rotating disk and the slider, the air is compressed by the ramp 12a on the leading edge of the ABS 11a. This pressure creates a hydrodynamic lifting force at the ramp section which is sustained through the trailing edge of the ABS, thus allowing the slider to fly without contacting the disk surface.
The conventional slider of this type suffers a drawback in that the flying height, pitch angle and roll angle vary considerably according to the skew angle of the rotary type actuator, i.e., according to the radial position of the slider over the disc surface. For flying heights of 3.0 millionths of an inch and greater, minor height and tilt fluctuations in the slider do not generally affect the read/write operations of the disk. However, current-day standards require flying heights below 2.0 millionths of an inch. At such small flying heights, even minor variations in pole tip flying height can severely affect the reliability of the head read/write function of a hard disk drive.
An improved configuration aimed at countering flying height variations over the entire disc surface is the transverse pressure contour (TPC) slider, as described, for example, in U.S. Pat. No. 4,673,996. As shown in FIG. 2 herein, this slider is also characterized by ABS rails 11b formed on a slider body 10b, and ramp portions 12b formed at the leading edge of the ABS rails 11b. In addition, however, a step-down 111b is formed lengthwise on the both sides of each of the ABS rails 11b. The slider of this TPC structure has the advantage of maintaining reasonably constant flying height regardless of skew angle variations. However, this TPC slider exhibits reduce flying stability which is caused by insufficient air stiffness resulting in the reduction of the ABS surface area. Also, the TPC modification does not improve pitch and roll angle variations resulting from changes in skew angle.
In light of the above, to better realize a constant flying height and constant pitch and roll angles and to obtain an improve contact start stop (CSS) performance, most current air bearing sliders have adopted a negative pressure air bearing (NPAB) type of configuration with a variety of air bearing surface shape changes. A basic NPAB slider has the same structure of the slider shown in FIG. 1, together with a cross rail connecting the ABS rails. That is, as shown in FIG. 3, two ABS rails 11c each having a slope 12c at a leading edge thereof are formed in parallel on a surface of a body 10c. A cross rail 13c having the same height as the ABS rail 11c is formed between the rails 11c proximate the slopes 12c. The cross rail 13c creates a negative pressure cavity 14c in proximity to the central surface portion of the body 10c. Thus, since the pressure of the air passing over the cross rail is diffused as it passes the negative pressure cavity 14c, a pulling or suction force is downwardly applied on the slider which reduces suspension gram load and provides the advantage of a fast take off from the disc surface. The counter action between the positive and negative forces reduces the sensitivity of the slider flying height relative to disc velocity and increases the slider stiffness characteristics.
Because of sub-ambient pressure of cavity 14c, roll angle during a high skew condition can worsen, meaning that the NPAB slider of FIG. 3 exhibits more negative roll effects at high skew positions than the convention tapered flat slider of FIG. 1. Also, there is a tendency for debris to gather at the cross-rail 13c. Such debris can ultimately have an adverse effect on performance.

Flying-type negative pressure air bearing slider


An inspecting method increases the accuracy of a DSA (Defect Source Analysis) for thereby increasing the yield of semiconductor devices which are manufactured. For performing a DSA using data of a defect inspecting process obtained when wiring patterns are formed on a wafer and data of a VC (Voltage Contrast) inspecting process performed after the wiring patterns are formed, a rectangular DSA area is established in relation to a wiring pattern in which a nonconductive area is detected, based on the shape of the wiring pattern. For example, if three defects are detected in the defect inspecting process, then it is possible to select only at least one of those defects which affects the wiring pattern in the DSA area. Since fabrication steps can appropriately be evaluated based on the selected defect, suitable actions may be taken for any problematic fabrication step based on the evaluation of the fabrication steps.

(1) Field of the Invention
The present invention relates to an inspecting method, an inspecting apparatus, and a method of manufacturing semiconductor devices, and more particularly to a method of and an apparatus for inspecting samples such as wafers or the like for pattern defects, extraneous deposits, etc., and a method of manufacturing semiconductor devices, which includes a process of inspecting samples such as wafers or the like for pattern defects, extraneous deposits, etc.
(2) Description of the Related Art
In the field of the fabrication of semiconductor wafers, wafers are inspected at suitable stages for pattern defects, extraneous deposits, etc. (simply referred to as "defects") in an effort to provide a stable supply of high-quality semiconductor products.
At present, there have been employed various processes for inspecting samples for defects. Those processes include a dark field (DF) process for irradiating a sample surface with a laser beam and detecting scattered light therefrom, a bright field (BF) process for irradiating a sample surface with light and detecting reflected light therefrom, and a scanning electron microscope (SEM) process for irradiating a sample surface with an electron beam and detecting secondary electrons emitted from the sample surface. Heretofore, there have also been proposed a process of comparing an SEM-generated sample image with a given reference image and detecting any image difference as a defect, and a process of comparing an SEM-generated sample image with a given standard range and detecting an image area out of the standard range as a defect (for details, reference should be made to Japanese laid-open patent publication No. 9-312318).
Still another inspection process is known as a voltage contrast (VC) process for observing an SEM image of a produced wiring pattern for a potential state thereof to check if it suffers electrical defects such as disconnections or the like.
Although each of the various inspection processes referred to above may be carried out alone, it may be combined with another inspection scheme for higher defect detecting accuracy. It has also been attempted to perform a defect source analysis (DSA) on the results of inspections in a plurality of steps of a semiconductor device fabrication process for identifying any fabrication step that is responsible for a defect. If such a defect-causing fabrication step can be hunted down, then it is possible to take an appropriate action to correct the fabrication step for a higher semiconductor device yield.
However, some problems arise out of the DSA as described below.
A DSA using the results of a DF or BF inspecting process performed prior to the formation of a wiring pattern and the results of a VC inspecting process subsequent to the formation of the wiring process will be described below.
FIG. 10 of the accompanying drawings is illustrative of a conventional DSA.
For forming a TEG (Test Element Group) 101 shaped as shown in FIG. 10 on a wafer 100, fabrication steps of film growth, photolithography, and etching are performed prior to the formation of a combtoothed wiring pattern 102 and isolated wiring patterns 103 according to the Damascene process. After these fabrication steps are carried out, a DF or BF inspecting process is performed. Then, a wiring material is embedded and a CMP (Chemical Mechanical Polishing) process is performed, after which a VC inspecting process is performed.
FIG. 10 shows that three defects 104a, 104b, 104c are detected by the inspecting process performed prior to the formation of the combtoothed wiring pattern 102 and the isolated wiring patterns 103. Of these defects 104a, 104b, 104c, the defect 104a is present in the combtoothed wiring pattern 102 that is finally produced, and the defects 104b, 104c are present in areas other than the combtoothed wiring pattern 102 and the isolated wiring patterns 103 that are finally produced.
In the VC inspecting process performed subsequent to the formation of the combtoothed wiring pattern 102 and the isolated wiring patterns 103, an area (referred to as a VC inspection area) 105 including areas of the combtoothed wiring pattern 102 near its tip ends is observed based on an SEM image thereof while a certain voltage is being applied to the combtoothed wiring pattern 102. Since the potential in an area of the combtoothed wiring pattern 102 which is suffering a disconnection and the potential in an area of the combtoothed wiring pattern 102 which is suffering no disconnection differ from each other, secondary electrons emitted from these different areas have different levels of energy. Consequently, the SEM image of the VC inspection area 105 has a certain contrast difference. The VC inspecting process checks if there is a disconnection or the like or not based on the contrast information of the SEM image.
The VC inspection area 105 does not necessarily require to contain a defect a disconnection or the like therein. Even if a disconnection or the like exists at the base of a tooth of the combtoothed wiring pattern 102, the defect shows its influence on the tooth from the base up to its tip end in the VC inspecting process. Specifically, as shown in FIG. 10, the area extending from the defect 104a in the tooth of the combtoothed wiring pattern 102 to the tip end thereof shows a different level of contrast than the other area, and represents a nonconductive area 106. Actually, the defect 104a has caused the nonconductive area 106 to occur, and the fabrication step which has produced the defect 104a is responsible for the nonconductive area 106. The fact will be made clear by a DSA.
For performing a DSA using the data from the defect inspection prior to the formation of the wiring patterns and the data from the VC inspection subsequent to the formation of the wiring patterns, a circular DSA area 107 is established around the center at the center O of gravity of a nonconductive area 106a that is present in the VC inspection area 105, based on the pattern data of the TEG 101, the circular DSA area 107 being large enough to cover a relatively wide range of the TEG 101. The circular DSA area 107 thus established, however, is likely to reduce the accuracy of the DSA.
Specifically, though only the defect 104a is actually responsible for the occurrence of the nonconductive area 106 in the example shown in FIG. 10, the DSA counts all the defects 104a, 104b, 104c that are present in the DSA area 107 as being responsible for the occurrence of the nonconductive area 106. Even if the defect 104a, i.e., a killer defect, and the defects 104b, 104c, i.e., non-killer defects, are produced in different fabrication steps, the fabrication steps which have actually caused only the non-killer defects to occur are regarded as fabrication steps that have produced killer defects. As a result, the defect-producing fabrication step cannot accurately be identified.
Furthermore, if all the defects 104a, 104b, 104c in the DSA area 107 are regarded as having caused the nonconductive area 106 regardless of the types of those defects 104a, 104b, 104c, then it may become impossible to determine whether the nonconductive area 106 has been caused by an extraneous deposit or a pattern void. This failure is applicable irrespective of whether the defects 104a, 104b, 104c in the DSA area 107 are produced in respective different fabrication steps or in the same fabrication step.

Defect source analysis method, defect source analysis apparatus, and method of manufacturing semiconductor device


This invention concerns an intraocular artificial lens with variable optical power which lens is comprised of two optical elements which can be shifted relatively to each other in a direction perpendicular to the optical axis wherein the optical elements have such a shape that they exhibit, in combination, different optical powers at different relative positions and positioning means for positioning the optical elements in the eye and driving means for at least one of the optical elements to execute a movement relative to the other optical element and whereby the positioning means provide for forcing the optical elements to a resting position.

1. Field of the Invention
This invention concerns an intraocular artificial lens with variable optical power comprising two optical elements mutually shiftable in a direction perpendicular to the optical axis wherein the optical elements have such a shape that they exhibit, in combination, different optical powers at different relative positions and comprising positioning means for positioning the optical elements in the eye and driving means for driving at least one of the optical elements to execute a movement relative to the other optical element.
2. Description of the Prior Art
Such a intraocular lens has been also described in the Dutch patent application 1025622.
The ciliary body of the eye of which the ciliary muscle forms a part is positioned just behind the iris and in front of the vitreous body of the eye. In the resting position the ciliary muscle has a relative large diameter and when contracting it contracts to a muscle with a smaller diameter. This muscle drives the accommodative function. The capsular bag is positioned within the ciliary muscle and the natural flexible lens of the eye is positioned in the capsular bag. The capsular bag is connected to the ciliary muscle by zonulea extending substantially radially.
The natural accommodation of the eye with a natural lens occurs as follows. During distant viewing the ciliary muscle is relaxed and has a relatively large diameter. Thus a pulling force is applied on the zonulae stretching the capsular bag resulting in a relatively flat lens. The natural state of the ciliary muscle results in distant viewing. The ciliary muscle contracts at distant viewing resulting in a smaller diameter. The zonulae relax and the natural lens resumes its natural more concave shape.

Construction of an intraocular artificial lens


Molten glass is press-molded by a metallic die in which a cylindrical body is provided in a vertically standing manner at a central part of a bottom surface of a bottomed hole and a molding surface corresponding to a chamfering shape of an outer peripheral edge surface of a glass substrate is consecutively formed in an inner peripheral wall, and a glass substrate precursor provided with the chamfering shape axially consecutive on an outer peripheral surface thereof and a through hole formed at a central part thereof is thereby formed. The glass substrate precursor is cut perpendicular to an axial direction to be separated into respective glass substrates. Next, the respective glass substrates are subjected to a lapping process and a polishing process, if necessary, to produce a glass substrate as a final product. According to the manufacturing method, a glass substrate for information recording medium whose inner and outer peripheral edge surfaces are chamfered can be manufactured with an improved efficiency. Further, a glass substrate having a small diameter can be manufactured with a high efficiency.

1. Field of the Invention
The present invention relates to a method of manufacturing a glass substrate for an information recording medium (hereinafier, may simply referred to as "glass substrate"), in which at least one of an inner peripheral edge surface and an outer peripheral edge surface has a chamfered shape.
2. Description of the Related Art
A generally called "hard disk" is used as an information recording medium capable of writing and reading a large volume of information at a high speed, and as a substrate used of the hard disk, a glass substrate superior in evenness, hardness and the like has been more often used in recent years in place of a conventional aluminum substrate. FIG. 1 shows respective steps in a conventional method of manufacturing the glass substrate (for example, U.S. Publication 2003/0134734).
First, a glass material is melted (glass melting step), and the molten glass is cast into a lower die and pressed by an upper die to be molded (press-molding step). In the press-molding step, a method shown in FIG. 2 is generally adopted. As shown in FIGS. 2(a)-(c), molten glass 3 is press-molded in a predetermined thickness by an upper die 11 and a lower die 12 comprising a molding surface having a plane shape. For reference, an outer diameter regulating frame having a ring shape for regulating an outer diameter of the glass substrate may be interposed between the upper die and the lower die so as to regulate an outer diameter of a molded glass substrate precursor 13.
The press-molded glass substrate precursor 13 is crystallized or annealed and cooled down (crystallizing step or annealing step). In the cooled-down glass substrate precursor 13, a hole is formed at a central part thereof, if necessary, by a core drill or the like (coring step). Then, in a first lapping step, both surfaces of the glass substrate are lapped so that a general shape of the glass substrate, that is parallelism, flatness, and thickness of the glass substrate, is preliminarily adjusted. Next, an outer peripheral edge surface and an inner peripheral edge surface of the glass substrate are ground and chamfered so that a dimension of the outer diameter and circularity of the glass substrate, a dimension of an inner diameter of the hole, and concentricity between the glass substrate and the hole (inner/outer diameter high-precision processing step) are fine-adjusted. After that, the outer and inner peripheral edge surfaces of the glass substrate are polished so as to remove fine flaws and the like thereon (periphery edge surface polishing step). Next, both surfaces of the glass substrate are lapped again so that the parallelism, flatness and thickness of the glass substrate are fine-adjusted (second lapping process). Then, the both surfaces of the glass substrate are polished so as to remove any undulation on the surfaces (polishing step). The both surfaces of the glass substrate are further polished, if necessary, by an abrasive material having a different grain size (second polishing step). Finally, the glass substrate is washed and examined, and shipped as a glass substrate for hard disk.
As described, according to the conventionally employed method, for example, the two steps, which are the lapping/polishing step and the polishing step, are required for processing the inner and outer peripheral surfaces. As a result, the manufacturing steps are increased, which complicates the overall process and deteriorates a manufacturing efficiency. Further, devices in which the hard disk substrate is installed are increasingly reduced in size and weight, in response to which the diameter of the glass substrate is also being reduced. In order to manufacture the glass substrate having a reduced diameter, however, it is necessary to downsize manufacturing jigs used in the process in comparison to the conventional method, for example, reducing a diameter of the core drill for forming the central hole, as a result of which the work process is complicated. Therefore, the manufacturing efficiency unavoidably deteriorates in the conventional manufacturing method.

Method of manufacturing glass substrate for information recording medium


A multi-domain alignment liquid crystal display device in which liquid crystal molecules are aligned through a simple process and panel gap is maintained in stable fashion includes a first plate having a thin-film transistor provided at each point of intersection of a scanning line and signal line, a pixel electrode connected to the thin-film transistor and a first orientation layer formed on the pixel electrode and defining a curved surface, and a second plate having RGB color layers, an counterelectrode provided so as to oppose the pixel electrode, and a second orientation layer. A columnar spacer for regulating the panel gap is provided between the two opposing plates, and liquid crystal is sandwiched between the two plates and subjected to multi-domain alignment by the first orientation layer having the curved surface and the columnar spacer.

Widely known examples of liquid crystal display devices include those of the twisted nematic (TN) type and those which employ electrically-controlled birefringence (ECB). However, a problem with these conventional devices is that since the alignments of the liquid crystal molecules aligning under application of a voltage are uniform within a pixel, tonality differs depending upon the angle of view. A technique (multi-domain alignment) through which the directions of alignment of liquid crystal molecules in a single pixel are made to differ is available as a method of improving upon the visual-angle characteristic. With a liquid crystal device of this kind, the visual-angle characteristics of the multi-domains compensate for each other, as a result of which the characteristic is improved.
Multi-domain alignment methods are described in the specifications of Japanese Patent Kokai Publication JP-A-Nos. 7-318940, 8-292423, 9-80399, 9-304757 and 9-21913. These examples of the prior art place surrounding walls about a pixel and regulate the alignment of the wall surfaces to thereby realize an alignment that is symmetrical with respect to an axis perpendicular to a plate (substrate) at the center of the area surrounded by the walls. Multi-domain alignment is achieved as a result. Alternatively, protruding and recessed portions having axial symmetry with respect to the above-mentioned axis of symmetry are formed to correspond to the pixel, whereby similar multi-domain alignment is achieved. The art set forth in the specification of Japanese Patent Kokai Publication JP-A-8-292423 will be described with reference to FIG. 6. FIG. 6 is a sectional view showing one pixel of a conventional liquid crystal display device. As shown in FIG. 6, walls 23, 24 each comprising a resist or the like are formed on a plate 1 so as to surround a pixel electrode 22, and a recessed portion 25 consisting of a resist film is formed between the walls 23 and 24. A counterelectrode 26 is provided on a plate 2 on the opposite side of the device, and a projecting portion 27 is formed on the counterelectrode 26. The plates 1, 2 are arranged to oppose each other in such a manner that the recessed and projecting portions 25, 26 will have common axes of symmetry. If the gap between the plates 1, 2 is filled with a mixture of at least liquid crystal and a hardening resin and the liquid crystal and hardening resin are caused to undergo phase separation, a liquid crystal area will develop in such a manner that the liquid crystal precipitates in the recess 25 or surrounds the protrusion 27. When this occurs, the liquid crystal molecules in the vicinity of the recess 25 or in the vicinity of the protrusion 27 become oriented with axial symmetry, such as in radiating form or in the form of concentric circles, with the axis being perpendicular to the plates.

Liquid crystal display device with curved alignment surface


According to an example aspect of the present invention, there is provided an apparatus comprising a receiver configured to receive, from a first node, an indication of privacy preference and, from a second node, an indication relating to an accuracy at which the second node can determine a location of the first node (510), and at least one processing core configured to determine routing information based at least in part on the indication of privacy preference and the indication relating to the accuracy (520).

In wireless networks, mobile devices may communicate with base stations, or access points. In cellular networks, base stations comprised in radio access networks are configured to provide wireless access to mobile or non-mobile devices, such as cellular telephones, smartphones, tablet devices and other cellular-enabled devices. Examples of cellular networks include global system for mobile communication, GSM, wideband code division multiple access, WCDMA, long term evolution, LTE, and CDMA2000. In non-cellular systems, an access point may be configured to provide access to mobile or non-mobile devices. Access points may be connected to Internet routers, or to network nodes controlling the access points. An example of a non-cellular technology is wireless local area network, WLAN.
In addition to, or alternatively to, communicating with a base station or access point, devices may be arranged to communicate with each other directly. Such direct communication is known as device-to-device, D2D, communication. In detail, D2D communication comprises that devices, such as for example mobile devices, communicate with each other wirelessly such that electromagnetic signals transmitted by a first device are received in a second device, without the electromagnetic signals being re-transmitted along the way. In other words, a D2D communication link does not traverse any node along the D2D communication path that connects the D2D-communicating devices. For D2D communication to succeed, the participating devices need to be within communication range of each other.
In Wi-Fi Direct, a mobile device may assume, at least in part, the role of an access point, enabling further mobile devices to communicate with this mobile device. Wireless networks with single D2D wireless links may be referred to as single-hop ad hoc networks. An ad hoc network may comprise, for example, a network wherein network nodes have equal status and are free to associate with other network nodes in link range. Where D2D wireless links can be chained between several participating devices, the network may be referred to as a multi-hop ad hoc network. Wi-Fi 802.11 can support an ad-hoc mode which enables multi-hop ad hoc networking among a plurality of mobile devices. In general where devices engage in D2D communication with each other, this group of devices forms an ad hoc network. For example, a group of mobile devices may engage in D2D communication with each other, thus forming an ad hoc network.
In LTE networks D2D communications are presented as proximity services, ProSe. ProSe in LTE has two main aspects, firstly, ProSe discovery wherein it is established that two or more ProSe-enabled mobile devices are nearby, and, secondly, ProSe direct communication wherein the network facilitates establishment of D2D communication between the discovered ProSe-enabled mobile devices.


An electronic control unit comprises at least one controller and at least one memory device, wherein the controller comprises at least one electronic component mounted on a main circuit board. An embedded circuit board is formed in one piece with the main circuit board, and a predetermined separation line is provided for separating the embedded circuit board from the main circuit board.

Electronic control units (ECUs) are used in various automotive applications. For storing data of the controller they usually comprise non-volatile memory devices which currently are distributed either as chip package form factor or as module form factor devices.
Memory devices in chip package form factor contain all necessary electronics to access data which has previously been stored in this device. Said memory devices are commonly soldered to a printed circuit board (PCB) of the ECU, thereby being permanently affixed to it. Thereby, all connections between the memory device chip package are realized using the PCB and are permanent in nature. By realizing the electrical connection between the PCB and the memory device chip package, also a mechanical connection is realized. Due to the rugged electrical and mechanical connection between the memory device chip package without any movable part, the memory device chip package can be used in high-vibration environments.
Memory devices in module form factor follow a different approach. The memory device module uses a carrier material, like for example PCB material, which mechanically holds together several different components, which are needed to implement the desired data access mechanisms. The carrier material mechanically fixes the different components, keeps them together and often realizes the electrical interconnections as well. The memory device module is employed in an electrical system of larger scope. Electrical connections between the memory device module and a controller are realized using a pre-defined electro-mechanical connector standard enabling a separable and non-permanent electrical connection. Thereby, the memory device module can be electrically and mechanically separated from the ECU using the connector. By using a pre-defined connector standard, disconnection of the memory device module from the controller and connection of this memory device module to a read-out system for retrieving data is easily possible.
Both variants of non-volatile memory devices have some inherent limitations.
Memory devices in chip package form factor can only be accessed from that device, which they are soldered to. Moreover, memory device chip packages can only economically be used when no second physical entity may require to read from or write to the memory device. This is due to the high effort that is required to remove the memory device chip package from the original system by desoldering, and to insert it into another, identical or different system by resoldering. Thereby, removal of the memory device chip package is only possible using specialized equipment, like reflow ovens, hot air tools and the like, if the function of the memory device chip package needs to be kept. Removal of a memory device chip package is therefore often costly and a time-consuming process. Additionally, specialized readout circuitry is needed to access the data of the memory device chip package.
Memory devices in module form factor on the other hand suffer from inherent problems of electro-mechanical connections. In an environment with vibrations, springy metal contacts that make contact to their mating counterparts within a plug-socket part of a connector may vibrate, causing intermittent electrical connections. This constitutes a fundamental issue of all electro-mechanical separable connections and therefore cannot be solved by different contact forms or arrangements. These spring-loaded metal tabs or tongues will move and vibrate once agitated by external periodic movement, especially at their eigenmode. Movement of these metal tabs causes minimal breakups of the electrical connection, rendering the entire connection apparatus unusable for high power due to micro arcing or high speed signals due to missed bits or spurious extra level changes.
Accordingly, there is a need for an electronic control unit comprising a controller a memory device which is very vibration-resilient to be used in high-vibration environments and which is easily removable from the controller to be accessible for a read-out of data stored in the memory device.