Command sequences that form a meaningful unit in terms of syntax are integrated into drawing and environment contents corresponding to the type of command. Clusters are formed from the drawing contents and the environment contents required to process those drawing contents, and the clusters are assigned to processors, respectively. The assignment of the clusters to the processors is carried out on the basis of drawing loads and the efficient distribution of resource information. The processing results of the processors are recovered in the order in which the command sequences are produced, whereby the completeness of an image is assured.

1. Field of the Invention
The present invention relates to a print processing system and method which produce printed output by processing the print information described in print languages, such as page-description languages, using a plurality of image forming units.
2. Description of the Related Art
As development of a print system suitable for use in high-speed digital printing operations such as electrophotography or ink-jet printing operations, a print control scheme that breaks from conventional textual-information-oriented printing, that deals with images, graphics, characters, or the like, in the same manner, and that uses "page-description languages" capable of freely controlling the enlargement, reduction, rotation, and deformation of characters or graphics has achieved widespread use. Various page-description languages were developed during the 1980s. PostScript (a registered trademark of Adobe Systems in U.S.) and Interpress (a registered trademark of Xerox Corporation in U.S.) are representatives of the page-description languages. Various printers employ many page-description languages.
In a conventional page-description language processing print system, the central processing unit (CPU) of the print system sequentially interprets a page-description language, whereby a printer of the print system executes a printing operation. One example of the conventional page-description language processing print systems is disclosed in Unexamined Japanese Patent Application No. Hei 1-188374. The conventional page-description language processing print system is provided with a storage device that receives and stores a program for printing purposes (hereinafter referred to as print information) fed from a computer (hereinafter referred to as a host computer), a processor for sequentially interpreting that information, and a printing apparatus for executing a printing operation according to the thus-interpreted print information. After the print information has been transmitted from the host computer to the printing apparatus, the printing apparatus translates the print information and carries out a printing operation, whereby the load on the host computer is relieved. In consequence, the possessing speed of the overall print system is improved.
The sharing of a printing apparatus is standard practice in a decentralized network environment. Such a printing apparatus receives print requests from many host computers and must interpret and execute the print information described in a page-description language. Where many host computers concurrently use that printing apparatus, the printing apparatus serially interprets and executes the print information described in the page-description language, which results in a longer wait time elapsing between requesting and receiving print output.
To solve the foregoing problem and process print information at high speed, several techniques have been proposed: for example, a multiprocessing print processing system (see, e.g., Unexamined Japanese Patent Application No. Hei 4-128068) that interprets and executes print information in a parallel manner by use of a plurality of processors which are tightly coupled through a bus, or a print processing system (see, e.g., U.S. Pat. No. 5,333,246) that interprets and executes print information in a parallel manner by means of a decentralized network consisting of a plurality of loosely-coupled processors.
In the print processing system disclosed in Unexamined Japanese Patent Application No. Hei 4-128068, a special processing is not carried out with regard to the division of print information in order to interpret and execute the print information in a parallel manner. The print information is simply split page by page. In the case of the print information whose print job consists of a plurality of pages, a processing time is reduced. However, in the case of the print information whose print comprises only one page, the effect of reducing the processing time is not achieved.
In the print processing system disclosed in U.S. Pat. No. 5,333,246, the overlap between images is detected with regard to the division of the print information in order to interpret and execute the print information in a parallel manner. The print information is split on "an image group basis which does not affect another image even if that image group is separated from the print information". The thus-split print information is subjected to parallel processing. In this case, even in the case of the print information whose print job consists of one page, the effect of reducing the processing time is achieved. Since the processing is executed on a split-image group basis, the time required to carry out the processing will become a bottleneck if some of the plurality of split image groups are very complicated, for example, if they comprise overlapping images. As a result, the processing time of the entire page is not frequently reduced.
Neither the technique disclosed in Unexamined Japanese Patent Publication No. Hei 4-128068 nor the technique disclosed in U.S. Pat. No. 5,333,246 takes into consideration the efficient arrangement of the resources necessary for the print information. Specifically, in the case where the processing of print information is shared between the plurality of print information processing apparatuses, many print processing apparatuses respectively hold the resource information required to carry out raster graphics processing of the print information such as font information. The holding of the same resource information of the print processing apparatuses in an overlapped manner results in considerable overhead in the print processing system, as is the case of memory locations, processing costs, and transmission costs. In an extreme case, as a result of the overhead, the parallel processing carried out by a plurality of print information processing apparatuses may become inferior to the ordinary processing carried out by a single print information processing apparatus. For this reason, the effect resulting from high-speed parallel processing will not be achieved unless the efficient arrangement of the resources required to print the print information is not taken into consideration.


A game of catch is enhanced by the provision of a special glove and football. The glove is symmetrical so that it can be worn on either the right hand or the left hand and is formed from a close fitting elastic fabric. One part of a hook and loop fastener is attached to the glove while a complimentary part of the hook and loop fastener is attached to the football. The fasteners are disposed on the glove in a preferred pattern which provides a large area of contact without inhibiting the flexibility of the glove. The fasteners are attached to the football in a preferred configuration which completely covers the end sections of the football while leaving the central section of the football with spaced fasteners facilitating the grasping and throwing of the football.

1. Field of the Invention
This invention relates generally to apparatus useful in a game of catch and more specifically to a glove and ball provided mutually attractive materials facilitating the game of catch.
2. Discussion of Prior Art
In the past, various mitt and ball combinations have been provided with hook and loop materials which facilitate catching the ball with the mitt. Where the hook and loop material has completely covered the mitt, is has provided the mitt with relatively rigid characteristics which make it difficult for the user to bend his or her hand while catching the ball. Where the hook and loop material has only been disposed in certain areas of the mitt, the mitts have not had a symmetrical configuration permitting use on either the right or left hand of the user. These mitts have not been formed from close fitting, elastic material; as a consequence, they have been less responsive to articulation of the user's hand.
Balls adapted for this game of catch have typically had spherical configurations. Where footballs have been contemplated, the hook and loop material has been provided in widely separated longitudinal strips extending across the central section of the football. Since footballs are thrown with their end sections leading, the absence of velcro over their end sections has made this type of ball particularly difficult to catch with a mitt.

Glove and ball facilitating a game of catch


A DRAM providing a capacitor capacity sufficient for maintaining stable storage of data even if elements are further reduced in size in accordance with high density integration of semiconductor devices is disclosed. The DRAM has its capacitor upper electrode formed of an upper layer and a lower layer, and its capacitor lower electrode formed to surround the lower layer of the capacitor upper layer, and the upper layer of the capacitor upper layer formed to cover the upper surface and both sides of the capacitor lower electrode. Thus, a capacitor capacity is tremendously increased as compared to a conventional one in the same plane area as the conventional one.

1. Field of the Invention
The present invention relates generally to semiconductor devices and methods of manufacturing thereof, and more specifically, to a structure of a DRAM (Dynamic Random Access Memory) and a method of manufacturing thereof.
2. Description of the Background Art
Conventionally, demands for semiconductor memory devices have expanded rapidly with information equipments coming into wide use. Furthermore, there exists a demand for a device having a large storage capacity and capable of high speed operation. Accordingly, recent development is under way on semiconductor devices in relation to high density integration, high speed response, and high reliability.
Among various semiconductor memory devices, a DRAM is known as allowing random input and output of storage information. A DRAM generally includes a memory cell array portion which is a storage region in which a plurality of pieces of information are stored, and peripheral circuitry necessary for external input and output. FIG. 68 is a block diagram showing a general structure of a DRAM. Referring to FIG. 68, a DRAM 150 includes a memory cell array 151 for storing a data signal of storage information, a row and column address buffer 152 for receiving an external address signal to select a memory cell constituting a unit storage circuit, a row decoder 153 and a column decoder 154 for designating the memory cell by decoding the address signal, a sense refresh amplifier 155 for amplifying a signal stored in the designated memory cell and reading out the signal, a data in buffer 156 and a data out buffer 157 for inputting and outputting data, and a clock generator 158 for generating a clock signal.
Memory cell array 151 which occupies a large area on a semiconductor chip has a plurality of memory cells in a matrix for storing unit storage information. More specifically, a memory cell is usually formed of an MOS transistor and a capacitor connected thereto. The memory cell is widely known as a memory cell of 1 transistor per 1 capacitor type. A memory cell of such a structure is advantageous for increasing the integration density of a memory cell array for its simple structure, and, therefore, widely used for a DRAM of a large capacity.
Memory cells for DRAMs can be divided into several types due to the structures of their capacitors. Among them, a stacked type capacitor can increase the capacity of a capacitor by increasing the facing area between the electrodes of capacitors by extending the essential part of the capacitor over a gate electrode or a field oxide film. The stacked type capacitor with such a feature, can secure the capacity of the capacitor even when devices are reduced in size due to an increasing integration density of a semiconductor device. As a result, with high density integration of semiconductor devices, more stacked type capacitors have been used. These capacitors are for example disclosed in U.S. Pat. No. 4,907,046.
FIG. 69 is a cross sectional view of a structure of a DRAM including a conventional stacked type capacitor. Referring to FIG. 69, the conventional DRAM includes a P type silicon substrate 201, a field oxide film 202 for isolating elements formed in a prescribed region on the main surface of P type silicon substrate 201, source/drain regions 203a and 203b formed a prescribed distance apart from each other with a channel region 214 therebetween in an active region surrounded by field oxide film 202, a gate electrode 205 formed on a channel region 214 with a gate oxide film 204 therebetween, an interlayer insulating film 206 formed covering gate electrode 205, a capacitor lower electrode 207 electrically connected to source/drain region 203a and formed extending on the upper part of gate electrode 205 with interlayer insulating film 206 therebetween, a capacitor insulating film 208 formed covering capacitor lower electrode 207, a capacitor upper electrode 209 formed covering capacitor insulating film 208, an interlayer insulating film 210 having a contact hole 210a on source/drain region 203b, a bit line 211 electrically connected to source/drain region 203b in contact hole 210a and extending along the surface of interlayer insulating film 210, an interlayer insulating film 212 formed covering bit line 211 and having its surface planarized, and an aluminum interconnection 213 formed on interlayer insulating film 212 and corresponding to gate electrode 205. Capacitor lower electrode 207 and capacitor upper electrode 209 are formed of polysilicon. Bit line 211 is formed of an aluminum film. Capacitor insulating film 208 is formed of a silicon oxide film.
A pair of source/drain regions 203a and 203b, and gate electrode 205 constitute the transfer gate transistor of a memory cell. Capacitor lower electrode 207, capacitor insulating film 208, and capacitor upper electrode 209 constitute a stacked type capacitor for storing charge corresponding to a data signal.
In a writing operation, charge corresponding to a data signal is transferred to source/drain region 203b through bit line 211. Applying a prescribed voltage to gate electrode 205 turns on the transfer gate transistor. Thus, the charge transferred to source/drain region 203b is further transferred to capacitor lower electrode 207 through channel region 214 and source/drain region 203a. As a result, the charge corresponding to the data signal is stored in the capacitor.
In a reading operation, applying a prescribed voltage to gate electrode 205 turns on the transfer gate transistor. Thus, charge stored in the capacitor is transferred to source/drain region 203b through source/drain region 203a and channel region 214. The charge transferred to source/drain region 203b is read out externally through bit line 211.
FIGS. 70-78 are cross-sectional views for use in illustration of a manufacturing process (from a first step to a ninth step) of the conventional DRAM shown in Fig. 69. Referring to FIGS. 69 and 70-78, a description of a manufacturing process of the conventional DRAM follows.
Now, as shown in FIG. 70, field oxide film 202 for element isolation is formed in a prescribed region on the main surface of P type silicon substrate 201 by means of thermal oxidation. A gate oxide film layer (not shown) is formed by means of thermal oxidation, and a polysilicon layer (not shown) is formed on the gate oxide film layer by chemical vapor deposition. Gate oxide film 204 and gate electrode 205 are formed by means of photolithography and etching techniques. Source/drain regions 203a and 203b are formed by implanting ions using gate electrode 205 as mask. Interlayer insulating film 206 covering gate electrode 205 is formed by means of chemical vapor deposition or the like.
As shown in FIG. 71, a polysilicon layer 207a is formed by means of CVD on the entire surface.
Then, as shown in FIG. 72, using photolithography and etching techniques, polysilicon layer 207a (see FIG. 71) is patterned to form capacitor lower electrode 207.
Then, as shown in FIG. 73, silicon oxide film (capacitor insulating film) 208 is formed on the surface of capacitor lower electrode 207 by means of thermal oxidation.
Then, as shown in FIG. 74, polysilicon layer 209a is formed by chemical vapor deposition. Using photolithography and etching techniques, polysilicon layer 209a is patterned to form capacitor upper electrode 209 as shown in FIG. 75.
As shown in FIG. 76, interlayer insulating film 210 is formed by chemical vapor deposition. Then, as shown in FIG. 77, using the photolithography and etching techniques, contact hole 210a is formed in interlayer insulating film 210. Thus, the surface of source/drain region 203b is exposed.
As shown in FIG. 78, an aluminum film to be a bit line is formed to be electrically connected to source/drain region 203b by sputtering.
Finally, as shown in FIG. 69, interlayer insulating film 212 is formed on bit line 211. The surface of interlayer insulating film 212 is a planarized by reflow process. Then, aluminum interconnection 213 is formed on interlayer insulating film 212 corresponding to gate electrode 205. Thus, the DRAM having the conventional stacked type capacitor is completed.
As described above, conventionally, in order to secure a certain capacity of a capacitor even when elements are reduced in size due to an increased integration of semiconductor device, stacked type capacitors having a structure shown in FIG. 69 are used.
The structure of FIG. 69 however makes it difficult to secure a certain capacity of a capacitor with further down scaling of elements. More specifically, when the elements are further reduced in size, in the structure shown in FIG. 69, the facing area between capacitor lower electrode 207 and capacitor upper electrode 209 decreases. It is therefore difficult to secure a sufficient capacity of a capacitor for maintaining stable storage of data as the capacity of the capacitor is reduced and the elements are further reduced in size.

Semiconductor device having stacked type capacitor


A hoist trolley assembly includes first and second hoist trolleys, electric motors to drive the trolleys and a control system. The control system receives a preliminary speed reference for the trolleys and forms a final speed reference for the first hoist trolley by using initial data including the preliminary speed reference. The control system is adapted to use a hoist trolley coefficient Krb that is calculated by

The invention relates to a hoist trolley assembly.
It is sometimes necessary to add to a hoist trolley assembly an auxiliary lifting apparatus with a faster lifting rate but a lower lifting capacity than that of the main lifting apparatus. One way of doing this is to place two lifting machines into the same hoist trolley. This is expensive and requires a special hoist trolley designed for two lifting machines. Alternatively, the auxiliary lifting apparatus may be placed in a separate hoist trolley with no drive equipment. This separate hoist trolley is then connected mechanically to the main hoist trolley. This solution is expensive and manufacturing-wise poor, because its implementation requires special parts designed exactly for this purpose. In addition, the order in which the main hoist trolley and the auxiliary hoist trolley without drive equipment are placed on their travel route affects the power supply implementation of the hoist trolleys that is difficult to alter.
The auxiliary lifting apparatus with a smaller lifting capacity may also be placed in a hoist trolley having its own drive equipment. A situation where the auxiliary hoist trolley carries a heavy load generates a problem in this arrangement. When the torques of the hoist trolley motors are of equal size, the friction of the main hoist trolley wheels is not necessarily enough, and they may start to slip. Slipping may damage both the wheel and the carrier of the wheel, which may be a rail, for instance. In addition any position measurement information is lost, if the position measurement sensor is connected to the slipping wheel.

Abstract: k      rb        =                            T          A_nom                          T          B_nom                    ·                        v          B_nom                          v          A_nom                    ·                                    m            TB                    +                      m            LB                                                m            TA                    +                      m            LA                                ,wherein TA—nom=the rated torque of the electric motor of the first hoist trolley, TB—nom=the rated torque of the electric motor of the second hoist trolley, vA—nom=nominal speed of the first hoist trolley, vB—nom=nominal speed of the second hoist trolley, mTA=dead weight of the first hoist trolley, mTB=dead weight of the second hoist trolley mLA=load of the first hoist trolley, and mLB=load of the second hoist trolley.


The invention provides a semiconductor light emitting device and the method of making it. The semiconductor light emitting device, according to the invention, includes an undoped InxGAyAl2N film, as an Ohmic layer, formed between a top-most semiconductor material layer and a transparent conductive oxide layer. Since the undoped film as a tunneling layer is very thin (≦20 angstroms), the electric field across the tunneling layer, under forward bias, will make electron tunneling from valence band to conduction band, and return to the transparent conductive layer, A reasonably low and stable forward voltage of the semiconductor light emitting device according to the invention can be achieved.

1. Field of the Invention
The present invention relates to a semiconductor light emitting device and the method of making it, especially to the semiconductor light emitting device that comprises a strong ohmic layer formed between a top semiconductor material layer and a transparent conductive oxide layer, based on which the semiconductor light emitting device has lower and steadier forward voltage.
2. Description of the Prior Art
The transparent conductive oxides, e.g. ITO, ZnO, InO, ZrO, and so on, have been used for overlaying the semiconductor light emitting device. The main function of the transparent conductive oxide layer (TCOL) overlaying the semiconductor light emitting device is to be a conductive medium layer for current diffusion and light passing to improve the external quantum efficiency of the semiconductor light emitting device.
However, the ohm contact between the transparent conductive oxide layer and the top semiconductor material layer (e.g. P-type GaN layer) is not easy to be achieved, The key point of the technology of how the transparent conductive oxide layer is overlaid depends on how the lower and steadier forward voltage (Vf) is achieved. Several prior arts will be described in the following to show the difficulty in the technology.
In U.S. Pat. No. 5,977,566, Okazaki and others propose adding a metal agent layer between an ITO layer and a P-type GaN contact layer to reduce the offset of the conductive area. The material being used to form the above agent layer comprises Mg, Ni, Au, Zu, and Ti. Accordingly, the forward voltage (Vf) of the semiconductor light emitting device is reduced. Moreover, in U.S. Pat. No. 6,078,064, Ming-Jiunn and others propose using a P-type contact layer with highly doped consistency (more than 5×1018) to be the agent layer. In U.S. Pat. No. 6,479,836, Suzuki and others propose selectively doping P-type carrier with high consistency to form super-lattice (e.g. InGaN/GaN, AlGaN/GaN, or other combinations), so as to obtain lower forward voltage (Vf). Furthermore, somebody also proposes using Ni to be the agent layer and utilizing the difused oxygen in the ITO layer to convert it to a NiO layer, so as to reduce the forward voltage (Vf) of the semiconductor light emitting device.
However, in the above arts utilizing an agent layer, the agent layer itself can absorb the intensity of the light outputted by the semiconductor light emitting device, or else during the operation, the carrier is diffused between the agent layer and the contact layer due to the agent layer having highly doped consistency, so that the forward voltage (Vf) of the semiconductor light emitting device may be very unsteady.
The process, which utilizes the ITO layer as the current diffusion layer to improve the intensity of the light outputted by the semiconductor light emitting device and to further overlay the general Ni/Au transparent conductive layers (TCLs), is well-known in the prior arts. For example, in U.S. Pat. No. 5,925,897, Oberman and others propose forming a very thin Au/Ni composite layer between the ITO layer and the P-type InGaN contact layer. Moreover, in U.S. Pat. No. 6,465,808, Lin and others propose a lattice transparent conductive layer. Because the lattice transparent conductive layer has fewer absorption areas, more light emitted by the semiconductor light emitting device can be outputted. In U.S. Pat. No. 6,287,947, Ludowise proposes forming a plurality of transparent conductive layers between the ITO layer and the P-type GaN contact layer. However, the problem of the above technology is that the reproduction of the forward voltage (Vf) and the luminance (Iv) of the semiconductor light emitting device is worse due to the difference of the surface roughness of the epitaxial wafer or the hydrogen passivation effect.
Although there are many different types of ohm contact layers for performing the function of contacting the ITO layer or the transparent conductive oxide layer, the above ohm contact layers are all N-type or P-type with highly doped consistency. During the process of manufacturing the semiconductor light emitting device, the environment of the process, such as residual oxygen or hydrogen, will easily affect the effect of the ohm contact layer. The forward voltage (Vf) of the semiconductor light emitting device will also experience offset caused by unsteady quality of the ohm contact layer.
Therefore, the objective of the present invention is to provide a strong ohmic layer for a semiconductor light emitting device, so that the semiconductor light emitting device can have a lower and steadier forward voltage.

Semiconductor light emitting device and method of making the same


A two-level IR detector imaging array of high fill-factor design. The upper microbridge detector level is spaced above and overlies the integrated circuit and bus lines on the substrate surface below.

This invention is directed to a pixel size sensor of an array of sensors for an infrared pitless microbridge construction of high fill factor. In this invention the large fill factor (>75%) is made possible by placing the detector microbridge on a second plane above the silicon surface carrying the integrated diode and bus lines.
Prior art microbridge thermal detector arrays in a silicon substrate have been fabricated and one such example is shown in the U.S. Pat. No. 3,801,949. In these prior art references, the small pixels have a low fill factor because the detector, the bus lines and the diode are all in the same plane each using a substantial share of the available pixel area.


Systems and methods for providing voice-to-text haptic augmentation in a user interface are disclosed. For example, in one embodiment, a system for converting audible speech information to a haptic effect includes a microphone and a processor in communication with the microphone, the processor configured to receive an audio signal associated with a voice from the microphone, determine a characteristic of the audio signal, and generate an actuator signal based at least in part on the characteristic, the actuator signal configured to cause an actuator to output a haptic effect.

Electronic devices provide users with a variety of feedback, including visual and aural feedback. Some devices also provide forms of haptic feedback to the user. Haptic feedback can in some instances provide a user receiving a message with information that may not be apparent in the message itself. For example, a voice message that is converted into a text message may fail to convey the level of emotion the sending user feels about the topic expressed in the message or to convey other contextual information regarding the message. Users often try to fill this void by expressing this subtext by appending well-known symbols (e.g., emoticons) onto the message. However, such symbols are limited in the complexity of the messages they can convey. In contrast, haptic feedback can provide a more complex and direct way to express such subtext to other users in a more compelling fashion.

This patent is subject to a terminal disclaimer.

Systems and methods for haptic augmentation of voice-to-text conversion


Disclosed are various embodiments for controlling an output power of a transmitter. Adjustment amounts for a transmitter to transmit at a desired power level are determined. For a predetermined time period, an actual power level of the transmitter is adjusted at a first adjustment rate. Upon an expiration of the predetermined time period, the actual power level is adjusted at a second adjustment rate, wherein the second adjustment rate is slower than the first adjustment rate.

A communication device in wireless communication with a base station may attempt to transmit data at a desired power level. However, due to various factors, such as a change in battery voltage, temperature variations, environmental changes, or other factors, the actual power level may differ or drift from the desired power level.


A process for the disposal of waste comprising the steps of passing a waste into a sealed container, purging the sealed container of oxygen, mixing pressurized oxygen and hydrocarbons so as to produce heat directed to the sealed container, and heating the interior of the sealed container to a temperature of greater than 2700.degree. F. An inert gas is introduced to the interior of the sealed container so as to displace oxygen. Water is dissociated so as to separate hydrogen and oxygen components. The separated oxygen is pressurized to greater than 1000 p.s.i. The water is heated to a temperature of greater than 2000.degree. F. in an oxygen-free environment.

Garbage and waste are produced in communities in great quantities. This garbage and waste must be disposed of in a variety of ways. The disposal of various kinds of garbage and waste in large quantities in cities is one of the important new administrative problems facing city government. Typical methods for the disposal of garbage include discharging garbage into the sea for reclamation and burying garbage underground. However, there are great problems, such as pollution of sea water and difficulty in getting land, associated with these methods. The general trend at present is directed toward the disposal of garbage by complete incineration. However, and unfortunately, the prevailing technique for the disposal of garbage is by incineration, a method used which burns garbage on fire grates with large quantities of air supplied, thus creating a number of associated problems.
It has been found that the use of large quantities of air produces large quantities of exhaust gases, thereby creating and exacerbating air pollution. Since the combustion temperature of garbage is relatively low, the residue of burnt garbage cannot be made completely harmless. A great deal of environmental pollution is caused by such effluents from this incineration process. Since the combustion of garbage on fire grates is unstable, the efficiency of heat recovery is low and it is difficult to effectively use the heat generated by the combustion and garbage. Additionally, vast space is occupied by the fire grates. This requires a large area for the combustion site. Furthermore, there is a difficulty in getting the sites for the construction of large incinerating plants because of the environmental problems associated therewith.
Recently, disposal methods have been proposed which attempt to solve some of the problems associated with thermal decomposition. Essentially, the garbage is introduced into an incinerator with the heat necessary for thermal decomposition so as to produce a generated slag and gas. There are two processes that are available--a process which uses external heat as an intense heat source necessary for thermal decomposition and a process which utilizes heat generated by the partial oxidation of the garbage with air or oxygen supplied. In the former process, since an external heat is used, the problem lies in economy. In the latter process, since combustion gas gets mixed with generated gas, the calorific value of generated gas is decreased, disadvantageously making the usefulness of the generated gas inferior to that of the former process.
Another problem facing city governments is the disposal of toxic or hazardous materials, such as polychlorinated biphenyls (PCB's) These are toxic and hazardous compounds whose use is being withdrawn or prohibited because of the irreversible harm to the health and the environment. These materials must be managed and disposed of effectively. In addition to polychlorinated biphenyls, there are also organophosphorous, organonitrogen, and organometallic compounds, as well as other materials, that exist in massive quantities and demand effective means of disposal. The majority of the toxic compounds are in a complex matrix format often combining organic and inorganic compounds or fractions, and in these cases, little or no disposal technology is available.
Various methods have been used for disposing of these toxic wastes, including thermal destruction, chemical detoxification, long-term encapsulation and specific landfill methods. With the exception of high temperature incineration, little success has been demonstrated for the safe disposal of highly toxic or extremely persistent waste, such as PCB's. The methods that have been tried have either not been able to handle anything but homogenous waste feed streams or they have only been able to handle relatively low concentrations of toxic compounds in the waste materials. Further, very few of the disposal methods tried to date have been able to develop to operate on a commercial scale.
Of the many methods tried for the disposal of toxic or hazardous wastes, thermal destruction has been the most promising. However, the toxic waste materials are usually very stable organic molecules, and they require long dwell times at high temperatures to effect thermal destruction. Some combustion or incineration systems can achieve the necessary conditions, but the facilities required are very large scale, and often the products of the combustion process present as much of a disposal problem as the original toxic wastes.
In the past, attempts have been made to use electric plasma arcs to destroy toxic wastes. An electric plasma arc system, being essentially pyrolytic, overcomes many of the deficiencies of an incineration or combustion process. The volume of gaseous products produced is much less. As a result, the equipment is substantially smaller in scale. Laboratory demonstrations have shown that a plasma ar is capable of atomizing and ionizing toxic organic compounds, and these atoms and ions usually recombine into simple products. While residual toxic materials are formed, these can be captured, so that no significant amount of toxic material is released to the environment.
Unfortunately, such pyrolytic destruction of waste materials is not suitable for a commercially viable system. Often, the gaseous products that are released into the environment can contribute to various forms of air pollution. In addition, the release of such gases causes concern among the various regulatory authorities in control of the destruction of such toxic materials. Furthermore, and importantly, such plasma arc, pyrolytic methods of waste destruction are extremely costly processes. The cost of the power needed to operate lasers, plasma arcs, or various other methods, cannot be justified on a large scale garbage disposal basis. Furthermore, the by-products of the combustion process are not acquired for later sale or cost offset.
Various United States patents have attempted to address the issue of waste disposal by high temperature incineration process. U.S. Pat. No. 4,665,841, issued on May 19, 1987, describes a municipal trash destruction system in which hydraulic systems move the rubbish, garbage, and other municipal trash into a processor. The processor includes a trash processing zone, a fractionating system, a combustion zone, a heating exchange zone, a waste heat recovery system, and a precipitator for cleaning the emissions prior to release into the atmosphere. U.S. Pat. No. 4,644,877, issued on Feb. 24, 1987, describes the pyrolytic destruction of toxic and hazardous waste materials. The waste materials are fed into a plasma arc burner where they are atomized and ionized. These materials are then discharged into a reaction chamber to be cooled and recombined into product gas and particulate matter. The product gas is then extracted from the recombining products using a scrubber. The product gas may then be burned and utilized as a fuel. U.S. Pat. No. 4,695,448, issued on Sept. 22, 1987, describes the dissociating of toxic compounds by an electric arc (e.g. 12,000.degree. F.) in an airtight chamber charged with oxygen. U.S. Pat. No. 4,759,300, issued on July 26, 1988, shows a method and apparatus for the pyrolysis of waste products. In this invention, the waste materials to be pyrolyzed are efficiently dehydrated prior to introduction into the pyrolysis retort using microwaves generated by a large microwave generator. After the waste material is dried, the initial ignition of the material is accomplished by using a high intensity laser beam. Laser ignition is continued until sufficient methane and other volatile gases are produced for burning in a burner unit to sustain the pyrolysis reaction. U.S. Pat. No. 4,667,609, issued on May 26, 1987, describes the destruction of soil contaminated with hydrocarbons by passing the material through a sealed, negatively pressurized, high temperature furnace. The temperature in one zone of this process is maintained at 2,900.degree. F. so as to effectively destroy the contaminating hydrocarbons. U.S. Patent No. 3,575,119 shows an apparatus for disintegrating and incinerating a concentrated slurry of solid organic material. Material passes through an arcuate tunnel having a plurality of arc electrodes spaced therealong. These electrodes cause the temperature to abruptly raise from about 2,000.degree. F. to about 15,000.degree. F. so as to dissolve the bonds between the carbon and the other atoms.
In the past, various techniques have been used to create high temperature burning systems. Typically, these rely on vast quantities of fuel. It has been found that the expense of attaining such destruction of waste could not justify the technique for the destruction of waste. Whenever vast quantities of fuel are required to attain a desired temperature, the cost of such fuel becomes an important consideration when evaluating the merits of a waste disposal system. As such, it was difficult to justify the benefits of the pyrolysis of waste since the cost of such waste destruction is so expensive.
Various U.S. patents have attempted to create large temperatures by the dissociation of water. For example, U.S. Pat. No. 4,848,250, issued on July 18, 1989 to J. M. Wunderley, describes a refuse container in which refuse is injected into an ignition chamber so as to ignite a readily burnable material. Water in the refuse reacts with the carbon to produce a hydrogen gas. The gas is passed to a secondary chamber wherein the hydrogen is burnt, resulting in an increase in temperature to above 3,000.degree. F. and producing water. Because of this high temperature, the water dissociates into hydrogen and oxygen. The hydrogen burns repeatedly and forms water and hydrogen in rapid succession, thereby generating thermal energy devoid of particulate matter. At high temperatures, water is dissociated into its hydrogen and oxygen components. This spontaneous occurrence keeps the system operating at temperatures of above 3000.degree. F. This does not use the combination of oxygen and hydrocarbons.
U.S. Pat. No. 4,132,065, issued on Jan. 2, 1979 to R. McGann describes a system in which a free-oxygen containing gas is heated while under pressure in a gas-fired pressurized heater and then reacted with a hydrocarbonaceous fuel. The system is designed to produce a H.sub.2 +CO-containing product gas. One portion of the product gas is reacted in the pressurized heater with air in order to heat the free-oxygen containing gas going into the gas generator.
U.S. Pat. No. 4,242,076, issued on Dec. 30, 1980, to E. Rawyler-Ehrat, describes a process of combustion in which the dissociation of water vapor is promoted by the presence of a catalyst. This catalyst is a glowing carbon. The presence of active oxygen is sufficient to activate the combustion process. A nozzle is used for the introduction of water vapor into the combustion chamber of the process.
It is an object of the present invention to provide a waste disposal system that cleanly burns the waste material.
It is another object of the present invention to provide a waste disposal system that is inexpensive and economically beneficial.
It is a further object of the present invention to provide a waste disposal system in which waste-destroying temperatures are achieved by the dissociation of water.
It is still another object of the present invention to provide a waste disposal system in which waste hydrocarbons can be used for the purpose of attaining high waste-destroying temperatures.
These and other objects and advantages of the present invention will become apparent from a reading of the attached specification and appended claims.

Apparatus and method for heating a waste disposal system


A mobile mountable to an infant support structure includes a housing having a drive mechanism, a support arm extending from the housing, and an assembly supported from the support arm. The support arm is connected to the drive mechanism and movable relative to the housing in first and second opposite directions. The assembly includes a hub, a motion portion, and a hanging portion. The motion portion has a resilient component coupled to the hanging portion, which drives the hanging portion in a third direction when the support arm moves in the first direction.

Infants develop by interacting with their surrounding environment. Sensory stimuli are an infant's first sources of learning. For example, seeing moving elements fosters development of visual tracking skills, and listening to music and sounds stimulates auditory skills.
Consequently, toys are often developed to create an interactive, sensory stimulating experience for an infant. For example, mobiles aid the development of an infant by improving vision and eye-tracking skills. When an infant focuses on an object suspended from a mobile, visual tracking skills are stimulated. In addition, it is believed that music and sounds generated by the toys enhance listening skills and inspire creative thinking.
Some mobiles include rotatable elements to enhance sensory stimulation. Movement of the rotatable elements may be activated by a wind-up mechanism or powered by a motor. However, such mobiles only provide for movement about a single stationary axis. It would be desirable to provide a mobile that increases the developmental potential of an infant by providing an additional level of visual tracking stimulation.


Methods for fast magnetic resonance imaging (“MRI”) using a combination of outer volume suppression (“OVS”) and accelerated imaging, which may include simultaneous multislice (“SMS”) imaging, data acquisitions amenable to compressed sensing reconstructions, or combinations thereof. The methods described here do not introduce fold-over artifacts that are otherwise common to reduced field-of-view (“FOV”) techniques.

In magnetic resonance imaging ("MRI"), a rectangular field-of-view ("FOV") covering an entire cross-section of the body is typically excited, even if the region-of-interest ("ROI") in the subject's body is relatively small. In some imaging applications, such as body imaging applications including cardiac imaging, this can be problematic where the field-of-view extends up to approximately 35 cm, even though the heart itself covers only a fraction (e.g., 25-33 percent) of the FOV.
Several techniques have been proposed to suppress signal outside the ROI. These include approaches for spatially selective excitation (e.g., inner volume selection) or for suppression of tissue outside the ROI (e.g., outer volume suppression, or "OVS"). However, OVS is commonly not effective enough to allow for a reduction in the FOV because the residual signal outside the ROI creates fold-over artifacts.
First pass myocardial perfusion imaging is the clinical gold-standard for detection of myocardial ischemia. It is commonly performed with two to four short-axis slices acquired every RR interval with T1-weighted contrast using saturation-recovery. However, limited left-ventricular coverage and coarse spatiotemporal resolutions are main factors compromising diagnostic image quality. To improve this, highly-undersampled 2D or 3D imaging techniques have been proposed, often relying on the utilization of spatiotemporal correlations. This necessitates modeling of the temporal dynamics, breath-holding, or motion correction. An alternative is to use simultaneous multislice or multiband ("MB") imaging to acquire multiple slices simultaneously. The SNR reduction and leakage artifacts in cardiac imaging may be mitigated by suppression of extra-cardiac tissue. Such suppression has recently shown potential in 3D stack-of-spirals perfusion imaging.
Cine MRI is routinely used in most cardiac MRI protocols for assessment of cardiac function. However, covering the entire ventricle necessitates long scan-times with conventional methods, leading to increased patient discomfort and associated health-care costs. SMS has been proposed for scan acceleration, by simultaneously exciting multiple slices and reconstructing these using coil information. The use of band shifts, as in CAIPIRINHA, has improved noise amplification in SMS imaging. However, unfavorable coil geometries in cardiac applications limit the SMS acceleration compared to neuroimaging.

Methods and apparatus for scan time reductions in magnetic resonance imaging using outer volume supression


Multiple-node communication link management apparatus and methods are disclosed. Management information is exchanged between a management system and a local communication node over a connection with the local communication node. The management information includes management information associated with the local communication node and management information associated with a peer communication node that communicates with the local communication node through a communication link. Views of the communication link, in its context between the local communication node and the peer communication node, as well as partner and peer partner communication nodes in the case of a related link pair, for example, are provided at the management system. Through the management system and the local communication node, any or all of the communication nodes including the local, peer, partner, and peer partner communication nodes can be managed through the single connection with the communication node.

Traditional communication network management UIs (User Interfaces) include CLI (Command Line Interface), Web interface, EMS (Element Management System) which is usually a GUI (Graphical User Interface) running on a host that interacts with a managed entity, and SNMP (Simple Network Management Protocol) clients. Each one of these UIs has its own merits. For example, Web interface may provide graphical configuration management capabilities, CLI may allow users to exercise greater control into the configuration of a system, and SNMP may provide a mechanism to manage entities through standard SNMP clients which lets one potentially integrate the management plane into a third party management tool.


A cutting system for cutting a workpiece by laser emission relies upon local cooling of the workpiece at the point at which cutting starts and ends. Optionally, local cooling can also be provided at a cross point where two cutting lines intersect. Relying upon the difference in thermal stress between the laser beam incidence point and the surrounding cooled portion, an initial crack can be generated in a specified direction, whereby the initial crack is propagated to form the desired cutting line. In one embodiment, the cooling is provided by a low temperature solid such as a Peltier cooling plate and the temperature of the workpiece near a point of incidence of the laser beam is determined. The determination can be made by measuring the temperature of a plasma generated near the point of incidence, or by directly measuring the temperature of the portion of the workpiece near the point of incidence.

1. Field of the Invention
The present invention relates generally to the cutting of brittle materials to define, for example, a ceramic board used for an electrical device such as a printed circuit board, or a semiconductor wafer; to a cutting system suitable for carrying out the cutting method; and to a chip material obtained by laser cutting. The invention relates more particularly to such a cutting method and cutting system for initiating a clean cut in a board or chip material by controlling the initial parameters of the cut.
2. Description of the Related Art
Laser cutting is a preferred method of cutting a workpiece because it is substantially free of dust, dross cracking, and cutting allowance. Typically, laser cutting is performed by establishing an initial crack under thermal stress, and then by propagating the crack in the direction initiated by the crack itself. Laser cutting is considered quite suitable for cutting brittle materials such as silicon wafers and electronic circuit boards.
One prior art laser cutting method, disclosed in Japanese Patent Laid-Open No. 4-37492, forms a fine hole by emission of a laser beam, wherein laser cutting starts from a micro-crack generated around the fine hole. However, this method suffers from the lack of control over the direction of the crack generated by the first piercing, and in turn, over the direction of the cutting direction determined by the initial crack. Thus, the accuracy of the cutting direction is reduced.
Another laser cutting method is disclosed in Japanese Patent Laid-Open No. 4-167985. According to this method, a modified layer is formed along a predetermined cutting line, and cutting is performed by scanning the cutting line with a laser beam. The method of JP-4-167985 suffers from the increased number of working steps necessary for forming the modified layer along the predetermined cutting line.
Japanese Patent Laid-Open No. 6-39572 discloses a laser cutting method wherein cutting is performed by multiple scanning of the laser beam using a rotating mirror. JP 6-39572 suffers from poor cutting accuracy in any case other than a linear cut.
Moreover, each of these prior art methods is incapable of accurately cutting a board which has a pattern (such as a metallized wiring) that is high in laser absorptivity, because the laser beam absorption tends to cause damage to the board.

Laser cleavage cutting method and system


An apparatus for analyzing the task specification of a source program automatically extracts and outputs data necessary in rebuilding the source program, it reduces the workload of a human operator performing maintenance works, thereby enhancing efficiency in rebuilding work.

1. Field of the Invention
This invention pertains to an apparatus for analyzing the task specification of a source program, for analyzing the processing content of an existing source program, and for outputting an analysis result.
2. Description of the Related Art
A computer system needs to have its software rebuilt when it has a specification change e.g. when it has changed its specification pursuant to an update of the mainframe. In rebuilding software, it is necessary to fully understand existing software, particularly the processing content of an existing source program. This requires work of sorting and analyzing the procedures of an existing source program. Generally, a source program comprises a task specification part for processing data items having an external interface (e.g. performing for the data item an input/output process or a "check process") and a computer control part for performing a file access related command process and other processes dependent on the OS (Operating System). Recently, it has become more prevalent to use a CASE (Computer Aided Software Engineering) tool for enhancing the efficiency of generating a source program. However, the CASE tool is not yet very effective in rebuilding software.
As described above, the prior art requires a human operator, such as a user and a system engineer, to manually extract from a source program a task specification part and a computer control part in rebuilding software. That is, the human operator sorts and extracts data necessary in rebuilding software through the analysis and judgment of an individual procedure by giving consideration to the global configuration of the listing of a source program. Thus, rebuilding software demands a high workload from a human operator, and rewriting the source program is very labor intensive.

Apparatus for analyzing the task specification (business rule specification) of a source program


A method for use in mass-producing, from a plane sheet of metal, a three-dimensional structure consisting of plane mirrors and plane structural members, said three-dimensional structure of a type in which each mirror or structural member has at least one edge that is collinear with an edge of another mirror or structural member, whereby said three-dimensional structure can be formed by bending the sheet of metal along various edges, the method including the steps of: producing masks bearing images defining the location of bending grooves, shallow grooves, separation grooves and holes for indexing pins, selecting a mask, applying a coating of photoresist to both sides of the sheet of metal, transferring the images on the selected mask to the coating of photoresist, removing those portions of the coating of photoresist to which the images were transferred, etching the sheet of metal where the portions of the coating of photoresist were removed, removing the remaining photoresist from the sheet of metal, and repeating the process using the next mask until all of the masks have been used. The two-dimensional part thus formed is then bent to form the desired three-dimensional structure, and a layer of a highly reflective material may finally be applied to those portions intended to serve as mirrors.

1. Field of the Invention
The present invention generally relates to the field of reflective optical systems and, more particularly, to the design and fabrication of mirror systems used for projecting one or more optical images from one location to another, such as in a kaleidoscope.
2. The Prior Art
Reflective optical systems such as those comprising an arrangement of several mirrors for the purpose of projecting one or more images from one location to another are typically constructed using a precise level base plate as the starting structural component. Mirror holders and supports are then precisely laid out on this base plate according to the optical design of the reflective system.
The level of cost and precision for the design and construction for reflective optical systems or mirror systems attainable by such a method is generally directly proportional to the amount of efforts devoted to such tasks. For applications where cost, precision and size are of paramount importance for such reflective optical systems, the general design and construction for them as referred to above are grossly insufficient. The need for an entirely new approach for addressing this problem, taking advantage of concomitantly developed technologies over the past few decades such as the evolution of the so-called "micro-chip" in the semiconductor industry and the like, is apparent.
One interesting and relevant example illustrating this can be found in the kaleidoscope mirror arrangements. There are two basic systems of mirrors in kaleidoscopes: the two-mirror system which produces one central image and the three-mirror which produces images reflected throughout the entire field of view. Both are set up in a triangular configuration in a tube similar to a prism. In the two-mirror system, the two mirrors are arranged in a "V" with the third side of the triangle a blackened, non-reflective surface. The angle of the "V" determines the number of reflections contributing to the overall intricacy of the central pattern. The three-mirror system reacts similarly to the two-mirror system with one major exception. A third mirror replaces the blackened side of the triangle in the two-mirror system and produces a continuation of reflections throughout the entire field of view. Symmetrical images are much harder to achieve in a three-mirror system because now there are three angles which must be accurate instead of only one angle in the two-mirror design. The most common and simplest arrangement for the 3-mirror system is the 60.degree.-60.degree.-60.degree. equilateral triangle. Here each angle produces 6-fold patterns which results in a design of continuous triangles.
Oddly, the construction of the kaleidoscope mirror arrangements, two of the most common ones as described above, has not changed since the invention of this wonderful device by Sir David Brewster in 1816. Mirror systems entail choice of material, dimension, angles and configuration, and they are the soul of the kaleidoscope. However, even though the design for the mirror systems has gone through many changes since the invention of the kaleidoscope, the manner in which the mirror systems are put together remain virtually unchanged.
The first surface mirrors (as versus second surface mirrors for better overall optical quality of the images) are first cut into the correct sizes and then they are manually glued or soldered together along the axial or long edges of the mirrors, with or without the use of a fixture or tooling. In order to achieve just a reasonably acceptable optical precision for such mirror systems, tooling fixtures must be used unless it is being handled by a skillful artisan who has had many years of practice in the art. But even then the optical precision of such mirror systems is very much limited to probably no more than a few thousandths of an inch. For those mirror systems that are put together without tooling fixtures, the optical precision will indeed be very marginal, leading to rather poor or "amateurish" image quality.
The use of manual labor to construct kaleidoscope mirror systems without relying on tooling fixtures generally not only leads to poor optical precision, but also much increased costs due to the amount of time needed for such an assembly. Even with the help of tooling fixtures, the assembly time is not much reduced unless the assembly is automated, which could add significant unwanted capital expenditure. Thus at least from the cost standpoint, there exists a need for an improved methodology for fabricating such mirror systems for kaleidoscopes.
Another major drawback for not attaining high optical precision for such mirror systems, when manual labor without tooling fixtures is used, is the limitation on the size reduction for such systems. For large mirror systems, poor optical precision in their assembly might still lead to acceptable performance from the standpoint of image quality. However, when the size of the mirror systems starts to come down, for example by an order of magnitude, then the same optical imprecision could lead to totally unacceptable image quality. This is another reason why an improved methodology for fabricating such mirror systems is highly desirable.
As mentioned above, the most common mirror systems for kaleidoscopes are the two-mirror and three-mirror systems which comprise basically three optical elements (two mirrors and a non-reflective element for the two-mirror system, and three mirrors for the three-mirror system) set up in a triangular configuration--in a tube similar to a hollow prism. Other more complicated mirror systems are also possible in theory, such as the square, rectangular, and large multiples of mirrors or n-mirror systems, where n is greater than three. Tapered mirrors of three or more sides are also possible. Even combined mirror systems such as two separate but adjoined mirror systems within a kaleidoscope, each with its own eye-piece and view point of the object chamber, are possible. The main reason why these more complicated mirror systems are seldom used and seen in kaleidoscopes is that the currently prevalent manual construction method makes them virtually impossible to construct. It goes without saying that such complicated mirror systems would lead to far more exciting symmetrical image patterns and is therefore highly desirable. Thus there is a need for an improved methodology for fabricating mirror systems for the kaleidoscopes which can handle the construction for more complicated mirror systems.
For the kaleidoscope cited as an example in the present discussion, the mirror system is but one of many components that together make up the kaleidoscope. While kaleidoscopes may vary greatly in appearance and quality, there are four primary elements in any design. They are 1) the eye piece, 2) the body, 3) the mirror system and 4) the object chamber.
In a conventional way of making a kaleidoscope, each of the above elements is individually constructed and then they have to be painstakingly assembled together. Since the mirror system is the soul of the kaleidoscope, it is highly desirable in terms of time and ease of assembly to have it constructed with built-in or integrated features so as to be able to easily accommodate the other three elements in the making of the kaleidoscope. Clearly the manual method of making the mirror system for the kaleidoscope cannot fulfill this desirable feat. Thus there exists a further need for an improved kaleidoscope mirror system fabrication methodology that can provide this desirable feature of overall system integration for the construction of the kaleidoscope.


An operational amplifier circuit includes a potential control circuit connected between a current sense semiconductor element connected in parallel with a main semiconductor element and a current detection resistor. The potential control circuit controls an output potential of the current sense semiconductor element to be equal to that of the main semiconductor element. The potential control circuit includes a current control element controlling an output current of the current sense semiconductor element and an operational amplifier outputting a signal corresponding to an output potential difference between the current sense semiconductor element and the main semiconductor element to the current control element. An input offset voltage polarity determination unit determines a polarity of an input offset voltage of the operational amplifier according to the output potential difference. The polarity of the input offset voltage is controlled to be constant based on polarity determination of the input offset voltage.

As this type of operational amplifier circuit, for example, a semiconductor device has been proposed in which a current sense semiconductor element is connected in parallel with a main semiconductor element configured to supply current to a load, an output potential of the main semiconductor element and an output potential of the current sense semiconductor element are input to an operational amplifier whose differential output controls a current-limiting semiconductor element, thereby controlling the potential of an external current detection resistor (e.g., see JP 2007-135274 A).

Operational amplifier circuit and current detection device using the same


A method for devulcanization of rubber feedstock and a related arrangement are provided. The method includes doping rubber feedstock with a photoactive substance (104, 110), configured to activate upon exposure thereof to external radiation of a predetermined wavelength; and further exposing cured rubber feedstock to the external radiation of the predetermined wavelength. Radiation exposure results, upon photoactive substance activation, in initiation of selective scission of intermolecular crosslinks, such as sulfur crosslinks, in the vulcanized rubber elastomers. The photoactive substance may be configured to initiate an excitation emission response and/or chemical reaction. The photoactive substance is preferably selected from semiconducting nanocrystals, such as quantum dots. An arrangement for carrying out the method is presented.

Discovery of rubber vulcanization almost two centuries ago gave rise to a continued interest in the use and recycling of cured rubber. Vulcanization is a chemical process for improving rubber elasticity and strength by heating thereof in the presence of sulfur. Sulfur is the oldest vulcanization agent, which links rubber polymer molecules together thus forming a three-dimensional network of individual polymeric chains cross-linked by sulfur bonds or sulfur bridges. During devulcanization process aforesaid sulfur-to-sulfur bonds are broken and the rubber particles are preferably returned to its reactive state.
Enormous numbers of used tyres, conveyor belts, hosepipes and other items are discarded each year. According to some estimates, annual production of rubber items reaches massive amount of 21 million tons, which corresponds to eight billion car tyres, for instance. These used rubber products typically end up at a landfill since there is no or very little use for them after the intended life-span.
As the demand for rubber in world market is extremely high and seems to remain that way, recycling of used rubber materials should be in the interest of both industrial users and environmentalists to secure the availability of the raw material and minimize e.g. the obvious waste problems associated with the rather challenging waste management of the used rubber products, respectively.
The existing rubber reclaiming and regenerating processes do not exploit devulcanization of rubber feedstock to the extent that would make a clear difference in the demand of new raw rubber eligible for vulcanization. The reason resides in the low yield and inferior quality, complexity, and obviously high price of the available devulcanization technology. Various microwave or ultrasound based methods, temperature control or temperature change based methods, biological methods, chemical methods such as oil-based methods, mechanical methods, and different combinations of the above have previously been suggested for use in devulcanization processes without considerable success. Devulcanization of discarded, cured rubber still remains a challenging problem, largely because during vulcanization the cross-linked rubber becomes thermoset and cannot be reformed into other products.
Polymeric molecular backbone created by vulcanization comprises apart the aforesaid sulfur bridges, also carbon-sulfur and carbon-carbon bonds, with characterizing binding energies of about 271.8 KJ (440 nm), 301 KJ (397 nm) and 347 KJ (345 nm), respectively. Known devulcanization processes rely on a wellknown fact that the energies of S—S and C—S bonds in the cured rubber network are lower than that of C—C bonds; therefore the former two types of bonds can be selectively broken up by various above mentioned methods while the parallel chains of molecular backbone are not influenced. However, the above-mentioned selective breakage has turned out to be a difficult objective. Since the mentioned binding energies are relatively close to each other, a de-crosslinking process of high selectivity is required. Implementation of such processes in practice by current devulcanization techniques remains problematic.

Method and related arrangement for devulcanization of vulcanized rubber


Machine for balancing vehicle wheels includes:                a base frame supporting elements for gripping and rotating a wheel around a balancing axis;        first sensor elements associated with the gripping and rotation elements for detecting the unbalance of the wheel;        an electronic processing and control unit associated with the first sensor elements for calculating a balancing weight to apply onto the wheel; and        an auxiliary detection appliance associated with the base frame and having:                    a rolling device for pressing onto the wheel, and in turn including:                            a support structure for two rollers revolving around axes parallel to each other; and                a flexible member closed on itself in a loop, wrapped around the rollers and having a substantially flat active section, and a return section substantially opposite the active section; and                                    second sensor elements associated with the rolling device for detecting the behaviour of the wheel when pressed by the rolling device.

It is known that the wheels of vehicles circulating on roads require frequent balancing operations, consisting in the application to the rim of the wheel of small balancing weights, made of lead or other material, suitable for offsetting the irregular distribution of the weights in the tyre.
To perform this operation, balancing machines are commonly used having a so-called "balancing" horizontal revolving spindle, on which the wheel to be balanced must be positioned integral by means of one or more centring and fastening parts.
The amount of wheel unbalance is determined once the wheel has been made to rotate on the balancing spindle by means of a series of electronic or electromechanical devices, such as force transducers applied along the balancing spindle.
To the measurement of the unbalance must be generally added other characteristic measurements, such as the measurement of the roundness of the wheel, of the eccentricity of the wheel, of the level of wear of the tread or the like.
For this purpose, the use is known of auxiliary detection methods and appliance which allow assessing and measuring all the parameters, different from unbalance, caused by non-uniform weight distributions of the tyre/rim assembly, which can affect the correct rolling of the wheel when mounted on the vehicle being driven on the road.
It is in fact underlined that a banal lack of geometric uniformity of the rim, called lateral or radial run-out, can produce a corresponding lack of geometric uniformity on the tyre and, consequently, the wheel will jump during road rolling even though, by means of the balancing machine, its balancing has been correctly performed.
Furthermore, it should not be forgotten that any build-up of weight inside the tyre can also create lack of uniformity on the tyre structure and, therefore, lack of uniformity of the elastic constant of the tyre, which negatively affects the correct rolling, of the wheel on the road.
Such condition can be detected by means of an indirect method based on the determination of the unbalance of the tyre only due to the above weight build-up after deducting any unbalance attributable to the rim.
This method allows determining any geometric faults on the rim and any weight build-up localised faults on the tyre structure, with, if necessary the two effects being offset by means of a matching operation, wherein the rim fault is placed in geometric opposition with respect to the weight fault of the tyre so as to offset the two effects.
This indirect method, nevertheless, is rather complicated and hard to implement. As an alternative to the indirect method, the use is known of auxiliary appliance fitted on balancing machines wherein an idle roller is placed in contact with the wheel with a constant load and the assessment of the lack of uniformity is made by analysing the movement which the roller performs in the presence of the lack of uniformity itself.
A piece of equipment made this way is shown, e.g., in patent document U.S. Pat. No. 6,581,463.
In such piece of equipment the geometric faults of the wheel and any tyre weight build-ups determine the lack of uniformity of the elastic constant of the elastic system of the wheel, in a radial and/or lateral direction, which consequently cause vibrations, or movements in a radial and/or lateral direction which discharge onto the roller.
Such a situation produces in the auxiliary appliance forces in a radial or lateral direction which can be read by suitable sensors.
In other words, we are able to assess the rigidity, or better the rigid nature, of the tyre structure according to the correlation between the quantity of the applied load and the amount of movement of the roller or of the forces which discharge onto it.
This auxiliary appliance of known type is not without drawbacks.
Once combined in fact with a conventional balancing system and in combination with mechanical or no-contact devices for detecting the lateral/radial run-out of the rim and of the tyre, it allows assessing or predicting the behaviour of the wheel on the road once this finds itself operating in real load and speed conditions but, nevertheless, with a rather high degree of approximation.
The application of a rotating roller on the tyre, in fact, does not allow accurately simulating the future rolling of the wheel on the road and this approximation depends on the radius of the roller or, more in detail, on the ratio between the roller radius and wheel radius.
In the appliances of known type, furthermore, the reading of the radial run-out and of the lateral run-out is not always an easy operation, taking into account the fact that the lack of geometric and weight uniformity of the rim/tyre assembly usually produces both a radial component and a lateral component and the measurement of one can affect the accuracy of the measurement of the other.

Balancing machine for balancing vehicle wheels


A lens for an LED includes a top face, a bottom face, and a circumferential periphery interconnecting the top and bottom faces. The top face defines a recess therein. A concave wall defines a bottom of the recess. In cross section of the lens, the concave wall consists of two symmetrical curves extending outward and upwardly from a bottom tip of the recess to connect with the top face. Each curve is a part of a hyperbola. The cavity is for receiving an LED therein. The lens further forms a cone-shaped top wall enclosing a top of the cavity. Light emitted from the LED travels through the cone-shaped top wall to strike the concave wall and be reflected thereby to radiate sideward and downwardly. The sideward and downwardly reflected light then is reflected by a reflective coating on a substrate to illuminate upwardly.

LEDs have increased in popularity due to many advantages, such as: high luminosity, low operational voltage, quick response time, and low power consumption. However, since LEDs are point light sources, how to uniformly distribute the light from LEDs become an issue. This issue is more significant when the LEDs are used as light sources for an application which requires a uniform illumination such as a backlight module for a liquid crystal display (LCD) panel.
Usually, a secondary optical element is used to improve the uniformity of the light from the LEDs. However, it is found that the conventional secondary optical element cannot satisfy the requirement.

Lens for light emitting diode and LED module having the lens


A sampling method sampling a lower-layer liquid from a liquid body comprised of two layers of liquids, an upper-layer liquid (octanol) and the lower-layer liquid (buffer solution), without mixing the layers. An extracting device is provided with a tubular apical end and is adapted to bring the apical end from above into a liquid to extract the liquid through the apical end. The method includes a plug injection step of injecting a plug liquid without mixing with the upper-layer liquid 50a, into the apical end 11a of the extracting device, and an extraction step of extracting the lower-layer liquid with the plug liquid by means of the extracting device.

Concerning many medical products, absorbability, metabolizability, solubility, etc. of a drug are associated with hydrophobicity of a compound used as the drug. There is a conventional technique of determining logD (water-octanol partition coefficient) as an index to indicate the hydrophobicity of a compound (e.g., cf. Patent Documents 1-3 below).    Patent Document 1: Japanese Patent Application Laid-Open No. 2001-124756    Patent Document 2: Japanese Patent No. 3444872    Patent Document 3: Japanese Patent No. 3523207
A method of determining logD is to calculate logD on the basis of a retention time in HPLC (High Performance Liquid Chromatography), as described in Patent Documents 1-3 above. However, this method obtains the calculated logD as an estimate value, and thus has a problem that it is more likely to produce an error than a method using actually measured values as described below.
Another method of determining logD is a shake-flask method. The shake-flask method is to put a compound as a measured object, water, and octanol in a flask, to shake the mixture, to measure a concentration of the compound in water and a concentration of the compound in octanol, and to calculate logD on the basis of the measured values.
The shake-flask method involves the step of measuring the concentrations in the respective solutions, which may be a method of separating water and octanol and measuring the concentrations in the separate solutions. However, this separating operation is cumbersome and does not suit lump-sum handling of multiple analytes. The separating operation originally involves adsorption on a container or the like and could cause error.
There is another method of sampling each of an aqueous solution and octanol by means of a liquid handler or the like. However, since the water layer is located below the octanol layer, this method normally has a problem that octanol is mixed in the aqueous solution during sampling thereof to cause contamination. Particularly, when logD is a large value in the range of about 4-6, the concentration in the aqueous solution is 1/104 to 1/106 of the concentration in octanol, and mixing of a small amount of octanol will pose a serious problem in the calculation of logD.

Sampling method and sampling device, and logD measuring method and logD measuring system


A design for a trench DMOS transistor having improved current carrying capability is presented. The principal improvement lies in the periodic replacement of the individual cells in the array with a protection cell of a different size. When this is done it becomes possible to significantly increase the density of cells per unit area. This results in a corresponding improvement in the amount of channel area available to the device and hence an increase in its current carrying capability.

In order for field effect devices to be able to handle large currents and voltages it becomes necessary for the active regions of such devices to be significantly larger than those used for their counterparts in more conventional applications involving low power. One structure in which this has been achieved, without adding large amounts to the area that is occupied by the device, has been the trench DMOS (double diffusion metal oxide semiconductor) transistor.
An example of such a device is shown in schematic cross-section in FIG. 1. Layer 1 of N+ material is formed at the lower surface of a silicon wafer. Deep trenches in a criss-cross grid-like pattern are etched in the upper surface of the wafer. The walls of these trenches are lined with a layer of dielectric 2, typically silicon oxide, following which they are filled with polysilicon 3. The latter will serve as the gate electrode while layer 2 will serve as the gate oxide. A source region consisting of N+ silicon 4 is formed on either side of gate oxide 2.
Surrounding source 4, and most of the trench, is a body of P type silicon 6. The space between the body 6 and drain layer 1 comprises N- material 7. The device operates like a normal field effect transistor--no current will flow between source 4 and drain 1 until a positive voltage is applied to gate 3, setting up a field across gate dielectric 2 and resulting in the formation of a conductive channel in the active region pointed to by arrow 8. Once this active region becomes N type, current from source 4 is able to traverse P body 6 and enter region 7. The latter includes a drift field which results in the acceleration of electrons over to drain layer 1.
Since the thickness of P body 6 must be kept relatively small in order to provide an optimum channel length for the active region, the separation between P body 6 and drain region 1 is as shown by arrows 11. However, this arrangement causes the device to break down in the vicinity, of the corner of oxide layer 2 first, when sufficient voltage is applied. Breakdown of this type will reduce the device reliability, is destructive, and is to be avoided at all costs. To overcome this problem, P body 6 is shaped so that a part of it extends downwards in selected places thereby reducing the separation between P body 6 and drain 1 at these locations, symbolized by arrows 12. Under these conditions, PN junction breakdown will occur at the interface between 6 and 7 before the gate oxide layer to can be destroyed.
We note that the full device is made up of a series of individual cells, whose width is defined here by arrows 13, arranged as a continuous linear or two-dimensional array.
The major disadvantage of the design illustrated in FIG. 1 is that the cell pitch can be reduced only slightly because of the lateral diffusion of deep P body 6.
In order to overcome this problem the design shown FIG. 2 has been widely adopted in the art. Cells 21, which we will henceforth refer to as active cells, are similar to the cells seen in FIG. 1. Cell 22, henceforth referred to as a protection cell, is shown at one end of the array. Its main distinguishing difference from the active cells is that its P body 26 extends further into N- region 7 than do the active cells, thereby guaranteeing that breakdown will always occur there.
A plan view of the structure is shown in FIG. 3, FIG. 2 being a cross-section of FIG. 3 taken at 2--2. The protection cell is periodically located within the array. In this case, one of every four cells is a protection cell. FIG. 4 shows the arrangement of FIG. 2 in a two-dimensional array of active cells such as a 41 and including one protection cell 42. This design is widely used in the prior art. Note that the dimensions of the protection cell are the same as those of the active cells. This leads to a cell pitch of about 4.5 microns corresponding to a cell density of about 32 million cells per square inch. The separation 45 between cells is typically about 1 micron. Neither the cell density nor the separation between cells is limited by technological considerations, rather these quantities are determined by the need to make the active cells the same size as the protection cell (whose dimension is limited by the simultaneously formed lateral diffusion distance when P body 26 is vertically driven in), in order not to lose the regular array format.
During a routine search of the prior art no references that solve the problem of increasing the array density in the matter taught by the present invention were uncovered. Several references of interest were, however, encountered. For example, Hsieh et al. (U.S. Pat. No. 5,629,543) provide P+ regions that extend into the drift region while the drain region immediately below it extends upwards. Hsieh et al. (U.S. Pat. No. 5,468,982) avoid breakdown at the intersections between the trenches by not forming the N+ source regions there. Bulucea et al. (U.S. Pat. No. 5,410,170) describe several different cell geometries which make for more efficient operation, and Hsieh et al. (U.S. Pat. No. 5,639,676) describe a process for manufacturing a DMOS array using fewer process steps than the prior art.

Power trench DMOS with large active cell density

Industrial Technology Research Institute


The present invention provides a method for cleaning particles from a semiconductor topography that has been polished using a fixed-abrasive polishing process by applying a cleaning solution including either (a) an acid and a peroxide or (b) an acid oxidant to the topography. According to an embodiment, a semiconductor topography is polished by a fixed-abrasive process in which the topography is pressed face-down on a rotating polishing pad having particles embedded in the pad while a liquid absent of particulate matter is dispensed onto the pad. The particles may include, e.g., cerium oxide, cerium dioxide, .alpha. alumina, .gamma. alumina, silicon dioxide, titanium oxide, chromium oxide, or zirconium oxide. A cleaning solution including either (a) an acid and a peroxide, e.g., hydrogen peroxide, or (b) an acid oxidant is applied to the semiconductor topography after the polishing process is completed. Examples of acids that may be used include, but are not limited to, sulfuric acid, hydrochloric acid, hydrobromic acid, hydrofluoric acid, formic acid, acetic acid, nitric acid, perchloric acid, perbromic acid, performic acid, phosphoric acid, and peracetic acid. Advantageously, the cleaning solution effectively eliminates all or at least a significant portion of the particles on the semiconductor topography.

1. Field of the Invention
This invention relates to integrated circuit manufacturing, and more particularly, to a method for cleaning particles from a semiconductor topography that has been polished using a fixed-abrasive polishing process, wherein the particles are provided to the topography from an abrasive polishing surface. The particles are removed from the semiconductor topography by applying a cleaning solution to the topography using either (a) an acid and a peroxide or (b) an acid oxidant.
2. Description of the Relevant Art
Fabrication of an integrated circuit involves numerous processing steps. After implant regions (e.g., source/drain regions) have been placed within a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the implant regions from overlying conducting regions. Interconnect routing is then placed over the interlevel dielectric and connected to the implant regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. Alternating levels of interlevel dielectric and interconnect may be placed across the semiconductor topography to form a multi-level integrated circuit.
As successive layers are deposited across previously patterned layers of an integrated circuit, elevational disparities develop across the surface of each layer. If left unattended, the elevational disparities in each level of an integrated circuit can lead to various problems. For example, when a dielectric, conductive, or semiconductive material is deposited over a topological surface having elevationally raised and recessed regions, step coverage problems may arise. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Also, stringers may arise from incomplete etching over severe steps. Furthermore, correctly patterning layers upon a topological surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational "hill" or "valley" area. The presence of such elevational disparities therefore makes it difficult to print high resolution features.
Chemical-mechanical polishing ("CMP") is a technique commonly employed to planarize or remove the elevational fluctuations in the surface of a semiconductor topography. A conventional CMP process involves placing a semiconductor wafer face-down on a polishing pad which lies on or is attached to a rotatable table or platen. A popular polishing pad medium comprises polyurethane or polyurethane-impregnated polyester felts. During the CMP process, the polishing pad and the semiconductor wafer are rotated relative to each other as the wafer is forced against the pad. An abrasive, fluid-based chemical suspension, often referred to as a "slurry", is deposited onto the surface of the polishing pad. The slurry fills the space between the polishing pad and the wafer surface such that a chemical in the slurry may react with the surface material being polished. The rotational movement of the polishing pad relative to the wafer causes abrasive particles entrained within the slurry to physically strip the reacted surface material from the wafer. The pad itself may also physically remove some material from the surface of the semiconductor topography.
In order to achieve planarization of the semiconductor topography, elevationally raised regions must be removed at a substantially faster rate than elevationally recessed regions. Unfortunately, the difference in polish rate that can be achieved between the high elevation regions and the low elevation regions is somewhat limited by the use of a slurry in the conventional CMP process. In particular, the slurry, being a relatively viscous fluid, flows to the elevationally recessed regions of the topography where it can react with the surface material, releasing it from bondage with the bulk of the material. Because of the toxic nature of some of its effluent components, the slurry waste must be disposed of and subjected to waste treatment after planarization is complete. The disposal and waste treatment of the slurry effluent significantly increases the cost of manufacturing an integrated circuit.
To avoid the problems associated with the conventional CMP process, a more recently developed polishing process known as the "fixed-abrasive" polishing process may be employed to planarize a semiconductor topography. The fixed-abrasive process involves placing a liquid which is substantially free of particulate matter between the surface of the topography and an abrasive polishing surface of a rotating polishing pad. Since no slurry is required, the time consuming and costly disposal of such a slurry may be avoided.
The liquid applied to the polishing surface in a fixed abrasive process may comprise deionized water or an acid diluted with water, depending upon the features of the topography being polished. The polishing surface comprises a polymer-based matrix entrained with particles selected from the group consisting of cerium oxide, cerium dioxide, aluminum oxide, silicon dioxide, titanium oxide, chromium oxide, and zirconium oxide. The abrasive polishing surface belongs to a polishing pad that is substantially resistant to deformation even when placed across an elevationally recessed region of relatively large lateral dimension (e.g., over 200 microns lateral dimension). Therefore, the pad is non-conformal to the underlying surface and thus does not come in contact with elevationally recessed regions of the surface. It is believed that the particles dispersed throughout the abrasive polishing surface in combination with the polishing liquid interact chemically and physically with the elevated regions of the topography to remove those regions. However, the liquid alone is believed to be incapable of removing the topography in elevationally recessed regions. Therefore, preferential removal of high elevation regions relative to low elevation regions is possible using the fixed-abrasive polishing process.
Some of the particles in the abrasive polishing surface of the polishing pad may be dislodged from the surface during polishing. The particles may thus accumulate upon the surface of the semiconductor topography being polished. Adhesion forces between dielectric surfaces (e.g., silicon dioxide) and the particles (e.g., CeO.sub.2) are quite strong, such that the particles particularly adsorb on dielectric surfaces. It is believed that a high zeta potential, i.e., electric static or charge difference, exists between the particles and the dielectric, causing the particles to "stick" to the dielectric. The presence of such particles on the semiconductor topography may scratch the surface of the topography and contaminate the ensuing integrated circuit. Considering the minute dimensions of integrated circuit features, even the tiniest defect in the semiconductor topography can render the ensuing integrated circuit inoperable.
A post-planarization cleaning process is therefore commonly employed to eliminate the abrasive particles from the semiconductor topography. The cleaning process typically involves three main steps. First, the polished surface of the semiconductor topography is buffed at a relatively low pressure for approximately 15 to 30 seconds using the polishing pad. Second, deionized water is directed to another pad softer than the polishing pad (e.g., a Politex Pad commercially available from Rodel Products Corp.) as the topography is buffed by the pad at a relatively low pressure for approximately 30 to 45 seconds. Unlike the polishing pad, this pad does not have particles fixed in the pad. Third, polyvinylalcohol ("PVA") brushes apply a solution comprising ammonium hydroxide and deionized water to the surface of the topography while concurrently mechanically scrubbing that surface for approximately 60 to 90 seconds. A special machine (e.g., the SYNERGY Integra.TM. commercially available from OnTrak Systems Inc.) is needed to perform the PVA brush scrub step.
The post-planarization cleaning process has several drawbacks, for example, some particles nonetheless remain on the surface of the polished semiconductor topography once the cleaning process is completed. The presence of such particles may be detrimental to the operation of the ensuing integrated circuit. Furthermore, the combined costs of the machine, the PVA brushes, and the extra pad required for the post-planarization cleaning procedure are relatively high. Also, the number of wafers that may be cleaned at the same time is somewhat limited by the number of tools having the pads and brushes required for the cleaning. Further, the number of wafers that may be buffed on a single pad is generally 5 or less. The considerable amount of time required to clean all of the wafers being processed might be better spent fabricating subsequent layers of those wafers. It would therefore be desirable to develop a more effective, cheaper, and faster post-planarization cleaning process.

Method for cleaning a surface of a dielectric material