An electrostatic latent-image developing toner comprising:                a core particle and a shell layer formed on an outer portion thereof,        wherein the shell layer comprises a crystalline polyester resin having a softening point from 60 to 120° C. at 70 to 100% by weight of the entire shell-layer constituent resin, and an image-forming method using the toner.

1. Field of the Invention
The present invention relates to an electrostatic latent-image developing toner.
2. Description of the Related Art
The electrostatic latent-image developing toner, which is used in an image-forming apparatus of an electrophotographic system, contains at least a resin and a colorant, and normally, a wax is added thereto in order to prevent high-temperature offset as well as low-temperature offset. The high-temperature offset refers to a phenomenon in which inter-toner aggregating force of fused toner to form a toner image is weakened due to overheat and one portion of the toner image is transferred onto a fixing roller, with the result that the toner adheres to the next recording medium (paper or the like). The low-temperature offset refers to a phenomenon in which heat energy to be used for fusing toner becomes insufficient to cause unfused toner in the vicinity of a recording medium with only the toner in the vicinity of the fixing roller being fused so that the adhesivity between the fixing roller and the toner becomes greater than the adhesivity between the toner and the recording medium to cause the toner image to adhere to the fixing roller, with the result that the subsequent toner adheres to the next recording medium. When the colorant and the wax are exposed to the surface of toner particles, the colorant and the wax tend to be transferred onto members such as a photosensitive member and a developing roller that contact the toner particles to cause image noise such as filming, which forms a main problem with the toner.
With respect to the toner, there have been demands for a low-temperature fixing property and a heat-resistant storing property, which are contradictory properties. In other words, the low-temperature fixing property is a property that allows a toner image to be sufficiently fixed on a recording medium at a comparatively low temperature, and in order to improve such a low-temperature fixing property, a method for using a resin having a comparatively low melting temperature as the toner constituent resin is proposed. However, the application of such a method results in a decrease in the glass transition point of the resin and the subsequent degradation in the heat-resistant storing property to cause aggregation at the time of storage at comparatively high temperatures. This also causes degradation in the image storing property. The image storing property is related to the storing property of the recording medium bearing an image that has been subjected to electrophotographic processes. In the case when the image storing property deteriorates, upon storing superposed images (in particular, double sided copies) at a high temperature (for example, 50° C.), the recording media adhere to each other, causing image separation when detached from each other.
With respect to toner particles having a core-shell shell structure in which a shell layer is formed on the surface of core particles so as to achieve both of the low-temperature fixing property and the heat-resistant storing property, a technique has been proposed (see Japanes Patent Application Laid-Open No. 2002-229251 and Japanese Patent Application Laid-Open No. 2002-229248) in which a low-softening-point resin is used as a core material, while a high-softening-point resin is used as a shell material. This method tries to improve the low-temperature fixing property by lowering the softening point of the core to decrease the viscosity, while improving the heat-resistant storing property by using a high-softening-point substance as the shell. With respect to the high-softening-point resin, generally known amorphous resins may be used. With this method, when the colorant and the wax are added to the core particles, the colorant and the wax are not exposed to the surface of toner particles because of the existence of the shell layer, thereby making it possible to effectively prevent image noise such as filming. In this method, however, the existence of the shell layer makes the core difficult to dissolve, failing to provide a sufficient low-temperature fixing property. Since the time required for the wax to elute to the surface of toner particles is too long, it is not possible to sufficiently prevent high-temperature offset. The resulting problem is that the fixing temperature range (non-offset temperature width) in which neither low-temperature offset nor high-temperature offset takes place is narrowed. The toner particles having the core-shell structure are generally obtained by adhering/fusing shell-use resin particles onto the surface of core particles in an aqueous medium; however, since the surface of the toner particles is formed by the high-softening-point shell-use resin particles, it becomes difficult to increase the fusing property of the toner particles and the degree of roundness in the entire toner particles.
In order to improve the low-temperature fixing property of the toner particles of the core-shell structure, a technique has been proposed (Japanese Patent Application Laid-Open No. 2002-341586) in which 2 to 15% by weight of crystalline resin is added to the shell layer. However, from the viewpoint of balance with the heat-resistant storing property, this structure has failed to exert a sufficient low-temperature fixing property.
It has been known that, upon transferring a toner image from an intermediate transferring member or a photosensitive member onto a recording medium to be fixed thereon, a simultaneous transferring/fixing system, which simultaneously carries out a transferring process and a fixing process, is preferably used from the viewpoints of a small size of the device and an improvement of the transferring efficiency (see Japanese Patent Application Laid-Open No. 2002-341584). However, the conventional toner particles fail to exert a sufficient low-temperature fixing property from the viewpoint of ensuring proper balance between the low-temperature fixing property and the heat-resistant storing property, and consequently fail to effectively reduce the fixing temperature even when applied to the above-mentioned simultaneous transferring/fixing system. For this reason, repeated image-forming processes cause a roughened surface of the intermediate transferring member, resulting in a problem of gloss irregularities.
In the case of a mono-component developing system in which, upon developing a latent image on the photosensitive member, the toner particles are allowed to pass through a gap between a developing member and a regulating member, such as a sleeve and a roller, to be friction-charged, the toner particles need to have an anti-braking property against mechanical stress. However, the above-mentioned toner particles having a core-shell structure are susceptible to separation of the shell layer, and have a problem with anti-breaking property. In the case when the anti-breaking property of the toner particles is poor, the toner particles are broken during developing processes to cause a widened charge-quantity distribution and the subsequent pollution inside the actual machine, as well as toner adhesion to the regulating blade and the subsequent longitudinal scratch lines.

Electrostatic latent-image developing toner

Konica Minolta Business Technologies, Inc.


In a nonvolatile semiconductor memory device, a voltage Vpp of 12 V applied to an external terminal is dropped by a resistance element of 3500 xcexa9 to a voltage Vrpin. Vrpin is inputted to a regulator circuit to output a stabilized voltage Vpll of 5 V, so that Vpll is applied to a common source line as an erase pulse voltage. Termination of a first erase pulse application is judged by a level detection circuit based on a result of comparison between a reference voltage Vref of 11 V and an input voltage Vrpin which begins with 5 V upon start of the erase operation. Thus, since a large voltage magnitude of the input voltage is secured, a variation in the threshold voltage of a memory cell after the termination of the first erase pulse application can be made small, thereby preventing degradation of the erase speed.

The present invention relates to a nonvolatile semiconductor memory device wherein a high voltage is applied to a source of the nonvolatile semiconductor memory device during erasure and a method of erasing the same.
ETOX (brand name of an Intel product, abbreviation of EPROM Thin Oxide) is one of conventional flash memories i.e. batch erase type memories that are most widely used. FIG. 8 shows a schematic cross sectional view of this ETOX-type flash memory cell. As shown in FIG. 8, a floating gate 5 is formed via a tunnel oxide film 4 on a source 1, a drain 2 and a well of substrate 3 between the source and the drain. A control gate 7 is further formed on the floating gate 5 via an interlayer insulating film 6.
The operation principles of the above ETOX-type flash memory are explained below. During a write operation, a voltage Vpp (for example, 10 V) is applied to the control gate 7, a standard voltage Vss (for example, 0 V) is applied to the source 1 and a voltage of 6 V is applied to the drain 2 as shown in Table 1. Consequently, a large amount of current flows in a channel layer. Channel hot electrons are generated in a portion on the drain 2 side having a high electric field, and then electrons are injected into the floating gate 5. As a result, the threshold voltage of the memory cell 8 is increased and data is written to the memory cell. FIG. 9 shows a threshold voltage distribution in a written i.e. programmed state and an erased state. As shown in FIG. 9, the threshold voltage of the written memory cell becomes 5 V or higher.
Furthermore, during an erase operation, a voltage Vnn (for example, xe2x88x929 V) is applied to the control gate 7 and a voltage Vpe (for example, 5 V) is applied to the source 1 to open the drain 2 as shown in FIG. 10. Consequently, a strong electric field is generated in the tunnel oxide film 4 between the source 1 and the floating gate 5. Then, electrons are pulled to the source 1 side by Fowler-Nordheim (FN) tunneling to decrease the threshold voltage of the memory cell 8. As a result, the threshold voltage of the erased memory cell 8 becomes 1.5 to 3 V as shown in FIG. 9.
Furthermore, during a read operation, a voltage of 1 V is applied to the drain 2 while a voltage of 5 V is applied to the control gate 7. Here, when the memory cell 8 is in an erased state and therefore its threshold voltage is low, a current flows into the memory cell 8 and a state xe2x80x9c1xe2x80x9d is determined. On the other hand, when the memory cell 8 is in a written state and therefore its threshold voltage is high, a currents does not flow into the memory cell and a state xe2x80x9c0xe2x80x9d is determined.
Based on such operation principles, the write, erase and read operations are performed in the memory cell 8.
The method of erasing the flash memory is hereinafter referred to as a conventional erase method 1.
In an actual erase operation in a nonvolatile semiconductor memory device, batch erasure is performed in units of relatively large blocks, for example, 64 kB. In this case, since threshold voltages of memory cells in the block to be erased may be in a written state or an erased state, a complicated algorithm is used for the batch erasure. A basic algorithm of the conventional erase method 1 is shown in FIG. 11. This batch erasure algorithm is briefly explained below.
When an erase operation is started, a write-before-erase operation is first performed in all the memory cells to prevent overerasure in step S1. That is, pulses having a prescribed width as write-before-erase pulses are applied to the control gate 7 and the drain 2 of a memory cell 8. In step S2, a write-verify operation is performed. That is, the threshold voltage value of each memory cell 8 is verified. In step S3, whether the verify result is acceptable, that is, whether the threshold voltage values of all the memory cells are a prescribed value (5.0 V) or higher, the voltage for a written state, is judged. As a result, when the result is unacceptable, the operation goes back to the aforementioned step S1 and the write-before-erase operation is repeated. On the other hand, when the result is acceptable, the operation proceeds to step S4. Thus, until the threshold voltages of all the memory cells in a block to be erased become the prescribed value or higher, the write-before-erase pulse application and the verify operation are repeated.
In step S4, erase pulses are applied. In this erase pulse application, to prevent overerasure (excessive erasure, which means in the case of FIG. 9 that a threshold voltage value of a memory cell becomes 1.5 V or lower), the pulse width of the erase pulses is set to be shorter than time required for complete erasure (for example, 10 ms) and pulses are applied to the control gate 7 and the source 1 in a memory cell to be erased in units of word lines in a batch.
In step S5, an erase-verify operation is performed. That is, the threshold voltage value of each memory cell 8 is verified. In step S6, whether the verify result is acceptable, that is, whether the threshold voltage values of all the memory cells are a prescribed value (3.0 V) or lower representing an erased state, is judged. As a result, when the result is unacceptable, the operation goes back to the aforementioned step S4 and the erase pulses application is repeated. On the other hand, when the result is acceptable, the operation proceeds to step S7.
The erase-verify operation in the above step S5 is the same as the read operation in Table 1 except that a voltage of 3.0 V is applied to the control gate 7 via a word line. That is, a voltage of 3.0 V is applied to a word line of a selected memory cell to be verified while 0 V is applied to word lines of the other unselected memory cells. Then, a verify operation is performed by successively selecting a word line and detecting whether a cell current flows into a memory cell. Alternatively, a voltage of 5.0 V is applied to a word line and its current level is compared with that of a memory cell having a threshold voltage of 3.0 V. Then, if there is at least one memory cell having the prescribed threshold voltage or higher, erase pulses are applied again. Thus, until the threshold voltages of all the memory cells in the block to be erased become a desired value or lower, the erase pulse application and the verify operation are repeated.
In step S7, an overerase-verify operation is performed to verify existence an overerased memory cell. In step S8, whether the verify result is acceptable is judged. As a result, if at least one overerased memory cell is detected, the operation proceeds to step S9. If not, the erase operation is terminated. In step S9, a soft program (light-level write) is performed in the overerased memory cell. Thus, the threshold voltage of the overerased memory cell is increased. When it is determined in the aforementioned step S8 that the threshold voltage distributions of all the memory cells fall in the range of 1.5 to 3.0 V, the erase operation is terminated.
Usually, an erase characteristic of the memory cell 8 varies as shown in FIG. 12 and there are memory cells wherein the erase operation is fast performed (fast cells) and memory cells wherein the erase operation is slowly performed (slow cells). FIG. 12 shows that, when erase pulses are applied for 300 ms in total, the threshold voltage of the fast cell becomes 3 V which is the upper limit voltage of the erased state and that the threshold voltage of the slow cells becomes 1.5 V which is the lower limit voltage of the erased state.
However, the variation in the erase characteristic of the memory cell 8 is further increased, and the overerasure is progressed. In particular, if there is a memory cell of which threshold voltage is 0 V among unselected memory cells and there is a memory cell of which threshold voltage is 0 V or lower, a cell current flows into the memory cell even if 0 V is applied to the word lines of unselected memory cells during the erase-verify operation. Therefore, a correct verify operation cannot be performed for the selected memory cell and thus reliability of the flash memory is degraded.
Accordingly, to avoid this overerasure, in a series of erase operations, changes in the threshold voltage value need to be frequently checked (verified) while erase pulses having a short pulse width are being applied. Furthermore, the erase pulse application and the erase-verify operation need to be repeated.
In the conventional erase method 1, a positive high voltage (for example, 5 V) is applied to the source 1 while a negative voltage (for example, xe2x88x929 V) is applied to the control gate 7 so that electrons are pulled from the floating gate 5. However, since depletion occurs in a region under the floating gate 5 due to a potential difference between the floating gate 5 and the source 1, a work current i.e. BTBT (Band To Band Tunneling) current is generated from the source 1 to the substrate 3 due to tunneling between bands. The larger the potential difference between the floating gate 5 and the source 1 becomes, the more remarkable this phenomenon becomes. That is, the larger the amount of electrons injected in the floating gate 5 and the higher the threshold value of the memory cell becomes, the more work current is generated. Since a leakage current is increased, the total current consumption is increased. Therefore, as shown in FIG. 13, the amount of an erase current is largest immediately after start of erase pulse application and as the erasure is progressed, the amount of the erase current is decreased.
In addition, in the conventional erase method 1, among these series of erase operations, the erase-verify operation needs to be performed only when the memory cells have threshold voltages decreased to some extent and are becoming an erased state. In a conventional batch erase algorithm shown in FIG. 11, wherein the erase pulse application and the erase-verify operation are repeated from the beginning, time spent for the erase-verify operation in an initial stage of an erase operation is wasted.
As one of methods for solving such a wasting problem, a method of erasing a flash EEPROM (Electrically Erasable Programmable Read-Only Memory) described in Japanese Patent Laid-Open Publication H08-111096 has been disclosed. Hereinafter, this method of erasing a flash EEPROM is referred to as a conventional erase method 2.
According to the conventional erase method 2, the erase operation is performed by utilizing the increase of the source line voltage shown in FIG. 14. FIG. 15 shows a circuit diagram of an erase operation system. This erase operation system circuit has a level detection circuit 12 for detecting the voltage of the common source line 11 and for sending a feedback to a first level shifter circuit HV1. Furthermore, the erase method in this case is a high voltage source erase method, wherein +12 V (Vpp) is applied to the source while 0 V is applied to the control gate and the drain is floated, and is different from a negative voltage control gate erase method which is the above-described conventional erase method 1.
The conventional erase method 2 is also of a source erase type, wherein electrons of the floating gate are pulled to the source. There is also a large leakage current from the source of the memory cells to the substrate in the initial stage of the erase operation as in the case of the conventional erase method 1 of erasing a the flash memory. Therefore, as shown in FIG. 14, the conventional erase method 2 has characteristics that the voltage of a source line for a memory cell being erased is greatly decreased and then increased by decreasing the threshold value of the memory cell as the erase operation proceeds, so that the amount of the leakage current from the memory cell is reduced.
FIG. 4 shows an erase algorithm in the conventional erase method 2. When the start of the erase operation, a write-before-erase operation is first performed in steps S11 to S13 in the same manner as in steps S1 to S3 in the erase algorithm of the conventional erase method 1 shown in FIG. 11. When the result of the write-verify operation is acceptable, the operation proceeds to step S14. In step S14, the first erase pulse application is started. In step S15, whether the source line voltage Vs is equal to a voltage Vref or higher is judged. As a result, when the voltage becomes equal to the voltage Vref or higher, the operation proceeds to step S16. In step S16, the first erase pulse application is terminated. The relationship between the source line voltage and the erase pulse application time in this case is the same as the one shown in FIG. 14. Furthermore, FIG. 16 shows the relationship between the source line voltage Vs and the threshold voltage Vth. As shown in FIG. 14, in the initial stage, a large amount of a leakage current flows and the source line voltage does not reach 12 V, the voltage to be applied during erasure. Then, the amount of the leakage current is reduced with time. The source line voltage is gradually increased and finally increased to a level close to 12 V. As described above, this is because the BTBT current is reduced as the threshold voltage Vth is decreased (see FIG. 16).
In the above conventional erase method 2, this relationship is utilized for an erase operation. That is, the first erase pulse application is continued until the source line voltage Vs is increased and reaches the voltage Vref (for example, 10 V). Then, when the source line voltage Vs becomes equal to the voltage Vref, an output of a level detection circuit 12 changes. The output of the level shifter circuit HV1 is set as xe2x80x9cHxe2x80x9d to turn off a P-MOS transistor 13 and the erase pulse application is stopped. Then, the operation is transited to a usual erase operation by a level shifter circuit HV2 based on an output from an erase pulse generation circuit 14.
In steps S17 to S22, application of erase pulses having a pulse width of about 10 ms and the erase-verify operation are repeated. When all the memory cells are checked and whether there is any overerased memory cell, whose threshold voltage is 3 V or lower, is determined. If there is any, a soft program is performed and the erase operation is terminated. These are in the same manner as in steps S4 to step S9 in the erase algorithm of the conventional erase method 1 shown in FIG. 11.
The conventional erase method 2 has a disadvantage that current consumed in the source section during the erase operation is larger as compared with the conventional erase method 1. In the high voltage source erase of the conventional erase method 2, 12 V is applied to the source, the amount of an erase current is about five times larger than that in the negative voltage control gate erase of the conventional erase method 1. For example, in the case of a 64-kB block erasure, the erase current is about 2 mA in the negative voltage control gate erase of the conventional erase method 1. On the other hand, it is about 10 mA in the high voltage source erase of the conventional erase method 2.
Therefore, it is desirable to apply the negative voltage control gate erase method to the conventional erase method 2. However, when the negative voltage control gate erase method is applied to the conventional erase method 2, the following problems arise.
FIG. 17 shows the relationship between the threshold voltage Vth and the source line voltage Vs with respect to an erase time when the negative voltage control gate erase method is applied to the conventional erase method 2. FIG. 18 shows the relationship between the source line voltage and the erase time when the negative voltage control gate erase method is applied to the conventional erase method 2. FIG. 19 is a circuit diagram for application of source voltage during an erase operation when the negative voltage control gate erase method is applied to the conventional erase method 2.
As described above, in the conventional erase method 1, an erase current including a leakage current is about ⅕ of that of conventional erase method 2. Therefore, a small amount of a BTBT current is generated in the memory cell section. Therefore, as shown in FIG. 18, the source line voltage Vs is increased desirably from its initial state to a level close to 5 V, a voltage to be applied. When the voltage Vref of a level detection circuit 15 in FIG. 19 is set at 4.5 V and the source line voltage Vs is increased to 4.5 V, an output signal of the level detection circuit 15 is inverted and the output level of a level shifter circuit 16 becomes xe2x80x9cHxe2x80x9d. Then, the first erase pulse application is terminated.
However, since the level detection circuit 15 is configured by comparators as shown in FIG. 3, an offset voltage is present in an input stage until the source line voltage Vs reaches near 4.5 V and the output level is inverted. Since this offset voltage changes due to a process variation or a temperature variation, a variation of about 0.1 V may be generated. As shown in FIG. 17, since the voltage Vref is 4.5 V, only a small voltage magnitude VB from the source line voltage Vs is possible immediately after the start of the erase operation. Therefore, the variation of the offset voltage reaches about 1 V in maximum as a variation of the source line voltage Vs.
When the conventional erase method 2 is employed in the negative voltage control gate erase method, there is a small amount of the BTBT current. Therefore, since there is a small voltage difference due to the change in the source line voltage Vs and, furthermore, the applied voltage is as small as 5 V, the threshold voltage upon the termination of the first erase pulse application is greatly changed as shown in FIG. 17. Thus, a serious problem arises that a large variation occurs in the threshold voltage distribution.
As a result, when a variation in the threshold voltage after the first erase pulse application is shifted to a value higher than the voltage Vref, the number of times of the second and subsequent erase pulse applications and the erase-verify operations vary, resulting in a longer erase time. Furthermore, there is also a problem that, when the variation of the threshold voltage is shifted to a value lower than the voltage Vref, overerasure occurs in memory cells positioned on the lower threshold voltage distribution side. As one means for preventing the latter problem, a resistance element 17 can be inserted between the output of the level shifter circuit 16 and the input of the level detection circuit 15 as shown in FIG. 19. Consequently, when the change of the source line voltage Vs is increased, the variation in the threshold voltage upon the termination of the first erase pulse application is reduced. However, since the change in the source current is limited when this method is employed, the change in the source line voltage Vs with time becomes as shown in FIG. 20. Therefore, as compared with the case where the resistance element 17 is inserted (see FIG. 18), the rise of the source line voltage Vs immediately after the start of the erase pulse application is small and slowly increased afterwards. Therefore, as a result, the erase speed is degraded and the erase time becomes longer.
Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device wherein a time of a first erase pulse application can be set without degrading an erase speed so that a variation of a threshold voltage can be made small, and a method of erasing the same.
To achieve the above object, a nonvolatile semiconductor memory device, comprising:
floating gate field effect transistors each having a control gate, a floating gate, a drain and a source and capable of electrically writing and erasing data, the floating gate field effect transistors being arrayed in a matrix on a substrate or a well;
a plurality of row lines connected to control gates of the floating gate field effect transistors arrayed in a row direction;
a plurality of column lines connected to drains of the floating gate field effect transistors arrayed in a column direction;
a common source line connected to sources of the floating gate field effect transistors constituting a block;
a regulator circuit for supplying a voltage applied to the common source line at least during erasure;
a resistance element inserted between the regulator circuit and an external power source;
voltage level detecting means for instructing start of the erase voltage application to the common source line, detecting that an input voltage from the resistance element to the regulator circuit reaches a prescribed voltage level and instructing termination of the erase voltage application to the common source line; and
erase voltage applying means for receiving an instruction from the voltage level detecting means and applying an erase voltage from the regulator circuit to the common source line.
According to the present invention, since the threshold voltage of a floating gate field effect transistor in a written state is high immediately after the start of the erase operation, a large amount of leakage current including the BTBT current flows and there is a great voltage drop due to a resistance element inserted between an external power source and a regulator circuit. However, when an erase voltage continues to be applied to the common source line by erase voltage applying means, the threshold voltage of the floating gate field effect transistor is decreased. Along with this decrease, the leakage current is reduced and the voltage drop due to the resistance element is also reduced. Thus, the input voltage to the regulator circuit is increased. Eventually, when the voltage level detecting means detects that the prescribed voltage level is reached, the erase voltage applying means is instructed to terminate the erase voltage application to the common source line.
Therefore, reduction of the leakage current including the BTBT current with the decrease of the threshold voltage of a floating gate field effect transistor with the lapse of the erase time can be extracted as a change in the voltage drop by the resistance element inserted between the external power source and the regulator circuit.
Therefore, when the voltage of the external power source and the resistance value of the resistance element are appropriately selected, a large voltage magnitude of the input voltage from the resistance element to the regulator circuit, which is the voltage detected by the voltage level detecting means, can be secured. An influence of the variation on the output stage in the voltage level detecting means attributable to a temperature variation, a process variation or the like can be made small. Thus, the variation in the threshold voltage of the floating gate field effect transistor upon the termination of the erase voltage application can be made small.
That is, according to the present invention, when the erase pulse applications and the erase-verify operations are subsequently repeated, an overerased memory cell in an state attributable to the variation in the threshold voltage to a lower value and a longer erase time attributable to the variation in the threshold voltage to a higher value can be prevented. Therefore, as a result, the erase time can be shortened and excess discharge generated upon the erase pulse application and the erase-verify operation does not need to be repeated. Thus, a lower current consumption can be achieved.
In one embodiment of the present invention, the nonvolatile semiconductor memory device further comprises:
a voltage boosting circuit provided between the external power source and the resistance element, wherein
an output voltage from the voltage boosting circuit is supplied to the regulator circuit via the resistance element.
According to this embodiment, a voltage from the external power source is increased to a desired voltage by a voltage boosting circuit and then supplied to the regulator circuit via the resistance element. Thus, a nonvolatile semiconductor memory device wherein the current consumption can be reduced without degrading the erase speed is constructed by utilizing the voltage boosting circuit for internally generating voltages to write, erase and read data from a single power source, which is conventionally used in a flash memory or the like.
In one embodiment of the present invention, the prescribed voltage level detected by the voltage level detecting means is a voltage higher than the erase voltage applied to the common source line.
According to this embodiment, with a lapse of the erase time, the threshold voltage of the floating gate field effect transistor is decreased and the leakage current is reduced. When the input voltage to the regulator circuit is increased from the erase voltage along with this decrease, the termination of the erase voltage application is precisely determined based on the input voltage.
In one embodiment of the present invention, a resistance value of the resistance element is set at {a voltage of the external power sourcexe2x80x94the erase voltage}/{a maximum value of erase current}.
According to this embodiment, the input voltage to the regulator circuit can be reliably set to be the erase voltage even when the erase current is at the maximum value.
In one embodiment of the present invention, the resistance value of the resistance element is set at {the output voltage of the voltage boosting circuit during erasurexe2x80x94the erase voltage}/{a maximum value of erase current}.
According to this embodiment, the input voltage to the regulator circuit is secured as the erase voltage even if the erase current is at the maximum value.
In one embodiment of the present invention, an output voltage of the external power source during erasure is a voltage higher than the erase voltage.
According to this embodiment, the threshold voltage of the floating gate field effect transistor is decreased with the lapse of the erase time. When the leakage current is reduced along with this decrease, the input voltage to the regulator circuit can be increased from the erase voltage. Therefore, the termination of the erase voltage application can be precisely and stably determined.
In one embodiment of the present invention, the voltage of the external power source during erasure is 9 V or higher.
According to this embodiment, when the erase voltage applied to the common source line is, for example, 5 V, the voltage magnitude, which is the increased amount of the input voltage to the regulator circuit, can be made sufficiently large at 4 V.
The present invention also provides a method of erasing a nonvolatile semiconductor memory device in which floating gate field effect transistors each having a control gate, floating gate, drain and source and capable of electrically writing and erasing data are arrayed in a matrix on a substrate or a well, a plurality of row lines connected to control gates floating gate field effect transistors arrayed in a row direction and a plurality of column lines connected to drains of floating gate field effect transistors arrayed in a column direction are included and sources of the floating gate field effect transistors constituting a block are connected to a common source line, the method comprising:
a first erase operation for continuing to apply an erase voltage to the common source line; and
a second erase operation for repeating erase pulse application to the common source line and an erase-verify operation alternately,
wherein a current value flowing between a stabilization circuit for generating a voltage applied to the common source line and a power source of this stabilization circuit is detected during the first operation and when the current value reaches a prescribed current value, the first erase operation is stopped and the second erase operation is started.
According to the above invention, the threshold voltage of the floating gate field effect transistor in the written state is high immediately after the start of the erase operation in the first erase operation. Therefore, a large amount of leakage current including the BTBT current flows and the current value from the power source to a stabilization circuit is also large. However, when the erase voltage continues to be applied to the common source line, the threshold voltage of the floating gate field effect transistor is decreased. Along with this decrease, the leakage current is reduced and the current value from the power source to the stabilization circuit is also reduced. Thus, when the current value from the power source to the stabilization circuit is reduced and the prescribed voltage value is reached, the first erase operation is stopped and the second erase operation is started.
Reduction of the leakage current including the BTBT current along with the decrease of the threshold voltage of the floating gate field effect transistor with the lapse of the erase time can be extracted as a change in the current value from the power source to the stabilization circuit.
Therefore, even when there is a temperature variation, a process variation or the like, the variation in the threshold voltage of the floating gate field effect transistor upon the termination of the erase voltage application can be made small. That is, according to the present invention, during the subsequently performed repetition of the erase pulse application and the erase-verify operation, an overerased memory cell attributable to the variation in threshold voltage to a lower value or a longer erase time attributable to the variation in the threshold voltage to a higher value can be prevented.

Nonvolatile semiconductor memory device and method of erasing the same


An object is to provide a heating tank capable of highly efficiently heating a target to be heated and having high safety and reliability, and a hot water storage tank. The heating tank in which the target to be heated is stored and which heats the target to be heated by a circulated refrigerant of a heat pump, for example, the hot water storage tank which is heated by the circulated refrigerant of the heat pump to produce hot water in the tank includes a heat exchanger in which a wall surface of a tank main body is partially secured to peripheral edge portions and inner portions of two metal plates and in which non-secured portions swell to constitute a refrigerant passage closed except an inlet and an outlet. A thickness dimension of one metal plate is set to be larger than that of the other metal plate, and the one metal plate is arranged on the inner side of the other metal plate.

The present invention relates to a heating tank which heats a target to be heated stored by a circulated refrigerant of a heat pump in the tank, and a hot water storage tank.
Heretofore, in this type of heating tank, for example, a hot water storage tank in which hot water is stored, water (a target to be heated) has been heated by a circulated refrigerant of a heat pump to produce the high-temperature hot water. The hot water is stored in the hot water storage tank, and the hot water stored in the hot water storage tank is taken out, if necessary. Specifically, the hot water storage tank is connected to a heat exchanger via a pipe, and the hot water produced via the heat exchanger is stored in the hot water storage tank.
However, in a case where the hot water produced via the heat exchanger is stored in the hot water storage tank in this manner, a pump for feeding water is required for circulating the water through the heat exchanger, and there has occurred a problem that a device cost and a power consumption increase. Furthermore, since the high-temperature hot water produced by the heat exchanger returns to the hot water storage tank via the pipe, reliability of a component such as the pipe needs to be sufficiently considered, and there are many problems that the temperature of the hot water drops in a process of passing the hot water through the pipe, to result in heat loss and the like.
To solve the problem, there has been developed a device in which the heat exchanger is incorporated in the hot water storage tank, or a refrigerant pipe of the heat exchanger is wound around a wall surface of the hot water storage tank, to directly heat the water in the hot water storage tank by the circulated refrigerant of the heat pump, for example, a device in which a so-called heat release section of the heat pump is provided integrally in the hot water storage tank (e.g., see Japanese Patent Application Laid-Open No. 2001-221500).
However, as in the former case, when the pipe where the refrigerant of the heat exchanger flows is incorporated in the hot water storage tank, the above problem of the heat release loss can be solved, but the refrigerant pipe needs to be provided in the hot water storage tank. When the pipe is cracked or broken, the water in the hot water storage tank is polluted, and there have been many problems of safety and reliability.
On the other hand, as in the latter case, when the refrigerant pipe of the heat exchanger is wound around the wall surface of the hot water storage tank, heat of the refrigerant is conducted to the water in the tank via the pipe and the wall surface, and this lowers heat conductivity. Moreover, since a contact area between the pipe and the wall is very small, an even thermally conductive surface cannot be secured, and efficiency deteriorates.


Various implementations include devices, systems and approaches for tracking user orientation. In some cases, a wearable audio device includes: an electro-acoustic transducer for providing an audio output; an inertial measurement unit (IMU) for indicating motion of the wearable audio device; a set of distance sensors; and a controller coupled with the electro-acoustic transducer, the IMU and the set of distance sensors, the controller configured to: determine an orientation of a user of the wearable audio device based on the indication of motion from the IMU; verify the orientation of the user as detected by the IMU, using data from the set of distance sensors; and execute an orientation-based action in response to verifying the orientation of the user.

Detecting user orientation from wearable devices such as wearable audio devices can be challenging. For example, microelectromechanical systems such as inertial measurement units (IMUs) and/or magnetometers are prone to measurement error due to the integrating nature of their measurements, which can cause drift from the original reference point of measurement (also called "bias drift"). This bias drift can make orientation-based control of such devices challenging.


A recording apparatus includes a feeding device for feeding a recording medium, recording heads arranged along a feeding direction and extending in a direction orthogonal to the feeding direction, and a control unit for controlling the recording heads, and including storage for storing printing cycle data for printing cycles. For each printing cycle the printing cycle data includes head drive data and head identifying data identifying each head in a corresponding positional relationship with the recording medium in the feeding direction. As the recording medium advances in the feeding direction, the number of heads identified by the head identifying data in a printing cycle changes over time. Also, the apparatus includes a drive unit for reading the printing cycle data associated with a corresponding printing cycle and drives each head identified by the head identifying data based on the head drive data corresponding to the printing cycle data.

1. Field
Aspects of the present invention relate to a recording apparatus for forming an image on a recording medium, a recording data generating apparatus, a program, and a data structure.
2. Description of the Related Art
Some printers for recording color images on a recording medium such as recording paper include recording heads corresponding to respective colors such as black (K), cyan (C), magenta (M), and yellow (Y) relating to the color image to be recorded and image memories in which image data relating to the respective colors are stored. The recording heads are arranged in parallel to each other in a feeding direction so that the positions of both ends in the longitudinal direction are aligned, and are driven on the basis of the image data read from the image memories in association with feeding of the recording paper. Therefore, dots are recorded on the recording paper in sequence from the recording head arranged on the upstream side. That is, dots in the image to be recorded are formed at different timings by the respective recording heads. Therefore, a technology for constituting image memories with delay memories separately for each color and differentiating the timings of driving the recording heads by the respective delay memories which delay data outputs according to the arranged positions of the recording heads (for example, JP-A-2001-287411) is known.

Recording apparatus, recording data generating apparatus, program, and data structure


A description is given of a method of providing an electroluminescent device (20) comprising an active layer (5) of conjugated 2,5-alkyl- or alkoxy-substituted poly(p-phenylene vinylene) with inactive regions (51) and emissive regions (52) by means of patterned irradiation with UV light. Both regions (51) and (52) of the active layer (5) show a clear difference in electroluminescence, electrical resistance and solubility. By means of the above-described effects, displays can be manufactured without making use of structured electrode layers (3) and (11).

The invention relates to an electroluminescent device comprising an active layer having an electroluminescent property, which layer includes 2,5-substituted poly(p-phenylene vinylene) and which is situated between two electrode layers, at least one of said electrode layers being transparent to the light to be emitted and, in operation, said device exhibiting a light-emitting pattern. The invention also relates to a method of manufacturing an electroluminescent (EL) device having a structured active layer.
The active layer and both electrode layers can jointly form one light-emitting diode (LED), but the EL device preferably comprises various LEDs, for example in the form of a matrix of light-emitting surfaces, as intended for a display. An EL device emits light when an electric field is applied across the active or emissive layer. Such a device cannot only be used as a display but also, for example, as a light source.
The use of inorganic materials such as GaAs for the active layer has been known for a long time. Since a few years also organic materials are known, in particular semiconductive organic polymers, which can be used for the active layer. Semiconductive organic polymers have a conjugated polymer chain. A well-known polymer is, for example, poly(p-phenylene vinylene) (PPV), in particular 2,5-substitued PPV. The band gap, the electron affinity and the ionization potential can be adjusted by choosing the proper conjugated polymer chain and proper side chains. Unlike electrically conducting polymers, these conjugated polymers are undoped. In addition, such polymers enable flexible substrates to be used. The active layer of an organic polymer is situated between two electrode layers of electrically conducting materials, namely one for the injection of holes and one for the injection of electrons into the active layer.
Both electrode layers can be structured in accordance with a pattern by means of a customary photolithographic process, so that the desired pattern for a display or, for example, for an illuminated logo is obtained. In a typical example of a display, the electrodes of the first and the second electrode layers have line structures which intersect each other at right angles and hence form a matrix of individually addressable rectangular LEDs. Said rectangular LEDs form the pixels or picture elements of the display. If the electrodes of the first and the second electrode layers are connected to a voltage source, light-emitting pixels are formed at the intersections of the electrodes.
Such an EL device is known from the international Patent Application WO 90/13148. In said known EL device both electrode layers are provided in the form of strips intersecting at right angles by means of a vacuum-evaporation process. For this purpose use is made of a mask during said vacuum-evaporation process. A drawback of said known method is that both electrode layers must be structured in order to cause individual pixels to luminesce.


An integrated circuit that operates with application of an external power source supplying a first source voltage, the circuit comprising: a source voltage monitoring unit that monitors the level of the first source voltage supplied from the external power source, and that determines whether the first source voltage is supplied from the external power source; a clock selecting unit that is supplied with a first clock of a first frequency and a second clock of a second frequency lower than the first frequency, and that selects and outputs the first clock when it is determined by the source voltage monitoring unit that the first source voltage is supplied and the second clock when it is determined by the source voltage monitoring unit that the first source voltage is not supplied; and a processor that operates with supply of either one of the first clock and the second clock output by the clock selecting unit and controls the operation of the integrated circuit.

1. Field of the Invention
The present invention relates to an integrated circuit and a signal processing apparatus by use thereof.
2. Description of the Related Art
In accordance with a recent progress of electronic technology, there has been a remarkable spread of signal processing apparatuses that have a selling point of portability for handiness of carrying and execute signal processing for desired applications such as portable audio players, cellular phones, portable game machines, and PDAs (Personal Digital Assistants). Such signal processing apparatuses achieve the portability by mounting an internal power source composed of a secondary battery (nickel hydrogen rechargeable battery, lithium ion rechargeable battery, etc.) and a primary battery (alkaline battery, manganese battery, etc.) (see, e.g., Japanese Patent Application Laid-Open Publication No. 2001-184146).
In this connection, long-time execution of the desired application only with a source voltage of the internal power source will necessarily result in an increased power consumption of the internal power source. Accordingly, in consideration of the fact that a large variety of applications are executed for a long time, measures to further reduce the power consumption is essential for the signal processing apparatus and existing measures are insufficient.

Integrated circuit and signal processing apparatus using the same


Systems, methods and apparatus for stabilizing resistance measurements in electroporation systems so as to achieve high-accuracy measurements, and for controlling the pulse duration, or time constant, of electroporation pulses. Circuitry is provided to accurately determine the resistance of a sample in the electroporation system, for example a sample provided in an electroporation cuvette. Additionally, a resistance control system is provided to automatically measure the resistance of a sample, determine a capacitance and determine a parallel add-on resistance that substantially provides a desired pulse duration (time constant) for an electroporation pulse.

The present invention relates generally to electroporation systems and more particularly to systems and methods for stabilizing resistance measurements and for controlling the duration of applied electrical pulses in electroporation systems.
It is known that exposure of cells to intense electric fields for brief periods of time temporarily destabilized membranes. This effect has been described as a dielectric breakdown due to an induced transmembrane potential, and has been termed xe2x80x9celectroporationxe2x80x9d. A variety of procedures use electroporation treatments including production of monoclonal antibodies, cell-cell fusion, cell-tissue fusion, insertion of membrane proteins, and genetic transformation. Protocols for the use of electroporation to load cells in vitro typically use a suspension of single cells or cells that are attached in a planar manner to a growth surface. In vivo electroporation is more complex because tissues are involved. Tissues are composed of individual cells that collectively make up a three-dimensional structure. In either case, the effects on the cell are generally the same.
The cells or tissue are exposed to electric fields by administering one or more direct current pulses. Electrical treatment is conducted in a manner that results in a temporary membrane destabilization with minimal cytotoxicity. The intensity of electrical treatment is typically described by the magnitude of the applied electric field. This field is defined as the voltage applied to the electrodes divided by the distance between the electrodes. Electric field strengths ranging from 1000 to 5000 V/cm are typically used for delivering molecules in vivo and are also specific to the cells or tissue under investigation.
U.S. Pat. Nos. 6,258,592, 5,729,426, 5,656,926, 5,642,035, and 4,750,100, each of which are hereby incorporated by reference in its entirety, disclose examples of electroporation systems and various subsystems such as voltage control subsystems. In a typical electroporation system, an internal charge reservoir (e.g., a capacitor) stores electric energy (charge). A high-voltage switch couples the charge reservoir to a sample cuvette containing cells to be electroporated, and the stored charge discharges into the sample, typically as one or more pulses. Pulses are usually exponentially decaying in shape; however, square waves have also been used. The duration of each pulse is called pulse width. Molecule loading has been performed with pulse widths ranging from microseconds (xcexcs) to milliseconds (ms). Typically, one or multiple pulses are utilized during electrical treatment.
One problem is that the sample can have a wide range of resistance values, however, the electroporation effect may have a narrow range of parameters, e.g., pulse voltage and pulse duration, for which efficiency is highest. There is a narrow gap between electroporation and electrocution; if a pulse has too long a duration or too high a field strength, the cells may be lysed (destroyed). Minimal conditions tend to reduce the efficiency of electroporation. It is, therefore, desirable to provide systems and methods for controlling the pulse duration, or time constant, of electroporation pulses.
It is also generally desirable to apply an appropriate voltage to the sample so as to not damage the sample. Thus, it is important to accurately determine the resistance of the sample. Methods and apparatus for measuring resistance in electroporation systems and correcting for the series protection resistor are disclosed in U.S. Pat. Nos. 5,729,426, 5,642,035, and 5,656,926, each previously incorporated by reference in its entirety for all purposes. However, the resistance-measuring circuits as disclosed therein require sufficient stability of a coupling capacitor to achieve high-accuracy measurements.
Accordingly, it is desirable to provide systems, methods and apparatus for stabilizing resistance measurements in electroporation systems to achieve high-accuracy measurements and to provide systems and methods for controlling the pulse duration, or time constant, of electroporation pulses.
The present invention provides systems, methods and apparatus for stabilizing resistance measurements in electroporation systems so as to achieve high-accuracy measurements. The present invention also provides systems, methods and apparatus for controlling the pulse duration, or time constant, of electroporation pulses.
According to the present invention, circuitry is provided to accurately determine the resistance of a sample in the electroporation system, for example a sample provided in an electroporation cuvette. Additionally, a resistance control system is provided to automatically measure the resistance of a sample, determine a capacitance and determine a parallel add-on resistance that substantially provides a desired pulse duration (time constant) for an electroporation pulse.
According to an aspect of the invention, a method is provided for applying an electrical pulse to a sample for a desired duration. The method typically includes identifying a desired pulse duration, automatically measuring the resistance Rs of the sample, automatically selecting a capacitance C to be placed in series with the sample, and automatically determining a resistance R2 to be placed in parallel with the sample such that a time constant T=Cxc3x97R is substantially equal to the desired pulse duration, wherein R=(Rsxc3x97R2)/(Rs+R2). In certain aspects, R2 may be implemented using a single resistor or a multiple resistor arrangement, however, R2 is generally a composite resistance that includes any resistance continuously within the circuit arrangement and any selected component or components. Similarly, C may be a composite capacitance including any capacitance continuously within the circuit arrangement and any selected component or components.
According to another aspect of the present invention, a method is provided for automatically determining the resistance of a sample in an electroporation system. The method typically includes applying a first input signal to the sample across a coupling capacitor and a drive resistor circuit, the first input signal having an input voltage Ein at a first frequency f1, the drive resistor circuit having a resistance R1, and measuring the voltage E1 across the sample at said first frequency. The method also typically includes applying a second input signal to the sample across the drive resistor circuit, the second input signal having the input voltage Ein at a second frequency f2, and measuring the voltage E2 across the sample at said second frequency. The method further typically includes determining the sample resistance Rs using Ein and the measured values E1 and E2 without using the capacitance of the coupling capacitor.
According to yet another aspect of the invention, a circuit arrangement is provided in an electroporation system configured to determine the resistance of a sample. The arrangement typically includes a signal source for providing a sinusoidal voltage signal to a sample across a coupling capacitor and drive resistor, a frequency switch coupled to the signal source, the switch configured to adjust the frequency of the voltage signal applied by the signal source, and a microprocessor coupled to the frequency switch, an output of the signal source and the sample. The microprocessor typically controls the signal source, via the frequency switch, to apply a first voltage signal to the sample at a first frequency and a second voltage signal to the sample at a second frequency, the first and second voltage signals having substantially the same voltage amplitude. The microprocessor is typically configured to determine the sample resistance Rs based on the applied voltage amplitude of the first and second voltage signals and on the detected voltage levels across the sample at the first and second frequencies without using the capacitance of the coupling capacitor.
Reference to the remaining portions of the specification, including the drawings claims and Appendices, will realize other features and advantages of the present invention. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements.

Resistance circuit stabilization and pulse duration control systems for electroporation instruments


A data replacement apparatus according to one aspect of the present invention includes an acquisition unit, a determination unit, and a replacement unit. The acquisition unit acquires first control data having a value based on the position of a first device which can be mounted on a user's head and the position of a second device which can be gripped by a user. The determination unit determines whether or not a prescribed condition is satisfied. The replacement unit replaces the first control data with second control data when it is determined that the condition is satisfied. The second control data has a value not based on the position of the first device and/or the position of the second device.

Conventionally, it is known that a virtual experience, that is, a VR experience, is shared between a plurality of users wearing a head mounted display (HMD) via a network. Specifically, it is known that a posture of an avatar, which is an alter ego of the user in a virtual space, is controlled according to a posture (for example, gaze, head orientation, and the like) of the user.
An object of Patent Document 1 is ([0005]) to improve a problem that the second user feels uncomfortable ([0004]) for the first avatar (first user) not reacting because the second user does not know that the first user is not wearing the HMD when the first user has removed the HMD, and provide the user with a rich virtual experience. Specifically, in Patent Document 1, it is described that it is determined whether or not the user A has removed the HMD 110 based on inclination information of the HMD 110 [0095], non-wearing information is generated when it is determined that the user A has removed the HMD 110 [0100], and the user terminal 1B sets the facial expression of the avatar 4A to the default facial expression after receiving the non-wearing information [0101]. In addition, it is also described that it is determined whether or not the user A is wearing the HMD 110 again [0113], and when being worn, the facial expression of the avatar 4A is updated [0115].

Data replacement apparatus, computing device, and program for user and avatar coordination


Systems, methods, and apparatuses are directed to facilitating disabling of wireless transmission of wireless communication devices using messages. In one embodiment, logic is configured to generate a disabling message that indicates disabling of wireless transmission, and wirelessly transmit the disabling message to cause disabling of a transmitter portion of a wireless transceiver of a wireless communication device that receives the disabling message. In another embodiment, logic is configured to generate a disabling message that indicates disabling of wireless transmission, and wirelessly transmit the disabling message to cause disabling of a transmitter portion of a wireless transceiver of a wireless communication device that receives the disabling message. In some embodiments, the disabling message may cause the transmitter portion of the wireless transceiver to be disabled while a receiver portion of the wireless transmitter remains enabled.

Typically, users manually disable and enable transmitting/receiving of radio frequency (RF) signals of their wireless communication devices. For example, when a user is in an environment in which wireless interference from his/her communication device may risk the safety of the user or others, the user is generally advised to turn the communication device off or to change the mode of the communication device to "Airplane Mode" (e.g., wireless transmission and reception of the communication device is disabled). However, the user may nonetheless still forget to follow such procedures, resulting in the increased risk of danger to the user as well as others. These and other drawbacks exist with typical approaches of disabling and enabling wireless signals of wireless communication devices.

This patent is subject to a terminal disclaimer.

Disabling of wireless transmission of wireless communication devices using messages


Base stations on an Internet protocol (IP) network define a number of paging areas. An IP mobile host assumes one of (i) an active state, wherein the host informs other network nodes of a change in its point of attachment from one base station to another, and (ii) a standby state wherein the host informs other nodes only when a new point of attachment is a base station of a different paging area from a last point of attachment, thus conserving power at the mobile host. When data on the network is addressed to a standby mobile host, a page request is directed to a base station(s) in the host's current paging area for transmission. The host enters the active state and transmits a page response which is received by a base station in the current paging area, and network routing information for the host is updated accordingly.

1. Field of the Invention
This invention relates to a scheme for delivering confirmation packets to mobile hosts affiliated with an Internet protocol (IP) network.
2. Discussion of the Known Art
In networks that support mobility, the precise location of a mobile host must be known before data addressed to the host can be delivered. There is a tradeoff between how closely the network tracts the host's current location, and the processing time required to locate the host when its current position is not precisely known beforehand.
Tracking the location of the mobile host involves procedures in which the host informs the network of its location at times triggered by movement, timer expiration, and the like. Specific protocols for tracking an IP mobile host are given in Request for Comment (RFC) 2002 of the Internet Engineering Task Force (IETF), all relevant portions of which are incorporated herein by reference.
Efforts are now underway to integrate both indoor (LAN) and outdoor (WAN) wireless access technologies over a common IP based access network. Such would allow more flexibility in deploying equipment which may greatly reduce network operation costs. In addition, an IP based access network should be able to support both voice and data services on a common infrastructure, resulting in seamless support of services across both wired and wireless networks. Such IP based networks are expected to be a basis for future third and fourth generation wireless networks.
It is known that the location of a mobile host can be determined using procedures such as paging that trigger a response from the mobile host. Paging typically involves transmitting a request for a given host to a number of potential locations of the host. This set of locations is defined as a paging area, and the area corresponds to an overall scope of coverage of a set of neighboring base stations.
A paging service is available in wireless wide-area networks (WAN) such as the General Packet Radio Service (GPRS), and CDMA data. Wireless local area network (LAN) protocols such as IEEE 802.11 also have the notion of a power-save state. That is, paging is deployed in these networks as a means for waking a mobile host from a standby or power-save state to an active state, at a single base station of the network. The paging architecture and protocols in each of the networks are defined independently and do not inter-operate. Because of this, seamless movement of the mobile host between local-area and wide-area networks, or between wide-area networks of different types, is precluded. The mobility protocol for IP networks set out in RFC 2002 does not disclose or suggest a paging feature with a view toward power conservation at an IP mobile host.

Paging of mobile hosts on an internet protocol network


The present invention relates to electrolyte systems and electrochemical cells comprising conductive salts having different anionic and/or cationic radii.

Electrochemical double layer capacitors, also super- or ultracaps, use high porous electrodes, usually based on activated carbon. The partitioning of pore sizes into small, medium-sized, and large pores depends on the electrode material used and on the preparation of the electrodes (The Ultracapacitor Opportunity Report, Menahem Anderman, Advanced Automotive Batteries, 2005). The electrodes are separated by a so called separator, usually consisting of polypropylene or polyethylene. Paper or ceramic membranes may also be used. The electrolyte, which is mostly based on organic solvents, is placed between the electrodes, partially sucked by the separator and the electrodes. The electrolyte is the ionic conductive connection between the electrodes and it penetrates in between the single electrode particles.
Typical electrolyte systems used in today's supercapacitors are solutions of N(C2H5)4BF4 or N(CH3)(C2H5)3BF4 dissolved in acetonitrile or ethyl-methyl-imidazoliumBF4 in propylene carbonate. Owing to the extraordinary combination of low viscosity and high dipole moment of acetonitrile, these electrolytes have a very high conductivity. A typical electrolyte of 1.0 mol/l N(C2H5)4BF4 in acetonitrile shows an ion conductivity of almost 60 mS/cm at 25° C. Additionally, such electrolytes based on acetonitrile show superior characteristics at low temperatures and an acceptable voltage. Present capacitors are charged up to 2.5 V, partially up to 2.7 V.
Compared to modern lithium ion batteries, double layer capacitors can only accumulate a fractional part of energy. But they are capable of high current rates and they can be charged and discharged completely within seconds. Supercaps show additional advantages with regard to stability of life cycles (up to 1 million charge/discharge cycles compared to some hundred cycles for lithium ion batteries) and hence they seem to be interesting energy storage systems for a variety of stationary and mobile applications. Solely, their relative low energy density is regarded to be obstructive.


Atomic multiple word writes are provided when emulating a target system that supports atomic multiple word writes on a host system that does not. For each except the last word to be written, a gate flag is read, tested, and locked when it is found unlocked. The words are then written to memory in reverse order, unlocking the gate flags as they are written. In a host system with a longer word size than the target system, the gate flags can be stored in otherwise unused bits in the host system words containing the target system words to be written.

The present invention generally relates to computer system emulation, and more specifically to emulation of a target system utilizing a multiprocessor host system with a dissimilar word length.
The cost of designing a computer processor continues to increase. Some computer architectures thus ultimately become uneconomical to implement directly, despite these architectures having significant installed bases.
One solution to this problem is to simulate one computer architecture on another computer architecture. Herein, the simulating computer architecture will be termed the xe2x80x9chostxe2x80x9d computer system, while the simulated computer architecture will be termed the xe2x80x9ctargetxe2x80x9d computer system. Emulators have been available almost since the advent of the first compilers.
Emulators typically utilize the same word length and byte length on the host computer system and the target computer system. One reason for this is that it is significantly easier to implement a similar system emulator. Another reason is that most computer architectures presently are 32-bit architectures. However, there is a move toward 64-bit architectures. Two 32-bit words fit exactly within a single 64-bit word. This is not the situation where the target system operates on for example 36 bits, while the host system operates on 64 bits. Any problems encountered when implementing an emulator on a host system are significantly increased when the word size of the emulated target system does not evenly divide the word size of the host system.
When the two architectures have different word sizes the data type alignment of the target data in the emulated host memory will not align with the native data types in the host emulation machine. This is particularly a problem in multiprocessor emulations that require atomicity for updates of adjacent target data types within a cache line of the emulating host system memory. The atomicity of the emulating host system will not match the required atomicity of the emulated target system. This is because the atomicity paradigms of the host system will not properly merge the updates within a cache line.
This would normally be addressed by use of a separate software gating mechanism. A distinct gate would be employed by each instance of the processor emulation in order to perform any data update to the emulated memory where atomicity needed to be enforced. Such a software gating mechanism typically employs hardware instructions to lock and unlock an agreed-to gate operand in order to guarantee single-threaded operation. This software gating mechanism has the potential of adding significant processor, memory, and bus overhead to the operation of the emulator.
The problem is compounded when it is necessary to read and write double words. Double word reads and writes are common in many legacy architectures. It is possible with single word synchronization to have a situation where the first and second words in a double word write are written by two different processors at almost exactly the same time. This would necessarily lead to inconsistent results.
Double word read and write atomicity is important in many architectures and systems. In the preferred embodiment, in the emulation of the GCOS 8 operating system on a target architecture such as the Intel IA-64 architecture that does not fully support double (or more) atomic reads and writes, atomic double word reads and writes are important in maintaining system security since system security is built around double word descriptors. Lack of double (or more) word atomicity may open up significant security holes in the GCOS 8 operating systems.
It would thus be advantageous to be able to emulate efficiently a target system that has a word size and/or byte size that is not the same as that of the emulating host system. It would be even more advantageous to be able to emulate efficiently such a system when the word size of the host system is not an even multiple of the word size of the emulated target system. In performing this emulation, an efficient mechanism for reading and writing double word cached memory contents without violating atomicity constraints of an emulated target system would also be advantageous.

Method and data processing system for performing atomic multiple word writes


A method for providing interoperability between a plurality of security services and target applications by an interoperability service. The method includes receiving a request from one of the plurality of security services to perform a task on a target application, preparing a unified data model for interaction with the target application, determining and organizing data connections to perform the task on the target application, generating a set of requests using the unified data model based on the task and utilizing business logic of the interoperability service for the data connections with the target application, transforming the set of requests into commands and data structures specific to the target application, and sending the set of requests on respective data connections with the target application.

Online platforms support large numbers of users, organizations, and applications. These online platforms can rely on separate security services to perform functions for enabling the users, organizations, and applications to securely utilize the resources of the online platform. However, each security service utilizes a set of separate proprietary interfaces, protocols, connectors and similar components to interact with the online platform, users, organizations, and other security services. These security services do not provide a composable, reusable, or scalable way to connect their services to target applications, data, users, organizations, and other security solutions.
Each security service works in a silo with each application that the security service provides a service to. Each security service utilizes a connection that needs to be replicated for each application as well as any partnering security product it integrates. The connections that are provided by the security services are point to point integration with minimal reusability and scalability. If the provided connector does not fit the requirements of the platform or application the only option is to create a custom connector which adds complexity and cost to the use of the security service in connection with the platform. This issue makes the use of custom connectors and similar solutions inflexible and non-reusable in large scale implementations. In addition as more connections between security services and applications and other aspects of the platform are created it puts a high load and stress on the security service with no way to distribute the load other than to add more security service servers. This creates performance limitations, increases management, and increases cost.
Security services can provide a range of services including identity governance and administration (IGA) and identity and access management (IAM). IGA is a service that implements policies for identity management and access control. IGA services can combine identity governance processes with identity administration processes for a wide range of security processes. IGA can be implemented to support auditing, legal compliance requirements in certain jurisdictions, and similar services. IGA and similar security services are in increasing demand as users access a wide array of applications and resources provided by online platforms where the users can be connecting from a wide range of devices and locations.

Method and system for universal security services abstraction


The application pertains to methods of treating and/or preventing actinic keratosis, comprising administering a therapeutically effective amount of KX-01,

Actinic keratosis, or solar keratosis, are scaly, crusty growths (lesions) caused by damage from the sun's ultraviolet rays. They typically appear on sun-exposed areas such as the face, bald scalp, lips, and the back of the hands, and are often elevated, rough in texture, and resemble warts. Most become red, but some will be tan, pink, and/or flesh-toned. If left untreated, up to ten percent of actinic keratosis develop into squamous cell carcinoma (SCC), the second most common form of skin cancer. In rarer instances, actinic keratosis may also turn into basal cell carcinomas, the most common form of skin cancer. It is estimated that more than 58 million Americans suffers from actinic keratosis. The treatments for actinic keratosis include cryotherapy, surgical removal, chemical peel, photodynamic therapy, laser resurfacing, and/or drug-containing gel and creams. Due to the prevalence of actinic keratosis, and its ability to turn into skin cancer if not treated properly, development of further treatments is warranted.

Methods of treating and/or preventing actinic keratosis

Abstract: to a subject in need thereof.


In an embodiment, an application server is configured to manage privacy settings of a subscriber for one or more social networking services. The application server determines a set of privacy settings (e.g., a manually configured or default set of privacy settings) of the subscriber for the one or more social networking services, and then receives, from the subscriber, permission to dynamically modify the set of privacy settings. The application server monitors, responsive to the received permission, passive behavior of the subscriber that is separate from interactions between the subscriber and the one or more social networking services (e.g., calls, text messages, instant messages made to/from the subscriber, a location of the subscriber, etc.). The application server triggers a modification to the set of privacy settings based on the monitored passive behavior of the subscriber.

1. Field of the Invention
Embodiments of the present invention are directed to interacting with a subscriber to a social networking service based on passive behavior of the subscriber.
2. Description of the Related Art
Due to the complex nature of social relationships and the uniqueness of people, it is very difficult to predict the preferences of subscribers to social networking services. Accordingly, conventional social networking services (e.g., Facebook, Twitter, MySpace, etc.) typically rely upon subscribers to input information associated with their social interests and desired privacy settings.
This can be relatively burdensome for the subscriber because, after registering to a particular social networking service, the subscriber must either accept default settings that are not customized to the subscriber, or else must enter his/her privacy settings and social interests (e.g., friends, hobbies, blogs of interest, etc.) before the social networking service can be used or accessed by the subscriber.
Also, managing privacy settings for a social networking service can be confusing for subscribers. For example, while the privacy policies of social networking services are often clarified either in an account-settings section of the service, subscribers are often surprised when their social networking services make certain information public to other individuals (e.g., friends, family, strangers, etc.) or entities (e.g., advertisers, etc.).

Interacting with a subscriber to a social networking service based on passive behavior of the subscriber


A pickup truck cab, rear window, and bed protector, referred to herein as a “cab and bed protector,” particularly suitable when transporting four wheelers or all terrain vehicles (ATVs) in the bed of a pickup truck. In a presently preferred embodiment, the cab and bed protector can be mounted in the bed of a variety of pickup truck models and is easily removable. The present invention serves as a shield to arrest the forward movement of the ATV during sudden stops, to prevent damage to the truck bed, cab, and/or rear window, and protect the passengers from harm. The preferred embodiment incorporates a plate fixed to a frame to transfer forces imposed on the plate by the ATV to the front wall of the truck bed, preventing damage to either the truck or the ATV.

1. Field of the Invention
The present invention relates to cab and bed protectors designed for mounting in the bed of pickup trucks in order to prevent damage to the truck, including denting of the truck bed and cab, and breakage of the rear truck cab windows, and additionally to prevent injury to occupants of the cab, in the event that a load in the truck bed shifts toward the front of the truck. More particularly, the present invention pertains to cab and bed protectors capable of mounting on a variety of pickup truck models and easily removable, nonpermanent cab and bed protectors.
2. Related Art
Pickup trucks have proven to be desirable vehicles due to their versatile utility, in particular their ability to haul cargo of varied types. The variety in shapes and sizes of cargo carried in a pickup truck often make it difficult to secure the load, which can result in damage to the truck's bed or cab or injury to its passengers. In particular, four wheelers, all terrain vehicles (ATVs), motorcycles, lawnmowers, and similar cargo can be difficult to restrain. For exemplary purposes only, the present invention will be described in connection with the carrying of ATVs in truck beds, although it is understood that the invention has utility in connection with hauling any type of load or cargo in any truck or cargo-carrying vehicle. When a truck carrying an ATV slows suddenly or stops, and when the ATV is being driven up into the bed when loading, there is a risk of the ATV hitting the front of the truck bed, cab, or rear window, damaging same. The present invention serves as a "shield" or blocking device, to arrest forward movement of the ATV, and prevent such damage to the truck and possibly the ATV. For exemplary purposes only, the present invention will be referred to herein as a "cab and bed protector," although it is understood that the invention relates to the field of attachments for pickup trucks designed to prevent damage to the truck cab, bed, and/or window, and to prevent injury to cab occupants, which are commonly referred to as headache racks, bed or cab guards, truck protection shields, protective racks, and several other similar terms.
The prior art reveals an evolving field of bed and cab protectors that have been enhanced to solve a variety of problems and there currently exists a wide variety of multifunctional bed and cab protectors. For example, U.S. Pat. No. 4,611,824 issued to Thomas K. McIntosh on Sep. 16, 1986 discloses a bed and cab protector including a rigid screen structure having two ends which was alternatively mountable for a wide-bed pickup truck and a mini-pickup truck. This basic design has been fitted with tie down clips for securing cargo, adjustable louvers to reduce heat radiation, and brackets for mounting lights and other accessories. Cab and bed protectors have also been strengthened to protect passengers in the event of a rollover and expanded to accommodate elongated cargo such as ladders or pipes.
While the related art cab and bed protectors may be suitable for the multitude of purposes to which they are intended to address, there is still a need for a cab and bed protector to arrest the forward movement of an ATV or other cargo, that can be mounted to a variety of pickup truck models and can be easily removed from the same. The present invention distinguishes itself from the prior art in cab and bed protectors by providing a universal, demountable cab and bed protector with virtually no obstruction of vision through the rear window.

Pickup truck window, bed, and cab protector


A skate wheel including a tire support structure adapted to reduce roll resistance generally encountered from a tire comprising a 60 A to 75 A Shore hardness material. The tire support structure comprises a flexible torus portion proximal to an inner core, and a substantially rigid radially extending portion extending radially outward from the flexible torus portion. The flexible torus portion cooperates with the inner core to form a cavity. The radially extending portion extends to approximately eighty to ninety five percent of the total wheel diameter. When a load is placed on the wheel, the radially extending portion is pressed against the flexible torus portion, and the flexible torus portion deforms into the cavity. The combination of the radially extending portion and the flexible torus portion moderates distortion of the soft tire, thereby reducing roll resistance. The resulting combination of a relatively hard radially extending portion and a relatively soft tire, allows for a more optimal balance of low rolling resistance and high traction.

The present invention relates to inline skate wheels, and more particularly to inline skate wheels having an internal tire support structure allowing a softer tire material without increased roll resistance.
Inline skates have been in wide use since the early 1990's. Inline skates generally comprise a boot, shoe, or the like, having a multiplicity of wheels attached to the bottom, which wheels are in-line. Early skate wheels comprised a relatively hard injection molded polyurethane plastic inner core and a relatively soft open cast thermoset polyurethane tire surrounding the inner core. Individual wheels may vary in outside diameter and in relative softness of the tire. A softer tire results in greater grip, and a harder tire reduces rolling resistance.
The inner core in skate wheels designed in the early 90's generally comprised a hard plastic material and a diameter about sixty to seventy percent of the tire outside diameter. A smaller diameter inner core may result in a wheel without sufficient support under horizontal traction loading (i.e., side loads). A larger diameter inner core may result in a "hard" feel and vibrations. Typically, the tire may be a 76 A hardness (76 Shore Hardness A), material. A harder tire material may be used to obtain greater support, but with a loss of traction, and a softer material may be used to obtain greater traction, but with a loss of support. Such typical tire may be made from Polytetramethylene Ether Glycol (PTMEG) ether-based, high rebound, thermoset, polyurethane elastomer formulation using a gravity fill, liquid to solid, cured casting manufacturing method.
U.S. Pat. No. 5,908,519 issued Jun. 1, 1999 for "Hollow Core In-line Skate Wheel Having Contour Conforming Polyurethane Wall," teaches skate wheels having a tubular bladder. The bladder allows the tire to conform to a surface for greater traction. Unfortunately, when used by roller hockey players weighing one hundred and seventy five pounds or more, deformation of the tire (e.g., conformance of the tire to the riding surface) allowed by the bladder resulted in increased roll resistance. U.S. Pat. No. 5,922,151 issued on Jul. 13, 1999 for "Polyurethane Skate Wheel with Shaped Foam Core," utilizes a foam insert suspended in the tire to replace the bladder of the '519 patent, to reduce the conformance of the tire under straight rolling. The wheel of the '151 patent had slightly less roll resistance than the wheel of the '519 patent, but the energy absorption of the foam was inefficient, and heat build-up resulted.
In 1999, Kyrptonics in Cypress, Calif. introduced a skate wheel having an 82 A hardness solid insert bonded directly to the inner core. The insert is made of high rebound thermoset polyurethane with much lower compressive losses than the foam of the '151 patent, but the overall stiffness limits traction to be less than desirable. The Kyrptomics wheels reduce roll resistance, but do not provide sufficient structural support to allow a softer polyurethane material to be used for the tire. Redstar Wheels in Garden Grove, Calif. designed a skate wheel similar to the Kyrptonics wheels, but with a near 88 A hardness insert. The resulting wheel had low roll resistance, but at the cost of much reduced traction as well.
Another attempt at a low roll resistance skate wheel with good traction was made by Labeda Precision Sports, Inc. in Lake Elsinore, Calif. The Labeda wheels included an 85 A hardness transition layer bonded to the inner core, and a 78 A hardness rebound ring bonded to the transition layer. Although some improvements to performance were made, the Labeda wheel still required about a 76 A tire to avoid increased roll resistance.
The "Rink Rat" wheel manufactured by MPC in Cranston, R.I., have a soft inner layer covered by a harder outer layer, and is described in U.S. Pat. No. 6,036,278 issued Mar. 14, 2000 for "Multi Durometer Wheel for In-Line Skates," and U.S. Pat. No. 6,227,622 issued May 8, 2001 for "Multilayer Skate Wheel." Unfortunately, the soft inner core allows the Rink Rat wheels to deform (i.e., flatten) during straight line skating, resulting in roll resistance, and requires a tire of 76 A or greater hardness.
Roller hockey presently competes for audience with ice hockey. In order to be successful, roller hockey must provide the same "quickness" that ice hockey audiences are accustomed to. Obtaining such quickness requires skate wheels which overcome the deficiencies of known skate wheels, and unfortunately, the various wheels described above have failed to provide a wheel combining low rolling resistance for speed, and traction for maneuvering, and in general require a hard tire (i.e., at least 76 A hardness.) Thus, there remains a need for a skate wheel with reduced roll resistance and sufficient traction, and which does not result in heat buildup.

Inline wheel with softer tire and internal support structure


An embodiment of a compound semiconductor device includes: a first lower electrode; a first insulating film over the first lower electrode; a first upper electrode over the first insulating film; a second lower electrode separate from the first lower electrode; a second insulating film over the second lower electrode; a third insulating film over the second insulating film; and a second upper electrode over on the third insulating film. A thickness of the first insulating film is substantially the same as a thickness of the third insulating film, a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view, and a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view.

There is a semiconductor device including a memory cell region and a logic circuit region. Memory cells are in the memory cell region, and each memory cell includes a memory capacitor and a transistor. A smoothing capacitor and others are in the logic circuit.
Conventionally, capacitor insulating films which are made of one film are sometimes used for both of a memory capacitor in a memory cell region and a smoothing capacitor in a logic circuit region, when such a semiconductor device is manufactured. In recent years, there has been a demand for a memory capacitor to reduce a thickness of a capacitor insulating film to enable a low-voltage operation, and there has been a demand for a smoothing capacitor to have a capacitor insulating film with a sufficient thickness to suppress a leak current. Thus, it is difficult to use capacitor insulating films which are made of one film for both of a memory capacitor and a smoothing capacitor.
Meanwhile, there is a ferroelectric memory in which a ferroelectric film is used as a capacitor insulating film of a memory capacitor, and a transistor gate structure, in which a silicon oxide film is used as a capacitor insulating film, is adopted for a smoothing capacitor, for example. However, a dielectric constant of a silicon oxide film is significantly lower that a dielectric constant of a ferroelectric film, and it is not possible to achieve sufficient characteristics.
Accordingly, a technique is proposed in which a stack of ferroelectric films is used as a capacitor insulating film of a smoothing capacitor. However, even with this technique, it is difficult to achieve sufficient characteristics with a memory capacitor and a smoothing capacitor.
The problems as above sometimes exist not only in a ferroelectric memory but also in other semiconductor devices such as a DRAM (dynamic random access memory).
Patent Literature 1: Japanese Laid-open Patent Publication No. 2010-10455
Patent Literature 2: Japanese Laid-open Patent Publication No. 2013-168494
Patent Literature 3: Japanese Laid-open Patent Publication No. 10-98169
Patent Literature 4: Japanese Laid-open Patent Publication No. 2002-217381

Semiconductor device and method of manufacturing the same