An aqueous ink composition including water; a co-solvent; and an aqueous submicron colorant wax dispersion comprising a plurality of colorant wax particles comprising a colorant core surrounded by a wax shell, wherein the colorant wax particles exhibit a particle size distribution of from about 150 nanometers to less than about 300 nanometers; wherein the aqueous submicron colorant wax dispersion is prepared by (a) melting and mixing a dry colorant with at least one wax to form a colorant concentrate, wherein the colorant concentrate contains at least 25 percent by weight of colorant; (b) milling the colorant concentrate of step (a) to form a milled colorant concentrate; (c) combining the milled colorant concentrate of (b) with water and dispersing to form the colorant wax dispersion; wherein the melting and mixing of step (a) and the milling of step (b) is done in an immersion media mill or a horizontal mill; and wherein the combining of step (c) is done using a piston homogenizer.

Disclosed herein is an aqueous ink jet printing ink containing nano-pigmented or dyed wax particles for improved release and gloss properties and which are suitable for use with a broad range of color and printing media.
Ink jet printing technology often comprises jetting of inks onto a transfix belt or drum, followed by transferring of the ink onto a printing medium, such as paper, under pressure. This is often referred to as transfer or transfix ink jet printing. Ink jet printing technology also often involves jetting of inks directly onto printing media, such as direct to paper printing.
Inks formulated for transfer or direct ink jet printing technologies can comprise aqueous dispersions of dyes or pigments dispersed to have an "average" particle or drop size D50 of less than about 150 nanometers and which are stabilized using a dispersant, plus other ingredients including lubricant, solvents and binders. "Average" particle or drop size is typically represented as d50, or defined as the volume median particle size value at the 50th percentile of the particle size distribution, wherein 50% of the particles in the distribution are greater than the d50 particle size value, and the other 50% of the particles in the distribution are less than the d50 value. Average particle size can be measured by methods that use light scattering technology to infer particle size, such as Dynamic Light Scattering. The particle diameter refers to the length of an individual drop of the discontinuous layer as derived from images of the particles generated by Transmission Electron Microscopy or from Dynamic Light Scattering measurements.
Pigments are typically heavier than water and tend to agglomerate and settle unless they are stabilized by a dispersant.
Challenges associated with designing inks for transfix printing technology include achieving desired ink adhesion and release of the ink to the transfix belt or drum. To achieve the desired adhesion and release performances, a non-stick printing plate, i.e. a "blanket" can be used and an application of a layer of starch, i.e. "Skin", and glycerol disposed to the transfix belt or drum before jetting inks.
Challenges associated with designing inks for direct-to-paper printing technology include the challenges related to printing onto different printing media, including coated paper, uncoated paper, or plastic, which can be hydrophilic or hydrophobic.
The appropriate components and process aspects of the each of the foregoing U.S. Patents and Patent Publications may be selected for the present disclosure in embodiments thereof. Further, throughout this application, various publications, patents, and published patent applications are referred to by an identifying citation. The disclosures of the publications, patents, and published patent applications referenced in this application are hereby incorporated by reference into the present disclosure to more fully describe the state of the art to which this invention pertains.


There is disclosed a shunt voltage regulator which utilizes a reference voltage which generates a floating output voltage with respect to a voltage to be regulated. The shunt voltage regulator of this invention also utilizes the voltage to be regulated as a power supply to its reference voltage generator, the level shifters and the Op-Amp.

This invention relates generally to a voltage regulator and more particularly, to a shunt voltage regulator utilizing a reference voltage generator which generates a floating output voltage with respect to the voltage of the power supply.
Referring to FIG. 1, there is shown a prior art shunt voltage regulator 10. In FIG. 1, a power supply V.sub.1 generates a voltage such as 15 volts which due to temperature or load variations might have some fluctuations. In order to create a constant voltage, the shunt voltage regulator 10 is needed. In this example, in addition to regulating the voltage (creating a constant voltage), the output voltage V.sub.OUT1 is also lowered to 5 volts in order to supply a constant 5 volts to a CMOS circuitry.
The shunt voltage regulator 10 comprises a reference voltage generator 14, an Op-Amp 16, a Metal Oxide Silicon Field Effect Transistor (MOSFET) T.sub.1 and two resistors R.sub.2 and R.sub.3. The negative terminal of the reference voltage generator 14 is grounded and the positive terminal of the reference voltage generator 14 is connected to the inverting input (-) of the Op-Amp 16. The output of the Op-Amp 16 is connected to the gate of the of transistor T.sub.1. The source of transistor T.sub.1 is grounded and the drain of transistor T.sub.1 is connected to an output node 12. The non-inverting (+) input of the Op-Amp 16 is connected to node 12 through resistor R.sub.2 and also grounded through resistor R.sub.3. In addition, the power supply V.sub.1 is connected to the output node 12 through resistor R.sub.1.
In FIG. 1, the output voltage V.sub.OUT1 at node 12 is equal to: EQU V.sub.OUT1 =(R.sub.2 +R.sub.3)I.sub.1 =(R.sub.2 +R.sub.3).V.sub.3 /R.sub.3 !=(1+R.sub.2 /R.sub.3)V.sub.3.
Also, since Op-Amp 16 is used in linear mode, the voltage of the non-inventing input is set to be equal to the voltage of the inverting input which is equal to the output voltage of the reference voltage generator 14. The reference voltage generator 14 generates a reference voltage V.sub.R of 1 volt. Therefore, both voltages of the inverting and the non inverting inputs of the Op-Amp 16 are equal to 1 volt. Therefore, since EQU V.sub.3 =V.sub.R,
then EQU V.sub.OUT1 =(1+R.sub.2 /R.sub.3)V.sub.3 =(1+R.sub.2 /R.sub.3)V.sub.R.
The above relationship indicates that the shunt voltage regulator 10 keeps the output voltage V.sub.OUT1 independent of input voltage V.sub.1 and proportional to the reference voltage V.sub.R from the reference voltage generator 14. The shunt voltage regulator 10 regulates the output voltage V.sub.OUT1 and compensates for any variation in the voltage of the power supply.
For example, if the power supply V.sub.1 fluctuates from 15 volts to 16 volts, the output voltage V.sub.OUT1 tends to increase. Once the output voltage V.sub.OUT1 momentarily changes, the voltage of the non-inverting input of the Op-Amp 16 increases. The difference between the two inputs of the Op-Amp 16 increases the gate voltage of the transistor T.sub.1 which in turn increases the current drawn from T.sub.1 and R.sub.1. The increase in the current of T.sub.1 and resistor R.sub.1 will decrease the voltage of node 12. This continues until the voltage V.sub.1 and hence the output voltage V.sub.OUT1 return back to original values.
By selecting proper R.sub.2 and R.sub.3, a desired output voltage V.sub.OUT1 can be selected. For example in FIG. 1, R.sub.2 and R.sub.3 are selected to set the output voltage at node 12 to 5 volts. In this circuit, since the reference voltage V.sub.R of the reference voltage generator 14 is temperature insensitive, the output voltage V.sub.OUT1 is also temperature insensitive.
Typically, shunt voltage regulators utilize reference voltage generators to create a fixed voltage at the inverting and the non-inverting inputs of the Op-Amp to generate a fixed voltage at the output node. However, due to the popularity of the CMOS process and in particular P-substrate CMOS process, it is desirable to design a reference voltage generator using bipolar transistors fabricated with P-substrate CMOS technology. Fabricating a bipolar transistor in P-substrate CMOS technology is well known in the industry. Yet, designing a reference voltage generator with bipolar transistors in P-substrate CMOS technology creates a temperature dependent reference voltage with respect to the power supply.
The transient variation of the voltage of the power supply causes the output of the reference voltage generator to vary (float). A typical voltage generator is designed to generate a reference voltage with respect to the ground of the integrated circuit and therefore, the voltage is substantially fixed as the power supply voltage or the temperature varies.
The reason a reference voltage generated by P-substrate CMOS technology has a floating voltage is that the bipolar transistors fabricated by P-substrate CMOS technology are PNP transistors. In order to generate a reference voltage with respect to the ground, NPN transistors are required which can be easily fabricated in N-substrate CMOS technology.
Referring to FIG. 2, there is shown a bipolar transistor 20 fabricated with P-substrate CMOS technology. In P-substrate CMOS technology, the substrate which is a P-substrate is typically connected to ground or the most negative voltage used in the integrated circuit. Therefore, in P-substrate CMOS technology, in order to create a bipolar transistor, the bipolar transistor has to be created in a well. Since the substrate is a p-substrate, the well has to be n-well which then dictates that the bipolar transistor to be a PNP transistor. In this type of configuration, n-well is used as the base B, one of the p+ regions is used as collector C and the other p+ region is used as the emitter E of the bipolar transistor 20.
In FIG. 2, layer 22 is an insulator and layer 24 is a material such as aluminum to be used for the gate G of a P-substrate CMOS transistor. Since the transistor 20 is used as a bipolar transistor, gate G is connected to a voltage above 5 volts which does not affect the function of bipolar transistor 20.
Referring to FIG. 3, there is shown a block diagram of a reference voltage generator 30 built with NPN transistors which generates a fixed 1 volt reference voltage. The reference voltage 1 volt is generated with respect to ground and since the voltage of ground is designated as zero, the output voltage V.sub.R1 of the reference voltage generator 30 is a fixed 1 volt.
Referring to FIG. 4, there is shown a block diagram of a reference voltage generator 40 built with PNP transistors which generates 1 volt. The reference voltage generator 40 generates a fixed 1 volt reference voltage with respect to power supply V.sub.2 and since the voltage of the power supply V.sub.2 is typically 5 volts, the output V.sub.R2 of the reference voltage generator 40 is 5-1=4 Volts. The output of the reference voltage generator 40 is floating since any transient change in the power supply causes the output voltage V.sub.R2 to vary. For example, if the voltage of the power supply changes to 5.2, then the output V.sub.R2 is 5.2-1=4.2 Volts.
Therefore, in this specification the term "floating" shall mean "a voltage which is a fixed voltage below the voltage of a power supply and therefore follows the transient changes of the power supply". Furthermore, in this specification "floating reference voltage generator" shall mean a reference voltage generator which generates a floating output voltage such that the difference between the voltage of the power supply and the floating output voltage is a fixed voltage independent of temperature variations.
It is an object of this invention to provide a shunt voltage regulator which utilizes a floating reference voltage generator.

Shunt voltage regulator utilizing a floating reference voltage


The invention relates to an intervertebral implant comprising a spacer designed to be applied between two spinous processes of two vertebrae. The spacer comprises: two elements (10, 12) made of a first material, and each presenting a first end (10a, 12a) and a second end (10b, 12b), said first end (10a, 12a) being securable to a spinous process; and a connection piece (14) made of a second material of greater elastic deformability than said first material, said connection piece interconnecting said second ends (10b, 12b) of said two elements (10, 12) so that the stresses that are exerted on said two elements (10, 12) are damped, and said connection piece enabling said intervertebral implant to limit and brake the relative movements of said vertebrae.

The indications for which this type of implant is inserted and fixed between the spinous processes generally originate from deterioration of the intervertebral disk. In particular, when the posterior portion of an intervertebral disk has deteriorated, extension of the spine causes the two vertebrae that are separated by the disk to move towards each other abnormally. This generally causes the nerve roots to become trapped and causes the person who is affected by this problem to experience pain.
Intervertebral implants comprising a spacer that is inserted between the spinous processes and that includes fixing means are well known. These spacers, generally made of titanium alloy, present a notch at each of their ends, with the spinous processes being received in the notches. In addition, the spacer is held by ties, interconnecting the two opposite edges of each of the notches and tightened around part of the wall of each spinous processes.
Such implants limit the extent to which the vertebrae can move towards each other since, when the spine is in extension, the spinous processes tend to come into abutment against the bottoms of the opposite notches in which they are inserted. However, the material of which the spacer is made is hard compared with the material of an intervertebral disk which, when it is intact, limits the extent to which the vertebrae can move towards each other, so much so that the jolts which can be transmitted to the spine, e.g. while walking, are not damped between two vertebrae interconnected by a spacer. Furthermore, since the spacer does not have the same mechanical properties as the remaining portion of the intervertebral disk, the overall mechanical properties of the spine present significant discontinuities compared with an intact spine, thereby increasing deterioration of the intervertebral disk.

This patent is subject to a terminal disclaimer.


A vehicle parking indicator including an elongated marker having a longitudinal dimension and a top edge. The marker is mounted on an outer body of a motor vehicle and is visible from outside of the motor vehicle. The elongated marker is configured such that when an axis of the motor vehicle is positioned at a 45° angle to a curb, a sight-line between a side-view mirror of the motor vehicle and the curb is tangential to the top edge of the elongated marker.

Parallel parking is a method of parking a vehicle in line with other parked cars. Cars parked in parallel are in one line, parallel to the curb, with the front bumper of each car facing the back bumper of an adjacent one. Since parallel parking is parallel to the curb of a road, roads that facilitate said parking have an extra lane or a large shoulder for parked cars. It is also employed anytime perpendicular parking facilities are not available or hard to come by commonly, that's in large metropolitan areas where there is a high density of vehicles and few (or restricted) accommodations such as parking garages.
Parallel parking is considered by many to be one of the hardest skills for new drivers to learn. Following are the typical steps for performing a parallel parking:                Signal into the space.        Ensure that the desired parking space is about 2 meters longer than the vehicle's length.        Line up the vehicle beside the vehicle in front of the parking space.        Turn the steering wheel one turn towards the curb and put the vehicle into reverse.        Back up the vehicle so that the rear bumper is first to enter the parking space.        Once the vehicle is at 45° to the parking spot, slow down and turn the steering wheel all the way, to the road side.        Continue backing up until the vehicle is parallel with the curb.        Gradually turn the steering wheel towards the curb to curve the vehicle into a straight position.        Brake once the vehicle occupies the middle of the parking space.        Make sure that the vehicle is not parked too far from the curb.
Recognizing the problem of performing an accurate parallel parking some car manufacturers are trying to automate the parking process. For example, one car manufacturer recently disclosed its automated parking system. This system relies on a built-in computer, steering sensor and a tiny camera in the car's rear and works like this:
A dashboard display shows the image taken by the camera. When you near a parking space and shift into reverse, computerized lines pop up on the display, along with arrows pointing up, down, left and right. Using the arrows, you move the lines around until they define exactly where you want the car to be parked. Then you push the "set" button on the display. Keep your foot lightly on the brake pedal, and the car will start backing up, the steering wheel responding to an invisible hand. Voila, the car will park itself in the spot you've chosen with the arrows.
While easy to use, the above automated system is expensive and difficult to implement during the manufacturing process.
Other solutions include the one described in U.S. Pat. No. 6,163,253 entitled "Method and Apparatus for Guided Parking of a Vehicle Using Ultrasonic Position Detection." The '253 Patent discloses a system having a sensing and indicating device mounted at a fixed location and using transmitted and reflected acoustic or electrical energy to determine the distance between the sensor and an approaching vehicle. The sensor provides visual and/or audible indication of the distance between the vehicle and the sensor. The driver of the vehicle uses that displayed or audible information to locate the vehicle within a defined space or envelope, e.g., within a garage. The sensor and indicator may also be located laterally with respect to the vehicle so that the distance between the vehicle side and the sensor can be determined whereby the vehicle can be located laterally within the defined space or envelope.
Similarly to the system described above, the system of the '253 Patent is expensive is difficult to implement.
Accordingly, there is a need in the art for a structure providing a more convenient and safe way to correctly and accurately perform parallel parking.

Parallel parking assisting vehicle indicator


An improved and new apparatus and process for conditioning a chemical-mechanical polishing (CMP) pad has been developed, wherein sufficient conditioning is assured in order to restore the "fresh pad" polish removal rate performance of the polishing pad, while at the same time prolong the life of the CMP polishing pad. The result is a lower cost process and improved product throughput for the CMP apparatus.

(1) Field of the Invention
This invention relates to an apparatus and method for chemical-mechanical polishing (CMP) a semiconductor substrate and more particularly to an apparatus and method for conditioning the polishing pad in order to control the polish removal rate and prolong the life of the polishing pad.
(2) Description of Related Art
Chemical-mechanical polishing (CMP) has been developed for providing smooth topographies on surfaces deposited on semiconductor substrates. Rough topography results when metal conductor lines are formed over a substrate containing device circuitry. The metal conductor lines serve to interconnect discrete devices, and thus form integrated circuits. The metal conductor lines are further insulated from the next interconnection level by thin layers of insulating material and holes formed through the insulating layers provide electrical access between successive conductive interconnection layers. In such wiring processes, it is desirable that the insulating layers have a smooth surface topography, since it is difficult to lithographically image and pattern layers applied to rough surfaces. CMP can, also, be used to remove different layers of material from the surface of a semiconductor substrate. For example, following via hole formation in an insulating material layer, a metallization layer is blanket deposited and then CMP is used to produce planar metal studs.
Briefly, the CMP processes involve holding and rotating a thin, flat substrate of the semiconductor material against a wetted polishing surface under controlled chemical, pressure and temperature conditions. A chemical slurry containing a polishing agent, such as alumina or silica, is used as the abrasive material. Additionally, the chemical slurry contains selected chemicals which etch various surfaces of the substrate during processing. The combination of mechanical and chemical removal of material during polishing results in superior planarization of the polished surface.
The wetted polishing surface comprises a porous pad material, such as blown polyurethane, saturated with the polishing slurry. Mounting of the polishing pad to the polishing apparatus is a labor intensive operation and the mounting process, also, interrupts use of the polishing apparatus. The initial cost of the polishing pad, labor cost for mounting the pad to the polishing apparatus, and reduced throughput of the apparatus due to the polishing apparatus down-time while mounting the polishing pad add to the cost of polished product. Therefore, it is desirable to prolong the life of a polishing pad. A principal factor in polishing pad degradation is a phenomenon referred to as "glazing", in which, during use, abrasive particles from the polishing slurry and polished by-product become embedded and packed into the pores of the polishing pad. The result of "glazing" is a reduction of polish removal rate and underpolishing of product until a correction is made. FIG. 1 shows polish pad removal rate versus accumulated polishing time on a polishing pad. In this example, the polishing pad removal rate is significantly degraded after about 250 min. of accumulated polishing time. A technique used to overcome "glazing" is to periodically condition the polishing pad to rid the pad of embedded abrasive particles and polished by-product. State-of-the-art conditioning techniques include liquid rinsing, air blowing the polishing pad surface, and grinding of the polishing pad surface to expose a fresh surface. The grinding technique is typically accomplished by using a rotating diamond wheel to remove a portion of the pad surface. FIG. 2 shows polish pad removal rate versus accumulated polishing time, degradation of the polish pad removal rate over time, and restoration of the polish pad removal rate following pad conditioning using grinding with a diamond wheel to remove a layer of the polish pad surface. In this example, pad conditioning at about 350 min. accumulated polish time, restores the degraded polish pad removal rate to the "fresh pad" removal rate. It is important to know when pad conditioning is necessary and when the pad conditioning operation is effective. Unnecessary cost is added to the polishing process if pad conditioning is done before "glazing" has reduced the polish removal rate. It is, also, important to know when the pad conditioning operation is effective because under-conditioning will not restore the polish removal rate to the "fresh pad" polish removal rate and over-conditioning will excessively consume the polishing pad and will thereby decrease the polish pad life.
Polish pad life is a subject of concern in current CMP technology, as shown in the U.S. Pat. Nos. 5,310,455 and 5,232,875. U.S. Pat. No. 5,310,455 entitled "Techniques For Assembling Polishing Pads For Chemi-Mechanical Polishing of Silicon Wafers" granted May 10, 1994 to Nicholas F. Pasch et al describes a method of mounting polishing pads to a polishing apparatus, wherein the polishing slurry solution is diverted away from the adhesive interface between pads, thereby prolonging the life of the polishing pad by reducing catastrophic delamination of the polishing pad from the polishing apparatus. U.S. Pat. No. 5,232,875 entitled "Method and Apparatus For Improving Planarity of Chemical-Mechanical Planarization Operations" granted Aug. 3, 1993 to Mark E. Tuttle et al describes an improved polishing pad having a porous surface and perforations which extend from a lower surface thereof to an upper surface thereof. The perforations effect efficient distribution of the polishing slurry and prolong the life of the polishing pad.
The present invention is directed to a novel method and apparatus for dynamic control of polishing pad conditioning processes in order to prolong the life of the polishing pad, maintain the non-degraded polish removal rate for the polishing pad, and improve the product throughput of the polishing apparatus.

Chemical-mechanical polish (CMP) pad conditioner

Industrial Technology Research Institute


The present invention is to produce non-oriented silicon steel sheets having excellent magnetic properties in dependence upon a hot direct rolling, wherein the slab is directly sent to the direct rolling without maintaining the heat and soaking, whereby others than AlN precipitated during hot rolling check the precipitation of AlN, and a delay time is taken between the roughing and the finish rolling so that precipitating nuclei of AlN are introduced into the steel, and uniform and coarse AlN precipitation is formed by a subsequent annealing treatment, thereby to enable to provide uniform and satisfied ferrite grain growth at the recrystallization annealing.

As important factors of governing magnetic properties of electrical steel sheets, sizes and dispersing conditions of AlN and MnS precipitates in steels are taken up. This is why these precipitates themselves become to obstacles to movements of magnetic domain walls and deteriorate not only the magnetic flux densities under a low magnetic field and the characteristic of iron loss, and in addition they hinder grain growth during recrystallization annealing, and immature grain growth thereby of ferrite grains give bad influences to developments of recrystallization texture preferable to the magnetic properties.
It is known that coarser precipitates are preferable for the movements of the magnetic domain walls during magnetization. Based on such background, there has been disclosed prior art trying to provide the precipitations and coarsenings of AlN or MnS before the recrystallization annealing in the processes of making the electrical steel sheets. For example, Japanese Patent Laid-Open Specification 38814/74 checks re-solution of the coarse AlN during a slab soaking by lowering the heating temperature thereof; Japanese Patent Laid-Open Specification 22,931/81 lowers amounts of S and O accompanying growthes of fine non-metallic inclusions; Japanese Patent Laid-Open Specification 8,409/80 control formation of sulphides by addition of Ca or REM; Same 108,318/77, 41,219/79 and 123,825/83 coasen AlN by brief soaking of the slab before the hot rolling; and Same 76,422/79 utilizes self-annealing effect by coiling at super high temperature after hot rolling for coarsing AlN and accelerating growth of ferrite grain.
From a viewpoint of saving the energy in the process, it is advantageous to carry out a hot direct rolling from the continuous casting of slab when performing the hot rolling. However, if depending upon this process, a problem occurs that the coarse precipitations of AlN and MnS are insufficient, and for solving the problem, the slab is subjected to the brief soaking before the hot rolling.
However, although the soaking time is short, such a process which once transfers the slab into the heating and soaking furnaces, could not enjoy merits of saving energy brought about by the hot direct rolling, and further for providing precipitation of AlN, if the soaking time is short, the precipitation will be non-uniform at the inside and outside of the slab.

Method of making non-oriented silicon steel sheets having excellent magnetic properties


A system and method that transforms data formats into contour metrics and further transforms each contour of that mapping into contours pattern metric sets so that each metric created has a representation of one level of contour presentation, at each iteration of the learning contour identification system defined herein. This transformation of data instance to contour metrics permits a user to take relevant data of a data set, as determined by a learning contour identification system, to machines of other types and function, for the purpose of further analysis of the patterns found and labeled by said system. The invention performs with data format representations, not limited to, signals, images, or waveform embodiments so as to identify, track, or detect patterns of, amplitudes, frequencies, phases, and density functions, within the data case and then by way of using combinations of statistical, feedback adaptive, classification, training algorithm metrics stored in hardware, identifies patterns in past data cases that repeat in future, or present data cases, so that high-percentage labeling and identification is a achieved.

Field of the Invention
The present invention is in the technical field of contour detection and identification within file format data types for use in pattern recognition analysis.
Description of the Related Art
Image detection algorithms locating objects (people, mechanical, signal waveform representations, or objects of any physical nature), within data formats, identify the objects for a possible purpose of tracking the object within the image. They do so whether objects are stationary (image that does not change in time or frequency) or dynamic (change in time or frequency); that is, they find an image object, but do not take the objects found outside of the source for further processing. As a result, current technologies, in image processing analysis work, desires the computational process to remain with the original source when performing calculations for any attempts to make object identification possible.
Current technologies chose not to remove the image objects searched for from the data set so that objects found may be portable to other applications that may wish to further analyze the image data instances. Current technology makes no attempt to transform the image it finds into another numerical quantity source that is not object related in a typical sense; that is, current technology does not talk about an object as an equation, it speaks of an identification processed by showing the processed image within a modified version of its own data format source. Current technology stays within the realm of the image and talks about any identifications that need to be stated to a user of such a system as a reference to the original data set and its data values from where identifications came.
There are no current methods that use metrics of recognizable and unrecognizable patterns, of as small as 1 pixel, to identify an object, instead. There are no systems that use such methods to group such patterns so that a pattern of one dimension can be paired to an entirely different dimensioned pattern in an effort to identify an object in still another dimension. There are no current methods that use a pattern as a collection of metrics to identify an object, whether or not the final identified object is identifiable by human visual experiences or expectations, and make that representation portable to other entirely different computer system designs. There are no current methods that use a pattern grouping method, whose output from a system of hardware is portable and independent of the source to define an object and fingerprint it without having to reuse irrelevant data of the source. No current method uses contours, created from contour maps of data sets (typically associated to the study of topography) to create contour metrics for a new type of system now introduced as a learning contour identification system.
These novel metrics herein are called contour metrics and are derived from contours of contour mappings, where each contour of the map has its own set of metrics stored as container sets usable by the design of the learning contour identification system. The metrics of the container sets are typically statistical density sets, areas sets, coordinate point sets, and other metrics created and determined by a system of hardware components that make up a learning object identification system. Other container sets are subsets of the same, or other analysis sets that could very well be the output of a mathematical processes, machine code instruction sets, or subsets of its own container set. The containers group together to define the objects or the groups of objects, and to essentially leave out irrelevant information of the data source for the benefit of pattern localization and final labeling. All decisions and conversions and storage locations in memory is determined by the learning contour identification system by creating a new, if you will, mathematical representation of the patterns. Essentially, the containers, then, by supplying the metrics as memory location elements, or variables (metrics of the individual containers) make the learning identification system a function processor as the metrics are plug-in modules to a learning contour identification system to make it perform a precise way that it also determines autonomously. Basically, the system and its metrics create its own encryption code set to describe a data case that has micro patterns that are found to re-occur in sets of data cases having similar data pattern representations only recognizable by the learning system hardware that created it.
The current technology does little for the purpose of further mathematical or statistical analysis on what can be learned from the object after an object is found like on a line. Current technology may identify a line, but does not provide a searchable set of metrics on that line that has relevance to the image it came from. Current technology, therefore, cannot allow the user to walk away from the source image with some pattern, in hand, as a completely different translation but having the same identification and same meaning to the application using the information detected. Current technology prefers the user and the applications using the data to remain close with source, and requires the system to show the user the object found within the source file, or to use the source file as a reference. Current technology does not attempt to "transform" an object into another quantity so that it can leave its data format environment and still have an object identity. Current technology does not attempt to provide a user with a process form derived entirely from hardware and its application software control, which not only identifies the shape, but fingerprints the pattern by a sequence of metric representations of a pattern.

Learning contour identification system using portable contour metrics derived from contour mappings


Systems, devices, and methods permit insufflation of a body cavity prior to the insertion of a cannula into the body cavity. Some embodiments of an access system comprise an obturator, a trocar, and a fluid flow channel. The access system has a closed configuration, in which a distal end of the access system is fluidly isolated from the fluid flow channel, and an open configuration, in which the distal end of the access system is fluidly connected to the fluid flow channel, thereby permitting fluid flow, for example, an insufflation gas into a body cavity.

1. Technical Field
This application is generally directed to surgical instruments, and more particularly, to a first entry, insufflating access system.
2. Description of the Related Art
In laparoscopic procedures in which a patient's abdomen is insufflated or inflated with gas, placing a device through which the abdomen is insufflated, also referred to as a first entry device, is often problematic. Because the peritoneum directly contacts the organ bed, a device puncturing the peritoneum can also damage the underlying organ bed. Placing subsequent devices is less dangerous because the insufflating the abdomen lifts the peritoneum above a gas-fill space or cavity above the organ bed, thereby reducing the risk of inadvertent damage thereto.
Several techniques are used to achieve pneumoperitoneum in laparoscopic surgery. A first technique uses a Veress needle, which is a sharp needle placed blindly through the abdominal wall into the abdominal cavity. An insufflation gas, for example, CO2, is then pumped through the hollow Veress needle and into the abdominal cavity, thereby insufflating the peritoneal cavity. The Veress needle technique, also known as a controlled stab, is capable of damaging organs such as the intestinal tract. The technique provides little or no feedback to the surgeon that any damage to an anatomic structure has occurred.
A second technique is known as the Hassan technique in which a surgeon performs a mini-laparotomy through the abdominal layers into the abdominal cavity, through which a trocar is inserted and the abdomen insufflated. The Hassan technique is a cut-down technique that results in larger abdominal defects and increased patient scarring. The technique is also difficult to perform on obese patients with very thick abdominal walls.
In a third technique, the surgeon places a trocar optically, visualizing the abdominal layers as the trocar is placed through the abdominal wall through a laparoscope disposed within the obturator of the trocar. The tip of the obturator can penetrate about 2 cm (about 0.75″) into the organ bed of the abdominal cavity when placing the cannula and establishing pneumoperitoneum.
In a fourth technique, the abdominal layers are visualized while the trocar is advanced though the abdominal wall. As soon as the tip of the obturator punctures the peritoneum, gas is pumped through the trocar system into the abdominal cavity through vent holes disposed at the tip of the obturator. The fourth technique uses a vacuum release, which causes the organs to fall away from the abdominal wall, thereby creating a space in the abdominal cavity for the obturator tip. Accordingly, the abdominal cavity can be inflated with minimal penetration into the space. As soon as the tip of the obturator punctures the peritoneum, gas enters the abdominal cavity through the vent holes in the tip of the obturator, thereby reducing the negative pressure caused by the surgeon's lifting of the abdominal wall, and in turn, creating a space above the organ bed into which the trocar system is fully inserted into the cavity. A seal is disposed within the obturator that provides a gas tight seal both with and without the laparoscope in place. The vent holes at the tip of the obturator allow moisture and tissue to enter the obturator, however, which obscure the field of view within the obturator tip. Gas flowing directly past the laparoscope within the obturator can cool the laparoscope, thereby fogging of the lens thereof.


The present invention relates to a bracket for holding metal bar at an angle for use in linear tracking technology to provide a v-bar oriented in a manner in order to track a v-wheel along its angled edge.

1. Field of the Invention
The present invention relates to linear guide technology such as for a computer numerical controlled device (e.g. a CNC router). Specifically, present invention relates to CNC router guides for holding a rectangular extruded aluminum bar, or other metal stock, at an angle to use as guide tracking with a v-groove wheel for use with a linear tracking device.
2. Description of Related Art
The use of a linear tracking device, e.g. a computer controlled tracking device such as a CNC router or other CNC device as a tool for use with aluminum, steel, plastic, wood, and foam fabrication is well known. The CNC device is run by a computer and coordinates are uploaded into the computer machine controller from a separate program. These routers are generally very useful at not only carrying out precision work, but also to do repetitive work that is very precise.
The tracking of the router head is usually done by means of use of v-groove track for use with a v-groove wheel. The wheel moves along the v-track coordinated by the computer control. A v-groove rail, however, is a specially formed product just for this use, and thus relatively very expensive. Each project normally requires cutting and positioning new pieces of rail to match the project. When CNC devices are used for home or small projects, this can be a prohibitively costly expense in considering the use of the CNC device. Other devices specifically use linear tracking, such as architectural elements (sliding doors and windows), agricultural equipment, medical equipment, semiconductor equipment, woodworking tools, and the like which require linear motion tracking.


Relative changes in organic matter in soil in an agricultural field are mapped by a computer-implemented system and method that uses a number of individual bands from one or more remotely sensed images of the agricultural field. Each of the bands is associated with a light spectrum wavelength range, and each of the bands is weighted based on its contribution to predicting relative changes in organic matter. Elevation data may also be used in the weighted calculation. The map is separated into zones based on the relative predicted organic matter falling within a predefined range. Each zone may be associated with a different average organic matter content, and nutrient supplements are recommended for each zone based on the average organic matter associated with each of the mapped zones.

Over-fertilization of a vital nutrient can be as detrimental as under fertilization. Over fertilization increases input costs, may negatively impact crop quality and excess fertilizer runoff can be damaging to the environment. Under fertilization does not allow the growing crop to achieve its potential yield and quality. Organic Matter is defined as carbonaceous remains in the soil made up of organisms and organic compounds which can be mineralized into primary and secondary nutrients essential for plant growth.

Organic matter mapping using remotely sensed images

Southern Minnesota Beet Sugar Cooperative


Methods of forming transistor devices having an increased gate width dimension are disclosed. In one example, the method includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active region in the substrate, performing an ion implantation process on the isolation structure to create a damaged region in the isolation structure and, after performing the implantation process, performing an etching process to remove at least a portion of the damaged region to define a recess in the isolation structure, wherein a portion of the recess extends below an upper surface of the substrate and exposes a sidewall of the active region. The method further includes forming a gate insulation layer above the active region, wherein a portion of the insulation layer extends into the recess, and forming a gate electrode above the insulation layer, wherein a portion of the gate electrode extends into the recess.

1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming transistor devices having an increased gate width dimension.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NFET and PFET transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NFET transistors and create a compressive stress in the channel region for PFET transistors). Stress engineering techniques typically involve the formation of specifically made silicon nitride layers that are selectively formed above appropriate transistors, i.e., a layer of silicon nitride that is intended to impart a tensile stress in the channel region of an NFET transistor would only be formed above the NFET transistors. Such selective formation may be accomplished by masking the PFET transistors and then blanket depositing the layer of silicon nitride, or by initially blanket depositing the layer of silicon nitride across the entire substrate and then performing an etching process to selectively remove the silicon nitride from above the PFET transistors. Conversely, for PFET transistors, a layer of silicon nitride that is intended to impart a compressive stress in the channel region of a PFET transistor is formed above the PFET transistors.
FIGS. 1A-1D depict an illustrative prior art transistor 100. FIG. 1B is a plan view of the transistor 100 while FIGS. 1A and 1C are cross-sectional views of the transistor taken as indicated in FIG. 1B. FIG. 1D is an enlarged view of a portion of the transistor 100. As shown in FIGS. 1A-1C, the illustrative transistor 100 is formed above a semiconducting substrate 10 in and above an active area defined by an illustrative isolation structure 11. The transistor 100 generally comprises a gate insulation layer 12, a gate electrode 14, a sidewall spacer 16, a source region 18A and a drain region 18B. The approximate gate length (or channel length) 13 of the transistor 100 is depicted in FIG. 1A, whereas the approximate gate width (or channel width) 15 of the transistor is depicted in FIG. 1C.
Various materials of construction and techniques may be employed in forming the illustrative transistor 100. For example, the gate insulation layer 12 may be comprised of a variety of different materials, such as, for example, silicon dioxide, a so-called high-k (k greater than 10) insulation material, etc. Similarly, the gate electrode 14 may also be of a material such as polysilicon or amorphous silicon, or it may be comprised of one or more metal layers that act as the gate electrode 14. The gate electrode structure for the transistor 100 may be made using either so-called "gate-first" or "gate-last" techniques.
FIG. 1D is an enlarged view of a portion of the transistor 100 wherein the gate insulation layer 12 and the gate electrode 14 pass over the isolation structure 11. In one illustrative embodiment, the isolation structure 11 is a trench isolation structure that is performed using well-known techniques. Typically, a pad oxide layer (not shown) will be formed on the substrate 10 followed by the formation of a so-called pad nitride layer (not shown) on the pad oxide layer. The pad nitride layer is then patterned (using a patterned photoresist mask) to define a patterned hard mask. An etching process is then performed through the patterned hard mask to define a trench in the substrate 10. An insulating material, such as silicon dioxide, is then blanket deposited across the substrate 10 so as to over-fill the trench. A chemical mechanical polishing (CMP) process is then performed using the patterned hard mask layer as a polish stop layer to remove the insulating material that is positioned outside of the trench. The patterned hard mask is then removed. The resulting isolation structure 11, a so-called shallow trench isolation (STI) structure, is formed in the substrate 10 and it serves to electrically isolate the transistor 100 from other devices.
Although not depicted in FIGS. 1A-1D, due to the manner in which the isolation structure 11 is formed, the upper surface of the isolation structure 11 is typically above the surface 10S of the substrate 10. Ultimately, the transistor 100 will be subjected to many additional processing operations, such as etching and cleaning operations, which consume some of the isolation structure 11. As shown in FIG. 1D, these cleaning and etching processes result in so-called illustrative "divots" 21 in the isolation structure 11. In some cases, such divots 21 may have a depth 23 of about 1-2 nm, depending on the particular application. Depending upon the extent and location of such divots 21, the isolation function provided by the isolation structure 11 may be compromised. Ideally, none of the isolation structure 11 would be consumed in subsequent processing operations, however, that is not the case in real-world semiconductor manufacturing operations.
The present disclosure is directed various methods of forming transistor devices having an increased width dimension.

Method of forming transistor with increased gate width


An electronic apparatus includes a processor configured to select a type of an object subject to measurement; calculate a first distance to the object, based on output of a first sensor configured to detect passing of the object; calculate a second distance to the object, based on output of a second sensor configured to detect passing of the object; obtain based on the first distance, a first time point at which the object passes the first sensor; obtain based on the second distance, a second time point at which the object passes the second sensor; and calculate based on the first and second time points and a distance between the first and second sensors, a velocity of the object. The processor drives the first and second sensors at measurement time intervals corresponding to the type, and causes the first and the second sensors to detect the passing of the object.

According to one conventional apparatus that measures the velocity of a moving object, three or more trajectory weight measuring units are disposed along a direction in which a vehicle travels and the velocity of the vehicle is calculated based on differences of the times measured by the trajectory weight measuring units (see, e.g., Japanese Laid-Open Patent Publication No. 2001-50801). According to another apparatus, one infrared sensor are disposed to measure the time that elapses from the time that the head of a train passes a point until the time that the tail of the train passes the point and the velocity of the train is computed based on the detected time that elapses and the length of the train as determined by the formation of the train (see, e.g., Japanese Laid-Open Utility Model No. H6-28739).
However, according to the one conventional apparatus, the velocity is calculated based on the weight of the object subject to measurement and therefore, a problem arises in that the velocity cannot be measured of an object whose weight cannot be measured. For example, the velocity cannot be measured of an object that is not in contact with the ground such as a head of a golf club, a bat, or a tennis racket that is being swung. The other conventional apparatus calculates the velocity based on the length of the object subject to measurement and therefore, a problem arises in that the velocity cannot be measured of an object whose length is not known in advance. For example, a problem arises in that the velocity cannot be measured of an object such as the head of a golf club whose length differs according to club.

Electronic apparatus, mobile terminal, and velocity measuring method


A period from when switching elements S1, S4 at first diagonal positions in a full-bridge inverter are turned off at the same time to when switching elements S2, S3 at second diagonal positions are turned on at the same time, is defined as T1, and a period from when the switching elements S2, S3 at the second diagonal positions are turned off at the same time to when the switching elements S1, S4 at the first diagonal positions are turned on at the same time, is defined as T2. With a total length of T1 and T2 set to be constant, the lengths of T1 and T2 are controlled to be changed every switching cycle.

In an isolation DC/DC converter having a full-bridge inverter and a rectification circuit in combination, when all switch elements are OFF, a resonance phenomenon occurs between a parasitic capacitance of each switch element, and a leakage inductance and a parasitic capacitance of a transformer. Turn-on voltage varies depending on the timing of turning on, and thus switching loss varies. Since a cooling device is designed at the maximum value of switching loss, the size of the cooling device is increased and the cost thereof is increased.
In order to solve the above problem, the following power conversion device is disclosed. A first OFF period is defined as a period in which all switching elements are OFF from when a switching element of an upper arm in a first series circuit and a switching element of a lower arm in a second series circuit are turned off to when a switching element of a lower arm in the first series circuit and a switching element of an upper arm in the second series circuit are turned on, and a second OFF period is defined as a period in which all switching elements are OFF from when the switching element of the lower arm in the first series circuit and the switching element of the upper arm in the second series circuit are turned off to when the switching element of the upper arm in the first series circuit and the switching element of the lower arm in the second series circuit are turned on. The first OFF period and the second OFF period are set to be different from each other, and the first OFF period and the second OFF period are adjusted so that turn-on operation is performed when the drain-source voltage of any of the switching elements reaches a local minimum (for example, Patent Document 1).


A hybrid single-phase variable reluctance motor (31) has a stator (33) having a plurality of inwardly salient teeth (41A-41D) terminating at a central bore (37). The teeth are arranged in generally diametrically opposed pairs of teeth and are generally evenly spaced around the bore. A phase winding (43) is operatively associated with one pair of the stator teeth. The winding, when energized, causes a temporary magnetization of the stator teeth. A rotor (35) is disposed for rotation in the bore and has outwardly salient teeth (45A, 45B) generally diametrically opposed to each other. A permanent magnet (53) is disposed adjacent the bore at the end of one tooth (41D) of a second pair (41C, 41D) of stator teeth. One tooth (41D) of the second pair of stator teeth is offset with respect to a longitudinal axis (A.sub.1) of the second pair of teeth. This offset acts to eliminate a stable detent position in which the rotor could otherwise "park" itself when it stops running. Parking in such a position makes it difficult to restart the motor.

This invention relates to variable reluctance motors and, more particularly, to single-phase variable reluctance motors in which a motor pole is shifted to improve the torque profile of the motor.
In U.S. Pat. No. 5,122,697, which is assigned to the same assignee as the present application and which is incorporated herein by reference, there is disclosed a hybrid single-phase variable reluctance motor. A particular problem which the motor described therein is designed to solve is improvement in starting of the motor. This is because these types motors have a minimum reluctance position from which, if the rotor stops in that position, it is difficult to generate torque to start the motor. While various embodiments of the invention are described, in general, the motor is designed to have the rotor come to rest at a preferred position from which it is easy to start the motor.
While the motor of this invention works well for its intended purpose, some problems still persist. One, for example, is that the rotor may still have a stable detent or minimum reluctance position from which it is difficult to start the motor if the rotor "parks" there. While this problem is no longer as severe as in prior art single-phase variable reluctance motors which the motor of the 5,122,697 patent is designed to replace, it nevertheless can still be occur. One contributor to this problem is the type of bearings used in the motor. Typically these are either ball bearings or sleeve bearings. Each type bearing has a frictional load band. The actual amount of friction is a function of motor speed; but in general, at normal operating speeds, self aligning sleeve bearings are subject to 2-3 times the amount of friction as roller bearings. There is a critical region where the rotor must not stop if the motor is to start again. This region is where both the Hall effect device is not activated and where negative torque by the coil excited poles would result. The magnet torque available in this critical region must be sufficient to overcome the load friction due to the bearings or the rotor will stop in this area. The motor will not start if this should occur.
A second problem deals with the noise generated by motor "ovalizing". Motors are made such that the stator and rotor assemblies are installed within a shell or frame. In the typical two-pole motor construction of single phase variable reluctance motors, forces are produced as the rotor and stator poles come into alignment which produce an inward or pulling force on the lamination back iron at the location of the poles, and an outward or pushing force on the shell and lamination back iron at the point 90 electrical degrees from the poles. These forces cause the shell, which is generally circular in cross-section to distort into an oval shape. The metal flexure resulting from the distortion produces noise. In tests, this noise level has measured as high as 45 dba. This is an undesirable level.

Shifted pole single phase variable reluctance motor


Methods, computer readable media, and apparatuses for providing trusted services management using a hybrid service model are presented. According to one or more aspects, a first transaction log of a first secure element included in a mobile computing device may be received. The first secure element may be provisioned with first secure information provided to a user of the computing device by a first entity, such as a first financial institution. Subsequently, a second transaction log of a second secure element included in the mobile computing device may be received. The second secure element may be provisioned with second secure information provided to the user of the computing device by a second entity different from the first entity, such as a second financial institution, for instance. In some arrangements, incentive offers may thereafter be provided to the user based on the first transaction log and the second transaction log.

Trusted Services Management (TSM) is a set of technologies that supports activities generally related to transferring information that might typically be stored in a person's physical wallet, such as the person's credit card numbers, debit card numbers, driver's license information, and so on, to a secure element on a mobile computing device, such as a MicroSD card or a Near Field Communications (NFC) sticker associated with a smartphone. Currently, some TSM services are offered to organizations, such as financial institutions, as hosted services managed by third party vendors. In dealing with third party vendors, however, organizations, such as financial institutions, may have to take additional measures to implement TSM services, which may increase the cost and complexity associated with providing such services, while decreasing revenue and information security.

Providing trusted services management using a hybrid service model


Lighting apparatuses include an enclosure around first and second light engines. The enclosure has a diffuser over first, second and third regions. The first and second regions are separated by the third region; a first light spectrum is emitted from the first region; a second light spectrum is emitted from the second region; and a mixture of the spectrums is emitted from the third region. In some embodiments, the first spectrum has a CCT≥7000K; the second spectrum has a CCT≤6500K. In some embodiments, the first spectrum has a first CCT≥3500K; the second spectrum has a second CCT≤6500K; the second CCT<first CCT and the difference between the CCTs is at least 1000K. In some embodiments, the first spectrum has a color bounded by a first set of chromaticity coordinates, and the second spectrum has a color bounded by a second set.

Retinal ganglion cells (RGC) take neurotransmitter information from the inner and outer layers of the retina and potentiate action firing potentials to the visual cortex of the brain. Approximately 1% of RGCs contain an intrinsic photopigment melanopsin, with peak in vivo sensitivity at around 490 nm. These intrinsically photosensitive retinal ganglion cells (ipRGCs) project information to different portions of the brain and contain signals from both melanopsin and rods and cones. These ipRGCs mediate physiological effects of light beyond just vision.
There are multiple subtypes of ipRGCs, classified by dendrite morphology. Each subtype appears to mediate a different physiological effect. Some of these effects are direct and some are indirect. An example of a direct effect is melatonin suppression, where light will instantaneously suppress melatonin with exposure. An example of an indirect effect is circadian alignment, in which circadian rhythms will align in response to a whole day's light exposure, not just a single short duration of light exposure. The resulting circadian shift from this light exposure will present itself on the following day.
Melanopsin is a type of photopigment belonging to a larger family of light-sensitive retinal proteins called opsins and is found in ipRGCs of humans and other mammals. Melanopsin plays an important non-image-forming role in the photoentrainment of circadian rhythms as well as potentially many other physiologic functions. Stimulation of melanopsin-containing ipRGCs contributes to various reflexive responses of the brain and body to the presence of light. Melanopsin photoreceptors (OPN4) are sensitive to a range of wavelengths and reach peak light absorption at wavelengths around 480-500 nanometers (e.g., 490 nm). Melanopic light, that is light corresponding to the melanopsin action spectrum, including particularly the wavelengths in the 480-500 nm region, is important for non-visual stimuli including physiological and neurological effects such as pupillary light reflex and circadian entrainment and/or disruption. Time-coordinated exposure, including over-exposure and under-exposure to melanopic light, can be used to entrain and facilitate healthy circadian rhythms in humans and other mammals.
Circadian related photoreceptors are located throughout the retina. However, subtypes may be located in different regions within the retina. This has been evidenced by direction-dependent physiological effects, such as melatonin suppression. Melatonin related photoreceptors are most sensitive in the lower hemisphere of the retina. Selective stimulation of these photoreceptors is possible by directing illumination, and specifically melanopic light, towards or away from the region of the retina where ipRGC subtypes are most concentrated or most sensitive or responsive in order to mediate a specific physiological response. Equivalent Melanopic Lux (EML) is a metric for measuring the biological effects of light on humans. EML as a metric is weighted to the ipRGCs response to light and translates how much the spectrum of a light source stimulates ipRGCs and affects the circadian system. Melanopic ratio is the ratio of melanopic lux to photopic lux for a given light source.
The variation of the intensity of light output has a relatively straightforward and understandable effect. Namely, higher or lower light intensities incident on the human visual system provide greater or lesser biological stimulation respectively (e.g., with respect to circadian rhythms), and the combination of both color variation (e.g., via spectral tuning) and intensity variation can create complementary, and in some cases, synergistic biological effects. However, spatial distribution is a factor that adds a great deal of complexity and potential cost to lighting design. Scientific studies have shown that light emanating from above the horizon has high biological significance, related to melatonin suppression, compared with light coming from below the horizon. One consequence of this finding is that illumination emanating (e.g., reflecting) from above (e.g., from upper portions of walls and ceilings) has a higher biological significance compared to light emanating from below (e.g., from desktops and tabletops). This difference in biological effect is due at least in part to the fact that there is a greater concentration or sensitivity of ipRGC subtypes related to melatonin suppression in the lower hemisphere of the human retina than in the upper hemisphere. Thus, the biological effect of light impacting the lower hemisphere of the retina may be greater than the biological effect of the same light incident on the upper hemisphere.
Many systems exist for attempting to provide proper daytime cues for circadian entrainment (synchronization), such as light therapy devices or general lighting systems that simulate natural sunlight. Light therapy boxes are typically aimed at a user's eyes for intense exposure over a short duration. While these light therapy boxes have proven to be effective, compliance of use is generally very low due to various reasons including lack of comfort, time required to use, and the invasive nature of a large dedicated light therapy box. Some light therapy apparatuses include a diffusing surface to reduce the intensity and make the illumination more comfortable for the user. General lighting systems, such as ceiling lights and skylights, are also used to provide biological light for circadian entrainment, typically through indirect lighting such as light reflecting off walls. Thus, these lighting systems are designed to supply biological light for the overall space of the room in which they are installed.

Biological Innovation and Optimization Systems, LLC


A pneumatic tool has a body, a handle, a clip, a biasing member and a cap. The handle is formed on and extends from the body and has a free end and an annular shank extending from the free end. The clip is rotatably and slidably mounted on the shank and has a collar and a clip tab. The collar is rotatably and slidably mounted around the annular shank and has multiple teeth formed on a side of the collar facing away from the body. The clip tab extends from the collar. The biasing member is mounted around the annular shank and has two ends abutting respectively with the handle and the collar. The cap is detachably attached to the shank and has multiple recesses respectively corresponding to and engaging with the teeth on the collar.

1. Field of the Invention
The present invention relates to a nail gun, and more particularly to a nail gun with a clip assembly, wherein the position of the clip assembly on the tool can be adjusted.
2. Description of Related Art
To carry a nail gun conveniently, a clip is mounted on the tool to allow a user to hang the nail gun on a waist belt. With reference to FIG. 6, a conventional nail gun with a clip (44) substantially comprises a body (40), a handle (42), a nail magazine (43), a holding bar (44) and a clip (46). The handle (42) is formed on and extends from the body (40). The nail magazine (43) is attached to the body (40) for containing nail inside. The holding bar (44) is securely mounted between the handle (42) and the nail magazine (43), and the clip (46) is securely attached to the holding bar (44). Accordingly, the user can hang the nail gun on his/her waist belt with the clip (46).
However, the clip (46) is securely attached to the holding bar (44) and is not adjustable, such that the clip (46) is not versatile in use.
To overcome the shortcomings, the present invention tends to provide a nail gun with an adjustable clip assembly to mitigate or obviate the aforementioned problems.

Nail gun with an adjustable clip assembly


The apparatus is of the type having a double column and a mixing column. The latter is fed at the bottom portion with auxiliary air that is compressed at a pressure different from that of the mean pressure column, and at the top by means of a liquid withdrawn from the bottom of the low pressure column and pumped at the same pressure as the auxiliary air. Impure oxygen is withdrawn at the top of the mixing column as production gas, and substantially pure oxygen is produced at the bottom of the low pressure column.

(a) Field of the Invention
The present invention relates to the technology of air distillation.
(b) Description of Prior Art
Some industrial applications require important quantities of impure oxygen under various pressures: gasifying of carbon, gasifying of petroleum residues, direct reduction-melting of iron minerals, injection of carbon in blast furnaces, metallurgy of non-ferrous metals, etc.
On the other hand, some industrial applications require the simultaneous supplying, in large quantities, of practically pure oxygen and of impure oxygen under different pressures. This is for example the case of steel mills having oxygen converters and in which the blast furnace is supplied with oxygen or oxygen enriched air.
The invention aims at fulfilling such means in an economical manner, i.e. permitting, with relatively low investment and energy consumption, to produce impure oxygen at a purity and a pressure which are selected at will and, if necessary, the production of practically pure oxygen.

Process or apparatus for distilling air and application in feeding gas to a steel mill

L'Air Liquide, Societe Anonyme Pour L'Etude et L'Exploitation Des Procedes Georges Claude


A method for use in characterizing a digital imaging system (53) having an array of imaging elements (35), and in particular for measuring the modulation transfer function (sometimes called the spatial frequency response) even in directions (33) at large angles to both horizontal rows and vertical columns of the array of imaging elements (35), wherein at large angles compared to either horizontal rows or vertical columns of the array of imaging elements (35)—and even at angles other than for directions lying along a diagonal to the array of imaging elements—only non-interpolated readings of the imaging elements (35) are used in determining a supersampled characterization of the digital imaging system (53).

The prior art—and in particular ISO 12233, "PHOTOGRAPHY—ELECTRONIC STILL PICTURE CAMERAS—RESOLUTION MEASUREMENTS," first edition, published Sep. 1, 2001—describes a technique for estimating a modulation transfer function (MTF) in the horizontal or vertical direction of a digital camera based on imaging a sharp edge slightly slanted when compared with the MTF measurement direction. An MTF is, in brief, the ratio of the image modulation to the object modulation at all spatial frequencies, i.e. as a function of spatial frequency or, in other words, as a function of e.g. lines per unit distance, and can be different in different directions in the image, and so is usually provided along a particular direction. FIG. 1 shows an example of a MTF for an imaging system. The MTF is the Fourier transform of what is called the line spread function, which indicates the variations in intensity in an image produced by an imaging system when imaging a line. The line spread function is the one-dimensional counterpart to what is called the point spread function, which indicates the variations in intensity in an image produced by an imaging system when imaging a point. The MTF is sometimes referred to as the spatial frequency response (SFR), as in IS012233. More generally, the MTF (and so the SFR) is the magnitude of the (usually complex-valued) optical transfer function.
The method described in ISO 12233 was intended for use for characterizing digital imaging systems using a two-dimensional array of columns and rows of imaging elements, i.e. charge-coupled devices (CCDs) or other kinds of devices such as complementary metal oxide semiconductor (CMOS) devices, all called here pixels, that respond to light in proportion to the intensity of the light by storing a corresponding amount of charge, the value of which is read in providing a human-readable/viewable image.
(The actual pixel values in the image are typically produced from the values read out from the imaging element by applying some amount of image data processing. In particular, as defined also in ISO 12233, the MTF algorithm typically first linearizes the image data. Because image sensor response typically has a nonlinear correspondence between object luminance and image data values, the edge response of the image can be distorted. When the nonlinear response is known, the image data can be corrected to have a linear response, thus making MTF results more comparable in different regions of the image.)
The slightly slanted edge method of ISO 12233 is, in brief, as follows: First, a slightly slanted edge (say nearly vertical, with perhaps a 5-degree slant) is imaged by the digital imaging system being characterized so as to cause each of the imaging elements of the array to provide as an output a signal corresponding to the amount of light arriving at the imaging element during the imaging process. Each row of imaging elements (horizontal scan line) from a small area across the imaged edge gives an approximation to the edge spread function of the system. The line spread functions are obtained by differentiating the edge spread functions. The centroids of the line spread functions are computed to give an estimate of the location of the edge on each scan line. To smooth the data a straight line is fit to the centroid positions. In what amounts to a process of projecting the data along the edge onto a single horizontal line and thereby average/supersample the smoothed edge spread functions, each horizontal scan line is then translated by the amount estimated from the fit, and a supersampled (e.g. by a factor of four) edge spread function is then obtained by binning the translated scan lines (i.e. by putting groups of four outputs in a respective bin). Differentiation then gives a supersampled line spread function. The MTF is then obtained as the Fourier transform of the supersampled line spread function. So first edge spread functions are determined for each scan line, then smoothed, then averaged, and then a line spread function is determined, which is finally transformed into the MTF—called the SFR in ISO 12233—and might be expressed as lines per unit distance able to be displayed by the imaging system (hence the "spatial frequency" terminology).
As indicated, ISO 12233 requires that the slanted edge be only slightly slanted (with respect to either the horizontal rows of a digital imaging system, or with respect to the vertical columns). Thus, ISO 12233 allows estimating only horizontal and vertical slices of an MTF. However, in order to obtain a good description of the optics of a digital camera, measurements in other directions are useful.
What is needed is a way to estimate for a digital imaging system slices of the MTF at arbitrary angles relative to the rows or columns of the imaging elements. The prior art—Reichenbach, et al., CHARACTERIZING DIGITAL IMAGE ACQUISITION DEVICES, Optical Engineering, Vol. 30, No. 2, February 1991—provides a method for making diagonal measurements, and, in principle, measurements at an arbitrary angle. However, Reichenbach discloses simply "assembling scans" at an appropriate angle (see section 3.2), in what is there called a "knife edge" method. A scan therefore contains pixels from different rows and columns of the sensor/array of imaging elements of the digital imaging system. If the knife edge is arranged at a 45 degree angle, the scans are also at 45 degrees, and so provide pixel values at regularly spaced intervals, but at a spacing larger than the horizontal or vertical spacing of the imaging elements. The larger distance between the pixels of such a scan needs to be taken into account, but after that it is possible to use the standard algorithm. For scan lines at other than 45 degrees, however, interpolation may be needed because pixels do not necessarily lie along the scan lines. However, interpolation can introduce an additional factor contributing to the overall MTF, a factor that is purely an artifact of the measurement process.
Thus, what is really needed is a way to estimate for a digital imaging system slices of the MTF at arbitrary angles relative to the rows or columns of the imaging elements, without degrading the measurement of the MTF by the measurement process itself.

Method for characterizing a digital imaging system


Conventionally, a MONOS type nonvolatile memory is fabricated by subjecting a silicon nitride film to ISSG oxidation to form a top silicon oxide film of ONO structure. If the ISSG oxidation conditions are severe, repeats of programming/erase operation cause increase of interface state density (Dit) and electron trap density. This does not provide a sufficient value of the on current, posing a problem in that the deterioration of charge trapping properties cannot be suppressed.

1. Field of the Invention
The present invention relates in general to nonvolatile semiconductor storage devices (nonvolatile memories) capable of electrical programming and erase operation and methods of manufacturing the same. More in particular, it relates to a nonvolatile semiconductor storage device having a stacked structure of a silicon oxide film and a silicon nitride film and a method of manufacturing the same.
2. Description of the Related Art
The nonvolatile semiconductor memory devices (nonvolatile memories) having a stacked structure possessing a silicon oxide film on top of a silicon nitride film can roughly classified into two systems: one is a system that uses a non-conductive charge trap film; and the other is a floating gate system that involves accumulating charge in electrically-isolated conductive polycrystalline silicon.
First of all, a nonvolatile memory cell structure using a non-conductive charge trap film will be set forth with reference to FIG. 4. There are formed a semiconductor substrate 401 having a source region 404 and a drain region 405 formed by ion implantation and an insulating film 402 on the channel between these source and drain regions; furthermore a gate electrode 403 made of poly silicon is formed on the insulating film 402. The insulating film 402 is comprised of, in order from the substrate, a bottom silicon oxide film 402a, a silicon nitride film 402b, and a top silicon oxide film 402c. Conventionally, the nonvolatile memory of this type is the Metal-Nitride-Oxide-Silicon (MNOS) type without formation of the top silicon oxide film 402c. Representative examples of products using this structure include IC cards. Programming operation in an MNOS type nonvolatile memory is carried out by applying an appropriate positive voltage to the gate electrode 403 and injected electrons from the channel into the silicon nitride film 402b by direct tunneling through the bottom silicon oxide. At this time, the bottom silicon oxide film 402a has a film thickness of about 2 nm so as to allow direct tunnel phenomena to occur. The erase operation is performed by applying a suitable negative voltage to the gate electrode 403 to extract the electrons injected in the silicon nitride film 402b into the side of the substrate 401 directly through direct tunneling phenomena.
In this MNOS type nonvolatile memory, subjecting the surface of the silicon nitride film 402b to dry oxidation or ozone oxidation makes it possible to form an oxide film of as thin as about 2 nm (402c). As a result, the suppression of a leak current flowing from the SiN holding charge to the gate electrode 403 can improve charge trapping attributes, which is disclosed in Japanese Patent No. 3028635. This patent teaches that the dry oxidation method, however, requires heat treatment at a high temperature (900 to 1200° C.), so ozone oxidation is preferable that enables oxidation at a low temperature of about 350° C.
There have recently emerged growing needs for not only applications (IC cards, etc) in which environmental use temperatures are relatively low (100° C. and less), but nonvolatile memories that can have charge trapping attributes at high temperatures (e.g., 150° C.) and high operation speeds (e.g., on-board applications). An oxide film having a thickness of as thick as 4 nm or more placed on the SiN is essential for meeting these needs. As such, attention has been paid to, instead of the conventional MNOS type, the Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type having a thick oxide film (4 nm or more) placed on the SiN. The MONOS has a structure having a silicon oxide film on a silicon nitride film. Thus, the operation mode is quite different from the above MNOS type. For increased speed, programming is carried out that involves, for example, applying 0 V to the source region 404 and applying appropriate positive voltages to the drain region 405 and the gate electrode 403 to have the transistor switched on, and then accumulating hot electrons generated proximate the drain region 405 in the above silicon nitride film 402b. Read is performed that involves detecting a value of drain current flowing into the source region 404 and the drain region 405. In addition, the erase operation is carried out that involves applying an appropriate positive voltage to any of the substrate 401, the source region 404 and the drain region 405, and extracting the electrons accumulated in the above silicon nitride film 402b by use of the Fowler Nordheim (FN) tunnel phenomena. Alternatively, the erase operation is carried out that involves applying 0 V to the drain region 405 and applying an appropriate positive voltage to the source region 404, applying an appropriate negative charge to the gate electrode 403, and applying a high electric field to between the source region 404 and the gate electrode 403 to generate hot holes from the source region 404, and then implanting the holes into the above silicon nitride film 402b. In this MONOS type, the thicknesses of the bottom silicon oxide film 402a and the top silicon oxide film 402c are from about 4 to about 6 nm.
In the step of forming the above stacked ONO structure, the formation of the top silicon oxide film 402c has utilize, for example, a wet (external combustion type) oxidation method of the batch system. The method, however, has been shown unsuitable as a fine (e.g., a node of 90 nm or less) semiconductor device forming means, because of high-temperature, long-time processing resulting in a large thermal budget. Accordingly, single wafer type In-Situ-Steam-Generation (ISSG) oxidation (internal combustion pyrogenic oxidation) has gone mainstream that is capable of forming a thick oxide film in a short time and meets a larger aperture of the wafer. ISSG oxidation features the formation of radical oxygen immediately above the wafer. This enables the formation of a thick oxidation film at a high temperature in a short time. Well-known examples thereof include a disclosure of Japanese Patent Laid-open No. 2002-289715.
Next, the structure of a floating gate type nonvolatile memory cell will be described. As shown in FIG. 2, the method of fabricating the conventional floating gate type involves forming a semiconductor substrate 201 having a source region 206 and a drain region 207 formed by ion implantation, and a tunneling silicon oxide film 202 on the channel between these source-drain regions. The method further involves forming a floating gate electrode 203 comprised of poly-silicon thereon, forming an interlayer insulating film 204, and subsequently forming a control gate electrode 205 comprised of poly-silicon. The interlayer insulating film 204 includes a silicon oxide film (O) 204a, a silicon nitride film (N) 204b and a silicon oxide film (O) 204c, i.e., an ONO stacked structure, in order from the substrate. The programming of data in this flowing gate type nonvolatile memory cell involves applying, for example, 0 V to the source region 206, applying an appropriate positive voltage to the drain region 207, and further applying an appropriate positive voltage to the control gate electrode 205 to implant the hot electrons generated in the channel into the flowing gate electrode 203. Read is carried out by detecting a value of drain current that passes through the source region and drain region. The erase operation involves applying an appropriate negative voltage to the control gate electrode 205 and applying an appropriate positive voltage to the substrate 201, and then extracting electrons accumulated in the floating gate electrode 203 into the substrate 201 by use of FN tunnel phenomena. In the step of forming the above interlayer insulating film, the formation of the upper layer silicon oxide film 204c conventionally makes use of low pressure CVD, wet oxidation, and the like. A film fabricated by CVD, however, poses the problem of the presence of many electron traps. Wet oxidation requires heat treatment for a long period of time at a high temperature. This apparently presents the problem of forcing a large thermal budget. In addition, Japanese Patent Laid-open No. 5-152288 discloses the degradation of film quality by wet oxidation. The patent describes dry oxidation and ozone oxidation as means without degradation. It also discloses the use of ozone oxidation, which makes it possible to form a relatively thick (2.6 nm) oxide film as compared with the case of dry oxidation (1.1 nm), thereby well suppressing the interlayer leak current.

Method of manufacturing nonvolatile semiconductor memory device

Abstract: For the solution to the problem, the silicon nitride film is oxidized by means of a high concentration ozone gas to form the top silicon oxide film.


An information device performs data processing by executing program codes loaded in a memory with a central control unit. The information device includes a detection unit which detects a timing when any one of the program codes is called, a return address acquisition unit which sequentially acquires return addresses of the program codes loaded in the memory at the timing detected by the detection unit, and a termination unit which searches for an illegal access based on destination addresses that are respectively pointed by the return addresses sequentially acquired by the return address acquisition unit at the timing detected by the detection unit and which terminates the data processing when the illegal access is detected.

Generally, on information devices such as PC (Personal Computer) and WS (Work Station) there exists a control unit such as CPU (Central Processing Unit) which executes various types of data processing by sequentially executing program codes loaded in a working area of a storage unit such as a RAM (Random Access Memory). In recent years, illegal accesses to the information devices has been occurring by way of unauthorized execution using program codes created by malicious users.
Data managed by the information devices are generally assigned with access rights. Accordingly, the illegal accesses will not occur as long as the user has no access right. The illegal accesses will be possible if an unauthorized operation is made using a general program code assigned with the access rights to data. One known technique of this sort is using the so-called buffer overflow, allowing data at the time of execution of the program codes overflow out from a predetermined area allocated in the RAM or anything similar to RAM.
The illegal access using the buffer overflow will now be described in detail by showing comparison between the case where the program codes are properly ran and the case where the program codes are ran with an illegal action.
First, a model case where the program codes are properly ran will be explained referring to FIG. 9 and FIG. 10.
FIG. 9 is an illustration of an example source code of a program code. The source code in FIG. 9 starts with main( ) function, wherein strcpy_helloworld( ) function is called in main( ) function. In the source code, a character string "Hello!" is prepared in strcpy_helloworld( ) function, and is displayed on a monitor, computer screen and the like with the aid of printf( ) function in main( ) function. Note that the function herein means a subroutine or a subprogram having predetermined functionalities gathered into a module, and can be called in the main program as required.
The information about running the program code illustrated in FIG. 9 is stored in a call stack area allocated in the RAM. In the call stack area, the data are stored according to a LIFO (Last In First Out) or FILO (First In Last Out) structure.
FIG. 10 is an illustration example of an outline of the call stack area when the program code is running. As illustrated in FIG. 10, information about running the program code is stored downward into sequentially allocated areas.
For example, in the program code based on the source code illustrated in FIG. 9, Return Address1, ebp backup 1, char buf[8] and so forth are stored as a single stack frame, when main( ) function is processed. Next, when strcpy_helloworld( ) function in main( ) function is called, ReturnAddress2, ebp backup2, int i and so forth are also stored as a single stack frame.
ReturnAddress (return address) indicates an address value to which the process is to return upon the completion of a program. Return address is also an address value to which the process is to return upon completion of the subprogram or a function being called. ReturnAddress is automatically stored in the stack area by the CPU immediately after the execution of the program or immediately after the subprogram, i.e. function, is called.
Ebp is one type of CPU register, and indicates an address which is located just before the address of a temporary memory area currently being used. In the example illustrated in FIG. 10, ebp indicates addresses before char buf[8] and int i, and ReturnAddresses in the stack frame correspond to ebp. Accordingly, in the stack frame, by backing up the register value as ebp backup, an area in the stack frame can be easily used as a memory area for storing temporary data (variables and arrays).
In char buf[8], buf which is an array used in main( ) function is stored. The above-mentioned buf is an array which can store eight char-type (1 byte) variables, and 8-byte data can be stored in the above-mentioned buf. Int i is an int-type variable used in strcpy_helloworld( ) function.
Accordingly, by executing the above-mentioned program code, a stack frame for main( ) function is allocated in the stack area and a stack frame for strcpy_helloworld( ) function is allocated in the stack area. Then, the value of int i is sequentially incremented and the 6-byte character string "Hello!" is to be stored in char buf[8]. Next, upon completion of strcpy_helloworld( ) function, ReturnAddress2 is read out to return to main( ) function, and upon completion of main( ) function, ReturnAddress1 is read out and the program is terminated normally.
Next, a case where an illegal act took place when the program code is executed will be described with reference to FIG. 11 and FIG. 12.
FIG. 11 is a schematic diagram illustrating an example of source code of the program code. The program code illustrated in FIG. 11 is different from the program code illustrated in FIG. 9, in that a 12-byte data (11 characters+character string null terminator) "Hello World" is written in the array buf.
FIG. 12 is a schematic diagram illustrating an outline of the stack area when the program codes are executed. As illustrated in FIG. 12, in the stack area, an 8-byte area is allocated as an area for storing the buf array. Accordingly, when strcpy_helloworld( ) function is executed, data having a size larger than the allocated size to be is written. In such way, buffer overflow occurs when data having a size larger than the allocated size of memory is to be written in the memory. Note that the buffer overflow which occurs in the stack area is referred to as the stack-based buffer overflow.
In the stack area illustrated in FIG. 12, the allocation of areas is sequentially carried out downward, from the top to the bottom, and the writing of data into the allocated areas is carried out upward, from the bottom to the top. Accordingly, ReturnAddress1 and ebp backup are illegally overwritten with the 12-byte data "Hello World", if strcpy_helloworld( ) function is executed. When the content of ReturnAddress1 is rewritten with an address where an executable program code is located by the above mentioned overwriting process, ReturnAddress1 is read out upon completion of main( ) function and the program code is executed.
According to the source code illustrated in FIG. 11, the overflow is caused by the character string named "Hello World" which is defined in advance. However, in practice, there is a case where data received through a network port of a mail server or Web server, or data entered through a console or files, is stored into the buf array. In such case, an arbitrary program code may be executed by a malicious user through network, entry through a console, or entry through files, and thereby illegal access such as data theft and falsification may occur.
As a method of detecting such illegal access, one possible method is by detecting whether any illegal access is executed or not by inspecting the return addresses stored in the stack area and comparing the arrangement pattern of the return addresses under execution of the normal program and the arrangement pattern of the return addresses under operation of an attack code. For example, the program may be judged as normal, if a destination memory attribute pointed by the return address has a program code attribute, or if the memory areas have a non-writable attribute.
However, return-to-libc attack (see Non-Patent Document 1) may not be detected by the above-described method of detecting illegal access. The return-to-libc attack refers to a technique of making an illegal access by calling a function preliminarily stored in a computer without adding any malicious code into the program code.
FIG. 13 is a schematic diagram illustrating an example of an outline of the stack area under the return-to-libc attack, when executing the program codes illustrated in FIG. 11. As illustrated in FIG. 13, in the return-to-libc attack, the value pointed by the above-described return address, that is, the content of ReturnAddress1, is set to the top address of the normal function such as OS (Operating System) standard functions. If the return addresses in the stack area indicate memory areas for the program code, or if the memory areas have a non-writable attribute, the program including the return-to-libc attack may not be distinguishable from the normal program.
A possible attack could be an attack using the return-to-libc attack in which a predetermined program code is executed by combining program codes of programs which are stored in a storage unit of an information device in advance. Also in this method of attack, the return addresses in the stack area seem to have similar pattern as those in the return-to-libc attack, so that the program including the attack using the return-to-libc attack may not be distinguishable from the normal program.
Patent Document 1 discloses a technique using branch trace which is one of the CPU functions so as to detect an action of returning back to the top address of the OS standard function, when returning from the function which is being executed to the process of the function at a caller.

Information device, program, method, and computer readable recording medium for preventing execution of malicious program code