A method and apparatus for rotating wafers in a scrubber, wherein both sides of a wafer are scrubbed without slipping or hesitating. A rotating roller imparts rotary motion to a semiconductor wafer during a cleaning process wherein both sides of a wafer are scrubbed. The rotating roller and wafer contact at their outer edges and the friction between their outer edges causes the wafer to rotate. The roller has an outer edge with a groove. The wafer edge is pinched inside the groove to create enough friction that when cleaning solutions are applied the wafer does not slip and continues to rotate. Also, the groove allows the roller to pinch the wafer just enough so that when the roller reaches the flat of the wafer, the roller may regain the radius of the wafer without hesitating.

1. Field of the Invention
The present invention relates to semiconductor wafer processing, specifically the cleaning process of a semiconductor wafer.
2. Background Information
In the manufacture of semiconductor devices, the surface of semiconductor wafers must be cleaned of wafer contaminants. If not removed, wafer contaminants may affect device performance characteristics and may cause device failure to occur at faster rates than usual.
One system used to remove wafer contaminants is called a scrubber, wherein both sides of a wafer are scrubbed. In this particular type of scrubber a semiconductor wafer is scrubbed simultaneously on both sides by brushes. Since the wafer is being scrubbed simultaneously on both sides by the brushes there must be a way of holding the wafer in place and rotating the wafer so the entire surface of the wafer is cleaned. A mechanism used for this purpose is called a roller.
The scrubber, wherein both sides of a wafer are scrubbed usually comprises a conveyor type mechanism, rollers, and brushes. In general, the wafer lies flat on the conveyor mechanism and the conveyor mechanism moves the wafer into the brushes. While being scrubbed, the wafer is supported (or held horizontally) by the conveyor mechanism, brushes, rollers, or a combination thereof. As the wafer is being scrubbed by the brushes the roller rotates the wafer so the entire wafer surface may be cleaned. The roller itself is being rotated about its central axis by a stepper motor. The rotary motion of the roller is then transferred to the wafer when the edge of the roller comes into contact with the outer edge of the wafer.
FIG. 1 illustrates a prior art roller. The top and bottom surfaces 110 and 120 of the roller are generally flat and the outer edge 130 of the roller has a slight concave indentation (concave outer edge). As is shown in FIG. 1, the concave outer edge of the roller contacts the outer edge of the wafer. When the roller and wafer contact each other, friction between the edges is created, so that the rotation of the roller causes the wafer to rotate. As can be seen from the Figure, the wafer and roller are in essentially single point contact.
One problem with the prior art roller is that the roller/wafer contact may be insufficient, so that the wafer hesitates, i.e., fails to rotate. This problem is worsened when certain cleaning solutions are used, for example ammonium hydroxide (NH.sub.4 OH). The NH.sub.4 OH or other cleaning solution acts as a grease between the outer edge of the wafer and the outer edge of the roller, reducing the friction between the edges when they contact. Instead, the rotating roller continually slips off the edge of the wafer without imparting any motion to the wafer.
Another problem with the prior art roller is that the roller tends to stall (hesitate) when the roller is in the flat trying to regain the radius. FIG. 2 illustrates this problem. Most semiconductor wafers have a small portion of their outer edge which is flat, e.g. flat 251. When the roller 200 reaches the point P on the flat 251 the wafer stalls (hesitates) until the roller is able to regain the radius. In other words the wafer hesitates until the roller can reach the curved portion of the outer edge of the wafer 250. This problem arises because the roller is downstream of the brush, such that the brush pushes the wafer into the roller. Therefore, when the flat first encounters the roller, it is pushed into it such that the roller can continue to rotate the wafer along the flat (so long as the above described slipping does not occur). However, the prior art roller may not have enough of a grip to push the wafer back toward the brush to regain the radius.
If the wafer fails to rotate during the scrub operation, some areas of the wafer will not be scrubbed, so that the wafer is not cleaned to the level desired. An additional problem which may occur is that if the system relies on the roller to rotate the flat into a predetermined position for the next operation, the flat may be misplaced. For example, after the scrub operation, the wafer may next go to a spin dry operation where it is held by its edges. If the flat is misplaced, the wafer may not be held properly.
What is needed is a method and apparatus for rotating the wafers in a scrubber, wherein both sides of a wafer are scrubbed without slipping or hesitating.


Techniques for detecting label shift and adjusting training data of predictive models in response are provided. In an embodiment, a first machine-learned model is used to generate a predicted label for each of multiple scoring instances. The first machine-learned model is trained using one or more machine learning techniques based on a plurality of training instances, each of which includes an observed label. In response to detecting a shift in observed labels, for each segment of one or more segments in multiple segments, a portion of training data that corresponds to the segment is identified. For each training instance in a subset of the portion of training data, the training instance is adjusted. The adjusted training instance is added to a final set of training data. The machine learning technique(s) are used to train a second machine-learned model based on the final set of training data.

Machine learning is the study and construction of algorithms that can learn from, and make predictions on, data. Such algorithms operate by building a model from inputs in order to make data-driven predictions or decisions. Thus, a machine learning technique is used to generate a statistical model that is trained based on a history of attribute values associated with one or more objects. The statistical model is trained based on multiple attributes described herein. In machine learning parlance, such attributes are referred to as "features." To generate and train a statistical model, a set of features is specified and a set of training data is identified.
The accuracy of a machine-learned model largely depends on the quality and quantity of the training data. For example, if there are not enough training instances in the training data, then the model will not be able to make accurate predictions for inputs that are similar (but not identical) to the training instances. As another example, if the training instances do not reflect real-world scenarios, then the resulting model will not be able to make accurate predictions.
Changes in an environment for which predictions are made is natural and common. For example, a cloud service that monitors performance of, and resource consumption by, cloud applications may implement a model to predict how many computer resources of one or more types to allocate to each cloud application based on the cloud application's performance. Cloud application performance may change over time in response to changes in how the cloud application is used (e.g., what features are being leveraged), how frequently it is being relied upon by other applications and/or users, and the number of machines that are available for the cloud application to execute on.
Usually, changes in the environment cause minor shifts in the output labels. This is referred to as a shift in label distribution. "Labels" refer to not only the labels of training instances, but also to real-world results, irrespective of the output (predictions) of a machine-learned model. Input labels are labels that are part of the training data while output labels are actual labels as observed in historical results. For example, a machine-learned model is trained to predict whether an entity will perform a particular action in response to one or more events occurring. Also, about twenty entities typically perform the particular action each week, but only ten entities actually perform that action in the most recent week. Thus, there is a (output) label shift from twenty to ten. A shift in label distribution results in a decrease in the accuracy of the machine-learned model. For minor shifts in label distribution, a refresh of the machine-learned model is sufficient. A refresh involves generating new training instances based on recent data and retraining the machine-learned model based on the new training instances and older training instances.
However, for significant shifts in label distribution, model refreshment might not work well because a dramatic change in label distribution probably indicates a large change in feature weights or coefficients to derive the correct label from the feature set. Thus, the model learned from the historical data is likely to provide incorrect predictions. However, to completely rebuild the model, there is not sufficient recent data to generate new training instances, since most of the data was collected before the factor(s) that led to the significant label shift. Thus, refreshing the model may still result in inaccurate predictions on newly measured scoring data.
The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.

Label shift detection and adjustment in predictive modeling


A method and device are provided for taking a database snapshot using a fuzzy snapshot. In one example, the method includes starting and maintaining a transaction log of the database, starting and maintaining a fuzzy snapshot of the database without applying any hindering locks to the database, and restoring the database by applying the transaction log to the fuzzy snapshot.

Main memory database systems maintain a simple but potentially large, in-memory data structure that holds the data of the database. This type of database is typically between about 1 Gigabyte and about 4 Gigabytes in size, and cannot be larger than the memory of the particular computer because the database is in-memory. The memory utilized is standard RAM in standard servers.
in order to be able to recover such a database after a crash, the database maintenance system needs to ensure that all the information contained in memory is also on disk as a backup. Accordingly, the database maintenance system logs updates to the database. In other words, every time a change happens to the database, the database maintenance system logs the change into the log. When the database is restarted, the database maintenance replays the log. As can be imagined, after a relatively short time, the log can grow to be extremely long. Every time the database is rebooted, the database start time is longer than the previous reboot as the log grows.
To address this problem, the database maintenance software periodically takes snapshots of the database in order to reduce the recovery time when the database needs to be restarted. For example, after every 10,000 transactions or so, the database maintenance takes a snapshot of the database. After each snapshot, the database maintenance software starts a new log. Otherwise, without the snapshots, the database log would grow without bounds and the startup time would be proportional to the size of the database log. Using this snapshot method, when the database maintenance system needs to do a recovery, the system returns to the last snapshot and applies the log entries. The database maintenance system may thereby quickly recover a database. Continuing with the example above, at most, the database maintenance system has to restore a snapshot and replay 10,000 transactions.
Unfortunately, in order to take a snapshot, the database maintenance system must lock the database, write the entire database onto disk and unlock the database in order to start updating the database again. Meanwhile, real world implementations of databases are relatively large. Accordingly, as the database grows, it takes longer and longer to snapshot. So, the time to take a snapshot is much higher than the minimum request latency of updates to the database. For example, a database over about one Gigabyte requires a time for a lock that is too long for practical implementations of the database. For this reason, the database maintenance system cannot lock the database to take a snapshot of the database.
To address these problems, a proposed solution is to use some form of copy-on-write or partial locks. Copy-on-write is an optimization strategy used in computer programming. The fundamental idea is that if multiple callers ask for resources which are initially indistinguishable, you can give them pointers to the same resource. This fiction can be maintained until a caller tries to modify its "copy" of the resource, at which point a true private copy is created to prevent the changes becoming visible to everyone else. All of this happens transparently to the callers. The primary advantage is that if a caller never makes any modifications, no private copy need ever be created. A database maintenance system uses the copy-on-write concept hi maintenance of instant snapshots on database servers like Microsoft® SQL Server® 2005. As discussed above, instant snapshots preserve a static view of a database by storing a pre-modification copy of data when underlying data is updated.
Unfortunately, copy-on-write complicates certain implementations of database maintenance software. Also, partial locks still introduce unwanted latencies.

Restoring a database using fuzzy snapshot techniques


The present invention relates to a pharmaceutical composition for preventing or treating a muscle wasting-related disease comprising diaminodiphenylsulfone (Dapsone; DDS) or a pharmaceutically acceptable salt thereof as an active ingredient. The composition according to the present invention may be effectively used to prevent or treat a muscle wasting-related disease by increasing muscle mass, preventing muscle loss and effectively restoring muscle function.

The muscle mass in all people decreases by about 10-15% in 50-70 years of age and 30% or more in 70-80 years of age, resulting in decreases in muscle strength and function. This is called sarcopenia. Sarcopenia, a muscular disease that occurs in most elderly individuals, presents with the decrease in muscle mass with aging. When this senile sarcopenia is not treated, it causes a painful old age life due to a discomfort performance of physical function and can also cause various age-related diseases, including diabetes, obesity, cardiovascular diseases, osteoporosis and the like.
Various studies on the efficient control of sarcopenia have been conducted. It was found that treatment with, for example, growth hormone (GH), can increase muscle mass. However, this treatment is very expensive and cause some undesired side effects such as shortening average life expectancy. As one of the most efficient methods for delaying the progression of sarcopenia, exercise has been recommended, but it is very unsuitable for elderly or sickbed patients. Thus, there is an urgent need to develop a drug and technology for treating sarcopenia, which can induce the regeneration and differentiation of muscle.
Meanwhile, it was reported that diaminodiphenylsulfone (Dapsone; DDS) well-known as an antibiotic increases the life span of Caenorhabditis elegans by 20-30%. DDS is a substance synthesized one century ago, is well known as a therapeutic agent for leprosy and is used as an important drug for many other skin diseases.

Pharmaceutical composition for preventing or treating muscle wasting-related disease comprising diaminodiphenylsulfone or pharmaceutically acceptable salt thereof


A semiconductor apparatus includes a MOS transistor and a resistive element having insulative first polysilicon and conductive second polysilicon films, an insulating film for a resistive element, and a third polysilicon film. The second polysilicon film is formed in a region adjacent each side edge of the first polysilicon film, and has a contact hole formed therein. The third polysilicon film determines a resistance value of the resistive element, and is continuously formed on the second polysilicon film and the insulating film formed on the first polysilicon film. The MOS transistor is formed in an active region surrounded by the field insulating film, and includes a gate oxide film and a gate electrode including a polysilicon film formed as a lower layer with the second polysilicon film and a polysilicon film formed as an upper layer with the third polysilicon film. A method of making this semiconductor apparatus is also described.

1. Field
This patent specification describes a semiconductor apparatus and method of making the same, and more particularly a semiconductor apparatus with a stable contact resistance and a method of making the semiconductor apparatus.
2. Discussion of The Background
A highly integrated SRAM (static random access memory) and a hybrid LSI (large-scale integration) circuit with an analog circuit, typically use a relatively high resistive element made of a polysilicon film.
A resistive value of a resistive element is generally expressed by an equation;
R=(xcfx81/t)xc3x97(L/W),
wherein R represents a resistive value, xcfx81 represents a resistivity, t represents a film thickness, L represents a length of the resistive element, and W represents a width of the resistive element.
From the above equation, it is understood that an increase of one or both of the resistivity xcfx81 and the length L or a decrease of one or both of the film thickness t and the width W increases the resistive value R. A decrease of the film thickness t is useful as a method of stably increasing the resistive value R. However, it also causes problems such as those discussed below.
FIG. 1 is a schematic diagram showing a cross section view of a polysilicon thin film resistive element with a contact hole for connecting the thin film resistive element to a metal wiring. In FIG. 1, a resistive element pattern 41 is formed on a field oxide film 3 formed on a semiconductor substrate. The resistive element pattern 41 is made of a polysilicon film including an N-type or P-type impurity. On the resistive element pattern 41, an inter-layer insulating film 43 is formed. To form a contact to the resistive element 41, a relatively low resistive region 45 including a relatively high concentration impurity is normally formed to both sides of the resistive element pattern 41 to have a better electrical conductivity. A contact hole 47 is formed in the inter-layer insulating film 43 to the low-resistive region 45. A metal wiring layer 49 is formed on the inter-layered film 43. A conducting filler 51 fills in the contact hole 47 to electrically connect the low-resistive region 45 and the metal wiring layer 49.
When the polysilicon film constituting the resistive element 41 and the low-resistive region 45 are made thin to increase a resistance value of the resistive element 41, the low-resistive region 45 may unexpectedly be etched through by the dry etching used to form the contact hole 47. As a result, the bottom of the contact hole 47 comes through the low-resistive region 45 and reaches the base, the field oxide film 3, as shown in FIG. 2. In this case, a contact area between the conducting filler 51 filled in the contact hole 47 and the low-resistive region 45 is limited to a side portion 47a of the contact hole 47 and a contact resistance consequently increases. As a result, an attempt to make a desired resistive value by determining the length and width of the resistive element 41 fails and such a desired resistive value is not obtained.
One attempt to solve the above-mentioned problem is to make thicker the polysilicon film in the region forming the contact hole. This attempt is described, for example, in Japanese Laid-Open Patent Application Publication No. 05-055520, Japanese Laid-Open Patent Application Publication No. 06-069207, Japanese Laid-Open Patent Application Publication No. 10-032246, and Japanese Laid-Open Patent Application Publication No. 10-163430.
For example, a first background method described in Japanese Laid-Open Patent Application Publication No. 05-055520 is shown in FIG. 3. This method forms a thick polysilicon film 155 for a low-resistant portion on a first insulating film 103 (i.e., the field oxide film 3). The polysilicon film 155 includes an additive of a high concentration impurity to make an electrical connection in a wiring region via a metal wiring layer 149 and a contact portion 147 (i.e., similar in function to contact hole 47) for an electrode. After that, the polysilicon film 155 is etched to have an opening 153 for a high-resistive portion, reaching the first insulating film 103. Then, a thin polysilicon film 141 (i.e., similar in function to resistive element pattern 41) is formed to cover the entire surfaces of the first insulating film 103 including the opening 153 and the polysilicon film 155. The thin polysilicon film 141 is for a high-resistive portion and includes no impurity additives or a relatively low concentration impurity additive. After that, a second insulating film 143 (i.e., the inter-layer insulating film 43) is formed on the entire surface of the thin polysilicon film 141 and, in the second insulating film 143, the contact portion 147 for an electrode is formed.
In this way, the first background method attempts to avoid variations of the value of contact resistance by having the polysilicon film 155 underneath the contact portion 147 which may include a contact opening portion 157 coming through the thin polysilicon film 141 that constitutes a resistive element.
When the first background method is applied to a manufacturing process for a SRAM (static random access memory) or a hybrid LSI (large scale integration) circuit, for example, it is needed to form a polysilicon-made gate electrode for a MOS (metal oxide semiconductor) transistor in addition to the resistive element pattern which is the thin polysilicon film 141. This patent specification uses the term MOS for FET (field effect transistors) using a gate made of any conductive material such as a metal, a polysilicon, etc. When an electrode of the MOS transistor is formed with the thick polysilicon film 155, a residue film may be formed from the thin polysilicon film 141 on the side of the polysilicon electrode made from the thick polysilicon film 155. Such residue film on the electrically conductive film can significantly affect the characteristic of the transistor. To avoid the generation of such residue, the process may become excessively complex.
A second background method is described in Japanese Laid-Open Patent Application Publication No. 06-069207, and its procedure is shown in FIGS. 4 and 5. As shown in FIG. 4, a first polycrystalline silicon layer 255 (i.e., similar in function to thick polysilicon film 155) is formed on the insulating film 3 formed on the semiconductor substrate 1. The upper surface of the first polycrystalline silicon layer 255 is covered with a silicon dioxide film 259 serving as an insulating film, and a second polycrystalline silicon layer 241 (i.e., similar in function to resistive element pattern 41) is formed on the silicon dioxide 259 and the insulating film 3 of the substrate surface such that the second polycrystalline silicon layer 241 contacts by its side the silicon dioxide 259 and the insulating film 3.
With this arrangement, a multi-layered structure of the first and second polycrystalline silicon layers 255 and 241 is applied to the region of the wiring and the contact holes, and only the second polycrystalline silicon layer 241 is applied to the high resistive region. Therefore, as in the case of the first background method, the contact resistive value would not be affected by the second polycrystalline silicon layer 241 even if the second polycrystalline silicon layer 241 comes through around the contact opening area because there is the first polycrystalline silicon layer 255 underneath the second polycrystalline silicon layer 241.
As shown in FIG. 5, the second background method forms a gate insulating film 261 on the semiconductor substrate 1 as it forms the resistive element. Then, the first polycrystalline silicon layer 255 and the silicon dioxide film 259 are formed on the gate insulating film 261. After that, the second polycrystalline silicon layer 241 is formed to cover the first polycrystalline silicon layer 255 and the silicon dioxide film 259. Then, from above, an impurity ion is implanted to the semiconductor substrate 1 so as to form a diffusion region 263 serving as a source or a drain.
However, when the first polycrystalline silicon layer 255 is used as a gate electrode of the MOS transistor, the second polycrystalline silicon layer 241 which is of high resistivity directly contacts the side of the gate electrode, just as in the case of the first background method, causing similar problems.
Another attempt to solve the above-mentioned problem of the variations in the contact resistive value is to form a metal silicide layer only on a region in an upper surface of a thin polysilicon film where a contact hole is formed in order to avoid an etching leakage during the formation of the contact hole. This attempt is described, for example, in Japanese Laid-Open Patent Application Publication No. 05-029346 and Japanese Laid-Open Patent Application Publication No. 07-183526.
This attempt uses a fact that the etching rate of the metal silicide layer is lower than that of the silicon dioxide film and the inter-layer insulating film so that the etching of the metal silicide layer is completed during the etching process to form the contact hole.
For example, a third background method described in Japanese Laid-Open Patent Application Publication No. 07-183526 relates to a method of forming a contact on a thin film transistor and is applied to a process of forming a resistive element made of a thin film polysilicon. However, this document does not describes a method of forming a resistive element made of a thin film polysilicon and a MOS transistor on the same substrate. Therefore, when this method is applied to a process of forming a resistive element made of a thin film polysilicon and a MOS transistor on the same substrate, the same problem as with the first background method may occur. That is, a residue of the thin polysilicon film for the resistive element may remain on the side of the polysilicon side.
There is further another attempt to solve the above-mentioned problem of the variations in the contact resistive value. This attempt forms an inter-layer insulating film on a high resistive pattern and, after forming a contact hole, fills the contact hole with a silicon. This attempt is also described in Japanese Laid-Open Patent Application Publication No. 05-036624 and Japanese Laid-Open Patent Application Publication No. 05-235276, for example.
For example, Japanese Laid-Open Patent Application Publication No. 05-036624 describes a method in which an electrical contact is arranged in a diffusion area of a thin film transistor. According to this description, this method can form a good contact by again filling in the silicon filler even when the thin silicon film at the bottom of the contact hole is etched and is made even thinner during the forming process of the contact hole.
However, in this method, every contact hole is required to have a common diameter in consideration of the polysilicon injection. For example, when a contact hole has a diameter at least twice greater than the thickness of the silicon thin film, the silicon injection cannot be performed in a perfect manner and a desired contact cannot be achieved.
This patent specification describes a novel semiconductor apparatus which makes a contact resistance value stable. In one example, a novel semiconductor apparatus includes a semiconductor substrate, a resistive element, and a metal oxide semiconductor transistor. The semiconductor substrate is covered with a field insulating film. The resistive element is formed on the field insulating film. The resistive element includes an insulative first polysilicon film, a conductive second polysilicon film, a resistive-element-aimed insulating film, and a third polysilicon film. The insulative first polysilicon film is formed on the field insulating film. The conductive second polysilicon film is formed in a region adjacent to each side edge of the insulative first polysilicon film in which a contact hole is formed. The resistive-element-aimed insulating film is formed on the insulative first polysilicon film. The third polysilicon film for determining a resistance value is formed in a continuous manner on the conductive second polysilicon film and the resistive-element-aimed insulating film. The metal oxide semiconductor transistor is formed in an active region surrounded by the field insulating film on the semiconductor substrate. The metal oxide semiconductor transistor includes a gate oxide film and a gate electrode which is formed on the gate oxide and includes a multi-layered film. The multi-layered film includes a polysilicon film formed on the gate oxide as a lower layer when the conductive second polysilicon film is formed and a polysilicon film formed on the lower layer as an upper layer when the third polysilicon film is formed.
The resistive-element-aimed insulative film of the resistive element may be made of a silicon dioxide or a silicon nitride.
This patent specification also describes a novel method of making a semiconductor device which makes a contact resistance stable. In one example, this novel method includes the steps of first forming, second forming, third forming, fourth forming, first patterning, fifth forming, sixth forming, second patterning, seventh forming, and eighth forming. The first forming step forms a field insulating film for separating elements and an active region surrounded by the field insulating film on a semiconductor substrate. The second forming step forms a gate oxide film on a surface of the active region. The third forming step forms an insulative first polysilicon film on an entire surface of the semiconductor substrate. The fourth forming step forms a resistive-element-aimed insulating film on the insulative first polysilicon film. The first patterning step patterns the resistive-element-aimed insulating film so that the resistive-element-aimed insulating film remains in a region corresponding to a middle portion of a resistive element formed on the field insulating film. The fifth forming step forms a second polysilicon film at a position adjacent to the insulating first polysilicon film formed underneath the resistive-element-aimed insulating film by diffusing or implanting an impurity to provide a conductivity to the insulating first polysilicon film with a mask of the resistive-element-aimed insulating film. The sixth forming step forms a third polysilicon film determining a resistance value on an entire surface of the semiconductor substrate. The second patterning step patterns the third polysilicon film, the resistive-element-aimed insulating film, the second polysilicon film, and the insulating first polysilicon film to form a resistive element on the field insulating film, including the insulating first polysilicon film, the second polysilicon film adjacent to each edge side of the insulating first polysilicon film, the resistive-element-aimed insulating film, and the third polysilicon film, and a gate electrode of a metal oxide semiconductor transistor in the active region, including the second polysilicon film and the third polysilicon film. The seventh forming step forms an inter-layer insulating film on an entire surface of the semiconductor substrate. The eighth forming step forms a contact hole in the inter-layer insulating film in a region in which the second polysilicon film adjacent to each side of the resistive element and the third polysilicon film are multi-laying.
The resistive-element-aimed insulating film may be made of a silicon dioxide film or a silicon nitride film.

Semiconductor apparatus with a stable contact resistance and a method of making the semiconductor apparatus


A semiconductor structure including: a semiconductor substrate (18/19) having active regions (21) of devices (T1, . . . ) therein and/or polysilicon lines (23-1, . . .) formed. thereupon; a first thick passivating layer (26/27) formed above the substrate having a set of first metal contact studs (30-1, . . .) therein contacting at least one of the active regions (21) and/or the polysilicon lines (23-1, . . . ); the surface of the first contact studs is coplanar with the surface of the first passivating layer; a plurality of polysilicon lands (31-1, . . .) formed on the planar structure in contact with the first contact studs; the polysilicon lands are either highly resistive, highly conductive or a mix thereof; a second thick passivating layer (34/35) formed above the resulting structure having a set of second metal contact-studs (37-1 . . .) therein contacting at least one of the polysilicon lands and/or one of the first contact studs; the surface of the second contact studs is coplanar with the surface of the second thick passivating layer. a plurality of metal lands (38-1, . . . ) formed above the second thick passivating layer (34/35) in contact with the second contact studs; a final insulating film (39).. The structure of the present invention may be advantageously used in chips implementing four device SRAM cells with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology.. The present invention also relates to the method for fabricating the same.

Polycrystalline silicon (polysilicon) resistors are commonly used as load devices in a variety of digital and analog applications. Popular digital applications include semiconductor memory circuits such as Static Random Access Memories (SRAMs). FIG. 1 shows a conventional four device SRAM cell circuit referenced 1 with polysilicon load resistors. Two cross-coupled FETs T1 and T2, so-called the driver transistors, are connected between common node 2 tied to a first supply voltage Vs (usually the ground Gnd) and respective nodes 3 and 4, so-called charge storage nodes. These nodes 3 and 4 are connected to a common node 5 tied to a second supply voltage (usually a positive voltage Vc) respectively through load resistors R1 and R2. On the other hand, nodes 3 and 4 are also respectively connected to the bit lines BLT and BLC through FETs T3 and T4, so-called the access transistors. All FETs T1 to T4 are of the N type for best performance. The gates of the access transistors are connected to the word line WL, the potential of which controls FETs T3 and T4 for READ and WRITE operations. The circuit of FIG. 1 will be hereinafter referred to as the 4D/2 R SRAM cell.
The flexibility that is offered by polysilicon load resistors in the design of the 4D/2R SRAM chip layout allows a significant reduction in the cell size, which in turn, results in a greater integration density It is now a general practice in the industry to have the load resistors of 4D/2R SRAM cells formed by resistive polysilicon lands obtained from a very thin layer of either intrinsic or low doped polysilicon material. In addition, the polysilicon load resistors are stacked above the FETs for further increased integration density according to the advanced state of the art known to date. However, because these polysilicon load resistors must be fairly high-valued, say in the tera-ohms (10.sup.12 .OMEGA.) range, in order to decrease the current drawn by the cell, chip capacity appears to be limited to 1 megabits. Beyond 1 megabits, the polysilicon layer must be so thin that the process tolerances would be too difficult to control, consequently PFETs have to be used as load devices, but this is at the cost of a significantly more complicated manufacturing process.
FIG. 2 of the present application shows partial cross-sectional view of a typical structure of the prior art referenced 6, integrating the 4D/2R SRAM cell circuit of FIG. 1 with stacked polysilicon load resistors. Reference numeral 7 indicates the P type silicon substrate. Numerals 8 indicate the different field recess oxide (ROX) regions that are used to isolate the different active regions of the structure. Numerals 9 are active N+ implanted source and drain regions of the FETs. Numerals 10 indicate the gate dielectric layer, typically an SiO.sub.2 layer. The highly doped polysilicon gate electrodes of access FET T3 and driver FET T2 are respectively referenced 11-1 and 11-2. A polysilicon conductor referenced 11-3 is represented for sake of illustration. Conductor 11-3 overlies a ROX region 8 and makes an electrical contact with the source region 9 of FET T3. Gate electrodes 11-1 and 11-2 and conductor 11-3 result from the patterning of a first highly doped polysilicon layer 11 and they are covered by a thin insulating protective layer 12, except a small portion of gate electrode 11-2 which remains exposed. A small polycide (polysilicon converted in polysilicon silicide) land 13-1 is used to make a low resistivity interconnection between gate electrode 11-2, N+drain region 9 of FET T3, and one end of load resistor R1 formed by a highly resistive polysilicon land 14-1. Polysilicon land 14-1 is obtained after patterning a second polysilicon layer 14 of either intrinsic or low doped polysilicon material. Polycide land 13-1 is exemplative of the local interconnect scheme at an early mask level that is conventionally used to provide short connections: e.g. from one active region of a FET to the polysilicon gate electrode of another FET or strap connections between two adjacent active regions separated by a ROX region. Alternatively, conductor 11-3 could be made of polycide instead of highly doped polysilicon as well. The resistive polysilicon land 14-1 is protected by top insulating layer 15. This top insulating layer 15 is relatively thick, say about 500-1000 nm and is generally made of phosphosilicate glass (PSG). As such, the structure results from the FEOL (Front End Of the Line) processing. At this stage of the process, the silicon wafer may be stored before personalization. Elements that will now be described are formed during the personalization steps or BEOL (Back End Of the Line) processing. Layer 15 is provided with contact openings to allow appropriate contacting with the bit lines, and power busses connected to either Vc or Gnd, through metal contacts that correspond to the M1 mask level. As apparent from FIG. 2, the other end of resistor R1 is connected to the said second supply voltage Vc via metal contact 16-1. Conductor 11-3 is connected to bit line BLT via metal contact 16-2.
FIG. 3 shows a cross-section of the structure of FIG. 2 taken along line I--I. FIG. 3 reveals in particular the implementation of driver FET T1 whose polysilicon gate electrode is referenced 11-4. Polysilicon land 14-2 forming load resistor R2 is located atop of it, but isolated therefrom by protective layer 12. Numeral 13-2 is another polycide land making a low resistivity interconnection between two active regions 9 separated by a ROX region 8.
Structure 6 depicted in FIGS. 2 and 3, that is obtained through a standard CMOS manufacturing process, exhibits some major inconveniences, mainly because the resistive polysilicon lands are formed during the FEOL processing steps. As apparent from FIGS. 2 and 3, all the succeeding layers are deposited conformally which results in the typical "corrugated" relief aspect of the upper metal/insulator structure. In particular, polysilicon load resistors (e.g. R1) formed by a polysilicon land (e.g. 14-1) have a very irregular shape. The top insulating layer 15 could be planarized as taught in "An advanced SA BICMOS technology for high performance 1 Mbits ECL I/0 SRAMs" by W. R. Burger et al., IEEE proceedings IEDMP, p. 16.3.1 to 16.3.5, see in particular FIG. 1. However, this would necessitate a step of reflow at a relatively high temperature (about 800-900.degree. C.), that would change both the dopant distribution in the resistive polysilicon lands (e.g. 14-1) and polysilicon grain size thereof, which in turn, would modify value of the resistors (e.g. R1). It is a major characteristic of the structures of the prior art, to have the resistive polysilicon lands formed upon non-planar surfaces and before the PSG deposition takes place. In other words, the resistive polysilicon lands are fabricated during the FEOL processing steps.
In addition, should the photolithographic step that is used to delineate the resistive polysilicon lands, e.g. land 14-2 atop the gate electrode 11-4 of FET T1, be subject to misalignment, this in turn, would result in a misregistration between land 14-2 and gate electrode 11-4. This point is illustrated in FIG. 3, where the offset of land 14-2 in land 14-2', as a result of said misregistration, is shown. As a consequence, the offset polysilicon land 14-2' is not only subject to the well known "step or edge coverage" effect which may result in a break of the land, but also to a significant change in the land section, thereby preventing load resistor R2 from attaining a value that is necessary for an appropriate operation of the circuit of FIG. 1. In addition, misregistration also results in poor reproducibility from chip to chip.
Another important point is the trimming of the resistive polysilicon lands during the wafer processing. This step is usually completed in CMOS standard processes by implanting dopants to trim the resistivity of the resistive polysilicon lands at the high resistance value that is desired and to ensure that a good matching between the pair of resistors of a same cell is obtained. With structure 6 of FIG. 2, this objective is difficult to attain because both polysilicon layer 14 and protective layer 12 are very thin, e.g. about 50-100 nm. Layer 14 must be thin to permit achievement of high value resistors, and layer 12 has to be thin enough not to create additional undesired relief in the upper metal/insulator structure. As a result, the implant energy must be accurately controlled. Otherwise, implantation dopants will contaminate underlying FETs. In addition, thinness of protective layer 12 creates a problem of modulation of the value of the resistor (e.g. R2) by the underlying polysilicon gate electrode (e.g. 11-4).
Finally, as explained above, the structure of FIGS. 2 and 3 capitalizes on the local interconnect conductive pattern scheme formed at an early mask level. It is well known that this pattern is limited to very short distance connections and at the vicinity of the surface of the silicon wafer. This limitation causes a serious problem to the circuit designer, particularly in multilevel chips. It is also apparent from FIG. 2 that the fragile polycide land 13-1 is also subject to the above mentioned "edge coverage" effect due to the sidewall sharpness of polysilicon gate electrode 11-2. Moreover, formation of polycide lands 13-1 and 13-2 also necessitates a specific photolithographic step.
As a result, for all the above mentioned reasons, the reliability of semiconductor structures integrating the 4D/2R SRAM cells manufactured according to standard CMOS processes as well as the inherent limitations thereof are not satisfactory in many respects.

Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconductor chips and structures resulting therefrom

International Business Machines Corporation


According to one embodiment, energy manager includes first estimator, second estimator, creator and controller. First estimator estimates power amount of power generator. Second estimator estimates energy demand. Creator creates schedule of devices based on estimated power amount and energy demand. Controller controls the devices based on the schedule. Second estimator includes storage, extractor and calculator. Storage accumulates load data. Extractor extracts load patterns including different load data. Calculator calculates weight for each of extracted patterns. Creator includes simulator and scheduler. Simulator simulates evaluated value of each schedule based on the pattern and weight. Scheduler creates schedule based on evaluated value.

In recent years, new energy devices such as a Photovoltaic (PV) unit, a battery and a fuel cell (FC) are being introduced in houses. Technologies for HEMS (Home Energy Management Systems) or energy management apparatuses have also extensively been developed. Using technologies of this type enables to implement energy use optimization, energy saving, and cost reduction in customers such as houses.
Many energy management apparatuses estimate an amount of energy to be consumed by energy consuming devices and creates the operation schedules of home appliances, energy storage devices, energy generation devices, and the like (to be generically referred to as electrical devices hereinafter) based on the estimation result.
The energy management apparatus creates the operation schedule of an electrical device based on the estimated value of load electric energy (to be referred to as an estimated load hereinafter). Hence, if the estimation is wrong, it is impossible to create an appropriate operation schedule. For example, assume that a user has two life patterns: a pattern in which he/she goes out during the daytime, and a pattern in which he/she stays at home during the daytime. If an algorithm for the going-out pattern is used to create the operation schedule of an electrical device in the user's home, the estimated load for the at-home case is not accurate. Hence, the operation schedule is not appropriate. If a load estimation algorithm for the at-home pattern is used, the operation schedule in the going-out case is not appropriate.
The estimated loads in both patterns may be added with weighting coefficients such as at-home and going-out frequencies and averaged. However, an operation schedule created based on such an estimated load is eventually inappropriate for both the at-home pattern and the going-out pattern.

Renewable energy management using weighted load patterns


A variety of optical arrangements and methods of modifying or enhancing the optical characteristics and functionality of these optical arrangements are provided. The optical arrangements being specifically designed to operate with camera arrays that incorporate an imaging device that is formed of a plurality of imagers that each include a plurality of pixels. The plurality of imagers include a first imager having a first imaging characteristics and a second imager having a second imaging characteristics. The images generated by the plurality of imagers are processed to obtain an enhanced image compared to images captured by the imagers. In many optical arrangements the MTF characteristics of the optics allow for contrast at spatial frequencies that are at least as great as the desired resolution of the high resolution images synthesized by the array camera, and significantly greater than the Nyquist frequency of the pixel pitch of the pixels on the focal plane, which in some cases may be 1.5, 2 or 3 times the Nyquist frequency.

Image sensors are used in cameras and other imaging devices to capture images. In a typical imaging device, light enters at one end of the imaging device and is directed to an image sensor by an optical element such as a lens. In most imaging devices, one or more layers of optical elements are placed before and after the aperture stop to focus light onto the image sensor. Recently array cameras having many imagers and lenses have been developed. In most cases, multiple copies of the optical elements must be formed laterally for use in array cameras.
Conventionally, optical arrays can be formed by molding or embossing from a master lens array, or fabricated by standard lithographic or other means. However, the standard polymer-on-glass WLO and monolithic lens WLO manufacturing techniques have so far not been adapted for the specific high performance requirements of array cameras. In particular, some technical limitations of conventional WLO-processes need to be reduced, such as, for example, minimum substrate thickness requirements, inflexibility of where to place the aperture stop, accuracy, etc. The flexibility of such choices or processes needs to be increased in order to meet the high demands by array cameras otherwise such WLO techniques cannot be used to manufacture array cameras. Accordingly, a need exists for fabrication processes capable of accurately forming these arrays and for optical arrangements that give an increased flexibility in manufacturing so that the image processing software of these new types of array-type cameras can take advantage to deliver superior image quality at the system level.
The optical transfer function (OTF) of an imaging system (camera, video system, microscope etc.) is considered the true measure of an imaging system's performance, i.e., the resolution (minimum feature size or maximum spatial frequency that can be imaged with sufficient contrast) or image sharpness (the contrast at a given spatial frequency) obtainable by an imaging system. While optical resolution, as commonly used with reference to camera systems, describes only the number of pixels in an image, and hence the potential to show fine detail, the transfer function describes the ability of adjacent pixels to change from black to white in response to patterns of varying spatial frequency, and hence the actual capability to show fine detail, whether with full or reduced contrast. The optical transfer Function (OTF) consists of two components: the modular transfer function (MTF), which is the magnitude of the OTF, and the phase transfer function (PTF), which is the phase component.
In cameras, the MTF is the most relevant measurement of performance, and is generally taken as an objective measurement of the ability of an optical system to transfer various levels of detail from an object to an image. The MTF is measured in terms of contrast (degrees of gray), or of modulation, produced from a perfect source of that detail level (thus it is the ratio of contrast between the object and the image). The amount of detail in an image is given by the resolution of the optical system, and is customarily specified in line pairs per millimeter (Ip/mm). A line pair is one cycle of a light bar and dark bar of equal width and has a contrast of unity. Contrast is defined as the ratio of the difference in maximum intensity (Imax) and minimum intensity (Imin) over the sum of Imax and Imin, where Imax is the maximum intensity produced by an image (white) and Imin is the minimum intensity (black). The MTF then is the plot of contrast, measured in percent, against spatial frequency measured in Ip/rm. This graph is customarily normalized to a value of 1 at zero spatial frequency (all white or black).

This patent is subject to a terminal disclaimer.

Array cameras incorporating optics with modulation transfer functions greater than sensor Nyquist frequency for capture of images used in super-resolution processing


There are provided uses of an antibody directed to CX3CR1 and fractalkine. Killer lymphocytes can be readily identified, eliminated and separated by using an anti-CX3CR1 antibody. Further, there can be provided an antibody drug for suppressing chemotaxis and cytotoxic activity of killer lymphocytes by suppressing an interaction between CX3CR1 and fractalkine.

The present invention relates to applications of an antibody directed to CX3CR1, an antibody directed to fractalkine and fractalkine.
Killer lymphocytes play a central role in elimination of pathogens that invade into living bodies, abnormal cancer cells and so forth. However, their excessive cytotoxic reactions sometimes destroy normal tissues and they are tightly associated with onsets of autoimmune diseases such as nephritis, rheumatism, diabetes mellitus and myocarditis. Killer lymphocytes are classified into NK cells, CD8T cells, CD4T cells, γδ T cells, NKT cells and so forth, which commonly have a mechanism for inducing apoptosis of a target cell. The most known mechanism is mediated by perforin, which is a pore-forming protein, and granzyme B, which is a serine protease, released from cytotoxic secretory granules of the killer lymphocytes. Perforin forms pores in target cells, and then granzyme B is mobilized from these pores into the target cells and induces apoptosis of the target cells. Further, FasL and TARIL belonging to the TNF family are expressed or secreted on the cell surface of killer lymphocytes, bound to a receptor on the target cells and induce apoptosis. The cytotoxic mechanism and the activation mechanism of killer lymphocytes have been studied in detail, but little is known about factors for regulating migration of these cells in living bodies.
Infiltration of lymphocytes from the bloodstream into an inflammatory tissue is considered to require multistep reactions involving cell adhesion molecules and cellular chemotactic factors. In a typical infiltration mechanism, an initial reaction is contact and rolling of lymphocytes on endothelial cells. These are mainly performed by adhesion molecules called selectin. By performing the rolling, the lymphocytes become able to sense cellular chemotactic factors locally produced and presented on vascular endothelial cells. The cellular chemotactic factors activate adhesion molecules called integrin mainly by signal transduction via a G protein-coupled seven-transmembrane receptor and induce strong adhesion between lymphocytes and endothelial cells. Then, finally, lymphocytes are infiltrated into a tissue through intercellular spaces of endothelial cells.
Chemokines are major cellular chemotactic factors in living bodies and regulate tissue infiltration of lymphocytes through acceleration of cell motility and activation of cell adhesion molecules. Chemokines are classified into four subfamilies, CC, CXC, C and CXXXC, depending on the sequence of their first two cysteine residues. Members of the CC, CXC and C chemokine subfamilies are secretory proteins composed of about 70 amino acids. Although they themselves do not have activity as adhesion molecules, they can induce cell adhesion. Secreted chemokines are bound to seven-transmembrane receptors on the surface of target cells and activate integrin through a trimer G protein to induce cell adhesion and migration. The cell-type specific activity of a chemokine is primarily determined by whether its specific receptor exists in a certain cell subset. Therefore, cell-type specificity of a chemokine bound to the receptor can be revealed by closely investigating an expression state of a specific chemokine receptor on lymphocytes for each cell subset.
Recently, in addition to the previously revealed cellular chemotactic mechanism, a novel simple lymphocyte infiltration mechanism was identified. This mechanism is mediated by fractalkine, which is expressed on activated endothelial cells, and a seven-transmembrane receptor, CX3CR1, which is expressed on monocytes, NK cells and a part of T cells in the bloodstream. Fractalkine is the only member of the CXXXC chemokine subfamily and has distinct structural and functional characteristics, which cannot be observed in other chemokines. Fractalkine is expressed on the cell surface as a membrane-bound chemokine which has a chemokine domain, a mucin domain, a transmembrane domain and an intracytoplasmic domain. When the membrane-bound fractalkine binds to CX3CR1, it can solely mediate strong adhesion without mediation by selectins or integrins even at a physiological blood flow rate. That is, the fractalkine-CX3CR1 cellular infiltration system mediates, by one-step reaction, the same function as that of the multistep cellular infiltration mechanism mediated by selectins and integrins. Further, secretory fractalkine secreted by shedding from the membrane-bound fractalkine binds to CX3CR1 and induces activation of integrin and cell chemotaxis as in the case of the known chemokines.
Further, expression of fractalkine is induced by treating vascular endothelial cells with inflammatory cytokines such as TNF or IL-1. CX3CR1 is expressed on monocytes, most of NK cells and a part of T cells, but not on neutrophils. Therefore, the fractalkine CX3CR1-cellular infiltration system is considered to be an extremely efficient mechanism for recruiting a kind of immunocytes onto endothelial cells of a damaged tissue or into the tissue. However, kinds of cells migrated by the cellular infiltration system and actions of the cellular infiltration system in inflammatory reactions have not been analyzed.

Uses of anti-CX3CR1 antibody, anti-fractalkine antibody and fractalkine


The invention provides an apparatus and method for reducing a volume of sound that travels away from a volume of space that is proximate to an instrument, while limiting an amount of physical contact with the instrument and limiting change to characteristics of the sound being produced by the instrument.

Some musical instruments produce sounds that are considered too loud in some circumstances, when received by a human ear or by a microphone. For example, when playing percussion instruments in a small venue, such as by striking drums and cymbals. In some circumstances, being exposed to sound of a high volume is irritating to a listener and/or can cause damage to the hearing of a listener.
The discussion above is merely provided for general background information and is not intended to be used as an aid in determining the scope of the claimed subject matter.


A transmitter capable of suppressing a peak of a transmission signal includes a frequency domain acquisition unit for obtaining a frequency domain signal from the signal for transmission; and a level control unit for controlling a level of the frequency domain signal obtained by the frequency domain acquisition unit to suppress a peak in a time domain transmission signal. Further, the transmitter includes a time domain conversion unit for converting the frequency domain signal into the time domain transmission signal whose level has been controlled by the level control unit; and a transmission unit for transmitting the time domain transmission signal.

For example, in a wireless communications system, wireless signals are transmitted from a transmitter in a communication device for transmission and then received by a receiver of a communication device for reception.
FIG. 6 shows an exemplary configuration of a conventional transmitter. Herein, like parts as shown in FIG. 1, which will be described later in conjunction with an embodiment of the present invention, are designated by like reference numerals without limiting the scope of the present invention.
The transmitter shown in FIG. 6 has a limiter function for transmission signals and is capable of perform distortion compensation function for an amplifier 7.
As the distortion compensation for the amplifier 7, various methods to compensate distortion caused by the nonlinear characteristics of amplifiers may be used.
A limiter 41 and a LPF (Low Pass Filter) 42 different from those in FIG. 1 will now be described to explain a conventional method of peak suppression.
A modulated signal inputted from a modulator 1 to the limiter 41 via a multiplier 2 is delayed by a delay unit 51, and then is fed to both a peak suppression filter 53 and a peak detection unit 52. A peak of the modulated signal is detected by the peak detection unit 52, and the detection result thereof is sent to the peak suppression filter 53. Then, the modulated signal whose peak is suppressed by the peak suppression filter 53 based on the detection result is outputted to the LPF 42. Thereafter, an output signal from the LPF 42 is fed to a D/A (Digital to Analog) converter 4 and a delay unit 17.
Here, for example, according to a digital modulation/demodulation scheme with a non-constant envelope such as a QPSK (Quadrature Phase Shift Keying) scheme or a CDMA (Code Division Multiple Access) scheme, a peak may occur as shown in FIG. 7, which results in an amplifier distortion of the amplifier.
FIG. 7 schematically shows an exemplary carrier signal with a peak power. The horizontal axis indicates the time and the vertical axis indicates the amplitude (instantaneous power).
Further, FIG. 7 also shows the peak power and the average power.
In order to reduce such a peak as shown therein, a limiter for suppressing a peak component in the baseband or in the IF (Intermediate Frequency) band has been proposed, and has been used in the digital modulation/demodulation method with a non-constant envelope.
Meanwhile, frequency utilization efficiency is recently considered more important than amplifier efficiency. For example, it is not proper to use the conventional limiter for, e.g., a wideband CDMA scheme or to an OFDM (Orthogonal Frequency Division Multiplexing) scheme of high frequency efficiency, because the limiter may generate distortion to cause frequency interference, which significantly deteriorates wireless characteristics in the OFDM scheme. In such a case, a signal having an unsuppressed peak is inputted to the amplifier. To prevent this, a sufficiently large backoff is needed, which lowers the amplifier efficiency noticeably.
As a specific example, a mobile phone according to a PDC (Personal Digital Cellular) method as the second generation technology uses π/4 QPSK modulation and has the PAPR (Peak Average Power Ratio) of about 3 dB, whereas an OFDM modulated wave used in a wireless LAN (Local Area Network) or in a digital TV has a peak of 10 dB or more. Further, since the third (and later) generation mobile phone technology uses a wider band, it is expected that the PAPR will further increase.
(Patent Document 1) Japanese Patent Laid-open Application No. 2002-044054
As described above, there are demands for a transmitter having a limiter capable of suppressing a peak without generating frequency interference even for a high PAPR.
In response thereto, it has been suggested that the conventional limiter be improved to cope with a high PAPR. For example, in the transmitter shown in FIG. 6 suppresses a peak, and then the LPF 42 eliminates distortion. However, in this configuration since a peak may be further generated after a transmission signal passes through the LPF 42. To solve this problem, it has been proposed to provide a plurality of limiter 41 and a plurality of LPF 42 in a repetitive manner for performing the operations repeatedly.
However, the processing in this manner is too complicated, and it is difficult to install a transmitter with such a configuration.

Transmitter capable of suppressing peak of transmission signal


The invention is directed to an encapsulated fuel cell including a methanol source that feeds liquid methanol (CH3OH) to an anode. The anode is electrical communication with a load that provides electrical power. The fuel cell also includes a hydrogen peroxide source that feeds liquid hydrogen peroxide (H2O2) to the cathode. The cathode is also in communication with the electrical load. The anode and cathode are in contact with and separated by a proton-conducting polymer electrolyte membrane.

The present invention relates to the field of fuel cells. In particular, the present invention relates to electrochemical fuel cells where oxidation and reduction reactions occur causing changes in the free energy and electrical energy.
In an organic and air fuel cell, an organic fuel is oxidized at the anode and an oxygen source is reduced at the cathode. For example, the organic fuel may be methanol, formaldehyde, or formic acid, which is oxidized and reacted with water to produce carbon dioxide and H+ protons (or hydronium ions, H3O+). At the cathode, oxygen in air is reduced and combined with H+ protons (or hydronium ions) to form water. In the context of the invention, protons and hydronium ions are used interchangeably. An exemplary direct organic fuel cell is shown in U.S. Pat. No. 5,599,638 to Surampudi et al.
Surampudi et al. discusses the advantages and disadvantages of known indirect, or reformer fuel cells and direct oxidation fuel cells. It also discusses the problems associated with known electrode structures, and their fabrication and use in fuel cells thereof. For example, electrodes made by conventional methods lacked adequate porosity and wetting during use. Surampudi et al. solves such problems by employing a solid polymer membrane for conducting protons, such as a perfluorinated sulfonic acid polymer membrane. Preferably, the proton-conducting membrane is NAFION(trademark) which is a co-polymer of tetrafluoroethylene and perfluorovinylether sulfonic acid.
In Surampudi et al., the problems associated with prior organic fuel cells (i.e., toxicity, corrosiveness, expensive, poor performance, and complex electrode structure and fabrication) were overcome, in part, by employing the proton-conducting membrane. The primary benefit of using the membrane was that it became practical and feasible to use methanol as the organic fuel. Methanol is desirable because it is relatively non-toxic, non-corrosive, inexpensive and in abundant supply. Methanol also performs well providing a high current density. The use of methanol also allows the electrode structure and fabrication procedure to be simplified producing a more effective electrode.
However, there still exists a need for an organic fuel cell capable of using an alternative oxygen source. In some fuel cell applications, air is absent or available in only limited quantities. For example, submarines and other underwater applications have little to no oxygen available for fuel consumption. Low noise signature, high volume and high specific energy density are also desirable for such underwater applications. High energy fuel cells based on pure compressed hydrogen and oxygen gas are disadvantageous for several reasons. The compressed tanks present safety concerns. The compressed tanks are also heavy and take up a lot of space which are impracticable or undesirable for some applications. Such cells also present other environmental and safety problems.
A need also exists for an oxygen source that is liquid around room temperature so that an electrode for use with liquids may be employed. In some applications, the gas diffusion electrode disclosed in Surampudi et al. may be undesirable. [please describe advantages and disadvantages of liquid v. gas diffusion cell]
As can be appreciated, it would be desirable to provide improved fuel cells that overcome the disadvantages associated with the liquid methanol and oxygen gas fuel cell.
Hence the various general objects of the invention set forth above are achieved. Other objects and advantages of the invention will be apparent from the detailed description set forth below.
One aspect of the present invention is a fuel cell comprising an electrical load, an anode including a catalyst, a cathode including a catalyst, a proton conducting membrane, a methanol source, and an O2 source that is liquid at room temperature. Preferably, the O2 source is hydrogen peroxide. Preferably, the proton conducting membrane is constructed from a perfluorinated sulfonic acid polymer. Preferably, the proton conducting membrane is constructed from a co-polymer of tetrafluoroethylene and perfluorovinylether sulfonic acid. Preferably, the anode includes a platinum-ruthenium catalyst. Preferably, the cathode includes a platinum catalyst. Preferably, the catalysts are particles in supported or unsupported layer configuration on a carbon fiber sheet backing. Preferably, the cathode includes an ion conductor and a catalyst layer comprising the catalyst, an oxygen solvent agent, and a hydrophilic wetting agent, and wherein the anode includes an ion conductor and a catalyst layer comprising the catalyst, and a hydrophilic wetting agent. Preferably, the wetting agent is a compound having perfluorocarbon moieties, and the ion conductor is a carbon fiber sheet backing. Preferably, the wetting agent is a material selected from the group consisting of polytetrafluoroethylene and a co-polymer of tetrafluoroethylene and perfluorovinylether sulfonic acid. Preferably, the oxygen solvent agent is a material selected from the group consisting of a co-polymer of tetrafluoroethylene and perfluorovinylether sulfonic acid and a polytetrafluoroethylene. Preferably, the fuel cell further comprises a separator for maintaining concentration of the hydrogen peroxide in the cathode and a pump for recycling the hydrogen peroxide to the cathode. Preferably, the separator includes a hydrogen peroxide selective membrane. Preferably, the fuel cell further includes an evaporator and condenser for conserving water removed by the separator. Preferably, the fuel cell further comprises a pump for recycling unreacted methanol to the anode. Preferably, the hydrophilic wetting agent is a member selected from the group consisting of a polymeric perfluorosulfonic acid, a polyhydrocarbon sulfonic acid, a polyetherketonesulfonic acid, a polyethersulfone sulfonic acid and a polybenzimidazole. Preferably, the methanol is in a concentration of about 0.25 to 3.0 molar. Preferably, the hydrogen peroxide is in a concentration of about 1-30% volume/volume. Preferably, the hydrogen peroxide is in a concentration of about 3-5% volume/volume.
Another aspect of the invention includes a method of generating electrical energy in a fuel cell comprising the acts of electrochemically reacting methanol in an anode chamber, and electrochemically reacting hydrogen peroxide in a cathode chamber. The method may further include the acts of recycling unreacted methanol to the anode chamber, maintaining an electrochemically sufficient concentration of hydrogen peroxide, and recycling unreacted hydrogen peroxide to the cathode chamber.

Power generation in fuel cells using liquid methanol and hydrogen peroxide


A ballast (4) for providing power to a high intensity discharge lamp (8) includes a first sensor (32) and a control subsystem (16). The first sensor (32) generates a first signal indicative of a current level in the ballast (4). The control subsystem (16) computes a real time power level of the ballast (4) based at least upon the first signal, compares the computed real time power level to a specified power level, and modifies a frequency of operation of the ballast (4) in response to the comparison. The first sensor (32) can measure the current level at an output of the ballast (4). The ballast (4) can also include a second sensor (32) that generates a second signal indicative of a voltage output of the ballast (4). The control subsystem (16) can compute the real time power level of the ballast (4) based upon the second signal. The control subsystem (16) can be configured to read a lamp specified maximum power level, receive an input indicative of a dimming level, and/or compute the specified power level based upon the lamp specified maximum power level and the dimming level. The control subsystem (16) can incrementally decrease the frequency when the comparison indicates that the computed real time power level is less than the specified power level and/or incrementally increase the frequency when the comparison indicates that the computed real time power level is greater than the specified power level.

High intensity discharge (HID) arc lamps are in wide use for general illumination. Applications include roadside street lamps, sports arena illumination, stadium illumination, auto dealership illumination, warehouse illumination, and other purposes requiring a high power of illumination with high efficiency. They tend to be mounted at fairly high elevations requiring maintenance crews to replace.
Ballasts used with these lamps historically are designed to optimize characteristics of power delivered to the lamps when the lamps are new having an initial impedance. As the lamps age, the characteristics of the lamps change. Typically the impedance of the lamp changes and the power levels and efficiency deteriorate. Ballasts have been designed to compensate for this impedance change, but there is still an efficiency loss in most ballasts.

Ballast configured to compensate for lamp characteristic changes


Eye diseases or disorders are treated by an active agent being a melanotropin peptide or an analogue thereof, the analogue being an agent having a biological effect resembling that of the melanotropin peptide. The active agent may be administered topically onto the eye, by injection into the eye or systemically.

Age related degenerative changes in the eye's retina pigment epithilium (RPE), a highly pigmented epithilium underlying the retina, occur mainly in the macula area. Since the macula is the area which enables to discern small details and to read, its deterioration may bring about visual impairment and even blindness. Age related changes of varying degrees in the macula are evident in about 10% of subjects over 50 and about 25% of subjects over 75. One of the main factors responsible for age related macular degeneration (AMD) is aging of the Retinal Pigment Epithelium (RPE) at the macular area. In the intact eye, the RPE cells, through their phagocytic activity and active metabolism, constantly remove the toxic metabolites produced by the overlaying photoreceptoric retinal cells during the visual transduction process.
As a consequence of the age dependent reduction in the metabolic and pharmaceutical activity of cells of the RPE, metabolic waste products are accumulated within these cells causing a slow deterioration of the activity of the RPE cells and their death. This deterioration, and death of cells occurs mainly in the macula region, eventually causes the degradation of the overlaying retinal layer and photoreceptors with subsequent impairment of vision or even blindness.
Although AMD is the most prevalent cause of blindness in the elder population in developed countries, there is to date no effective treatment available to prevent the development of AMD or to ameliorate the condition following the onset of this disorder.
Melanotropin (alpha melanocytic stimulating hormone (.alpha.-MSH)) is an N-Acetyl-tridecapeptide hormone which is synthesized and secreted by the intermediate lobe of the pituitary gland, and is known to control skin pigmentation in many animals by stimulating melanin synthesis and movement within integumental melanocytes. Recently, melanotropin has been also reported to affect other physiological functions including: endocrine and exocrine gland activities, temperature regulation, immuno modulation and nerve regeneration. Cellular responses to melanotropin in cultured melanoma cells include elevation of c-AMP levels, increase in melanin synthesis and stimulation of cell proliferation.
Melanotropin was found to have also various effects on the eye. This hormone causes the acceleration of the regeneration of retinal visual purple both in vivo and in vitro and increases light sensitivity (Hanoka, 1953); it was also found to stimulate the melanin synthesis in the RPE of rats with inherited retinal dystrophy (Stroeva and Bibikova, 1988). In addition, this hormone was found to increase the release of retinal neurotransmitters, especially dopamine and GABA (Bauer and Ehringer, 1980). Recently it has been found that melanotropin enhances eicosanoid production by bovine RPE in organ culture without any effect on other retinal layers (Bar-Ilan et al., 1992).
Derivatives of this naturally occurring tridecapeptide in which one or more amino acids has been replaced by another are well known. Some of these derivatives are more stable than the native protein, and others, such as Nle.sup.4 D-Phe.sup.7 .alpha.-MSH were found to be more potent than the native peptide in affecting various biological phenomenon (Dayes et al., 1987). Sawyer et al. (Sawyer et al. 1990) have established the fact that only a few amino acids are sufficient to cause the full biological activity of the native protein.

Pharmaceutical compositions for the treatment or prevention of disorders in the eye

Ramot University Authority for Applied Research and Industrial Development Ltd.


Individual data packets are transmitted together with information about the end of a respective data packet, without padding, and then virtual padding is effected for generating redundant packets. At the receiver, the data packets are obtained using the information about the respective end of packet if no packet was lost, and are only expanded by padding if a packet has been lost and can be reconstructed by one or more redundant packets.

1. Field of the Invention
The invention relates to a method and an arrangement for protecting against packet losses in packet-oriented transmission of data in which, in particular, the size of the data packets varies greatly, as is the case, for example, with video data, such packet losses mainly being caused by overloading at network nodes in landline networks and due to atmospheric interference and multi-path propagation in mobile channels.
2. Description of the Related Art
The currently most widely used protocols on the transport layer (Layer 4) are user datagram protocol (UDP) and transmission control protocol (TCP) which react very sensitively to bit errors in received packets. As soon as a bit error is detected in a packet by an error-detecting code, the affected packet is discarded or erased. In other words, packet loss also occurs. So-called reliable transport protocols such as TCP use automatic repeat request methods to be able to transport lost or discarded packets reliably to the receiver in spite of disturbed channels. However, this is associated with a very great increase in transmission delay which, however, cannot be tolerated by many applications (for example, communication applications). For this reason, unreliable transport protocols such as, for example, UDP, are used in this case. Although these do not cause any increase in delay, they do not offer any mechanisms for compensating for packet losses either. For this reason, intensive efforts have been made for some time in the Audio-Visual Transport Group (AVT) of the Internet Engineering Task Force (IETF) to connect forward error correction (FEC) methods and packet-oriented transmission with unreliable transport protocols. The principles of these methods are described in IETF RFC 2733—An RTP Payload Format for Generic Forward Error Correction and IETF Internet Draft—An RTP Payload Format for Reed Solomon Codes, both by J. Rosenberg and H. Schulzrinne and will be briefly presented in the section following. These methods are very inefficient with respect to the bandwidth needed, especially in the case of variable-bit-rate data sources, for example video.
In the case of packet losses, the data are not corrupted but are completely lost and so-called erasures occur as described in "Error Control Coding", by Shu Lin and Daniel Costello, Prentice-Hall, 1983. Since each packet-oriented transport protocol uses sequence numbers, the receiver knows which packets have been lost in a sequence. The coding theory offers a multiplicity of methods for fighting erasures. The IETF, which decides on the standardization of IP-based transport protocols, has recently developed much activity for integrating methods for protecting against packet losses into their real-time transport protocols (RTP), as described by Rosenberg et al. Although these methods use a number of different codes as far as coding is concerned, the basic principle is the same in all approaches. In the transmitter, n, n=1 successive data packets of the source are in each case protected against erasures. As soon as a data packet comes from the source, it is copied into a memory. If the nth packet is available, coding is carried out. Since the data packets in the memory can be generally of different sizes, they are first made the same size. For this purpose, the length, that is to say the number of bytes in a data packet, of the largest data packet is determined and all shorter packets are expanded to this length by adding known bits or symbols, for example zeros. This process is called padding. After that, the packets, which are now of the same size, are combined with one another with the aid of a coding rule of any systematic code. These can be either simple parity codes or complex block codes. Similarly, the coding can be carried out at bit level or at symbol level with appropriate segmenting. Depending on the coding rule, the combining results in a number of redundant packets which, together with the data packets, are then transmitted to the receiver in accordance with the transport and network protocols used. These redundant packets enable the receiver to reconstruct the payload of any lost packets. If the data packets vary greatly in their size, as is the case, for example, with video data, a very large number of symbols which are absolutely redundant must be transmitted in the data packets due to the padding, as a result of which the coding is extremely inefficient with regard to economic utilization of the transmission channel.
If, for example n=5 data packets with lengths of 200, 400, 800, 500 and 600 bytes are used and three redundant packets are generated, the maximum length is 800 bytes and a total of 1500 bytes are therefore needed for the padding, which must be transmitted without being useful for error protection and for source decoding.

Method and apparatus for protecting against packet losses in packet-oriented data transmission


An in vivo method for the production of pHS via a recombinant host cell is disclosed. The host cell expresses at least one gene encoding a polypeptide having para-hydroxycinnamic acid decarboxylase activity in combination with either at least one gene encoding a polypeptide having tyrosine ammonia lyase activity or at least one gene encoding a polypeptide having phenylalanine ammonia lyase activity.

Para-hydroxystyrene (pHS) is a well-known compound having potential utility in a wide variety of industrial applications, including the production of resins, coatings and inks.
A number of methods for the chemical synthesis of pHS are known. For example, pHS may be produced from ethyl benzene in a five-step process (U.S. Pat. No. 4,503,271) or from para-hydroxyacetophenol in a two step process (U.S. Pat. No. 5,523,378). Although it is possible to generate pHS by these methods, they typically require strongly acidic or basic reaction conditions, high reaction temperature, and generate large amounts of unwanted byproducts. In addition, chemical methods require expensive starting materials, which raise the cost of producing pHS. Despite the wide variety of uses for pHS, an inexpensive source of the material has not been developed.
A number of microorganisms have been found to produce 4-hydroxystyrenes, including fungi (Bayne et al., J. Gen. Microbiol. 95, 188–190 (1976) and Harada et al., J. Gen. Microbiol. 11, 1258–1262 (1976)), yeast (Goodey et al., J. Gen. Microbiol, 128, 2615–620 (1982)), and both Gram-negative and Gram-positive bacteria (Finkle et al. J. Biol. Chem. 237, 2926–2931 (1962), and Lindsay et al., J. Appl. Bacteriol. 39, 181–187 (1975)). In each of the above cases carboxylic acids of the phenylpropanoid class are decarboxylated to produce the corresponding 4-hydroxystyrene.
A para-hydroxycinnamic acid decarboxylase activity converts para-hydroxycinnamic acid (pHCA) to pHS (Hashidoko et al., Biosci. Biotech. Biochem., 58(1), 217–218, (1994)). Release of 4-hydroxystyrene was reported when a DNA fragment carrying the 4-hyroxycinnamate decarboxylase gene from Klebsiella oxytoca was consitutively expressed in E. coli JM109. The recombinant host cell did not contain any additional genes for the production of the para-hydroxycinnamic acid (pHCA), the expected pHS precursor.
Additionally, Hashidoko et al. demonstrated production of hydroxystyrene by decarboxylation of 4-hydroxycinnamic acids by hydroxycinnamate decarboxylase from Klebsiella oxytoca (Arch. Biochem. Biophys. (1998), 359(2), 225–230)). The in vitro biological method of Hashidoko et al. for the production of pHS is limited to very low titer from the expensive starting material, pHCA.
In light of the foregoing, it would be an advancement in the art to provide a method for the production pHS using inexpensive materials such as carbohydrates or sugars and to increase the efficiency of a process for production of pHS through the pHCA intermediate. It would be particularly advantageous if the method produced a high level of the desired product with limited by-products. Development of such a method will require the ability to manipulate the genetic machinery responsible for the conversion of carbohydrates such as glucose to pHCA and pHCA to pHS.
The above mentioned biological and chemical systems provide a number of pathways that may be useful in the production of pHS, however, the efficient production of this monomer has not been achieved. The problem to be overcome therefore is to design and implement a method for the efficient production of pHS from a biological source using an inexpensive substrate or fermentable carbon source. Applicants have solved the stated problem by engineering a microbial host to produce pHS by expressing foreign genes encoding phenylalanine ammonia lyase/tyrosine ammonia lyase (PAL/TAL) and para-hydroxycinnamic acid decarboxylase (PDC) activity.

Microbial conversion of glucose to para-hydroxystyrene


An advantageous measurement technique for evaluating the overall scheduling regularity producible by a scheduling template having particular slot assignment orderings for respective classes of events such as, for example, transmitting order of communication signals over respective virtual circuits by a node of a network. This measurement technique is used for measuring the overall scheduling regularity producible by each of a plurality of different scheduling templates to select the template having a desirable regularity measure for use in establishing a scheduling order of events for a network.

Networks are a principal means of exchanging or transferring information, such as information signals representing voice, audio, data or video, among communication devices. Such communication devices often include devices for sending and/or receiving information, such as computer terminals, multimedia workstations, facsimile machines, printers, servers and telephones. Information transmitted on the network can be of many different forms but is often formatted into fixed-length data packets or cells. Networks, such as broadband ISDN (BISDN) employing asynchronous transfer mode (ATM) packet switching, are increasingly being used for the reliable, high-speed transmission of information. This increased use has brought major changes in network architecture and infrastructure design, as well as in network operations, to increase communication capacity and quality.
A typical network includes switch nodes having ports coupled by links to ports of other nodes and to the communication devices. Each link is uni- or bi-directional and is characterized by a bandwidth or link capacity in the directions of information transfer. Information to be exchanged is often conveyed over a path containing a set of nodes and links connecting two devices. Such a path can be regarded as a "virtual circuit" (VC) whereby one communication device specifies the intended destination device for the information, and the network delivers the information as though a dedicated circuit connected the two communication devices. Often multiple VCs are simultaneously maintained through a single switch node. In a similar manner, different VCs are often simultaneously maintained over a common link between switch nodes.
Buffer memories are typically employed in the switch nodes to increase the number of VC's that can simultaneously be carried by the node by buffering transmission of data packets of a type that is relatively delay insensitive while buffering to a lesser extent transmission of those packets of a type that is relatively delay sensitive. Such buffer memories effectively operate as respective queues for the packets that are to be conveyed through the respective ports to a common link or multiple links. By selecting an advantageous order in which packets from these queues are routed through a common switch node or multiplexed over a common link, it is possible to increase the number of VCs that the switch node can simultaneously maintain as well as increase communication quality.
In particular networks, a template is used to provide the transmission scheduling order for data packets of the respective VCs. A conventional template includes a fixed number of slots, wherein each slot position represents a scheduling position of corresponding packets for a particular VC. The order of such slots in the template determines the order or sequence in which the switch node repetitively transmits packets for the corresponding VCs. Desirable scheduling orders that facilitate increased VC capacity and improved quality of service transmit packets for VCs of relatively delay sensitive information in a manner that is substantially regular such as, for example, at least roughly periodic and non-bursty.
Known methods for determining scheduling orders or template slot positions include round robin and golden ratio techniques which are described in Y. Arian and Y. Levy, "Algorithms for Generalized Round Robin Routing", Operations Research Letters, vol. 12, no. 5, pp. 313-319 (November 1992), and A. Itai and Z. Rosberg, "A Golden Ratio Control Policy for a Multiple-Access Channel", IEEE Trans. on Automatic Control, vol. AC-29, no. 8, pp. 712-718 (August 1984), respectively, and which are both incorporated by reference herein. However, such scheduling methods provide marginally enhanced ordering of the template slots and, at times, overlook more advantageous slot orderings.
Accordingly, a need exists for a technique for determining improved scheduling templates orderings.

Apparatus and method for template-based scheduling processes using regularity measures


A telescopic illuminating tool includes a handle with an accommodating chamber for receiving a battery unit, and first and second electric contacts spaced apart each other. A plurality of telescopic metal concentric tubes is connected to a head of the handle at one end and, is provided with a bulb seat at an opposite end. The bulb seat has a contact area in electrical contact with a ring contact of an electric bulb, and a third electric contact in electrical contact with the concentric tubes. A stretchable electrically conductive member, such as a tension spring with an electrically insulative sheath thereon, is secured in the concentric tubes for connection with a tip contact of the bulb and a first electric contact of the handle which, in turn, is adapted to be in electrical contact with one electrode of the battery unit. A second electric contact of the handle is in electrical contact with the concentric tubes and the other electrode of the battery unit. The stretchable electrically conductive member can be stretched or retracted when the concentric tubes are extended or shortened, thereby adjusting desirably the length of the illuminating tool.

1. Field of the Invention
This invention relates to a telescopic illuminating tool, more particularly to a telescopic illuminating tool with telescopic tubes and a stretchable electrically conductive wire disposed in the telescopic tubes for electrical connection with a battery unit and an electric bulb.
2. Description of the Related Art
Referring to FIG. 1, a conventional illuminating tool is shown to include a conductive barrel housing 1 for receiving a battery unit 2, a press button 3 which is disposed outwardly of a rear end of the housing 1, and a flexible core 4 which has an end connected to a front end of the housing 1, and the other end provided with an electric bulb 5 and a tool member 6. The electric bulb 5 is lighted by the battery unit 2, and the flexible core 4 can be adjusted at any desired angle. However, the flexible core 4 can not be adjusted in length, thereby resulting in inconvenience during use.
Referring to FIG. 2, another conventional illuminating tool is shown to include a plurality of metal tubes 11 which are fitted telescopically and slidably with one another, a switch member 12, a battery receiving tube 14 for receiving battery cells 13, and a plurality of spiral conducting wires 17, each received in the respective metal tube 11. Since the conducting wires 17 are made of enameled wires which are difficult to be stretched, the extension range of the illuminating tool is limited.