When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically, the application of the bias power is initiated before the application of source power is initiated. Alternatively, the source power and the bias power are applied such that the effective value of the source power reaches a second predetermined value after the effective value of the bias power reaches a first predetermined value.

The present invention relates to a dry etching method for a material containing silicon, a method for fabricating a semiconductor device using the dry etching method, and a dry etching apparatus for implementing the dry etching method.
When dry etching is performed with respect to a material containing silicon (hereinafter referred to as the silicon-containing material) in the fabrication of a semiconductor device, a dry etching apparatus having a dual power source such as an inductively coupled plasma etching apparatus (ICP) has been used to miniaturize a semiconductor element and increase the precision thereof. The dry etching apparatus having the dual power source features separate and controlled application of first electric power (hereinafter referred to as source power) for generating a plasma of a process gas introduced into a chamber and adjusting the density of the plasma and second electric power (hereinafter referred to as bias power) for drawing ions (etching species) from the plasma into an object to be etched. The use of the dry etching apparatus having the dual power source provides high-accuracy processing properties. In a typical dry etching apparatus having a dual power source, the source power is applied to a coil or the like provided on an outer wall of the chamber and the bias power is applied to a sample stage provided in the chamber to carry the object to be etched.
The step of forming an isolation in a silicon substrate has conventionally used LOCOS (Local Oxidization of Silicon) for forming the isolation by locally oxidizing the silicon substrate masked with a nitride film. As feature sizes have been reduced increasingly, however, the problem has arisen that the isolation is larger than a desired size, which makes it difficult to provide an active region having a sufficient size. To solve the problem, STI (Shallow Trench Isolation) has been used as a replacement in which an isolation is formed by forming a trench in a silicon substrate, filling an oxide film in the trench, and then planarizing a surface of the silicon substrate including a surface of the oxide film by CMP (Chemical Mechanical Polishing). The foregoing dry etching apparatus having the dual power source is used to form the trench for isolation.
Herein below, a conventional method for fabricating a semiconductor device, specifically a method for forming a trench for isolation by etching a silicon substrate by using the dry etching apparatus having the dual power source will be described with reference to the drawings.
FIGS. 11A to 11D are cross-sectional views illustrating the individual process steps of the conventional method for fabricating a semiconductor device.
First, as shown in FIG. 11A, a first silicon oxide film 81 is formed on a silicon substrate 80 by thermal oxidation, followed by a silicon nitride film 82 formed on the first silicon oxide film 81 by using a film forming method such as CVD (chemical vapor deposition). Then, a resist pattern 83 having openings each corresponding to a region to be formed with an isolation is formed on the silicon nitride film 82 by photolithography.
Next, as shown in FIG. 11B, dry etching is performed with respect to the silicon nitride film 82 and to the first silicon oxide film 81 by using the resist pattern 83 as a mask, thereby patterning each of the silicon nitride film 82 and the first silicon oxide film 81. Thereafter, the resist pattern 83 is removed by ashing and the silicon substrate 80 is cleaned.
Next, as shown in FIG. 11C, dry etching is performed with respect to the silicon substrate 80 by using the patterned silicon nitride film 82 as a mask, thereby forming trenches 84 for isolation in the silicon substrate 80. A detailed description will be given to the dry etching step shown in FIG. 11C. First, the silicon substrate 80 as an object to be etched is placed in the chamber (not shown) of the dry etching apparatus. Then, the chamber is evacuated till a specified degree of vacuum is reached and a gas required to etch the silicon substrate 80 (hereinafter referred to as a process gas), specifically a mixture of a halogen-containing gas such as Cl2 or HBr and an oxygen gas is introduced into the chamber. Subsequently, a plasma of the process gas is generated by initiating the application of source gas and then ions in the plasma are drawn into the silicon substrate 80 by initiating the application of bias power. As a result, the ions in the plasma and an exposed portion of the silicon substrate 80 react with each other to form a volatile reaction product (such as a compound of silicon and chlorine). At this stage, dry etching is performed with respect to the silicon substrate 80 by evacuating the chamber and thereby exhausting the foregoing volatile reaction product from the chamber. Thereafter, the silicon substrate 80 is cleaned such that a deposit (such as a compound of the foregoing volatile reaction product and oxygen) formed on the silicon substrate 80 during dry etching is removed therefrom, whereby the trenches 84 are formed in the silicon substrate 80.
Since the dry etching step shown in FIG. 11C requires processing accuracy as high as required by the processing of a gate electrode due to a reduced size of the isolation, a dry etching apparatus having a dual power source such as an inductively coupled plasma etching apparatus is used in the dry etching step.
Next, the portions of the silicon substrate 80 located adjacent the wall and bottom surfaces of the trench 84 are thermally oxidized by using an oxidation furnace in order to lower a surface state in the portions of the silicon substrate 80. Then, a second silicon oxide film 85 is deposited on the silicon nitride film 82 by CVD to completely fill the trench 84. Subsequently, a surface of the silicon nitride film 82 including a surface of the second silicon oxide film 85 is planarized by CMP such that the portions of the second silicon oxide film 85 located externally of the trenches 84 are removed. Thereafter, the silicon nitride film 82 is removed by wet etching and the first silicon oxide film 81 remaining on the surface of the silicon substrate 80 is removed by cleaning the silicon substrate 80 as shown in FIG. 11D, whereby isolations composed of the second silicon oxide film 85 filled in the trenches 84 are formed.
A description will be given herein below to a conventional method of applying the source power and the bias power in the dry etching step using the dry etching apparatus having the dual power source and shown in FIG. 11C (hereinafter referred to as the conventional dry etching method) and to the effect of the conventional dry etching method.
FIG. 12 shows an example of the respective time-varying effective values of the source power and the bias power in the conventional dry etching method. In FIG. 12, the time at which the application of the source power is initiated is used as the reference for power application time (0 second). In the present specification, the effective value of the bias power is the effective value of the bias power actually applied to the sample stage and the effective value of the source power is the effective value of the source power actually applied to the coil or the like. The effective value is defined herein as the value of an alternating power equal to the square root of the arithmetic mean of the squares of the instantaneous values taken throughout one complete cycle.
As shown in FIG. 12, the application of the bias power is initiated one second after the application of the source power is initiated. On the other hand, the effective value of the source power is set to 600 W, while the effective value of the bias power is set to 200 W.
FIGS. 13A to 13C are views showing the effect of the conventional dry etching method, specifically showing changes in the internal state of the chamber of the dry etching apparatus in the dry etching step shown in FIG. 1C, of which FIG. 11A shows the state immediately after the introduction of the process gas into the chamber, FIG. 11B shows the state immediately after the application of the source power is initiated, and FIG. 11C shows the state immediately after the application of the bias power is initiated. It is to be noted that the silicon nitride film and the like on the silicon substrate as well as the sample stage and the like in the chamber are not depicted in FIGS. 13A to 13C.
First, as shown in FIG. 13A, the silicon substrate 80 as an object to be etched is placed in a chamber 86 of the dry etching apparatus. Then, the chamber 86 is evacuated till a specified degree of vacuum is reached and a process gas 87 required to etch the silicon substrate 80 is introduced into the chamber 86. Then, as shown in FIG. 13B, a plasma 87A of the process gas 87 is generated with application of the source gas. Thereafter, ions 88 in the plasma 87A are drawn into the silicon substrate 80 with application of the bias power, as shown in FIG. 13C.
Thus, the dry etching apparatus having the dual power source is capable of controlling the generation of the plasma of the process gas and the adjustment of the plasma density independently of the drawing of the ions from the plasma into the object to be etched. In accordance with the conventional dry etching method using the dry etching apparatus having the dual power source, therefore, etching is performed with respect to the object to be etched by generating the plasma of the process gas with application of the source power and then drawing the ions from the plasma into the object to be etched with application of the bias power.
If a trench for isolation is formed in a silicon substrate by using the conventional dry etching method, e.g., however, etching is halted halfway, as shown in FIG. 14, which leads to the problem that the trench for isolation having a desired isolation depth cannot be formed. FIG. 14 shows the state in which etching has been halted halfway in the dry etching step shown in FIG. 11C. In FIG. 14, the same reference numerals as used in FIG. 11C are retained for the same members.
If the conventional dry etching method is used for a silicon substrate or the like as an object to be etched, an etching-induced damaged layer is formed in the silicon substrate or the like, which causes the problem that the electric characteristics of the semiconductor device are degraded.
If a trench for isolation is formed in a silicon substrate by using the conventional dry etching method, e.g., it is necessary to thermally oxide the portions of the silicon substrate located adjacent the wall and bottom surfaces of the trench for isolation in order to lower a surface state in the portions of the silicon substrate, while cost for fabricating the semiconductor device is increased disadvantageously by using an oxidation furnace.
In view of the foregoing, it is therefore a first object of the present invention to prevent a halfway halt in etching performed with respect to a silicon-containing material by using an etching apparatus having a dual power source. A second object of the present invention is to prevent the degradation of the electric characteristics of a semiconductor device induced by a damaged layer formed in the silicon-containing material during dry etching. A third object of the present invention is to lower a surface state in the portions of the silicon substrate located adjacent the wall and bottom surfaces of a trench for isolation at low cost.
To attain the first object, the present inventors have examined the cause of an etching halt in the conventional dry etching method (see FIG. 14) and found the following fact.
FIGS. 15A to 15C are views illustrating the mechanism of the etching halt occurring in the conventional dry etching method, specifically showing the internal states of the chamber of a dry etching apparatus at different times in the dry etching step shown in FIG. 11C, of which FIG. 15A shows the state immediately after the application of the source power is initiated in the chamber in which a process gas has been introduced, FIG. 15B shows the state in which the application of the source power is continued before the application of the bias power is initiated, and FIG. 15C shows the state immediately after the application of the bias power is initiated. It is to be noted that a silicon nitride film and the like on a silicon substrate as well as a sample stage and the like in the chamber are not depicted in FIGS. 15A to 15C.
First, as shown in FIG. 15A, the silicon substrate 80 as an object to be etched is placed in the chamber 86 of the dry etching apparatus. Then, the chamber 86 is evacuated till a specified degree of vacuum is reached. Subsequently, the process gas 87 (such as a mixture of a halogen-containing gas and an oxygen gas) required to etch the silicon substrate 80 is introduced into the chamber 86 and the source power is applied, whereby the plasma 87A of the process gas 87 is generated.
Next, if the application of the source power is continued before the application of the bias power is initiated, active oxygen (hereinafter referred to as oxygen radicals) 89 is generated in conjunction with the ions 88 as an etching species in the plasma 87A, as shown in FIG. 15B. At this time, the oxygen radicals 89 and an exposed portion of the silicon substrate 80 react with each other to form a thin silicon oxide film 90 on the silicon substrate 80.
Next, as shown in FIG. 15C, the ions 88 in the plasma 87 are drawn into the silicon substrate 80 with application of the bias power. However, since the silicon oxide film 90 has been formed on the silicon substrate 80 as an object to be etched and an etching speed for the silicon oxide film is about one hundredth of an etching speed for silicon, etching performed with respect to the silicon substrate 80 hardly proceeds.
To verify the mechanism of the etching halt in the conventional dry etching method (FIGS. 15A to 15C), the present inventors conducted the following two experiments.
First, to verify oxidization at a surface of the silicon substrate when the application of the source power is continued before the application of the bias power is initiated in the first experiment, the thickness of the silicon oxide film formed on the surface of the silicon substrate was measured by exposing the silicon substrate to the plasma generated only with application of the source power for a specified period. At this time, an inductively coupled plasma etching apparatus was used as a dry etching apparatus having a dual power source and the respective effective values of the source power and the bias power were set to 600 W and 0 W. As a process gas, a mixture of Cl2 and O2 gases (Pressure: 7 Pa, Cl2 Gas Flow Rate: 150 ml/min, O2 Gas Flow Rate: 6 ml/min) was used.
FIG. 16 shows the result of the first experiment, specifically the dependence of the thickness of the oxide film (the vertical axis) at the surface of the silicon substrate on the source power application period (the horizontal axis).
As shown in FIG. 16, it was found that, if the application of the source power was initiated before the application of the bias power was initiated, oxidization at the surface of the silicon substrate proceeds with a lapse of the source power application period to form a thick oxide.
Next, to verify the relationship between each of the timing of applying the source power and the timing of applying the bias power and a halt in etching performed with respect to the silicon substrate in the second experiment, the etching depth (hereinafter referred to as an amount of shaved silicon) was measured when dry etching was performed with respect to the silicon substrate, while varying the timing of initiating the application of the source power and the timing of initiating the application of the bias power. As a sample used in the second embodiment, a silicon substrate formed by the conventional method for fabricating a semiconductor device shown in FIGS. 11A and 11B (the silicon substrate 80 formed with the silicon nitride film 82 as a mask pattern for forming isolation) was selected.
An objective value of the amount of shaved silicon was set to 300 nm in the second experiment. As a dry etching apparatus having a dual power source, an inductively coupled plasma etching apparatus was used and the respective effective values of the source power and the bias power were set to 600 W and 200 W. As a process gas, a mixture of Cl2 and O2 gases (Pressure: 7 Pa, Cl2 Gas Flow Rate: 150 ml/min, O2 Gas Flow Rate: 6 ml/min) was used.
In the second embodiment, the time at which the application of the source power was initiated was used as the reference time and the time at which the application of the bias power was initiated was expressed as a delay time from the reference time (which assumes a negative value if the time at which the application of the bias power was initiated precedes the time at which the application of the source power was initiated).
FIG. 17 shows the result of the second experiment, specifically shows the dependence of the amount of shaved silicon (the vertical axis) on the delay time (the horizontal axis).
As shown in FIG. 17, it was found that a halt in etching performed with respect to the silicon substrate occurred if the application of the source power was initiated before the application of the bias power was initiated. Specifically, even if an interval between the time at which the plasma is generated with application of the source power and the time at which the application of the bias power is initiated, i.e., an interval between the time at which the application of the source power is initiated and the time at which etching of the silicon substrate is initiated is short, oxidization proceeds at the surface of the silicon substrate and etching performed with respect to the silicon substrate is halted consequently.
From the results shown in FIGS. 16 and 17, the present inventors have concluded that, to attain the first object, i.e., to prevent a halfway halt in dry etching performed with respect to the silicon-containing material, it is important to prevent oxidization at a surface of the silicon-containing material during dry etching. As a specific method for preventing oxidization at the surface of the silicon-containing material, the present inventors have developed a method of initiating the application of the bias power before initiating the application of the source power in the dry etching apparatus having the dual power source. As a value predetermined for an effective value of applied power is larger, the time required by the effective value to reach the predetermined value from the initiation of the application thereof becomes longer. Even in the case where a value predetermined for the effective value of the source power (second predetermined value) is higher than a value predetermined for the effective value of the bias power (first predetermined value) and where the application of the source power is initiated at the same time as or before the application of the bias power is initiated, if the effective value of the source power reaches the second predetermined value after the effective value of the bias power reaches the first predetermined value, effects equal to those achieved by the foregoing xe2x80x9cmethod of initiating the application of the bias power before initiating the application of the source powerxe2x80x9d are achievable.
The present inventors have also found that, if etching is performed with respect to the silicon-containing material by using the dry etching apparatus having the dual power source, the second object can be attained, i.e., the degradation of the electric characteristics of the semiconductor device can be prevented by applying the source power by continuously using the same dry etching apparatus having the dual power source as used for etching without applying the bias power, thereby oxidizing the damaged layer formed in the silicon-containing material during etching and then removing the oxidized damaged layer by cleaning the substrate.
Further, the present inventors have found that the third object can be attained, i.e., a surface state in the portions of the silicon substrate located adjacent the wall and bottom surfaces of the trench for isolation can be lowered at low cost without using an oxidation furnace by applying the source power in the dry etching apparatus having the dual power source without applying the bias power and thereby oxidizing the portions of the silicon substrate located adjacent the wall and bottom surfaces of the trench for isolation.
The present invention has been achieved based on the foregoing findings. Specifically, to attain the first object, a dry etching method according to the present invention assumes a dry etching method using a dry etching apparatus having a dual power source capable of independently controlling source power for generating a plasma in a chamber and bias power for drawing ions from the plasma into an object to be etched in the chamber, the method comprising the steps of: placing a substrate having a member containing at least silicon exposed thereat in the chamber; introducing a process gas containing at least oxygen into the chamber in which the substrate has been placed; and performing etching with respect to the member by generating a plasma of the process gas with application of the source power and drawing the ions from the plasma into the member with application of the bias power, the step of performing etching with respect to the member including the step of initiating the application of the bias power before oxidization proceeds at a surface of the member.
If etching is performed with respect to the silicon-containing material as the object to be etched by using the dry etching apparatus having the dual power source, the dry etching method of the present invention initiates the application of the bias power before the oxidization at the surface of the silicon-containing material proceeds. This prevents the situation in which the drawing of the ions from the plasma into the silicon-containing material is inhibited by an oxide film formed on the surface of the silicon-containing material and surely prevents a halfway halt in dry etching performed with respect to the silicon-containing material.
In the dry etching method of the present invention, the step of performing etching with respect to the member preferably includes the step of initiating the application of the bias power before initiating the application of the source power.
The arrangement ensures the drawing of the ions from the plasma into the silicon-containing material before the surface of the silicon-containing material is oxidized by oxygen radicals generated in the plasma with application of the source power and thereby ensures etching performed with respect to the silicon-containing material.
In the dry etching method of the present invention, the step of performing etching with respect to the member preferably includes the step of applying the source power and the bias power such that an effective value of the source power reaches a second predetermined value after an effective value of the bias power reaches a first predetermined value.
The arrangement ensures the drawing of the ions from the plasma into the silicon-containing material before the surface of the silicon-containing material is oxidized by oxygen radicals generated in the plasma with application of the source power and thereby ensures etching performed with respect to the silicon-containing material. Specifically, if the second predetermined value for the source power is higher than the first predetermined value for the bias power, the time at which the effective value of the source power reaches the second predetermined value is posterior to the time at which the effective value of the bias power reaches the first predetermined value even when the application of the source power is initiated at the same time as or before the application of the bias power is initiated. In this case, therefore, the same effect as achieved when the application of the source power is initiated after the application of the bias power is initiated is achievable.
In the dry etching method of the present invention, a silicon substrate, a polysilicon film, an amorphous silicon film, a silicide film, or the like may be used as a silicon-containing material.
To attain the first object, a first method for fabricating a semiconductor device according to the present invention assumes a method for fabricating a semiconductor device using a dry etching apparatus having a dual power source capable of independently controlling source power for generating a plasma in a chamber and bias power for drawing ions from the plasma into an object to be etched in the chamber, the method comprising the steps of: forming a mask pattern having an opening corresponding to a region to be formed with an isolation on a silicon substrate; placing the silicon substrate formed with the mask pattern in the chamber; introducing a process gas containing at least oxygen into the chamber in which the silicon substrate has been placed; and forming a trench for isolation in the silicon substrate by generating a plasma of the process gas with application of the source power, drawing ions from the plasma into the silicon substrate with application of the bias power, and thereby performing etching with respect to the silicon substrate, the step of forming the trench for isolation including the step of initiating the application of the bias power before oxidization proceeds at an exposed portion of the silicon substrate.
If the trench for isolation is formed by performing etching with respect to the silicon substrate by using the dry etching apparatus having the dual power source, the first method for fabricating a semiconductor device initiates the application of the bias power before oxidization proceeds at the exposed portion of the silicon substrate. This prevents the situation in which the drawing of the ions from the plasma into the silicon substrate is inhibited by an oxide film formed on the surface of the silicon substrate and surely prevents a halfway halt in dry etching performed with respect to the silicon substrate. Accordingly, there can be formed the trench for isolation having a desired isolation depth in the silicon substrate.
In the first method for fabricating a semiconductor device, the step of forming the trench for isolation preferably includes the step of initiating the application of the bias power before initiating the application of the source power.
The arrangement ensures the drawing of the ions from the plasma into the silicon substrate before the surface of the silicon substrate is oxidized by oxygen radicals generated in the plasma with the application of the source power and thereby ensures etching performed with respect to the silicon substrate.
In the first method for fabricating a semiconductor device, the step of forming a trench for isolation preferably includes the step of applying the source power and the bias power such that an effective value of the source power reaches a second predetermined value after an effective value of the bias power reaches a first predetermined value.
The arrangement ensures the drawing of the ions from the plasma into the silicon substrate before the surface of the silicon substrate is oxidized by oxygen radicals in the plasma generated with the application of the source power and thereby ensures etching performed with respect to the silicon substrate.
To attain the first object, a second method for fabricating a semiconductor device according to the present invention assumes a method for fabricating a semiconductor device using a dry etching apparatus having a dual power source capable of independently controlling source power for generating a plasma in a chamber and bias power for drawing ions from the plasma into an object to be etched in the chamber, the method comprising the steps of: forming a conductive film containing at least silicon on a substrate; forming a mask pattern covering a region to be formed with a gate electrode on the conductive film; placing the substrate formed with the conductive film and with the mask pattern in the chamber; introducing a process gas containing at least oxygen into the chamber in which the substrate has been placed; and forming a gate electrode composed of the conductive film by generating a plasma of the process gas with application of the source power, drawing ions from the plasma into the conductive film with application of the bias power, and thereby performing etching with respect to the conductive film, the step of forming the gate electrode including the step of initiating the application of the bias power before oxidization proceeds at an exposed portion of the conductive film.
If the gate electrode is formed by performing etching with respect to the silicon-containing conductive film formed on the substrate by using the dry etching apparatus having the dual power source, the second method for fabricating the semiconductor device initiates the application of the bias power before oxidization proceeds at the exposed portion of the silicon-containing conductive film. This prevents the situation in which the drawing of the ions from the plasma into the silicon-containing conductive film is inhibited by the oxide film formed on the surface of the silicon-containing conductive film and surely prevents a halfway halt in dry etching performed with respect to the silicon-containing conductive film. Accordingly, there can be formed the gate electrode having a desired size.
In the second method for fabricating a semiconductor device, the step of forming the gate electrode preferably includes the step of initiating the application of the bias power before initiating the application of the source power.
The arrangement ensures the drawing of the ions from the plasma into the silicon-containing conductive film before a surface of the silicon-containing conductive film is oxidized by oxygen radicals generated in the plasma with the application of the source power and thereby ensures etching performed with respect to the silicon-containing conductive film.
In the second method for fabricating a semiconductor device, the step of forming the gate electrode preferably includes the step of applying the source power and the bias power such that an effective value of the source power reaches a second predetermined value after an effective value of the bias power reaches a first predetermined value.
The arrangement ensures the drawing of the ions from the plasma into the silicon-containing conductive film before a surface of the silicon-containing conductive film is oxidized by oxygen radicals generated in the plasma with the application of the source power and thereby ensures etching performed with respect to the silicon-containing conductive film.
In the second method for fabricating a semiconductor device, a polysilicon film, an amorphous silicon film, a silicide film, or the like may be used as a silicon-containing conductive film.
To attain the second object, a third method for fabricating a semiconductor device assumes a method for fabricating a semiconductor device by using a dry etching apparatus having a dual power source capable of independently controlling source power for generating a plasma in a chamber and bias power for drawing ions from the plasma into an object to be etched in the chamber, the method comprising the steps of: performing etching with respect to the member by placing a substrate having a member containing at least silicon exposed thereat in the chamber, introducing a first process gas into the chamber, generating a first plasma of the first process gas with application of the source power, and drawing ions from the first plasma into the member with application of the bias power; exhausting the first process gas from the chamber after the step of performing etching with respect to the member and then introducing a second process gas containing at least oxygen into the chamber, while leaving the substrate in the chamber; oxidizing a damaged layer formed in the member in the step of performing etching with respect to the member by generating a second plasma of the second process gas by applying the source power without applying the bias power; and removing the oxidized damaged layer by retrieving the substrate from the chamber and cleaning the substrate.
The third method for fabricating a semiconductor device performs etching with respect to the silicon-containing material by using the dry etching apparatus having the dual power source, oxidizes the damaged layer formed in the silicon-containing material during dry etching by applying the source power without applying the bias power by using the same dry etching apparatus having the dual power source, and then removes the oxidized damaged layer by cleaning the substrate. This prevents the degradation of the electric characteristics of the semiconductor device induced by the damaged layer formed in the silicon-containing material during dry etching. Since the damaged layer can be oxidized by using the dry etching apparatus having the dual power source used for dry etching instead of using an oxidation furnace, the fabrication cost for the semiconductor device can be reduced significantly.
In the third method for fabricating a semiconductor device, the member is preferably a silicon substrate, the step of performing etching with respect to the member preferably includes the step of forming a trench for isolation in the silicon substrate, and the step of oxidizing the damaged layer preferably includes the step of oxidizing the damaged layer formed in portions of the silicon substrate located adjacent wall and bottom surfaces of the trench for isolation.
When the trench for isolation is formed by performing dry etching with respect to the silicon substrate, the arrangement allows low-cost removal of the damaged layer formed in the portions of the silicon substrate located adjacent the wall and bottom surfaces of the trench for isolation.
In the third method for fabricating a semiconductor device, the member is preferably a conductive film formed on the substrate and containing at least silicon, the step of performing etching with respect to the member preferably includes the step of forming a gate electrode composed of the conductive film on the substrate, and the step of oxidizing the damaged layer preferably includes the step of oxidizing the damaged layer formed in a side surface of the gate electrode.
When the gate electrode is formed by performing dry etching with respect to the silicon-containing conductive film formed on the substrate, the arrangement allows low-cost removal of the damaged layer formed in the side surface of the gate electrode.
In this case, a polysilicon film, an amorphous silicon film, a silicide film, or the like may be used as a silicon-containing conductive film.
To attain the third object, a fourth method for fabricating a semiconductor device according to the present invention assumes a method for fabricating a semiconductor device by using a dry etching apparatus having a dual power source capable of independently controlling source power for generating a plasma in a chamber and bias power for drawing ions from the plasma into an object to be etched in the chamber, the method comprising the steps of: placing a silicon substrate formed with a trench for isolation in the chamber; introducing a process gas containing at least oxygen into the chamber in which the silicon substrate has been placed; forming a silicon oxide film by generating a plasma of the process gas by applying the source power without applying the bias power and thereby oxidizing portions of the silicon substrate located adjacent wall and bottom surfaces of the trench for isolation; and forming an isolation by retrieving the substrate from the chamber and filling an insulating film in the trench for isolation formed with the silicon oxide film.
The fourth method for fabricating a semiconductor device oxidizes the portions of the silicon substrate located adjacent the wall and bottom surfaces of the trench for isolation by applying the source power without applying the bias power by using the dry etching apparatus having the dual power source and thereby forms the silicon oxide film. As a result, a surface state in the portions of the silicon substrate located adjacent the wall and bottom surfaces of the trench for isolation can be reduced without using an oxidation furnace. In addition, the breakdown voltage of the isolation can be increased by rounding up the corner portions of the trench for isolation. This achieves a significant reduction in the fabrication cost for the semiconductor device. Moreover, the fourth method for fabricating a semiconductor device allows simultaneous oxidization for removing the damaged layer with oxidization for lowering the surface state and increasing the breakdown voltage by more deeply oxidizing the portions of the silicon substrate located adjacent the wall and bottom surfaces of the trench for isolation than the damaged layer formed during dry etching. In this case, the cleaning step for removing the oxidized damaged layer can be omitted.
The step of forming the isolation of the fourth method for fabricating a semiconductor device may include the step of forming the insulating film on the silicon substrate such that the trench for isolation is completely filled with the insulating film, planarizing a surface of the silicon substrate including a surface of the insulating film by CMP, and thereby removing a portion of the insulating film located externally of the trench for isolation.
To attain the first object, a dry etching apparatus according to the present invention assumes a dry etching apparatus having a dual power source capable of independently controlling source power for generating a plasma in a chamber and bias power for drawing ions from the plasma into an object to be etched in the chamber, the apparatus comprising: bias power applying means for initializing and operating a timer at the same time as application of the bias power is initiated; and source power applying means for initiating application of the source power when an elapsed time measured by the timer reaches a specified time.
In the dry etching apparatus of the present invention, the source power applying means initiates the application of the source power when the time elapsed from the time at which the bias power applying means initiates the application of the bias power reaches the specified time. In short, the application of the bias power is inevitably initiated before the application of the source power is initiated. Even if etching is performed with respect to the silicon-containing material as the object to be etched by using a process gas containing oxygen, therefore, the ions in the plasma can surely be drawn into the silicon-containing material by initiating the application of the bias power before the silicon-containing material is oxidized by oxygen radicals generated in the plasma with the application of the source power. This prevents the situation in which the drawing of the ions from the plasma into the silicon-containing material is inhibited by an oxide film formed on a surface of the silicon-containing material and surely prevents a halfway halt in dry etching performed with respect to the silicon-containing material.

Dry etching method, fabrication method for semiconductor device, and dry etching apparatus

Matsushita Electric Industrial Co., Ltd.


A merchandise saddle display system for attachment to a vertical wall of a display case, including a male back containing at least two vertically aligned slots, and means for attaching the male back to the vertical wall, a saddle adapted to be cantilevered from the male back, the saddle having means for supporting at least one merchandise package, and engaging means mounted from the saddle for detachably securing the saddle to the male back, and including at least one engaging member having a body portion and at least one upper and at least one lower tab, each of the tabs being adapted to be received within the slots, the upper and lower tabs being spaced from the body portion, wherein the upper tab is spaced to a greater distance from the body portion than the lower tab for facilitating insertion and removal of the tabs into and from the slots, whereby the saddle is easily removable and replaceable in the vertically aligned slots on the male back.

Merchandising display systems are old and well known. There are many variations of display systems which are used in supermarkets, groceries, drugstores, and sundry stores. Generally the displays consists of a floor platform with a vertical upright peg board. The board carries either ordinary inserts or specially designed members which can be locked into a desired position.
Refrigerated desserts are normally merchandised in four and six packs in small cups wrapped with a chip board paper sleeve. The current practice is to display them on a double peg hook or standard shelf. The double peg hook is attached to traditional cross or peg bars which are retrofited to be placed in traditional dairy cases containing products such as shredded cheese, sliced cheese, or prepackaged deli, luncheon meat and turkey slices. However the current prior art construction is neither proprietary to the product packaging nor is it particularly efficient. For example, if pudding packaging is hung, the peg hook flap and the needed display space on the top of the package wastes approximately one and one quarter inches of space over each package size. This accounts for approximately thirty percent of the available cubic volume in the refrigerated display cases.
The more efficient a cubic display space is, the more profitable that particular space can be. Thus it is desirable to increase the amount and attractiveness of the inventory presented within the display space.


A battery charger for use with different types of batteries, such as batteries requiring constant current charging, such as nickel cadmium (NiCd) and nickel metal hydride (NiMH) batteries, as well as batteries which not only require constant current charging, but also require constant voltage charging, such as lithium ion batteries. The battery charger includes a pulse width modulator circuit for controlling a power transistor to provide a constant current or a constant voltage output as a function of the battery characteristics. The battery charger may include dual pockets for charging two modular batteries on a time division multiplex basis. In the dual pocket application, power is divided between the two pockets as a function of the charging characteristics of the battery and the power dissipation of the power transistors used for supplying charging current to the pockets.

1. Field of the Invention
The present invention relates to a battery charger and, more particularly, to a battery charger for providing both constant current and constant voltage outputs suitable for charging batteries requiring constant current charging, such as nickel-cadmium (NiCd) and nickel metal hydride (NiMH), as well as batteries requiring both constant current and constant voltage charging, such as lithium ion batteries. The battery charger includes a pulse width modulator (PWM) for controlling a power transistor to provide a constant current or a constant voltage output to the battery being charged as a function of the battery characteristics. The battery charger may include dual pockets for charging two modular batteries at a time. In the dual pocket application, charging is divided between the two pockets on a time slice basis. In such a configuration, the power dissipation of the power supply and the power transistors used for supplying charging current to the pockets is monitored and controlled.
2. Description of the Prior Art
Various portable devices and appliances, such as cellular phones, require rechargeable batteries. Various types of rechargeable batteries are known to be used in such applications. For example, nickel-cadmium (NiCd), nickel metal hydride (NiMH), as well as lithium ion batteries are known to be used. Because of the different charging characteristics of such batteries, different battery chargers are required. For example, both nickel-cadmium (NiCd), as well as nickel metal hydride (NiMH), require constant current charging. On the other hand, lithium ion batteries require constant current charging up to a certain voltage value and constant voltage charging thereafter. Because of the different charging requirements, different charging circuits are often required.
Standard battery packs normally consist of one or more battery cells disposed in a modular housing with external contacts for easy and convenient coupling with the portable device in which it is used. Smart battery packs, in addition to the battery cells, normally include a memory storage device which contains information regarding the characteristics of the battery as well as the battery type. Some smart battery packs are known to include a microcontroller which allows communication by way of a bi-directional communication line with the battery charger regarding various battery characteristics. Examples of such smart battery packs are disclosed in: "Smart Battery Specifications", .sup..COPYRGT. Duracell Inc., Intel Corporation, hereby incorporated by reference. Because of the differences between the standard battery packs and the smart battery packs, different chargers are used for the smart battery packs and the standard battery packs.
Battery chargers for charging batteries which require constant current charging and batteries which require constant current and constant voltage charging, such as lithium batteries, are known in the art. Battery chargers are also known that are adapted to automatically sense the type of battery connected to the battery charger and provide the appropriate charging characteristic. As mentioned above, such battery chargers are used for various portable devices, such as cellular phones. Cellular phone battery chargers are commonly available as single pocket and dual pocket devices. Dual pocket devices are known to be used for charging a spare battery, as well as the battery connected to the cellular phone. Unfortunately, with known dual pocket battery chargers, each pocket is known to be treated independently. In particular, in situations in which batteries to be charged are disposed in both pockets, the battery in the active pocket is normally fully charged before any servicing of the battery in the other pocket is done. Lithium ion batteries are known to take 3-4 hours to charge. Should a second battery be placed in the inactive pocket while a lithium battery is being charged in an active pocket, the second battery could remain in the inactive pocket for 3-4 hours before charging is even commenced. If the second battery also happens to be a lithium battery, it could take from 6-8 hours for the second battery to be charged from the time the second battery is inserted in the inactive pocket. Unfortunately, the end user will normally not be aware of such a limitation in the charging system.


An oscillation method and a device of fluorine molecular laser with narrow spectral line width are provided. For this purpose, the device includes main electrodes (14, 15) for performing main discharge (50) in substantially a same direction as an optical axis of laser light (11) to be oscillated to excite a laser gas containing fluorine, an insulator (12) which is held between the main electrodes and into which the laser gas containing fluorine is injected, and resonators (16, 18) which are placed with the insulator between them, and a space (M(λ)) of a vertical mode expressed in wavelength is made larger than full width at half maximum (Δλ) of a gain curve (R) of the laser gas.

Fluorine molecular laser devices are conventionally known, and, for example, Japanese Patent Laid-open No. 2000-216471 discloses one. FIG. 12 shows a fluorine molecular laser device 101 disclosed in the same Laid-opened Patent, and FIG. 13 shows a constitution of the fluorine molecular laser device 101 seen from a side, which is not disclosed in the same Laid-opened Patent. In FIG. 12 and FIG. 13, the fluorine molecular laser device 101 includes a laser chamber 102 in which a laser gas containing fluorine is sealed, and a pair of main electrodes 104 and 105 for exciting the laser gas by main discharge 150. A one-through fan 114 for leading a flow of the laser gas shown by the arrow 157 to an area between the main electrodes 104 and 105 and a heat exchanger 103 for cooling the laser gas are placed at predetermined positions in the laser chamber 102.
The main electrodes 104 and 105 are placed to oppose each other with the laser gas between them, and cause the main discharge 150 to a discharge space 151 by applying a high-voltage current from a high-voltage power supply 113 to excite the laser gas. A front mirror 106 and a rear mirror 108 are respectively placed in front of and at the rear of the laser chamber 102, and laser light 111 is oscillated in a rightward direction in FIG. 12, which is perpendicular to the main discharge 150. The method for causing the main discharge 150 perpendicularly to an optical axis of the laser light 111 with the main electrodes 104 and 105 being opposed to each other with the laser gas between them as described above is called a lateral excitation type.
As shown in FIG. 13, in the fluorine molecular laser device 101, preionization discharge is performed by preionization electrodes 110 as in an excimer laser device, whereby ultraviolet rays 100 are caused to perform preionization for the discharge space 151. As a result, the laser gas is ionized before the main discharge 150 occurs, and thereby the main discharge 150 is favorably performed. As a result, the laser light 111 with a wavelength of about 157 nm is emitted from the fluorine molecular laser device 101, and is used as a light source for an aligner for lithography, for example, or the like.
However, the prior art disclosed in the aforementioned Japanese Patent Laid-open No. 2000-216471 has the problem described below.
Namely, when the fluorine molecular laser device 101 is used as the light source of an aligner, it is necessary to narrow a spectral line width of the wavelength of the laser light 111 (this is called band-narrowing), and decrease chromatic aberration caused by an optical system of the aligner to improve resolution of exposure. In the conventional fluorine molecular laser device 101, the pressure of the laser gas is about 0.3 MPa to 0.4 MPa (about 3 atmospheres to 4 atmospheres). At such high pressure, pressure broadening in the spectral line width is increased, and the spectral line width of the laser light 111 in a state in which band-narrowing is not performed becomes as wide as about 1 pm. As a result, there arises the problem of reducing resolution of exposure.

Oscillation method and device of fluorine molecular laser


A rotary pawl latch has a lock bar that engages with the pawl when the pawl is latched and that moves toward the center of the pawl to release the pawl for unlatching. This lock bar never completely becomes disengaged from the envelope of the pawl. There are cutouts in the pawl which allow the pawl to rotate as the lock bar is actuated.

1. Field of Invention
The present invention relates to the field of latches.
2. Brief Description of the Related Art
Latches are relied on in many applications for securing, for example, doors in a closed position. Although many latches are known in the prior art, none are seen to teach or suggest the unique features of the present invention or to achieve the advantages of the present invention.


The invention is a compound motor having an internal combustion engine, a turbine driven by exhaust from the engine and compressor connected to the turbine. The compound motor has a clutch means to declutch the compressor from the turbine and to disable the turbine from transferring power to a gear set. The gear set is capable of simultaneously receiving power from the engine and the turbine and transferring this power to a final output shaft. The clutch mechanism brake or debrakes, and clutches or declutches, in response to torque or rotational force exerted on the turbine by the exhaust gas from the engine.

The invention relates to hybrid or compound motors wherein two engines of differing types are coupled together to drive a common output shaft.
The invention is a compound motor or power plant having a turbine engine or turbo unit, and having a rotary engine coupled with the turbo unit. The turbo unit, powered by exhaust from the rotary engine, can both turbocharge the rotary engine and drive a common output shaft. The common output shaft is also driven by the rotary engine. At lower motor speeds, the rotary engine will be more efficient than the turbo unit, and will supply all or most of the motor power, whereas at higher speeds the turbo unit will be more efficient and will supply most of the power. The compound motor has a planetary gear set connecting both the turbo unit and the rotary engine to the common output shaft. This gear set can simultaneously and independently receive drive inputs from the turbo unit and the rotary engine, so that turbo unit speed and rotary engine speed need not be matched. The turbo unit also includes a clutch assembly which selectively brakes the turbine of the turbo unit or disconnects a turbocharge compressor from the turbine. The clutch assembly operates in response to the torque exerted on the turbine by exhaust gases from the rotary engine.


A digital Storage Element is described. A device is configured including a Storage Element for access by a user responsive to a native control code. A processing arrangement executes a control program for controlling the overall device and executing at least a portion of the native control code as part of the control program for interfacing with the Storage Element. A programming arrangement is provided separate from the device for customizing a read channel within the Storage Element. Command, user interaction and data transfer execution are discussed for mitigation of potential mechanical shock effects. Status indications relating to the Storage Element are provided including head position and mechanical shock. Calibration, test and operational monitoring procedures, for using head position status, are described. Failure configuration monitoring is provided in tracking overall performance and design considerations.

The present invention is related generally to a digital device architecture and, more particularly, to a digital system configuration and associated method for devices including an electromechanical data Storage Element. The invention is particularly well-suited for use in a portable device.
One need only briefly survey virtually any public area in modem society in order to gain an appreciation for the popularity of electronic devices. Such devices include, but are not limited to cellular phones, music players, portable computers, personal digital assistants, pagers, digital cameras, digital camcorders, personal gaming devices and e-books. Continuous improvement has been seen in the capabilities present in these devices attributable, at least in part, to a movement into digital implementations.
Demands, with regard to future electronic devices, include further miniaturization coupled with still further improvements in performance. These demands are markedly intense with regard to portable devices. A particular area of concern resides in a desire to store ever-increasing amounts of digital information. At the same time, it should be appreciated that an electronic device, especially in a portable or miniaturized form, is likely to be subjected to a somewhat harsh environment, particularly with regard to mechanical shock. In an attempt to cope with the need for a significant amount of digital data storage while, at the same time, dealing with the problem of mechanical shock, designers resorted to the use of electronic memory, particularly in the form of flash memory. This solution is evident in the instance of state-of-the-art music players, including MP3 players. As of this writing, the popular configuration of these players is to use a removable flash memory card having a size of approximately 32 MB. Unfortunately, several problems are associated with this solution, as will be described.
One problem seen with regard to the flash memory solution resides in the fact that 32 MB is, in itself, a somewhat limited amount of storage. It is not unforeseeable that in the near future even amounts less than 512 MB will be considered as small. Considering present day devices, the owner of a portable device that relies on the use of flash memory cards typically must own a number of the cards in order to provide a sufficient overall amount of storage. Otherwise, the portable device owner may be forced to frequently reload the flash memory card via a personal computer or otherwise be subjected, for example, to listening to a quite limited music selection in the instance of an MP3 player. Moreover, the cost of flash memory cards is currently somewhat prohibitive. Many portable device owners simply choose not to incur the expense of buying numbers of additional flash memory cards.
In coping with the problems inherent in the use of flash memory cards, a recent alternative solution has been the provision of a larger, electromechanical digital storage arrangement that is nonetheless removable. This solution is exemplified by the IBM Microdrive™. The latter is a removable miniaturized computer hard disk drive provided with a connector that mates with a corresponding connector incorporated within the portable device to be served. It is noted that such miniature hard drives, including the Microdrive, have essentially the same configuration as prior art hard drives seen in personal computers. That is, the miniature hard drive is made up of two general assemblies including a head disk assembly (HDA) and a printed circuit board assembly (PCBA). The HDA itself includes a rotatable magnetic media, a sensor assembly for reading from and writing to the rotatable media and motors for accomplishing rotation of the rotatable media and positioning of the sensor assembly. The PCBA includes essentially all of the electronics needed to operate the HDA with the common exception of a preamplifier. While the Microdrive brings improvement in data capacity, as of this writing, the cost of the Microdrive is quite high in terms of megabytes per dollar and absolute cost when compared to such costs in conventional drives. It is submitted that this absolute cost, in and by itself, will prove to be a significant barrier with regard to broad-based use of the product.
The Microdrive utilizes a CompactFlash interface. This interface raises concerns for a number of reasons, not the least of which is the requirement for a rather bulky interface connector having fifty pins, as described in the CF+ and CompactFlash Specification Revision 1.4. Further concerns with regard to CompactFlash will be addressed below.
With regard to the removable configuration of the Microdrive, it is noted that the perceived need for removable media has been greatly reduced in certain environments once viable, significant levels of "permanently" installed storage space has been provided. Available embedded storage has traditionally taken a precedent over removable storage, as evidenced in desktop computers. Still further concerns are associated with removable storage, as will be discussed below.
While the use of a miniaturized bard disk drive effectively resolves the problem of limited storage by providing many times the storage currently available in a typical flash memory card, the issue of the use of such a component in the potentially harsh environment of a portable device is once again brought to the forefront. It should be appreciated that, under certain circumstances, prior art hard disk drives tolerate relatively high levels of mechanical shock- even as high as 1500 Gs. Under operational circumstances, unfortunately, hard disk drives are generally quite susceptible to mechanical shock events, for example, during the time that the head or sensing assembly is actually accessing the rotating media. Consequences of a mechanical shock event occurring at precisely the most inopportune time include potential drive failure. For instance, a drive may fail when subjected to a 175G event during an access. In this regard, Applicants are unaware of a miniaturized hard drive or overall device architecture incorporating effective features specifically intended to cope, for example, with the potentially harsh environment of a portable electronic device.
U.S. Pat. No. 6,061,751 (hereinafter the '751 patent), sharing the lead inventor of the present application, serves as one reference point with regard to several suggestions which may be utilized within a system incorporating a hard drive. The framework of the '751 patent, however, resides not in the area of drive miniaturization, ruggedization or portability, but primarily in reducing the cost of a hard disk drive as provided in an overall computer system. One approach taken by the patent encompasses moving all possible functionality out of the overall hard disk drive, including the controller, and onto the motherboard of the host device. For example, unused silicon "real estate" might be utilized for implementation of the controller. Moreover, such a controller may utilize memory that is already present on the host side. Thus, the drive cost is reduced to some extent. At the same time, it should be appreciated that the prior art functional control implemented as between the CPU and the controller is unchanged with respect to locating the controller on the motherboard. Specifically, the controller includes processing power which executes control code that is "native" to the peripheral device. As used herein, "native code" refers to the lowest level control code required to control a particular peripheral device. It is that code which is customarily executed by a device controller in a fashion that is isolated from the CPU resident within the host system.
FIG. 1 is a representation of FIG. 2 of the '751 patent, including alternative reference numbers assigned consistent with the present discussion. Accordingly, a prior art computer system 10 includes a host circuit board 12. A controller 14 is included as a single integrated circuit having further functions, as will be mentioned. A servo integrated circuit 16 is used to spin motors in any attached peripheral devices. Three peripheral devices are shown including a head disk assembly (HDA) 20, a CDROM/DVD 22 and a floppy drive 24. Alternatively, the latter may comprise a high capacity floppy drive, a miniature drive, or other suitable device.
One advantage, alluded to above, in the patent is the use of the HDA as an alternative to a complete hard disk drive (HDD) since costs are lessened by including components such as, for example, controller 14 within the host system. Components of the HDA (described above, but not illustrated) include a data media, a sensor/head mechanism to read and/or write data to and from the media, and motors to spin the media and position the sensor/head mechanism. A preamplifier is included to amplify the data read from or to be written to the media. The preamplifier may be installed on a flex circuit (see item 17 in FIG. 1A of the '751 patent) that electrically connects the HDA to the PCBA. It is appropriate to note, at this juncture, that the '751 patent also describes the location of a read/write channel, electrically in communication with the preamplifier, as potentially being arranged in the host system, distributed between the host system and the peripheral device or being within the peripheral device. The conventional location of the read/write channel in prior art HDD's is on the PCBA in close physical proximity to the electrical connection point of the HDA, for reasons described below.
Continuing with a description of FIG. 1, each peripheral device may also have an associated personality ROM 26. The specific location of the personality ROM is shown for an individual component in FIG. 3 (item 64) of the '751 patent. It is noted that the personality ROM is isolated from the rest of the individual component and is accessed via the PCI arrangement. Integrated circuit 14, in FIG. 1, further includes peripheral component interconnect (PCI) bus functionality such that the integrated circuit is interfaced to a PCI bus 28. It is noted that PCI bus 28 comprises one example of a number of possible bus mastering buses. A CPU 30 and chipset 32 are provided with the chipset connected to PCI bus 28. CPU 30 is, in turn, interfaced with chipset 32. A RAM section 34 is also interfaced to chipset 32. It is important to note that CPU 30 is indirectly connected to the peripheral components. Specifically, PCI bus 28 is interposed between the peripheral components, including HDA 26, and the CPU. While this arrangement may be advantageous with regard to cost reduction, certain disadvantages that accompany this configuration will be considered at appropriate points below. For the moment, it is noted that system control is accomplished by the CPU issuing commands that are placed on PCI bus 28 in accordance with mandated PCI protocol. It is submitted that certain penalties are associated with this style of command configuration. For example, commands issued through levels or layers of protocol higher than the native code are particularly inflexible.
The present invention provides a highly advantageous digital device configuration and method that are submitted to resolve the foregoing problems and concerns while providing still further advantages, as described hereinafter.


A nanobioremediation method is for soil in a high-concentration polycyclic aromatic hydrocarbon (PAH)-contaminated site. The method includes adding a carbon nanomaterial and a base fertilizer to soil in a high-concentration PAH-contaminated site, evenly broadcast sowing alfalfa seeds to the contaminated soil, and keeping the soil moisture content at 60% of the field moisture capacity, and when the alfalfa grows to the flowering or maturity stage, harvesting and removing the plants from the contaminated soil.

Polycyclic aromatic hydrocarbons (PAHs) are a type of persistent organic pollutants composed of two or more benzene rings, and are common in the environment. Due to the carcinogenic, teratogenic and mutagenic effects, PAHs have been listed as priority pollutants by the United States, the European Union, etc. In addition, seven kinds of PAHs including benzo[a]pyrene and the like have also been included in the "Chinese environmental priority pollutants blacklist". In recent years, with the rapid development of industrialization and urbanization in China, PAHs have gradually accumulated in the soil. As shown in the Official Journal of National Survey on Soil Pollution released jointly by the Ministry of Environmental Protection and the Ministry of Land and Resources of the People's Republic of China in 2014, the points in PAH-contaminated soil exhibit an over-limit ratio of 1.4%, with points in the heavily-polluted soil accounting for 0.2%. PAHs are mainly accumulated in the heavily-polluted enterprise land, industrial wasteland, chemical industry park, oil-producing area, and sewage irrigation area and surrounding soil, and the PAH pollution in soil of these sites is characterized by complex types, high pollution concentration, wide pollution range or the like, thereby posing a great threat to the health of soil ecosystems and the safety of human settlements. In addition, for the development and reutilization of these lands, the government or land owners must conduct risk assessment and remediation for soil in the contaminated sites, and it usually needs to achieve the remediation target value within a short time. Therefore, it has become an urgent and important environmental science and technology problem in China to develop an efficient, low-cost, environment-friendly and sustainable soil remediation technology for soil in a high concentration PAH-contaminated site.
The current remediation techniques for PAH-contaminated soil mainly include washing remediation, chemical oxidation remediation, thermal desorption remediation, biological remediation or the like. However, the above techniques all have limited application scopes and some defects, and thus need to be further improved. For example, the washing remediation will produce a large amount of washing wastewater for organic contamination, requires complicated technical operations, has high requirements on the equipment, and tends to cause secondary pollution (Sun et al., 2013); the chemical oxidation technique will increase the base ion content in soil as a lot of oxidant is added to the soil, which changes the physical and chemical properties of the soil itself and causes the soil to have decreased permeability and texture (Tsitonaki et al., 2010); the thermal desorption remediation technique has high requirements on the equipment, high remediation cost, and long remediation period (Chen, 2004); and the biological remediation mainly includes plant remediation and microbial remediation, and such techniques have advantages, such as simple and convenient operations, low remediation cost, environmental protection and no secondary pollution, and thus demonstrate promising research and application prospects in the field of remediation for the organic-contaminated soil. For example, as described in Chinese patent 201010547623.2, the degradation of PAHs in soil is achieved by adding biosurfactant (rhamnolipid) to the soil, planting alfalfa in the soil and inoculating a bacterial agent comprised of arbuscular mycorrhizal, Bacillus and the like in the soil; and as reported in Chinese patent 201610438092.0, a bacterial agent formulated by chitosan, zeolite powder and the like can effectively degrade or adsorb PAHs in the soil. However, with low removal efficiency and long remediation period, the current bioremediation technology is only suitable for the remediation of soil in a low-concentration PAH-contaminated farmland, but not suitable for the rapid and environment-friendly remediation of soil in a high-concentration PAH-contaminated site.
Nanomaterials are a class of materials that have basic units sized within the nanoscale range (1 nm to 100 nm) in at least one dimension of the three-dimensional space or are composed of such basic units. Nanotechnology has been listed by many countries as an important area among top priorities for research and development in the 21st century (Xiao et al., 2009). The nanomaterial shows huge application potential in many fields such as environment and agriculture due to its unique characteristics such as surface/interface effect, small size effect and quantum size effect (Adeleye et al., 2016; Prasad et al., 2017). Studies have shown that carbon nanomaterials are widely used as adsorption materials for organic pollutants and heavy metal ions in sewage treatment (Santhosh et al., 2016), and magnetic carbon nanomaterials can achieve the adsorption and removal of PAHs and antibiotics in water environments (Shi, 2013), but there are few reports on the application of carbon nanomaterials in the field of remediation for contaminated soil. Some carbon nanomaterials can promote the germination and growth of plants, enhance the stress resistance of plants (Ren et al., 2016), and change the microbial community structure in soil, but there is no report about the application of carbon nanomaterials in the bioremediation of high-concentration PAH-contaminated soil.

Nanobioremediation method for soil in high-concentration polycyclic aromatic hydrocarbon (PAH)-contaminated site

INSTITUTE OF SOIL SCIENCE, CHINESE ACADEMY OF SCIENCES


Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.

The present invention generally relates to termination impedances and more particularly to dynamically controlling termination impedances for input and output pins.
Data rates at integrated circuit input and output pins have increased dramatically the last several years, and further increases are sure to follow. These high data rates place strict requirements on signal integrity. Transmitted and received signals need to be substantially free from glitches and other undesirable artifacts to maintain the highest possible data rates.
Reflections due to impedance mismatches are one source of these artifacts. Reflections are caused when a signal is received from a transmission line by a receiver having an impedance that does not match the impedance of the transmission line. In short, this mismatch prevents some of the energy of the signal from being absorbed by the receiver. This unabsorbed energy is reflected back to the signal source. To prevent these reflections, a receiver termination impedance is connected from a receiver input to an AC ground, where the termination impedance matches the transmission line. Similarly, reflections can be caused by mismatches between a transmitter and its transmission line, so a source termination impedance is connected between a transmitter output and the transmission line.
The receiver termination impedance is in parallel with the receiver, so it is referred to as a parallel termination. Similarly, a source impedance is in series with a transmitting circuit, and is referred to as a series impedance. When signaling is limited to one direction, fixed series and parallel terminations can be used. A difficulty arises when bidirectional (or full duplex) signaling is used. A parallel termination used to receive signals creates an impedance mismatch when transmitting data. Similarly, a series termination used when transmitting causes an impedance mismatch when data is received.
It is desirable to be able to switch these impedances in and out of their transmitting and receiving circuits. That is, when one integrated circuit is transmitting, that integrated circuit should have a series termination, but when it is receiving, a parallel termination is required.
Accordingly, what is needed are circuits, methods, and apparatus that provide dynamic control of these series and parallel termination impedances.

Dynamic termination-impedance control for bidirectional I/O pins


The invention discloses a flexible printed circuit board, a chip on film and a manufacturing method. The flexible printed circuit board used for hot pressing includes an insulating substrate with long edges; the insulating substrate is provided with a plurality of pins used for hot pressing; the pins of the flexible printed circuit board used for hot pressing are along the long edge of the insulating substrate; the spacing between two adjacent pins is gradually reduced from both ends to the middle. In the invention, after hot lamination, the spacing between the pins can almost keep constant and is equivalent to the expansion result of the LCD panel; thus, better electrical connection of the pins and the leads of the LCD panel can be ensured, and electrical contact is more reliable.

The flexible printed circuit board is also called "flexible board", is a printed circuit made of a flexible insulating substrate, and has many advantages not available to a rigid printed circuit board. For example, the flexible printed circuit board can be freely bent, coiled and folded, and can be arbitrarily arranged according to space layout requirements, and arbitrarily moved, expanded and contracted in a three-dimensional space, thus achieving integration of assembly of components and wire connection. The flexible printed circuit board can be used for greatly reducing the volume of electronic products, and adapts to the need of the electronic products for development of high density, miniaturization and high reliability. Thus, FPC is widely applied in the fields or products of aerospace, military affairs, mobile communication, portable computers, computer peripheral, PDA (Personal Digital Assistant), digital cameras, etc. In a conventional flexible printed circuit board formed by hot-press laminating, because of a heat expansion effect, the positions of pins of the conventional flexible printed circuit board may be deflected; in the application occasion with enormous number of the pins and small spacing, alignment errors may easily occur if the pins are deflected, resulting in poor contact or forming wrong electrical connection.
A chip on film in an LCD panel is used as an example to explain:
An LCD device includes a backlight module and an LCD panel. The LCD panel is provided with a plurality of criss-cross scan lines and data lines; the scan lines or the data lines extend to the edges of the LCD panel to form leads used for connecting with an external circuit board. Because there are enormous scan lines and data lines, and it is difficult to process by a conventional welding process, a chip on flex is generally adopted, and a hot-press laminating mode is adopted for fitting and fixing the pins of the chip on film with the pins of the data lines or the scan lines to form electrical connection. The pins on the conventional chip on film are equally spaced; the corresponding leads on the LCD panel are also equally spaced; the pins and the leads correspond one by one and keep high-precision overlapping; because the spacing among the pins and the spacing among the leads are too small, and the reliability of direct butt joint is not high, a layer of anisotropic conductive adhesive shall be arranged between the chip on film and the LCD panel; conductive particles are included in the anisotropic conductive adhesive; after the flexible printed circuit board and a glass substrate are hot laminated, the spacing among the leads and the pins is minimal; thus, anisotropic conductive adhesive in the middle is extruded, and the conductive particles among the leads and the pins are compacted, deformed and mutually butted to form an electrical pathway; one end of the electrical pathway is butted against with the lead; and the other end of the electrical pathway is butted against the pins to realize the electrical connection among the leads and the pins. The spacing among the leads and the pins is large, the conductive particles are still in a loose state, and the conductive particles are almost separated; thus, two adjacent leads or pins will not be short-circuited and the reliability of the electrical connection is enhanced.
The problem in the prior art is that: the expansion coefficient of colloid material among the leads on the flexible printed circuit board, such as chip on film, etc., is large; so during hot bonding, enormous heat of a laminating head may cause that the leads are not equally spaced; for the chip on film, the expansion extent of the corresponding LCD panel is small, resulting in that the pins of the chip on film and the leads of the LCD panel are difficult to better overlap, and signal transmission is abnormal.

Flexible printed circuit board, chip on film and manufacturing method

SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.


An apparatus for generating a DBI signal in a semiconductor memory apparatus includes a data switching detection unit that detects whether or not previous data is consistent with current data and outputs a detection signal according to a detection result, and a DBI detection unit that outputs a DBI signal according to a difference in charge sharing level using the detection signal. Therefore, it is possible to minimize current consumption. Further, since there is no effect due to resistance skew of a transistor, an error in DBI signal generation and an error in data transfer accordingly can be prevented. Therefore, it is possible to improve the reliability of a system to which a semiconductor memory apparatus is applied.

1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to an apparatus and a method of generating a DBI signal in a semiconductor memory apparatus.
2. Related Art
A DBI (Data Bus Inversion) system is used in order to prevent a problem, such as simultaneous switching noise or inter symbol interference, that occurs as the number of data bits to be switched increases upon data transmission, that is, as the number of currently switched data bits among the entire data bits becomes larger than the number of previously switched data bits.
In the DBI system, in order to solve the above problem, when the number of switched data bits is half or more of the number of all data bits, a DBI signal (DBI Flag) is enabled, and inverted data is transmitted, instead of original data, thereby reducing the number of switched data bits to half or less.
Hereinafter, the related art will be described with reference to FIG. 1.
As shown in FIG. 1, an apparatus for generating a OBI signal in a semiconductor memory apparatus according to the related art compares previous data PREV_DATA and current data CURR_DATA, each of which has N+1 bits from 0 to N, using an XOR gate.
When a previous data bit is different from a current data bit, a signal corresponding to the changed bit among signals EVAL<0:N> is enabled and inverted signals EVALB<0:N> of the signals EVAL<0:N> are generated.
At this time, when the previous data bit is consistent with the current data bit, a signal corresponding to the unchanged bit among signals EVALB<0:N> is enabled.
The signals EVAL<0:N> and the inverted signals EVALB<0:N> are correspondingly input to inverter arrays whose output terminals are connected to the same node. The outputs of the individual inverter arrays are input to a negative input terminal (−) and a positive input terminal (+) of a comparator.
At this time, the number of P-type transistors and N-type transistors to be turned on in the inverters varies according to the number of enabled signals among the signals EVAL<0:N> and the inverted signals EVALB<0:N>.
Accordingly, a voltage difference occurs between the negative input terminal (−) and the positive input terminal (+) of the comparator according to a resistance ratio between the P-type transistor and the N-type transistor. The comparator outputs a DBI signal at high level or low level according to the voltage difference.
For example, when N=7 and the number of enabled signals among the signals EVAL<0:N> is four or more, the voltage at the negative input terminal of the comparator becomes lower than the voltage at the positive input terminal thereof, and the DBI signal is enabled (for example, a high level). Otherwise, the DBI signal is disabled, that is, the DBI signal changes to a low level.
However, the apparatus for generating a DBI signal in a semiconductor memory apparatus according to the related art has the following problems.
First, since the outputs of the inverters are connected to the same node, a short circuit current may be generated, thereby increasing current consumption.
Second, there may be an error in DBI signal generation due to resistance skew of a transistor of each inverter, which causes an error in data transfer. As a result, an operation error in a system to which a semiconductor memory apparatus is applied may occur.

Apparatus and method of generating DBI signal in semiconductor memory apparatus


The subject matter of the present invention relates to a cleaning device for a combine harvester, with a precleaning sieve, to the upper surface of which a mixture of grain and chaff can be fed during the operation, an upper sieve, to which the mixture of grain and chaff rearwardly discharged from the back surface of the precleaning sieve can be fed, a lower sieve, to which the mixture of grain and chaff passing through the precleaning sieve can be fed, and with a fan for applying currents of air to the precleaning sieve, the upper sieve and the lower sieve. On its way between the precleaning sieve and the lower sieve, the mixture of grain and chaff that has passed through the precleaning sieve be passed via a grating which is permeable to air and disposed separately from the lower sieve, to which grating a current of air can be applied by the fan as well.

A combine harvester with a multi-drum threshing system has been described in the German Patent DE 30 42 734 C. The mixture of grain and chaff passing through openings in the threshing concave and the downstream separating baskets is fed via grain pans to a cascade pan to which a rearwardly directed current of air is applied via an upper fan outlet. Disposed below this cascade pan is a precleaning sieve to which a current of air is also applied via the upper fan outlet, and disposed below said precleaning sieve is an additional grain pan. The rearwardly moving mixture on the upper surface of the precleaning sieve falls on an upper sieve, while the precleaned grain and chaff which fall downwardly through the precleaning sieve are transported via the additional grain pan to a lower sieve. A rearwardly directed current of air is applied to the upper and lower sieves by means of a lower fan outlet.
The disadvantage of this design is that the precleaned mixture of grain and chaff which has been passed through the additional grain pan to the lower sieve is compacted to a relatively high degree since it was passed only through the precleaning sieve and was subsequently transported through the additional grain pan. A cascade pan is, in fact, disposed between the additional grain pan and the lower sieve, but only a relatively low current of air is applied to said cascade pan. Thus, compacted material falls onto the lower sieve, which, given a certain sieve opening, limits the potential throughput through the lower sieve and thus through the combine harvester. It is possible to further open the fins of the lower sieve in order to increase the throughput; however, this has a detrimental effect on the cleanness of the ultimately harvested grain.


A printed circuit board which is thin and incorporates a large-capacitance capacitor function and a manufacturing method thereof. In one embodiment, the printed circuit board manufacturing method includes forming inner layer conductor circuits on a core substrate; forming a recess part on the core substrate; housing, in a recess part, a planar capacitor device that is not resin molded and has electrodes on the surfaces on a shared side; interposing the same between insulator resin and conductor metal foil to heat pressurize the same for forming a multi-layer plate; forming via holes for electrically connecting an outer layer conductor circuit to the electrodes of the capacitor device; forming a conductor layer on them; and forming the outer layer conductor circuits on the surfaces of the multi-layer plate.

1. Field of the Invention
The present invention relates to a printed circuit board and a manufacturing method thereof. More specifically, the present invention relates to a multi-layer printed circuit board incorporating a capacitor function and a manufacturing method thereof.
2. Description of Related Art
With the higher performance of electronic equipment, the number of parts mounted on a printed circuit board is being increased. Due to the miniaturization of electronic equipment, the size of the printed circuit board is required to be further reduced. The area on which the parts can be mounted is being made smaller.
With reduction of the parts in size, the density of surface mounting is becoming higher due to microfabrication of the conductor pattern of the printed circuit board.
The increased number of leads of mounted parts, smaller pitch, increased wiring resistance with a higher multi-layer printed circuit board due to a growing number of mounted parts and finer lines, signal delay due to cross talk noise, heat generation, and malfunction of the equipment with these become problems.
To solve these problems, the wiring length of parts need to be reduced. Specifically, there are proposed a method of burying the parts into a printed circuit board as well as of mounting the parts on the surface of the printed circuit board, and a method of incorporating a function equal to that of the parts into a printed circuit board using a high dielectric sheet material having a high dielectric constant and a paste material. Such techniques disclosed in Japanese Published Unexamined Patent Application Nos. 2002-100875 and Hei 6(1994)-69663 are known.
According to the above related art, the formation of a recess part on the printed circuit board to incorporate a smaller chip part therein to is proposed. At present, the printed circuit board is required to be thinner. Although the chip part is being made smaller, its thickness cannot be sufficiently small, obstructing making the printed circuit board thinner.
The smaller chip reduces the capacitance of a capacitor. It is difficult to respond to a request to make the capacitance larger.

Printed circuit board and manufacturing method thereof


Systems, storage media and apparatus for voice separated server architecture for privacy of a plurality of users of a massively multiplayer online game (MMOG) enabling a gaming computing environment that is separate from a voice channel for the plurality of users of the massively multiplayer online game (MMOG) are disclosed. Some embodiments may include: communicating with a gaming server for a Massively Multiplayer Online Game, the gaming server enabling a Massively Multiplayer Online Game environment, communicating with a voice server for the Massively Multiplayer Online Game, the voice server for the Massively Multiplayer Online Game being completely separate from the gaming server enabling privacy for the plurality of users of the massively multiplayer online game, and providing a MMOG primary voice channel, integrating the MMOG primary voice channel and the Massively Multiplayer Online Game environment, enabling a subsection of the plurality of users to verbally communicate.

Millions of children of afflicted parents are falling through the cracks when the parents of the children get sick. Medical and family support systems focus on the patient and existing support structures cannot cope with supporting the children of sick parents. For example, children afflicted by sick parents include 2.85 million children from at least one parent suffering from cancer and 10 million children from at least one parent suffering with substance abuse (e.g., alcoholism). (Sources: New York Times 2020/01/09; Cancer 116(18): 4395-4401, 2010).
A deep impact on children is manifested in later life problems including a Cycle of Psychological Damage the includes the following manifestations. Disruption of daily routine including sleeping problems and post-traumatic stress. The Cycle of Psychological Damage further includes role changes, with increased responsibility for children and loss of childhood. The Cycle of Psychological Damage also includes emotional problems for children (e.g., aggression and hostility, guilt, fear, anxiety). The Cycle of Psychological Damage further includes that effects social functioning of children such as little "fun"/positive reinforcement and shunning friends due to depression. The Cycle of Psychological Damage further includes fracturing of child/parent relationship such as inability to cope with each other open communication may be blocked. Thus, there is a need for systems and methods to help children cope when their parents are sick.

Voice separated server architecture systems for privacy of massively multiplayer online games