An image processing method includes the steps of performing resolution conversion processing on input image data to increase the number of grayscale levels, performing edge enhancement processing to increase the number of grayscale levels of the input image data, and performing dithering processing to reduce the number of grayscale levels of each pixel of the input image data. The number of pseudo grayscale levels is determined, based on a combination of a parameter concerning the resolution conversion processing and a parameter indicating the level of the edge enhancement processing.

1. Field of the Invention
The present invention relates to image processing methods and apparatuses, and more particularly, to a method for processing digital image signals.
2. Description of the Related Art
Thin display devices, liquid crystal displays (LCDs), plasma displays (PDPs), and field emission displays (FEDs) have attracted attention.
The LCDs, PDPs, and FEDs are fixed-pixel matrix-driven display devices, which can be driven by digital image signals. The number of grayscale levels of the above-described display devices is represented by the number of bits of a video signal corresponding to each pixel.
Techniques for displaying images so that they can be visually aesthetic to the human eye by performing signal processing on image signals are being considered. Such techniques include edge enhancement processing for enhancing edge portions and high-frequency components of images so as to apparently increase the resolution of the images.
FIG. 8 illustrates the configuration of an edge enhancer 800 for performing edge enhancement processing on image signals.
An image signal input from an input terminal 801 is output to a high-pass filter 803 and also to an adder 807.
The high-pass filter 803 extracts high-frequency components of the input image signal and outputs the resulting image signal to a multiplier 805.
Under the control of a controller 809, the multiplier 805 multiplies an enhancement coefficient, indicating the level of enhancement of the high-frequency components of the image, by the high-frequency components, and outputs the resulting signal to the adder 807. By controlling the enhancement coefficient, the level of enhancement of the high-frequency components of the image can be adjusted.
As the bit precision of the high-frequency components which are output from the multiplier 805, an 8-bit image signal input from the input terminal 801 can be increased to a 12-bit image signal by the high-pass filter 803 and by the multiplier 805.
Then, the adder 807 adds the original 8-bit image signal and the 12-bit high-frequency components output from the multiplier 805 and outputs the resulting 12-bit image signal having enhanced high-frequency components to a rounding unit 811.
By outputting an enhancement coefficient having a negative sign from the controller 809, the image can be made smoother instead of enhancing the edges.
To convert the 12-bit image signal into an 8-bit image signal, the rounding unit 811 truncates the lower four bits of the 12-bit image signal by a rounding operation, and outputs the resulting 8-bit image signal to an output terminal 813.
FIG. 9 illustrates the configuration of an image processing apparatus for performing resolution conversion on an image signal before performing edge enhancement.
An image signal input from an input terminal 901 is supplied to a resolution converter 903.
The resolution converter 903 converts the resolution of the input signal to the resolution of a display device (not shown) under the control of a controller 909.
If, for example, the horizontal resolution and the vertical resolution of the display device are 1280 pixels and 720 pixels, respectively, and if the number of horizontal pixels and the number of vertical pixels of an input image signal are 720 and 480, respectively, the horizontal resolution and the vertical resolution are scaled up by 16/9 and 3/2, respectively.
If, for example, the horizontal resolution and the vertical resolution of the display device are 1280 pixels and 720 pixels, respectively, and if the number of horizontal pixels and the number of vertical pixels of an input image signal are 1920 and 1080, respectively, the horizontal resolution and the vertical resolution are scaled down by ⅔ and ⅔, respectively.
If the input pixel signal has 8 bits, the resolution converter 903 expands the pixel signal into a 10-bit pixel signal to maintain the precision of the converted pixel signal, and outputs the 10-bit pixel signal to an edge enhancer 905.
Under the control of the controller 909, the edge enhancer 905 enhances high-frequency components of the image and outputs the resulting image signal to a rounding unit 907.
If the input pixel signal has 10 bits, the edge enhancer 905 expands the pixel signal into a 12-bit pixel signal to maintain the precision of the image signal with enhanced edges, and outputs the 12-bit pixel signal to the rounding unit 907.
To reduce the 12-bit pixel signal into an 8-bit pixel signal, the rounding unit 907 truncates the lower four bits of the pixel signal, and outputs the resulting 8-bit data to an output terminal 911.
Meanwhile, the controller 909 controls the resolution conversion (scaling) ratio in the resolution converter 903 and also controls the level of edge enhancement in the edge enhancer 905.
In printers, halftone processing using dithering processing has been performed as a binarizing method. In printers, such as that disclosed in Japanese Patent Laid-Open No. 2000-134471, images are divided into, for example, a character portion and a photograph portion, and different binarizing methods are used for these portions.
Japanese Patent Laid-Open No. 2003-69830 discloses an image processing method for performing resolution conversion and dithering processing.
When edge enhancement is conducted after performing resolution conversion and when the resulting image is then rounded, pseudo contours may easily occur depending on the type of image.
When enlargement processing is performed, the correlation of adjacent pixels becomes high, and pseudo contours easily occur, which is visually noticeable.
To prevent the occurrence of pseudo contours, dithering processing can always be performed instead of the rounding operation. In this case, however, dithering processing does not produce a noticeable effect on images subjected to resolution reduction processing or edge enhancement, since pseudo contours do not easily occur because of the low correlation between adjacent pixels of such images. Conversely, dithering processing easily produces an adverse influence, for example, noise having a fixed pattern, which is noticeable.


A nonvolatile semiconductor memory device includes a memory cell having a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node coupled to a word selecting line and a source/drain node coupled to a bit line, and the MIS transistor becoming conductive in response to a first state of the word selecting line and becoming nonconductive in response to a second state of the word selecting line, and a test circuit coupled to the bit line to sense a current running through the MIS transistor, the test circuit configured to indicate error in response to either a detection of presence of the current when the word selecting line is in the second state or a detection of absence of the current when the word selecting line is in the first state.

1. Field of the Invention
The present invention generally relates to a memory device, and particularly relates to a nonvolatile memory device which is capable of retaining stored data in the absence of a power supply voltage.
2. Description of the Related Art
Nonvolatile semiconductor memory devices, which can retain stored data even when power is turned off, include flash EEPROMs employing a floating gate structure, FeRAMs employing a ferroelectric film, MRAMs employing a ferromagnetic film, etc.
In the case of EEPROMs, there is a need to manufacture a transistor having a special structure comprised of a floating gate. In the case of FeRAMs and MRAMs, which achieve nonvolatile storage by use of a ferroelectric material and a ferromagnetic material, respectively, there is a need to form and process a film made of these respective materials. The need for such transistor having a special structure and the need for such film made of a special material are one of the factors that result in an increase in the manufacturing costs.
PCT/JP2003/016143, which was filed on Dec. 17, 2003, the entire contents of which are hereby incorporated by reference, discloses a nonvolatile memory cell (i.e., a basic unit of data storage) comprised of a pair of MIS (metal-insulating film-semiconductor) transistors that have the same structure as ordinary MIS transistors used for conventional transistor functions (e.g., switching function). Namely, these memory cell transistors use neither a special structure such as a floating gate nor a special material such as a ferroelectric material or a ferromagnetic material. These MIS transistors are configured to experience an irreversible hot-carrier effect on purpose for storage of one-bit data.
The hot-carrier effect leaves an irreversible lingering change in the transistor characteristics such as the threshold or on-resistance of the transistors. Changes in the characteristics of the MIS transistors caused by the hot-carrier effect achieve nonvolatile data retention. Which one of the MIS transistors has a stronger lingering change determines whether the stored data is "0" or "1".
A latch (flip-flop) circuit may be used together with the pair of MIS transistors for the purpose of reading (sensing) the data stored in the pair of MIS transistors. Such latch circuit may also be used to determine data to be stored in the memory-cell MIS transistors. That is, data to be stored as nonvolatile data may be first set in the latch circuit, and, then, the data stored in the latch circuit may subsequently be stored in the pair of MIS transistors. The latch circuit and the memory-cell MIS transistors together constitute a memory cell (memory circuit).
When a nonvolatile memory device having the nonvolatile memory cells as described above is manufactured, there is a need to conduct a test to ensure that the memory cells perform properly as designed. The latch circuit portion of each memory cell may properly be tested by use of a conventional SRAM test. The nonvolatile memory portion (comprised of a pair of memory-cell MIS transistors) of each memory cell, however, cannot be tested by use of a conventional test technique. This is because the operation of the nonvolatile memory portion is founded on an irreversible change of the transistor characteristics. If a test that creates such an irreversible change is actually performed, the memory circuit may no longer be usable.
Accordingly, there is a need for a nonvolatile memory device provided with a test mechanism that can test the operation of the memory cells without undermining the function of the memory cells where the memory cells include MIS transistors that are designed to experience an irreversible change in their characteristics for the purpose of nonvolatile data retention.

Nonvolatile memory device with test mechanism


A traffic shaping method and circuit of a packet switching system in which input packets having a fixed length and multiplexed on a plurality of inputs are multiplexed to be delivered on any output of a plurality of outputs, connects the input packet to a list structure using an address chain formed for each output, forms the list structure even for each line identifier provided in the packet, and assigns the identifier for each time slot of the output to take out the packet from the list structure, to thereby prevent the packet having the same identifier from being multiplexed and delivering to the output continuously.

The present invention relates to a traffic shaping method and system for a virtual path or a virtual connection in a packet switch of a cross connector or a switch for a fixed-length packet, and more particularly to a re-arrangement control method and system for a burst packet arriving from a subscriber line. Specifically, it is suitable for a cell switch in an apparatus using an ATM (Asynchronous Transfer Mode) system.
In the ATM system which complies with the international standard of the CCITT (International Telegraph and Telephone Concultative Committee) in regard to a broadband and multimedia communication in a communication field, a fixed-length packet named a cell is used to effect transmission and switching. Many switch systems for switching the cells have been proposed.
Further, in a transmission apparatus for connecting between switching systems, a virtual line named a virtual path is used as a unit to modify the architecture of the network flexibly and simplify the administration of the line. In this case, it is able to establish a plurality of virtual channels in each virtual path to realize plural pairs of inter-terminal communications on the same path by providing each cell with a virtual path identifier and a virtual channel identifier to discriminate its connection. An apparatus for switching the cell in accordance with the virtual path is employed and this apparatus is named an ATM cross connector. This cross connector is considered to be a kind of ATM switch.
One of the ATM switch system is a shared buffer memory switch. An example of its arrangement method is described in an article "LSI IMPLEMENTATION FOR SHARED BUFFER TYPE ATM SWITCH" by Kosaki et al., Technical Report of the Institute of Electronics, Information and Communication Engineers of Japan, SSE89-144, pp. 49-54 (February, 1990) and is shown in FIG. 2.
Generally, various terminal equipments connected to a subscriber line produce a so-called burst traffic having a period in which data is continuously produced and a period in which no data is produced. When an ATM switching system accommodates such a burst traffic, an amount of buffers required in the ATM switching system is known to require ten and several times to several tens times as large as that in the case where the traffic in which the cell occur at random is accommodated. Accordingly, in order to arrange the ATM network economically by using the cross connector having less amount of buffers, it is necessary to eliminate the burst traffic in the apparatus which accommodates the subscriber lines. To this end, it is necessary to arrange the cells belonging to the same virtual channel or virtual path extremely uniformly in time. This procedure is named the traffic shaping.
A method of effecting such a traffic shaping is described by way of example in an article "PATH HANDLING IN ATM NETWORKS" by Shigesada et al., Technical Report of the Institute of Electronics, Information and Communication Engineers of Japan SSE89-120 pp. 31-36 (January, 1990). More particularly, a system is described in which the traffic shaping is effected by previously determining a time position of the cell belonging to the virtual path or the virtual channel within a frame in an output of the switching system or the cross connector. Further, an algorithm for defining the time position for each output dynamically is also described.
In the switch arrangement by a shared buffer memory switch using the above conventional technique, the traffic shaping is not considered. Accordingly, the line having the burst traffic is switched and delivered while preserving the burst characteristic. As a result, there is a problem that a large amount of buffer memories are required in the cross connector or the switch connected to the output.
Further, even if the traffic shaping for each output is made by the above conventional technique, it is necessary to change the order of time in order to effect the traffic shaping. In this case, since a waiting buffer is required, there is a problem that a great number of buffers are required for a traffic shaping apparatus. On the other hand, by using the algorithm shown in the above conventional technique for dynamically defining the time position, reduction of the memory capacity is also shown. However, since an apparatus for executing this algorithm is complicated and it is necessary to lengthen the period of determining the arrangement to effect more uniform arrangement, there is a problem that the memory capacity is increased.
Further, when the memory capacity is increased, there is a problem that the time that the cell stays in the memory is made long and the delay in the transmission and switching is increased.


A system for representing line drawings by polygonal lines. In the system, a binary digital image is scanned in a main scanning direction to form picture element connection data with a first image picture element as a start point picture element which is scanned next to a first background picture element and with a second background picture element as an end point picture element which is scanned next to a second image picture element, and the relationships between the picture element connection data are detected to provide as picture element block data a group of picture element connection data which have predetermined relationships. Further, it is determined from each picture element block data whether or not the picture element block thereof represents a straight segment, and straight line approximation data is provided according to both the uppermost picture element connection data and the lowermost picture element connection data in the picture element block when it is determined that the picture element block represents a straight segment, whereby parts of the drawing to be represented by polygonal lines are detected and processed with high efficiency.

This invention relates to a system for representing line drawings by polygonal lines in which a line drawing is read as binary digital data, and the binary digital data are converted into polygonal line data.
A method of representing a line drawing by polygonal lines is often employed for data compression or data reuse, as is well known in the art. More specifically, the following three methods have been employed for representing line drawings by polygonal lines:
(1) A first method in which a line drawing is represented by a number of thin lines, and the resultant picture elements are traced (cf. Japanese Patent Application Unexamined Publication Nos. Hei. 1-134682 and Hei. 1-142880).
(2) A second method in which the contour lines of an image are extracted, and the center lines of the contour lines thus extracted are obtained.
(3) A third method in which an image is divided into a number of squares arranged in a matrix form, and the local pattern of each square is identified (cf. Japanese Patent Application Unexamined Publication No. Sho. 62-191988).
However, these methods are disadvantageous in that, since it is necessary for each of the methods to employ an image processing technique which accesses an image in its entirety, the image processing time is necessarily long, and it is essential to provide a large capacity memory because the image must be kept in memory during the image processing time.
On the other hand, a method has been employed in which polygonal lines are obtained from run data (cf. Japanese Patent Application Unexamined Publication No. Sho. 63-45687). In the method, straight segments different in inclination are detected from the variation between the gravity center values of the m-th run and the (m-n)-th run. However, the method depends only on the local data called "run" in the image, and therefore it cannot determine whether or not the run can be represented by polygonal lines. For instance, in the case of a solid arrow mark in a drawing, the method cannot detect its configuration from the run data.

System for representing line drawings by polygonal lines


The present invention provides a high-voltage detection circuit, detector, battery device and vehicle, the high-voltage detection circuit includes: a controller including a first signal input port, a second signal input port, and a signal output port; a current detection sub-circuit for sampling a current signal of internal side of a main negative switch and for transmitting the current signal to the first signal input port; a switch detection sub-circuit, a first end of the switch detection sub-circuit being configured to sample a first electric signal of external side of a to-be-detected switch, and a second end of the switch detection sub-circuit being configured to transmit the first electric signal to the second signal input port; and a switch driving sub-circuit, configured for sampling a switch control signal via the signal output port and generating a switch driving signal according to the switch control signal.

At present, the substitution from fuel vehicles to electric vehicles has become a developing trend in the automobile industry. However, the safety of vehicle batteries has become one of the problems that impede the promotion of electric vehicles. Now then, in order to reduce the safety risk of the high-voltage loop of the vehicle battery during operation, parameters of status of each relay in the high-voltage loop needs to be detected, so that the battery can be protected by adjusting the high-voltage loop when unsafe factors are detected.
In the related art, the detection circuit for each parameter in the high-voltage loop of the vehicle battery is connected to a battery management unit (Battery Management Unit, BMU) of a low-voltage section of the vehicle battery and is controlled by the BMU, so that a harness is required for connecting the low-voltage section to the high-voltage loop.
In order to allow both the low-voltage section and the high-voltage loop to work normally, an isolation unit is required for isolating the low-voltage section from the high-voltage loop. However, such a circuit design is complicated and error-prone, and the cost of the isolation unit is quite high.
Therefore, at least one technical problem exists in the related art, that is, the internal circuit structure of a vehicle battery is excessively complicated.

High-voltage detection circuit, detector, battery device and vehicle

CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED


A method for assembling a reinforced non-compressible pipe support by inserting a plurality of generally cylindrical holes in a first sheet of insulation in a pre-determined pattern, inserting a similar group of holes in at least a second sheet of insulation so that the holes of both sheets line up when the first sheet is placed against a pre-determined cylindrical or flat form and the second sheet is placed on top of the first sheet thereby forming contiguous voids where mating holes are positioned adjacent each other, applying a pressurized flowable material to fill each void along its longitudinal axis, and curing the material until it forms a hardened material thereby forming the plurality of sheets into a non-compressible arcuate body having an inner radius of curvature that fits against a pipe or into a rectilinear block. Multiples sheets may be adhered and thermoplastic or resin used to fuse them together.

Currently, pipe and other conduit used in various industrial applications including refineries are insulated by wrapping insulation in a continuous overlapping pattern. When the insulation approaches the location near where the pipe is supported, it must be stopped and restarted before and after the pipe support to maintain the load bearing characteristics of the pipe support. In this region where the pipe is supported, the wrapped insulation is positioned about the pipe in increased diameters of insulation to provide adequate insulation and maintain the proper load bearing characteristics. This is wasteful and creates areas of compromised insulation prone to thermal leakage and breaking of the insulation due to movement of the pipes caused by stresses placed on the pipe due to fluids or gases moving through the pipe. There thus exists a need to configure flexible insulation material in a manner to withstand compressive forces while maintaining a low profile about a pipe or other longitudinal member. In addition current methods of insulating tank bases require the use of very thick insulation that increases the overall height of a given tank. The use of the new insulation material reduces the tank height thus saving significantly on the materials required to build the tank.
In accordance with a preferred embodiment of the invention, there is shown a reinforced insulation material having one or more sheets of insulation material having a plurality of voids in each sheet, wherein the sheets are operably connected to each other in a layered configuration, the voids on each sheet are oriented in a mating pattern that generally forms cylindrical regions on the layered configuration, and a synthetic material inserted into the voids of each sheet to connect the sheets to each other.
In accordance with a preferred embodiment of the invention, there is shown a reinforced insulation material having a plurality of sandwiched sheets of insulation material, each sheet having a plurality of voids, the voids on each sheet oriented in a mating pattern to the voids on the other sheets to form cylindrical voids when connected together and a synthetic material inserted into the voids of each sheet to connect the sheets.
In accordance with a preferred embodiment of the invention, there is shown a reinforced insulation material having one or more sheets of insulation material having a void in each sheet, wherein the sheets are operably connected to each other, the void on each sheet oriented in a mating pattern to the void on said other sheets to form a three dimensional void when connected together, and a synthetic material inserted into the voids of each sheet to connect the sheets.

Method and system for reinforced pipe insulation


The present invention serves to reduce the costs associated with the overall life cycle of storage batteries by performing support so that a plurality of batteries are transferred between and used at a plurality of facilities. This storage battery transfer support device comprises: a collection unit that collects battery information representing the status of each battery used at a plurality of facilities; a battery information storage unit that stores the battery information collected by the collection unit; and a deterioration prediction unit that, on the basis of the battery information stored in the battery information storage unit, predicts deterioration of storage batteries that have been transferred between and used at a plurality of facilities.

In recent years, a large number of electric vehicles running with electric power from storage batteries, such as HEVs (Hybrid Electric Vehicles), PEVs (Plug-in Electric Vehicles), and EVs (Electric Vehicles), have been utilized. Examples of the storage batteries mentioned herein include a lithium ion secondary battery and a nickel hydrogen secondary battery.
Electricity storage systems for supplementing electric power supply using storage batteries have been put in practical use at, for example, houses, buildings, or factories. In such electricity storage systems, storage batteries are charged with surplus generated electric power or low cost midnight electric power, while the storage batteries are used to supply electric power to electric appliances when the amount of electric power generation decreases, or during a time period when the cost of a commercial power source is high, or when electric power is in shortage.
Moreover, as an example of the related art of the present invention, Patent Literature 1 discloses a power supply service system that manages the use state of the battery of a car and the customers and enables smooth charging and replacing of the battery.

Storage battery transfer support device and storage battery transfer support method

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


A battery includes a cell casing that has recessed portion on a major surface of the casing, the recessed portion being substantially planar and bordering a remainder of the major surface at ridge portions on at least three sides of the recessed portion, whereby the recessed portion, the ridge portions, and the remainder of the major surface cooperate under an increase of gauge pressure to cause a plane defined by a boundary between the ridge portions and the remainder of the major surface to move.

Li-ion batteries in portable electronic devices typically undergo different charging, discharging and storage routines based on their use. Batteries that employ Li-ion cell chemistry may produce gas when they are improperly charged, shorted or exposed to high temperatures. This gas can be combustible and may compromise the reliability and safety of such batteries. A current interrupt device (CID) is typically employed to provide protection against any excessive internal pressure increase in a battery by interrupting the current path from the battery when pressure inside the battery is greater than a predetermined value.
However, even in the absence of excessive internal pressure that would diminish performance or cause safety concerns, li-ion batteries undergo increased internal pressure during recharging. In prismatic cells, increased internal pressure causes the cell casing to flex. Depending upon the makeup and amount of electrode and electrolyte material within a cell casing, such as a 183665 prismatic cell casing, an outside diameter of about 18.02 mm can increase during recharging by over one millimeter, to about 19.5 mm. Use requirements of many battery types, including prismatic cells, often limit the space available for expansion during charge cycles, thereby restricting the types of batteries employed, their capacity, or the patterns of their use (e.g., removal from devices during charging).
Therefore, a need exists for a cell casing that significantly reduces or eliminates the above-mentioned problems.

Prismatic storage battery or cell with flexible recessed portion


A method for providing leased network addresses for a host from a server executing on a server device is disclosed. A first request for a leased network address from the host, relayed by an intermediate device, is received. The intermediate device filters communications between the host and the server device. A response is generated for the host, by the server, which offers a leased network address for a particular period of time and includes a network address of the intermediate device. The network address of the intermediate device is provided in a portion of the response normally designated for indicating a network address of the server. By providing the address of the intermediate device in the portion of the response designated for the server address, the server causes the client to send renewal requests to the intermediate device so that a relay process on the intermediate device can properly operate on the request, without modifying the client process.

A computer network includes computer processors or "hosts" that host software applications that provide or request services, or both. The hosts may be network terminals or end stations that do not perform network traffic routing or forwarding functions. The hosts communicate with each other through network devices, such as switches and routers, sometimes called intermediate devices, which do perform routing and forwarding functions. When a host is added to a network by connecting directly to another host, or indirectly to another host through one or more intermediate devices, the host must be configured for network operations. For example, the newly added host is assigned a logical network address for itself, and a network address for the intermediate device that routes or forwards its traffic, among other configuration information.
Computer networks that employ the Transmission Control Protocol and Internet Protocol (TCP/IP) for sending packets of information between devices on the network are proliferating, and as a result, logical network addresses that are used to locate each device on the network have become scarce. Further, in many local networks with many different computers, the number and location of the computers connected to the network may change regularly. In addition, of the many computers physically connected at one time, only a fraction of the computers are on and operating at one time. Thus one or more hosts are being added and dropped frequently.
A specific context in which this problem arises involves large-scale cable modem networks in which voice and other services are delivered over an Internet Protocol network that uses coaxial cable for communications. Addresses are dynamically assigned to cable modems of end users as the users subscribe to and terminate use of service, and to devices that cannot persistently store an address. In this context, it is wasteful to give every device a unique and permanent network address. A number of addresses sufficient for the total anticipated subscriber base can be shared, but configuring each host with a new address is a tedious process to perform manually.
The Dynamic Host Configuration Protocol (DHCP) provides a mechanism through which computers using TCP/IP can obtain network addresses and other configuration information automatically. DHCP is an open standard protocol for dynamic host configuration described in request for comments (RFC) documents numbered 2131 and 2132 available at the time of this writing as rfc2131.txt and rfc2132.txt, respectively, on the worldwide web (www) at domain and directory ietf.org/rfc/. A DHCP server process operates on a DHCP server host that is conveniently located for several hosts on one or more local networks. One or more DHCP server hosts and processes are set up by a system administrator with information to configure the hosts on one or more local networks to reflect the current architecture of those local networks. A DHCP client process operates on each host of the local networks. As used hereinafter, a server refers to the server process and a client refers to the client process unless otherwise indicated to refer to the host or device on which the process executes.
When a host begins operations on the local network, the DHCP client on that host requests configuration information from one of the DHCP servers. In response to the request from the DHCP client, one or more of the DHCP servers respond with configuration information to be used by the host of the DHCP client for a predetermined period of time ("lease time"), including an IP address for the host of the DHCP client. Such responses take the form of "offers" of data. The DHCP client notifies the servers that one of the offers is accepted. The host that is executing the DHCP client then uses the configuration information including the address. The configuration information is bound to the particular DHCP client, and the binding is recorded by the DHCP server that offered it.
At a first time, t1, when a substantial portion of the lease time has passed, the DHCP client sends a renewal request to the DHCP server indicating that the lease time should be extended. For example a renewal request may be sent when 75% of the lease time has elapsed. If the DHCP server of the accepted offer does not receive a renewal request from the DHCP client within the lease time, the DHCP server is free to offer that configuration information and IP address to another DHCP client after the lease time expires. If the DHCP client does not receive a response from the DHCP server to a renewal request by a second time, t2, after t1, when almost all of the lease time has passed, such as 95%, the DHCP client sends a rebinding request to all the DHCP servers to provide a new lease for the IP address the DHCP client is currently using.
A DHCP relay agent is a process that executes on an intermediate device to forward DHCP messages between DHCP client and DHCP server. The DHCP relay agent facilitates communications with the DHCP client before the DHCP client's host is bound to a particular IP address. The DHCP relay agent is used when the DHCP client cannot broadcast directly to the DHCP server because it is separated from that DHCP server by network routing elements. In this case, the DHCP relay agent on the router closest to DHCP client receives a broadcast to port 67 and then forwards the DHCP client's packet on to all DHCP server for which it is configured. In this way, the DHCP client can broadcast locally and still make contact with one or more DHCP servers.
A problem arises with the exchange of messages described above in circumstances in which the DHCP client and the DHCP servers cannot communicate directly. In such circumstances an intermediate device, such as a router, prevents direct communication between the DHCP client and the DHCP server. If either the DHCP client or DHCP server wishes to send information to the other, the sender directs the information in a message to the intermediate device and the intermediate device determines that the information is appropriate for sending to the other or not. In some circumstances, the intermediate device may alter the information in the original message, such as by adding to or deleting from the information in the original message, and send the altered message to the other. As used herein, when an intermediate device prevents direct communication, or receives and reviews information in a message in order to determine whether to forward the message, or alters information in the message, or performs any combination of these actions, the intermediate device is said to filter the communication. An example circumstance in which an intermediate device filters communications among hosts is when the intermediate device enforces some security policy, such as for a firewall. In some circumstances, hardware problems on a wire, interface, or intermediate device can lead to special processing by another intermediate device that constitutes filtering as used herein. Also, an intermediate device filters traffic when a host is on a virtual private network. In virtual private networks, routers are configured to communicate traffic between certain network addresses only when the traffic is encrypted at the intermediate device that routes the traffic onto a public network such as the Internet. If the DHCP server host is not among the certain network addresses, the intermediate device prevents direct traffic.
In circumstances in which an intermediate device filters the communications, the intermediate device prevents the DHCP renewal message sent from a DHCP client to the particular DHCP server that provided the original lease. With renewal messages blocked, clients are forced into risking the validity of their configuration information. The client is routinely forced to rely on use of re-binding requests to carry out renewal in the last hours of the lease time, although the re-binding was designed only for unusual circumstances. If the DHCP servers are off-line for maintenance or for updating by the system administrator at the time a re-binding request is sent, or out of available IP addresses, the client will lose its IP address and be unable to maintain or establish communication with other hosts on the networks until a new IP address is obtained.
If a relay agent is properly configured, the initial DHCP request of a client is not affected, because the initial request is a broadcast not directed to a particular DHCP server. Initial requests normally are issued to a well-known port number, most often "67." The intermediate device receives the broadcast, determines the value of the port from the message, recognizes it as a DHCP message if the port value is 67, and invokes the DHCP relay agent to handle the message. If the system administrator has made an exception for DHCP messages, e.g., allowing a host behind the firewall or on the VPN to use the local DHCP servers, the relay agent sends the message to the one or more local DHCP servers.
Direct communication messages that indicate a particular network address as a destination address are called unicasts. DCHP relay agents are not configured to check unicasts in which the intermediate device is not the destination, because doing so would severely impede network traffic through the intermediate device. Thus DHCP relay agents do not detect and process renewal requests because the renewal requests are unicasts addressed directly to the DHCP server that provided the configuration information bound to the DHCP client. It is not practical to implement an approach that has the relay agent inspect every unicast passing through the intermediate device to detect DHCP messages; because such a approach would severely impede network performance.
In another approach, the DHCP client could be modified to send renewal requests directly to the intermediate device. However, this approach is not practical because tens of millions of DHCP clients have already been deployed over the last decade without such a modification. It would be expensive and take many years to even replace a significant fraction of the deployed DHCP clients. In addition, a modification to the DHCP standard, as embodied in Internet Requests for Comment (RFCs), would be required. Such a change to the DHCP standard is not likely to be accepted, or if it is accepted, it would not be implemented quickly.
Based on the foregoing, there is a clear need for techniques that dynamically assign network addresses when communications between a client host and a server host are filtered by an intermediate network device, without modifying the client process.

Techniques for dynamic host configuration without direct communications between client and server


A flexible foam wedge, designed with a finger pocket and application tip with that allows for direct support of the applicator from a finger digit particularly useful for the application of cosmetics. The foam applicator comprises a base block defining the finger opening. The application tip, having any of a plurality of configurations extends from the base block. The applicator can be an integral unit, or can comprise separate components connected together. Further, various methods of manufacturing and using the applicator are provided.

1. Field of the Invention
The present invention relates to foam applicators for use on a finger or other digit. The foam applicators are particularly useful for the application of cosmetics.
2. Description of the Related Art
In the past, cosmetic applicators have taken a variety of shapes such as pads, rounds, puffs, swabs, etc. as a means for applying various cosmetic products. Direct hand application of cosmetic products is undesirable, since the fingers do not optimally retain or apply the cosmetic product. The use of swabs is common as it provides an extension for an applicator, although by nature it is a less direct method of cosmetic product application. Such a swab applicator is shown in WO 99/58017. Furthermore, applicators of the past have often been complicated or uneconomical for efficient use.


This invention relates to methods and compositions for bringing about changes in skin pigmentation. More particularly, this invention relates to compounds which affect melanogenesis and can be used as depigmenting agents or as agents for darkening skin utilizing the PAR-2 pathway.

Skin coloring has been of concern to human beings for many years. In particular, the ability to remove hyperpigmentation, such as found in age spots, freckles or aging skin generally, is of interest to individuals desiring a uniform complexion. In certain areas of the world, general body whitening is desirable. There are also hypopigmentation and hyperpigmentation disorders that are desirable to treat. Likewise, the ability to generate a tanned appearance without incurring photodamage due to solar radiation is important to many individuals. There have been many methods proposed to accomplish depigmentation, as well as to accomplish darkening of the skin. For example, kojic acid, hydroquinone, retinoids and other chemical compounds have been used for depigmentation. Dihydroxyacetone and like chemical compounds have been utilized for their ability to "tan" the skin without exposure to the sun.
Many of these previous solutions have not been found acceptable. There is often a distinct line of demarcation between the areas of skin to which such previous compositions have been applied. Therefore, precise application of all these compounds is necessary in order to achieve the desired result. Many of these compounds have been found to be quite irritating to the skin and therefore undesirable for use.
The understanding of the chemical and enzymatic basis of melanogenesis is heavily documented. Melanocytes migrate from the embryonal neural crest into the skin to produce secretory granules, melanosomes, which produce melanin. Melanogenesis occurs within the melanosome, and the melanin is later distributed to keratinocytes via the melanocyte dendrites. The key enzyme in melanogenesis is tyrosinase, which initiates a cascade of reactions which convert tyrosine to the biopolymer melanin. Two tyrosinase-related proteins (TRP's) are known, TRP-1 and TRP-2. These proteins share with tyrosinase about 40% homology and have catalytic activities as well as regulatory roles in melanogenesis. TRP-1 is the most abundant glycoprotein in melanocytes.
In spite of the fact that the chemical and enzymatic basis of melanogenesis is well-documented, its regulation at the cellular level is only partially understood. Tyrosinase and the TRP's share structural and biological properties with the lysosomal-associated membrane protein (LAMP) gene family, therefore their targeting to the melanosomal membrane might induce their activation. A phosphorylation/dephosphorylation reaction at the cytoplasmic tails of thes proteins could be involved in the regulation of melanogenesis. The beta isoform of the Protein Kinase C (PKC) family has been shown to regulate human melonogenesis through tyrosinase activation. Gene expression of tyrosinase, TRP-1 and TRP-2 is coordinated. All three enzymes are expressed in human epidermis. In melanocytes co-cultured with keratinocytes, these transcripts are expressed at a ratio of 45:45:10, respectively. In melanocytes cultured alone, only TRP-1 transcripts are present, indicating that a keratinocyte-derived signal is involved in the coordinate expression of these genes. The regulation of keratinocyte-melanocyte interactions and the mechanism of melanosome transfer into keratinocytes are not yet understood.
The Protease-activated receptor-2 (PAR-2) is a seven transmembrane G-protein-coupled receptor, that is related to, but distinct from the thrombin receptors (TR, also named PAR-1, and PAR-3) in its sequence. Both receptors are activated proteolytically by an arginine-serine cleavage at the extracellular domain. The newly created N-termini then activate these receptors as tethered ligands. Both receptors could be activated by trypsin, but only the TRs are activated by thrombin. Only PAR-2 is activated by mast cell tryptase. Both receptors could also be activated by the peptides that correspond to their new N-termini, independent of receptor cleavage. SLIGRL, the mouse PAR-2 activating peptide, is quipotent in the activation of the human receptor. While the function of the TR is well documented, the biology of the PAR-2 has not yet been fully identified. A role for PAR-2 activation in the inhibition of keratinocyte growth and differentiation has been recently described (Derian et al., "Differential Regulation of Human Keratinocyte Growth and Differentiation by a Novel Family of Protease-activate Receptors", Cell Growth & Differentiation, Vol. 8, pp. 743-749, July 1997).

This patent is subject to a terminal disclaimer.

Johnson & Johnson Consumer Companies, Inc


A method of estimating a virtual contour of an insulating material is disclosed. The method includes the following steps: obtaining a first and a second images at a pair of diagonal locations of the insulating material respectively; determining a first and a second corner locations from the first and the second images respectively; selecting a first set of longitudinal end-point positions and a first set of transverse end-point positions within a range between a first specific distance and a second specific distance from the first corner location; selecting a second set of longitudinal end-point positions and a second set of transverse end-point positions within a range between the first specific distance and the second specific distance from the second corner location; and determining a first transverse axis direction, a first longitudinal axis direction, a second transverse axis direction and a second longitudinal axis direction based on these positions.

The manufacturing process for fabricating printed circuit boards (PCB) includes steps of multi-layer stacking to stack conducting layers and insulating layers on each other and then pressing to integrate the layers. A common PCB manufacturing procedure is to start from a core substrate, subsequently attach metal conducting layers on both sides of the core substrates by means of stacking, perform pressing and etching on the metal conducting layers to form circuits, stack to attach insulating material on both sides of the core substrate with two circuit layers, and then repeat the aforementioned steps until the outer circuit layer is formed.
After years of technical innovation and improvement, the regular substrates and insulating materials usually take the form of sheets having a rectangular shape with longitudinal and transverse dimensions of about 20 to 30 inches while the thickness can be only a few millimeters or even less than one millimeter. The sizes of those materials are virtually the same. According to traditional stacking methods, the operators need to manually transport and place each sheet of the materials at the appropriate location based on visual inspections and personal experience, which significantly limits the production efficiency and causes variations in terms of quality. The manual operation for transportation and stacking can no longer satisfy the needs of the industry due to the large amount of market requirements and the rapidly reduced lead time.
Some PCB manufacturers tend to use a method of disposing markers at some specific locations on the materials and take advantage of visual identification by a computer to establish models of automatic transportation and stacking for production. However, these methods rely on the accuracy of the locations of the markers previously disposed on the surface of the materials, which can cause an increase in the production costs of the materials on the one hand. On the other hand, errors may occur if any inconsistency or deviation of locations among the markers exists on different batches of the materials made by the vendors. Therefore, there are technical issues to be resolved to avoid the abovementioned problems.

Method for estimating the simulated contour of a material composed of longitudinal and transverse line elements


A computer peripheral input device includes a signal receiver for wirelessly receiving an input remote signal for a computer, a signal transmitter for wirelessly transmitting an output remote signal from the computer, a signal processing circuit electrically connected to the signal receiver and the signal transmitter for providing the computer with a signal in response to the input remote signal received by the signal receiver and providing the output remote signal for the signal transmitter in response to a signal generated from the computer, and a peripheral input circuit electrically connected to the computer for providing a computer peripheral input signal for the computer.

It is believed that a signal receiver and a signal transmitter for wirelessly receiving and transmitting signals, respectively, will eventually become standard equipments of a computer in view of the current trend that the data communications between two computers are brought about by remote data signals, and that more and more computer users are on the buying spree of such a signal receiver and such a signal transmitter, which are hooked up with the computer and its peripheral equipments.
It is rather conceivable that such a practice, as described above, of adding the signal receiver and the signal transmitter for wirelessly receiving and transmitting signals, respectively, to a computer system is not only expensive but also wasteful.

Computer peripheral device with circuit for wirelessly receiving and transmitting signals


A semiconductor memory device includes a memory cell array including a plurality of memory banks, an address input portion which receives a row address and a column address through address pins during a normal mode operation and which receives the row address, the column address and write data through the address pins during a test mode operation, an address decoder which accesses one of the plurality of memory banks during the normal mode operation and at least two of the plurality of memory banks during the test mode operation in response to the row address and the column address, a data input portion which inputs write data applied through data pins to the memory cell array during the normal mode operation and which inputs write data output from the address input portion to the memory cell array during the test mode operation, and a data output portion which outputs read data output from the memory cell array to the data pins during the normal mode operation and the test mode operation.

1. Field of the Invention
The present disclosure relates to a semiconductor memory device and, more particularly, to a method of reading and writing data from/to the semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices are routinely tested for defects that may have occurred during the manufacturing process. During a typical memory test, a test engineer applies a command including an address and a data type to the memory device. Upon application of this command, an output is received from the memory device. If the output is in accordance with the input provided to the memory device, the memory device is considered to have passed the test.
With recent advances in semiconductor fabrication technology, semiconductor memory devices are becoming increasingly integrated in size, i.e., their size is being continually reduced. As part of this reduction in size, the line width of the semiconductor chip is being continually reduced. The line width of a chip is the distance between the edge of the wafer and the active are (i.e., memory cells) on the wafer. With a decrease in the line width of the semiconductor chip, the probability of manufacturing defects occurring on the chip increases. The increase in the probability of defects occurring in the chip has lead to increasing tests being performed to ensure the quality of the chip. As a consequence, testing times, and hence manufacturing costs, of semiconductor chips have increased.
Generally, I/O pins are used to write data to a memory device and also read data from the memory device. Because the same set of pins are used for reading and writing data from/to the memory device, a typical semiconductor memory device can not simultaneously perform the data read operation and the data write operation.
While a semiconductor memory device may have data input pads and data output pads, these data pads are configured to be commonly used for data input/output. Therefore, no simultaneous transmission and reception of data from the semiconductor memory device may occur via the data input pads and data output pads.
Because of the lack of simultaneous transmission and reception of data from memory devices, the test times for testing memory devices are generally high. This is because a tester has to first input all the test data and then, after inputting all the test data, receive data output from the memory device to determine whether the memory device has passed the test.
Various test modes have been developed in order to reduce the test time. For example, a conventional test method uses a parallel bit test (PBT) to simultaneously test a plurality of semiconductor memory devices. The PBT method does not receive and output data through all data I/O pads of the semiconductor memory device but does receive and output data through a predetermined number of representative data I/O pads, whereby a large number of semiconductor memory devices can be tested simultaneously.
However, even though a number of devices may be tested simultaneously, each test is still performed by first inputting test data and then, after all test data is input, receiving an output to determine whether the device under test as passed the test. That is, there is no method for simultaneously performing the data write operation and the data read operation.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device. The semiconductor memory device of FIG. 1 comprises a memory cell array 30, an address input buffer 10, a command decoder 12, a mode setting circuit 14, a clock buffer 16, a row address decoder 20, a column address decoder 22, a data write circuit 24, and a data read circuit 28. The memory cell array 30 comprises four memory banks BA_A, BA_B, BA_C, and BA_D. The functions of the components of FIG. 1 are described below.
The clock buffer 16 receives and buffers an external clock signal CLK to generate a buffered clock signal PCLK. The address input buffer 10 receives and buffers an external address ADD to generate an internal row address ra[14:0] in response to an active signal ACT and the buffered clock signal PCLK during an active operation. Furthermore, the address input buffer 10 also receives and buffers the external address ADD to generate an internal column address ca[14:0] in response to a write or read signal WE or RE respectively, and the buffered clock signal PCLK during the write or read operation.
The command decoder 12 receives a command signal CMD and decodes it in response to the buffered clock signal PCLK to generate the active signal ACT, the write signal WE and the read signal RE. The mode setting circuit 14 receives the command signal CMD and the external address ADD and decodes them in response to the buffered clock signal PCLK to generate a test mode setting signal TMRS.
The row address decoder 20 receives the internal row address ra[14:0] and the active signal ACT and decodes them under control of the test mode setting signal TMRS to activate one of a plurality of word selecting signals WL_A, WL_B, WL_C, and WL_D per each of the four memory banks BA_A, BA_B, BA_C, and BA_D. Similarly, the column address decoder 22 receives the buffered internal column address ca[14:0] and the active signal ACT and decodes them under control of the test mode setting signal TMRS to activate one of a plurality of column selecting signals CSL_A, CSL_B, CSL_C, and CSL_D per each of the four memory banks BA_A, BA_B, BA_C, and BA_D.
The data read circuit 28 receives parallel read data outputted from the memory cell array 30 to generate a predetermined number of serial output data Do under control of the test mode setting signal TMRS. Similarly, the data write circuit 24 receives write data Di which are serially input into the data write circuit 24 and converts them into parallel data under control of the test mode setting signal TMRS to generate input data to be input into the four memory banks BA_A, BA_B, BA_C, and BA_D.
The memory cell array 30 comprises the four memory banks BA_A, BA_B, BA_C, and BA_D, and receives write data from the data write circuit 24 in response to the data write signal WE and inputs the write data to each memory bank. In addition, the memory cell array 30 receives read data from each memory bank in response to the data read signal RE and outputs them to the data read circuit 28.
A row address RA and a column address CA are applied to the semiconductor memory device through address pins, and input and output data Di and Do applied to the memory cell array 30 are read from or written to the semiconductor memory device through common data request (DQ) pins or pads.
FIG. 2 is a timing diagram illustrating the data write and read operations of the conventional semiconductor memory device of FIG. 1. The external clock signal CLK, the command signal CMD, the input address signal ADD, the data I/O signal DQ, the test mode setting signal TMRS, the buffered clock signal PCLK, a plurality of memory bank word line selecting signals WL_A, WL_B, WL_C, and WL_D, and a plurality of memory bank column line selecting signals CSL_A, CSL_B, CSL_C, and CSL_D are shown in FIG. 2.
The external clock signal CLK is toggled with a predetermined phase and cycle. Furthermore, the buffered clock signal PCLK is toggled with the same cycle as the external clock signal CLK by buffering the external clock signal CLK.
The command signal CMD loads the active signal ACT, the data write commands WE of each memory bank, and the data read commands RE of each memory bank in order. In addition, the input address signal ADD loads the row address RA through the address pin according to the active command ACT, the column address CA for writing data according to the data write command WE, and the column address CA for reading data according to the data read command RE. Furthermore, in the data I/O signal DQ, write data Di_A-1 to Di_A-M of each of a plurality of memory banks are applied through data pins according to the data write signal WE and read data Do_A-1 to Do_A-M of each of a plurality of memory banks are outputted according to the data read signal RE.
FIG. 3 is an operation timing diagram illustrating data write and read operation time of a plurality of memory banks in the conventional semiconductor memory device of FIG. 1. In particular, the external clock signal CLK, the command signal CMD, and the data I/O signal DQ are shown in FIG. 3.
The buffered clock signal PCLK is toggled with a predetermined cycle, and data write commands WE_A, WE_B, WE_C, and WE_D and data read commands RE_A, RE_B, RE_C, and RE_D of the first to fourth memory banks are alternately loaded as the command signal CMD. In the data I/O signal DQ, a plurality of input data Di_A, Di_B, Di_C, and Di_D and a plurality of output data Do_A, Do_B, Do_C, and Do_D of the first to fourth memory banks are alternately loaded according to the data write commands WE_A, WE_B, WE_C, and WE_D and the data read commands RE_A, RE_B, RE_C, and RE_D of the first to fourth memory banks.
If a time spent to write/read data to/from one memory bank is defined as "T", a time 8T is spent to perform both the data write and read operations in the first to fourth memory banks BA_A, BA_B, BA_C, and BA_D. In particular, the data write and read operations of the conventional semiconductor memory device during a testing operation are described below with reference to FIGS. 1 to 3.
The operation is described below based on the assumption that a plurality of word line selecting signals are n-bit signals, a plurality of column selecting signals are m-bit signals, and test write data Di and test read data Do are M serial data which are converted to (from) N-bit parallel data. First, an operation for sequentially writing data to the first to fourth memory banks BA_A, BA_B, BA_C, and BA_D in the memory cell array 30 from an external device to the semiconductor memory device is described below.
When the row address RA[14:0] of 15 bits is applied together with the active command ACT from the external portion, the command decoder 12 internally generates the active command ACT, and the address input buffer 10 buffers the row address RA to generate the buffered internal row address ra[14:0] of 15 bits in response to the buffered clock signal PCLK. At this time, the row address decoder 20 decodes 13 bits ra[12:0] of the internal row address ra[14:0] to generate word line selecting signals WL1 to WLn, so that one of the word line selecting signals WL1 to WLn is activated. At this time, the row address decoder 20 decodes 2 most significant bits ra[14:13] as the bank address to select the memory bank in the memory cell array 30. The 2 most significant bits may be "00", "01", "10" and "11" which represent the first to fourth memory banks BA_A, BA_B, BA_C, and BA_D.
Thereafter, when the column address CA[14:0] of 15 bits are applied together with the write command from the external portion, the command decoder 12 generates the write command WE, and the address input buffer 10 buffers the column address CA to generate the buffered column address ca[14:0] of 15 bits in response to the buffered clock signal PCLK. The column address decoder 22 decodes 13 bits ca[12:0] of the buffered internal column address ca[14:0] to generate a plurality of column selecting signals CSL1 to CSLm, so that one of the column selecting signals CSL1 to CSLm is activated. Like the row address decoder 20, the column address decoder 22 decodes 2 most significant bits ca[14:13] as the bank address to select the memory bank in the memory cell array 30.
The data write circuit 24 receives M write data Di_A-1 to Di_A-M which are serially inputted, converts them into N-bit parallel data under control of the test mode setting signal TMRS and writes them to memory cells of the selected memory bank of the memory cell array 30.
An operation for sequentially reading data from the first to fourth memory banks in the memory cell array 30 to the external portion is described below.
When the row address RA of 15 bits is applied from the external portion, the same operation as the active command ACT is applied in the above described data write operation is performed, so that one of the word line selecting signals WL1 to WLn and 2 most significant bits ca[14:13] are decoded as the bank address to select the memory bank of the memory cell array 30.
When the column address CA of 15 bits are applied together with the read command RE from the external portion, the command decoder 12 generates the read command RE, and the address input buffer 10 buffers the column address CA to generate the buffered internal column address ca[14:0] of 15 bits in response to the buffered clock signal PCLK.
The column address decoder 22 decodes 13 bits ca[12:0] of the buffered internal column address ca[14:0] to generate the column selecting signals CSL1 to CSLm, so that one of the column selecting signals CSL1 to CSLm is activated. Like the row address decoder 20, the column address decoder 22 decodes 2 most significant bits ca[14:13] as the bank address to select the memory bank in the memory cell array 30.
The data read circuit 28 receives M-bit parallel data outputted from the selected memory bank in the memory cell array 30, converts them into M serial data Di_A-1 to Di_A-M under control of the test mode setting signal TMRS and outputs them.
As described above, the conventional semiconductor memory device cannot perform the data write and read operations simultaneously because data applied through the data I/O pins from an external device are sequentially inputted to each of a plurality of memory banks and data is output sequentially to an external device through the same data I/O pins.
In a semiconductor chip testing scenario, the time taken to first input test data and then to receive outputted test results only after all the test data is input may increase the overall testing time. This problem may be exacerbated as the integration density of semiconductor memory devices increases. This is because as the integration density of semiconductor memory devices increases, the probability of manufacturing defects occurring on the devices also increases thus leading to increased testing times and hence, increased manufacturing costs.
Therefore, there is a need for a method for the simultaneous input of test data and output of the test results so as to reduce the test time for the semiconductor memory device. This reduction in the test time of the semiconductor memory device may lead to lower manufacturing costs, high system operation efficiency and a high speed system operation.

Semiconductor memory device and data write and read method thereof


The present invention relates to an apparatus and a method for sensing an event occurring from a target device in a smart plug installed on a supply route of power applied to the target device. To this end, a power measurement unit which comprises the smart plug measures power supplied to the target device, and an event determination unit predicts an event occurring from the target device on the basis of a power signal characteristic of the supplied power measured by the power measurement unit. The power signal characteristic indicates a variation characteristic of the supplied power caused by the occurrence of the event on the basis of supplied power before the event occurs from the target device.

A home network system supports interworking between home electronic products based on a variety of short-range wireless communication technologies.
Due to the development of smart devices capable of exchanging information with other devices using the communication function, the home network system has evolved into a smart home network system capable of collecting information about component devices. It is possible for the smart home network system to provide a new value, owing to the interworking between smart devices.
However, since the smart devices widely used at home include just the television or so, it is not free to expand the usage scenario of the smart home network system. As a result, there is a need for the ideas that can be used in a 'home automation system' utilizing the legacy products, which is in an earlier stage of the smart home network system.
The home automation system supports a monitoring function and a control function, as its basic functions. The home automation system may be built by using legacy devices. At least one sensor may be attached or installed to/on the legacy devices used to build the home automation system. The legacy device may monitor an individual operation of an adjacent legacy device, using the at least one attached or installed sensor. The legacy device may transfer information generated by detection of the adjacent legacy device to an information collection device provided on the outside. As a result, the legacy device may interwork with the device provided on the outside. The information collection device may provide the information collected from a plurality of legacy devices to the user or the third parties.
For example, an additional sensor may be installed on the refrigerator door and open/close of the refrigerator door may be monitored through the installed additional sensor, to provide the information collected by the monitoring to the user.
As described above, in order to monitor various events (detailed operations) occurring in each legacy device constituting the home automation system, it is necessary to attach or install individual sensors suitable to monitor the features of the events.

Apparatus and method for sensing event in smart plug device


An embodiment of the present invention provides a method for manufacturing a composite preform from tape material, including feeding a tape section into a tape section guide that suspends the tape across a tooling surface, moving at least one of the tape section guide and the tooling surface relative to each other to position the tape section at a desired location and orientation relative to the tooling surface, moving the tape section toward a pre-existing tape section disposed on the tooling surface, and tacking the tape section to the pre-existing tape section. A corresponding apparatus for manufacturing composite preforms is also disclosed.

1. Field of the Invention
The present invention relates generally to advanced composites and, more particularly, to a system and method for rapidly fabricating advanced-composite laminates with low scrap using automated equipment.
2. Background of the Invention
Advanced composite materials are increasingly used in high-performance structural products that require low weight and high strength and/or stiffness. Composite materials are engineered materials that comprise two or more components. This patent relates to polymer composites that combine reinforcing fibers such as carbon fiber, glass fiber, or other reinforcing fibers with a thermosetting or thermoplastic polymer resin such as epoxy, nylon, polyester, polypropylene, or other resins. The fibers typically provide the stiffness and strength in the direction of the fiber length, and the resin provides shape and toughness and transfers load between and among the fibers. Structural performance of an advanced composite part increases with increased fiber-to-resin ratio (also called fiber volume fraction), increased fiber length, degree of fiber orientation to line up with a part's loads (in contrast to random fiber orientation), and the straightness of the fibers. Weight of an advanced-composite part can also be improved by selectively adding or subtracting material according to where it is highly and lightly stressed.
Typically, the manufacture of high-performance, advanced-composite parts is a slow and labor-intensive process. Thus, several approaches for automating the fabrication of advanced composite parts have been developed to reduce touch labor, decrease cycle time, and improve part quality and repeatability. Such machines are used to fabricate small and large parts ranging from entire plane fuselages to pressure vessels, pipes, blades for wind turbines, and wing skins. These machines typically place tape material directly on a mandrel or a mold using a material placement head mounted on a multi-axis numerically controlled machine. As the material is laid up, it is consolidated with any underlying layers. This is called "in situ" consolidation.
A different approach, described in U.S. Pat. Nos. 6,607,626 and 6,939,423, which are herein incorporated by reference, is to lay up a flat "tailored blank" where all the plies of the composite laminate are only tacked together. Once the tailored blank has been made, subsequent processing steps are used to consolidate the plies together and form the blank into its final shape.
One characteristic typical to tape and fiber placement machines is the overall technique used to apply material to a tooling surface: machines progressively unroll a tape or tow material onto a tooling surface and tack it in place using one or more compaction rollers or shoes as the material is fed onto the surface. While this technique yields high quality parts, one main limitation is that increasing material placement speed requires larger, higher power machines, which have a compounding effect on system size, energy consumption, cost, and precision. In many systems, speed is also constrained by heat transfer, especially for thermoplastic composites that are typically melted and then refrozen during placement.

System and method for the rapid, automated creation of advanced composite tailored blanks


The clock signal generator can be used to generate a first and/or a second output clock signal from an input clock signal. The rising and/or falling edges of the input clock signal are shifted using delay stages. The clock signal generator has a delay stage with a plurality of delay elements that are wired up in parallel and that have different delay lengths, and a selection device that is used to determine which of the output signals from the delay elements is to be output as the output signal of the delay stage.

FIELD OF THE INVENTION
The invention lies in the electronics field. Specifically, the present invention relates to a clock signal generator in which the duty ratio of the clock signals produced is programmable.
A clocked logic circuit has been disclosed, for example, in U.S. Pat. No. 4,719,365 to Misono (European EP 0 183 875 A). That device, however, is not suitable for producing clock signals of the type to which the invention pertains.
Clock signal generators of the known type are used, amongst other things, for controlling master/slave registers and the like, for example. Master/slave registers contain two storage elements connected in series, namely a so-called master store and a so-called slave store, which are controlled using two mutually different clock signals. More precisely, the first clock signal determines the instant at which any data present are transferred to the master store, and the second clock signal determines the instant at which data stored in the master store are transferred to the slave store.
Data may generally be transferred from the master store to the slave store only when the clock signal controlling the master store has assumed a state which prevents data from being written to the master store. If this were not the case, the data stored in the master store would still be able to change while being transferred to the slave store, which should normally be avoided if possible.
Consequently, the first clock signal and the second clock signal must never simultaneously be in a state which allows data to be transferred to the respective store. This can be achieved, for example, by generating the second clock signal by inversion of the first clock signal, so that the clock signals have essentially complementary waveforms. Clock signals generated in this manner are, in principle, suitable for controlling master/slave systems and the like.
However, on account of signal delay times, component tolerances, and the like, the above-mentioned overlaps in the signal waveforms, which are to be avoided, may nevertheless occur with the clock signals. This is undesirable and a serious problem, particularly at high clock frequencies and with stores responding at a correspondingly fast rate.
In order to avoid this, it is possible to process the mutually inverse clock signals in such a manner that a so-called overlap-free phase is imposed between the respective active phase of one clock signal and the subsequent active phase of the other clock signal. Both clock signals are in an inactive phase, for example a low-level phase, during the overlap-free phase.
Such an overlap-free phase can be provided (while maintaining the respective clock frequencies) by appropriately shifting the rising and/or falling edges of the first and/or of the second clock signal. This can be achieved using appropriate delay stages. See, for example, U.S. Pat. No. 5,453,707 to Hikichi (European EP 0 606 912 A).
Even though the use of such clock signals matched to the supposed conditions generally permits master/slave registers and the like to be driven considerably more reliably, there are nevertheless repeatedly cases, in practice, in which master/slave registers or the like cannot be operated correctly, despite the provision of the measures. This necessitates research into the cause and requires the relevant circuit or its affected circuit parts to be redesigned, which processes are frequently very extensive and correspondingly costly.
The same also applies to the case where the duty ratio of the clock signals used is responsible for the master/slave registers or the like operating incorrectly. In that case, too, matching to the supposed conditions does not automatically lead to the correct operation of the master/slave registers.


Shelf suspension member for shelf arrangements that install easily and quickly on sash windows without tools or fasteners by engaging into existing window structures and by being supported by or suspended from such structures in cantilevered manner, which is convenient in use, low in cost and attractive in appearance, which does not appreciably obstruct daylight, and which permits opening of at least a part of the window without removal of the arrangement.

The present invention relates to shelf suspension members for shelf arrangements, in particular for easy and quick installation and mounting on, respectively removal from double-hung sash windows and associated window frame structures without a need for tools, special skills, and without need for invasive measures for fastening, as for instance given by conventionally required screw or anchor holes in wall, window, or window frame.
Shelf space, particularly near and inside of certain windows, is generally desired and needed in many households and other buildings. For instance, potted plants and miscellaneous utilitarian and decorative articles are often placed on or near the sill or kitchen windows (as well as other windows)--usually in places where there is little space anyway. Flowers, herbal plants, vases, ornaments, knick-knacks, books, etc. are kept in such locations, often because of high visibility, hardiness, and high daylight levels, as well as for reasons of convenience and accessibility. Shelf arrangements for locations directly in front of and on the inside of windows have not been available commercially. Although appropriate adaptations of known or commercially available shelf arrangements might perhaps be visualized by a person skilled in the art, the complexity and comparatively high cost of the relatively time-consuming adaptations and the need for permanent fastening to wall, window frame, or window by means of screws, anchors, clamps, etc., as well as the most likely resulting clumsy and unappealing appearance have precluded adoption of such shelf arrangements. Additionally, such arrangements do not permit easy access to the window, do not allow quick and easy installation and removal of the shelf arrangement, and may not permit convenient opening of at least part of the window without removal of the shelf arrangement.
Accordingly, it is an object of the present invention to provide an improved shelf suspension member for shelf arrangements which mount on (and may be removed from) a sash window structure.
Advantages of the suspension members of the invention are that they are mounted easily and quickly without any need for tools and fasteners, which require no special skill in installation or removal, which are convenient, low in cost and attractive in appearance, which do not significantly obstruct daylight entering through the window, which permit opening of at least part of the window without removal of the shelf arrangement or the articles carried by it, and which exhibit further advantages which will become apparent from the detailed description of the present invention.

Shelf suspension member for double-hung sash windows


A computer system includes a system bus having a plurality of address lines and having a first control line. A connector is coupled to the address lines and the first control line, and can removably receive a circuit card which can accept and/or generate signals on the address lines and first control line. A bus control circuit is coupled to the address lines and to a second control line, and can accept and/or generate signals on the address lines and second control line. A signal blocking circuit is coupled to both of the control lines and to the address lines, responds to the occurrence of a control signal on the second control line by respectively effecting and inhibiting application of the control signal to the first control line when the address on the address lines is respectively within and outside a predetermined group of addresses, and responds to the occurrence of the control signal on the first control line by applying the control signal to the second control line regardless of the address on the address lines.

For several years, commercially available personal computers of the type commonly referred to as IBM compatible have typically used a standard system bus design commonly referred to as the Industry Standard Architecture (ISA). The ISA specification provides for twentyfour memory address lines. Now, systems are being introduced which utilize a system bus design which is an enhanced version of the ISA approach, commonly referred to as the Extended Industry Standard Architecture (EISA). The EISA standard provides for thirty-two address lines.
Existing circuit boards designed for use with the ISA standard can be used with an EISA system, but look at only the twenty-four least significant bits of the thirty-two EISA address lines, and thus ignore the eight most significant address bits. Consequently, where an ISA device, which is designed to respond to a particular combination of the twenty-four least significant bits and thus a unique address under the ISA standard, is used in an EISA system, it could potentially respond to several EISA memory addresses which have the same twenty-four least significant bits but different combinations of the eight most significant bits. An ISA device which responds to multiple EISA addresses in this manner could cause errors.
An integrated circuit is commercially available and can be used to control an EISA system bus. This integrated circuit produces certain control signals which are intended exclusively for use by ISA devices and which could thus be suppressed if an EISA address was outside the range of normal ISA addresses, but the design of the integrated circuit happens to be such that it does not do this and thus presents the potential for errors of the type discussed above. Of course, it would be possible to use, instead of this integrated circuit, a custom circuit made of discrete components and performing the same function, but this approach would involve significant additional cost, space and power consumption.
It is therefore an object of the present invention to provide a way of facilitating use of ISA devices in association with this EISA integrated circuit in a manner ensuring system operation free of errors.
The objects and purposes of the invention are met, for a system which includes first and second control lines and a plurality of address lines, by providing a method and apparatus which involve supplying an address to the address lines and a control signal to one of the control lines, monitoring the address lines and control lines, responding to detection of the control signal on the second control line by respectively effecting and inhibiting application of the control signal to the first control line when the address on the address lines is respectively within and outside a predetermined group of addresses, and responding to the occurrence of the control signal on the first control line by applying the control signal to the second control line regardless of the address on the address lines.

Method and apparatus to disable ISA devices for EISA addresses outside the ISA range