A method for performing computer-assisted lesion assessment includes acquiring contrast enhanced MRI data. A region of interest is identified. Kinetic properties, morphological properties and pattern of enhancement are determined for the identified region of interest. A score is calculated for each of the kinetic properties, morphological properties, pattern of enhancement. A cumulative score is calculated for the identified region of interest. The scores are provided to a medical practitioner to assist in diagnosing the identified region of interest.

1. Technical Field
The present disclosure relates to lesion assessment and, more specifically, to computer aided lesion assessment in dynamic contrast enhanced breast MRI images.
2. Discussion of Related Art
Breast cancer is the second leading cause of all cancer deaths for women in the United States. Early detection and treatment may significantly increase a patient's chances for survival and recovery. Accordingly, effective breast cancer screening is of particular importance. Various techniques are available for imaging a patient's breast to accurately diagnose breast cancer. For example, x-ray mammography, thermal imaging, magnetic resonance imaging (MRI), etc. Many conventional approaches to breast imaging involve x-ray mammography.
Mammography may be used to identify two types of abnormalities in breast tissue: soft tissue lesions (tumors) and clusters of microcalcifications which may be an early sign of possible cancer. Tumors are generally characterized as palpable lesions while microcalcifications are generally characterized as non-palpable. While mammography remains the most popular clinical modality of breast cancer screening, it may lack sufficient specificity to adequately distinguish between certain types of cancerous lesions and certain types of benign abnormalities. Moreover, mammography may be incapable of effectively imaging dense breast tissue.
MRI may also be used to image a patient's breast. For example, dynamic contrast enhanced breast MRI may be used. In dynamic contrast enhanced MRI, four-dimensional volumetric data, including three spatial dimensions and a temporal dimension, a magnetic contrast agent, for example, a gadolinium based contrast agent (Gd-DTPA), may be delivered and the patient's breast may be imaged continuously over a period of time thereafter. Such a technique may provide a medical practitioner, for example, a radiologist, with the opportunity to monitor the kinetic characteristics of the contrast agent as it interacts with the area of the suspicious region. Such information may be particularly useful in differentiating between cancerous lesions and benign abnormalities, especially when analyzed along with other imaging data such as morphological characteristics and patterns of enhancement formations.
Assessment of such properties as morphological characteristics and patterns of enhancement formations, however, remains something of an art and is difficult to measure quantitatively. Accordingly, such diagnostic techniques may lack a sufficient level of consistency and accuracy.

Computer aided lesion assessment in dynamic contrast enhanced breast MRI images


The present invention relates to a system and a method for improving the use of energy in an electric motor by inducing currents generated from magnets and/or electromagnets that result in an increase of primary power and creating, directing and introducing a counter current obtained from primary coils of the motor into a resonant LC circuit which is introduced as a transient secondary process to increase the overall efficiency of the motor. Furthermore, the motor produces rotational torque without using alternating magnetic polarity, but rather magnetic compression that utilizes permanent magnets arranged in a dipolar manner around an axial plane and, in another embodiment, uses ferrous cores arranged in a dipolar manner around an axial plane or alternatively, electromagnetic dipoles arranged in a dipolar manner around an axial plane.

Numerous attempts have been made to increase the efficiency of electric motors. Many of these attempts are set forth in patents and patent applications such as:    U.S. Pat. No. 6,392,370, Bedini, Device and Method of a back EMF permanent electromagnetic motor;    U.S. Pat. No. 7,230,358, Smith, D C Resonance Motor;    US Patent Application 2009/0045690, Kerlin, D C Homopolar Motor/Generator.

This patent is subject to a terminal disclaimer.


A method of controlling the opening or the closing of an AC electric circuit in an electricity meter by means of a relay is provided. The method times relay activation commands so as to take account of the inertial delay (di) of the relay, in such a manner that the actual activation command applied to the relay causes the relay actually to take action on the electric circuit when an electrical parameter of said circuit reaches a zero value, in order to limit the formation of electric arcs in the relay.

Electricity meters are devices that enable the instantaneous consumption of current and the voltage on an electricity line to be measured with metrological precision, so as to enable the exact electricity consumption of electrical equipment to be billed, e.g. in a house. In known manner, such meters include one or more electromechanical type relays that make it possible to open or close the electric circuit passing through the meter, so as to establish or disconnect the supply of electricity to the house in question. It may be necessary to open the circuit as a result of detecting a voltage surge upstream from the meter. It may also be necessary to do so in the event of the user not paying for electricity consumption, with the instruction to activate the relay then coming from outside the meter. The relay is generally controlled by electronic means of the microprocessor type housed in the meter itself. In the same manner, closure of the circuit may be controlled from the outside or by components within the meter itself.
Electromechanical relays are components that are subject to wear, and they present a lifetime that depends on the electrical conditions in which they are activated, while the relay is being opened or closed. It can happen that they are severely stressed in the event of electric arcs being struck in uncontrolled manner while opening or closing a circuit.
Document EP 0 108 538 describes an alternating current (AC) electric circuit that may be closed or opened by means of a relay, said relay being connected to an electronic control unit in order to activate opening or closing of the electric circuit when an electrical parameter of the circuit reaches a zero value. The timing of the closing or opening of the electric circuit takes the inertial delay of the relay into account. Nevertheless, the inertial delay is merely predetermined.

Method for controlling the opening or closing of an electric circuit in an electric meter


A process for replacing the printing sleeves of a printing machine includes mounting printing sleeves that are not required for the printing process in at least one storage device. The transportation of the printing sleeves necessary for replacement between the storage device and the printing machine is performed by a transportation device. The transportation device has printing sleeve retaining devices that bring the printing sleeves into a position that facilitates their replacement. The arrangement of the printing sleeves in the transportation device is determined by a processing and control unit to which set positions of the printing sleeves during the next printing job are known. The processing and control unit adjusts the arrangement of the printing sleeves such that at least one printing sleeve retaining device remains free in the transportation device.

1. Field of Invention
The invention relates to a process for replacing printing sleeves in a printing machine in which printing sleeves that are not required for the printing process are mounted in at least one storage device. The transportation of the printing sleeves necessary for replacement between the storage device and the printing machine is performed by at least one transportation device that has printing sleeve retaining devices which bring the printing sleeves into a position that facilitates their replacement.
2. Description of the Prior Art
The invention relates to a process for replacing printing sleeves in a printing machine according to the generic term of claim 1.
For the processing of printing jobs it is frequently necessary to replace the printing motifs of the print rollers of a printing machine. For the purpose of being able to execute this job changeover as quickly and easily as possible, frequently only the printing sleeves carrying the printing motifs and lying on the roller mandrels are replaced.
The unpublished patent application DE 102 23 414 suggests a transportation device for printing sleeves with several carrying mandrels for accommodating the printing sleeves. Every two adjoining carrying mandrels have a distance between them that corresponds to the distance of the print roller and the anilox roller in their set-up positions. Both these carrying mandrels form one row inside the transportation device. The transportation device can be coupled to a lifting device by means of which it can move horizontally and vertically with respect to the printing machine.
If a printing sleeve is supposed to be replaced, the operating personnel must first equip the transportation device with the printing sleeves to be inserted into the printing machine. The operating personnel also has to position the transport device with the help of the lifting device in front of the printing unit in which the printing sleeves to be replaced are located, so that two free carrying mandrels are positioned in front of the print rollers. Then the printing sleeves located on the print roller mandrels can be pulled out by the operating personnel. Subsequently, the transportation device is placed in a new position in order to bring the printing sleeves into a suitable position for fitting them on the roller mandrels. Then the printing sleeves can be fitted. If necessary, the process is carried out similarly for additional printing units.
In the described process for the replacement of printing sleeves of a printing machine, the operating personnel equips the transportation device without observing any predetermined arrangement of the printing sleeves. Thus the operating personnel must independently plan the arrangement of the printing sleeves in the transportation device. This arrangement is in part disadvantageous for the set-up process. Additionally, it also entails the risk of an erroneous allocation of the printing sleeves to the roller mandrels.

Method for replacing printing sleeves in a printing press


An arrangement for producing first to third effective addresses by processing an indirect designation processing instruction indicated by its code. An address register first memorizes, as the first effective address, an indirect descriptor address. An address register memorizes this latter portion as the second effective address instead of the first one. This makes the main memory produce a direct designation data descriptor comprising a direct designation indicating and a direct designation address portion. Meanwhile, a storing circuit stores the code and the first effective address in a first part of a buffer memory. The storing circuit stores this portion and the second effective address in the first part instead of the code and the first effective address. The address register now memorizes the direct designation address portion as the third effective address instead of the second one to make the main memory produce an operand datum. Meanwhile, the storing circuit is energized by the direct designation indicating portion and stores this portion and the third effective address in a second part of the buffer memory.

This invention relates to an effective address producing and storing apparatus or arrangement supplied with an indirect designation effective address processing instruction for producing a succession of a plurality of effective addresses comprising first, second, and third effective addresses and for successively storing the first through third effective addresses in a buffer memory of a configuration which includes an information processing system comprising a main memory, a reading apparatus or arrangement, and the buffer memory.
The buffer memory is used in administering an addressing exception which occurs when the reading arrangement attempts to access an unavailable location of the main memory. The unavailable location is equivalent in meaning to a location which is not available in the configuration.
The main memory is for memorizing an operand datum at an operand address, a direct designation data descriptor at a direct descriptor address, and an indirect designation data descriptor at an indirect descriptor address. The direct designation data descriptor comprises a direct designation indicating portion and a direct designation address portion representative of the operand address. The direct designation indicating portion indicates direct designation for the operand datum. The indirect designation data descriptor comprises an indirect designation indicating portion and an indirect descriptor address portion representative of the direct descriptor address. The indirect designation indicating portion indicates indirect designation for the operand datum.
The indirect designation effective address processing instruction comprises an indirect designation indicating code and a source address section representative of the indirect descriptor address. The indirect designation indicating code indicates indirect designation for the operand datum.
A conventional effective address producing and storing apparatus or arrangement comprises an instruction register having first and second instruction register areas for memorizing the indirect designation indicating code and the source address section. Connected to the second instruction register area, a source address processing circuit processes the source address section into a source accessing signal representative of the indirect descriptor address.
Connected to the source address processing circuit, an effective address register memorizes the source accessing signal as the first effective address and uses the source accessing signal in making the reading arrangement access to the indirect descriptor address and read the indirect designation data descriptor as a first read-out data descriptor. The effective address register is connected to the buffer memory. Connected to the buffer memory, a storing circuit stores the first effective address in a first part of the buffer memory.
A descriptor register is connected to the indirect descriptor address of the main memory. The descriptor register has first and second descriptor register areas for memorizing, as a first designation indicating portion and a first designation address portion, the indirect designation indicating and the indirect descriptor address portions, respectively, which are had by the indirect designation data descriptor read as the first read-out data descriptor.
Connected to the second descriptor register area and the effective address register, an updating circuit updates the effective address register to make the effective address register memorize the first designation address portion as the second effective address instead of the first effective address. The effective address register thereby uses the first designation address portion in making the reading arrangement access to the direct descriptor address and read the direct designation data descriptor as a second read-out data descriptor. The storing circuit stores the second effective address in a second part of the buffer memory.
The descriptor register is furthermore connected to the direct descriptor address of the main memory. The descriptor register memorizes, as a second designation indicating portion and a second designation address portion instead of the first designation indicating and the first designation address portions, the direct designation indicating and the direct descriptor address portions, respectively, which are had by the direct designation data descriptor read as the second read-out data descriptor.
The updating circuit updates the effective address register to make the effective address register memorize the second designation address portion as the third effective address instead of the second effective address. The effective address register thereby uses the second designation address portion in making the reading arrangement access to the operand address and read the operand data. The storing circuit stores the third effective address in a third part of the buffer memory.
Thus, the conventional effective address producing and storing arrangement successively stores the first through the third effective addresses in the first through the third parts of the buffer memory, respectively. Thereafter, supplied with another indirect designation effective address processing instruction, the conventional effective address producing and storing arrangement produces another succession of a plurality of effective addresses and successively stores the effective addresses in different parts of the buffer memory that are different from the first through the third parts of the buffer memory.
The conventional effective address producing and storing arrangement is operable in cooperation with the information processing system in a pipeline fashion of first, second, third, and several subsequent pipeline stages. The first pipeline stage is carried out by the instruction and the descriptor registers. The second pipeline stage is dealt with by the effective address register. The third pipeline stage is carried out by the buffer memory. The subsequent stages are dealt with by the reading arrangement and the main memory.
Inasmuch as the conventional effective address producing and storing arrangement produces a succession of a plurality of effective addresses in accordance with the indirect designation effective address processing instruction and successively stores the effective addresses in different parts of the buffer memory and inasmuch as each of the effective addresses is typically thirty-one bits long, an overflow of the effective address which should be stored in the buffer memory, is liable to occur in the buffer memory when the conventional effective address producing and storing arrangement is supplied with the indirect designation effective address processing instruction which makes the conventional effective address producing and storing arrangement produce an increased number of the effective addresses. The overflow causes the pipeline of the information system to become clogged and degrades performance of the information processing system. In particular, the overflow makes it impossible to accurately deal with the addressing exception which occurs at the subsequent pipeline stages immediately after the overflow occurs. This is because the effective address in question overflows and is not perfectly stored in the buffer memory.
To avoid the overflow, another conventional effective address producing and storing apparatus or arrangement comprises another storing circuit which successively stores a plurality of the effective addresses in a same part of the buffer memory. That is, only a trailing one of the effective addresses remains in the buffer memory for each of the indirect designation effective address processing instructions. The trailing one of the effective addresses is equivalent to the direct designation address portion representative of the operand address. When an addressing exception occurs at the subsequent pipeline stages immediately after the trailing one of the effective addresses is stored in the buffer memory, operation of the information processing system is terminated for the trailing one of the effective addresses in question in a manner known in the art. It will be supposed that the trailing one of the effective addresses and a preceding effective address immediately preceding the trailing one of the effective addresses are necessary as an exception address and a preceding factor address, respectively, in processing the addressing exception in the information processing system which operates under the control of exception processing firmware with reference to the buffer memory. The exception address is equivalent in meaning to an effective address at which the addressing exception occurs and which designates the operand address. The preceding factor address is equivalent in meaning to another effective address which precedes the exception address and which designates the direct description address. In this case, the information processing system cannot deal with the addressing exception. This is because the preceding effective address does not remain in the buffer memory as the preceding factor address.

Information processing system with addressing exception


Provided is a financial device. The financial device comprise a registered medium storage box storing a medium to be registered and withdrawn, a discrimination part recognizing information of the registered medium withdrawn from the registered medium storage box, a display unit displaying a screen on which the registered medium to be withdrawn is registered, and a control part controlling the display unit. The control part acquires information of at least one registered medium stored in the registered medium storage box by using the discrimination part, and a screen for registering the registered medium to be withdrawn on which the acquired registered medium information is reflected is displayed on the display unit.

The present disclosure relate to a financial device.
In general, financial devices are devices for processing financial business desired by customers. Financial devices may deposit/withdraw a medium or automatically transfer a medium. For example, financial devices may deposit or withdraw an unregistered medium or a registered medium.
To process the registered medium in the financial devices according to the related art, a process of registering the registered medium in the financial devices is performed. For example, a bank teller registers a serial number of a registration medium, the number of medium, a kind of medium (hereinafter, referred to as registration medium information), and the like in a financial device. Then, when the registration medium information is inputted into the financial device, the inputted registration medium information is transmitted into and stored in a host server.
However, in the related art, the bank teller should manually input the registration medium information. Thus, if the registration medium information is entered incorrectly, the actual registration medium information withdrawn from the financial device and the registration medium information stored in the host server may be different. As a result, the registration medium withdrawn by a customer may be processed as an unregistered medium or incident registered medium.


A printing machine or press including at least one printing unit having at least one frame wall. The at least one frame wall defines a machine space of the machine unit. The at least one frame wall has a thickness and includes a narrow side. At least one passage is formed in the frame wall and is at least partially open. The at least one passage is formed on at least one surface of the frame wall and with its surface opening disposed on the narrow side of the frame wall and which extends along the surface of the frame wall. At least one of a power line and a data line can be disposed in the passage.

From DE 102 61 274 A1, a frame section for a base frame of an industrial system having a profiled part that is open toward one side is known, wherein the profiled part is embodied as a cable chute for laying at least one electrical cable, and has at least one reinforcing part, fastened in the profiled part, to which a holding device for raising the industrial system is attached, said reinforcing part having an opening through which the electrical cable can be guided, wherein the opening in the reinforcing part is open on at least one side of the reinforcing part such that the electrical cable can be inserted from that side into the opening in the reinforcing part.
From DE 30 47 765 A1, a pedestal structure is known, wherein a tub-like device, in this case called a pedestal, accommodates a pipe, wherein narrower pipes are placed inside a pipe that is connected to the pedestal, or other pipes are telescoped into each other and securely connected to one another, wherein lines are laid inside the pipes.
From US 2005/0055917 A1, a corner connecting piece for a frame of an air handling unit is known, wherein this corner connecting piece comprises an element, which comprises a first section, a second section and a third section, wherein the first section, the second section and the third section each have a first leg and a second leg, wherein the first leg of the first section and the second leg of the second section form a first edge, wherein the second leg of the first section and the first leg of the third section form a second edge, and wherein the first leg of the second section and the second leg of the third section form a third edge, wherein the first edge, the second edge and the third edge form a corner, wherein ends of the first opposite edge, the second edge and the third edge are assembled to form the corner of the frame.

Printing press having at least one machine unit with at least one of a power line and a data line installed in the at least one machine unit


There is provided a slackless drawbar assembly which connects the adjacent ends of a pair of railway cars together in a substantially semi-permanent fashion. The assembly includes a yoke, an adjustable blockout apparatus which has a pair of spaced end blocks and an adjustable securing device which comprises a pair of spaced wedge members. There are outwardly extending flanges on the confronting end faces of the end blocks which engage tongues or tenons on the end walls of the spaced wedge members. The adjustable securing device comprises coaxial bores through the spaced wedge members and a threaded member extending between and through the coaxial bores and threadably engaged with threads formed in at least one of the bores such that upon rotating the threaded member in one direction, the spaced wedge members will be moved together, to push the pair of end blocks apart, while upon rotating the threaded member in the other direction, the spaced wedge members will be moved apart to pull together the pair of spaced end blocks. A preferred yoke includes a rear end portion which has a front face that forms a rear seat for a blockout device. There are a top strap portion and a bottom strap portion extending forwardly of the front face of such rear end portion of the yoke. Each of such top and bottom strap portions includes a thickened portion, at its end remote from such rear end portion of the yoke, which has a bore therethrough to receive an end of a drawbar connecting pin to connect the yoke to a drawbar.

The railroad locomotives used in the railroad industry prior to the introduction of the more powerful and efficient diesel engine in such locomotives, were in most cases generally underpowered. Therefore, it was usually necessary to provide each end of a railway freight with a draft gear assembly. This was required in order for these underpowered locomotives to start a train consist, having a number of cars, in motion. As is known in the railway art, these draft gear assemblies were used to provide a requisite amount of slack in the coupling arrangement between the adjacent ends of several such freight cars making up the train consist. This slack, as is generally well known in the railway art, enabled start-up movement of the lead car and, thereafter, each of the following cars in succession. In other words, during start-up of the train consist the locomotive would begin taking up the slack between it and the lead car first. Thereafter the available slack in each following car, in turn, would be taken up. This start-up procedure enabled the generally lower powered locomotive to gain sufficient initial momentum to start the train consist in motion.
Furthermore, in the railway art, it is equally well known that at least a portion of the buff and draft forces which are generated and then applied to the railroad freight cars in such a coupling arrangement, during in-track operation of the train consist, were normally absorbed by these draft gear assemblies- It is con, non practice in this type of coupling arrangement for such draft gear assemblies to be mounted in a draft gear pocket located in a yoke disposed within the center sill member of the railway freight car. The yoke is connected to the railway car coupler mechanism by means of a striker plate casting.
These prior art type coupling arrangements did not absorb or avoid all of the dynamic loading which occurred in a train and the portion which remained resulted in detrimental dynamic loading on both the car body members and their contents. This dynamic loading almost always results in considerable wear of the various components of the coupling mechanism disposed on the freight car and depending upon the contents being transported by such freight car such dynamic loading can even result in damage to such contents. It is obvious that wear of the various coupling components will require considerable maintenance to be carried out so that the car can remain in service. It is further obvious that such maintenance is costly.
However, since the introduction of the more powerful diesel locomotive, in the modern railroad industry, it has been discovered that the slack formerly required in the older style coupling arrangements is no longer necessary to start the train consist in motion. A diesel locomotive, in other words, provides the capability of starting the movement of a train consist containing multiple freight cars without the need for considerable amounts of slack being provided by the draft gear assemblies of the prior art car coupling arrangements. As a result, slackless drawbar assemblies have generally come into widespread use in the railroad industry as the coupling arrangement for joining together the adjacent ends of a pair of railway freight cars in a substantially semi-permanent manner. It has been demonstrated that these slackless drawbar assemblies enable the buff and draft forces which are generated by in-track movement to be distributed through the car center sill member to all of the railway cars making up such train consist with less damage to both the freight car components and cargo.

Slackless drawbar assembly employing adjustable blockout apparatus


Techniques for improving security of an electronics device are disclosed. In one aspect of the present disclosure, security of a device may be improved by generating a working key based on a hardware secret key and at least one security parameter of the device, e.g., with a key derivation function. The security parameter(s) may be related to software to be authenticated on the device and/or other aspects of security for the wireless device. The security parameter(s) may indicate whether the software is authorized and/or at least one operating function authorized for the software. At least one security function may be performed for the device based on the working key. For example, the working key may be used to encrypt, sign, decrypt, or verify data for the device. The working key may be used directly or indirectly by the software for the at least one security function.

I. Field
The present disclosure relates generally to electronics, and more specifically to techniques for providing security on an electronics device.
II. Background
An electronics device (e.g., a cellular phone or a smartphone) typically operates based on software that controls the operation of hardware on the device and supports various functions of the device. A security mechanism (e.g., a secure boot) may be employed to ensure that only software that has been authorized for the device can be executed on the device. However, the device may be vulnerable to malicious attack (e.g., during manufacturing) prior to activation of the security mechanism on the device. During this vulnerable time period, unauthorized software may be maliciously loaded onto the device and executed by the device to access security information (e.g., security keys) on the device and/or to manipulate data using the security information.

Generation of working security key based on security parameters


A short-wavelength infrared imaging lens includes first and second lens groups arranged in order from an object side. The first lens group has a negative refractive power as a whole. The second lens group has a positive refractive power as a whole and includes at least one positive lens that satisfies following conditional expressions (1) and (2):V2p>40  (1)N2p>1.7  (2)

Generally, infrared rays are classified into near infrared, short-wavelength infrared, mid infrared, and far infrared rays according to the wavelengths, and the short-wavelength infrared rays usually refer to a wavelength band of 1000 to 2500 nm. Since the short-wavelength infrared rays have a wavelength close to that of visible light, they are reflected or absorbed by an object similarly to visible light, and thus are advantageous for high-resolution imaging. In addition, there are objects that cannot be effectively discriminated in the visible range but can be discriminated by using short-wavelength infrared rays, and therefore, short-wavelength infrared optical systems are used in fields such as inspection, detection, and monitoring. As a conventional technology relating to such a short-wavelength infrared optical system, there is an optical system described in JP2008-026594A, for example.
As a conventionally known optical system, there is a retro-focus lens including a first lens group having a negative refractive power and a second lens group having a positive refractive power (for example, JP5891912B2). The retro-focus lens can ensure a sufficient distance from the image plane to the exit pupil.
Further, as a conventionally known optical system, there is an optical system having two lens groups located in front of and behind an aperture stop, respectively (for example, JP2018-040858A).
The short-wavelength infrared optical system described in JP2008-026594A favorably corrects chromatic aberration in a wavelength range of 1500 to 2000 nm but has an f-number of about 4 and hence is not bright. There are short-wavelength infrared imaging lenses for wavelength ranges of 900 nm to 1700 nm and 1700 nm to 2400 nm.
However, there is no high-resolution imaging lens with a small f-number and well corrected chromatic aberration over a wide band of 900 to 2400 nm.
The optical system described in JP5891912B2 is a bright optical system having an f-number of about 1.8, but the target wavelength range of this optical system is a visible range.
The optical system described in JP2018-040858A is a bright optical system having an f-number of about 1.4, but the target wavelength range of this optical system is a visible range and the optical system has a large number of lenses including an aspheric lens.
As a commonly used low-dispersion optical glass, there is one having an Abbe number Vd for d-line of 70 or more but its refractive index Nd for d-line is 1.55 or less. Such a glass has a low dispersion in the short-wavelength infrared range but cannot sufficiently correct spherical aberration due to the small refractive index. In the optical systems described in Patent Documents 2 and 3, the optical glass has a refractive index Nd of 1.7 or more and an Abbe number Vd of 50 or more, which is relatively large. In such a glass, an Abbe number V in a short-wavelength infrared range is of about 26, which is so small for a positive lens (a lens having a positive refractive power) and so large for a negative lens (a lens having a negative refractive power) that sufficient chromatic aberration correction cannot be made.

Short-wavelength infrared imaging lens and imaging device including two lens groups of −+ refractive powers having seven lenses of −++−−++ refractive powers or eight lenses of −+++−−++ refractive powers

Abstract: Here, N2p is a refractive index N [1.53] of the positive lens at a wavelength of 1.53 μm, and the Abbe number V2p is an Abbe number of the positive lens in a short-wavelength infrared range and is defined as (N [1.53]−1)/(N [0.9]−N [2.325]) when refractive indexes of the at least one positive lens at wavelengths of 0.9 μm, 1.53 μm, and 2.325 μm are represented by N [0.9], N [1.53], and N [2.325], respectively.


A positioning device for clipping apparatus includes a hollow body which has an open side on one side that holds a track portion and an anchor portion on another side. The body houses a sliding member having a clipping unit and a harness arm. The harness arm is connected to the track portion to form a displacement path of the sliding member. The clipping unit includes an upper clipping portion and a lower clipping portion. The upper clipping portion is driven by the sliding member to move close to the lower clipping portion. A linking means connects an elastic element to the anchor portion and the sliding member so that the elastic element can be stretched and retracted against the displacement path of the sliding member to provide a returning elastic force to the sliding member. Thereby the sliding member can be positioned rapidly on each displacement path.

A clipping apparatus basically aims to couple two elements together or release one of the two elements through a simple operation. It generally is adopted on doors or the like. For instance, the door of the operation panel of household appliances usually uses such an apparatus. The conventional clipping apparatus have many types and are operated in different ways. The commonly adopted operation is depressing. A first depressing aims to clip, and a second depressing aims to release. A desirable clipping apparatus has to be simple to use, clip firmly and not getting loose easily. The movement of the sliding member on every displacement path has to be accurate and crisp. To release the clipping article rapidly also is important. The design of the internal structure of the clipping apparatus directly affects those characteristics.
R.O.C. patent publication No. M285631 entitled "Sideward clipping apparatus" discloses a clipping apparatus which has a seat containing a housing trough. The housing trough holds an elastic element and a guiding member. The housing trough also contains a sliding member directed by the elastic element and the guiding member at a first position in normal conditions and at a second position when depressed. The sliding member has a movable linking element and a clipping pawl which has an upper clipping end and a lower clipping end. The lower clipping end at the initial force receiving stage drives the upper clipping end through the movable linking element to form a first fan-shape moving track. The lower clipping end is in contact with the sliding member under the force and moves vertically downwards to the second position to drive the upper clipping end to form a second fan-shape moving track. The upper and lower clipping ends form a clipping zone when the sliding member is moved to the second position to clip an article.
When the sliding member is moved from the second position to the first position, the article is released. Due to the upper and lower clipping ends are linked by a flexible linking blade, when the article is released the flexible linking blade does not have enough return force. As a result, the upper and lower clipping ends cannot open rapidly to release the article. While it can securely clip the article, it cannot release the article quickly and crisply. It causes problems when in use. Moreover, the guiding member and elastic element are located on the same side of the housing trough. When the lower clipping end is depressed under force the distal end of the guiding member easily skews due to the action force. As a result, the sliding member cannot be moved to the intended position and the clipping apparatus cannot function as desired. This also causes a lot of troubles.

Positioning device for clipping apparatus


Methods are disclosed for system scenario-based design for an embedded platform whereon a dynamic application is implemented. The application meets at least one guaranteed constraint. Temporal correlations are assumed in the behavior of internal data variables used in the application, with the internal data variables representing parameters used for executing a portion of the application. An example method includes determining a distribution over time of an N-dimensional cost function, with N an integer number N≧1, corresponding to the implementation on the platform for a set of combinations of the internal data variables. The method also includes partitioning an N-dimensional cost space in at least two bounded regions, each bounded region containing cost combinations corresponding to combinations of values of the internal data variables of the set that have similar cost and frequency of occurrence, whereby one bounded region is provided for rarely occurring cost combinations.

Real-time embedded systems have become much more complex due to the introduction of a lot of new functionality in one application, and due to running multiple applications concurrently. This increases the dynamic nature of today's applications and systems and tightens the requirements for their constraints in terms of deadlines and energy consumption. State-of-the-art design methodologies try to cope with these issues by identifying several most used cases and dealing with them separately, reducing the newly introduced complexity.
Embedded systems usually comprise processors that execute domain-specific applications. These systems are software intensive, having much of their functionality implemented in software, which is running on one or multiple processors, leaving only the high performance functions implemented in hardware. Typical examples include TV sets, cellular phones, wireless access points, MP3 players and printers. Most of these systems are running multimedia and/or telecom applications and support multiple standards. Thus, these applications are full of dynamism, i.e., their execution costs (e.g., number of processor cycles, memory usage, energy) are environment dependent (e.g., input data, processor temperature).
Scenario-based design in general has been used for some time in both hardware and software design of embedded systems. In both of these cases, scenarios concretely describe, in an early phase of the development process, the use of a future system. These scenarios are called use-case scenarios. They focus on the application functional and timing behaviours and on the interaction with the users and environment, and not on the resources required by a system to meet its constraints. These scenarios are used as an input for design approaches centred round the application context.
The present disclosure, however, focuses on a different and complementary type of scenarios, called system scenarios. System scenario-based design methodologies have recently been successfully applied to reduce the costs of dynamic embedded systems. They provide a systematic way of constructing workload-adaptive embedded systems and have already been proposed for multimedia and wireless domains. At design-time, the system is separately optimized for a set of system scenarios with different costs, e.g., alternative mapping and scheduling of tasks on multiprocessor systems. At run-time, certain parameters are monitored, changes to the current scenario situation are detected, and mapping and scheduling are changed accordingly. Up to today, only so-called control variable-based system scenario approaches based on bottom-up clustering have been studied in-depth in the literature.
State-of-the-art advanced multiprocessor system-on-chip platforms and applications typically require a dynamic scheduling of instructions and threads to be able to meet stringent performance and low energy requirements. The Task Concurrency Management (TCM) methodology is a systematic approach for mapping an application onto a multiprocessor platform in real-time embedded systems. The methodology is based on a two-step scheduling technique that, at design-time, performs computation-intensive parts of the mapping and scheduling, leaving for run-time the parts that result in less overhead for computing the actual schedule.
An application is divided into thread frames, each consisting of a number of thread nodes, as will be further detailed below. At design-time, each thread node is profiled to find its execution time and power consumption for all possible input data and on all possible processors on the platform. With profiling is meant the simulation of hardware based emulation of the system behaviour to obtain the system responses for a representative set of input stimuli. The resulting numbers are used to find all thread frame schedules with an optimal trade-off between execution time and energy consumption. A schedule candidate is optimal if it, e.g., has the lowest energy consumption for a given execution time. As a result, each thread frame has a set of optimal schedules along a curve in a two-dimensional execution time-energy consumption solution space. In cases where different sets of input data give too wide a spread in a thread node's execution times, system scenarios can be used to find a thread frame Pareto-curve for each of the individual scenarios. Each system scenario corresponds then to a different (non-overlapping) cluster of run-time situations that are similar enough in their Pareto-curve positions (close enough in the N-dimensional trade-off space, see also further). At run-time, input data is monitored to keep track of the currently active scenario. It should be stressed though that system-scenario based approaches for identifying clusters of similar run-time situations are usable in many more contexts than only thread-frame scheduling of dynamic embedded systems. This disclosure focuses on the broadly applicable system scenario concept itself.
The scenarios are derived from the combination of the application behaviour and the application mapping on the system platform. These scenarios are used to reduce the system cost by exploiting information about what can happen at run-time to make better design decisions at design-time, and to exploit the time-varying behaviour at run-time. While use-case scenarios classify the application's behaviour based on the different ways the system can be used in its over-all context, system scenarios classify the behaviour based on the multi-dimensional cost trade-off during the implementation trajectory. By optimizing the system per scenario and by ensuring that the actual system scenario is predictable at run-time, a system setting can be derived per scenario to optimally exploit the system scenario knowledge.
FIG. 1 depicts a design trajectory using use-case and system scenarios. It starts from a product idea, for which the product's functionality is manually defined as use-case scenarios 1, 2, and 3. These scenarios characterize the system from a user perspective and are used as an input to the design of an embedded system that includes both software and hardware components. In order to optimize the design of the system, the detection and usage of system scenarios augments this trajectory (the cost perspective box of FIG. 1). The run-time behaviour of the system is classified into several system scenarios (A and B in FIG. 1), with similar cost trade-offs within a scenario. For each individual scenario, more specific and aggressive design decisions can be made. The sets of use-case scenarios and system scenarios are not necessarily disjoint, and it is possible that one or more use-case scenarios correspond to one system scenario. But still, they are usually not overlapping, and it is likely that a use-case scenario is split into several system scenarios, or even that several system scenarios intersect several use-case scenarios.
The system scenario-based design methodology is a powerful tool that can also be used for fine grain optimizations at the task abstraction level and for simultaneous optimization of multiple system costs. The ability of handling multiple and non-linear system costs differentiates system-based design methodologies from the dynamic run-time managers intended for Dynamic Voltage and Frequency Scaling (DVFS) type platforms. DVFS methodologies concentrate on optimization of a single cost (the energy consumption of the system), that scales monotonically with frequency and voltage. They perform direct selection of the system reconfiguration from the current workload situation. This, however, cannot be generalized for costs that depend on the parameters in a non-uniform way. That makes the decision in one run-time step too complex. Scenario-based design methodologies solve this problem by a two-stage approach decided at run-time: they first identify what scenario the working situation belongs to, and then choose the best system reconfiguration for that scenario. Since the relationship between the parameters and the costs will, in practice, be very complex, the scenario identification is, however, performed at design-time.
When using system scenarios, both information about the system at design time and the occurrence of certain types of input at run-time, which results in particular (groupings of) run-time situations, are considered. The term "run-time situation" (RTS) is an important concept used in task level system scenario-based design methodologies. An RTS is a piece of system execution with an associated cost that is treated as a unit. The cost usually consists of one or several primary costs, like quality and resource usage (e.g., number of processor cycles, memory size). The system execution on a given system platform is a sequence of RTSs. One complete run of the application on the target platform represents the sequence of RTSs. The current RTS is known only at the moment it occurs. However, at run-time, using various system parameters—so-called RTS parameters—it can be predicted in advance in which RTS the system will run next for a non-zero future time window. If the information about all possible RTSs in which a system may run is known at design-time, and the RTSs are considered in different steps of the embedded system design, a better optimized (e.g., faster or more energy efficient) system can be built because specific and aggressive design decisions can be made for each RTS. These intermediate per-RTS optimizations lead to a smaller, cheaper and more energy efficient system that can deliver the required quality. In general, any combination of N cost dimensions may be targeted. However, the number of cost dimensions and all possible values of the considered RTS parameters may lead to an exponential number of RTSs. This will degenerate to a long and really complicated design process, which does not deliver the optimal system. Moreover, the run-time overhead of detecting all these different RTSs will be too high compared to the expected gain over their (quite) short time windows. To avoid this situation, the RTSs are classified and clustered from an N-dimensional cost perspective into system scenarios, such that the cost trade-off combinations within a scenario are always fairly similar (i.e their Euclidean distance in the N-dimensional cost space is relatively small), the RTS parameter values allow an accurate prediction, and a system setting can be defined that allows to exploit the scenario knowledge and optimizations.
In the paper 'System scenario based design of dynamic embedded systems' (V. Gheorghita et al., ACM Trans. On Design Automation for Embedded Systems, Vol. 14, No. 1, January 2009), a general methodology is proposed which can be instantiated in all contexts wherein a system scenario concept is applicable. Important steps of the method comprise choosing a good scenario set, deciding which scenario to switch to (or not to switch), using the scenario to change the system knobs, and updating the scenario set based on new information gathered at run-time. This leads to a five step methodology, including design time and run-time phases. The first step, identification, is somewhat special in this respect, in the sense that its run-time phase is merged into the run-time phase of the final step, calibration. The initial identification at run-time is incorporated in the detection step, but a re-identification can happen at run-time in a calibration step.
The various steps are now introduced. Special attention is hereby paid to the steps that are most relevant for the present disclosure.
Design-Time Identification of the Scenario Set
In order to gain the advantages offered by a scenario approach, it is necessary to identify the different scenarios that group all possible RTSs. A scenario identification technique therefore lies at the heart of any system scenario-based design methodology. It determines how the different observed RTSs should be divided into groups with similar costs, i.e. The system scenarios, and how these system scenarios should be represented to make their run-time prediction as simple as possible. In prior art system scenario based solutions, parameters that decide the scenario boundaries have been limited to control variables, or variables with a limited number of distinct values.
In the identification step the relevant RTS parameters are selected and the RTSs are clustered into scenarios. This clustering is based on the cost trade-offs of the RTSs, or an estimate thereof. The identification step should take as much as possible into account the overhead costs introduced in the system by the following steps of the methodology. As this is not easy to achieve, an alternative solution is to refine the scenario identification (i.e., to further cluster RTSs) during these steps.
A task-level scenario identification split can be performed in two steps. In the first step, the variables in the application code are analyzed, either statically, or through profiling of the application with a representative data set. The variables having most impact on the run-time cost of the system are determined. These variables are called RTS parameters, denoted by ξ1, ξ2, . . . , ξk, and are used to characterize system scenarios and design the scenario prediction mechanism. Typically a small set of RTS parameters is selected to keep the run-time prediction overhead low.
The output of the first step is the set of the selected RTS parameters and, for each RTS i, its RTS signature is given by Equation 1 below:r(i)=ξ1(i),ξ2(i), . . . ,ξk(i);c(i),  (1)containing parameter values ξ1(i), ξ2(i), . . . , ξk(i) and the corresponding task costs c(i), i.e., each run instance of each task has its own RTS signature. The number N of RTS signatures will hence be very large. Depending on the number of RTS parameters and how many different values each of them can take, there is a small or large number of different RTS signatures. This is important for the complexity of the second step of the scenario identification. In this second step, the RTS signatures are divided into groups with similar costs—the system scenarios. This can be done by a bottom-up clustering of RTS signatures with a resulting multi-valued decision diagram (MDD) that is used as a predictor for the upcoming system scenario (see step of scenario prediction).
As mentioned, the impact of RTS parameters can be evaluated either statically or through profiling. When based on purely static analysis of the code, the frequencies of occurrence of different RTS parameter values are not taken into consideration. Therefore, system scenarios may be produced that almost never occur. This technique can be extended with profiling information, and then forms a system scenario set that exploits run-time statistics. This approach typically leads to only a limited amount of parameters being labelled as important enough to incorporate in the identification step, which is crucial to limit the complexity.
The existing scenario identification approaches cannot be used in a system with many-valued RTS parameters, causing an explosion of states in the MDD and the associated run-time/implementation costs. In that case the bottom-up clustering approach has a fundamental complexity limitation which cannot be overcome by any incremental change only.
Prediction of the Scenario
At run-time, a scenario has to be selected from the scenario set based on the actual parameter values. This selection process is referred to as scenario prediction. In the general case, the parameter values may not be known before the RTS starts, so they may have to be estimated. Prediction is not a trivial task; both the number of parameters and the number of scenarios may be considerable, so a simple lookup in a list of scenarios may not be feasible. The prediction incurs a certain run-time overhead, which depends on the chosen scenario set. Therefore, the scenario set may be refined based on the prediction overhead. In this step two decisions are made at design-time, namely selection of the run-time detection algorithm and scenario set refinement.
Exploitation of the Scenario Set
At design-time, the exploitation step is essentially based on some optimization that is applied when no scenario approach is applied. A scenario approach can simply be put on top of this optimization by applying the optimization to each scenario of the scenario set separately. Using the additional scenario information enables better optimization.
Switching from One Scenario to Another
Switching is the act of changing the system from one set of knob positions (see below) to another. This implies some overhead (e.g., time and energy), which may be large (e.g., when migrating a task from one processor to another). Therefore, even when a certain scenario (different from the current one) is predicted, it is not always a good idea to switch to it, because the overhead may be larger than the gain. The switching step selects at design-time an algorithm that is used at run-time to decide whether to switch or not. It also introduces into the application the way how to implement the switch, and refines the scenario set by taking into account switching overhead.
Calibration
The previous steps of the methodology make different choices (e.g., scenario set, prediction algorithm) at design-time that depend very much on the values that the RTS parameters typically have at run-time; it makes no sense to support a certain scenario if in practice it (almost) never occurs. To determine the typical values for the parameters, profiling augmented with static analysis can be used. However, the ability to predict the actual run-time environment, including the input data, is obviously limited. Therefore, also support is foreseen for infrequent calibration at run-time, which complements all the methodology steps previously described.
Hence, there is a need for an improved method for system scenario based design.

Method for system scenario based design of dynamic embedded systems

Katholieke Universiteit Leuven, KU Leuven R&D


A method of automatically and accurately accomplishing focusing and astigmatism correction in an electron beam apparatus such as a scanning electron microscope. The electron beam is raster scanned to scan a specimen in two dimensions. If the obtained signal intensity distribution curve has only one peak, the peak position P2 of a curve obtained by raster scanning the beam vertically is detected. The peak position P1 of a curve obtained by raster scanning the beam horizontally is detected. An intermediate position P0 is calculated, using the formula EQU P0=(P1+P2)/2. The intensity of excitation of the objective lens is adjusted to this intermediate position P0. In this way, if two peaks cannot be obtained by a horizontal raster scan of the beam, depending on the state of the surface of the specimen, it is possible to accurately bring the beam into focus at the position of the circle of least confusion. After this focusing operation, an automatic astigmatism correction is made.

Where an electron beam apparatus such as a scanning electron microscope automatically effects both focusing and astigmatism correction, an automatic focusing operation is first performed. In this focusing operation, the focus is brought into the position of the circle of least confusion. Then, an astigmatism correction is made. To bring the focus into the position of the circle of least confusion, an electrical current supplied to the objective lens or to a lens auxiliary to the objective lens is varied in a stepwise fashion. The position of the focus is shifted for each different value of the lens current so that the electron beam scans the surface of a specimen in two dimensions. During the two-dimensional scan, secondary electrons or reflected electrons emanating from the specimen are detected by a detector. The output signal from the detector is integrated for one frame of image. The signal distribution curve shown in FIG. 1 is obtained from the integrated values derived from every value of lens current. The integrated values are plotted on the vertical axis of FIG. 1. The intensity of excitation of the objective lens is plotted on the horizontal axis. It is known that the position of the peak of this distribution curve is the position of the circle of least confusion. The objective lens current is so controlled that the intensity of excitation of the lens corresponds to the position of the peak. Then, an automatic astigmatism correction is made. Subsequently, a second automatic focusing operation is performed. FIG. 2 is a flowchart illustrating these focusing operations and astigmatism correction operations.
Where the electron beam involves astigmatism, the above-described signal distribution curve has two peaks as shown in FIG. 3. In this case, it is known that the position of least confusion lies midway between the two peaks P1 and P2. If the difference in height between the two peaks is great, then there is the possibility that the control system erroneously regards the maximum peak position P1 as the position of least confusion. At this time, if the focus is brought to an overlying position that is not the position of least confusion, and if an astigmatism correction is made at that position, then the correction is not carried out accurately.

Automatic focusing and astigmatism correction for electron beam apparatus


Systems and methods for characterizing networks are disclosed. In several embodiments, a network analyzer applies a network analysis to a network that replaces components of the network in a model of the network with equivalent or bounding models. The network analyzer can then characterize the simplified model of the network and an assessment can be made concerning the accuracy of the characterization of the network.

A communication network includes a collection of communicating devices (e.g., telephones, moderns, computers, PDAs, video game consoles, routers, sensors) that can transmit and receive signals through a variety of communication media (e.g., wires, cables, air, water, space) for the purpose of delivering data (e.g., text, images, audio, video, sensor measurements) across space or time. There are a wide variety of communication networks in use today. These include, but are not limited to, traditional (wireline) telephone networks, wireless phone networks (e.g., cellular phone networks, satellite phone networks), local area networks (LANs), wide area networks (WANs), the Internet, cable television networks, RFID networks, and sensor networks.
There are many metrics used in characterizing the performance of a network. One common measure is the maximal data rate at which the network can deliver information. (Maximal data rates are sometimes described using terms such as the "network bandwidth," "data band-width," "information rate," or "network capacity." The term "bandwidth" in the context of data networks is typically used to quantify the amount of data delivered per unit of time. The term "capacity" is used to refer to the maximum possible data rate or collection of data rates that a link, path, or network can deliver per unit time.) In other cases, it may be useful to describe the minimal distortions with which a network can deliver a collection of sources to their intended destinations, the latency or delay suffered in information delivery, the robustness of the network to component failures or adversarial attack, the extent to which information can be protected against eavesdropping, and so on. The metric of interest in analyzing a given network is often highly dependent on the application. For example, transmissions of live voice and video are far more sensitive to delay than is email, even when both data types travel through the same network.
Analyzing a network's performance is useful for a variety of applications. These include but are not limited to the following examples. Network users who wish to compare a variety of available networks can use network analysis to determine which network will give the best performance for their needs. Network designers interested in building new networks or reconfiguring old ones can use network analysis to optimize design choices with respect to relevant network metrics. Network analysis is also of potential use for guiding research and development. For example, by analyzing both metrics that provide theoretical bounds on a network's best possible performance and metrics that measure current performance using existing algorithms, researchers and entrepreneurs can distinguish between problems for which current solutions already achieve good performance and those where large gaps between theory and practice suggest a greater potential for advance. Network service providers can use network analysis to discover underlying structure in their networks, understand how much enabling a new service impacts existing services, inform pricing, guide network design, and improve network upgrades. Techniques for estimating network performance are also important for overlay network routing, traffic engineering, and capacity planning support.
Theoretical analysis of network performance is often extremely difficult. For example, the capacity of a single memoryless, noisy point-to-point channel is well-characterized, but the capacities for many memoryless three-node networks (e.g., non-degraded broadcast and relay channels), most networks that can be built from memoryless, noisy point-to-point channels, and most channels with memory remain unsolved. A key challenge is that the capacities of a network's components do not necessarily determine the capacities of networks that can be built from those components. For example, consider a 4-node network in which node 1 transmits to nodes 2 and 3 through a broadcast channel and nodes 2 and 3 transmit to node 4 through a multiple access channel. Assume that the noise in the broadcast channel is independent of that in the multiple access channel. The capacity region for the complete network cannot be solved by combining the capacity regions of the two component channels. For example, the maximal rate at which node 1 can send information to node 4 is different when the broadcast channel is physically degraded than when the broadcast channel is stochastically degraded even though the capacity of the physically and stochastically degraded broadcast channels are identical.
One special family of networks for which the network capacity is relatively well-understood is the family of networks built from noiseless capacitated links (bit pipes). In these networks (bit-pipe networks) under some very structured connection types, network capacities are precisely characterized. For example, for multicast connections, where all messages start at a single node in the network and each receiver wishes to reconstruct all messages transmitted by that source node, the capacity is fully characterized for all network topologies. Unfortunately, finding capacities for general connection types remains a difficult problem. For example, the capacity of a network with single multicast connection is solved, but the capacities of most networks with two or more multicast connections remain unsolved.
For the family of noiseless wireline networks under general connection types, information theoretic inequalities can be used to find outer bounds on network capacities. The linear outer bound described in R. W. Yeung, "A framework for linear information inequalities," IEEE Transactions on Information Theory, 43(6): 1924-1934, November 1997 (the disclosure of which is incorporated by reference herein in its entirety) gives the tightest outer bound implied by Shannon-type inequalities. This bounding technique has been implemented as the software programs Information Theoretic Inequalities Prover (ITIP) and XITIP. The program has complexity exponential in the number of links in the network and can thus only be used to compute capacity bounds for relatively small problem instances.
Since signals transmitted through real communication networks are corrupted by physical phenomena such as noise and attenuation, the tools for computing capacities of bit-pipe networks cannot be directly applied to compute capacities of real networks. As a result, the tools used to approximate the capacities of real networks are quite different from the tools described above. The tools used to study large networks are typically empirical, measuring achieved rate, available bandwidth, and bulk transfer capacity (BTC) across a single link or path. A network manager with administrative access to network routers and/or switches can measure bandwidth metrics by gathering data rate statistics at all accessible nodes (e.g., routers and switches). Since such access is typically available only to administrators and not to end users, end users can often only estimate the bandwidth of individual links or paths from end-to-end measurements. As a result, many such mechanisms yield only partial and unreliable assessments of a network's capacity.

Systems and methods of network analysis and characterization


Provided is a power supply wiring structure which comprises a first and a second power supply wirings, which are disposed on different planes to cross each other two-dimensionally. The first and second power supply wirings are interlayer-connected by a first via at a crossing area where those power supply wirings cross each other. An extension wiring which is formed by partially extending from the crossing area along a wiring extending direction of other power supply wiring is provided at least to either the first power supply wiring or the second power supply wiring. The extension wiring and either the first power supply wiring or the second power supply wiring, which are disposed on a different plane from the extension wiring to face the extension wiring, are interlayer-connected by a second via. Thereby, generation of electro migration can be suppressed.

1. Field of the Invention
The present invention relates to a power supply wiring structure and a designing method of a power supply wiring.
2. Description of the Related Art
A semiconductor integrated circuit comprises a greater number of minute wirings such as clock wirings, signal wirings, power supply wirings, etc. compared to an ordinary conductive wiring. When an electric current is flown into such minute wirings, migration of electrons occurs. The migrated electrons urge atoms (for example, copper atoms, aluminum atoms, etc), which forms the wiring, thus causing an atomic depletion (void). Such void induces a decrease of a cross sectional area of a wiring film, an increase of the electric current density, and a temperature increase caused by Joule heat. More accelerated growth of the void finally comes to break down the wirings. Such phenomenon is referred to as electro migration (referred to as EM hereinafter).
In the recent semiconductor integrated circuit technology, gate length of transistors constituting a semiconductor integrated circuit is shortened to improve the degree of integration. When the degree of the integration is improved in this manner, it is possible to reduce the area of the semiconductor integrated circuit. However, the number of operating transistors per unit area is increased thus increasing the consumed electric current per unit area. As a result, the electric current density in the power supply wiring is increased and a problem of EM in the power supply wiring becomes significant.
In the meantime, the wiring of the semiconductor integrated circuit is formed by electrically connecting multilayer wirings through vias. With the same amount of electric current, the EM problem is more significant in the vias than in the wirings. This is due to a meteoric failure phenomenon. The meteoric failure phenomenon will be described in the followings.
In the recent manufacturing procedure of a semiconductor integrated circuit, a great number of vias are concentrated so that there is a swollen part by the vias in an area with a great number of the concentrated vias compared to an area where the vias are not concentrated. The density of via numbers per unit wiring is referred to as a via density. Due to such swollen part by the vias, the wiring becomes let out and connected to other wirings at the time of forming a wiring which is a layer over the via. Such phenomenon is referred to as the meteoric failure phenomenon.
The wiring width of the power supply wiring is wider than that of the signal wiring, so that it is possible to form a grater number of vias compared to the case of the signal wiring. Thus, in order to avoid the meteoric failure phenomenon, the power supply wiring is designed with the decreased via density. However, with this, the cross sectional area of the via is decreased due to a decrease in the via density. Thus, the EM problem is more increased.
For the EM problem as described above, in the semiconductor integrated circuit, a standard of the allowable electric current density is set and the wirings and vias therein are so constituted that the electric current density falls within the allowable electric current density.
However, the recent semiconductor integrated circuit uses a multilayer structure. Further, the semiconductor integrated circuit is formed by disposing various cells or blocks as will be described below. Specifically, the semiconductor integrated circuit is constituted by disposing various cells or blocks, e.g. logic cells such as an AND circuit and OR circuit with relatively small power consumption, sequence cells such as an FF circuit and a latch circuit, a memory cell such as SRAM with relatively a large power consumption, etc.
Because of the structural reasons, there is a locally-declined power consumption of the circuit generated in the semiconductor integrated circuit, resulting in complication of the electric current paths from the power source to the transistor. Thus, it becomes difficult to calculate the allowable electric current density of the wiring and the via. In addition, it is difficult to specify the section within the semiconductor integrated circuit where the EM becomes an issue.
Furthermore, when looking into the blocks of the semiconductor integrated circuit, there raise the following shortcomings. That is, even if the EM problem is eliminated in each block, there may have an EM problem when the power supply wiring within the block is a bypass circuit of the power supply wiring for the other high-power-consumption block though there is no EM problem generated in that block, due to the corresponding relation between the bypass circuit and the semiconductor integrated circuit as a whole.
Because of the reason described above, when designing the blocks within the semiconductor integrated circuit, it is necessary to design the circuit for excessively supplying power so as not to have the EM problem. Furthermore, when designing each block of the semiconductor integrated circuit, used is a designing method in which a power supply wiring area necessary for the block is determined based on the consumed electric current of each block, and the EM problem is not generated if the area of the power supply wiring occupying the block is a prescribed value or more. When the block design is carried out by such block designing method, there is an excessive power supply area provided in the designed block. As a result, the power supply area of the semiconductor integrated circuit is increased thus hindering the size-reduction of the semiconductor integrated circuit.
Japanese Patent Unexamined Publication (JP-A 5-226331) discloses the related art which is directed to coping with the EM problem of the vias in the power supply wiring as described above. In the followings, the power supply wiring structure of the related art will be described.
FIG. 13A and FIG. 13B illustrate an example of an electric power supply wiring structure of the related art. In FIG. 13A, reference numeral 12010 is a first power supply wiring before modification. 12020 is an original width of the first power supply wiring 12010. 12030 is a width of the power supply wiring 12010 after the modification. 12040 is a wiring extending direction of the first power supply wiring 12010. 12050 is a second power supply wiring. 12060 is a width of the second power supply wiring 12050. 12070 is a wiring extending direction of the second power supply wiring 12050. 12080 is a first power supply wiring area. 12090 is a via. 12100 is a notable power supply wiring part. The first power supply wiring 12010 illustrated in the drawings by a broken line is connected to the second power supply wiring 12050 through the via 12090. The via 12090 is disposed in an area where the first power supply wiring 12010 and the second power supply wiring 12050 cross each other. The width 12030 of the first power supply wiring 12010 after the modification is formed wider than the width 12060 of the second power supply wiring 12050.
The effect achieved by the structure of the semiconductor integrated circuit as described above will be described in the followings. In the semiconductor integrated circuit formed in multiple layers, in the manufacturing procedure thereof, a great number of different masks are stacked many times to be disposed at the same position for forming the wirings and the vias. Thus, when stacking the masks at the same position, shift in the masks cause problems, e.g. a short circuit of the wiring between the upper layer wiring and the lower layer wiring, floating of the via, etc.
In the related art for overcoming such problems, the first power supply wiring is formed with the modified width 12030 of the first power supply wiring 12010, which is wider than the width 12020 of the first power supply wiring 12010 before the modification. With this, it is possible to prevent a decrease in the yield of the semiconductor integrated circuit even if there is a shift in the position of the via in the manufacturing procedure of the semiconductor integrated circuit.
Next, FIG. 13B is a cross sectional view of the notable power supply wiring part 12100 shown in FIG. 13A. Reference numeral 12110 is a first power supply wiring 12110. 12120 is a height of the first power supply wiring 12110. 12130 is a second power supply wiring. 12140 is a height of the second power supply wiring 12130. 12150 is a via. 12160 is a width of the first power supply wiring 12110 before modification. 12170 is a width of the first power supply wiring 12110 after modification. 12180 is a flow direction of the electric current. 12190 is a width of the second power supply wiring 12130.
For the wirings of the semiconductor integrated circuit, the heights of the wirings are formed to be uniform since it is easier for manufacture. Thus, the height 12120 of the first power supply wiring 12110 and the height 12140 of the second power supply wiring are set to be an arbitrary height without any specific reasons. Further, since the heights of the wirings are uniform, in a regular state, if the width of the power supply wiring is determined, the resistance of the power supply wiring and the electric current density of the power supply wiring are determined uniquely.
The direction 12180 of the electric current flows from the second power supply wiring 12130 towards the first power supply wiring 12110 through the via 12150. In the related art, the width 12160 of the first power supply wiring 12110 before the modification is widened to the proposed width 12170 of the first power supply wiring 12110. By widening the wiring width in this manner, the resistance of the first power supply wiring 12110 is reduced so that still larger amount of the electric current is to be flown.
However, there is no increase in the number of the via 12150. Thus, even if the resistance of the first power supply wiring 12110 is reduced, there is no change in the electric current flown to the first power supply wiring 12110 from the second power supply wiring 12140. As described above, in the conventional structure, there is no measure taken for the via 12150 which is a bottleneck in overcoming the EM problem.
As is clear from those described above, the conventional structure shown in FIG. 13A and FIG. 13B is aimed at increasing the productivity (increase the yield) of the semiconductor integrated circuit, while an increase in the number of vias for the wiring is only taken as a means for avoiding a shift of the vias in the manufacturing procedure.
Next, by referring to FIG. 14A-FIG. 14C, described is a conventional method in which the number of vias for the wiring is increased. In FIG. 14A, reference numeral 13010 is a relation between the regularity of the wiring and a general yield. 13020 is a relation between the regularity of the wiring and the yield when particularly paying attention to the yield related to the via density at the crossing area between the wirings. 13030 is a relation between the overall yield and the regularity of the wiring.
When forming the wires in the semiconductor integrated circuit, by enhancing the regularity of the wirings through taking a measure such as arranging rectangular wirings at equal intervals, etc, for example, manufacture of the semiconductor integrated circuit becomes easy thus improving the productivity (yield) of the semiconductor integrated circuit. Thus, when looking at the yield, an increase in the regularity of the wiring improves the yield as can be seen in the relation 13010 between the regularity of the wiring and the yield.
However, for the overall yield of the semiconductor integrated circuit, in addition to the yield related to the regularity of the wiring, there is also the yield 13020 related to the via density at the crossing area between the wirings. By increasing the via density in the crossing area between the wirings, while the regularity of the wiring becomes deteriorated, the EM problem can be improved. For that, the yield is improved.
Therefore, when looking at the overall yield of the semiconductor integrated circuit, the overall yield 13030 is determined as a result of the multiplier of both an increase/decrease property 13010 of the ordinary yield related to the regularity of the wiring and an increase/decrease property 13020 paying attention to the via density at the crossing area of the wirings.
Further, the number of vias in the wiring will be described by referring to FIG. 14B and FIG. 14C. As shown in FIG. 13 and the like, an increase in the number of the vias enables to prevent a shift of the masks. However, if the number of the vias in all the wirings is increased in the semiconductor integrated circuit, there cause increases in the capacity of the signal wirings and in the area of the wirings. Thus, it is necessary to go with the following relational expressions for the number of vias.
Referring to FIG. 14B, in an area where an increase in the area and the wiring capacity is not a problem, the relation can be expressed by a following relational expression:Number of vias=number which causes no problem in manufacturing procedure+α  (1)
Next, referring to FIG. 14C, in an area where an increase in the area and the wiring capacity is a problem, the relation can be expressed by a following relational expression:Number of vias<number which causes no problem in manufacturing procedure+α  (2)
Based on these, since there are larger areas of the above-mentioned expressions (1) in the related art, it enables to reduce the possibilities of causing shift of the vias in the semiconductor integrated circuit.
Furthermore, as semiconductor integrated circuit designing methods, there are many designing methods in which a desired semiconductor integrated circuit is formed by stacking wirings in a rectangular shape as the wiring shape since it is easier to manufacture.
In the semiconductor integrated circuit, EM in the wiring and the via is an issue. Particularly, EM is a problem in the power supply wiring, since power is supplied to each transistor of the semiconductor integrated circuit therethrough and also a larger amount of electric current is flown compared to that of the signal wiring. Furthermore, in the recent designing method of the semiconductor integrated circuit, the via density is decreased to cope with the meteoric failure phenomenon. In addition, due to the substrate structure, when the cross sectional area of the wiring and that of the via being orthogonal to the direction of the electric current are compared, the cross sectional area of the via being orthogonal to the direction of the electric current is smaller than that of the wiring. Therefore, the EM problem is significant in the via. Further, in the multilayer structure which is used in the recent semiconductor integrated circuit, the electric current paths to the transistors become complicated so that it becomes difficult to cope with the EM by calculating the electric current density of the vias in each wiring layer and stage, which is locally concentrated.
In the power supply wiring structure shown in FIG. 13A and FIG. 13B, the wiring width of the power supply wiring where the EM is significant is widened so that the area of the power supply wiring is increased. Further, since designs of the power supply wiring and the signal wiring are modified for expanding the power supply wiring after detecting the section where the EM becomes an issue, there requires a great number of complicated steps for modifying the semiconductor integrated circuit. Moreover, in the semiconductor integrated circuit shown in FIG. 13B, the width 1219 of the second power supply wiring is simply widened to the still wider width 1217 of the power supply wiring, and there is no measure taken for the via where the EM problem becomes most significant.
Further, the number of vias in the power supply wiring structure of the related art corresponds to the shift of the vias caused in the manufacturing procedure of the semiconductor integrated circuit, which is designated in accordance with the expressions (1), (2) when determining the number of the vias in the wirings. Thus, it is not possible to cope with the EM problem of the vias when it occurs, thereby deteriorating the productivity (yield) of the semiconductor integrated circuit.

Matsushita Electric Industrial Co., Ltd.


A system and method are disclosed for detecting anomalies in input data. The input data can include enrollment information for members of a health insurance product offered by an insurance carrier. A system is configured to process one or more parameters associated with the input data to detect whether an anomaly is indicated in the input data. At least one artificial intelligence algorithm is configured to compare a parameter in the one or more parameters to a range defined by a moving average. When an anomaly is detected, the processing can be paused and manual intervention can be facilitated. When no anomaly is detected, a database is updated based on the input data. In an embodiment, the input data is an ANSI 834 format file that includes a plurality of membership records, and the one or more parameters are derived from statistics related to the membership records.

The Health Insurance Portability and Accountability Act (HIPAA) established a requirement that all health plans or health insurance carriers accept a standard enrollment format for transmitting enrollment data electronically between a plan sponsor (e.g., employer) and a payer (e.g., insurance carrier). That enrollment format, ANSI (American National Standards Institute) 834 EDI (Electronic Data Interchange) Enrollment Implementation Format (hereinafter referred to as ANSI 834), specifies certain fields included in a file in order to transfer information related to members and benefits of an insurance product (e.g., health insurance) offered by the insurance carrier.
A plan sponsor, such as an employer or a state entity, generally transmits to the payer periodically (or provides access to retrieve) a file formatted according to the ANSI 834 format (e.g., once per day, once per month, etc.). The file contains membership records for individuals enrolled in the plan sponsor's health insurance plan. The payer then processes this file to update their records and facilitate the handling of claims filed by the various individuals that are enrolled. Processing this file manually can be time consuming and expensive. For example, a state entity may submit a file containing hundreds or thousands of records for those citizens of the state enrolled in a state-sponsored plan such as Medicare or Medicaid. In order to reduce costs and facilitate automated integration of enrollment data included in these files, some insurance carriers may utilize automated systems that attempt to parse the data from the ANSI 834 file and update one or more databases with the appropriate information parsed from the file.
However, in some cases, the ANSI 834 file may contain corrupt, inaccurate, or false information. For example, an automated system implemented by the plan sponsor may not generate an accurate file that reflects real enrollment data. For example, the fields in the file can be formatted improperly, the information in the fields can be incorrect due to improper data entry, or false records can be included in the file (e.g., records can be created for test purposes that do not reflect real membership information). If these records are received by the automated systems, the systems may perform as intended and create false records in the local database. The insurance carrier cannot rely on the records in the database in this case and, sometimes, correcting these issues can cause large disruptions to services provided by the insurance carrier (e.g., claim payments can be delayed, new claims might not be accepted, etc.). Thus, there is a need to address these and other issues with automated systems used for enrollment purposes.

Artificial intelligence automation for enrollment