An emergency ballast for a fluorescent lamp including a heater disposed adjacent the battery for maintaining the battery at a safe and effective operating temperature during the time which the lamp is powered by the normal AC power supply. Additionally, the ballast includes a charging control circuit which precludes charging of the battery when normal AC power is supplied to the ballast charging circuit during the time when the battery is below a temperature for safe and effective charging.

Not Applicable
1. Field of the Invention
The invention relates to emergency lighting, and particularly to fluorescent lighting wherein a fluorescent lamp is connected to a source of electrical energy other than normal AC line current in the event that the normal AC current fails.
Emergency lighting is required in commercial, industrial, and institutional buildings just as fire extinguishers, smoke alarms and other safety equipment. Three types of emergency lighting are common in such installations: unit equipment, engine generators and central battery systems. Unit equipment falls into two principle types: fluorescent and incandescent.
The fluorescent emergency units are customarily combined or within a conventional fluorescent lighting unit by merely adding the emergency ballast consisting of a battery, a battery charger, inverter and sensing circuitry adjacent the standard fluorescent AC ballast. The sensing circuit of the emergency ballast observes the interruption of normal AC power to the lamp unit and immediately switches on the emergency ballast to power individual lamp(s) or the light fixture for the required period. Under most state safety codes, this is a period of at least ninety (90) minutes, a standard called out in the National Electrical Code, NFPA Article 70, and NFPA Article 101 Light Safety Code.
2. General Background of the Invention
U.S. Pat. No. 5,004,953 entitled Emergency Lighting Ballast for Compact Fluorescent Lamps with Integral Starters, assigned to the assignee of the present invention is illustrative of the general fluorescent type of emergency lighting with a ballast. It is common in the installation of emergency fluorescent lighting that an emergency ballast is added to a conventional fluorescent fixture or provided integrally in a fixture having internal regular and emergency ballast installed. When main AC power fails, voltage sensing circuitry instantly connects DC current from a battery (in the emergency ballast) to an inverter which produces high frequency, high voltage power to illuminate the fluorescent lamp(s) in emergency mode for the required period.
The present invention is directed to fluorescent lighting fixtures which are likely to be exposed to extreme low temperatures wherein the battery which supplies the power for lighting when main AC power fails is apt to freeze. Until now, emergency lighting has been utilized in such as commercial an governmental buildings wherein it is unlikely that power will be out for such a long period of time that the batteries for providing the back-up power will freeze. The state of the art units typically are recommended for temperature ranges of about 0xc2x0 C. to about 50xc2x0 C. Unit contained emergency fluorescent lighting is now so reliable and common that it is being considered for such as smaller out buildings, garages, outside staircases and warehouses where the building (or fluorescent unit) is unheated, or if subjected to prolonged power outage during winter, the internal environment may cool to 0xc2x0 C. or lower. After a prolonged time at below freezing temperatures, the battery internal to the emergency ballast is likely to freeze. A problem arises when normal AC power is restored and the battery charging circuit of the unit attempts to recharge the battery. With the inclusion of the present invention, emergency fluorescent lighting may be extended to an operating range of about xe2x88x9220xc2x0 C. to about 50xc2x0 C.
It is known that rechargeable batteries such as the nickel-cadmium type typically used in fluorescent emergency lighting systems have difficulties in charging when frozen. Charging may be erratic, and at times at rates much higher than the rate recommended by manufacturers for safe operation. There is also a danger that during an erratic charging process that volatile gasses, particularly hydrogen, may build-up and pose the threat of explosion. The present invention provides a heating mechanism for the rechargeable battery which keeps it at a suitable charging temperature during normal operation whether the installation site building is heated or not, enabling the use of the unit in unheated or lesser heated facilities. Further, the heater circuit addition includes means for connecting the charging circuit to an alternate load while the battery comes up to suitable temperature for charging, while keeping the appropriate relays connected so that upon the resumption of AC power, the normal fluorescent lighting may be powered by the AC main power. Once the battery temperature is sensed to be at a sufficient level for safe charging, the charging current is switched to the battery from the alternate load so as to fully recharge the battery.
Those skilled in the art will recognize that alternative approaches to the preferred embodiments of the present invention disclosed herein may be made without departing from the scope of the present invention.
The present invention is directed to an emergency ballast for operation in extreme temperature conditions where the battery powering the emergency ballast and emergency fluorescent lamp becomes frozen and requires heating to a recognized minimum temperature before safe recharging may be initiated.
One of the objectives of the present invention is to cause the internal battery of the fluorescent emergency ballast to remain in its normal operating temperature range during when main AC power is supplied to the fluorescent lamp.
A further objective of the present invention is to delay the charging of the battery in the emergency ballast after a loss of main AC power during extreme cold wherein the internal temperature of the battery has dropped below the recommended operating temperature, or has frozen, and the battery is heated to a permissible operating range before recharging current is applied.
An alternate objective of the present invention is the inclusion of the described delay in charging the battery when its internal temperature is below recommended, and the inclusion of enabling circuitry to cause the fluorescent fixture to illuminate on the return of main AC power, irrespective of the ambient temperature.
These and other objectives will be evident from the detailed descriptions of the preferred embodiments provided below.


A standardized hot-pluggable transceiving unit comprising a housing, a board and a chipset. The housing has specific standardized dimensions and is adapted to being inserted into a chassis of a hosting unit. The board and chipset are in the housing. The board comprises at least two electro-mechanical components. The chipset also comprises at least two electro-mechanical components. Each electro-mechanical component of the chipset collaborates with a corresponding electro-mechanical component of the board for simultaneously providing a mechanical anchor and an electrical connection between the chipset and the board. The chipset further comprises a programmable processing component for processing a signal transmitted by the board via the electrical connection between the board and the chipset. For instance, the programmable processing component of the chipset comprises a coding module for encoding or decoding data having a first form into data having a second form.

Small Form-factor Pluggable (SFP) units represent one example of standardized hot-pluggable transceiving units. SFP units are standardized units adapted to be inserted within a chassis. A suite of specifications, produced by the SFF (Small Form Factor) Committee, describe the size of the SFP unit, so as to ensure that all SFP compliant units may be inserted smoothly within one same chassis, i.e. inside cages, ganged cages, superposed cages and belly-to-belly cages. Specifications for SFP units are available at http:/www.sffcommittee.com/ie/index.html.
SFP units may be used with various types of exterior connectors, such as coaxial connectors, optical connectors, RJ45 connectors and various other types of electrical connectors. In general, an SFP unit allows connection between an external apparatus, via a front connector of one of the aforementioned types, and internal components of a hosting unit, for example a mother board, a card or a backplane leading to further components, via a back interface of the SFP unit. Specification no INF-8074i Rev 1.0, entitled "SFP (Small Form-factor Pluggable) Transceiver, dated May 12, 2001, available at ftp://ftp.seagate.com/sff/INF-8074.PDF, generally describes sizes, mechanical interfaces, electrical interfaces and identification of SFP units.
The SFF Committee also produced specification no SFF-8431 Rev. 4.1, "Enhanced Small Form-factor Pluggable Module SFP+", dated Jul. 6, 2010. This document, which reflects an evolution of the INF-8074i specification, defines, inter alia, high speed electrical interface specifications for 10 Gigabit per second SFP+ modules and hosts, and testing procedures. The term "SFP+" designates an evolution of SFP specifications.
INF-8074i and SFF-8431 do not generally address internal features and functions of SFP devices. In terms of internal features, they simply define identification information to describe SFP devices' capabilities, supported interfaces, manufacturer, and the like. As a result, conventional SFP devices merely provide connection means between external apparatuses and components of a hosting unit, the hosting unit in turn exchanging signals with external apparatuses via SFP devices.
Recently, SFP units with internal features and functions providing signal processing capabilities have appeared. For instance, some SFP units now include signal re-clocking, signal reshaping or reconditioning, signals combination or separation, etc. However, such SFP units lack the capability to easily adapt their signal processing capabilities, by having generic components providing a common base of SFP functionalities and dedicated components for customizing the SFP units to perform dedicated signal processing tasks.
Therefore, there is a need for a new standardized hot-pluggable transceiving unit with a chipset mechanically anchored and electrically connected to a board, the chipset providing dedicated signal processing capabilities.

Standardized hot-pluggable transceiving unit with a chipset mechanically anchored and electrically connected to a board


An improved binary decoder incorporating a selection circuit that activates a selected output corresponding to a input binary value, and a deselecting circuit coupled to each output that deactivates all other outputs when the selected output is activated. The deselecting circuit arrangement has a single input connected to the selected output and a plurality of outputs each of which is connected to one of the remaining outputs and forces them to the inactive state whenever the selected output is activated.

1. Field of the Invention
This invention relates to electronic integrated circuits, and in particular to improved binary decoders in integrated circuits.
2. Description of the Related Art
A binary decoder is a circuit that enables a single selected digital output from a defined set of digital outputs, based on an input binary value. The decoder produces an output signal on the single output that matches the input binary value. Binary decoders are essentially combinatorial logic circuits formed by an arrangement of logic gates. A binary decoder having an input value "n" bits is required to have "2n" outputs one of which corresponds with the n-bit value applied at the input. Binary decoders are widely used for performing selection functions where any single device or any single set of devices are required to be selected or enabled from a defined collection of devices or defined collection of device sets. A typical application is in selecting a row of memory cells in a memory device. Another typical application is in selecting a single IO device from a collection of IO devices in an electronic circuit.
A 2-to-4 decoder implementation according to the known art requires 16 transistors covering four different circuits, one for each combination of the input. At the same time each input signal is required to drive four GATE loads. Similarly, a 3-to-8 decoder requires as many as 32 transistors covering 8 different circuits, one for each combination of inputs, with each input having to drive 4 gate loads. This manner of implementation results in a bulky and expensive circuit requiring an undesirably large chip area. The capacitive loading on the input signals reduces the speed of the operation of the device.

Binary decoders in electronic integrated circuits


An arrangement structure for a charging port cover includes a charging port (15) having a charging inlet (21) in a charging port opening portion (17) provided on a vehicle body, and a lid (7) that covers the charging port opening portion and is openable and closable on the vehicle body. The arrangement structure further includes a charging port cover (35) attached to the lid in an opened state to cover open sections (16, 18) between the charging port opening portion and the lid. The lid is fixed to the vehicle body by hinges (5) in an openable and closable manner. The open sections are located in side portions of the lid and the charging port opening portion in an axis direction (X) of the hinges and in a front portion in a direction (Y) orthogonal to the axis direction of the hinges.

Vehicles such as electric vehicles and so-called hybrid vehicles are commonly provided with a charging port to charge an on-board battery. The charging port has a charging inlet connected to the on-board battery, and an openable and closable lid that covers the charging inlet. When the lid is open, a charging gun (a paddle) is inserted in the charging inlet to charge the battery (for example, refer to Patent Document 1).

This patent is subject to a terminal disclaimer.

Arrangement structure for charging port cover


A reliable synchronization apparatus and method within a multicast and broadcast service (MBS) zone having m sync executers (SEs) belonging to n retransmission zones is provided. Each retransmission zone has a selected leader SE and other member SEs. The apparatus comprises a sync controller and the n selected leader SEs. When the Sync controller multicasts a sync ruler to all SEs in a retransmission zone, the leader SE that loses the Sync ruler sends a NACK message to request the sync controller to retransmit the sync ruler. An election is triggered for updating leader information and announcing election to all SEs. The member SE that loses the sync ruler sends a NACK message to request its leader or the Sync controller to retransmit the sync ruler.

IEEE 802.16 standard and related international industrial association, such as, WiMAX (Worldwide Interoperability for Microwave Access), work hard to assure that high speed data transmission is available to a large number of users in a large coverage area. In wireless Internet technologies, multicast and broadcast service is provided through MBS zone. FIG. 1 shows an exemplary schematic view of a WiMAX MBS zone architecture. Under this architecture, in an access service network (ASN) environment, after receiving content data from connectivity service network (CSN) 111, a MBS controller 110 transfers the data content stored in a content sync controller server 110a to an anchor 103. Anchor 103 then distributes the content data to other linked sync controllers, such as, a synch controller 113, and a sync executer (SE), such as, SE 121-124. These SEs are distributed in a plurality of MBS zones, such as, MBS zones 101, 102.
Single-BS mode and multiple-BS mode are architectures that may realize MBS zones. In single-BS mode architecture, a mobile station always attaches to a node. In multiple-BS mode architecture, when a mobile station moves from a node to other nodes in the same MBS zone, no handover process is executed. This mobile station may receive the signals from a plurality of nodes in the MBS zone. Under multiple-BS mode architecture, all base stations (BSs) in the same MBS zone need to synchronize.
In the frame-level synchronization technique, when a subscribed service is distributed to a MBS transmission zone, all the MBS zones in the MBS transmission zone need frame-level synchronization. All MBS zones of this MBS transmission zone need to transmit the same content to the subscriber and a MBS controller is responsible for coordination so that all the MBS zones transmit the content in synchronization.
In the macro-diversity level synchronization technique, the physical parameters and the scheduling positions in waveform of all the mobile stations in the same MBS zone need to be identical. FIG. 2 shows an exemplary schematic view of the synchronization architecture. When receiving the content data from a CSN 210, a MBS distribution function unit 220 transfers the content data to a MBS sync controller 230. MBS sync controller 230 generates sync ruler and time information 232 according to the content data and transmits to MBS SE 240. SE 240 uses the information 232 to create the same waveform. Sync ruler is the guideline for creating waveform.
The locations of sync controller and SE depend on the situations. For example, sync controller and upper SE are in the access service network gateway (ASN-GW), while lower SE is in the mobile station. Or, sync controller is in ASN-GW, while SE is in the BS. Or, sync controller is an independent unit and SE is in the BS.
U.S. Pat. No. 6,718,361 disclosed a system for distributing information to a plurality of group members in a communication network. The information distribution system may use unicast to transmit sync message from sync controller to SE. As shown in FIG. 3, an information distribution system 300 includes a content control manager 301 and a group leader, such as, 303a-303c, 305a-305c. Content control manager 301 uses a tree-based structure to unicast sync message to all the connected leaders. The leaders are responsible to transfer the information to other leaders and corresponding clients. In the unicast transmission, sync message is directly transferred to SE instead of through network.
U.S. Pat. No. 6,269,080 discloses a method of using multicast to distribute data file and implement synchronization. As shown in the exemplary flowchart of FIG. 4, a file distribution and synchronization protocol (FDSP) server selects an active receiver from a group of FDSP clients (step 410). The FDSP server multicasts the data file to all the receivers and let the active receiver control the transmission rate (step 420). The active receiver uses unicast to request the FDSP server to retransmit lost data packets (step 430). The FDSP server retransmits lost data packets to respond to the active receiver (step 440). Once the active receiver obtains all the file data, the FDSP server determines whether other FDSP client still needs to obtain data file (step 450). If so, the FDSP server selects a new active receiver from the FDSP clients (step 460). Then, steps 430-460 are repeated until all the FDSP clients receive all the data files transmitted by the FDSP server.
U.S. Pat. No. 6,507,562 disclosed a method for finding an optimal repair tree in multicast communication. The optimal repair tree is formed by a sender station and a plurality of repair head stations. This method finds an optimal repair head station from a plurality of neighboring receivers. The plurality of neighboring receivers dynamically forms a repair group. The repair head station of each repair group is responsible for receiving the ACK and NACK message from the destination station of the repair group, and helps to retransmit the lost data multicast by sender station but not received to the destination station of the repair group.

Reliable synchronization apparatus and method within a multicast and broadcast service zone

Industrial Technology Research Institute


An anti-kink control for an electric cord wherein the cord has relatively flat top and bottom surfaces and relatively round side surfaces. The anti-kink control includes a series of washers assembled on the cord in closely spaced co-axial relation. A first pair of washers are joined by a first axially extending finger along each side of the cord. A next washer adjacent to one of the pair of washers is joined to the one of the pair of washers by a second axially extending finger along the top and bottom surfaces of said cord. The assembled washers form a sleeve about the cord. The space along the side surfaces between adjacent washers joined along the top and bottom surfaces is relatively larger than the space along the top and bottom surfaces between adjacent washers joined along the side surfaces.

This invention relates to an anti-kink control for an electric cord and in particular to an anti-kink control for an electric cord having flat top and bottom surfaces.
The use of high temperature, flame retardant, electrical cord or cable on small appliances such as electric skillets, kettles and the like is required by both the U.L. in the United States and the C.S.A. in Canada. One type of electric cord that has found acceptability by both the U.L. and C.S.A. for high temperature, flame retardant applications is identified as HPN grade heater cord. The elastomeric insulating jacket of the cord is extruded over the cord's conductors. The three conductive wires of the cord are positioned in the same vertical plane and lie parallel to each other. HPN grade heater cord has generally flat top and bottom surfaces and rounded side surfaces. The flat electrical cord having an HPN insulating jacket, can readily flex in directions that are vertically upward or downward relative to the flat surfaces. However, the cable does not readily flex when moved in a horizontal plane in a direction that is generally 90.degree. to the longitudinal axis of the cable. In most instances with anti-kink devices presently available, a cord when flexed in a horizontal plane, 90.degree. to its longitudinal axis, will develop a sharp bend or radius causing stress on the electrically conductive wires passing through the cord. This stress will eventually result in fatigue of the wires causing premature failure of the cord.
The present invention overcomes the foregoing problem by enabling a flat electric cord to be flexed both vertically upwardly and downwardly and also in a horizontal plane 90.degree. relative to the longitudinal axis of the cord. The durability of the electrical cord has been improved. In the prior art, the cord would fail after 5,000 flexes with a one quarter pound load on the cord. Utilization of the present invention enables the cord to withstand in excess of 10,000 flexes with a one pound load.
As a secondary benefit, since the anti-kink control is molded integral with the jacket of the electrical cord, the anti-kink control also functions as a strain relief for the electric cord.
It is accordingly an object of this invention to form an anti-kink control for an electric cord which effectively enables the cord to be flexed both upwardly and downwardly relative to the top and bottom surfaces thereof and in a horizontal plane 90.degree. relative to the longitudinal axis of the cord.


The present invention relates to a dressing (1) for protecting the skin around objects projecting out from the skin, the dressing including a first liquid impermeable film layer (2) coated with a skin friendly adhesive (3) on the lower side thereof, i.e. the side intended to adhere to the skin when the dressing is used. According to the invention a body (4) of absorbent material is enclosed between the first film layer (2) and a second liquid impermeable film layer (5), the second film layer being affixed to the first film layer in parts extending beyond the periphery of the body of absorbent material, and the dressing includes an element (8) for facilitating passing of an object projecting out from the skin through the dressing.

Many medical or surgical interventions include penetration of objects, such as tubes, instruments and other medical articles, through the skin and into tissue or cavities in the body of a patient. In certain cases such objects are left in the body for shorter and longer periods, from a few minutes to months or years. Examples of such objects are percutaneous endoscopic gastrostomy (PEG) feeding tubes, tracheostomies, cannulae, catheters and pins for external fixation of bones. Leakage of body fluids often occurs around such penetrating objects. The leaking body fluids often gather around the penetration openings for the objects which can result in maceration of the skin, irritation of the skin, skin infection and even sores.
In order to take care of possible leaking fluid around penetration openings, compresses or pads of cotton wool or other absorbent materials are often wound or laid around the object projecting out of the skin. A slit is often made in such pads to facilitate application thereof in the area around the object. Such pads or compresses are usually affixed to the skin and to the object by self-adhesive tape. Wound dressings or plasters comprising a wound pad and a self-adhesive fixation part are also used. A drawback by such compresses or pads is that they exhibit a wet or moist surface to the skin after having absorbed fluid. Thereby there is still a risk for maceration and skin irritation. Such pads or compresses have to be changed often in order to exhibit a dry surface to the skin. Since the skin around penetration openings often is very sensitive, the frequent changing of absorbent pads or compresses increases the risk for irritation of and damage to the skin which in turn increases the risk for infection to occur.
WO 2007/013912 describes a disposable pin site wound protection system for covering the entry or exit of a surgical pin, wherein the system substantially reduces the time required to change a dressing at a pin site wound. This system comprises a sponge and a clip, both of which are designed to be attached to a pin site wound.
Allevyn Tracheostomy from Smith&Nephew is made of a non-adhesive, cushioned foam having a key-hole shaped hole for application around a tracheostomy tube or on the stoma.
Drawbacks with non-adhesive products are the weak affixing to skin which can increase the risk of leakage and in turn cause skin maceration and even infections.
WO2006/99173 relates to a fork-like device for changing tracheostomy sponges on a patient.
As tracheostomy dressings in hospitals today are often used adhesive dressings or foams cut manually to fit the stoma. Other than a risk of maceration and skin damage there is also a risk of leakage at dressing changes with such non adhesive and non encapsulated foam dressings.
The adhesives of the fixation tapes, wound dressings or plasters usually used for such products usually take portions of the skin away when these products are loosened from the skin. The risk for damage to the skin by frequent changing of such products is thus relatively high if the object projecting out of the penetration opening is disposed in the body of the patient during a long period of time. The changing of such products will also lead to pain to the patient since it hurts when the product is loosened from the skin. Another drawback is that gauzes or other types of absorbent material disposed around such objects will have a wet outside which can soil clothes or the like disposed outside the penetration opening.
Prior art describes the problem of time consuming dressing changes, but it does not describe the problem of exudate leaking out from the wound to the periwound skin causing risk of maceration and bacterial growth on the skin, which can lead to wound infection.
The objective of the invention is to improve a dressing of the kind mentioned in the introduction which is easy to apply and eliminates or at least greatly reduces the drawbacks mentioned above.

Dressing for protecting the skin around objects projecting out therefrom


A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.

The present invention relates to a method for fabricating a semiconductor memory device; and, more particularly, to a method for fabricating a CMOS transistor.
A complementary metal oxide semiconductor (CMOS) transistor includes a nMOS transistor and a pMOS transistor. If the CMOS transistor is used for configuring a peripheral circuit of a memory device of 0.18 xcexcm and below, the COMS transistor includes the 0.25 xcexcm and larger nMOS and pMOS transistors having a gate length larger than a minimum line width. The above mentioned CMOS transistor is configured by concurrently forming a lightly doped drain (LDD) region of a surface channel nMOS transistor and a punch stop layer of a buried channel pMOS transistor. The LDD region and the punch stop layer is formed by ion implantation of an n-type dopant such as phosphorus (P) into a forming region of the nMOS transistor and a forming region of the pMOS transistor without using a mask.
FIGS. 1A to 1B are cross-sectional views showing a conventional process for fabricating a CMOS transistor.
Referring to FIG. 1A, after forming a device isolation layer for isolating each of devices in a semiconductor substrate 11, a n-type well 13 is formed on a region of a pMOS transistor in the semiconductor substrate 11 and continuously an n-type field stop layer 14 is formed in the n-type well 13. A p-type well 15 is formed on a nMOS transistor region in the semiconductor substrate 11 and a p-type field stop layer 16 is formed on the p-type well 15.
After forming the p-type field stop layer 16, a gate oxide layer 17 and a gate electrode 18 is formed on a selected region on the semiconductor substrate 11 providing the pMOS transistor and nMOS transistor. Finally, there formed an n-type punch stop layer 20 on the pMOS transistor and an n-type LDD 21 on the nMOS transistor by ion-implanting phosphorus (P) by using a blanket ion implantation and depositing a nitride layer 19 on the above entire structure.
Referring to FIG. 1B, after an oxide layer (not shown) is deposited on the entire structure, a spacer 22 contacting to lateral sides of the gate electrode 18 is formed by an etch-back process. At this time, the nitride layer 19 and the gate oxide layer 17 are concurrently proceeded with an etch-back process applied to an upper surface of the semiconductor substrate 11. Reference numerals 19A and 17A are a remaining nitride layer and a remaining gate oxide layer, respectively.
Next, a p-type source/drain region 23 is formed by ion-implanting a p-type impurity in the pMOS transistor region, and an n-type source/drain region 24 is also formed by ion-implanting an n-type impurity on the nMOS transistor region.
In FIGS. 1A and 1B, when the n-type LDD doping layer 21 is formed on the nMOS transistor region, the n-type punch stop layer 20 is also formed on the pMOS transistor region.
However, in the above mentioned conventional method for fabricating the CMOS transistor, optimum characteristics of the nMOS transistor and the pMOS transistor cannot be obtained, since forming conditions for the LDD region of the nMOS transistor and the punch stop layer of the pMOS transistor are identical. As a result, one of the characteristics of the nMOS transistor and the pMOS transistor is degraded.
Furthermore, the above mentioned conventional method cannot control a short channel effect provided by each of the nMOS transistor and the pMOS transistor since a gate length of a peripheral circuit is below 0.25 xcexcm in the memory device of above 0.15 xcexcm.
For example, when the n-type impurity is ion-implanted for concurrently forming the LDD region and the punch stop layer, the short channel effect of the pMOS transistor is constrained according to an amount of the n-type impurity for ion-implantation, however, the short channel characteristic of the nMOS transistor is degraded. Also, when the n-type impurity is ion-implanted with a minimally increased quantity for increasing driving current of the nMOS transistor, a threshold voltage VT is dynamically increased and the driving current is decreased. Therefore, reducing the gate length of the MOS transistor provides a limitation in a fabricating process for the CMOS transistor.
For overcoming the above mentioned problem, another conventional CMOS transistor fabricating method is introduced by Takashi Hori et al., at xe2x80x9cA 0.1 xcexcm CMOS technology with tilt-implanted punch through stopper (TIPS)xe2x80x9d IEDM, 1994 (hereinafter Takashi). The Takashi teaches a method for fabricating a CMOS transistor having a gate length around 0.1 xcexcm. The Takashi""s method individually performs ion-implantations to form the punch stop structure of a surface channel nMOS transistor and a buried channel pMOS transistor by using different masks.
FIG. 2 is a cross-sectional view of a CMOS transistor for explaining the Takashi""s forming process of a CMOS transistor.
Referring to FIG. 2, a gate oxide layer 25 and a gate electrode 26 are formed on a semiconductor substrate 24, and a spacer 27 is formed on both lateral sides of the gate electrode 26. A LDD region 28 is formed at edges on both sides of the gate electrode 26 in the nMOS transistor region. An n+ source/drain region is formed by contacting to the LDD region 28, and the p-type punch stop layer 30 is formed on a bottom of the LDD region 28 by performing the tilted ion implantation of boron (B). In the pMOS transistor region, a p+ source/drain region 31 is formed and an n-type punch stop layer 32 is formed on a side of the p+ source/drain region 31 by tilted ion implanting phosphorus (P).
Atsuki Hori et al. introduces another method for fabricating a CMOS transistor in xe2x80x9cA 0.05 xcexcm CMOS with ultra shallow source/drain junctions fabricated by 5 KeV ion imimplantation and rapid thermal annealingxe2x80x9d IEDM, 1994 (Hereinafter Atsuki). The Atsuki""s method teaches to fabricate the nMOS transistor and the pMOS transistor in order to have a gate of 0.5 nm by using a self aligned pocket implantation (SPI) and a source/drain extension (SDE).
FIG. 3 is a cross-sectional view of a CMOS transistor for explaining the Atsuki""s forming process.
Referring to FIG. 3, a gate oxide layer 34 and a gate electrode 35 are formed on a semiconductor substrate 33. Also, a spacer 36 is formed on both lateral sides of the gate electrode 35. An n+ source/drain extension region 37A is formed on both edges of the gate electrode 35 in the nMOS transistor region. An n+ source/drain region 38B is formed by contacting to the n+ source/drain extension region 37A. A p-type self aligned pocket layer is formed beneath of the n+ source/drain extension region 37A by tilted ion-implanting boron (B). An n-type self aligned pocket layer 39A and a p+ source/drain extension region 37A are formed on both edges of the gate electrode 35 in the pMOS transistor region. A p+ source/drain region 38B is formed by contacting to the p+ source/drain extension region 37B and the n-type self aligned pocket layer 39B.
As mentioned above, the Atsuki and Takasi provide methods that optimize characteristics of the nMOS transistor and the pMOS transistor. However, the methods use different masks for each of nMOS transistor region and pMOS transistor region. Additional processes such as a LDD doping process and a source/drain extension region process are performed. As a result, a complexity of a fabricating process is increased and a manufacture expense is also increased. Therefore, the above mentioned methods are incongruent for manufacturing a semiconductor memory device.
Specially, in case of the Atuski"" method, arsenic (AS) is used for forming the source/drain extension region of the nMOS transistor. As a result, a problem with respect to a hot carrier is arose when the nMOS transistor is used in one of peripheral circuits, which require a higher driving voltage such as an external voltage.
Therefore, it has been demanded that a simple and low cost method for fabricating a CMOS transistor in order to be implemented to a semiconductor device of 0.15 xcexcm, wherein the method can maintain optimum characteristics of the nMOS transistor and pMOS transistor and prevent the hot carrier problem.
It is, therefore, an object of the present invention to provide a simple and low cost method for fabricating a CMOS transistor in order to constrain a short channel effect and a hot carrier effect.
In accordance with an aspect of the present invention, there is provided a semiconductor, comprising a gate electrode and a gate oxide layer on a semiconductor substrate; spacers formed on sides of the layer; a first conductive type source/drain region formed at edge of the spacers in the semiconductor substrate; a second conductive type punch stop layer formed in a region between the first conductive type source/drain region in the semiconductor substrate; a first conductive type source/drain extension region occupying a extended region from the first conductive type source/drain region to the both edges of the gate electrode; and a first conductive type lightly doped drain (LDD) region being adjoined to the source/drain region and surrounding the source/drain extension region, wherein the junction depth of the first conductive type LDD region is constrained by the punch stop layer.
In accordance with another aspect of the present invention, there is also provided a semiconductor device, comprising: a semiconductor substrate having a nMOS region and a pMOS region; a gate electrode and a gate oxide layer formed on each of the nMOS region and the pMOS region; spacers contacted to sides of the layer; a p-type source/drain region formed in the pMOS region by lining up at edges of the spacers; a n-type source/drain region formed in the nMOS region by lining up at edges of the spacers; a first punch stop layer formed by overlapped on bottom of the p-type source/drain region; a second punch stop layer formed by contacting to one side of the p-type source/drain region and on the bottom of the spacers; a third punch stop layer formed by contacting to one side of the n-type source/drain region; a source/drain extension region formed by contacting to one side of the n-type source/drain region and on bottom of the spacers; and a lightly doped drain (LDD) region surrounding the source/drain extension region.
In accordance with still another aspect of the present invention, there is also provided A method for fabricating a CMOS transistor, comprising: a) forming a n-type well region in a semiconductor substrate; b) forming a first n-type punch stop layer in the n-type well; c) forming a p-type well region in the n-type well region; d) concurrently forming a first n-type LDD region in the p-type well region and a second n-type punch stop layer in the n-type well region by ion-implanting an impurity to the gate electrode as a mask; e) forming a n-type source/drain extension region having higher concentration of the impurity than the first LDD region in the first LDD regions; f) forming a second n-type LDD region, which surrounds the n-type source/drain extension region; g) forming a spacer at a side of the gate electrode; h) forming p-type source/drain region contacting to the first punch stop layer and the second punch stop layer; and i) forming a n-type source/drain region contacting to the source/drain extension region and the first and second LLD region.


A vehicle control device includes a detection unit detecting an object around the vehicle, a storage unit storing static object information acquired in advance and reliability of the static object information in association with each other, an acquisition unit acquiring calculation load information of the vehicle control device, a decision unit deciding a reliability threshold to be small with respect to an increase in a calculation load based on the calculation load information, a selection unit selecting the static object information associated with reliability equal to or greater than the reliability threshold from the static object information, a target decision unit deciding a tracking target by comparing a detection result and the static object information selected by the selection unit to each other, a tracking unit tracking the tracking target, and a control unit performing the traveling control based on a tracking result.

Japan SPOTLIGHT 2016 July/August pp. 28-pp. 33 "Future Advanced Driving Support System with Automated Driving Technology" discloses a background subtraction method for detecting a dynamic object. According to this method, the measurement result of a sensor at a time when no dynamic object is present is stored in a database as static object information. Then, the static object information is compared to the measurement result of the sensor at each time. The difference between both (part where both do not correspond) is detected as the dynamic object.


A guide blade of a turbomachine, in particular of a compressor, a blade of the guide blade without an inner shroud having a flow inlet edge, a flow outlet edge, a suction side, and a pressure side. The blade is formed by a plurality of blade sections stacked one on top of the other in the radial direction, and the centers of gravity of the blade sections extend along a stacking axis. The blade sections are stacked one on top of the other in the radial direction in such a way that, in a radially inner section of the blade adjacent to a radially outer section of the blade, the stacking axis has its single inflection point in its radial curvature, namely, between a first, radially inner subsection of the radially inner section in which the stacking axis has a concave curvature toward the pressure side, and a second, radially outer subsection of the radially inner section in which the stacking axis has a concave curvature toward the suction side.

A turbomachine, for example a compressor of a gas turbine, has a stator and a rotor. The stator includes a housing as well as guide blades on the stator side. The rotor includes a rotor base body as well as rotor blades which rotate together with the rotor base body.
A stator-side guide blade has a blade, the blade being defined by a flow inlet edge, a flow outlet edge, a suction side, and a pressure side. The blade of a guide blade radially outwardly adjoins the stator-side housing, and is preferably fastened to the stator-side housing via a blade root. An end, i.e., a tip, of a guide blade without an inner shroud radially inwardly adjoins a hub of a rotor base body, a so-called running clearance being formed between the hub of the rotor base body and the radially inwardly situated end of the guide blade without an inner shroud.
Guide blades known in practice are formed or defined by blade sections which are stacked on or above one another, viewed in the radial direction of the guide blade. The centers of gravity of these blade sections extend along a so-called stacking axis; in guide blades known in practice, the stacking axis extends uncurved or continuously curved essentially in the radial direction. For such a guide blade having no associated inner shroud, losses in the proximity of the rotor hub increase greatly with the height of the running clearance, resulting in loss of efficiency of a turbomachine, which is disadvantageous.


A fuse link (50) is formed using a method which offers greater scalability of the general conductor system used to wire the device. An oxide mask (36) having the shape of a desired fuse link is formed over a thin metallization layer (34). A barrier layer (38) is formed over the thin metallization layer (34). A conductive layer (40) is formed over the barrier layer (38). A photoresist mask (42) supplied to the conductive layer (40), and the conductive layer is etched to formed interconnects (44, 46). Subsequently, the barrier layer (38) and thin metallization layer (34) are etched, thus rendering a fuse link (50) between interconnects (44, 46) under the oxide mask (36).

Fuse links have been used for many years in digital integrated circuits, particularly programmable read-only memories (PROMS) and programmable logic arrays (PALS). The fuse links are used to connect matrices of circuit elements for custom applications or for permanent data storage, by selectively breaking unwanted fuse links. Fuse links are broken by various techniques such as selectively applying a sufficiently large current through the unwanted links.
As with many other semiconductor products, increasing integration of devices on a single chip is rapidly obsoleting the processing techniques used to fabricate fuse link devices. Dry plasma etching is increasingly replacing wet chemical etching, providing an increased level of integration. Although dry plasma etching allows smaller device widths and pitches, it can damage sensitive components on the surface of the substrate by overetching. Hence, it is important to minimize interaction between the dry etch and surface components as much as possible.
Scalability is also an important criterion in semiconductor processing. A process which can be easily adapted to smaller components is one which has a high degree of scalability. Previously developed processes for forming a fused link are not adaptable to highly integrated circuits wherein the width of the interconnecting leads and the spaces between the interconnecting leads have substantially decreased.
Furthermore, competitive forces have applied pressure to reduce the price of semiconductor products. Therefore, it is important that semiconductor production be as efficient as possible. The cost of a semiconductor device is largely dependent upon the number of masking levels used in fabricating the device. Thus, it is desirable to reduce the number of masking levels, and the associated critical alignment tolerances required during masking. Previously developed techniques for fabricating fuse links have presented difficulties in reducing the number of mask levels and in reducing alignment tolerances.
Therefore, a need has arisen for a fuse link process which minimizes dry etch damage and over etch of sensitive layers on the surface of the substrate, reduces the number of masking levels and the associated critical alignment of tolerances required during masking, and offers a high degree of scalability by using dry processing as much as possible.

Method of making a scalable fuse link element


A method of controlling or containing radioactive contamination by providing a neutron absorbing material to a radioactive contamination site. Preferably the neutron absorbing material is present as a powder, granule, slurry or suspension, allowing the neutron absorbing material to blanket cover the radioactive contamination site. Suitable neutron absorbing materials include lanthanide elements having a cross section of 100 Barns or greater, as well as hafnium, zirconium, tantalum, silver, indium, and hydrogen.

Radioactivity involves spontaneous disintegration of unstable atomic nuclei by the emission of subatomic particles including alpha particles (helium ions), beta particles (electrons), and/or neutrons along with the emission of electromagnetic radiation including X-rays or gamma rays. Due to the charged nature of alpha and beta particles, their penetrating ability into matter is limited. However, electromagnetic radiation and especially neutrons can penetrate deeply into matter and thick physical barriers are necessary to provide adequate shielding. Neutron emission and subsequent bombardment is especially damaging to living system and has the unique quality that it can interact with the nucleus of many atoms and destabilize them to cause/promote additional radioactivity.
The release and subsequent interactions of neutrons with another atoms nucleus is the basis of nuclear fission. For example, when a neutron hits a uranium 235 atom, this atom in turn releases about 2.5 neutrons, on average, from the split nuclei. The neutrons released in this manner quickly cause the fission of two more atoms, thereby releasing four or more additional neutrons and thus a self-sustaining series of nuclear fissions, or a chain reaction is initiated resulting results in a sustainable release of nuclear energy. Analogously, when plutonium 239 itself absorbs a neutron, fission can occur, and on the average about 2.8 neutrons are released. Additionally, many atoms can be made radioactive after being hit with a neutron even though they are not capable of sustaining nuclear fission. Instead of releasing neutrons, these atoms release alpha particles, beta particles, and gamma radiation, all of which are highly damaging to living biological systems. Other classes of atoms, called neutron absorbers, can absorb neutrons and yet remain stable; i.e. not radioactive. Thermal neutrons (0 to 500 keV) are absorbed very effectively by specific elements including boron (or B-10 isotope), gadolinium, dysprosium, samarium, cadmium, or europium. Very high energy neutrons (1 to 15 MeV) are absorbed by elements such as zirconium, hafnium, tantalum, indium, hydrogen, or silver.
The power of the atom has been harnessed in several ways including the development of nuclear weapons and in nuclear power plants. Modern nuclear power plants are inherently safe, however, accidents have occurred in the past. In 1979, a nuclear accident occurred in the United States at the Three Mile Island PWR near Harrisburg, Pa. and a small amount of radioactivity escaped from the containment vessel. In 1986, one of four nuclear reactors at Chernobyl exploded and burned for an extended period of time and radioactive material spread over the Ukraine, Scandinavia, and northern Europe.
Since the terrorist attack on Sep. 11, 2001 in the United States, it has become increasingly apparent that the world is an inherently dangerous place. Terrorists, state enemies, criminals, etc. may have at their disposal a wide variety of mass destruction weapons including biological, chemical, and nuclear based weapons. This invention disclosure involves drastically reducing/minimizing the effects of nuclear based/derived weapons by the application of neutron absorber materials/particulates in various forms. Several key scenarios will be listed to give examples of the key embodiments of this invention. Other applications which are not listed but which are variations of this are also covered by this invention.
It has been known since the 1950's that neutron absorbers may be used to moderate the reaction rate in nuclear reactors. Additionally, in the 1990's, it was known that neutron absorbers may have uses in waste packages for the long term storage of nuclear waste. However, there has been no previous knowledge for using neutron absorber materials in the manner identified herein.

Method of containing radioactive contamination


A sprocket damping assembly for a sprocket wheel of a track-type work machine may include an annular damping ring having an annular retention device. The damping ring may include a ring body section having a ring body section radial thickness, and a retention groove section integrally formed at an outboard side of the ring body section. The retention groove section may have a retention groove section axial width and a retention groove section radial thickness. The retention device may have a retention device axial width that is less than or equal to the retention groove section axial width. The retention device is disposed on the retention groove section when the damping ring is disposed on a sprocket drum outer surface of the sprocket wheel to retain the sprocket damping assembly. The retention groove section radial thickness may be less than the ring body section radial thickness.

Work machines such as track-type tractors are used in a great many different operations, ranging from pushing loose material or debris about a worksite to grading, production dozing or scraping where materials are dug from a substrate, and still other applications related to site preparation, forestry, mining, and general civil engineering. Track-type tractors offer the advantage of a rugged build and substantial capacity for drawbar pull and traction in challenging underfoot conditions, steep terrain, and when towing or pushing large loads. A typical undercarriage of a track-type work machine consists of an endless track made of a number of connected links with shoes mounted thereon, a drive sprocket driven by a power source of the work machine such as an internal combustion engine or electric motor that meshes with the links to drive the track, and a number of idler wheels and rollers that distribute the weight of the work machine along the track.
Track-type work machines are generally quite noisy in operation. Such noise is becoming increasingly objectionable, especially when such work machines are operated in highly populated areas. Environmental regulations, both in the United States and in other countries, are increasingly being directed to the suppression of noise emitted by construction equipment. One source of such noise can be the metal-to-metal impact occurring between the teeth of the drive sprocket and the bushings of the track links during the meshing between the teeth and the links.
Various types of devices have been utilized to reduce the noise generated by the track. For example, U.S. Pat. No. 4,034,618 to Groff et al. discloses a pair of annular treads of resilient material that are mounted about the peripheries of cylindrical wall members on opposite sides of the sprocket and positioned in radial alignment with respective inwardly facing rail surfaces on links of the track. The treads are formed from a plurality of arcuate segments constructed from a plurality of separated tapered pads each having an aligned opening to cooperatively form a continuous cavity within which a curved steel band is disposed. Ends of the steel bands of adjacent segments are connected to each other and/or to the periphery to form the annular treads.


Disclosed are stair stepped PCB structures which provide high performance, direct path, via-less interconnections between various elements of an electronic interconnection structure including, among others, IC packages and connectors.

Since the development of the integrated circuit there has been a constant increase in the speed of electronic signals brought on by the continuous increases in transistor density in semiconductor process. While the needs of electronic signals were successfully handled by traditional methods of IC packaging and interconnection for most of the history that followed the introduction of the IC, beginning in the late 1990s it was becoming increasingly clear that traditional approaches would reach a point where they could no longer deliver the performance needs of the signal. Today, semiconductor technology has finally pushed the limits of traditional IC packaging, printed boards and connector technology to the point where the current construction techniques can no longer provide adequate signal quality.
For current and foreseeable future generations of electronic systems, controlling signal loss and the impedance of signal traces has become the key area of focus for the electronic system designer intent on transmitting electrical signals in the gigahertz range. The approach to date for IC chip packaging and printed circuit board design to address the problem has been to make incremental changes in material choice and design and supplement those choices with sophisticated semiconductor electronics that pre and/or post emphasize the signal and to employ higher power to overcome the losses associated with the parasitic effects of present design and manufacturing practices. To gage the size of the gap, one can look at current generation IC microprocessors which are operating at near 4 gigahertz while the PCB bus which serves them operate at only 800 MHz.
Included among those features that can have deleterious effects are abrupt transitions and features such as plated vias which alter the capacitance in mid run creating signal discontinuities and their stubs which cause reflections and electronic noise. Thus plated vias, solder balls and trace transitions between layers all introduce deleterious impedance changes resulting in poor signal quality. This limits overall signal speed.
While their have been attempts to minimize the parasitic effects of circuit design elements, adjustments so far have yielded only marginal benefit and there is opportunity and need to improve on current design and manufacturing approach to meet the pending demand for a significant magnitude leap in performance required for next generation electronic systems. However, if one can eliminate or severely limit or mitigate the use of vias, solder balls and trace transitions, a printed circuit board is capable of supporting much higher signal speeds with less signal degradation.

Stair step printed circuit board structures for high speed signal transmissions


A channel region is formed in a device after the source and drain regions are formed by implanting ions into the channel region with a tilt angle using multiple rotations. A rapid thermal annealing step is performed to activate the channel dopant. Because the source and drain regions are already formed, a relatively low temperature, e.g., 990 to 1010 degrees Celsius, and short, e.g., 1 to 5 seconds, rapid thermal annealing step may be performed to activate the channel region. Thus, the dopant concentration in the channel region may be well localized and accurately controlled.

Current processing methods for transistors, e.g., field effect transistors (FETs), metal oxide semiconductor devices (MOS), and complimentary MOS devices (CMOS), uses ion implantation in the channel region to control the threshold voltage of the device. The channel region becomes conductive when an appropriate gate to source voltage difference is applied to cause a conductive channel to form between the source and the drain. By controlling the channel dopant concentration, the threshold voltage may be controlled to achieve high performance transistors.
Conventionally, a blanket doping of the substrate with the intended channel implant is performed prior to gate formation. The gate oxide and gate are then formed followed by the source/drain regions. The implants are then activated with an annealing step. During the annealing step, transient enhanced diffusion occurs, causing the channel dopants (and the source/drain implants) to be redistributed in an uncontrolled fashion. Consequently, the channel dopant concentration is difficult to control using conventional methods.
Thus, there is a need for a method of forming well localized channel regions that is not redistributed by subsequent processing steps.

Channel formation after source and drain regions are formed


A multi-layer composite synthetic test bed may be used to model fracture propagation and fracture networks. For example, a fracturing fluid may be introduced into a multi-layer composite synthetic test bed at a pressure and a flow rate sufficient to create a fracture network therein. Then, the fracture network may be analyzed to produce synthetic fracture data, which may be used in a fracture model.

The exemplary embodiments described herein relate to fracturing operations of subterranean formations.
Subterranean formations are often stimulated by hydraulic fracturing operations to enhance the volume of fluid produced from the formation in later production operations. In traditional hydraulic fracturing operations, a fracturing fluid, which may also function simultaneously or subsequently as a carrier fluid, is pumped into a portion of a subterranean formation at a rate and pressure sufficient to create or extend at least one fracture therein. Typically, particulate solids, often referred to as proppant particles, are suspended in a portion of the fracturing fluid or subsequently introduced proppant slurry. The proppant particles fill at least a portion of the fractures to form a proppant pack and serve to prevent the fractures from fully closing once the hydraulic pressure is removed. By keeping the fractures from fully closing, conductive paths are formed through which fluids produced from the formation may flow.
The degree of success of a subsequent production operation depends, at least in part, upon on the design of the fracturing operation and its relative optimization vis-à-vis the particular formation in which it will be placed. Designing the right fracturing operation for a given application often involves modeling many interrelated parameters including materials (e.g., fracturing fluids, proppants, etc.), tools (e.g., zonal isolation devices, etc.), pumping schedules, treatment pressures, fluid rates, fracture mechanics, and the parameters relating to the well bore and the surrounding subterranean formation (e.g., rock type, deviation of the well bore, depth of the zone in the formation to be fractured, etc.) Predicting the outcome and results of a fracturing operation is important to not only maximize production levels for hydrocarbons, but also protect water tables and other surrounding concerns.
To design fracturing methods optimized for the specific interrelated parameters associated with a given job or project, oftentimes researchers create lab scale models mimicking the subterranean formation, rock type, rock mechanics, and other parameters affecting fracturing of subterranean, which are referred to as synthetic test beds (STBs). Using these STBs, researchers can test theories relating to the interrelated parameters involved in the fracturing operation to design a particular fracturing job.
Standard STBs usually consist of homogenous plastic blocks, e.g., polymethylmethacrylate blocks, like that illustrated in FIG. 1. The STB is placed in a test rig and then fractured using conditions and fluids of interest. Although the clearness of the plastic in the STB enables the observer to observe the fracturing effect of an injected modeled fluid, the monolithic nature and homogeneity of the STBs composition is not representative of actual sedimentary rock. Sedimentary rock is a layered composite structure (e.g., bedding planes), each layer potentially having different characteristics (e.g., rock mechanical properties) that may affect a fracturing operation. Thus, these homogenous plastic STBs are not able to model a fracturing operation sufficiently to optimize fracturing operations. Consequently, observers cannot gain an adequate understanding of the relative effect of changes in the interrelated parameters (e.g., stress interference, rate, viscosity, process order, etc.) that affect the modeled fracturing operations. Additionally, observers are unable to accurately test or create optimized hypotheses from which more predictable fracturing operations result, which is important because of the extra scrutiny placed on fracturing operations.

Synthetic test beds for fracturing optimization and methods of manufacture and use thereof


An ultrasonic transducer comprises: an acoustic matching layer including at least a layer made up of a hard material; a piezoelectric member of which the length dimension is shorter than this acoustic matching layer, which is fixed and disposed at a predetermined position of a layer made up of the hard material which makes up the acoustic matching layer, and divided into a plurality of piezoelectric devices in this disposed state; and a transducer shape-formative member made up of a hard material, wherein, in a state in which the surfaces of the piezoelectric devices divided and formed are disposed on the inner circumferential surface side, the plurality of piezoelectric devices are arrayed in a predetermined shape, fixed and disposed on the surface where the piezoelectric devices of the acoustic matching layer protruding from the piezoelectric devices have been disposed.

1. Field of the Invention
The present invention relates to an ultrasonic transducer employed for an ultrasonic diagnostic apparatus and the like.
2. Description of the Related Art
In the medical field, various types of ultrasonic diagnostic apparatuses have been proposed in conventional art wherein information regarding living body tissue is obtained by transmitting an ultrasonic wave toward the living body tissue from an ultrasonic transducer, and also receiving a reflected wave reflected by the living body tissue with the same ultrasonic transducer as the ultrasonic transducer which transmitted the ultrasonic wave, or another ultrasonic transducer provided in another member to perform signal processing for making an image.
Examples of ultrasonic transducers employed for such an ultrasonic diagnostic apparatus include an ultrasonic transducer employing the electronic scanning method wherein a plurality of piezoelectric devices are arrayed regularly, and driven sequentially. Examples of such an ultrasonic transducer include a radial-array type wherein a plurality of piezoelectric devices are arrayed in a cylindrical shape, a convex-array type arrayed in a generally partially cylindrical shape, and a linear-array type arrayed in a flat plate shape.
Of these, the radial-array ultrasonic transducer is applied to the ultrasonic probe disclosed in Japanese Unexamined Patent Application Publication No. 2-271839, for example. With this ultrasonic transducer, a transducer unit is formed by sequentially bonding piezoelectric device plates and acoustic-matching layers of which materials are lead zirconate titanate, or the like to a supporting member made up of a thin plate having flexibility with damper effects. Subsequently, a transducer array having a plurality of ultrasonic transducers are configured by forming grooves in a predetermined pitch orthogonal to one side in the longitudinal direction using cutting means while excluding lower supporting members, and the backsides of the supporting members making up this transducer array are bonded and formed around a damper member (backing member described in the specification of the present application) also serving as a circular fixing member.
Also, with Japanese Patent No. 2502685, the method for manufacturing an ultrasonic probe has been disclosed wherein a first acoustic matching layer, and a backside load member made up of a deformable member or the like, on both sides of a piezoelectric device is provided, grooves reaching part of the backside load member from the first acoustic matching layer side are formed in a predetermined interval using cutting means, and the backside load member is bonded and fixed on the outer side of a curved member formed with a desired curvature.
Also, an example of the above array ultrasonic transducer has been disclosed in Japanese Unexamined Patent Application Publication No. 10-308997. This ultrasonic transducer is formed by forming a recessed portion made up of a groove or a notch on at least any one of the first side and the second side of a piezoelectric member having electrodes, and engaging a conductive member with this recessed portion, and also electrically connecting this conductive member to the electrode near the recessed portion.
Also, with Japanese Patent No. 2729442, the ultrasonic probe has been disclosed wherein the ultrasonic probe comprises an ultrasonic transducer, a ground electrode provided on the front surface side of this ultrasonic transducer, a positive electrode provided on the back surface side of the ultrasonic transducer, an acoustic matching layer bonded on the ground electrode surface side of the ultrasonic transducer, and a conductive member for forming a superimposed structure by superimposing the acoustic matching layer and a backside load member provided on the positive electrode side of the ultrasonic transducer, also exposing the ground electrode by cutting and removing part of the side edge portion of one-side of this superimposed structure from the acoustic matching layer on the front surface side to the backside load member on the back surface side, and electrically connecting the cut surface of the backside load member and the edge surface of the ground electrode by firmly fixing the conductive member, which is connected to the positive electrode.
Also, the electronic scanning ultrasonic probe according to Japanese Unexamined Patent Application Publication No. 2-271843 has been disclosed wherein a damper member is flowed into a cylinder made up of a transducer unit to make up a radial scanning ultrasonic probe.

Ultrasonic transducer and manufacturing method thereof


Method and apparatus for analyzing particles based on different depolarizing structure associated with the different particle types. Cells in a flow cytometer are illuminated with a linearly polarized light, producing scattered depolarized light whose intensity range, at a selected measuring angle, and in a suitable discriminating space, is used to analyze different particle types.

Particle discrimination methods are useful in a variety of clinical assays, such as in determining the number and types of cells in a blood sample, detecting bacterial or virus particles in a body fluid sample, and assaying cell volumes and density, e.g., sperm count. Detection of non-cellular particles, such as uric acid crystals in a urine sample, is also valuable in certain clinical tests. Analysis of crystals and other particles in fluid suspension also has important industrial uses.
One method which allows rapid and efficient particle discrimination in a particle-suspension sample is flow cytometry. In this method, a suspension of particles, typically cells in a blood sample, is transported through a flow chamber where the individual particles in the sample are illuminated with one or more focused light beams. The interaction of the light beam(s) with the individual particles flowing through the chamber is detected by one or more light detectors. Commonly, the detectors are designed to measure light absorption or fluorescence emission, at specific beam or emission wavelengths, and/or light scattering at specific scattering angles. Thus each particle that passes through the flow chamber can be characterized as to one or more features related to its absorption, fluorescence, light scattering or other optical or electrical properties. The one or more properties which are measured by the detectors allow each particle to be mapped into a feature space whose axes are the light intensities or other properties which are measured by the detectors. In the ideal, the different particles in the sample map into distinct and non-overlapping regions of the feature space, allowing each particle to be analyzed based on its mapping in the feature space. Such analysis may include counting, identifying, quantifying (as to one or more physical characteristics) and/or sorting of the particles.
Two general types of light scattering measurements are routinely made in flow cytometry. Light intensity measurements made at small angles (about 1.5.degree.-13.degree. with respect to the incident light beam), usually called forward or small-angle scattering, give information on cell size (Mullaney). Forward scattering also strongly depends on the difference of refraction between cells and the extracellular medium, so that cells with a damaged membranes, for example, can be distinguished. Light intensity measurements made at an angle of about 65.degree.-115.degree. from the incident light, usually referred to as orthogonal light scattering, and these provide information about the size and degree of structuredness of particles (Visser). As an example, the inventors and co-workers have recently shown that human cytotoxic lymphocytes appear to have different structural characteristics than regulatory and B-lymphocytes, based on the greater orthogonal light scattering intensities of the cytotoxic cells (Terstappen). If the width of the illumination beam is smaller than the diameter of the particles, the pulse shape of the light at orthogonal scattered angles yields information about the length and shape of the cells.
Simultaneous light scattering measurements at different angles or in combination with absorption or fluorescence measurements have been proposed in flow cytometry methods. Simultaneous measurement of forward and orthogonal light scattering can be used to discriminate cytotoxic lymphocytes from regulatory and B-lymphocytes as indicated above (Terstappen), and lymphocytes from other peripheral leukocyte cells (Hoffman). Absorption of light in combination with light scattering is used in flow cytometry to distinguish between erythrocytes and thrombocytes, and between lymphocytes, monocytes, basophilic granulocytes, eosinophilic granulocytes, and neutrophilic granulocytes (Technicon Hemalog or Hl systems). However, this method requires staining the cells, and is therefore rather complex and may preclude using the cells for further study after cell sorting.
Light scattering measurements combined with circular dichroism (CD) and optical rotatory dispersion (ORD) also have the potential for particle discrimination in suspensions of virus particles or cells. Studies of the effect of Mie (isotropic particle) scattering on the CD and ORD spectra of DNA in viral particles (Gordon, 1972; Gordon, 1974) suggest that scattering measurements can be used to correct ORD and CD measurements in larger biological structures, such as virus particles and cells, to allow particle discrimination on the basis of characteristic ORD and CD characteristics. Differential scattering of right and left circularly polarized light, for discrimination of a number of different microorganisms, has been demonstrated (Salzman). The circular intensity differential scattering (CIDS) method is like CD, which exploits the differential absorption of left and right circularly polarized light, but takes advantage of differential scattering by helical structures, such as DNA, of right and left circularly polarized light.


A barrier structure of a plasma display panel that can prevent an excessive increase of discharging current during a supply of discharging voltage and thereby avoid damages to electrodes caused by an excessive discharging current. A plasma display panel including both a first and second substrate, the second substrate spaced a distance from the first substrate. The plasma display panel also includes sustain electrodes arranged in parallel with one another on the first substrate; data electrodes arranged on the second substrate substantially perpendicular to the sustain electrodes; and a barrier on the first substrate and projected toward the second substrate, the barrier having at least one side contacting at least one sustain electrode.

A. Field of the Invention
The present invention relates to a barrier structure of a plasma display panel and, particularly, to a barrier structure formed on a substrate in order to define a space for discharges.
B. Discussion of Related Art
A typical color PDP (Plasma Display Panel), as shown in FIG. 1, has upper and lower structures. The upper structure, which is viewed the side for better understanding, consists of upper substrate 1, dielectric layer 5 for sustaining surface charges formed during a discharge of the sustain electrodes 3, a protection layer 6, and upper barriers 9. The lower structure consists of lower substrate 2, lower electrodes 4 formed on the lower substrate 2 perpendicular to the sustain electrodes 3, lower barriers 7 formed between the upper and lower substrates 1 and 2 in parallel with the lower electrodes 4, and phosphor 8 coated on the surface of the lower barriers 7.
The space between the upper and lower structures is sealed with inert gas contained therein, forming a discharging area.
Initially, when a high voltage is applied sufficient to cause discharges in all discharging cells on the panel between both ends of the sustain electrodes 3, the charges formed on the surfaces of the barriers 7 and 9 and the dielectric layer 5 are eliminated and charges are thereby distributed uniformly all over the discharging cells. As a result, the inner surface of the discharging area has no charge formation.
In the subsequent addressing step, cells to be discharged are supplied with an address voltage, causing a discharge between the lower electrodes 4 and the sustain electrodes 3 that are energized by a scan voltage, thus forming wall charges on the surface of the protection layer 6.
A sustain voltage is then applied between the sustain electrodes 3 during a sustain period so as to sustain the discharges in the cells having wall charges. Discharges cannot continue in the cells that have no wall charges formed thereon, when sustain voltage is supplied.
However, as shown in FIG. 2, a discharging voltage applied to both ends of transparent electrode lines a and a' out of sustain electrodes 3 causes a cooperative surface discharge in the discharging area. Bus electrode lines b and b' are formed on the transparent electrode lines a and a', respectively, to prevent a voltage drop that may be caused by the resistance of the transparent electrode lines a and a'. Unfortunately, an excessive discharging current generated at this stage can damage the electrodes.

Barrier structure of plasma display panel


A substrate made of glass serves both as a substrate for a touch panel and as that for a front light, and has both functions of propagating an ultrasonic wave in order to detect a touched position, and propagating light emitted from a light source to guide the light toward a reflective-type liquid crystal display. In the case where an image on the liquid crystal display is made visible by external light, external light which has been transmitted through the substrate is reflected by the liquid crystal display, and the reflected light is again transmitted through the substrate to be emitted from the front face. In the case where the front light function is used, light which has been introduced into the substrate from the light source is reflected by the liquid crystal display, and the reflected light is transmitted through the substrate to be emitted from the front face.

The present invention relates to a touch panel device which detects a position where an article such as a finger or a pen is touched, and more particularly to a touch panel device which integrally comprises a front light that is to be used for a reflective-type liquid crystal display.
As computer systems which are typically personal computers become widespread, touch panel devices are used. In a touch panel device, an area of a screen of liquid crystal display on which data are displayed by a computer system is pointed by an object such as a finger or a pen, thereby inputting new data or giving various kinds of instructions to the computer system.
Liquid crystal displays are roughly classified into transmissive-type ones and reflective-type ones. A transmissive-type liquid crystal display is configured so that an image is made visible by transmitted light from a light source (back light) which is placed in rear of a liquid crystal panel. A touch panel device having a transmissive-type liquid crystal display must use a back light, so that the power consumption is increased by the back light and the driving time by a battery power source is shortened. As a result, such a touch panel device is not suitable for a portable electronic apparatus such as a portable telephone or a PDA (Personal Digital Assistant).
In order to reduce the power consumption, therefore, a reflective-type liquid crystal display which does not require a back light is used. A reflective-type liquid crystal display is configured so that light entering through the front face of a liquid crystal panel is reflected by the back face of the liquid crystal panel and an image is made visible by the reflected light. A touch panel device having a reflective-type liquid crystal display is suitable for a portable electronic apparatus because the nonuse of a back light reduces the power consumption, and also because visibility under external light in an outdoor use is excellent.
Usually, such a touch panel device having a reflective-type liquid crystal display comprises a light source (front light) which illuminates the reflective-type liquid crystal display from the front face of the liquid crystal panel so that the device can be used even in the case where the amount of external light is insufficient, or during the night. Therefore, such a device can use both external light and light emitted from the front light.
FIG. 1 is a section view showing the configuration of a conventional touch panel device using an ultrasonic wave. The touch panel device is configured by a combination of a touch panel 51, a front light 52, and a reflective-type liquid crystal display 53. In the touch panel 51, a plurality of transmitter elements which transmit an ultrasonic wave, and a plurality of receiver elements which receive the ultrasonic wave are formed on a glass plate 51a, the ultrasonic wave is propagated through the glass plate 51a between the transmitter and receiver elements, and attenuation of the ultrasonic wave due to a touch of an object such as a finger or a pen with the glass plate is sensed to detect the position where the object is touched. The front light 52 is placed between the touch panel 51 and the liquid crystal display 53, and has: an elongated light source 52a which emits light; and a planar light guide 52b which converts the light from the light source 52a into planar light and emits the planar light.
FIG. 2 is a diagram showing optical paths in the conventional touch panel device. In the case where an image on the liquid crystal display 53 is made visible by external light, as indicated by the thick solid arrow in FIG. 2, external light which has been transmitted through the touch panel 51 (the glass plate 51a) and the front light 52 (the planar light guide 52b) is reflected by the liquid crystal display 53, and the reflected light is again transmitted through the front light 52 (the planar light guide 52b) and the touch panel 51 (the glass plate 51a) to be emitted from the front face (the upper face in FIG. 2). In the case where the front light 52 is used, as indicated by the thin solid arrow in FIG. 2, light which has been guided into the planar light guide 52b from the light source 52a is reflected by the liquid crystal display 53, and the reflected light is transmitted through the front light 52 (the planar light guide 52b) and the touch panel 51 (the glass plate 51a) to be emitted from the front face (the upper face in FIG. 2).
In these optical paths, there are four optical interfaces (the front face (the upper face in FIG. 2) and the back face (the lower face in FIG. 2) of the glass plate 51a, and the front face (the upper face in FIG. 2) and the back face (the lower face in FIG. 2) of the planar light guide 52b). Therefore, the incident light is reflected in the respective optical interfaces as indicated by the broken lines in FIG. 2. There is a problem that the reflected light indicated by the broken lines becomes noises and the amount of useful light is reduced and visibility is therefore impaired.
The above-mentioned problem occurs similarly in a conventional touch panel device using a resistance film.
Specifically, in the case where anti-reflection treatment (AR treatment) based on surface coating is not applied, the reflectance in each optical interface is about 4%, and, in the case where AR treatment is applied, the reflectance in each optical interface is about 1%. When external light is used, the light passes through the eight optical interfaces, and hence the amount of light is reduced by 28% in the case where AR treatment is not applied, and by 8% even in the case where AR treatment is applied, with the result that the display brightness is lowered. When the front light 52 is used, light passes through the four optical interfaces, and hence the display brightness is reduced by 15% in the case where AR treatment is not applied, and by 4% even in the case where AR treatment is applied.
As described above, a conventional touch panel device in which a touch panel, a front light, and a reflective-type liquid crystal display are combinedly used has a problem in that the display brightness is lowered by reflected light caused in the touch panel and the front light and hence visibility is low.


A multilayer substrate device formed from a base substrate and alternating metalization layers and dielectric layers. Each layer is formed without firing. Vias may extend through one of the dielectric layers such that two metalization layers surrounding the dielectric layers make. contact with each other. The vias may be formed by placing pillars on top of a metalization layer, forming a dielectric layer on top of the metalization layer and surrounding the pillars, and removing the pillars. Dielectric layers may be followed by other dielectric layers and metalization layers may be followed by other metalization layers. Vias in the substrate may be filled by forming an assembly around the substrate, the assembly including printing sheets containing a conductive ink and pressure plates for applying pressure. A vacuum may be applied to remove air in the ink. Pressure may then be applied to the printing sheets through the pressure plates. The conductive ink in the printing sheets is pushed through the vias when pressure is applied by the pressure plates.

1. Field of the Invention
The present invention relates to the field of semiconductor fabrication technology and, in particular, to the formation of substrates having multiple layers, i.e., the formation of multilayer substrates.
2. Description of Related Art
Multilayer substrates are becoming increasingly popular in the microelectronics arena for a variety of reasons. The high packing densities, accommodation of varied types of circuit elements and facilitation of complex circuitries afforded by multilayer substrates have generated an increased interest and use in these devices. As the requirements for increased packing densities, complex circuit functionality and other requirements necessitated by current market conditions proliferate, so too will the demand for multilayer substrates that enable such requirements.
A number of techniques currently exist for multilayer substrate fabrication. One method of fabricating multilayer substrates is to laminate single, unfired semiconductor tapes, commonly referred to in the industry as "green sheets" or "green tape." In a typical, conventional layered green sheet process, a multilayer substrate may be produced by a) printing a circuit pattern on a glass or ceramic green sheet; b) laminating several green sheets that have been printed; and c) firing or sintering the laminated green sheets in a reducing atmosphere. The resulting product is a laminated, multilayer substrate that may be used in a variety of applications.
Multilayer substrates formed from green sheets have a number of disadvantages. Although any number of green sheet layers may be laminated together, the overall height of the multilayer substrate is determined by the thickness of each individual green sheet used in the multilayer structure. Green sheet thickness is determined by the green sheet manufacturer, and, typically, the thickness of an individual green sheet is in the area of 6 mils to 30 mils. Most conventional multilayer substrate fabrication techniques cannot accommodate green sheets of less than 6 mil thickness because green sheets of these thicknesses tend to be too thin to be successfully fabricated into a multilayer substrate. Thus, where a multilayer substrate having thin layers is desired, green sheets are generally not feasible as an option.
Also, because the end user has no control over the thickness of each individual green sheet, the end user is forced to limit the number of layers of the multilayer substrate according to the maximum height allowable for the intended application of the multilayer substrate device. For applications requiring minimum substrate height, the number of green sheets available for lamination may be limited due to their predetermined thickness, thus limiting the complexity of the design. Accordingly, for small footprint devices that require complex designs, laminated green sheets may prove inadequate.
Another disadvantage of using laminated green sheets for multilayer substrate fabrication is that the green sheets must be sintered, or fired during the fabrication process. As is the case with many physical processes requiring the introduction of heat, firing the laminated green sheet, i.e., heating the green sheet, causes shrinkage in the various elements of the substrate, including the circuit traces printed on each laminate. Thus, the tolerances, dimensions and other parameters of the traces and other elements of the substrate are subject to variance. Moreover, the exact amount of shrinkage during firing may be difficult to control. For designs in which geometries are critical, requiring minimum variance in trace tolerances and high accuracy in trace dimensions or other substrate parameters, laminated green sheets may prove wholly inadequate. If a multilayer substrate is fabricated using green sheets in which each of the individual green sheets have thicknesses of varying heights, a technique which is common in the semiconductor industry, the effects of firing and shrinkage are even more pronounced and dramatic.
Another disadvantage of using laminated green sheets for multilayer substrate fabrication is that the dielectric used to form the green sheets is generally not of as high a quality as is required for some applications. Because multilayer substrates fabricated with green sheets are subjected to elevated temperatures during processing, the dielectrics used in green sheets must be able to tolerate elevated temperatures without compromise to the integrity of the dielectric. Accordingly, impure dielectrics, which typically show enhanced reliability at elevated temperatures, are used as the dielectric in green sheets. These impure dielectrics can be limiting when forming circuit elements, such as high voltage capacitors for example. Thus, in applications where pure dielectrics are required, the temperature processing required for multilayer substrates fabricated using green sheets generally precludes green sheets as an option for forming such substrates.
Another method of fabricating multilayer substrates is to use thick film processes. The thick film process is a sequential process requiring a) printing a circuit pattern on a substrate; b) drying the substrate; and c) firing the substrate. This process is repeated as many times as is necessary or desired in order to obtain the number of layers required. Each individual substrate is printed, dried and fired, then adhered to the other substrates which have been printed, dried and fired to form a substrate stack. In this way, a multilayer substrate is formed from individually prepared substrates.
However, multilayer substrates formed from thick film processes suffer from many of the same disadvantages as green sheet multilayer substrates. The thickness of a multilayer substrate formed using thick film processes is dictated by the thickness of each individual substrate. As is the case with green sheets, the ultimate height of the substrate is determined by the cumulative height of the substrates rather than the requirements of the application. Excessive cumulative substrate height may be an unacceptable design restriction and, thus, thick film processes may be inadequate for forming multilayer substrates in the intended application.
Because thick film processes require firing each substrate layer, multilayer substrates formed using thick film processes also suffer from shrinkage issues. Like green sheets, designs requiring minimum variance in substrate parameter tolerances and high accuracy in substrate parameter dimensions may not be adequately served by thick film multilayer substrate formation processes.
The filling of vias in the substrate is a normal part of the substrate fabrication process. Traditional via filling is usually accomplished using thick film printing techniques, where squeegee printing processes push conductive ink into the vias, or with vacuum techniques that effectively pull conductive ink through the vias.
When conductive ink is pulled through a via, much of the ink is lost due to waste. For small production runs, such waste may be of little concern. However, for large production runs, the cost attributed to wasted ink could ultimately exceed the cost of the substrate itself. Thus, for large production runs, filling substrate vias using vacuum techniques becomes cost prohibitive.
Although there is less waste in thick film techniques, traditional squeegee via filling techniques typically allow air to be trapped in the conductive ink, causing air voids to form within the interior of the via. Air voids are deleterious to the conductive path through the via, plaguing the via with a variety of performance detractors. Air voids can greatly reduce the electrical conductance through the path, increasing via resistance and generating excess heat in the via. To complicate matters, air voids can greatly reduce the thermal conductance through the path, providing even less of a mechanism by which to remove the excess heat resulting from the decrease in electrical conductance.
Of equal if not greater concern for practitioners involved with devices that are implanted into a human or animal body, air voids compromise the hermeticity of the conductive path through the via. Often, the conductive path through the via is the single path bodily fluids may take to reach sensitive microelectronics that could be damaged or destroyed by exposure to such fluids. If an implantable device is formed having vias that require hermetic sealing, any air voids within the via that compromise the hermeticity of the path and allow fluids to pass through the via could result in device malfunction or even device failure, which could have disastrous consequences for the user of the device.
Accordingly, there is a need in the semiconductor industry for multilayer substrates having layers which may vary widely in thickness and which may be accurately controlled. There is also a need in the semiconductor industry for multilayer substrates in which circuit element and trace tolerance is tightly controlled and line dimension shrinkage is minimized. There is yet another need in the semiconductor industry for multilayer substrates in which high purity dielectrics may be used.
In addition, there is a need in the semiconductor industry for methods and systems for filling vias in a substrate that do not waste conductive ink. There is yet another need in the semiconductor industry for methods and systems for filling vias in a substrate that eliminate air voids in the conductive path through the via.