A stereo 3D video frame includes left and right components that are combined to produce a stereo image. For a given amount of distortion, the left and right components may have different impacts on perceptual visual quality of the stereo image due to asymmetry in the distortion response of the human eye. A 3D video encoder adjusts an allocation of coding bits between left and right components of the 3D video based on a frame-level bit budget and a weighting between the left and right components. The video encoder may generate the bit allocation in the rho (ρ) domain. The weighted bit allocation may be derived based on a quality metric that indicates overall quality produced by the left and right components. The weighted bit allocation compensates for the asymmetric distortion response to reduce overall perceptual distortion in the stereo image and thereby enhance or maintain visual quality.

Digital video capabilities can be incorporated into a wide range of devices, including digital televisions, digital direct broadcast systems, wireless communication devices, personal digital assistants (PDAs), laptop computers, desktop computers, digital music and video players, handheld gaming devices, video game consoles, digital cameras, digital recording devices, cellular or satellite radio telephones, and the like. Digital video devices can provide significant improvements over conventional analog video systems in processing and transmitting video sequences with increased bandwidth efficiency.
Different video encoding standards have been established for encoding digital video sequences. The Moving Picture Experts Group (MPEG), for example, has developed a number of standards including MPEG-1, MPEG-2 and MPEG-4. Other examples include the International Telecommunication Union (ITU)-T H.263 standard, and the ITU-T H.264 standard and its counterpart, ISO/IEC MPEG-4, Part 10, i.e., Advanced Video Coding (AVC). These video encoding standards support improved transmission efficiency of video sequences by encoding data in a compressed manner. Application of video encoding standards to 3D video is desirable to support 3D viewing by users via a wired or wireless network with a finite bandwidth.
Video content may be recorded in a conventional, two-dimensional (2D) format or in three-dimensional (3D) format. 3D video content can be obtained and presented in different ways. As an example, 3D video content may be obtained by a stereoscopic dual camera and presented by left eye and right eye components. Alternatively, a conventional single camera may be used in conjunction with a depth camera to obtain both a cyclopean view and depth data. As another alternative, a single camera may be used to produce a cyclopean view that is processed to produce both a cyclopean view and depth data. Different 3D video sources may require different types of video output devices, such as a conventional 2D display, a stereoscopic display aided by special glasses, or an autostereoscopic display.


Serial suspended microchannel resonator sensor array. The array includes a plurality of resonator cantilevers in fluid communication with one another and a plurality of delay channels in fluid communication with, and disposed between, the resonator cantilevers. An object introduced into the array will flow in one direction and be measured by each of the cantilevers in turn after a selected delay in the delay channels.

This invention relates to suspended microchannel resonators and more particularly to an array of serially-arranged suspended microchannel resonators.
Suspended microchannel resonators are well-known for measuring properties such as the mass of objects that pass through the resonator. Suspended microchannel resonators are described in the references attached hereto. A suspended microchannel resonator is a fluidic device in which objects pass along a cantilever that is oscillating. As an object moves along the resonator, the resonant frequency changes, enabling the measurement of properties such as mass of the object.
Suspended microchannel resonators are often used to analyze cells. In particular, such resonators are often used to assess cellular growth rate. Prior art single suspended microchannel resonators have a limited throughput of a few cells per hour. Cell samples that are to be screened may contain up to 105 cells so that a single suspended microchannel resonator would be too slow to make a practical screening device.
It is therefore an object of the invention to provide a suspended microchannel resonator system capable of a throughput of up to 104 cells per hour.

Serial arrays of suspended microchannel resonators


The present invention provides an integrated circuit test device and method which creates a pattern for minimizing a difference from a pattern generated by a pattern generation device. In the invention, a list of all failures assumed to be in the circuit is created, and, for example, a random number pattern is inputted so that a signal value in the circuit is defined by a logic simulation using the inputted pattern, as a result of which the controllability, observability and testability are calculated. A target failure minimizing the testability is selected from the list, for which target failure path-sensitization is performed using the controllability and observability of the input pattern, which pattern is corrected so as to minimize the number of inversions of signal values of the input pattern. A failure simulation for the target failure is also performed using the corrected pattern, and when a failure to be detected further exists, the failure is removed from the failure list.

1. Field of the Invention
The present invention relates to a device and method for testing an integrated circuit device, for detecting production failure of an integrated circuit (LSI).
2. Description of the Related Art
Detection of production failure of an integrated circuit (LSI) is performed such that a suitable signal value is applied to an input pin of the LSI by using a tester (ATE), and a signal value appearing at an output pin is compared with an expected result. A combination of the signal value of an input pin and the expected value of an output pin is referred to as a test pattern. A defect caused in a LSI by a production failure of the LSI is referred to as a fault, and in order to perform verification on all faults that may be caused in a LSI, a large number of test patterns are required. In addition, a ratio of faults which can be verified to faults which can be assumed to be in the LSI by a test pattern is referred to as a diagnosis rate (or detection rate), which is used as a measure when the quality of the test pattern is evaluated.
The method for creating a test pattern includes the following:                Random Test Generation (RTG)        Manual Test Generation        Automatic Test Pattern Generation (ATPG)
Although the above described methods are combined to be used as required, the ATPG is used widely in order to obtain a high diagnosis rate. There are several methods in the ATPG, but those belonging to a path-sensitization algorithm are currently prevailing methods.
The path-sensitization algorithm consists of two fundamental steps of fault excitation and fault-effect propagation, for detecting a fault.
In the fault excitation, a value opposite to a fault value is set at a failure-assumed point. This makes a state value in a fault point different between a case where a fault is present and a normal case. This state is referred to that a failure is excited.
In addition, the fault-effect propagation is to propagate the effect of an excited failure to an observation point (external output). This makes all signal values on a path from a fault point to an observation point different between a normal time and a failure time. The path is referred to as a sensitized path. An example of the sensitized path is shown in FIG. 10. A thick solid line shows the sensitized path in a circuit shown in FIG. 10. The sensitized path also shows that a signal value for fault-excitation is set on a signal line a, and a signal value for fault-effect propagation is set on a signal line c and a signal line d.
In order to realize the fault excitation and the fault-effect propagation, it is necessary to set a desired signal value on a specified signal line. A signal line value in a circuit will be eventually resulted in a signal value of an external input which is a control point of a LSI. That is, in order to detect a fault, the ATPG creates a test pattern which consists of signal values of an external input for forming a sensitized path of the fault and expected values (signal values expected at a normal time) of an output to which the effect of the fault is propagated.
Several selections may take place in a process in which the ATPG creates a test pattern. For example, when a fault is excited by setting the output of a two-input AND gate to 0, either of the two inputs may be 0, so that either of the two inputs needs to be selected as the input to be set to 0. Also, in the case where there is a branch point of a signal line in the course of failure propagation, either one of the paths may be sensitized, so that a selection is also required in this case.
In a common ATPG, when several options exist, it is necessary to select one of them for the time being to advance processing. However, when the selection results in generation of a discrepancy in setting signal values or in a failure to sensitize the path, it is necessary to return to the processing of one previous step where the selection was performed and to select another option so as to advance processing. This is referred to as back-tracking.
In the case where a LSI includes a sequential circuit elements (flip-flop (F/F), latch and RAM), the complexity of the test pattern creation is drastically increased. Accordingly, there is performed a scan designing, in which a shift register (referred to as scan path) is formed by sequential circuit elements mainly comprising F/Fs in the LSI, so as to make a desired value shifted in at the time of test and values of the shift register read out to the outside after clock application. A technique referred to as the Deterministic Stored Pattern Test (DSPT), which is performed by storing in a tester a test pattern created by the ATPG, is widely employed for a circuit designed with the scan designing. FIG. 11 is a conceptual diagram of the DSPT. In the DSPT, a test pattern TP1 is shifted in a scan path SP provided in the LSI, so that a test pattern TP2 is shifted out.
However, since sequential circuit elements included in a LSI has recently increased drastically with high integration of the LSI, the DSPT which repeats the setting and reading operations for every test pattern for all sequential circuit elements constituting a scan path, causes to increase test time and data, so as to be difficult to be applied. Especially the shortage of memory capacity of a tester due to the increase in the amount of test data results in a memory expansion and an upgrade of the tester, thereby substantially increasing test costs.
In order to solve the problem, a Built-In Self Test (BIST) has come to be applied. FIG. 12 is a conceptual diagram of the BIST. In the BIST, a random pattern generated in a pseudo random number pattern generator 91 is applied to an internal circuit 90 of a LSI, and the output result is verified and stored in an output verification device 92. A linear feedback shift register (LFSR) is used, in many cases, for the pseudo random number pattern generator 91 and the output verification device 92, and the latter is in particular referred to as a multi-input signature register (MISR) as it compresses and stores the output result as a signature.
In the BIST, in which a pattern generator is installed in a LSI so that an input test pattern need not be stored in an external tester, and in which the test result is compressed by the MISR, the amount of data to be loaded in the tester can be drastically reduced. In the BIST, the number of scan paths is increased to enable the operation speed of shifting in and shifting out of a scan path to be increased, thereby reducing the test time.
Although the BIST is capable of improving the above described problem of the DSPT, it also has several disadvantages. In the BIST, since a pseudo random number pattern is used, a problem is involved in the test quality (diagnosis rate). In order to enhance the diagnosis rate, it is necessary to apply the DSPT as an additional test or to insert test points in the circuit inside the LSI so as to increase the controllability and observability.
Also, since the BIST is constructed such that output data are compressed and stored in the MIST, when an indeterminate state (X value) is taken in the MISR, the indeterminate value destroys the values in the MISR, thereby making it impossible to test. Generally, since sequential circuit elements including RAM in a LSI are in an indeterminate state when the power supply is turned on, it is necessary to initialize the sequential circuit elements or to devise a circuit for preventing the indeterminate state from being propagated to the MISR.
Further, it is necessary to devise in designing a bus to prevent a random pattern from causing a conflict and floating in the bus, which forces a strict design limitation on a designer when the BIST is applied to an actual circuit. In addition, a problem is also caused by an area overhead and performance degradation, which result from additional circuits and test points inserted for use in the BIST.
In order to solve the above described problems of the DSPT and BIST, a related test device and method are proposed in Japanese Patent Application Serial No. H12-372231, "Device and Method for Testing Integrated Circuit", which enables a test time and the amount of test data to be reduced and the high quality of test to be attained.
FIG. 13 shows a block diagram of a circuit of a test device disclosed in the above described patent application. In the related art disclosed in the patent application, which is based on the BIST circuit, a pattern created by a pseudo random number pattern generator (LFSR) 93 is corrected by a pattern correction device 94 to be a pattern equivalent to that created by the ATPG, so as to be shifted in a scan path. After application of a test clock, the scan path output, of which indeterminate state values are subjected to mask-processing in an indeterminate state masking device 95, is compressed and stored in the MISR in an output verification device 96.
In general, the number of patterns created by the ATPG, values of which patterns are explicitly set to F/Fs, is very small compared with the total number of F/Fs (several %). In the technique disclosed in the above described patent application, only the values explicitly set to the F/Fs are provided for an external tester through a control signal 97, so as to enable a pseudo random number pattern to be corrected to be a high quality pattern equivalent to that created by the ATPG through the pattern correction device 94. Also, indeterminate state values which causes a design limitation in the BIST are blocked by the indeterminate state masking device 95 from being taken in the MISR, thereby substantially reducing a burden on a designer.
Thus, in the technique disclosed by the patent application, any test pattern generated by any kind of ATPG can be utilized. However, in order to substantially reduce test costs, such as the amount of test data and test time, the difference between a random pattern generated by the LFSR 93 provided inside the circuit and a pattern generated by the ATPG needs to be small.
Here, the ATPG determines values of several F/Fs necessary for several target failures and a number of remaining F/Fs are set to values created by the LFSR 93 provided in the circuit. This enables the difference between a random pattern and a test pattern to be made small. However, in the case where there are a number of target failures, or where sensitization is complicated, the number of F/Fs which need to be set by the ATPG is increased, as a result of which the test cost reduction rate is lowered.
In the related art disclosed in the above described patent application, F/F values set by the ATPG have no relation to F/F values set by the LFSR. F/F values set by the ATPG may be identical with half of F/F values set by the LFSR, but on the average, in the half of F/Fs set by the ATPG, additional patterns are created by the tester, which lowers the test cost reduction rate.
Accordingly it is an object of the present invention is to provide a test device and method for performing a test pattern creation so as to make the difference from a random number pattern generated by a pseudo random number pattern generator as small as possible, thereby increasing the test cost reduction rate.

Device and method for testing integrated circuit


A phased array antenna comprising: a substrate; a plurality of circular polarized wideband antenna elements disposed on the substrate, wherein each element comprises two orthogonal feeds; wherein the plurality of elements are organized into subarrays and physically oriented such that constituent elements of each subarray are sequentially rotated with respect to each other about respective axes that are perpendicular to a surface of the substrate so as to allow RHCP and LHCP transmission and reception; a phase shifter communicatively coupled to the feeds of all the elements and configured to electronically any dynamically compensate for phase regression or progression introduced by the sequential rotation of the elements without relying on physical transmission lines of different dimensions, and further configured to introduce a progressive phase shift across a beam steering plane to enable beam steering of the phased array antenna.

All satellite communications in the microwave and millimeter-wave frequency bands require circular polarization for communications. Circular polarization is more resilient to scintillation through the atmosphere. There are two types of circular polarization, right hand circular (RHCP), and left hand circular (LHCP). For satellite communications, typically one is chosen for transmit and one is chosen for receive. The frequencies for transmit and receive could be the same, whereby time division duplexing is used, or they could be separate frequencies that are close in proximity, this is known as frequency division duplexing.
Phased array antennas are a class of antennas where the beam can be electronically steered. This is desirable especially as more constellations are deployed in LEO orbit. In LEO orbit, satellites can move overhead every 3-10 minutes, and so the ground antenna needs to constantly be changing its pointing angle. Also, in order to allow for smooth hand-over, the antenna must be able to slew quickly in order to not lose link. Previously, this was done with a two-antenna solution, where each antenna is mechanically steered because the antennas were not fast enough such that a single antenna can support the hand-over.
Generating circular polarization in antenna arrays is widely known, especially for microstrip type antennas. The main challenge for planar microstrip type antennas are (1) obtaining a wide impedance bandwidth (2) obtaining a wide axial bandwidth to preserve circular polarization, and (3) retaining good axial ratio across wide beam angles. Circular polarization can be obtained by exciting orthogonal modes and then recombining. Axial ratio is defined as the ratio between two perpendicular linear polarized signals. Typically, when the ratio is less than 3 dB, we consider the antenna to be circularly polarized. Zero dB would be ideal case, but in real life, asymmetries in the design, etc. limit how low this ratio can go. The Axial Bandwidth is then defined as the bandwidth for which the axial ratio is less than 3 dB. In typical microstrip antennas, the axial ratio bandwidth is very low. There is a need for an improved phased array antenna.

Circular polarized phased array with wideband axial ratio bandwidth using sequential rotation and dynamic phase recovery

United States of America as represented by the Secretary of the Navy


A method for motion correction using coil arrays, termed “MOCCA,” is provided, in which coil-dependent motion-related signal variations are employed to determine information related to motion in two and three directions. With such a method, navigator echoes are not required, nor is the acquisition of additional data required to resolve complex motions in more than one direction. The motion estimation and compensation method provided by MOCCA is also applicable to applications of cardiac, respiratory, and other physiological self-gating techniques.

The field of the invention is systems and methods for magnetic resonance imaging ("MRI"). More particularly, the invention relates to systems and methods for motion correction in MRI.
When a substance such as human tissue is subjected to a uniform magnetic field (polarizing field B0), the individual magnetic moments of the nuclei in the tissue attempt to align with this polarizing field, but precess about it in random order at their characteristic Larmor frequency. If the substance, or tissue, is subjected to a magnetic field (excitation field B1) that is in the x-y plane and that is near the Larmor frequency, the net aligned moment, Mz, may be rotated, or "tipped," into the x-y plane to produce a net transverse magnetic moment Mxy. A signal is emitted by the excited nuclei or "spins," after the excitation signal B1 is terminated, and this signal may be received and processed to form an image.
When utilizing these "MR" signals to produce images, magnetic field gradients (Gx, Gy, and Gz) are employed. Typically, the region to be imaged is scanned by a sequence of measurement cycles in which these gradients vary according to the particular localization method being used. The resulting set of received MR signals are digitized and processed to reconstruct the image using one of many well known reconstruction techniques.
The measurement cycle used to acquire each MR signal is performed under the direction of a pulse sequence produced by a pulse sequencer. Clinically available MRI systems store a library of such pulse sequences that can be prescribed to meet the needs of many different clinical applications. Research MRI systems include a library of clinically-proven pulse sequences and they also enable the development of new pulse sequences.
The MR signals acquired with an MRI system are signal samples of the subject of the examination in Fourier space, or what is often referred to in the art as "k-space." Each MR measurement cycle, or pulse sequence, typically samples a portion of k-space along a sampling trajectory characteristic of that pulse sequence. Most pulse sequences sample k-space in a raster scan-like pattern sometimes referred to as a "spin-warp," a "Fourier," a "rectilinear," or a "Cartesian" scan. The spin-warp scan technique employs a variable amplitude phase encoding magnetic field gradient pulse prior to the acquisition of MR spin-echo signals to phase encode spatial information in the direction of this gradient. In a two-dimensional implementation ("2DFT"), for example, spatial information is encoded in one direction by applying a phase encoding gradient, Gy, along that direction, and then a spin-echo signal is acquired in the presence of a readout magnetic field gradient, Gx, in a direction orthogonal to the phase encoding direction. The readout gradient present during the spin-echo acquisition encodes spatial information in the orthogonal direction. In a typical 2DFT pulse sequence, the magnitude of the phase encoding gradient pulse, Gy, is incremented, ΔGy, in the sequence of measurement cycles, or "views" that are acquired during the scan to produce a set of k-space MR data from which an entire image can be reconstructed.
There are many other k-space sampling patterns used by MRI systems. These include "radial," or "projection reconstruction" scans in which k-space is sampled as a set of radial sampling trajectories extending from the center of k-space. The pulse sequences for a radial scan are characterized by the lack of a phase encoding gradient and the presence of a readout gradient that changes direction from one pulse sequence view to the next. There are also many k-space sampling methods that are closely related to the radial scan and that sample along a curved k-space sampling trajectory rather than the straight line radial trajectory.
An image is reconstructed from the acquired k-space data by transforming the k-space data set to an image space data set. There are many different methods for performing this task and the method used is often determined by the technique used to acquire the k-space data. With a Cartesian grid of k-space data that results from a 2D or 3D spin-warp acquisition, for example, the most common reconstruction method used is an inverse Fourier transformation ("2DFT" or "3DFT") along each of the 2 or 3 axes of the data set. With a radial k-space data set and its variations, the most common reconstruction method includes "regridding" the k-space samples to create a Cartesian grid of k-space samples and then performing a 2DFT or 3DFT on the regridded k-space data set. In the alternative, a radial k-space data set can also be transformed to Radon space by performing a 1DFT of each radial projection view and then transforming the Radon space data set to image space by performing a filtered backprojection.
Depending on the technique used, many MR scans currently used to produce medical images require many minutes to acquire the necessary data. The reduction of this scan time is an important consideration, since reduced scan time increases patient throughout, improves patient comfort, and improves image quality by reducing motion artifacts. Many different strategies have been developed to shorten the scan time.
One such strategy is referred to generally as "parallel imaging." Parallel imaging techniques use spatial information from arrays of radio frequency ("RF") receiver coils to substitute for the encoding that would otherwise have to be obtained in a sequential fashion using RF pulses and field gradient, such as, for example, phase and frequency encoding. Each of the spatially independent receiver coils of the array carries certain spatial information and has a different sensitivity profile. This information is utilized in order to achieve a complete location encoding of the received MR signals by a combination of the simultaneously acquired data received from the separate coils. Specifically, parallel imaging techniques undersample k-space by reducing the number of acquired phase-encoded k-space sampling lines while keeping the maximal extent covered in k-space fixed. The combination of the separate MR signals produced by the separate receiver coils enables a reduction of the acquisition time required for an image, in comparison to conventional k-space data acquisition, by a factor that, in the most favorable case, equals the number of the receiver coils. Thus the use of multiple receiver coils acts to multiply imaging speed, without increasing gradient switching rates or RF power.
Because it requires time to acquire a complete k-space MR data set, subject motion presents a problem in many clinical applications. Motion due to respiration, cardiac motion, or peristalsis can produce image artifacts such as blurring or ghosting. There are many strategies used to suppress such artifacts. These include cardiac or respiratory gating techniques that acquire MR data only during certain phases of the cardiac or respiratory cycle. The subject is thus scanned while in a particular position, but the overall scan time is increased substantially because MR data is not acquired over substantial portions of each motion cycle.
Another technique for dealing with subject motion is to interleave so-called "navigator" pulse sequences into the scan to measure subject motion. Navigator pulse sequences may be used during a scan to periodically acquire subject motion information with which the acquired k-space MR image data may be retrospectively corrected. Such navigator data may also be used to alter scanner operation to prospectively correct for subject motion. In either case, the interleaved navigator pulse sequences can add considerable scan time and in some cases they can disrupt the magnetization equilibrium required by imaging pulse sequences.
Two types of subject motion commonly exist when imaging a subject with MRI. These include rigid motion, including bulk translation and rotation; and non-rigid motion, including cardiac and respiratory motion. Numerous motion compensation methods have been proposed to address these sources of subject motion, including navigator echo methods; radial self-navigation methods; PROPELLER methods, such as those described by J. Pipe in "Motion Correction with PROPELLER MRI: Application to Head Motion and Freebreathing Cardiac Imaging," Magnetic Resonance in Medicine, 1999; 42(5):963-969; general matrix inversion methods, such as those described by P. G. Batchelor, et al., in "Matrix Description of General Motion Correction Applied to Multishot Images," Magnetic Resonance in Medicine, 2005; 54(5):1273-1280; and projection-based self-gating methods, such as those described by P. Lai, et al., in "A Respiratory Self-Gating Technique with 3D-Translation Compensation for Free-Breathing Whole-Heart Coronary MRA," Magnetic Resonance in Medicine, 2009; 62(3):731-738.
The use of multi-coil arrays to accelerate image acquisition using parallel imaging presents the opportunity to use the redundant information provided by coil arrays for motion estimation and correction. For example, it has been shown that a generalized SMASH technique can be employed to predict a k-space line using previously acquired adjacent lines, as described by M. Bydder, et al., in "SMASH Navigators," Magnetic Resonance in Medicine, 2003; 49(3):493-500. In this method, the predicted k-space line is compared with the actual acquired k-space line and the difference is used to correct for two-dimensional translations. However, this method does not correct for common imaging scenario where the body and coil array have relative motion, such as, in brain imaging applications using a rigid brain coil or in cardiac imaging applications with static posterior coil elements.
In another method, such as the one described by R. Bammer, et al., in "Augmented Generalized SENSE Reconstruction to Correct for Rigid Body Motion," Magnetic Resonance in Medicine, 2007; 57(1):90-102, the bulk motion parameters (translation and rotation) were integrated into an iterative SENSE method, such as the one described by K. P. Pruessmann, et al., in "Advances in Sensitivity Encoding with Arbitrary k-Space Trajectories," Magnetic Resonance in Medicine, 2001; 46(4):638-651, in order to correct for motion effects. In this method, the motion parameters are estimated from separately acquired, low-resolution navigator images using a similarity measure. For the most commonly used Cartesian sampling, the time required to acquire the navigator images is likely prohibitively long because they need to be acquired for every imaging shot.
In yet another method, such as the one described by D. Atkinson, et al., in "Coil-Based Artifact Reduction," Magnetic Resonance in Medicine, 2004; 52(4):825-830, a separate uniform image for each coil is estimated using a generalized SMASH method that integrates motion parameters into the reconstruction and compares them with ones estimated from all the coils. In this method, the motion parameters that minimize the differences are chosen as the estimated motion.
For cardiac and respiratory motion, accurately resolving the amount of motion is more difficult because these types of motion are typically non-rigid. Currently, the method most widely recognized as being successful for cardiac motion compensation is electrocardiogram ("ECG") gating. In addition, navigator-based methods have been successful for respiratory motion compensation in cardiac imaging applications. Recently, various cardiac and respiratory self-gating methods have been developed to remove the need for ECG signals, breath-holding, or navigator echoes. In one such method, such as the one described by T. A. Spraggins in "Wireless Retrospective Gating: Application to Cine Cardiac Imaging," Magnetic Resonance Imaging, 1990; 8(6):675-681, a surrogate ECG signal is derived by monitoring the k-space center peak signal. This concept was extended in a radial imaging cardiac self-gating method, such as the one described by A. C. Larson, et al., in "Self-Gated Cardiac Cine MRI," Magnetic Resonance in Medicine, 2004; 51(1):93-102, in which k-space peak magnitude, center of mass ("COM"), and a series of low-resolution navigator images are utilized to estimate motion. Similar methods with radial sampling have also been applied to respiratory self-gating, such as the one described by P. Lai, et al., in "A Dual-Projection Respiratory Self-Gating Technique for Whole-Heart Coronary MRA," Journal of Magnetic Resonance Imaging, 2008; 28(3):612-620. Such self-gating methods use the signal from a single coil or combine multiple coil signals into a single composite signal.
With multiple receiver coil arrays commonly used in parallel imaging, each coil has localized sensitivity profiles. Thus, motion of the object relative to the coils causes variations in the received signal. The amount and polarity of these variations are different among the coils depending on the geometric configuration of each coil.
It would therefore be advantageous to provide a method for motion estimation and compensation that does not require the acquisition of time-intensive navigators and in which three-dimensional motion can be resolved without the acquisition of significant additional image data.

Method for motion correction in magnetic resonance imaging using radio frequency coil arrays

Beth Israel Deaconess Medical Center, Inc.


The invention provides for a system, method, and computer readable medium storing instructions related to controlling a presentation in a multimodal system. The method embodiment of the invention is a method for the retrieval of information on the basis of its content for incorporation into an electronic presentation. The method comprises receiving from a user a content-based request for at least one segment from a first plurality of segments within a media presentation preprocessed to enable natural language content searchability; in response to the request, presenting a subset of the first plurality of segments to the user; receiving a selection indication from the user associated with at least one segment of the subset of the first plurality of segments and adding the selected at least one segment to a deck for use in a presentation.

1. Field of the Invention
The present invention relates to media presentations and more specifically to a system and method of creating a presentation using natural language.
2. Introduction
In the workplace and classroom, a common task is the preparation of a sequence of media segments such as slides to an audience as part of a formal presentation. Microsoft's PowerPoint® software provides an example of an application that enables users to prepare a presentation of visual images stepping from one slide to another. Such applications provide users with an opportunity to teach, sell, give briefings and so forth with more substance and power than merely by speaking.
Use of such presentation software over time results in a collection of old presentations, each comprising a plurality of segments. While old presentations are not often used in their entirety in the future, individual segments pulled from old presentations are useful in composing new presentations. The problem with the current technology is that users have to sort through existing sources of content manually, often one-by-one, in order to find the slides or other segments they need.
Furthermore, in many cases where a user is working to create a presentation, various images, pictures, text, and other information needs to be researched in order to prepare the presentation. This can be a time-consuming process in that the specific information desired by the user may not be readily available.
What is needed in the art is an improved method and system for retrieving electronic presentation segments from existing sources to be used in composing a new presentation.

This patent is subject to a terminal disclaimer.

System and method for creating a presentation using natural language


Compound semiconductor light emitting devices capable of suppressing the surface state density on the facets of semiconductor light emitting devices such as semiconductor lasers for a long time and stable operating even when the passivation layer diffuses can be easily obtained. Compound semiconductor light emitting devices with an emission wavelength of xcex (nm) wherein a first conduction type of clad layer, an active layer and a second conduction type of clad layer are grown on a substrate and two facets are opposite to each other so as to form a cavity, characterized in that said active layer is transparent to the emission wavelength in the vicinities of the facets and that the surfaces of the first conduction type of clad layer, active layer and second conduction type of clad layer forming said facets are each coated with a passivation layer.

1. Field of the Invention
This invention relates to semiconductor light emitting device and a method of fabricating the same, in particular, a process for producing semiconductor lasers. The device and the process according to the present invention are usable appropriately in semiconductor lasers which should have high light output power and high reliability, for example, excitation light sources for optical fiber amplifier and light sources for optical data storage system. Moreover, the device and the process of the present invention are applicable to LED of super-luminescent diodes, etc. wherein the facet of the light emitting device serves the light emission vertical cavity surface emitting lasers, etc.
2. Description of the Related Art
In recent years, optical data processing technology and optical communication technology have achieved brilliant extraordinary results exemplified by high-density recording with the use of optical magnetic discs and two way communication with optical fiber networks.
In the communication technology, for example, studies have been energetically made in various fields to develop large-capacity optical fiber transmitters usable in the coming multimedia age as well as Er3+-doped optical fiber amplifiers (EDFA) as signal amplifiers flexibly applicable to these transmission systems. Under these circumstances, it has been required to develop semiconductor lasers with high output power and high reliability which are essentially required as a component of EDFA.
The emission wavelengths usable in EDFA theoretically include the following three wavelengths, i.e., 800 nm, 980 nm and 1480 nm. By taking the characteristics of amplifiers into consideration, it is known that excitation at 980 nm, among all, is most desirable from the viewpoints of amplifier efficiency, noise figure, etc. It is needed that lasers with the emission wavelength of 980 nm have two contrary characteristics of high output and high reliability. Moreover, there are demands for lasers with wavelength in the vicinities thereof (for example, 890-1150 nm) as light source of secondary harmonic generation (SHG) and a source of thermal laser printers. In addition thereto, it has been urgently required to develop highly reliable lasers with high output in various fields.
In the field of data processing, attempts have been made to increase the output and shorten the wavelength of semiconductor lasers to achieve high-density recording and rapid writing and reading. That is to say, it has been strongly required to increase the output of laser diodes (hereinafter referred to simply as LDs) with the conventional emission wavelength of 780 nm and studies have been energetically made to develop LDs of 630 to 680 nm.
To achieve both of high output and high reliability which are essentially required in these lasers, there have been proposed a number of methods, for example, one comprising making the band gap in the active layer region around the facets so as to suppress the light absorption in the vicinities of the facets. Lasers with these structures, which are generally called window-structure lasers or non absorbing mirror (NAM)-structure lasers, are highly effective in establishing high output laser diodes.
On the other hand, JP-A-3-101183 (the term xe2x80x9cJP-Axe2x80x9d as used herein means an xe2x80x9cunexamined published Japanese patent applicationsxe2x80x9d) proposes another method for solving the above problem. According to this patent, it is effective to form a contamination-free facet and then form a passivation layer or a part of the same with the use of a material which undergoes neither any reaction with the semiconductor facet nor diffusion per se and contains no oxygen.
As known reference similar to the above patent JP-A-3-101183, citation may be made of L. W. Tu et al., In-vacuum cleaving and coating of semiconductor laser facets using Si and a dielectric, J. Appl. Phys. 80 (11) Dec. 1, 1996. According to this paper, when cleavage is performed in vacuum in the step of coating laser facets with an Si/AlOx structure, the carrier recombination in the cleaved facet is retarded and thus the initial catastrophic optical damage (COD) level is increased.
Further, there has been known a technique for inserting an Si layer having an optical thickness corresponding to xc2xc of the emission wavelength between a coating film and each semiconductor layer so as to displace the facets from the anti-node of the standing wave in the direction of the cavity, thus lowering the electric field strength at the beam emission facet.
For example, there have been already developed semiconductor lasers of 980 nm or therearound and withstanding continuous use for about 2 years at light output of 50 to 100 mW and a process for producing the same. When operated at higher light outputs, however, these lasers are rapidly degraded, thus showing poor reliability. The same applies to LDs of 780 nm or 630-680 nm. Thus, it is the problem which now confronts all semiconductor lasers, in particular, those with the use of GaAs substrates to ensure a high reliability at higher output.
One of the reasons therefor resides in the degradation of the diode facet exposed to extremely high light output density. As well known regarding GaAs/AlGaAs semiconductor lasers, there are a number of surface states (gap state) in the vicinities of facet. Since these states absorb the output light, the temperature in the vicinities of the facets is generally higher than the temperature at bulk of the laser. This increase in temperature further narrows the band gap in the vicinities of the facets and then the output light can be more easily absorbed, thus causing a positive feedback. This phenomenon is known as so-called COD observed when a large current is injected instantly. On the other hand, there arises a problem, in common to a number of semiconductor laser elements, of the sudden failure associating a decrease in the COD level after long time driving. Although attempts have been vigorously made to solve these problems as described above, the technical level at the present stage is insufficient.
An LD with the window-structure can be produced by, for example, epitaxially growing a semiconductor material transparent to the emission wavelength on the laser facets. In this method, the epitaxial growth is performed on the facets while making the laser in the so-called bar state, which makes the subsequent electrode step highly troublesome.
Furthermore, there are various methods which comprise intentionally thermal-diffusing or ion-implanting Zn, Si, etc. as impurities into an active layer in the vicinities of laser facets so as to disorder the above-mentioned active layer, as proposed by JP-A-2-45992, JP-A-3-31083 and JP-A-6-302906.
During the production of an LD, impurities generally diffuse in the epitaxial growth direction of the laser element toward the substrate. Accordingly, there arise problems in controlling the diffusion depth and controlling the horizontal diffusion to the cavity direction, which makes stable production difficult.
When ion-implantation is carried out, ions with high energy are introduced from the facets. As a result, damages frequently remain on the LD facets even after annealing. Moreover, there arise another problem that an increase in the reactive current accompanying the decrease in the resistance in the region into which impurities have been introduced would increase the threshold current and driving current.
On the other hand, the process disclosed in JP-A-3-101183 as cited above, which comprises forming a contamination-free facet and then forming a passivation layer or a part of the same with the use of a material which undergoes neither any reaction with the semiconductor facet nor diffusion per se and contains no oxygen, suffers from technical problems as will be described below.
It is generally impossible to prevent the formation of non-radiative recombination centers such as Gaxe2x80x94O and Asxe2x80x94O on the facet at cleavage by performing the operation in the atmosphere in, for example, a clean room. From this point of view, it is essentially required to form a passivation layer in situ at the point of cleaving for the xe2x80x9cmethod of forming a contamination-free facetxe2x80x9d as disclosed in Claim 1 in the gazette of this patent. To embody this method in practice, the cleavage should be carried out in vacuum as stated in Claim 10 in the gazette. For an effect cleavage in vacuum, an extremely complicated procedure and troublesome labor are required in general, compared with the case where cleavage is effected in the atmosphere. Many non-reactive recombinatiori centers are formed on facets formed by dry-etching as stated in Claims 11 to 14 in the gazette, compared with facets formed by cleavage. Thus, this dry etching procedure is unsuitable for the production of LDs which should have high reliability.
The optimum examples of the passivation layer are Si (single crystal or polycrystal Si) and amorphous Si. However, there is no substance never undergoing diffusion in general. In semiconductor lasers which are to be operated at high output and high temperature for a long time, in particular, it is feared that the passivation materials disclosed in the above patent might diffuse.
Although it is described in L. W. Tu et al., In-vacuum cleavage and coating of semiconductor laser facets using Si and a dielectric, J. Appl. Phys. 80 (11) Dec. 1, 1996 as cited above that when an Si/AlOx structure is cleaved in vacuum in the step of coating onto a laser facet, the carrier recombination on the cleaved facet is retarded and thus the initial COD level is increased. However, this reference refers to neither reliability over a long time nor the relationship between coating and the LD structure.
Further, there has been known a technique for inserting an Si layer having an optical thickness corresponding to xc2xc of the emission wavelength of between a coating film and each semiconductor layer so as to displace the facets from the anti-node of the standing wave in the direction of the cavity, thus lowering the electric field strength at the beam emission facet. However, this technique suffers from a fear that Si per se would serve as a light absorption in the emission wavelength region embodied by usual semiconductor lasers, in particular within the range of from 400 to 1600 nm needed for high-output LDs and thus there is a possibility that the degradation of devices might be accelerated by an increase in temperature on facets.
An object of the present invention, which has been completed to solve the above problems, is to provide semiconductor lasers capable of suppressing the surface state density on the facets of semiconductor light emitting devices such as semiconductor lasers for a long time and stable operating even when the passivation layer diffuses, and a process for conveniently producing the same. In other words, the present invention provides high-performance semiconductor lasers establishing both of high output and high reliability by preventing degradation on facets.
The present inventors have found out that semiconductor light emitting devices having compound semiconductor layers containing at least a first conduction type of clad layer, an active layer transparent to the emission wavelength in the vicinities of the facets and a second conduction type of clad layer formed on a substrate and having cavity facets coated with passivation layers are much superior in high output and high reliability to the conventional ones, thus completing the present invention.
Accordingly, the gist of the present invention resides in a compound semiconductor liglit emitting device having a compound semiconductor layer containing at least a first conduction type of clad layer, an active layer and a second conduction type of clad layer formed on a substrate and have a cavity facets, characterized in that the active layer is transparent to the emission wavelength in the vicinities of the facets, preferably free from oxide, and that the facets are coated with a passivation layer.
The present inventors have also found out that semiconductor light emitting devices having a p-type active layer preferably containing In and having a cavity facet coated with a passivation layer containing Si, more preferably having disordered cavity facet free from oxide are much superior in high output and high reliability.
Accordingly, the gist of the present invention resides in compound semiconductor light emitting devices wherein a first conduction type of clad layer, an active layer and a second conduction type of clad layer are grown on a substrate and two facets opposite to each other form a cavity, characterized in that said conduction type of active layer is P and that the surfaces of the first conduction type of clad layer, active layer and second conduction type of clad layer forming said facets are each coated with a passivation layer containing Si.
The present inventors have further conducted extensive studies to solve the above-mentioned problem. As a result, they have found out that when said facets are treated by irradiating with plasma having energy falling within an optimized range from the facet side, the facets can be easily made transparent without any problems (for example, control of the diffusion depth and the horizontal diffusion to the cavity as observed in the case where impurities are diffused; difficulties in the electrode formation as observed in the case where epitaxial growth is performed on the facets; passage of reactive current accompanying the decrease in the resistance in the vicinities of the facets), thus giving semiconductor lasers achieving both of high output and high reliability. The present invention has been completed on the basis of this finding.
Accordingly, the gist of the present invention resides in a process for producing a semiconductor laser having a first conduction type of clad layer, an active layer and a second conduction type of clad layer formed on a semiconductor substrate, characterized in that at least one facet forming a cavity is irradiated with plasma having energy of from 25 eV to 300 eV.
The present inventors have further conducted extensive studies to solve the above-mentioned problem. As a result, they have found out that semiconductor light emitting devices produced by a process for producing a semiconductor light emitting device having a compound semiconductor layer containing at least a first conduction type of clad layer, an active layer and a second conduction type of clad layer formed on a substrate and having a cavity, which comprises forming the compound semiconductor layer on the substrate by crystal growth; next forming the cavity facets; then desorping a part of the elements constituting at least the active layer in the vicinities of the facets exposed on at least one of the facets via irradiation with ion, electron, heat and/or light, etc. to thereby form a region transparent to the emission wavelength in the vicinities of the semiconductor light emitting device; and forming a passivation layer in vacuum; are much superior both in high output and high reliability to the conventional ones, though the production process is highly convenient, thus completing the present invention.
Accordingly, the gist of the present invention resides in a process for producing a semiconductor light emitting device having a first conduction type of clad layer, an active layer and a second conduction type of clad layer formed on a substrate and having a cavity, characterized by comprising forming the compound semiconductor layer on the substrate by crystal growth; next forming the cavity facets; then desorption of a part of the elements constituting at least the active layer in the vicinities of the facets exposed on at least one of the facets; and forming a passivation layer in vacuum.
The present inventors have further conducted extensive studies to solve the above-mentioned problem. As a result, they have found out that, in a semiconductor laser having a first conduction type of clad layer, an active layer containing quantum well and a second conduction type of clad layer on a semiconductor substrate, elements with high vapor pressure in the vicinities of the facets can be selectively desorbed by irradiating ion, electron, light and/or heat in vacuum to at least one facet forming the cavity. Thus a region having a band gap exceeding the effective band gap of the materials constituting the active layer is formed in the vicinities of the facet. That is to say, the region is made transparent to the emission wavelength of the semiconductor laser. Thus, high-performance semiconductor lasers with the window-structure capable of achieving both high output and high reliability can be easily obtained without suffering from the above problems encountering in the prior art. The present invention has been thus completed.
Accordingly, the gist of the present invention resides in a semiconductor laser having a first conduction type of clad layer, an active layer containing quantum well and a second conduction type of clad layer formed on a semiconductor substrate, characterized in that the active layer is made transparent to the emission wavelength by desorping a part of the constituting elements in the vicinities of at least one facet forming the cavity.
Another gist of the present invention resides in a process for producing a semiconductor laser having a first conduction type of clad layer, an active layer containing quantum well and a second conduction type of clad layer formed on a semiconductor substrate, characterized by comprising forming the first conduction type of clad layer, active layer containing quantum well and second conduction type of clad layer on the semiconductor substrate; and selectively desorping elements with high vapor pressure by irradiating in vacuum at least one facet forming the cavity with ion, electron, light and/or heat beam to thereby form a region which has been made transparent to the emission wavelength in the vicinities of the facet of the active layer.
The present inventors have further conducted extensive studies to solve the above-mentioned problem. As a result, they have found out that a compound semiconductor light emitting device having at least a first conduction type of clad layer, an active layer and a second conduction type of clad layer grown on a substrate, two facets which are opposite to each other forming a cavity and having an emission wavelength of xcex (nm), characterized in that the surfaces of the first conduction type of clad layer, active layer and second conduction type of clad layer forming the transparent facets are coated with passivation layers, and the surfaces of the passivation layers are coated with a coating layer comprising a dielectric material optionally combined with a semiconductor, is much superior in high output and high reliability to the conventional ones, thus completing the present invention.
Accordingly, the gist of the present invention resides in a compound semiconductor light emitting device having at least a first conduction type of clad layer, an active layer and a second conduction type of clad layer grown on a substrate, two facets which are opposite to each other forming a cavity and having an emission wavelength of xcex (nm), characterized in that the surfaces of the first conduction type of clad layer, active layer and second conduction type of clad layer forming the facets are coated with passivation layers made of Si, and the surfaces of the passivation layers are coated with a coating layer comprising a dielectric material optionally combined with a semiconductor.
A first aspect of the device is a compound semiconductor light emitting device of present invention, which comprises
a first conduction type of clad layer;
an active layer; and
a second conduction type of clad layer grown on a substrate and
two of said first conduction type of clad layer; said active layer, and said second conduction type of clad layer, being opposite to each other so as to form a cavity,
wherein said active layer is transparent to the emission wavelength in the vicinities of the facets and the surfaces of the first conduction type of clad layer, active layer and second conduction type of clad layer forming said facets are each coated with a passivation layer.
A second aspect of the device is a compound semiconductor light emitting device according to the first aspect, wherein at least one of the constituting elements of the surfaces of the first conduction type of clad layer, active layer and second conduction type of clad layer forming said facets exists in the form free from an oxide.
A third aspect of the device is a compound semiconductor light emitting device according to the first aspect, wherein the vicinities of said facets have been disordered.
A fourth aspect of the device is a compound semiconductor light emitting device according to the first aspect, wherein a coating layer comprising a dielectric material optionally combined with a semiconductor material is formed on the surface of said passivation layer.
A fifth aspect of the device is a compound semiconductor light emitting device according to the first aspect, wherein said passivation layer contains Si.
A sixth aspect of the device is a compound semiconductor light emitting device according to the first aspect, wherein one of said facets is coated with an anti-reflective coating layer containing an AlOx layer while the other is coated with a high-reflective coating layer containing AlOx layer and Si layer.
A seventh aspect of the device is a compound semiconductor light emitting device according to the first aspect, wherein said active layer comprises a compound semiconductor layer containing In.
An eighth aspect of the device is a compound semiconductor light emitting device of the present invention, which comprises:
a first conduction type of clad layer; an active layer; and a second conduction type of clad layer, grown on a substrate and
two facets of said first conduction type of clad layer; said active layer; and said second conduction type of clad layer, being opposite to each other so as to form a cavity,
wherein a conduction type of said active layer is p type and the surfaces of the first conduction type of clad layer, active layer and second conduction type of clad layer forming said facets are coated with a passivation layer containing Si.
A ninth aspect of the device is a compound semiconductor light emitting device according to the eighth aspect, wherein at least one of the constituting elements of the surfaces of the first conduction type of clad layer, active layer and second conduction type of clad layer forming said facets exists in the form free from an oxide.
A tenth aspect of the device is a compound semiconductor light emitting device according to the eighth aspect, wherein the vicinities of the facets of the cavity have been disordered.
A eleventh aspect of the device is a compound semiconductor light emitting device according to the eighth aspect, wherein said active layer comprises a compound semiconductor layer containing In.
A twelfth aspect of the method is a method of fabricating a compound semiconductor light emitting device of the present invention, which comprises the steps of:
growing a first conduction type of clad layer, an active layer and a second conduction type of clad layer on a substrate;
forming facets of a cavity; and
irradiating said facets of the cavity with plasma having energy of from 25 eV to 300 eV in vacuum.
A thirteenth aspect of the method is a method of fabricating a compound semiconductor light emitting device according to the twelfth aspect, wherein step of forming facets of a cavity comprises a cleavage of the first conduction type of clad layer, the active layer and the second conduction type of clad layer so that two facets are opposite to each other to form the cavity.
A fourteenth aspect of the method is a method of fabricating a compound semiconductor light emitting device according to the twelfth aspect, wherein plasma of an element of the group 18 is used in said irradiating step.
A fifteenth aspect of the method is a method of fabricating a compound semiconductor light emitting device according to the twelfth aspect, which further comprises a step of:
forming a passivation layer on each facet after said plasma irradiation step.
A sixteenth aspect of the method is a method of fabricating a compound semiconductor light emitting device according to the twelfth aspect, which further comprises a step of: forming an anti-reflective coating and/or a high-reflective coating on said facets while evacuating continuously after the irradiating step.
A seventeenth aspect of the method is a method of fabricating a compound semiconductor light emitting device of the present invention, which comprises the steps of:
growing a first conduction type of clad layer, an active layer and a second conduction type of clad layer on a substrate;
forming facets of a cavity by cleavage of the first conduction type of clad layer, the active layer and the second conduction type of clad layer so that two facets are opposite to each other so as to form a cavity;
removing, from said facets, a part of elements constituting the facet; and
forming a passivation layer on each facet after said removing step.
An eighteenth aspect of the method is a method of fabricating a compound semiconductor light emitting device according to the seventeenth aspect, wherein said removing step comprises a step of irradiating said facets with at least one selected from the group consisting of ion, electron, light and heat in vacuum.
A nineteenth aspect of the method is a method of fabricating a compound semiconductor light emitting device according to the seventeenth aspect, wherein plasma having energy of from 25 eV to 300 eV is used in said irradiating step.
A twentieth aspect of the method is a method of fabricating a compound semiconductor light emitting device according to the seventeenth aspect, wherein plasma of an element of the group 18 is used in said irradiating step.
A twenty-first aspect of the method is a method of fabricating a compound semiconductor light emitting device according to the seventeenth aspect, which further comprises a step of forming, on said passivation layer, a coating layer containing at least one combinations of dielectrics and semiconductors.
A twenty-second aspect of the method is a method of fabricating a compound semiconductor light emitting device according to the seventeenth aspect, wherein said passivation layer contains Si.
A twenty-third aspect of the method is a method of fabricating a compound semiconductor light emitting device according to the twenty-first aspect, wherein, at the formation of said coating layer, the surface is irradiated with plasma simultaneously with the formation of the coating layer.

Compound semiconductor light emitting device and method of fabricating the same


An impact driver (1) includes a main housing (2) encasing a motor (5); an internal gear case (8) which is secured by screws to the main housing (2) and is provided with an externally threaded portion (12); and a hammer case (13) with an internally threaded portion (14) which is adapted for threadable engagement with the externally threaded portion (12) of the internal gear case (8) so as to couple the hammer case (13) to the internal gear case (8). The impact driver (1) additionally includes a rotation stop mechanism comprised of a rack (24) disposed within a forward extending portion (23) of the main housing (2) for meshing with dimples (27) formed in the outer surface of the hammer case (13). By fixing the rack (24) with a feed screw (26) disposed transversely in the forward extending portion (23), the hammer case (13) is prevented from rotation with respect to the internal gear case (8) after assembly of the impact driver (1). The impact driver (1) further includes an LED light unit (28) disposed in the extending portion (23) forward of the rotation stop mechanism so as to illuminate objects in front of the hammer case (13).

This application claims priority on Japanese Patent Application No. 2001-350,543 filed on Nov. 15, 2001.
1. Field of the Invention
The present invention generally relates to impact power tools. More particularly, the present invention relates to an impact driver which includes a housing containing a motor and further includes a hammer case which is assembled to the front end of the main housing and contains an impact mechanism.
2. Description of the Related Art
An impact driver generally includes a main housing that contains a motor and a hammer case which is assembled to the front end of the main housing and contains an impact mechanism. As disclosed in Japan Published Unexamined Patent Application No. 7-148669, typically, the hammer case and the main housing of such an electric power tool are both provided with protuberances or bosses with screw holes such that the case can be assembled to the housing from the front of the tool by tightening screws into the screw holes.
While this arrangement achieves its intended objective, it is not free from certain problems and inconveniences. For example, the bosses, as they protrude from the outer peripheral surfaces of the main housing and the hammer case, may hinder or interfere with work in tight space, or damage the material, such as a board, being fastened, for example, with screws by the power tool during operation.
In view of the above-identified problems, an important object of the present invention is to provide an impact power tool with a main housing and a hammer case both having a simplified shape so as to improve the ease of use of the tool and work efficiency.
Another object of the present invention is to provide an electric power tool that is free from protrusions that may hinder the use of the tool.
The above objects and other related objects are realized by the invention, which provides an impact tool that includes a main housing containing a motor and having a front end. The tool further includes a hammer case containing an impact mechanism and having a rear end, with the hammer case being assembled to the front end of the main housing. The front end of the main housing includes a first threaded portion, whereas the rear end of the hammer case includes a second threaded portion adapted for threadable engagement with the first threaded portion of the main housing so as to couple the hammer case to the main housing. The impact tool additionally includes a rotation stop mechanism provided in the main housing at a position below the hammer case for engaging an outer surface of the hammer case so as to prevent rotation of the hammer case with respect to the main housing upon coupling of the hammer case to the main housing. Due to the foregoing arrangement (i.e., the threadable engagement between the hammer case and the main housing in combination with the provision of the rotation stop mechanism), the outer surfaces of the main housing and the hammer case are free of obstructive protrusions or protuberances, thus ensuring unimpeded tool operation and greatly reducing the possibility of damaging the material, such as a board, being fastened by the electric tool. The arrangement additionally ensures reliable connection between the main housing and the hammer case. Due to the simplified shapes of the main housing and the hammer case, the manufacture of these components is also advantageously simplified. As there are no protrusions on the hammer case and the internal gear case, there is no need to locate or position the hammer case with respect to the main housing during assembly, thus eliminating at least one step from the entire assembly procedure of the tool.
According to one aspect of the present invention, the hammer case is screwed on the main housing in a first direction so as to couple the hammer case to the main housing. Furthermore, the rotation stop mechanism includes: a plurality of recesses provided in the outer surface of the hammer case; a rack disposed in the main housing for being transversely slidable therein and capable of engaging the recesses; and a screw member which is inserted into the rack from a side surface of the main housing and threadably engages the rack, the screw member being capable of causing the rack to travel in the first direction when tightened into the rack. This arrangement realizes a simply constructed and reliable mechanism for stopping the rotation of the hammer case.
According to another aspect of the present invention, the impact tool further includes an on/off trigger below the hammer case for activating the motor. The rotation stop mechanism is disposed immediately above the on/off trigger between the trigger and the hammer case.
According to still another aspect of the present invention, the main housing includes a forward extending portion protruding therefrom above the on/off trigger and covering a lower portion of the hammer case.
According to yet another aspect of the present invention, the impact tool further includes an illuminant disposed in the main housing forward of the rotation stop mechanism so as to illuminate objects in front of the hammer case. In this way, the illuminant can be disposed in an advantageous position without compromising the simple outer shape of the impact tool.
According to one feature of the present invention, the forward extending portion includes an opening at a front end thereof into which the illuminant is inserted, and furthermore the illuminant is oriented at an upwardly inclined angle.
In one embodiment of the invention, the main housing includes an internal gear case having a ring portion which has an outer peripheral surface. The first threaded portion is provided as an external thread in the outer peripheral surface of the ring portion. Furthermore, the hammer case includes an opening at a rear end thereof The second threaded portion is provided as an internal thread in an inner peripheral surface of the opening of the hammer case.
Other general and more specific objects of the invention will in part be obvious and will in part be evident from the drawings and descriptions which follow.


A lens plate includes at least one lens row including a plurality of lenses aligned in a first direction, each lens including a lens surface that includes perimeter portions extending in a second direction substantially perpendicular to the first direction such that two adjacent lenses are contiguous with each other at the perimeter portions.

1. Field of the Invention
The present invention relates to a lens plate, a lens unit, an exposing apparatus, an image forming apparatus, and an image reading apparatus.
2. Description of the Related Art
Existing electrophotographic image forming apparatus incorporate an exposing device for forming an electrostatic latent image on a photoconductive drum. One such exposing device is an LED head which irradiates the charged surface of the photoconductive drum with light emitted from LED arrays using an optical system. Scanners and facsimile machines employ an optical system that forms an image on an image capturing section in which a plurality of light receiving element arrays are arranged.
The optical system includes a plurality of micro lenses aligned substantially in a straight line, the lenses forming an erect image of unity magnification with high resolution. One such optical system is disclosed in Japanese Patent Publication No. 2008-92006. This publication discloses a lens array in which a plurality of lenses are aligned in two adjacent rows such that the distance between the optical axes of adjacent lenses in each of the two adjacent rows is L1. Further, a micro lens in one of the two adjacent rows is between two adjacent micro lenses in the other of the two adjacent rows, and the distance between the optical axes of the two adjacent lenses is L2. The distance L1 is longer than the distance L2.
In order to improve the resolution of an electrostatic latent image, the size of LEDs in the LED head must be reduced to increase the density of dots of light. Decreasing the size of LEDs causes light output of individual LEDS to decrease. Thus, the light emitting efficiency of individual LEDs needs to be improved. In addition, the light generating efficiency of the light source must be improved in order to reduce power consumption.

Lens plate, lens unit, exposing apparatus, image forming apparatus, and image reading apparatus


A normalization threshold side size Nr which serves as an index indicative of how many times the pattern frequency r is repeated in one threshold matrix is defined as Nr=N×r/R where N represents a size of one side of the threshold matrix as the number of pixels, and the threshold array of the threshold matrix is determined such that the normalization threshold side size Nr is of an value greater than 65.

1. Field of the Invention
The present invention relates to a threshold matrix for generating a screen which is called an FM screen or a stochastic screen for converting a continuous-tone image into a dot pattern representative of a binary image, and more particularly to a threshold matrix suitable for use in a printing-related apparatus (output system) such as a filmsetter, a platesetter, a CTP (Computer To Plate) apparatus, a CTC (Computer To Cylinder) apparatus, a DDCP (Direct Digital Color Proof) system, etc., an ink jet printer, or an electrophotographic printer.
2. Description of the Related Art
Heretofore, so-called AM (Amplitude Modulation) screens characterized by screen ruling, screen angle, and dot shape, and FM (Frequency Modulation) screens have been used in the art of printing.
A process of generating a threshold matrix for FM screens is disclosed in Japanese Laid-Open Patent Publication No. 8-265566.
According to the disclosed process, an array of elements of a threshold matrix, i.e., an array of thresholds, is generated in an ascending order or a descending order by determining threshold positions such that the position of an already determined threshold is spaced the greatest distance from the position of a threshold to be newly determined. The dot pattern of a binary image that is generated using the threshold matrix thus produced has dots which are not localized. Even when a dot pattern is generated using a plurality of such threshold matrixes that are juxtaposed, the dot pattern does not suffer a periodic pattern produced by the repetition of threshold matrixes.
A plurality of patent documents given below are relevant to the generation of a threshold matrix.
Japanese Patent No. 3400316 discloses a method of correcting halftone image data by extracting a pixel having a weakest low-frequency component of a certain dot pattern, from white pixels (unblackened pixels), and a pixel having a strongest low-frequency component of the dot pattern, from blackened pixels, and switching around the extracted white and blackened pixels. Thus, the dot pattern is intended to be smoothed or leveled.
Japanese Laid-Open Patent Publication No. 2001-292317 reveals a process of determining threshold positions in a threshold matrix such that a next blackened pixel is assigned to a position having a weakest low-frequency component of the threshold matrix.
Japanese Laid-Open Patent Publication No. 2002-368995 shows a process of determining threshold positions in a threshold matrix such that when an array of thresholds in the threshold matrix has been determined up to a certain gradation and a threshold position for a next gradation is to be determined, blackened pixels are assigned to positions for not strengthening a low-frequency component.
Japanese Laid-Open Patent Publication No. 2002-369005 discloses a process of generating a threshold matrix according to the process shown in Japanese Patent No. 3400316 or Japanese Laid-Open Patent Publication No. 2001-292317, based on an ideal dot pattern at a certain gradation which is given.
When an FM screen is used for offset printing, it causes shortcomings in that the quality of printed images suffers some grainness. FM screens also cause disadvantages in that a dot gain tends to become large and images are reproduced unstably when images are printed, or when films are output in an intermediate printing process, or when a printing plate is output by a CTP apparatus.
According to the conventional FM screening process, when a dot size is determined to be the size of a dot made up of one pixel or a dot made up of four pixels according to a 1 (1×1)-pixel FM screen or a 4 (2×2)-pixel FM screen, an array of thresholds of a threshold matrix is determined by an algorithm for generating FM screens, thus determining an output quality, and only the dot size serves as a parameter for determining the quality of FM screens. For example, if a dot size is determined to be a 3×3-pixel FM screen dot size with respect to an output system which is incapable of stably reproducing 2×2-pixel FM screen dots for highlight areas, then the resolution (referred to as pattern frequency or pattern resolution) for intermediate tones is lowered, resulting in a reduction in the quality of images.
FIG. 25 of the accompanying drawings shows a conventional dot pattern 1 in a highlight area where the dot percentage of a 2×2-pixel FM screen is 5%, a conventional dot pattern 2 in an intermediate tone area where the dot percentage of the 2×2-pixel FM screen is 50%, a conventional dot pattern 3 in a highlight area where the dot percentage of a 3×3-pixel FM screen is 5%, and a conventional dot pattern 4 in an intermediate tone area where the dot percentage of the 3×3-pixel FM screen is 50%.
FIG. 26 of the accompanying drawings shows a power spectrum generated when the dot pattern 2 of the 2×2-pixel FM screened shown in FIG. 25 is FFTed (Fast-Fourier-Transformed), and FIG. 27 of the accompanying drawings shows a power spectrum generated when the dot pattern 4 of the 3×3-pixel FM screen shown in FIG. 25 is FFTed.
In FIG. 25, at the dot percentage of 50% in the intermediate tone area, the dot pattern 2 of the 2×2-pixel FM screen suffers less grainness than the dot pattern 4 of the 3×3-pixel FM screen, but has the dot percentage less reproducible in the printed image. On the other hand, at the dot percentage of 50% in the intermediate tone area, the dot pattern 4 of the 3×3-pixel FM screen has a pattern frequency 6 of about 13 c/mm which is lower than the pattern frequency 5 of about 20 c/mm of the dot pattern 2 of the 2×2-pixel FM screen. The pattern frequencies 5, 6 which are of peak values are also called a peak spatial frequency fpeak.
The output resolution of an output system such as an imagesetter, a CTP apparatus, etc. (the output resolution of an output system will hereinafter be referred to as output resolution R) is set to 2540 pixels/inch=100 pixels/mm or 2400 pixels/inch=94.488 pixels/mm, for example. With those settings, the dot size of the 1×1 pixel FM screen is 10 μm×10 μm (10.6 μm×10.6 μm), and the dot size of the 2×2 pixel FM screen is 20 μm×20 μm (21.2 μm×21.2 μm). In this description, the output resolution R is different from the pattern frequencies 5, 6 of the dot patterns 2, 4 shown in FIGS. 26, 27.
As described above, only the dot size is a parameter for determining the quality of conventional FM screens.
It is considered in this connection that the conventional FM screens have a greater periphery length (to be described in detail later on) than the AM screens at the same dot percentage.
Based on the concept that N×M pixels (usually N=M) constitute a unit for reproducing a gradation, a threshold matrix is made up of an array of N×M thresholds corresponding to the N×M pixels. A plurality of such threshold matrixes (also called as dither matrixes) are repetitively arrayed for comparison with continuous-tone image data. Accordingly, undesirable unevenness or irregularity of hue or shade in image tends to occur at a pitch or an angle due to the repeated units of the threshold matrix.
For example, if 100×100 threshold matrixes corresponding to 100×100 pixels are obtained with respect to an output system whose resolution R is 2540 pixels/inch=100 pixels/mm, then grid-like unevenness (noise) at a pitch of 1 mm or unevenness inclined at 45 degrees at a pitch of about 0.71 mm are liable to occur in output images.

Threshold matrix, storage unit for storing threshold matrix as data, and raster image processor incorporating storage unit


A micro-leakage regulating valve, in which a metal block has a through hole and a tapped hole extending from one side of the metal block and communicating with the through hole at the center thereof. The through hole has inserted therethrough a capillary metal tube. At one end of the through hole a sealing member provides a seal between the outer peripheral surface of the capillary metal tube and a surrounding wall surface of the metal block. An adjusting screw is screwed into the tapped hole, to crush the capillary metal tube to a desired degree, setting a desired flow rate.

The present invention relates to a micro-leakage regulating valve which is capable of generating a reference leakage for calibrating a leakage measured by leakage test equipment.
Leakage test equipment is used to test containers which must be free from leakage of gas or liquid, or gas fittings. The test equipment applies a fixed pneumatic pressure to the device under test and a leak-free reference container of the same content volume as the device under test, monitors the difference in internal pressure between the device under test and the reference container, and measures the differential pressure to thereby make a check for leakage.
In such a leakage test equipment the sensitivity for detecting leakage is calibrated by:
(A) generating a known amount of leakage at the side of the device under test, or PA1 (B) changing the content volume of the device under test by a known value so that the resulting differential pressure produces the same effect as that by leakage.
With method (A), when the amount of leakage is relatively large, it can be set to a desired value by use of the existing throttle valve or the like. In the case where the amount of leakage is, for example, as small as 1 cc or less per minute, it cannot be set by the conventional means, and even if it can be set, the set state is unstable.
The method (B) is suitable for reproducing a very small amount of leakage, but this method calls for conversion between a volume change and the amount of leakage, and hence consumes much time for calibration. On this account, there is a strong demand for the implementation of a micro-leakage regulating valve which permits reproduction of a very small amount of leakage.


A touch screen panel provided in an image display device. The touch screen panel includes a transparent substrate, a plurality of first sensing patterns on a first side of the transparent substrate and coupled to each other along a first direction, a first insulating film on the first sensing patterns, and a plurality of second sensing patterns on the first insulating film and coupled to each other along a second direction crossing the first direction. The second sensing patterns are alternately arranged with the first sensing patterns to not overlap with the first sensing patterns, wherein the thickness of the first sensing patterns is different from that of the second sensing patterns.

1. Field of the Invention
The present invention relates to a touch screen panel provided in an image display device, etc., and a method of fabricating the same.
2. Description of Related Art
A touch screen panel is an input device by which a user can input his or her instruction by selecting an instructed content displayed on a screen such as an image display device, etc. using a human's finger or an object.
To this end, the touch screen panel is provided on the front face of the image display device to convert a contact position with the human's finger or object into an electrical signal. Therefore, the instructed content selected on the contact position is accepted as an input signal.
Applications of the touch screen panel as described above are expanding widely because it can replace an input device that is coupled to and operates the image display device such as a keyboard, a mouse, or the like.
A touch screen panel can be categorized into a resistive type, a photosensitive type or an electrostatic capacitive type.
Among the types of touch screen panels, the electrostatic capacitive type touch screen panel utilizes a conductive sensing pattern to sense a change in electrostatic capacitance formed in association with other sensing patterns in the vicinity thereof or a ground electrode, etc., thereby converting a touch with a contact position into an electrical signal.
Here, in order to determine the contact position on the contact surface, the sensing pattern includes first sensing patterns (X patterns) formed to be coupled along a first direction, and second sensing patterns (Y patterns) formed to be coupled along a second direction.
The first and second sensing patterns as described above are generally positioned in the same layer. In this case, the sensing patterns positioned in the same X or Y lines are coupled by forming separate coupling patterns through contact holes formed in insulating films thereon. Accordingly, additional masks may be required and the fabrication process thereof may be complicated.
In addition, the touch screen panel is positioned on the display panel such as a liquid crystal display panel, etc., and an external light incident on the touch screen panel is reflected by the touch screen panel. Therefore, in order to display a uniform image, it is desirable to reduce the difference in light reflectance over the entire touch screen panel.

Touch screen panel and method of fabricating the same


A combined packing and assembly method that efficiently packs ribonucleic acid (RNA) into virus like particles (VLPs) has been developed. The VLPs can spontaneously assemble and load RNA in vivo, efficiently packaging specifically designed RNAs at high densities and with high purity. In some embodiments the RNA is capable of interference activity, or is a precursor of a RNA capable of causing interference activity. Compositions and methods for the efficient expression, production and purification of VLP-RNAs are provided. VLP-RNAs can be used for the storage of RNA for long periods, and provide the ability to deliver RNA in stable form that is readily taken up by cells.

In RNA interference (RNAi), an iRNA (an RNA molecule with gene interference activity) of appropriate sequence will down-regulate a given gene by preventing a specific messenger RNA (mRNA) from producing protein. RNAi has been rapidly developed into a potent and broadly applied tool in medicine, biofuels, agriculture and basic research (Sledz and Williams, Blood, 106(3):787-794 (2005)).
Production, packaging, storage and delivery of RNA remains the central challenge to the therapeutic application of RNAi technology. Purified RNAs are notoriously unstable and are extremely vulnerable to degradation, for example by nucleases, hydroxyl radicals, UV light, and Mg2+-mediated inline attack. The low-stability of RNAs precludes storage for long periods of time and severely limits the potential range of distribution and application methods for RNA-based pharmaceutical compounds. As a result, RNA-based applications commonly require costly and inefficient chemical modification of RNA for stabilization and delivery.
Therefore, it is an object of the invention to provide methods and compositions for the improved delivery of RNA to a target cell or a host.
It is still another object of the invention to provide methods and compositions for down-regulating gene expression in a host.

Compositions and methods for inhibiting gene expressions


Palletizing apparatus of the invention comprises a load forming station, a device for placing a layer on a pallet, devices for forming and placing a cap on the layer, and devices for applying restraint to formed edge panels of the cap. A formable cap sheet is received into the palletizing system as a flat sheet, and leaves the palletizing system as a formed cap on a load layer. The resulting pallet loads are preferably stretch wrapped. Methods of operating the apparatus are also disclosed.

This invention relates to handling of materials in layers, and especially in layers on pallets and other supporting surfaces. It relates to palletizing materials with a minimum amount of manual lifting of product or other load materials by attending labor or machine operators. Individual elements of material being handled may be thin as a single sheet of paper, or thicker such as a magazine, a book, or a conventional carton of product. Particularly with reference to cartons and other boxes, the individual elements are sometimes susceptible to lateral displacement relative to each other in a layer, especially where there are gaps in rows, or between rows.
Individual layers on a pallet are typically separated by separating sheets, typically referred to as tie sheets. This invention is particularly concerned with the handling of separating sheets which are formed and used as 3-dimensional caps over each layer. Such a cap has a main panel covering the layer, and a plurality of edge panels depending downwardly from the main panel and engaging the sides of the respective layers. The cap is conventionally used to cover, in combination, a plurality of open-topped cartons which form a palletized layer of such cartons. Such cap is also used to cover an entire layer for the purpose of providing lateral stability to a palletized layer of unstable product such as e.g. a palletized layer of empty 2-liter polyethylene terephthalate soft drink bottles. Typically, the above caps are shipped to the user set up in 3-dimension format, and are placed on the pallet by hand labor. The use of hand labor for such repetitious task is wasteful of manpower. It is also wasteful to ship the caps set up if they can be shipped flat and automatically set up by the user in the palletizer.
Apparatus for automatically palletizing layers of material is known in the art. A conventional palletizer for boxes or cartons may use a horizontally, reciprocally movable transfer plate for carrying boxes to a position above a pallet onto which the boxes are to be loaded. The transfer plate is then withdrawn from beneath the boxes, thereby depositing them onto the pallet. Retaining means are used for preventing the boxes from moving with the transfer plate as it is withdrawn. Such retaining means commonly include a bar which abuts the side of the boxes facing the direction of transfer plate withdrawal. Structures of this general nature are disclosed in, for example, U.S. Pat. No. 3,149,732 Gagnon et al and U.S. Pat. No. 3,833,132 Alduk.
Palletizing and depalletizing apparatus are disclosed in the following U.S. Pat. Nos.
______________________________________ Paxton et al 2,243,919 Samler 2,656,047 Locke 2,875,907 Woodcock 2,875,908 Keyes 2,878,948 Lazott et al 2,937,482 Reed 2,940,617 Freeman 2,978,125 Magnuson 3,105,598 Gagnon 3,149,732 McWilliams 3,157,301 Jeremiah 3,166,203 Kampert 3,257,006 Bruce 3,278,048 Roth et al 3,389,810 Grasvoll 3,594,977 Larson 3,606,310 Brockmuller 3,637,093 Grasvoll 3,648,857 Carlson 3,669,282 Von Gal Jr. et al 3,682,338 Munroe 3,720,176 Alduk 3,833,132 Dawson et al 3,836,018 Golantsev 3,837,140 Ballard 3,884,368 Beal 3,946,883 Wilde et al 3,986,620 Kelley 4,030,618 Mabey et al 4,032,021 Schmitt 4,067,456 Zimmerman 4,159,058 Schmitt 4,162,016 Shorthouse 4,172,686 Schmitt 4,195,959 Pantin 4,205,934 Faltin 4,230,311 Donnelly 4,234,280 Meratti 4,255,074 Pulda 4,339,220 Cox 4,342,531 Sylvander 4,383,788 Ishida et al 4,397,246 Werkheiser 4,422,549 Werkheiser 4,439,084 Wise 4,477,067 Feldkamper 4,671,723 Liebel 4,708,247 as well as Fed. Rep. of Germany 3,107,495 Japan 54,129661 ______________________________________
So far as is known to the inventors herein, none of the above references teach any apparatus or method adapted to automatically place a cap on a formed layer on a pallet. Neither does any reference teach apparatus or method for forming a cap as an integral part of the palletizing process.
It is an object of this invention to provide palletizing apparatus including means to automatically form and place caps on layers in the formation of pallet loads.
It is another object to provide apparatus and methods to preform the caps from flat sheets and to place the pre-formed caps on the respective layers of material.
It is yet another object to provide apparatus and methods to place the flat sheets, adapted to being formed into caps, on the layers, in the pallet load, and subsequently to form the flat sheets into layer caps in the pallet load.
It is still another object to provide apparatus and methods adapted to form the flat sheets into layer caps in the pallet load, and to hold each so-formed cap in its formed configuration until the formed configuration is secured by stretch wrapping.