Disclosed herein is technology for, among other things, a current feedback fully differential amplifier. The amplifier includes an input stage operable to sense an input current at a first terminal and a second terminal. The input stage includes a first buffer having an input coupled with the first terminal and an output coupled with said the terminal. The input stage further includes a second buffer having an output coupled with the first terminal and an input coupled with the second terminal.

1. Field
Embodiments of the present invention relate generally to the field of feedback amplifiers.
2. Background
The fully differential amplifier (FDA) has become a key component in signal processing applications where high speed and signal fidelity are essential system requirements. Advantages offered by fully differential amplifiers over single ended amplifiers include inherent resistance to external noise sources, reduced even order harmonics, and increased dynamic range. FIG. 1 shows a circuit 100 illustrating a general purpose FDA 110 in a typical data acquisition application. Within the scope of this discussion, the term "general purpose" will refer to an amplifier circuit generally having the following properties: 1) a pair of differential inputs, νip and νim; 2) a pair of differential outputs, νop and νom; 3) a common mode reference input, νcm, to control the common mode voltage level at the FDA's outputs; 4) a feedback network external to the chip (i.e., user configurable gain); 5) the ability to DC couple both inputs and outputs; and 6) the ability to drive the closed loop FDA from either a differential or single ended source. The FDA in this example shall be considered ideal, meaning infinite differential open loop gain and input impedance across the frequency domain. The closed loop gain of circuit 100, assuming an ideal FDA 110, is given by:
                                          v                          o              ,              dm                                =                                    2                                                f                  1                                +                                  f                  2                                                      *                          [                                                                    v                    sp                                                                          (                                          1                      -                                              f                        1                                                              )                                                  -                                                      v                    sm                                                                          (                                          1                      -                                              f                        2                                                              )                                                              ]                                      ,                            (        1        )            where νo,dm, the differential mode output voltage, is defined asνo,dm≡νop−νom,  (2)f1 and f2 are the respective gain factors for positive and negative feedback networks
                                          f            x                    =                                    R              gx                                                      R                fx                            +                              R                gx                                                    ,                            (        3        )            and νsp and νsm refer to the positive and negative terminals of the source. For the balanced feedback network case, Rf1=Rf2=Rf and Rg1=Rg2=Rg, and Equation 1 reduces to:
                                          v                          o              ,              dm                                =                                    v                              s                ,                dm                                      *                          (                                                R                  f                                                  R                  g                                            )                                      ,                                          where                            (        4        )                                          v                      s            ,            dm                          ≡                              v            sp                    -                                    v              sm                        .                                              (        5        )            The output common mode voltage level, defined as
                                          v                          o              ,              cm                                ≡                                    (                                                v                  op                                +                                  v                  om                                            )                        2                          ,                            (        6        )            is controlled by means of a separate integrated amplifier circuit. The inverting terminal of this amplifier is connected to both output terminals of the FDA through a matched resistive divider network while the non-inverting terminal is connected to a reference voltage, Vcm. The closed loop gain of this amplifier, usually referred to as the common mode feedback amplifier (CMFB), is set to unity in most FDA integrated circuits.
FIG. 2 illustrates one possible implementation of the FDA 110 of FIG. 1. The architecture in FIG. 2 is based on a voltage feedback approach. Using this architecture, the balanced FDA gain relationship given in Equation 4 becomes:
                              v                      o            ,            dm                          =                              v                          s              ,              dm                                *                                                    (                                                      R                    f                                                        R                    g                                                  )                            [                              1                                  1                  +                                      1                                          2                                                                                G                          dm                                                                                (                          s                          )                                                                                Z                          t                                                                                (                          s                          )                                                                                f                                                                                ]                        .                                              (        9        )            This is the conventional closed loop gain expression for a linear voltage feedback FDA with finite open loop gain, where Gdm(s) is the transconductance of the differential input stage 210, and Zt(s) is the transimpedance gain of each half of the forward amplifier's signal path.
The amplifier's loop gain is given by:T(s)=2Gdm(s)Zt(s)f.  (10)This equation reveals the fundamental limitation of voltage feedback amplifier architectures, whether differential or single ended out, which is the direct proportionality of loop gain to the feedback factor f. As closed loop gain is increased (i.e., f is decreased), the loop gain is reduced, resulting in a corresponding reduction in closed loop bandwidth.
Another limitation of the voltage feedback FDA architecture depicted in FIG. 2 is the sensitivity of its high impedance inputs to parasitic capacitance at the νip and νim nodes. Analysis of the circuit of FIG. 2, introducing capacitors Cip and Cim at νip and νim respectively and ground, shows that the loop gain equation is modified by an additional high frequency pole:
                                          T                                      (              s              )                                =                                    2                                                              G                  dm                                                                  (                  s                  )                                                                                Z                  t                                                                  (                  s                  )                                                          f                                      (                              1                +                                                      sC                    i                                                                          R                    eq                                                              )                                      ,                            (        11        )            where it is assumed for simplicity that Cip=Cim=Ci and Req is simply Rf∥Rg. Typically, the parasitic capacitance contributions from PCB, package, and ESD protection circuits can add up to 1-2 pF. For example, a FDA configured for a gain of +1, with Rf equal to 500 ohms, will exhibit a parasitic pole between 318 MHz and 636 MHz. Any attempt to improve bandwidth by decompensation of the open loop amplifier will be limited by the loss of phase margin in the vicinity of this pole frequency.
The noise power spectral density at the differential output of the FDA is given by the following equation, where contributions from the resistive feedback network elements have been ignored for simplicity.
                              Pn          o                =                                                                                (                                              2                                                                          Vn                          i                                                                    )                                        2                                    +                                                            (                                              2                                                                          In                          ip                                                                                R                                                      eq                                                                                1                                                                                )                                        2                                    +                                                                                (                                              2                                                                          In                          im                                                                                R                                                      eq                                                                                2                                                                                )                                        2                                    +                                                            (                                              2                                                                                Vn                            cm                                                                                (                                                                                f                                1                                                            -                                                              f                                2                                                                                )                                                                                )                                        2                                                                                (                                                f                  1                                +                                  f                  2                                            )                        2                                              (        7        )
Vni is the input referred voltage noise, Inip and Inim, are the input referred current sources at the positive and negative input terminals respectively, and Vncm is the input referred noise of the CMFB amplifier. Reqx is defined as Rfx∥Rgx. If the feedback networks are balanced, the noise equation reduces to:
                              Pn          o                =                                                                              (                                      2                                                              Vn                      i                                                        )                                2                            +                                                                    (                                          2                                                                    R                        eq                                                              )                                    2                                *                                  (                                                            In                      ip                      2                                        +                                          In                      im                      2                                                        )                                                                                (                                  2                                    f                                )                            2                                .                                    (        8        )            Since the differential input to the voltage feedback FDA is high impedance, the noise contribution from circuit elements referred to the input as voltage sources will usually dominate the differential noise spectral density at the FDA output. The noise gain of the voltage feedback FDA will be proportional to the closed loop amplifier's feedback factor f.
      Pn    o    =            Vn      i      2              f      2      Thus, operation at higher signal path gains will necessarily be accompanied by higher noise levels at the FDA outputs.
In addition to voltage feedback, current feedback techniques have been applied in the design of high speed single ended output op-amps for a number of years. Advantages of current feedback (CFB) op-amps over their voltage feedback (VFB) counterparts include gain-bandwidth independence, generally higher slew rates, and improved even order non-linearity rejection. These performance benefits usually come at the price of less precision, smaller input common mode voltage range, and higher inverting input referred noise current. CFB techniques have not easily migrated to FDAs, primarily due to the difficulty in developing practical, low input impedance, fully differential input stage architectures with good common mode voltage rejection. However, the case for integrating current feedback techniques into the design of fully differential amplifiers is becoming more and more compelling as the demands of data acquisition systems continue to drive signal path components to provide high signal fidelity across much wider system bandwidths.
Previous attempts at designing a current feedback FDA have involved using two single-ended CFB amplifiers to form a differential amplifier. For example, U.S. Pat. No. 6,636,116, entitled "FULLY DIFFERENTIAL CURRENT FEEDBACK AMPLIFIER" and assigned to Texas Instruments Incorporated, discloses a CFB FDA that develops a differential low impedance input from the outputs of a pair of buffers, both referenced to a potential at their respective high impedance inputs. However, a dual, "un-balanced" input approach such as this results in an input stage that cannot discriminate between differential and common mode signals. In order to correct the balance error that results from such an implementation, the interfering input common mode signal must be cancelled elsewhere in the circuit. This is achieved by means of an additional circuit that replicates and 180° phase shifts the output current from one input buffer and combines it with the output current from the other, and vice versa. Moreover, in single ended input to differential output applications, where the common mode voltage at the FDA inputs is "boot strapped" to the differential voltage at the FDA outputs, holding the input buffer inputs to a fixed reference voltage could cause heavy current loading on each of the input buffers, and therefore introduce a significant distortion in the input stages of these circuits.

Class AB differential current conveyor input stage for a fully differential current feedback amplifier


A two-step process for forming champagne profiles on semiconductor wafers that provide, when metallized, good reliability, microcracking-free contacts and vias is disclosed. Dry etch apparatus having electrodes in a triode configuration, two plasma forming regions, and a pressure control system operative to provide a wide setpoint pressure range is also disclosed.

In dry etch apparatuses and processes, one or more plasmas are caused to interact with suitably prepared surfaces of semiconductor or other materials to form one or more intended microstructures thereon. In one form of dry etch apparatus, the plasmas are controllably produced by two electrodes in a diode configuration, and in another form of dry etch apparatus, the plasmas are controllably produced by three electrodes in a triode or other three-electrode configuration. Selected etches corresponding to the intended microstructures being fabricated are effected by varying the applied electrode powers and relative spacings, and by varying the gas chemistries and other plasma control parameters, in a manner well known to those skilled in the art.
One important etch known to those skilled in the art is intended to allow its subsequent metallization as a contact or via. The smaller the dimensions of these contact holes and vias are to be, the more difficult it becomes to provide acceptable metallization. For physical dimensions of about a micron and less, typically called for in VLSI and other applications, the profiles of these etches must be carefully controlled or the subsequent metallization is subject to undesirable microcracking and metal fatigue that adversely impact the reliability of the contacts or vias.
An etch having a so-called "champagne" profile is able to provide microcracking-free contacts and vias when subsequently metallized, and such an etch has been produced by different dry etch apparatuses by a variety of different processes. In an article entitled "Contact Hole and Via Profiling by High Rate Isotropic and Anisotropic Etching of Oxides", by Grewal et al., appearing in the proceedings of an IEEE V-MIC Conference (June 1987), incorporated herein by reference, the use of a single wafer etcher from LAM-Research having electrodes in a diode configuration is reported to implement a two-step isotropic/anisotropic etch process to form such champagne profiles, and the use of the LAM-Research single wafer etcher to implement an isotropic etch followed by the use of an Applied Materials RIE hex etcher to implement an anisotropic etch is also reported to form these champagne profiles. For the two-step etch process implemented in the LAM-Research single wafer etcher, the electrode gap and gas chemistries were varied to first implement the isotropic step and then the anisotropic step. The gas chemistries for the isotropic etch were carbon tetrafluoride (CF.sub.4) and oxygen (O.sub.2), and the gas chemistries for the anisotropic etch implemented in the LAM-Research etcher and in the Applied Materials RIE hex etcher were a trifluoromethane (CHF.sub.3) and oxygen (O.sub.2) mixture.
In an article entitled "Silicon Dioxide Profile Control for Contacts and Vias", by Giffen et al., appearing at Solid State Technology (April 1989), incorporated herein by reference, the use of a Tegal 1513e single wafer etcher having top, side and bottom electrodes in a three-electrode configuration is reported to provide such champagne profiles. In one process mode reported therein, the wafer rests on the bottom electrode, which is powered, the side electrode is at floating potential, and the top electrode is grounded. Radio frequency (RF) power is pulsed to the bottom electrode for segregating ions and radicals in the induced plasma discharge, thereby etching photoresist isotropically while anisotropical1y etching oxide. In another reported process mode, the three electrodes are powered in such a manner that the oxide layer first is etched isotropically by powering the side electrode while holding the wafer electrode at floating potential, and then etched anisotropically. In the pulsed power process mode, the duty cycle, which controls the ratio of the anisotropic to the isotropic etch, controls the oxide slope, and nitrogen trifluoride (NF.sub.3) was the primary etchant reported. For the isotropic/anisotropic process mode, different chemistries were used for the different tri-electrode RF power configurations, NF.sub.3 for the isotropic etch and SF.sub.6 /CHF.sub.3 for the anisotropic etch.
In an article entitled "Isotropic Plasma Etching of Doped and Undoped Silicon Dioxide for Contact Holes and Vias", by W. G. M. van den Hoek et al., appearing at J. Vac. Sci. Technol. A7 (3), (May/June 1989), incorporated herein by reference, the use of a Matrix System One etcher having two chambers separated by a grounded aluminum grid to implement an isotropic etch followed by the use of an AME 8110 hexode reactor to implement an anisotropic etch are reported for providing such champagne profiles. The isotropic etch in the Matrix System One etcher uses He and NF.sub.3 gas chemistries, and the AME 8110 hexode reactor uses CHF.sub.3 /CO.sub.2 /He gas chemistries.
Other diode and triode reactors are known, such as the model "384"diode reactor commercially available from the instant assignee, and the Waferetch 606/616 triode reactor, commercially available from GCA Corporation.
The utility of these heretofore known dry etch machines and/or processes has been limited either by an inability to form champagne profiles, or the etches that have been able to be formed thereby have suffered from less than desirable reproduceability, critical dimension control and/or, among others, resist erosion.

Dry etch process for forming champagne profiles, and dry etch apparatus


A wireless communication device is configured as an in-home node-B (H(e)NB). The H(e)NB is configured to perform a locking function to control modification of carrier and user controlled parameters, and also configured to detect a change in location.

A goal of the Third Generation Partnership Project (3GPP) Long Term Evolution (LTE) program is to develop new technology, new architecture and new methods for LTE settings and configurations in order to provide improved spectral efficiency, reduced latency, and better utilization of radio resources for faster user experiences and richer applications and services with less cost. As part of these efforts, the 3GPP has introduced the concept of an in-home, evolved node B (called H(e)NB) for LTE networks. 3GPP is also considering the in-home NB (called HNB) for Release 8 wideband code division multiple access (WCDMA). The acronym H(e)NB is used in this application to refer to both a H(e)NB and a HNB.
The in-home (e)NB (H(e)NB) is preferably similar to a wireless local area network (WLAN) access point (AP). It gives users access to LTE services (it may also provide Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communication (GSM) Edge Radio Access Network (GERAN), and other cellular services) over extremely small service areas such as homes and small offices. This can be particularly useful in areas where LTE has not been deployed and/or legacy 3GPP radio access technology (RAT) coverage already exists. This may also be useful in areas where cellular services have yet to be deployed, or where coverage may be faint or non-existent for radio related reasons, such as in an underground metro or shopping mall. The subscriber, whether an individual or an organization, will be able to deploy a H(e)NB in an area where such service is desired. FIG. 1 shows an example of a possible H(e)NB deployment.
Several issues should be addressed regarding the use of an H(e)NB. H(e)NB mobility is a potential problem. An H(e)NB could easily change location. A new location may pose a challenge if, for example, the operator who originally provided the H(e)NB did not offer coverage at the new location, thus a user may need to use a different operator and follow a location update procedure. An H(e)NB preferably would include high-level functions to implement detection of its own mobility as well as functions to implement other operator restrictions. All of this must be accomplished in a cost effective manner.


A method of testing for short circuits between networks of a printed circuit board comprising a plurality of such networks comprises measuring an impedance value between each of the networks and a ground plane of the board, using a pair of probes; and, also using the probes, effecting tests for short circuits only between any two networks for which the measured impedance value is substantially the same and for which this measured impedance value is greater than a predicted lowest impedance for the two networks to be short-circuited together.

The present invention relates to testing electrical circuits.
In the field of testing printed circuit boards, for example such boards before they have components added, it is known to test for open or short circuit faults in conductive tracks by making resistance value checks or capacitance value checks. Such checks may be made using at least one electrical testing probe, automatically controlled by a computer system to contact the board at appropriate points to make appropriate measurements.
Printed circuit boards may comprise a very large number of conductive tracks, forming a large number of networks, and it is necessary to know if there are undesired short circuits between such networks. For a printed circuit board having N such networks, the number of resistance based measurements required to verify that no undesired short circuit electrical paths exist between any two networks is: EQU N (N-1)/2
This is explained as follows. First, the resistance between a first network and every other network is measured, meaning a first number (N - 1) of measurements. Then, the resistance between a second network and every other network (except the first) is measured, meaning a second number ((N - 1) - 1) of measurements. Then, the resistance between a third network and every other network (except the first and second) is measured, meaning a third number ((N - 1)- 2) of measurements, and so on until the Nth network. The total number of measurements as a result of this is a series represented as above.
For a printed circuit board with a thousand networks, making resistance measurements between all networks as above would mean substantially half a million measurements and if, as is typical, the measurements are made using electrical testing probes, this would result in an extremely long test duration. A means of reducing the number of measurements in testing for short circuits between networks would clearly be an advantage.
To reduce the number of probe movements, U.S. Pat. No. 4,565,966 (Burr, et al) discloses a method and apparatus for testing a circuit board using a combination of capacitance measurements, between networks and a reference, and end-to-end resistance measurements of networks, the measured capacitance and resistance values being compared with respective pre-established values (obtained in a learning mode) for a board with no faults. There is also disclosed in Burr, et al a diagnostic routine for those networks which have been identified as being possibly faulty. More particularly, for those of the networks which have been identified as being possibly faulty and which have the same capacitance value in relation to the reference, inter-network resistance checks are carried out to check if any of them are short-circuited together, on the rationale that networks which have the same capacitance value in relation to the reference are likely to be short-circuited together. It would be possible to use such a routine for all the networks of a printed circuit board, by measuring the capacitance between each one of the networks and a reference, and carrying out tests for short circuits between pairs of networks which have the same capacitance value. However, this might result in too many short circuit tests being carried out than are actually necessary, since it is possible that two networks have the same capacitance value coincidentally and might not be actually short-circuited together.


A high resolution energy-selecting electron beam apparatus and method for improving the energy resolution of electron-optical systems by restricting the energy range of admitted electrons, and optionally also for improving the spatial resolution by correcting chromatic and geometric aberrations. The apparatus comprises a plurality of magnetic or electrostatic prisms that disperse an electron beam according to the energies of the electrons into an energy spectrum, a plurality of magnifying lenses such as electromagnetic or electrostatic quadrupoles that increase the energy dispersion of the energy spectrum, an energy-selecting slit that selects a desirable range of energies of the electrons, and optionally also sextupole, octupole and higher-order lenses that correct chromatic and geometric aberration of the electron-optical system. The apparatus also comprises further magnetic or electrostatic prisms and electron lenses arranged such that the energy dispersion of the electron beam emerging from the apparatus is cancelled.

1. Field of the Invention
The invention relates to electron-optical systems such as electron microscopes and microanalyzers. It relates particularly to high resolution scanning electron microscopes, high resolution scanning transmission electron microscopes, and to high resolution fixed-beam transmission electron microscopes.
2. Description of Prior Art
Electron-optical systems able to form electron beams that are narrow in spatial extent and also narrow in their energy spread are able to probe matter on an atomic scale, and are able to provide valuable information about the structure of matter, its chemical composition, chemical bonding, and electronic and vibrational properties. Information about chemical composition and bonding, and the electronic and vibrational properties of matter is typically derived from electron energy loss spectra, formed by passing a monochromatic beam of electrons through a thin sample in which the beam suffers discrete energy losses, dispersing the beam in energy, and recording a spectrum of the losses. The spatial resolution of such studies is largely determined by the brightness of the electron source and by the aberrations of the electron-optical system that forms the electron probe. The energy resolution of the spectrum is largely determined by the energy width of the electron beam incident on the sample, and by the energy resolution of the spectrometer.
The spatial resolution determines the size of the smallest sample features that may be imaged and analyzed, and atomic resolution becomes possible if the electron probe is smaller than one atom. The energy resolution of the recorded energy-loss spectrum determines what kinds of information may be obtained from it. Chemical composition information may be obtained from spectra showing an energy resolution of a few eV, chemical bonding and electronic properties typically require spectra with energy resolution of a few tenths of eV, and the sample vibrational properties may be probed by spectra with an energy resolution of a few meV. Because more information becomes available at higher resolution, there is much interest in improving the ability of electron-optical systems to focus electron beams into very narrow probes, and to form energy loss spectra with very high energy resolution.
Recent introduction of correctors of geometric aberrations has allowed the spatial extent of electron beams of medium primary energies of around 100 keV to be made smaller than the diameter of a hydrogen atom (i.e., <1 Å). Cold field emission electron guns are able to produce electron beams as narrow in energy as 0.25 eV, and electron monochromators are able to produce beams of electrons with primary energy of 100-200 keV that are as narrow as 30 meV and therefore can potentially lead to 30 meV energy resolution in electron energy loss spectra. However, no electron beam apparatus has yet been able to produce an electron beam of atomic size (1 Å diameter) at a primary beam energy of less than 50 keV, nor to illuminate a sample with an atom-sized electron beam and at the same time to resolve features in electron energy loss that are separated by less than 30 meV.
Being able to produce atomic-sized probes at the lowered primary energies would be advantageous when exploring materials made from light atoms, in which a lower primary energy often results in a dramatic reduction of knock-on radiation damage. Being able to produce electron energy loss spectra with an energy resolution better than 30 meV and preferably just 1-5 meV would allow an exploration of vibrational spectra of materials, and in this way provide a particularly rich new source of information.
The principal limit on the spatial resolution in electron beam systems corrected for geometric aberrations comes from chromatic aberration. There are two principal ways how the chromatic limit may be improved. In the first way, the energy spread of the beam is decreased through the use of an optical system that disperses the electrons according to their energies, and then intercepts, typically using an energy-selecting slit, all electrons whose energies lie outside a given pass-band of energies. Such an apparatus is typically called an electron monochromator. The resultant beam of narrower energy width is then affected by the chromatic aberration of the optical system much less, and an improvement in spatial resolution is typically obtained. The monochromator also significantly improves the attainable resolution in electron energy loss spectra. However, the improvement comes at the cost of a decreased brightness of the electron beam, caused by a large part of the beam being stopped by the energy-selecting slit. In the second way, the chromatic aberration of the optical system is corrected by a corrector of chromatic aberration. The chromatic aberration corrector does not filter out any electrons and therefore preserves the brightness of the electron beam, but it cannot improve the energy resolution of electron spectra.
Many types of both electron monochromators and chromatic aberration correctors have been developed over the years, as described for instance in U.S. Pat. Nos. 5,838,004, 6,407,384 B1, 6,580,073 B2 and 6,770,878 B2. Because chromatic aberration and a lack of a sufficiently bright electron beam are the two main factors that determine the spatial resolution when operating at lowered primary energies of the order of 20-60 kV, the chromatic correction is especially suitable for this type of operation.
A useful measure of the quality of a monochromator is the order of aberrations that it is able to correct. All monochromators are able to focus electron beams as needed to first order and some are also able to do second-order focusing, but no monochromator has yet achieved full third order focusing by correcting all important third-order aberrations. The higher the order of focusing a monochromator is able to do, the greater the range of angles of the electron beam it is able to monochromate correctly. Increasing the acceptable range of angles allows beams of greater total electron current to be monochromated. The interception of electrons of unwanted energies by the monochromator's energy-selecting slit results in a significant loss of total beam current, and being able to monochromate electron beams of larger starting current is therefore a significant advantage.
Another useful distinction is that existing monochromator designs can be separated into two broad classes: monochromators that disperse the electron beam according to energy and send the dispersed beam back into the overall electron-optical apparatus without nulling the dispersion, and monochromators that disperse the beam in order to do the energy selection, and subsequently null the dispersion before re-inserting the beam into the rest of the electron-optical apparatus. The second class is often called dispersing-undispersing monochromators. The first class of monochromators is simpler to build, but suffers from the disadvantage that the uncancelled energy dispersion causes a significant broadening of the virtual source of electrons, and hence a significant loss of brightness of the incident electron beam even when the energy-selecting slit is wide open, and no energy selection is taking place.
Monochromators developed up to the present time have typically acted on an electron beam of a low energy of the order of a few hundred eV to a few keV. This increases the energy dispersion the monochromators are able to achieve, and in this way allows the selection of narrower pass-bands of energies. The electrons are typically accelerated up to their final energy only after the energy selection has been accomplished. Unfortunately, performing the energy selection on particle beams of low energy increases the importance of Coulomb interactions between the individual electrons that constitute the electron beam. This interaction then limits the ultimate spatial and energy resolution that can be attained by the apparatus. Another limitation of monochromators performing the energy selection on a low energy beam is that variations in the high voltage used for the final acceleration cannot be readily compensated in the spectrometer part of the total apparatus, unless the electron beam is decelerated before the spectrometer, which is impractical and costly, and leads to further Coulomb interactions. Most spectrometers currently in existence therefore do not decelerate the electron beam before the spectrometer, with the result that instabilities in the accelerating voltage show up as instabilities in the energy of the final energy spectrum formed by a total apparatus comprising an electron spectrometer in addition to the electron source and the monochromator.
A monochromator system described in U.S. Pat. No. 5,097,126 was designed to perform energy selection on electrons of the full primary energy, in order to decrease the deleterious effect of Coulomb interaction. Because it operated on electrons of the full primary energy, it was able to link the energy being selected by the monochromator to the energy being analyzed by a spectrometer situated downstream in the optical system, simply by running the same current in the windings of all the magnetic prisms used in the monochromator and the spectrometer that were connected in series. This should have been able to give a very useful improvement in the energy stability and the energy resolution of the total optical system. Unfortunately, this monochromator was of the type that does not cancel dispersion before re-inserting the beam back into the electron-optical column, and the maximum attainable brightness of the electron beam monochromated by it was there therefore much more limited than in a dispersing-undispersing design. Further, the monochromator was only able to do a partial correction of second order aberrations, and provided no correction of third order aberrations, and no chromatic correction. For all these reasons, the intensity of the monochromated electron beam produced by this monochromator would have been very weak if the energy-selecting slit were closed down as necessary for an energy resolution of a few meV, rendering the monochromator unsuitable for this application.
Correctors of chromatic aberration of electron-optical systems have traditionally employed crossed electrostatic and electromagnetic fields in electrostatic/electromagnetic quadrupoles or Wien filters, as for instance described in U.S. Pat. Nos. 4,962,313 and 6,797,962 B1. The electrostatic elements create difficulties due to their need for relatively high voltage (several kV) to be supplied to small electrodes held in vacuum, which often leads to discharges. Another problem that arises with this type of chromatic aberration correctors is that voltage stabilities of the order of 1 part in 108 need to be achieved if an improvement in the spatial resolution is to be reached in modern, highly-perfected electron-optical systems, and such stabilities are difficult to attain and hold for an extended period of time.
Most users of electron microscopes and microanalyzers would find significant advantage in a energy-selecting apparatus and method acting on electrons of the full primary energy and therefore able to link the energy being selected by the apparatus to the energy being analyzed by a spectrometer, and which also performed correction of geometric and chromatic aberrations. They would especially appreciate it if the chromatic correction was performed electromagnetically, and thus avoided the need to bring large voltages inside the vacuum of the energy-selecting apparatus. They would also appreciate an energy-selecting apparatus able to cancel the energy dispersion before reinserting the electron beam into the column, which was therefore better able to preserve the brightness and intensity of the electron beam. They would further very much appreciate an ability to form electron energy spectra with an energy resolution sufficient for studying the vibrational modes of materials, at the same time as producing an electron probe of atomic dimensions, so that the vibrational properties could be explored on an atomic scale.

High resolution energy-selecting electron beam apparatus


The present invention is directed to an electrochemical medium for use in a reversible electrodeposition device including at least one solvent, at least one anodic electroactive material, at least one active metal; and optionally at least one redox buffer.

1. Field of the Invention
The present invention relates in general to electrochemical devices, and, more particularly, to reversible electrodeposition devices having electrochemical media which serve to enhance both durability and reversible deposition uniformity of the electrodeposition devices relative to the same without such electrochemical media.
2. Background Art
Electrodeposition devices have been known in the art for several years and are the subject of a plurality of United States Patents, including, for example, U.S. Pat. No. 5,056,899 entitled "Material For Light Modulation and Manufacturing Processes," U.S. Pat. No. 5,903,382 entitled "Electrodeposition Cell With High Light Transmission," U.S. Pat. No. 5,923,456 entitled "Reversible Electrochemical Mirror," U.S. Pat. No. 6,111,685 entitled "Reversible Electrochemical Mirror (REM) With Improved Electrolytic Solution," and U.S. Pat. No. 6,166,847 entitled "Reversible Electrochemical Mirror For Modulation Of Reflected Radiation"—just to name a few.
Generally, electrodeposition devices can be categorized into two groups, namely: "rocking chair" type electrodeposition devices wherein deposition/plating occurs via a plating-solution-plating mechanism (e.g. U.S. Pat. No. 5,903,382), and electrodeposition devices wherein deposition takes place while oxidation of a halide occurs at the anode (e.g. U.S. Pat. No. 5,056,899). While the above-identified electrodeposition devices have been known in the art for years, operational limitations and device configurations remain largely problematic, or at least, less than desirable for commercial applications.
For example, some electrodeposition devices can be susceptible to dendrite formation at or near an electrode, which, in turn, can adversely affect the electrochemical performance of the device, and in some circumstances render the electrodeposition device inoperable—even after only relatively few cycles (i.e. a transition from a high transmission state to a low transmission state). Moreover, several of the "rocking chair" type electrodeposition devices incorporate specially configured anodes which are distributed in localized, patterned areas and/or utilize a specially modified cathode as is disclosed in U.S. Pat. No. 5,923,456. Such configurations can materially increase manufacturing complexity, as well as compromise optical performance due to gridlines, dots, etcetera.
Electrodeposition devices as disclosed in U.S. Pat. No. 5,056,899 suffer from numerous drawbacks, the details of which are well disclosed in U.S. Pat. No. 5,903,382 and related cases.
It has now been surprisingly discovered that electrodeposition devices can be fabricated which exhibit enhanced durability by controllably selecting concentrations of anodic and/or cathodic materials within the electrochemical media without such complex device configurations. It has also been surprisingly discovered that incorporating redox buffers into the electrochemical media further enhances the electrochemical performance of such electrodeposition devices. (See, for example, U.S. Pat. Nos. 6,188,505; 6,310,714; and 6,433,914—all of which are hereby incorporated herein by reference in their entirety).
It is therefore an object of the present invention to provide an electrodeposition device having an electrochemical medium that remedies the aforementioned detriments and/or complications associated with conventional electrodeposition devices.
These and other objectives of the present invention will become apparent in light of the present specification, claims, and drawings.

This patent is subject to a terminal disclaimer.

Reversible electrodeposition devices and associated electrochemical media


A location processing device includes a selection member configured to select multiple flight vehicles to form a flight group. The location processing device also includes a determination member configured to determine first relative location information of the multiple flight vehicles of the flight group while instructing an operation device configured to control the multiple flight vehicles to perform operations.

In recent years, there are known scenarios in which multiple unmanned aerial vehicles ("UAVs") fly in collaboration in a region. In order to enable the multiple UAVs to fly in collaboration, a predetermined flight program may be executed, for example, to enable the multiple UAVs to fly in collaboration (refer to Patent Document 1). In Patent Document 1, multiple flight vehicles such as multiple UAVs, move to specified locations in the air and hover and then flash, based on instructions received from a ground station. As such, an observer may simulate observing the constellation.

Location processing device, flight vehicle, location processing system, flight system, location processing method, flight control method, program and recording medium


A power take off system for a hybrid-electric vehicle comprises an internal combustion engine, a hybrid-electric motor and generator, a power take off mechanism, a hybrid control module, and an engaging mechanism. The hybrid-electric motor and generator couples to the internal combustion engine. The power take off mechanism couples to the internal combustion engine and the hybrid-electric motor and generator. The power take off mechanism receives torque from at least one of the internal combustion engine and the hybrid-electric motor and generator. The hybrid control module is disposed in electrical communication with an electronic system controller. The hybrid control module generates output signals for controlling the internal combustion engine. The engaging mechanism is disposed in electrical communication with the electronic system controller. The engaging mechanism has a first mode and a second mode. The power take off mechanism is decoupled from the internal combustion engine and the hybrid-electric motor and generator in response to an output signal generated by the electronic system controller.

Many vehicles now utilize hybrid-electric drivetrains in order to increase the efficiency of the vehicle. A hybrid-electric drivetrain typically involves an internal combustion engine that operates a generator that produces electrical power that may be used to drive electric motors used to move the vehicle. The electric motors may be used to provide power to wheels of the vehicle to move the vehicle, or the electric motors may be used to supplement power provided to the wheels by the internal combustion engine and a transmission. In certain operational situations, the electric motors may supply all of the power to the wheels, such as under low speed operations. In addition to providing power to move the vehicle, the hybrid-electric drivetrain may be used to power a PTO of the vehicle that in turn powers PTO driven accessories. A hybrid-electric drivetrain may solely power the PTO of the vehicle when the PTO is operating a PTO driven accessory adapted to only be utilized by a stopped vehicle, such as lift attachment, or a digging attachment. In some situations, the hybrid-electric drivetrain is not capable of providing sufficient power to the PTO, and thus, the PTO needs to be powered by the internal combustion engine. In other situations, batteries of the hybrid-electric drivetrain may need to be recharged. In both of these situations, if the PTO is being powered by the hybrid-electric drivetrain, the PTO must be stopped, such that the internal combustion engine may be started to deliver power to the PTO, or to recharge batteries of the hybrid-electric drivetrain. Therefore, a need exists for a system and method that is capable of shutting down a PTO that is being driven by a hybrid-electric drivetrain, such that an internal combustion engine may be started to power the PTO, or to recharge batteries of the hybrid-electric drivetrain.

Control system for PTO equipment on a vehicle with a hybrid-electric drivetrain

International Truck Intellectual Property Company, LLC


A shape processor for processing an objective shape in a three-dimensional space while approximating, characterized by comprising an approximating section for generating a basic tile chain, i.e., a chain of basic tiles approximating the structure of the objective shape partially or entirely, by connecting the basic tiles of predetermined three dimensional shape having substantially tetrahedral shape including four vertexes sequentially starting with a starting point basic tile on the face of the basic tile.

1. Field of the Invention
The present invention relates to shape processors and methods for representing shape.
2. Description of the Related Art
So far, as methods for representing the shape of an object in a three-dimensional space, there are two known methods.
One is the polygon mesh method which uses polygons to imitate the outline of an object and describe the shape by the vertices, edges and faces of the polygons used.
The other is the CSG (Constructive Solid Geometry) method which uses reference blocks, such as cuboids, spheres and cylinders, to imitates the shape. In the method the shape is represented as a set of the reference blocks.
In these methods, an object is decomposed into a set of components and the shape of the object is described by specifying the shape of the components and their positions. Thus, some objects may require a lot of computation for their decomposition. And some objects may require a large amount of data to describe the shape of the components and their positions, i.e., to describe their shapes. On the other hand, for example, in the field of chemistry, pharmacy and nano-technology, an efficient method to represent the structure of a polymer is required since the function of a polymer is often determined by its structure.
The present invention aims to reduce the amount of computation and data to represent the shape of an object.

Shape processor and method for representing shape


A semiconductor circuit with the reduced scale of circuitry and a semiconductor integrated circuit chip which is obtained by integrating the semiconductor circuit and enables chip size reduction are provided. For this purpose, a two-decode method is used. The method uses: a pre-decode circuit comprising a first decoder of the preceding stage which decodes an arbitrary bit of an address signal of eight bits and a second decoder of the preceding stage which decodes the remaining bits; level conversion circuits which shift the output of the pre-decode circuit; and post-decode circuits which decode the decode outputs of the decoders in the pre-decode circuit, level-converted through the level conversion circuits.

The present invention relates to a semiconductor circuit. More particularly, it relates to a semiconductor circuit which constitutes a drive circuit for driving the pixels of an active panel-typed is play device using a liquid crystal panel, an organic electroluminescence panel, or the like.
An STN display device is so constituted that wiping is installed in two directions, x-axis direction (first direction) and y-axis direction (direction different from the first direction), throughout its display portion. When voltage is applied in the two directions, x and y, the liquid crystal at the intersection point is driven. An active matrix display device has an active element, such as thin film transistor (TFT), for each pixel, and in the display device, these active elements are switched and driven. These display devices are known as panel-type display device, such as liquid crystal display device and organic electroluminescence (organic EL) display device. The present invention is characterized in the circuitry of a semiconductor circuit which functions as a drive circuit for producing a screen display on a display panel, applied to these types of panel-type display devices. Also, the present invention is characterized in the circuit topology of a semiconductor integrated circuit chip wherein the above circuit is integrated.
For example, an active matrix liquid crystal display device using thin film transistors as active elements has a liquid crystal layer sealed between a pair of insulating substrates for which glass plates are favorably used. In its display area, a large number of pixels are formed in matrix arrangement. Outside the display area, a semiconductor integrated circuit chip as drive circuit is mounted. The thin film transistors constituting the individual pixels are led out of the display area through outgoing lines, and connected with this semiconductor integrated circuit chip. The thin film transistors disposed in the display area are connected with the, for example, 256 output terminals of gate drivers constituting the semiconductor integrated circuit chip through 256 gate lines in the scanning direction. The thin film transistors are selected by gate signals outputted through the output terminals, and the source lines of thin film transistors connected with the selected gate lines are supplied with indicative data. Thus, a screen display is produced.
In such an active matrix liquid crystal display device, liquid crystal driving voltage (gradation voltage) is applied to pixel electrodes for red (R), green (G), and blue (B) through thin film transistors. Therefore, no cross talk occurs between pixels, and a screen display with a large number of steps of gradation without cross talk can be produced.
FIG. 25 is a block diagram illustrating an example of the constitution of the gate driver unit the present inventors previously invented. FIG. 26 is an operating waveform chart of major parts of FIG. 25. In this constitution, address signals for selecting gate lines G1, G2, G3, G4, . . . , and G256 are of eight bits, and the address signals of eight bits [0] to [7] are counted up by address counters (not shown) and then inputted. The inputted address signals of eight bits [0] to [7] are decoded into (A000) to (A255) through a decode circuit DCR, and latched into latches LT on a latch clock. The decode outputs latched in the latches LT are inputted to a high breakdown voltage unit through NOR gates NR. The range of voltage level of the latched decode output is, for example, 3V to 0V. Shift registers may be used in place of the latch circuits.
The high breakdown voltage unit comprises level conversion circuits LS and a plurality (3×256 in this case) of high breakdown voltage inverters HV. Its output terminals (gate line terminals) GTM are connected with the gate lines of the display panel, and supply gate signals G1 to G256. The level conversion circuit LS converts inputted signals of 3V to 0V into as high a voltage level as 1.6V to −14V. Each of the gate line G1, G2, G3, G4, . . . , and G256 is provided with a gate driver GDR comprising a level conversion circuit LS and three high breakdown voltage inverters HV. The NOR gate NR is a gate for turning on and off a screen display on the display panel. During a non-display period when a full selection signal is inputted, the NOR gate NR discharges the electric charges in the pixels of the display portion.
The address signals of eight bits [0] to [7] are inputted as illustrated in FIG. 26, and latched into the latches LT when a latch clock is driven high. The latched address signals are level-shifted at the high breakdown voltage unit, and supplied as gate signals G1, G2, G3, . . . to corresponding gate lines through the gate line terminals GTM.
FIG. 27 is an explanatory drawing illustrating an example of the constitution of the level conversion circuit LS in FIG. 25, and FIG. 28 is an explanatory drawing illustrating a concrete example of the level conversion circuit LS in FIG. 25. The voltage values in FIG. 27 and FIG. 28 are as follows: VCC=3V; GND=0V; DDVDH=5V; VGH=15V; and VGL=−10V. This level conversion circuit LS comprises a series circuit of three high breakdown voltage inverters HV; a common inverter V connected in parallel with the series circuit; and a series circuit of three high breakdown voltage inverters HV. Its input is the output of a latch LT.
As illustrated in FIG. 27, the ranges of output voltage of various components are as follows: the range of output voltage of the inverter V is VCC to GND; the range of output voltage of the level conversion circuit LSa in the first stage constituting the level conversion circuit LS is DDVDH to GND; the range of output voltage of the level conversion circuit LSb in the second stage is DDVDH to VGL; and the range of output voltage of the level conversion circuit LSc in the final stage is VGH to VGL.
The level conversion circuit LSa in the first stage comprises four PMOS transistors and two NMOS transistors, as illustrated in the figure. The level conversion circuit LSb in the second stage comprises two PMOS transistors and four NMOS transistors, as illustrated in the figure. The level conversion circuit LSc in the final stage comprises two PMOS transistors and two NMOS transistors, as illustrated in the figure. The level conversion circuit LSb in the second stage and the level conversion circuit LSc in the final stage are connected together through two inverters.
FIG. 29 is an explanatory drawing illustrating an example of the constitution of the latch in FIG. 25. The latch comprises six inverters V and a NAND gate ND, as illustrated in the figure, and latches the output of the decode circuit DCR on a latch clock.
FIG. 30 is an explanatory drawing illustrating an example of the constitution of the 8-bit decode circuit in FIG. 25. The decode circuit comprises inverters V which are fed with eight bits [0] to [7] of an address signal, respectively, and NAND gates ND and NOR gates NR. Thus, the decode circuit produces 256 decode outputs (A000) to (A255).
FIG. 31 is a circuit diagram illustrating an example of the gateless driver the present inventors previously invented. This gateless driver GLDR is used together with a display panel GIPNL incorporating gates. The display panel GIPNL includes gate drivers which are formed over a substrate constituting a display panel. The gate drivers are constituted by thin film transistors formed of a high current mobility semiconductor film of low-temperature polysilicon or the like. The gate driver comprises a shift register SR, a high breakdown voltage NOR gate HNR, and a high breakdown voltage inverter HV with respect to each gate line.
The gateless driver GLDR comprises level conversion circuits LS which level-convert externally inputted full selection signals of, for example, 3V to 0V, frame leading pulses, and shift register clocks into large-amplitude signals of, for example, 16V to −14V. The gateless driver outputs these level-converted signals to the lead-out terminals GTM of the display panel GIPNL.
FIG. 32 is an explanatory drawing illustrating an example of the circuit of the shift register in FIG. 31, and FIG. 33 is a waveform chart illustrating the operation of the shift register in FIG. 32. The shift register comprises six high breakdown voltage inverters HV and two high breakdown voltage NOR gates HNR, as illustrated in the figure. The shift register is fed with a frame leading pulse which was level-shifted by a level shifter LS through the input terminal INPUT, and shifts it on a shift register clock which was similarly level-shifted by a level shifter LS. Its output is applied as gate signals G1, G2, G3, G4, . . . , and G256 to respective gate lines through the high breakdown voltage NOR gates HNR, the high breakdown voltage inverters HV, and its output terminal OUTPUT.
Documents disclosing this type of prior art include Patent Document 1.
[Patent Document 1] Japanese Unexamined Patent Publication No. Hei 8(1996)-106272


A memory (20) includes a nonvolatile memory array (32) and a volatile memory array (22). The nonvolatile memory array (32) is subdivided into banks of memory cells. The volatile memory array (22) may also be subdivided into multiple banks, and is smaller than the nonvolatile memory array (32). A transfer circuit (40) transfers the contents of a bank of nonvolatile memory array (32) into a bank of volatile memory array (22) before the data can be accessed by a processor (160). In addition, a preload decision logic circuit (180) may transfer a bank of nonvolatile memory array (32) into volatile memory array (22) invisibly to the processor (160), to have the data available when needed, thus avoiding a space fault. Coupling a smaller volatile memory array (22) to a nonvolatile memory array (32) combines the advantages of faster access times and nonvolatility without greatly increasing the size of the memory (20).

In general, semiconductor memories may be divided into two types, volatile memories and nonvolatile memories. Volatile memories lose stored data when power is removed, whereas nonvolatile memories, retain stored data when power is removed. Static random access memories (SRAMs) and dynamic random access memories (DRAMs) are two types of volatile memories. An SRAM cell is comprised of a bistable flip-flop, and data is stored by setting the state of the bistable flip-flop. In a DRAM cell, a capacitor is used to store data.
There are several types of nonvolatile memories. Read only memory (ROM) is a type of nonvolatile memory that is preprogrammed in the silicon by the semiconductor manufacturer. The preprogrammed contents of a ROM cannot be altered. Another type of nonvolatile memory is the Erasable Programmable Read Only Memory (EPROM). EPROMs can be erased and reprogrammed by the user using special ultraviolet light equipment. The Electrically Erasable Programmable Read Only Memory (EEPROM) is a type of nonvolatile memory that is reprogrammable without the special equipment needed for EPROMs. ROMs, EPROMs, and EEPROMs may be fabricated in relatively high density.
Nonvolatile memory is used in various ways in the design of digital systems. For example, nonvolatile memory may be used to store the standard program needed for enabling the various operations of a microprocessor. Also, nonvolatile memory may be used to provide look-up tables needed in some mathematical functions, or for the display of characters. In addition, nonvolatile memory is used in the design of control units for computers to store the sequence of control variables needed for enabling the various operations in the computer.
Nonvolatile memories have several disadvantages as compared to volatile memories such as SRAMSs. Nonvolatile memories suffer from relatively long access times, and they require relatively high power supply voltages for programming and for high speed operation. The relatively long access time of the nonvolatile memory may be reduced by using various circuit improvements, but the reduction in access time usually results in increased power consumption, or larger die sizes, with marginal increases in performance. In integrated circuits, it is common practice to use a lower power supply voltage to decrease power consumption. However, if a lower supply voltage is used with a nonvolatile memory, (for example, 3.3 volts), the long access time of the nonvolatile memory may be further increased.
Another solution to the problem of slow access times of nonvolatile memories has been to copy data from a nonvolatile memory array to a volatile memory array, upon power-up of the system. Then, the microprocessor in the system only has to access the SCRAM or DRAM. A disadvantage of this solution is that there needs to be as much volatile memory in the system as there is nonvolatile memory, substantially increasing the cost of the system. Also, a substantial amount of time is required to down load the contents of the nonvolatile memory into the volatile memory. The processor must wait until this transfer is complete before performing any other operations.

Memory having nonvolatile and volatile memory banks


An apparatus for forming a pattern of a nanoparticle-based ink on a substrate has a printing apparatus that is energizable to deposit the nanoparticle-based ink in a pattern on a surface of the substrate. An illumination apparatus is energizable to direct a patterned illumination to cure the deposited ink pattern on the substrate, the illumination apparatus having an array having at least a first and a second laser diode, each laser diode coupled to a channel in a laser light coupling element through an optical fiber and having an illumination lens disposed to direct illumination from the coupling element onto the surface of the substrate. A transport apparatus is energizable to provide relative motion between the substrate and the illumination apparatus.

Fabrication of mass-produced electronic items typically involves temperature- and atmosphere-sensitive processing. Conventional material deposition systems for electronic fabrication, including plasma-enhanced chemical vapor deposition PECVD and other vacuum deposition processes, rely on high temperatures and rigidly controlled ambient conditions. Conventional processes are typically subtractive, applying a conductive or other coating over a surface, treating the coating to form a pattern, then removing unwanted material. The conventional method for forming copper traces is one example of this process, requiring multiple processing steps with the use of toxic chemicals and the complications and cost of proper waste disposal.
Recent advances in printed electronics provide solutions that reduce the cost, complexity, and energy requirements of conventional deposition methods and expand the range of substrate materials that can be used. For printed electronics, materials can be deposited and cured at temperatures compatible with paper and plastic substrates and can be handled in air. In particular, advances with nanoparticle-based inks, such as silver, copper, and other metal nanoparticle-based inks, for example, make it feasible to print electronic circuit structures using standard additive printing systems such as inkjet and screen printing systems. Advantageously, nanoparticle-based inks have lower curing temperatures than those typically needed for bulk curing where larger particles of the same material are used.
Commercially available systems for curing nanoparticles typically employ heat from convection ovens or Xenon flash illumination energy. In such illumination systems, the Xenon lamps emit pulsed light that is directed onto films of nanoparticles to be cured. High light energy levels are required for nanoparticle curing. Exemplary nanoparticle-based inks such as Intrinsiq Material Ltd. CI-002, a copper nanoparticle based inkjet ink, or CP-001, a copper nanoparticle-based screen print ink, can be sintered through the use of photonic energy from Xenon lamp or other illumination, provided that the illumination system delivers adequate energy to volatilize coatings used in the ink formulations and to sinter and cure the inks over large surface areas.
Conventional approaches for conditioning of the nanoparticle material, however, suffer from a number of deficiencies. Xenon lamp emission is characteristically distributed over a broad range of wavelengths and often includes wavelengths that can cause unwanted effects, even at non-peak energy levels. This inherent spectral spread in Xenon lamp emission can have effects that result in incomplete or uneven curing. One result can be limited penetration of light energy into thicker films or premature sealing of top surface layers, trapping unwanted organic species in the remaining structure. This type of problem can occur when higher frequency light, such as light energy from the tail of the spectral distribution, inadvertently sinters the film and renders its top layers opaque to other wavelengths of emitted Xenon light, delaying or preventing curing of the lower layers. When this happens, the binder or organic suspension in which nanoparticles are suspended is only partially removed, causing uneven sintering, which can limit the conductivity of the applied materials.
With Xenon light, the distribution of energy intensity is non-symmetrical; the co-lateral dispersive energy that is produced can reduce curing efficiency or may even cause overheating and damage to the substrate. Further, pulsing of the Xenon lamp or other light source tends to create high energy peaks that can ablate films rather than melt and reflow films. As a result, the cured product may not have the desired structure.
Conventional methods are also limited with respect to the number of substrates that can be used. With materials having high thermal conductivity, such as aluminum, silicon, and ceramics, the applied energy intended for curing may dissipate too quickly. With such materials, heat can be drawn away from the area of incident light before sintering occurs. Furthermore, particular wavelengths emitted from the Xenon lamps can damage some polymeric films and other substrates, making them less suitable for curing.
Thus, it can be seen that there is a need for improved methods for sintering and curing nanoparticulate inks and similar materials.

Method for depositing and curing nanoparticle-based ink


A substrate processing apparatus which causes a processing tape to abut against a processing object, including: a tape supply reel configured to supply the processing tape; a tape recovery reel configured to recover the processing tape; a recovery motor configured to apply a torque to the tape recovery reel; a tape feed motor configured to feed the processing tape between the tape supply reel and the tape recovery reel; and a control unit configured to control the tape feed motor, wherein the control unit controls the torque of the recovery motor depending on a change in an outer diameter of a roll of the processing tape wound by the tape recovery reel such that tension applied to the processing tape is constant, using a feed length of the tape fed by the tape feed motor and a thickness of the processing tape.

In a substrate processing apparatus in the related art, a torque of a motor which rotates a tape supply reel (also referred to as a tape supply roller) supplying a processing tape (for example, polishing tape) which is a tape for processing a substrate is controlled such that tension of the tape is constant. For example, in JP 2006-303112 A, it is disclosed that a tape outer diameter detected by a tape outer diameter detection means is sent to a controller of a motor which feeds a tape from a tape supply roller, and thus, a torque value of the motor which feeds the tape from the tape supply roller is smoothly switched continuously, and tension of the tape is constant. Here, the tape outer diameter detection means disclosed in JP 2006-303112 A includes an optical sensor having a light projecting unit and a light receiving unit, and the outer diameter of the tape wound around the tape supply roller is detected by detecting an amount of light received by the light receiving unit.
In addition, in JP 2008-87136 A, it is disclosed that an outer diameter of a roll of a polishing tape is calculated, output torque of a drive motor rotating a tape supply reel and output torque of a drive motor rotating a tape recovery reel are calculated such that tension applied to the polishing tape in a subsequent processing is a predetermined constant value, and both drive motors are controlled such that the output torque is realized. Here, a calculation of the outer diameter of the roll of the polishing tape is performed by changing a tilt angle of a polishing head from 0° to α°, detecting a rotation angle of the tape recovery reel by a rotary encoder, and returning the tilt angle to a standby angle.
However, in the tape outer diameter detection means disclosed in JP 2006-303112 A, it is necessary to provide the optical sensor having the light projecting unit and the light receiving unit, and thus, there are problems that space for installing the light projecting unit and the light receiving unit is required on both sides of the tape supply reel and a cost increases. Moreover, in JP 2008-87136 A, in order to calculate the outer diameter of the tape, it is necessary to tilt the polishing head and detect the rotation angle of the tape recovery reel by the rotary encoder, and thus, there are problems that it is not possible to correctly calculate the outer diameter of the tape during polishing and processing is required between polishing processing.

Substrate processing apparatus and control method


An aminophenolic compound can be synthesized by contacting a halo-nitro-phenolic compound, such as 2-chloro-4,6-dinitrorescorcinol, with a hydrogenating agent, such as hydrogen, and a catalyst, such as palladium-on-carbon, in an aqueous solution in the presence of an acid such as phosphoric acid.

This invention relates to the art of synthesizing aminophenols.
Metal catalyzed hydrogenation of halo-dinitro-dihydroxy benzenes is known to be useful for synthesizing diaminobenzenediols, such as 4,6-diaminoresorcinol, which are useful as monomers for polybenzoxazole polymers. See Lysenko, High Purity Process for the Preparation of 4,6-Diamino-1,3-benzenediol, U.S. Pat. No. 4,766,244 (Aug. 23, 1988) which is incorporated herein by reference. During hydrogenation, the halogen is removed from the aromatic ring as hydrogen halide.
Halogen is difficult to remove by hydrogenation from the aromatic ring of aminophenol compounds when the aminophenol moiety is protonated. Hydrogenation of halo-nitro-phenolic compounds is ordinarily carried out under basic conditions, so that the amine group produced by hydrogenation of the nitro group is not protonated. However, the free base of the aminophenolic product is unstable with respect to oxidation in aqueous media, so the hydrogenation is ordinarily carried out in organic solvents. See U.S. Pat. No. 4,766,244 at column 3, lines 52-59. Organic solvents are very costly to use in commercial scale production. Furthermore, organic solvents can present an undesirable fire risk, particularly in the presence of flammable hydrogenation catalysts and potentially explosive nitrated phenols. What is needed is a high yield process for the synthesis of aminophenolic compounds which can be practiced in an aqueous medium containing either reduced levels of organic solvent or no organic solvent at all.

Aqueous reduction process for halo-nitro-phenols


A magnetic well tubing and pipe protector/fluid ionizer for protecting the interior of pipes from scaling, corrosion, and algae, comprising a case (14) containing four magnetic condensers comprised of rectangular neodymium iron boron magnets (10 . . . ) and tapered concentrators (11 . . . ) which drive magnetic flux through a core (13) into flowing oil, water, or other fluids, ionizing and charging the fluid positive and the core (13) and all connected pumps and tubing negative. The flowing oil or water or other fluid cutting the perpendicular lines of magnetic flux (16) generates an electrical current which charges the pump and tubing or pipe negative enough to repel and prevent scaling, corrosion, and algaes. Also, the electrical current ionizes the oil, water or other fluids, improving separation of crude oil from water and contaminants. improving combustion of petroleum fuels, and increasing the heat transfer coefficient of heating and cooling water.

1. Field of Invention
This invention relates generally to devices for protecting pipes and ionizing fluids, specifically to an improved magnetic oil and water well tubing protection and fluid ionizing device.
2. Prior Art
Oil well pumps and the steel pipe or tubing which carries crude oil to the surface are normally susceptible to scaling, corrosion, and algaes, because of the large amount of high-mineral-content water that normally accompanies the crude oil. As a result, the pumps and tubing become restricted and weakened so that they pump and carry less oil, leak, and even burst. Also, many crude oil deposits are high in paraffin, causing heavy "paraffining" of the pumps and well tubing, which restricts the pumps and tubing, eventually stopping the flow of crude oil from the well.
The major cause of these problems is known as "pipe charging": Fluids running in pipes create a static interface with the inside pipe wall, charging it positive (Helmholtz, 1879; Gouy-Chapman, 1910-1913.)
The primary mineral in hard water is calcium carbonate, which dissolves into the water from limestone deposits in the earth. Calcium carbonate forms a rock-like calcite deposit in oil well and water pumps and oil tubing and all water pipes, and is commonly known as "pipe scale," or "scale." Scale gradually blocks and eventually stops oil and water pumps and well tubing and water pipes. Also, water itself causes problems. The water molecule is dipolar, with the hydrogen side positive and the oxygen side negative. The oxygen in water causes rust or corrosion in oil well and water pumps, well tubing, and water pipes, eventually weakening them until they leak or burst.
Paraffin is a wax that is common in most crude oils. Paraffin forms hard waxy layers inside oil well pumps and tubing. This growing restriction slows and eventually stops the pump and the flow of oil, in the tubing. Algaes that grow in water and oils stick on metal surfaces, grow slime and restrict flow, while digesting the iron and sulphates in the metals, causing "microbiological corrosion."
Toxic chemicals, solvents, and hot oil are normally used to combat these problems in oil wells. Such toxic chemicals, usually acids and expensive biocides, are generally added to water systems to prevent or dissolve these damaging deposits. While these chemicals and processes are marginally successful, they are very expensive and they are harmful to humans and the environment.
Magnetic devices have been used for preventing scaling, corrosion, and algae growth in pipes. U.S. Pat. No. 2,652,925 to Vermeiren (1949), U.S. Pat. No. 4,210,535 to Risk (1980), U.S. Pat. No. 4,265,746 to Zimmerman, Sr. et al. (1981), U.S. Pat. No. 4,265,754 to Menold (1981), and U.S. Pat. No. 4,265,755 to Zimmerman (1981), and International Application PCT/US81/00304 to White Light Industries (1981) show magnetic devices which fit around water pipes. These comprise a plurality of magnets with opposite poles spaced axially along the pipes. These magnets can project magnetic fields into nonferrous pipes only. The flux lines are generally parallel to the direction of water flow. According to the Faraday effect, a conductor--which in this case is the water--cuts magnetic flux lines and generates an electrical current in the conductor. However, because no current can be generated by a conductor that moves parallel to the flux lines, these devices did not generate any current. Also, these devices did not project magnetic flux lines through steel pipe walls, nor could they be fitted between well tubing and casing under a pump and sent to the bottom of a well. These factors rendered them ineffective and impractical for charging any commonly used pipe walls and well tubing negative. Since all of the damaging materials, in oil and water wells--carbonates, oxygen, algaes, and paraffin--are negative, a sufficient negative charge on the oil and water well pumps, valves, tubing and pipes, will protect them.

Apparatus for magnetically treating a fluid


Disclosed herein are methods of treating or preventing complications associated with a SARS-CoV-2 infection, comprising: administration of a combination comprising: a) Green Tea and/or extract thereof; b) Blueberry and/or extract thereof; c) Nigella sativa and/or extract thereof; and d) broccoli and/or extract thereof in an amount and frequency sufficient to treat or prevent complications associated with said SARS-CoV-2 infection.

SARS-CoV-2, the viral pathogen causative of COVID-19, is a novel coronavirus that is most phylogenetically similar to SARS. The virus is presumed to have initially been transmitted from an animal reservoir (bats) to humans, most likely via an amplifying host (pangolin) [1, 2]. It is a single strand positive sense RNA virus whose infectivity is mediated by the envelope spike (S) glycoprotein which binds to its cellular receptor angiotensin-converting enzyme 2 (ACE2) [3]. Interestingly, antibody responses have also been detected towards the S glycoprotein [3-6].
It is known that Coronaviruses (CoVs) belong to a subfamily of large and enveloped viruses containing a single strand of sense RNA. There are four genera, of CoVs, i.e., alpha, beta, gamma, and delta, of which alpha- and beta-CoVs are known to infect humans [7]. Infectivity of CoVs is mediated by the envelope spike (S) glycoprotein which binds to its cellular receptors angiotensin-converting enzyme 2 (ACE2) and dipeptidyl peptidase 4 (DPP4) for SARS-CoV and MERS-CoV, respectively, this facilitates fusion of the virus with the membrane [8, 9]. The viral RNA genome is released into the cytoplasm; after replication of the viral genome, genomic RNA accompanied by envelope glycoproteins and nucleocapsid proteins forms virion-containing vesicles, which then fuse with the plasma membrane to release the virus [10]. The viral cause of COVID-19 is attributed to the SARS-CoV-2 type of CoV, which was found to be a new type of beta-CoV with more than 99.98% genetic identity among 10 sequenced samples collected from the original site of the outbreak [11]. SARS-CoV-2 is genetically more similar to SARS-CoV than to MERS-CoV [12].
Subsequent to the virus binding to the target cells, which appear to be primarily type 2 pulmonary epithelial cells, the virus fuses with the cellular membrane, allowing viral entry into the cytoplasm [13]. Once the viral genome is unleashed in the cell, it replicates and the viral RNA accompanied by envelope glycoproteins and nucleocapsid proteins form virion-containing vesicles, which then fuse with the plasma membrane to release the virus [14].
At a clinical level, the usual presentation of COVID-19 is pneumonia, as demonstrated by computer tomographic (CT) scan or chest X-ray and fever. At the beginning phases of the infection, the patients showed the acute respiratory infection symptoms, with some that quickly developed acute respiratory failure (ARDS) and other serious complications [15]. The original patients that were published from the China Novel Coronavirus Investigating and Research Team all developed severe pneumonia and two of these three patients with available clinical profiles showed a common feature of fever and cough [13].
After this, another study of a family of six patients in the University of Hong Kong-Shenzhen Hospital demonstrated that all of them had pulmonary infiltrates, and other flu-like characteristics [16]. The chest X-ray and CT imaging in a study showed that 75% of 99 patients possessed bilateral pneumonia and the remaining 25% unilateral pneumonia [17]. In total about, 14% of the patients showed multiple mottling and ground-glass opacity [17]. The first cases of coronavirus infection in the United States also showed basilar streaky opacities in both lungs by chest radiography. However, the pneumonia for this patient was only detected on the day 10 of his illness[18].
As reviewed by Zheng [1], identifiable characteristics of COVID19 patients are fever and cough, with fatigue in 96% of patients (n=138) in one study, but was less outstanding (18%, n=44) in another report. Overall analysis revealed that fever was observed in around 90% whereas cough is relatively less at 68%, and shortness of breath, muscle ache, headache, chest pain, diarrhea, haemoptysis, sputum production, rhinorrhoea, nausea and vomiting, sore throat, confusion, and anorexia were also observed in an numerous patients.
Currently no interventions have demonstrated efficacy in double blind trials, however multiple approaches are in development. These can be categorized into a) antigen specific vaccines [19-22]; b) innate immune stimulators [23-25]; c) small molecule antivirals; d) small molecules which modulate viral interactions with host cells [26-29]; e) plasma/antibodies from patients who recovered [30-40]; f) small molecule blockers of cytokine signaling [41-44]; g) antibodies to inflammatory cytokines [45-53]; and h) cell based therapies [54-64].
At present there appears to be no clear consensus on which approaches are most promising, with various institutions utilizing differing protocols. It is expected that clinically significant signals will be reported in up to 18 months from now. In the absence of established pharmaceutical approaches, exploration of scientific based natural based treatments may have merit.

Nutraceuticals for the prevention, inhibition, and treatment of SARS-CoV-2 and associated COVID-19

Therapeutic Solutions International, Inc.


A process for integrating an alignment mark and a trench device. A substrate having first and second trenches is provided. The second trench is used as the alignment mark having a width larger than the first trench. The trench device is formed in each of the low portion of the first and second trenches, and then a first conductive layer is formed on the trench device in each of the first and second trenches. A second conductive layer is formed overlying the substrate and fills in the first trench and is simultaneously and conformably formed over the inner surface of the second trench. The second conductive layer and a portion of the first conductive layer in the second trench are removed and simultaneously leave a portion of the second conductive layer in the first trench by the etch back process.

1. Field of the Invention
The present invention relates in general to a semiconductor process. More particularly, it relates to a simplified process for integrating an alignment mark and a trench device to reduce fabrication cost.
2. Description of the Related Art
Lithography is one of most important processes for fabricating semiconductor integrated circuits. Lithography is used in the transfer of a pattern onto a thin film or the fabrication of a mask for ion implantation. In general, lithography is conducted many times in the production of is semiconductor circuits. In a lithography step, however, one critical factor is pattern alignment. When a wafer is processed to form patterns in the different thin films deposited thereon, the wafer must be properly aligned relative to the previous pattern. Conventionally, an alignment mark (AM) is used for alignment before carrying out photo-exposure.
In general, alignment marks are formed outside the device region, such as the scribe line of a wafer, at the same time as a thin film such as an insulating layer or a conductive layer is patterned. FIGS. 1a to 1d are cross-sections showing a conventional process for integrating an alignment mark and a trench device. First, in FIG. 1a, a substrate 100, such as a silicon wafer, is provided. The substrate 100 has a device region 10 and an alignment mark region 20 which is at the scribe line of the wafer 100.
Next, a patterned masking layer 105 is formed on the substrate 100. The patterned masking layer 105 can be composed of a pad oxide layer 102 and a thicker overlying silicon nitride layer 104. Next, the substrate 100 is etched using the patterned masking layer 105 as an etch mask to form deep trenches 110a and 110b therein. The deep trench 110a is on the device region 10 and the trench 110b having a width larger than the deep trench 110a is on the alignment mark region 20.
Next, trench capacitors 118a and 118b are respectively formed in the lower portion of the deep trenches 110a and 110b. The trench capacitor 118a includes a top plate 116a, a capacitor dielectric layer 114a, and a bottom plate 112a. Also, the trench capacitor 118b includes a top plate 116b, a capacitor dielectric layer 114b, and a bottom plate 112b. Next, collar insulating layers 117a and 117b are respectively formed on the trench capacitors 118a and 118b and over the sidewall of the deep trenches 110a and 110b. Thereafter, conductive layers 120a and 120b, such as polysilicon, are respectively formed in the deep trenches 110a and 110b, which have a height substantially equal to the collar insulating layers 117a and 117b.
Next, a conductive layer 122, such as polysilicon, is formed on the masking layer 105 and fills in the deep trenches 110a and 110b.
Next, in FIG. 1b, chemical mechanical polishing (CMP) is performed on the conductive layer 122 to respectively leave a portion of the conductive layers 122a and 122b in the deep trenches 110a and 110b.
Next, in FIG. 1c, the conductive layers 122a and 122b are etched to leave a portion of the conductive layers 124a and 124b in the deep trenches 110a and 110b, respectively. The conductive layer 120a and the remaining conductive layer 124a in the deep trench 110a are used as a wiring layer for the trench capacitor 118a. In addition, the trench capacitor 118b, the conductive layer 120b, and the remaining conductive layer 124b are used as an alignment mark.
Since the trench capacitor 118b and the conductive layers 120b and 124b are formed in the deep trench 110b, the step height of the substrate 100 on the alignment mark region 20 is reduced, lowering the image contrast of the alignment mark.
Accordingly, in FIG. 1d, a patterned photoresist layer (not shown) is formed on the masking layer 105 by lithography to completely cover the deep trench 110a and expose the deep trench 110b only. Thereafter, the conductive layer 124b is completely removed and then the underlying conductive layer 120b and the collar insulating layer 117b are partially removed by etching using the patterned photoreist layer as a mask to leave a portion of the conductive layer 120c and the collar insulating layer 117c, thereby increasing the step height of the substrate 100 on the alignment mark region 20. However, such a process is complex, thus increasing fabrication cost and the time required thereby.
Accordingly, an object of the present invention is to provide a novel process for integrating an alignment mark and a trench device, thereby simplifying the process to reduce fabrication cost and time and increase throughput.
According to the object of the invention, a process for integrating an alignment mark and a trench device are provided. First, a substrate having first and second trenches is provided, wherein the second trench used as the alignment mark is wider than the first trench. Next, the trench device is formed in each of the low portions of the first and second trenches, and then a first conductive layer is formed on the trench device in each of the first and second trenches. Thereafter, a second conductive layer is formed overlying the substrate filling in the first trench and is simultaneously and conformably formed over the inner surface of the second trench. Finally, the second conductive layer and a portion of the first conductive layer in the second trench are removed and simultaneously leave a portion of the second conductive layer in the first trench by an etch back process, wherein the etch back process employs chemical mechanic polishing to remove the second conductive layer overlying the substrate.
Moreover, the first and second conductive layers can be a polysilicon layer, which have a thickness of about 2000xc3x85 to 4000xc3x85.

Process for integrating alignment mark and trench device