A power supply voltage control apparatus capable of freely setting a clock period setting margin according to a system clock frequency, and capable of converging power supply voltage to minimum power supply voltage where normal operation is possible in a short period of time without errors in operation of internal circuits in response to changes in the system clock frequency is provided. Power supply voltage control apparatus 100 is provided with frequency-dividing circuit 121 that frequency-divides the system clock at frequency-dividing ratio 1, frequency-dividing circuit 122 that frequency-divides the output of voltage control oscillator circuit 110 at frequency-dividing ratio 2, phase comparator/frequency comparator 130 that carries out phase comparison/frequency comparison on the respective output signals of frequency-dividing circuits 121 and 122, and controller 145. Frequency-dividing ratios of frequency-dividing circuits 121 and 122 are set by control circuit 141 according to an operation mode signal corresponding to the system clock frequency.

1. Field of the Invention
The present invention relates to a power supply voltage control apparatus that controls power supply voltage of a semiconductor integrated circuit apparatus such as an LSI (Large Scale Integration)
2. Description of the Related Art
In recent years, as important methods for reducing power consumption of the semiconductor integrated circuit, methods of changing power supply voltage according to clock frequencies are well-known. However, when the accuracy of power supply voltage setting is coarse, or, when a power supply voltage setting circuit is temperature dependant, errors in circuit operation may occur as a result of timing errors by reducing power supply voltage too low. Further, there are also cases where timing errors may occur as a result of decrease of the driving performance of a MOS transistor due to temperature fluctuation, and may lead errors in circuit operation.
With regards to this problem, conventionally, a voltage generating circuit technology is disclosed that is capable of generating the minimum required operation power supply voltage in a predetermined clock frequency. For example, as shown in FIG. 10, Patent Document 1 (Japanese Patent Application Laid-Open No. Hei. 9-285109) discloses a semiconductor apparatus having: a logic circuit that operates using first power supply voltage; a voltage control oscillator section that generates a clock signal of a frequency corresponding to second power supply voltage; a phase comparator that compares phases of the clock signal and a reference clock signal; a low pass filter section that smoothes an input signal using an integrating circuit; a charge pump section that charges and discharges the low pass filter section using the result of the phase comparison; and an internal power supply voltage generating section that generates the first power supply voltage of a level corresponding to output of the low pass filter section, wherein the first and second power supply voltages causing the logic circuit and the clock generating section to operate are shared and supplied from the power supply voltage generating section.
Further, as shown in FIG. 11, Patent Document 2 (Japanese Patent Application Laid-Open No. Hei. 10-49242) discloses, in place of the voltage control oscillator section of Patent Document 1, a power supply generating circuit that performs phase comparison between a clock signal subjected to gate delay at a voltage control delay circuit and an original clock signal, generates a voltage signal using an integrator and a buffer, feeds this back to the voltage control delay circuit as operating power supply voltage, and generates internal power supply voltage using the buffer and PchMOS transistor.
Further, as shown in FIG. 12, in order to provide versatility to the voltage control delay circuit having various delay values in Patent Document 2, Patent Document 3 (Japanese Patent Application Laid-Open No. 2002-100967) discloses a power supply voltage control apparatus provided with an input signal generating circuit that is capable of changing, upon generation of a reference signal inputted from a clock signal to a delay detection circuit and an input signal inputted to a voltage control delay circuit, a phase difference between both signals according to a control signal.
Moreover, as shown in FIG. 13, Patent Document 4 (Japanese Patent Application Laid-Open No. 2000-216337) discloses a power supply voltage control apparatus having: a semiconductor circuit; a replica circuit that monitors delay time of a critical path of the semiconductor circuit; a control circuit that sets a level control signal so that an initial value of power supply voltage becomes a minimum limit power supply voltage value where the semiconductor circuit is capable of operating properly, and setting the level control signal after start-up so as to obtain the power supply voltage value based on a monitor apparatus of the replica circuit; and a power supply voltage generating circuit that generates a power supply voltage according to the level control signal and supplying the voltage to the semiconductor circuit and replica circuit, and thereby enabling convergence time and stable operation upon start up of the power supply.
However, the conventional power supply voltage control apparatuses have the following problems.
The apparatus disclosed in Patent Document 1 sets a period of the reference clock signal inputted to the phase comparator as, for example, one period of the system clock signal. Further, the voltage control oscillator circuit is configured with a fixed number of stages of inverter circuits and critical path replicas, and therefore the period of the clock signal outputted from the voltage control oscillator circuit is equal to the period of the reference clock signal regardless of the frequency of the reference clock signal.
Similarly, the apparatuses disclosed in Patent Documents 2 and 4 set a period of the reference clock signal inputted to the phase comparator as, for example, one period of the system clock signal as with Patent Document 1. Further, the voltage control delay circuit is configured with a fixed number of stages of inverter circuits, and therefore a delay value generated by the voltage control delay circuit is equal to one period of the reference clock signal regardless of the frequency of the reference clock signal.
However, the power supply voltage control circuit takes a certain amount of time from when the power supply voltage is applied and a lag of phase or frequency between the clock output signal of the voltage control oscillator circuit and the reference clock signal is detected till when control actually operates and corrected power supply voltage is applied, and therefore the power supply voltage fluctuates. Moreover, the fluctuation value of the power supply voltage is substantially fixed regardless of the level of the power supply voltage. Therefore, fluctuation values of a maximum system clock frequency where normal operation is possible at the internal circuit with respect to the fluctuation value of the supply power voltage when the supply voltage is small and a clock frequency of the voltage control oscillator circuit, are larger than a fluctuation value of the respective clock frequencies with respect to the fluctuation value of the power supply voltage when the power supply voltage is large.
The reason for this is that the respective clock frequencies are substantially decided by the driving performance of the MOS transistor—the drain current—, and proportional to the square of a value in which the threshold voltage is subtracted from the gate voltage as expressed by the following equation.IDS=α(VGS−Vt)2  (1)
For example, when MOS transistor threshold voltage is 0.5V and a power supply voltage fluctuation value is 0.05V, drain current ratio is 1.07 times between power supply voltages of 2.0V and 2.05V, but between power supply voltages of 1.0V and 1.05V, the drain current ratio becomes 1.21 times.
Therefore, the first problem is that, though it is necessary to change a setting margin of a period of a clock signal outputted from the voltage control oscillator circuit or a delay value generated by the voltage control delay circuit and a period of the reference clock signal with respect to the minimum power supply voltage corresponding to the system clock frequency, Patent Documents 1, 2 and 4 cannot be compatible with this, since the setting margin is fixed.
Further, the apparatus of Patent Document 3 incorporates an input signal generating circuit capable of, when the reference signal and input signal are generated from the inputted clock signal, changing a phase difference between both signals according to a control signal. However, the input signal generating circuit is shared with a monitor circuit having various delay values compatible with functions of the semiconductor circuit, and does not function for changing the clock period setting margin according to the above-described system clock frequency. Further, the input signal generating circuit is configured with a PLL (Phase-Locked Loop) and selector, and therefore the problem arises that circuit scale increases substantially.
The apparatus of Patent Document 4 sets the level control signal so that the initial value becomes a start-up minimum power supply voltage, and, upon start-up of the semiconductor circuit, time for the power supply voltage to converge to an optimum value can be reduced However, the setting of the level control signal is only considered upon start-up of the power supply, and therefore the apparatus cannot be compatible with switching of a plurality of system clock frequencies. Namely, the second problem is that, when the system clock frequency is changed from a high frequency to a low frequency, first, the system clock frequency changes, and the power supply voltage is adjusted to be small according to this frequency, but, when the change in frequency is large, the change in power supply voltage also becomes large, and it takes a great deal of time to converge the power supply to the minimum power supply voltage for normal operation. Further, when the system clock frequency is changed from a low frequency to a high frequency, if the system clock frequency increases before the power supply voltage increases, a problem of inviting errors in the internal circuit operation arises.


A structure for a flip chip package assembly includes: a flip chip die with solder attach bumps; a substrate for receiving and solder attaching the flip chip die; an underfill material with spatially varying curing properties applied to fill voids between the flip chip die and the substrate, and for forming a fillet around the perimeter of the flip chip die and extending to the surface of the substrate; and wherein the portion of the underfill material forming the fillets is cured prior to curing the portion of the underfill material that fills the voids between the flip chip die and the substrate.

1. Field of the Invention
This invention relates generally to flip chip technology, and more particularly to providing a structure and method for reducing internal package stresses and improving module coplanarity in flip chip packages by spatially varying underfill properties.
2. Description of the Background
The packaging industry has adopted the widespread use of flip chip technology for high performance applications, at the expense of other packaging solutions, such as wirebonding, which do not offer the same level of interconnect density, electrical performance, or thermal management capabilities. In a flip chip package, the semiconductor die is bumped with individual conducting pads over its entire area. These pads are connected to corresponding pads on a substrate using small solder balls, called controlled collapse chip connections (C4). The pads on the substrate are connected to circuitry that routes the electrical signals to an array of conductors (ball grid arrays (BGA), column grid arrays (CGA) or land grid arrays (LGA)) for the connection to the printed circuit board. The backside of the die is exposed in a flip chip package, and is available for establishing a thermal connection to a heat sink in order to control the die temperature. Flip chip packages with high interconnect counts (about 9000) and large thermal power dissipation capabilities (about 200 W) are currently available.
Recent years have witnessed important changes in the flip chip technology, such as the change from ceramic substrates to lower cost, higher performance organic substrates, and the transition to lead-free soldering alloys. Semiconductor technologies have also been evolving rapidly, with smaller feature sizes, and lower-K dielectric materials, for instance. Many interactions between these changing parameters have been observed to lead to important failure mechanisms that had to be fixed in order to preserve the package reliability. Further, the aforementioned interconnect counts in flip chip packaging continues to increase, resulting in smaller interconnects and larger die, both of which increase the stresses imparted on the interconnections.
The open spaces between the flip chip surface and the substrate is filled with a non-conductive adhesive "underfill" material to protect the bumps (C4 interconnections) and the flip chip surface from moisture, contaminants, and other environmental hazards. More importantly, this underfill material mechanically locks the flip chip surface to the substrate, thereby reducing the strains imposed on the small C4 interconnects by the difference between the coefficient of thermal expansion (CTE) of the flip chip and the substrate. The underfill consequently prevents the C4 interconnects from being damaged during thermal excursions of the module. Flip-chip underfilling is generally achieved by needle dispensation along the edges of the flip-chip. Capillary action draws the dispensed underfill inwards, until the open spaces between the C4 interconnects are filled. Thermal curing of the underfill is performed to form a permanent bond.
The underfill coupling of a chip to a substrate is normally performed at high curing temperatures (approximately 150° C.), where both the chip and the substrate are relatively flat and stress free. During the cooling of the package back to room temperature, differences in CTE between chip and substrate result in different changes in dimension from thermal contraction. This leads to package warpage, and to stress in various critical structures (C4 interconnects, laminate copper structures, etc.). When the substrate is an organic laminate, the differences in CTE are especially significant, exacerbating these problems, especially in areas furthest from the chip geometrical center (the neutral point). Organic laminates typically have CTE's of about 15-20 ppm/° C. or larger, while the CTE of a typical semiconductor die is in a range of less than 5 ppm/° C.
FIG. 1A is a cross sectional view of a typical flip chip assembly 100 with a die 102 attached with C4 interconnections 106 to a substrate 104. A heat cured underfill material 108 fills the spaces between the C4 interconnections 106 in the gap between the die and substrate, and also forms a fillet 110 around the perimeter of the die 102. At room temperature the die 102 has a side length defined as 1, and the substrate 104 has a side length defined as L. FIG. 1B is a cross sectional view of the ball grid array assembly 100 at an elevated temperature for curing the underfill 108. At the elevated curing temperature, the length 1 of the die 102 increases to 1′, and the length L of the substrate 104 increases to L′. However, due to the greater overall increase in length L′ versus length 1′ resulting from the substrate having a larger CTE than the die, a warping results in the assembly 100 as it cools down to room temperature after the underfill curing at the elevated temperature. FIG. 1C illustrates the warpage, in an exaggerated manner, as the assembly 100 returns to room temperature, and the substrate 104 and die 102 undergo different amounts of thermal contraction. Therefore, there is a need for structures and methods for mitigating the warpage of flip package assemblies due to the high temperature curing of the underfill material.

Structure and method for stress reduction in flip chip microelectronic packages using underfill materials with spatially varying properties

International Business Machines Corporation


The use of liquid metal contacts for devices based on thermotunneling has been investigated. Electric and thermal characteristics of low wetting contact Hg/Si, and high wetting contacts Hg/Cu were determined and compared. Tunneling I-V characteristics for Hg/Si were obtained, while for Hg/Cu, I-V characteristics were ohmic. The tunneling I-V characteristic is explained by the presence of a nanogap between the contact materials. Heat conductance of high wetting and low wetting contacts were compared, using calorimeter measurements. Heat conductance of high wetting contact was 3-4 times more than of low wetting contact. Both electric and thermal characteristics of liquid metal contact indicated that it could be used for thermotunneling devices. To reduce the work function and make liquid metal more suitable for room temperature cooling, Cs was dissolved in liquid Hg. Work function as low as 2.6 eV was obtained.

This invention relates to tunnel junctions.
In recent years, much work has been done on using electron tunneling for cooling applications. The first theoretical investigation of cooling by means of electron tunneling was done to deal with overheating in single electron transistors [A. N. Korotkov, M. R. Samuelsen, S. A. Vasenko, "Effects of overheating in a single-electron transistor," J. Appl. Phys., 76 (6), p. 3623-3631, (1994)]. Inside the metal/insulator/metal (MIM) tunnel junction, electron tunneling takes place through an insulator layer, but because of the high thermal conductivity of ultra-thin insulator layer, the MIM junctions exhibited large heat backflow, which reduces cooling efficiency. Huffmann (U.S. Pat. No. 3,169,200) attempted a solution to the heat backflow problem, using multiple MIM tunnel junctions connected in series. However, a device of this type could not be fabricated because of its technological complexity. The present inventors have designed tunnel junctions of metal/vacuum/metal (MVM) type, having very low heat backflow [A. Tavkhelidze, G. Skhiladze, A. Bibilashvili, L. Tsakadze, L. Jangidze, Z. Taliashvili, I. Cox, and Z. Berishvili, Proc. XXI International Conf. on Thermoelectric, August 26-29 IEEE, New York, pp. 435-438 (2002); L. B. Jangidze, A. N. Tavkhelidze, M. O. Tetradze and T. N. Devidze, "Methods for improving surface flatness in thick Cu film electrodeposition", Russian Microelectronics, Vol. 36 (2), p. 116, (2007)]. Such tunnel junctions may be used for efficient cooling. A theoretical investigation of MVM tunnel junctions has shown that the cooling coefficient could be as high as 20-30% [Y. Hishinuma, T. H. Geballe, B. Y. Moyzhes, and T. W. Kenny, Appl. Phys. Lett. 78, 2572 (2001); T. Zeng, Appl. Phys. Lett. 88, 153104 (2006)]. An approach using emission from semiconductor resonant states across a vacuum gap has also been proposed [A. N. Korotkov and K. K. Likharev, Appl. Phys. Lett. 75, P. 2491-2493 (1999)].
Most cooling applications require tunnel junctions with a large area—of the order of square centimeter and more. The electrodes for tunnel junctions should be flat within few Angstroms to allow fabrication of uniform vacuum nano gap. Available polishing methods allow fabrication of surfaces with local roughness of 0.2 nm. However gradual deviation in the surface relief over large distances is as high as 500 nm per centimeter. The local roughness (0.2 nm) is low enough to obtain local vacuum tunneling, but because of a gradual deviation in the surface relief, it becomes impossible to bring large areas of two electrodes (polished independently) close enough to each other.

Liquid metal contact as possible element for thermotunneling


An entertainment management system for the gaming industry provides real-time multi-site, slot accounting, player tracking, cage credit and vault, sports book data collection, and table game accounting.

The present invention relates generally to an entertainment management system for use in gaming environments such as casinos. The growth and competition in the casino gaming market in recent years and the increasingly sophisticated and complex technology being integrated into the gaming environment, at the individual game, casino management, and auditing levels, presents both challenges and opportunities to game manufacturers, gaming establishment operators, and regulatory agencies. The technological capabilities and requirements of, for example, advanced electronic games, multi-site gaming operations, detailed player tracking, wide area progressive jackpots, and various alternatives to the use of currency and coins by players, all present a potentially huge pool of ever-changing data which can be of great value to casino operators (from a management standpoint) and to regulators from an audit/compliance standpoint.
Given the value of such information to operators and regulators alike, there is an ever-increasing need for an expandable, flexible system which can efficiently, accurately, and in a real-time manner capture, access, accumulate, and process this potentially vast volume of audit, player, and other operations/management data being generated throughout the gaming environment. In turn, there is a corresponding need for a system which can efficiently, accurately and in a real-time manner share, communicate and distribute such information amongst other devices, networks, and systems within the gaming environment. Similarly, there is also the need for a system which can efficiently, accurately, and in a real-time manner analyze, manage, communicate, display, and otherwise report and allow ready access to such data for use by management and regulators.
Existing gaming management systems are, however, cumbersome in their implementations. They are often inefficient in, or incapable of, accumulating and/or processing the vast amount of data generated in a modern gaming environment. They are similarly often inefficient in, or incapable of, sharing, distributing, and communicating the data collected amongst other devices, networks, and systems within the gaming environment in a timely fashion, and, in particular, in a real-time manner. In addition, they are often inefficient, confusing, and burdensome insofar as providing for the display, presentation, or reporting of data to management or regulators, and, in particular, doing so in a real-time manner. Moreover, current systems often utilize hardware or software implementations which are limited in terms of expandability and capability as the needs and demands of the system grow. It is thus desirable to have a system which addresses the shortcomings of the current systems, and which provides additional features not available in existing systems.

Entertainment monitoring system and method


A compactor for use in compacting at least two separate classes of material comprises a charging box, a storage container and a packer ram. The charging box is internally, longitudinally divided into at least first and second charging chambers, each charging chamber having a charging opening and a discharging opening. The storage container is internally divided into at least first and second storage chambers and each chamber has a material receiving opening in communication with a respective discharging opening of the charging box. The storage container is releasably fixed relative to the charging box. The packer ram has at least first and second compacting faces, in a first configuration each face forming a portion of a wall of a respective charging chamber opposite the discharging opening, the faces being mounted to a common actuator and movable from the first configuration across the charging chambers to simultaneously push material from the charging chambers through the discharging openings and into the respective storage chambers. Different classes or grades of material, such as recyclable and non-recyclable garbage, may thus be compacted and stored separately using a single compactor apparatus.

Existing garbage compactors are typically formed as a single metal container connected to a compacting unit. The compacting unit includes a charging box in communication with the container, a ram being provided for pushing garbage which has collected in the charging box into the container. In many malls, offices and factories, compactors are provided for receiving a particular form of waste, for example, corrugated cardboard, which is collected for recycling. At some sites only a single compactor will be provided at a site, and other forms of garbage may be thrown into the charging box with the corrugated cardboard. This may result in the loss of the entire load of the filled container for recycling, and such contamination of a load is often not discovered until the container load of material has been taken to a recycling depot and unloaded. If the material has been spoiled, it is necessary to reload the container and transport the material to another site for, for example, incineration or disposal in a landfill site. In addition to the loss of the recyclable material, there is also a considerable expense in transporting the material and there will likely be a charge for disposing of the material.


An insulated organic copolymer is provided, having the excellent mechanical strength and deposition property at an interface contacting the lower base or the upper layer of the inorganic insulation film, and the effective dielectric constant is low as the whole film, which is suitable as the interlayer insulation film that separates the multi-layer copper wirings of the semiconductor device. The organosiloxane copolymer film is obtained by the polymerization of the cyclosiloxane and the straight-chain siloxane as the raw materials by the plasma excitation of both. At the interfaces contacting the inorganic insulation films, the interface layers having a film quality that is intricate and excellent in deposition property are prepared whereby the main component of the film composition is the straight-chain siloxane. The inner section of the copolymer film mixes the cyclosiloxane component having pores surrounded by the cyclosiloxane backbone and the straight-chain siloxane components, has the network structure layer relatively suppressing the density, and has the composition changing in the thickness direction whereby the multi-layer wirings embedding the copper thin film is formed.

The design rule of a semiconductor integrated circuit is continuously being shrinked, accompanied by the performance deterioration due to wiring delay which is becoming prominent. That is, a wiring signal delay of a semiconductor integrated circuit is determined by a wiring CR time constant (C: wiring capacity, R: wiring resistance). Because of the increase in wiring resistance due to the decrease in a wire width and the increase in a capacity due to the decrease in a gap between wires, there is a danger that the wiring CR time constant may not catch up with the improvement in switching speed of transistors. Conventionally, an aluminum alloy was mainly used as a wiring material of a semiconductor integrated circuit. However, a copper wiring has been used in an integrated circuit requiring high-speed operation for a purpose of decreasing the resistance in a wiring.
In order to reduce the capacitance between wirings, an insulation film material that has a lower dielectric constant than the currently used silica (SiO2) is beginning to be adopted. As an insulation film having a low dielectric constant, a fluorine-containing silica (SiOF), a porous silica, and an organic polymer film (organic insulation film) are known. The fluorine-containing silica is already being used in part of some products, however, if the fluorine concentration inside the film is increased for promoting a low dielectric constant of the film itself, the problem of corrosion of a wiring metal occurs with hydrofluoric acid generated from a reaction with moisture or hydrogen, or the problem of the increased dielectric constant occurs by desorption of fluorine. Furthermore, as the technology of the semiconductor integrated circuit progresses, the fluorine-containing silica film (SiOf) providing the dielectric constant of 3.3 can no longer meet the requirement of the insulation film. The insulation film that does not contain fluorine and has the dielectric constant of 3 or less is in high demand as the interlayer insulation film of the multi-layer wirings. As one of the candidates, the organosiloxane copolymer film having excellent properties both in heat and moisture resistance has been in urgent demand for development. Conventionally reported methods of forming the organosiloxane copolymers are broadly classified to the spin coating method and the CVD method.
1. First Related Art
In the spin coating method, a raw material organosiloxane monomer is dissolved in an organic solvent. The spin-coated film is formed, the solvent is removed during the film formation, the organosiloxane monomer inside the coated film is heated, and a polymerization reaction of the monomer proceeds. Consequently, a two-dimensional or three-dimensional network structure polymer film is formed by the thermal polymerization reaction. A backbone configuring the organosiloxane copolymer film which is the product, depends on the structure of the organosiloxane monomer dissolved in the organic solvent.
For example, according to "REAL-TIME FT-IR STUDIES OF THE REACTION KINETICS FOR THE POLYMERIZATION OF DIVINYL SILOXANE BIS BENZOCYCLO BUTENE MONOMERS" (material Research Symposium Proceeding vol, 227, p, 103, 1991), by T. M. Stokich, Jr., W. M. Lec, and R. A. Peters discloses the method of forming an organosiloxane polymer film. After dissolving a divinylsiloxane-bisbenzocyclobutene (BCB-DVS) monomer which is one type of the straight-chain siloxane in a mesitylene which is spincoated, the mesitylene in the solvent is removed by baking at 100 degrees Celsius, and the residue was further heated up to 300 degrees Celsius to 350 degrees Celsius to obtain the organosiloxane polymer film. A divinylsiloxane-bisbenzocyclobutene monomer, as shown in chemical formula (1) below, is an organosiloxane monomer that includes 2 vinyl groups and 2 cyclobutene groups which are unsaturated hydrocarbon chains, and the straight-chain siloxane. Its thermal polymerization reaction is progressed as follows.
Chemical Formula (1): divinylsiloxane-bisbenzocyclobutene
First of all, accompanied by the reaction of chemical formula (2) shown below, the cyclobutene group inside the divinylsiloxane-bisbenzocyclobutene monomer undergoes thermal ring-opening polymerization reaction by thermal energy, and changes to 2 vinyl groups (methylene groups).
Chemical Formula (2): Ring-Opening Reaction of Benzocyclobutene Group
Accompanied by the reaction of chemical formula (3) shown below, 2 vinyl groups (methylene groups) react to another vinyl group inside the BSB-DVS monomer to form the 6-membered hydrocarbon (dihydronaphthalene) so that the polymerization reaction is generated. From this reaction path, a dimer that connects 2 BSB-DVD shown in chemical formula (4) below, is obtained.
Chemical Formula (3): Addition Polymerization Reaction of Vinyl Group and Open-Ring Group of Benzocyclobutene Group.
Chemical formula (4): divinylsiloxane-bisbenzocyclobutene Dimer
Inside the dimer of BCB-DVS to bc synthesized, 3 unreacted benzocyclobutenes and 3 vinyl groups remain. That is, at least 6 BCB-DVS monomers and the dimer may further undergo addition polymerization. If a mobility of the divinylsiloxane-bisbenzocyclobutene is sufficiently large, then a complex and intricate polymer film where the BSB-DVS are bridged to one another is formed as shown in chemical formula (5).
Chemical Formula (5): Organic Polymer Film Synthesized by Addition Polymerization of divinylsiloxane-bisbenzocyclobutene (BSB-DVS)
However, as for the polymer formation by using the spin coating method, a BSB-DVS monomer is being dissolved in a solvent, but, if the monomer concentration increases accompanied by the evaporation of the solvent, the viscosity is increased, and the monomer mobility gets less. In other words, although there are total of 4 sites available for addition polymerization in the BSB-DVS monomer itself, it can only bond to a few BSB-DVD nearby. Because of this, the polymer formation by using the spin coating method cannot attain a sufficient bridge density. Incidentally, there was a problem of deterioration in thermal resistance of the obtained polymer film, and a problem of decline in the film strength. Furthermore, the spin coating method in this case dissolves the organic monomer to a solvent, and the dissolved solid is spin coated. However, the spin coating process has a drawback that the yield of the starting raw material is low because about 90% of the dissolved material is scattered from the substrate. Moreover, the method of heating a spin-coated film in a baking furnace thereby to remove a solvent beforehand, and further heated at high temperature to cause the polymerization reaction of the organic monomer thereby forming an organic polymer film. At this time, when oxygen is present in the baking furnace, the organic polymer film having the desired characteristics is not obtained sometimes by the reaction of oxygen with a portion of the organic monomer. To prevent that from happening, for example, the atmosphere in the whole baking furnace is effectively replaced by a nitrogen gas, however, it is difficult to realize that at a low cost. Furthermore, since the dissolved oxygen in the solvent had sometimes reacted with the organic monomer during baking, a strict atmosphere control is required throughout the whole process, but it is practically difficult to carry out the strict atmosphere control in the spin coating method. Although the spin coating is conducted in a locally evacuated spin coating chamber to prevent scattering of the volatile solvent in the working environment, there is also a risk of contamination of the spin-coated film with floating dust particles or fine particles of the dried organic monomer adhered to the inner wall of the spin coating chamber. In this case, the film quality is deteriorated. Furthermore, the spin coating also has a problem that the environmental burden is large because a large amount of organic solvent is required and the amount of evaporation is also large.
(Second Prior Art)
Japanese unexamined patent publication No, HEI 11-288931 discloses a plasma CVD method using as a raw material a single vaporized gas which is the silicon type hydrocarbon compound where the saturated hydrocarbon is bonded to the straight-chain siloxane (—Si—O—Si—), for obtaining the silicon type organic insulation film with the dielectric constant of 3 or less. By adjusting the FR power or the deposition pressure during the plasma polymerization, although the composition ratio of elements such as carbon, hydrogen, silica and oxygen inside the synthesized organosiloxane film can be controlled, however, the molecular backbone structure of the obtained organosiloxane film or the polymerization structure of the whole film cannot be controlled.
(Third Prior Art)
Published Japanese translations of PCT international publication for patent application No. 2002-503879 (hereinafter referred to as literature 3) discloses a technique to form the organosiloxane film by reacting the oxidized gas eliminated by using a low-powered plasma with the organosilicone compound monomer (organosiloxane monomer) composed of the saturated hydrocarbon group and the siloxane. This reaction process does not have the polymerization selectivity such as activating a specific hydrocarbon group in the organosiloxane monomer and bonding to a specific site and an oxidizing agent gas. Accordingly, when oxidizing the organosiloxane monomer inside the plasma, it was difficult to strictly control its oxidation reaction or its degree of oxidation. In other words, it was difficult to design molecules of porous film by inducing minute pores to the silicone type organic insulation film. Furthermore, in order to improve the deposition property of the silicone organic insulation film synthesized as the lower and upper layers, it was necessary to control the composition of organosiloxane film near to the interface. According to the disclosed organosiloxane film formation method, it does not have the means for controlling the molecular structure or the chemical composition of the intermediate layer or the composition near to the interface. The present inventors have developed the technology to form the organosiloxane film on the substrate surface by vaporizing the organosiloxane monomer including an unsaturated hydrocarbon group, transporting it through the vapor using a carrier gas, and spraying to the heated substrate surface via the He plasma formed in the reaction chamber. This relating technology is disclosed in Japanese unexamined patent publication No. HEI 2000-12532. According to this organosiloxane film formation method, a vapor-transported organoxiloxane monomer generates the polymerization reaction on the substrate surface, and the organosiloxane film is formed. For example, if divinylsiloxane-bisbenzocyclobutene (BCB-DVS) monomer is utilized shown in chemical formula (1), having the straight-chain organosiloxane as backbone, its plasma polymerization reaction process is assumed to coincide approximately to the thermal polymerization reaction, and the cyclobutene group and the vinyl group which are the unsaturated hydrocarbon groups included in the organosiloxene are selectively activated, and the organosiloxane film having an intricate bridge structure shown in the chemical formula (5) is obtained, by the polymerization reaction via the elementary reaction processes shown in the chemical formulae (2) to (4).
The key point of this technology is in the fact that the unsaturated hydrocarbon group such as cyclobutene group or vinyl group is included in the organosiloxene monomer used as a raw material, and the organosiloxene monomers are bonded in a network shape via these unsaturated hydrocarbon groups. In other words, by controlling the position of the unsaturated hydrocarbon groups taking part in the polymerization reaction, the position of the polymerization reaction is specified, and a network structure of the desired organosiloxane film with organosiloxane monomer backbone is formed. Since the organosiloxane monomer supplied as a vapor is in high vacuum, in comparison to the spin coating method, its mobility is large on the surface, and the film strength and the thermal resistance of the obtained organosiloxane film are increased by improving the bridge density of the network structure. For example, as for the organosiloxane film obtained from the BCB-DVS monomer by the plasma polymerization, it has a highly dense bridge structure of the straight-chain siloxanes via the unsaturated hydrocarbon, and its dielectric constant is ranging from 2.5 to 2.7.
Particularly, in the case of using it as the interlayer insulation film of the multi-layered wiring of ULSI, the organosiloxane film structure is formed in between the upper wiring layer and lower electrode layer. At this time, other insulation film is used in the production of the lower electrode layer and the upper wiring layer. Accordingly, the organosiloxene film of the interlayer insulation film is of a laminated structure with the organic or inorganic insulation film of the upper layer and lower layer. Because of this, it is necessary that the film strength and the deposition property of the insulation film at the interface contacting the upper plane or the lower plane of the organosiloxane film to be high. To improve the film strength near to the interface or the deposition property of the organosiloxane film, it is effective to increase its bridge density but that accompanies the increase in the dielectric constant.
Ideally, the organosiloxene film utilized as the interlayer insulation film, has a high strength film quality and a high bridge density which is excellent in the deposition property only near to the interface with other film material. Other section of the interlayer other than the interface ideally has a film configuration that keeps a bridge density that can attain the appropriate dielectric constant. However, as for the plasma polymerization film utilizing the single organosiloxene monomer as the raw material, it was generally difficult to arbitrarily select the bridge density of the obtained polymer film in the film thickness direction to make the polymer film with the continuously changing deposition property and dielectric constant. That is, in the plasma polymer film using the conventional single raw material, it was impossible to arbitrarily control the bridge density for controlling the film quality to a large extent and continuously in the film thickness direction.

Organic siloxane copolymer film, method and deposition apparatus for producing same, and semiconductor device using such copolymer film


A phase locked loop circuit, system, and method of operation are provided. The phase-locked loop (PLL) includes a first PLL and a second PLL. The first PLL is nested inside the second PLL. According to one embodiment, the first PLL is coupled to the output of a surface acoustic wave (SAW) resonator, and includes first divider coupled within a feedback loop of the first PLL. The second PLL is coupled between an input of the overall PLL circuit, and output from the first PLL and the first divider. According to a second embodiment, the second PLL includes a SAW voltage-controlled oscillator (VCSO) and a second divider coupled to an output of the first PLL. Regardless of whether the first or second embodiments are contemplated, the nested first and second PLL circuits provide an agile, low phase noise, clock synthesizer and jitter attenuator hereof.

1. Field of the Invention
The present invention relates generally to electronic circuits and, more particularly, to a nested pair of phase-locked loop (PLL) circuits that are agile, in that multiple frequencies can be synthesized at the output, a low phase noise surface acoustic wave (SAW) resonator is used to synchronize the output and, with one of the PLL circuits being a low bandwidth PLL, jitter on the output is attenuated.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In electronic circuits, clock distribution occurs throughout the circuit to synchronize performance of the product. Clock skew and jitter can occur if poor clock distribution is present. This may cause problems in operation of the electronic circuit. Techniques have been developed using PLL's to successfully manage these problems and reduce both to an acceptable level. However, the current solutions are not without some disadvantages.
A PLL can be used for clock distribution, clock multiplication, skew suppression, clock recovery, and other applications. A PLL can suppress skew and jitter in digital systems (for example, clock to data out delay), and can generate multiple phases of output clocks. In an exemplary application, a PLL may operate as a clock multiplier, where an input clock of 10 MHz may be multiplied by the PLL to yield, for example, 1000 MHz. Typically, a PLL includes a phase frequency detector, a charge pump, a low-pass filter, and a voltage-controlled oscillator (VCO). The phase frequency detector detects and tracks small differences in phase and frequency between the incoming signal and the output from the VCO, and provides output pulses that are proportional to that difference. In many instances, a PLL can include a frequency divider within the feedback loop between the VCO and the phase frequency detector. For example, an N divider allows the frequency output from the VCO to equal N times the input signal frequency, namely FOUT=N*FIN. In the ideal embodiment, clock multiplication function can result in an output clock that is in perfect phase alignment with the input clock, yet at a higher frequency (i.e., a frequency N times the input frequency).
Therefore, a PLL is oftentimes used as a clock synthesizer. In a 10 GHz XFP optical module, it may be necessary to translate one data/clock rate to another data/clock rate while keeping phase noise as small as possible on that output. The transfer can occur through clock multiplication and, possibly, clock division to achieve a particular ratio between an input and output frequency (FIN and FOUT).
One mechanism in which to generate the output frequency with low phase noise is to utilize a SAW oscillator. As described in "Integrated RF transmitter based on SAW Oscillator," 23rd EP Solid-State Circuits Conference, September 1997 (herein incorporated by reference), SAW oscillators operate using a SAW resonator coupled to an output amplifier. The resonating frequency can be modified through an input voltage to form what is known as a voltage-controlled SAW oscillator, or VCSO. Further details of a VCSO are set forth in U.S. Pat. No. 6,933,794 (herein incorporated by reference).
A VCSO can be placed in a PLL by substituting a VSCO for the VCO. A primary benefit of a VCSO is that there is very little phase noise at the PLL output. This is due primarily to the VCSO having a high Q factor exceeding, for example, 10,000. Moreover, operation at the fundamental frequency of the resonator avoids any spurious emission on that output. Unfortunately, however, a VCSO has a very narrow pulling range. In other words, the VCSO, while having low phase noise and good jitter attenuation within a PLL, cannot be tuned much beyond 300 ppm.
Recognizing the shortcomings of a VCSO, some PLL circuits use the more traditional inductor/capacitor VCO, or LCVCO. An LCVCO, while having a higher phase noise and greater spurious emissions than a VCSO, can be tuned far beyond the 300 ppm of a VCSO. In some examples, an LCVCO can achieve a tuning range greater than 10%. The synthesized multiple rates associated with, for example, clock recovery in a 10 GHz XFP application, VCSO cannot be utilized because its incoming frequency variation can extend beyond the tuning range of the VCSO.
It would be desirable to implement a clock recovery or translation circuit that has low phase noise with good jitter attenuation of a VCSO within a PLL, yet with a wider range of tunability which conventional VCSO PLL circuits cannot achieve. Thus, a more agile, lower phase noise, clock synthesizer with jitter attenuation is desired.

Agile, low phase noise clock synthesizer and jitter attenuator


A modular approach to the design of motion modules, e.g., positioning elements, is provided. Thus, a single positioning element can be integrated into a number of multi-axis configurations through combination with other basic positioning elements all of which share a modular interlocking feature.. In an embodiment of the invention a motion module is disclosed which includes a base and a mobile stage. The base includes an exterior surface and a first interconnector located on the exterior surface. The mobile stage includes an exterior surface and a second interconnector. The mobile stage is positionable with respect to the base. The second interconnector is located on the exterior surface of the mobile stage. The first and the second interconnector are mutually engagable in releasable frictional engagement with second and first interconnectors of other motion modules for stackable interconnection therebetween.

1. Field of the Invention
This invention relates generally to positioning instruments, and particularly to a motion module with interlocking elements to allow stacking with other motion modules, to produce multi-axis positioning instruments.
2. Description of Related Art
The use of adjustable mounting or clamping devices is a common technique for experimental optics, telecommunications, semiconductor inspection and manufacturing, biological probing and sampling, electronic probing and sampling, magnetic probing and sampling and machining. Such mounts are used to position objects, e.g., optical elements, such as light sources and other optical devices. These devices have varying sizes and shapes, and are frequently positioned in close proximity to each other. Separate modules are used to perform different positioning functions. For example, linear translation stages allow axial movement of an element, rotary translation stages provide for rotation of an element, planarization stages provide tip-tilt for leveling of an element, and goniometers provide for angulation of an object. The modules are expensive due to the high degree of precision with which they are manufactured.
Typically, a customer's needs will vary from experiment to experiment. For example, in one experiment X-axis positioning of an object may be required. In another experiment combined X-Y axis positioning may be required, in another experiment X-Y-Z axis positioning may be called for. In still another experiment a combination of X-Z positioning and rotation may be called for. To achieve each of these positioning objectives the X, X-Y, X-Y-Z, and X-Y-Z+ rotation combinations must be purchased as fully assembled integral modules. This of course results in considerable expense and duplicity of investment. A customer may for example own four X-axis positioning elements, one as a stand-alone and the others as integral portions of various multi-axis positioners.
What is needed is a way to reduce the expense and duplication associated with existing multi-axis positioning modules.

Modular motion stages utilizing interconnecting elements


Provided are a mobile terminal, an electronic system, and a method of transmitting and receiving data using the same for effectively transmitting and receiving data between the mobile terminal and external electronic devices.

1. Field
This document relates to a mobile terminal and an external electronic device, and more particularly, to transmission and receiving of data between the mobile terminal and the external electronic device.
2. Related Art
Recent technological development has realized smooth data transmission and receiving between a mobile terminal and a variety of electronic devices.
However, conventional methods of transmitting and receiving data between a mobile terminal and an external electronic device required a user to operate multi-stage operations or perform complicate setting, and thus it was inconvenient for the user to use the mobile terminal

Mobile terminal, electronic system and method of transmitting and receiving data using the same


Provided is a method for programming a nonvolatile memory apparatus which includes a bit line selector coupled to first and second bit lines and a page buffer including a main data transmission switch coupled to the bit line selector, a first latch coupled to the main data transmission switch, a temporary data transmission switch coupled to the bit line selector, and a second latch coupled between the temporary data transmission switch and the first latch. In the programming when the first bit line is precharged to a power supply voltage level, a main data transmission switch and a temporary data transmission switch are simultaneously turned on to set up a voltage of the second bit line depending on data levels stored in the first and second latches.

1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a programming method for a nonvolatile memory apparatus.
2. Related Art
In a nonvolatile memory apparatus represented by a flash memory apparatus, a data level stored in each memory cell is defined by a threshold voltage of the memory cell, and a program operation is performed by a method of changing the threshold voltage of the memory cell.
In general, a program operation of a nonvolatile memory apparatus is performed by an incremental step pulse program (ISSP) scheme, and will be described below with reference to FIG. 1.
An active high signal is said to be asserted when it is in the high level, and an active low signal is said to be asserted when it is in the low level. Additionally, when referring to signals, the terms "asserted," and "enabled" may be used interchangeably depending upon context. Similarly, the terms "deasserted" and "disabled" may be used interchangeably depending upon context.
FIG. 1 is a diagram explaining a program method using the ISSP scheme.
First, a first-step program pulse VPGM1 is applied to program selected memory cells. Then, a verification voltage PVER is applied to the selected memory cells so as to pass memory cells with threshold voltages Vth1 higher than the verification voltage PVER.
After that, a second-step program pulse VPGM2, which has an increase of a constant voltage over the first step-program pulse Vth1, is applied to program the memory cells with threshold voltages Vth2 equal to or lower than the verification voltage PVER. At this time, the passed memory cells with the threshold voltages Vth1 are not programmed, thereby preventing the memory cells from being over-programmed.
Similarly, even after the second-step program pulse VPGM2 is applied to perform the program, the threshold voltages Vth3 and Vth4 of the memory cells are compared with the verification voltage VPER, and the program and the verification are performed while gradually increasing the program pulse (VPGM3, VPGM4, . . . ) until all the memory cells are programmed.
That is, referring to FIG. 2, the program pulse voltage is increased in steps as the threshold value Vth of certain memory cells selected for programming become increasingly higher than the verification voltage PVER.
Recently, a double verification method has been used during a program operation, in order to make more uniform the threshold voltage distribution of programmed cells.
In the double verification method, the level of a program pulse differs depending on the threshold voltage levels of selected cells. In a verification process, cells having a threshold voltage Vth higher than a verification voltage are classified into program-prohibited cells, cells having a threshold voltages Vth lower than the verification voltage but higher than a preset reference voltage are classified into low-speed program cells, and cells having a threshold voltages Vth lower than the preset reference voltage are classified into general program cells.
After the cells are classified in such a manner, a subsequent program pulse is not applied to the program-prohibited cells. Meanwhile, a low-speed program pulse is applied to the low-speed program cells, and a normal program pulse is applied to the general program cells, as in a general ISSP scheme.
For this process, an operation of setting up a bit line depending on the threshold voltages of cells to be programmed should be done before the program pulses are applied.
FIG. 3 is a diagram explaining a conventional bit line setup method in a nonvolatile memory apparatus, and shows a case in which an even bit line BLe is programmed.
When the even bit line BLe is to be programmed, an odd bit line BLo should be in a program-prohibited state. For this condition, an even discharge signal DISCHE and an odd discharge signal DISCHO are enabled, and a power supply voltage VCC is applied to a verification voltage application terminal VIRPWR to precharge the even bit line BLe and the odd bit line BLo ({circle around (1)}).
Subsequently, in order to discharge a bit line coupled to a memory cell to be programmed, that is, the even bit line BLe, the even discharge signal DISCHE is disabled, and an even bit line selection signal SELBLE is enabled. Furthermore, the odd discharge signal DISCHO maintains the enable state, and an odd bit line selection signal SELBLO is disabled.
At this time, a first latch SL1 of a page buffer coupled to a memory cell which has been programmed stores high-level data such that the memory cell is not over-programmed. As a sensing control signal PBSENSE and a main data transmission signal MTRAN are enabled, a discharge operation does not occur in a bit line coupled to the memory cell which has been completely programmed. On the other hand, since the first latch SL1 of a page buffer coupled to the memory cell classified as a general program cell stores low-level data, a discharge operation occurs ({circle around (2)}).
Then, in order that a bit line coupled to a low-speed program cell has a preset level Va (<VCC), a temporary data transmission signal TTRAN is enabled. At this time, the sum Vth+Va of a threshold voltage of a transistor N4 to which the temporary data transmission signal TTRAN is applied and the preset level of voltage is applied ({circle around (3)}).
Through the above-described process, the bit line voltage of the program-prohibited cell becomes a power supply voltage (VCC) level, the bit line voltage of the low-speed program cell becomes the preset voltage (Va) level, and the voltage of the general program cell becomes a logic low level.
FIG. 4 is a graph explaining changes in the bit line voltage during the bit line setup.
While the even bit line BLe and the odd bit line BLo are precharged ({circle around (1)}), the voltage V_BL of the even bit line BLe gradually increases to the power supply voltage level.
While the even bit line BLe is discharged ({circle around (2)}), the bit line voltage V_BL of the program-prohibited cell which has been already programmed maintains the power supply voltage level, and the bit line voltage V_BL of the general program cell is discharged to a low level.
Furthermore, while the bit line coupled to the low-speed program cell is set up ({circle around (3)}), the bit line voltage V_BL of the program-prohibited cell maintains the power supply voltage level, the bit line voltage V_BL of the general program cell maintains a low level, and the bit line voltage V_BL of the low-speed program cell changes to the preset level Va.
In FIG. 4, '11' represents a data value stored in the first and second latches SL1 and SL2 when the bit line of the program-prohibited cell is set up, '00' represents a data value stored in the first and second latches SL1 and SL2 when the bit line of the general program cell is set up, and '01' represents a data value stored in the first and second latches SL1 and SL2 when the bit line of the low-speed program cell is set up.
As such, since the process of setting up the bit line for the program operation in the nonvolatile memory apparatus is performed in three stages, a considerable amount of time is required for the setup process.
Furthermore, after a bit line of a memory cell to be programmed should be precharged, the bit line should be discharged, and the discharged bit line should be again precharged to the preset level Va. Therefore, the current consumption increases. Furthermore, when the precharged bit line is again discharged, a coupling capacitance with an adjacent bit line may occur. In this case, the voltage of the bit line which should maintain the precharge state may be reduced, and thus current consumption may occur to compensate this reduction. Furthermore, when a voltage is supplied to maintain the precharge voltage, a peak current may flow. In this case, a sudden voltage drop may occur, and thus a system clock down may occur.

Programming method for nonvolatile memory apparatus


A scroll type compressor has a housing, a rotary shaft, a fixed scroll member, a movable scroll member and a rotation preventing mechanism. The rotation preventing mechanism has a movable pin that is provided on the surface of movable end plate and extends toward end surface of the housing in parallel with an axis of the rotary shaft, a fixed pin that is provided on the end surface of the housing and extends toward the surface of the movable end plate in parallel with the axis of the movable pin, a rolling element that is disposed between the movable and the fixed pins, being contactable with the movable and the fixed pins and a retainer retaining the rolling element between the movable and the fixed pins.

The present invention relates to a scroll type compressor having a fixed scroll member and a movable scroll member which is adapted to make an orbital motion while being prevented from rotating on its axis by a rotation preventing mechanism whereby a compression chamber whose volume is variable is formed between the fixed scroll member and the movable scroll member.
In general, a scroll type compressor includes a fixed scroll member having a fixed end plate and a fixed scroll wall and a movable scroll member having a movable end plate and a movable scroll wall. The fixed and the movable scroll members are disposed in a housing with the scroll walls thereof engaged with each other. The movable scroll member orbits around the axis of the fixed scroll member and refrigerant gas taken into a compression chamber defined between the fixed and the movable scroll walls of the scroll members is compressed with a decrease in the volume of the compression chamber in accordance with the orbital motion of the movable scroll member.
The scroll type compressor has a rotation preventing mechanism that prevents the rotation of the movable scroll member and allows the movable scroll member to orbit around the axis of the fixed scroll member Japanese Patent Application Publication H7-167067 discloses a rotation preventing mechanism. The rotation preventing mechanism includes a plurality of movable pins provided on the end surface of the movable scroll member for orbiting in accordance with orbital motion of the movable scroll member and a plurality of fixed pins provided on the end surface of a casing forming a part of the fixed scroll member for contact engagement with the movable pins. When the movable scroll member orbits around the axis of the fixed scroll member, each movable pin of the movable scroll member orbits around its paired fixed pin of the fixed scroll member. Contact engagement of the paired movable and fixed pins allows the movable scroll member to make an orbiting motion while being prevented from rotating on its axis.
In the rotation preventing mechanism of the above Publication, the movable pins and the fixed pins are fixed to the end surface of the movable scroll member and the casing, respectively, by press fitting. A force acting on the movable scroll member for rotation on its axis is transmitted to each fixed pins due to the contact engagement thereof with its paired movable pin and further to the casing. With the fixed and the movable pins in contact engagement with each other, sliding contact arises in the movable pin and/or fixed pin and friction resistance due to the sliding contact arises therebetween. Accordingly, there has been problems that the power loss increases in the scroll type compressor and both movable and fixed pins are subject to wear.
The present invention is directed to providing a scroll type compressor that can reduce the friction resistance between the movable and the fixed pins and the wear of the pins.


The present invention discloses the structure of the array lens that at least any one of the diagonal size, vertical size and lateral size of lens cell is set to almost 1/(4.5 or more) for each corresponding size of the display elements. The diagonal size of lens cell is set to almost 0.18 inch or less. The total number of lens cells is set to almost 240 or more. Finally, the lens focal distance of lens cell is set to almost 30 mm or less.

1. Field of the Invention
The present invention relates to a technique of displaying images on a screen using a liquid crystal panel and other display elements, for example, a liquid crystal projector, a reflection type image displaying projector, a liquid crystal television and a projection type display apparatus.
A projection type imaging apparatus such as a liquid crystal projector has been popular, in which the display element such as a liquid crystal panel or the like is irradiated with a light beam emitted from a light source and thereby an image on the display element can be projected as an enlarged image.
In the imaging apparatus of this type, the light from the light source is adjusted through conversion to gray scale of each pixel with the display element and is then projected to the screen. For example, in the case of the twisted nematic (TN) type liquid crystal display element in which the display element is a typical example of the liquid crystal display element, two sheets of polarizing plates are arranged to result in a difference of 90 degrees of polarizing directions before and after the liquid crystal cell which is formed by supplying the liquid crystal to the space between a couple of transparent substrates having the transparent electrode films. In this case, amount of transmitting light of the incident light beam is controlled to display the image of information by combining the operations for rotating the polarizing plane with the electro-optical effect of the liquid crystal and selecting the polarizing element of the polarizing plate. In recent years, such transmitting type or reflection type display element has remarkably reduced the size of the element itself and also has improved performance such as resolution, etc.
Therefore, with advancement in size reduction and performance of the apparatus utilizing the display element, a projection type imaging apparatus has newly been proposed as an apparatus not only for realizing image formation by a video signal or the like which has been done in the related art, but also for use as an image output device of a personal computer. The projection type imaging apparatus of this type is particularly required to be small in size and to assure that a bright image can be obtained up to the corners of the display screen.
However, the projection type imaging apparatus of the related art has problems that the apparatus size is large and brightness and quality of image attained finally are insufficient.
For example, in the case of a liquid crystal display apparatus, size reduction of the light bulb, namely liquid crystal element itself is effective for size reduction of the apparatus as a whole, but when the liquid crystal display element is reduced in size, the area irradiated by the light of liquid crystal means becomes small, creating a problem in that a ratio in amount of light flux on the liquid crystal display element for amount of total light flux radiated by the light source (hereinafter, referred to as light application efficiency) becomes lower and side area of display screen becomes dark. Moreover, since the liquid crystal display element can utilize the polarized light beam of only one direction, about a half of the light beam emitted from the light source which radiates the random polarized light beam is left unused.
As a means for attaining the bright image at the four sides of the display screen, an integrator optical system, for example, has been proposed, in which a couple of lenses are used as described in the Japanese Published Unexamined Patent Publication No. HEI 3-111806. The integrator optical system divides the light from the light source with a plurality of condenser lenses in the shape of the rectangular opening forming a first array lens and then focuses in overlapping the output light in the shape of rectangular opening at the radiating surface (liquid crystal display element) with a second array lens formed by the condenser leans group corresponding to the condenser lenses in the shape of rectangular opening. In this optical system, intensity distribution of the light irradiating a the liquid crystal display element can be almost equalized. Meanwhile, as the optical system for irradiating the liquid crystal display element with the light beam emitted from the light source and arranged in one polarizing direction, a system is disclosed in the Japanese Published Unexamined Patent Publication No. HEI 4-63318, in which the light beam emitted from the light source and is polarized at random is isolated to P-polarized light beam and S-polarized light beam using the polarizing beam splitter and these are then combined with a prism.
However, in the conventional integrator optical system, since a diagonal size of one lens cell of array lens is 0.25 inch or larger, an F value of the light system must be set to almost 2 or 3 in order to improve equality of brightness and quality of image using the liquid crystal display element with a micro-lens. As a result, distance between the first and second array lenses becomes not shorter than 31 mm, disabling reduction in size of the optical system. Therefore, it has been difficult for the projection type liquid crystal apparatus of the related art to reduce the size of apparatus exceeding the size of the A4 file size. Moreover, even in the optical system utilizing the polarizing beam splitter, it is difficult to realize matching in accuracy in the array lens and therefore size reduction has also been difficult. As a result, it has been difficult to simultaneously realize reduction in size of the apparatus as a whole and improvement in performance such as brightness. In addition, in the case of the projection type liquid crystal apparatus, it has also been difficult, even when only the lighting means is improved, to attain the display apparatus which is small in size and assures good display image quality because the image quality depends on various factors, in addition to such lighting means, such as optical characteristic of objection leans and optical characteristic of liquid crystal element.
Moreover, it has been required to use a larger array lens in order to improve brightness in the integrator optical system of the related art and when the projection type liquid crystal apparatus is reduced in size, brightness has been decreased. In addition, this phenomenon can also be observed when size reduction is conducted in the optical system using the polarizing beam splitter. As a result, it has been difficult to simultaneously realize size reduction of the apparatus as a whole and improvement in performance such as brightness. Moreover, when a polarized beam combining means is used, performance deterioration due to unwanted light beam, namely the P-polarized light beam entering the S light path has also been observed.

Array lens, lighting optical system, optical unit and imaging apparatus


A carrier for articles has a case with an interior compartment that holds sleeves called pages for holding articles. The pages are accessed when the case is opened. The pages are attached to the case inside the compartment so they may be rotated to access either side. The pages may be detached from the case. A kit comprising a case and a number of detachable and varied pages may be employed to construct a carrier according to the needs of the user.

Carriers have been designed with convenient features for organizing articles such as clothing, toiletries, electronics, office supplies, files, and the like. For example, carriers may be provided with means such as pockets, pouches, compartments, and the like for containing these articles.
Preferably such carriers will securely contain the articles while allowing the user to easily access the articles. Easy access to the means for containing the articles is desirable in order to reduce the time needed to locate and access the articles.
Carriers usually may not be altered after they are made. A user may have to acquire more than one carrier in order to accommodate the articles chosen by the user.


In a mail processing machine having a receive deck for receiving a stack of mail items for printing, jogging means for jogging the stack of items against a reference wall, selection means for extracting mail items for printing one by one from stack of items, and print means for printing a postal imprint on the selected mail item, a jogging device is provided that includes an external strip slidably mounted on a moving slideway and having a jogging flat mounted at the terminal end thereof, a brake-forming friction shoe secured to the stationary slideway and mounted between the stationary slideway and the moving slideway, and a resilient element having one end connected to the moving slideway and its other end connected to the external strip in order to cause the external strip to back off automatically through a determined distance from the moving slideway once the jogging flap has been brought into contact with the stack of mail items.

1. Field of the Invention
The present invention relates exclusively to the field of mail processing, and more particularly it relates to a device for jogging mail items and intended for fitting to a module for feeding a mail processing machine with mail items.
2. Brief Description of Related Developments
A device for jogging mail items that acts directly on the lateral positioning (and possibly also the rear positioning) of mail items is essential in a mail processing machine, since without jogging, the mail items are not presented in a suitable position to the station for printing the postal imprints, and as a result the imprint might be refused by the postal authorities. The device must also be retractable so as to leave room to pass mail items of large dimensions.
U.S. Pat. No. 5,628,504 discloses a lateral jogging device which can be moved transversely between two guide positions corresponding to two determined envelope widths. That device therefore cannot pass mail items of size larger than the larger of the two widths, unlike the device in U.S. Pat. No. 5,927,708 which includes a telescopic member that can pivot to allow such items to pass through, and also items of great thickness. Nevertheless, such pivoting presents the drawback of requiring means for holding the telescopic member in a high position, which means are relatively complex, and this high position on the transport path puts a limit on the thickness of the stack of large-sized mail items that can be jogged. In addition, it can be seen that the stack of mail items is not accurately compressed with such a telescopic system, and the system is also somewhat unsightly.

Jogging device for a mail processing machine


An apparatus and method for unloading a plurality of items from a carrier is provided. The items are preloaded in the carrier, in a column having a top row. The apparatus has a first conveyor which has a first end for approaching the top row, an opposite second end and a conveyor body connecting the first end and the second end. The first end has an end platform for receiving the top row and an arm associated with the end platform for transporting the top row onto the end platform. A second conveyor is operatively connected to the first conveyor for receiving the top row from the first conveyor and transporting the top row for further processing the top row. The apparatus also has a control unit for controlling the movement of the first conveyor and the second conveyor.

The present disclosure relates generally to a container loading and unloading apparatus, and more particularly to an apparatus and method for loading and unloading containers with respect to a carrier in a controlled manner, involving minimum human intervention.
Containers, particularly road-transportable shipping containers, are commonly used to ship and store cargo. Typically, the containers are loaded into and unloaded from a carrier, such as a shipping trailer, for transportation of the cargo. During the loading process, the container may be handled in an uncontrolled manner, resulting in unorganized arrangement of the containers, which causes waste of the limited space of the shipping trailer and difficulty in locating and unloading the containers. Furthermore, in order to organize the containers, additional human labor and/or equipment may be needed, for example, to place the containers in a stacked manner. Furthermore, the addition of the human element increases the safety and physiological concerns associated with manually lifting and placing shipping cases.
U.S. Pat. No. 6,725,999 to Luevano teaches an unloading system, which includes a loading platform, a conveyor positioned below the loading platform, and a slanted ramp between the loading platform and the conveyor. Items to be unloaded from a carrier can be slid from the platform to the conveyor through the ramp, relying on the gravity of the items. However, since the items are slid on the ramp, it is impossible for the system of Luevano to position a plurality of items in a stacked manner under control. Accordingly, interference of the items during the unloading process is inevitable and additional human labor is necessitated to organize the items.
U.S. Pat. No. 5,829,947 to Litten teaches a hydraulic ramp loader, which includes an extendible ramp and a hydraulic system for moving the ramp up and down with respect to a carrier. The ramp can be moved up and down by the hydraulic system. The ramp, including four panels connected with one another, allows an item to slide on the panels. Thus, similar to Luevano, Litten cannot load or unload a plurality of items in a stacked manner under control. Accordingly, additional human labor is necessitated to organize the items.
Therefore, it is desirable to provide a container loading and unloading apparatus and method, which is capable of loading and unloading the containers in a controlled manner, and minimizing human intervention during the loading and unloading process, thereby reducing human safety and physical concerns.

Apparatus and method for loading and unloading containers


The invention relates to a rotational X-ray device (100), for example a CT scanner, for generating phase contrast images of an object (1). In a particular embodiment of the device (100), a plurality of X-ray sources (11), an X-ray detector (30), and an analyzer grating (G2) are attached to a rotatable gantry (20), while a ring-shaped phase grating (G1) is stationary. The X-ray sources are disposed such that X-rays first pass an object under study before traversing the phase grating (G1) and subsequently the analyzer grating (G2). This is achieved by either shifting the X-ray sources axially with respect to the ring-shaped phase grating (G1) or by disposing the X-ray sources in the interior of the ring. Moreover, the phase grating (G1) and the analyzer (G2) shall have spatially varying relative phase (and/or periodicity), for example realized by line grids that are tilted with respect to each other. During the rotation of the gantry (20), the synchronized activation of X-ray sources (11) allows to generate projection images of an object (1) from the same viewing angle with different relative positions (and therefore phases) between the phase grating (G1) and the analyzer (G2).

While classical X-ray imaging measures the absorption of X-rays caused by an object, phase contrast imaging aims at the detection of the phase shift X-rays experience as they pass through an object. According to a design that has been described in literature (T. Weitkamp et al., "X-ray phase imaging with a grating interferometer", Optics Express 13(16), 2005), a phase grating is placed behind an object to generate an interference pattern of intensity maxima and minima when the object is irradiated with (coherent) X-rays. Any phase shift in the X-ray waves that is introduced by the object causes some characteristic displacement in the interference pattern. Measuring these displacements therefore allows to reconstruct the phase shift of the object one is interested in.
A problem of the described approach is that the feasible pixel size of existing X-ray detectors is (much) larger than the distance between the maxima and minima of the interference pattern. These patterns can therefore not directly be spatially resolved. To deal with this issue, it has been proposed to use an absorption grating immediately in front of the detector pixels, thus looking only at small sub-sections of the interference pattern with the pixels of the detector. Shifting the absorption grating with respect to the pixels allows to recover the structure (i.e. the deviation from the default pattern without an object) of the interference pattern. The necessary movement of optical elements is however a nontrivial mechanical task, particularly if it has to be done fast and with high accuracy, as would be required if phase contrast imaging shall be applied in a medical environment.

Rotational X ray device for phase contrast imaging


A solid-state switch for an external system includes a cover member, a first solid-state transducer, a microcontroller, a user feedback device, and a switching circuit. The first transducer is mechanically coupled to the cover member and configured to generate first signals in response to a perturbation at the cover member. The microcontroller is configured to obtain first data from the first signals and determine user inputs in accordance with at least the first data and an operational state of the solid-state switch. The user feedback device is configured to provide feedback to a user of the solid-state switch in accordance with a switching behavior of the switching circuit. The microcontroller is couplable to a master controller of the external system. The switching behavior of the switching circuit is determined in accordance with: (a) the commands from the master controller to the microcontroller, and/or (b) user inputs as determined by the microcontroller.

In some use cases, it is desirable to make switches of electronic systems weatherproof, e.g., sealed against moisture dust. For example, some electronic systems, such as solar-power systems, are placed outdoors. Weatherproof switches would be attractive for such outdoor electronic systems. It is feasible but quite cumbersome or costly to seal a mechanical switch against moisture and dust because of the mechanical moving parts. Additionally, the movable parts in a mechanical switch undergo degradation upon repeated use and exposure to the outside elements. On the other hand, solid-state transducers can be made using micro-electromechanical systems (MEMS) technologies. Solid-state transducers can enable a more simplified approach to weatherproof switches. A solid-state transducer does not need any moving parts, other than an active material that might undergo mechanical deformation at the micrometer level (or less). Accordingly, the probability of material fatigue and failure is reduced. Additionally, by using MEMS and CMOS (complementary metal-oxide semiconductor) processing technologies, solid-state transducers, analog front-end processors, and microcontrollers can be integrated into one integrated circuit (IC) device.

Solid-state touch-enabled switch and related method


A molding system has a base, a fixed mold plate secured to the base, a fixed mold half carried on the fixed mold plate, a movable mold plate displaceable on the base longitudinally forward away from the fixed mold half and backward toward the fixed mold half, and a movable mold half carried on the movable plate and fittable with the fixed mold half. A mold-closing apparatus has a pair of main cylinders fixed to the fixed mold half and respective main pistons subdividing the main cylinders into respective front and rear main compartments and each having a piston rod secured to the movable mold plate and formed with a longitudinally extending chamber. A small-diameter fast-closing piston and cylinder are formed in one of the piston rods, and the other piston rod is provided internally with a force-amplifying piston unit. Two flow-control valves and check valves control the system.

A standard molding system has a base, a fixed mold plate secured to the base, a fixed mold half carried on the fixed mold plate, a movable mold plate displaceable on the base longitudinally forward away from the fixed mold half and backward toward the fixed mold half, and a movable mold half carried on the movable plate and fittable with the fixed mold half. Normally a plurality of massive cylinders are mounted on the fixed plate with their piston rods projecting through this plate and secured to the movable mold plate so that pressurization of these cylinders holds the mold tightly closed as molding material is injected into the closed mold and this material cures.
In order to speed operations, separate cylinders are provided for high-speed closing and opening of the mold, as the big pressurizing cylinders are designed to work at great pressure and are therefore fairly slow. Such systems are described in German patent document 1,625,651 of H. DeCorta et al (based on a French priority of Sep. 26, 1966), 2,811,332 of M. Manceau based on a French priority of May 25, 1977), 2,845,448 of K. Hehl, 3,008,715 of P Florjanolo, and 2,852,516 of W. Wohlrab (citing U.S. Pat. No. 3,418,693), as well as in East German patent 226,039 of S. Maras et al, European patent application 88 109,144 of Y. Kushibe et al, and in "Aufbau und Funktion einer neuartigen Spritzgiessmaschine" of E. Sauerbruch (Kunststoff, vol. 61, 1971, bk. 6).
Such systems are typically also provided with pressure-amplifying devices that serve to apply greatly augmented force via the main cylinders to the mold during the molding operation. Such a pressure-amplification system typically has a piston with one big face that is exposed to the high-pressure side of the source and an opposite much smaller face that pressurizes liquid that is applied to the pressurizing pistons. Thus the force is multiplied by a factor determined by the relative sizes of the two faces.
The main problem with these known systems is that they are all fairly complex. The fast-closing and -opening equipment as well as the force-amplification system are mounted on and around the mold plates, taking up space and making access to the mold difficult.

Mold-closing apparatus for injection-molding machine


A method for fabricating a semiconductor device, wherein the method comprises steps as follows: Firstly, a device wafer is provided and a patterned bonding layer is then formed within a scribe line region of the device wafer. Subsequently a handle wafer is bonded to the device wafer by the patterned bonding layer. Next, a dicing process is performed along the scribe line region in order to divide the device wafer into a plurality of dices and remove the patterned bonding layer simultaneously, whereby the divided dices can be separated from the handle wafer.

Typically, wafer thinning is a necessary process for fabricating semiconductor devices, such as micro-electro-mechanical system (MEMS) devices. However, thinned wafers may be frangible during wafer transition and vulnerable to the subsequent treatments for fabricating semiconductor devices. For example thinned wafers may be bowed and warped during a subsequent chemical mechanical polishing (CMP), etching step or ion implant step.
Currently, in order to resolve the problems, a temporary bonding/debonding technology thus was adopted. After integrated circuit (IC) elements are formed on the device wafer, a carrier wafer is bonded on the device wafer via an adhesive for temporary bonding, and wafer thinning steps are carried out on the backside of the device wafer. However, the temporary bonding/debonding technology not only necessitated an adhesive consisting of specific materials but also requires relatively complex processes, such that it is unlikely to reduce the processing cost of the semiconductor or MEMS devices.
Therefore, there is a need of providing an advanced method for fabricating a semiconductor device to obviate the drawbacks and problems encountered from the prior art.

Method for fabricating semiconductor device


Programmable switches and routers are described herein for enabling their internal network fabric to be configured with a topology. In one implementation, a programmable switch is arranged in a network having a plurality of switches and an internal fabric. The programmable switch includes a plurality of programmable interfaces and a buffer memory component. Also, the programmable switch includes a processing component configured to establish each of the plurality of programmable interfaces to operate as one of a user-facing interface and a fabric-facing interface. Based on one or more programmable interfaces being established as one or more fabric-facing interfaces, the buffer memory component is configured to store packets received from a user-facing interface of an interconnected switch of the plurality of switches via one or more hops into the internal fabric.

FIG. 1 is a diagram showing a data center 10 where switches 12L, 12A, 12S within the data center 10 are arranged in a conventional Clos network configuration. The data center 10 may include a plurality of racks 14, where each rack 14 may include a Top of Rack (TOR) leaf switch 12L and a plurality of servers 16. Each leaf switch 12L within the rack 14 may include a plurality of internal ports 18 for connection with the respective servers 16. In this arrangement, servers 16 within a single rack 14 may communicate with each other via the directly-connected leaf switch 12L. For instance, communication from one server to another within a single rack 14 may include a first hop from a first server to the leaf switch 12L and a second hop from the leaf switch 12L to a second server.
The Clos network in this data center 10 includes a first layer 20 (e.g., "leaf" layer) of leaf switches 12L that are arranged within the racks 14. Furthermore, the Clos network includes a second layer 22 (e.g., "aggregation" layer) of aggregation switches 12A and a third layer 24 (e.g., "spine" layer) of spine switches 12S. The Clos arrangement includes a first set of links 26 between the leaf switches 12L and the aggregation switches 12A and a second set of links 28 between the aggregation switches 12A and the spine switches 12S.
The portions of a telecommunications network that are typically incorporated within data centers, enterprise networks, Local Area Networks (LANs), High Performance Computing (HPC) environments, or other well-defined network environments are usually built with a highly-structured architecture. Some examples of highly-structured architectures that are frequently used within modern data center networks include Fat Tree, Clos, Dragonfly, Slim Fly, and B-Cube. These highly-structured network architectures are easy to visualize, can be built from smaller building blocks, provide high bisectional bandwidth, etc.
In addition to the overall network, the internal structure of traditional spine switches 12S and aggregation switches 12A is based on systems having a multi-stage Clos architecture. There are many examples of such systems in the industry. A typical configuration may be based on integrated circuits that include fully-featured Ethernet switches, which are deployed at a client-facing "edge" and provide packet processing (e.g., deep buffering, scheduling, shaping, prioritization, etc.) and framing packets into standard size cells. An example of the integrated circuits includes Jericho System-on-Chip (SoC) switch-router chips from Broadcom. A centralized fabric is composed of much simpler fabric element switches, which only support a very simple standard-size cell forwarding and minimal buffering.
The SoC switch-router chips also implement a Virtual Output Queues (VOQ) function, whereby a transmitter (TX) port indicates the amount of traffic that is buffered to a particular receiver (RX) destination port, and the RX maintains a record of such requests and issues TX credits to make sure that the RX port is not oversubscribed. Thus, the RX controls traffic injection into the system, while most buffering occurs at the TX side. The architecture is based on Clos configuration, such that a centralized switch fabric is deployed on day one of establishing a data center. Since each path is the same length, cells are forwarded via random paths (e.g., Equal-Cost Multi-Path (ECMP) routing) without controlling flow paths. Also, there may be a cell order reassembly at the RX ports.
The Clos-based configuration with VOQ buffering may be simple to operate, follows well-accepted industry standards, and may be efficient when fully filled. However, it also has a number of drawbacks. First, the centralized switch fabric of the Clos system must be deployed on day one, regardless of the number of client connections. Also, depending on the overall system port count, the system may include several layers of fabric element switches that are required, with a large fraction of ports (i.e., which increases the cost, size, and power being consumed) for internal scale-out interconnect.
Another drawback is that packets in the Clos system are buffered exclusively at the ingress to the large composite switch. Therefore, sufficient memory and memory bandwidth must be allocated to deal with local ingress packet congestion. Ingress memory must be sized such that each individual ingress location can fully deal with local congestion.
Clos type multi-layer fabrics need some redundancy and may have resilience limitations, depending on how many centralized elements are deployed and in what configuration. Lower cost configurations generally have reduced resilience to failures. Also, Clos configurations have lower throughput, higher latency, higher cost, and higher power compared to flat networks described with respect to the embodiments defined below. Also, longer Clos cables require more expensive Active Optical Cables (AOCs), instead of Direct Attach Cables (DACs). Existing products force a single physical mode for their fabrics: 100% on PCB traces or 100% on cables, not both.
Therefore, there is a need to provide a data center architecture that is able to overcome the drawbacks of the conventional systems. Also, data centers may benefit by having a way to gradually grow or scale to different network sizes based on current demand and the number of services being offered to customers.

Programmatically configured switches and distributed buffering across fabric interconnect


Techniques for providing semantic search of a data store are disclosed. A similarity metric of a document comprising the data store to a concept represented in a semantic model derived at least in part from a reference source that includes content not included in the data store is determined. A relevance metric of a search query to the concept is computed. The similarity metric and the relevance metric are used to determine, at least in part, a ranking of the document with respect to the search query.

In the field of information retrieval, semantic search techniques have been used to build a semantic model from a set of documents (webpages, emails, or documents on a file system, for example), and given a search query, find the set of documents that best relate to that query. The conventional method has been to build an inverted index of all words in a document across all documents, and then using various relevancy metrics, compare the words of the search query (assumed to be another kind of document) against the index, and finding a ranked set of files that are 'closest' to the query. In practice, this serves to simulate semantic search because words that represent a semantic concept tend to cluster together in co-occurrences.
Early methods involved techniques such as Latent Semantic Analysis to calculate the singular value decomposition (SVD) of a matrix derived from the inverted document-word index. For reasonable accuracy, one must specify the k number of dimensions in the Eigen decomposition ahead of time, which can dramatically affect overall search results. More recent approaches, based on principled probabilistic models that bypass the resource intensive SVD computation, including probabilistic latent semantic analysis (PLSA) and ranking support vector machines (SVMs), accomplish the same task, but also require that the number of concepts be known at training time.
While this works quite well in limited domains (such as spam-mail filtering), it proves infeasible for full-fledged desktop search. This is typically due to: a) the user has few or no files to create an index, leading to sparsity of data, and therefore sub-optimal searches; b) the user has hundreds of gigabytes of data, leading to huge indexes and inexcusable computation times when building the model; or c) even with a reasonable index size, it can be difficult finding the optimal k parameter for each individual dataset.

Semantic search using a single-source semantic model