A method for polysilicon crystallization by simultaneous laser and rapid thermal annealing is disclosed. In the method, a substrate that has an amorphous silicon layer on top is first provided and positioned on a conveyor situated inside a temperature-controlled chamber. The temperature-controlled chamber is equipped with a window in a top wall that is substantially transparent to thermal and laser energy. A beam of thermal energy and simultaneously a beam of laser energy merged with the thermal energy is then directed through the window onto a top surface of the substrate to convert an amorphous silicon film into a polysilicon film.

The present invention generally relates to a method for crystallization of an amorphous silicon film into a polysilicon film and more particularly, relates to a method for polysilicon crystallization from amorphous silicon by a simultaneous laser and rapid thermal annealing process.
There are numerous methods for converting an amorphous silicon into crystallized polysilicon has been developed and used. Excimer laser crystallization of amorphous silicon films is a promising method for fabricating polysilicon thin film transistor on glass substrate for application of active matrix liquid crystal displays. Excimer laser annealing has been shown to be superior to other crystallization techniques because of its high efficiency. In addition, it is a low temperature processing technique since the entire process takes place in only about 200 ns, consequently inducing a shallow heat-affected zone in the glass material. This interesting feature of excimer laser crystallization allows the use of inexpensive glass substrates instead of quartz substrates.
When a silicon film is deposited at a deposition temperature below 450xc2x0 C. using plasma enhanced chemical vapor deposition, the deposited film exhibits an amorphous structure. This can be confirmed by the fact that only a detraction pattern of defuse rings can be found in a transmission electron microscope image.
To convert an amorphous silicon to polysilicon, a subsequent annealing process after deposition can be used. The excimer laser process, furnace or rapid thermal annealing process, can be used to crystallize the amorphous film to polycrystalline.
While furnace annealing and laser annealing have been used to convert amorphous silicon to polysilicon, both techniques have severe drawbacks and limitations. For instance, in the conventional fabrication process for polysilicon thin film transistors, an excimer laser is used for annealing or crystallization of an amorphous silicon film. Since the excimer laser is of the pulse laser type, the period between pulses is only between 40 and 100 nano-seconds. Moreover, the energy of each pulse is in the low range of about 1 joule. As a result, the excimer laser is only effective in annealing a small area by scanning and a high level of overlapping is necessary to make up for the short period characteristics of the excimer laser and to obtain a satisfactory crystallization result. The conventional excimer laser therefore can only produce a low throughput for the crystallization process. Moreover, the variation in energy level between pulses of the excimer laser renders the process control difficult leading to a narrow process window that is available for the laser annealing method.
The conventional furnace annealing process, or the rapid thermal annealing (RTA) process, while producing high enough throughput for crystallization, the polycrystalline produced does not have the necessary high quality of large grain crystals, especially when compared to the grain size of crystals obtained by the laser annealing process.
It is therefore an object of the present invention to provide a method for polysilicon crystallization from amorphous silicon that does not have the drawbacks or shortcomings of the conventional thermal or laser annealing methods.
It is another object of the present invention to provide a method for polysilicon crystallization by the simultaneous annealing of laser energy and thermal energy.
It is another object of the present invention to provide a method for polysilicon crystallization by the simultaneous annealing of an excimer laser and the thermal energy from a Xe arc heating source.
It is another further object of the present invention to provide a method for polysilicon crystallization by moving a substrate on a conveyor under a combined energy source of laser and heat.
It is still another object of the present invention to provide a method for polysilicon crystallization by first merging an energy beam of laser and an energy beam of a thermal source and then irradiating the merged beam onto an amorphous silicon surface.
It is yet another object of the present invention to provide a method for polysilicon crystallization by using an excimer laser and a tubular Xe arc lamp simultaneous producing a merged energy beam on an amorphous silicon film.
In accordance with the present invention, a method for polysilicon crystallization by simultaneous laser and rapid thermal annealing is provided.
In a preferred embodiment, a method for polysilicon crystallization by simultaneous laser and rapid thermal annealing can be carried out by the operating steps of first providing a substrate that has an amorphous silicon layer on top; positioning the substrate on a conveyor situated inside a temperature-controlled chamber; providing a window that is substantially transparent to thermal and laser energy in a top wall of the temperature-controlled chamber; and directing a beam of thermal energy and simultaneously a beam of laser energy merging with the beam of thermal energy through the window onto a top surface of the substrate converting the amorphous silicon into polysilicon.
The method for polysilicon crystallization by simultaneous laser and rapid thermal annealing may further include the step of mounting a quartz window in the top wall of the temperature-controlled chamber, or the step of positioning a partially reflective lens in a path of the beam of thermal energy, or the step of positioning a partially transmissive lens in a path of the beam of thermal energy.
The method may further include the step of generating the beam of thermal energy by a radiation source selected from the group consisting of Xe arc lamp, Ar arc lamp, Kr arc lamp and W/halogen lamp. The method may further include the step of generating the beam of laser energy by an excimer laser source, or the step of generating the beam of laser energy by a XeCl laser source. The method may further include the step of producing the thermal energy by a tubular Xe arc lamp. The method may further include the step of reflecting incident beams of the thermal energy emitted by an arc lamp of a partially reflective lens prior to passing through the window, or the step of directing the beam of laser energy in a straight line through the partially reflective lens prior to passing through the window, or the step of reflecting thermal energy of a tubular Xe arc lamp by an oval-shaped mirror producing the incident beams.
The present invention is further directed to a method for crystallizing an amorphous silicon film into a polysilicon film by simultaneously irradiating with laser and thermal energy which can be carried out by the operating steps of first producing a laser beam and directing downwardly through a window into a process chamber; producing a thermal energy beam for reflecting downwardly by a partially reflective lens through the window merging with the laser beam; directing the merged laser and thermal energy beams onto an amorphous silicon film on a pre-processed substrate; and moving the pre-processed substrate linearly under the merged laser and thermal energy beams at a predetermined speed until the amorphous silicon film is converted to polysilicon film.
The method for crystallizing an amorphous silicon film into a polysilicon film by simultaneously irradiating with laser and thermal energy may further include the step of positioning a partially transmissive lens between a laser beam source and the pre-processed substrate for merging the laser beam with the thermal energy beam. The method may further include the step of positioning a partially reflective lens between a thermal energy source and the pre-processed substrate for merging the laser beam with the thermal energy beam. The partially reflective lens may be partially transmissive. The method may further include the step of preheating the process chamber to a temperature of at least 600xc2x0 C., or the step of moving the pre-processed substrate on a conveyor at a speed higher than 1 cm/min. The method may further include the step of producing the laser beam by an excimer laser source, such as an XeCl laser source. The method may further include the step of producing the thermal energy beam by a source selected from the group consisting of Xe arc lamp, Ar arc lamp, Kr arc lamp and W/halogen lamp.

Method for polysilicon crystallization by simultaneous laser and rapid thermal annealing

Industrial Technology Research Institute


The purpose of the present invention is to estimate, with a small amount of computation, a linear prediction synthesis filter after conversion of an internal sampling frequency. A linear prediction coefficient conversion device is a device that converts first linear prediction coefficients calculated at a first sampling frequency to second linear prediction coefficients at a second sampling frequency different from the first sampling frequency, which includes a means for calculating, on the real axis of the unit circle, a power spectrum corresponding to the second linear prediction coefficients at the second sampling frequency based on the first linear prediction coefficients or an equivalent parameter, a means for calculating, on the real axis of the unit circle, autocorrelation coefficients from the power spectrum, and a means for converting the autocorrelation coefficients to the second linear prediction coefficients at the second sampling frequency.

An autoregressive all-pole model is a method that is often used for modeling of a short-term spectral envelope in speech and audio coding, where an input signal is acquired for a certain collective unit or a frame with a specified length, a parameter of the model is encoded and transmitted to a decoder together with another parameter as transmission information. The autoregressive all-pole model is generally estimated by linear prediction and represented as a linear prediction synthesis filter.
One of the latest typical speech and audio coding techniques is ITU-T Recommendation G.718. The Recommendation describes a typical frame structure for coding using a linear prediction synthesis filter, and an estimation method, a coding method, an interpolation method, and a use method of a linear prediction synthesis filter in detail. Further, speech and audio coding on the basis of linear prediction is also described in detail in Patent Literature 2.
In speech and audio coding that can handle various input/output sampling frequencies and operate at a wide range of bit rate, which vary from frame to frame, it is generally required to change the internal sampling frequency of an encoder. Because the same operation is required also in a decoder, decoding is performed at the same internal sampling frequency as in the encoder. FIG. 1 shows an example where the internal sampling frequency changes. In this example, the internal sampling frequency is 16,000 Hz in a frame i, and it is 12,800 Hz in the previous frame i−1. The linear prediction synthesis filter that represents the characteristics of an input signal in the previous frame i−1 needs to be estimated again after re-sampling the input signal at the changed internal sampling frequency of 16,000 Hz, or converted to the one corresponding to the changed internal sampling frequency of 16,000 Hz. The reason that the linear prediction synthesis filter needs to be calculated at a changed internal sampling frequency is to obtain the correct internal state of the linear prediction synthesis filter for the current input signal and to perform interpolation in order to obtain a model that is temporarily smoother.
One method for obtaining another linear prediction synthesis filter on the basis of the characteristics of a certain linear prediction synthesis filter is to calculate a linear prediction synthesis filter after conversion from a desired frequency response after conversion in a frequency domain as shown in FIG. 2. In this example, LSF coefficients are input as a parameter representing the linear prediction synthesis filter. It may be LSP coefficients, ISF coefficients, ISP coefficients or reflection coefficients, which are generally known as parameters equivalent to linear prediction coefficients. First, linear prediction coefficients are calculated in order to obtain a power spectrum Y(ω) of the linear prediction synthesis filter at the first internal sampling frequency (001). This step can be omitted when the linear prediction coefficients are known. Next, the power spectrum Y(ω) of the linear prediction synthesis filter, which is determined by the obtained linear prediction coefficients, is calculated (002). Then, the obtained power spectrum is modified to a desired power spectrum Y′ (ω) (003). Autocorrelation coefficients are calculated from the modified power spectrum (004). Linear prediction coefficients are calculated from the autocorrelation coefficients (005). The relationship between the autocorrelation coefficients and the linear prediction coefficients is known as the Yule-Walker equation, and the Levinson-Durbin algorithm is well known as a solution of that equation.
This algorithm is effective in conversion of a sampling frequency of the above-described linear prediction synthesis filter. This is because, although a signal that is temporally ahead of a signal in a frame to be encoded, which is called a look-ahead signal, is generally used in linear prediction analysis, the look-ahead signal cannot be used when performing linear prediction analysis again in a decoder.
As described above, in speech and audio coding with two different internal sampling frequencies, it is preferred to use a power spectrum in order to convert the internal sampling frequency of a known linear prediction synthesis filter. However, because calculation of a power spectrum is complex computation, there is a problem that the amount of computation is large.

This patent is subject to a terminal disclaimer.

Linear prediction coefficient conversion device and linear prediction coefficient conversion method


In a device for analog-to-digital converting an input signal, the input signal is applied to a plurality of delay units constituting a pulse delay circuit in order to change a delay time to be given by the delay units. The number of delay units through which a pulse signal has passed during one period of sampling clocks is numerically expressed. The A/D conversion device has a plurality of pulse position numerizing units that is used for A/D conversion. Sampling clocks of which the phases are different from one another are applied to the respective pulse position numerizing units. An adder summates numerical data items produced by the respective pulse position numerizing units so as to generate final numerical data representing a result of A/D conversion.

1. Field of the Invention
The present invention relates to an analog-to-digital (A/D) conversion method and device for converting an analog input signal into numerical data using a pulse delay circuit that has a plurality of delay units, which delay and transmit a pulse signal, connected in series with one another.
2. Description of the Related Art
In the past, A/D conversion devices known as types of A/D conversion devices that provides high-resolution digital data despite a simple configuration include a pulse delay circuit that has a plurality of delay units, which are realized with various kinds of gate circuits, connected annularly. In the A/D conversion device, an analog input signal, that is an object of A/D conversion, is transmitted as a supply voltage to the pulse delay circuit. At the same time, a transmission pulse signal is applied to the pulse delay circuit. Consequently, the pulse signal is circulated through the pulse delay circuit at a speed dependent on the delay time of the delay units. The number of delay units in the pulse delay circuit through which the pulse signal passes within a predetermined sampling time during the circulation of the pulse signal is counted. Thus, the analog input signal is converted to numerical data (refer to, for example, Japanese Unexamined Patent Application Publication No. 5-259907).
The A/D conversion device utilizes the fact that a delay time to be given by the delay units varies depending on a supply voltage. Since an analog input signal is transmitted as a supply voltage to the delay units included in the pulse delay circuit, the speed at which a pulse signal circulates through the pulse delay circuit is changed with the analog input signal. The moving speed is measured by counting the number of delay units through which the pulse signal has pass through within the predetermined sampling time. The result of the measurement (count value) is provided as numerical data resulting from A/D conversion.
According to the A/D conversion device, a voltage resolution to be expressed by resultant numerical data can be determined with a delay time given by one stage of a delay unit included in the pulse delay circuit and a sampling time required for A/D conversion. In order to increase the voltage resolution expressed by the numerical data, the delay time to be given by one stage of a delay unit is shortened or the sampling time is extended. Consequently, an A/D conversion device capable of realizing high-precision A/D conversion can be provided inexpensively with a simple configuration.
However, in the foregoing A/D conversion device, the delay time to be given by one stage of a delay unit included in the pulse delay circuit is determined by a fineness level (a rule for CMOS design). The fineness level indicates how fine circuit elements (inverters or other gate circuits) included in each delay unit are. Even if an attempt is made to shorten a delay time of one stage of a delay unit included in the pulse delay circuit for the purpose of improving a resolution to be offered through A/D conversion, there are limitations.
Moreover, when, in the A/D conversion device, the sampling time required for A/D conversion is extended in order to improve a resolution to be offered through A/D conversion, and the A/D conversion device is employed in a system required to achieve high-speed A/D conversion at an A/D conversion speed ranging from, for example, several megahertz to several tens of megahertz, the system would suffer from insufficient speed. The system could not satisfy a requirement for high-speed A/D conversion.
The foregoing A/D conversion device is a so-called integrating type A/D conversion device. Produced digital data is a result of integration performed on a variable component of an analog input signal over a sampling time required for A/D conversion. Therefore, if the sampling time required for A/D conversion is extended in order to improve a resolution to be offered through A/D conversion, quantity of variation of the analog input signal cannot be reflected on the resultant digital data. The A/D conversion device cannot be employed in a system requested to achieve high-speed A/D conversion.
Therefore, a system that requires the speed and precision of A/D conversion conventionally employs a successive approximation type A/D conversion device or a parallel type A/D conversion device (also called a flash type A/D conversion device). The successive approximation type A/D conversion device can achieve A/D conversion at a higher speed than the aforesaid integrating type A/D conversion device can. The parallel type A/D conversion device can achieve A/D conversion instantaneously.
In order to improve the resolution offered through A/D conversion by the successive approximation type A/D conversion device or parallel type A/D conversion device, numerous reference voltages must be produced according to the required resolution. Therefore, a system that requires the speed and precision of A/D conversion must employ an expensive A/D conversion device having a complex configuration. This invites an increase in the cost of the entire system.
The present invention attempts to solve the foregoing problem. Accordingly, an object of the present invention is to provide an A/D conversion method for converting an analog signal into digital data at high speed with high precision using an A/D conversion device that can be realized inexpensively with a simple configuration, and the A/D conversion device.
According to an A/D conversion method in which a first embodiment of the present invention is implemented in order to accomplish the object, a delay time to be given by delay units constituting a pulse delay circuit is changed with an analog input signal. A pulse signal is applied to the pulse delay circuit and transferred within the pulse delay circuit. The position of the pulse signal within the pulse delay circuit is numerically expressed at a plurality of different timings. The results of the numerical expression are summated in order to produce numerical data representing the analog input signal.
According to the A/D conversion method of the present invention, similarly to the method implemented in the aforesaid conventional A/D conversion device, the pulse delay circuit is used to convert the analog input signal into numerical data. During the A/D conversion, the position of the pulse signal within the pulse delay circuit is not numerically expressed at the timing that a predetermined time has elapsed since the pulse signal is applied to the pulse delay circuit, but numerically expressed at a plurality of different timings. The results of the numerical expression are summated in order to produce numerical data.
Herein, the number of bits constituting numerical data that results from the numerical expression of the position of the pulse signal within the pulse delay circuit is n, and the number of numerical data items produced at the plurality of different timings is m. In this case, the number of bits constituting numerical data produced by the A/D conversion method of the present invention is provided as n+log2m.
The numerical data n+log2m bits long corresponds to an average of numerical data items produced at the plurality of different timings. Consequently, a voltage resolution expressed by final numerical data is higher than that expressed by numerical data produced according to the conventional method.
According to the A/D conversion method of the present invention, the action of numerically expressing the position of the pulse signal within the pulse delay circuit is not merely performed a plurality of times. The plurality of timings at which the numerical expression is performed is differentiated from one another. The time required for A/D conversion is not longer than the one required according to the conventional method. A/D conversion can be achieved with high precision by taking the same time as the one required by the conventional method. Moreover, if a voltage resolution expressed by numerical data resulting from summation may be of the same level as the one provided by the conventional method, the time required for A/D conversion can be shortened.
According to the A/D conversion method of the present invention, an A/D conversion device capable of converting an analog input signal into digital data at a higher speed with higher precision can be realized without the necessity of shortening a delay time to be given by one stage of a delay unit or of extending a sampling time.
Moreover, unlike the successive approximation type or parallel type A/D conversion device, the A/D conversion device need not produce a reference voltage with which an analog input signal is compared. The A/D conversion device can be realized inexpensively with the configuration thereof simplified. Consequently, by utilizing the method of the present invention, a system that requires speed and precision in A/D conversion can be realized at a lower cost than a conventional system can.
Herein, the number of pulse delay circuits employed in A/D conversion may be identical to the number of timings at which the numerical expression is performed. More preferably, one pulse delay circuit is, as it is in a second embodiment, used to numerically express the position of a pulse signal. The position of the pulse signal within the pulse delay circuit is numerically expressed at different timings.
In this way, the configuration of an A/D conversion device in which the method of the present invention is implemented can be simplified. Moreover, numerical data items produced at the respective timings can be prevented from becoming uncertain because of differences among a plurality of pulse delay circuits occurring in the process of manufacture. Consequently, a result of A/D conversion can be provided with higher precision.
According to the method of the present invention, the analog input signal is used to change the delay time to be given by the delay units constituting the pulse delay circuit. As for a method of changing the delay time, which is given by the delay units, using the analog input signal, for example, a method employed in a third embodiment may be adopted. Namely, the analog input signal may be applied as a driving voltage, with which the delay units are driven, to the pulse delay circuit. Otherwise, the analog input signal may be, as it is in a fourth embodiment, applied as a signal, with which a driving current flowing into the delay units is controlled, to the pulse delay circuit.
Specifically, each of the delay units constituting the pulse delay circuit is normally composed of inverters or other gate circuits. The larger a driving voltage or driving current, the higher the operating speed of each delay unit. Therefore, according to the third or fourth embodiment, the analog input signal is applied as a driving voltage control signal or a driving current control signal, with which a driving voltage or current input to the delay units is controlled, to the pulse delay circuit. Thus, the delay time to be given by the delay units constituting the pulse delay circuit can be changed readily according to the voltage level of the analog input signal.
On the other hand, according to the method of the present invention, the position of a pulse signal within the pulse delay circuit is numerically expressed at the aforesaid timings. An average of the results of numerical expression is used to produce numerical data representing the analog input signal. This sequence of A/D conversion may be performed once after application of the pulse signal to the pulse delay circuit. However, when A/D conversion is performed according to the sequence, the continuously variable analog input signal cannot be sequentially analog-to-digital converted (A/D-converted) at a high speed.
In order to repeatedly analog-to-digital convert (A/D-convert) an analog input signal at intervals of a predetermined A/D conversion cycle in the same manner as in a typical A/D conversion device, a plurality of numerical data items to be summated may be produced according to a procedure employed in a fifth embodiment.
In an A/D conversion method of the fifth embodiment, the position of a pulse signal within a pulse delay circuit is repeatedly numerically expressed synchronously with a plurality of sampling clocks that have the same cycle but are out of phase with one another. Based on a deviation of new data representing the numerically expressed position of the pulse signal from previous data representing it, the number of delay units within the pulse delay circuit through which the pulse signal has passed during one cycle of the sampling clocks is calculated. Thus, a plurality of numerical data items to be summated is produced.
Consequently, when the numerical data items are summated synchronously with one of the plurality of sampling clocks, a result of A/D conversion performed on an analog input signal can be obtained once each cycle of the sampling clock. Eventually, A/D conversion of the analog input signal can be achieved repeatedly at a high speed with high precision.
As mentioned above, a plurality of sampling clocks is used to express the number of delay units, through which a pulse signal has passed within a pulse delay circuit, during one cycle of the sampling clocks so as to produce numerical data items. In this case, the sampling clocks should be out of phase with one another.
The sampling clocks to be applied to each pulse position numerizing means are out of phase with each other by a difference, which ranges from several tens of picosecond to several nanosecond, because of a jitter stemming from white noise occurring within the circuit. A phase difference is also caused by a difference of the length of an input path along which one sampling clock is applied to each pulse position numerizing means from the length of an input path along with another sampling clock is applied thereto.
A phase of the sampling clocks to be applied to each pulse position numerizing means need not be intentionally make different one another in order to improve a resolution to be offered through A/D conversion. Preferably, the phases of the sampling clocks are determined as they are in a sixth embodiment, so that the timings of numerical expressions determined with the respective sampling clocks will be different from one another by certain times. More preferably, the phases of the sampling clocks are determined as they are in a seventh embodiment, so that the timings of numerical expression synchronous with the respective sampling clocks are different from one another at even intervals of one cycle of each sampling clock.
In other words, when the phases of the sampling clocks are determined as they are in the sixth embodiment, the timings of numerical expression performed for producing numerical data items that are to be summated are different from one another by an equal duration. Consequently, by summating the numerical data items, numerical data representing a continuously variable analog input signal can be averaged accurately. This results in improved precision in A/D conversion.
Moreover, the phases of the sampling clocks may be determined as they are in a seventh embodiment. Especially in this case, numerical data items produced synchronously with the respective sampling clocks may be summated at the respective timings of the rising or falling edges of the associated sampling clocks. Therefore, numerical data resulting from A/D conversion of an analog input signal can be produced a plurality of times within one cycle of the sampling clocks. Thus, A/D conversion can be achieved at a higher speed.
Moreover, when a plurality of sampling clocks is, as mentioned above, used to produce numerical data items to be summated, a time calculated by adding a maximum value of a phase difference between sampling clocks to the cycle of the sampling clocks may be longer than the time from the instant a pulse signal was applied to the pulse delay circuit to the instant the pulse signal passes through all the delay units included in the pulse delay circuit. This makes it impossible to produce numerical data expressing the number of delay units through which the pulse signal passes within the pulse delay circuit during one cycle of the sampling clocks. Eventually, an analog input signal cannot be A/D-converted highly precisely.
In order to implement the A/D conversion method of the fifth embodiment, the sampling clocks are preferably defined as they are in an eighth embodiment. Preferably, the time which is calculated by adding a maximum value of a phase difference between sampling clocks to the cycle of the sampling clocks should be equal to or shorter than at least the time from the instant a pulse signal was applied to the pulse delay circuit to the instant the pulse signal passes through all the delay units included in the pulse delay circuit.
By the way, as mentioned above, numerical data items to be summated are repeatedly produced using a plurality of sampling clocks. In this case, if the pulse delay circuit is formed as a delay line that transmits a pulse signal, the number of delay units constituting the pulse delay circuit must be very large. However, if the number of delay units increases, the number of circuit elements (including transistors) constituting the pulse delay circuit increases. This invites an increase in the scale of circuitry.
In order to implement the A/D conversion method of the fifth embodiment, more preferably, a procedure employed in a ninth embodiment is adopted. Specifically, a pulse circulation circuit which has delay units concatenated annularly and through which a pulse signal is circulated is adopted as the pulse delay circuit. A circulation-number counter is used to count the number of times by which the pulse signal has circulated through the pulse circulation circuit after being applied to the pulse circulation circuit. The position of the pulse signal within the pulse circulation circuit is numerically expressed synchronously with an associated one of the sampling clocks. Numerical data having as low-order bit data numerical data resulting from the numerical expression, and having as high-order bit data the number of times by which the pulse signal is circulated and which is counted by the circulation-number counter is produced. Based on a deviation of a new one of the produced numerical data from previous one thereof, the number of delay units through which the pulse signal has passed during one cycle of the sampling clocks is calculated.
In this case, the pulse signal repeatedly passes through the annularly concatenated delay units in the pulse delay circuit. Even if the number of delay units constituting the pulse delay circuit is decreased, A/D conversion can be repeatedly performed over a prolonged period of time.
In this case, the cycle of the sampling clocks may get longer than the time from the instant the pulsating signal was applied to the pulse delay circuit to the instant the circulation-number counter overflows. In this case, the circulation-number counter overflows a plurality of times within one cycle of the sampling clocks. Consequently, the number of times by which the pulse signal has circulated through the pulse delay circuit (pulse circulation circuit) within one cycle of the sampling clocks cannot be calculated accurately from a count value presented by the circulation-number counter. Eventually, an analog input signal cannot be A/D-converted highly precisely.
In order to implement the A/D conversion method of the ninth embodiment, preferably, the sampling clocks are defined as they are in a tenth embodiment. Specifically, the sampling clocks are defined so that the cycle of the sampling clocks will be equal to or shorter than the time from the instant a pulse signal was applied to the pulse delay circuit to the instant the circulation-number counter overflows.
According to the A/D conversion methods described as the fifth embodiment to the tenth embodiment, the plurality of sampling clocks that has the same cycle but is out of phase with one another is employed, and A/D conversion is performed synchronously with the respective sampling clocks. A sampling time per A/D conversion that is performed using the sampling clocks (in other words, the sensitivity offered through A/D conversion) remains constant. The sensitivity to an analog input signal offered by the result (numerical data) of A/D conversion achieved using the sampling clocks remains constant.
Consequently, a resolution expressed by final numerical data calculated by summating the results of A/D conversion is improved according to the number m of sampling clocks. However, as long as an analog input signal remains constant and within a resolution, which is offered through A/D conversion performed using the sampling clocks, the finally produced numerical data always assumes a fixed value. The resolution expressed by the numerical data cannot be improved.
In order to improve the resolution expressed by final numerical data, the sampling time per A/D conversion (in other words, the sensitivity offered through A/D conversion) should be changed for each of the plurality of times of A/D conversion. For this purpose, any of A/D conversion methods provided as eleventh to fifteenth embodiments may be adopted.
According to the A/D conversion method of the eleventh embodiment, the position of a pulse signal that changes within a pulse delay circuit is numerically expressed during sampling times that are different from one another by a predetermined unit time. Thus, a plurality of numerical data items to be summated is produced.
According to the A/D conversion method of the eleventh embodiment, the position of a pulsating signal that changes within the pulse delay circuit is not numerically expressed during the same sampling time determined with the cycle of the sampling clocks. Instead, the position of the pulsating signal that changes within the pulse delay circuit is numerically expressed during the respective sampling times which are different from one another by the predetermined unit time.
Consequently, according to the A/D conversion method of the eleventh embodiment, the sensitivity offered at each time of A/D conversion performed for producing numerical data items to be summated varies depending on a difference between adjoining sampling times. Eventually, the resolution expressed by numerical data finally produced by summating the results of A/D conversion can be improved more successfully than it can according to the A/D conversion methods of the fifth to tenth embodiments.
Moreover, when A/D conversion is performed within the pulse delay circuit, a resolution exhibited by numerical data that is a result of A/D conversion is determined with a delay time Td to be given by one stage of a delay unit included in the pulse delay circuit. In order to A/D-convert an analog input voltage more accurately according to the A/D conversion method of the eleventh embodiment, a unit time by which a sampling time is different from an adjoining sampling time may be determined as it is in a twelfth embodiment. Specifically, the unit time by which one sampling time is different from an adjoining sampling time is set to a time (Td/m) calculated by dividing a delay time (Td) to be given by the delay units constituting the pulse delay circuit by the number (m) of sampling times. Otherwise, the unit time is set to a time calculated by adding an integral multiple (Td, 2Td, 3Td, etc.) of the delay time (Td) to be given by the delay units to the time Td/m.
In this case, resolutions exhibited by numerical data items produced during each sampling times (in other words, voltage levels corresponding to the least significant bits of the respective numerical data items) are different from each other by 1/m of a resolution determined with the delay time (Td) to be given by the delay units that delay the pulse signal within the pulse delay circuit. Consequently, a resolution expressed by numerical data finally produced through summation can be improved.
According to the A/D conversion method of the eleventh embodiment, A/D conversions are performed a plurality of times during different sampling times, using the pulse delay circuit. For each A/D conversion, a plurality of sampling times must be determined. For determining the sampling times, m sampling clocks having the same cycle and being out of phase with one another by a unit time may be employed according to a thirteenth embodiment.
In this case, the sampling clocks may be, according to a fourteenth embodiment, readily produced by delaying a reference clock having a certain cycle by times that are integral multiples of the unit time.
However, according to the A/D conversion method of the thirteenth embodiment, all the sampling clocks have the same cycle. In order to define m sampling times, which are different from one another, using the sampling clock having the same clock, the sampling times are preferably determined as according to a fifteenth embodiment. Specifically, one of m sampling times is set to a period from the rising or falling edge of a specific sampling clock, which phase leads to the maximum among the m sampling clocks, to the next rising or falling edge thereof. The other sampling times are set to periods from the rising or falling edge of the specific sampling clock to the rising or falling edges of the other sampling clock.
In this case, one of the m sampling times equals a reference cycle Ts synchronous with the cycle of the specific sampling clock. The cycle of the other sampling clock equals a time (Ts+1xc3x97unit time, Ts+2xc3x97unit time, Ts+3xc3x97 unit time, etc.) calculated by adding an integral multiple of a unit time (1xc3x97unit time, 2xc3x97unit time, 3xc3x97unit time, etc.) to the reference cycle Ts. Consequently, the A/D conversion method (provided as the eleventh or twelfth embodiment of the present invention) in which the present invention is implemented can be realized readily.
As mentioned above, according to the A/D conversion methods of the eleventh to fifteenth embodiments, the position of a pulse signal that changes within the pulse delay circuit is expressed numerically during sampling times which are different from one another by a predetermined unit time. Thus, a plurality of numerical data items exhibiting different resolutions is produced, and then summated. Consequently, an analog input signal is A/D-converted with high precision. Ideas implemented in the A/D conversion methods of the eleventh to fifteenth embodiments can be adapted not only to the integrating type A/D conversion device having the pulse delay circuit but also to the other integrating type A/D conversion devices including, for example, a double integral (sequential integral) type A/D conversion device. Moreover, the ideas can be adapted to other types of A/D conversion devices including the successive approximation type A/D conversion device and parallel type A/D conversion device.
According to the sixteenth embodiment, a plurality of A/D conversion circuits that offer different voltage resolutions which are exhibited by numerical data items that are results of A/D conversion is used to numerically express an analog input signal. The results of numerical expression performed by the respective A/D conversion circuits are summated in order to produce numerical data representing the analog input signal. Thus, the same technological ideas as those implemented in the eleventh embodiment can be adapted not only to the A/D conversion device having the pulse delay circuit but also to the other integrating types A/D conversion devices or the successive approximation type or parallel type A/D conversion device. The same advantages as those of the eleventh embodiment can be provided.
However, in this case, in order to achieve A/D conversion as precisely as that according to the twelfth embodiment, voltage resolutions to be offered by the A/D conversion circuits are preferably determined according to a seventeenth embodiment. Specifically, the voltage resolutions to be offered by the A/D conversion circuits are set to resolutions obtained by shifting a predetermined reference resolution in units of a unit resolution calculated by dividing the predetermined reference resolution by the number of A/D conversion circuits.
The following eighteenth to twenty-fifth embodiments are concerned with A/D conversion devices suitable for implementing the aforesaid A/D conversion methods (provided especially as the first to tenth embodiments) of the present invention.
The A/D conversion device of the eighteenth embodiment includes a pulse delay circuit having a plurality of delay units connected in series with one another. Each of the delay units delays a pulse signal by a delay time corresponding to the voltage level of an analog input signal, and transfers the resultant signal. Moreover, m pieces of pulse position numerizing means detect the position of the pulse signal within the pulse delay circuit at the respective timings of the rising or falling edges of m sampling clocks that are out of phase with one another. The detected positions of the pulse signal are expressed numerically. An adding means summates numerical data items produced by the respective pieces of pulse position numerizing means, and transmits the result of the summation as numerical data representing the analog input signal.
In the A/D conversion device, an analog input signal can be converted into numerical data according to the A/D conversion method of the first embodiment. Compared with the aforesaid conventional A/D conversion device, the analog input signal can be A/D-converted at a high speed with high precision without the necessity of shortening a delay time to be given by one stage of a delay unit.
The A/D conversion device of the nineteenth embodiment is identical to the A/D conversion device of the eighteenth embodiment except that clock signals which vary at intervals of the same cycle are used as the m sampling clocks. The pieces of pulse position numerizing means repeatedly numerically express the position of a pulse signal within the pulse delay circuit at the respective timings of the rising or falling edges of the associated sampling clocks. A deviation of new data representing the numerically expressed position of the pulse signal from previous data representing it is calculated in order to produce numerical data expressing the number of delay units within the pulse delay circuit through which the pulse signal has passed within one cycle of the sampling clocks.
In the A/D conversion device of the nineteenth embodiment, the analog input signal can be converted into numerical data according to the A/D conversion method of the fifth embodiment. A/D conversion of the analog input signal can be repeatedly performed at intervals of a certain cycle corresponding to the cycle of the sampling clocks.
Moreover, the A/D conversion device of the twentieth embodiment includes a pulse circulation circuit, which has delay units concatenated annularly, as a pulse delay circuit. A pulse signal is circulated through the pulse circulation circuit. A circulation-number counter counts the number of times by which the pulse signal has circulated through the pulse circulation circuit.
Each of the pieces of pulse position numerizing means has a pulse position detecting circuit that numerically expresses the position of the pulse signal within the pulse circulation circuit at the timing of the rising or falling edge of an associated sampling clock. An arithmetic circuit included in each of the pieces of pulse position numerizing means calculates a deviation of new numerical data, which has as low-order bit data thereof numerical data produced by the pulse position detecting circuit and has as high-order bit data thereof numerical data produced by the circulation-number counter, from a previous one thereof. The calculated deviation is used to calculate the number of delay units within the pulse delay circuit through which the pulse signal has passed within one cycle of the sampling clocks.
In the A/D conversion device of the twentieth embodiment, an analog input signal can be converted into numerical data according to the A/D conversion method of the ninth embodiment. Although the number of delay units constituting the pulse delay circuit is decreased, A/D conversion can be repeatedly performed over a prolonged period of time.
The A/D conversion device of the twenty-first embodiment has, in addition to the same components as the A/D conversion device of the twentieth embodiment, an input circuit. The input circuit selectively receives a pulse signal from the delay unit of the last stage included in the pulse delay circuit and a test clock used to test the counting action of the circulation-number counter.
In the A/D conversion device of the twenty-first embodiment, a test clock is transferred to the circulation-number counter via the input circuit. The counting action of the circulation-number counter can be tested. The action performed in the A/D conversion device (or the circulation-number counter) can be verified easily.
The A/D conversion devices of the nineteenth to twenty-first embodiments repeatedly perform A/D conversion using m sampling clocks that vary at intervals of a certain cycle. Among the A/D conversion devices, the A/D conversion device of the nineteenth embodiment does not use the pulse circulation circuit serving as the pulse delay circuit. Preferably, the A/D conversion method of the eighth embodiment is adapted to the A/D conversion device of the nineteenth embodiment. Namely, the sampling clocks are defined so that a time calculated by adding a maximum value of a phase difference between adjoining sampling clocks to the cycle of each sampling clock is equal to or shorter than the time from the instant the pulsating signal was applied to the pulse delay circuit to the instant the pulsating signal has passed through all the delay units included in the pulse delay circuit.
Preferably, the A/D conversion method of the tenth embodiment is adapted to the A/D conversion device of the twentieth or twenty-first embodiment that uses the pulse circulation circuit as the pulse delay circuit. Namely, the sampling clocks are defined so that the cycle of the sampling clocks is equal to or shorter than the time from the instant the pulsating signal is applied to the pulse delay circuit to the instant the circulation-number counter overflows.
Preferably, the A/D conversion method of the second embodiment is adapted to the A/D conversion devices of the eighteenth to twenty-first embodiments. Namely, one pulse delay circuit (or one pulse circulation circuit) is used to numerically express the position of a pulse signal.
When a delay time to be given by the delay units constituting the pulse delay circuit (or pulse circulation circuit) is changed corresponding to an analog input signal, the A/D conversion method of the third embodiment may be adopted. Consequently, the analog input signal may be used as a driving voltage with which the delay units are driven. Otherwise, according to the A/D conversion method of the fourth embodiment, a driving current flowing into the delay units may be controlled based on the analog input signal.
Preferably, the A/D conversion method of the sixth embodiment is adapted to the A/D conversion devices of the nineteenth to twenty-first embodiments that repeatedly perform A/D conversion using the m sampling clocks that vary at intervals of a certain cycle. Namely, the sampling clocks are defined so that a phase difference between adjoining sampling clocks will always be set to the same time. More preferably, the A/D conversion method of the seventh embodiment is adapted. Namely, the sampling clocks are defined so that a phase difference between adjoining sampling clocks will correspond to 1/m of one cycle of the sampling clocks.
Especially in the A/D conversion device of the nineteenth embodiment, when a phase difference between adjoining ones of the m sampling clocks corresponds to 1/m of one cycle of each of the sampling clocks, an adding means is configured like the one included in a twenty-second embodiment.
In an A/D conversion device provided as the twenty-second embodiment, the adding means fetches numerical data items from the respective pieces of pulse position numerizing means synchronously with the rising or falling edges of the m sampling clocks applied to the respective pieces of pulse position numerizing means. The adding means then summates the m fetched numerical data items so as to produce numerical data representing an analog input signal at intervals of 1/m of the cycle of the sampling clocks.
In the A/D conversion device, A/D conversion of the analog input signal can be performed at a high speed at intervals of the 1/m of one cycle of the sampling clocks. If the A/D conversion device is adapted to a system that is required to perform A/D conversion at a high speed, more advantages could be provided.
In the A/D conversion device of the nineteenth embodiment, a phase difference between adjoining ones of the m sampling clocks is set to a certain duration corresponding to a 1/m of one cycle of each sampling clock. For this purpose, for example, a sampling clock generating circuit is included as it is in a twenty-third embodiment. Specifically, the sampling clock generating circuit calculates a 1/m of the frequency of an externally applied reference clock, and successively produces m shift clocks which are out of phase with one another by a phase difference corresponding to one cycle of the reference clock. The sampling clock generating circuit then transmits the m shift clocks as sampling clocks.
In an A/D conversion device of the twenty-third embodiment, the cycle of the externally applied reference clock corresponds to a 1/m of the cycle of the sampling clocks that are applied to the respective pieces of pulse position numerizing means. The reference clock may be used as an operating clock synchronously with which the adding means operates (in other words, an operating clock for A/D conversion), and applied to the adding means. In this case, the A/D conversion device of the twenty-second embodiment can be constructed.
In the A/D conversion device of the twenty-third embodiment, the sampling clock generating circuit is realized with a frequency division circuit including a counter. When the frequency of the externally applied reference clock ranges, for example, from 1 MHz to 10 MHz or is a high frequency equal to or higher than 10 MHz, the sampling clock generating circuit may operate too slowly to produce m shift clocks. In this case, the sampling clock generating circuit is configured like the one included in a twenty-fourth embodiment.
Namely, the sampling clock generating circuit included in an A/D conversion device of the twenty-fourth embodiment comprises a delay line and mxe2x88x921 groups of switches. The delay line includes a plurality of delay units which gives a predetermined delay time. A reference clock is transferred while being sequentially delayed by a plurality of stationary delay units. Each of the mxe2x88x921 groups of switches includes a plurality of switches. The switches belonging to each group each have one contact thereof connected to the output node of the respective delay unit included in the delay line, and have the other contact thereof connected to an output path of each shift clock.
In the sampling clock generating circuit, a time A/D conversion means numerically expresses the cycle of an externally applied reference clock. Pieces of switch selecting means multiply numerical data, which is produced by the time A/D conversion means and divided by m, by integers 1 to mxe2x88x921, and thus produce mxe2x88x921 numerical data items. Based on the produced numerical data items, the locations of switches that should be turned on and those belong to the respective groups of switches are specified. The switches at the specified locations are selectively turned on, whereby mxe2x88x921 shift clocks are produced by sequentially delaying a reference clock by a duration that corresponds to a 1/m of the cycle of the reference clock. The shift clocks are transmitted along the output paths extending from the respective groups of switches. The sampling clock generating circuit transmits the reference clock and the mxe2x88x921 shift clocks, which are transmitted along the output paths extending from the respective groups of switches, as m sampling clocks.
In the A/D conversion device of the twenty-fourth embodiment, the sampling clock generating circuit delays the reference clock by a delay time to be given by the delay units constituting the delay line. Herein, the delay time is regarded as a temporal resolution offered by the A/D conversion device. Consequently, the sampling clock generating circuit produces mxe2x88x921 shift clocks by shifting the phase of the reference clock. The sampling clock generating circuit transmits the shift clocks and reference clock as the m sampling clocks.
In the A/D conversion device of the twenty-fourth embodiment, even if the frequency of an externally applied reference clock ranges, for example, from 1 MHz to 10 MHz or is equal to or higher than 10 MHz, the sampling clock generating circuit produces the m sampling clocks, which are out of phase with one another by a 1/m of the cycle of the reference clock, with high precision.
In the A/D conversion device of the twenty-third embodiment, the cycle of an externally applied input clock may not be a 1/m of the cycle of the sampling clocks that are applied to the respective pieces of pulse position numerizing means. In the A/D conversion device of the twenty-fourth embodiment, the cycle of an externally applied input clock may not be the same as the cycle of the sampling clocks that are applied to the respective pieces of pulse position numerizing means. In this case, a reference clock producing circuit may be included as it is in a twenty-fifth embodiment. Specifically, the reference clock producing circuit produces a reference clock having a desired frequency by multiplying or dividing the frequency of an externally applied input clock by a certain value. The reference clock produced by the reference clock producing circuit is applied to the sampling clock generating circuit.
The following twenty-sixth to thirty-fifth embodiments are related to preferred A/D conversion devices to which the A/D conversion methods of the eleventh to seventeenth embodiments are adapted.
First, in the A/D conversion device of the twenty-sixth embodiment, a plurality of A/D conversion circuits that offer different voltage resolutions (or in other words, different sensitivities for A/D conversion) which are expressed by numerical data items that are results of A/D conversion is used to numerically express an analog input signal. An adding means summates the results of the numerical expression produced by the respective A/D conversion circuits.
According to the A/D conversion device of the twenty-sixth embodiment, a resolution expressed by final numerical data can be improved without the necessity of improving resolutions offered by the A/D conversion circuits.
In order to realize the A/D conversion device of the twenty-sixth embodiment for the purpose of improving the precision in final numerical data, voltage resolutions offered by the A/D conversion circuits are preferably set to resolutions determined by shifting a predetermined reference resolution in units of a unit resolution calculated by dividing the predetermined reference resolution by the number of A/D conversion circuits.
The aspect of the present invention implemented in the twenty-sixth embodiment can be adapted not only to the A/D conversion device using a pulse delay circuit but also so other integrating type A/D conversion devices including a double integral type A/D conversion device or the other types of A/D conversion devices including the successive approximation type and parallel type A/D conversion devices. In order to simplify the configuration of an A/D conversion device so as to reduce a cost, a pulse delay circuit like the one included in an A/D conversion device of a twenty-seventh embodiment is adopted. Specifically, the pulse delay circuit has a plurality of delay units, which delays a pulse signal by a delay time dependent on the voltage level of an analog input signal and which transmits the resultant pulse signal, connected in series with one another. Moreover, a plurality of A/D conversion circuits is realized with m pieces of pulse position numerizing means that numerically express the position of a pulsating signal, which varies within the pulse delay circuit, during respective sampling times that are different from one another by a predetermined unit time.
In this case, similarly to the A/D conversion devices of the eighteenth to twenty-fifth embodiments, the pulse position numerizing means that need not produce a reference voltage for A/D conversion can be used to A/D-convert the analog input signal. Consequently, the A/D conversion device can be realized inexpensively with a simple configuration.
In the A/D conversion device of the twenty-seventh embodiment, an analog input signal is A/D-converted according to the method of the eleventh embodiment. Compared with the A/D conversion devices of the eighteenth to twenty-fifth embodiments, a resolution expressed by final numerical data improves and the precision in A/D conversion improves.
In the A/D conversion device of the twenty-seventh embodiment, a difference (that is, a unit time) between adjoining ones of the sampling times during which the position of a pulse signal changing within the pulse delay circuit is numerically expressed by the pieces of pulse position numerizing means is preferably determined as it is in a twenty-eighth embodiment. Specifically, the difference between adjoining sampling times is set to a time (Td/m) calculated by dividing a delay time (Td) to be given by the delay units constituting the pulse delay circuit by the number (m) of pieces of pulse position numerizing means. Otherwise, the difference between adjoining sampling times is set to a time calculated by adding an integral multiple of the delay time (Td) to be given by the delay units to the time Td/m.
In this case, resolutions expressed by numerical data items produced by the respective pieces of pulse position numerizing means (in other words, voltage levels corresponding to least-significant bits of the respective numerical data items) are different from one another by a 1/m of a resolution determined with the delay time (Td) by which the delay units included in the pulse delay circuit delay the pulsating signal. Consequently, a resolution expressed by final numerical data resulting from summation improves.
Incidentally, in order to realize the A/D conversion device of the twenty-seventh embodiment, the m pieces of pulse position numerizing means must be operated at intervals of different sampling times. For this purpose, a sampling clock generating circuit for generating m sampling clocks that have a certain cycle and that are out of phase with one another by a unit time is included as it is in a twenty-ninth embodiment. Moreover, the m pieces of pulse position numerizing means use the m respective sampling clocks generated by the sampling clock generating circuit to numerically express the position of a pulsating signal that changes within the pulse delay circuit.
In this case, the sampling clock generating circuit includes, like the one included in a thirtieth embodiment, m delay units that give delay times different from one another by a unit time. The m delay units are used to delay a reference clock having a certain cycle, whereby the m sampling clocks are produced.
Furthermore, when the sampling clock generating circuit is used to produce the m sampling clocks, the m delay units included in the sampling clock generating circuit are, as they are in a thirty-first embodiment, realized with inverters that invert the voltage level of an input signal at different inversion levels which are the voltage levels of a varying input signal. The inversion timings at which the inverters invert the input signal along with a change in the voltage level of a reference clock are different from one another. Consequently, the reference clock is delayed by delay times that are different from one another by a unit time.
Especially in the A/D conversion device of the thirty-first embodiment, similarly to the A/D conversion device of the twenty-eighth embodiment, the sampling times during which the respective pieces of pulse position numerizing means numerically express the position of a pulse signal that changes within the pulse delay circuit are differentiated from one another by a 1/m of the delay time (Td) given by the delay units constituting the pulse delay circuit. In this case, an output level transition time Tf, during which the levels of the outputs of the respective inverters realizing the m delay units included in the sampling clock generating circuit make a transition, is, as it is in a thirty-second embodiment, made nearly equal to the delay time Td to be given by one stage of a delay unit included in the pulse delay circuit.
In this case, the inversion levels of the m inverters realizing the m delay units included in the sampling clock generating circuit should merely be regulated. Thus, a difference between inversion timings of adjoining inverters can be readily set to a 1/m of the delay time Td to be given by one stage of a delay unit included in the pulse delay circuit. Consequently, the A/D conversion device of the twenty-eighth embodiment can be relatively easily realized.
The delay time to be given by the delay units constituting the pulse delay circuit changes according to an analog input signal that is an object of A/D conversion. In the A/D conversion device of the thirty-second embodiment, similarly to an A/D conversion device of a thirty-third embodiment, the inverters realizing the m delay units included in the sampling clock generating circuit are operated using an analog input signal as a supply voltage.
In this case, even if the delay time Td to be given by the delay units constituting the pulse delay circuit changes along with an analog input signal, the output level transition time Tf during which the output levels of the inverters realizing the m delay units included in each sampling clock generating circuit make a transition can be changed proportionally to the change in the delay time. Consequently, a resolution expressed by final numerical data resulting from summation can be prevented from changing depending on the variation of the analog input signal.
On the other hand, in the A/D conversion devices of the twenty-ninth to thirty-third embodiments, the m pieces of pulse position numerizing means numerically express the position of a pulsating signal, which varies within the pulse delay circuit, using the m respective sampling clocks produced by the sampling clock generating circuit. Specifically, the position of the pulse signal that varies within the pulse delay circuit is expressed numerically during the time from the rising (or falling) edge of an associated sampling clock to the next rising (or falling) edge thereof. In this case, the sampling times during which the m respective pieces of pulse position numerizing means numerically express the position of the pulse signal are identical to one another. Therefore, during the sampling times from the common start timing serving as a reference to the rising (or falling) edges of the m sampling clocks produced by the sampling clock generating circuit, the respective pieces of pulse position numerizing means must numerically express the position of the pulse signal that varies within the pulse delay circuit (or in other words, the number of delay units the pulse signal passes through).
For the above purpose, a timing generating circuit for generating a signal indicating the common start timing that serves as a reference may be included independently of the sampling clock generating circuit. The timing generating circuit may inform the pieces of pulse position numerizing means of the timing of starting numerical expression. Otherwise, the reference clock which the sampling clock generating circuit uses to generate the m sampling clocks may be used to inform the pieces of pulse position numerizing means of the timing of starting numerical expression. For a simpler configuration, the pieces of pulse position numerizing means may be configured as they are in a thirty-fourth embodiment. Specifically, a sampling clock that leads other sampling clocks by phase among the m sampling clocks generated by the sampling clock generating circuit is regarded as a common clock. The pieces of pulse position numerizing means numerically express the position of a pulse signal, which varies within the pulse delay circuit, during the respective sampling times from the rising or falling edge of the common clock to the rising or falling edges of the sampling clocks associated with the respective pieces of pulse position numerizing means.
Moreover, in order to repeatedly perform A/D conversion, a specific numerizing means that is one of the m pieces of pulse position numerizing means is configured as it is in a thirty-fifth embodiment. Specifically, the specific numerizing means repeatedly numerically expresses the position of a pulse signal within the pulse delay circuit at the rising or falling edge of a sampling clock serving as a common clock. The specific numerizing means then transmits a deviation of new data representing the numerically expressed position of the pulse signal from previous data representing it as the result of the numerical expression to an adding means. The pieces of pulse position numerizing means other than the specific numerizing means are configured so that they will repeatedly numerically express the position of the pulse signal within the pulse delay circuit at the rising or falling edges of the respective sampling clocks associated with the pieces of pulse position numerizing means. The pieces of pulse position numerizing means then transmit a deviation of the data representing the numerically expressed position of the pulsating signal from the previous data produced by the specific numerizing means as the result of the numerical expression to the adding means.
In the A/D conversion device of the eighteenth or twenty-seventh embodiment including the pulse delay circuit, the delay units constituting the pulse delay circuit may be realized with any circuit as long as the circuit (generally, a gate circuit) can delay a pulse signal and transmit it. In order to simplify the delay unit to the greatest extent, the delay unit is, as it is in a thirty-sixth or thirty-seventh embodiment, realized with one stage of an inverter that inverts a pulse signal and transmits it. When the delay unit is realized with one stage of an inverter, a delay time to be given by one stage of a delay unit can be set to a very short time. Consequently, A/D conversion can be achieved at a higher speed.
However, in this case, a delay time that is to be given by an inverter and that corresponds to a period from the rising edge of an input pulse to the falling edge of an output pulse is different from a delay time that is to be given thereby and that corresponds to a period from the falling edge of the input pulse to the rising edge of the output pulse. Results of A/D conversion may be slightly different from one another. In order to prevent the differences, each delay unit may be, as it is in a thirty-eighth or thirty-ninth embodiment, composed of two stages of inverters connected directly to each other.
The A/D conversion device of the eighteenth or twenty-seventh embodiment including the pulse delay circuit has the plurality of pieces of pulse position numerizing means that numerically expresses the position of a pulsating signal within the pulse delay circuit. By the way, input paths (or lengths thereof) along which the pulse signal is transmitted from the pulse delay circuit to the pieces of pulse position numerizing means may be different from one another. In this case, numerical data items expressing the position of the pulse signal within the pulse delay circuit and being produced the respective pieces of pulse position numerizing means become uncertain. Numerical data representing a result of A/D conversion and being calculated based on the numerical data items may contain an error.
In order to realize the A/D conversion device of the eighteenth or twenty-seventh embodiment, a plurality of delay units constituting a pulse delay circuit is disposed along a straight line as it is in a fortieth or forty-first embodiment. Moreover, m pieces of pulse position numerizing means are divided into two groups. The pieces of pulse position numerizing means belonging to each group are arranged symmetrically to a straight line extending in a direction of disposition in which the delay units constituting the pulse delay circuit are disposed.
In this case, the lengths of the input paths along which a pulse signal is transmitted from the pulse delay circuit to the pieces of pulse position numerizing means are made uniform. Therefore, the timings of transmitting the pulse signal to the pieces of pulse position numerizing means can be identical with one another. Consequently, an error in an A/D result can be prevented from occurring due to the uncertainty in numerical data items that express the position of the pulse signal within the pulse delay circuit and that are produced by the pieces of pulse position numerizing means.
The A/D conversion device of the eighteenth or twenty-seventh embodiment changes a delay time, which is given by the delay units constituting the pulse delay circuit, according to an analog input signal. The changed delay time is numerically expressed based on the position of the pulse signal within the pulse delay circuit. The delay time to be given by the delay units changes with temperature or any other use environment. A result of A/D conversion (numerical data) produced by the A/D conversion device of the eighteenth or twenty-seventh embodiment may therefore vary with a change in the use environment.
In order to overcome the above problem, an input signal selecting means is included as it is in a forty-second or forty-third embodiment. Specifically, the input signal selecting means selects a signal, with which the delay time to be given by the delay units is changed, from an analog input signal and a reference signal whose voltage level is known, and applies the selected signal to the pulse delay circuit. When the contacts of the input signal selecting means are switched in order to apply the analog input signal to the pulse delay circuit, an uncorrected data holding means holds as uncorrected data numerical data produced by the adding means (in other words, a result of A/D conversion performed on the analog input signal). When the contacts of the input signal selecting means are switched in order to apply the reference signal to the pulse delay circuit, a reference data holding means holds as reference data the numerical data produced by the adding means (in other words, a result of A/D conversion performed on the reference signal). A dividing means divides the uncorrected data held in the uncorrected data holding means by the reference data held in the reference data holding means. Thus, corrected numerical data representing the analog input signal may be produced.
The embodiments of the present invention will be described in conjunction with the drawings described below.

Analog-to-digital conversion method and device


Each of busbars of a busbar unit includes a main body part that extends along a circumferential direction of the stator so that a plate thickness direction coincides with an axial direction of a stator; a projecting part that projects radially outwardly of the stator from outer periphery of the main body part; an extending part bent from the projecting parts, the extending part extending in the axial and radial direction of the stator; and a connecting part provided on a tip of the extending part, the connecting part being connectable to the winding wire ends of the coils. A position of the connecting part is specified in accordance with length of the extending part in the axial and radial directions of the stator.

It is known to use a busbar unit to supply a current to a winding wire of each coil from an external terminal part in a stator of a motor or the like.
JP6-233483A discloses a busbar unit including busbars that corresponds to a U-phase, a V-phase and a W-phase, and an insulating resin for holding these busbars in a state spaced apart in an axial direction of a stator.
The busbar includes an arcuate main body part that extends along a circumferential direction of the stator, and a connecting part that extends radially outwardly of the stator from the main body part and to be connected to a winding wire end of a coil.


Microwave radiation of frequency 0.1 to 20 GHz, is applied to the melt of viscosity in the range 104 to 101 Pa·s. The outside surface of heated space, where an outlet of the waveguide of microwave radiation is located, can be cooled. The microwave radiation in the melt may be reflected by the reflective metallic elements in the melt back to the place of radiation entry into the melt and shielded from the surroundings by a shielding metallic element. An outlet is provided of at least one waveguide from the source of the microwave radiation, in any direction to the outside surface of the melt, into the space with the melt of a given viscosity. At least one waveguide is led, for example, to the outside surface of the bottom of the channel of the forehearth.

a. Field of Invention
The invention is related to a method of homogenizing of melt, dielectric type, e.g. glass, by removing or minimizing local concentration differences, i.e. inhomogeneities in the melt, and an apparatus for performing of this method.
b. Description of Related Art
Traditional methods—insertion of gas-generating elements into the molten glass, when the gas bubbles are rising to the surface and thus mixing the content of the bath, are still being used for achieving homogenous melt, for example of glass.
Modern method of homogenizing is mechanical stirring by rotating stirrers. With regard to strictly laminar flow it causes only elongation of cords. The main disadvantage of mechanical rotation stirring is, that the stirrer action does not reach to the bottom, where the cords are located. It is not possible to lower the stirrer to the level of cords, i.e. 1 mm above the bottom.
Inhomogeneities of the melt, mainly in molten glass, are present mainly as cords, i.e. parts of melt in the shape of thin layers or cords of thickness 0.001-1 mm, that is in dimensions, which cause diffusion of visible light. Glassmelt with cords has different chemical composition and thus also different physical properties:                refractive index, then the cords are visible in the glass and visually disturbing, increasing diffusion of light and thus reduce spectral transmissivity, reduce brilliancy of the glass;        thermal expansion, which reduces strength of the product,        viscosity and surface tension, which have an influence on cord reduction through these properties having an adverse effect in the forming process;        and cords usually also have higher specific density. i.e. they are concentrated on the bottom and there, they create a thick cords, which are especially dangerous in final products.
Description of microwave heating, in such manner that an inert additive chosen from the group of carbides, borides or nitrides is added to glass material mixture in the quantity 5 to 50 g to 1 kg of glass material, which is melted using microwave radiation of frequency 2450 MHz, is provided in Czech patents No. 289191 and No. 289193. The device consists of a microwave furnace with at least one generator. It is a modern method of glass material melting from cold conditions, i.e. of glass bath using microwave energy heating.
An additive agent—additive needs to be used for melting the glass.
The purpose of the present invention is homogenization of already melted glass, with a melt viscosity higher than that in the melting area, without the additive.

Method and apparatus for homogenisation of melt


The invention relates to a tool for a breaking hammer, a breaking hammer, and the use of a breaking hammer. The breaking hammer includes a percussion device, the percussion piston of which providing impacts to the tool for breaking rock. An impact surface of the tool has a curved form surface that has a radius of curvature and a center axis on the longitudinal axis of the tool. The direction of the centre axis is transverse to the plane through the longitudinal axis of the boom of a work machine.

The invention relates to a tool used in a breaking hammer. The tool has an impact surface, on which impact pulses can be provided with a percussion device of the breaking hammer. At the opposite end of the tool, there is a tip that under the influence of the impacts penetrates rock and breaks it. Further, the tool has fastening surfaces for fastening to the breaking hammer.
The invention further relates to a breaking hammer and its use. The field of the invention is described in more detail in the preambles of the independent claims of the patent application.
A breaking hammer is typically used as an attachment device in an excavator or another work machine when the intention is to break rock, concrete or some other relatively hard material, for instance. The breaking hammer has a percussion device, with which impacts can be provided to a tool that is fastened to the breaking hammer and transmits the impact pulses to the material to be broken. The percussion device has a percussion piston that makes a reciprocating motion and hits an impact surface at the top end of the tool. At the same time as impacts are provided with the percussion piston, the tool is pressed against the material to be broken, and the tool penetrates into the material to be broken under the influence of the impact and pressing and breaks it. Generally, the breaking hammer is used in the upright position, when breaking boulders and ground crust. The tool of the breaking hammer is supported by bearing bushings to the body of the breaking hammer. Bearing bushings wear in use, as a result of which an angle error forms between the percussion piston and tool over time. As a result of this angle error, the impact surfaces of the percussion piston and tool may damage during percussion operation.

Tool for breaking hammer, breaking hammer, and use thereof


Examples of devices and method for quantifying opacities in an eye are shown. Examples include analysis of still images or video images. In one example a cross section area of opacities within a visual axis are quantified. Opacities in the vitreous of an eye, such as “floaters” can vary in severity from little or no reduction in vision, to bothersome, to high reduction in visual function. It is desirable to be able to quantify a level of severity of visual obstruction within a patient's eye and proceed with a level of treatment to match the condition.

Opacities in the vitreous of an eye, such as "floaters" can vary in severity from little or no reduction in vision, to bothersome, to high reduction in visual function. It is desirable to be able to quantify a level of severity of visual obstruction within a patient's eye and proceed with a level of treatment to match the condition.

Device and method to quantify vitreous opacity impairment


Method and apparatus for recovering leaked fluid or directing fluid flow or propagation through utilization of negative pressure pulses occurring in a pressurized fluid system. The invention has particular application in double acting hydraulic fluid motors where leakage of hydraulic fluid past the output shaft seal may be efficiently collected and redirected into the pressurized hydraulic fluid system through utilization of negative pressure pulses that are developed periodically by fluid direction changes during operation of the hydraulic fluid motor.

Many different types of mechanical devices are provided having pressurized fluid systems for operation thereof. The present invention, though being described particularly as it relates to double acting hydraulic motors such as is commonly used in paint pumps and the like, has a wide variety of applications in various and sundry fluid energized mechanisms wherein the methods of the present invention are applicable. The term "fluid" as utilized herein is intended to encompass a wide variety of liquid compositions including water, oil such as hydraulic oil and various other compositions including a liquid as a material constituent thereof. The term "liquid" as utilized herein is intended to mean any material or composition of materials capable of flowing, without regard to the particular viscosity thereof.
The use of hydraulic cylinders for a variety of mechanical applications is well known. In general, great care is taken in the design of the seals around the moving piston to prevent leakage of hydraulic oil out of the system. In spite of the best seal technology available, leakage is inevitable as the seals and piston wear during normal use of the apparatus. In most cases the initial leakage is small and is generally accepted. The hydraulic reservoir of the apparatus is refilled occasionally to replace the lost fluid.
In some applications any degree of leakage can have serious effect. One such application is a hydraulically operated paint pump which can be used to deliver paint to spray guns in industrial plants. Leakage of oil in this environment, even though slight, over extended periods of time can result in contamination of the paint supply. In some instances paint is stored in large containers and oil contamination can be very expensive because of the expensive paint that must be discarded as unusable. This invention pertains to a method for automatically and inexpensively collecting oil which leaks from the cylinder and directing the leaked oil back into the hydraulic system, thus preventing it from causing contamination to materials or apparatus externally of the fluid energized motor or device.
Many different types of mechanical devices, such as the hydraulic motors for paint pumps, incorporate a housing structure having internal movable components and form or otherwise incorporate a pressurized fluid system for operation thereof. In most cases, the mechanical device, to provide a work output, will have an output shaft that rotates, reciprocates or includes a combination of rotation and reciprocation in its movement. The housing structure of the apparatus in such cases defines a passage through which the output shaft extends and a seal, such as a resilient O-ring or any other commercially available sealing device is utilized to establish a seal between the output shaft and the housing. Obviously these sealing devices are always designed to prevent leakage of liquid materials such as lubricating oils, hydraulic oil, etc. from the mechanical device. Through normal wear, unusual seal erosion or other character of seal deterioration leakage will develop in time. In some cases, a small amount of leakage is tolerated until the apparatus can be shut down for repair. In many cases, especially in the cases of fluid motors for paint pumps, even a small amount of leakage can cause contamination of a large volume of paint, thereby requiring that the paint be discarded. In mechanical devices where even minimal seal leakage is undesirable the present invention has application. It is therefore desirable to provide an anti-leakage system for mechanical apparatus having a fluid energized system for operation thereof or a fluid system providing other necessary features such as lubrication, cooling, etc.


Alkylation processes are described. The processes utilize ionic liquid catalysts having a kinematic viscosity range of about 50 cSt to about 100 cSt at 25° C. Catalysts within this range produce alkylate having higher octane than catalysts outside this range, especially at higher process temperatures which are preferable from an operating cost standpoint. The alkylate can have one or more of a research octane number of at least about 93, a selectivity of C8 of at least about 65%, and a mole ratio of trimethylpentane to dimethylhexane of greater than about 7:1.

The alkylation of paraffins with olefins for the production of alkylate for gasolines can use a variety of catalysts. The range of suitable process conditions that result in products with high octane and desired selectivity depends on the choice of catalyst.
Ionic liquids are catalysts that can be used in a variety of catalytic reactions, including the alkylation of paraffins with olefins. Ionic liquids are primarily mixtures of salts which melt below about 100° C.
Ionic liquids comprise an organic cation and an anion where the anion is usually an inorganic anion. Ionic liquids are described in U.S. Pat. No. 4,764,440, U.S. Pat. No. 5,104,840, and U.S. Pat. No. 5,824,832 for example. The properties vary extensively for different ionic liquids depending on the cation and the anion. The use of ionic liquids depends on the properties of a given ionic liquid. In addition, the behavior of an ionic liquid may vary considerably for different temperature ranges.
Some alkylation processes utilize low temperatures, typically 10° C. or less, which generally requires chilled cooling fluid for the reactor and/or reactor feeds. This adds substantial cost in the form of additional equipment and energy usage. In some alkylation processes, isoparaffin to olefin (I/O) ratios of 20:1 or greater are used. However, high I/O ratios like these are not desirable from an operating standpoint because they increase the cost of operation, for instance, by requiring larger reactors and more energy for distillation of isoparaffin per unit of alkylate product. Some alkylation processes use ionic liquids having low viscosity (e.g., less than 25 cSt at 25° C.), such as 1-butylpyridinium heptachloroaluminate, 1-butyl-3-methylimidazolium heptachloroaluminate, and triethyl ammonium based ionic liquids. The kinematic viscosity of these ionic liquids was measured in a comparative example herein and determined to be 21.5, 15.0 and 16-19 cSt at 23-25° C. respectively. Viscosity measurements of other halometallate ionic liquids are available in literature, for instance in Okoturo, O. O; VanderNoot, T. J; Journal of Electroanalytical Chemistry, "Temperature dependence of viscosity for room temperature ionic liquids", 2004, vol. 568, pp. 167-181.
U.S. Pat. No. 7,432,408, U.S. Pat. No. 7,432,409, U.S. Pat. No. 7,531,707, and US 2007/0225538 broadly disclose alkylation processes using chloroaluminate ammonium, pyridinium and imidazolium ionic liquids with I/O ratios in the range of 1 to 100, catalyst volume in the reactor in the range of 2% to 70%, reaction temperatures in the range of −40° C. to 150° C., and residence times of a few seconds to a few hours. However, the Examples use low viscosity (e.g., less than 25 cSt at 25° C.) ionic liquids including 1-butylpyridinium heptachloroaluminate, and 1-butyl-3-methylimidazolium heptachloroaluminate. The viscosity of several of the ionic liquids used is unknown, including 1-butyl-4-methylpyridinium heptachloroaluminate, 1-H-pyridinium chloroaluminate, and tributyl-methyl-ammonium chloroaluminate. Based on related ionic liquids, the viscosity of 1-butyl-4-methylpyridinium heptachloroaluminate is believed to be below 40 cSt. In addition, the Examples show an I/O ratio of 4, and a temperature of 50° C. for the isopentane and ethylene alkylation. For the isopentane/propylene alkylation and isobutane/isobutene alkylation, an I/O ratio of 8, and a temperature of 10° C. were used. There are no examples for alkylation using propylene or butene at temperatures greater than 10° C., and no discussion of the problems associated with operating at those temperatures.
US 2004/0133056 describes an alkylation process utilizing alkyl-containing ammonium or pyridinium ionic liquid combined with metal compounds of Groups IB and IIB and transition metals. The broad reaction conditions include an I/O ratio of 1:1 or greater, a reaction temperature in the range of −20° C. to 100° C., and a reaction time of 2 sec to 60 min. The ionic liquids used in the Examples were low viscosity (e.g., less than 25 cSt at 25° C.) ionic liquids including triethylammonium chloroaluminates combined with copper chloride, nickel chloride, copper nitrate, and copper sulfate. Most Examples were run at low temperature (less than 10° C.: Ex. 6, 7, 11, 13, 14, 16, and 18) or high I/O ratios (30:1 or more: 10, 12, 13, 14, 16, 17, and 18). The only Examples having I/O ratios of 20:1 or less were run at low temperature (less than 10° C.: Ex. 6, 7, and 11), the reaction products had low C8 content (Ex. 6-9), and/or had low TMP/DMH ratios (Ex. 6-9, 11, and 15).
US2007/0142676 describes an alkylation process for isopentane and ethylene using pyridinium-based ionic liquids. The broad conditions include a reaction temperature in the range of −20° C. to 200° C., and a reaction time of 0.1 min to 24 hr. The I/O ratio in the example was 3.2, and the ionic liquid was 1-butylpyridinium heptachloroaluminate.
US 2009/166257 describes an alkylation process utilizing chloroaluminate ammonium, pyridinium, and imidazolium ionic liquids. The broad conditions include an I/O ratio in the range of 1 to 100, a catalyst volume in the reactor of 2% to 70%, a reaction temperature in the range of −40° C. to 150° C., and a residence time of a few seconds to a few hours. The Examples showed a 1-butylpyridinium chloroaluminate ionic liquid, a catalyst volume of 10-15%, and a temperature of 0° C.
US 2012/0178982 describes the alkylation of isobutane and/or isopentane with an olefin having 2 to 8 carbons using an alkyl-containing ammonium, imidazolium, or pyridinium ionic liquid. The I/O ratio is 1:1 or greater, with high I/O ratios being preferred, e.g., at least 20:1, more preferably at least 50:1, even more preferably at least 100:1. The reaction temperature is in the range of −20° C. to 100° C. No examples are given.
US2012/0283500 describes the alkylation of isobutane and butene using alkyl-containing ammonium, imidazolium, or pyridinium ionic liquids. The examples used ionic liquids containing triethylammonium (Et3NH) and 1-butyl-3-methylimidazolium cations, and anions containing chlorohexabromoaluminate or heptachloroaluminate, with some including various copper compounds. The Examples show I/O ratios of 10:1 to 40:1, and temperatures of 20° C. to 30° C. The olefin feed rate for Examples 3-8 and Comparative Examples 1-2 was calculated from the information given to be less than 0.2 g olefin/g ionic liquid/hr (1.4 mol olefin/mol ionic liquid/hr). The olefin feed rate cannot be calculated for Examples 1a-b and 2a-b because no feed rate or olefin feed rate is given for those examples. However, assuming these feed rates were the same as that in Example 4, the olefin feed rate would be less than 0.2 g olefin/g ionic liquid/hr (1.4 mol olefin/mol ionic liquid/hr). In addition, no volume fraction of ionic liquid or residence times are given.
US Application Serial Nos. 2013/0345484 and 2014/0113804 teach that certain phosphonium ionic liquids having a kinematic viscosity greater than 50 cSt at 20° C. are preferable because they result in higher octane than do lower viscosity ionic liquids, and that this advantage is larger at higher operating temperatures. However, the olefin was added with a slow flow rate (0.5 g olefin/g ionic liquid/hr or 5.2 mol olefin/mol ionic liquid/hr), leading to long residence times (e.g., about 115-120 min) Such long residence times are not desirable for commercial practice as they would require very large reactors or very small product production rates.
Therefore, an alkylation process utilizing ionic liquids that does not require operation under more extreme conditions such as refrigeration or long residence times would be desirable.

Process for alkylation using ionic liquid catalysts


An image recording apparatus employs a transfer type recording medium which includes a photosensitive pressure-sensitive recording sheet and a developer sheet. The former sheet is exposed to light to form a latent image corresponding to an image of an original. This sheet is exposed to light while being transported at a speed equal to or in the case of making a copy of enlarged or reduced size, at a speed different from a speed at which the original is scanned by light. The photosensitive pressure-sensitive recording sheet on which the latent image is formed is brought into facial contact with the developer sheet and the latent image is developed under pressure to provide a visible image on the developer sheet. This developing operation is performed while moving the superposed two sheets at the same speed as the speed when the latent image is formed on the photosensitive pressure-sensitive recording sheet. Since both the exposure and developing operations can be performed substantially simultaneously, the copying speed is increased. Further, no receiving unit needs to be provided in a position between the exposure unit and the developing unit, which may otherwise be needed for receiving the exposed recording sheet if development is performed upon completion of the exposure. Thus, the overall apparatus can be made compact in size.

The present invention relates to an image recording apparatus such as a copying machine or a printer, and more paticularly to such an image recording apparatus using a photosensitive pressure-sensitive recording medium.
In a conventional image recording apparatus, light emitted from a light source is irradiated onto an original and a photosensitive pressure-sensitive recording medium is exposed to light which has passed through or reflected from the original to form a latent image on the recording medium. At the time of light exposure, the recording medium is conveyed at a speed equal to or at a speed different from the moving speed of an original support stand glass on which the original is placed. Upon completion of the exposure, the recording medium is fed between a pair of pressure rollers serving as a developing unit where pressure is applied to the recording medium to develop the latent image and provide a visible image.
In the conventional apparatus, the pressure development is carried out after exposure of the entire surface of the original is completely terminated. Therefore, it has been necessary to provide a receiving unit for receiving the exposed medium in a position between the exposure unit and the developer unit. The provision of this receiving unit causes to enlarge the overall size of the apparatus. Besides, a period of time for completion of copying is prolonged, since the development is not taken place simultaneous with the exposure.

Image recording apparatus using photosensitive pressure-sensitive recording medium