A bistable MEMS microswitch produced on a substrate and capable of electrically connecting ends of at least two conductive tracks, including a beam suspended above the surface of the substrate. The beam is embedded at its two ends and is subjected to compressive stress when it is in the non-deformed position. The beam has an electrical contact configured to produce a lateral connection with the ends of the two conductive tracks when the beam is deformed in a horizontal direction with respect to the surface of the substrate. Actuators enable the beam to be placed in a first deformed position, corresponding to a first stable state, or in a second deformed position, corresponding to a second stable state, and the electrical contact ensures connection of the ends of the two conductive tracks.

In the field of communications, conventional microswitches (i.e. those used in microelectronics) are very widely used. They are useful in signal routing, impedance-matching networks, amplifier gain adjustment, and so on. The frequency bands of the signals to be switched can range from several MHz to several dozen GHz.
Conventionally, microelectronic switches have been used for these RF circuits, which switches enable circuit electronics integration and have a lower production cost. In terms of performance, however, these components are rather limited. Thus, silicon FET switches can switch high-power signals at low frequencies, but not at high frequencies. MESFET (Metal Semiconductor Field Effect Transistor) switches made of GaAs or PIN diodes work well at high frequencies, but only for low-level signals. Finally, in general, above 1 GHz, all of these microelectronic switches have a significant insertion loss (conventionally around 1 to 2 dB) when on and rather low insulation in the open state (from −20 to −25 dB). The replacement of these conventional components with MEMS (Micro-Electro-Mechanical-System) microswitches is therefore promising for this type of application.
Owing to their design and operation principle, MEMS switches have the following characteristics:                low insertion losses (typically lower than 0.3 dB),        high insulation in the MHz to millimetric range (typically over −30 dB),        no response nonlinearity (IP3).
Two types of contact for MEMS microswitches are distinguished: ohmic contact and capacitive contact. In the ohmic contact switch, the two RF tracks are contacted by a short circuit (metal-metal contact). This type of contact is suitable both for continuous signals and for high-frequency signals (greater than 10 GHz). In the capacitive contact switch, an air space is electromechanically adjusted so as to obtain a capacitance variation between the closed state and the open state. This type of contact is particularly suitable for high frequencies (greater than 10 GHz) but inadequate for low frequencies.
Several major actuation principles for MEMS switches are distinguished.
Thermal actuation microswitches, which can be described as standard, are non-bistable. They have the advantage of a low actuation voltage. They have several disadvantages: excessive consumption (in particular in the case of mobile telephone applications), low switching speed (due to thermal inertia) and the need for a supply voltage to maintain contact in the closed position.
Electrostatic actuation microswitches, which can be described as standard, are non-bistable. They have the advantages of a high switching speed and a generally simple technology. They have problems of reliability, in particular in the case of low actuation voltage electrostatic switches (structural bonding). They also require a supply voltage in order to maintain contact in the closed position.
Electromagnetic actuation microswitches, which can be described as standard, are non-bistable. They generally operate on the principle of the electromagnet and essentially use iron-based magnetic circuits and a field coil. They have several disadvantages. Their technology is complex (coil, magnetic material, permanent magnet in some cases, etc.). Their consumption is high. They also require a supply voltage in order to maintain contact in the closed position.
Two configurations for moving the contact are differentiated: a vertical movement and a horizontal movement.
In the case of a vertical movement, the movement occurs outside the plane of the RF tracks. The contact occurs over the top or over the bottom of the tracks. The advantage of this configuration is that the metallization of the contact pad is easy to perform (flat deposit) and, therefore, the contact resistance is low. However, this configuration is poorly adapted for performing the function of dual contact switch. The contact over the top is indeed difficult to obtain. It is generally achieved by using a contact on the cap. This configuration also has poor integration compatibility. Indeed, for resistive switches, tracks and contacts with gold metallization are conventionally used (good electric properties, no oxidation). However, this metal is not integration compatible, even though it has been used since nearly the beginning of the technology for this type of configuration. There is no possible optimisation of the contact. Its surface can only be planar. The stiffness of the beam forming the contact is poorly controlled. This stiffness is conditioned by the final form of the beam which is dependent on the topology of a sacrificial layer which is itself dependent on the form and thickness of the tracks located below. The beam profile is generally irregular, which substantially increases the stiffness of the switch and therefore its actuation conditions.
In the case of horizontal movement, the movement takes place in the plane of the tracks. The contact takes place on the side of the tracks. This configuration is suitable for dual contact, with a symmetrical actuator. The "gold" metallization can be performed in the very last technological step. All of the preceding steps can be compatible with the production of integrated circuits. The form of the contact is determined in the photolithography step. For example, it is possible to have a round contact so that the contact occurs at one point and so as to thus limit the contact resistance. The form of the beam is determined in the photolithography step. Its stiffness is therefore well controlled. However, the metallization on the side is delicate. The contact resistance can therefore be poorly controlled. This configuration is unsuitable for electrostatic actuation due to the significantly-reduced opposing actuation surfaces.
The number of equilibrium states is another characteristic of the movement of the switches. In the standard case, the actuator has only one equilibrium state. This means that one of the two states of the switch (switched or unswitched) requires a continuous voltage supply in order to hold it in position. The interruption of the excitation causes the switch to move back to its equilibrium position.
In the bistable case, the actuator has two distinct equilibrium states. The advantage of this mode of operation is that the two "closed" and "open" positions of the switch are stable and do not require a power supply when there is no switching from one state to the other.

Low power consumption bistable microswitch


Systems, methods and apparatus are provided through which, in some embodiments, an extending column is comprised of a plurality of stacked slides that are mounted to each other through linear bearing assemblies that allow the extending column to telescope inward and outward. Some embodiments of the extending column have a synchronization mechanism between each slide to extend each slide in equal distances relative to each other.

In conventional medical diagnostic X-ray radiography, an X-ray source and a collimator are suspended from a ceiling by an extending column. The extending column is often referred to as an overhead tube suspension system. The X-ray source sends a beam of X-rays from the X-ray source behind the patient, through the patient's chest, to the recording medium (e.g. film or digital recording means). A collimator is a diaphragm or system of diaphragms made of an absorbing material, designed to define and restrict the dimensions and direction of a beam of radiation from the X-ray source.
The extending column is mounted to carriages to provide freedom of motion that allows general positioning of the X-ray source at the desired location and orientation within an X-ray examination room. In conventional extending columns, the extending column consists of a series of concentric cylinders, either circular or prismatic (e.g. octagonal), with ball bearing assemblies running in channels or on tracks in at least two planes to provide smooth motion with as little free play as possible. In one embodiment, the ball bearing assemblies are on opposing sides of the concentric cylinder. The amount of free play in the extending column is minimized by closely controlling tolerances, and also by providing adjustment means to reduce the clearance for the bearings as much as possible. Conventional extending columns are approximately symmetrical, with guiding and synchronizing means being distributed approximately equally in 2, 3, or 4 sides of the columns.
One problem with conventional extending columns is that the precision of motion is poor, since it is very difficult to manufacture the telescoping sections precisely enough to maintain the parallelism and straightness required among the various column sections thus employed.
Another problem is that that adjustment of the bearings is difficult, and this leads to inconsistencies in moving efforts and stiffness, as well as lost motion in the assemblies.
Yet another problem is that synchronized motion of the column sections is achieved through the use of "J-bars" and the like, which are long bars extending from one section into the next. These J-bars often rub against the sections, which increases friction in movement, which in turn increases wear of the extending column and requires a greater manual force by an operator of the X-ray equipment to position the X-ray source and the collimator mounted on the extending column.
Still yet another problem is that the length of travel permissible for a given column length is limited, because the bearings are not stiff enough if spaced close together. As a result, clinical usage is somewhat restricted, and extensions are sometimes employed to achieve the desired anatomical coverage range.
A further problem is the size of the conventional extending columns. The area close to an X-ray examination table has rather close quarters for the operators of the X-ray equipment. Reducing the size of the extending column would provide more room for the operators.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an extending column for medical diagnostic that has improved precision of motion. There is also a need for reducing inconsistencies in moving efforts and stiffness, as well as reducing lost motion in the assemblies. There is an additional need to reduce the rubbing of J-bars against sections. There is a further need increase rigidity in order to improve clinical usage without the need for extensions to achieve the desired anatomical coverage range. There is also a need to reduce the size of the extending column.

Systems, methods and apparatus of an extending column


A system having a UHF RFID transceiver is adapted to communicate exclusively with a single electro-magnetically coupled transponder located in a predetermined confined transponder operating region. The system includes a near field coupling device comprising a plurality of lines connected in parallel with an unmatched load. The near field coupling device may be formed, for example on a printed circuit board with a plurality of electrically interconnected traces and a ground plane. The system establishes, at predetermined transceiver power levels, a mutual electro-magnetic coupling which is selective exclusively for a single transponder located in a defined transponder operating region. Also included are methods for selective communication with the transponder in an apparatus such as a printer-encoder.

1. Field of the Invention
The invention relates to RFID systems, operable with a variety of different dimensioned electro-magnetically coupled transponders, working at close proximity, to an RF transceiver antenna that is spatially selective for an individual transponder located in a predetermined transponder operating region to the exclusion of other adjacent transponders, and its application to printers-encoders or other systems utilizing such in UHF RFID systems.
2. Description of Related Art
UHF radio frequency identification (RFID) technology allows wireless data acquisition and or transmission from and or to active (battery powered) or passive transponders using a backscatter technique. To communicate with, i.e., "read" from and or "write" commands and/or data to a transponder, the transponder is exposed to an RF electro-magnetic field by the transceiver that couples with and energizes (if passive) the transponder through electro-magnetic induction and transfers commands and data using a predefined "air interface" RF signaling protocol.
When multiple passive transponders are within the range of the same RF transceiver electro-magnetic field they will each be energized and attempt to communicate with the transceiver, potentially causing errors in "reading" and or "writing" to a specific transponder in the reader field. Anti-collision management techniques exist to allow near simultaneous reading and writing to numerous closely grouped transponders in a common RF electro-magnetic field. However, anti-collision management increases system complexity, cost and delay response. Furthermore, anti-collision management is "blind" in that it cannot recognize where a specific transponder being processed is physically located in the RF electro-magnetic field, for example, which transponder is located proximate the print head of a printer-encoder.
One way to prevent errors during reading and writing to transponders without using anti-collision management is to electrically isolate a specific transponder of interest from nearby transponders. Previously, isolation of transponders has used RF-shielded housings and/or anechoic chambers through which the transponders are individually passed for personalized exposure to the interrogating RF field. This requires that the individual transponders have cumbersome shielding or a significant spatial separation.
RFID printers-encoders have been developed which are capable of on-demand printing on labels, tickets, tags, cards or other media with which a transponder is attached or embedded. These printer-encoders have a transceiver for on-demand communicating with the transponder on the individual media to read and/or store data into the attached transponder. For the reasons given, it is highly desirable in many applications to present the media on rolls or other format in which the transponders are closely spaced. However, close spacing of the transponders exacerbates the task of serially communicating with each individual transponder without concurrently communicating with neighboring transponders on the media. This selective communication exclusively with an individual transponder is further exacerbated in printers-encoders designed to print on the media in or near the same space as the transponder is positioned when being interrogated.
When transponders are supplied attached to a carrier substrate, for example in RFID-attached labels, tickets, tags or other media supplied in bulk rolls, Z-folded stacks or other format, an extra length of the carrier substrate is required to allow one transponder on the carrier substrate to exit the isolated field area before the next transponder in line enters it. The extra carrier substrate increases materials costs and the required volume of the transponder media bulk supply for a given number of transponders. Having increased spacing between transponders may also slow overall printer-encoder throughput.
When transponders of different sizes and form factors are processed, the RF shielding and or anechoic chamber configuration will also require reconfiguration, adding cost, complexity and reducing overall productivity. In certain printer-encoders it is desired to print on transponder-mounting media in the same transponder operating region in which the transponder is being read from or written to. This may be very difficult to accomplish if the transponder also must be isolated in a shielded housing or chamber.
UHF transponders may operate in, for example, the 902-928 MHz band in the United States and other ISM bands designated in different parts of the world. For example, in FIG. 1 a conventional one-half wavelength "Forward Wave" microstrip prior art coupler 3 consisting of a, for example, rectangular conductive strip 5 upon a printed circuit board 7 having a separate ground plane 9 layer configured for these frequencies. One end of the conductive strip 5 is connected to transceiver 42 and the other end is connected through terminating resistor 8 to ground plane 9. The conductive strip 5 as shown in FIG. 1 has a significant width due to RF design requirements imposed by the need to create acceptable frequency response characteristics. This type of prior art coupler 3 has been used with UHF transponders that are relatively large compared to the extent of prior art coupler 3.
As shown by FIGS. 2a and 2b, recently developed transponders 1, designed for operation at UHF frequencies, have one dimension so significantly reduced, here for example a few millimeters wide, that they will be activated upon passage proximate the larger prior art coupler 3 by electro-magnetic power leakage 10 concentrated at either side edge of the conductive strip 5 of prior art coupler 3. In FIG. 2A, the two leakage regions "A" and "B" defined by electro-magnetic power leakage 10 are small and relatively far apart, increasing system logical overhead and media conveyance positioning accuracy requirements. If the transponders 1 were placed close together, then multiple transponders 1 might be activated by the physically extensive one-half wavelength "Forward Wave" microstrip prior art coupler 3.
Thus the minimum required spacing of these transponders 1 to isolate them, and thus the minimum size of media 11 (assuming that they are embedded one per label or media 11 on carrier substrate 13) must be large relative to the size of the microstrip coupler 3. This creates issues for media suppliers by limiting the available space on the media 11 for transponder 1 placement and significantly increasing the necessary accuracy of the transponder 1 placement within and or under the printable media 11 and along the liner or carrier substrate 13. This also reduces the cost advantages of using the narrow dimensioned transponder(s) 1 within media 11, as the media 11 must be much larger than the transponder 1 to achieve adequate RF isolation.
Competition in the market for such "integrated" printer-encoder systems as well as other RFID interrogation systems has focused attention on the ability to interrogate with high spatial selectivity any transponder from a wide range of available transponders having different sizes, shapes and coupling characteristics as well as minimization of overall system, media size, and transponder costs.
Therefore, it is an object of the invention to provide a device, systems, and methods that overcome deficiencies in such prior art.

Spatially selective UHF near field microstrip coupler device and RFID systems using device


A video distribution system minimizes bandwidth use between a headend and a remote video distribution center through an origin segmentation server and an edge segmentation server. The origin segmentation server is located at the headend and creates segments and playlists for every video stream originating at the headend. An edge segmentation server is located at the remote video distribution center and receives a request for a playlist of a content stream from CPE. The edge segmentation server joins a multicast group with the content stream and requests the playlist from the origin segmentation server. The edge segmentation server constructs a second playlist with a predetermined final number of segments from the playlist to return to the CPE, generates segments from the content stream received from the headend, identifies and obtains missing segments from the origin segmentation server, and updates the second playlist with the missing segments and segments generated by the edge segmentation server.

Segmenting video into small chunks and then sending the small chunks over the internet has become a popular way to deliver video. Examples of segmented video streaming standards include the HTTP Live Streaming standard (HLS), MPEG-DASH, and Smooth Streaming. A segmentation server receives a video stream as input, and then creates segments or chunks. The segmentation server creates the segments, and stores them on a disk, in computer RAM or in some other method of storage as needed. As the segments are created, a playlist file is maintained that lists the available chunks, and addresses where the chunks can be accessed by a requestor. One key advantage that segmented video delivery has over linear video delivery (e.g. delivery via unicast, multicast or http chunked transfer encoding) is that the playlists, and video chunks can be delivered using ubiquitous http servers and caching technology.
In a cable TV headend, typically there are a large number of satellite receivers, terrestrial broadcast receivers and fiber broadcast receivers. Each of the various types of receivers receive video content which is then passed through a number of video encoders or transcoders to transform the input signals into a format required by the design of the cable TV system. For example, if a cable TV system is using a digital transmission method to their customers, and the customers have customer premise equipment (CPEs) that support playback of MPEG4 AVC video, MPEG4 AAC audio in a MPEG2 Transport Stream, then the encoders or transcoders would input the various formats provided by the various receivers, and output a standard MPEG2 Transport Stream containing the required codecs.

Method for creation and distribution of segmented video over distributed multicast-aware sparse networks with low latency


An information recording/reproducing device includes a first electrode layer, a second electrode layer, a recording layer as a variable resistance between the first and second electrode layer, and a circuit which supplies a voltage to the recording layer to change a resistance of the recording layer. Each of the first and second electrode layers is comprised of IV or III-V semiconductor doped with p-type carrier or n-type carrier.

1. Field of the Invention
The present invention relates to an information recording/reproducing device with a high recording density.
2. Description of the Related Art
In recent years, compact portable devices have been widely used worldwide and, at the same time, a demand for a small-sized and large-capacity nonvolatile memory has been expanding rapidly along with the extensive progress of a high-speed information transmission network. Among them, particularly a NAND type flash memory and a small-sized HDD (hard disk drive) have rapidly evolved in recording density, and accordingly, they now form a large market.
Under such circumstances, some ideas for a new memory have been proposed, with the goal of greatly increasing the limit of recording density.
For instance, PRAM (phase change memory) adopts a principle in which materials capable of taking two conditions, an amorphous condition (ON) and crystalline condition (OFF), are used as recording materials, and these two conditions are caused to correspond to binary data "0" and "1" to record data.
Writing/erasing is performed in such a way that, for instance, the amorphous condition is prepared by applying a large power pulse to the recording material, and the crystalline condition is prepared by applying a small power pulse to the recording material. A reading is performed by causing a small read current to flow in the recording material to the degree that the writing/erasing is not generated, followed by measuring an electric resistance of the recording material. The resistance value of the recording material in the amorphous condition is larger than the resistance value of the recording material in the crystalline condition, and its ratio is in the degree of 103.
The greatest feature of the PRAM lies in a point that, even though element size is reduced to about 10 nm, the element can be operated. In this case, since the recording density of about 10 Tbpsi (tera bytes per square inch) can be realized, and accordingly, this is one of candidates for realizing increased recording density (for instance, refer to T. Gotoh, K. Sugawara and K. Tanaka, Jpn. J. Appl. Phys., 43, 6B, 2004, L818).
Further, a new memory has been reported which is different from the PRAM but has a very similar operation principle to the PRAM (for instance, refer to A. Sawa, T. Fuji, M. Kaisaki and Y. Tokura, Appl. Phys. Lett., 85, 18, 4073 (2004)).
According to this report, a representative example of a recording material to record data is nickel oxide, in which, like the PRAM, the large power pulse and the small power pulse are used for performing the writing/erasing. There has been reported an advantage that the power consumption at the time of the writing/erasing becomes small as compared with the PRAM.
Until now, although the details of an operation mechanism of the new memory are not clear, reproducibility is confirmed, and thus this is noticed as one of the candidates for the increased recording density. Further, some research groups are attempting to clarify the operation mechanism.
In addition thereto, proposed is a MEMS memory using MEMS (micro electro mechanical system) technology (for instance, refer to P. Vettiger, G. Cross, M. Despont, U. Drechsler, U. Durig, B. Gotsmann, W. Haberle, M. A. Lants, H. E. Rothuizen, R. Stutz and G. K. Binng, IEEE Trans. Nanotechnology 1, 39(2002)).
In particular, the MEMS memory, called Millipede, has a structure in which a plurality of array shaped cantilevers face a recording medium to which an organic substance is applied, and a probe at a tip of the cantilever comes into contact with the recording medium with appropriate pressure.
A writing is performed by selectively controlling the temperature of a heater added to the probe. That is, when increasing the temperature of the heater, the recording medium is softened, and then, depressions are formed on the recording medium because the probe forms dents in the recording medium.
A reading is performed by scanning the probe on a surface of the recording medium while causing a current to flow through the probe to the degree that the recording medium is not softened. When the probe sinks into the depression of the recording medium, temperature of the probe decreases, and the resistance value of the heater increases, so that it is possible to sense the data by reading this change of resistance value.
The greatest feature of the MEMS memory such as the Millipede lies in a point that since it is not necessary for each recording part to provide wiring to record bit data, the recording density can be improved remarkably. Under existing circumstances, a recording density of about 1 Tbps has already been achieved (for instance, refer to P. Vettiger, T. Albrecht, M. Despond, U. Drechsler, U. Durig, B. Gotsmann, D. Jubin, W. Haberle, M. A. Lants, H. E. Rothuizen, R. Stutz, D. Wiesmann and G. K. Binng, P. Bachtold, G. Cherubini, C. Hagleitner, T. Loeliger, A. Pantazi, H. Pozidis and E. Eleftheriou, in Technical Digest, IEDM03 pp. 763 to 766).
Further, subsequent to the Millipede, recently, performed are attempts to achieve a large improvement concerning power consumption, recording density or working speed while combining the MEMS technique with a new recording principle.
For instance, proposed is a system in which a ferroelectric layer is provided on the recording medium, and recording of the data is performed by causing dielectric polarization in the ferroelectric layer by applying a voltage to the recording medium. Theoretically, this system is predicted to be able to utilize one crystal as a unit (recording minimum unit) for recording one byte of data.
If the recording minimum unit is equivalent to one unit cell of the crystal of the ferroelectric layer, the recording density rises to a phenomenal approx. 4 Pbpsi (peta bytes per square inch).
Recently, based on development of a read system using SNDM (scanning nonlinear dielectric microscope), the new memory has advanced considerably toward practical use (for instance, refer to A. Onoue, S. Hashimoto, Y. Chu, Mat. Sci. Eng. B120, 130(2005)).


A light fixture that can be built upon itself to scale up or down the lumen output. More specifically, embodiments of the light fixture include an electronic housing flanked on each side with one or more light modules. The fixture can be tailored to the light needs of particular applications by adding or removing light modules from the fixture.

Different light fixtures, such as fixtures having different lumen outputs, are needed for different applications. Challenges arise in designing solutions that easily accommodate this range of options. Oftentimes, different and unique fixtures or fixture parts must be designed and offered, each targeted for a particular application. It would be useful to have a single fixture that could be built upon itself to scale up or down the lumen output.


There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing an instruction of an instruction set using a non-contiguous register specifier of a non-contiguous register specification. The instruction includes the non-contiguous register specifier.

1. Technical Field
The present invention generally relates to the processing of instructions in a microprocessor, and more particularly, to implementing an extended register set for one or more classes of instructions in a microprocessor.
2. Description of the Related Art
In modern microprocessors, increases in latencies have been an increasingly severe problem. These increases are occurring both for operations performed on the chip, and for memory access latencies. There are a number of reasons for this phenomenon.
One reason is the trend to achieve performance increases by using higher clock frequencies. This leads to deeper pipelining (i.e., the division of a basic operation into multiple stages) and, hence, a larger number of total stages, as an operation is divided into ever smaller units of work to achieve these high frequencies.
Yet another reason relates to the differences in chip and memory speeds. That is, while chip speeds have been increasing, memory speed has been increasing at a much smaller rate. Thus, in terms of processor cycles to access a memory location in memory, latency has increased significantly. The relatively faster increase in chip speed is due to both the above-mentioned deeper pipelining, and to CMOS scaling used as a technique to increase chip speeds, as disclosed by R. H. Dennard et al., in "Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions," IEEE Journal of Solid-State Circuits, SC-9, pp. 256-68, 1974, which is incorporated by reference herein.
Moreover, another reason relates to differences in wire and logic speeds. That is, as CMOS scaling is applied ever more aggressively, wire speeds do not scale at the same rate as logic speeds, leading to a variety of latency increases, e.g., by increasing the time required to write back an operation's results.
In addition to aggressive technology scaling and deep pipelining, computer architects have also turned to the use of more aggressive parallel execution by means of superscalar instruction issue, whereby multiple operations can be initiated in a single cycle. Recent microprocessors such as the state-of the art Power5 or PowerPC 970 processor can dispatch 5 operations per cycle and initiate operations at the rate of 7 and 9 operations per cycle, respectively.
To continue improving the performance of microprocessors, two challenges are of significance: namely achieving high levels of parallelism and tolerating increasing latency (in terms of processor cycles) of memory. Both achieving higher parallelism and tolerating longer latency require that programs are compiled so as to simultaneously use more independent strands of computation. This, in turn, requires a large number of registers to be available to support the multiple independent strands of computation by storing all of their intermediate results.
A result of the ability to execute more instructions in pipelines with increasing latency, and to initiate execution in multiple pipelines, requires ever-larger amounts of data to be maintained by a processor, to serve as inputs or to be received as results of operations. To accomplish this, architects and programmers have two options: retrieve and store data in a memory hierarchy; or in on-chip register file storage.
Of these choices, register file storage offers multiple advantages, such as higher bandwidth and shorter latency, as well as lower energy dissipated per access. However, the number of registers specified in architectures has not increased since the introduction of RISC computing (when the size of register files was increased from a customary 8 or 16 registers to 32 registers) until recently. Thus, as the demands for faster register storage to buffer input operands and operation results from an increasing number of instructions simultaneously being executed is growing, the number of architected registers has stayed constant, while the performance of memory hierarchies has de facto decreased in terms of processor cycles to provide data to the processor core.
To show how the effectiveness of register files has diminished, in light of changes to processor architecture that have occurred in response to technology shifts, consider the following simple ratios. About 15 years ago (circa 1990), a processor would typically have one floating point pipeline, with about 3 computational pipeline stages, plus typically an additional cycle for register file access. When processing Fused Multiply and Add (FMA) operations, i.e., merged floating point multiply-add high performance computation primitives, a four stage pipeline would have 4 FMA operations simultaneously in flight, each requiring 3 input registers and one output register, for a total of 16 registers to support all these computations in flight, leaving an additional 16 registers to hold other data and/or constants. Considering the parallelism provided by state-of-the-art microprocessors (e.g., the PowerPC 970 provides two floating-point pipelines) coupled with the latencies incurred by deep pipelining, a number of registers well in excess of the 32 registers provided by the PowerPC architecture are required to exploit the peak execution rate provided by a modern microprocessor.
Similarly, in that historic timeframe, a second level cache could be accessed with a 3 (processor) cycle hit latency, giving a ratio of about 10 registers per cycle of L2 cache access latency. This is a conservative measure; to express the actual amount of data required to be maintained in the register files in order to decouple memory access from computational, one would need to determine the number of operands consumed during such time, which scales up with issue width. Still, today, with a 10 to 12 cycle latency to L2, one could expect to see a requirement for 100 to 120 registers.
Large numbers of registers are in fact built, e.g., both the Power4 and Power5 microprocessors have well in excess of 32 registers. However, to exploit such larger register files, complex and area intensive renaming logic and out-of-order issue capabilities are required. Even then, the inability to express the best schedule in the program using a compiler or a skillfully tuned Basic Linear Algebra Subprogram (BLAS) or other such library limits the overall performance potential.
Some current microprocessors implement a technique called register renaming, whereby the limited number of architected registers is translated to use more registers internally. However, while this allows for an increase of the number of registers, register renaming is complex and incurs additional steps in the instruction processing of microprocessors. Thus, what is required to address the challenges in modern microprocessor design is an increased number of registers which are easy to access using an extended name space in the architecture, as opposed to techniques such as register renaming used in high-end microprocessors such as the IBM PowerPC 970 and Power5.
Recently, the IA-64 architecture and the CELL SPU architectures have offered implementations with 128 registers. In reference to these implementations, the IA-64 offers an implementation using instruction bundles, a technique to build instruction words wider than a machine word. While this resolves the issue of instruction encoding space, it leads to inefficient encoding due to a reduction of code density because an instruction word disadvantageously occupies more than a single machine word, thereby reducing the number of instructions which can be stored in a given memory unit.
Recent advances in the encoding instruction sets disclosed in the U.S. patent application to Altman et al., entitled "Method and Apparatus to Extend the Number of Instruction Bits in Processors with Fixed Length Instructions in a Manner Compatible with Existing Code", U.S. patent application Ser. No. 10/720,585, filed on Nov. 24, 2003, which is commonly assigned and incorporated by reference herein, advantageously allow wide instruction words to be used in conjunction with fixed size word instruction set architectures having an instruction format requiring only a single machine word for most instructions. While this offers a significant advantage over prior wide-word bundle-oriented instruction sets in terms of code density, decoding complexity is increased.
In an advantageous implementation of fixed width 32 bit instruction words, the CELL SPU instruction set architecture supports the specification of 128 registers in a 32 bit instruction word, implementing a SIMD-ISA in accordance with the U.S. patent application to Gschwind et al., entitled "SIMD-RISC Microprocessor Architecture", U.S. patent application Ser. No. 11/065,7017, filed on Feb. 24, 2005, and U.S. Pat. No. 6,839,828 to Gschwind et al., entitled "SIMD Datapath Coupled to Scalar/Vector/Address/Conditional Data Register File With Selective Subpath Scalar Processing Mode", which are commonly assigned and incorporated by reference herein.
While the SPU advantageously offers the use of 128 registers in a fixed instruction word using a new encoding that, in turn, uses fields of 7 adjacent bits in a newly specified instruction set, legacy architectures are not without deficiency. For example, since many bit combinations have been assigned a meaning in legacy architectures, and certain bit fields have been aside to signify specific architectural information (such as extended opcodes, register fields, and so forth) legacy architectures offer significant obstacles to encoding new information. Specifically, when allocating new instructions, the specification for these new instructions cannot arbitrarily allocate new fields without complicating the decoding of both the pre-existing and these new instructions.
Additionally, the number of bits in instruction sets with fixed instruction word width limits the number of different instructions that can be encoded. For example, most RISC architectures use fixed length instruction sets with 32 bits. This encoding limitation is causing increasing problems as instruction sets are extended. For example, there is a need to add new instructions to efficiently execute modern applications. Primary examples are multimedia extensions such as Intel's MMX and SSE2 and the PowerPC VMX extensions. Moreover, the number of cycles required to access cache and memory is growing as processor frequencies increase. One way to alleviate this problem is to add more registers to the processor to reduce the number of loads. However, it is difficult or impossible to specify additional registers in the standard 32-bit RISC instruction encoding.
The most common solution to this problem is an approach typically associated with CISC architectures, which allows multiple instruction lengths, not a fixed size such as 32 bits. This variable length CISC approach has several problems, and was one of the reasons RISC was developed in the 1980s. Among the problems with variable length CISC encoding is that it complicates instruction decode, adding pipeline stages to the machine or reducing frequency. Moreover, another problem with variable length CISC encoding is that it allows instructions to span cache line and page boundaries, complicating instruction fetch, as well as virtual address translation. Further, another problem with variable length CISC encoding is that such a CISC approach cannot be compatibly retrofitted to a RISC architecture. Most specifically, architectures having fixed length instructions today assume pervasively that all instructions are aligned on the boundary, that branch addresses are specified at a multiple of a fixed length instruction, and so forth. Further, no mechanisms are defined how to address the issue of page-spanning instructions, and so forth.
A second solution to the problem would be to switch to widening all instructions to a wider format, preferably a multiple of the original instruction set. For typical 32 bit RISC instruction sets, the next multiple is 64-bit instructions. However, if all instructions are 64-bits, approximately twice as much space as is currently used would be required to hold instructions. In addition, this would not be compatible with existing RISC code with 32-bit instructions. If 32-bit and 64-bit instructions are intermixed, the instruction set becomes CISC-like with variable width instructions, and with the associated problems just described.
Another solution to the encoding problem is employed by the IA-64 architecture from INTEL and HEWLETT PACKARD. The IA-64 packs 3 instructions in 16 bytes, for an average of 42.67 bits per instruction. This style of encoding avoids problems with page and cache line crossings. However, it "wastes" bits specifying the interaction between instructions, for example "stop bits" are used to indicate if all three instructions can be executed in parallel or whether they are to be executed sequentially or some combination of the two. The 3 instruction packing also forces additional complexity in the implementation to deal with three instructions at once. Finally, this 3 instruction packing format has no requirement to be compatible with existing 32-bit instruction sets, and there is no obvious mechanism to achieve compatibility with 32-bit RISC encodings.
All instruction bundles in this encoding are located at multiples of the bundle size.
A number of approaches have been disclosed to address this increasingly severe problem.
U.S. Pat. No. 6,157,996 to Christie et al., entitled "Processor Programably Configurable to Execute Enhanced Variable Byte Length Instructions Including Predicated Execution, Three operand Addressing, and Increased Register Space", which is incorporated by reference herein, teaches the use of a prefix byte to extend instruction semantics to include at least one of predicate information, extended register specification, and a third register operand. This implementation is undesirable for fixed instruction width RISC processors, as extension bytes cannot readily be accommodated in the instruction stream of a fixed width instruction set architecture.
U.S. Pat. No. 6,014,739 to Christie, entitled "Increasing General Registers in X86 Processors", which is incorporated by reference herein, discloses that an extra byte is extended in a variable instruction set to provide additional encoding bits. This implementation is undesirable for fixed instruction width RISC processors, as extension bytes cannot readily be accommodated in the instruction stream of a fixed width instruction set architecture.
U.S. Pat. No. 5,822,778 to Dutton et al., entitled "Microprocessor and Method of Using a Segment Override Prefix Instruction Field to Expand the Register File", which is incorporated by reference herein, discloses a microprocessor with expanded functionality within an existing variable length instruction set architecture. The control unit detects the presence of segment override prefixes in instruction code sequences executed in flat memory mode and uses prefix values to select a bank of registers. Those skilled in this and related arts will understand that the cost of decoding a prefix, determining the mode and the bank field, accompanied by fetching the instruction being modified by the prefix, incurs a significant complexity, delay and hardware inefficiency. In particular, the decoding of the prefix and bank selector has to be performed early, leading to additional complexity. In addition, prefixes cannot be readily employed in an architecture supporting only a fixed instruction word width.
Another non-transparent use of segment register override prefix bytes may be embodied within an instruction decode/execution unit. Decode/execution unit reads instructions, and operates on operands in a register(s) specified in the instruction. In this implementation, it is described that segment register override prefix bytes are used by a control unit to select one of multiple register banks which store the operands to be operated on by the decode/execution unit. Each register bank includes the full complement of x86 registers. In this manner, the register set of the architecture may be expanded without changing the instruction encodings. As will be appreciated by those skilled in this and related arts, a larger register set allows more operand values to be held in registers (which may be accessed quickly) and, thus, accesses to memory (which typically require a longer period of time) are lessened. In one implementation, no segment register override prefix byte is used to specify the first bank of registers, a segment register override prefix byte indicating the FS segment register specifies a second bank of registers, a segment register override prefix byte indicating the GS segment register specifies a third bank of registers, and a segment register override prefix byte indicating the ES segment register specifies a fourth bank of registers. In another implementation, the value stored within the selected segment register is used to select the appropriate register bank from numerous register banks.
In accordance with the preceding description relating to the other non-transparent use of segment register override prefix bytes embodied within an instruction decode/execution unit, all operands for a given instruction have to be retrieved from a common bank selected by the prefix selector, specified within the prefix selector in an alternate implementation. Using the segment selector as a bank selector for all operands of a given instruction is undesirable because it requires access to a control register to identify a bank, and restricts all instructions to have operands coming from just a single bank, leading to inefficient register allocation. Thus, if a common value has to be combined with other operands residing in multiple banks, copies of the common value have to be maintained, computed and updated in all banks, such that they can be combined with the other operands residing in the other banks, leading to inefficient register usage due to data duplication, and inefficient performance profile due to the duplication of work to compute the common value in all banks. It is to be appreciated that the preceding implementation has to be programmed like a clustered machine, with distinct register files represented by the different banks.
U.S. Pat. No. 5,822,778 to Christie et al., entitled "Microprocessor and Method of Using a Segment Override Prefix Instruction Field to Expand the Register File", which is incorporated by reference herein, discloses that the prefix and the bank select are decoded first, before the instruction is actually retrieved. Then the instruction word is combined, and an access performed. In comparison, the wide select can start the access early, and decode additional information in parallel with the access cycle.
U.S. Pat. No. 5,768,574, to Christie et al., entitled "Microprocessor Using an Instruction Field to Expand the Condition Flags and a Computer System Employing the Microprocessor", which is incorporated by reference herein, discloses a microprocessor that is configured to detect the presence of segment override prefixes in instruction code sequences being executed in flat memory mode, and to use the prefix value or the value stored in the associated segment register to selectively enable condition flag modification for instructions. An instruction which modifies the condition flags and a branch instruction intended to branch based on the condition flags set by the instruction may be separated by numerous instructions which do not modify the condition flags. When the branch instruction is decoded, the condition flags it depends on may already be available. In another implementation of the referenced invention, the segment register override bytes are used to select between multiple sets of condition flags. Multiple conditions may be retained by the microprocessor for later examination. The conditions that a program utilizes multiple times in a program may be maintained while other conditions may be generated and utilized.
U.S. Pat. No. 5,838,984 to Nguyen et al., entitled "Single-Instruction-Multiple-Data Processing Using Multiple Banks of Vector Registers", which is incorporated by reference herein, discloses a digital signal parallel vector processor for multimedia applications. As disclosed therein, a single instruction multiple data processor uses several banks of vector registers. This processor uses a bank bit included in a control register to identify a primary bank, and a secondary alternate bank to be identified by a select set of instructions. This is undesirable because it requires access to a control register to identify a bank, and restricts all operations to have operands coming from just a single bank, leading to inefficient register allocation. Thus, if a common value has to be combined with other operands residing in multiple banks, copies of the common value have to be maintained, computed and updated in all banks, such that they can be combined with the other operands residing in the other banks, leading to inefficient register usage due to data duplication, and inefficient performance profile due to the duplication of work to compute the common value in all banks. It is to be appreciated that the preceding implementation has to be programmed like a clustered machine, with distinct register files represented by the different banks.
U.S. Pat. No. 5,926,646 (hereinafter the "'646 patent") to Pickett et al., entitled "Context-Dependent Memory-Mapped Registers for Transparent Expansion of a Register File", which is incorporated by reference herein, discloses a context dependent memory mapped register accessing device for transparent expansion of a register file in a microprocessor in a computer system. Therein, in-core registers are made available as a memory-mapped address space. While the adding of additional registers in the core to be referenced by the processor is allowed, the use of memory mapping has several disadvantages. Specifically, the disadvantages relate to the fact that register names can only be properly resolved after the address generation phase, as a multitude of memory address forms can refer to a memory mapped register. This will increase the latency of access to these registers to almost the latency for first level cache access. In addition, a memory-mapped register can only be referenced for those instructions that have operand forms allowing memory accesses. This typically represents only a subset of operations, and often only a subset of operands therein. This limitation is particularly severe for RISC processors, which can only reference memory operands in load and store operations, imposing the additional cost of performing copies from the memory-mapped in-core registers to computationally useable operand registers.
In other disadvantageous aspects of the '646 patent, when addresses are generated before address generation from a subset of "preferred forms", address aliasing can occur and lead to incorrect program execution. In another disadvantageous aspect of the '646 patent, when an address to such in-core register is added to a linked list, and accessed by a remote processor, this will lead to data coherence inconsistencies. Alternatively, costly methods for accessing such registers from symmetric multiprocessing (SMP) remote nodes have to be implemented and provided.
U.S. Pat. No. 6,154,832 to Maupin, entitled "Processor Employing Multiple Register Sets to Eliminate Interrupts", which is incorporated by reference herein, discloses a processor which assigns a specified register set for default task and other sets for different interrupt source. While this extends the number of registers implemented in the processor, such an approach is not suitable for the extension of the register set useable by a single process or program.
U.S. Pat. No. 5,737,625 (hereinafter referred to as the "'625 patent") to Jaggar, entitled "Selectable Processing Registers and Method", which is incorporated by reference herein, discloses a high performance memory register selection apparatus which has a controller responding to a selection-word to control a circuit to select registers depending on the control field of a word and the prior register selection. This is limited in that only the architected set of prior art registers can be accessed at any one time, thereby not making more than the number of prior art registers available at any one time.
In another disadvantageous aspect of the '625 patent, additional instructions are required in the instruction stream to update the control word. In typical implementations, these updates will have to be made context synchronizing, i.e., no operations before the update may have outstanding references, nor can any instruction occurring in the instruction stream be dispatched until the control register update has completed. In one non-synchronizing aspect of an implementation, multiple rename versions of the control register have to be maintained, disadvantageously leading to design complexity, and high area and power usage.
U.S. Pat. No. 5,386,563 to Thomas, entitled "Register Substitution During Exception Processing", which is incorporated by reference herein, discloses a data processing system operable in either main or exception processing mode. In accordance with the invention, the CPU restores data stored in a saved processing status register, to another register upon leaving exception-processing mode. While this extends the number of registers implemented in the processor, this is not suitable for the extension of the register set useable by a single process or program.
Microcode used for implementing microprocessor ISAs using internal layering has used a variety of formats, using contiguous or non-contiguous fields. None of these were concerned with the maintenance of cross-generational compatibility or programming orthogonality. In general, microcode has different requirements, and methods from microcode are recognized to not be applicable to architected instruction sets by those skilled in this and related arts due to issues related to the internal representation, requirements for compatibility, decoding of instructions and detection of data and structural hazards (which are not supported in the restricted microcode programming model), as well as the need of maintaining compatible across generations of a design.
Prior art instruction sets have offered the use of non-contiguous immediate constants, e.g., as disclosed by Moreno et al., in "An innovative low-power high-performance programmable signal processor for digital communications", IBM Journal of Research and Development, Vol. 47, No. 2/3, 2003, which is incorporated by reference herein, to allow extended immediate specifications in bundle encodings, but do not address the encoding of non-contiguous fields in a fixed width instruction. The issues for immediate operand and similar fields are different because they do not require any early steering and access to determine dependences, access of register files, and so forth. In particular, this also has not required advanced decoding and/or register file access implementations. Thus, while constants have been encoded in non-contiguous ways in bundle instruction sets, the encoding of non-contiguous register file specifiers in fixed width instruction sets have eluded the inventors of this and other instruction sets.

Implementing instruction set architectures with non-contiguous register file specifiers

International Business Machines Corporation


In an apparatus for multi-segment recording/reproducing of a compressed digital video signal, a reproduced position within a group unit of the video signal is detected by a reproduced position detector in its reproducing state. A relative position detector detects and stores a phase difference of the reproduced position and a position indicated by a reference signal synchronized with the input video signal. A delay time adjuster adjusts a delay time of the compressed video signal according to this phase difference. A head is changed over from its reproducing state to its recording state by a switch so as to record the compressed video signal delayed by the delay time adjuster on a recording medium.

1. Field of the Invention
The present invention relates to a digital signal recording and reproducing apparatus capable of recording and reproducing a digital information signal, such as a digital video signal having compressed data and reduced bandwidth.
2. Description of the Prior Art
A digital signal recording and reproducing apparatus, such as a digital video tape recorder (e.g. a digital VCR), for recording and reproducing digitized video signals has been developed for professional use because it has reduced in deterioration of recorded and reproduced video signals caused by dubbing as compared with an analog signal recording and reproducing apparatus. Digitized video data, however, large contain an amount in the quantity of information, and consume a very large amount of tape for recording. So, for consumer-use, attempts have been made to record the digital video signal after data compression and bandwidth reduction by predictive coding, DCT (discrete cosine transform) coding, and variable length coding. For example, the data in each frame of the video signal is compressed, divided and recorded on plural consecutive tracks of a tape (e.g. "An Experimental Digital VCR with 40 mm Drum, Single Actuator and DCT-Based Bit-Rate Reduction", S. M. C. Borgers et al., IEEE Transactions on Consumer Electronics, Vol. 34, No. 3, pp. 597-605, August 1988).
This method is explained below with reference to FIG. 1. A magnetic tape 11 having a specific tape width is wound on a cylinder 12, and is driven to run at a constant speed. In recording, an input video signal 211 is inputted to an A/D (analog-to-digital) converter 201 to be digitized into a digital video signal 212 having a specific bit width. A compressor 202 compresses the data of the digital video signal 212, and produces a compressed video signal 213. At this time, the compressor 202 divides a specified group unit (one frame) of the digital video signal 212 further into small blocks, and shuffles the small blocks. A modulator 203 modulates the compressed video signal 213 to be suited to magnetic recording, and produces a modulated video signal 214. The modulator 203 also combines the modulated video signal 214 with a pilot signal when necessary. A switch 204 is connected to the 204A side when recording to send the modulated video signal 214 to magnetic heads 13A and 13B and record the signal on a magnetic tape 11. By the shuffling conducted in the compressor 202, the video signal within each specified group unit (in each frame) is divided into six tracks.
When reproducing and magnetic heads 13A, 13B mounted on the cylinder 12 reproduce the modulated video signal 215 from the magnetic tape 11. The reproduced modulated video signal 215 is demodulated into a compressed video signal 216 by a demodulator 205, and then decompressed into a digital video signal 217 by a decompressor 206. A D/A (digital-to-analog) converter 207 converts the digital video signal 217 to an analog video signal 218.
In such digital recording and reproducing apparatus (for example, a digital VCR), when a new video signal is recorded on an already recorded magnetic tape, the linkage part of the recorded tracks and the shuffling group units partially become discontinuous. As a result, when reproducing a discontinuously recorded tape, noise is formed in the reproduced image at this discontinuous portion, and the quality of the reproduced image is impaired.
For example, as shown in FIG. 2, when a new signal is newly recorded in a pre-recorded region, the continuity of the tracks is interrupted at the starting position of the new recording. Further, when one frame which is the group unit of shuffling and compression is divided into six tracks to be recorded, the starting position of the new recording also spoils the continuity of this six-track unit. Therefore fore, when such a discontinuously recorded tape is reproduced, the tracking control is disturbed due to track discontinuity, or the decompression operation is disturbed due to discontinuity of the group unit, thereby producing noise temporarily on the reproduced screen.
To avoid such discontinuity, for example, a method of eliminating discontinuity by mechanical action is disclosed in U.S. patent application "Reproducing Apparatus", Yoshio Sakakibara et al., Ser. No. 08/041,124 (tentatively assigned), filed Mar. 31, 1993. According to this method, a magnetic tape is preparatory run in a reproduction in a pre-roll section before the start of recording, and the reproduced position of the magnetic tape 11 is changed by an amount corresponding to a specified number of tracks so that the phase of the frame of the reproduced signal coincides with the phase of the frame of the signal to be recorded. At the moment of reaching the recording start position, the actual recording is started. In such method, however, since it requires a mechanical action, it takes a very long time until the transfer action of the reproduced track position of the magnetic tape is finally stabilized.

Apparatus for edit recording of a compressed digital video signal on a recording tape

Matsushita Electric Industrial Co., Ltd.


A service provider receives a set of credentials from a customer and a request to access one or more services provided by the service provider. An authentication service of the service provider receives the set of credentials and, based at least in part on the received set of credentials, one or more activities performed by the customer, the customer's user profile, and the system configuration of the customer's computing device, calculates a risk score. The authentication service subsequently utilizes the calculated risk score to determine a credential rotation schedule for the set of credentials. The authentication service updates one or more servers to enforce the new credential rotation schedule and enables the customer to utilize the set of credentials to access the one or more services.

Customers and other users often utilize one or more sets of credentials to protect their personal accounts and to enable access to these accounts or other computing resources. As a general business practice, service providers may recommend to these customers and other users to rotate these credentials to reduce the risk of a potential credential leakage or to respond to incidents of credential leakage. For instance, service providers may schedule the rotation of users' credentials at fixed time cycles based on regulatory requirements and/or an organization's internal policies. In such schemes, all credentials may be treated the same in terms of how often these credentials are to be rotated. However, such practices may not take into account the sensitivity of a customer's account to a potential credential leakage, thereby necessitating a shorter rotation cycle. Manually adjusting a fixed credential rotation schedule to account for such sensitivity may be time and resource intensive, thereby making it difficult for service providers to quickly and efficiently address any potential schedule adjustments.

Risk-based scheduling for credential rotation


A method for producing a tubular body with reduced internal stress uses 3D printing. The tubular body has an outer wall with a stiffening structure extending along at least part of the outer wall. The method sets a printing plane for 3D printing with a 3D printer, and prints a tubular body layer in the printing plane with the 3D printer. The tubular body layer has an outer wall layer and a stiffening structure layer extending in the printing plane along a periphery of the outer wall layer. The stiffening structure layer has at least two portions spaced apart from one another. The method produces an outer wall with a stiffening structure for a tubular body with reduced internal stress.

Additive Layer Manufacturing (ALM) or 3D printing (three-dimensional printing) is being used increasingly frequently in aircraft construction. In the case of some types of aircraft, this applies in particular to fuel manifolds, which have previously been produced in an expensive casting or welding process. In the case of larger components, measuring about 400 mm in one direction, however, 3D printing causes great internal stresses, which deform the component during the printing, so that cracks are produced and the printed component possibly ruptures.
In order to reduce the internal stress during production, it is known to optimize the alignment of the components in the printing chamber. In the case of larger components, however, the entire printing chamber is used, so that it is not possible to optimize the alignment of the component.

Method for producing a tubular body with reduced internal stress by using 3D printing, and a tubular body with reduced internal stress


An on-board update device that acquires an update program transmitted from an external server located outside a vehicle, and performs processing to update a program for an on-board ECU provided in the vehicle, the on-board update device including a control unit that controls transmission of the update program to the on-board ECU, wherein, when the transmission is to be resumed after an interruption of the transmission, if identification information of the on-board ECU is different from the identification information before the interruption of the transmission, the control unit determines that the on-board ECU has been replaced during the interruption of the transmission, and performs predetermined processing.

Vehicles are provided with on-board ECUs (Electronic Control Units) for controlling on-board devices such as a power train system for controlling an engine and so on, and a body system for controlling an air conditioner and so on. The on-board ECUs include computation processing units such as MPUs, rewriteable nonvolatile storage units such as RAMs, and communication units for communicating with other on-board ECUs, and control on-board devices by reading and executing control programs stored in the storage units. Furthermore, relay devices that have wireless communication functionality are mounted in the vehicles. It is possible to communicate with a program providing device that is connected to a network outside the vehicle, via the relay device, download (receive) a control program for the on-board ECUs from the program providing device, and update a control program for the on-board ECUs (for example, see JP 2017-97851A).
A relay device according to JP 2017-97851A is problematic in that no consideration is given regarding how to address a case in which the on-board ECU is replaced with another one while transmission between the relay device and the on-board ECU is interrupted during the processing performed to transmit a downloaded control program to the on-board ECU.
An object of the present disclosure is to provide an on-board update device and so on that can appropriately address a case in which, when a program for an on-board ECU is to be updated, the on-board ECU is replaced with another one during the interruption of the transmission between the on-board update device and the on-board ECU.

On-board update device, update processing program, program update method, and on-board update system


A pneumatic radial ply tire (50) has a tread (52), a carcass (61) with two sidewalls (77, 78), a single radial ply (70) reinforced with inextensible metal cords, two annular beads (36axe2x80x2, 36bxe2x80x2), and a belt structure (58) located radially between the tread and the radial ply structure (56). Each sidewall (77, 78) is reinforced with wedge inserts (59a, 59b) containing stiffener layers (72a, 72b, 73a, 73b) that carry the compressive loading to which the tire is subjected during runflat operation. The incorporation of wedge-insert stiffeners (72a, 72b, 73a, 73b) provides a light-weight runflat tire having a simplified construction.

This invention relates to pneumatic radial-ply runflat tires and ways to increase the bending stiffness of sidewall wedge inserts.
Various methods have been devised for enabling the safe, continued operation of unpressurized or underpressurized vehicle tires with the intent of minimizing further damage to the uninflated tire and without simultaneously compromising vehicle handling over a distance from the location where the tire has lost its pressure to a place desired by the driver, such as a service station where the tire can be changed. Loss of tire pressure can result from a variety of causes, including puncture by a foreign object such as a nail or other sharp object piercing the pneumatic tire installed on a vehicle.
Pneumatic tires designed for sustained operation under conditions of unpressurization or underpressurization are also called runflat tires, as they are capable of being driven in the uninflated, or what would generally be called the xe2x80x9cflatxe2x80x9d condition. A conventional pneumatic tire collapses upon itself when it is uninflated and is carrying the weight of a vehicle. The tire""s sidewalls buckle outward in the circumferential portion of the tire where the tread contacts the ground, making the tire xe2x80x9cflatxe2x80x9d.
The term xe2x80x9crunflatxe2x80x9d is generally used to describe a tire that is designed such that the tire structure alone, in particular the structure of the sidewalls, has sufficient rigidity and strength to support the vehicle load when the tire is operated without being inflated. The sidewalls and internal surfaces of the tire do not collapse or buckle onto themselves, and the tire does not otherwise contain or use other supporting structures or devices to prevent the tire from collapsing.
In general, runflat tires incorporate sidewalls that are thicker and/or stiffer than a conventional non-runflat tire so that the tire""s load can be carried by an uninflated tire with minimum adverse effects upon the tire itself and upon vehicle handling until such reasonable time as the tire can be repaired or replaced. The typical methods used in sidewall thickening and stiffening include the incorporation of circumferentially disposed wedge inserts in the inner peripheral surface of the sidewall portion of the carcass, which is the region in the tire usually having the lowest resistance to deformation under vertical loading. In such runflat tire designs, each sidewall is thickened in such a way that its overall thickness is increased in the region between the bead and the tread shoulder. The inserts in each sidewall, in combination with the plies, add rigidity to the sidewalls in the absence of air pressure during runflat operation. Such reinforced sidewalls, when operated in the uninflated condition, experience a net compressive load in the region of the sidewall that is in the road-contacting portion of the tire. Also, the bending stresses on the sidewalls are such that the outer portions of the reinforced sidewalls experience tensile forces while the inner portions experience compression stresses during runflat operation.
U.S. Pat. No. 5,368,082 (""082) of Oare et al, having a common assignee with the present invention, discloses a low aspect ratio, runflat, pneumatic radial ply tire which employs special sidewall inserts to improve stiffness. Approximately six additional pounds of weight per tire was required to support an 800 lb load in this uninflated tire. This earlier invention, although superior to prior attempts at runflat tire design, still imposed a weight penalty that could be offset by the elimination of a spare tire and the tire jack. However, this weight penalty becomes even more problematic in the design of tires having higher aspect ratios. The ""082 Patent teaches a sidewall construction for runflat tires in which the tire is constructed with two plies, an inner liner and two reinforcing wedge inserts in each sidewall. The two inserts in each sidewall are disposed such that one insert is located between the two plies while the other insert is located between the inner liner and the first or innermost ply.
U.S. Pat. Nos. 5,427,166 and 5,511,599 of Willard, Jr., and assigned to Michelin Corporation disclose the addition of a third ply and the addition of a third insert in the sidewall to theoretically improve the runflat performance of a runflat tire over that of the ""082 Patent discussed above. These two Michelin patents discuss some of the load relations that occur in the uninflated condition of the tire and demonstrate that the principle disclosed in the ""082 patent can be applied to additional numbers of plies and inserts.
However, use of large amounts of rubber to stiffen the sidewall members, as in the Michelin patents previously discussed, usually increase flexure heating and lead to earlier tire failure during runflat operation. This is especially so when the tire is operated at high speeds. Therefore, one goal of runflat tire design is to minimize the number of wedge inserts used to stiffen each sidewall and reduce the total amount of elastomeric wedge insert material used in a runflat tire.
While the increased resistance to compression deflection of the multiple inserts tends to prevent the collapse of the uninflated loaded tire, the use of multiple plies and more than one reinforcing wedge insert in each sidewall, has drawbacks which include the above mentioned increase in tire weight and flexure-induced heat build up. Such designs also increase the tire""s complexity in ways that adversely affect manufacturing and quality control.
U.S. Pat. No. 3,464,477 of Henri Verdler, and assigned to Michelin Corporation discloses a pneumatic tire particularly for off-highway (OTR) use wherein the inflated tire is to be protected against damage such as cuts and abrasion to the sidewalls when the tire is used on rocky or rough ground. Although this is not a runflat design, there are useful teachings presented since the inventor has determined that sidewall damage from such OTR operation can be ameliorated by reinforcing the tire sidewalls: xe2x80x9csurprisingly . . . the sidewalls should be reinforced inwardly of the carcass plies.xe2x80x9d The disclosed reinforcement of each sidewall is a single reinforcing wedge insert (xe2x80x9celastomeric reinforcementxe2x80x9d) which has a maximum thickness at the mid height of the sidewall of the tire between about 1% and 3% of the overall maximum width of the tire, the reinforcement tapering toward its edges, that is toward the tread and toward the corresponding bead of the sidewall and extending about half of the height of the tire. The elastomeric composition is not very important other than that it should not have a hysteretic loss greater than 25%. The elastomer may contain one or more plies of elastic cords of metallic or non-metallic type arranged radially or only slightly inclined to the radial direction, for example at an angle between about 10 and 30 degrees to the radial. Suitable elastic cords for reinforcing the internal layer of the tire are polyamide cords, such as nylon, or elastic metallic cables, preferably having a modulus of elasticity less than 5000 DaN/mm2. The preferred embodiment of the sidewall reinforcement xe2x80x9clayersxe2x80x9d is summarized in claim 6 and includes xe2x80x9ca pair of plies of elastic polyamide cords, . . . the cords of one ply crossing the cords of the other ply, said layers and said plies therein terminating short of said bead and the edge of said tread adjacent to said sidewall.xe2x80x9d There is no discussion or specification of the length or position of the ends of one ply relative to the other ply in the pair of plies. The disclosed design, with specific limits on insert thickness and insert ply cord angles, provides sidewall reinforcement suitable for providing xe2x80x9csurprisingly increased resistance to damage . . . cutting or gashing by cutting objectsxe2x80x9d when operating an inflated tire on rocky terrain.
Clearly, the goal in runflat tire design is to provide a low-cost, light-weight tire that gives good runflat vehicle handling as well as good service life during runflat operation.
It is an object of the present invention to provide a pneumatic, radial runflat ply tire as defined in one or more of the appended claims and, as such, having the capability of being constructed to accomplish one or more of the following subsidiary objects.
One object of the present invention is to provide a pneumatic radial runflat ply tire with a simplified design that allows for improved manufacturing quality control.
Another object of the present invention is to provide a pneumatic radial runflat ply tire having a reduced weight as compared with prior art designs.
Another object of the present invention is to provide a pneumatic radial runflat ply tire having a reduced heat generating potential during runflat operation as compared with prior art designs.
Still another object of the present invention is to provide a pneumatic radial runflat ply tire having good normal inflation handling and ride characteristics as well as good runflat handling properties and runflat durability and operational life.
The present invention relates to a pneumatic radial ply runflat tire having a tread, a carcass comprising a radial ply structure, a belt structure located between the tread and the radial ply structure, an inner liner and two sidewalls each reinforced by a single circumferential wedge insert between the radial ply structure and the inner liner that contains a pair of wedge-insert stiffener layers circumferentially disposed therein. Within each sidewall wedge insert, a first stiffener located closest to the inner liner has a radial width preferably within the range of the range of 30 percent to 50 percent of the total radially oriented span of the respective wedge insert. A second stiffener within each sidewall wedge insert, i.e., the one located most distant from the innerliner, has a radial width that is preferably within the range of between 60 percent to 90 percent and most preferably in the range of 70 percent to 80 percent of the total radially oriented span of the respective wedge insert. The radially innermost and outermost ends of the first wedge-insert stiffener are located radially within the radial span of the second wedge-insert stiffener. Each wedge-insert stiffener comprises parallel-aligned monofilaments, wires or metal cords, which are angularly oriented preferably between 20 degrees and 55 degrees with respect to the radial direction. The parallel-aligned monofilaments, wires or cords of each of the respective two wedge-insert stiffeners within each sidewall wedge are angularly oriented in opposite directions with respect to the radial direction. The wedge-insert stiffeners can be constructed of parallel-aligned nylon or wire monofilaments, or of parallel-aligned metal cords.
Other benefits and advantages of the invention will become apparent to those skilled in the art to which it pertains upon a reading and understanding of the following detailed specification.

Reinforced wedge-insert construction for extended mobility tires


A dental sensor holder including a strip of pliable, longitudinally elastic material having two ends. The holder is constructed by permanently bonding the two ends of the strip to form a somewhat elastic loop. In addition, the sensor holder includes an adjustable bond portion on the inside of the loop which may selectively be engaged to join adjacent portions of the strip into a functional bitewing.

In the dental arts the term "bitewing" has two related meanings. In one instance a bitewing refers to a dental x-ray image or film designed to show the crowns of the upper and lower teeth simultaneously. Additionally, a bitewing may be defined as the holder for an x-ray film or sensor that includes a projecting fin on one side that in use is held between the teeth. According to this second definition, the bitewing, or bitewing holder, thus extends perpendicular to the plane of an x-ray film or sensor such that a dental patient may bite down on the bitewing while the film or sensor is inside of his or her mouth, opposite the x-ray source.
Historically, bitewings or bitewing tabs were simple cardboard devices which were attached to an x-ray film holder, used once and then thrown away. Many dentists no longer use x-ray film. On the contrary, x-ray images are often now acquired with digital electronic x-ray sensors.
Unlike a traditional x-ray film, a digital x-ray sensor (referred to herein as a sensor) is a reusable device. Typical sensors are provided in a substantially flattened package with a data cable extending from one end. In use the sensor will typically be associated with a bitewing type device to take bitewing images. Thus, in use a modern sensor is positioned in the same manner as a traditional film for a bitewing image, with the patient biting down on a projecting fin attached to the sensor.
Unlike conventional x-ray film, a sensor must be used multiple times. Therefore, sensors are typically placed within sterile disposable sheaths before use to avoid the transfer of germs or other substances from one patient to another. Various bitewing type holders have been developed which tightly wrap around the sensor or sensor sheaths or alternatively are bonded with adhesives to a sensor and sheath and which further provide a bitewing fin. Known sensor holders can be somewhat problematic to use because they can be uncomfortable for the patient, or difficult to install and remove from the sensor. For example, sensors may be easily damaged by pulling on the data cable during sheath or holder removal. A conventional holder applied loosely to facilitate removal may not adequately secure the sensor during the x-ray imaging process.
The embodiments disclosed herein are directed toward overcoming one or more of the above problems set forth above.

This patent is subject to a terminal disclaimer.

Dental sensor holder and method of holding a dental sensor


A cap for fastening devices comprises an inner cap member fittable over a hexagonal engageable portion of the fastening device and having a top wall centrally formed with a threaded bore, an outer cap member fittable over the inner cap member and having a bolt hole formed in a top wall thereof and corresponding to the threaded bore in position, and a bolt to be screwed into the bore through the bolt hole. The inner cap member has a peripheral wall formed with six deformation promoting slits extending longitudinally thereof. The outer surface rear end portion of the peripheral wall has projecting tapered portions for inwardly moving the rear end portion of the inner cap member when the outer cap member is slidingly moved relative to the inner cap member by rotating the bolt relative to the inner cap member in a screwing-in direction.

The present invention relates to a cap for fastening devices which is useful for motor vehicle wheels, studded devices on wheels, butteries, roof lamps of four-wheel drive vehicles and like parts for preventing a third person from stealing such a part by loosening bolts or nuts fastening the part without permission or for attaching the studded device to the wheel.
FIG. 9 shows a cap 60 for fastening devices which is already known. With reference to FIG. 9, the cap comprises a cap body 61 generally in the form of a hollow cylinder for covering a polygonal engageable portion of a wheel attaching nut A. The top wall 61a of the cap body 61 has a through hole 62 close to a peripheral portion thereof. A pressure piece 65 for preventing the cap from slipping off has an outer slanting face 64 and is disposed inside an inner slanting face 63 internally provided on the cap. A pressure piece sliding screw 66 inserted through the hole 62 has an end portion screwed into a threaded bore in the pressure piece 65. A spring 69 is provided around the screw 66. The head 67 of the screw 66 is formed in its front surface with an engagement cavity 68 of specified shape. When rotated relative to the pressure piece 65 in the screwing-in direction, the screw 66 slidingly moves the outer slanting face 64 on the inner slanting face 63, moving the pressure piece 65 also radially inward simultaneously with the axial movement and thereby pressing the pressure piece 65 against the nut A with a great force, whereby the cap 60 is prevented from slipping off the nut A.
The conventional cap 60 has the advantage of being usable for fastening devices of any type, but since the cap body needs to accommodate therein the pressure piece 65 for preventing the cap from slipping off, the cap body has an outwardly projecting side portion corresponding to the pressure piece. In the case where the wheel has a small nut insertion hole in which only a small clearance is available around the nut A, there arises the problem that the projecting portion interferes with the edge of the wheel defining the nut insertion hole to render the cap 60 not fittable to the nut A.

Cap for fastening devices for motor vehicle wheels and the like


A slider mounted TAMR (Thermal Assisted Magnetic Recording), DFH (Dynamic Flying Height) type read/write head using optical-laser generated surface plasmons in a small antenna to locally heat a magnetic medium, uses the same optical laser at low power to pre-heat the antenna. Maintaining the antenna at this pre-heated temperature, approximately 50% of its highest temperature during write operations, allows the DFH mechanism sufficient time to compensate for the thermal protrusion of the antenna at that lower temperature, so that thermal protrusion transients are significantly reduced when a writing operation occurs and full laser power is applied. The time constant for antenna protrusion is less than the time constant for DFH fly height compensation, so, without pre-heating, the thermal protrusion of the antenna due to absorption of optical radiation cannot be compensated by the DFH effect.

1. Field of the Invention
This invention relates to the fabrication of magnetic read/write heads that employ dynamic fly height (DFH) to control their aerodynamics and TAMR (thermally assisted magnetic recording) to enable writing on magnetic media having high coercivity and high magnetic anisotropy. More particularly, it relates to a method for controlling thermally induced protrusion of a TAMR plasmon antenna to prevent head/disk interference during hard disk drive (HDD) operation.
2. Description of the Related Art
Magnetic recording at area data densities of between 1 and 10 Tera-bits per in2 (Tbpsi) involves the development of new magnetic recording mediums, new magnetic recording heads and, most importantly, a new magnetic recording scheme that can delay the onset of the so-called "superparamagnetic" effect. This effect is the thermal instability of the extremely small regions on which information must be recorded, in order to achieve the required data densities. A way of circumventing this thermal instability is to use magnetic recording mediums with high magnetic anisotropy and high coercivity that can still be written upon by the increasingly small write heads required for producing the high data density. This way of addressing the problem produces two conflicting requirements: 1. the need for a stronger writing field that is necessitated by the highly anisotropic and coercive magnetic mediums and; 2. the need for a smaller write head of sufficient definition to produce the high areal write densities, which write heads, disadvantageously, produce a smaller field gradient and broader field profile. Satisfying these requirements simultaneously may be a limiting factor in the further development of the present magnetic recording scheme used in state of the art hard-disk-drives (HDD). If that is the case, further increases in recording area density may not be achievable within those schemes. One way of addressing these conflicting requirements is by the use of assisted recording schemes, notably thermally assisted magnetic recording, or TAMR.
The prior art forms of assisted-recording schemes being applied to the elimination of the above problem share a common feature, which is to pump energy into the magnetic recording system through the use of physical methods that are not directly related to the magnetic field produced by the write head. If such an assisted recording scheme can produce a medium-property profile to enable low-field writing localized at the write field area, high data density recording can be achieved by even a weak write field because of the multiplicative effect of the spatial gradients of both the medium property profile and the write field. These prior art assisted-recording methods either involve deep sub-micron localized heating by an optical beam or ultra-high frequency AC magnetic field generation. The heating effect of TAMR works by raising the temperature of a small region of the magnetic medium to essentially its Curie temperature (TC), at which temperature both its coercivity and anisotropy are significantly reduced and magnetic writing becomes easier to produce within that region. In the following, we will address our attention to a particular implementation of TAMR, namely the transfer of electromagnetic energy to a small, sub-micron sized region of a magnetic medium through interaction with the near field of an optical frequency laser excited surface plasmon. The surface plasmon is excited in a small conducting antenna approximately 200 nm in width that is incorporated within the read/write head structure. The source of optical excitement is a laser diode, also incorporated within the read/write head structure, which directs its beam at the antenna through a means such as an optical waveguide.
Referring first to FIG. 1, there is shown an underside view (looking up from the recording medium) of the air bearing surface (ABS) plane of a ceramic slider (42) in which is contained a read/write head (40) that incorporates a magnetoresistive type read head (42) and an inductive write head (43). Note, the figure shows only the emergent portions of the head in the plane of the ABS. The ABS is not truly planar, but has surface structures, such as a central rail (56), side rails (58) and airflow channels (60) that allow the slider to fly over a rotating disk. The rotation of the disk and resulting airflow direction (shown as an arrow) is into edge (64), called the leading edge of the slider, and away from edge (66), called the trailing edge of the slider. We shall refer below to additional features within the head structure itself and surrounding the head within the slider.
Referring now to FIG. 2, there is shown a schematic illustration of a prior art read/write head, as shown by Ratner et al., U.S. Patent Application 2003/0112542, that includes an exemplary form of thermal-assisted magnetic recording, (TAMR), that could be the subject of the present invention. The head is shown in vertical cross-section, positioned above a magnetic recording medium (7). The active elements of this head that are exposed to the surface of the recording medium, or elements substantially similar in structure, are shown as (40) in FIG. 1 and also schematically indicated as being enclosed within rectangular box labeled (40) in FIG. 2. These elements include a read sensor (74) and the upper (100) and lower (98) pole tips of the inductive write head. Although the figure also shows the inductive coils (84), the upper yoke (94) and insulative filling material (88) of the write head, these structures are not the focus of the present invention.
In this exemplary read/write head, an optical laser diode (shown with no detail) (200) directs a beam of optical frequency electromagnetic radiation (203) through a waveguide (204) and thereupon onto a small region of the ABS surface (48) of the read/write head. This small region, which is substantially between the poles of the write head, contains a small metallic antenna (102), typically of about 200 nm width, which is struck by the laser beam. The laser beam excites a plasmon mode within the antenna surface and because the antenna is close to the medium surface (within an optical wavelength), the electromagnetic near field of the plasmon impinges on a small, sub-micron sized area of the medium (77) and deposits energy at that area to heat it. This region of energy deposition must be no larger in area than a magnetic recording grain, since a larger deposition area could erase information already stored in neighboring grains.
As noted, the energy of the plasmon near field is focused into a sub-micron size optical spot (77) on the recording layer (7) close to the magnetic recording pole-tips (98) and (100), where the magnetic write field profile of the pole-tip overlaps with the optical spot. The optical energy delivered to the recording layer heats up the layer locally to a temperature substantially equal to the Curie temperature, TC, of the recording medium. This temperature rise produces a decrease in the magnetic anisotropy and coercivity of the recording layer material and the magnetization of the recording layer grains becomes more easily switched by the write field. With the optically created thermally modified medium anisotropy profile overlapping with the writer magnetic field profile, the effective write field spatial gradient can be significantly enhanced due to the multiplicative effect of the thermal and magnetic field gradients. Thus, recording can be achieved with the lower magnetic write field of the smaller write head with a resulting higher recording density.
Along with such technology as TAMR to enhance recording on high coercivity media at very high area density, the modern read/write head also incorporates technology, called dynamic fly height, DFH, that allows it to fly very close to a disk surface during disk drive operation, while minimizing the incidence of head/disk interference, such as inadvertent contact between the head and the disk surface. Referring now to schematic (prior art) FIG. 3, there is shown the ABS structure of FIG. 1 further containing a heating element (47) that is adjacent to the read/write head (40). When this heating element is energized, it locally heats the region (40), causing it to protrude relative to the ABS plane. This thermally produced protrusion enables the operational flying height of the slider to be controlled during HDD operation, so that the read and write heads can be lowered relative to the disk surface or raised relative to the disk surface. Since DFH technology is well known in the prior art (including prior art cited below), it will not be discussed further here other than by its incorporation through the cited prior art.
The combination of TAMR technology and DFH technology produces the following problem. As the plasmon antenna heats up due to the absorption of optical energy from the laser, it very quickly protrudes from the surface of the read/write head and approaches the medium surface. In principle, the thermal response of the DFH element can compensate for the antenna protrusion by slightly lifting the head away from the disk surface to increase fly height. However, the time constant for plasma antenna protrusion, ΘPA, is less by a factor between 10 and 50 than the time constant for DFH response, ΘDFH so the DFH mechanism cannot adequately compensate for the antenna protrusion. This will be discussed with relation to FIG. 5, below. This large difference in response times leads to an antenna protrusion transient during switching between the read/write and write/read condition which can lead to head/disk interference.
The prior art discloses both DFH technology and TAMR technology, as, for example: U.S. Patent Application 2004/0252396 (Pleiss) discloses preheating by applying an electrical current to the write element to reduce pole tip protrusion. U.S. Patent Application 2007/0247744 (Satoh et al) teaches preheating to prevent poor overwriting. U.S. Patent Application 2006/0092550 (Ishii et al) shows preheating a write head to avoid the instability of thermal protrusion. U.S. Published Patent Application 2008/0170321 (Shimozato) discusses preheating of the MR heater.
U.S. Pat. Nos. 7,428,124 and 7,430,098 (Song et al) and U.S. Pat. No. 7,372,665 (Stoev et al) propose a variety of heating elements. U.S. Pat. No. 6,940,691 (Maat) shows a TAMR system where heaters induce protrusion of the write head pole tips. U.S. Patent Application 2003/0112542 (Rettner et al) discloses a TAMR including surface plasmon resonance.
None of the above prior art inventions discuss the protrusion transient problem or suggest methods of eliminating it.

Thermally-assisted magnetic recording head capable of reducing the transient protrusion of an antenna