The semiconductor device includes a first semiconductor region of a first conductivity type partially extending to a top face of a semiconductor substrate; a second semiconductor region of a second conductivity type formed on the first semiconductor region; a third semiconductor region of the first conductivity type formed on the second semiconductor region; a fourth semiconductor region of the second conductivity type formed on the second semiconductor region and adjacent to the third semiconductor region; a trench penetrating through the second semiconductor region and the third semiconductor region; a gate insulating film formed on an inner wall of the trench; and a gate electrode formed on the gate insulating film within the trench. The semiconductor device further includes a fifth semiconductor region of the second conductivity type formed on the second semiconductor region to be sandwiched between the fourth semiconductor region and a portion of the first semiconductor region positioned on a side of the fourth semiconductor region. An impurity concentration in the fifth semiconductor region is higher than an impurity concentration in the second semiconductor region.

The present invention relates to a semiconductor device having a trench MIS (Metal-Insulator-Semiconductor) gate structure and a method for fabricating the same.
A trench gate structure formed by filling a gate electrode in a trench formed in a semiconductor substrate is conventionally applied to semiconductor devices such as an IGBT (Insulated Gate Bipolar Transistor) and a MISFET (Field Effect Transistor), and is advantageous for power supply and the like in particular. For example, an IGBT having a trench gate structure has both a high input impedance characteristic of a MISFET and a low saturated voltage characteristic of a bipolar transistor, and is widely used in an uninterruptible power supply and various types of motor driving devices.
FIG. 10 is a cross-sectional view of a semiconductor device having a conventional trench MIS gate structure disclosed in Japanese Patent No. 2662217. The conventional semiconductor device of FIG. 10 has a flat surface in all masking steps while a vertical contact to a gate electrode can be formed. Specifically, on a multilayered structure of a high concentration drain region 110 and a low concentration drain region 111 of a first conductivity type (N-type), body regions 120a and 120b of a second conductivity type (P-type) spaced from each other by an upward opening trench are formed. The high concentration drain region 110 is connected to a drain contact 117. Also, source regions 121a and 121b of the first conductivity type are formed in portions of the body regions 120a and 120b in the vicinity of the upward opening trench. Metal contacts 118 and 119 for attaining contact with the source regions and the body regions are formed on the source regions 121a and 121b and the body regions 120a and 120b, respectively.
The upward opening trench extends into the low concentration drain region 111 through portions between the source regions 121a and 121b and between the body regions 120a and 120b. A gate insulating film 132 is formed on the inner wall of the upward opening trench, and a gate electrode (vertical gate) 133 is filled in the upward opening trench excluding an upper portion thereof with the gate insulating film 132 sandwiched therebetween. The upper face of the gate electrode 133 is placed at a level within the heights of the source regions 121a and 121b. Also, an insulating film 135 is filled in the upper portion of the upward opening trench on the upper face of the gate electrode 133, and the upper face of the insulating film 135 is planarized to be at the same level as the upper faces of the metal contacts 118 and 119.
Although not shown in the drawing, an insulating film is formed on the structure shown in FIG. 10, so as to give a transistor with a flat face. The semiconductor device (MISFET) having the trench MIS gate structure as described above can be easily fabricated. In addition, vertically extending channel regions 122c1 and 122c2 are formed in portions of the body regions 120a and 120b in the vicinity of the gate insulating film 132 on sides of the trench. The channel region 122c1 is sandwiched between the low concentration drain region 111 disposed below and the source region 121a disposed above. The channel region 122c2 is sandwiched between the low concentration drain region 111 disposed below and the source region 121b disposed above. Since the channel regions 122c1 and 122c2 vertically extend in this manner, carriers are allowed to continuously pass vertically in the downward direction, and therefore, the on resistance can be reduced.

Semiconductor device and method for fabricating the same

Matsushita Electric Industrial Co., Ltd.


This document describes systems and methods for treating and recovering water from feed solutions using a membrane module that has a plurality of hollow fiber membranes encapsulated in a collection chamber and an expansion chamber that is connected to the outlet of the membrane module.

In many countries, the discharge of industrial wastewater (e.g. from mining, oil and gas, semiconductor fabrication, electroplating, pharmaceutical, dye/textile and nuclear power production etc.) with high Total Dissolved Solids (TDS) or/Chemical Oxygen Demand (COD) into the sewer or natural water bodies is prohibited to prevent overloading of the water treatment plant or destruction to marine lives.
Reverse osmosis (RO) is one of the major technologies that have been used to treat low strength industrial wastewater, seawater, surface wastewater for reuse or drinking. However, a drawback of RO, for instance in seawater desalination, is its low recovery of water (approximately 45%) from seawater due to limitations in highly pressurized systems that are required for recovering water from solutions having high osmotic strengths. Furthermore, RO poses a challenge in the disposal of the brine or high strength industrial wastewater that remains after water has been recovered.
Therefore, brine/high strength industrial wastewater treatment systems with zero liquid discharge (ZLD) are potentially advantageous. Currently, conventional thermal separation processes such as, multi-stage evaporator and crystallizer technology have been used as a post RO process to recover more water and to separate other contaminants/salts from the wastewater. However, these thermal separation processes are highly energy demanding.
More recently, membrane distillation has been considered as a low cost, energy-saving alternative to the above thermal separation processes. In a membrane distillation system, a membrane that is permeable to vapour but impermeable to liquid water separates a heated feed water stream from a cooler product water stream. Water vapour that is evaporated from the heated feed stream passes through the membrane due to a gradient in vapour pressure and condenses in the product water stream. The advantages of the membrane distillation system are relatively low operating pressures and temperatures as compared with conventional thermal based separation process, hence decreasing energy demands.
Hence, membrane distillation is a good alternative for treating wastewater. However, the distillation membranes that are used are very sensitive to acid and organic solvents that alter the wettability of the membranes. If the membrane is wetted, the wetted membrane as used in conventional membrane distillation process will allow contaminants to pass through the membrane and contaminates the product water.
It is an objective of this invention to provide membrane based systems and methods thereof for treating water with enhanced energy efficiencies over the current thermal separation and water distillation processes. The present invention also ideally provides zero liquid discharge and could complement other water processes such as but not limited to RO to improve water recovery. The present invention is also able to separate liquids with different boiling points (e.g; alcohol:water/acetone:water/oil:water/glycol:water/etc.).

Membrane water treatment system and method thereof


The invention relates to a method of detecting a differentially expressed gene in a first sample of nucleic acids representing a first population of RNA transcripts and a second sample of nucleic acids representing a second population of RNA transcripts. The nucleic acids in the samples are labled with a member of specific binding pair, and the labeled nucleic acids in each sample are then hybridized to an excess of copies of a gene-specific sequence. The hybridized nucleic acids in each sample are further labeled by binding a second member of the specific binding pair to the first member, in which the second member has an activity to convert a chromogenic substrate into a chromogen. As a result of contacting the second member with the chromogenic substrate, the chromogenic substrate is converted into the chromogen. A difference in the amounts of chromogen produced from assaying the two samples indicate that the gene-specific sequence is differentially expressed in the samples.

Exploring regulated gene expression in complex biological systems often requires the ability to monitor expression of a large number of expressed genes in a simple, inexpensive assay. Nucleic acid hybridization on filter membranes (e.g., nitrocellulose or nylon) are familiar to most researchers practicing molecular biology, as is autoradiography, which has been the standard detection method for measuring gene expression via hybridization. True-color signals generated by chromogen-converting enzymes yield more information than just intensity, the focus of many known detection methods. Based on how the human eye works, true color can be separated into three components: hue, saturation, and brightness. Alternatively, true color can be separated into the subtractive primary colors cyan, magenta, and yellow. A slight change in any of the three components results in a difference often observable by the human eye.

Methods for detecting differentially expressed genes


This disclosure relates to an air inlet for an aircraft with an integrated hand hold. One innovative aspect of the subject matter described herein can be implemented as an air inlet on the exterior surface of a cowling for a rotorcraft, wherein the air inlet having a scoop that includes a bottom surface having a wide, flat, front edge that angles downward towards the back, an opening in the back for air to enter, and two lateral sides coupled to the bottom surface, where the two sides are planar on a top surface and become longer in height towards the opening in the back, and hand hold, where the hand hold is a trough or an indentation in the bottom surface of the scoop that extends along a side.

It is beneficial to provide structures for maintenance personnel to efficiently and safely access the upper portions of an aircraft. Some rotorcrafts include cowlings configured to act as a protective fairing around equipment, such as propulsion related components, auxiliary power units (APU) and environmental control units (ECU). A cowling may include an air intake or air inlet structure to provide an aerodynamic flow path from the exterior of the cowling to the engine inlet.

Air inlet with integrated structural hand hold


It is an object of the invention to provide a VCSEL having both a high beam quality or a low M2-factor, respectively, and a reduced mirror thickness which improves the heat dissipation due to the reduced thickness and the production cost. It is suggested to employ a Bragg-reflector in combination with a metal reflector terminating the distal side of the Bragg-reflector as seen from the laser cavity, wherein the metal reflector layer is localized at the center around the optical axis.

Vertical-cavity surface-emitting lasers (VCSELs) are attractive devices for high-power applications. Since the output power and efficiency of VCSELs in CW-operation is usually limited by thermal effects, bottom-emitting VCSELs with an emission wavelength of around 980 nm are preferred for high-power applications. They are mounted p-side down in order to have the active area close to the heat sink and to avoid high thermal resistances. Nevertheless, bottom-emitting VCSELs required quite some distributed Bragg reflectors (DBRs) on the p-side of the VCSEL in order to achieve moderate threshold currents and to avoid outcoupling losses on the wrong facet. Since the number of p-DBRs determines the thermal performance, the design of bottom-emitting VCSELs for high-power applications usually needs a difficult compromise between optical performance and thermal management.
State-of-the-art vertical-cavity surface-emitting lasers that emit to the bottom (substrate) side require approximately 30 pairs of distributed Bragg reflectors (DBRs) on the p-side of the laser diode. If these devices are intended to be used in a high-power application, they are typically mounted p-side down and the number of p-DBRs defines the thermal resistance.
In the publication "Hybrid dielectric/metal reflector for low threshold vertical-cavity surface emitting lasers", M. R. Daniel et al, Electron. Lett. 1997 Vol. 33 No. 20, pp 1704 ff, a bottom emitting VCSEL is disclosed comprising a dielectric top mirror with a metallic overcoat to reduce the mirror thickness. However, coming along with the reduced mirror thickness, not only the bandwidth increases, as disclosed in the above mentioned publication, but also the amplification of a variety of modes. This on the other hand is detrimental for the beam quality.

Vertical cavity surface emitting laser with improved mode-selectivity


A phase shifter includes a low-pass filter, a high-pass filter, and an all-pass filter coupled in series between an RF input terminal and an RF output terminal of the phase shifter, at least one of the filters being tunable, controlling the phase of an input signal over a wide range of frequencies.

There are many applications in which it is desirable to control the phase of a signal over a wide range of frequencies with nearly linear phase change with input control voltage (or current). It is also desirable to have that phase tuning sensitivity be nearly constant over the entire operating frequency range. This is useful when it is necessary to phase modulate signals over a wide range of frequencies with the goal of obtaining the same phase modulation independent of frequency for the same input stimulus. Another very desirable attribute is to have a range of phase adjustment greater than 360 degrees to be able to reach all possible phase states across the specified frequency range. In addition it is also very desirable to achieve the above described performance with relatively low and flat insertion loss.
One prior art phase shifter that attempted to address these problems is disclosed in U.S. Pat. No. 4,961,062. In this case an analog phase shifter is provided by cascading T high-pass filter and π low-pass filter sections. The high-pass filter section provide more phase shift as a function of input tuning voltage at the low end of the operating frequency range and less at the high end. The low-pass filter does the opposite providing more phase shift at the high end of the operating frequency range and less at the low end. When combined the two filters together may provide a "U-shaped" phase shift response vs. frequency with the most phase shift and highest phase tuning sensitivity occurring at the extreme low and high ends of the frequency range and the least phase shift and phase tuning sensitivity occurring in the middle of the frequency range. In the example given a variable phase shifter covering the frequency range of 6 to 18 GHz has a total phase range of ˜95° at either end of the band and ˜55° in the center.
The analog phase shifter of the '062 patent includes a T-section high-pass filter network and a π-section low-pass filter network. The low-pass π-network includes a fixed inductance element and a pair of variable capacitance elements connected in shunt, and the T-network includes a pair of variable capacitance elements connected in series and an inductive element connected in shunt. By cascade connecting the high-pass and low-pass filter sections, a composite phase shift characteristic may be obtained which forms a "U-shaped" phase shift response vs. frequency.
The user of such an analog phase shifter preferably ensures that the phase-frequency response of T-section high-pass filter is more abrupt than the π-section low-pass filter, and the overall phase shift over the bandwidth is not constant due to the "U-shaped" nature of the phase shift response vs. frequency. Also, in order to increase the total phase shift range, higher filter orders may be required for both high-pass filter and low-pass filter, which leads to an even worse phase shift variation over frequency when large overall phase shift is demanded.
The current analog phase shifters that use a low-pass filter section cascaded with a high-pass filter section suffer from certain disadvantages. Due to the "U-shape" phase-frequency response, the phase shift variation over frequency is typically large between the center of the frequency band and the high/low end of the frequency band. Also, these phase shifters also typically provide limited phase shift range at the frequency of interest, usually near the center of the frequency band.
Another prior art phase shifter that attempted to address the above problems is disclosed in U.S. Pat. No. 7,276,993. In this instance multiple all-pass networks tuned to different center frequencies are cascaded to provide a relatively flat response over a specified range of frequency.
The analog phase shifter of the '993 patent includes two or more cascaded all-pass sections with each section centered at a distinct frequency. Typically, the use of a single all-pass filter by itself would not provide a flat response over a range of frequencies, but by cascading multiple all-pass sections tuned at different center frequencies, the cumulative phase shift response curves results in a composite frequency-phase response that may provide a relatively flat phase over a specified range of frequencies.
There are also drawbacks from cascading multiple all-pass sections centered at different frequencies. Typically, these filters have degraded overall input/output return loss due to the narrowband nature of each single all-pass section. Two or more all-pass sections at the same (or similar) center frequency may be required to provide a necessary overall phase shift range due to the limited phase shift range for the single all-pass section. This may degrade the insertion loss by a factor of two or more.
Another method previously employed is to use a reflection-type phase shifter, as disclosed for example in U.S. Pat. Nos. 4,638,269 and 5,119,050. In such analog phase shifters, a pair of varactor diodes is serially connected to each of the phase shifting ports of a 3 dB hybrid coupler. However, the bandwidth of such type of analog phase shifter is limited and the insertion loss is generally high due to the limited bandwidth and the extra loss introduced by the 3 dB coupler.


Thin film spatial filters are disclosed. The filters are constructed with a continuous thin film of low resistance conductor (for example with a resistance of from 10.sup.-2 to 10.sup.8 Ohms-cm) with plurabilty of resistive elements defining pixels. A thin film of high resistance material is on other side of the pixels in the case of grounded filters. The conductor film provides lateral blurring for image processing.

Spatial frequency filtering is essential to a variety of image processing applications. Spatial frequency filtering is currently being used for image enhancement in medical imagery, such as in Positron Emission Tomography (PET) and Magnetic Resonance Imaging (MRI), as an aid to detection of cancerous regions. In military applications, spatial frequency filtering is useful in the arena of target detection. In this case, bandpass filtering can be used to isolate features of a given dimension from an image, thus facilitating greatly the target detection algorithms.
Two of the existing methods for achieving spatial frequency filtering of images are computer software and analog discrete circuit implementations; both have significant drawbacks.
For the digital software approach, even a simple algorithm which produces "blurring" (low pass spatial frequency filtering) of an image can take up to several minutes to calculate, and is strongly dependent on the resolution of the image. For example, for a standard 1024.times.1024 grayscale image, a Gaussian blur of 20 pixels would take approximately 30 seconds using a standard Pentium computer; for higher resolution images with full color capability, this operation would take much longer. The power consumption for these systems is relatively high, with a standard desktop computer consuming in excess of 75 Watts.
Spatial frequency filtering has also been implemented [C. M. Mead, Analog VLSI and Neural Systems, 1989] in the analog domain using digital circuits comprising discrete circuits comprising field effect transistors (FETs). This method was shown to be effective for achieving local contrast control (high pass spatial frequency filtering). However, the discrete circuit approach has two fundamental drawbacks.
First, the lateral conductance between pixels is emulated by a complicated multiple FET circuit, which requires a large unit cell area ("real estate") for each pixel; typically dimensions of nearly 100 .mu.m.times.100 .mu.m are required. Because there is such a large real estate demand for this implementation, large format arrays (e.g. 1024.times.1024) cannot be fabricated, since the resultant array would have dimensions of 10 cm.times.10 cm. Current semiconductor processing techniques are not compatible with devices larger than 2 cm.
Second, like the computational algorithmic approaches to spatial frequency filtering, the discrete FET implementation also has a slow time response (.sup..about. 100 msec), in addition to large power requirements (>20W for a 1024.times.1024), both of which are incompatible with real time remote sensing applications which require sub-millisecond response with sub-Watt power consumption.


Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the 3D memory device includes a peripheral circuitry formed on a first substrate. The peripheral circuitry includes a plurality of peripheral devices on a first side of the first substrate, a first interconnect layer, and a deep-trench-isolation on a second side of the first substrate, wherein the first and second sides are opposite sides of the first substrate and the deep-trench-isolation is configured to provide electrical isolation between at least two neighboring peripheral devices. The 3D memory device also includes a memory array formed on a second substrate. The memory array includes at least one memory cell and a second interconnect layer, wherein the second interconnect layer of the memory array is bonded with the first interconnect layer of the peripheral circuitry, and the peripheral devices are electrically connected with the memory cells.

As memory devices are shrinking to smaller die size to reduce manufacturing cost and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. A three-dimensional (3D) memory architecture can address the density and performance limitation in planar memory cells.
In a 3D memory, some peripheral circuits, such as bit-line drivers of a page buffer, use high voltage to support storage functions, for example, erasing and programing the memory cells. However as the dimensions of a 3D memory become smaller and smaller, isolation between the peripheral devices, for example bit-line drivers, becomes complicated. A need exists for an isolation that can provide the desired properties (e.g., low leakage current and high breakdown voltage) for a 3D memory to achieve high density and high performance.

Structure and method for isolation of bit-line drivers for a three-dimensional NAND


A power supply system for a long-stator drive having at least two independent tracks, which each have at least one long-stator section and which can be connected to one another using at least one track-changing device, the long-stator sections being split into a plurality of drive regions, using which each vehicle can be independently driven, and at least one track-changing device having at least one electrical contact which is positively guided by the track-changing device in such a manner that an electrical connection can be produced or eliminated between various long-stator sections.

A conventional power supply system is described, for example, in German Patent No. 28 05 994. The conventional power supply system has two mutually independent tracks, each having a long-stator winding. The winding sections of each track can be connected to the substations via two parallel power cables and switching devices. The switching devices include non-contacting semiconductor switches and contacting switching elements. The contacting switching element is closed by the corresponding semiconductor switch before the voltage is connected, while in contrast the contacting switching element is opened by the semiconductor switch after the voltage has been disconnected.
Furthermore, "Energieversorgund des Langstatorantriebs" Supplying Power to a Long-Stator Drive), J. Meins, "etz", Vol. 108, No. 9, 1987, pp. 378-81 describes a conventional power supply system for a long-stator drive. This power supply system includes a track having a left and a right motor side. A plurality of long-stator sections are combined to form at least one drive region. Each drive region is characterized in that all its stator sections are supplied with power by the same converter. The limits for the drive regions are generally chosen such that these limits are at the preselected interval between trains, so that a plurality of vehicles may travel at the same time interval on the single track.
In addition, for a track having a long stator, a track-changing device, designed as a switch, is described in "Stand der Entwicklung des elektromagnetischen Schnellbahnsystems" (Development Status of the Electromagnetic High-Speed Railway System), Von Rudolf Zurek, ZEV-Glas. Ann., Vol. 104, Nos. 8-9, August-September 1980, pp. 233-40. The relevant switching section ends at the moving end of the switch.
In addition, French Patent No. 2,688,523 describes a track-changing device for two independent tracks of a long-stator drive. The track-changing device is designed as a switch and the two independent tracks each have at least one long-stator segment.
Finally, German Patent No. 25 44 665 describes a mechanically regulatable switch for a magnetic overhead railway. The switch includes a movable tongue, on which a stator winding of a linear motor and secondary conductor loops, situated beneath, are arranged.

Power supply for a longitudinal stator drive


Dosage equipment, which includes a peristaltic pump for the dosage of liquid. The set of hoses (17) of the peristaltic pump includes an upper piece (18) and a lower piece (19). The body of the pump includes an attaching piece (13), to which the upper piece and the lower piece can be attached.

Peristaltic pumps have been used commonly for transfer of liquids in applications in which the requirements of accuracy of the dose quantities are not so high.
The use of a peristaltic pump in precise dosage apparatuses has been made difficult by factors related, e.g., to the elasticity properties of the hoses and to the rotor speed and acceleration, which cause differences between the doses, in particular if the pump stands periods of different lengths between the times of use.


The semiconductor device manufacturing method comprises the step of transferring patterns formed on a reticle to a semiconductor substrate by an exposure with oblique incidence illumination. In the step of making the exposure with oblique incidence illumination, the exposure is made with an aperture stop 16 including a first ring-shaped aperture 22, and a plurality of second apertures 24a1-24a4 formed around the first ring-shaped aperture 22. The exposure is made with an aperture stop 16 having the first ring-shaped aperture 22 which can transfer patterns arranged at a medium pitch to a relatively large pitch with a relatively high resolution and the second aperture 24a1-24a4 which can transfer patterns arranged at a relatively small pitch with a relatively high resolution, whereby even when the patterns are arranged at various pitch values, the DOF can be surely sufficient, and the patterns can be stably transferred.

The present invention relates to a semiconductor device manufacturing method, more specifically, a semiconductor device manufacturing method using oblique incidence illumination.
Semiconductor devices have been continuously required to be micronized, and recently, patterns of a line width shorter than a wavelength of the exposure light source used in the manufacturing process of a semiconductor device are required to be formed.
Accompanying this, recently various illumination techniques for improving the resolution for transferring patterns are proposed. As such illumination technique, oblique incidence illumination (off-axis illumination), for example, is proposed. The oblique incidence illumination is largely divided in modified illumination and annular illumination. As major types of the modified illumination, e.g., two-point illumination (double polar illumination), wherein two apertures are formed in the aperture stop of the illumination system, is known, and four-point illumination (quadrupole illumination), wherein four apertures are formed in the aperture stop of the illumination system, is known. On the other hand, in the annular illumination, an annular aperture is provided in the aperture stop of the illumination system. The size of the aperture of the annular illumination is expressed by the outer sigma (σout), the inner sigma (σin) or others. FIG. 18 is a plan view of the conventional aperture stop of the annular illumination. In FIG. 18, the outer border indicates the border of the effective region of the aperture stop. As illustrated in FIG. 18, a ring-shaped aperture 122 is formed in the annular illumination stop. FIG. 19 is a graph of the relationship between the pitch of patterns and the depth of focus (DOF). In FIG. 19, the pitch of patterns is taken on the horizontal axis, and on the vertical axis, the DOF is taken. In FIG. 19, the DOF is the value with the exposure latitude is 4%.
In FIG. 19, the ● marks indicate the DOF given when the conventional annular illumination stop 116 illustrated in FIG. 18 is used in the illumination system. As indicated by the ● marks in FIG. 19, when the exposure is made with the conventional annular illumination stop, the DOF cannot be always sufficiently large in the range where the pitch of the patterns is about 300 nm or over.
FIG. 20A is a plan view of the layout of the mask pattern for forming holes. In FIG. 20A, on the left side of the drawing, patterns 118a for forming holes are formed on the reticle with high density. On the other hand, on the right side of the drawing of FIG. 20A, an isolated pattern 118b for forming a hole is formed on the reticle.
FIG. 20B is a graph of critical dimension-focus (CD-FOCUS) curves (Part 1). In FIG. 20B, the □ marks indicate the CD-FOCUS curve of the case of the left side of the drawing of FIG. 20A, i.e., the patterns 118a for forming holes are formed relatively densely. In FIG. 20B, the ◯ marks indicate the case of the right side of the drawing of FIG. 20A, i.e., the pattern 118b for forming a hole is formed isolated. Such CD-FOCUS curves show what influences changes of the DOF give on the resist size. In FIG. 20B, the shift of the focus in exposing the patterns is taken on the horizontal axis. On the vertical axis, the size of the patterns transferred on a resist is taken, and relative pattern sizes to the maximum size of the patterns which is set at 100 are plotted. The inclination of an upward parabola being relatively blunt means that the DOF is relatively wide, and the focus margin is relatively large. On the other hand, the inclination of an upward parabola being relatively acute means that the DOF is relatively narrow, and the focus margin is relatively small. The focus value at the summit of a parabola is called a best focus, and generally the resist size is largest at the best focus. Generally, in comparing the DOF, the focus range where the resist size is 90% or above of the resist size at the best focus is used as the effective DOF.
In FIG. 20B, as indicated by the ◯ marks, when the pattern 118b for forming a hole is isolated, the focus margin is considerably small.
As a technique of making the focus margin larger, it is proposed to use the exposure technique using together the annular illumination stop and the sub-resolution assist feature (SRAF) technique.
FIG. 21A is a plan view of the mask pattern having assist patterns for increasing the DOF. FIG. 21B a graph of CD-FOCUS curves (Part 2). As illustrated in FIG. 21A, the patterns 121 for increasing the DOF are formed around a pattern for forming a hole.
The □ marks in FIG. 21B are the same as the □ marks in FIG. 20B, i.e., the left side of the drawing of FIG. 20A, i.e., the case that the patterns 118a for forming holes are formed with relative high density. In FIG. 21B, the ◯ marks are the same as the ◯ marks in FIG. 20B, i.e., the right side of the drawing of FIG. 20A, i.e., the case that the pattern 118b for forming a hole is formed isolated. In FIG. 21B, the Δ marks indicate the case of FIG. 21A, i.e., the case that the assist patterns 121 are formed around the pattern 118c for forming a hole.
As seen in FIG. 21B, the assist patterns 121 are suitably provided (see FIG. 21A), whereby the focus margin can be increased in comparison with the case that the pattern for forming a hole is isolated (see FIG. 20A).
In FIG. 19, the ◯ marks indicate the graph of the case that the assist patterns are suitably formed on the reticle over the region where the patterns are dense to the region where the patterns are rare. As indicated by the ◯ marks in FIG. 19, the use of the SRAF technique could somewhat increase the DOF.
Following references disclose the background art of the present invention.    [Patent Reference 1]    Specification of Japanese Patent Application Unexamined Publication No. 2002-122976    [Patent Reference 2]    Specification of Japanese Patent Application Unexamined Publication No. 2003-234285
However, as indicated by the ◯ marks in FIG. 19, even the combined use of the oblique incidence illumination technique and the SRAF technique cannot always give sufficiently large DOF in the range of, e.g., about 300 nm-600 nm pattern pitch. Then, a technique which can transfer with a high resolution all patterns which are formed on a reticle at various pitches is expected.

Semiconductor device manufacturing method


In a communications system, such as a Power-Over-Ethernet system, where power supply equipment (PSE) supplies power to powered requiring devices (PRDs), a system and method of dynamic power management is implemented. The system and method monitors the power consumed at each port by the PRDs. Based on this monitoring, the PSE dynamically determines the minimum power which can be allocated to each PRD, and so dynamically maximizes the available reserve power. The PSE maintains a queue or queues wherein PRDs are listed in order of a power allocation priority. When additional power is available, the PSE preferentially allocates power to a PRD or PRDs which have higher priority. The system and method of the present invention minimizes the power allocated to each individual network device, as a result of which the total number of network devices that can be supported with the available power may be maximized.

1. Field of the Invention
The present invention pertains to the field of providing power from power source equipment (PSE) to one or more devices which are part of a communications system or communications network, and to managing the power which is supplied to the networked devices.
2. Background Art
Network devices which require power are conventionally referred to in the art as "powered devices", or "PDs" for short. In this document, for reasons explained further below, such devices will be referred to as "power requiring devices", or "PRDs", wherein the terms "power requiring device", "PRD", and the plurals thereof are entirely synonymous with the terms "powered device", "PD", and the plurals thereof, as conventionally employed in the art.
Conventionally, in a communications system, such as a network environment where cabling is employed to provide power to PRDs, at least two separate cables are connected to each PRD. One PRD cable conveys data to and from the (data communications equipment (DCE), while a second cable supplies each PRD with power from a power supply which is typically separate from the DCE. The disadvantages of this approach have long been obvious. Using two cables increases the physical bulk of cabling which must be wired through the physical environment, demanding more space and making it more difficult to track which cables are serving which functions. If power is supplied to a PRD via a local power outlet, for example, a standard wall outlet, then it may be necessary to locate a separate uninterruptible power supply (UPS) near many or all of the PRDs. As a result, multiple UPS may be required. Some PRDs have required transformers co-located with the PRD, further increasing bulk and complicating deployment efforts. Overall, dual cable solutions typically cost more than a single cable solution and tend to be unwieldy to deploy and maintain.
In addition, a key limitation of dual cable solutions is that they inherently tend to exclude the transmission of data which is related to the power consumption of a PRD. For example, if a PRD is plugged directly into a wall socket, or connected to a wall socket via a dedicated UPS or transformer, there typically does not exist any means to monitor the power delivered to the PRD, nor to regulate the power delivered to the PRD. In turn, this makes it difficult to monitor and control overall network power consumption.
A single cable solution, wherein the single cable carries both data and power, has long been known in certain fields. For example, the cabling employed by the plain old telephone system (POTS) network carries both power and data. Other technologies, such as USB communications systems and IEEE 1392 ("Firewire") systems, typically are capable of supporting both data and power transmission on a single cable. The advantages of single cable solutions are obvious: Lower cost, half as many wires to be tracked and untangled, and, if all the cables extend from a single DCE, then a single UPS can provide power support to all the network devices via the DCE. Furthermore, single cable solutions are inherently more friendly to technology which monitors and regulates power consumption by the PRDs, since the power cable is already designed to support data transmission as well.
A problem has existed, however, in adapting certain widely used legacy technologies to take advantage of single cable power and data solutions. In particular, Ethernet communications systems, which are widely deployed for wired computer networks worldwide, have long relied on one cable (the Ethernet cable) to carry data to PRDs and another separate cable to supply power to the PRDs, with all the disadvantages already noted above.
Recently a solution has emerged to enable Ethernet networks to take advantage of single cable data and power solutions. Specifically, the IEEE 802.3af protocol defines standards wherein power can be carried to PRDs from a DCE, such as an Ethernet switch, over the same industry-standard Ethernet cabling and Ethernet connectors (i.e., the RJ-45 plug and jack) that formerly was used to carry only data. As a result, where it was formerly necessary to employ a separate source of power to deliver power to PRDs, the power source equipment (PSE) can now be integrated into the DCE itself. Newly designed PRDs, such as wireless access points (WAPs) for 802.11 and Bluetooth devices, web cameras, IP telephones, security access devices, point-of-service (POS) terminals, and similar technologies are designed to accept power directly over the Ethernet cabling, dramatically simplifying deployment of network devices.
The IEEE 802.3af standard is also referred to as the "Power Over Ethernet" standard, or "PoE", and the terms "802.3af" and "PoE" are used interchangeably in this document, along with such terms as "802.3af-compliant", "PoE-compliant", and related terminology.
An advantage of PoE is that a PoE-compliant PSE, or PoE PSE for short, can detect the presence of legacy Ethernet devices which are not designed to accept power over the Ethernet cable, and so not deliver power to such devices. This makes it possible to support both PoE-compliant PRDs and legacy PRDs in the same network. Additionally, legacy Ethernet switches, which are not PoE-compliant, can be used with the newer PoE-compliant PRDs. This is done by inserting, between the legacy Ethernet switch and the PRDs, a so-called "mid-span" PSE, also referred to as a PoE mid-span hub. The PoE mid-span hub accepts the Ethernet cabling from the Ethernet switch, and loads the power onto Ethernet cables which extend from the PoE hub to the PRDs. When data is received from the PRDs, the mid-span PoE hub passes the signals on to the Ethernet switch.
A further advantage of the IEEE 802.3af standard is that PoE-compliant PRDs can have an embedded management information base (MIB), which contains data on the power requirements of the device as determined by the device manufacturer. Specifically, 802.3af-compliant PRDs can be classified at power levels designated as '1', '2', or '3', which respectively indicate increasing power requirements. (A default '0' value encompasses all three power levels. A fifth designation, '4', is currently reserved for future use.) The PoE PSE can read the power classification from a PoE PRD via the Ethernet connection. This enables the PoE PSE to allocate only the designated amount of power to a PRD, which conserves power for other attached devices and contributes to the general goal of efficient power utilization. Yet another advantage of combining data signaling and power delivery over a single cable is that PRDs can be shut down remotely, via control signals sent from the DCE, without the need for a power switch or reset button.
In summary, PoE technology, and similar protocols which may be employed in the context of other kinds of communications links such as USB and Firewire, enable power to be carried over the same cable that is used for data transmission. These technologies further enable intelligent management by DCEs of the power consumption by PRDs.
In spite of the improvements in network power allocation and power management that have come with 802.3af and similar protocols, shortcomings remain. One problem is that, in real-world operation, PRDs often use significantly less power than the maximum power they might request. For example, an 802.3af-compliant PRD might classify itself in Class 2, meaning that the DCE should be able to deliver 7.0 watts to the port to which the PRD is connected, and therefore that at least 7.0 watts should be held in reserve by the DCE to support the Class 2 PRD. However, in actual use, the PRD might never use anywhere near this much power, or possibly the PRD might draw near the maximum power at infrequent intervals, while using dramatically less power most of the time. This might be the case, for example, with a wireless access point that has a light load of wireless devices associated with it.
In addition, it is not always a requirement of the standards that a device provide any power classification. For example, PoE devices are not required to provide a power classification. As a result, when a PoE-compliant PRD is connected to the DCE, and the PRD does not report any power classification, by default the DCE may allocate or reserve the maximum allowed power under the 802.3af protocol, namely 15.4 watts, to the port to which the PRD is connected. This will be the case even if the PRD never actually consumes anywhere near 15.4 watts.
As a result of these factors, the actual power allocated to PRDs, or held in reserve by the DCE to support the PRDs, may be well in excess of the amount of power that these devices actually require to support their operation. If many devices are connected to the DCE, a further result may be that insufficient power is available to power all the devices, leaving some devices effectively non-operational. It is desirable, then, that a means be found to ensure that the minimum possible power is allocated to each PRD, while still ensuring full functionality of each PRD. In turn, this will ensure that the number of PRDs which may actually be allocated power tends to be maximized, while still minimizing overall power consumption.
A further short-coming of existing power technologies is that they provide no way to prioritize attached network devices. That is to say, if insufficient power is available to support the operations of all PRDs attached to the DCE, it may be desirable that some specific PRDs have a higher priority for power allocation than other PRDs. The exact choice of which PRDs should have higher priority will naturally depend on many factors specific to the nature of the network, the usage being made of the network devices, and the specific requirements of a company or other enterprise implementing the network.
Therefore, it is desirable that means be provided so that network engineers can indicate a priority among network devices, such that if insufficient power is available to power all PRDs connected to the DCE, then those PRDs assigned the highest priority are preferentially allocated power ahead of lower priority PRDs whenever possible. It is further desirable that network engineers be provided the maximum possible flexibility in determining the criteria which are used to assign power allocation priority levels to PRDs.
A further shortcoming of present technologies is that, in the event of a sudden decrease in available power, no method is provided to deallocate power from the PRDs. It is desirable that, in the event of an unexpected decrease in available power, a means exist to deallocate power from some of the PRDs, preferably in an order which reflects some kind of priority among the attached PRDs, where that priority may or may not be the same priority used to assign power to the PRDs to begin with.
Given the foregoing, what is needed is a system and method of improved, dynamic power management and allocation for power requiring devices which are part of a communications system or communications network.
In particular, what is needed is a system and method of dynamic power management and allocation for determining the actual power consumption of power requiring devices which are part of the communications system, and adjusting the power allocation so that the minimum necessary power is allocated to power requiring devices which are part of the communications system. What is further needed is a system and method of dynamic power management and allocation for determining a priority among power requiring devices which are part of the communications system, and for ensuring that whenever possible power requiring devices of a higher prior are preferentially allocated power ahead of power requiring devices of a lower priority.

Power management of PoE devices based on powered queue and unpowered queue of time order connection priority while maintaining reserve power


First electrodes disposed on the surface of the substrate comprise a plurality of chip select electrodes, and the first chip select electrode among a plurality of chip select electrodes to in electrically connected only to a semiconductor element. The N-th (N is a integer of 2 or more) chip select electrode is electrically connected only to the second electrode disposed on the back at position corresponding to the (Nxe2x88x921)-th chip select electrode, and the plurality of chip select electrodes are sporadically disposed in the first electrodes.

1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device comprising semiconductor elements packaged on an interposer.
2. Description of the Background Art
Heretofore, in order to reduce the packaging area of semiconductor devices on a circuit substrate, there have been disclosed techniques for laminating a plurality of semiconductor devices comprising semiconductor elements (chips), such as memories, disposed on the substrate called an interposer and for packaging the laminated semiconductor devices on a circuit substrate (e.g., Japanese Patent Laid-Open No. 11-135711).
A conventional semiconductor device will be briefly described below referring to FIGS. 6 to 8. FIG. 6 is a schematic sectional view of a conventional semiconductor device, and FIG. 7 is a schematic plan thereof. Specifically, FIG. 6 shows the cross-section along the line X-X in FIG. 7. Furthermore, FIG. 8 is a schematic sectional view of a conventional semiconductor device module manufactured by laminating semiconductor devices of FIG. 6.
In FIGS. 6 to 8, the reference numeral 1 denotes a chip (semiconductor element) cut from a wafer; 2, and 2A to 2C denote an interposer (substrate) made of materials such as glass-epoxy base and copper foil; 2a denotes the back of the interposer 2; 2b denotes the top surface of the interposer 2; 3 denotes common electrodes for transmitting common signals to the chip 1; 3a denotes a first chip select electrode (chip select electrode No. 1); 3b denotes a second chip select electrode (chip select electrode No. 2); 3c denotes a third chip select electrode (chip select electrode No. 3). The reference numeral 4 denotes second electrodes for the common electrodes disposed on the location of the back 2a corresponding to the common electrodes 3; 4a denotes a second electrode for the first chip select electrode disposed on the location of the back 2a corresponding to the first chip select electrode 3a; 4b denotes a second electrode for the second chip select electrode disposed on the location of the back 2a corresponding to the second chip select electrode 3b; 4c denotes a second electrode for the third chip select electrode disposed on the location of the back 2a corresponding to the third chip select electrode 3c; 5 denotes thin metal wires for electrically connecting the chip 1 to the first electrode group; 6 denotes a first wiring for chip selecting; 7 denotes wirings for the common electrode; 7a denotes a second wiring for chip selecting; 7b denotes a third wiring for chip selecting; and 8 denotes an encapsulating resin for protecting the chip 1 and metal wires 5, and fixing the chip 1 to the interposer 2.
As FIGS. 6 and 7 show, a chip 1 is disposed on substantially the central portion of the surface 2b of an interposer 2. A first electrode group is linearly disposed on the both sides of the chip 1 so as to sandwich the chip 1. The first electrode group comprises a plurality of common electrodes 3 and a plurality of chip select electrodes 3a to 3c, and these are solder-ball terminals disposed so as to protrude from the surface 2b of an interposer 2. The a plurality of chip select electrodes 3a to 3c are disposed on the end region of the first electrode group so as to be adjacent to each other.
Also, as FIG. 6 shows, a second electrode group is disposed on the back 2a of the interposer 2 on the location corresponding to the first electrode group on the surface 2b. The second electrode group comprises a plurality of second electrodes 4 for common electrodes and a plurality of second electrodes 4a to 4c for chip select electrodes, and these are land patterns formed by, for example, photoengraving. The second electrodes 4 for common electrodes on the back 2a are disposed on the locations plane-symmetrical to the common electrodes 3 on the surface 2b, and the second electrodes 4a to 4c for chip select electrodes on the back 2a are disposed on the locations plane-symmetrical to the chip select electrodes 3a to 3c on the surface 2b.
Also, as FIG. 6 shows, the first chip select electrode 3a is electrically connected to the predetermined electrode pad on the chip 1 through a thin metal wire 5 and a first wiring for chip selecting 6. The second chip select electrode 3b is electrically connected to the second electrode 4a for the first chip select electrode disposed on the back 2a side of the first chip select electrode 3a through a second wiring for chip selecting 7a. Furthermore, the third chip select electrode 3c is electrically connected to the second electrode 4b for the second chip select electrode disposed on the back 2a side of the second chip select electrode 3b through a third wiring for chip selecting 7b.
On the other hand, the common electrodes 3 are connected to the chip 1 through the thin metal wires and wirings, and also connected to the second electrodes 4 for common electrodes on the back 2a through the wirings 7 for common electrodes.
The wirings 7 for common electrodes, the second wiring for chip selecting 7a, and the third wiring for chip selecting 7b are adopted to connect the first electrodes on the surface 2b with the second electrodes on the back 2a through through-holes formed in the interposer 2.
The semiconductor devices thus constituted are laminated, as shown in FIG. 8, to form a semiconductor device module. Specifically, the first electrode group formed on the surface 2b of the interposer 2B in the second-level semiconductor device is stacked on the second electrode group formed on the back 2a of the interposer 2A in the first-level semiconductor device. Furthermore, the first electrode group formed on the surface 2b of the interposer 2C in the third-level semiconductor device is stacked on the second electrode group formed on the back 2a of the interposer 2B in the second-level semiconductor device.
The semiconductor device module thus formed is packaged on a circuit substrate (not shown) such as a motherboard. Specifically, the first electrode group in the first-level semiconductor device is stacked on the predetermined electrodes formed on the circuit substrate.
Then, common signals, such as ground signals, address signals, and data signals, are transmitted from the circuit substrate to chips 1A, 1B, and 1C of the first, second and third levels, respectively.
On the other hand, the chip select signals transmitted from the circuit substrate for selecting predetermined chips 1A to 1C are transmitted to predetermined chips 1A to 1C through predetermined chip select electrodes 3a to 3c.
Specifically, the first chip select signal for selecting the chip 1A of the first-level semiconductor device transmitted from the circuit substrate is transmitted to the chip 1A of the first-level semiconductor device through the first chip select electrode 3a, the first wiring 6 for chip selecting, and a thin metal wire 5 in the first-level interposer 2A.
The second chip select signal for selecting the chip 1B of the second level transmitted from the circuit substrate is transmitted to the chip 1B of the second level through the second chip select electrode 3b, the second wiring for chip selecting 7a, and the second electrode 4a for the first chip select electrode in the first-level interposer 2A; and further through the first chip select electrode 3a, the first wiring 6, and a thin metal wire 5 in the second-level interposer 2B.
The third chip select signal for selecting the chip 1C of the third level transmitted from the circuit substrate is transmitted to the chip 1C of the third level through the third chip select electrode 3c, the third wiring for chip selecting 7b, and the second electrode 4b for the second chip select electrode in the first-level interposer 2A; through the second chip select electrode 3b, the second wiring for chip selecting 7a, and the second electrode 4a for the first chip select electrode in the second-level interposer 2B; and further through the first chip select electrode 3a, the first wiring 6, and a thin metal wire 5 in the third-level interposer 2C.
In a conventional semiconductor device, as described above, the packaging area of the semiconductor device on a circuit substrate is reduced by packaging a semiconductor device module of a laminated structure on the circuit substrate. Since an interposer is used in common to laminated semiconductor devices, the productivity of the semiconductor device module is raised, and the manufacturing costs are reduced.
In the above-described semiconductor device, however, since a plurality of chip select electrodes are arranged in columns always on limited locations in the first electrode group, i.e., on the locations adjacent to each other, there has been a problem that the locations of the electrodes on the circuit substrate corresponding to these electrodes are also limited. In other words, on the circuit design of a circuit substrate, there has been a layout problem that the electrodes that contact the chip select electrodes must be disposed in column so as to be adjacent to each other.
The present invention has been conceived to solve the previously-mentioned problems. An object of the present invention is to provide a semiconductor device having a reduced semiconductor-device packaging area on a circuit substrate, using a common substrate of the laminated semiconductor devices, and having a high freedom of circuit design.
The above object of the present invention is attained by a following semiconductor device.
According to an aspect of the present invention, the semiconductor device comprises a semiconductor element disposed on the surface of a substrate. A first electrodes disposed on the surface of the substrate. A second electrodes disposed on the back of the substrate at positions corresponding to the first electrodes. The first electrodes have a plurality of chip select electrodes. The first chip select electrode of the plurality of chip select electrodes is electrically connected only to the semiconductor element. The N-th (N is a integer of 2 or more) chip select electrode of the plurality of chip select electrodes is electrically connected only to the second electrode disposed on the back on the location corresponding to the (Nxe2x88x921)-th chip select electrode. The plurality of chip select electrodes is sporadically disposed in the first electrodes.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.

Semiconductor device having semiconductor element packaged on interposer


A computer-controlled robot cutting system for making angled or beveled cuts along a preselected path in a workpiece having a generally planar cutting surface. A cutting knife, such as a high-intensity fluid jet, is pivotably mounted in a support frame having two pairs of arcuate guides disposed at right angles to each other for motor-driven rotation of the cutting knife about orthogonal axes. The centers of curvature of both guides lie on a critical plane containing a pivot point about which the cutting knife pivots. An opposing workpiece gantry with horizontal and vertical slides for motor-driven translation of the workpiece along two axes also includes means for holding the workpiece such that its surface to be cut faces the cutting knife and lies in the critical plane. The workpiece is thus translated to define the cutting path on the obverse surface, while the cutting knife is pivoted to define the entry angle of the cut along the cutting path. Four motion controllers under computer control coordinate the motors driving each axis of rotation or translation. Because the obverse cutting surface of the workpiece is maintained in the critical plane containing the pivot point, pivoting of the knife does not change its entry point in the cutting surface, thereby simplifying motion control algorithms. Furthermore, because the cutting knife is pivoted and the workpiece is translated, the relatively massive gearing and movable frame structures are distributed between the cutting knife section and the workpiece gantry, lowering the inertia and enabling the use of lighter-duty motors.

Cutting tools that operate by directing a high-intensity energy source such as a high-speed fluid stream along a cutting path in a workpiece are used in many industrial applications to cut various patterns. In simple cutting tools of this kind, the fluid stream is emitted from a stationary nozzle and the workpiece translated to produce the desired cutting path. A similar effect can be achieved by maintaining the workpiece in position and translating the nozzle. Often, it is necessary to make a beveled or angled cut in a workpiece. To produce a beveled cut, the nozzle must be pivoted with respect to the workpiece to change the angle of entry of the fluid jet as it advances along the cutting path. Coordination of translation and pivotal rotation is essential to fast, accurate cutting.
In the field of tuna fish processing, for example, the completely or partly automated cutting of frozen slabs of tuna to remove blood meat and skin portions from edible loin meat portions is described in three U.S. Pat. Nos. (3,800,363; 4,738,004; and Re. 33,917) to James M. Lapeyre and assigned to the assignee of this application. Besides discussing the cutting of tuna slabs along irregular paths, the patents also describe scanners for producing images of one or both sides of the slabs from which control signals are generated to control the cutting apparatus. The two older patents (U.S. Pat. Nos. 3,800,363 and 4,738,004) discuss general methods of visioning and cutting tuna slabs with few details of the conversion of the electrical signals representing the cutting path as determined by the video scan into control signals for the cutting apparatus. Reissued patent Re. 33,917 shows a water jet robot relatively movable with respect to the stationary slab to be cut. None of the patents addresses the problem of achieving fast and accurate cutting paths.
The water jet nozzle on the water jet robot shown in Re. 33,917 is at the end of a sequence of pivot joints having long and massive connecting arms that are unwieldy and slow, exhibiting a lot of inertia, which is detrimental to the rapid direction changes needed for cutting irregular paths and to the overall fast throughput required on a production line. Furthermore, more energy is consumed in powering the motors driving the heavy arms of the robot.
Another shortcoming of the Re. 33,917 robot, which is a standard commercial robot used in many manufacturing fields besides tuna processing and water-jet cutting, is that the pivotal motion provides translation as well as rotation of the water jet with respect to the workpiece. As such, the pivoting of one joint can cause a translation that must be compensated for by pivoting other joints. Consequently, a complex control algorithm is required to coordinate the rotation and translation of the nozzle with respect to the workpiece.
Thus, an object of the present invention is to provide a cutting system capable of rapidly producing beveled cuts in a workpiece in an energy-efficient manner suitable for production-line applications.


The present disclosure provides a receiving device including, a receiver configured to receive a signal that is transmitted via a propagation path and is modulated by a predetermined system prescribed by a predetermined standard, a demodulator configured to demodulate a received signal, an estimator configured to estimate a signal-to-noise ratio relating to the propagation path, obtained from a data signal included in the demodulated received signal, and a corrector configured to correct an estimated signal-to-noise ratio in accordance with a transmission parameter obtained from the received signal.

The present disclosure relates to receiving devices and methods, demodulating devices and methods, and programs, and particularly to receiving device and method, demodulating device and method, and program that enable enhancement in the accuracy of estimation of the SNR (Signal-to-Noise Ratio) relating to a propagation path.
As shown in FIG. 1, a digital terrestrial broadcast signal transmitted from a transmitting device 2 of a broadcast station or the like is received by a receiving device 1 via a propagation path 3. In the digital terrestrial broadcasting and so forth, e.g. OFDM (Orthogonal Frequency Division Multiplexing) is employed as the digital modulation system for data (signal).
The propagation path 3 gives the influence of noise and so forth to the signal transmitted from the transmitting device 2. In general, the influence given to the signal by the propagation path 3 is represented by the SNR.
In the receiving device 1, the path SNR of the propagation path 3, obtained from the signal transmitted from the transmitting device 2 via the propagation path 3, is estimated. Hereinafter, the estimated path SNR will be referred to as the estimated SNR.
FIG. 2 is a diagram showing the relationship between the ideal path SNR and the estimated SNR.
In FIG. 2, the estimated SNR represented by the axis along the vertical direction in the diagram is indicated by the dashed line, and the path SNR represented by the axis along the horizontal direction in the diagram is indicated by the solid line. As shown in FIG. 2, as the relationship between the estimated SNR (dashed line) and the path SNR (solid line), the value of the estimated SNR is closer to the value of the path SNR when the value of the SNR is larger. In contrast, the value of the estimated SNR is divergent from the value of the path SNR at a higher degree when the value of the SNR is lower.
The reason for the occurrence of such divergence will be described with reference to FIGS. 3A and 3B.
In the case of obtaining the estimated SNR from an unknown data signal included in a signal transmitted via the propagation path 3, generally the result of a hard decision for the constellation of the data signal is utilized. Specifically, when the path SNR is not low, the transmission point corresponds with the estimated transmission point in the constellation in the IQ plane as shown in pattern A of FIG. 3A, so that the ideal estimated SNR is obtained. In this case, the correct estimated SNR is obtained based on S and N indicated by the solid lines.
In contrast, as shown in pattern B of FIG. 3B, when the path SNR is low, the result of a hard decision is mistaken for an adjacent symbol and the transmission point does not correspond with the estimated transmission point. As a result, an erroneous estimated SNR is obtained. In this case, although the correct estimated SNR is obtained based on S and N indicated by the dashed lines, actually the erroneous estimated SNR is obtained by S′ and N′ indicated by the solid lines.
As a method for calculating the SNR, there has been disclosed an OFDM demodulating device that calculates the SNR based on a complex correlation signal obtained by complex correlation calculation of a baseband signal (refer to e.g. Japanese Patent Laid-open No. 2007-208748).

Receiving device and method, demodulating device and method, and program


A medical device, for example a stent, has a surface which in use contacts body tissue, wherein said surface has on it a biocompatible coating layer comprising a polymer having covalently bound allyl-terminated pendent groups, said pendent groups comprising a moiety selected from -0-CH2—CH═CH2—S—CH2—CH═CH2—S(=0)-CH2—CH═CH2—Se—CH2—CH═CH2 and —Se (=0 J-CH2—CH═CH2. This surface has good biocompatibility and can bind strongly to a metallic surface. The polymer may be made from an electropolymerisable monomer, e.g. a pyrrole.

In the field of medicine, many devices are employed which contact body tissue and fluids. These include for example implanted devices, components of blood dialysis devices and blood storage containers. It is important that the surfaces which contact body tissue have certain properties to make them suitable for their function. One of the most important of these is biocompatibility, and non-toxicity to cells. When the device is intended for contact with blood, it is important that the surface of the device does not induce thrombosis. Other considerations are important, depending on the intended use of the device.
For example, in the case of coronary stents, it is desirable that the surface of the stent does not induce inflammatory response, does not promote thrombosis and is rapidly endothelialised. In earlier practice, bare metal stents made from medical steel or other alloys in various designs were predominantly used in coronary stenting procedures. However, following the arterial vessel damage inevitably associated with the stenting operation, smooth muscle cell proliferation and migration into the lumen occurs. This is called restenosis. In 15-20% of operations using a bare metal stent, restenosis leads to serious loss of lumen volume. This requires further medical intervention, commonly re-stenting of the vessel.
In recent years, coronary stents have been modified with polymer coatings which are loaded with drugs, commonly paclitaxel, rapamycin and closely related drugs. These drugs elute from the polymer and inhibit cell migration and neointimal thickening of the arterial wall. Such devices are known as drug-eluting stents. The use of such stents has led to a dramatic reduction in the occurrence of restenosis.
However, certain concerns about the safety of drug-eluting stents have emerged. Late-onset thrombosis leading to death occurs in some patients between 1 and 4 years after implantation of drug eluting stents. For this reason, the proportion of drug eluting stents used in coronary stenting operations has declined in favour of bare metal stents.
The cause of this late onset thrombosis is likely to be that the polymer coating or the combination of polymer and residual drug induces an inflammatory response, leading to platelet adhesion and activation, which triggers the thrombogenic cascade. Paclitaxel and rapamycin diminish restenosis, but they also inhibit endothelial cell proliferation which is necessary for healing of the damaged artery and is protective against thrombosis.
In the light of these problems, the aim of the present invention is to provide improved biocompatible polymeric coatings on stents and other medical devices which are in contact with body tissue.
It is known that extracts of Allium sativum (garlic) have a platelet inhibiting effect (1). In a double-blind, placebo-controlled study on 60 voluntary subjects with cerebrovascular risk factors and constantly increased platelet aggregation, it was demonstrated that the daily ingestion of 800 mg of powdered garlic (in the form of coated tablets) over four weeks led to a significant inhibition of the pathologically increased ratio of circulating platelet aggregates and of spontaneous platelet aggregation.
Some of the compounds in extracts of garlic with anti-inflammatory and platelet inhibiting effects are ajoene, allicin, alliin and ethiin, shown below
See: Bioactive S-alk(en)yl cysteine sulfoxide metabolites in the genus Allium: the chemistry of potential therapeutic agents.    P. Rose, M. Whiteman, P. K. Moore and Y Z Zhu.Nat. Prod. Rep., 2005, 22, 351-368
WO03/018082 discloses an implantable medical device, such as a stent, comprising a substrate and a biocompatible polymeric coating, wherein the coating contains ajoene and/or allicin or isomers, analogues, homologues or derivatives thereof. The biocompatible coating has a composition which permits the ajoene and/or allicin to be controllably released in a predetermined manner and over a prolonged period of time. Therefore, the medical devices disclosed in this document are in the "drug-eluting" category.
U.S. Pat. No. 4,917,921 discloses antithrombogenic and antibiotic compositions for use as coatings on artificial prostheses and implants which remain in contact with blood or other physiological fluids. The compositions are copolymers of 2-vinyl-4H-1,3-dithiin with a biocompatible monomer. The dithiin is a garlic extract having an allyl functionality. Thermal initiation using free-radical initiators, photochemical initiation using photoinitiators, or chemical initiation using group transfer polymerisation with activated methyl-methacrylate are disclosed as possible routes for generating the copolymer. The allyl group is the polymerising part of the monomer, and is therefore not present in the polymer.
The monomer
has been disclosed, as an intermediate in a synthesis of other derivatised pyrroles (2). It is mentioned that this intermediate, along with a number of others, is electropolymerisable.


A method of adaptive filtering for multiple reference line of intra prediction in video coding, a video encoding apparatus and video decoding apparatus therewith are provided in the disclosure. In the method of intra prediction in video coding, a method of adaptive filtering is used to dynamically determine operation of filtering is applied to input samples in the intra prediction or not, which can reduce the complexity of the intra prediction in video coding if multiple reference lines are used for the operation of the intra prediction, and also increase the efficiency of compressing performance of ultra-high resolution video.

Applications that need a large number of video data are increasingly wide, such as a digital television, a digital live broadcast system, a wireless broadcast system, a personal digital assistant (PDA), a laptop or desktop computer, a tablet, an e-book reader, a digital camera, a digital recording device, a digital media player, a video game device, a video game control console, a cellular or satellite radio telephone (the so-called "smart phone"), a video teleconferencing device, a video streaming device and other similar devices. When the data needs to be transmitted via a stream or transferred in a communication network with limited bandwidth capacity, the difficulty may be possibly increased. Therefore, video data is usually compressed before the video data is transmitted in a modern telecommunication network. When the video data is stored on a storage device, the size of a video may also be a problem because memory resources may be limited. Before the transmission or storage of the video data, video compression devices often use software and/or hardware to encode the video data at the source, thereby reducing the data volume required to represent digital video images. Then, compressed data is then received and decompressed at an object apparatus by a video decompression circuit that decodes the video data. With the limited network resources and the increasing demand for higher video quality, there is a need for improving compression and decompression techniques that increase the compression ratio and almost have no reduction to the image quality.

Method of adaptive filtering for multiple reference line of intra prediction in video coding, video encoding apparatus and video decoding apparatus therewith

Industrial Technology Research Institute


Interactive geographic information systems (GIS) and techniques are disclosed that provide users with a greater degree of flexibility, utility, and information. A markup language is provided that facilitates communication between servers and clients of the interactive GIS, which enables a number of GIS features, such as network links (time-based and/or view-dependent dynamic data layers), ground overlays, screen overlays, placemarks, 3D models, and stylized GIS elements, such as geometry, icons, description balloons, polygons, and labels in the viewer by which the user sees the target area. Also, “virtual tours” of user-defined paths in the context of distributed geospatial visualization is enabled. Streaming and interactive visualization of filled polygon data are also enabled thereby allowing buildings and other such features to be provided in 3D. Also, techniques for enabling ambiguous search requests in a GIS are provided.

A geographic information system (GIS) is a system for archiving, retrieving, and manipulating data that has been stored and indexed according to the geographic coordinates of its elements. The system generally can utilize a variety of data types, such as imagery, maps, and tables. One company involved in geographic information systems is ESRI, which maintains a website at www.gis.com that includes background information on conventional geographic information systems.
Generally, conventional geographic information systems have limited usefulness in both their overall functionality and user interface. For example, any information search capabilities present in conventional GIS and distributed geographic information systems (DGIS) have historically required a user to disambiguate the nature of a search request, selecting search scopes like "address search" or "lot number search" as either an explicit component of the search process or implicitly by allowing only a single scope (most often "address") within which all search requests are interpreted. In this sense, conventional GIS are effectively hardwired to search and use particular kinds of information.
What is needed, therefore, are geographic information systems that provide users with a greater degree of flexibility, utility, and information.

Dynamic view-based data layer in a geographic information system