Provided is a multicolor organic light emitting apparatus having a plurality of organic light emitting devices formed on a substrate, for emitting two or more types of luminescent colors. A thickness of a layer formed between a light emitting layer and a reflection surface of a cathode is the same as that of each of first and second organic light emitting devices, and an optical distance between a light emitting surface of each of the light emitting layers and the reflection surface of the cathode is adjusted such that each thickness of the light emitting layers is varied to enhance light emitted from the light emitting layers by optical interference.

1. Field of the Invention
The present invention relates to an organic light emitting device (organic electroluminescence device) for emitting light through energization of an organic layer including a light emitting layer formed between electrodes, and more particularly, to a multicolor organic light emitting apparatus having a plurality of organic light emitting devices formed on a substrate, for exhibiting two or more luminescent colors.
2. Description of the Related Art
In general, as a self-emitting device used for a display, a light source, or the like, an EL (electroluminescence) or an LED (light emitting diode) is known. Particularly, an organic light emitting device in which an organic compound material is used as a luminous body has been focused because it is possible to obtain luminance of several hundreds to 1,000 Cd/m2 or more at a low voltage of about 10 V or less (when the device is DC driven).
Further, by appropriately selecting an organic compound material having emission spectrums corresponding to red (R), green (G), and blue (B), it is possible to produce an organic light emitting device for exhibiting three primary colors, and it is also possible to produce a full color display having a plurality of organic light emitting devices formed on a substrate with relative ease. From this point of view, at present, studies and development of the organic light emitting device are vigorously conducted.
However, a thickness of an organic layer of the organic light emitting device is the same as or less than that of an emission wavelength. Therefore, in order to obtain an organic light emitting device having a desirable luminous efficiency, it is necessary for the organic light emitting device to be designed in view of an influence of optical interference.
Accordingly, the following techniques are disclosed as a technique of optimally designing the organic light emitting device from an optical point of view.
Japanese Patent Application Laid-Open No. 2000-323277 discloses an organic electroluminescence multicolor display having a plurality of organic electroluminescence devices which is formed on a transparent substrate and in which a light emitting layer is made of a different material from the other, and which exhibits various luminescent colors. In addition, functional layers having the same function as that of the organic compound material layer other than the light emitting layer have thicknesses different from each other corresponding to each luminescent color. In other words, by varying each thickness of a hole transporting layer, an electron transporting layer, and the like for each luminescent color, optically optimum conditions for each luminescent color are satisfied.
Thus, Japanese Patent Application Laid-Open No. 2000-323277 describes that it is possible to provide an organic EL multicolor display having a desirable external light extraction efficiency with a simple method as compared with a conventional method of satisfying the optically optimum conditions by partially changing a thickness of an ITO anode.
Further, Japanese Patent Application Laid-Open No. 2000-323277 describes that a distribution of an emission intensity in the light emitting layer of the organic EL device formed of the organic compound material layer corresponds to an index function distribution with respect to a thickness, in which the emission intensity is strong on an interface on the hole transporting layer side, and the emission intensity decreases toward the electron transporting layer side. In addition, it is described that the interface on the hole transporting layer side is known as a light emitting interface having an emission intensity peak (see paragraph [0040]).
Further, Japanese Patent Application Laid-Open No. 2004-127795 discloses a display apparatus including a light emitting layer between a first electrode and a second electrode, and an organic light emitting device having a resonator structure in which light emitted from the light emitting layer is resonated between a first end portion and a second end portion. In addition, for respective organic light emitting devices for red emission, green emission, and blue emission, a maximum emission position of the light emitting layer and an optical distance between electrodes that sandwich the light emitting layer are defined. In this case, the thicknesses of the hole transporting layer, the light emitting layer, and the electron transporting layer of the organic light emitting devices for each color are different from each other, and all the thicknesses of the organic layers are adjusted (see paragraph [0045] to [0050])
Thus, Japanese Patent Application Laid-Open No. 2004-127795 describes that it is possible to obtain a relationship in which reflected light and generated light are mutually enhanced between the first end portion and the second end portion, which improves an extraction efficiency of light generated in the light emitting layer.
Further, Japanese Patent Application Laid-Open No. 2004-127795 describes that the organic light emitting device for red emission emits light on an interference on a side of the first electrode which is a anode, but the maximum emission position is on an interface on a side of the second electrode because the light emission on a side of the second electrode which is a cathode is larger than that on the first electrode side. The organic light emitting devices for green emission and blue emission emits little light on the side of the second electrode which is a cathode, so the maximum emission position is on the interface on the side of the first electrode which is a anode (see paragraph [0031]).
However, in both the organic EL multicolor display described in Japanese Patent Application Laid-Open No. 2000-323277 and the display apparatus described in Japanese Patent Application Laid-Open No. 2004-127795, the thicknesses of the hole transporting layer and the electron transporting layer are varied, which are unnecessary to be varied for each luminescent color if the optical interference between the light emitting layer and the reflecting electrode is not utilized. As a result, there arises a problem in that the number of manufacturing processes is drastically increased. In addition, it is necessary to severely control an alignment accuracy of a mask necessary for varying the thickness for each luminescent color, and an impurity or the like generated when the mask is exchanged, which leads to a reduction of a yield. Because of those problems, it is extremely difficult to vary each thickness of the layers having the same functions for each luminescent color in an actual manufacturing process. As a result, there is a demand for improving the external light extraction efficiency for each luminescent color by varying each thickness of the layers for each luminescent color not with the structure described in Japanese Patent Application Laid-Open No. 2000-323277 or Japanese Patent Application Laid-Open No. 2004-127795 but with a simpler structure.

Multicolor organic light emitting apparatus


Methods, systems and apparatuses are disclosed for joining assemblies, particularly joints and joining assemblies for co-joining composite components and metal components in a joining assembly, and inhibiting corrosion of metal components secured to composite component via a joining assembly.

Joint assemblies on structures, particularly aircraft and other vehicle structures and assemblies often join components made from dissimilar materials. For example, joint assemblies typically operate to join components made from similar or dissimilar materials. When dissimilar materials are to be joined, composite materials may, for example, be joined to metal-containing components. When joining components made from dissimilar materials, such as a component made from a composite material joined to a component made from a metal such as, for example, aluminum, a large difference in electrical potential is created. Such differential in electrical potential can increase the probability of corrosion of, for example, aluminum, especially when oriented proximate to composite components having exposed carbon fibers edges. Any flaws in the edges or ends of the composite material or the sealant covering the edges or ends can exacerbate the collection of, or otherwise serve as sites to retain moisture that may build up within joints used to connect the components (e.g. butt joints). Such moisture that is then subjected to varying temperatures can potentially degrade the ends or edges of an exposed composite component. Moreover, if moisture is allowed to remain in contact with ends or edges of joined metal components, such as aluminum components, corrosion can occur.
In the aerospace field, including the manufacture of aircraft, it may be desired to join composite components with metal components via joining assemblies. The joining of dissimilar components can offer particular advantages, as the properties of both materials may be desirable for a particular assembly.
The joining of dissimilar components in a joint assembly can present challenges as the dissimilar materials may react differently to various environment conditions. For example, the dissimilar materials may react differently to moisture build-up that could lead to the corrosion of the metal components. While the CFRPs themselves demonstrate good corrosion resistance, moisture may build up and present undesirable effects at and within a joint assembly. Structures comprising joined assemblies can experience wide ranging temperatures that can lead to degradation of certain mechanical properties of the CFRPs, such as, for example, at the matrix-fiber interface and at the edges of the composite components where the fibers may be exposed to and retain amounts of moisture. When composite components are joined in close proximity to metal components, such as in a common joint (e.g. joining of dissimilar materials), even though the CFRPs themselves may not be affected by the moisture present, the carbon fibers in the CFRPs can contribute to galvanic corrosion in the commonly-joined metal components.
Galvanic corrosion is caused by dissimilar metals and alloys have different electrode potentials coming into contact through an electrolyte (e.g. moisture/water, especially if salt or industrial pollutants are present) with one metal acting as anode and the other metal acting as a cathode. The electrode potential difference between the dissimilar metals results in an accelerated attack on the anode member of the galvanic couple. The anode metal dissolves into the electrolyte, and a deposit collects on the cathodic metal. In the case of moisture build-up, water can become an electrolyte, thereby providing a means for ion migration whereby metallic ions move from the anode to the cathode within the electrolyte. This leads to the metal at the anode corroding more quickly than it otherwise would and corrosion at the cathode being inhibited.
Such corrosion, including galvanic corrosion of joined metal components, can necessitate the replacement of such metal components, resulting in increased cost as the structure comprising the corroding metal component must be removed from service while the metal component is serviced or replaced.

Methods and apparatuses for providing corrosion protection to joined surfaces


An embodiment is a technique to classify a flash device. Test data to a flash device are accessed in unscramble and scramble modes under a test mode. Error correcting code (ECC) results are recorded on the test data for the unscramble and scramble modes. A device quality figure is calculated based on the ECC results for the unscramble and scramble modes. The flash device is classified using the device quality figure.

Flash memory devices (e.g., NAND flash devices) have become increasingly popular in data storage for computer systems, mobile devices, and consumer devices (e.g., cameras). Solid-state drives (SSDs) using flash devices have now become important in many data storage applications. The life expectancy and data quality of flash devices depend on several factors such as data write rate, program and erase cycles, and environmental conditions (e.g., temperature). Applications using flash devices may have various requirements. For data intensive applications such as real-time databases with frequent updates, it is important to have long-life flash devices. In contrast, applications that have short commercial time span and infrequent data updates such as mobile phones may not need long-life flash devices. Accordingly, there exists a need to classify flash devices according to their quality and reliability so that they may be properly used in a variety of applications.
Current techniques for classifying flash devices have a number of drawbacks. Manufacturers of flash devices do not provide grades for their flash devices. While they do provide test information on their flash devices (e.g., initial valid blocks when first shipped, Total Bytes Written or Tera Bytes Written), this information may not be useful because it does not provide an accurate picture of the quality of the devices. In addition, most flash devices have comparable number of invalid blocks or Total Bytes Written or Tera Bytes Written (TBW) and therefore it is difficult to distinguish them. Furthermore, each manufacturer may have its own test parameters and therefore classifying flash devices that are manufactured by different manufacturers may not be accurate.


Techniques to determine particular bad tapes or tape drives. All tape and tape drive combinations within a system may be obtained. A read error or a write error that occurs with each tape and tape drive combination may be detected, and the read error, the write error, or a parameter may be analyzed to determine the particular tape or the particular tape drive that is bad.

A tape drive is a computer component used to write data to a tape, such as a magnetic tape. The tape drive is typically used to backup data from the computer onto the tape. In the event of a malfunction, data can be restored to the computer system from the tape using the tape drive.
Errors may occur when manipulating data, including reading data from a tape or writing data to a tape. When a read error or a write error occurs, a user may view graphs of write margin data in order to pinpoint the error. Based on the graphs of write margin data, the user can decide what action to take in order to remedy the error. The action may include replacing drives or tapes within the system that the user believes to be the cause of the error. However, the write margin data of most systems is extensive and can easily overwhelm the user. As a result, the user typically engages in a lengthy trial and error process of replacing drives and tapes until the error is resolved, with no clear indication of the faulty tape or tape drive.

Linking errors to particular tapes or particular tape drives

Hewlett-Packard Development Company, L.P.


A method for fractionating a fuel includes heating the fuel and flowing it through hollow superhydrophobic membranes in a membrane module. Vapor from the fuel permeates the hydrophobic membranes and enters a distillate collection chamber, producing distilled fuel and residual fuel. The residual fuel is removed from the module and cooled. The cooled residual fuel is flowed through hollow tubes in the module and the distilled fuel is removed from the distillate collection chamber. Burning the distilled fuel reduces engine emissions. A fuel fractionation system includes a distillate collection chamber, hollow superhydrophobic membranes, hollow tubes and a distillate outlet. The hollow superhydrophobic membranes receive heated fuel and allow vapor from the heated fuel to permeate the membranes and enter the distillate collection chamber. The hollow tubes receive cooled residual fuel and are positioned to allow vapor in the distillate collection chamber to condense on outer surfaces of the hollow tubes.

Exhaust gas is emitted by engines as a result of fuel combustion. Exhaust gas typically contains nitrogen, water vapor and carbon dioxide, but can also include carbon monoxide and particulate matter. Particulate matter consists either of solid carbonaceous materials (e.g., soot or non-volatile particulates) or condensed volatile matter which is referred to as volatile particulates. Emissions of both volatile and non-volatile particulates are known to increase with high concentrations of the heavier hydrocarbon fractions in the fuel. Engines that burn fossil fuels tend to produce the most particulate emissions during a cold start. In the case of gasoline engines, most of the particulate emissions are released within the first few minutes of a cold engine start. Similar emission levels are observed in jet engines on aircraft. In addition to cold starts, jet engines produce higher levels of emissions during take off.
Membrane distillation has recently become increasingly popular in a variety of fluid-treatment applications. The membranes are typically hydrophobic and microporous to keep the feed solution separated from that of the distillate during operation. Both hollow fiber and flat sheet membranes have been used in laboratory studies. For membrane distillation, hollow fiber membranes are typically employed in tube/shell configurations, where bundles of hollow fiber membranes are arranged along the longitudinal axes of the modules. Each hollow fiber membrane in the bundle is typically a hydrophobic, microporous membrane having an exterior surface and an inner hollow tubular region. In some membrane distillation systems, the inner hollow tubular regions define a tube side of the module, which serves as a conduit to contain the feed solution. The exterior surfaces of the hollow fiber membranes face a shell side of the module, which provides a region for collecting the distillate fluid separated from the feed solution.
During membrane distillation, the feed solution is typically heated to form a temperature differential across the hollow fiber membranes. This temperature differential creates a vapor pressure differential between the tube side and the shell side of the membranes in the module, which causes a portion of the feed solution to evaporate near the pore entrance on the feed solution side and the vapor to transmit through the hollow fiber membranes. The transmitted vapor then condenses at a gas/liquid interface near the pore entrance of the membranes on the distillate side, thereby providing the desired distillate. According to the present invention, membrane distillation concepts can be used to reduce engine emissions.

Fuel fractionation using membrane distillation


A broadcast radio event such as a song or a concert promotion, and a plurality of radio data fields corresponding to the event such as RTplus information, are received at a device. A user selects to display broadcast radio options simultaneous with receiving the broadcast radio event. Then is displayed a set of user-selectable options, at least one o which is derived from at least one of the radio data fields. In various embodiments, each time a new set of radio data fields are received, the set of displayed options is updated, with certain provisions to ‘freeze’ the displayed set of options. Examples of a derived option include a link to an Internet page, a phone number or email address, and posting a time and place of an advertised event to a calendar. A method, device, computer program product, and apparatus are detailed.

Broadcast radio has adapted to the digital music environment by adding RDS information to its broadcasts. The term broadcast radio is used herein consistent with its normal understanding, a wireless transmission intended for public reception, rather than a point t point message. Radio Data System RDS is text and data transmitted with a broadcast radio signal by radios with an RDS decode capability, which typically display some of the RDS information as text to a user.
There are fifty or more different RDS categories, including station name, program type or PTY flag (e.g., pop, rock, talk radio); travel announcement or TA flag, enhanced other networks or EON flag, alternative frequency or AF flag, time and date or CF flag, and radio text. The station name is generally eight digits maximum, such as "Jazz FM" or the actual station identifier (e.g., BBC4, WTIC). The TA flag can be switched on when a radio station starts a travel report, and switched off at the end, so that the user's RDS compatible radio receiver can switch to a station carrying travel news (or in a car, pause a cassette or a CD) when local travel news is broadcast. The EON flag allows an RDS radio receiver to know about other associated stations, so a radio can know that when listening to one program, it should keep an ear on another (local) station for relevant travel news. The AF flag contains information about the current station's other FM frequencies, so that the radio can switch to a better signal while driving. The CF flag carries the current date and time, which automatically resets the clock in RDS clock radios and updates for seasonal time changes.
The radio text information 'scrolls' across RDS radio displays, providing information that's sent from the radio station. When a compatible radio receiver is tuned to a broadcast radio station that broadcasts RDS information, the receiver is tuned to a broadcast event and displays on a graphical display interface certain of the RDS information as text, such as the station name, program type, or information about a song being played such as title, artist, and/or album. This is not normally fitted to an in-car radio, as it's seen as a distraction to drivers.
The original RDS was developed by the European Broadcast Union EBU in 1984. Among those skilled in the art, the features of RDS are known by a large number of abbreviations, such as PS (Program Service name), PTY (Program Type), AF (Alternative Frequency list) and ODA (Open Data Applications). A more detailed review of RDS and its latest advancement, Radiotext Plus (RTplus), can be found in the specification entitled: "Radiotext plus (RTplus) Specification" (version 1.0), RDS Forum 2005 R05/036—1. RTplus was jointly developed by the Westdeutscher Rundfunk WDR, Nokia Corporation and the Institut für Rundfunktecknik IRT.
RTplus provides additional information elements over standard RDS. Some examples illustrate the potential uses of these additional information elements. While a broadcast station broadcasts a song, RTplus provides classes of information while that song is being broadcast, in addition to regular RDS, that may indicate when and where the song artists might be playing in concert locally. The broadcast radio station may promote a contest, and the RTplus information broadcast with that promotion might provide a phone number, email address, and/or SMS address to register a vote or entry in that contest. While broadcasting an advertisement, the associated RTplus information might provide a link to an Internet page (URL) that relates to the product or service being advertised. While broadcasting a weather report or news, RTplus may provide a link to the broadcast station's local weather page or breaking news page of its web domain. Much like domains within the Internet, RTplus provides a depth of information that may be further explored by interested users, in this case, interested radio listeners.
What is needed in the art is a way to facilitate interested users to access and explore that additional information that RTplus provides.


A method for fabricating a rotor shaft using a welding process. The method includes positioning a first rotor shaft section adjacent a second rotor shaft section, and using a submerged arc welding process with an included weld preparation angle of between about 0° and about 30° to join the first and second rotor shaft sections together.

This invention relates generally to methods for fabricating rotor shafts, and more specifically to methods for repairing damaged rotor shafts for turbine generators.
At least some known turbine generators include one or more turbines coupled to a generator. The generator may include a rotor shaft that is coupled to one or more turbines via a coupling. Over time, such rotors may develop cracks, such as, but not limited to, at holes, fillets, and/or diameter changes along the shaft. Such cracks may sometimes propagate to a bore of the rotor, which may adversely affect a performance of the rotor and/or over time may shorten the useful life of the rotor. For example, the rotor shaft may include one or more keyways to facilitate radial alignment with the coupling. Stress cracks may develop at and/or adjacent such keyways, which may cause the rotor shaft to fail adjacent and/or underneath the coupling.
To repair a cracked rotor shaft, a section of the rotor shaft including the crack is sometimes cut off from an undamaged section of the rotor shaft and replaced with a new section. For example, if one or more keyways within an end of the rotor shaft that is coupled to the turbines are cracked, the cracked end may be cut from the rotor shaft and replaced with a new stub shaft end. At least some known methods for welding a new shaft section to an existing rotor shaft include using a combination of Gas Tungsten Arc Welding (GTAW) and Submerged Arc Welding (SAW). More specifically, and for example, at least some known methods include using a weld preparation angle of about 45° or more included, and applying one or more buttering layers using GTAW to trap elements in the base material and to minimize dilution into the weld. Such methods also use SAW to complete the weld between the new shaft section and the existing rotor shaft. However, the weld preparation angle and applied buttering layers may increase an amount of metal used to complete the weld, and may possibly increase a cost and/or time of completing the repair. Moreover, the use of both GTAW and SAW processes may require more equipment and/or operator training, and/or or may increase a time of completing the repair.
At least some other known methods used for welding a new shaft section to an existing rotor shaft include narrow groove GTAW, wherein a narrow groove with parallel sidewalls is used for the weld preparation. Although narrow groove GTAW may not require buttering layers to trap elements in the base material and minimize dilution into the weld, narrow groove GTAW may be limited by the depth of weld attainable. Moreover, narrow groove GTAW may require more operator training and/or specialized equipment, which may increase a cost and/or time of completing the repair.


A computing system can perform a layout-to-schematic process on a geometric layout design of an integrated circuit, which can generate a device-level layout design for the integrated circuit. The computing system also can perform a parasitic extraction process on the geometric layout design by utilizing the device-level layout design for the integrated circuit. The computing system implementing the parasitic extraction process can sub-divide a conductor in the device-level layout design into multiple sub-divided conductor portions based on conversion rules corresponding to the physical properties of layers for the integrated circuit described in a technology file. The computing system can generate a physical layout design of the integrated circuit from the device-level layout design having the sub-divided conductor portions based on the technology file. The computing system can extract electrical representations of nets corresponding to the conductors in the physical layout design to form a netlist for the physical layout design.

Electronic devices or systems, such as integrated circuits, can be used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating integrated circuits typically involves many steps, known as a "design flow." The particular steps of a design flow often depend upon the type of integrated circuit being designed, its complexity, the design team, and the fabricator or foundry that will manufacture the integrated circuit. Typically, software and hardware "tools" verify the design at various stages of the design flow, and errors in the design can be corrected or the design can be otherwise improved.
Several steps are common to most design flows for integrated circuits. Initially, the specification for a new integrated circuit can be transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit, or a schematic design. With this logical design, the integrated circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design can employ a Hardware Design Language (HDL), such as the SystemVerilog or Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit can be analyzed to confirm that it will accurately perform the functions desired for the integrated circuit. This analysis is sometimes referred to as "functional verification."
After the accuracy of the logical design has been confirmed, the logical design can be converted into a device design by synthesis software. The device design, typically in the form of a netlist, describes the specific electronic devices, such as transistors, resistors, and capacitors, which can be used in the integrated circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams.
The device design can be transformed with a place-and-route process into a geometric "layout" design, which describes specific geometric elements. The geometric elements, typically in the form of polygons, define the shapes that can be created in various materials to manufacture the integrated circuit. Typically, a designer can select groups of geometric elements representing circuit device components, e.g., contacts, gates, or the like, and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Once the groups of geometric elements representing circuit device components have been placed, geometric elements representing connection lines can be placed between these geometric elements according to the predetermined route. These lines can form the wiring used to interconnect the integrated circuit.
Before the geometric layout design can be utilized to create a mask for use in a photolithographic manufacturing process that produces the integrated circuit, the geometric layout design can undergo a number of physical verification analyses. A layout-versus-schematic (LVS) tool can confirm that the geometric layout design accurately represents the device design. The LVS tool can generate a netlist based on the geometric layout design and compare this netlist against the device design, which can also be a netlist, to determine whether the geometric layout design conforms to the device design. To generate the netlist from the geometric layout design, the LVS tool can extract design devices, such as transistors, diodes, capacitors, resistors, or the like, and their associated connectivity, from the geometric layout design based on an LVS rule deck from a foundry that will manufacture the integrated circuit. The LVS tool can utilize the extracted devices and connectivity to generate a device-level layout design and then convert the device-level layout design into the netlist corresponding to the geometric layout design.
Another physical verification analysis can be parasitic extraction, where a parasitic extraction tool can analyze the geometric layout design to determine parasitic values, such as resistances, capacitances, inductances, or the like, and utilize the parasitic values to determine whether an integrated circuit manufactured according to the geometric layout design would include voltage drops, signal delay, or signal noise. The parasitic extraction tool can convert the device-level layout design generated by the LVS tool into a physical layout design representing the integrated circuit three-dimensionally based on an Interconnect Process Technology (IPT) file generated by the foundry, and then utilize the physical layout design to generate parasitic electrical models for nets in the physical layout design and write the parasitic electrical models to an extracted parasitic netlist. The extracted parasitic netlist can be utilized to identify voltage drops, signal delay, or signal noise that could be present in the integrated circuit manufactured using the geometric layout representation.
Conventionally, the LVS rule deck and the IPT file from the foundry describe the layers of the geometric layout design at a common level of abstraction, for example, describing the same layers with the same connectivity. For example, when the LVS rule deck describes a metal layer and its connectivity, the IPT file describes the metal layer as also having the same connectivity, so that the parasitic extraction tool can perform the parasitic extraction process. In some instances, the foundry may have additional process details, such as varied heights for different portions of a metal layer, which can be added to the IPT file. This additional detail can allow for more accurate extracted parasitic netlist to be generated during the parasitic extraction process, but if added to the LVS rule deck introduces time-consuming and resource intensive processing during the LVS process. Thus, in the generation of the LVS rule deck and the IPT file, foundries trade-off accuracy in the parasitic extraction process with speed and ease of processing in the LVS process.

Conductor subdivision in physical integrated circuit layout for parasitic extraction


A hot swap circuit board and associated cable and connector arrangement for an ATA100 computer-disk drive interface is disclosed. The hot swap circuit board comprises a key-switched power supply control circuit with a simultaneously key-operated mechanical lock, a logic control circuit for READ and WRITE control signals and a set of logic switchable bi-directional impedance circuits with signal regeneration for the control and data signals across the ATA100 Interface. During normal operation, a security lock on the hot swap circuit board is kept in its locked position thus preventing any accidental disconnection of the ATA100 interface connector while simultaneously supplying electrical power and transmitted and regenerated control and data signals across the ATA100 interface. The unlocking mechanism is also disclosed.

This invention is related to, although not limited to, the computer-disk drive interface. More specifically, the invention is related to an electronic hardware for the hot swapping of individual disk drives or disk arrays from a microcomputer.
With the rapid development of micro-computers and associated peripherals of higher performance at ever decreasing cost, operating systems with ever increasing functionality and reliability, numerous application software for easy creation of multi-media, content rich information and the explosive advancement of the Internet infrastructure for information delivery and sharing, micro-computer users now routinely demand that their hard disk drives sustain a tremendous data transfer rate while storing voluminous data. For example, one of the latest industry standard definitions of the computer-disk drive Interface, or I/F, is called ATA100, and it specifies a data transfer rate of 100 MB/s (Megabyte/sec) through an 80 wire flat data cable. Additionally, these hard disk drives must be quickly interchangeable with data security followed by easy I/O in the course of data transfer. Since the traditional practice for disk swapping of power cycling and rebooting of the micro-computer is still quite time consuming and prone to system reliability problems, an emerging market requirement for the process of disk swapping is that the micro-computer power supply stay on throughout the process, or the so-called hot swapping of disk drive. With this technique, the hard disk drive can now be easily plugged into and pulled out of the drive rack. In other words, the hard disk drive now behaves more like a removable hard disk.
As the speed of Central Processing Unit (CPU) of the micro-computer continues to increase without bound, the corresponding data transfer rate between a single hard disk drive and the host adapter needs to be improved to maintain the system data throughput. In fact, even at the data transfer rate of 100 MB/s, it is much too slow compared to the speed of CPU and has become the data bottleneck of the computer system. A natural solution for this problem is the deployment of disk arrays working in parallel to ease this data bottleneck. Consequently, the same market requirement of hot swapping also gets applied to the disk array.
Therefore, a solution is needed to allow, with secured access, the hot swapping of individual hard disk drives and disk arrays from a micro-computer while maintaining an ATA100 data transfer rate of 100 MB/s across the computer-disk drive interface, which is an industry standard definition of the computer-disk drive interface.
The first objective of this invention is to devise a technique that allows the hot swapping of individual hard disk drives and disk arrays from a micro-computer, thus effectively making the hard disk drive or disk array behave more like a removable hard disk or removable disk array.
The second objective of this invention is to devise a technique that allows the hot swapping of individual hard disk drives and disk arrays from a micro-computer wherein the computer-disk drive interface is the industry standard ATA100.
The third objective of this invention is to devise a technique that allows the hot swapping of individual hard disk drives and disk arrays from a microcomputer with secured access.
Other objectives, together with the foregoing are attained in the exercise of the invention pursuant to the following description and resulting in the embodiment illustrated in the accompanying drawings.

Hot swap safeguard circuit of ultra DMA hard disk


A method, non-transitory computer readable medium and apparatus for detecting a tethering function being performed by an endpoint device in a communications network are disclosed. For example, the method analyzes a data packet directed towards the endpoint device, detects a signature based upon analyzing the data packet, and identifies the endpoint device as performing the tethering function based upon detecting the signature.

Currently, software patches exist that allow endpoint devices to share their wireless data connection with other devices using a hotspot or a direct cable connection (known as "tethering"). Currently, it is difficult to identify endpoint devices that are tethering.
Tethering is detrimental to a network service provider. For example, tethering creates more network data traffic over the service provider network by end point devices that are not subscribers of the network service provider. Unauthorized tethering effectively "steals" bandwidth from the network service provider without paying for the service.

Method and apparatus for detecting tethering in a communications network


A laser (e.g., excimer laser) and masking apparatus performs controlled sculpting of eye surfaces, such as corneal surfaces. The masking system includes a single/multi-layer (e.g., metallic) coated substrate (e.g., fused silica) with multiple openings in the substrate of desired size, shape and spacing to control the power transmission of a laser used in conjunction with the mask. The power transmission is controlled through the use of diffraction and absorption. The power transmission can be attuned to a particular surface by using topographical information of the surface in question. The surgeon can observe the topographical information and then pattern the openings (size, number, shape, spacing) so that reshaping can be done with greater intensity (using larger or more openings) to remove more corneal tissue in areas that the surgeon feels need more reshaping. Areas that need less reshaping can be masked complete by not placing holes or openings in that area of the mask, or by placing fewer or smaller openings.

1. Field of the Invention
The present invention relates to an improved laser surgical method and more particularly relates to an improved method of reshaping or sculpting the outer surface of a patient's cornea wherein a masking system includes a single or multi-layer coated substrate used to control the power transmission of a laser that is used in conjunction with the masking system. More particularly, the present invention relates to a laser surgery masking system for sculpting a patient's cornea using a mesh constructed to control power distribution through its substrate, preferably in the form of a grid having defined variable sized patterns etched through a reflective substrate over a transparent or translucent material (e.g. fused silica) wherein the pattern can be etched onto a deposited metal coating or other reflective or totally absorbent coating.
2. General Background
The corneal tear/air interface is the major refracting surface in the eye with an average convergent refractive power of 48.8 D. The human cornea has an average thickness of about 0.52 mm, and a transmittance cutoff wavelength of 300 nm. In recent years considerable advancement in low wavelength lasers has opened frontiers in refractive surgery.
Corneal topography can be used to estimate deformations and abnormalities of the corneal surface prior to refractive surgery. Low wavelength lasers could make refractive surgery a cost effective and common surgical procedure.
Various surgical techniques have been proposed for reprofiling of the corneal surface. One common technique is radial keratotomy in which a set of four to eight radial incisions are made in the eye to flatten the curvature of the cornea.
Another suggested technique employed the use of a low wavelength excimer laser to perform controlled ablative photodecomposition. Although altering the curvature of the outer corneal surface has been effective in correcting spherical myopia, the limitation with current laser technology is the inadequacy of corrective surgery in aspheric, irregularly astigmatic corneal surfaces.
Some patents have been issued which relate generally to the sculpting of a patient's cornea. For example, U.S. Pat. No. 4,911,711 entitled "Sculpting Apparatus for Correcting Curvature of the Cornea" provides ultraviolet-laser sculpting of the cornea to achieve optical correction through a newly shaped anterior surface. The apparatus subjects the laser beam to certain shaping and homogenizing operations prior to any attempt to specially characterize the beam for a particular sculpting procedure. In a preferred embodiment, the shaping and homogenizing operations present a tolerably homogeneous beam of enlarged dimension, so that specialty-characterizing may proceed on a dimensional scale that is greater than the corresponding dimension of ultimate surgical delivery to the eye, thereby enabling greater control of the quality of specialty characterizing. Provision is made for selectively monitoring the quality of the homogeneity and/or the specially characterized beam, with further provision for automatic cutoff of laser beam delivery to an eye in the event that quality is not within the predetermined limits of tolerance. And preferably, all beam shaping, homogenizing and characterizing operations proceed in a controlled environment which precludes ozone development and thus minimizes the beam degrading effect of ozone and particulates or other contaminants.
U.S. Pat. No. 4,994,058 entitled "Surface Shaping Using Lasers" issued to Anthony Raven et al. provides a laser system and masking apparatus for reprofiling surfaces, such as corneal surfaces. The system includes a laser and a mask disposed between the laser and the surface to be reprofiled, the mask providing a predefined profile of resistance to laser radiation, such that upon irradiation, part of the radiation is selectively absorbed and part is transmitted to the surface in accordance with the masked profile, to selectively erode the surface. The masking apparatus disclosed is a mask to be affixed to the surface, or may include a support structure to support and position the mask above the surface. The resistance profile is stated as created by varying the thickness or the composition of the mask.

Laser surgical method of sculpting a patient's cornea and associated intermediate controlling mask


Systems and methods for operating a series of generators configured to provide power to a motor or motors. Generators generally operate at different efficiency levels depending on the operating capacity. A computation component can analyze the current efficiency of the generators and determine if there is an alternative power distribution among the existing generators that would result in a more efficient operation of the system.

Oil and gas drilling operations require significant quantities of power and control over that power. A typical drilling rig uses generators which consume fuel to create mechanical and electrical power which is then used to operate a drilling rig. Drilling itself consumes a large portion of the power required at the rig but there are many other components that all factor in. Managing the power created and consumed in an efficient way is a continuous challenge to a drilling operation.

Load management algorithm for optimizing engine efficiency


There is provided a cell search apparatus and method in a mobile communication system. The cell search apparatus is slot time-synchronized by receiving a first synchronization code in each slot of a P-SCH frame and in addition receives over the slots of an S-SCH frame a base station group specific code representing one of base station groups and a base station specific code representing one of base stations in the base station group. In the cell search apparatus, a base station group specific code detecting unit detects the base station group specific code received on the S-SCH in the slot-synchronized state, and a base station specific code detecting unit detects a transmitting base station by detecting the base station specific code received following the base station group specific code.

1. Field of the Invention
The present invention relates generally to a mobile telecommunication system, and in particular, to a cell search apparatus and method in an asynchronous base station (BS) and a mobile station (MS).
2. Description of the Related Art
The UMTS (Universal Mobile Telecommunication System) is an asynchronous BS system in which an inter-BS operation is asynchronously done. Each constituent BS in the system is assigned to a unique cell specific code for identification. If the UMTS includes 512 cells (i.e. 512 BSs) for instance, 512 cell specific codes are assigned to the respective 512 BSs. To search for its serving BS, an MS should search the 512 BSs by checking the phases of their cell specific codes, consuming a large amount of time. To overcome the inefficiency of the conventional cell search algorithm, a multi-step cell search algorithm has been explored. For implementation of the multi-step cell search algorithm, the BSs in the UMTS are divided into a predetermined number of groups (e.g., 32 or 64 groups), each BS group being assigned to a different group specific code. Thus, for 512 base stations, each BS group is comprised of 16 BSs. Each of the 16 BSs is assigned to a different broadcasting channel (BCH) spreading code (cell specific code) so that the MS can search for its serving BS. This multi-step cell search algorithm includes the steps of (1) receiving a primary synchronization channel (P-SCH) signal from a serving BS and synchronizing to the slot time of a slot received with the highest power; (2) receiving a secondary synchronization channel (S-SCH) signal from the BS while the MS is synchronized with the slot time and detecting frame synchronization and the group specific code of the BS; and (3) searching for the cell specific code of the BS by means of a BCH received from the BS based on the frame synchronization and the BS group specific code.
The multi-step cell search algorithm will be described in detail referring to FIGS. 1, 2, and 3.
FIG. 1 illustrates a conventional UMTS channel structure. Along the time axis of a channel signal transmitted by a BS, one UMTS slot has 2,560 chips and 16 slots form one frame. Thus, one frame has 40,960 chips.
A P-SCH is the same code for each BS in the UMTS. It is transmitted with a synchronization code #0, SC 0, for a tenth of the each slot period, that is, for 256 chips. Then, an MS receives the P-SCH and synchronizes with a BS slot time (the first cell search step).
Along with the P-SCH, the BS transmits its BS group specific code on an S-SCH. The BS group specific code is a 16-symbol codeword. The 16 symbols corresponds to 16 synchronization codes selected from 1st to 17th synchronization codes SC1 to SC17 and each symbol is mapped in one of the 16 slots of one frame. The slot-time synchronized MS acquires the group specific code and frame synchronization of the serving BS from the received S-SCH (the second cell search step).
A BCH message signal transmitted along with the S-SCH signal is comprised of pilot and data symbols in each slot. The BCH message signal is spread with a cell specific code (a BS specific code), one of the 32 scrambling (cell specific code) code which mapped with the 16-symbol codeword, synchronization codes SC1 to SC16. The MS despreads the BCH signal with the 32 scrambling codes and selects a cell specific code with a maximum correlation as the BS specific code (the third cell search step).
The third cell search step will be described in detail referring to FIG. 2.
FIG. 2 is a block diagram of a conventional cell search apparatus to implement the third cell search step. Referring to FIG. 2, the MS, frame-synchronized with the BS and informed of the BS group in the second cell search step, receives the BCH signal at 1st to 32th correlators 211 to 223 in the cell search apparatus. Each BS group in the UMTS has 32 cell specific codes and a BCH signal is spread with one of the 32 scrambling code (cell specific code) which mapped with the 16-symbol codeword, synchronization codes SC1 to SC16. That is why the MS has 32 correlators to despread the BCH signal. The 1st correlator 211 calculates a correlation of the BCH signal in an auto-correlation function for a 1st cell specific code (scrambling code), a 2nd BCH correlator 215 calculates a correlation of the BCH signal in an auto-correlation function for a 2nd cell specific code (scrambling code), a 31th BCH correlator 219 calculates a correlation of the BCH signal in an auto-correlation function for a 31th cell specific code (scrambling code), and a 32th BCH correlator 223 calculates a correlation of the BCH signal in an auto-correlation function for a 16th cell specific code (scrambling code). Here, 3rd to 30th BCH correlators are not shown for convenience sake, but each unshown correlator calculates a correlation of the BCH signal in an auto-correlation function for the 3rd to 30th synchronization code. Then, the correlations are accumulated in 1st to 32th BCH accumulators 213 to 225. That is, the 1st BCH accumulator 213 accumulates the correlation received from the 1st BCH correlator 211, the 2nd BCH accumulator 217 the correlation received from the 2nd BCH correlator 211, the 31th BCH accumulator 221 the correlation received from the 31th BCH correlator 219, and the 32th BCH accumulator 225 the correlation received from the 32th BCH correlator 223. Though not shown, 3rd to 30th BCH accumulators accumulate the correlations received from the 3rd to 30th BCH correlators, respectively. A maximum BCH correlation detector 227 detects a maximum of the BCH accumulator outputs received from each BCH accumulator, to determine the BS specific code.
To detect its serving BS, as described above, the MS should perform the first to third cell search steps sequentially. This cell search method has the distinctive problems that (1) complex additions involved in the multi-step cell search consume a large amount of time and especially 16×256 complex calculations required to detect correlations of a 256-chip sequence with respect to 16 second synchronization codes take a long time and increase hardware load; (2) the requirement of 32 correlators corresponding to the BS specific codes for the third cell search step increases hardware complexity; and (3) many computations caused by concurrent parallel operation of the correlators leads to excess power consumption in an MS.

Cell search apparatus and method in CDMA mobile communication system


A rotatable sunshade includes a pole rotatably coupled to a connection tube fixed to a base. A runner is slideably mounted around the pole to fold, unfold, or tilt a canopy. A control tube is slideably mounted around the pole. When the canopy is tilted and the control tube is in an engagement position, at least one tooth of the control tube engages with at least one tooth of a positioning ring fixed to the connection tube, and the pole is not rotatable about a longitudinal axis of the pole relative to the connection tube. When the canopy is tilted and the control tube is in a disengagement position, the at least one tooth of the control tube disengages from the at least one tooth of the positioning ring, and the pole is rotatable about the longitudinal axis relative to the connection tube.

The present invention relates to a sunshade and, more particularly, to a sunshade that can be rotated in response to a change in the position of the sun.
A type of outdoor sunshade includes a pole located on the ground and a plurality of ribs each having an end pivotably connected to a top end of the pole. A runner is slideably mounted to the pole. A plurality of stretchers is pivotably connected between the runner and the ribs. A canopy is provided on the ribs. The runner can be moved towards or away from the top end of the pole to unfold or fold the canopy. The pole is fixed to a heavy base to avoid undesired rotation of the sunshade while the canopy is under a strong wind load. To provide an enhanced shielding effect, the unfolded canopy can be tilted according to the position of the sun. However, the positions of the sun in the morning, at noon, and in the afternoon, are so different from each other that the tilted canopy may not be able to provide a satisfactory shielding effect, and it is difficult to move the heavy base in response to the significant positional change of the sun.
Thus, a need exists for a rotatable sunshade providing enhanced shielding effect through easy operation.


1,1-Dichloro-1-fluoroethane and/or 1-chloro-1,1-difluoroethane are selectively produced by fluorination of 1,1,1-trichloroethane. Conditions in a first reaction zone selected to preferentially form 1,1-dichloro-1-fluoroethane. The reaction effluent is split between a 1,1-dichloro-1-fluoroethane recovery system, and a second reaction zone. The effluent from the latter is routed to 1-chloro-1,1,-difluoroethane recovery system. The second reaction zone conditions are selected for form 1-chloro-1,1-difluoroethane. The ratio of product formed by the overall process may be varied from up to 98% 1,1-dichloro-1-fluoroethane to greater than 98% 1-chloro-1,1-difluoroethane.

1,1-Dichloro-1-fluoroethane (hereinafter referred to by its American Society of Refrigeration Engineers designation, "141b") is presently under consideration as a replacement for trichlorofluoromethane as a foam blowing agent. It has a substantially lower ozone depletion index than trichlorofluoromethane. Moreover, 141b displays a 10-15% greater blowing efficiency in rigid foam, and an improved solubility in aromatic polyester polyol, in comparison to trichlorofluoromethane.
1-Chloro-1,1-difluoroethane (hereinafter "142b") is the starting material for the production of polyvinylidene fluoride.
The fluorination of 1,1,1-trichloroethane (hereinafter "140a") to manufacture 142b results in a product stream which includes unreacted starting materials as well as by-products including HCl, vinylidene chloride and 1,1,1-trifluoroethane (hereinafter "143a"). The reactor bottoms include unreacted hydrogen fluoride, pentafluorobutane and possibly small amounts of other organics. Pentafluorobutane is the principal component of reactor tars which accumulate in the reactor bottoms. Vinylidene chloride and pentafluorobutane have boiling points so close to 141b that they cannot be removed by simple distillation. Additional steps for separating 141b from these undesired side products are required, contributing to the overall expense of the process. Moreover, large yield losses are suffered when reactor tars are dumped.
U.S. Pat. No. 3,833,676 discloses a non-catalytic process for the fluorination of 140a with hydrogen fluoride to produce 141b and 142b, without formation of tar substances.

Process for production of 1,1-dichloro-1-fluoroethane and/or 1-chloro-1,1-difluoroethane


The invention relates to a device for adjusting the camber and/or toe of the wheels of a wheel suspension, particularly for motor vehicles, having a wheel carrier on which each wheel is rotatably supported and comprising a carrier part receiving the wheel and a guide part connected to the wheel suspension, between which rotating parts (26, 28) rotating about a rotation axis and preferably driven by an electric motor are disposed, bringing about a defined displacement of the carrier part and/or the guide part by the rotational actuation thereof for changing the camber and/or toe. According to the invention, a single adjusting drive (54) is provided for actuating the rotary parts (26, 28), by means of which the two rotary parts (26, 28) can be adjusted in different, particularly in opposite, directions.

The invention relates to a device for adjusting the camber and/or toe of the wheels of a wheel suspension, in particular for motor vehicles.
A wheel suspension of this type is generally known and has a structure wherein the actuating cylinders determining the camber and/or toe are adjusted by way of two actuators and two electric motors in both rotation directions in opposite directions and in the same direction. Only a few angular degrees are usually required to correct the camber and/or the toe for adjusting the rear wheels of wheel suspension, wherein the use of two actuators and two electric motors adds a not insignificant complexity.
It is an object of the invention to propose a device for adjusting camber and/or toe of the wheels of a wheel suspension which can be easily manufactured and controlled.

Device for adjusting camber and/or toe of the wheels of a wheel suspension


A preparation method of an electroconductive copper patterning layer includes (Step 1) preparing a dispersion solution of copper-based particles selected from the group consisting of copper particles, copper oxide particles, and their mixtures; (Step 2) forming a copper-based particle patterning layer by printing or filling the dispersion solution of copper-based particles to a substrate into a predetermined shape; and (Step 3) irradiating laser to the copper-based particle patterning layer to burn and interconnect the copper-based particles contained in the copper-based particle patterning layer. This preparation method burns a copper-based particle patterning layer with a strong energy within a short time by using laser. Thus, it is possible to obtain a copper patterning layer that is hardly oxidized even in the atmosphere, so a copper patterning layer with excellent electric conductivity is formed.

Circuit boards, semiconductor devices, and various displays have a patterning layer such as a wiring layer or an electrode layer, which is made of metal such as copper, nickel or silver. In particular, a patterning layer using copper is widely used due to good electric conductivity and low price.
Particularly, copper particles and copper oxide particles such as cuprous oxide may be produced with small diameter in a several nanometer or several micrometer level such that they may form a fine pattern, so they are useful in forming an electroconductive copper patterning layer.
Seeing conventional methods for forming an electroconductive copper patterning layer using copper-based particles, a paste mainly containing copper-based particles is printed on a substrate surface or filled in through holes of the substrate to form a copper-based particle patterning layer, and then the layer is thermally treated at a high temperature under the inert gas circumstance for burning. Accordingly, among the copper-based particles contained in the copper-based particle patterning layer, copper oxides are reduced into copper and thus connected with each other, and organic substances included in the paste are removed, so an electroconductive copper patterning layer is formed (see Japanese Laid-open Patent Publication No. 2006-93003).
This burning method gives a copper patterning layer with good electric conductivity to some extent, but it is not easy to adopt the burning process under an inert gas circumstance in the industrial aspect. On the while, in case a burning process under a common atmospheric circumstance, copper may be oxidized, which results in bad quality of electric conductivity of the formed copper patterning layer.

Preparation method of electroconductive copper patterning layer by laser irradiation


A vehicle speed control system includes an engine control system with an engine idle speed controller which maintains the engine idle speed set point for varying engine torque outputs and a vehicle braking system for braking the vehicle and which is operated by a deceleration demand means. The idle speed controller is arranged to receive signals from the deceleration demand means such that any increase in engine torque output demanded by the idle speed controller to maintain idle speed is limited in response to signals received from the deceleration demand means.

This invention relates to the control of a vehicle speed and is particularly applicable to vehicles having engine control systems with anti-stall ability.
4xc3x974 xe2x80x9coff roadxe2x80x9d vehicles may be equipped with anti-stall systems to prevent the vehicle stalling when traversing surfaces which resist vehicle motion, for example mud and sand. Such systems give the driver confidence when driving off-road and reduces the demands on the driver through clutch and throttle co-ordination.
However, anti-stall systems have a disadvantage in relation to vehicle control in that the system will not allow the vehicle engine speed to drop below that required to maintain the set idle speed, when a driver operates a braking system or a hill descent control system (HDCS). Such a situation may arise during the application of HDCS, or during the application of the brakes when traversing an obstacle. In such situation the idle speed controller xe2x80x9cfightsxe2x80x9d the braking system, with the idle speed controller increasing engine torque to maintain idle engine speed (and hence road speed) and the braking system or HDCS having to apply an increasing braking load to slow the vehicle down.
The situation arises because some 4xc3x974 off-road vehicles are not provided with a low ratio gearbox and road speed associated with the idle set speed may be relatively high. For Example, with an idle speed set point at about 1000 rpm and the vehicle in first gear, this may give a ground speed of up to 10 kph. This idle speed set point may be increased by the engine speed controller for cold starting, operation of air conditioning systems, increased battery loads, etc.
The present invention provides an improved vehicle speed control system.
According to a first aspect of the present invention there is provided a vehicle speed control system having an engine control system with an engine idle speed controller which maintains the engine idle speed at varying engine torque outputs, and a vehicle braking system for braking the vehicle and which is operated by a deceleration demand means wherein the idle speed controller is arranged to receive signals from the deceleration demand means and any increase in engine torque output demanded by the idle speed controller is limited in response to signals received from the deceleration demand means when the braking system is operational.
The braking system may include at least one of a wheel braking system and a transmission braking system which are activated by the deceleration demand means.
The deceleration demand means includes at least one of a driver operable brake pedal, a HDCS, or a stability control system, each of which produces a respective deceleration demand signal and the actual permitted increase in engine torque output may vary depending upon the source of a deceleration demand signal.
When the deceleration demand signal is derived from a driver operated brake pedal for a wheel braking system, the vehicle driver will experience through the brake pedal an increase in braking effort due to an increase in engine torque output which indicates to the driver that the vehicle is being slowed and that the idle speed may drop below the idle speed set point. This increase is limited to minimise additional brake wear, heat input, and braking effort.
When the deceleration demand signal is derived from a stability control system or the HDCS, then the increase in engine torque output is reduced to a minimum so that no excess effort is required from the braking system. This has the benefit of reducing brake wear, increases engine durability, reduces fuel usage and exhaust emissions.
The limited lower torque output demand is not activated instantaneously but is applied progressively so that no instantaneous changes in produced engine torque are generated, provided that said lower torque demand is above the actual torque demand at that instant. This is particularly important when a vehicle ascending a hill in low gear with the engine operating at the idle set point and the driver needing to operate the vehicle brakes. If the lower limit were applied immediately and the engine torque reduced the vehicle may stop and even roll back. With a progressive reduction in torque the vehicle will slow and the driver can take corrective action e.g. increase the throttle torque demand.


The present invention evaluates the power dissipation of an electronic circuit. A power dissipation value is calculated for each transition or event generated during the electronic simulation of an electronic circuit design that corresponds to an actual electronic circuit. The present invention relies on data that includes an electronic circuit design description of the electronic circuit, such as a gate level netlist; a cell library having a power model corresponding to a cell instance; cell activity data such as net transitions; and the total effective load seen by each cell pin of the logic cell to be evaluated for power. The power model includes simple arcs (transition delay values, energy per arc values, cell input capacitances, and output slew rate values) and power evaluation data. The total energy dissipated by the cell during the modeled activity is calculated by determining the number of simple arcs applicable to the cell, attributing an energy dissipated for each arc, adding the energy values, and compensating for any double counting of short circuit and internal charge/discharge energy. Two fix-width queues are used by system as directed by the software code in the power evaluation tool. A queue may be defined in memory under program control but may be of any structure either in software or hardware. For each cell instance, power evaluation tool uses a first queue to track every transition and direction of the transition that occurs at an input pin, while a second queue is used to track every transition and direction of the transition that occurs at a boundary pin (i.e., an input pin or at an output pin). A power value for the cell instance may then also be obtained from the total energy dissipated during the modeled activity.

1. Field of the Invention
The present invention relates to power evaluation of an electronic circuit design. More particularly, the present invention relates to a power evaluation system and a power evaluation tool that use simple arcs for calculating the power dissipation of an electronic circuit design under simulation.
2. Background
Power evaluation of integrated circuits (ICs), such as calculating on-chip power dissipation of logic circuits, has become more important, in part, due to the growing number of mobile products and the need to determine "hot spots" on ICs early in the design stage. Also, power evaluation has become much more complex since the increases in die size, speed (even though feature size and/or voltage supply may decrease), and device count of ICs has greatly complicated the task of optimizing power dissipation.
The ability to accurately evaluate, predict, and optimize power dissipation of an IC, or cells within the IC, enables designers to design better products. Power dissipation is a major issue in mobile products by virtue of the battery driven nature of such products, with lower power consumption resulting in longer battery life per charge. Low power dissipation also means lower package and die costs. In high performance computer products, power dissipation is a major concern since excessive power consumption, either by heat or by electro-migration, can damage a chip. Thus, there has been an increase in the reliance and use of power analysis tools to aid in the fabrication of ICs using traditional fabrication design tools.
The term EDA (Electronic Design Automation) as used herein includes all design automation tools that facilitate the design of an electronic circuit at the behavior, register, gate-level transistor and/or layout levels.
Also, the term cell is intended to include circuit portions within an IC that can be identified as discrete structures providing a function. For example, depending on the level of abstraction used to model a cell, the term may include structures defined at the physical level such as a transistor; at the gate/logic level such as a NAND or OR gate; or at the macro level such as a simple adder or flip-flop. The level of abstraction used depends on the design cycle stage and the speed at which modeling needs to be completed, among other things. Design automation tools that generate cell models at higher levels of abstraction tend to run faster but have a relatively greater margin of error, while such models using lower levels of abstraction tend to run slower but have a relatively lower margin of error.
Power dissipation within a cell has two fundamental components--dynamic and static power dissipation. Dynamic power dissipation is the amount of power expended by a cell in response to at least one input signal transitioning from one switching threshold to another (input signal transition) and which may also result in at least one output signal transition from one switching threshold to another within a given time period. For example, an input signal going from high to low, or vice versa, is defined as an input signal transition. Static power dissipation is the power dissipated due to current flowing from Vdd to ground such as when no signals are switching from one logic state or another. Thus, dynamic power dissipation is a function of circuit switching activity and the state of the cell, while static power dissipation is only a function of the logic state of the circuit.
The focus of the following invention is on dynamic power dissipation rather than static power dissipation since dynamic power dissipation represents a much larger portion of the total power dissipation of a typical logic circuit.
Dynamic power dissipation comprises a charge/discharge power component due to capacitive load and a short-circuit power component due to the effect of non-ideal switches that cannot be turned on and off instantaneously. As discussed in "On-Chip Power Evaluation Methods and Issues," by authors Amir Zarkesh and Wolfgang Roethig, published in the proceedings of the session entitled "On-chip Systems Design Conference," Design Supercon 97, page S141-S141-33, ISDN: 0-1933217-29-3,the energy dissipated for a charge of capacitance can be expressed with the equation below, where E is the total energy dissipated for a given capacitance C and voltage Vdd. EQU E=1/2*C*Vdd
Therefore, the charge/discharge power consumed by a driver of a signal switching circuit with frequency f is: EQU P=f*[1/2*C*Vdd].
For circuits that do not switch at a constant frequency f, an effective frequency, f_eff may be introduced. The effective frequency is the basic switching frequency multiplied with an activity factor, act, and is shown by the following equation: f_eff=f* act.
Table 1 below shows the activity factors for certain types of cell activities.
TABLE 1 Signal Activity Factor Clock 2 Counter LSB 1 Random Data 0.5 Reset Approx. 0
FIG. 1 is a schematic diagram showing a capacitive output load seen by the output pin of a driving cell in an example electronic circuit. For example, the capacitive output load seen by an output pin 2 at driving cell 4 includes cell load 6 and wire load 8. Cell load 6 includes all input pin capacitances of cells driven by driving cell 4, such as input pin capacitances 10a through 10n in cells 12a through 12n , respectively. Wire load 8 is the sum of the effective capacitance of net 14 to which output pin 2 is attached.
Measuring the cell load of driven cells may be accomplished through design automation modeling. Wire load may be measured through parasitic extraction if the wire load is calculated at the post-layout state. Parasitic extraction is known in the art. Both self capacitance to Vdd and Vss, and mutual capacitance to other signal interconnect wires also must be taken into account when measuring wire load.
Short-circuit power is proportional to the effective frequency f_eff since short circuit power always occurs concurrently with dynamic power and is dependent on the short circuit current path of a cell. As known in the art, characterization by accurate simulation is one method of modeling short circuit power in a cell.
Analyzing the power dissipation in an electronic circuit having multiple and/or different structures or cells, requires differentiating between external and internal cell power dissipation. External power may be defined as the power dissipated due to an external load, while internal power consists of short circuit power plus charge/discharge power dissipated by internal cell capacitances. Thus, in an electronic circuit having multiple cells or stages, both charge/discharge power and short circuit power in every cell must be calculated to determine the total power dissipation of the circuit. Since short circuit power of internal states of a cell depends on internal input slew rates rather than on primary input slew rates, and since the capacitive load is only seen by the last stage, the slew rate and load dependency of internal power is somewhat decoupled. The first stage is affected by the input slew rate (its load is a constant internal capacitance), and the last stage is affected by the external load seen by the last stage (since the last stage's input slew rate is an internal slew rate weakly affected by the primary input slew rate).
As known in the art, the term "slew rate" is defined as the rate of change of a voltage signal that changes from one signal value to another signal value over-time, such as a logic transition that changes from a logic LOW state to a logic HIGH state, or vice versa.
Power dissipation in sequential cells, such as a basic latch or flip-flop, is discussed below. A basic latch consumes power, if an input switches while the latch is transparent. If the latch is blocked, the switching input causes no power consumption. A flip-flop consists of basic master and slave latches in addition to an input buffer and a clock buffer. Therefore, power is consumed whenever the input or the clock signal switches. If the input switches while the clock is low, the master stage is transparent and thus, will consume power as well. On the rising edge of the dock, data is transferred from master to slave. Hence the slave and the output buffer will consume power, if the new output data is different from the old output data. On the falling edge of the clock, data is transferred from the input buffer to the master latch. Hence, the master latch consumes power if the new input data is different from the old stored data.
Sources of Dynamic Power Dissipation in a Cell
As pointed out above, short circuit currents and currents due to transient signals, such as switching transitions between logic states, are the main sources of power dissipation in a cell. For deep submicron designs, wire load tends to become more important than cell load in the case of random logic where the wires can be routed all around the chip. For data path structures with regular layout, both wire load and cell load scale down in essentially the same way. The overall ratio between load and short circuit current is almost unaffected, since both slew rate and load scale down in deep submicron design. However, the design style chosen has a major impact on the transient load current versus short circuit current. For example, optimally sized buffers exhibit both better performance and less power. For low threshold devices, static leakage current tends to increase, but is not of a significant amount compared to the dynamic power dissipated by such devices.
The switching activity component of dynamic power dissipation, which is predominant in logic and flip-flops, is more difficult to estimate, model and characterize than short circuit current. Currently, only simulation-based tools with accurate timing models can give a good picture of the power dissipated as a function of the input stimulus. Power optimization techniques in later design stages need to be able to reduce this part of the power consumption locally such as at the macro cell or even gate-level stage using characterization and simulation data that may be generated using design automation tools.
Prior methods of calculating the dynamic power dissipation of a cell at the macro cell or gate level are either very simplified and not very accurate, or are accurate but unwieldy since the number of variables used for computing power dissipation is exponentially proportional to the number of input and output pins used in the cell. More importantly, such prior methods are not well-suited for use with existing cell libraries that use complex arcs for cell timing information. A complex arc defines a sequence of events, such as an event X followed by events Y and Z, and is further described below.
The term "pin" is used herein to denote electrical connection points located on the boundary of the structure being modeled, such as first and second inputs 62, 64, carry-in input 66, carry-out output 68, and sum output 70 in a full adder like that shown in FIG. 2A, or such as the pins found in a NAND gate having two logical inputs (two input pins) and one logic output (one output pin)
A Simplified Linear Method for Analyzing Dynamic Power Dissipation
One prior art method of analyzing dynamic power dissipation of a cell includes using a simplified linear model to express energy dissipated as a function of the slew rate of an input signal transition asserted on the cell, the load seen by the output of the cell (output load), and the voltage swing of the input and output signal transitions. A more accurate model may be obtained by using a non-linear model that is a function of the slew rate of the input transition signal, the output load, and a characterization table having energy per transition values. As noted above, the simplified linear model is not very accurate, while the non-linear model can become very unwieldy when used to calculate the power dissipation of a cell having many input and output pins.
The energy per transition values, input slew rates, output loads, and cell state are obtained from cell modeling, as known in the art.
Non-Linear Methods for Analyzing Dynamic Power Dissipation
Under the non-linear approach, state-based modeling of the power dissipation of a cell uses input slew rates, output loads, and cell state generated from cell modeling to determine which energy per transition value is applicable for each transition analyzed. Total dynamic power dissipation of a particular cell includes calculating the energy dissipated by the cell for every pin having a state change in response to the assertion of a signal transition to one of the input pins of the cell. This approach results in an accurate model of the energy expended per transition. But the process can become very unwieldy depending on the number of input and output pins contained by a cell since it requires calculating the energy dissipated for every output state change that occurs in the cell for each rising and falling transition that can occur at each input pin of the cell.
For example, turning now to FIGS. 2A and 2B, calculating the power dissipation of a full adder 60 requires a total of four (4) energy per transition calculations per transition direction of an input signal because for each signal transition asserted for each input there can be four possible states. Specifically, an input signal transition asserted at first input 62 having a slew rate with a falling slope (a falling input signal transition direction), will require an energy per transition calculation for the possible case that:
1) second input 64 is at logic 0, carry-in input 66 is at logic 0, carry-out output 68 is at logic 0 and sum output 70 is at logic 0; PA1 2) second input 64 is at logic 0, carry-in input 66 is at logic 1, carry-out output 68 is at logic 0 and sum output 70 is at logic 1; PA1 3) second input 64 is at logic 1, carry-in input 66 is at logic 1, carry-out output 68 is at logic 0 and sum output 70 is at logic 1; and PA1 4) second input 64 is at logic 1, carry-in input 66 is at logic 1, carry-out output 68 is at logic 1 and sum output 70 is at logic 0. PA1 1) second input 64 is at logic 0, carry-in input 66 is at logic 0, carry-out output 68 is at logic 0 and sum output 70 is at logic 1; PA1 2) second input 64 is at logic 0, carry-in input 66 is at logic 1, carry-out output 68 is at logic 1 and sum output 70 is at logic 0; PA1 3) second input 64 is at logic 1, carry-in input 66 is at logic 1, carry-out output 68 is at logic 1 and sum output 70 is at logic 0; and PA1 4) second input 64 is at logic 1, carry-in input 66 is at logic 1, carry-out output 68 is at logic 1 and sum output 70 is at logic 1.
Another set of energy per transition calculations must also be performed for the case where an input signal transition having a rising slope is asserted at first input 62, as shown in truth table 72 of FIG. 2B which corresponds to full adder 60 in FIG. 2A. The energy per transition calculation for a rising input signal transition includes the possible case that:
Thus, as can be seen in the preceding example, each input pin in the cell which could possibly be affected by input signal transitions would require four (4) energy per transition calculations--a situation that can quickly become unwieldy as the number of output pins per cell increases.
Another known method for determining energy dissipation of a cell assumes that the energy per transition of a cell is equal to the energy dissipated by a signal transition occurring at an output for a given input signal, while all other outputs are held to a zero load.
For example, referring again to FIGS. 2A and 2B, calculating the energy dissipation for a signal transition asserted at second input 64 includes calculating the energy dissipated by a signal transitioning at sum output 70 by using the slew rate from the input signal applied at second input 64 and a load 71 seen by sum output 70 to determine the energy dissipated by the transition.
In the situation where more than one output undergoes a transition for a given input signal, the energy dissipated at each additional output transition also must be calculated. In the event that an input signal at second input 64 causes both sum output 70 and carry-out output 68 to change states, the total energy dissipated is the energy dissipated by the switching that occurs at second input 64, the switching that occurs at both outputs 68, 70 and the short-circuit energy dissipated by adder 60. In this scenario, determining the total energy dissipated requires calculating the energy dissipated due to: 1) the switching that occurs at second input 64 using a given slew rate and the resulting switching that occurs at sum output 70 having load 71, while the other remaining output, carry-out output 68 is held to have zero load at load 69; and 2) the switching that occurs at second input 64 using a given slew rate and the resulting switching that occurs at carry-out output 68 having load 69, while sum output 70 is held to have zero load at load 71. This method must also account for the double counting of short circuit and internal charge-discharge energy of the adder caused by the calculation, which is subtracted from the calculated energy dissipated by subtracting the energy dissipated by the switching of second input 64, while both outputs 68, 70 are held to have zero load at loads 69 and 71.
The above method is applicable to cells having many output pins without becoming too unwieldy to calculate because the state of the cell is not required in order to determine energy per transition values but is used simply to determine whether power dissipation that is due to two output states transitioning has occurred. However, this method is not compatible with the cell characterizations that are generated under the widely used arc-based cell modeling technique.
Arc-based Modeling under the Advance Library Format Method
Arc-based modeling, described in the reference manual entitled, "Advance Library Format for ASIC Cells and Blocks," version 0.9, published by Open Verilog International, (hereinafter, Advance Library Format reference) and, hereby incorporated by reference as if fully set forth herein, relies on a delay-based timing model of a cell to provide the necessary set of characterization variables necessary for analyzing the energy dissipation (and hence, power dissipation) of a cell. For a given set of stimuli, a delay-based timing model describes the cell's timing characteristic using complex arcs to describe a sequence of events. For example, an "input event a that is eventually followed by an output event X, output event Y, and output event Z."
An event is defined as a logic transition that occurs at a pin. For example, an input and output pin pair may have a timing characteristic that would be represented using a complex arc that is defined for a "rising edge on input pin A (first logic transition or event) which is followed by a falling edge on output pin Z (second logic transition or event)."
A complex arc is obtained from functional information that may be available for a library that describes the cell or directly from a design automation tool that generates functional information about the cell. The complex arc may include output pin load, input pin slew rate, skew between multiple switching inputs, voltage, and temperature. A complex arc may also contain state information. For example, in the delay-based timing model, a complex arc is created for each input and output pin pair in the cell for a given input pin slew rate and output pin load, while all other output pins are held to a zero load. Thus, a complex arc describes cell behavior without explicitly describing the stimuli (output pin load, and the like . . . ) applied to the cell that caused the events described by the arc.
Power characterization is a superset of cell timing characterization using the same set and range of characterization variables, including load, input slew rate, skew between multiple switching inputs, voltage, and temperature. Thus, a complex arc can provide the necessary cell characterization variables that are required to determine the power dissipated by the cell switching activity described by the arc.
The energy per transition values, input slew rates, output loads, cell state, and the like, are related to the cell's functional characteristics and may be obtained, with varying degrees of accuracy depending on the level of abstraction used, through the modeling of the cell using design automation tools discussed above. The cell is modeled to characterize the circuit's dynamic response to a given set of inputs, resulting in a set of values representing over time the circuit's performance characteristics. The cell models form a library of circuit information that give designers circuit characteristics such as capacitance (pin capacitances, transistor capacitances, interconnect capacitances, and the like), and output values of the cell in response to asserted input signals and the slew rates of such input signals to the circuit or cell. Calculating the power dissipation of the cell through energy per transition values uses these modeled characteristics.
As discussed above, energy dissipation caused by switching activity is a function of the charge/discharge current and short circuit current for a given set of cell characterization variables. Consequently, complex arcs are used, as disclosed in the Advance Library Format reference, to determine the number and type of transitions that occur for a given set of stimuli. The transitions in each complex arc can then be used to determine the energy dissipated by the cell.
The method tracks transitions (both input and output) by maintaining an event queue for each output transition that occurs for a given input transition. Also, in a case where more than one output transition occurs for a given input pin transition, the method must determine the order of occurrence for each output transition. This causes the method to maintain a variable number of queues for tracking each transition for a given input pin and for all output pins, and for determining the order of occurrence of each transition that occurs at each output pin. This is inefficient because the number of queues required to perform energy and power dissipation calculations vary according to the number of output pins that may incur a transition caused by an input transition that occurs at a cell. Thus, the method becomes inefficient very quickly when evaluating cells that have many output pins, such as a cell having more than two outputs, because a queue must be maintained for each of the output pins.
Since a complex arc that represents the case where a signal transition occurs at more than one output for a given input transition cannot accurately model the actual sequence of each output transition, the method must model each possible sequence of output pin transitions that can occur. Each possible sequence must be considered because the order of transitions occurring at the output pins cannot be predicted by cell modeling. This greatly increases the inefficiency of the method in calculating energy dissipated since an arc must be generated for each possible output transition sequence for a given input pin transition.
For example, the case where carry-out output 68 and sum output 70 transition in response to an input transition at second input 64 in full adder 60 requires the generation of two arcs to cover all possible sequences that can occur between carry-out output 68 and sum output 70; an arc where carry-out output 68 transitions first and sum output 70 transitions second; and another arc where sum output 70 transitions first and carry-out output 68 transitions second. The need to cover all possible output pin sequences exponentially increases the number of arcs that must be generated.
The increased use and importance of power analysis tools has created a need for new cell libraries. But library creation/generation is also a complex task, resulting in a need to leverage existing cell libraries by providing a power analysis tool that is compatible with EDA tools that provide widely-used cell characterizations, such as arcs, while remaining easy to implement and efficient to use.
Accordingly, there exists a need to provide a power analysis system and tool that are both accurate and efficient yet compatible with the arc-based timing methodology.

Efficient power analysis method for logic cells with many output switchings


A method of fabricating a semiconductor device, includes: removing, after forming solder for forming a plurality of bumps on a semiconductor substrate, an oxide film formed on a surface of the solder while heating the semiconductor substrate with first radiant heat; and heating the semiconductor substrate with an amount of second radiant heat that is greater than the amount of the first radiant heat by holding the semiconductor substrate at a position apart from a front surface of a heater stage at a predetermined distance to reflow the solder from which the oxide film is removed.

1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and an apparatus for fabricating a semiconductor device.
2. Description of the Related Art
In installing a semiconductor device on a printed circuit board, the semiconductor device is encapsulated with resin or the like and the semiconductor device is protected from an external environment, in order to facilitate the handling of the semiconductor device. In mounting the encapsulated semiconductor device, electrodes formed both on the semiconductor device and the printed circuit board are connected to each other using a lead frame. In an early phase of development, the electrodes of the semiconductor device are connected to the lead frame through wires made of gold (Au) or the like. In doing so, it is necessary that the semiconductor device be brought close to the lead frame and placed thereon and space for routing wires be provided between them.
In order to satisfy market requirements for a reduction in the size of semiconductor devices together with requirements for high integration of these semiconductor devices, projecting terminals (in the following, referred to as bumps) are used instead of wire connections.
The term "bump" here means a terminal that is projected from the main surface of the semiconductor device, which is formed by laminating solder on the electrode of the semiconductor device; electrodes are connected to each other through this solder. More specifically, bumps are formed at predetermined positions on the front and rear surface of a plurality of semiconductor chips to be connected, and the bumps formed on the front surface of a semiconductor chip and the bumps formed on the rear surface of another semiconductor chip are aligned and compressed to each other for bonding. With this scheme, it is possible to stack and electrically connect a plurality of semiconductor chips to each other without using wires. According to this connection method using bumps, it is possible that a lead frame is laid on a semiconductor device and the lead frame and the semiconductor device are electrically connected to each other. Thus, space can be saved, and this method is effective for reducing the size of the semiconductor device.
In the forming of bumps, one method that is typical is one in which the electrodes are formed on the semiconductor device and the solder is then plated thereon. However, projections and depressions are formed on the surface of the solder formed by plating, and air bubbles are caught in the depressions which cause a reduction in connection strength if the bumps are connected to the lead frame as they are. In order to prevent this, heat treatment is performed such that solder is heated at a temperature above its melting point to smooth the solder surface before connecting the bumps to the lead frame. In the following, this heat treatment is referred to as reflow.
Various schemes are disclosed concerning reflow. For example, JP11-163036A discloses a method of using radiant heat emitted from a halogen lamp. JP2004-6818A and JP2001-58259A disclose methods performed with conductive heat using a heater.
However, methods using a halogen lamp for a heat source like the method in JP11-163036A separately need a reflecting mirror or a reflector in addition to the lamp, so that there is a problem in that the configuration of a fabrication apparatus becomes complicated.
In the methods disclosed in JP2004-6818A and JP2001-58259A, because a wafer on which semiconductor devices are formed comes into direct contact with the heater, some portions of the wafer come into contact with the heater and some do not come into contact with the heater if there is warpage or the like on the wafer. In this case, variations occur in heating semiconductor devices, causing a problem in that solder cannot be smoothed. In addition, JP2007-294990A discloses a technique concerning an ashing method for a photoresist.

Method of fabricating semiconductor device allowing smooth bump surface