In a dielectric block, an array of three excitation holes, in each of which one opening is a short-circuited end and the other opening is an open-circuited end, are disposed so as to be interdigitally coupled and balanced input-output terminals are provided at the opening of the excitation holes at both ends of the array. A resonator hole is provided so as to be coupled to one excitation hole of the excitation holes at either end of the array. Thus, a compact dielectric filter with balanced input-output terminals is constructed.

1. Field of the Invention
The present invention relates to a dielectric filter and dielectric duplexer used in the microwave band, etc., and to a communication device provided with the dielectric filter or the dielectric duplexer.
2. Description of the Related Art
Up to now, dielectric filters in which internal-conductor-formed holes are provided inside a dielectric block and an external conductor is formed on the outside surface of the dielectric block and which is composed of one stage or a plurality of stages of resonators have been for filters in the microwave band, etc.
In a dielectric filter using such a dielectric block, input-output terminals, which are capacitively coupled to internal conductors, are provided on the outside surface of the dielectric block for inputting and outputting unbalanced signals. Therefore, for example, in order to supply signals to a balanced-input amplifier, unbalanced signals are converted to balanced signals by using a balun (unbalanced-to-balanced converter). However, in such a construction, there are problems in that the insertion loss due to the balun is large and, since a space for the balun is required on the circuit board, the filter cannot be made smaller.
The applicant of the present invention has filed Japanese Patent Application No. 11-314657 and Japanese Patent Application No. 2000-036302 for dielectric filters in which balanced signals can be input and output without any outside help.
In related dielectric filters having balanced input-output terminals, since the axial length of each resonator is long, the required mounting area on a mounting board is inevitably increased. Furthermore, since the balanced input-output terminals are disposed in the vicinity of both open ends of a half wavelength resonator, there is a problem in that the design freedom of the space between balanced input-output terminals is low.
Accordingly, it is an object of the present invention to provide a dielectric filter and dielectric duplexer in which the above problems are solved and the freedom for arranging balanced input-output terminals is increased and which are small as a whole. It is also an object of the present invention to provide a communication device using the dielectric filter or the dielectric duplexer.
According to the present invention, a dielectric filter comprises a dielectric block; an array of three excitation holes provided inside the dielectric block, one opening of each hole being a short-circuited end and the other opening or the vicinity of the other opening being an open-circuited end, the three excitation holes being interdigitally coupled in order along the array; balanced input-output terminals provided at the open-circuited ends of the excitation holes at both ends of the array of three excitation holes; and a resonator hole which is coupled to at least one of the excitation holes at an end of the array of three excitation holes and in which one opening forms a short-circuited end and the other opening or the vicinity of the other opening forms an open-circuited end, the resonator hole being provided inside the dielectric block.
In this way, the array of three excitation holes and the resonator hole coupled to at least one of the excitation holes at an end of the three excitation holes have an axial length substantially equal to a quarter wavelength and, as a result, the dielectric filter can be made smaller as a whole. Furthermore, since the above balanced input-output terminals are provided in the open-circuited ends of the excitation hole at either end of the array of three excitation holes, the terminals can be disposed in a relatively small area.
Furthermore, according to the present invention, a dielectric duplexer comprises a first dielectric filter which is a dielectric filter having the above construction; a second dielectric filter containing another resonator hole which is different from the resonator hole of the first dielectric filter, the second dielectric filter being formed in the dielectric block having the first dielectric filter; a common input-output terminal coupled to the first and second dielectric filters, the common input-output terminal being formed on the dielectric block; and an input-output terminal coupled to the second dielectric filter, the input-output terminal being formed on the dielectric block.
Because of this construction, the dielectric duplexer can be used as an antenna-sharing device, for example, in which a filter to input or output a signal through the balanced input-output terminal is provided.
Furthermore, according to the present invention, in a dielectric duplexer, the input-output terminal coupled to the second dielectric filter and the common input-output terminal are unbalanced input-output terminals.
Because of the construction, the dielectric duplexer can be used as an antenna-sharing device, for example, in which a first filter to input or output a signal through the balanced input-output terminals and a second filter to output or input a signal through an unbalanced input-output terminal are provided and an unbalanced signal is input and output through a common input-output terminal.
Furthermore, according to the present invention, in a dielectric duplexer, the common input-output terminal is the balanced input-output terminals having the above construction.
Because of the construction, a balanced input-output type antenna can be directly used.
In an aspect of the present invention, a communication device comprises the above dielectric filter or the above dielectric duplexer.

Dielectric filter, dielectric duplexer, and communication device


A lead lag damper (10, 11) for a helicopter rotor unit has a rotor and a hub (8), said rotor having N rotor modes, with N being the number of blades. This centered single lead lag damper (10, 11) for the entire rotor unit has an essentially cylindrical shape, with an elastomer material shear element between a first side (7) and a second side (9) having a homogenous resistance to shear deformation and being axially preloaded, so that the lead lag damper (10, 11) acts in a homogenous manner in the rotor inplane eigenmodes. Thus, the lead lag damper (10, 11) acts as a single unit on the critical inplane mode of the rotor, which is having N identical blades (1-4). The elastomeric material is loaded by a uniform shear deformation in contrary to the commonly used oscillatory deformation.

(1) Field of the Invention
The invention relates to a lead lag damper for a main rotor unit of a rotary wing aircraft, e.g. a helicopter, with a rotor and a hub.
(2) Description of Related Art
Each degree of freedom of a rotor can be described by N rotor modes, with N being the number of blades of said rotor. There are cyclic modes (longitudinal and lateral), collective modes and differential modes.
The critical regressive rotor inplane mode is a non-harmonic cyclic mode. Rotary wing aircrafts main rotors feature a lead lag damping device acting on said inplane motion of the rotor blades by transforming shear deformation in the lead lag damping device into heat. Said lead lag damping is necessary for preventing aeromechanical instabilities of the helicopter, so called ground and air resonance caused by an interaction between modes of the fuselage and the regressive rotor inplane mode composed by the lead-lag oscillation of the individual rotor blades as a consequence of a circular rotating displacement of the centre of rotating rotor blades relative to the hub of a helicopter. The design and lay-out of a lead lag damping device depend on the applied rotor concept.
The document U.S. Pat. No. 5,372,478 describes a rotorcraft rotor with blades hinged in flap and lag. A common lag damper system is centered on an axis of rotation of the rotor. A squared shaped damper comprises planar strips with rigid plates superposed along the rotor axis, with elastomer layers. Strips and layers are resiliently interconnected. Each rigid plate of this central common lag damper system is connected only to one distinct blade root, via a dedicated ball joint.
The document U.S. Pat. No. 4,297,078 discloses a helicopter rotor with a rotor head, arranged to support a plurality of rotor blades for rotation about an axis. The rotor head comprises a generally hollow structure. Each rotor blade is supported by an elastomeric bearing arranged to permit blade flap, lead/lag and feathering movements. The support means comprises interconnected inner and outer elastomeric assemblies, the outer assembly being connected to each rotor blade through a common elastomeric lead/lag damper unit which provides inter-blade damping of blade lead/lag movements. The elastomeric assemblies are pre-compressed.
The document EP0424267 describes drag elastic-return damping devices for rotorcraft rotor blades. Such a device comprise a member for elastic return with incorporated damping, of the rotary type and whose functioning is ensured by circumferential shearing of a viscoelastic material highly stable to distortions, such as an elastomer. This ensures an elastic return of the blades to a neutral position in drag. A connecting rod drives, by way of a rotational joint, a lever and an outer armature of the corresponding member in rotation about an inner armature. This inner armature is retained in a fixed position relative to the hub. Flanges are fixed to the inner armature, onto a zone of the periphery of the hub, between two adjacent blades.
The document WO2010068194 describes a rotor system with a lead stop mounted to a spindle and a lead stop plate mounted to a rotor hub arm, this stop being operable to contact the lead stop plate. The rotor hub has a plurality of rigid hub arms.
The document US2007071602 discloses a rotorcraft rotor comprising a hub and at least two blades hinged by respective joints relative to the hub about respective pitch axes and about respective flap axes and about respective lag axes. Each blade is secured to a respective pitch lever. The rotor includes a respective pitch control rod connected to each pitch lever by a first ball joint and a common lag damper system centred substantially on the axis of rotation of the rotor. Connected to each of the blades; the damper system is secured to a respective lateral projection from each blade via a respective second ball joint that is sufficiently close to the first ball joint connecting the pitch rod to the pitch lever for the lag damper system to be relatively insensitive to flap oscillations of the hinged blades. The damper when seen from above is a square frame; each "side" of the frame forms a respective damper unit, these four identical damper units being connected together in pairs.
Said existing concepts for lead-lag dampers of the quoted state of the art have in common that each blade of the rotor has a hinge and an individual elastomeric damping device associated. The elastomeric material of said dampers undergoes a linear shear deformation due to the applied circular rotating displacement. The inplane motion of each of the blades of a rotor has to be taken into account said inplane motion comprising n/rev (n=0, 1, 2, 3 . . . −rev=revolution) and non-harmonic displacements. Said non-harmonic displacements are from the inplane eigenmodes of the blades of a rotor. Said inplane eigenmodes are superposed with said n/rev displacements. The coupling of said circular, non-harmonic rotating displacement with an airframe mode can yield the phenomenon of ground resonance, if the embedded damping is not sufficient.

Lead lag damper for helicopter rotor unit


An overvoltage protection device made by: employing a machining technique to make a through hole through opposing top and bottom walls of a substrate, and then filling an overvoltage protection material in the through hole of the substrate, and then curing the overvoltage protection material, and then coating a flat electrode on each of the top and bottom walls of the substrate over and in connection with top and bottom sides of the overvoltage protection material.

1. Field of the Invention
The present invention relates to overvoltage protection technology and more particularly, to an overvoltage protection device made by: making at least one through hole on a substrate, and then filling an overvoltage protection material in each through hole, and then employing a metallization technique to form a flat electrode on the top and bottom sides of the overvoltage protection material in each through hole.
2. Description of the Related Art
Regular electronic products and their related peripheral devices use many active and passive components. An active (microprocessor or chip) can perform operation and data processing independently. A passive component does not require electrical power to operate and is not capable of power gain. Capacitor, resistor and inductor are the three major passive components intensively used in information, communication and consumer electronics as well as many other industrial products to constitute an electronic control loop.
However, abnormal high voltage and static electricity are harmful to electronic devices and difficult to be eliminated. When an electronic product receives an abnormal high voltage or electrostatic discharge, an unstable condition, such as function failure, may occur. When this problem occurs, the user may have to reset the system, or the internal components may be damaged by the abnormal high voltage or electrostatic discharge. To avoid this problem, an overvoltage protection device may be used. An overvoltage protection device is a passive component intensively used in cell phone, motherboard, notebook computer, digital camera and etc. to protect the internal electronic components of the electronic product against any abnormal high voltage and electrostatic discharge, for example, to protect the LED of a backlight module of an electronic product against abnormal high voltage and electrostatic discharge.
Further, in a conventional LED device, LED chips are installed in a cooling substrate, and gold or aluminum wires are bonded to electrically connect the electrodes of the LED chips to positive and negative electrodes of the cooling substrate, and overvoltage protection device, for example, Zener diode are bonded to the cooling substrate by means of SMT or flip-chip technology. Alternatively, low-temperature cofired ceramics may be directly formed in the surface of the cooling substrate, and then gold or aluminum wires are bonded to electrically couple the overvoltage devices to positive and negative electrodes of the cooling substrate for enabling the overvoltage protection devices to protect the LED chips against abnormal high voltage and electrostatic discharge.
The aforesaid method of coupling Zener diodes in parallel to LED chips to form an overvoltage protection loop can effectively protect the LED chips against abnormal high voltage and electrostatic discharge. However a LED product of this design does not allow positioning of the optical axis at the center. A certain area of the cooling substrate must be left for the installation of the overvoltage protection devices, shortening the effective reflective area, lowering the light extraction and heat dissipation efficiency and complicating optical axis design. If aluminum nitride, high purity aluminum oxide or other high conductivity material is used, or a crystal-pulling technique is employed, a vacuum or reduction sintering process is necessary to sinter the material at a high temperature (1600˜1700° C.). It is difficult and expensive to make an embedded overvoltage protective device under this high temperature condition.
Therefore, there is a strong demand to provide an overvoltage protection device fabrication method for making an overvoltage protection device for LED product by embedding a high thermal conductivity type overvoltage protection material in a cooling substrate that effectively protects the LED chips against overvoltage and electrostatic discharge, keeps the surface of the substrate smooth, allows free arrangement of the LED chips to keep the optical axis at the center of the substrate, and improves light extraction and heat dissipation efficiency.

Overvoltage protection device and its fabrication


A rare gas-halide excimer laser uses a buffer gas consisting of from 5 to 50% by volume helium the balance being neon.

Excimer lasers are molecular lasers which have a metastable excited state. The lasing medium is a gas which usually consists of active components such as a halogen/rare gas combination in an inert buffer such helium or neon. Heretofore the buffer gas has usually been either pure neon or pure helium. This known choice of neon or helium gives the user the option between a high cost gas with high output power or a low cost gas with a lower laser power output. For example, the use of the relatively cheaper helium as the buffer gas typically yields only 60 to 70% of the power achieved with a pure neon buffer gas.
It is known from European Patent Publication No. 0430411 for a gas mixture for an excimer laser to contain about 99% of one or more of helium and neon. However, this document does not give details of the percentage of helium or neon in the inert buffer. U.S. Pat. No. 4674099 describes a typical lasing gas mixture including a diluent rare gas such as helium and/or neon in concentrations in the order of 95%. Again, this document does not give details of any helium/neon mixture.
For the avoidance of doubt the expression "buffer gas" used throughout this specification is intended to embrace the inert gas(es) which represent the balance of the lasing gas mixture excluding the active lasing constituents.
Laser gases are expensive and efforts are continuously being made to reduce costs in this area.


A highly active hydroprocessing catalyst that comprises an inorganic oxide support particle having been impregnated with a metals-impregnation solution comprising a complexing agent and a hydrogenation metal that is further incorporated with an organic additive blend.

Hydroprocessing catalysts are used in processes to remove organic sulfur and nitrogen compounds from hydrocarbon feedstocks that are typically derived from the distillation of crude petroleum. In these processes the organic sulfur and nitrogen compounds are catalytically converted in the presence of hydrogen respectively to hydrogen sulfide and ammonia to then subsequently be removed from the hydrotreated feedstock.
Typical hydroprocessing catalysts include a carrier having deposited thereon a Group VIB metal, such as molybdenum and tungsten, and a Group VIII metal, such as nickel and cobalt. Phosphorus may also be present in the hydroprocessing catalyst. One method of preparing a hydroprocessing catalyst includes impregnating a carrier with the hydrogenation metal components followed by calcining the impregnated carrier to convert the metal components into oxides. The calcined catalyst is then subjected to a sulfidation treatment to convert the metal oxides to metal sulfide. Presented in the prior art are many different catalyst compositions that are useful in hydroprocessing of hydrocarbon feedstocks. For instance, U.S. Pat. No. 9,156,029 (Gabrielov et al.) discloses a hydroprocessing catalyst having a support loaded with an active metal precursor, an amine component, and a non-amine containing polar additive. The catalyst is made by incorporating a metal component into the support material to give a metal-loaded support followed by impregnation with the amine compound and non-amine containing polar additive. This impregnated composition is then treated with hydrogen and a sulfur compound and used in the hydrotreating of a hydrocarbon feedstock.
Another catalyst found to be useful in hydroprocessing of hydrocarbon feedstocks is disclosed in U.S. Pat. No. 8,262,905 (Gabrielov et al.). This catalyst is prepared by incorporating a metal component into a support material to provide the support material loaded with the metal followed by impregnation with a hydrocarbon oil and a polar additive. The impregnated composition is then treated with hydrogen and a sulfur compound and used in the hydrotreating of a hydrocarbon feedstock.
U.S. Pat. No. 9,211,536 (Gabrielov et al.) discloses a hydroprocessing catalyst having exceptional hydrodesulfurization and hydrodenitrogenation activity and good catalytic stability. This catalyst includes a shaped support formed from a mixture of inorganic oxide powder and catalyst fines. Incorporated into the shaped support that has been dried and calcined are a chelating agent, at least one catalytic metal, and a polar additive. The polar additive is impregnated into the dried chelant treated metal-incorporated support. This composition is then treated with hydrogen and a sulfur compound and used in the hydrotreating of a hydrocarbon feedstock.
U.S. Pat. No. 9,376,637 (Gabrielov et al.) discloses another exceptional hydroprocessing catalyst. This catalyst comprises a shaped support that has had a metal solution with a chelating agent incorporated into the shaped support by a single-step impregnation. Incorporated into this dried metal-incorporated support is a polar additive followed by treatment with hydrogen and sulfur to provide the catalyst composition. This activated additive impregnated composition may suitably be used in hydrotreating of distillate feedstocks.
There is an ongoing need to find new and improved hydroprocessing catalysts with enhanced catalytic properties. Industry is perpetually searching for better hydroprocessing catalyst compositions that are highly active and stable when used in the treatment of petroleum-derived hydrocarbon process streams that have high concentrations of sulfur and nitrogen.

This patent is subject to a terminal disclaimer.

Hydroprocessing catalyst having an organic additive with metals incorporated using chelant and method of making and using such catalyst


An apparatus and method manages timings of Node Bs by performing a first-step cell search on primary synchronization channel signals transmitted from the Node Bs, and stores frame boundary indexes representing frame boundaries for the Node Bs by performing a second-step cell search on secondary synchronization channel signals received from the Node Bs. Upon receiving a third-step cell search start command, the apparatus and method compares frame boundary timing corresponding to each of the frame boundary indexes to a current timing from a reference timer, performs a third-step cell search on hypotheses corresponding to the frame boundary indexes at a next slot boundary following the current timing by using scrambling codes in a Node B code group obtained by the second-step cell search, and provides a third-step cell search complete information after completing the third-step cell search on hypotheses corresponding to the frame boundary indexes.

1. Field of the Invention
The present invention relates generally to a cell search apparatus and method in a mobile communication system, and in particular, to an apparatus and method for performing a multisearch operation on a plurality of cells to be searched.
2. Description of the Related Art
In general, a mobile communication system is classified into a synchronous system developed and used in the United States and an asynchronous system developed and used in Europe. With the rapid development of the mobile communication industry, there have been demands for a future mobile communication system which can provide not only a voice service but also a multimedia service including data and image services. 3rd Generation Partnership Project (3GPP) has been standardizing both the synchronous future mobile communication system and the asynchronous future mobile communication system. The synchronous future mobile communication system is called a "code division multiple access-2000 (CDMA-2000) system," and the asynchronous future mobile communication system is called a "wideband-CDMA (W-CDMA) system." The W-CDMA mobile communication system comprises UMTS (Universal Mobile Telecommunications System) Terrestrial Radio Access Networks (UTRANs) that perform an asynchronous operation between Node Bs. Therefore, in order to identify the Node Bs, unique scrambling codes are assigned to the Node Bs. For example, if the number of cells, or Node Bs, constituting the UTRAN is 512, each of the 512 Node Bs is assigned its own unique scrambling code among 512 scrambling codes, for its identification. Since a Node B transmits a signal with a scrambling code for its identification, a user equipment (UE) must be able to identify a scrambling code for the Node B in order to normally receive a signal provided from the Node B.
That is, in order to normally receive a signal provided from a Node B, a UE must determine a scrambling code of a signal received at the highest energy among signals received from its neighboring Node Bs, and such a process of determining a scrambling code is called "cell search." The cell search is performed in various ways according to circumstances, and includes (i) initial cell search for acquiring pseudo noise (PN) code timing by a UE upon power on, (ii) multipath search for detecting a multipath signal component of a received signal for rake demodulation while continuously maintaining the acquired PN code timing, (iii) neighbor cell search for searching target neighbor cells to which the UE is to be handed off when the UE is located in a handoff region, and (iv) re-acquisition for re-acquiring PN code timing, which was lost when the UE selects a slotted mode in an idle state or wakes up from a sleep state.
In the W-CDMA mobile communication system, a UE, as stated above, must perform cell search by measuring a phase of each of all scrambling codes that are assignable to Node Bs, i.e., 512 scrambling codes, in order to determine a scrambling code for a Node B to which the UE itself belongs (hereinafter, referred to as a "source Node B"). However, such a cell search algorithm for determining phases of all scrambling codes for the Node Bs one by one requires a long cell search time. To solve this problem, a new multistep cell search algorithm has been proposed.
The multistep cell search algorithm will now be described below.
Node Bs constituting the W-CDMA mobile communication system are assigned their own unique cell identification codes, or scrambling codes, for identification of the Node Bs. A UE identifies the Node Bs with the assigned scrambling codes. It will be assumed herein that the number of cells constituting the W-CDMA mobile communication system is 512 and one cell exists in each Node B, so the number of Node Bs constituting the W-CDMA mobile communication system becomes 512. However, the Node B may employ one or more cells. In this case, the 512 Node Bs are assigned their own unique scrambling codes, and a UE identifies the Node Bs using the unique scrambling codes assigned to the Node Bs.
Currently for a cell search, in order to search a source Node B, a UE must perform a cell search on each of the 512 Node Bs constituting the W-CDMA mobile communication system. Since performing a cell search on each of the 512 Node Bs constituting the W-CDMA mobile communication system is equivalent to measuring a phase of each of all the scrambling codes for the 512 Node Bs, the UE requires a large amount of time to perform the cell search. As a result, it is inefficient to apply the existing cell search algorithm to each of the Node Bs constituting the W-CDMA mobile communication system. Therefore, the UE employs the multistep cell search algorithm. In order to realize the multistep cell search algorithm, a plurality of Node Bs, e.g., 512 Node Bs, belonging to the W-CDMA mobile communication system are divided into a predetermined number of groups, e.g., 64 groups Group#0 to Group#63. The divided 64 Node B groups are assigned their own unique group identification codes, for identification of the Node B groups. In addition, each Node B group includes 8 Node Bs, and the 8 Node Bs are assigned their own unique scrambling codes for spreading a common pilot channel (CPICH), so that the UE can search for its source Node B, using the assigned scrambling codes.
The multistep cell search algorithm includes in the first-step a search, in the second-step a cell search and in the third-step another cell search. In the first-step cell search process, a UE receives primary synchronization channel (P-SCH) signals transmitted from a Node B and acquires slot timing for a signal received at the highest power among the received P-SCH signals. In the second-step cell search process, the UE acquires slot synchronization based on the slot timing information acquired in the first-step cell search process, and then acquires frame synchronization and detects a Node B group to which the UE belongs by receiving a secondary synchronization channel (S-SCH) transmitted from the Node B. In the third-step cell search process, the UE finally searches for its source Node B using a scrambling code for the Node B by receiving a CPICH signal transmitted from the Node B based on the frame synchronization and Node B group information acquired in the second-step cell search process.
The multistep cell search will now be described with reference to FIG. 1.
FIG. 1 illustrates an example of a structure of synchronization channels in a general W-CDMA mobile communication system. Referring to FIG. 1, in the W-CDMA mobile communication system, a searcher in a UE uses a synchronization channel (SCH) and a common pilot channel (CPICH), for synchronization. Node Bs transmit the CPICH using their own unique scrambling codes. A period of the scrambling code is equal to a one-frame length. In the W-CDMA mobile communication system having the channel structure illustrated in FIG. 1, as many Gold codes (not shown) having a period of 218-1 as a one-frame length are used as the unique scrambling codes. Only M (=512) Gold codes among all available Gold codes are used. The SCH, a downlink channel used for cell search by the UE, comprises two subchannels primary SCH (P-SCH) and secondary SCH (S-SCH). Since each time slot of the P-SCH and S-SCH comprises 2,560 chips and 15 time slots constitute one radio frame, one radio frame, therefore, comprises 38,400 chips. Further, as illustrated in FIG. 1, the P-SCH and S-SCH are transmitted by N chips, i.e., 256 chips, amounting to 1/10 of the chips transmitted over one time slot, at the beginning of each time slot. In addition, as orthogonality is maintained between the P-SCH and the S-SCH, it is possible to overlap the two channels during transmission. The P-SCH, a channel over which the 512 Node Bs constituting the W-CDMA mobile communication system transmit the same code, transmits a primary synchronization code (PSC) acp. Further, the P-SCH transmits as much primary synchronization code as 1/10 period, i.e., 256 chips, of a time slot at each time slot. The UE acquires the slot timing from a Node B by receiving a P-SCH signal transmitted from the Node B.
The Node B transmits an S-SCH signal along with a P-SCH signal. If the 512 Node Bs constituting the W-CDMA mobile communication system are divided into 64 Node B groups, the S-SCH transmits a secondary synchronization code (SSC) acsi,k, i.e., a Node B group identification code to which the Node B belongs. The secondary synchronization code is a 15-symbol sequence having a 256-chip length. In the secondary synchronization code, acsi,k, i (=0, 1, . . . , 63) represents the number of Node B groups, i.e., the number of scrambling code groups, where k (=0, 1, . . . , 14) represents a time slot number. Further, the secondary synchronization code is selected from 16 code groups having a 256-chip length. A sequence of the secondary synchronization code represents a code group to which a downlink scrambling code for a corresponding Node B belongs. The code group further represents a group of codes for generating the Node B group identification code. The secondary synchronization channel also transmits the secondary synchronization code using 1/10 period of a time slot, i.e., using 256 chips, at each time slot. The UE detects a Node B group which is its source Node B and synchronizes with a frame boundary by receiving a secondary synchronization channel signal transmitted from the Node B.
The Node B group identification code is used to determine a group to which the Node B belongs. A comma-free code is typically used as the Node B group identification code. The comma-free code comprises 64 codewords, and each codeword comprises 15 symbols. The 15 symbols are transmitted every frame. However, as mentioned above, values of the 15 symbols are mapped to one of the secondary synchronization codes acsi,k of acsi,0, acsi,1, . . . , acsi,15 before being transmitted. That is, as illustrated in FIG. 1, an ith secondary synchronization code corresponding to a symbol value i is transmitted every time slot. In addition, 64 codewords of the comma-free code identify 64 code groups. The comma-free code is characterized such that the cyclic shift of each codeword is unique. Therefore, it is possible to acquire information on a code group, i.e., a Node B group, where the UE belongs, and information on frame synchronization by receiving a secondary synchronization channel signal for a period of several time slots, correlating secondary synchronization codes with a secondary channel signal for the period of several time slots, and performing a cyclic shift operation on each of the 64 codewords 15 times. The term "frame synchronization" means synchronization on timing or phase within one period of a scrambling spreading code for a spread spectrum system. In the existing W-CDMA mobile communication system, one period of a spreading code and a length of a frame are both 10 ms, so this is called "frame synchronization."
After performing the first-step cell search process and the second-step cell search process, the UE can acquire information on slot synchronization, Node B group identification code and frame synchronization through the P-SCH and S-SCH. However, since the UE cannot distinguish a scrambling code for its source Node B from 8 other Node B scrambling codes within a code group based on the acquired Node B group identification code, scrambling code synchronization is not completed achieved yet. Therefore, the UE can identify a scrambling code to be used among the 8 scrambling codes by performing correlation on each of the 8 scrambling codes belonging to the code group for the CPICH via a third-step cell search process.
The UE must periodically measure the strength of the signals transmitted from Node Bs neighboring its source Node B, in order to receive an optimal multipath signal from the Node B in a radio channel environment or a handoff situation. In this case, the UE acquires timing information of neighbor Node Bs by the multistep cell search algorithm or from the current Node B in service, receives CPICH from each of the corresponding Node Bs, and periodically performs correlation on each of the received CPICH signals. Herein, a process of periodically measuring strength of signals from Node Bs neighboring a source Node B to acquire the timing information of the neighboring Node Bs will be referred to as a "multipath search" in order to distinguish this process from the above-stated cell search process that is performed before the UE acquires timing of the neighbor Node Bs.
Generally, the UE identifies signals from Node Bs to which it may probably move, by cell search, and continuously manages the Node B signals through the multipath search. Further, the UE demodulates valid multipath signal components, i.e., valid multipath signals, among the signals received by the cell search and multipath search. In the case of the multipath search, the UE should be able to perform a high-speed search in order to promptly respond to an abrupt variation in channel conditions. The multipath search calculates correlation values for all hypotheses at stated intervals in a window and then detects a plurality of correlation values which are peak values and larger than or equal to a predetermined threshold value. Then, scrambling code timings having the detected correlation values become timings of multipath signal components.
As stated above, the W-CDMA mobile communication system acquires scrambling code synchronization while continuously performing the third-step cell search. That is, a UE acquires time slot synchronization with P-SCH in the first-step cell search process, and acquires frame synchronization and scrambling code group information, i.e., group information of its source Node B, with S-SCH in the second-step cell search process. Finally, in the third-step cell search process, the UE detects a scrambling code assigned to a corresponding Node B among the 8 scrambling codes within the determined scrambling code group by searching CPICH after the frame synchronization is achieved. In order to perform the third-step cell search process in this manner, the UE must determine reference timing for where it will start the first-step cell search process, and reference timing for where it will start the second-step cell search process after acquiring time slot synchronization as the first-step cell search process is completed. That is, in order to identify a scrambling code group and acquire frame synchronization in the second-step cell search process, the UE must determine reference timing where it will perform cyclic shift so as to determine a frame boundary from the number of cyclic shifts performed during codeword decoding. In addition, after acquiring scrambling code group information and frame synchronization information through the second-step cell search process, the UE must determine reference timing for where it will start the third-step cell search process.
However, the UE must continuously perform such a cell search process for communication with Node Bs instead of performing the search only once at the initial cell search. Therefore, in order to calculate and manage a timing difference between a frame boundary of a signal currently demodulated by a UE and a frame boundary of signals received from the same Node B or different Node Bs, that may probably be demodulated later, a specified criterion is required. That is, it must be possible to calculate a timing difference between a frame boundary of neighboring Node Bs, detected through a cell search process, and a frame boundary of other Node Bs, detected by the previous cell search. In the multipath search, a UE calculates a correlation for scrambling codes of Node Bs to which the UE may probably move, and measures the strength of signals received from the Node Bs. However, since the Node Bs have different frame boundaries, the UE must initialize scrambling codes to match phases of the scrambling codes of the Node Bs before calculating the correlation. Therefore, it is necessary to provide reference timing for initializing the scrambling codes of the Node Bs. Multipath signal components determined to be valid by the cell search and the multipath search are assigned to a modulator or finger of a UE, for demodulation. The demodulator of the UE must initialize a scrambling code of a corresponding Node B synchronized with a frame boundary of a corresponding multipath signal, and provide reference timing for initializing the scrambling code. A device for proving the reference timing is a reference counter, and the reference counter continuously performs a count operation at periods of 10 ms by managing timing by the time slot. The count unit is 1/n chips, where n is the number of oversamples.
A mask operation or a slew operation is used to currently perform search on hypotheses to be searched when performing the third-step cell search or the multipath search. However, since the W-CDMA mobile communication system is an asynchronous mobile communication system, a UE has difficulty in performing a cell search on a plurality of Node Bs while in motion, and information that the UE holds for the cell search is limited. Particularly, the UE cannot store all mask values chip by chip (or in a chip unit) within 10 ms which is a unit of managing the reference timing. In addition, when a UE is designed to usually start the third-step cell search or the multistep search at a frame boundary, the UE should always wait for a frame boundary, suffering a loss in terms of demodulation timing, i.e., search rate. That is, the multipath search increases demodulation performance by demodulating and combining signals received through multiple paths, and when the UE usually starts the multipath search at a frame boundary, a delay occurs in actual combining due to the waiting time, causing a decrease in demodulation performance. Therefore, the UE suffers a loss in terms of demodulation timing.
Therefore, in general, a central processing unit (CPU) of the UE detects current timing by reading a current index value of the reference counter, determines an actual point of time where a searcher will operate, based on the detected current timing, and then sets a mask value for a phase of a corresponding scrambling code and activates the searcher.
As described above, in the third-step cell search and the multipath search, the CPU plays a part in determining an operation point of a searcher, and activates the searcher at the determined point of time. Of course, if the CPU fixes an operation point to a specific point instead of variably determining the operation point according to circumstances, the searcher will be usually activated at the fixed specific point of time. However, when cell search is performed in a channel environment, the search rate serves as an important parameter in the signal demodulation performance. In this case, the search rate must be high so that the UE can adaptively cope with a variation in the radio channel environment. However, the search rate is determined according to a plurality of parameters, such as hardware complexity, CPU speed, and software task scheduling. Therefore, in the case where there exists N search targets, in order to reduce a software load, it is possible to write by hardware all parameters related to the N search targets at once, thereby enabling a corresponding hardware to sequentially search the N search targets. The operation of searching by hardware for a plurality of search targets in a lump will be referred to as a "multisearch operation."
In the W-CDMA mobile communication system, a counter operating in a frame unit (=10 ms), i.e., a reference counter, is used to continuously calculate a timing difference between Node Bs, i.e., a difference between frame boundaries. Herein, the reference counter will be referred to as an "index counter," since an output of the reference counter is used as reference timing for a cell searcher, a multipath searcher and a multipath signal demodulator.
The index counter continuously operates, after being initialized by a CPU upon powering a UE. If a resolution of a searcher is 1/K chip, the index counter should also have a resolution of over 1/K chip. In the 3GPP specification, a length L of one frame is L=38,400 chips, the number M of time slots constituting one frame is M=15, and a length N of one time slot is N=2,560 chips. The length L of one frame becomes a period of one frame, and the length N of one time slot becomes a period of one time slot. A resolution of the searcher represents accuracy of the search, and is used to search for a more accurate synchronization point. Therefore, the minimum unit is 1 chip. In order to detect an accurate synchronization point, it is preferable to check a plurality of hypotheses or sampling points per chip and select an optimal point among the points.
FIGS. 2 and 3 illustrate different examples of a general index counter.
Referring first to FIG. 2, an index counter 210 comprises a slot counter 212 for counting time slots constituting one frame and a lower counter 214 for counting the number, K×N−1, of chips corresponding to a length of a predetermined number of time slots. A count value by the slot counter 212 ranges from 0 to M−1, and a count value by the lower counter 214 ranges from 0 to K×N−1. As stated above, in the W-CDMA mobile communication system, one frame comprises 15 time slots. The M, in this case, becomes 15. Further, in the W-CDMA mobile communication system, one time slot comprises 2,560 chips. The N, in this case, becomes 2,560. The lower counter 214 is reset to 0, when its count value becomes K×N. The slot counter 212 increases its count value by 1, each time the lower counter 214 counts a multiple (K×N) of N, i.e., counts the number N of chips constituting one time slot. The slot counter 212 is reset to 0, when the number of time slots constituting one frame is counted, i.e., the count value becomes M.
Referring now to FIG. 3, an index counter 310 has a structure for deriving count values of a slot counter 314 and a lower counter 316, using a single counter. The slot count 314 and the lower count 316 of FIG. 3 are substantially identical in function to the slot counter 212 and the lower counter 214 of FIG. 2, although they are represented by different reference numerals. A counter 312 constituting the index counter 310 counts from 0 to J×K×L−1, where J is an integer (J=1, 2, 3, . . . ). Count values of the slot counter 314 and the lower counter 316 are derived from a value counted by the index counter 310 in accordance with Equation (1).Slot count value=└(count value)/(K×N)┘ modulo M Lower count value=(count value) modulo (K×N)  Equation (1)
In Equation (1), └x┘ represents a maximum integer smaller than a given value "x," and "a modulo b" represents a remainder obtained by dividing "a" by "b."
Since the index counters 210 and 310 of FIGS. 2 and 3, respectively, operate at periods of a frame length, frame boundary points of all asynchronous cells (or Node Bs) are mapped to either specific count values of the slot counter 212 and the lower counter 214 in the index counter 210, or specific count values of the slot counter 314 and the lower counter 316 in the index counter 310. When the frame boundary point of the index counter 210 or 310 is defined as a reference point, a position of a frame boundary point of each asynchronous cell is called a "frame timing index" of the corresponding cell. Therefore, if a frame timing index of each cell is given, it is possible to calculate an offset between the cells. Here, the term "offset" means a difference between frame boundary points of the asynchronous cells.
In addition, it is possible to count a time slot length with the lower counter 214 or 316 of the index counters 210 and 310, respectively. Therefore, slot boundary points of all asynchronous cells can be mapped to a specific count value of the lower counter 214 or 316 in the index counters 210 and 310. When a slot boundary point of the lower counter 214 or 316 is defined as a reference point, a position of a slot boundary point of each asynchronous cell is called a "slot timing index" of the corresponding cell. Therefore, if a slot timing index of each cell is given, it is possible to calculate an offset between slot boundary points of the cells.
FIG. 4 illustrates an example of a timing relationship between an index counter and asynchronous cells. Specifically, FIG. 4 illustrates a timing relationship between two asynchronous cells Cell_A and Cell_B, by way of example. Referring to FIG. 4, an index counter's frame boundary 410, which is a reference point for determining a frame-boundary of the cells, may correspond to a count start point of the index counters 210 and 310. The slot counter 212 or 314 of the index counters 210 and 310 counts index counter's slot boundaries 412 up to M−1 after being reset to 0 at the index counter's frame boundary 410. The index counter's slot boundary 412, which is a reference point for determining slot boundaries in one frame, may correspond to a count start point of the lower counter 214 or 316 of the index counters 210 and 310. The lower counter 214 or 316 restarts counting, after being reset to 0 at the index counter's slot boundary 412.
A Cell A's slot boundary 426 is a point where the first-step cell search process is completed after the first-step cell search process is performed at a given time point T1=0. "T1=0" means that a count value of the lower counter 214 or 316 is 0. In this case, the first-step cell search process is performed at any one of the index counter's slot boundaries 412. If the Cell A's slot boundary 426 is determined, a Cell A's slot timing index 430 is determined by an offset between the Cell A's slot boundary 426 and the give time T1=0. For example, the Cell A's slot timing index 430 is determined by a count value of the lower counter 214 or 316 at the Cell A's slot boundary 426.
A Cell B's slot boundary 424 and a Cell B's slot timing index 428 are determined in the same process as used for the Cell A's slot boundary 426 and the Cell A's slot timing index 430. The Cell A's slot boundary 426 and the Cell B's slot boundary 424 correspond to one of count values 0 to NK−1, counted by the lower counter 214 or 316. An offset between the Cell A's slot boundary 426 and the Cell B's slot boundary 424 is defined as a slot offset 432. A Cell A's frame boundary 414 is determined by the number of cyclic shifts of codewords for a code group having a maximum correlation energy by performing the second-step cell search process at the Cell A's timing index 430. That is, a point spaced apart from the start point or the Cell A's slot timing index 430 of the second-step cell search process by a length of as many slots as the number x of cyclic shifts becomes the Cell A's frame boundary 414. A Cell A's frame timing index 418 is defined as a value counted by the slot counter 212 and the lower counter 214, or the slot counter 314 and the lower counter 316 at the Cell A's frame boundary 414.
A Cell B's frame boundary 416 and a Cell B's frame timing index 420 are determined using the same process that was used for the Cell A's frame boundary 414 and the Cell A's frame timing index 418. The Cell A's frame boundary 414 and the Cell B's frame boundary 416 are determined by one of count values 0 to M−1, counted by the slot counter 212 or 314, and the Cell A's slot boundary 426 or the Cell B's slot boundary 424. An offset between the Cell A's frame boundary 414 and the Cell B's frame boundary 416 is defined as a frame offset 422.
FIG. 5 illustrates an example of a cell search apparatus for a UE in a general W-CDMA mobile communication system. Referring to FIG. 5, a controller 510 controls an overall operation for cell search. Here, the controller 510 is identical in operation to the above-stated CPU. An index counter 514, having the structure illustrated in FIGS. 2 and 3, performs a counting operation stated above. A memory 512 stores a value counted by the index counter 514 in response to a save command from the exterior. The save command is divided into a lower count save command from a first-step searcher 518, a slot count save command from a second-step searcher 522, and a count save command from the controller 510. The memory 512 provides the controller 510 with the stored count value in response to the count save command from the exterior.
A first-step operation signal generator 516 generates a first-step search operation signal based on a count value provided from the index counter 514 in response to a first-step search command received from the controller 510. A first-step searcher 518 is initialized in response to an initialization command from the controller 510, and performs a first-step search operation on a received signal in response to the first-step search operation signal from the first-step operation signal generator 516. After completing the first-step search operation, the first-step searcher 518 provides the search result by the first-step search operation to the controller 510.
A second-step operation signal generator 520 generates a second-step search operation signal based on the count value provided from the index counter 514 in response to a second-step search command and a slot timing index by the first-step search operation, received from the controller 510. A second-step searcher 522 is initialized in response to an initialization command from the controller 510, and performs a second-step search operation on the received signal in response to the second-step search operation signal from the second-step operation signal generator 520. The received signal indicates a multipath signal, which is determined as a valid signal by the first-step search. After completing the second-step search operation, the second-step searcher 522 provides the search result by the second-step search operation to the controller 510. Meanwhile, the second-step searcher 522 commands the memory 512 to store a slot count value counted by the index counter 514, at a specific time point during the second-step search operation. For example, the second-step searcher 522 commands the memory 512 to store the slot count value counted by the index counter 514, at a point where the second-step search operation is started or a point where the second-step search operation is completed.
A third-step operation signal generator 524 generates a third-step search operation signal based on the count value provided from the index counter 514 in response to a third-step search command and the search result by the second-step search operation or a third-step search start point by a hypothesis for the second-step search result, received from the controller 510. A third-step searcher 526 is initialized in response to an initialization command from the controller 510, and performs a third-step search operation on the received signal in response to the third-step search operation signal from the third-step operation signal generator 524. The received signal means a multipath signal which is determined as a valid signal. After completing the third-step search operation, the third-step searcher 526 provides the search result by the third-step search operation to the controller 510. The controller 510 can determine a scrambling code for a target cell to be searched based on the search result from the third-step searcher 526.
A multipath operation signal generator 528 generates a multipath search operation signal based on the count value provided from the index counter 514 in response to a multipath search command and a multipath search start point, received from the controller 510. A multipath searcher 530 is initialized in response to an initialization command from the controller 510, and performs a multipath search operation on the received signal in response to the multipath search operation signal from the multipath operational signal generator 528. The received signal indicates a multipath signal, which is determined as a valid signal. After completing the multipath search operation, the multipath searcher 530 provides the search result by the multipath search operation to the controller 510.
A plurality of demodulation finger operation signal generators 532, 536 and 540 each generate a demodulation finger operation signal based on the count value provided from the index counter 514 in response to a finger demodulation command and a demodulation start point, received from the controller 510. The demodulation start point is a frame timing index indicating a frame boundary based on a scrambling code of a corresponding multipath signal to be demodulated. A plurality of demodulation fingers 534, 538 and 542 each are initialized in response to a corresponding initialization command from the controller 510, and perform demodulation on the received signal in response to the demodulation finger operation signals from the demodulation finger operation signal generators 532, 536 and 540. The received signal indicates a valid multipath signal, and the scrambling operation includes an initialization operation on the scrambling code.
However, the above-stated general cell searcher sequentially searches all search targets from the first search target to the last search target in the first-step cell search process, second-step cell search process, third-step cell search process and multipath search process, instead of multi-searching all the search targets in a lump. That is, a CPU writes search parameters for the first search target in the cell searcher. Thereafter, the cell searcher informs the CPU of a completed search on the first search target. The CPU then reads the completed search result provided by the cell searcher. Thereafter, as described in conjunction with the first search target, even for the next search target, the CPU writes search parameters for the corresponding search target in the cell searcher. Thereafter, the cell searcher informs the CPU of a completed search on the corresponding search target. The CPU then reads the completed search result by the cell searcher. In this manner, the CPU repeatedly performs a write operation for cell search and/or a read operation for reading search results, each time a search on each of all the search targets is completed. However, since the CPU performs a plurality of software tasks while controlling the overall operation of a UE, the repetition of the write and read operations for a cell search serves as a heavy load in operation of the CPU.

Cell search apparatus and method for supporting multisearch functions in a mobile communication system


A video signal processing circuit of a single chip color camera including a color separation filter for performing a color separation on incident light passing therethrough so as to output color separated light, a solid state pickup device for picking up the color separated light passed through the color separation filter and outputting a video signal, main circuit means for generating a first luminance signal, a second luminance signal, a first color difference signal, and a second color difference signal from the video signal, compensating signal generating means for obtaining a compensation signal from the first and second color difference signals, operational means for applying the compensation signal to the first luminance signal to produce as output luminance signal, and color temperature detection means for detecting a color temperature of the incident light and outputting a DC control voltage so as to determine the compensation signal.

The present invention generally relates to a video signal processing circuit of a video camera, and more particularly relates to a video signal processing circuit of a single chip colour camera which employs a solid state pickup device such as a charge coupled device (hereinafter referred to as a CCD).
An example of the conventional video signal processing circuit of the single chip colour camera is described with reference to FIG. 7. FIG.7 shows a system block diagram of a signal processing circuit 20 of the single chip colour camera which employs the CCD. Due to incident light from a camera lens (not shown) an electric charge is generated and accumulated in a CCD image sensor 12. The accumulated electric charge is read out from the CCD image sensor 12 responsive to a horizontal driving pulse .phi.H and a vertical driving pulse .phi.V. The read out accumulated charge is inputted to a sample and hold circuit 13 in a form of CCD output gate reset pulse .phi.R of approximately 0.6 volts p-p being superposed with a video signal of approximately 0.1 volt p-p. The sample and hold circuit 13 transforms the CCD output gate reset pulse .phi.R superimposed with the video signal into a continuous signal and supplies the continuous signal to an automatic gain control circuit (hereinafter referred to as an AGC circuit) 14. The AGC circuit 14 has a variable gain of 0 to 9 dB for example, and operates so that when an iris within the single chip colour camera is opened, the AGC circuit 14 adjusts the video signal input therein to a suitable level, and supplies the video signal subjected to the adjustment to low pass filters (hereinafter referred to as LPF) 15 and 16, and a band pass filter (hereinafter referred to as BPF) 17.
An explanation is now given of an operation of processing a luminance signal from the video signal. The LPF 15 has a cut-off frequency of approximately 3.2 MHz, and accordingly a luminance signal Y.sub.H is obtained by the LPF 15. In addition, a horizontal resolution of up to approximately 270 lines can be determined by the LPF 15. At a following stage, an equalizer 24 compensates a time difference between the luminance signal Y.sub.H and a colour signal which is separately processed from the video signal as described later and thus adds a time delay of approximately 0.4 .mu.sec to the luminance signal Y.sub.H. Next, a clamping circuit 25 determines a set-up value of the luminance signal, and thereafter a gamma compensation circuit 26 determines a .gamma. characteristic, that is a .gamma. value, for determining an output characteristic of the luminance signal. The .gamma. characteristic of the signal obtained from the CCD image sensor 12 is such that .gamma. is approximately equal to 1. However, the gamma compensation circuit 26 is designed to perform a compensation so as to obtain a gamma value of 0.45, and therefore compensates the luminance signal Y.sub.H output from the single chip colour camera to the gamma value of 0.45. Following the gamma compensation circuit 26, a trap circuit 31 removes a cross-talk component of a colour signal of 3.97 MHz from luminance signal Y.sub.H, and thereafter supplies the luminance signal Y.sub.H to a delay circuit 32 and an operational circuit 33. A horizontal contour compensation signal for compensating a horizontal contour of the luminance signal Y.sub.H is produced through the delay circuit 32 and a differential amplifier accommodated in the operational circuit 33. The operational circuit 33 adds the contour compensation signal to the luminance signal Y.sub.H and thereafter outputs the luminance signal Y.sub.H to an adder 37. Further, a vertical contour compensation signal is produced from a luminance signal Y.sub.L which is obtained through the LPF 16 which has a cut-off frequency at approximately 0.8 MHz. The luminance signal Y.sub.L is subjected to a similar process to that described above for the luminance signal Y.sub.H with respect to a clamping circuit 34, a gamma compensation circuit 27, a delay circuit 35, and an operational circuit 36. Thus, the vertical contour compensation signal which is added to the luminance signal Y.sub.L is outputted to the adder 37.
Next, a description is given of an operation of processing the colour signal in the conventional video signal processing circuit. The video signal is supplied from the AGC circuit 14 to the BPF 17 which has a band width of 3.97+1 MHz and thereby extracts a signal from the video signal. This extracted signal is supplied to and detected by a synchronous detector (hereinafter referred to as a detector) 18 and as a result, a colour difference signal is obtained. The colour difference signal has values of 2R-G and 2B-G, where R denotes a red primary colour signal, B denotes a blue primary colour signal and G denotes a green primary colour signal. The colour difference signal alternates between the values 2R-G and 2B-G for every one scanning line and is a line sequential colour difference signal. The line sequential colour difference signal is subjected to a band limitation to 0.8 MHz in a LPF 19. Thereafter the luminance signal Y.sub.L supplied from the LPF 16 is added to the line sequential colour difference signal in an adder 21. As a result, the green signal G is cancelled out from the line sequential colour difference signal having the values 2R-G and 2B-G, so that a line sequential colour signal having values of 2R and 2B is outputted from the adder 21. Next, white balance gain control amplifiers (hereinafter referred to as a white balance GCA) 22 and 23 determine a set-up value and a white balance of the primary colour signals R and B. Thereafter, the primary colour signals R and B are subjected to a gamma compensation in respective gamma compensation circuits 28 and 29 and then are supplied to respective colour difference signal circuits (subtracting circuit) 38 and 39. The luminance signal Y.sub.L from the gamma compensation circuit 27 is supplied to both of the colour difference signal circuits 38 and 39 so that line sequential colour difference signals R-Y.sub.L /B-Y.sub.L are produced therefrom and supplied to a sequential-to-simultaneous conversion circuit 49. The sequential-to-simultaneous conversion circuit comprises a switching circuit 41, a delay circuit 44 which delays the sequential colour difference signal by one horizontal scanning interval, and switching circuits 42 and 43. The line sequential colour difference signals R-Y.sub.L /B-Y.sub.L are supplied to the switching circuit 41 which switches for every one scanning line and thereby obtains a continuous line sequential colour difference signal. Thereafter, two line sequential colour difference signals R-Y.sub.L /B-Y.sub.L are formed such that one of the line sequential colour difference signals R-Y.sub.L /B-Y.sub.L is delayed by the delay circuit 44 by one horizontal scanning interval. Next, the switching circuits 42 and 43 perform switching operations so as to convert the two line sequential colour difference signals R-Y.sub.L /B-Y.sub.L into two colour difference signals R-Y.sub.L and B-Y.sub.L which occur simultaneously for each horizontal scanning interval of 1H. The colour difference signals R-Y.sub.L and B-Y.sub.L from the sequential-to-simultaneous conversion circuit 49 are supplied to an encoder 45 where a balanced modulation is carried out on the respective colour subcarriers with the colour difference signals R-Y.sub.L and B-Y.sub.L respectively and the balanced modulated signals are mixed together. Thus, a chroma signal is outputted from the encoder 45. In the case of the NTSC system for example, the chroma signal has a frequency of 3.58 MHz.
However, the conventional CCD single chip colour camera does not have a construction so as to compensate by electrical means an error in luminance composition, and instead performs the compensation for the error in luminance composition by an optical construction. That is, the error in luminance composition is compensated by mounting a colour temperature conversion filter (an optical filter) for compensating for a change in colour temperature in front of the camera lens.
In general, the colour camera is adjusted by taking a reference object which is illuminated with a predetermined colour temperature of 3200 K for example. However, when taking an arbitrary picked object which is illuminated by light of a different colour temperature it is necessary to adjust the colour camera in order to obtain the predetermined colour temperature. There is a method of performing the adjustment optically by mounting a colour temperature conversion filter in front of the camera lens so as to convert the different colour temperature to 3200 K. This method for adjusting the colour temperature with respect to the conventional circuit by using the optical filter is beneficial in that the error in luminance is reduced. However, the use of the optical filter results in an increased weight of the colour camera and is a hindrance to manipulate a colour camera that should be compact and light in weight.

Video signal processing circuit of a video camera


Bispecific molecules which react both with an Fc.gamma. receptor for immunoglobulin G (IgG) of human effector cells and with either human low density lipoprotein (LDL), or fragment thereof, or human high density lipoprotein (HDL), or a fragment thereof, are disclosed. The bispecific molecules bind to an Fc.gamma. receptor without being blocked by the binding of IgG to the same receptor. The bispecific molecules having a binding specificity for human LDL are useful for targeting human effector cells for degradation of LDL in vivo. The bispecific molecules of the present invention which have a binding specificity for human HDL are useful for targeting human HDL to human effector cells such that the HDL takes up cholesterol from the effector cells. Also disclosed are methods of treating atherosclerosis using these bispecific molecules.

Atheromatous lesions consist of numerous cellular and acellular elements. Macrophages are a major constituent of these lesions as they develop into characteristic cholesteryl ester-laden foam cells (Ross, R. (1986) New England J. Med. 314:488-500; Munro, J. M. and Cotran, R. S. (1988) Laboratory Invest. 58:249-261). For macrophages, foam cell development during atherogenesis is ultimately dependent upon uptake of various forms of low density lipoprotein (LDL) (reviewed in Brown, M. S. and Goldstein, J. L. Ann. Rev. Biochem. 52:223-261). Of late, emphasis has been placed on the importance of the interaction of chemically modified or oxidized LDL with macrophage scavenger receptors (reviewed in Steinberg, D., et al. (1988) New England J. Med. 320:915-924), which may occur during atherogenesis in vivo (Steinberg, D., et al. (1988) New England J. Med. 320:915-924; Haberland, M. E., et al. (1988) Science 241:215-218; Palinski, W., et al. (1989) Proc. Natl. Acad. Sci. USA 86:1372-1376; Rosenfeld, M. E., etal. (1990) Arteriosclerosis 10:336-349; Boyd, H. C., et al. (1990) Am. J. Path. 135:815-825).
Foam cell development may also be influenced by the interaction of lipoproteins with pathways other than those associated with scavenger receptors. In particular, recent studies have shown that immune complexes consisting of LDL bound to anti-LDL antibodies (LDL-IC) can cause foam cell development in vitro through interaction with IgG Fc receptors (Fc.gamma.R) when administered to both mouse (Klimov, A. N., et al. (1985) Atherosclerosis 58:1-15) and human macrophages (Lopes-Virella, M. F., et al. (1991) Arteriosclerosis and Thrombosis 11:1356-1367; Griffith, R. L., et al. (1988) J. Exp. Med. 168:1041-1059). LDL-IC (reviewed in Orekhov, A. N. (1991) Curr. Opin. Lipidology 2:329-333) consisting of antibodies bound to either native or oxidized LDL exist in numerous situations in vivo (Szondy, E., et al. (1983) Atherosclerosis 49:69-77; Parums, D. V., et al. (1990) Arch. Pathol. Lab. Med. 114:383-387; Beaumont, J. L., et al. (1988) Atherosclerosis 74:191-201; Kigore, L. L., et al. (1985) J. Clin. Invest. 76:225-232), and in several cases have been correlated with abnormalities of lipid metabolism and atherosclerosis (Szondy, E., et al., supra; Parums, D. V., et al., supra; Beaumont, J. L., et al., supra; Kigore, L. L., et al., supra; Cohen, L., et al. (1966) Am. J. Med. 40:299-316).
In contrast to the role of LDL in foam cell development, human high density lipoprotein (HDL) may play a role in preventing foam cell development. HDL is known to play a role in cholesterol efflux from extrahepatic tissues, such as vascular tissue, to the liver where it can be metabolized. See, e.g., Badimon, J. J. et al. (1992) Circulation (Supp. III) 86(6):III-86-III-94; Castell, W. P. et al (1977) Circulation 55(5):767-772. Moreover, it has been shown that plasma HDL both inhibits the development of experimental atherosclerosis and induces regression of the lipid infiltration into vessel (e.g., aortic) walls. Badimon, J. J. et al., supra.
Human Fc.gamma. receptors (Fc.gamma.R) (reviewed in Fanger, M. W., et al. (1989) Immunology Today 10:92-99), of which there are three structurally and functionally distinct types (i.e., Fc.gamma.RI, Fc.gamma.RII and Fc.gamma.RIII), are well-characterized cell surface glycoproteins that mediate phagocytosis or antibody-dependent cell cytotoxicity (ADCC) of immunoglobulin G (IgG) opsonized targets.
Bispecific antibody technology has been used to evaluate the function of specific Fc.gamma.R. Investigators have shown that Fc.gamma.R are the only cell surface molecules on myeloid cells capable of triggering phagocytic or cytotoxic function (Shen, L., et al. (1986) J. Immunol. 137:3378-3382; Shen, L. et al. (1987) J. Immunol. 139:534-538; Connor, R. I., et al. (1990) J. Immunol. 145:1483-1489; Anderson, C. L., et al. (1990) J. Exp. Med. 171:1333-1345). However, clear differences in the functional ability of the different Fc.gamma.R could be demonstrated that was dependent not only on the Fc.gamma.R class or isoform but on the state of activation and differentiation of the cell (Fanger, M. W., et al. (1989) Immunology Today 10:92-99; Van de Winkel, J. G. and Anderson, C. L. (1991) J. Leukocyte Biol. 49:511-524).

Bispecific reagents for redirected targeting of human lipoproteins


A battery frame of the present invention has; any one of a conductive member and an insulating member which are sandwiched between electrode tabs of flat cells arranged in a stacking direction when a battery is formed, the conductive member electrically connecting the flat cells to each other and the insulating member electrically insulating the flat cells from each other; a holding member which holds any one of the conductive member and the insulating member so that the conductive member or the insulating member can swing in the stacking direction; and an electrode supporting portion in which the holding member is provided and which supports each of the electrode tabs of the flat cells. By this structure, it is possible to prevent deformation of the battery frame during the formation of the battery.

1. Field of the Invention
The present invention relates to battery frames used when stacking flat cells to form a battery, and a battery in which the frames are used.
2. Description of the Related Art
A plurality of single cells is combined in series or parallel to form a battery or a module battery with high power and capacity. For example, it is known that a plurality of flat single cells, each having an electric-power generating element covered with laminate films, is connected to each other in series or parallel to form a battery with high power and capacity (see Japanese Patent Laid-Open Publication No. 2001-256939). A flat single cell in which an electric-power generating element is covered with laminate films is called a laminate cell.
Where a battery is formed using laminate cells of this kind, a plurality of laminate cells is located on the same plane, a plurality of sets of these laminate cells on the same plane is further stacked, and then these laminate cells are connected to each other in series or parallel. By stacking the laminate cells like this, a battery with higher power and capacity can be formed.
When assembling this stack-type battery, locating and stacking laminate cells one by one results in poor workability. Therefore, laminate cells are located on a plate-like frame and a plurality of frames where the cells are located is stacked, thus improving workability in assembling a stack-type battery.
Further, in order to electrically connect the cells located on neighboring frames in the stacking direction, washers made of a conductive material (conductive washers) may be incorporated in the frames at positions where electrode tabs of the laminate cells lie. To electrically insulate cells, washers made of insulating material (insulating washers) may be incorporated in the frames. When electrically connecting or insulating the laminate cells located on neighboring frames in the stacking direction, the frames, where the laminate cells are mounted, are stacked and the frames or washers are pressed from the top and bottom of the stack. This ensures that the electrode tabs and the washers come into contact with to each other, enabling the neighboring cells to be electrically connected or insulated from each other.


A spray control device for use with vehicle mountable spraying apparatus having a pump for conveying fluid under pressure to a spray head. The control device has a pressure sensor for sensing the pressure of the fluid near the spray head. A speed sensor enables calculation of vehicle speed. An adjustment device adjusts the delivery of fluid to the spray head. A microprocessor is programmed to calculate from information derived from the pressure sensor and speed sensor spray application rate. The microprocessor compares the application rate with a stored target application rate to thereby cause the adjustment device to, if necessary, adjust the pump so that the pressure of fluid delivery achieves the target application rate.

This invention relates to a control device for spraying which is primarily but not exclusively intended for use with vehicles such as an all terrain vehicle (xe2x80x9cATVxe2x80x9d), small farm tractors, lawn tractors and the like.
It is known to provide a spray control system for ensuring that a correct spray application rate is maintained. Such a system will generally include a constant speed pump which pumps fluid to be sprayed from a holding tank to a spray boom having a series of spray nozzles. A valve means such as a butterfly valve or motor driven ball valve is provided in the main supply line between the tank and the boom. The valve means is operable to divert flow from the main supply line to a by-pass line so as to adjust the volume to the spray boom as may be required to achieve the application rate. A flow meter is provided to measure flow to the boom to enable the correct spray rate (usually measured in liters per hectare) to be achieved.
It is generally the case that a spray boom will have a plurality of set volume spray nozzles. After having determined nominal speed and application rate, the operator will select the necessary tip size. Generally, the nozzle tips are selected for optimum performance and therefore the tip size selected will be such that for the nominal speed and application rate the fluid flow through the nozzle tip will be at about midway in the performance range of the tip. Tip sizes are generally determined according to an international standard such as ISO 10625 or a national yet recognised standard such as BCPC.
Known spray control systems of this type are generally not suitable for spraying apparatus using 6, 12 or 24 volt DC pumps which are commonly used with eg smaller vehicles such as the now popular ATV. A flow meter is a high cost item as is the valving used to regulate the flow of spray fluid from the tank to the spray boom. This means that the system necessarily is of a cost greater than that which is justifiable for use with, for example, an ATV.
There is therefore a need for a low cost spray control system for use with vehicles such as an ATV yet is a system which at least includes the main features of bigger systems. The object of the present invention is to provide a low cost control device for spraying apparatus or at least provide the public with a useful choice.
According to one broad aspect of the invention, there is provided a spray control device for use with vehicle mountable spraying apparatus having a pump means for conveying fluid under pressure to a spray head, the control device including pressure sensing means for sensing the pressure of the fluid near the spray head, speed sensor means to enable calculation of vehicle speed, adjustment means for adjusting the delivery of fluid to the spray head and microprocessor means programmed to calculate from information derived from the pressure sensing means and speed sensor means a calculated spray application rate and compare same with a stored target application rate to thereby cause the adjustment means to, if necessary, adjust the pump means to deliver fluid so that a pressure is achieved such as to achieve the target application rate.


An apparatus for testing natural, partially artificial, or artificial musculoskeletal joints is provided as well as a method for using the same. In one aspect, the system employs a weighted, articulated apparatus, such as a pendulum, moving in response to a driving signal to determine a property of the musculoskeletal joint. Also within the invention is a method of growing cells under physiologic conditions of a musculoskeletal joint.

Musculoskeletal joints include bones that move relative to one another. The motion of the bones is facilitated by lubricating synovial fluid that lies in a space (intra-articular space) between the moving bones in the joint. In living beings, the body produces the synovial fluid to ease the effort of moving the joints, and to reduce wear on the contact points of the moving bones.
Similar principles apply to the motion of living natural joints, artificial joints, or partially artificial joints. Artificial and partially artificial joints include one or more elements made of synthetic, artificial materials. An artificial lubricating fluid, or a wear-resistant smooth material can be used to make or coat the artificial portions of the artificial or partially artificial joints.
Testing and measurement of various physiological and mechanical properties of a musculoskeletal joint can be carried out by observing its response to predetermined conditions. For example, certain mechanical properties of a musculoskeletal joint can be tested by subjecting the joint to a force and observing the dynamic response of the joint to the applied force.
Experiments have been conducted on musculoskeletal joints to determine the coefficients of friction between parts of the joints that move relative to one another. Earlier works studied the lubrication of animal joints in the context of arthritis and rheumatism research using a pendulum connected to a portion of the joint. Some of these experiments involved attaching a pendulum to one portion of a musculoskeletal joint, fixing another portion of the joint, then observing the system's response when the pendulum is swung under the force of gravity. Properties of the joint could be deduced using the principles of mechanics to measure the frictional coefficients of the musculoskeletal joint for example.


A system for co-generation of electricity combining a hydrocarbon catalytic reformer, an SOFC assembly and a generator driven by a gas turbine. The fuel cell assembly recycles a high percentage of anode exhaust gas into the reformer. Oxygen for reforming is derived from water in an endothermic process. The stack exit temperature is normally above 800° C. DC power from the fuel cell assembly and AC power from the gas turbine generator are directed to a power conditioner. Anode exhaust gas including carbon monoxide and hydrogen is divided into a plurality of portions by which heat may be added to the reforming, gas turbine, and cathode air heating processes. Water may be recovered from the exhaust. A power system in accordance with the invention is capable of operating at a higher total efficiency than either the fuel cell component or the gas turbine component alone.

Fuel cells which generate electric current by controllably combining elemental hydrogen and oxygen are well known. In one form of such a fuel cell, an anodic layer and a cathodic layer are separated by a non-permeable electrolyte formed of a ceramic solid oxide. Such a fuel cell is known in the art as a "solid-oxide fuel cell" (SOFC). It is further known to combine a plurality of such fuel cells into a manifolded structure referred to in the art as a "fuel cell stack" and to provide a partially-oxidized "reformate" fuel ("syngas") to the stack from a hydrocarbon catalytic reformer.
Prior art catalytic partial-oxidizing (POX) reformers typically are operated exothermically by using intake air to partially oxidize hydrocarbon fuel as may be represented by the following equation for a hydrocarbon and air,C7H12+3.5(O2+3.77N2)→6H2+7 CO+13.22N2+heat  (Eq. 1)wherein the oxygen/carbon atomic ratio is 1.0, and the resulting reformate temperature is in the range of about 1000° C. Prior art reformers typically are operated slightly fuel-lean of stoichiometric to prevent coking of the anodes from non-reformed hydrocarbon decomposition within the fuel cell stack. Thus conventional combustion of hydrocarbon and reformate occurs within the reformer and within the stack in addition to, and in competition with, the electrochemical combustion of the fuel cell process. Such conventional combustion is wasteful of fuel and creates additional heat which must be removed from the reformate and/or stack, typically by passing a superabundance of cooling air through the cathode side of the stack.
It is known to produce a reformate containing hydrogen and carbon monoxide by endothermic steam reforming (SR) of hydrocarbon in the presence of water in the so-called "water gas" process, which may be represented by the following equation,C7H12+7H2O+heat→13H2+7CO  (Eq. 2)wherein the oxygen/carbon atomic ratio is still 1.0 and the reformate temperature is still about 1000° C. The disadvantages of this process for providing reformate for operating a fuel cell are 1) a continuous water supply must be provided; 2) heat must be provided, typically in the form of burned fuel, thus reducing the efficiency of the system; and 3) the reforming temperature is hard on the reformer.
High temperature fuel cells inherently produce a combination of direct current electricity, waste heat, and syngas. The syngas, as used herein, is a mixture of unburned reformate, including hydrogen, carbon monoxide, and nitrogen, as well as combustion products such as carbon dioxide and water. In some prior art fuel cell systems, the syngas is burned in an afterburner, and the heat of combustion is partially recovered by heat exchange to the reformer, to the cathode inlet air, or to both.
In accordance with the invention disclosed in the co-pending and commonly owned patent application 10/793,302, entitled "Apparatus and Method for Operation of a High Temperature Fuel Cell System Using Recycled Anode Exhaust", a relatively small percentage, typically between 5% and 30%, of the anode syngas may be recycled into the reformer a) to increase fuel efficiency by endothermic reforming of water and carbon dioxide in the syngas in accordance with Equation 2 above (thus combining POX and SR reforming); b) to add excess water to the reformate to increase protection against anode coking; and c) to provide another opportunity for anode consumption of residual hydrogen. In such systems, and especially when using heavy fuels such as gasoline and diesel, the reformer typically is operated at a high temperature (which may even exceed the stack temperature) to provide the energy necessary for endothermic reforming. However, such high temperatures may be deleterious to the reformer over a period of time, and tend to lower system efficiency. From a durability point of view, it is desirable to be able to operate a reformer at the lowest temperature possible (without being in an operating region of carbon formation).
In a fuel cell stack, the reformate consumed is converted into approximately equal amounts of heat and electricity. The stack is cooled primarily by the flow of gases through it. Even with a modest amount of recycle flow added to the reformate, the total reformate massflow is relatively small, on the order of one-tenth the massflow of the cathode air, so the majority of cooling is done by cathode air. As previously noted, in endothermic reforming of recycled syngas, the reformate produced cannot be cooled below stack temperature without risk of carbon nucleation. Therefore, in order to keep a reasonable temperature gradient in the stack between the inlet and outlet of the cathode, a very high cathode air massflow is required, being many times the amount required for the electrochemistry of the stack. This creates an added energy parasitic to the stack in the form of a very large air blower, and also tends to make the size of the cathode heat exchanger much larger than would otherwise be necessary.
Gas turbines are well known for use in driving electric generators. Typically, a stream of hot gas is impinged against one or more bladed turbines mounted on a shaft of the generator. A typical gas turbine generator operates at about 38% fuel efficiency.
It is well known that a solid oxide fuel cell and a gas turbine can be integrated into a combined system known in the art as an SOFC/GT hybrid. Such systems have been commercialized on a limited or experimental basis, for example, by Siemens Westinghouse Power Corporation, using all ceramic high temperature stacks. Such a fuel cell system, running at a temperature of approximately 1000° C., is well matched to the thermal requirements of uncooled gas turbines, the system is inherently large and heavy; is high in materials and processing cost; and is slow in start-up time and in transient response.
Intermediate temperature SOFC stacks, operating at a nominal stack temperature between about 700° C. and 850° C. are expected to be smaller, less expensive, and more capable of fast start-up and transient response. However, the operating temperature is not so well suited to gas turbine integration.
As noted above, conventional cooling strategies for a conventional SOFC require considerable excess air on the cathode side and modest temperature differentials between the inlet and the exit of the stack. This results in a need for a relatively large heat exchanger for cathode air preheating, and a relatively large blower or compressor to supply air to the fuel cell.
What is needed in the art is a new configuration for an SOFC/GT hybrid that optimizes thermodynamic coupling of the SOFC and GT processes and allows the hybrid system to be operated with substantially less heat exchange required in fuel vaporization/reforming and in cathode air preheating. Such an optimized hybrid offers large reductions in system weight and cost, making such an auxiliary power unit (APU) system useful for applications in aerospace, aviation, road/rail/marine transport, and "containerized" distributed power generation.
What is further needed is a means for improving the efficiency of reformer and stack processes while operating the reformer at a temperature below the stack temperature; for minimizing the size and weight of the heat exchangers; and for retaining most or all of the latent heat value of the anode tail gas for downstream processes.
What is still further needed is means for increasing the fuel efficiency of a gas turbine generator.
What is still further needed is auxiliary power unit means for generating electricity which is relatively lightweight and highly fuel efficient.
It is a principal object of the present invention to provide electric power by combining high efficiency operation of a high temperature fuel cell system with a gas turbine generator.

Hybrid power generating system combining a fuel cell and a gas turbine


A method for performing enhanced wafer quality prediction in a semiconductor manufacturing process includes the steps of: obtaining data including at least one of tensor format wafer processing conditions, historical wafer quality measurements and prior knowledge relating to at least one of the semiconductor manufacturing process and wafer quality; building a hierarchical prediction model including at least the tensor format wafer processing conditions; and predicting wafer quality for a newly fabricated wafer based at least on the hierarchical prediction model and corresponding tensor format wafer processing conditions.

In many real-world applications, input data is naturally expressed in the form of tensors or multi-dimensional arrays, such as, but not limited to, virtual metrology in semiconductor manufacturing, face recognition and gait recognition in computer vision, etc. For example, in the context of semiconductor manufacturing, each recipe process usually comprises multiple steps. During each step, process variables such as temperature, pressure and gas flow per unit time are precisely measured and monitored. Therefore, to predict wafer quality, the input data are naturally expressed as tensors. For example, for a single-chamber recipe, the tensors have three modes, namely steps, time within a step, and observed process variables or features; for multiple-chamber recipes, the tensors have four modes, with the additional mode being the chamber recipes accomplished on the same or different chambers in one tool; if summary statistics for each process variable in a single step are used instead of instantaneous measurements, the modes of the tensors are reduced by one. Another example is in computer vision, where images can be modeled as second-order tensors, and image sequences can be modeled as third-order tensors.
Conventionally, work on dealing with tensor data converts tensors into one-dimensional vectors and applies a rich methodology for vector inputs to build a model, either for classification or for regression. However, by converting tensors into vectors, valuable information embedded in the structure of the tensors is lost, such as, for example, feature correspondence in different steps, in the example of semiconductor manufacturing, or neighborhood information of a pixel, in the example of computer vision. Hence, existing approaches to handling tensor data result in inaccurate predictive modeling and are therefore undesirable.

Method and apparatus for hierarchical wafer quality predictive modeling

International Business Machines Corporation