A real image projection system includes at least one curved reflector, positioned in a tilted configuration, wherein an optical axis of the reflector is not coincident with a viewing axis, and a beampath between a target source and the curved reflector neither passes through nor reflects off of a beamsplitter.

1. Field of the Invention
The invention pertains to the field of real image projection systems. More particularly, the invention pertains to a real image projection system having a tilted curved reflector, eliminating the need for a 50-50 beamsplitter in the system.
2. Description of Related Art
The present invention, referred to as an Ultra-High-Bright (hereinafter xe2x80x9cUHBxe2x80x9d) display system, pertains to a real image projection system and, in particular, to a system in which an image of a real object is formed in space, giving the illusion that a real object exists at that point in space, when in reality it does not.
Visual Display systems normally use a curved reflector with a beamsplitter positioned at a 45 degree angle to the curved mirror""s optical axis, to divert the input beampath at a 90 degree angle to the viewing axis or imaging beampath. This method has been used since the early 1950""s for flight simulation, and is referred to as the WAC window system. These systems typically are used in an on-axis configuration, meaning that the optical axis or the un-tilted curved mirror""s center of radius is located along the viewing axis. When viewing such an on-axis system, any object within the viewing area images within the system. When one looks straight at an un-tilted or on-axis curved reflector, the viewer sees an image of himself appearing upside down in the system. This generally is not a problem in flight simulators, since the cockpit typically is dark, and thus very little ghost imaging is visible.
One of the earliest working real image displays is depicted in White""s 1934 publication of xe2x80x9cFundamentals of Opticsxe2x80x9d. It shows a spherical mirror positioned behind a table. A flower vase is mounted below the table and a real image of the vase is projected sitting on the table-top. This system works, however, the viewer and room also are projected as a real image, which is known as ghosting. The White system uses an on-axis configuration, with the image being formed not at the focal point of the system or the center of radius of the curved mirror. This causes image distortion as the image deviates from the focal point of the system (center of radius).
In the late 1980""s, real image display systems were developed, consisting of two on-axis parabolic reflector segments, as shown in U.S. Pat. No. 4,802,750. This at least partially solved the ghost reflection problem, however, the manufacture of parabolic sectors was extremely difficult and the product was not commercially viable. In the early 1990""s, systems were built that used a beamsplitter with high reflection and low transmission to reduce the ghosting effects. This proved effective reducing the ghost image brightness from 21.5% to 5.4%, except it also reduced image transmission from 21.5% to 16.1%. Although the ghost image was much dimmer, it was still visible, and a serious distraction to the viewer.
In 1999, a system was developed using a circularly polarized window in an on-axis, WAC window style configuration, and the La Russa U.S. Pat. No. 6,163,408 was issued in 2000. This improvement effectively blocked all ghost reflections from the viewer, however the circular polarizer element had a transmission of 42%, which reduced the image brightness or transmission from 21.5% to 9%.
In 2000, a tilted system was developed, using an off-axis, curved reflector, as disclosed in International Patent Application No. PCT/US00/11234 and PCT Publication No. WO 00/65844. The system comprises a curved reflector tilted at an angle between 5 and 20 degrees from the viewing axis. A beamsplitter is positioned in the viewing axis, tilted at 45 degrees to the curved reflector axis. This is a significant improvement because it eliminates ghost imaging completely; the system no longer required a 42% transmission circular polarizer to eliminate ghosting. A 70% transmissive front window was instead used to provide a system transmission of 15%.
The goal of visual display companies has been to develop a system that has an image brightness and fields-of-view comparable to the parabolic system (e.g., U.S. Pat. No. 4,802,750), with no ghost reflections, and a system that can easily be manufactured.
The proposed UHB imaging system of the present invention incorporates a tilted mirror in conjunction with the classic single mirror imaging system depicted in White""s 1934 publication of xe2x80x9cFundamentals of Opticsxe2x80x9d. A preferred embodiment of the system of the present invention comprises a single curved reflector tilted approximately 15 degrees off-axis. The angle of tilt must be sufficient to allow the diverging beampath to strike the curved reflector without intersecting the area of the viewing window aperture. The angle of tilt preferably should be less than 17 degrees so as to minimize the effects of field curvature in the optical system. As the angle of tilt exceeds 17 degrees, the distortion caused by field curvature phenomena becomes critical. In one embodiment, light from a CRT or target object located directly below the curved reflector and facing forward, strikes a fold mirror or flat reflective surface positioned directly below the viewing window aperture with the reflective surface facing the target and curved reflector. Preferably, the fold mirror is positioned at an angle so that the light beam the monitor is reflected to the center of the curved reflector at an angle from horizontal equal to twice the tilt of the curved reflector. The diverging light beam reflects off the curved reflector and the converging beam exits on a horizontal axis, forming a real image at the focal point of the system. Because the system uses no beamsplitter, the system transmission is approximately 56% when used with a 70% Neutral Density Filter Window and 80% when used with no front window.
Now that a system transmission of 80% can be achieved, other devices can be incorporated into the real image projection system, that were not possible when system transmission was limited to 15-22%.
The present optical system exhibits more than a 300% increase in image brightness over prior art systems, and the elimination of all ghosting within the viewing area.
The present invention provides a method or optical configuration that has a high transmission or brightness, typically between 45% and 80% for the real image, with no visible ghost reflections, while maintaining a sufficient field of view or angle in which the image is visible. Another feature included in the configuration is a method of reducing the aberrations and distortions inherent in real image display systems.
A preferred embodiment of the invention is a tilted, off-axis, curved reflector of the conical family of curves, or an aspheric design. A toric curve optionally is used to reduce aberrations, inherent in off-axis systems. The curved reflector also optionally is a Mangin style reflector with two distinct curves, one on the concave and one on the convex for improved imagery. The UHB off-axis configuration can be applied to any optical imaging system incorporating a reflective imaging component that will form a real or virtual image or near-infinity image.
As an example, the optical axis of the curved mirror is tilted at a 15 degree angle to the viewing axis, with the top of the mirror leaning toward the front of the display. The target object or CRT screen is positioned under the curved reflector, facing the front of the display facing upward at 15 degrees. The diverging beampath of light from the target object or CRT strikes a vertical flat reflector or fold mirror at a 15 degree angle of incidence, reflecting at a complementary 15 degree angle and the reflected beam of light strikes the curved reflector with the axis or center of the reflected beam striking the physical center of the curved reflector. The diverging beam of light strikes the curved reflector at an angle of incidence of 15 degrees to the optical axis of the mirror. The light beam is then reflected as a converging beam of light off the curved mirror at a complementary angle of 15 degrees from the optical axis of the mirror, or along a horizontal line coincident with the viewing axis. The diverging beam of light emanating from the CRT or object and reflected off the fold mirror strikes the curved reflector at a 30 degree angle to the real image axis in relation to the vertex of the mirror surface or center of the mirror surface.
Outside light entering the window of the system, such as that reflected off the viewer or bright objects in the room, will be reflected downward by the tilted curved reflector and will not form an image in the viewing area. Therefore, visible ghost reflections are eliminated. To reduce the system size, a fold mirror optionally is positioned in the diverging beampath from the target object, to fold the beampath back into the display case. The object can then be moved to the new target focal point of the system inside of the case. The beampath length or focal length must be sufficient to allow the target object to be located outside of the beam of diverging light reflected off of the fold mirror to the curved reflector.
Optionally, a secondary target source is positioned behind the curved reflector, for example, when the curved reflector is a partially reflective beamsplitter coating, such as a 74% Reflective and 12% Transmissive coating. This allows the background image to be visible through the curved reflector. In an alternate configuration, a beamsplitter is positioned so that one edge of the beamsplitter is next to the top of the curved reflector, and the bottom edge of the beamsplitter is positioned at the bottom edge of the window aperture. The beamsplitter must allow the full converging beampath to pass through the beamsplitter, but not interfere with the diverging beampath from the target object. By using a high transmissive beamsplitter, such as an 83% transmissive and 12% Reflective coating, and positioning the background input target above the beamsplitter, a virtual image of the background target is formed floating in front of the curved reflector along a common viewing axis with the real image.
The system optionally is used with a window to isolate the inside of the display from the viewer. The window may be anti-reflective coated on one or both surfaces to reduce reflections. The window optionally is a tinted or neutral density filter, to reduce stray light from exiting the system, or it may be a circular polarizer.

Method of ghost reduction and transmission enhancement for a real image projection system


A method of determining an initial position in executing a positioning calculation based on satellite signals from positioning satellites, includes: (a) executing position converging calculation based on the satellite signals using each of a plurality of first candidate positions as a provisional initial position; (b) selecting at least one second candidate position from the first candidate positions based on a calculation result of the position converging calculation; and (c) selecting the initial position from one of the second candidate positions using the satellite signals.

1. Technical Field
The present invention is related to an initial position determination method and the like that determines an initial position when positioning calculation is executed based on satellite signals from positioning satellites.
2. Related Art
A global positioning system (GPS) that uses a positioning signal is widely known, and is used as a positioning apparatus incorporated in, for example, a portable phone or a vehicle navigation system. In a GPS, the positioning calculation is done by obtaining values of four parameters, namely three-dimensional coordinate values representing the location of the system itself and a timepiece error, based on the information such as the locations of a plurality of GPS satellites or pseudo-ranges between the GPS satellites and the system itself. Thus, the position of the present location of the system itself can be known.
In the positioning by the GPS, since the position (hereinafter referred to as an "initial position") of the positioning apparatus, which is used as an initial value of the positioning calculation (more accurately, position converging calculation), is required, various technologies for obtaining the initial position have been invented. For example, JP-A-2006-71460 discloses a technology for determining the initial position used in present positioning calculation by using the positioning error included in the positioning location obtained by the previous positioning calculation.
The positioning apparatus in the related art generally determines the initial position using a fractional part (code phase) of the pseudo random noise (PRN) code as a kind of spread code carried by the satellite signal from the GPS satellite. The PRN code is a signal with a bit rate of 1.023 Mbps and a bit length of 1,023 bits (=1 msec=300 km). Therefore, if the initial position is in an error range of within 150 km from the true position, the position converging calculation becomes possible using the fractional part (the code phase) of the PRN code. Therefore, in the positioning calculation in the related art, the error of the initial position is required to be within 150 km.
However, in reality, in some cases, it is difficult to obtain the initial position close to the true position of the positioning device. The case in which the positioning apparatus is powered on to first perform positioning after moving by air is a typical example. Depending on circumstances, in this case, it is also possible in which the initial position is separated by 500 km or even 1,000 km distance from the true position of the positioning apparatus. Thus, there is a need for a GPS can determine an initial position close to the true position of the positioning apparatus even in the aforementioned type of case. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.

Initial position determination method, positioning method, and positioning apparatus


The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.

A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash, memory cell includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. The flash memory cell provides for nonvolatile data storage.
A typical configuration of a flash memory cell consists of a thin, high-quality tunnel oxide layer sandwiched between a conducting polysilicon floating gate and a crystalline silicon semiconductor substrate. The tunnel oxide layer is typically composed of silicon oxide (SixOy). The substrate includes a source region and a drain region that can be separated by an underlying channel region. A control gate is provided adjacent to the floating gate, and is separated by an interpoly dielectric. Typically, the interpoly dielectric can be composed of an oxide-nitride-oxide (ONO) structure.
A typical configuration of an array of flash memory cells includes rows and columns of flash memory cells. The array is supported by word lines and bit lines, wherein the word lines are coupled to gates of flash memory cells, and the bit lines are coupled to drains. The sources of the flash memory cells are commonly coupled together.
The flash memory cell stores data by holding charge within the floating gate. In a write or program operation, charge can be placed on the floating gate through hot electron injection, or Fowler-Nordheim (F-N) tunneling. In addition, F-N tunneling can be typically used for erasing the flash memory cell through the removal of charge on the floating gate.
Prior Art FIG. 1 is a diagram of an exemplary MOSFET transistor 100 used as a flash memory device. Prior Art FIG. 1 illustrates the negative effects of punch-through due to reduced gate lengths. The MOSFET 100 includes a substrate 110 that includes a source region 140 and a drain region 170 that is separated by an underlying channel region under the stacked gate structure 120. The source region 140 intrudes under the gate stack 120. The drain region 170 also intrudes under the gate stack 120. These intrusions shorten the effective channel length between the source region 140 and the drain region 170.
As flash memory technology progresses, emphasis is directed to reduce the size of the memory cells in the flash memory. However, continued reduction in size of the gate length of the MOSFET has been limited by short channel effects. Specifically, the behavior of the transistor is negatively governed by punch-through of electrons at the higher voltages. When the effective channel length between the source region 140 and the drain region 170 becomes too short, the depletion region under the gate stack 120 is formed partly by the bias voltage on the drain region 170 and the built-in potential of the source region 140. As a result, the depletion region 180 due to the bias voltage on the drain region 170 can extend to the depletion region 150 surrounding the source region 140.
Correspondingly, the barrier for electron injection from the source region 140 to the drain region 170 decreases due to the extension of the depletion region 180. Specifically, at positive drain voltages, the effective energy barrier height for electrons can be reduced resulting in electrons migrating from the source region 140 to the drain region 170. This is known as drain induced barrier lowering (DIBL).
In the worst case, when the depletion regions 180 and 150 touch each other punch-through will occur. This will result in loss of gate control over the channel, and result in significant current flow from the source 140 to the drain 170.
Thus, even when the MOSFET 100 is turned off by biasing the stacked gate to zero volts, for voltages that are applied to the drain region 170, an unwanted current can flow from the source region 140 to the drain region 170 due to punch-through. This in turn reduces the breakdown voltage of the MOSFET 100.
What is needed is an apparatus and method for reducing short channel effects in flash memory cells.

Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors


An image processing apparatus includes a fixing unit including a heater and a fixing belt. The fixing belt is electrically connected between a first power source and a ground terminal. A controller is configured to control the heater to heat the fixing belt. The controller is further configured to determine whether a current is flowing through the fixing belt and, upon determining that a current is not flowing through the fixing belt, control the heater not to heat the fixing belt.

In a belt type or on-demand type fixing device, static electricity may be accumulated on a fixing belt because of its repeated sliding contact with sheets of paper and a heater element of the fixing device. When static electricity accumulates on the fixing belt, an electrostatic offset may occur, thereby deteriorating the quality of an output image formed on the sheet. To prevent the occurrence of such an electrostatic offset, a method has been developed to discharge the accumulated static electricity by connecting the fixing belt to a ground potential (hereinafter, referred to as "GND"). However, since the fixing belt rotates, the connection between the fixing belt and GND tends to be unstable or difficult to maintain continuously.

This patent is subject to a terminal disclaimer.

Image forming apparatus having a fixing unit and heating control method


Various embodiments are generally directed to an apparatus, method and other techniques for receiving a request to generate a bootable image in a cloud-based computing environment, creating a block storage volume in the cloud-based computing environment in response to receiving the request, the block storage volume having one or more partitions. Further, an apparatus, method and so forth may include installing software comprising one or more files in a file system on the block storage volume in the cloud-based computing environment, creating a snapshot of the file system including the software in the cloud-based computing environment, and creating a bootable image from the snapshot of the file system in the cloud-based computing environment.

Cloud computing is an architecture in which users do not own the physical infrastructure related to applications, data storage, remote processing etc. Instead, users avoid the various expenses associated with operating computers, maintaining large storage centers, maintaining software, etc. by purchasing usage from a third-party cloud system provider. The cloud computing model has become increasingly viable for many enterprises for various reasons, including that the cloud infrastructure may permit information technology resources to be treated as utilities that can be automatically provisioned on demand, while also limiting the cost of services to actual resource consumption. Moreover, consumers of resources provided in cloud computing environments can leverage technologies that might otherwise be unavailable. Thus, as cloud computing and cloud storage become more pervasive, many enterprises will find that moving data and processing to cloud providers can yield economies of scale, among other advantages.

Techniques for creating a bootable image in a cloud-based computing environment


A semiconductor integrated circuit device includes a charge pump circuit for outputting a predetermined negative voltage to a negative voltage node, a voltage detection circuit for generating a first detection signal when the voltage of the negative voltage node has reached a first detection voltage and for generating a second detection signal when the voltage of the negative voltage node has reached a second detection voltage, an oscillator that is driven in response to the first detection signal so as to generate a signal for driving the charge pump circuit, and a negative voltage raising circuit that has an output terminal connected to the negative voltage node, and that is driven in response to the second detection signal so as to raise the voltage of the negative voltage node through the output of its output terminal. The VBB voltage can be increased rapidly and can be controlled at higher speeds, thereby increasing the stability of the voltage.

1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices in which the stability of the negative voltage generated by a negative voltage generating circuit is increased, and methods of manufacturing such semiconductor integrated circuit devices.
2. Description of the Related Art
As manufacturing processes have become progressively miniaturized in recent years, there has arisen a need for system LSIs for specific applications that include dynamic random access memories (hereinafter, abbreviated as DRAM) and for which standard CMOS manufacturing processes can be used.
Conventionally, the negative voltage (VBB voltage) generated by a negative voltage generating circuit in the DRAM has been used as the well voltage of memory cell portions employing a triple well structure. Planar memory cell structures have been adopted as a way to form DRAMs through standard CMOS processing, as mentioned above, without the use of a triple well.
Here, FIG. 11 shows a planar memory cell structure. Numeral 300 denotes a p-type semiconductor substrate connected to a ground voltage VSS. An n-well 310 is formed in the upper portion of the p-type semiconductor substrate 300, and in the upper portion of the n-well 310 are formed a high-concentration n-type diffusion layer 320 and high-concentration p-type diffusion layers 330. A VDD power source is connected via the high-concentration n-type diffusion layer 320, and a bit line BL is connected to one of the high-concentration p-type diffusion layers 330. A gate 340 is a word line WL with an internally stepped down power source VINT as its power source. The two high-concentration p-type diffusion layers 330 and the gate 340 together make up a PMOS access transistor 360. The high-concentration p-type diffusion layer 330 to which the bit line BL is not connected and a memory cell plate 350 connected to VBB make up a PMOS memory cell capacitor 370.
This memory cell operates as follows. The PMOS access transistor 360 is activated by setting the gate 340, that is, the word line WL, to the ground voltage VSS, and data are written by injecting a charge from the bit line BL into the channel region formed near the surface of the n-well 310 below the memory cell plate 350.
FIG. 12 is an equivalent circuit of this planar memory cell structure.
As shown in FIGS. 11 and 12, the VDD power source, which is a positive voltage, is used for the well voltage of the memory cell portion in which the PMOS access transistor 360 is employed, and the VBB voltage, which is a negative voltage, is used as the memory cell plate power source for the PMOS memory cell capacitor 370.
Next, a conventional semiconductor memory device with the above planar memory cell structure is described. FIG. 13 is a block diagram of the conventional semiconductor memory device. Numeral 410 denotes a VBB voltage generating circuit and 480 denotes a memory cell array having a memory cell plate with a negative charge. The VBB voltage generating circuit 410 includes a charge pump circuit 420 for generating VBB voltage, a ring oscillator 430 for generating pulse signals that cause the charge pump circuit 420 to perform a charge pump operation, a VBB voltage detection circuit 450 to which the VBB voltage is fed back and which generates signals (BBDOWN) for activating the ring oscillator 430, and a constant voltage generating circuit 460 for generating a reference voltage that is used by the VBB voltage detection circuit 450. The VBB voltage detection circuit 450 is made of a comparison voltage generating circuit 451 and a non-inverting amplifier 454 for lowering the VBB voltage.
The comparison voltage generating circuit 451 is a series circuit of a resistor R21 and a resistor R22. One terminal of the resistor R21 is connected to a node of a constant voltage VREG output from the constant voltage generating circuit 460, and the other end is connected to one terminal of the resistor 22 and is also connected to a node of a comparison voltage VCOMP that is applied to a non-inverting input terminal (+) of the non-inverting amplifier 454 for lowering the VBB voltage. The other end of the resistor R22 is connected to the VBB node.
The operation of the semiconductor memory device configured as above is described below. The non-inverting amplifier 454 has two input terminals and one output terminal. As mentioned above, the comparison voltage VCOMP is applied to the non-inverting input terminal (+) and a reference voltage VREF (in the present conventional example, the ground voltage VSS) is applied to the inverting input terminal (xe2x88x92). Consequently, if the VCOMP voltage is higher than the reference voltage VREF, that is, the ground voltage VSS, then a voltage of the BBDOWN node, which is the output, become a logic xe2x80x98HIGHxe2x80x99 voltage (hereinafter, referred to simply as HIGH voltage), and if the VCOMP voltage is lower than the ground voltage VSS, then the BBDOWN node becomes a logic xe2x80x98LOWxe2x80x99 voltage (hereinafter, referred to simply as LOW voltage).
When the BBDOWN voltage is HIGH voltage, the ring oscillator 430 self-oscillates, and the charge pump circuit 420 that receives this oscillated pulse executes a pumping operation that causes the VBB voltage to drop. On the other hand, when the BBDOWN voltage is LOW voltage, the ring oscillator 430 does not self-oscillate, and the operation of the charge pump circuit 420 is stopped.
The VCOMP voltage is determined by the voltage division ratio of the resistor R21 and the resistor R22, and is expressed by Equation (1).
VCOMP=VBB+{R22(VREGxe2x88x92VBB)}/(R21+R22)xe2x80x83xe2x80x83(1)
If the resistor voltage division ratio determined by the resistor R21 and the resistor R22 is such that the VCOMP voltage is equal to the VREF (VSS) voltage when the VBB voltage is a desired voltage, the VBB voltage can be maintained at the desired voltage.
However, with the aforementioned conventional semiconductor memory device, although the VBB voltage can be actively lowered by activating the charge pump circuit, there is no function for raising the VBB voltage. Originally, if left free, the VBB voltage rises naturally due to leakage current, for example, in due time. Moreover, because the requirements for voltage control of the VBB current were not particularly stringent (for example, about xc2x150 mV fluctuation), it was adequate to provide only a function for lowering the VBB voltage.
As mentioned above, however, if the VBB voltage, which is a negative voltage, is used as the plate power source of the memory cell capacitor, then more stringent voltage control for the VBB voltage (for example, about xc2x110 mV fluctuation) becomes necessary. Also, ordinarily, due to reductions in power, the ability of the VBB voltage generating circuit to supply negative current is limited, that is, there is a high output impedance. Thus, when writing data to the memory cell capacitor, the memory cell plate voltage fluctuates due to capacitive coupling. If the VBB voltage rises due to this capacitive coupling, the VBB voltage can be lowered to the set voltage by operating the charge pump circuit. However, if VBB falls below the set voltage, it takes time for the VBB voltage to return to the set voltage, because the conventional VBB voltage generating circuits do not have a function for lowering the voltage. If data are read out from the memory when the VBB voltage is lower than the set voltage, the read voltage becomes low due to coupling, and this is problematic because it leads to the read out of erroneous data.
The above problem is not limited to semiconductor memory devices, and is common to general semiconductor integrated circuit devices having a configuration in which negative voltage (VBB voltage) generated by a negative voltage generating circuit is supplied.
Therefore, in light of the foregoing conventional problems, it is an object of the present invention to provide a semiconductor integrated circuit device onto which is installed a circuit for raising the VBB voltage so as to raise the VBB voltage quickly and control the VBB voltage at high speeds, thereby achieving voltage stability and preventing malfunctions.
To solve the foregoing problems, a semiconductor integrated circuit device of the present invention is provided with a charge pump circuit for outputting a predetermined negative voltage to a negative voltage node, a voltage detection circuit for generating a first detection signal when the voltage of the negative voltage node has reached a first detection voltage and for generating a second detection signal when the voltage of the negative voltage node has reached a second detection voltage, an oscillator that is driven in response to the first detection signal so as to generate a signal for driving the charge pump circuit, and a negative voltage raising circuit that has an output terminal connected to the negative voltage node, and that is driven in response to the second detection signal so as to raise the voltage of the negative voltage node through the output of its output terminal.
With this configuration, when the negative voltage falls below the second detection voltage, the voltage detection circuit generates a second detection signal, and in response to this second detection signal, the negative voltage raising circuit supplies current to the negative voltage node and thereby raises the voltage. Consequently, the function for raising the negative voltage is activated when the negative voltage is lower than the second detection voltage. By performing this control to raise the negative voltage quickly, a more stable negative voltage can be supplied to the load and malfunction of the semiconductor integrated circuit device can be prevented.
The second detection voltage may be lower than the first detection voltage.
The voltage detection circuit may have a configuration that includes a first comparison voltage generating circuit for outputting a first comparison voltage and a second comparison voltage in response to the voltage of the negative voltage node, a reference voltage generating circuit for outputting a reference voltage, a first amplifier for comparing the reference voltage and the first comparison voltage and amplifying the voltage difference between them to generate the first detection signal, and a second amplifier for comparing the reference voltage and the second comparison voltage and amplifying the voltage difference between them to generate the second detection signal.
The first comparison voltage generating circuit may have a configuration that includes a first resistive element, a second resistive element and a third resistive element, wherein one terminal of the first resistive element is connected to a constant voltage node, another terminal of the first resistive element is connected to one terminal of the second resistive element, another terminal of the second resistive element is connected to one terminal of the third resistive element, and another terminal of the third resistive element is connected to the negative voltage node. The second comparison voltage is the voltage of a node at which the first resistive element and the second resistive element are connected, and the first comparison voltage is the voltage of a node at which the second resistive element and the third resistive element are connected.
The reference voltage generating circuit may have a configuration that includes a fourth resistive element and a fifth resistive element, wherein one terminal of the fourth resistive element is connected to a constant voltage node, another terminal of the fourth resistive element is connected to one terminal of the fifth resistive element, and another terminal of the fifth resistive element is connected to a ground voltage. The reference voltage is the voltage of a node at which the fourth resistive element and the fifth resistive element are connected.
It is preferable that the fourth resistive element and the fifth resistive element have variable resistances, and that by changing the resistances of the fourth resistive element and the fifth resistive element, the voltage value of the reference voltage that is output from the reference voltage generating circuit can be changed.
Also, it is preferable that the first resistive element, the second resistive element, and the third resistive element have variable resistances, and that by changing the resistances of the first resistive element, the second resistive element, and the third resistive element, the voltage values of the first comparison voltage and the second comparison voltage that are output from the comparison voltage generating circuit can be changed.
It is preferable that each of the fourth resistive element and the fifth resistive element includes a plurality of resistors connected in series, a fuse is connected in parallel to at least one of the resistors, and the overall resistance can be changed by opening at least one of the fuses.
Also, it is preferable that each of the first, second, and the third resistive elements includes a plurality of resistors connected in series, a fuse is connected in parallel to at least one of the resistors, and the overall resistance can be changed by opening at least one of the fuses.
The reference voltage generating circuit may have a configuration that includes a fourth resistive element and a fifth resistive element, wherein one terminal of the fourth resistive element is connected to a constant voltage node, another terminal of the fourth resistive element is connected to one terminal of the fifth resistive element, and another terminal of the fifth resistive element is connected to a ground voltage, the reference voltage being the voltage of a node at which the fourth resistive element and the fifth resistive element are connected. At least one of the first, second, third, fourth, and fifth resistive elements includes a plurality of resistors connected in series, a fuse is connected in parallel to at least one of the resistors, and the overall resistance can be changed by opening at least one of the fuses.
It is preferable that the resistances of the plurality of resistors are set so that the negative voltage is changed linearly by trimming the fuse.
The negative voltage raising circuit may be a transistor having a control terminal for receiving the second detection signal, a terminal connected to a positive voltage power source, and a terminal connected to the negative voltage node. Alternatively, the negative voltage raising circuit may be a transistor having a control terminal for receiving the second detection signal, a terminal that is grounded, and a terminal connected to the negative voltage node.
The first amplifier and the second amplifier may have respective first and second current mirror-type differential amplifiers, and a constant current value of the transistor serving as a constant current source of the second current mirror-type differential amplifier is larger than a constant current value of the transistor serving as a constant current source of the first current mirror-type differential amplifier. Alternatively, each of the first amplifier and the second amplifier may have a three-stage current mirror-type differential amplifier.
The first comparison voltage may be lower than the second comparison voltage. It is preferable that the number of transistors making up the negative voltage raising circuit can be changed corresponding to the size of a load that is connected to the negative voltage node.
It is preferable that the device further includes a resistor, one terminal of which is connected to the negative voltage node and another terminal of which is connected to a load. In this configuration, a memory cell array further may be included, and that the load may be a memory cell plate of the memory cell array. Additionally, it is preferable that the size of the load can be changed depending on the number of installed memory bits, and that the number of transistors making up the negative voltage raising circuit may be changed in response to the number of installed memory bits. Also, it is preferable that the size of the load can be changed depending on the number of activated blocks of the memory cell array, and the number of transistors making up the negative voltage raising circuit can be changed in response to the number of activated blocks.
It is preferable that the device further includes a diode, one terminal of which is connected to a node connecting the resistor and the load, and that another end of the diode is connected to the ground voltage.
It is preferable that the device further includes a pad connected to a node connecting the resistor and the load, and that via the pad, voltage can be imparted from the outside and a voltage of the node can be detected. Also, it is possible that an output node of the negative voltage raising circuit is connected to a node connecting the resistor and the load, and that an output node of the negative voltage raising circuit is connected to the negative voltage node via the resistor.
The device further may include a resistor, one terminal of which is connected to the negative voltage node and another terminal of which is connected to a load. Further the first comparison voltage generating circuit may include a second comparison voltage generating circuit and a third comparison voltage generating circuit. The second comparison voltage generating circuit may have a sixth resistive element and a seventh resistive element, one terminal of the sixth resistive element being connected to a constant voltage node, another terminal of the sixth resistive element being connected to one terminal of the seventh resistive element, and another terminal of the seventh resistive element being connected to the negative voltage node. The third comparison voltage generating circuit may have an eighth resistive element and a ninth resistive element, one terminal of the eighth resistive element being connected to the constant voltage node, another terminal of the eighth resistive element being connected to one terminal of the ninth resistive element, and another terminal of the ninth resistive element being connected to a node linking the resistor and the load. The first comparison voltage is the voltage of a node at which the sixth resistive element and the seventh resistive element are connected, and the second comparison voltage is the voltage of a node at which the eighth resistive element and the ninth resistive element are connected.
In this configuration, it is preferable that each of the eighth resistive element and the ninth resistive element have variable resistances, and that by changing the resistances of the eighth resistive element and the ninth resistive element, the voltage value of the second comparison voltage that is output from the comparison voltage generating circuit can be changed. Also, it is preferable that one of the sixth resistive element and the seventh resistive element have variable resistances, and that by changing the resistances of the sixth resistive element and the seventh resistive element, the voltage value of the first comparison voltage that is output from the comparison voltage generating circuit can be changed.
It is preferable that a difference between a set voltage of the first detection voltage and a set voltage of a second detection voltage is larger than a maximum value of the total of an offset voltage of the first amplifier and an offset voltage of the second amplifier. Also it is also preferable that a capacitor is inserted between a reference voltage node to which the output of the reference voltage generating circuit is supplied and a ground voltage.
A method of manufacturing a semiconductor integrated circuit of the present invention is a method of manufacturing a semiconductor integrated circuit device with which the voltage value of the reference voltage that is output from the reference voltage generating circuit can be changed by adjusting the resistances of the aforementioned fourth resistive element and the fifth resistive element.
The method includes: preparing a semiconductor integrated circuit device including, in addition to the above configuration, a resistor, one terminal of which is connected to the negative voltage node and another terminal of which is connected to a load, and a pad that is connected to a node connecting the resistor and the load, wherein a voltage of the negative voltage node can be detected via the pad; and detecting, during wafer testing, a voltage appearing on the pad and changing the resistances of the fourth resistive element and the fifth resistive element so as to adjust the voltage value of the reference voltage that is output from the reference voltage generating circuit.
The aforementioned semiconductor integrated circuit device with which the voltage value of the first comparison voltage and the second comparison voltage that are output from the comparison voltage generating circuit can be changed by adjusting the resistances of the first resistive element, the second resistive element and the third resistive element, can be manufactured through the following method.
The method includes; preparing a semiconductor integrated circuit device including, in addition to the above configuration, a resistor, one terminal of which is connected to the negative voltage node and another terminal of which is connected to a load, and a pad that is connected to a node connecting the resistor and the load, wherein a voltage of the negative voltage node can be detected via the pad; and detecting, during wafer testing, a voltage appearing on the pad and changing the resistances of the first resistive element, the second resistive element, and the third resistive element so as to adjust the voltage values of the first comparison voltage and the second comparison voltage that are output from the comparison voltage generating circuit.
Another semiconductor integrated circuit device of the present invention is provided with a charge pump circuit for outputting a predetermined output voltage to an output voltage node; a voltage detection circuit for generating a first detection signal when the voltage of the output voltage node has reached a first detection voltage and for generating a second detection signal when the voltage of the output voltage node has reached a second detection voltage; an oscillator that is driven in response to the first detection signal so as to generate a signal for driving the charge pump circuit; and an output voltage transition circuit that has an output terminal connected to the output voltage node, and that is driven in response to the second detection signal so as to change the voltage of the output voltage node through the output of the output terminal to a direction reverse to a direction driven by the charge pump circuit.
According to this configuration, when the output voltage of the charge pump circuit reaches the second detection voltage, the voltage detection circuit generates a second detection signal, and in response to the second detection signal, the output voltage transition circuit changes the direction of the voltage of the output voltage node to opposite the direction in which it is driven by the charge pump circuit. Thus, by performing a control in which the voltage is rapidly shifted to the opposite direction even if the output voltage of the charge pump circuit exceeds the desired value, a more stable output voltage can be supplied to the load and malfunction of the semiconductor integrated circuit device can be prevented.

Semiconductor integrated circuit device and method of manufacturing the same

Matsushita Electric Industrial Co., Ltd.


A general user given beforehand a proxy right by an administrator is allowed to register a special user having the right to use an apparatus in a range of the function right equal to that of himself by operating a special user setting window.

1. Field of the Invention
The present invention relates to an image formation apparatus capable of personal authentication, a control method of an image formation apparatus, and a computer readable medium having a software program stored therein, and relates to an authentication technique for permitting use of an image formation function.
2. Description of the Related Art
Some of image formation apparatuses such as copiers, printers, scanners, facsimile machines, and MFP (Multi Function Peripheral) which is a combination of these include a personal authentication function for preventing information leakage resulting from unauthorized use.
According to image formation apparatuses of this kind with the personal authentication function, for example, only an administrator and general users individually registered by the administrator are permitted to use the image formation apparatus. This prevents information leakage resulting from unauthorized use.
However, in the absence of an administrator, inconvenience may be caused in use of the apparatus. For this problem, Japanese Laid-Open Patent Publication No. 2002-109172 discloses that, in the absence of an administrator who administers a computer system, one of users is granted a proxy right as an administrator by obtaining approval of a plurality of users.
However, it takes much time and trouble to obtain approval by a plurality of users, thereby complicating the application process for proxy right. In addition, if a proxy user is given full power of the administrator, security concern arises. Moreover, it is not preferable in terms of security that the proxy right which is exceptionally given because of the absence of an administrator is reserved for an indefinite time.

Image formation apparatus capable of personal authentication, control method of image formation apparatus, and computer readable medium having software program stored therein

Konica Minolta Business Technologies, Inc.


The invention relates to a synchronous machine with hybrid energization, in particular a generator for supplying the electrical system of a motor vehicle, comprising a laminated stator (16) with a multiphase stator winding (18) and a laminated rotor (20) with an energizer winding (29), which together with permanent magnets (24,25) around the rotor periphery, provides the energization for the machine. According to the invention, favorable electrical and magnetic properties and an improvement in manufacturing conditions of the machine can be achieved, wherein the grooves (40) for the energizer windings (29) are disproportionately enlarged in relation to the groove base (44) and are preferably bell-shaped.

The invention is based on an electric machine, such as is described in the older German patent application DE 10 2007 025 971.0. Such a hybrid-excited synchronous machine is suitable, in particular, for supplying the power supply of motor vehicles, wherein said synchronous machine is used in a multi-phase stator winding system in the generator mode with regulated induced voltage, and the poles of the rotor are excited on a permanently magnetic and/or electric basis.


A stripping corner for an inside form, such as for forming the inside corner of an elevator core in building construction for pouring concrete, is provided that includes a powered actuator that forcibly collapses the perimeter of the inside form, particularly the inside corners of the form, to allow displacement of the inside form from the formed concrete surface to strip the inside form from the concrete.

When concrete elevator cores are built on jobsites inside corners are required. Inside forms are used to form the inside of the elevator core. Once the concrete has set the inside forms must be stripped inside the elevator core. Typically, to strip the inside form, provisions must be made to forcibly decrease the perimeter of the form to break the form from the concrete and strip the form. This is necessary in order to reuse the form at the next elevation of forming to pour another course of concrete on top of the previously poured course. A self-lifting form, such as described in U.S. Pat. Nos. 9,611,663; 9,279,260 and/or 8,020,271 is used to move the inside form up the elevator core. These patents are herein incorporated by reference. In this way, the elevator core is cast course-by-course from a lowest elevation to a highest elevation, to complete the elevator core for the building.
One of the present design inside corners for self-lifting forms involves the use of a steel inside corner approximately 7″×7″. This inside corner is bolted to the adjacent form panel with an approximately ½″ thick rubber spacer. In order to strip this corner there are plates welded to the steel channel walers that meet at the inside corner.
These plates have two sets of holes through them, one set that overlaps (i.e., not precisely aligned or registered) and another set that is aligned. In order for the corner to strip away from the formed concrete, a tapered pin is driven out of the aligned set of holes and into the overlapping holes. This causes the overlapping holes to come into alignment. When the overlapping holes are aligned, the steel corner is caused to bend and flex. The rubber spacer also compresses on one edge. This causes the corner to collapse enough to allow the corner form to strip and the formwork to be raised.
In order to strip and reset the present design corner, a workman with a large hammer must climb up the formwork. The formwork may be as high as 18 feet. There are up to four different locations, at different elevations, where the driving of pins must be done in each corner. Once tied off at a location the workman must drive out a pin that is in the aligned position hole and re-drive the pin into the overlapping holes. Once this is done at all the corner locations the form can be raised. Once the form is raised to the next course, the workman once again must climb the formwork at all the pinning locations, drive the pin out of the overlapping hole or stripped position and then re-drive the pin into the aligned holes corresponding to the set position for forming and pouring concrete.
The present inventor has recognized that this must occur at all the pinning locations in all the corners. This involves significant climbing and work by workmen, and cost, to accomplish the task.

Power assisted stripping corner for forming concrete walls


An operating device for a manual transmission apparatus includes: a plurality of operation shafts, supported at a housing to move in an axial direction thereof and selectively engaging one of a plurality of shift gear sets by one of the plurality of the operation shafts being moved in the axial direction thereof; a shift-and-select shaft, supported at the housing, selecting one of the plurality of the operation shafts by rotating in a circumferential direction of the shift-and-select shaft and moving the selected operation shaft in the axial direction of the selected operation shaft by moving in the axial direction of the shift-and-select shaft; an operating portion for manually operating the shift-and-select shaft; and an inertia unit, including an engagement portion, which is engageable with the shift-and-select shaft, pivotably supported at the housing, and pivoting in response to a movement of the shift-and-select shaft in the axial direction thereof.

Generally, shift gear sets are provided to a synchromesh-type manual transmission apparatus in order to configure four to seven forward shift stages. Each of the shift gear sets is selectively engaged by means of a synchromesh mechanism. An operating device for performing a shift operation of the manual transmission apparatus includes fork shafts, each of which operates the corresponding synchromesh mechanism, a shift-and-select shaft for selecting and driving one of the fork shafts, a gear lever, which is operated by a driver, and an operation force transmitting mechanism for transmitting an operation force applied to the gear lever to the shift-and-select shaft. Generally, the shift-and-select shaft is configured so as to rotate in a circumferential direction and so as to move in an axial direction thereof. In a case where the shift-and-select shaft rotates in the circumferential direction thereof in order to select one of the fork shafts (a select operation), the shift-and-select shaft moves in the axial direction thereof in order to move the selected fork shaft in an axial direction thereof (a shift operation). On the other hand, in a case where the shift-and-select shaft moves in the axial direction thereof in order to select one of the fork shafts (a select operation), the shift-and-select shaft rotates in the circumferential direction thereof in order to move the selected fork shaft in an axial direction thereof (a shift operation). In the synchromesh mechanism, which corresponds to the selected fork shaft (a selected gear stage), when a sleeve of the selected synchromesh mechanism is shift-operated by the selected fork shaft, the synchronizer ring (an input side portion) and the selected gear (an output side portion) are frictionally engaged by an inner slide mechanism of the synchromesh mechanism, thereby synchronizing a rotation of the selected gear and a rotation of an output side shaft of the manual transmission apparatus. Accordingly, the sleeve and the selected gear are fittedly connected by an engaging mechanism of the synchromesh mechanism via the synchronizer ring and the selected shift stage is established. The operation force necessary in a process of the shift operation of the synchromesh mechanism is not constant. Furthermore, a reaction force may be generated when the synchronizer ring is frictionally engaged with the selected gear or when the synchronizer ring is fittedly connected with the selected gear, and such reaction force may be transmitted to the gear lever.
A demand for improving a shift feeling when performing the shift operation by controlling changes in the operation force or the reaction force of the synchromesh mechanism is increased. A shift device of a manual transmission apparatus for a vehicle, which is disclosed in JP2003-106449A, attempts to improve the shift feeling by using inertial action, which is generated when pivoting an outer lever, which pivots around a shift-and-select shaft and to which an inertia lever and an inertia mass are provided. Furthermore, according to a shift mechanism for a manual transmission apparatus, which is disclosed in JP2008-32158A, an inertia mass is configured so as to be relatively displaced on an inertia lever, which pivots around a shift-and-select shaft, so that an inertia generated when a shift operation is performed by a driver is increased and the inertia when the shift operation is not performed by the driver is decreased, in order to decrease vibration transmitted to a gear lever.
Further, in order to enhance inertial action when a shift-and-select shaft is moved in an axial direction, an inertia mass is attached and fixed at the shift-and-select shaft itself.
However, the shift device disclosed in JP2003-106449A and the shift mechanism disclosed in JP2008-32158A are adaptable to an operating device for a manual transmission apparatus, which is configured to shift-operate a fork shaft by rotating the shift-and-select shaft in a circumferential direction thereof. Therefore, the shift device disclosed in JP2003-106449A and the shift mechanism disclosed in JP2008-32158A are not adaptable to an operating device for a manual transmission apparatus, which is configured to shift-operate the fork shaft by moving the shift-and-select shaft in an axial direction thereof.
Further, in the configuration, in which the inertia mass is attached and fixed at the shift-and-select shaft itself, a mass of sufficient weight is not easily provided because an inside space of a manual transmission apparatus is not enough to accommodate the mass. Furthermore, the inertia mass acts in accordance with both a rotation of the shift-and-select shaft in a circumferential direction thereof and a movement the shift-and-select shaft in the axial direction thereof. Therefore, a select feeling at the time of select operation, in which the appropriate fork shaft is selected, may be deteriorated.
A need thus exists to provide an operating device for a manual transmission apparatus which is not susceptible to the drawback mentioned above.

Operating device for manual transmission apparatus


An image processing apparatus for performing an image processing on a body cavity image captured in a living body includes: a storage unit which stores information including image information of the body cavity image; a change amount calculator which reads out the image information of the body cavity image from the storage unit and calculates, in the read body cavity image, a pixel value change amount of a pixel of interest with a plurality of surrounding pixels located around the pixel of interest; and a candidate lesion region detector which detects a candidate lesion region in the body cavity image based on a calculation result of the change amount calculator.

1. Field of the Invention
The present invention relates to an image processing apparatus which detects a lesion in a body cavity image (or digestive organ image) captured in an inside of a living body, an image processing method, and a computer program product.
2. Description of the Related Art
Conventionally, as a processing of detecting a lesion with respect to a body cavity image captured in an inside of a living body, a technique of dividing the image into blocks, calculating color information of each block, and comparing a reference value for color information of a known lesion such as a bleeding site with a reference value for color information of a healthy tissue has been disclosed in Japanese translation No. 2004-521693 of PCT international application.
In addition, a technique of detecting a focal shadow (or calcification masses) with respect to a medical image has been known, for example, in Japanese Patent Application Laid-Open No. 2002-325762. In the technique presented herein, an image is scanned in sequence and an average of image values in a small region in which a pixel of interest is located in the center thereof is obtained for detecting a candidate focal shadow. A border of the candidate focal shadow is detected by categorizing each pixel in the small region into one of two groups depending on whether the pixel is larger or smaller than the average of the image values in the small region, obtaining an average of coordinate positions of pixels categorized into each one of the two groups, and extracting a place where a difference in distance among the coordinate positions is present. Thereafter, whether or not the region is a shadow caused by a focus is identified depending on a manner of a pixel value change in pixels lying between a pixel in the candidate focal shadow region and a pixel outside the region.
In Japanese Patent Application Laid-Open No. 2002-325762, a detection of a focal shadow by using the Quoit filter is disclosed as a conventional technique. The Quoit filter is formed by a circular filter and a ring filter surrounding the circular filter. When each pixel of an image is scanned by the Quoit filter, the circular filter shows a large value in a region where a luminance locally rises while the ring filter shows a small value. This enables a detection of a focus whose luminance is locally high.

Image processing apparatus, image processing method, and computer program product


In the present disclosure a system and method are described for removing fixed pattern noise. The system includes a positioning system for holding and positioning a target, an optical system for capturing images or the target, and a fixed pattern noise removal engine for identifying and removing fixed pattern noise. The fixed pattern noise removal engine preferably identifies fixed pattern noise by analyzing a reference image and target image.

The present invention relates in general to imaging systems and more particularly to filtering or noise removal methods for use with imaging systems.
Imaging systems are used in a variety of applications including the inspection of semiconductor wafers. Such imaging systems may be used to optically scan or capture images of the surface of a target such as a semiconductor wafer to measure the topography of a target surface. This topography may then be analyzed to identify manufacturing or material defects existing on the target. Such analysis is critical in diagnosing manufacturing problems to maintain a desired manufacturing throughput.
One problem that hampers the effectiveness of imaging systems is noise. Noise typically includes unwanted electrical or optical signals that distort and degrade the quality of the data collected by an imaging or inspection system. Noise may occur randomly as various external events may interfere with an imaging system. Noise may also recur regularly as some external events regularly effect an imaging system in the same manner, producing the same pattern of noise. This recurring noise may also be referred to as fixed pattern noise.
There are a several major sources of noise that effect imaging systems. These include camera and sensor noise, nonlinear response noise, optically created noise, photo statistical noise, misregistration noise, and optical aberration noise. Fixed pattern noise may result from a one or more of these types of noise. Other sources of noise may also contribute to fixed pattern noise. Characteristics of fixed pattern noise may include a similar pattern in all image data, a spatially fixed location of the noise, and a time varying complex phasor representing both the magnitude and phase of the noise.
Because noise represents an erroneous signal, noise significantly reduces the effectiveness of imaging and inspection systems. Accordingly noise can severely hamper the ability to identify and remedy manufacturing and material defects, negatively effecting manufacturing throughput and yield.
Therefore a need has arisen for a system and method for reducing fixed pattern noise in imaging systems.
A further need has arisen for a system and method for increasing the effectiveness of imaging systems used to identify defects in semiconductor manufacturing and materials.
In accordance with teachings of the present disclosure, a system and method are described for removing fixed pattern noise. The system includes a positioning system the can hold and position a target, such as a semiconductor wafer. An optical system is positioned proximate the target to capture images thereof and is also linked to a fixed pattern noise removal engine. The fixed pattern noise removal engine receives complete object wave data of both a reference image and a target image captured by the optical system. The fixed pattern noise removal engine utilizes a filter for fixed pattern noise removal by dividing the cross power spectral density of the reference image and the target image by the power spectral density of the reference image.
More particularly, the fixed pattern noise removal engine may identify fixed pattern noise by applying the filter to the reference image. Further, the fixed pattern noise removal engine may also remove the identified fixed pattern noise from the target image by subtraction on a pixel-by-pixel basis.
More particularly, the fixed pattern noise removal engine generates a Fast Fourier Transform (FFT) and a complex conjugate of the FFT of the reference image. The fixed pattern noise removal engine then generates the power spectral density of the reference image. The fixed pattern noise removal engine also generates a Fast Fourier Transform (FFT) and a complex conjugate of the FFT of the target image. The fixed pattern noise removal engine then generates the power spectral density of the target image. Finally, the fixed pattern noise removal engine calculates the cross power spectral density utilizing the power spectral density of the target image and the power spectral density of the reference image.
The present disclosure includes a number of important technical advantages. One important technical advantage is identifying the fixed pattern noise within the reference image and the target image by dividing the cross power spectral density of the reference image and the target image by the power spectral density of the reference image. This allows the system to identify fixed pattern noise and therefore removing fixed pattern noise. This method also acts to increase the effectiveness and sensitivity of imaging systems used to identify defects in semiconductor manufacturing and materials.

System and method for correlated noise removal in complex imaging systems


A fluororesin-containing composition comprising a fluororesin, a fibrous material coated by an electrically conductive oxide, an acrylic resin and a liquid medium wherein the weight ratio of the fluororesin to the fibrous material is from 95:5 to 50:50, and the weight ratio of the fluororesin to the acrylic resin is from 100:0 to 85:15. The coating formed from the composition has good heat, chemical and weather resistance and non-tackiness properties.

1. Field of the Invention
The present invention relates to a fluororesin-containing coating composition and the use thereof. More particularly, the present invention relates to a coating composition comprising a fluororesin, a fibrous material coated by an electrically conductive material, an acrylic resin and a liquid medium, which is suitable for forming a non-tacky, antistatic coating on a substrate.
2. Description of the Prior Art
A fluororesin coating is not only characterized with various desirable properties such as heat resistance, chemical resistance and weather resistance which are the inherent properties of the fluororesin but also non-tackiness, properties. Thus a fluororesin coating is useful for applications in which non-tackiness is required. However, since fluororesin is a good electrical insulator and easily electrostatically charged, a coating thereof is also easily electrostatically charged and absorbs dusts from the air, which is not acceptable for some applications. To overcome such a defect, it is proposed to add an electrically conductive material such as carbon black and metal powder to the fluororesin coating.
When carbon black is used as the electrically conductive material, the coating is black in color, which renders the coating impossible to freely color. When the coating containing carbon black is rubbed with another material, other material is blackened. Further, since carbon black easily agglomerates, it is necessary to disperse the coating composition containing the carbon black in a suitable mixing machinen, such as a ball mill for a long period of time in order to homogeneously disperse carbon black in the coating composition.
When the metal powder is used as the electrically conductive material, the conductivity of the coating does not increase proportionally the amount of the metal powder added. If a large amount of the metal powder is added to the coating composition, the stability of the composition is deteriorated and the mechanical strength of the coating is decreased.

Fluororesin-containing coating composition and use thereof


A condensate valve for condensate that is connectable to the inlet side of at least one oil/water separator of a compressor. The condensate valve is triggered for opening and closing via a blocking element. The outlet of the condensate valve discharges directly into a condensate collecting tank. The condensate valve also forms a pressure reducer for reducing the pressure of the outflowing condensate and discharges directly to the condensate collecting tank. Preferably, the condensate valve comprises a movable piston which can be pressed against a small-diameter opening of the valve seat when the condensate valve is closed by a blocking element. The piston has a larger cross-sectional area at its outlet side than at its inlet side on which condensate acts via an overflow line when the condensate valve has been opened. The overflow line can be formed by at least one through channel which extends axially through the piston.

1. Field of the Invention
The invention relates to a condensate valve for at least one oil-water separator on a compressor.
2. Description of Related Art
High and medium pressure compressors comprise oil/water separators for separation of oil and water from compressed air before the release of the pressurized air to the consumer. In particular, such a condensate drainage system is made as an automatic condensate drain by means of which all oil/water separators on high and medium pressure compressors can be automatically drained.
Some condensate drainage systems known to date are controlled by means of additional control air, and the system pressure of the compressor system is not reduced in the course of draining the condensate. When the condensate is drained, the drain volume thus becomes large and cannot be discharged directly into a condensate collection tank since the drained condensate must be decompressed beforehand in an additional tank. Due to the large drainage volume, the system pressure of the compressor system drops; this adversely affects the efficiency of the compressor system. When a condensate drainage system is actuated via additional control air, furthermore, there must be additional lines so that, viewed overall, a considerable effort for implementing such a condensate drainage system is necessary.
In other applications, the condensate valves are not attached directly to the oil/water separators of the compressor system, but are located separately, for which optionally still additional connecting lines must be provided between the oil/water separators and the condensate valves. For this reason, the construction, of course, also become more expensive.
There are also condensate drainage systems in which the condensate is discharged directly via piloted solenoid valves with a very small nominal diameter. The solenoid valves with a small nominal diameter are very sensitive to dirt, and moreover, these medium and high pressure solenoid valves for direct discharge of the condensate are ultimately expensive in their production costs. If, instead of solenoid valves with a small nominal diameter, one with a larger nominal diameter is chosen to avoid a tendency to fouling, such a large drainage volume is obtained that additional relief tanks, as intermediate tanks for the condensate, are necessary for decompression and damping.
There is also a condensate valve with an integrated solenoid valve which can be attached directly to an oil/water separator. This condensate valve, however, has an extremely complicated structure, is associated with high costs and is susceptible to faults since, to some extent, there are very small line cross sections in the condensate valve which easily tend to clog.


Therapeutic agents for degressive diseases in the central nervous system, which contain amide derivatives of dihydrocaffeic acid of the general formula (I) ##STR1## wherein, R.sub.1 and R.sub.2 and A are defined in the specification; the compounds exert a nerve growth factor inducing action and thus are effective for the prevention of the progression of degenerative diseases in the central nervous system and the therapeutic treatment thereof.

1. Field of the Invention
The present invention relates to amide derivatives of dihydrocaffeic acid and their application to pharmaceutical uses. More specifically, the present invention relates to amide derivatives of dihydrocaffeic acid which are capable of inducing production and secretion of a nerve growth factor (hereinafter referred to as NGF) in specific tissues in the brain and to pharmaceutical agents containing these derivatives as effective constituents for the prevention of the progression of degenerative diseases in the central nervous system and the therapeutic treatment thereof.
2. Description of the Prior Art
With extended average life expectancy, rapid progress in research has been made all over the world in order to establish methods for early diagnosis, ethiological study and therapeutic treatment of various gerontological diseases; degenerative diseases in the central nervous system are a major object of this research. In particular, senile dementia of Alzheimer type (hereinafter abbreviated to as SDAT), a typical disease of such diseases, is now becoming a big social problem because the number of the cases is markedly increasing, mainly in developed countries, and the patients suffer through a miserable progressive course. Although many researchers and clinicians have been intensively studying the pathology of this disease, particularly in recent years, the fundamental cause of the disease has not been elucidated and therefore no effective methods for the early diagnosis and treatment of the disease have been established.
However, a number of pathological observations demonstrates that the direct causes of the early characteristic symptoms of SDAT, such as memory failure and disorientation, are the progressive changes in large cell cholinergic nerve fibers which project into the memory and learning centers, i.e., the cerebral cortex and hippocampus, from the cerebral basal ganglia and dysfunctions in said controlled areas caused by this change. In fact, a few case reports showed that the symptoms were slightly improved by administering an acetylcholine biosynthesis precursor or a cholinesterase inhibitor as an activator to SDAT patients in order to activate the cholinergic system in the brain. However, in general, the observed effects were not so significant as expected.
Since discovery of NGF by R. Levi-Monterlcini, S. Cohen and others, considerable research on NGF has been carried out. To date, it has been proved by physiological experiments that NGF is an essential factor for differentiation and growth of sensory and sympathetic nerve cells in the peripheral nervous system, particularly in the embryonal period, and further for the survival of the sympathetic nerve cells and maintenance of their functions in the maturation period.
However, because NGF is a physiologically active substance which exists only in an extremely small quantity, accurate knowledge regarding distribution and movement of NGF in tissues, which directly demonstrates the action of NGF in the body, has not been attained in spite of intensive research for a long period of time. Only recently, a highly sensitive enzyme-linked immunosorbent assay (hereinafter referred to as ELISA) for an active subunit of NGF (beta-NGF, hereinafter simply designated as NGF) was developed and improved with sufficient sensitivity and specificity to study the matters described above (S. Furukawa et al.: J. Neurochem., 40, 734-744, 1983 and S. Korshing and H. Thoenen: Proc. Natl. Acad. Sci., USA, 80, 3513-3516, 1983).
Furthermore, the NGF gene was cloned and its structure was analyzed, which makes it possible to establish a method for the quantitative measurement of its messenger RNA (hereinafter abbreviated as mRNA) by using the complementary DNA (hereinafter abbreviated as cDNA) of beta-NGF (D. L. Shelton and L. F. Reichardt: Proc. Natl. Acad. Sci., USA, 81, 7951-7955, 1984 and R. Heumann et al.: EMBO J., 3, 3183-3189, 1984).
Then, using the techniques described above, it was proved that there is a positive correlation between the degree of control by the sympathetic nerve in the peripheral nervous system and expression of the NGF gene in the tissues being controlled.
More surprisingly, NGF is detected also in the central nervous system, particularly in the hippocampus, the neocortex, the septal area of the olfactory bulb and basal forebrain, the Broca's diagonal band and the large cell basal ganglia, and moreover mRNA concentrations are high in the hippocampus and the neocortex and are as low in the septal area of the basal forebrain as in other brain areas where NGF is not detected (S. Korshing et al.: EMBO J., 4, 1389-1393, 1985). Later these observations were re-examined one after another by other research groups (D. L. Shelton and L. F. Reichardt: Proc. Natl. Acad. Sci., USA 83, 2714-2718, 1986 and S. Whittemore et al.: Proc. Natl. Acad. Sci., USA, 83, 817-821, 1986).
These findings demonstrate that the NGF gene is expressed not only in the peripheral nervous system but also in the central nervous system and moreover that NGF is produced and secreted in the areas controlled by cholinergic nerve fibers which project into the neocortex and hippocampus, i.e., the memory and learning center, from the nucleus of origin of the cerebral ganglia, captured at the nerve endings and then brought to the cellular body of the nucleus of origin by reverse axon transport. It was proved by a series of physiological experiments that NGF is an essential factor for the survival of these cholinergic nerve cells and maintenance of their functions; it was thus proved from these observations that NGF specifically functions also in the central nervous system as one of the "nerve nutrition factors".
Later, these findings were re-examined by various research groups and also verified from research on NGF receptors and NGF distribution in the brain.
During the course of the research on the function of NGF in the central nerve system as a nerve nutrition factor, the present inventors concluded that although a direct cause of the disturbance in memory and learning, which is an early symptom of SDAT, may be progressive changes of the cholinergic nerve fibers and dysfunction caused by these changes in the areas being controlled, the disease may be caused more fundamentally by disturbance in production and secretion of NGF in these areas being controlled by responsible nerves.
In other words, the present inventors believe that marked improvement cannot be attained by conventional nosotrophic therapy for SDAT, for example by providing acetylcholine or by increasing availability of acetylcholine, but it may be far more effective as a therapy to secure the production and excretion of NGF in the cerebral cortex and hippocampus so as to stop a functionally vicious cycle established within the controlling nerves, if possible.
However, great pharmaceutical and pharmacological difficulties still exist in substitution therapy using NGF itself which is a protein having a molecular weight of more than 10,000 although a way of possible mass production of human type beta-NGF by cloning of the gene has opened. In particular, as to the application to the central nerve system, the prospect of development is still far from certain.
From the point of view mentioned above, for a substantial and effective NGF substitution therapy, it is of great importance to search for a low molecular weight molecule which can induce production and excretion of NGF in specified tissues. The present inventors have already reported on catechol derivatives which have this action (for example, Fukazawa: Japanese Patent Laid-open No. 53767/1990 and No. 152950/1990). Furthermore, there are reports by Furukawa et al. (Y. Furukawa et al.: J. Biol. Chem., 261, 6039, (1986) and FEBS Letters, 208, 258, (1986)).
As mentioned above, it is expected that compounds and modified compounds thereof, being modified based on pharmacological and pharmaceutical considerations, have a capability to promote production and secretion of NGF which functions as the "nerve nutrition factor" and acts on specific nerves in the tissues being controlled, and thus possibly increase the amount of available NGF to degenerated sites of the nerves by means of ordinary administration of said compounds, thereby recovering the functions of said specific nerves. In particular, use of these compounds for the therapy of SDAT, a disease in the central nervous system for which fundamental therapy has not yet been established, is ideal. If treated in the early stage of the disease and administered at the peripheral system, these compounds enhance capability of NGF production and secretion in the cerebral cortex and the hippocampus area in the central nervous system, prevent the progress of characteristic changes in the nerves being controlled by NGF, i.e., the cholinergic nerve system, and promote repair of damaged nerve cells or re-control by remaining nerve cells, thereby providing a revolutionary therapy based on the new action concept attributed to flexibility of brain functions.
However, later, research showed that none of the catechol derivatives so far reported were satisfactorily absorbable or retainable when orally administered. The present inventors continued their study in order to solve this problem and consequently found that the compounds of the present invention are increasingly absorbable when orally administered and their retention in the blood is highly improved as compared to the compounds described in Japanese Patent Laid-open No. 152950/1990 and No. 99046/1991 which were applied previously by the present inventors. Furthermore, it was found that the amount of NGF increased in various parts of brain when the compounds of the present invention were orally administered to rats, with which the present invention was deemed to be completed.

Amide derivatives of dihydrocaffeic acid and their application to pharmaceuticals