A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Additional embodiments are disclosed incorporating the programmable transistor array circuit.

Design of integrated circuits to perform newly identified functions has progressed for many years. Presently, system level designers who determine a need for a newly defined integrated circuit, for example to integrate a variety of functions into one chip, use two primary approaches. In the first known approach, a field programmable gate array (FPGA) is used. In the second known approach, application specific integrated circuit (ASIC) design is used. Each of these prior art approaches has disadvantages which are described in detail below.
FIG. 1 depicts a block diagram view of an application specific integrated circuit (ASIC) or "system on a chip" (SOC) design 100 that may be obtained using current cell based design approaches (CBD). In FIG. 1, an embedded functional module 101, which is a known function such as a microprocessor, RISC processor, analog to digital converter, radio transceiver such as for a mobile telephone or wireless device, or other known function such as a memory module, is incorporated with a plurality of user defined logic units. Another function 102 is also shown, which could be for example embedded memory. Logic cells 104 are shown disposed in rows in partition blocks 105. Routing channels 106 provide connections between the various blocks and logic cells.
FIG. 2 depicts a prior art design flow for performing integrated circuit design using a prior art CBD approach. The steps of FIG. 2 may be performed using electronic design automation (EDA) tools that are commercially available. In the first step, 211, a system design step is performed. System design may be performed using various tools that are commercially available, such as hardware description language (HDL) and VHDL descriptions, known functions may be available as reusable modules licensed by vendors such as processor and DSP modules and referred to as "IP", or callable routines, software modeling may be done in various environments. Typically system design is performed using high level descriptive constructs and simulations are then performed using the EDA tools to verify that the function specified by the behavioral HDL or VHDL model is correct. That is, the simulation verifies the design model in fact gives the right outputs for a given set of inputs or conditions, and that the design described will meet the overall functional requirements. In some cases multiple integrated circuits may be defined in a single system model, in other cases a specific integrated circuit may be defined.
Once the system definition for an integrated circuit is completed, the design flow transitions to a logic synthesis step 213. In automated logic synthesis, the behavioral model is replaced by a functionally equivalent register transistor level (RTL) or logic based model based on certain known functions by EDA synthesis tools. For example, selections between variables in the VHDL model may be replaced by a multiplexer RTL description; storage statements in the VHDL model may be replaced by RTL descriptions of registers or latches, delays may be replaced by delay lines, "add" statements may be replaced by an adder RTL representation, and so forth. The logic synthesis process results in a second description of the device which may then be verified functionally by another simulation and test process, typically using test patterns obtained in the simulations at the system design step.
After the logic synthesis 213 is complete, the device may be described as a netlist of logical functions that are technology independent. The functions may include register transfer language (RTL) or similar register and logic level descriptions including elements such as descriptions of adders, registers, multiplexers and the like. EDIF or other output formats may be provided for the logical level netlist.
Once the technology independent logic model for the cell based design is complete, the technology independent logic level description is again transformed, through the use of standard cell libraries and using technology mapping tools, to a netlist model of technology dependent standard cell or functional modules for known functions. The standard cell approach replaces technology dependent gate level models for the technology independent logical models. Gate loading, drive strength, and other specific parameters that vary with process technology may be considered in making the technology mapping. The new netlist is populated with the proper circuits from a standard cell library to implement the circuit desired in a specific semiconductor process. Once again, a verification process is needed to verify that the technology dependent gate level netlist and the cells and connections used in the gate level model fact are functionally equivalent to the behavioral model.
After the standard cell library is mapped onto the design, the automated design tools can place the elements of the circuit in a proposed circuit placement. A circuit designer may assist with placement based on certain parameters or design needs that the designer is aware of, for example a memory might be placed adjacent the outside of the integrated circuit to make it physically proximate to an external data buss. Alternatively, automatic placement tools may be used as are known in the art.
After placement is complete, the circuit layout process can continue. First, the global routing is performed at step 217. Automated route tools are executed which, using known cost functions based on the length of conductors, number of interconnects, resistance, power and metal migration requirements, and the pre-positioned routing channels provided by the placement tools, the major routing signals are placed, for example power, ground, clock and similar nets are routed in the global route step.
Following the global routing step, additional routing steps 227 and 219 are used to interconnect blocks as specified by the netlist, and detail routing of certain standard cell functions is performed. Following these steps a layout level model of the design is complete. Physical verification step 221 is performed to verify that the transistors and conductors specified are correctly coupled, and that no shorts or opens are formed.
The standard cell design flow ends at step 223 with a Graphic Data Systems II (GDSII) database. The GDSII output specifies graphical data describing the layout of the integrated circuit including the shapes for the transistors, the conductors, and the vias and contacts, etc. The GDSII output is formatted in terms of the individual layers and this data is needed to generate the photomasks to be used. The photomasks are used in a photolithographic semiconductor fabrication process to fabricate a wafer with a plurality of the circuit devices formed upon it. A set of masks for a new SOC may cost over 500,000 dollars to produce. The integrated circuit must then be manufactured from the set of masks in a semiconductor processing facility. Following manufacture of the silicon wafers, tests are run to verify the devices operate, the individual devices may be separated by a singulation step, additional tests performed, and integrated circuit packaging and additional testing of the individual integrated circuits are needed before the completed circuit is available to the customer. This cell based design process of the prior art thus requires expensive non-recurring manufacturing costs for the masks, package design, test pattern generation, and a lengthy turnaround time to get the first ICs completed for system verification.
Standard cell design manufacturing of SOCs or ASICs in the prior art is known to have several disadvantages. The need for a unique set of photomasks for each new IC defined incurs a substantial start up or non recurring engineering (NRE) cost. The use of random placements and routing results in circuit designs that may exhibit very wide process variation sensitivities. The time for producing the first integrated circuits may be very long. The engineering skills needed to design in the cell based design flow may not be present at all companies, as many different EDA tools are used and experience with system level, gate level, physical level integrated circuit layout and physical level design requirements such as packaging is necessary.
FIG. 3 depicts in a block diagram an integrated circuit 200 designed using an FPGA approach. Unlike the SOC CDB approach, for the FPGA approach a completed integrated circuit is provided as base material. The FPGA is configured with existing programmable logic functions and programmable interconnections. Automated design tools are then used to implement the customer design by mapping the design into the FPGA resources and to complete the process by programming functions and interconnections inside the FPGA device. Programmation may be accomplished by metal fuses, via programmation, non-volatile memory cells, or other means. At the end of the programming step, a completed integrated circuit is immediately available for use; no additional manufacturing time is required.
In FIG. 3 FPGA 200 is depicted. Functional module 201 may be a known complete IP function such as a processor, DSP, or embedded memory module which the FPGA manufacturer has provided. Routing channels 204 are provided with routing conductors already formed in a manner that allows connections between them to be made by interconnect programmation. Logic units 203 are provided in a predefined placement. Logic units 203 may include clocked circuits such as registers, storage elements and the like, as well as configurable logical blocks and other known functions such as multiplexers and buffers. Many rows of the logic units are provided. Initially, the functions of these logic units and the connections of these units are somewhat open. Simple EDA tools are used to create a programmation for the device and the tools are relatively inexpensive.
FIG. 4 depicts an example prior art design flow for designing an integrated circuit using an FPGA approach. Some of the steps in this top down design flow are similar to those in the CBD approach.
System design steps and logic synthesis steps 211 and 213 are similar to those described above and so will not be further described. After a technology independent circuit netlist is obtained, technology mapping step 231 is performed to create a netlist for implementing the design on the target FPGA. The FPGA is already a complete manufactured and packaged integrated circuit, except that the programmable functions and interconnections are yet to be formed, so the technology mapping step must use the available resources on the FPGA to implement the functions in the netlist, and once those are used no more are available. Thus, the EDA tools used may be aware of the resources available in a particular FPGA being used, which is provided by an FPGA definition tool 245.
The global routing step 233 is different from the global routing in the standard cell design flow. The routing conductors are already physically placed as the FPGA is a completed integrated circuit. Only the connections need be completed. Detail routing step 235 for the FPGA design flow does not actually route the conductors, but instead determines which conductors are to be interconnected. Several approaches are known for programming FPGAs. In one anti-fuses or fuses are blown to form connections. In another via programming is used to complete vertical connections between conductors formed overlying one another in different layers. In any case the completed netlist is again subjected to a physical verification step in 237 to ensure proper connections are formed. Finally, a programmation tool forms the completed netlist into the silicon device by programming an FPGA. In this design flow, the end step results in a functional integrated circuit without the need for additional manufacturing steps. The time to get the integrated circuit manufactured and tested is thus saved over the ASIC flow. However, each FPGA circuit must be programmed individually to produce the final design using an appropriate FPGA programming device.
Each of these prior art approaches to designing and producing a new integrated circuit has several disadvantages. Because FPGA devices are supplied as a completed IC with a variety of functions already implemented, and because the programmation blocks require additional circuitry, the devices are very expensive on a per unit basis and are therefore only economically useful at low volumes. Typically FPGA devices are not available at the most advanced technology nodes, for example current FPGA devices are available at the 90 nanometer technology node, while advances in semiconductor processing have moved to 60, 45, and now 32 and 28 nanometer technologies which offer smaller transistors, higher performance and lower power requirements, these advantages are not available to FPGA designers.
The prior art CBD approach has advantages over the FPGA approach in that it provides more flexibility in circuit design, allows access to more advanced semiconductor processes, and has a lower per unit cost in the long term and therefore is more useful for higher volumes. However, the CBD SOC or ASIC approach requires substantial additional expense to create a unique mask set, the cost to manufacture silicon wafers, test pattern development, as well as time and expense for performing packaging and additional tests that are required, and therefore the CBD approach incurs a lengthy delay to get the completed devices. These SOC devices are also known to have great sensitivity to process variations. Further SOC design requires additional design skills to perform that the customer may have to either hire, or purchase from another vendor, adding additional costs. Many companies simply do not have the resources to use this approach.
A continuing need thus exists for a cost effective customer specified integrated circuit design and production, and methods that overcome the disadvantages of the prior art.

This patent is subject to a terminal disclaimer.

Circuits and methods for programmable transistor array

Taiwan Semiconductor Manufacturing Company, Ltd.


To take advantage of the architecture of a systolic array tailored to perform sparse matrix multiplications, a weight matrix can be converted into a set of constrained fine-grained sparse weight matrices. The conversion process may include receiving a request to perform a matrix multiplication operation with a weight matrix, and determining that the weight matrix satisfies a sparsity condition to convert the weight matrix into a set of constrained fine-grained sparse weight matrices. The weight matrix can then be converted into a set of constrained fine-grained sparse weight matrices. Computer instructions can then be generated for an integrated circuit device to perform the requested matrix multiplication operation as a set of sparse matrix multiplication operations using the set of constrained fine-grained sparse weight matrices.

Artificial neural networks utilize a computational model with an architecture based on biological neural networks. An artificial neural network can perform computations using a set of weights. Through these computations, the weights are combined with input data (which can also be referred to as feature maps) to perform an inference operation. For example, for a computer vision application to detect an object, the artificial neural network can combine the weights with an input image to extract certain features of the object from the image. Based on the extracted features, the artificial neural network can generate a decision of whether the object is in the image. Artificial neural networks can be trained, using training data in a training operation, to learn about how to perform the inference operation for an application.
An artificial neural network can perform computations on data in the form of matrices to execute the training and inference operations. For example, input data and weights can be organized into matrices. The artificial neural network can perform various matrix computations (e.g., dot-product matrix multiplications) between the input data and weight matrices at each neural network layer for a computing task. The data and weights matrices can also be pre-processed to support the matrix computations.

Emulating fine-grained sparsity in a systolic array


A neural interface device that comprises an implantable microelectrode body. The implantable microelectrode body includes a neural interface probe, which includes a thin film metal trace connected to an interface pad and an amorphous silicon carbide insulation. The amorphous silicon carbide insulation surrounds the thin film metal trace to form an outside surface of the neural interface probe. The interface pad is exposed to an ambient environment of the neural interface probe through an opening in the amorphous silicon carbide insulation. Methods of manufacturing the neural interface device are disclosed.

Chronically implanted microelectrode arrays (MEAs) for recording extracellular neural activity are central to scientific studies of neural circuit function. In clinical applications employing brain-machine and brain-computer interfaces such MEAs are essential for recording electrical neural signals. Limitations to achieving chronically stable neural recordings with existing microelectrode arrays include reactive tissue foreign body response that encapsulates the electrodes and kills or damages neurons, and, a decline in device performance often characterized by a progressive decrease in neural signal amplitude and loss of viable recording channels. Likewise, chronically implanted MEAs are employed in clinical applications requiring the delivery of therapeutic electrical stimulation. Such stimulating MEAs have the same limitations as recording MEAs.

Neural interface probe employing amorphous silicon carbide

Board of Regents, The University of Texas System


The present invention discloses a method and a device for luminance correction so as to adjust the luminance of a digital image. The present invention is characterized in that luminance correction is performed according to R, G and B values of a pixel in the digital image such that the contrast between each color of the digital image is enhanced while luminance is being adjusted.

1. Field of the Invention
The present invention generally relates to a method and a device for luminance correction and, more particularly, to a method and a device for luminance correction to efficiently adjust luminance and enhance the contrast between each color of digital images.
2. Description of the Prior Art
With the arrival of the digital era, the digital video replaces the traditional analog video gradually. Owing to the popularity of digital video, digital image processing is being paid attention to.
Taking photography of digital cameras forming digital images for example, the sensing device of digital camera for detecting incoming light while taking picture is made of CCDs (charge-coupled device) in array arrangement. Each CCD has a color filter (red, green or blue). Therefore, each CCD can sense the intensity of a monochromatic light (R, G, or B) through its filter while light projects on the CCDs.
Accordingly, the process of taking pictures by the digital camera to produce digital images, at first, enables the light into camera lenses, senses the light and generates corresponding induced current, representing the R, G, or B value of a pixel, through the CCDs of the digital camera. The image processing unit of the digital camera generates the digital image utilizing the R, G, and B values of pixels. The colors of each pixel are seen as variable combinations of the so-called primary colors red (R), green (G), and blue (B).
In order to adjust the images shown on a display monitor, like a TV, a conventional method for luminance correction is to find out the corresponding luminance signal (Y) and chrominance signal (C) according to the R, G, and B values of pixels in an image. Luminance correction according to the prior art adjusts the luminance signal directly. In other words, the prior art directly adjusts the corresponding luminance signal of the digital image for luminance correction.
In the prior art method, although the luminance of a digital image can be adjusted, the luminance of each pixel is adjusted with the same gain value at the same time. Therefore, the degree of luminance correction for each pixel is identical. In other words, the contrast between each color in the digital image becomes lowered using the conventional method for luminance correction.
Therefore, there is need in providing a method and a device for luminance correction to prevent the contrast between each color from becoming lowered while adjusting the luminance of digital image. Furthermore, the present invention provides high luminance and improves the contrast between each color in the digital image while adjusting the luminance of digital images.

Method and device for luminance correction


A method for digital printing to reduce a printing image file size. The method may include receiving a plurality of printing orders, a printing order including a base image and printing size information; generating a plurality of raster image processor (RIP) orders corresponding to the printing orders; obtaining a plurality of printing jobs corresponding to the plurality of RIP orders; modifying the plurality of printing jobs such that a printing size of each printing job of the plurality of printing jobs is adjusted based on a size of the base image of the printing order corresponding to a respective printing job of the plurality of printing jobs and the base image of the printing order is repeated based on the printing size information of the printing order; and transmitting the modified plurality of printing jobs to one or more printers. Other aspects, embodiments, and features are also claimed and described.

Conventional digital printing systems generally exploit a small size of printing substrate (e.g., paper). As printing technologies advanced, the demand for printing on a large size of printing substrate (e.g., fabric) increases. When conventional digital printing systems use a small size of printing substrate, a printer may have enough memory capacity to load a printing image on the printing substrate. However, as the printing size linearly increases, the file size of the printing image exponentially increases. The exponentially increased file size may result in errors at the printer because the memory capacity for printing is limited and may not be sufficient for the exponentially increased file size. What are needed are systems and methods that address one or more of these shortcomings.

Digital printing auxiliary system and related methods


A method and device for performing spectrum analysis of a signal in a plurality of frequency bands with respective different frequency resolutions. The method includes a data acquisition step and a subsequent data evaluation step for every frequency band. The data acquisition step and the subsequent data evaluation step proceeds cyclically and continuously for every frequency band of the spectrum analysis. The corresponding device for performing spectrum analysis of a signal cyclically stores a scanning sequence of the signal for every frequency band in one circular buffer each. A discrete Fourier transformer uses the cyclically stored scanning sequences to calculate the spectral values pertaining to the respective frequency band.

1. Field of the Invention
The invention relates to a method and a device for spectral analysis of a useful signal or noise signal.
2. Related Technology
Analyzing a useful signal or noise signal with a spectrum analyzer or a noise-measurement station requires a spectral analysis over a broad frequency range. To achieve an efficient measurement of the signal or noise spectrum, the entire frequency range to be measured is subdivided into several frequency bands, each of which is measured with a different frequency resolution. For example, it may be meaningful to reduce the frequency resolution with an increasing frequency separation relative to the measured signal. As a result, lower-frequency frequency bands (frequency bands with a smaller frequency offset relative to the measured signal) are frequency measured with a higher frequency resolution than higher-frequency bands (frequency bands with a large frequency offset relative to the measured signal).
Modern spectrum analyzers typically operate according to the principle of superposition. With high frequency resolutions, the intermediate-frequency signal is sampled and subjected to a Fast Fourier Analysis (FFT). For low frequency resolutions, analog filters are used in the IF intermediate path and the analyzer is operated in a sweep mode.
With a spectrum analyzer operating according to the discrete Fast Fourier Analysis (FFT analysis), the total measuring time TMGes is obtained from the sum of measuring times TMi of the individual frequency bands. According to FIG. 1A, the measuring time TMi in each frequency band is once again composed of a multiple corresponding to the number of averagings of the additive combination of data-acquisition time TMesi—j and data-evaluation time TFFTi−j for the Fourier analysis with the addition of an averaging time TMiti and display time TDispi. The data-acquisition time TMesi—j in each frequency band is once again proportional to the frequency resolution of the respective frequency band. The total measuring time TMGes is therefore derived according to equation (1a).
                              T          MGes                =                                            ∑                              i                =                1                            M                                                                                T              Mi                                =                                    ∑                              i                =                1                            M                                                                                (                                                                    ∑                                          i                      =                      1                                        m                                                                                (                                                                  T                        Mesi_j                                            +                                              T                        FFTi_j                                                              )                                                  +                                  T                  Miti                                +                                  T                  Dispi                                            )                                                          (                  1                    a                )
A reduction of the total measuring time TMGes can also be achieved according to FIG. 1B with a compact data-acquisition to be implemented repeatedly corresponding to the number of averagings and a subsequent compact data-evaluation by means of Fourier analysis to be implemented repeatedly corresponding to the number of averagings. The total measuring time TMGes is once again obtained according to equation (1a). Only a parallelization of the data-acquisition and data-evaluation by means of Fourier analysis leads to a reduction of the total measuring time TMGes according to equation (1b)
                              T          MGes                =                                            ∑                              i                =                1                            M                                                                                T              Mi                                =                                    ∑                              i                =                1                            M                                                                                (                                                                    ∑                                          i                      =                      1                                        m                                                                                (                                          T                      Mesi_j                                        )                                                  +                                  T                  FFTi                                +                                  T                  Miti                                +                                  T                  Dispi                                            )                                                          (                  1                    b                )
Overall, a spectrum analyzer of this kind, which operates according to the discrete Fourier analysis in several frequency bands with different frequency resolutions, and which represents the prior art, provides an excessively long total measuring time by comparison. In particular, this excessively long measuring time is attributable to the intensive sequential data-acquisition for the individual frequency bands over several averagings. This sequential data-acquisition for the individual frequency bands leads to an intermittent time recording of the signal for the individual frequency bands, which disadvantageously necessitates a longer measuring time.

Method and device for performing spectrum analysis of a wanted signal or noise signal


A pulse frequency modulation (PFM) controller for controlling a switching mode power supply. The controller includes an output terminal for providing a control signal to turn on and off a current in the power supply to regulate an output of the power supply. A first input terminal receives a feedback signal related to the output of the power supply, the feedback signal exhibiting a ringing waveform when the current in the power supply is turned off. The controller also includes a control circuit configured to provide the control signal in response to the feedback signal. The control signal is adapted to turn on the current in the power supply when the feedback signal is substantially at a valley of the ringing waveform of the feedback signal. In an embodiment, such a PFM controller can reduce turn-on transition loss in a power supply and provides frequency dithering to reduce electromagnetic interference.

The present invention is directed to power supply control circuits. More particularly, the invention provides a method and system for Pulse Frequency Modulation (PFM) controller for controlling a switching mode power supply.
Regulated power supplies are indispensable in modern electronics. For example, the power supply in a personal computer often needs to receive power input from various outlets. Desktop and laptop computers often have regulated power supplies on the motherboard to supply power to the CPU, memories, and periphery circuitry. Regulated power supplies are also used in a wide variety of applications, such as home appliances, automobiles, and portable chargers for mobile electronic devices, etc.
In general, a power supply can be regulated using a linear regulator or a switching mode controller. A linear regulator maintains the desired output voltage by dissipating excess power. In contrast, a switching mode controller rapidly switches a power transistor on and off with a variable duty cycle or variable frequency and provides an average output that is the desired output voltage.
Compared with linear regulators, switching mode power supplies have the advantages of smaller size, higher efficiency and larger output power capability. On the other hand, they also have the disadvantages of greater noise, especially Electromagnetic Interference at the power transistor's switching frequency or its harmonics.
Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM) are two control architectures of switching mode power supplies. In recent years, green power supplies are emphasized, which require higher conversion efficiency and lower standby power consumption. In a PWM controlled switching mode power supply, the system can be forced to enter into burst mode in standby conditions to reduce power consumption. In a PFM controlled switching mode power supply, the switching frequency can be reduced in light load conditions. PFM-controlled switching mode power supply exhibits simple control topology and small quiescent current. Therefore, it is suitable for low cost small output power applications such as battery chargers and adapters.
Even though conventional PFM controllers are used in some applications, they suffer from many limitations. As discussed below, these limitations include inefficiency power utilization and electromagnetic interference.
From the above, it is seen that improved pulse frequency modulation techniques for switching mode power supplies are desired.

Method and system for pulse frequency modulated switching mode power supplies


A disc driving apparatus for stabbly driving a disc within a cartridge. In the apparatus, a vertical position of the disc to generate a force by an air pressure difference within the cartridge in the same direction as a force clamping the disc during rotation of the disc. A supporting member for supporting the cartridge or the disc is arranged such that the disc within the cartridge is positioned above the half height of the cartridge, so that a disc vibration is minimized during rotation of the disc to stabbly rotate the disc, thereby assuring a responsibility of recorded and reproduced information.

1. Field of the Invention
This invention relates to a disc driving apparatus, and more particularly to a disc driving apparatus that is adapted to drive a disc accommodated in a cartridge stabbly.
2. Description of the Prior Art
Generally, a disc, particularly a rewritable disc, having a high density is very sensitive to a contaminant such as dust, finger print, etc., and a physical damage such as scratch or the like. Accordingly, in order to protect the surface of the disc from the contaminant and the physical damage, the disc is usually accommodated in a cartridge made from plastic material, etc.
The disc cartridge is provided with an opening for exposing a part of information recording face. This opening is opened and closed by means of a shutter engaged thereto. The shutter is opened by a shutter opener when the cartridge is introduced to the disc driving apparatus, thereby rotating the disc in such a manner that a part thereof is exposed. Due to this, a non-symmetrical air flow is created around the rotating axis of the disc at the cartridge in which the disc is rotated. A pressure difference occurs within the cartridge because of the non-symmetrical air flow, so that the disc rotated within the cartridge vibrated constantly in a certain period. Particularly, a rotation speed of the disc is faster and a thickness of the disc is thinner, such a disc vibration appears more seriously.
As described above, the disc vibration occurring upon rotation of the disc within the cartridge unstabilizes an information recording and reproducing operation of the disc driving apparatus, so that it causes a problem of depreciating a responsibility of information. Also, when the disc vibration becomes serious, a recording face of the disc collides with the inner surface of the cartridge, so that a fatal problem of suffering a physical damage such as scratch and so on in the recording face occurs. In order to solve these problems, strategies for minimizing the disc vibration has been studied.
Accordingly, it is an object of the present invention to provide a disc driving apparatus that is capable of driving a disc within a cartridge stably, to assure a responsibility of recorded and reproduced information.
In order to achieve the above and other objects of the invention, according to an aspect of the present invention, there is provided with a disc driving apparatus wherein a vertical position of the disc is set in such a manner that a force by a difference in an air pressure within the cartridge is generated in the same direction as a force clamping the disc during rotation of the disc.
According to another aspect of the present invention, there is provided with a disc driving apparatus comprising supporting means for supporting the disc at a level higher than a supporting surface of the cartridge by a predetermined height in such a manner that the disc is positioned above the half height of the cartridge.
According to still another aspect of the present invention, there is provided with a disc driving apparatus comprising supporting means for supporting the cartridge at a level lower than a supporting surface of the disc by a predetermined height in such a manner that the disc is positioned above the half height of the cartridge.
According to still another aspect of the present invention, there is provided with a disc driving apparatus wherein the disc is rotated in a state in which the disc is positioned above the half height of the cartridge.
According to still another aspect of the present invention, there is provided with a disc driving apparatus including means for accommodating the disc; and driving means for rotating the disc, wherein a position relationship between the accommodating means and the driving means is set in such a manner that the disc is positioned above the half height of the accommodating means.

Disc driving apparatus with a disk having a center plane positioned above half height of the cartridge


A vehicle having electrical storage devices with at least one of several electrical energy storage cells for supplying electrical energy to at least one vehicle-side consumer of electrical energy. At least one receiving device that is or can be arranged in the subfloor of the vehicle for accommodation of electrical energy storage cells, which include at least two separate receiving parts for accommodation of electrical energy storage cells. At least two receiving parts are connected to at least one connecting bar extended between them, wherein in and/or on the at least one connecting bar at least one line connection is formed for electrical connection of the energy storage cells accommodated in the respective receiving parts and/or at least one line connection for guiding a temperature-control fluid to control temperature in the energy storage cells accommodated in the respective receiving parts.

The invention relates to a motor vehicle comprising at least one of several electrical storage cells comprising an electrical energy storage device for supplying electrical energy to at least one consumer of electrical energy on the side of the motor vehicle.
It is known that motor vehicle-side consumers of electrical energy, under which term is to be understood in particular also a drive unit or parts thereof forming electrical machines, can be or are supplied with electrical energy from at least one energy storage device built on the side of the motor vehicle. Such devices for storage of electrical energy generally include a number of electrically interconnected energy storage cells. According to a popular design form for such an electrical storage device, an electrical storage unit is formed from several lithium-based energy storage cells. The energy storage cells forming the electrical storage unit are typically accommodated in a receiving device in an energy storage device housing.
What needs to be improved in the existing technology described above is that the fact that the receiving device usually takes up a significant amount of space, which is in any case scarce on the vehicle-side. Therefore, only a limited number of arrangement possibilities are available for such receiving devices.

Motor vehicle and receiving device for receiving electrical energy storage cells


A rare earth optical temperature sensor is disclosed for measuring high temperatures. Optical temperature sensors exist that channel emissions from a sensor to a detector using a light pipe. The invention uses a rare earth emitter to transform the sensed thermal energy into a narrow band width optical signal that travels to a detector using a light pipe. An optical bandpass filter at the detector removes any noise signal outside of the band width of the signal from the emitter.

The invention described herein was made by employees of the United States Government and may be manufactured and used by or for the Government for Government purposes without the payment of any royalties thereon or therefor.
The present invention relates to temperature sensors and in particular to high temperature optical temperature sensors.
Selective emitters are devices for converting thermal energy into narrow band radiation or energy. Most solid state materials have nearly a constant spectral emittance (gray body). The spectral emittance of a rare earth is characterized by several emission bands in the visible and near infrared region resulting from electronic transitions from the lowest excited states. Materials containing rare earths (e.g., ytterbium (Yb), erbium (Er), thulium (Tm), dysprosium (DY), and holmium (Ho)) can emit in narrow wavelength bands in the visible and near infrared region of the spectrum.
Selective emitters have been used in thermophotovoltaic energy conversion systems such as those described in U.S. Pat. Nos. 4,584,426 and 5,080,724.
Many existing temperature sensors are unsuitable and/or uneconomical for use in high temperature (greater than 2,000xc2x0 K) harsh environments. For example, metal thermocouples suffer from high thermal conductivity (e.g., 1 W/cmK) that conducts heat away from the measurement site, causing errors in the measurement. Other sensors may require sophisticated electronics or other techniques to eliminate errors from the measurements.
An optical temperature sensor includes an emitter having a selective energy emission band. The emitter emits energy within the emission band in response to the emitter temperature. The sensor also includes a light pipe having a first and a second end. The first end communicates with the emitter. Also included is an optical bandpass filter communicating with the second end. The filter has a pass band corresponding to the emission band. Also included is a detector communicating with the filter. The detector detects the emitted energy as a measure of the temperature.

The United States of America as represented by the Admistrator of NASA


According to some embodiments, a system, method, means, and/or computer program code are provided to facilitation a compression of information. In some cases, uncompressed data may be divided into a plurality of portions. A first data density value may be determined for a first portion, and a second data density value may be determined for a second portion. Based on the first data density value, the first portion may be encoded using a first encoding technique. Similarly, the second portion may be encoded using a second encoding technique based on the second data density value. A compressed representation of the uncompressed data may then be stored in accordance with results of said encodings of the first and second portions.

In some cases, it may be desirable to create a compressed version of data. For example, a business intelligence application might create a compressed version of a warehouse data index to reduce an amount of memory or disk space required to store the index and/or to improve performance of the application.
The use of a single encoding technique to compress such information, however, may have disadvantages. For example, one encoding technique might be inefficient when the density of the information is relatively low (e.g., the information includes many long strings of "1" or "0"). Similarly, another encoding technique might be inefficient when the density is relatively high (e.g., the information is more random in nature).
It would therefore be desirable to provide improved methods and systems that facilitate the compression of information such as business data in an efficient manner.

Systems and methods associated with hybrid paged encoding and decoding


Methods and computing devices enable users to identify documents using a hash value mapped to a word mnemonic for easy recall and comparison. A hash algorithm may be applied a document to generate a distinguishing hash value. The hash value is mapped to a plurality of words to form the mnemonic. To obtain the words, the hash value may be mapped to word indices used to identify particular words in word lists. Word lists may include a list of nouns, a list of verbs, and a list of adverbs or adjectives, so that the resulting three word mnemonics are memorable. More word lists may be used to map hash values to four-, five- or more word mnemonics. The number-to-mnemonic mapping methods may be used to map large numbers, such as account numbers, telephone numbers, etc. into mnemonics which are easier for people to remember and compare.

In the computer arts there are many situations in which users are provided with very large numbers that users must recall. Such numbers include document file names, document version and date stamp values, and hash values. Such large numbers add to the blizzard of other large numbers that people are expected to memorize, including social security numbers, employee numbers, telephone numbers, badge numbers, combinations, zip codes, passwords, personal identifier numbers (PIN), etc. Studies have shown that most people have difficulty remembering numbers longer than four digits, yet the variety and quantities of long numbers and random letter combinations that people are expected to memorize (e.g., PINs) only seem to increase with each new technological innovation.
Another problem in the computer arts concerns tracking and distinguishing various versions of large documents, such as complex computer software programs. Small changes to such documents can be difficult to identify and yet may have significant impact on the usefulness of the document. Typically documents are saved under a single file name, with changes and subsequent versions saved to the same file name. Thus, a document's file name is not a reliable means for distinguishing different versions. Adding version numbers and time-stamps to documents and file names can be helpful, but are not fool proof, especially in cases where multiple people are working on "branches" of the same document. Also, users may forget version numbers and time stamps as, again, the complexity of such numerical data is difficult to remember.

Method and apparatus for generating hash mnemonics


An artificial tree suitable for interior or exterior use capable of being formed in a variety of possible configurations simulative of a natural palm tree. The artificial tree has a body consisting of a trunk with one or more branch segments joined thereto, a plurality of leaf assemblies joined to the upper end of each branch segment, and a base for retaining ballast material capable of supporting the tree in a generally upright orientation. To enhance the appearance and stability of the tree, triangularly shaped trunk support members may be attached to the lower end of the trunk. Similarly, simulative decaying fronds joined to the upper end of each branch segment enhance appearance. Leaf assemblies having nested leaves of metallic sheet material provide shade. The base, having attached seat members, permits users to sit comfortably beneath the shade provided by the instant tree.

The benefits of artificial trees over their natural counterparts are well known. Artificial trees require little maintenance. Such trees need not be watered, pruned, or sprayed with insecticide to remove unwanted pests. Furthermore, they shed no leaves, are green year-round, and provide desirable shade from the hot sun. Additionally, artificial trees bearing a resemblance to exotic species, such as palms, provide their high latitude owners with the ongoing and pleasant illusion of life in warmer climes. Unfortunately, most artificial trees available in the marketplace of today presenting a palm-like appearance suffer from their inability to withstand the effects of long-term exposure to the elements. A need, therefore, exists for a weather resistant artificial palm tree.

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A zipper hand with puller fixed function includes a body, a hook element, a connected element, a puller and a buckled means, wherein the hook element is disposed on the body, one end of the hook element has a hook portion inserted into two guiding grooves of the body, one end of the connected element is connected to a top of the body and contacted to an inner edge of the hook element, the puller is connected to the connected element, and the buckled is disposed between the body and the puller. When the zipper hand is in a buckled state, the puller can be buckled and fixed on the body, and do not worry about the puller is raised up, so as to maintain the zipper hand in the buckled state, for avoiding the zipper hand being loosed and occurring an unexpected move.

The present invention relates to a zipper hand with puller fixed function, especially to a self-locking zipper hand which can fix the puller on a body thereof, and do not worry about the puller is raised up, so as to ensure the zipper hand to maintain the buckled state.
Referring now to FIG. 1, a zipper hand of the prior art includes a body 100, a hook element 200 and a puller 300, wherein the body 100 has two guiding grooves 101, the two guiding grooves 101 can receive the zipper 400, the hook element 200 is made of an elastic metal material and received in the body 100, the hook element 200 has a hook portion 201 inserted into the guiding groove 101 of the body 100, for buckling the hook element 200 on a chain of the zipper 400 and getting the buckled function; whereby, when the puller 300 do not move yet and in a buckled state, so as to form a self-locking zipper hand. The puller 300 is pivoted on a top of the body 100, and the pivotal shaft 301 of the puller 300 is contacted with an inner edge of the hook element 200, hence when the puller 300 is pulled up, it can be moved upwardly with the hook portion 201 of the hook element 200 and separated from the zipper 400 of the guiding groove 101, to make the zipper hand can smoothly move on the zipper 400 for controlling the zipper 400 to be combined or separated.
However, even if the zipper hand of the prior art is in a buckled state, the puller still probably be raised up by itself and moved non-carefully, so as to cause the hook portion 201 be separated from the guiding groove 101, and the zipper hand will be loosed and occur an unexpected move, so as to cause the separation of the zipper, especially to a zipper hand which installed on the shoe, it will generate more serious question due to above.
The primary object of the present invention is to provides a zipper hand with puller fixed function, when the zipper hand is in a buckled state, the puller can be buckled and fixed on the body, and do not worry about the puller is raised up, so as to maintain the zipper hand in the buckled state, for avoiding the zipper hand being loosed and occurring an unexpected move.
In order to achieve the above objects, the present invention provides a zipper hand with puller fixed function including a body having two guiding grooves, a hook element disposed on the body, and the hook element having a hook portion at an end thereof and inserted into the guiding groove of the body, a connected element having one end connected to a top of the body and contacted with an inner edge of the hook element, a puller connected to the connected element; and a buckled means disposed between the body and the puller, for buckling and fixing the puller on the body.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which:

No. 165, Lane 256, Sec. 2, Chung Shan N. Rd.


Substituted 1H-pyrrolopyridine-3-carboxamides and their use in pharmaceutical compositions and in treating inflammation are disclosed.

The present invention relates to novel substituted 1H-pyrrolo[2,3-b]pyridine-3-carboxamides having antiinflammatory activity and to pharmaceutical compositions and pharmacological methods employing such compounds.
Various 2-oxindole carboxamides are disclosed in the art. For example, U.S. Pat. No. 4,569,942 discloses certain 2-oxindole-1-carboxamide compounds having an acyl substituent at the 3-position as having analgesic and antiinflammatory activities. European published patent Application Nos. 0 181 136 and 0 173 520 disclose substituted 2-oxindole-3-carboxamides and tricyclic and quadracyclic compounds including the 2-oxindole-3-carboxamide unit as antiinflammatory agents. Various oxindole carboxamides have also been described in U.S. Pat. Nos. 3,634,453; 3,749,731; 4,686,224; and in European Patent Application Nos. 0 173 520; 0 164 860; 0 181 136; 0 137 163 and 0 156 603.


A gas-insulated high or medium voltage circuit breaker comprising: a first arcing contact and a second arcing contact, wherein at least one of the two arcing contact is axially movable along a switching axis, wherein during a breaking operation, an arc between the first arcing contact and the second arcing contact is formed in a arcing region; a buffer housing defining a pressurizing volume; a nozzle arranged at a nozzle side of the pressurizing volume, the nozzle defining a channel connected to the pressurizing volume and directed to the arcing region, for blowing an arc extinguishing gas towards the arcing region during the breaking operation, the nozzle comprising a nozzle front face facing towards the interior of the pressurizing volume.

Circuit breakers are well known in the field of medium and high voltage breaking applications. They are capable of being used for interrupting a current, when an electrical fault occurs. As an example, circuit breakers have the task of opening contacts and keeping them apart from one another in order to avoid a current flow even in case of high fault current and/or electrical potential originating from the electrical fault itself.
When interrupting the current flowing in the electrical circuit, an arc is generally generated. This arc is extinguished by quenching gas within the nozzle of the electrical circuit, such that the gap between the contacts repeatedly can withstand the voltage. Due to the high temperature of the arc high pressure pulses are generated by expansion of the quenching gas. Such pressure pulses can cause parts of the breaker to deform or even to destroy during breaking action.
Thus, there is a need for solutions to improve the operation of the circuit breaker, in particular of the nozzle, and/or the durability of the circuit breaker.

Nozzle for high or medium voltage circuit breaker


An air-hockey table having a playing surface, a plurality of air-conducting openings in the playing surface, a blower supplying air to the openings and a pair of goals, the improvement wherein the playing surface is non-planar and includes a smooth-curved surface having spaced-apart outer playing-surface regions and a central playing region which is lower than the spaced-apart outer playing-surface regions.

Many types of air hockey tables are known in the art. Traditional air hockey tables include a planar horizontal playing surface, a plurality of air-conducting openings in the playing surface, a blower supplying air to the openings and a pair of goals.
There is a continuous effort in the field of game tables, including air hockey tables, to create new and exciting challenges to players, including new strategies and game dynamics. Some of the advances in air hockey tables have involved adaptation for more than two players, changes in the playing surface outline, concurrent use of multiple pucks, and revised scoring mechanisms.
Air hockey players often become "addicted" to this fast-paced competitive table game, and are extremely interested in changes and developments in the field. Thus, there has been and remains a demand for novelty and interesting advances in the field. Nonetheless, the basic puck air-cushion action has remained basically unchanged for decades, despite the fact that competitive development efforts have been on-going.


The effects of interfacial transition between organic and inorganic layers of a lithographic printing member are ameliorated by incorporating an inorganic component within the matrix of the organic layer. In a first aspect, a lithographic printing plate having adjacent organic and inorganic layers is fabricated by depositing a curable polymer, softening the polymer, and integrating an inorganic material therewith. The polymer is then cured to immobilize the integrated deposition material, and the desired inorganic layer is applied over the deposited inorganic material (and any exposed portions of the polymer). In a second aspect, a graded structure is built up on a substrate in successive deposition steps. Both polymer precursors and an inorganic filler material are deposited in stages, with each stage containing a desired ratio of polymer to filler.

1. Field of the Invention
The present invention relates to digital printing apparatus and methods, and more particularly to imaging of lithographic printing-plate constructions on- or off-press using digitally controlled laser output.
2. Description of the Related Art
In offset lithography, a printable image is present on a printing member as a pattern of ink-accepting (oleophilic) and ink-rejecting (oleophobic) surface areas. Once applied to these areas, ink can be efficiently transferred to a recording medium in the imagewise pattern with substantial fidelity. Dry printing systems utilize printing members whose ink-rejecting portions are sufficiently phobic to ink as to permit its direct application. Ink applied uniformly to the printing member is transferred to the recording medium only in the imagewise pattern. Typically, the printing member first makes contact with a compliant intermediate surface called a blanket cylinder which, in turn, applies the image to the paper or other recording medium. In typical sheet-fed press systems, the recording medium is pinned to an impression cylinder, which brings it into contact with the blanket cylinder.
In a wet lithographic system, the non-image areas are hydrophilic, and the necessary ink-repellency is provided by an initial application of a dampening (or "fountain") solution to the plate prior to inking. The ink-abhesive fountain solution prevents ink from adhering to the non-image areas, but does not affect the oleophilic character of the image areas.
To circumvent the cumbersome photographic development, plate-mounting and plate-registration operations that typify traditional printing technologies, practitioners have developed electronic alternatives that store the imagewise pattern in digital form and impress the pattern directly onto the plate. Plate-imaging devices amenable to computer control include various forms of lasers. For example, U.S. Pat. Nos. 5,351,617 and 5,385,092 (the entire disclosures of which are hereby incorporated by reference) describe an ablative recording system that uses low-power laser discharges to remove, in an imagewise pattern, one or more layers of a lithographic printing blank, thereby creating a ready-to-ink printing member without the need for photographic development. In accordance with those systems, laser output is guided from the diode to the printing surface and focused onto that surface (or, desirably, onto the layer most susceptible to laser ablation, which will generally lie beneath the surface layer).
U.S. Ser. Nos. 08/700,287 and 08/756,267, the entire disclosures of which are hereby incorporated by reference, describe a variety of lithographic plate configurations for use with such imaging apparatus. In general, the plate constructions include an inorganic layer (i.e., a metal, combination of metals, or a metal/non-metal compound) situated on an organic polymeric layer. The inorganic layer ablates in response to imaging (e.g., infrared, or "IR") radiation. In one approach, the inorganic layer represents the topmost surface of the plate and accepts fountain solution, while the underlying polymeric layer accepts ink. In another approach, the inorganic layer serves only a radiation-absorption (rather than a lithographic) function, with the underlying layer accepting ink and an overlying layer either rejecting ink or accepting fountain solution. Ablation of the inorganic layer by an imaging pulse generally weakens the topmost layer as well, and this, combined with disruption of its anchorage (due to disappearance of the ablated inorganic layer), renders the topmost layer easily removable in a post-imaging cleaning step. With either of these two approaches, application of an imaging pulse to a point on the plate ultimately creates an image spot having an affinity for ink or an ink-abhesive fluid differing from that of unexposed areas, the pattern of such spots forming a lithographic plate image.
These types of plates can pose manufacturing challenges, as well as performance limitations, owing to the abrupt transition between an inorganic layer and an organic, polymeric layer. The divergent physical and chemical characteristics of such distinct layers can compromise their anchorage to one another--a critical performance requirement--as well as the durability of the inorganic layer. For example, because inorganic and organic materials typically have very different coefficients of thermal expansion and elastic moduli, even perfectly adhered inorganic layers may undergo failure (e.g., fracturing) due to temperature variations or the stress of plate manipulation and use. The different responses of two adjacent layers to an external condition can easily cause damage that would not occur in either layer by itself.
To improve interlayer anchorage, polymeric layers may be selected (or applied as intermediate coatings) based on chemical compatibility with inorganic material. A polymeric layer may also be pretreated (e.g., through plasma exposure) to modify the surface for greater interfacial compatibility with a subsequently applied inorganic layer. These approaches, however, have limited utility in addressing the effects of transition between fundamentally different materials.

Lithographic imaging with constructions having mixed organic/inorganic layers


An LTE base station (10-1) sets another LTE base station, which has an X2 connection established with the LTE base station (10-1), as a handover destination when at least one other LTE base station which has an X2 connection established with the LTE base station (10-1) is present among other LTE base stations that have been determined as handover destination candidates.

A radio communication system such as LTE (Long Term Evolution), which is currently undergoing standardization in 3GPP (Third Generation Partnership Project), requires not only an S1 connection that is a logical transmission path between a radio base station (hereinafter referred to as a "LTE base station") and a core network, but also an X2 connection that is a logical transmission path between radio base stations in order to achieve a quick handover, reduction in a processing load on the core network, and so forth.
In order to establish X2 connections, an LTE base station acquires information on other neighboring LTE base stations and retains a neighboring base station list (hereinafter referred to as a "neighbor list") as a list of the information on the other LTE base stations. The other neighboring LTE base stations are other LTE base stations located at short distances from the LTE base station. Only after retaining the neighbor list, the LTE base station can control establishment of the X2 connections, load balancing with the LTE base stations, restrictions during a maintenance work, and the like.
An ANR (Automatic Neighbor Relation Function) is one of conceivable methods for the LTE base station to acquire the neighbor list. The ANR is the method in which the LTE base station receives a measurement report transmitted from a radio terminal either periodically or on an event basis and acquires a neighbor list based on the measurement report (see Non-patent Document 1, for example).
Moreover, the LTE base station can request the radio terminal to perform a handover based on the measurement report from the radio terminal. The measurement report contains an ID of an LTE base station which is a sender of a signal (a BCH signal) received by the radio terminal through a broadcast channel (BCH), information on radio field strength of the signal, and the like. Based on the ID of the LTE base information and the information on the radio field strength contained in the measurement report, the LTE base station can identify an LTE base station for a handover destination and instruct the radio terminal to perform a handover at an appropriate timing.
In addition, the LTE radio communication system has a data forwarding function for performing handovers with few packet losses. The data forwarding function is a function with which just before a handover, an LTE base station forwards data, which is yet to be transmitted from the LTE base station to a radio terminal, to another LTE base station of a handover destination via an X2 connection. The LTE base station of the handover destination transmits the data, which is received via the X2 connection, through a radio channel to the radio terminal that is newly connected as a consequence of the handover. Thus it is possible to prevent packet losses in the handover.
For the LTE radio communication system, there are prescribed above-described handover involving data forwarding via an X2 connection (hereinafter referred to as an "X2 handover") and a handover involving data forwarding via an S1 connection (hereinafter referred to as an "S1 handover").

Radio base station and communication control method


A PWM type D/A converter having a first PWM converter, a second PWM converter and an analog adder. The digital input signals are designated as odd and even numbered input signals and the reference timing points for outputting odd/even numbered input signal are designated as odd/even numbered reference timing points. The first PWM converter receive the digital input signal to output signal whose rising/falling timing point is set at the earlier/later timing, the larger the value of the odd/even numbered input signal relative to the odd/even numbered reference timing point and the pulse width is determined by the values of the odd numbered input signal and the next even numbered input signal. The second PWM converter receives the digital input signal to output signal whose rising/falling timing point is set at the later timing, the larger the value of the even/odd numbered input signal relative to the even/odd numbered reference timing point and the pulse width is determined by the value of the even numbered input signal and the next odd numbered input signal. In another aspect the second PWM converter receives the digital input signal to output signal whose rising/falling timing point is at the later the timing, the larger the value of the odd/even numbered input signal relative to the odd/even numbered reference timing point and the pulse width is determined by complementary values of the odd numbered input signal and the next even numbered input signal.

The present invention relates to a PWM (Pulse Width Modulation) type D/A (digital-to-analog) converter used in demodulating, for example, a PCM (Pulse Code Modulation) audio signal.
In demodulation (D/A converting) a PCM audio signal by using a PWM type D/A converter (hereinafter called a PWM converter), it is necessary to modulate an audio signal into PWM waveforms symmetrical in time relative to certain timing point in order to avoid generating a phase error in a demodulated signal.
FIG. 1 shows the waveforms of output signals according to to a conventional PWM type D/A converter.
In FIG. 1, seven values from +3 to -3 are the values of digital input signals, T is the period (sample period) for input signals, and t is the period of a clock signal CK used for conversion. The resolution m of the conventional of PWM signals is given by: EQU m=T/(2t)-1 (1)
As seen from FIG. 1, since T/t=16, the resolution m becomes 7 from the equation (1). PWM signals corresponding to respective seven values +3 to -3 can therefore be obtained.
As described above, if a conventional PWM converter is used in demodulating PCM audio signals at high speed and with high resolution, it is necessary, as understood from the equation (1), to use a clock signal of very high frequency. The use of such a clock signal poses various problems such as an increase of unnecessary radiation which interferes other devices, and a difficulty in obtaining a stable oscillator element.

Digital to analog converter using pulse width modulator for independently setting edge position


This application describes apparatus and methods for distributing computing resources using edge-computing. Apparatus may include an edge node that is positioned in a target geographic region. The edge-node may include information needed to process transactions that occur locally in the target geographic region. The edge-node may process the transaction without communicating with a central server. The edge-node may support processing transactions on behalf of a variety of financial institutions and merchant processing systems. Processing the transaction locally may reduce computational resources typically required by region server to process high volumes of transactions. The edge-nodes would process transactions locally, close to a location of at least one party to the transaction.

A merchant may operate multiple channels that provide customers with access to goods and services (hereinafter, "products"). A merchant may provide access via an online store. The merchant may provide access via a mobile application. The merchant may provide access via brick and mortar locations.
Each channel utilized by the merchant may have its own set of resource requirements. For example, an online store may need to be hosted by a computer system that provides customers uninterrupted access to the online store. An application may need to be installed on a mobile device that has sufficient computing resources to secure and process customer interactions with the online store. A brick and mortar location may require human resources to adequately service customers.
Typically, a merchant may attempt to allocate resources to each access channel based on characteristics of the channel and customer demand associated with the channel. However, such an approach may cause inefficient use, and potential waste, of important resources. For example, a merchant may estimate that a computer server requires a target amount of resources to meet peak customer demand. Target resources may include memory, processing power and network bandwidth.
Computer servers for processing customer interactions (e.g., purchase transactions) may be built with resources to reliably handle a high volume of transactions. For example, computer systems may receive 150 million transactions per day that require authorization decisions. At peak demand computer systems may receive 65,000 transactions a minute. To consistently meet performance goals, such computer systems may be built with resources to handle 24,000 transactions per second.
However, peak customer demand may only occur for an hour or two during the day. Thus, for most of the day, the merchant has over supplied resources to this access channel. Furthermore, peak customer demand may occur more often than expected. Peak customer demand may exceed allocated resources. Thus, a during peak demand, a customer that attempts to access the access channel may be denied access or receive a delayed response from resources such as a computer server.
It would be desirable to reduce waste associated with underutilized resources. It would be desirable to improve the efficiency of resources deployed to provide customer access to merchant products. It would be desirable to improve utilization of resources deployed by the merchant and improve customer satisfaction and quality of service provided by the merchant.
Accordingly it is desirable to provide apparatus and methods for a LOCAL EDGE-NODE SERVER.


A multipoint recorder with a slow effective chart speed is operated to provide good visibility for the most recent record. A number of consecutive values for each point are scanned and stored. These values are recorded by a high speed printing mechanism during a first period of the recording cycle after which the chart is advanced forward for the remaining period of the recording cycle to a point which makes that record easily visible. At the end of the recording cycle the chart is retracted to start the next printing period with the printing mechanism at a point which corresponds to that required make the record look like a continuous line and to provide the desired time scale along the chart. To accomplish this the cycle time is coordinated to the chart speed and the number of consecutive scans recorded during each recording cycle.

This invention relates to multipoint strip chart recorders for recording trend lines for the values of the input signals representing a number of points and particularly to recorders designed for industrial use where slow chart speeds are desirable and where it is also desirable to be able to view with ease the most recent part of the record. Industrial strip chart recorders typically have a horizontally oriented paper drive roll which is motor driven so that chart paper is fed at a predetermined rate from a supply system, such as a paper supply roll or supply tray in the back of the recorder case, over the chart drive roll and down the front of the case, frequently over a vertical table, to a collection system, such as a take-up roll or a paper collection tray, depending on whether the chart is in the form of a roll or a fan-fold. In industrial applications the chart is frequently fed at a speed of 1 or 2 cm/hr with the intent that the position of any record on the chart should be indicative not only of the value of the variable being recorded but also of the time at which the variable was measured.
In single point recording the record is typically made by a pen which continuously draws a line on the chart indicating the trend of the variable. In such recorders the pen is frequently constructed so that it is recording the current value of the variable at a point on the front half of the drive roll so that the current value can be easily viewed from in front of the recorder. Such pen structures utilize a long curved end so that the mark made by the end of the pen is not obscured either by the scale of the recorder, typically just above the feed roller and toward the front, or by the pen carriage and its supporting track, usually just above the paper drive roll.
In multipoint recording when slow chart speeds are used the problem of getting good visibility of the most recent record is complicated by the size of the required printing mechanism. Generally these recorders are designed to make their record on the top portion of the paper drive roll, preferably at top-dead-center, in order to accommodate the large printing mechanism. That position, in combination with the presence of a scale above the chart, almost completely obscures the most recent record. Others have attempted to mount the printing mechanism forward of top-dead-center, but these arrangements have been found to be unsatisfactory because the printing mechanism, by itself, substantially obscures the recent record when it is mounted in a forward position.
In recorders using slow chart speeds, the problem of reading the most recent record is at its worst. In fact, that part of the record may not be visible to the operator until more than an hour after the record is made. Such a time delay is frequently found to be intolerable. Also, since recorders of this type are frequently arrayed in large numbers on adjacent vertical panels, they must not require that a great effort be expended in monitoring the recent values and their trend, for otherwise mistakes resulting from erroneous monitoring will be the likely result. In order for the user to not only be able to read the most recent record but also to have confidence in the accuracy of his efforts he should be able to see some blank chart above the most recent recorded values.
It is an object of this invention to provide a method and apparatus for effecting a multipoint record on a strip chart recorder while at the same time providing good visibility for the most recent portion of that record.

Method and apparatus for increasing visibility of trend lines on strip chart recorders


A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current electrode (32) overlying the control electrode (28). MOS transistor (11) has a first current electrode (54) underlying a channel region (56), and a source lightly doped region (58) and a source heavily doped region (60) overlying the channel region (56). A control electrode conductive layer (40) is laterally adjacent a sidewall dielectric layer (48), and sidewall dielectric layer (48) is laterally adjacent channel region (56). Conductive layer (40) functions as a gate electrode for transistor (11). Each of the transistors (10 and 11) is vertically integrated such as in a vertically integrated BiMOS circuit. Transistors (10 and 11) can be electrically isolated by isolation ( 64 and 66).

Planar transistors are often used to fabricate integrated circuits. A planar MOS (metal oxide semiconductor) transistor has a diffused source electrode and drain electrode separated by a channel region. Overlying the channel region is a gate electrode that is separated from the channel region by a gate oxide. A planar bipolar transistor has a base electrode, a collector electrode, and an emitter electrode formed usually by diffusion technology. Planar transistors, although used and useful in many integrated circuit applications, are substrate area intensive and consume a large amount of substrate area per transistor. In addition, with integrated circuit geometries decreasing into sub-micron ranges, planar transistors have various disadvantages. At smaller geometries and thinner oxide thicknesses, well documented problems such as hot carrier injection, leakage currents, isolation, short channel behavior, diffusion junction depths, and channel length variations are major problems in planar transistors.
To overcome some of the disadvantages described above for planar transistors, elevated source and drain MOS transistors, lightly doped drain (LDD) MOS transistors, single polysilicon and double polysilicon planar bipolar transistors and other improvements were developed. Although the improvements reduced some of the disadvantages listed above, the improvements had some undesirable characteristics. The primary undesirable characteristic is the fact that the improved transistors were, in most cases, as area intensive or more area intensive than the planar transistor and in many cases are complex to manufacture.
Various approaches have been used to try to reduce transistor surface area and increase transistor packing density while at the same time reducing some of the adverse effects described above. The surrounding gate MOS transistor (SGT) was developed wherein a spacer gate and planar diffusions are used to form a vertical transistor. The SGT reduced some of the disadvantages that affect planar MOS transistors and reduced surface area due to a vertically positioned spacer gate. Topography problems and the geometry of the SGT usually result in source and drain contacts that are difficult to achieve and are difficult to consistently produce using sub-micron technology. In addition, doping of source regions, drain regions, and channel regions via implants can be difficult due to geometry and may require special processing.
In order to further increase circuit density, the thin film transistor (TFT) has been developed, especially for memory applications. Although small memory cell areas can result via the use of TFTs, TFTs are highly resistive and therefore not adequate for all applications.

Method for forming vertical transistor structures having bipolar and MOS devices


Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an analog to digital converter circuit, a data detector circuit, a filter circuit, an error generation circuit, and a target parameter adaptation circuit. The analog to digital converter circuit converts an analog input into corresponding digital samples. The data detector circuit applies a data detection algorithm to a data set derived from the digital samples to yield a detected output. The filter circuit convolves the detected output with a target parameter to yield a target output. The error generation circuit calculates an error value based on the digital samples and the target output. The target parameter adaptation circuit updates the target parameter based at least in part on the error value.

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for adaptive data processing.
Various data processing circuits have been developed that include a variable gain amplifier that amplifies an analog signal to yield an amplified signal. An analog to digital converter circuit converts the amplified signal into a number of digital samples representing the amplified signal. The digital samples equalized to yield an equalized output, and the equalized output is further processed by data detector and/or data decoder circuitry to yield a data output. In some cases, the amplified signal is noisy to the extent that data processing is undermined.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for data processing.

Systems and methods for adaptive gain control


A method of resource-synchronizing data that is transmitted on a communication link having at least one data lane, between a first device and a second device, wherein the second device has a resource that is accessible based on an access schedule. In one operation, a timing offset of the second device based on the access schedule is determined, followed by delaying the transmission of data from the first device to the second device through the communication link by an amount of time equal to the timing offset so that the data is received at the resource when the resource is accessible according to the access schedule.

The data lanes that make up a data interface between two devices, or chips, are called a data link. The different lanes in the data link are typically synchronized to the slowest lane. The different lanes on a receiving device receive data segments of a data frame at different times. However, a complete data frame is only transmitted from one layer to another after the last data word has arrived at the receiving device and the receiving device is then able to accept the data. This delay in transmission can cause latency in high-speed communications between devices. Depending upon the delay of individual data segments and the time at which the data frame was transmitted, the data frame might not be available for immediate use by the receiving device, and therefore would have to be stored until it can be used by the receiving device. This incurs additional undesirable latency.
For example, and with reference to FIG. 1, data is transferred over an interface link 104a or 104b from at least one first device 102 to a second device 106, such as a device that has some kind of internal resource 108. Timing offsets are determined between each lane of the link 104 and the lane of the link 104 containing the slowest arriving data, which determines when the frame is ready to be forwarded to the next layer. A serializer/deserializer 110 (SerDes) contains a buffer to hold data from the various lanes during this synchronization or deskewing process.
If, after the data is link-synchronized in the manner described above, the resource 108 is not accessible, then a resource buffer 109 is used to store the frame data until the resource 108 is able to accommodate the frame of data.

Data synchronization for circuit resources without using a resource buffer


A process for the manufacture of plastic moldings with decorative coatings by injection molding, on an injection molding machine with an injection screw, which introduces the plastic into a cavity located in a mold clamping device, and an apparatus for the performance of the process.

1. Field of the Invention
This invention relates to a process for the manufacture of plastic moldings with a decorative coating, by injection molding in an injection molding machine, which injection molding machine has an injection screw which introduces the plastic into the cavity located in a mold clamping device. This invention also relates to an injection molding machine with an injection screw, which is connected by closable hot runners to the cavity of a clamping device consisting of a stationary mold part and a movable mold part, including the drive mechanisms, and with measurement and control components for the control of the process.
2. Background Information
The application of a decorative coating in the form of textiles, leather, films etc. to the surface of plastic parts is generally done by lamination. As an alternative to this relatively labor-intensive process, the bond between the materials can also be achieved in a single operation by rear injection. That is, the plastic can be injected directly onto the decorative coating, which decorative coating is placed within the mold.
The article from "Kunststoffe 80" (1990) 9, Page 997 ff. "Hinterspritzen von Dekormaterialien durch Niederdruckspritzgieaen" [Rear injection of decorative materials by low pressure injection molding] discloses a method of directly bonding the plastic and decorative materials to one another by injection molding, whereby the decorative materials, several millimeters thick, are rear injected with a thermoplastic material. That is, the decorative material is placed in the mold, so that the decorative material is bonded directly to the plastic during the injection process. This publication also describes pre-testing methods for the rear injection. This publication does not indicate any measures to minimize the pressure to prevent sink marks on ribs and changes in the wall thickness. That is, the decorative coating can be damaged and deformed during the injection process if pressures are too high.
At the Technical Conference on Decorative Moldings held at the South German Plastics Center on Nov. 15 and 16, 1990, reference was made to the use of injection compression devices or swelling molds. This publication also describes the use of a controlled hot runner with long flow distances, and thus the use of cascade technology. A precision regulation system for the data relevant to the injection with graphic display capabilities is also mentioned, and reference is made to the injection pressure. This publication contains no indication that the measurement factor to be used for the cascade control might be the distance travelled by the injection molding screw of the injection molding machine.
German Published Patent Application No. 39 27 995 relates to a process for the control of the holding pressure during the injection molding of thermoplastic plastics. The application discloses nozzle runners which can be closed by shutters, which nozzle runners inject molding compound into the cavity of the mold, and pressure signals which can be used to record the distance measurement signal from the injection screw (Column 4, Lines 9-17). This process, in which one or more desired molding parameters are set as a function of several process parameters recorded during at least one learning cycle to establish the mold-plastic pair, is complex and expensive.

Process for the manufacture of plastic moldings with decorative coating


A method of cell selection/cell reselection and a terminal are provided. The method includes acquiring measurement configuration information of beams, wherein the measurement configuration information includes the number of beams measured by a terminal; measuring the beams based on the measurement configuration information to acquire a measurement result of each beam; performing, based on the measurement result of each beam, the cell selection/cell reselection of a cell in which the terminal camps when the terminal is in an idle state.

In a Fifth Generation (5G) system, high frequency beamforming is introduced. Together with the high frequency beamforming, a Multi-beam scenario is also introduced. However, this scenario may have an impact on existing schemes including measurement in an idle state, cell selection, and reselection.
However, in the related art, there is no scheme for the measurement in the idle state in the Multi-beam scenario and the cell selection and reselection may not be performed, thus affecting communication reliability.

Method and terminal for cell selection/reselection


A hand operated orbital sander having a hand grip portion provided with a fluid supply inlet connected to a source of pressurized fluid and a fluid discharge; a base portion for mounting a sanding pad and having a chamber, a fluid inlet for directing fluid into the chamber and a fluid outlet for discharging fluid from the chamber; a resiliently deformable sleeve portion for connecting the base portion to depend from the hand grip portion and defining a conduit for placing the fluid outlet in flow communication with the fluid discharge; a fluid operated rotor rotatably supported by the base portion within the chamber and mounting an eccentric weight for imparting orbital movement to the base portion; and a flexible conduit for connecting the supply inlet to the fluid inlet to apply pressurized fluid to the rotor to effect rotation thereof.

The present invention relates to hand manipulated, pneumatically powered sanders.
In typical commercially available, pneumatically operated sanders, an air operated motor is arranged within a manually manipulated housing and connected by a drive shaft to a sanding pad via an eccentric drive.
In another construction, a sander is provided with an air turbine associated with a sanding pad supporting plate, and coupled to a manually manipulated housing by a plurality of resiliently deformable columns.


Methods are provided for fabricating a fin-type field effect transistor(s), having a channel region within a fin. The methods include: establishing a protective material above an upper surface of the fin, and an isolation material adjacent to at least one sidewall of the fin, the isolation material being recessed down from the upper surface of the fin, for instance, for approximately a height of the channel region within the fin; and providing a punch-through stop dopant region within the fin below the channel region, the providing including implanting a punch-through stop dopant into the isolation material and laterally diffusing the punch-through stop dopant from the isolation material into the fin to form the punch-through stop region within the fin beneath the channel region.

Fin-type field-effect transistor (FinFET) devices continue to be developed to replace conventional planar metal oxide semiconductor field-effect transistors (MOSFETs) in advanced complementary metal oxide semiconductor (CMOS) technology. As is known, the term "fin" refers to a vertical structure within or upon which are formed, for instance, one or more FinFETs or other fin devices, including capacitors, diodes etc. Advantageously, the fin structure helps to control current leakage through the transistor in the off-stage, and a double-gate or tri-gate structure may be employed to control other short channel effects.
Further enhancements in fin device structures and fabrication methods continue to be pursued for enhanced performance and commercial advantage.

Fabricating fin-type field effect transistor with punch-through stop region