According to an aspect, there is provided a spectrometer comprising a first and second enclosed volumes. The second enclosed volume is formed by an absorption cell for containing a sample gas. The first enclosed volume of the spectrometer comprises an interferometer with a source of electromagnetic radiation, a first focusing mirror adapted to focus electromagnetic radiation received from the interferometer to the absorption cell, a second focusing mirror adapted to focus electromagnetic radiation received from the absorption cell and a detector adapted to detect electromagnetic radiation focused by the second focusing mirror. Moreover, the spectrometer comprises a main frame plate on which elements in the first enclosed volume are mounted and which is fixed to the absorption cell arranged on an opposing side of the main frame plate.

The following description of background art may include insights, discoveries, understandings or disclosures, or associations together with disclosures not known to the relevant art prior to the present invention but provided by the invention. Some such contributions of the invention may be specifically pointed out below, whereas other such contributions of the invention will be apparent from their context.
Infrared spectroscopy is a sub-discipline of spectroscopy based on employing electromagnetic waves in the infrared frequency range which corresponds to wavelengths larger than wavelengths of visible light. According to one definition, the infrared radiation has a wavelength range of 700 nm-1 mm (or frequency range of 300 GHz-430 THz). Infrared spectroscopy is based on the fact that different molecules interact differently with infrared radiation of a particular frequency. Specifically, each molecule has a set number (infrared) resonant frequencies at which a particular resonant vibration mode of the molecule is excited and consequently a maximum in the absorption of infrared radiation occurs. By taking advantage of knowledge of characteristic behavior of different molecules, infrared spectroscopy may be used for identifying and analyzing solid, liquids and/or gasses by studying the changes that occur in the infrared signal as it radiates in the sample solid, liquid or gas.
Fourier transform infrared spectroscopy is one commonly used measurement technique in infrared spectroscopy. In Fourier transform infrared spectroscopy, infrared radiation (or infrared light) is guided through an interferometer and subsequently through a sample (e.g., a gas sample) or vice versa. A moving mirror inside the interferometer is used to alter the frequency distribution of infrared light that passes through the interferometer. By moving said mirror and capturing the signal propagating through the sample, an interferogram of the sample describing absorption in the sample as a function of mirror position is captured. The spectrum of the sample under analysis (that is, absorption in the sample as a function of frequency) may be subsequently calculated based on the interferogram (and a reference interferogram for the spectrometer) and based thereon the sample may be identified.
As Fourier transform infrared spectroscopy is based on inducing phase shifts between two infrared signals having wavelengths below one millimeter in a controlled manner, it is obvious that even relatively minor misalignments or shifts in infrared optical elements in the interferometer may cause significant deterioration in the performance. Such minor misalignments or shifts may be caused, for example, by temperature variations and vibrations in the spectrometer. While good performance may be easily achieved in controlled laboratory conditions, it is not always convenient and efficient to bring the samples to such a controlled environment. Instead, the analysis of the sample may need to be carried out in less than ideal field conditions such as in a factory or a power plant. On the other hand, the sample gasses may be measured at a high temperature which may result in considerable thermal expansion of the body of the spectrometer causing further inaccuracies in the measurement results. Therefore, there is a need for robust Fourier transform infrared spectrometer solutions which enable sample analysis under varying conditions.


The present invention relates to a method for dewatering water-containing particle collections with the aid of gas under pressure, in which at least one of a possible multiple of stages is effected with the aid of gas to which a pressure difference is imparted through and across the particle collection. A smallest predetermined pressure difference is created and the time for establishing the pressure difference does not exceed appreciably the time taken for gas penetration of the therewith dewatered particle collection to occur.

1. Field of the Invention
The present invention relates to a method for dewatering water-containing particle collections in which at least one of a possible multiple of dewatering stages is effected with the aid of gas to which a pressure difference is imparted through and across the particle collection.
2. DESCRIPTION OF THE PRIOR ART
Water-containing particle collections, such as mineral suspensions and fibre suspensions, are often dewatered by first mechanically pumping the particle collection onto a filtering medium and/or by pressing said collection against said medium under high pressure, such as to form a filter cake from which water is then removed under the influence of gas under pressure. Dewatering can either be accomplished by employing a vacuum and/or by using a pressurized gas, said gas normally being compressed air. Thus, in both instances, and also in different combinations thereof, the filter cake is subjected to a pressure difference which consists, in principle, of the sum of the low pressure on the suction side and the high pressure on the pressure side. The dewatering process is effected through the influence of this pressure difference in three successive phases, mainly a first penetration phase, which is commenced by subjecting fully saturated filter cake to pressurized gas on one side thereof, and is terminated when the gas breaks through the filter cake (penetration) and thus exits from the other side of said cake. During this phase, water present in the cake is simply displaced forwardly by the advancing gas front. During the second phase, the drainage phase, the gas flows through the filter cake while maintaining a pressure difference within the cake, the water in this case being forced to move in the same direction as the gas. This phase will terminate when the water capillary forces are in equilibrium with the gas pressure prevailing locally within the filter cake, with a subsequent decrease in water flow. When this state is reached, further water can only be removed by vaporizing water into the passing gas flow. This last dewatering phase, the drying phase, is thus dependent on gas mass flow, temperature and pressure.
The aforedescribed dewatering mechanism is employed in several processes that are applied industrially for the purpose of dewatering particle collections in three phases or stages. Thus, a common feature of these processes is that dewatering is effected in at least one of the process stages with the aid of a gas to which there is imparted a pressure difference through and across the particle collection.
For instance, "Solid/Liquid Separation Technology", published by Uplands Press Ltd, 1981, describes on page 331 one such method in which gas is blown into the particle collection at a pressure of 6 bars, whereas the final stage is effected by mechanical pressing-dewatering of the particle collection.
According to another known method, described in Swedish patent application SE-8603070-7 (Sala International), the final lowering of the moisture content of the particle collection is achieved by compressed-air blowing. The above-cited publications and patent applications are incorporated herein by reference as if the texts thereof were fully set forth herein.
A common feature of all methods known hitherto, however, is that further lowering of the moisture content can only be achieved by extending the blowing time or the cake-heating time. Both cases thus require a high energy input. Furthermore, an extended blow time will lower the capacity of the filter medium used.
Because of higher energy costs and the ever greater industrial demands for more economical particle suspension dewatering processes, there is a need for further development of such dewatering processes which will render such processes less prohibitive, from the aspect of energy consumption, in the handling of these materials. In present times, energy costs are considered a very important factor in the total dewatering costs. Consequently, there is found an ever increasing desire for particle-collection dewatering processes which fulfill the requirements of lower energy consumption and/or higher productivity.

Method for dewatering water-containing particle collections with the aid of gas under pressure


Built-in electrical test structures are measured for lead-to-lead shorting during the fabrication of MR elements on a wafer. The test structures are fabricated in the same fashion as the MR elements, however, the active sensor region or track width is omitted from the test structures. Thus, the left and right leads for each test structure are electrically isolated from each other in their “track width” region. If there is lead-to-lead shorting on a test structure, then the left and right leads are electrically connected in the track width region. A simple resistance measurement between the left and right leads determines the extent of any lead shorting by giving a quantitative resistance value.

1. Technical Field
The present invention relates in general to evaluating magnetoresistive elements and, in particular, to an improved system, method, and apparatus for electrically testing and monitoring lead-to-lead shorting during magnetoresistive sensor fabrication on a wafer.
2. Description of the Related Art
Data access and storage systems generally comprise one or more storage devices that store data on magnetic or optical storage media. For example, a magnetic storage device is known as a direct access storage device (DASD) or a hard disk drive (HDD) and includes one or more disks and a disk controller to manage local operations concerning the disks. The hard disks themselves are usually made of aluminum alloy or a mixture of glass and ceramic, and are covered with a magnetic coating. Typically, one to five disks are stacked vertically on a common spindle that is turned by a disk drive motor at several thousand revolutions per minute (rpm). Hard disk drives have several different typical standard sizes or formats, including server, desktop, mobile (2.5 and 1.8 inches) and microdrive.
A typical HDD also uses an actuator assembly to move magnetoresistive (MR) read/write heads to the desired location on the rotating disk so as to write information to or read data from that location. Within most HDDs, the magnetic read/write head is mounted on a slider. A slider generally serves to mechanically support the head and any electrical connections between the head and the rest of the disk drive system. The slider is aerodynamically shaped to glide over moving air in order to maintain a uniform distance from the surface of the rotating disk, thereby preventing the head from undesirably contacting the disk.
A slider is typically formed with an aerodynamic pattern of protrusions on its air bearing surface (ABS) that enables the slider to fly at a constant height close to the disk during operation of the disk drive. A slider is associated with each side of each disk and flies just over the disk's surface. Each slider is mounted on a suspension to form a head gimbal assembly (HGA). The HGA is then attached to a semi-rigid actuator arm that supports the entire head flying unit. Several semi-rigid arms may be combined to form a single movable unit having either a linear bearing or a rotary pivotal bearing system.
The head and arm assembly is linearly or pivotally moved utilizing a magnet/coil structure that is often called a voice coil motor (VCM). The stator of a VCM is mounted to a base plate or casting on which the spindle is also mounted. The base casting with its spindle, actuator VCM, and internal filtration system is then enclosed with a cover and seal assembly to ensure that no contaminants can enter and adversely affect the reliability of the slider flying over the disk. When current is fed to the motor, the VCM develops force or torque that is substantially proportional to the applied current. The arm acceleration is therefore substantially proportional to the magnitude of the current. As the read/write head approaches a desired track on a disk, a reverse polarity signal is applied to the actuator, causing the signal to act as a brake, and ideally causing the read/write head to stop and settle directly over the desired track.
As HDDs have improved in performance, the widths of the tracks on the MR elements or heads have decreased. This decrease in MR head track width has the inverse effect of increasing the processing complexity of the MR heads. One specific difficulty associated with narrow track widths is an increased likelihood in the formation of an electrical short between the leads of MR heads when they are formed on the wafers. An "electrical bridge" between the leads can degrade head performance by shunting current from the sensor. Therefore, early detection of lead-to-lead shorting provides critical process feedback in terms of yield and cost control.
The conventional technique used to detect MR head lead-to-lead shorting utilizes a top-down scanning electron microscope (SEM) image or photograph of each MR head on a wafer. The drawbacks for using these images to detect lead-to-lead shorting are twofold. First, only the images (i.e., not the heads themselves) are manually inspected to determine if lead-to-lead shorting is present. This inherently provides a merely subjective detection scheme, which can be misinterpreted by the operator. Second, the images cannot tell the operator if a lead-to-lead short is a high resistance short (and, therefore, "unimportant"), or an "important" low resistance short. Thus, it would be desirable to improve the electrical monitoring of lead-to-lead shorting during the wafer fabrication of magnetoresistive sensors.

System, method, and apparatus for electrically testing lead-to-lead shorting during magnetoresistive sensor fabrication

Hitachi Global Storage Technologies Netherlands BV


A camera system according to an embodiment includes a camera device, a control device, and an application server. The camera device, which includes a camera module and a power line communication (PLC) camera adaptation module, captures and provides audio/video information. The camera device modulates the audio/video information, and provides the modulated information. The camera device also demodulates the modulated signal transferred from a power line to obtain a control signal, and adjusts camera parameters according to the control signal. The control device is connected to the PLC camera adaptation module via the power line. The control device demodulates a received modulated signal of the audio/video information, and provides the demodulated signal. According to a received control indication information, the control device generates a control signal, modulates the control signal, and controls the camera module. The application server stores and provides the audio/video information, camera device information and controlling purview information of the camera device. The application server also generates and provides the control indication information. A method for controlling camera is also disclosed. Embodiments of the present invention can control the camera device remotely without using a dedicated signal line.

With the increasing popularity of digital products, camera devices have become the primary choice for recording and storing information by households and corporations. A user can conveniently record video, audio, or composite audio/video information using these camera devices. Existing camera system usually comprises of a camera device which is located at the site of the camera, and a control device which controls the camera device. The camera device and the control device are usually connected by means of a power line and a dedicated signal line (such as a video cable), or by means of a special signal line (such as a USB cable) that also can provide power to the devices. The user can use the control device to control various camera parameters of the camera device, such as the camera angle, the focal length, the light sensitivity, and the produced media type etc., so as to meet different users' needs.
Existing camera systems and their control methods have the following shortcomings:
1. A dedicated signal line must be used to connect the camera device and the control device, however, when there is a relatively long distance between the camera device and the control device, for example when the two devices are not located in the same room, it is difficult to deploy a dedicated signal line between the devices, thus causing inconvenience to the user.
2. Because a dedicated signal line must be used to connect the camera device and the control device, the distance between these two devices is limited. If camera parameters such as the camera angle, the focal length, the light sensitivity or the produced media type need to be changed, the user must operate the control device at the site of the camera. Hence the camera device can not be remotely operated or controlled, causing inconvenience to the user.


Aspects of the present disclosure provide for composite structures including a bonding layer that adheres a substrate (e.g., including a polymeric composition such as rubber) to a material (e.g., including a polymer such as polyurethane). The adhesion of the substrate to the material through the bonding layer can include chemical bonds such as, but not limited to, siloxane linkages, silanol linkages, silyl linkages, or any combination thereof in the bonding layer.

Processes that are used to form textiles such as footwear typically involve the use of various chemicals and processes to adhere different parts of the footwear. Generally these processes use traditional stock fitting that is a labor intensive multi-step processes that include the use of primers, adhesives, and curing to adhere different parts of the textile.

Composite structures including a bonding layer and methods of making the composite structure


A disc brake for a utility vehicle is provided. The disc brake includes a brake caliper overlapping a brake disc, the brake caliper being held on a brake carrier located on the vehicle in an axially displaceable manner with respect to the brake disc. The brake carrier has brake lining slots on opposite sides of the brake disc defined by brake carrier lugs on the entry and the exit side. Each slot receives a brake lining having a brake plate and a friction lining fastened thereto, configured such that each brake lining is supported at least at the entry side in the direction of rotation of the brake disc on the entry side brake carrier lug during braking.

The invention relates to a disc brake for a commercial vehicle.
Such disc brakes, also referred to as sliding caliper disc brakes, are well known. The brake pads here, each comprising a pad-carrier plate and a friction lining retained thereon, are pushed in the direction of the brake-disc axis into the pad slots of the brake carrier, which is retained at a fixed location on the vehicle.
During braking, when the brake pads are pressed against the brake disc, the friction fit between the friction lining of the respective brake pad and the brake disc gives rise to the brake pad being subjected, in the direction of rotation of the brake disc, to a torque which is absorbed by the exit-side brake carrier lug.
However, over the course of operation of the brake pads, this results in so-called tangential diagonal wear to the brake pads such that, as seen in the main braking direction, i.e. when the commercial vehicle is travelling forwards, said brake pads wear to a more pronounced extent on the entry side than on the exit side.
It is therefore necessary for the brake pads, as soon as they reached their wear limit in the regions which are worn to a relatively pronounced extent, to be changed over, there still being usable wear volume available in the remaining regions of the brake pad or of the friction linings.
Of course, this stands in the way of operational-cost optimization, which is a constant aim, in particular also because commercial vehicles are usually equipped with a multiplicity of disc brakes, each having the aforementioned problems.
Although the prior art discloses disc brakes of which the brake pads have form-fitting elements which engage in a corresponding manner in the respective brake carrier, the form fits produced thereby are not suitable for preventing the problem of diagonal wear. In particular, the brake pads are not retained in a form-fitting manner in both directions of rotation of the brake disc.
DE 21 38 776 A discloses a disc brake in which the brake pads are mounted in guide grooves of the brake carrier by way of laterally formed protrusions, wherein, during braking, the entry-side protrusion is supported radially on the upper wall of the guide grooves without the brake carrier being capable of effectively absorbing a torque in this region. A comparable design is dealt with in DE 22 55 678 A.
It is an object of the invention to develop a disc brake of the type in question such that the service life of the brake pads and the operational costs are lowered.
The configuration of the disc brake according to the invention, in particular of the corresponding parts of the brake carrier, on the one hand, and of the brake pads, on the other hand, means that the torque which acts on the respective brake pad during braking acts on the entry-side region of the brake carrier, in particular on the entry-side brake carrier lug, and therefore the brake pad acts more or less as a tie.
As a result of the at least one form fit with the brake carrier, which according to the invention is provided on the entry side, the brake pad is more or less braced with the brake carrier in both directions of rotation of the brake disc. That is to say the torque acting on the brake pad is absorbed in the first instance exclusively by the entry-side region of the brake carrier, in particular, in this case, the brake carrier lug.
In the case of relatively large braking moments, which apply torque to the brake pads, it is possible for the entry-side brake carrier lug to flex to the extent where the brake pad, on the exit side abuts the associated brake carrier lug. It is always ensured, in the case of such torque absorption, that there is no diagonal wear to the brake pad.
The form fit between the brake pad and the brake carrier can be produced in different ways.
According to one idea of the invention, provision is made for the respective pad-carrier plate, on the side which is directed towards the floor of the brake carrier, to have a protrusion, which, as seen in the direction of rotation of the brake disc, butts against at least one supporting surface of the brake carrier, said supporting surface being formed by a protuberance arranged on the floor of the pad slot. It is also conceivable for the associated brake carrier lug to be used as a further supporting surface, and therefore the protrusion is positioned between the two supporting surfaces and butts against the same.
The two mutually opposite supporting surfaces, accommodating the associated protrusion of the brake pad between them, are arranged parallel to one another, are of smooth-surface design and run tangentially to the brake disc, and therefore the brake pad can be pushed in radially, as in relation to the brake disc.
According to the invention, it is indeed the case that the brake pad is supported on the brake carrier in both directions of rotation of the brake disc at least on the entry side, but it is preferred for the support to be provided both on the entry side and on the exit side, and therefore the brake pad may be of mirror-symmetrical design, as seen in relation to a radial centre axis. Depending on the direction of rotation of the brake disc, i.e. depending on whether travel is in the forward direction or in reverse, the entry side and exit side change round. That is to say the entry side for forward travel becomes the exit side for reverse travel, and vice versa.
Another variant of the invention makes provision for the support to be provided by a form fit between the brake pad and the brake carrier, for which purpose a claw-like formation is provided in that peripheral region of the pad-carrier plate which is directed towards the brake carrier lug, and said claw-like formation has an accommodating groove, into which is fitted a dimensionally adapted retaining pin of the brake carrier lug. This therefore also achieves the situation where the brake pad is arrested on the brake carrier lug in both directions of rotation of the brake disc.
Instead of a claw-like formation of the brake pad and a retaining pin of the brake carrier lug, it is also, of course, possible for the brake carrier lug to be of claw-like design and for the brake pad to be provided with a retaining pin, which engages in the groove formed in the brake carrier lug.
Otherwise, the form-fitting elements or formations of the brake pad are arranged on the brake carrier plate.
By virtue of the brake pad being more or less clamped in the direction of rotation of the brake disc both on the entry side and the on the exit side, it is possible for the corresponding brake pad to perform the function of a strut if one of the two pad slots is formed without a strut connecting the brake carrier lugs to one another.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of one or more preferred embodiments when considered in conjunction with the accompanying drawings.

KNORR-BREMSE Systeme fuer Nutzfahrzeuge GmbH


Semiconductor devices and methods of forming the same include forming a bottom source/drain structure around a fin. A multi-layer bottom spacer is formed on the bottom source/drain structure, around the fin. Each layer of the multi-layer bottom spacer has a respective vertical height above the bottom source/drain structure, with a layer of the multi-layer bottom spacer that is farthest from the fin having a greater vertical height than a layer that is closest to the fin, to address parasitic capacitance from the bottom source/drain structure.

The present invention generally relates to semiconductor device fabrication, and, more particularly, to the fabrication of vertical transfer field effect transistors (VTFETs) that include three-layer uniform bottom spacers that are self-aligned to a shallow trench isolation structure.
Bottom spacers in VTFETs insulate the gate conductor from the bottom source/drain structures. However, existing processes for VTFET fabrication provide bottom spacers that suffer from defects and large feature-to-feature variations. This decreases device yield and diminishes the performance of the finished device.

Self-aligned uniform bottom spacers for VTFETS

INTERNATIONAL BUSINESS MACHINES CORPORATION


A high speed voltage translator is responsive to an ECL input signal for providing a TTL output signal at an output while clamping the low output voltage thereof to a predetermined value. The ECL input signal is converted to first and second complementary control signals for driving the upper and lower transistors in the output stage, respectively. The second control signal enables a third transistor, the base of which is connected via a serial diode and resistor combination to a second collector of the lower transistor in the output stage. The base-emitter junction potential of the third transistor cancels the potential across the diode whereby the collector of the lower transistor that is the output of the voltage translator is clamped at one base-emitter junction potential less the voltage across the resistor. Furthermore, the current flowing through the resistor is compensated for temperature variation whereby the low output voltage is independent of temperature. The first and second control signals enable separate charge and discharge paths for the upper and lower transistors whereby the associated propagation delays may be controlled so as to inhibit simultaneous conduction through the output stage.

This invention relates in general to voltage translators, and more particularly, to an ECL to TTL voltage translator having a clamping circuit for limiting the low level TTL output signal to a predetermined value.
It is well known that many of today's complex electronic systems mix and match integrated circuits of different logic families to accomplish a series of interrelated functions. In one example, signals produced in the ECL (emitter coupled logic) family are converted to levels compatible with the TTL (transistor-transistor logic) family by a voltage translator circuit for further processing. The output stage of the conventional ECL to TTL voltage translator typically includes upper and lower bipolar transistors alternately conducting and serially coupled between a power supply conductor operating at a positive potential such as V.sub.CC and a ground potential terminal. The output is provided at the interconnection of the transistor pair. The upper transistor in the output stage pulls the output terminal toward V.sub.CC for providing a high TTL output signal, while the lower transistor draws the output terminal toward ground potential for providing a low TTL compatible output signal. It is important to clamp the low output voltage (V.sub.OL) within a predetermined narrow window of operation, otherwise if the V.sub.OL signal became too high it would exceed the generally accepted industry standard for a low TTL output signal (< 500 millivolts), or if the output voltage became too low, the collector-base junction of the lower transistor could become strongly forward biased, saturating the transistor and developing excessive charge in the base region thereby slowing its switching rate to an unacceptable value.
In conventional practice, a Schottky diode is coupled between the collector and base of the lower transistor in the TTL output stage for clamping the V.sub.OL output signal to approximately 300-500 millivolts. While the Schottky diode behaves satisfactorily as a clamping means, the manufacturing processes to implement the Schottky diode especially in more recent semiconductor technologies, requires several complex and expensive steps including an extra masking step to form the Schottky diode and its contacts. Although it is necessary to clamp the V.sub.OL output signal for the reasons advanced above, it is also desirable to provide such a feature without the expense and complexity imposed by the traditional Schottky diode.
Another significant problem with the conventional TTL output stage relates to the phasing of the control signals applied at the bases of the upper and lower transistors and the associated charge and discharge rates thereof, wherein it is possible for both transistors to conduct simultaneously at the transition of the output logic state creating a short circuit current therethrough which induces spikes in the power supply lines thus creating excessive system noise and peak power. In the prior art, a phase splitter transistor is typically used for alternately enabling the upper and lower transistors in the output stage. This single point of control is susceptible to race conditions taking into account the charge and discharge rates whereby the upper and lower transistors may jointly conduct between the power supply conductors for a short period of time at the transitions of the output logic state. Preferably, the control circuitry for the output stage should insure that the active transistor is completely off before the opposite one is turned on, thus avoiding the short circuit current.
Furthermore, the low level output signal of the conventional voltage translator is often sensitive to temperature variation. The V.sub.OL output signal is typically determined by the base-emitter junction potential of the lower transistor less the voltage across the Schottky clamp. The P-N junctions of the lower transistor and the Schottky diode are exponential functions of temperature as seen in the well known diode equation, V.sub.d =(kT/q) ln (I.sub.d /I.sub.s), where "V.sub.d " is the potential across the diode, "I.sub.d " is the current through the diode, "I.sub.s " is the diode saturation current, "k" is Boltzman's constant, "T" is absolute temperature and "q" is the electron charge. Hence, the V.sub.OL output signal is known to fluctuate with temperature by as much as 200-300 millivolts from 0.degree. C. to 125.degree. C. which is unacceptable in some applications and undesirable in most others.
Hence, there is a need for an improved ECL to TTL translator which limits the low output voltage to a predetermined value independent of temperature and without the use of a Schottky diode clamp, while insuring that the upper and lower transistors in the output stage do not conduct simultaneously.

High speed ECL to TTL translator having a non-Schottky clamp for the output stage transistor


An oscillator includes a reference voltage generator, an oscillation element configured to oscillate by either a drive voltage or a drive current and output an oscillation signal, a peak hold element configured to detect a peak level of the oscillation signal for output; and a controller configured to increase or decrease the drive voltage or drive current in accordance with the reference voltage generated by the reference voltage generator and the peak level output from the peak hold element.

1. Field of the Invention
The present invention relates to an oscillator with an oscillation circuit such as a crystal oscillation element which can reduce the power consumption of the oscillation circuit and reduce the occurrence of noise to prevent deterioration in oscillation property. It also relates to a clock generator, a semiconductor device and an electronic device incorporating such an oscillator. The electronic device is, for example, a wrist watch, a mobile phone, a personal digital assistance (PDA), or a computer terminal.
2. Description of the Prior Art
Such an electronic device often includes a crystal oscillator. For example, Japanese Patent Application Publication No. 2006-121477 (Reference 1) discloses, as shown in FIG. 8A, a crystal oscillator which includes an inverter circuit 84 which receives the output amplitude of a crystal oscillation circuit 81 to change in output pulse width in accordance with a change in the output amplitude. Thereby, it can detect the amplitude of an oscillation signal of the oscillation circuit 81 by monitoring the pulse width or duty ratio of a pulse signal from the inverter circuit 84, and control the drive voltage VOSC of the oscillation circuit 81 on the basis of a detected result so that the output amplitude thereof is almost turned to a saturation level. It aims to automatically secure, with a simple configuration, an optimal oscillation allowance in line with a difference in products, ambient environment or the level of oscillation at power-on while reducing power consumption during stationary oscillation.
Specifically, the oscillator includes an amplitude detector 82 having the inverter circuit 84, a level converter circuit 85, and a lowpass filter 86, a transformer circuit 83 having a differential amplifier 87 and a PMOS transistor 88, and a stabilizing capacitance 89. The level converter circuit 85 converts the pulse amplitude of the inverter circuit 84 and the low pass filter 86 acquires an integrated value thereof. The integrated value and a reference voltage VREF slightly lower than the output level in amplitude saturation are input to the differential amplifier 87. If the output (integrated value) of the inverter circuit 84 is lower than the reference voltage VREF, the voltage of the gate of the PMOS transistor 88 is decreased to increase the drive voltage VOSC and output amplitude of the crystal oscillation circuit 81. If it is higher than the reference voltage VREF, the voltage of the gate of the PMOS transistor 88 is increased to decrease the drive voltage VOSC and output amplitude of the crystal oscillation circuit 81.
As shown in FIG. 8B, the crystal oscillation circuit 81 in general includes an inverter CI having an enhancement P-channel MOS transistor Qp and an enhancement N-channel MOS transistor Qn, a crystal oscillation element X, load capacitances CG, CD, and a feedback resistance RF. The oscillation circuit 8 outputs an oscillation signal SO.
According to the oscillator disclosed in Reference 1 the oscillation signal SO is output from the crystal oscillation circuit 81 to the inverter circuit 84 of the amplitude detector 82.
The inverter circuit 84 includes a PMOS transistor and an NMOS transistor connected in series between the power supply voltage VOSC and a GND voltage. The oscillation signal is input to the common gate of the two transistors and output from a connecting point of the two transistors.
In this configuration, as long as the input signal has either the power supply voltage VOSC or GND voltage, current does not flow into the inverter circuit 84. However, when it has an intermediate potential simultaneously turning on both the transistors, feedthrough current flows into the inverter circuit 84.
The oscillation signal SO of the oscillation circuit 81 is generally a sine wave and mostly in an intermediate potential between the power supply voltage VOSC and GND voltage. Receiving such a sine wave at the inverter circuit 84 as a logic circuit, feedthrough current flows into the inverter circuit 84 intermittently or inconstantly in a sine wave cycle, which may lead to extraneous power consumption.
Furthermore, the intermittent or inconstant power consumption may cause periodic noise in the power supply voltage VOSC of the oscillation circuit 81, which is likely to adversely affect the oscillation property of the oscillator, especially a deterioration in the jitter characteristics of the oscillation signal.
Further, the inverter circuit 84 outputs a pulse signal with a rectangular sine wave between the voltage VOSC of the oscillation circuit and GND voltage. The pulse signal falls and rises fast and contains high frequency components, and due to its high amplitude, it is likely to cause parasitic capacitive coupling or electromagnetic coupling in the wires of the oscillator, resulting in noise in the voltage VOSC.
Reference 1 does not describe the level converter 85 in detail but it has to convert the output signal from the inverter circuit 84 into a level signal via a logic gate element or a switch element.
Thus, to mount such a logic circuit outputting a rectangular wave pulse signal and analog circuits as the oscillation circuit 81 and transformer circuit 83 on the same semiconductor circuit board, the layout of the elements need be carefully designed to prevent noise with advanced technical know-how. Because of this, there is a problem that development period and product performance are often in a tradeoff relation.
FIG. 9 schematically shows the structure of an oscillator disclosed in Japanese Patent No. 3136600 (Reference 2).
The oscillator in FIG. 9 includes an oscillation circuit 91, a level detector 92 to detect the amplitude level of an oscillation signal SO output from the oscillation circuit 91 and output a rectangular wave pulse signal SP to a switched capacitor 90, a reference voltage generator (frequency-voltage converter) 93, and an amplifier 94 to amplify a reference voltage VREF to supply it to the oscillation circuit 91 as a power supply voltage ED.
In this oscillator, upon receiving the oscillation signal from the oscillation circuit 91, the level detector 92 generates a pulse signal SP to operate an inverter circuit 99, a discharge switch 95 and a bypass switch 96 constituting the switched capacitor 90.
As the one in Reference 1, the oscillator disclosed in Reference 2 uses the logic gate circuits and switches generating rectangular sine wave signals so that it faces the same problem with increasing consumption current due to the feedthrough current and deteriorating the oscillation property due to noise.
Further, Japanese Patent Application Publication No. 2-94803 (Reference 3) discloses an oscillation circuit by use of a peak voltage. It includes an oscillation element, an amplifier supplied with the output of the oscillation element, a peak detector to detect the output peak level of the amplifier, a capacitor charged with the output of the peak detector and discharged with a constant current source, a smoothening circuit to smooth a voltage varying with the charge/discharge of the capacitor, and a comparator to compare the output of the smoothing circuit with a reference level. The gain of the amplifier is controlled in accordance with a result of the comparison by the comparator.
The oscillation circuit in Reference 3 aims to improve distortion in oscillation output waveform and the stability of a solid oscillation element not to shift into a high-order oscillation mode. However, it cannot lower the power supply voltage by just controlling the gain of the oscillation circuit and the oscillation circuit in FIG. 4 thereof is not configured to control the power supply voltage Vcc. Therefore, Reference 3 fails to consider the optimal control over the power supply voltage Vcc and current consumption so that they are to be minimal.
No oscillation technique for solving all the problems above as extraneous power consumption due to transient feedthrough current, deterioration in oscillation property due to noise, especially, jitter characteristics has been proposed. Further, any of References 1 to 3 fail to address the reduction in extraneous power consumption owing to the feedthrough current as described above.

Oscillator, and clock generator, semiconductor device, and electronic device including the same


The optimal configuration of a number of optional pipeline stages within the data paths of systems-on-chip is determined by application of a solver. The solver includes variables such as: the placement of modules physically within the floorplan of the chip; the signal propagation time; the logic gate switching time; the arrival time, after a clock edge, of a signal at each module port; the arrival time at each pipeline stage; and the Boolean value of the state of activation of each optional pipeline stage. The optimal configuration ensures that a timing constraint is met, if possible, with the lowest possible cost of pipeline stages.

By dividing a process into steps, and performing the steps simultaneously on different data, the frequency at which the processing system can operate depends on the length of time to complete its slowest step. The same process performed with a shorter "slowest step" can be performed faster. Designing shorter steps in order to achieve higher speed generally requires creating more steps. More steps, given imperfect balancing of the length of steps, require more time to generate the resulting output from any particular input.
Processes are often referred to as pipelines. Storage devices between steps are referred to as pipeline stages. The number of steps in a processing system is referred to as the pipeline depth. Within a system-on-chip (SoC) data moves through a pipeline no faster than one stage per clock cycle. Therefore, the number of stages determines the number of clock cycles for each input datum to be fully processed. Such time is often referred to as latency. Longer latency due to pipeline stages is undesirable, but the faster clock frequency due to pipeline stages is desirable. Designing an optimal number of pipeline stages requires a trade-off between clock frequency and cycles of latency.
Within the design of a data processing chip it is not immediately clear how to optimally apply pipelining. The conventional method of designing a pipeline that works is an iterative process of experimentation. It is time consuming. Furthermore, it rarely results in an optimal design.
The problem is further complicated when the physical layout of the chip is considered. The length of time for data to propagate from a point of production to a point of consumption depends on the distance and the average propagation rate through the wires between those points. Conventionally, the physical layout is considered at a later stage in the chip design process than the decisions about pipelining. To avoid unexpected problems achieving the desired clock frequency during physical design, pipeline stages are placed at smaller increments within the processing logic, thereby leaving extra time for data to propagate between points if they happen to be distant in the physical design. This over-design of pipeline stages costs area, power consumption, and especially latency. Therefore, what is needed is a system and method to automatically determine optional pipeline stages in order to meet clock frequency constraints.


An embodiment of a voltage conversion unit comprising a switching DC-DC converter including an input terminal for receiving an input voltage from a source, a control terminal adapted to receive a pulse width modulated driving signal oscillating at a first frequency, and an output terminal for providing to a load an output voltage generated from the input voltage according to the driving signal. The switching DC-DC converter and the switching control unit form a feedback loop having a loop gain defining a corresponding operating bandwidth. The load is configured to d rain a current pulse train having a second frequency; the values of the first and second frequencies are such to cause the occurrence of beat oscillations at frequencies comprised within the operating bandwidth. The switching control unit comprises means for reducing the beat oscillations by increasing the loop gain at least for a frequency interval comprised within the operating bandwidth.

In electronics, a DC-DC converter is an electronic circuit adapted to convert a direct current source from one voltage value to another voltage value.
One of the most relevant among the known types of DC-DC converters is represented by the switching DC-DC converters. Considering in particular a DC-DC converter of the "step-down" type, wherein the input voltage is converted into an output voltage having a lower value, an example of the operation thereof will be now described. During a first phase—denoted as "main phase"—the switching DC-DC converter electrically couples a source of the input voltage (to be converted) to a terminal of a reactive element, typically an inductor. As a consequence, in this phase the reactive element stores magnetic energy, absorbing an input current from the input voltage source. In this phase, the output load requiring the (converted) output voltage receives energy from the input voltage source. In a second phase—denoted "secondary phase"—the reactive element is disconnected from the input voltage source, and the output load receives the magnetic energy that has been stored in the reactive element during the main phase. Acting on the ratio between the main phase and secondary phase durations—denoted "duty cycle"—it is possible to regulate the transfer of energy from the voltage source to the output load in a controlled way, and thus bring the voltage provided to the output load to the requested value.
An important application field of the step down DC—DC converters regards the supplying of Central Processor Units (CPU) and Graphic Processor Units (GPU).
Modern processors are typically supplied with a switching DC-DC converter having a buck topology. Depending on the power consumption requirements, synchronous multiphase topologies may be employed. A multiphase topology is realized arranging N-single synchronous phase buck converters in parallel and controlling them with a same system control loop. The number of phase depends on the maximum current that the processor may drain, such as, two phases for maximum currents up to 40 A and eight phases for maximum currents up to 180 A.
Modern processors often require supply voltages having very stable values. For example, the maximum allowed deviation—caused by static accuracy, output voltage ripple, and drop due to heavy dynamic current transitions—may be equal to +/−5% (that is, for a supply voltage of 1 Volt, only +/−50 mV pp). The CPUs and GPUs of the latest generations have greatly increased their computational power; the current consumption (i.e., the amount of current drained in operation) of modern processors has changed from a "static" fashion to a "dynamic" fashion. More specifically, the current drained by modern processors may vary by a great extent based on the status of operation thereof with a high frequency (e.g., every microsecond). From an electrical point of view, modern processors may be modeled as current-pulse generators draining a current pulse train having a frequency repetition (Fl) up to 1 MHz with a high slew rate (e.g., up to 1000 A/μs).
The switching frequency (Fsw) of a standard switching DC-DC converter having the buck topology adapted to be exploited for supplying a processor is typically set (basically to increase the system efficiency) to a value ranging from approximately one to few hundreds of kHz.
The interference between the frequency repetition Fl of the current pulses drained by the load (the processor) and the switching frequency Fsw of the DC-DC converter may cause the generation of spurious beat oscillations (or frequency beats) at the (beat) frequencies of Fl−Fsw and Fl+Fsw (and multiples thereof). This phenomenon may negatively affect the correct operation of the converter, by, for example, introducing, in particular, low-frequency (Fl−Fsw) spurious oscillations in the current flowing through the reactive element (inductor) and in the output voltage generated by the converter. If sufficiently large, such spurious oscillations may cause the power components of the converters (such as the inductor and the switching elements) to be subjected to excessive electrical and thermal stresses and/or the value of the output voltage to exceed the maximum allowed deviation from the ideal value.
An example of such spurious beat oscillations is illustrated in the timing diagrams of FIG. 1, showing the simulated time course of the current flowing in the inductor (top) and of the output voltage (bottom) of an exemplary switching DC-DC buck converter operating at a switching frequency Fsw of 300 KHz for supplying a load draining a current pulse train having a frequency repetition Fl of 310 KHz (i.e., with a beat frequency of Fl−Fsw=10 kHZ).
In order to solve these and possibly other drawbacks, a first solution known in the art provides for using switching control units (i.e., the circuit that control the opening/closing of the switching elements of the converter) that exploit proper (typically, non-linear) techniques capable of eliminating the beat oscillations. However, switching control units of this type may be very complex and thus their cost may not be negligible.
A further known solution provides instead for using standard switching control units, but, at the same time, greatly reducing the bandwidth of the system for filtering out the beat oscillations. This solution may be very expensive, too. Indeed, a great bandwidth reduction slows the response time of the system; in order to restore the response time to comply with the output requirements, the output capacity needs to be increased, increasing thus the manufacturing cost.


A combination EMI shielding and environmental sealing gasket construction and method for its manufacture. The gasket includes at least one electrically-conductive EMI shielding gasket member, and at least one environmental sealing gasket member. The shielding gasket member, which may be in the form of a strip, has a lengthwise extent and an outer periphery having interstitial spaces, such as between the fibers of a metal wire or other fiber mesh or fabric, through a widthwise extent thereof. The sealing gasket member extends along the lengthwise extent of the shielding gasket member and is formed, such as by being dispensed to foam or otherwise formed-in-place along an adjacent side of the strip, of an elastomeric foam or other material which penetrates into at least a portion of the interstitial spaces of the shielding gasket member to bond the shielding gasket member and the sealing gasket member into an integral structure.

The present invention relates broadly to gaskets for providing electromagnetic interference (EMI) shielding and weather, dust, or other environmental sealing, and particularly to a combination or composite gasket construction and method of its manufacture combining a metal mesh strip gasket with an integral solid or foam elastomeric weather-sealing strip which is especially adapted for use within cabinets and other enclosures for electrical or electronic systems or devices.
The operation of electronic devices such as televisions, radios, computers, medical instruments, business machines, communications equipment, and the like is attended by the generation of electromagnetic radiation within the electronic circuitry of the equipment. As is detailed in U.S. Pat. Nos. 5,202,536; 5,142,101; 5,105,056; 5,028,739; 4,952,448; and 4,857,668, such radiation often develops as a field or as transients within the radio frequency band of the electromagnetic spectrum, i.e., between about 10 KHz and 10 GHz, and is termed xe2x80x9celectromagnetic interferencexe2x80x9d or xe2x80x9cEMIxe2x80x9d as being known to interfere with the operation of other proximate electronic devices.
To attenuate EMI effects, shielding having the capability of absorbing and/or reflecting EMI energy may be employed both to confine the EMI energy within a source device, and to insulate that device or other xe2x80x9ctargetxe2x80x9d devices from other source devices. Such shielding is provided as a barrier which is inserted between the source and the other devices, and typically is configured as an electrically conductive and grounded housing which encloses the device. As the circuitry of the device generally must remain accessible for servicing or the like, most housings are provided with openable or removable accesses such as doors, hatches, panels, or covers. Between even the flattest of these accesses and its corresponding mating or faying surface, however, there may be present gaps which reduce the efficiency of the shielding by presenting openings through which radiant energy may leak or otherwise pass into or out of the device. Moreover, such gaps represent discontinuities in the surface and ground conductivity of the housing or other shielding, and may even generate a secondary source of EMI radiation by functioning as a form of slot antenna. In this regard, bulk or surface currents induced within the housing develop voltage gradients across any interface gaps in the shielding, which gaps thereby function as antennas which radiate EMI noise. In general, the amplitude of the noise is proportional to the gap length, with the width of the gap having less appreciable effect.
For filling gaps within mating surfaces of housings and other EMI shielding structures, gaskets and other seals have been proposed both for maintaining electrical continuity across the structure, and for excluding from the interior of the device such contaminates as moisture and dust. Such seals are bonded or mechanically attached to, or press-fit into, one of the mating surfaces, and function to close any interface gaps to establish a continuous conductive path thereacross by conforming under an applied pressure to irregularities between the surfaces. Accordingly, seals intended for EMI shielding applications are specified to be of a construction which not only provides electrical surface conductivity even while under compression, but which also has a resiliency allowing the seals to conform to the size of the gap. The seals additionally must be wear resistant, economical to manufacture, and capability of withstanding repeated compression and relaxation cycles. EMI shielding gaskets and other electrically-conductive materials, their methods of manufacture, and their use are further described in U.S. Pat. Nos. 6,121,545; 6,096,413; 6,075,205; 5,996,220; 5,910,524; 5,902,956; 5,902,438; 5,882,729; 5,804,762; 5,731,541; 5,641,438; 5,603,514; 5,584,983; 5,578,790; 5,566,055; 5,524,908; 5,522,602; 5,512,709; 5,438,423; 5,294,270; 5,202,536; 5,142,101; 5,141,770; 5,136,359; 5,115,104; 5,107,070; 5,105,056; 5,068,493; 5,054,635; 5,049,085; 5,028,739; 5,008,485; 4,988,550; 4,979,280; 4,968,854; 4,952,448; 4,931,479; 4,931,326; 4,871,477; 4,864,076; 4,857,668; 4,800,126; 4,529,257; 4,441,726; 4,301,040; 4,231,901; 4,065,138; 3,758,123; 3,026,367; 2,974,183; and 2,755,079, in U.S. patent appln. Publ. No. 20020010223, International (PCT) Patent Appln. Nos. WO 01/71223; 01/54467; 00/23,513; 99/44,406; 98/54942; 96/22672; and 93/23226, Japanese Patent Publication (Kokai) No. 7177/1993, European Pat. Appln. No. 1,094,257, German Patent No. 19728839, and Canadian Patent No. 903,020, in Severinsen, J., xe2x80x9cGaskets That Block EMI,xe2x80x9d Machine Design, Vol. 47, No. 19, pp. 74-77 (Aug. 7, 1975), and in the following publications of the Chomerics Division of Parker Hannifin Corporation, Woburn, Mass.: xe2x80x9cSOFT-SHIELD(copyright) 1000 Series;xe2x80x9d xe2x80x9cSOFT-SHIELD(copyright) 2000 Series;xe2x80x9d xe2x80x9cSOFT-SHIELD(copyright) 4000 Series;xe2x80x9d xe2x80x9cSOFT-SHIELD(copyright) 5000 Series;xe2x80x9d and xe2x80x9cSOFT-SHIELD(copyright) 5500, Preliminary Product Data Sheet (1998) Series; xe2x80x9cCOMBO(copyright) STRIP Gaskets;xe2x80x9d xe2x80x9cSPRINGMESH(trademark) Highly Resilient EMI Mesh Gasket,xe2x80x9d Technical Bulletin 114; xe2x80x9cMETAL STRIP(copyright) All Metal Gaskets;xe2x80x9d xe2x80x9cSHIELDMESH(trademark) Compressed Mesh Gaskets;xe2x80x9d and xe2x80x9cMETALKLIP(copyright) Clip-On EMI Gasket.xe2x80x9d
EMI shielding gaskets typically are constructed as a resilient element, or a combination of one or more resilient elements having gap-filling capabilities. One or more of the elements may be provided as a tubular or solid, foamed or unfoamed core or strip which is filled, sheathed, or coated to be electrically-conductive, or otherwise which is formed of an inherently conductive material such as a metal wire spring mesh. One or more of the other elements, and particularly in the case of a composite or xe2x80x9ccombination gasketxe2x80x9d having a conductive EMI shielding element in combination with an integral weather sealing strip (such as is sold commercially by the Chomerics Division of Parker-Hannifin Corporation (Woburn, Mass.) under the name xe2x80x9cCOMBO(copyright) STRIP Gasketxe2x80x9d), may be formed of a sheet, strip, xe2x80x9cpicture-frame,xe2x80x9d or other open or closed geometry of a solid, i.e., unfoamed, or foamed elastomeric material providing enhanced environmental sealing capabilities to which the conductive element is adhesively-bonded or otherwise joined. Each of the core or strip of the conductive element and the elastomeric material of the environmental sealing element may be formed of an elastomeric thermoplastic material such as polyethylene, polypropylene, or polyvinyl chloride, a thermoplastic or thermosetting rubber such as a butadiene, styrene-butadiene, nitrile, chlorosulfonate, neoprene, urethane, or silicone, or a blend such as polypropylene-EPDM. Conductive materials for the filler, sheathing, or coating of the conductive element include metal or metal-plated particles, fabrics, meshes, and fibers. Preferred metals include copper, nickel, silver, aluminum, tin or an alloy such as Monel, with preferred fibers and fabrics including natural or synthetic fibers such as cotton, wool, silk, cellulose, polyester, polyamide, nylon, polyimide. Alternatively, other conductive particles and fibers such as carbon, graphite, or a conductive polymer material may be substituted.
Conventional manufacturing processes for EMI shielding gaskets include extrusion, molding, or die-cutting, with molding or die-cutting heretofore being preferred for particularly small or complex shielding configurations. In this regard, die-cutting involves the forming of the gasket from a cured sheet of an electrically-conductive elastomer which is cut or stamped using a die or the like into the desired configuration. Molding, in turn, involves the compression or injection molding of an uncured or thermoplastic elastomer into the desired configuration.
More recently, a form-in-place (FIP) process has been proposed for the manufacture of EMI shielding gaskets. As is described in commonly-assigned U.S. Pat. Nos. 6,096,413; 5,910,524; 5,641,438; 4,931,479, and International (PCT) Patent Appln. No. 96/22672; and in U.S. Pat. Nos. 5,882,729 and 5,731,541, International (PCT) Patent Appln. No. WO 01/71223, and Japanese Patent Publication (Kokai) No. 7177/1993, such process involves the application of a bead of a viscous, curable, electrically-conductive composition which is dispensed in a fluent state from a nozzle directly onto to a surface of a substrate such as a housing or other enclosure. The composition, typically a silver-filled or otherwise electrically-conductive silicone or polyurethane foamed or unfoamed elastomer, then is foamed and/or cured-in-place via a chemical, thermal, or physical reaction which may be initiated or catalyzed via the application of heat or with atmospheric moisture or ultraviolet (UV) radiation to form an electrically-conductive, elastomeric EMI shielding gasket profile in situ on the substrate surface. By forming and curing the gasket in place directly on the substrate surface, the need for separate forming and installation steps is obviated. Moreover, the gasket may be adhered directly to the surface of the substrate to further obviate the need for a separate adhesive component or other means of attachment of the gasket to the substrate. In contrast to more conventional die cutting or molding processes, the flashless FIP process reduces waste generation, and additionally is less labor intensive in that the need for hand assembly of complex gasket shapes or the mounting of the gasket into place is obviated. The process further is amenable to an automated or robotically-controlled operation, and may be employed to fabricate complex gasket geometries under atmospheric pressure and without the use of a mold.
As electronic devices continue to proliferate, it is believed that additional EMI shielding products and methods of manufacture therefor would be well-received by the electronics industry.
The present invention is directed to a combination EMI shielding and environmental sealing gasket construction and method of manufacturing the same which is especially adapted for use in xe2x80x9cpicture-framexe2x80x9d and complex geometric configurations and/or in applications requiring a high level of weather or other environmental sealing such as in outdoor cabinets. The gasket construction includes one or more electrically-conductive EMI shielding gasket members, each of which may be a mesh, spring mesh, or an elastomeric or foam core covered in a mesh, and one or more integral environmental sealing members which may be robotically dispensed or otherwise formed-in-place around the shielding members as formed of a foamed or unfoamed elastomer.
In an illustrative embodiment, the one or more shielding gasket members may be provided as a resilient strip of a mesh or spring mesh which may have a generally circular, oval, xe2x80x9cD,xe2x80x9d polygonal, or other shape cross-section and which may be preformed by conventional methods into the geometry, which may be a closed geometric shape such as a circle, square, rectangle, or other xe2x80x9cpicture framexe2x80x9d-like shape, of the cabinet door or other structure, equipment, or device to be sealed.
Alternatively, the shielding gasket members may be provided as individual strips. In whatever form provided, the members may be placed, typically in a spaced-apart arrangement in the case of two or more members, in a grooved formed into a mold or other tool or, alternatively, directly into the cabinet, door, access panel, housing, or other structure to be sealed, such groove having a width which is sized relative to the widthwise extents of the members to define a predefined clearance therebetween corresponding to the desired widthwise extent of the sealing member which is to be formed. With the one or more shielding members being received in the groove, a form-in-place (FIP) gasket material may be dispensed, such as from a nozzle which may be robotically-controlled or by other automated means, within the groove along at least a portion of one or both sides of at least one of the shielding gasket members. With the dispensed material being foamed or otherwise expanding or flowing within the groove, the material thus is made to penetrate through the open spaces or interstices of the mesh and into at least a portion of the widthwise dimension of the shielding gasket member.
Upon the curing of the material, one or both of the shielding gasket members are at least partially embedded within the material which otherwise forms one or more environment sealing members, typically having a D-shaped profile characteristic of formed-in-place seals, between the shielding gasket members and/or between such members and the side walls of the groove. Optionally, the free surface of the sealing gasket being formed may be contained within a by a molding plate or other forming tool so as to effect the forming of the sealing gasket into a different profile such as a square or rectangle. Advantageously, by virtue of the penetration of the sealing material into the interstices of the mesh, the shielding and sealing gasket members are thereby mechanically and/or, depending upon the composition of the sealing material, which may be a polyurethane or silicone foam, adhesively or otherwise chemically bonded to form an integral combination gasket structure, with the need to bond the members together using a separate adhesive layer or otherwise in a separate joining operation being obviated.
The combination of the gasket of the invention may be produced in frames, sheets strips, or other forms which may be mounted to the structure to be sealed. Alternatively, the gasket construction may be formed-in-placed directly on the structure to be sealed.
The present invention, accordingly, comprises the articles and methods of manufacture possessing the construction, combination of elements, and arrangement of parts and steps which are exemplified in the detailed disclosure to follow. Advantageously, the gasket construction and form-in-place method of the present invention facilitate the net shape manufacture of picture-frame and other complex shapes or patterns of any dimension and which may include internal openings with less waste as compared, for example, to a die-cut part. Such construction and method, moreover, are amenable to the use of automated processing equipment and obviate the need for splicing and other operations which conventionally are preformed by hand. Thus, the gasket construction and method of the invention are particularly reliable and economical, and may be used in a variety of configurations, such as sheets, strips, pads, picture-frames, and die-cut-like patterns, in thin or thick cross-sections, and in a host of shielding and/or grounding applications such as for door or access panels, vents, and covers of cabinets and other enclosures. These and other advantages will be readily apparent to those skilled in the art based upon the disclosure contained herein.

Combination EMI shielding and environmental seal gasket construction


In some examples, a computing device may receive a content item for formatting, the content item including at least one scalable object to be rendered with a portion of content during presentation of the content item on an electronic device. The computing device may convert a complex shape element in the scalable object to at least one path command that includes a sequence of one or more paths that correspond to the complex shape element. The computing device may format the at least one path command for parsing by a content parser of the electronic device. Further, the computing device may associate the at least one path command with the portion of content so that the at least one path command will be rendered in place of rendering information for the scalable object that was originally included with the content item.

The continued proliferation of digital content items has led to an increase in the availability of such content items, as well as an increase in the availability of electronic devices and applications used for consuming these content items. For instance, users may consume content items, such as electronic books (eBooks) and other types of content items that include text and/or images, on an assortment of electronic devices. As the number of content items and devices for consuming content items continues to increase, users are ever more interested in enhancing their experiences while acquiring and consuming these content items.

Formatting a content item having a scalable object


A communication system uses multiple communications links that may include a high latency/high bandwidth link using a fiber-optic cable configured to carry large volumes of data but having a high latency. The communications links may include a low latency/low bandwidth link using skywave propagation of radio waves and configured to carry smaller volumes of data with a lower latency. The low latency/low bandwidth link employs a transmitting antenna system where aspects such as antenna height, type of ground, and typography of the surrounding area at the transmitting site are adjusted to optimize the direction and angle of propagation. Controlling these and other aspects increases the predictability and reliability of the wireless link by managing the number of hops and skip distance between the transmitting and receiving antennas. The two communications links may be used together to coordinate various activities such as the buying and selling of financial instruments.

Recent technological improvements have dramatically improved the ability to communicate across vast distances. Extensive fiber optic and satellite networks now allow remote parts of the world to communicate with one another. However, by spanning across these great distances, such as across the Atlantic or Pacific Oceans, fiber optic cables can incur a round-trip latency or time lag of about 60 msec or more. Satellite communications can experience even greater lag times. In many cases, this high latency cannot be overcome because it is inherent in the communications medium and equipment. For example, light may traverse an optical fiber 30-40% more slowly than a radio wave traveling the same distance through free space. Fiber optic networks typically require multiple repeaters that further increase latency. While generally not problematic in a number of circumstances, this high latency can cause unacceptable delays in the execution of time sensitive activities, especially time sensitive activities that require complex logic and/or are dependent on conditions that rapidly change. These latency issues can for example create problems for a whole host of activities, such as in the operation and/or synchronization of distributed computer systems, scientific experiments with geographically large sensor arrays, and telemedicine/diagnostic activities, to name just a few. In one particular example, orders to buy and sell securities or other financial instruments in world markets typically rely on communications links that carry data and instructions over systems using fiber optic lines, coaxial cables, or microwave communication links. Any delays in executing an order, such as caused by the high latency across fiber optic lines, can lead to significant financial losses.
In order to send information across broad distances by radio communication, a radio signal may take advantage of skywave propagation where the signal "bounces" between the earth and the upper atmosphere to traverse long distances across the globe. This can advantageously result in communications traveling rapidly beyond line of sight. However, it can also mean that transmitted signals may never reach the intended receiving station because the signals may never return to earth at that specific location. Predicting the likelihood of a transmitted signal reaching a particular location on earth via skywave propagation can be a challenge given that skywave propagation is affected by multiple unrelated variables such as weather conditions, sunspot cycles, changes in solar radiation, the time of day, the desired transmission frequency, the type of antenna, the height of the antenna above the ground, and the topography of the ground around the transmission site.

Optimizing the location of an antenna system in a low latency/low data bandwidth link used in conjunction with a high latency/high bandwidth link


The invention provides a semiconductor wafer cleaving method and apparatus which are used to obtain an ideal vertical cleaved plane of semiconductor wafers. A semiconductor wafer (1) having a scribing mark (2) inscribed on the surface is set on fulcrum members (6a and 6b). The fulcrum members (6a and 6b) are left-right symmetrical centering around the scribing mark (2) and parallel to the scribing mark (2). Fulcrum members (4a and 4b) are disposed left-right symmetrically centering around the scribing mark (2) and in parallel to the scribing mark (2) on the upper side of the semiconductor wafer (1). The fulcrum members (4a and 4b) are disposed outside the fulcrum members (6a and 6b). Load is applied from the fulcrum members (4a and 4b) side, wherein fulcrum forces are caused to operate from the respective fulcrum members (4a, 4b, 6a and 6b) onto the semiconductor wafer (1). A shearing force becomes zero in an area of the semiconductor wafer (1) between the fulcrum members (6a and 6b), wherein the maximum main stress of bending tension is actuated in a direction orthogonal to the perpendicular plane of the scribing mark (2), thereby cleaving the semiconductor wafer (1).

Since priorly, various types of semiconductor chips have been obtained by cutting off a plurality of element areas formed and arrayed on a semiconductor wafer at boundary positions. Recently, the cutting of semiconductor wafers is carried out by, for example, cleaving the wafers along scribing marks with the scribing marks provided at boundary positions of the element formed areas at the end edge on the surface of the semiconductor wafers.
FIG. 11 and FIG. 12 show a conventionally general method for cleaving semiconductor wafers. The cleaving method is called a "three-point bending method." First, a plurality of scribing marks 2 are arrayed and formed at the end edge on the surface of a semiconductor wafer 1 (These scribing marks 2 are provided at the boundary positions of the element formed areas on a semiconductor wafer 1). Next, a pair of fulcrum members 4a and 4b are disposed in parallel to the scribing marks 2 with each of the scribing marks 2 placed therebetween on the surface 3 where the scribing marks are formed. Also, on the rear side 5 opposite the scribing mark formed surface, a fulcrum member 6 is disposed so as to become parallel to each of the scribing marks 2, at the position opposed to the above scribing marks 2. After that, a tensile force is given to the scribing marks 2 by causing fulcrum forces P2, P1, and F1 to operate thereon from these fulcrum members 4a, 4b and 6, whereby the semiconductor wafer 1 is cleaved at the plane ZOY from the position of the scribing marks 2.
The relationship between a shearing force and a bending moment in carrying out a cleaving by the "three-point bending method" is expressed as shown in FIG. 13. As shown in FIG. 13, the positive or negative polarity of the shearing force is reversed at the lower fulcrum member 6 used as the boundary. In fact, the operating point of a fulcrum force F1 acting from the fulcrum member 6 on the semiconductor wafer 1 has a definite width although being slight. Therefore, the shearing stress does not become zero in the entirety of the operating area of the fulcrum force F1. As shown in FIG. 12, a portion of a minute cubic volume dva of one-sided half of the scribing mark is taken for instance, wherein a shearing stress .tau. parallel to the plane ZOY to be cleaved, and a bending tensile stress .sigma..sub.ax perpendicular to the plane ZOY to be cleaved are produced.
If the shearing stress and bending tensile force are expressed in terms of Mohr's stress circle, they will become as shown in FIG. 14. That is, the direction of action of the ruling maximum main stress .sigma..sub.a1 of cleavage produced on the cleavage plane of the scribing mark is not a direction .sigma..sub.ax perpendicular to the vertical cleavage plane (plane ZOY) ideal to the semiconductor wafer 1, but has an angle .alpha.1 from the direction .sigma..sub.ax, (which can be easily calculated by Mohr's stress circle). Therefore, as in the cleavage plane of a cleavage state illustrated in FIG. 15, an oblique cleaved portion 7a is produced at the portion at the lower side of the scribing mark 2 on the cleavage plane 7 of the semiconductor wafer 1, whereby such a problem arises, by which an expected cleavage plane could not reliably be obtained.
In addition, as shown in FIG. 16, when actually carrying out a cleaving work, the fulcrum member 6 does not become parallel to the scribing marks 2, whereby a possibility exists, that the fulcrum member 6 is disposed so as to cross the extension line of the scribing marks 2. In such cases, a problem arises, by which a cleavage plane 7 bent as shown in FIG. 17 would be produced.
The present invention was developed in order to solve the above shortcomings and problems, and it is therefore an object of the invention to make the shearing stress zero in the vicinity of the scribing marks, and to make the direction of the maximum main stress produced in the scribing mark perpendicular to the ideal vertical cleavage direction. That is, the invention is to provide a semiconductor wafer cleaving method and apparatus which enables an ideal mirror-finished cleavage plane by operating only the bending tensile stress onto scribing marks.

Semiconductor wafer cleaving method and apparatus


A joining method that allows joining processing to be carried out simultaneously at a plurality of portions without being influenced by a supply time restriction on a joining material, and a semiconductor device manufacturing method using the joining method are provided. A chip and a lead frame are tentatively assembled having a solid solder block interposed therebetween. The solder block is provided with protruding parts that protrude in one direction. The protruding parts are inserted into solder supply ports of the lead frame, whereby the chip and the lead frame are tentatively assembled. Subsequently, the chip and the lead frame are fed into a reflow oven, and the solder block is melted and thereafter solidified. Thus, the chip and the lead frame are joined to each other.

1. Field of the Invention
The present invention relates to a joining method for joining two joining target members, e.g., a lead frame and a chip of a semiconductor device, with solder or the like, and to a semiconductor device manufacturing method using the same.
2. Description of the Background Art
Two joining target members, e.g., a lead frame and a semiconductor chip (which hereinafter may simply be referred to as the "chip") of a semiconductor device are joined to each other with a joining material such as solder. According to joining methods of conventional techniques, a heat spreader on which a lead frame and a chip are mounted is tentatively assembled before being put into an oven, and molten solder is supplied from a solder supply source in the oven. By solidifying the supplied molten solder, the lead frame and the chip are joined to each other (for example, see Japanese Patent Application Laid-Open No. 2008-182074).
According to the joining methods of the conventional techniques such as disclosed in Japanese Patent Application Laid-Open No. 2008-182074, since the solder supply source supplying the solder is provided one in number, the solder cannot be supplied to a plurality of portions at once. In the case where the solder is supplied to a plurality of portions, the molten solder must be supplied to those portions one by one in order, and hence it takes time.
Further, since the heat must be retained while the molten solder is supplied, the base material of the chip may be influenced by the molten solder at the portions where the molten solder has already been supplied. For the purpose of suppressing the influence, the heating time and the processing speed in the joining processing are restricted. Therefore, the time from when the supply of solder is started in the oven until when the supply ends is restricted. This is referred to as the supply time restriction. The supply time restriction poses a problem that the number of chips mounted on a semiconductor device cannot be increased.

Joining method and semiconductor device manufacturing method


This device provides a honeycomb structure in which stress concentration on a flat plate in the area of weld with a corrugated plate is avoided in the outer side area of the honeycomb structure, for example, the first and second layers from the outside thereof, whereby cracks and exfoliation of the flat plate are avoided in the area of the weld and the core is also protected from slipping out.. In honeycomb structure 5, corrugated plate 3 and flat plate 1 are disposed alternately and welded to form a wound block. In the range of at least not less than two layers from the outside in the honeycomb structure 5, two sheets of flat plate 1 are used in a pair so that they overlap without welding therebetween. When honeycomb structure 5 is used in an environment wherein thermal cycles of heating and cooling are repeated, the outer side thereof is always cooled by open air, while the inner side is not cooled, as a result of which a difference between the amount of thermal expansion and contraction due to the temperature difference occurs and stress is generated. However, this stress is absorbed by two overlapped sheets of flat plate 1.

1. Field of the Invention
The present invention relates to a honeycomb structure for use in a high temperature environment and to a method of manufacturing the same, and more particularly a honeycomb structure which carries a catalyst as a support matrix for use in a catalytic converter for purifying the exhaust gas from an automobile engine and to a method of manufacturing the same.
2. Prior Art
The honeycomb structure of the conventional type which has been used is usually composed of a strip of corrugated plate which is made by folding the plate into continuously corrugated unevenness and of a strip of flat plate, which are alternately disposed and welded to each other by brazing into multilayers, and made overall into a prescribed configuration in a form such as a wound multilayered block. As the base metal of the above, a corrugated plate and a flat plate each having a uniform thickness have generally been used. In order to withstand use in a high temperature environment, in many cases stainless steel foil or the like have been used, and for the same purpose a brazing filler metal from, for example, the nickel group and the iron group for the brazing filler metal has been used. The honeycomb structure of this type has been used in high temperature environments, particularly in environments subject to thermal cycles of repeated heating and cooling. For example, this honeycomb structure has been used in catalytic converters for purifying the exhaust gas from automobile engines, for carrying the catalyst on its corrugated and flat plates which serve as the support matrix, and the high temperature exhaust gases from the running automobile engine including noxious emissions have been purified through reaction with the catalyst which is effected by passing through the honeycomb structure.
As examples of the conventional honeycomb structure of this type, there are U.S. Pat. No. 5,084,361, 4,282,186 and 4,400,860, and B.P. 1,452,982, applied for by the present inventor.
However, there is the following problem which has been realized about the conventional honeycomb structure of this type. When this honeycomb structure is used as the catalyst support for an exhaust gas purifying apparatus, the temperature of the exhaust gas from the running engine passing through the honeycomb structure is uniformly elevated, and the whole body of the honeycomb structure, i.e., both its outer side or casing side and its inner side or center portion, is heated by the high temperature exhaust gas. Since the outer side of the honeycomb structure is cooled by open air through the casing, its temperature rise when heated is relatively small; but the honeycomb structure is rapidly cooled to a low temperature when the engine of the vehicle is stopped, while the inner side of the honeycomb structure is not cooled by open air, and the temperature rises to a high level when heated and is maintained at that high level for a long time even when the engine of the vehicle is stopped. In the honeycomb structure which is used in a high temperature environment like this, particularly in an environment subject to thermal cycles of repeated heating and cooling, a difference between the amounts of thermal expansion and contraction takes place, as a result of which stress is generated between the outer and inner sides of the honeycomb structure due to the large temperature difference existing therein.
FIG. 1a is an enlarged view showing the principal part of the outer side of the honeycomb structure of the conventional type. In the figure, flat plate 1 is welded to corrugated plate 3 by means of brazing filler metal 2 applied to both sides thereof. Corrugated plate 3 can absorb stress A by deformation; however, since flat plate 1 is fixed at the weld both sides, it is hard to absorb stress A, particularly in the range of the first and second layers from the outside thereof, and cracks B and exfoliation are liable to be generated in the area of the weld due to stress A concentrated thereto, and problems have been observed from the viewpoint of heat proofness, durability and reliability of the honeycomb structure. Hitherto, countermeasures have been taken to prevent concentration of stress A by limiting the location of welding flat plate 1 and corrugated plate 3 to only a part of the total contact line or by providing thicker flat plate 1; however, no fundamental solution has been obtained, and stress A is still concentrated in the area of the weld of flat plate 1, and cracks B and exfoliation are also still liable to be generated.
FIG. 1b is a perspective diagram showing the direction of stress A in the area of the outer side of the conventional type of honeycomb structure. When the honeycomb structure is used as the catalyst support for an exhaust gas purifying apparatus, a large temperature difference is generated as described above between the outer side of the honeycomb structure on the side of casing 4 and the inner side thereof on the side of the center; further, since casing 4 is thicker and of a different material than flat plate 1 and corrugated plate 3, thermal expansion and contraction due to heating and cooling thereof commonly take place but with different amounts on one side, i.e., in casing 4, the outer side of the honeycomb structure, and on the other side, i.e., on the inner side thereof, resulting in stress A working in the reverse direction on each side. For example, when the honeycomb structure is heated, the direction of thermal expansion, i.e., elongation, which occurs is the same as the passing direction of exhaust gas C, however, the amount is small with the outer side former but large with the inside. As shown in FIG. 1b, demarcating the range at the first or second layer from the casing 4 and at the inner side of the honeycomb structure, i.e., in the former, stress A works in the reverse direction of passing exhaust gas C, while in the latter, stress A works in the direction of exhaust gas C. Therefore, on the outer side of the honeycomb structure, in particular in the range of the first and second layers from the outside, stress A concentrates in the area of the weld of flat plate 1 and corrugated plate 3, whereby the core is sometimes caused to slip out, and problems of the honey-comb structure are observed from the view-point of heat proofness, durability and reliability.

Honeycomb structure for purifying exhaust gas and method of manufacturing same


The present invention relates to a downhole well tubular structure configured to be arranged in a borehole in a formation, comprising a well tubular part having an opening and an inner face, the well tubular part having an axial extension, a first sleeve configured to slide within the well tubular part along at least part of the inner face, the first sleeve having a first end face and a second end face, the first sleeve having a first sleeve groove facing away from the well tubular part, the first sleeve groove of the first sleeve having a first groove face extending radially and facing away from the first end face, and the first sleeve groove of the first sleeve having a second groove face inclining away from the first groove face, wherein the well tubular part has a first inclined face facing the first end face of the first sleeve, the first inclined face inclining from the inner face away from the first sleeve, wherein the well tubular part comprises a second inclined face facing the first inclined face, the second inclined face inclining from the inner face away from the first sleeve, and the first sleeve is configured to slide towards the first inclined face while uncovering or covering the opening. The present invention also relates to a downhole system comprising a downhole well tubular structure according to the present invention and to a sleeve operating method for uncovering or covering an opening in the downhole well tubular structure according to the present invention.

Opening or closing sliding sleeves in a well downhole is often performed by an operation tool having projectable keys, where each sleeve has a profile matching the profile of the key. When having sleeves with more positions than two, the operation of sliding sleeves has to be performed in several runs; one run for each position of the sleeve since the sleeves have different profiles in order to be able to be positioned in different positions, and thus the operation tool needs to change keys to match another profile of the sliding sleeve.

Downhole well tubular structure with valve sleeve