A system for controlling memory accesses in a memory device in a multi-processor computer system comprises a memory controller and a data storage. The data storage comprises a plurality of memory lines. Each memory line has a check field for storing a GONE code that indicates that the data is held in a cache, a g bit field for storing a G bit for confirming the code in the check field, a tag field for storing an identification of the processor in whose cache the data is held, and a d bit field for storing the true value of the G bit in rare situations. The memory controller comprises a data buffer, an address buffer, and a memory sequencer. The memory sequencer is a state machine for controlling the functions of the memory device. The method includes the steps of reading a memory line; determining if the data contained in a check field portion of the memory line matches a GONE code generated from the address of the memory line; if the check field and GONE code values do not match, reading the data as data; if the check field and GONE match, checking the G bit; if the G bit is 1, outputting the address of the processor that holds the data in its cache; and if the G bit is 0, reconstructing the data from a D bit and outputting the data as data.

1. Field of the Invention
The present invention relates generally to computer systems having multiple processors with caches. In particular, the present invention relates to a system and method for implementing cache tags in a memory for maintaining cache coherence.
2. Description of the Background Art
The use of multiple processors is a recent trend in computer design. Each processor may work on a separate portion of a problem, or work on different problems, simultaneously. The processors used in the multi-processor architectures generally each have cache. A cache is a relatively small group, when compared to shared memories, of high speed memory cells that are specifically dedicated to a processor. A processor""s cache is usually on the processor chip itself or may be on separate chips.
Processors use caches to hold data that the processor has recently accessed. A memory access is any action, such as a read or a write, where a processor receives, modifies, or receives as well as modifies the contents of a memory location. Generally, a processor can access data in its cache faster than it can access data in the main memory of the computer. Furthermore, by using data in its cache, a processor does not use the bus of the computer system to access data. This leaves the bus free for use by other processors and devices.
A particular problem associated with the use of caches is that the data becomes xe2x80x9cstale.xe2x80x9d A first processor may access data in the main memory and copy the data into its cache. The first processor may then modify the data in its cache. At the instant when the data in the cache of the first processor is modified, the corresponding data in the memory is stale. If a second processor subsequently accesses the original data in the main memory, the second processor does not find the most current version of the data. The most current version is in the cache of the first processor. The second processor, however, needs the most current version of the data. A prior art solution to this problem is for processors to eavesdrop on the bus. When the first processor detects the main memory access by the second processor for data that the first processor holds in its cache, the first processor inhibits the main memory and supplies the data to the second processor. In this way, a processor always receives the most current version of the data.
This prior art solution suffers from a number of problems. Computer architectures are moving to multiple-processor, multiple-bus configurations. The busses are coupled through an interface. For efficiency purposes, many signals on a bus are not transmitted across the interface to other busses. Among signals, which are not transmitted across the interface, are memory access signals where the path between source and target devices does not cross the interface. Many other devices also do not transmit all signals that they receive. For example, cross-bar switches, which concurrently connect multiple pairs of source and target ports, limit the transmission of memory access signals to the data path between source and target. When devices do not transmit all memory access signals over its data path, it is impossible for processors, which are not the source and target, to eavesdrop on memory accesses and therefore, impossible to determine when the data is stale. Thus, this prior art solution is not effective in systems that use devices that do not transmit all memory access signals.
Decreases in access time of main memories and increases in the size of caches have created other problems with eavesdropping. Eavesdropping on the bus assumes that a processor can inhibit the main memory and place the data on the bus faster than the main memory can access the data. Memories may, however, cache copies of recently accessed data within themselves; in which case, they often can provide data before a processor can inhibit the memory. Also, caches have become larger. Generally, larger memories, whether main memories or caches, require more time to access. Processors, with large caches, cannot access the larger cache fast enough to make the prior art solution workable unless other memory access are delayed while eavesdropping is performed. Such a delay would significantly degrade the performance of the processor.
Memory tags have been used to overcome some of these problems. A memory tag is associated with a memory address whose data is held in a cache. When a processor copies the data at that address into its cache, a memory tag is updated to identify the processor in whose cache the data is held. If a second processor attempts to access the data in the memory, the processor will receive the memory tag. Memory tags remove the need for eavesdropping. The memory tags are held in a separate memory device called a tag storage. When a processor reads or writes data to a memory address, both the tag storage and the memory address are accessed. The memory address is accessed for the data, and the tag storage is accessed for the possibility of a memory tag. If the accesses are performed sequentially, two accesses greatly slow the operation of the memory. If done in parallel, the tag storage greatly complicates the design of the memory controller. The width of the tag storage differs from the width of the main memory, in one embodiment the tag storage is 20 bits wide and the main memory is 64 bits wide. The different sized memories require complicated modifications to the memory controller. Furthermore, the tag storage requires changes in the bus width and requires additional circuit chips that occupy space, consume power, and add to the expense of the computer system.
Referring now to FIG. 1, a block diagram of a prior art memory 23 is shown. The prior art memory 23 comprises a data storage 40, a tag storage 42, and a memory controller 25. The data storage 40 comprises a plurality of memory lines. Each memory line comprises one or more words and has an unique address. A first memory line 44 has address 0, and a second memory line 46 has address 1. Each address indicates a complete memory line. The remaining memory lines of the data storage 40 are addressed similarly so that a last memory line 48 has address Nxe2x88x921, where N is the total number of memory lines in the data storage 40. Each word has a fixed bit size. A word may be any number of bits long, but currently is preferably 64 bits long or other powers of 2. A memory line 44, 46, 48 may include any number of words, but within the data storage 40 each memory line 44, 46, 48 has the same number of words. The tag storage 42 comprises a tag cell for each memory line of the data storage 40. Each tag cell has an address that corresponds to a memory line of the data storage 40. A tag cell 50 has an address 0 and corresponds to the first memory line 44. Similarly, a tag cell 52 has an address 1 and corresponds to a second memory line 46, and a tag cell 54 has address Nxe2x88x921 and corresponds to a final memory line 48. Each tag cell 50, 52, 54 is more than one bit wide and contains data that indicates if the data held in the corresponding memory line 44, 46, 48 is valid data or if a processor holds the data. Data is valid, or xe2x80x9cfresh,xe2x80x9d if no processor holds the data in its cache. Fresh data may also be referred to as xe2x80x9cunownedxe2x80x9d data. Data is referred to in this application as xe2x80x9cownedxe2x80x9d and is not fresh if a processor holds a copy of the data in its cache. If a processor owns the data, the tag cell 50, 52, 54 contains an indicator for indicating that the data is owned and a tag that identifies the processor that owns the data.
Any memory operation that requires the data held at an address is referred to as an access. The basic operations are ReadOwned and WriteReturn. ReadOwned and WriteReturn will be discussed in detail below. Other operations may also be performed. The processor that is executing an operation is referred to as the accessing processor. Every memory access requires an operation on the addressed memory line 44, 46, 48 and the assigned tag cell 50, 52, 54. This is true whether the memory access is a ReadOwned or a WriteReturn. If the access is a ReadOwned, the data storage 40 must be read, and the tag storage 42 must be read to determine if the data is fresh. If the memory access is a WriteReturn, the appropriate address must be written to and the assigned tag cell 50, 52, 54 must be set to indicate fresh data.
The memory controller 25 is a state machine for controlling the operation of the memory 23. The memory controller 25 is coupled to processors and other devices of a computer system by a bus 31. Data, control, and address signals are transmitted to the memory 23 on the bus 31. The memory controller is coupled to the data storage 40 by a line 27 and is coupled to the tag storage 42 by a line 29. In this application, a line refers to one or more wires. When the memory controller 25 receives a memory access signal, it must perform an operation on both the data storage 40 and the tag storage 42. For example, if the memory controller 25 receives a ReadOwned command on the bus 31 for a memory location in the data storage 40, the memory controller 25 first asserts a signal on line 27 for the data storage 40 to transmit the contents of the first memory line 44 to the memory controller 25. For purposes of this example, it will be assumed that the memory address was 0 for the first memory line 44. The data storage transmits the data on line 27. The memory controller 25 simultaneously asserts a signal on line 29 for the tag storage 42 to transmit the contents of tag cell 50 to the memory controller 25. The memory controller 25 determines if the data, received from the tag storage 42, indicates that the data contained in memory line 44 is owned. If the data contained in memory line 44 is unowned, the memory controller outputs the data onto the bus 31. If the data is owned, the memory controller 25 outputs the tag contained in the tag cell 50. Other memory accesses such as WriteReturn also require an operation on both the data storage 40 and the tag storage 42. This prior art memory 23 is slow and requires more complicated memory controller lines 27, 29.
As can be seen from the above example, there is a continuing need for a faster system and method for ensuring that processors receive fresh data and for identifying processors holding cached data. This system and method should not require modifications to other devices of a computer system.
The present invention overcomes the deficiencies and limitations of the prior art with a system and method for controlling memory accesses in a multi-processor computer system. The present invention advantageously provides a system for storing data that identifies valid data and identifies data held in a processor""s cache without a separate tag storage. The present invention also advantageously reduces the number of read functions that must be executed to access a memory location.
The system comprises a data storage device and a memory controller. The data storage device comprises a plurality of memory lines, each memory line having an unique address. A memory line comprises one or more 64 bit words. Words having any number of bits, however, may be used. Each memory line comprises a check field, a g bit field, a tag field, and a data field. A small portion of the data storage is used for a plurality of d bit fields. Each memory line in the remaining portion of the data storage has an assigned d bit field. A memory line may contain data or codes; the codes indicate that a processor owns the data in the cache.
When a memory line contains unowned data, the data resides in the memory line as in a conventional memory device. The check field, g bit field, and tag field are used to hold the data along with the rest of the memory line.
When the memory line contains owned data, the data resides in a cache of a processor. The check field and tag fields contain codes; the check field code contains a GONE code and the tag field code is a encoded identifier of the processor that holds the data. Thus, on each memory access, the data is output, or the location of the data in a cache is output. As opposed to the prior art, a second memory access is generally not required. A special case occurs, however, when data is being held in a memory line that happens by chance to have a check field equal to GONE. In this case, the data in the data storage is unowned, but it appears that the data is owned. For this rare situation, the present invention advantageously uses a g bit field. The g bit field contains a G bit. Whenever the data is owned, the G bit is set to 1. If the data is in the memory line, but the data in the check field by chance matches the GONE value, the G bit is set to 0 and the actual data value, normally held in the g bit field, is contained in the assigned d bit field. Thus, there are three cases: 1) The data is owned. In this case, the check field code is GONE, the g bit field contains a 1, and the tag field contains an indicator of the processor that owns the data; 2) The data is unowned, and the data contained in the check field portion of the memory line does not match the GONE code for identifying owned data. In this case the memory line contains the data; and 3) The data is contained in the memory line, and the data held in the check field portion of the memory line matches the GONE code. In this case, the g bit field holds a 0 and the d bit field holds the true value of the G bit.
As can be seen, only in the rare third case is a second memory access required to obtain the requisite data. For any memory line, the GONE code may be any value but is preferably the result of a hashing function of the address of the memory line.
The memory controller comprises a data buffer, an address buffer, and a memory sequencer. The data buffer receives data signals and outputs data signals for the memory device. Similarly, the address buffer receives address signals for the memory device. The memory sequencer is a state machine that receives control signals, compares data received by the data buffer to data stored in the data storage, and generates signals to control the operation of the memory device.
The present invention includes a method for implementing cache tags for multi-processor computer systems. The method includes the steps of reading a memory line; determining if the data contained in a check field portion of the memory line matches a GONE code generated from the address of the memory line; if the GONE code and data do not match, reading the data as data; if the GONE code and data match, checking a G bit; if the G bit is 1, outputting the address of the processor that holds the data in its cache; and if the G bit is 0, reconstructing the data from a D bit and outputting the data as data.

System for and method of efficiently controlling memory accesses in a multiprocessor computer system


A lens unit is detachably connected via a communication interface with a camera body having a strobe and constituting a camera device. The lens unit is configured to include an optical system including a lens; an imaging unit including an image sensor which photo-electrically converts light from a subject having transmitted through the lens; an image processor which generates image data from an output of the imaging unit; and a strobe controller which controls a flash operation of the strobe provided in the camera body in accordance with a release signal from the camera body.

1. Field of the Invention
The present invention relates to a lens unit which can perform flash control over a strobe, a camera body detachable from the lens unit, a camera device comprising the lens unit and the camera body, and an imaging method using such a camera device.
2. Description of the Prior Art
A type of camera device such as a digital camera incorporating a strobe or to which an external strobe is attached is well known. In case of a camera device comprising an interchangeable lens unit, the optimal property of the strobe for photographing differs depending on a combination of a lens unit used and an image sensor contained in the camera body. It is extremely difficult to incorporate a strobe or attach an external strobe suitable for all the lens units in/to the camera device.
In view of solving the above, Japanese Patent No. 3945052 (Reference 1) discloses an interchangeable lens unit type digital camera having a lens unit incorporating a strobe, and Japanese Patent Application Publication No. 2005-142831 (Reference 2) discloses a strobe unit of a digital camera configured to be replaceable with ones different properties.
In the digital camera disclosed in Reference 1, a strobe device can be selectively attached to each lens unit in accordance with a property of the lens unit. However, provision of a strobe device for each lens unit may increase the size and manufacture costs of the lens unit.
It is possible to select and mount an optimal strobe device for the digital camera disclosed in Reference 2. However, it requires preparation of different strobe devices with different properties in advance, resulting in an additional work for a user to change one strobe device to another one and increasing costs.

Lens unit, camera body, camera device, and imaging method


A pair of half core blocks, one of which is provided with a groove for providing a prescribed gap depth in a magnetic head, are bonded together to produce a ring core. The ring core is inserted into a slot formed in a top of a magnetic slider and secured in position which provides a precise flush relation between a base end of a half core provided with a groove and the top of the slider. The slider is ground from its bottom to expose the end of the ring core inserted into the slot to produce a head assembly. One side of the ring core portrudes from the slider in the head assembly. When one or more of the head assemblies are mounted on a base block, the protruding side is maintained in contact with a reference upstanding plane provided by a jig for definite positioning of the head assemblies so that gaps in the respective ring cores extends exactly in a running direction of a magnetic tape, thereby preventing azimuth loss.

This invention relates to a method of manufacturing a magnetic head to be used in various recording/reproducing instruments such as cassette tape recorders and video tape recorders and streamers associated with a computer for preventing accidental erasure of data stored in a hard disc unit of the computer.
Japanese Patent Publication No. (Sho) 51-44648 discloses a process for manufacturing the magnetic head comprising the steps of preparing a magnetic ring core element consisting of a pair of half bodies and providing a prescribed gap, and inserting and securing the ring core element in a slot formed in a parallelepiped block or slider of magnetic material. Into the slot is inserted a glass rod which is then melted and solidified so that the slot is filled with the glass material. The glass material in the slot is formed to form a groove of a width identical to a thickness of the magnetic core element and a depth greater than the slot. The core element is fitted into the groove and fixedly positioned by remelting and resolidifying the glass material. The slider is ground from the bottom side to expose the inserting end of the core element, thereby producing a head assembly. The head assembly may simply be used as a magnetic head. In other embodiments, one or more of the head assemblies are mounted in position on a base block to produce a composite magnetic head. The head assembly may include two or more of ring core elements fitted in slots or grooves extending in parallel in the slider.
According to this prior art, if the core element should be prepared with displacement in height with respect to the two half bodies, it would become difficult for the core element to be definitely positioned in the slot in the slider. If the base end of the core element fitted in the slider could not be maintained flush with the top side of the slider, a prescribed gap depth in the magnetic head would be impared, resulting in deterioration of characteristics of the magnetic head.
When producing the composite magnetic head, plural head assemblies are placed and secured on the base block with a jig providing a reference plane to be in contact with the side surface of the slider. This requires high working accuracy on the side surface of the slider, which will inevitably and considerably increase a manufacturing cost of the composite magnetic head. In case of degraded working accuracy on the side surface, the gaps in the ring cores in the respective head assemblies would not be aligned in parallel, which may cause azimuth loss. The above can also be said when a single head assembly is to be mounted in position on the base block.


A risk degree estimation device of a driving assistance device calculates the potential risk degree at a plurality of intersection points in a mesh set around a host vehicle. The risk degree estimation device changes the amount of information relating to the potential risk degree calculated for the entire region of the mesh in which the intersection points are set in accordance with at least one of the environment and state of the host vehicle. For this reason, it becomes possible to calculate the potential risk degree around the host vehicle depending on the situation.

A device which calculates the potential risk degree around a vehicle so as to increase traveling safety has been suggested. For example, Patent Literature 1 discloses a minimum risk locus generation device which detects a road shape and obstacles and calculates a minimum risk traveling locus, and an endangerment warning device using the same.
The endangerment warning device of Patent Literature 1 includes an obstacle detection radar, a white line detection camera, a traveling state detection sensor, and a CPU. The CPU acquires information relating to an obstacle from the obstacle detection radar, and acquires the road shape and the traveling position of the host vehicle from the white line detection camera. The CPU also acquires vehicle speed data and the operation situation of a direction indicator from the traveling state detection sensor, and acquires road information from a navigation device.
The CPU estimates a traveling route in a traveling route estimation unit on the basis of the acquired information, and sets the value of the risk degree at each point on the road in a risk degree setting unit. In this case, the surroundings of the vehicle are divided into a virtual mesh (lattice-shaped regions), and the value of the risk degree in each lattice is calculated. The CPU calculates the minimum risk traveling locus, in which the total risk degree is minimal, in a minimum risk locus calculation unit. When the risk degree on the minimum risk traveling locus exceeds a warning threshold value, a determination unit of the CPU outputs a warning to a display device and a speech device.


The present invention relates to a display device having a touch panel, and more particularly, to a touch panel display device which can improve visibility. The display device of the present invention includes: a display panel; a first film layer that is disposed on the display panel, and includes a first material, a first transparent layer having a first pattern disposed on the first material, and an index matching layer disposed between the first material and the first transparent layer; a second film layer that is disposed on the first film layer, and includes a second material, a second transparent layer having a second pattern disposed on the second material, and an index matching layer disposed between the second material and the second transparent layer; and a touch window disposed on the second film layer.

Portable information processing devices such as laptop computers, portable transmission units, and cellular phones execute text and graphic processing using a variety of input devices, for example, keyboards, mouses, and digitizers.
There are limitations as to convenience in use of only keyboards or mouses as the input devices. Accordingly, such input devices have been developed so that everybody may easily input characters without false operation and a user may input characters while carrying the input devices.
Recently, there is interest in micro-technologies such as fabrication technologies related to processing and design providing high reliability, new functions, durability, and materials or substances, which go beyond levels satisfying need for general functions of the input devices.
Particularly, touch panels are utilized as the input devices so that everybody may easily input characters without false operation while carrying the input devices and a user may input characters without other input equipment.


The invention relates to a laminating foil having an initial roughness on at least one side, which makes the laminating foil matte, wherein the laminating foil has a marking configured as a surface pattern with surface portions on the matte side or at least on one of the matte sides, wherein the roughness of the surface portions is different from the initial roughness. The invention furthermore relates to a laminating foil set comprising the laminating foils, a method for hot laminating sheet material using such laminating foils, a laminating unit for using the laminating foil, and eventually a laminating system including the laminating unit and the laminating foils.

In order to protect sheet material in particular valuable documents it is known to hot seal the sheet material with a laminating foil. This is done in the non industrial field, this means in the office and personal field through laminating units typically configured as table top units. Such laminating units are known e.g. from DE 20 2005 005 020 U1; and in combination with a cutting unit, they are known from EP 1 724 111 A2. They have essentially the same configuration; this means a housing in which a laminating apparatus is disposed. Between a feed opening on one side and an exit opening on the other side of the housing a pass through channel extends through the housing, wherein the laminating apparatus is associated with the pass through channel. The latter typically comprises at least one pair of rollers, possibly also several pairs of rollers, made of two respective laminating rollers disposed on top of one another and forming a laminating gap, wherein the laminating gap is adjusted, so that the combination of sheet material and laminating foil in the laminating gap is exposed to substantial pressure. In hot laminating units at least one of the laminating rollers, typically both are heated, so that the combination of sheet material and laminating foil is also heated additionally. During passage the laminating foils are glued together with the sheet material to be heat-sealed there between.
Typically, the sheet material is heat-sealed in between two foil sheets forming a laminating foil. These can be loose foil sheets or foil webs which are rolled up within the laminating unit and which are pulled off from the rollers during the laminating process, wherein the separation is provided through cutting apparatuses (re. US 2004/0050500 A1). Instead, the two foil sheets can also be provided in the form of a laminating foil pouch, wherein the two foil sheets are connected with one another at least at one lateral edge. Such laminating foils are known e.g. from DE 197 44 595 A1 and DE 201 00 328 U1. The foil sheets are configured as composite foils, wherein a transparent clear foil e.g. made from polypropylene is provided with a heat resistant glue layer which is made e.g. from EVA (Ethylen-Vinylacetate-Copolymer) (Re. DE 600 29 505 T2).
For the time being, laminating foils with a thickness of 30 μm to 500 μm are commercially available. Selecting the foil thickness can provide a desired flexibility or stiffness to the laminated sheet material. It is implied that more thermal energy has to be provided for hot sealing thick laminating foils, than has to be provided for hot sealing thin laminating foils made of the same materials. Laminating units, which are configured for processing laminating foils with different thickness therefore have to be adaptable to the thickness of the respective thickness of the laminating foil to be processed, so that on the one hand sufficient thermal energy is provided for welding the sheet material, on the other hand the laminating foil does not overheat so that it is damaged. Therefore such laminating units comprise adjustment apparatuses through which the temperature of the laminating apparatus and/or the pass through velocity can be adapted to the respective thickness of the laminating foil by hand.
However, in practical applications it has become apparent that there are always operator errors, in particular when, as in large offices, many persons have access to a laminating unit. An operator error has the consequence that the lamination is insufficient for a heat impact which is too small, thus the laminated sheet material is not protected sufficiently or that the laminating foil overheats for excessive heat impact and thus sticks to the laminating rollers which causes severe damages to the laminating unit. Furthermore, the laminated sheet material is damaged, so it is unreadable. The latter condition is mostly non repairable and in the worst case causes the destruction of the document.
DE 100 04 486 A1 discloses a cartridge laminating unit in which a control and/or regulation apparatus is provide through which control elements can be controlled which influence the laminating process as a function of properties of the respective cover to be laminated, which properties are detected by a sensor, wherein the control elements are e.g. the heating apparatus for adjusting a particular laminating temperature and/or a drive apparatus for adjusting a particular laminating speed and/or a press apparatus for adjusting a particular laminating pressure. For this purpose the roll film cartridge has a machine readable encoding strip on its outer surface, e.g. a typical bar code strip. Alternatively, the encoding can also be provided directly at the roll film and can e.g. be detected through a window in the cartridge wall, or at an end of the roll film which protrudes from the output slot. It is also conceivable that the roll film cartridge or the roll film is provided with a mechanically detected marking which can be detected by a detector and which can be converted into an electrical sensor signal which can be transmitted to a control unit.


One embodiment of the present invention provides a system that facilitates detecting an anomaly in a signal, wherein the signal is sampled to produce a set of possible quantized signal values. During operation, the system constructs a “reference distribution” for an “occurrence frequency” of a specific quantized signal value from the set of possible quantized signal values. The system then obtains a “deviant distribution” associated with the reference distribution, wherein the deviant distribution has an offset from the reference distribution to indicate an anomaly in the signal. Next, in response to a new occurrence of the specific quantized signal value, the system updates a mean and a variance of the reference distribution for the specific quantized signal value. The system also adjusts the deviant distribution for the specific quantized signal value based on the updated mean and the updated variance of the reference distribution for the specific quantized signal value.

1. Field of the Invention
The present invention relates to techniques for automatically detecting problems in systems. More specifically, the present invention relates to a method and an apparatus that facilitates automatic high-sensitivity detection of anomalies in a signal.
2. Related Art
Modern server computer systems are typically equipped with a significant number of sensors which monitor signals during the operation of the computer systems. Results from this monitoring process can be used to generate time series data for these signals which can subsequently be analyzed to determine how a computer system is operating. One particularly desirable application of this time series data is for purposes of "proactive fault monitoring" to identify leading indicators of component or system failures before the failures actually occur.
Unfortunately, many of these computer systems use low-resolution eight-bit analog-to-digital (A/D) converters in their physical sensors to sample the signals. This causes readings of physical variables such as voltage, current, and temperature to be highly quantized. Hence, the sampled signal values from these sensors can only assume discrete values, and no readings can be reported between these discrete values. For example, voltages for system board components may be quantized to the nearest 10 mV; e.g. 1.60 V, 1.61 V, 1.62 V, etc. Hence, if the true voltage value is 1.6035 V, it can only be reported as one of the quantized values, 1.60 or 1.61.
Note that the above-described quantization effect presents a serious problem for proactive fault monitoring. Normally, one can apply statistical pattern recognition techniques to continuous signal values to detect if the signals start to drift away from steady-state values at a very early stage of system degradation. However, with significant quantization, conventional statistical pattern recognition techniques cannot be used effectively to detect the onset of subtle anomalies that might precede component or system failures.
To overcome this quantization problem, researchers have used a moving histogram technique to represent each quantized physical signal and also use multi-hypothesis Sequential Probability Ratio Tests (SPRTs) to detect subtle changes in the signal. The moving histogram technique when combined with the SPRT technique has demonstrated promising sensitivity and robustness, even when the variations in the physical variables are a small percentage of the quantization resolution.
Unfortunately, the conventional moving histogram techniques suffer from a serious drawback over time. Specifically, when a system is monitored for a long period of time and exhibits no signal degradation, the conventional moving histogram technique builds up "inertia" in the collected data which makes it less sensitive in detecting the onset of subtle degradation. In other words, the sensitivity, as well as the robustness of the fault detection, decreases as the monitoring time increases.
What is needed is a method and an apparatus for facilitating high-sensitivity detection of anomalies in a signal without the above-described problems.

High-sensitivity detection of an anomaly in a quantized signal


The invention relates to a cable housing (1) for receiving optical fibers and fibers (28b) of a fiber optic cable (28a), comprising at least one locking element (15a, 15b) and at least one passage (16a, 16b) for the fibers (28b), wherein the locking element (15a, 15b) can be moved into at least one open and one closed state, wherein the fibers (28b) are held in the passage (16a, 16b) in the closed state, and a method for receiving optical fibers and fibers (28b) of a fiber optic cable (28a) in a cable housing (1), comprising the following process steps: a) disposing the locking element or elements (15a, 15b) in the open state; b) winding the fibers (28b) about the passage (16a, 16b); and c) disposing the locking element or elements (15a, 15b) in the closed state.

The present invention relates to a cable housing and to a method for holding optical fibers or fibers of an optical fiber cable.
The process of binding together two ends of optical fibers is known as splicing, resulting in a "splice" being created between the two fibers. Splices are particularly susceptible to damage from shock, stress, dynamic loading and the like. Modern optical fiber networks can contain cables comprising hundreds of optical fibers and a correspondingly large number of individual splices each of which needs to be protected against the aforementioned mechanical disturbances.
Housings such as splice trays, for the containment of optical fibers and cables, particularly in the vicinity of splices, for their protection against undesirable mechanical disturbances, are known. However, handling difficulties arise during the placement of new cables into such housings with cables already placed therein. Further, devices used to retain cables within the housings tend to be obtrusive when placing cables onto the tray.

Cable housing and method for receiving optical fibers and fibers of a fiber optic cable


A pill crusher is provided, which comprises a base, a stopper, an U-shaped movable pressing plate, a connecting rod and a handle, wherein the stopper is mounted on the base; the U-shaped movable pressing plate is sleeved on the outside of the stopper and comprises a pressing plate on one side of the stopper and two side walls connected with the pressing plate and pivotedly connected to the stopper, so that the U-shaped movable pressing plate can rotate relative to the stopper and a V-shaped crushing chamber formed between the pressing plate and the stopper is capable of being closed by pressing and being open; the connecting rod is positioned on the other side of the stopper and has a first end pivotedly connected with the stopper and a second end; the handle has a first end pivotedly connected with the second end of the connecting rod through a third shaft pin and a pivoting portion pivotedly connected with the two side walls; as the handle is pressed down, the angle between the connecting rod and the handle increases and the space of the V-shaped crushing chamber decreases gradually; and as the handle is raised up, the angle between the connecting rod and the handle reduces and the space of the V-shaped crushing chamber increases gradually. The pill crusher provided by the present invention has the advantages of labor saving, high efficiency, quietness, convenient maintenance and cleaning and the like.

Most oral drugs are taken by the patients in the form of pills with different shapes and sizes. The pills are produced into preparations in disc or anomalous shape by special forming process after uniform mixing of drugs and adjuvant materials, which are widely applied in the modern pharmaceutical industry, for having the advantages of accurate dosage, stable quality, convenient to carry and transport, and the like. In accordance with the requirements in various aspects such as treatment, the dosage of a single pill and the proportion of raw materials to adjuvant materials, different drugs have different requirements on the shape, the size or other characteristics of the pills. For instance, vitamin pills, calcium pills and the like are usually larger, which are inconvenient for ordinary people to take one or more once, particularly for those special patents, such as the aged, children, postoperative patients, dysphagia patients or coma patients, who have difficulty in directly taking the pills, and thereby limiting the use of oral drugs and even affecting the treatment of patients.
Therefore, a device capable of crushing appropriate pills into pieces or powder (i.e. pill crusher) is required, in order to assist the patients who need but cannot normally take standard preparations to take medicine for deserved treatment. The pill crusher should be safe, high efficient, low cost, quiet, labor-saving and easy to use and can avoid the cross-contamination of drugs. However, the traditional pill crushers, e.g., "pot for pounding drugs", generally employ the means of simple shock and grinding or employ a single lever to realize the action of crushing pills, which have the defect of low efficiency, loud noise, labor-consuming, quantity loss or the cross-contamination of pills and the like in the crushing process, and hence cannot fully meet the requirements of crushing the pills safely and efficiently. In particular, when pill crushers are used by medical personnel at medical institutions, their characteristics such as the crushing speed, efficiency, quietness, exogenous contamination/cross-contamination avoidance, labor-saving level and the like are especially important.
For instance, U.S. Pat. No. 7,413,137, with the inventor of James A. Donovan, filed on Sep. 21, 2006, provides a device, in which the bent-lever principle is utilized to convert the rotation of a handle into the parallel movement of a platen and further drive the platen to press towards a fixed plate to crush the pills between them and realize the objective of pill crushing, while the platen and the fixed plate are set on a same base. However, as the structure of this device is too complex, it has a lot of friction and relatively loud noise during its using process and make the crushing process inconvenient and high costly, this device cannot fully meet the users' needs. Moreover, for instance, the U.S. Pat. No. 3,915,393, with the inventor of Bill Webb Elkins, filed on Apr. 24, 1974, provides a device which simply utilizes the single-lever principle to convert the rotation of a handle into the downward pressing action so as to crush pills. But this single-lever structure, which cannot effectively provide the magnification factor of force, is labor-consuming, and particularly it is inconvenient to repeatedly crush lots of pills for a plurality of times when used in medical institutions. Furthermore, for instance, the U.S. Pat. No. Des. 337,828, with the inventor of David W. Gordon, filed on Dec. 12, 1990, provides a simple and portable pill crusher, which employs the principle of threaded rotation to convert rotation into linear motion to realize the action of crushing pills. Although this structure is labor-consuming, it is simple, convenient for crushing, and particularly applicable to crush a small amount of pills by family or individual. However, the structure cannot meet the requirement of medical institutions for crushing a large amount of pills.


A cooling structure for electrical circuit devices having a pair of cooling ducts, each having a coolant passageway therein, and an electrical circuit device housing formed by a pair of spaced apart heat transfer plates each joined to a housing side to provide a sealed housing space. An electrical circuit device is positioned in that sealed housing space and each of the pair of heat transfer plates is positioned adjacent to, and thermally coupled to, a corresponding one of the pair of cooling ducts. An electrically insulative heat transfer material is provided in the sealed housing space so as to be capable of being in contact with the electrical circuit device also therein.

The present invention relates to removing excess heat from electronic circuit housings and, more particularly, to the removal of such heat through use of heat transporting coolants.
The operation of electronic circuits inevitably involves the dissipation of electrical energy into heat in the electronic and passive circuit device structures used in forming such circuits. These circuits are typically provided for use by being housed in some kind of housing arrangement. In those situations in which the generated heat is sufficiently removed simply through convection or conduction to the surrounding atmosphere, or both, to thereby avoid raising temperatures to values that could lead to failures in the circuits or the housings in which they are positioned, nothing more is needed for cooling such circuit housing arrangements.
However, some kinds of electronic circuits are used to control relatively large amounts of electrical power and are often provided in large power dissipation electronic module assemblies. Correspondingly, such circuits dissipate relatively large amounts of electrical power in the controlling of these much larger amounts of electrical power, and so result in the generation of too much heat in the housing arrangements for removal by just atmospheric based convection and conduction means. In these situations, further housing cooling provisions must be made to avoid temperatures in those housings being raised to values that lead to failures in the circuits or their housings. A typical such further provision is a duct, in which a coolant can be caused to flow to form a heat exchanger, and this duct is thermally coupled to one side of the electronic circuit housing being cooled thereby.
Such a duct provision for circuit housings, while an improvement over relying on just atmospheric based conduction and convection, is only a limited improvement for circuit housings in which the supported circuits generate sufficiently large amounts of heat primarily because of the thermal resistivity encountered over the transport paths. That is, although the cooling duct removes heat well from the circuit and housing portions relatively close thereto, heat that must be transported thereto from more remote portions thereof, usually mostly by conduction, is limited often by the relatively small thermal conductivities of the materials present along those transport paths. Those thermal conductivities can be improved by use of alternative materials along the transport paths or by adding more parallel paths through broadening the heat sources such as by using heat generating components having larger sizes or lateral extents, or by enlarging the housing to have more area abutting the cooling duct. Such remedies, however, either substantially add to the cost or the weight of the circuit housings, or both. Thus, there is a desire for better arrangements to sufficiently remove excessive heat generated in housed circuit devices during their operation.


Provided is a field effect transistor (FET) type biosensor including a source electrode, a gate, and a drain electrode. A ligand that can bind to a side of a nucleic acid is added to the surface of the gate. In a conventional FET type biosensor, it is difficult to detect a signal within the debye length because a target nucleic acid is directly fixed to the surface of a gate of the conventional FET. However, in the present invention, this problem can be overcome and the debye length can be increased by treating the surface of a gate of an FET sensor with a ligand that can bind to a side of a nucleic acid. The ligand can be adsorbed onto the surface of the gate. In this case, the nucleic acid is adsorbed parallel to the surface of the gate, not perpendicular to the surface of the gate, thus generating an effective depletion region. In addition, hybridization efficiency can be increased because a hybridized sample can be injected into an FET sensor at high ionic strength.

1. Field of the Invention
The present invention relates to a field effect transistor (FET)-type biosensor including a source electrode, a gate electrode, and a drain electrode, and more particularly, to an FET type biosensor in which the surface of a gate is modified to increase sensitivity.
2. Description of the Related Art
As human DNA sequences become known through the completion of the genome project, research into the functions of genes and proteins encoded from genes are being more actively conducted. In response to this active research, the need for development of biosensors that can easily detect biomaterials has increased.
Biosensors that can detect biomaterials using an electric signal are disclosed in U.S. Pat. Nos. 4,238,757; 4,777,019; 5,431,883; 5,827,482; and the like. In particular, U.S. Pat. No. 4,238,757 discloses a field effect transistor (FET) including a source and a drain which is designed to have an antigen reacting to a specific antibody. In this case, the change in the concentration of the antigen in a solution with respect to a drain current was observed over time using the FET.
An FET disclosed in U.S. Pat. No. 4,777,019 includes a gate formed on the doped source and drain regions, and a complementary nucleotide with a nucleotide to be measured is affixed to the gate.
An FET disclosed in U.S. Pat. No. 5,431,883 includes a phthalocayanin thin layer connecting a gate to a drain. Phthalocyanin is an organic insulating material that can be transformed into a conductive material by reacting a chemical sample.
U.S. Pat. No. 5,827,482 discloses a biosensor which includes two FETs which includes molecular receptors bound to gates. The two FETs are arranged in a row to increase sensitivity to different bindings.
FIG. 1 is a schematic diagram of a conventional FET. Referring to FIG. 1, a target oligonucleotide is affixed to the surface of a gate of the FET. FIG. 2 illustrates an increase in the charge accumulation due to binding between an oligonucleotide and a desired complememtary DNA wherein the oligonucleotide is affixed to the surface of the gate of the FET shown in FIG. 1. FIGS. 3A and 3B illustrate the effects of variations in debye length in ImmounoFET. As the size of a molecule affixed to the surface of the gate increases, it is difficult to detect a signal within debye length. Referring to FIG. 3B, when the ionic strength is high, debye length (dAb) is small, and thereby, a signal resulting from a reaction between Ag and Ab is difficult to detect, but when the ionic strength is low, debye Length (dAb) is large, and thus, the signal resulting from the reaction between Ag and Ab can be detected.
Conventional techniques are based on the structure in which an oligonucleotide is affixed to the surface of the FET gate, and such a structure is often used in conventional microarrays. Although the structure does not cause any problems in the microarray, it does in an FET sensor. That is, in the FET sensor, a depletion region is generated from hybridization occurring in the surface of the gate and only charges within the debye length can derive the formation of the depletion region. In order to obtain an effective depletion region, DNA can be arranged parallel to the surface of the gate so that the contact area between DNA and the gate is increased. The parallel structure provides better results when DNA is arranged perpendicular to the surface of the gate. However, surface fixation methods often used in microarrays are used in conventional FET sensors, and thus, an effective depletion region is difficult to obtain. In addition, the fixation of the target oligonucleotide to the surface of the gate results in many disadvantages. For example, when a probe is fixed on the surface of the gate, a long time is required to fix the probe and to perform hybridization in a solution. Typically, DNA hybridization occurs in a solution, but in FET sensors a buffer solution with low ionic strength is used to hybridize DNA to maximize the debye length. The buffer solution with low ionic strength may be preferred for sensors, but results in decreased DNA hybridization efficiency. That is, the hybridization occurring on the surface of the gate is decreased and low signals are generated.
When attempting to overcome these problems in conventional techniques, the inventors of the present invention have confirmed that when the surface of a gate of an FET sensor is modified, a DNA backbone is adsorbed at the surface of the gate, and signals can be effectively detected within the debye length.

FET-type biosensor with surface modification


A bus assembly includes a planar first bus, a second bus including a first planar bus section on the first bus and a second planar bus section connected to the first planar bus section and offset from the first planar bus section, and a third bus comprising a third planar bus section disposed between the first bus and the second planar bus section, and a fourth planar bus section connected to the third planar bus section, offset from third planar bus section, and disposed on the first planar bus section.

The inventive subject matter relates to electrical power apparatus and methods and, more particularly, to bus assemblies for use with semiconductor switching devices.
Power electronics apparatus, such as power converters, solid-state circuit breakers and the like, may employ power transistors or other power semiconductor switching devices. Development of semiconductor technology has led to power semiconductor switching devices having dramatically increased voltage and switching frequency capabilities. For example, silicon carbide (SiC) transistors (e.g., SiC MOSFETs) have been developed capable of operating at frequencies that are multiples of operating frequencies of corresponding conventional silicon-based power devices (e.g., silicon IGBTs).
With the advent of such devices, impedance effects associated with conductive buses and other circuit components used with these devices have increased in significance. In particular, inductance and capacitance associated with such components may degrade system performance by introducing oscillation and other negative effects.

Low-impedance bus assemblies and apparatus including the same


A system and method are provided for controlling a wind turbine to protect the wind turbine from anomalous operations. Accordingly, in response to receiving data indicative of an anomalous operational event of the wind turbine, the controller initiates an enhanced braking mode for the wind turbine. The enhanced braking mode is characterized by operating the generator at a torque setpoint that generates maximum available torque for a given set of operating conditions. Additionally, the torque setpoint is in excess of a nominal torque limit for the generator.

Wind power is considered one of the cleanest, most environmentally friendly energy sources presently available, and wind turbines have gained increased attention in this regard. A modern wind turbine typically includes a tower, a generator, a gearbox, a nacelle, and one or more rotor blades. The nacelle includes a rotor assembly coupled to the gearbox and to the generator. The rotor assembly and the gearbox are mounted on a bedplate support frame located within the nacelle. The one or more rotor blades capture kinetic energy of wind using known airfoil principles. The rotor blades transmit the kinetic energy in the form of rotational energy so as to turn a shaft coupling the rotor blades to a gearbox, or if a gearbox is not used, directly to the generator. The generator then converts the mechanical energy to electrical energy and the electrical energy may be transmitted to a converter and/or a transformer housed within the tower and subsequently deployed to a utility grid. Modern wind power generation systems typically take the form of a wind farm having multiple such wind turbine generators that are operable to supply power to a transmission system providing power to an electrical grid.
In certain instances, the wind turbine may experience an anomalous operational event, such as an overspeed condition, a portion of a rotor blade (or the rotor blade in its entirety) separating from the wind turbine, and/or other significant deviation from the normal operating state of the wind turbine. Such events may cause significant damage to the wind turbine.
The damage resulting from the anomalous operational event may increase with continued operation of the wind turbine. For existing wind turbines, the controller typically decelerates the rotor using components of the wind turbine operating within nominal design limits. The nominal design limits may typically be established at levels which permits the operation of the components of the wind turbine in all conditions without affecting a nominal life expectancy of the components. However, the rate of deceleration achievable while operating under the nominal design limits may be inadequate to prevent or mitigate damage to the wind turbine resulting from the anomalous operational event. Accordingly, it may, in response to an anomalous operational event, be desirable in certain instances to decelerate the rotor in an expedited manner not achievable under the nominal design limits.
Thus, the art is continuously seeking new and improved systems and methods that address the aforementioned issues. As such, the present disclosure is directed to systems and methods for controlling a wind turbine to protect the wind turbine from anomalous operations.

System and method for controlling a wind turbine to protect the wind turbine from anomalous operations


A feature centric method of and system for monitoring the development and release process of a product, monitoring the development and release of a product, where the product is characterized by having a plurality of features is described. The method steps, which the system is configured to carry out, include enumerating features to be included in the product, enumerating tasks, task milestones, and task milestone completions identified to the features; enumerating required task approvals and feature approvals and completed task approvals and feature approvals, and enumerating required associated activities and completed associated activities. The enumeration preferably includes information to show linkages, associations, priorities, milestones, and missed milestones.

In order to accomplish a project, such as a new product introduction, it is necessary to effectively plan, schedule, and monitor progress on many sub-elements. This is the Release Management process. As shown in FIG. 1, Release Management typically consists of four main stages:
Stage 1: Product marketing defines product features and develops requirements for the product features. The requirements may take the form of requirements documents.
Stage 2: Engineering enumerates tasks to implement the features, sets milestones for the tasks, and completes the tasks to implement the features.
Stage 3: Quality assurance (QA) verifies the engineering designs and the engineering implementations, and tests the features in the product as it is developed.
Stage 4: Other ancillary steps must be completed, for example, the technical publications group documents the features for the end user, the training group may have to develop training programs, there may be business clearances, such as business practices, training, legal, insurance, environmental, marketing, and executive approvals.
Understandably, the product release process involves a lot of information flowing within and between organizations to ensure a quality product is built on time to the right requirements and with proper documentation. Prior project management methods and paradigms having typically emphasized the linearity and linear dependence aspects of Release Management. FIG. 1 illustrates the apparent linearity of Release Management. Without an integrated system providing overall visibility to help track and communicate task level and sub-task level information, organizations must get by with disconnected systems such as makeshift spreadsheets, white boards, memos, and slips of paper. Often, information is lost or miscommunicated, resulting in a misallocation of resources; missing, undocumented, or inadequately tested features; late product shipments; and, ultimately, dissatisfied customers. And the problem only becomes worse as companies grow and product releases become more frequent and more feature-rich.
Organizations sometimes hire a Release Manager to coordinate the information flow, track release status, and guide important release-related decision making.

Feature centric release manager method and system


The invention relates to methods for the chemical application of coatings by the decay of gaseous compounds, in particular to methods for injecting gases into a reaction chamber. The invention also relates to means for feeding gases into a reaction chamber, said means providing for the regulation of streams of reactive gases, and ensures the possibility of obtaining multi-layer epitaxial structures having set parameters and based on nitrides of group III metals while simultaneously increasing the productivity and cost-effectiveness of the process of the epitaxial growth thereof. Before being fed into a reactor, all of the gas streams are sent to a mixing chamber connected to the reactor, and are then fed into the reactor via a flux former under laminar flow conditions. The mixing chamber and the flux former are equipped with means for maintaining a set temperature. As a result of these solutions, a gaseous mixture with set parameters is fed into the reactor, and the formation of vortices is simultaneously prevented. The maximum allowable volume of the mixing chamber is chosen to take into account the process parameters and the required rarity of heterojunctions.

To grow epitaxial structures based on group III nitrides, ammonia and metalorganic compounds in the carrier gas flow are supplied to a reactor. Reactive gases that form group III nitrides are metalorganic compounds and ammonia.
A method for supplying gases into a reactor to grow III nitride epitaxial structures on crystalline substrates is known (U.S. Pat. No. 6,972,050 "Method for depositing in particular crystalline layers, and device for carrying out the method", filled May 15, 2003, date of patent Dec. 6, 2005); the method comprising supplying into the reactor two reactive gases, each of which is mixed with a carrier gas. In the known method, a separate inlet is designed to supply each mixture with a reactive gas to a reactor, and these inlets are placed one above another between the bottom and the lid of the reactor; the inlets cross-sections are different. Group V hydrides are used as a reactive gas injected through inlet that is closer to a reactor bottom, while group III metalorganic compounds are used as a reactive gas injected through inlet closer to a reactor lid; nitrogen, hydrogen and their mixtures are used as carrier gases.
In the known method the conditions for supplying a reactive gas through the inlet closer to a reactor lid are chosen such that a gas is pyrolytically decomposed in the input zone prior reaching substrates, and the decomposition products diffuse to substrates perpendicular to the flow injected through inlet closer to a reactor bottom, where substrates are placed, and react with the products of pyrolysis of gas, which is injected through inlet closer to a reactor bottom; as a result, a crystalline layer is formed.
The necessary condition for carrying out the known method is an adjustment of kinematic viscosity of a carrier gas injected through inlet closer to a reactor lid by means of mixing two gases with different kinematic viscosities to provide the necessary ratio of Reynolds numbers for gas flows passing through insulated inlets.
The known method allows one to grow semiconductor structures—group III arsenides and phosphides. However, for the growth of multilayered epitaxial structures based on group III nitrides a use of the known method has substantial drawbacks. In particular, a wide range of ratios of reactive to carrier gases, which is necessary for a growth of different group III nitrides in the composition of multilayer epitaxial structures, does not make it possible to provide the necessary ratio of Reynolds numbers for gas flows passing through insulated inlets. Failure of this relationship leads to the occurrence of vortex flows in a reactor, which reduce the quality of grown structures, their in-plane uniformity, and negatively affects the process reproducibility. Moreover, the necessity of choosing the kinematic viscosity of a carrier gas by means of mixing two gases, the kinematic viscosities of which are substantially different, reduces the process profitability. In particular, during the growth of GaN, AlN, and AlGaN hydrogen, i.e., the lightest possible carrier gas that provide the highest diffusion coefficient of products of metalorganic compound pyrolysis, should be mixed with a gas with higher molecular mass (e.g., nitrogen). This leads to a decrease of the diffusion coefficient of products of metalorganic compound pyrolysis, which reduces the efficiency of their diffusion transport to a substrate, decreases a growth rate, and, thus, reduces the processing profitability. During the growth of InGaN layers hydrogen should not be supplied into a rector. This means that it is necessary to use expensive helium for adjusting the kinematic viscosity of a carrier gas, which also reduces the profitability of a process.
Moreover, during the growing III nitride epitaxial structures, a growth rate of epitaxial layers and, hence, the efficiency of equipment, is limited by the parasitic reactions between metalorganic compounds and ammonia in the gas phase. The known method does not allow one to prevent them Ammonia is characterized by higher diffusion coefficient than metalorganic compound vapors. Therefore, ammonia diffusion from the region of its injection into a reactor to the region of metalorganic compound injection into a reactor occurs more rapidly than the diffusion of metalorganic compounds in the opposite direction towards the region near substrates. As a result, a zone with increased concentration of mixture of metalorganic compounds with ammonia is formed in a reactor, which increases the intensity of these parasitic reactions which leads to the growth rate decrease. The effect of parasitic reactions on the growth can be effectively suppressed if the residence time of the gas mixture in a hot reactor zone is substantially decreased by a substantial increase in the gas flows injected into a reactor. However, in this case in the known method the following undesired processes occur:                firstly, at a high velocity of a gas the first condition of the known method is broken: it is no enough time to pyrolytically decompose metalorganic compounds in the inlet zone of a reactor;        secondly, at a high velocity of a gas flows through a reactor it is no time for the products of pyrolytic decomposition of metalorganic compounds to diffuse through a gas layer nearby to substrates, which mainly consists of the mixture of a carrier gas and ammonia; this decreases the growth rate in comparison with theoretically achievable value and leads to a substantial decrease in the efficiency of using expensive metalorganic compounds, a greater part of products of pyrolytic decomposition of which leaves a reactor unused. The considered undesired processes substantially reduce the profitability of the known method and equipment for using it.
An increase in the profitability of the epitaxial structure growth can be achieved by the use of the deposition method that comprises supplying metalorganic compound vapors in a reactor in the mixture with a carrier gas through inlet located near a reactor bottom, where substrates are placed. (US2007031991 Application «Method for depositing compounds on a substrate by means of metalorganic chemical vapor deposition», filled Feb. 20, 2004, published Feb. 8, 2007). As well as in the aforesaid method, the necessary ratio of Reynolds numbers for gas flows passing through insulated inlets cannot be provided, which is accompanied by the occurrence of vortex flows. The known method makes it possible to suppress the rapid formation of polycrystalline deposits on a reactor ceiling; however, the polycrystalline deposits are formed with a high rate on a reactor bottom in front of the substrates, which is also unwanted.
The method for supplying gases into a reactor to grow III nitride epitaxial structures, comprising injection of at least two reactive gases in a reactor and at least one of the gases is mixed with a carrier gas, is known (U.S. Pat. No. 8,980,000 «Density-matching alkyl push flow for vertical flow rotating disk reactors», filled Oct. 6, 2006, date of patent Mar. 17, 2015).
To grow III nitride epitaxial structures, the known method provides injection of vapors of different reactive gases that contain III group metals mixed with different carrier gases into a reactor through different inlets. In this case, the method requires that at least one of the carrier gases is obtained by means of mixing two gases with different densities. The method also requires a choice of the parameters of gas mixtures supplied into a reactor through different inlets by means of such control over flowrates of gas mixtures and composition of a carrier gas that their linear velocities and densities at the reactor entrance are equal, which allows one to avoid the formation of vortexes in a reactor and obtain high uniformity of the parameters of a deposition process.
However, to obtain multilayered epitaxial structures with given characteristics as well as in the known method considered above, there appears the necessity to use gases with wide spread of parameters in wide ranges of their quantitative ratios. As well as in the aforesaid method, for a growth of InGaN layers expensive helium should be used, while for a growth of GaN, AlN, and AlGaN to meet the method requirements with respect to the simultaneous equality of rates and densities, nitrogen or noble gas with high molecular mass should be used as a carrier gas, which reduces the efficiency of diffusion of metalorganic compound pyrolysis products to the substrates through a depleted layer and leads to a decrease in the growth rate and efficiency of using expensive metalorganic materials.
Moreover, in the known method the regions with an increased concentration of metalorganic compounds are formed in a reactor and ammonia diffusive penetration in these regions promotes the acceleration of parasitic reactions in the gas phase. To obtain multilayered epitaxial structures with given characteristics, different flows of reactive gases and strict fulfillment of the processing conditions are required to obtain different layers. The vortex flows that negatively affect the parameters of the growing layer are formed even at slight deviations from the given parameters.
A device for supplying gases in a reactor to grow III nitride epitaxial structures is known (U.S. Pat. No. 6,972,050 «Method for depositing in particular crystalline layers, and device for carrying out the method», filled May 15, 2003, date of patent Dec. 6, 2005). The device has two inlets for injection of reactive gases into a reactor. The inlets are placed one above another between the bottom and lid of a reactor and have different cross-sections. To adjust a ratio of the cross-sections of inlets, the replaceable elements or mechanical system to change a ratio of inlet cross-sections can be designed in the device. However, in both cases it is impossible to guarantee the range of process conditions, which is necessary to obtain multilayered epitaxial structures with target characteristics, due to the insufficiently flexible and operative adjustment and impossible simultaneous fulfillment of all the given processing conditions, which is associated with that a design of the device provides the pyrolysis of metalorganic compounds prior reaching a substrate. Moreover, the presence of movable elements in the gas supply system in a reactor affects negatively the reproducibility of an epitaxial growth process because of the inevitable errors that occur during the replacement and complicates the system of gas injection into a reactor.
The device for supplying gases in a reactor to grow III nitride epitaxial structures, which contains at least two inlets for supplying reactive gases and system of gas injection into a reactor, is also known (U.S. Pat. No. 8,980,000 «Density-matching alkyl push flow for vertical flow rotating disk reactors», filled Oct. 6, 2006, date of patent Mar. 17, 2015).
In the known device the system of gas injection into a reactor contains a great number of inlets. At minimum three mass flow controllers are connected to each inlet for supplying a reactive gas: for injection of two different carrier gases with different densities and reactive gas itself. Each mass flow controller has a control error; the higher is the number of these controllers used in the device, the higher is the total error, which can increase during continuous changing parameters of the injected gas flows needed to obtain multilayered epitaxial structures, and the given structural characteristics cannot be provided.
The analysis of the considered methods and devices that effect on the characteristics of multilayered epitaxial structures based on group III nitrides has shown that the reason of these drawbacks is a separate injection of group III metalorganic compound vapors and ammonia and the necessity of complex controlling the parameters of gas flows injected into a reactor, which is accompanied by the unwanted processes, complicates the equipment, and cannot provide flexible and operative control over the process parameters.

Method of feeding gases into a reactor to grow epitaxial structures based on group III nitride metals and a device for carrying out said method


An electronic component, a leadframe, and a method for producing an electronic component are disclosed. In an embodiment, the electronic component includes a housing and a leadframe section partly embedded in the housing, wherein the leadframe section includes a first quadrant, a second quadrant, a third quadrant and a fourth quadrant, wherein each of the quadrants has a first leadframe part and a second leadframe part, wherein each first leadframe part includes a chip landing area, wherein the chip landing areas of all four quadrants are arranged adjacently to a common central region of the leadframe section, and wherein the four quadrants are configured symmetrically with respect to one another.

Electronic components comprising a housing with an embedded leadframe are known from the prior art. In particular, corresponding optoelectronic components are known, for example, light emitting diode components. In the case of such electronic components, the leadframe embedded into the housing serves for electrically contacting an electronic semiconductor chip of the electronic component, and for dissipating waste heat produced in the electronic semiconductor chip during the operation of the electronic component. Electronic components comprising more than one electronic semiconductor chip are also known.

Electronic component, leadframe, and method for producing an electronic component


The ceramic plasma reactor includes: a plurality of unit electrodes each of which comprises a plate-shaped ceramic dielectric body 4 and a conductive film 3 embedded in the ceramic dielectric body superimposing them each other with a gap which works as a discharge portion 11, and preferably being formed by sandwiching one unit electrode 2b having no through holes 15 by two unit electrodes having plural through holes 2a there between. A partition wall plate 9 is provided by facing one of unit electrodes on a side opposite to the gap and being held by a holding member 7 at a predetermined distance so as to form there between a gas introducing-circulating portion 21 for introducing and circulating gas in the through-holes 15 so as to send gas introduced to the gap between the unit electrodes as a discharge portion by applying a voltage thereto to generate plasma.

The present invention relates to a ceramic plasma reactor for generating a plasma by introducing gas between two unit electrodes and a plasma reaction apparatus.
There has been known the fact that silent discharge is caused by applying alternating high voltage or periodic pulse voltage with a dielectric body being disposed between two electrodes to form active species, radicals, and ions in a plasma field formed by the silent discharge, thereby accelerating reaction and decomposition of gas, and that this can be used for removal of harmful components contained in engine exhaust gas or various kinds of incinerator gas.
Since a coaxial cylindrical reactor shown in JP-A-2005-222779 has different electric fields between the central portion and the outer peripheral portion though it has a simple structure, it causes a difference in plasma treatment efficiency, and a large capacity is required in the case of quickly treating a large amount of gas such as automobile exhaust gas purification or fuel reforming.
Since a parallel flat plate type reactor shown in WO2005/1250 pamphlet can give a uniform electric field in a large space, a uniform plasma field can easily be formed by combining with a power source having a small pulse width, and gas can be reformed efficiently by a small reactor by superimposing each other electrodes to have multistages. However, in a gas circulation direction, an efficient gas reaction proceeds in the front portion since much untreated gas is present, but an untreated gas decreases as the gas flows and there arises a problem of inefficient reaction caused in the back portion with respect to the input energy.
In a semiconductor process, a parallel flat plate type reactor is used. JP-A-2004-296553 discloses a structure where through-holes are aligned in the upper electrode, and reaction gas is allowed to flow perpendicularly to the flat plate electrode, thereby supplying untreated gas in all the portions. However, it was difficult to downsizing the apparatus for vehicle installation though the disclosed technique can be applied to a semiconductor-manufacturing process apparatus capable of surrounding the reactor by a large chamber.
WO2004/114728 pamphlet discloses an electrode where a conductor having a through-hole is embedded therein. Since discharge is not caused in the through-hole portion of the conductive film, the gas passing through this portion does not have a plasma reaction. Therefore, the reaction efficiency on the back side can be made higher than in the case where the entire face discharges. However, high efficiency cannot be obtained sufficiently.
Therefore, there has been required a plasma reactor having a parallel flat plate type electrode structure, capable of effectively utilizing a plasma even at the back of the discharge portion with respect to the gas flow, and having high energy efficiency. The present invention aims to provide a small-sized ceramic plasma reactor capable of efficiently treating gas by generating plasma with introducing the gas between the unit electrodes and to provide a plasma reaction apparatus.

Ceramic plasma reactor and reaction apparatus


In an organic positive temperature coefficient thermistor first and second power supplying portions are arranged spaced apart from each other by a predetermined distance on a sheet made of a material exhibiting a positive temperature characteristic of resistance. A respective plurality of branch-shaped electrodes is connected to each of the first and second power supplying portions. The plurality of branch-shaped electrodes connected to each of the power supplying portions is arranged so as to extend toward the side of the other power supplying portion. The branch-shaped electrodes connected to each of the power supplying portions are arranged so as to be interdigitated with the branch-shaped electrodes connected to the other power supplying portion. The organic positive temperature coefficient thermistor is characterized in that at least one of the first and second power supplying portions is constituted by a plurality of power supplying electrodes which are insulated from each other. A plurality of branch-shaped electrodes is connected to each of the plurality of power supplying electrodes, and they are distributed along the power supplying electrodes with a predetermined spacing and with a predetermined ratio between the respective members of branch-shaped electrodes on each of the power supplying electrodes.

1. Field of the Invention
The present invention relates generally to organic positive temperature coefficient (PTC) thermistors used as face-like heating devices, and more particularly, to an organic positive temperature coefficient thermistor having an improvement in the structure of the electrodes that are formed on a sheet exhibiting a positive temperature characteristic of resistance.
2. Description of the Prior Art
For example, a material obtained by throughly mixing polyolefin such as polyethylene with conductive particles such as metal powder, carbon black or graphite exhibits a positive temperature characteristic of resistance. An organic positive temperature coefficient thermistor using a sheet made of this material can be used as a flexible face-like heating device.
In the above described organic positive temperature coefficient thermistor, the following electrode structure is formed on one surface of the sheet exhibiting a positive temperature characteristic of resistance. More specifically, this electrode structure has a pair of power supplying portions arranged opposed to each other and separated by a predetermined distance, and a plurality of branch-shaped electrodes electrically connected to the power supplying portions, respectively, and arranged so as to be inserted between each other (interdigitated) between the power supplying portions.
A face-like heating device utilizing this organic positive temperature coefficient thermistor can be kept at a constant temperature and can automatically control the heat generating temperature under abnormal conditions because it has a self-temperature control function. Consequently, it is superior in safety to a face-like heating device using a nichrome wire and a metal foil.
However, the organic positive temperature coefficient thermistor has the disadvantage in that it is very difficult to switch the temperature, that is, to change its output temperature because it has the above described self-temperature control function.
In the conventional organic positive temperature coefficient thermistor, the output is switched in the following manner. More specifically, a plurality of electrode structures as described above are formed on the sheet exhibiting a positive temperature characteristic of resistance, to construct a plurality of separate heat generating circuits. The electrical connections to the plurality of heat generating circuits can then be switched. That is, the heat generating circuits which are placed in the on state can be selected, so that the area in which heat is generated can be reduced to, for example, one-half or one-third of the area in a case where all the heat generating circuits are caused to generate heat.
In the above described structure, however, heat is generated on only part of the surface of the sheet exhibiting a positive temperature characteristic of resistance, that is, the portion where heat is generated and the portion where heat is not generated are completely divided. Accordingly, heat cannot be uniformly generated in the entire region where heat is desired to be generated.

Organic positive temperature coefficient thermistor


A pixel of an image sensor includes a well below a gate and containing a dopant at a first concentration, a shallow trench isolation (STI) configured to electrically isolate the well, and a channel stop adjacent to at least one border between the well and the STI and containing a dopant at a second concentration higher than the first concentration.

Embodiments of the inventive concept are drawn to an image sensor and to a pixel of the image sensor. More particularly, embodiments of the inventive concept are drawn to complementary metal oxide semiconductor (CMOS) images sensors and pixels of CMOS image sensors.
Digital images may be produced using complementary metal oxide semiconductor (CMOS) image sensors or charge coupled device (CCD) image sensors. Complementary metal oxide semiconductor (CMOS) image sensors are solid state image sensing devices that use a combination of p-type and n-type metal oxide semiconductor field effect transistors. Charge coupled device (CCD) image sensors include a high-voltage analog circuit. CMOS image sensors have lower manufacturing costs and are smaller than CCD image sensors and thus are advantageous in terms of power consumption, i.e., consume less power in general than CCD images sensors. In addition, CMOS image sensors offer far greater performance than they did during their early stages of development. Therefore, CMOS image sensors are the preferred choice for use in various electronic products that produce digital images including portable devices such as smart phones and digital cameras.
A pixel array of a CMOS image sensor includes a photoelectric conversion element in each pixel. The photoelectric conversion element generates an electrical signal varying with the quantity of incident light and the CMOS image sensor processes electrical signals to synthesize an image. There is on ongoing demand for electronic products that are more compact and yet which can produce high-resolution images. To meet this demand, the pixels of a CMOS image sensor must be miniaturized.
A trench isolation process, namely, a process which includes the forming of a trench in a substrate, is usually used to isolate elements in a miniaturized pixel. However, a pixel formed using a typical trench isolation process may allow for various types of noise to be produced, due to characteristics imparted to the pixel as a result of the trench isolation process.

Image sensor and pixel of the image sensor


This application provides a communication method and a communications apparatus. The communication method includes: receiving, from a second network device, a first message indicating one or both of a first data volume of first data sent from a core network device to the second network device and from the second network device to a terminal and a second data volume of second data sent from the terminal to the second network device and from the second network device to the core network device, wherein the first data and the second data are data of a bearer, data of a flow, or data of a session, and wherein the first network device is a master node and the second network device is a secondary node both connecting to the terminal; sending, to the core network device, a second message indicating one or both of the first data volume and the second data volume.

To improve a data transmission throughput, dual connectivity supporting different access technologies, for example, multi-RAT dual connectivity (Multi-RAT Dual Connectivity, MR-DC) and long term evolution (long term evolution, LTE)-wireless local area network (wireless local area network, WLAN) interworking (LTE-WLAN interworking, LWI), is introduced.
FIG. 1 is a schematic diagram of a network with dual connectivity. As shown in FIG. 1, a terminal 01 may communicate with both a master node A and a secondary node B. The master node A and the secondary node B are connected to a core network C. Access technologies used for the master node A and the secondary node B may be the same or different. For example, the master node A is an evolved node (evolved universal terrestrial radio access network NodeB, eNB), and the secondary node B is a new radio node (new radio nodeB, gNB); or the master node A is a gNB, and the secondary node B is an eNB; or the master node A is an eNB or a gNB, and the secondary node B is a wireless local area network (wireless local area network, WLAN) device, where the WLAN device may be a WLAN termination (WLAN termination, WT), an access controller (access controller, AC), or an access point (access point, AP). The core network may be a 4G core network EPC, or a 5G core network (5G core, 5GC).
In the network in FIG. 1, a secondary bearer or a secondary split bearer may be established for the terminal 01. The secondary bearer may be referred to as a secondary cell group (Secondary Cell Group, SCG) bearer in MR-DC, and corresponds to an entire bearer that is moved to a WLAN side in LWI. The secondary split bearer may be referred to as a secondary cell group (SCG) split bearer in MR-DC.
For related content of MR-DC, refer to, for example, related content in Section 4 in 3GPP TS 37.340 V0.2.1. For related content of LWI, refer to, for example, related content in Section 22A in 3GPP TS 36.300 V14.2.0.
FIG. 2 is a schematic diagram of a secondary bearer. As shown in FIG. 2, a user plane connection between a core network C and a secondary node B is established for a terminal 01, and a user plane connection is established between the secondary node B and the terminal 01. When there is downlink data, the core network C sends all data of the bearer to the secondary node B, and then the secondary node B sends all the data of the bearer to the terminal 01. When there is uplink data, the terminal 01 sends all data of the bearer to the secondary node B, and then the secondary node B sends all the data of the bearer to the core network C.
FIG. 3 is a schematic diagram of a secondary split bearer. As shown in FIG. 3, a user plane connection between a core network C and a secondary node B is established for a terminal 01, a user plane connection is established between the secondary node B and the terminal 01, and a user plane connection is established between a master node A and the terminal 01. When there is downlink data, the core network C sends all data of the bearer to the secondary node B, the secondary node B sends a part of the data to the master node A, the master node A sends the part of the data to the terminal 01, and the secondary node B sends remaining data to the terminal 01. When there is uplink data, the terminal 01 may send a part of data of the bearer to the master node A, the master node A sends the part of the data to the secondary node B, the terminal 01 sends remaining data of the bearer to the secondary node B, and the secondary node B sends all of the received data of the bearer to the core network C. Optionally, it may be configured that the terminal 01 sends all data of the bearer to the master node A, and the master node A sends all the data of the bearer to the secondary node B; or it may be configured that the terminal 01 sends all data of the bearer to the secondary node B.
For the secondary bearer or the secondary split bearer, how to more precisely count a transmitted data volume of the bearer is a problem that urgently needs to be resolved.

Communication methods and communications apparatuses


A new and distinct cultivar of Heuchera plant named ‘IFHEHB’, characterized by its compact and uniformly mounded plant habit; relatively rapid growth rate; densely foliated and bushy appearance; silvery purple-colored leaves; long flowering period; numerous inflorescences with sterile light red purple-colored flowers; and good garden performance and winter hardiness.

The present invention relates to a new and distinct Heuchera plant, botanically known as Heuchera hybrida, typically grown as a landscape Heuchera and hereinafter referred to by the name 'IFHEHB'.
The new Heuchera plant is a product of a planned breeding program conducted by the Inventor in Andijk, The Netherlands. The objective of the breeding program is to create new compact Heuchera plants with attractive leaf and flower coloration and good garden performance.
The new Heuchera plant originated from an open-pollination of a proprietary selection of Heuchera hybrida identified as code number 083-11-K016-02, not patented, as the female, or seed, parent with an unknown proprietary selection of Heuchera hybrida as the male, or pollen, parent in June, 2013. The new Heuchera plant was discovered and selected as a single plant from within the progeny of the stated open-pollination in a controlled nursery environment in Andijk, The Netherlands in July, 2014.
Asexual reproduction of the new Heuchera plant by in vitro meristem culture in a controlled environment in Andijk, The Netherlands since September, 2016 has shown that the unique features of this new Heuchera plant are stable and reproduced true to type in successive generations.


In an overlap addition unit, speech waveform data is subjected to overlap addition every period read out from a period storage unit, and in a simple addition unit, the waveform data obtained by the overlap addition and the aperiodic waveform data read out from an aperiodic waveform storage unit are added to each other. Thus, the aperiodic waveform is given to the speech waveform to improve the quality of synthesized speech.

The present invention relates to a speech synthesizer and more particularly to a speech synthesizer which is suitable for obtaining a synthesized speech of high quality.
The basic construction of a speech synthesis system is, for example, described in detail in an article "PROCESSING OF DIGITAL SIGNAL OF SPEECH" by Rabiner (translated by Suzuki), April 1983, and in an article "DIGITAL PROCESSING OF VOICE" by Furui, The Tokai University Publishing Society, September, 1985.
In those articles, "a vocoder" is introduced as a kind of speech synthesizer. The vocoder serves to increase the information compressibility of the speech to perform the transmission and synthesis. In the vocoder, the spectrum envelop is obtained from the speech and the speech to be reconstructed is synthesized on the basis of the spectrum envelop. The various kinds of vocoders have heretofore been developed in order to improve the sound quality. In this connection, as the typical ones, there are given the channel vocoder and homomorphic vocoder.
In the systems employing those vocoders, however, since the accuracy of extracting the spectrum envelop information is insufficient, the quality of the synthesized speech is questionable. On the other hand, as a new method of extracting the spectrum envelop information, there is recently proposed a PSE (Power Spectrum Envelop) method. This method is a method wherein the Fourier power spectrum of speech is sampled with a pitch frequency. It is considered that the synthesized speech obtained by this method has a high quality, as compared with the prior art system. The details thereof can be referred to an article "POWER SPECTRUM ENVELOP (PSE) SPEECH ANALYSIS/SYNTHESIS SYSTEM" by Nakajima et al. (JOURNAL OF THE ACOUSTICAL SOCIETY OF JAPAN, Vol. 44, No. 11, 1988-11).
In the system of synthesizing speech using in the above-mentioned PSE analysis/synthesis method, in the same manner as in the homomorphic vocoder, the impulse response is subjected to the synthesized speech at intervals of pitch period. According to the above article by the Nakajima et al., the impulse response is obtained by setting the zero phase. This is based on the knowledge in which the acoustic sense characteristics of a human has the dull sensitivity to the phase. Moreover, according to the above article "PROCESSING OF DIGITAL SIGNAL OF SPEECH" by Rabiner, in addition to the zero phase, the minimum phase and the maximum phase are set to obtain the impulse response, and the qualities of individual synthesized speech are compared with one another. As a result, it is concluded that the best quality of synthesized speech can be obtained by the minimum phase method.