A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.

1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices, and more particularly, to semiconductor integrated circuit devices including a plurality of dispersedly arranged cell array blocks.
2. Description of the Related Art
FIG. 7 is a diagram showing a layout on a conventional semiconductor memory chip. An input/output buffer region 7 is formed on the peripheral portion of a semiconductor chip 1 and a chip control circuit region 8 is formed on the central portion of semiconductor chip 1. Four memory cell array blocks 9 are formed on semiconductor chip 1.
Input/output buffer region 7 includes a bonding pad for inputting an externally applied signal and outputting a signal to the outside of the chip, a buffer for input/output signals including an address signal, some of peripheral circuits and signal interconnection therebetween.
A chip control circuit region 8 includes a control circuit for controlling each circuit in chip 1 and an address signal generation circuit such as a predecoder.
Each memory cell array block 9 includes a memory cell array having a capacity one-fourth of the storage capacity of the entire chip, a decoder, a sense amplifier, an input/output latch and some of control circuits for driving these circuits.
FIG. 8 is a functional block diagram showing the detailed arrangement of the semiconductor memory of FIG. 7. Chip 1 includes bonding pads (hereinafter referred to as pads) P1-P7, an input/output buffer circuit 70, a chip control circuit 80 and four memory cell array blocks 90. Pads P1-P7 and input/output buffer circuit 70 are formed in input/output buffer region 7 of FIG. 7. Chip control circuit 80 is formed in chip control circuit region 8 of FIG. 7. Each memory cell array block 90 corresponds to each memory cell array block 9 of FIG. 7.
Input/output buffer circuit 70 includes a data out buffer 801 in the final stage, and a data in buffer 802, address buffers 803 and 804, a row address strobe buffer 805, a column address strobe buffer 806 and a write enable buffer 807 all of which are in the first stage.
Data out buffer 801 outputs data Dout applied from chip control circuit 80 to pad P1. Data in buffer 801 inputs external data Din applied through pad P2 to chip control circuit 80. Address buffers 803 and 804 input external address signals A0-An applied through pads P3 and P4 to chip control circuit 80. Row address buffer 805, column address strobe buffer 806 and write enable buffer 807 input external row address strobe signal RAS, column address strobe signal CAS and write enable signal WE applied through pads P5, P6 and P7, respectively, to chip control circuit 80.
Chip control circuit 80 includes a data input/output buffer and selector 808, a block select circuit 809, an address buffer and predecoder 810 and a clock generator 811.
Clock-generator 811 controls data input/output buffer and selector 808, block select circuit 809 and address buffer and predecoder 810 in response to the row address strobe signal RAS, the column address strobe signal CAS and the write enable signal WE. Address buffer and predecoder 810 predecodes address signals A0-An and applies the predecoded signals to memory cell array blocks 90 and block select circuit 809. Block select circuit 809 selects one of the four memory cell array blocks 90 and activates the same. Data input/output buffer and selector 808 applies data read from the selected memory cell array block 90 to data out buffer 801 in a reading operation. Data input/output buffer and selector 808 also applies data applied from data in buffer 802 to the selected memory cell array block 90 in a writing operation.
Each memory cell array block 90 includes a memory cell array 901, a memory cell array block generator 902, a column decoder 903, a row decoder 904, an input/output latch 905 and a sense amplifier 906.
Memory cell array block clock generator 902 controls each circuit in memory cell array block 90. Column decoder 903 and row decoder 904 designate an address of a memory cell in memory cell array 901 in response to a predecoded signal. In a reading operation, data read from memory cell array 901 is amplified by sense amplifier 906 and applied to data input/output buffer and selector 808 through input/output latch 905. In a writing operation, the data applied from data input/output buffer and selector 808 is written in memory cell array 901 through input/output latch 905.
An operation of the semiconductor memory will be schematically described with reference to FIG. 7. Data, address signals and control signals input through the pads in input/output buffer region 7 are amplified by the input/output buffers in input/output buffer region 7 and transmitted to chip control circuit region 8 arranged at the center of chip 1. In chip control circuit region 8, an address signal selects one of the four memory cell array blocks 9. A writing or reading operation is performed in the selected memory cell array block 9.
In a reading operation, data read from the selected memory cell array block 9 is transmitted to chip control circuit region 8 at the center of chip 1 wherein the data is amplified. The amplified data is transmitted to input/output buffer region 7 and output to the outside of the chip through the output buffer and the pad.
Thus, a control signal or an address signal generated in chip control circuit region 8 arranged at the center of chip 1 drive memory cell array blocks 9 arranged externally to chip control circuit region 8. As a result, a length of the interconnection between chip control circuit region 8 and each memory cell array block 9 is approximately half the longer side of chip 1, causing signal delay due to the interconnection.
In order to prevent such signal delay, the size of a transistor for driving signals is increased, thereby enhancing current drivability.
The number of signals generated in chip control circuit region 8 is several times the number of signals input or output from or to the outside of the chip. Thus, circuits for generating a part of the signals for driving the memory cell array is located in each memory cell array block 9. As a result, the number of signals transmitted from chip control circuit region 8 to each memory cell array block 9 is reduced to decrease the load of the circuits for generating the signals for driving the memory cell array, thereby achieving a high-speed operation and reduction in power consumption.
However, chip control circuit region 8 arranged at the central portion of chip 1 increases a length of a signal interconnection between control circuits (by the amount approximately as long as the shorter side of chip 1).
As described above, the length of the signal interconnection between chip control circuit region 8 and each memory cell array block 9 is increased. In addition, a signal interconnection is increased in such a region including a large number of signal interconnections as chip control circuit region 8. Each load capacitance is also increased to increase signal delay due to the interconnections.
Enhancing current drivability of a signal generation circuit to reduce such delay results in an increase in a chip area and power consumption.

Semiconductor integrated circuit device including a plurality of cell array blocks


An area saving dielectrically isolated semiconductor structure is disclosed which allows for the merger of a plurality of active devices, which share a common terminal, in a single dielectrically isolated (DI) island, or tub. In particular, an isolation groove is formed in the bottom of the DI tub and extends upwards toward the top surface of the semiconductor structure. The common diffusion region associated with the common terminal is located in the DI tub directly over the isolation groove. The isolation groove and common diffusion region thus separate the single DI tub into isolated sections, where a separate active device can be formed in each section. Isolation is achieved through the interaction of the groove with the common diffusion region to "pinch off" the conductive channel between devices in the DI tub. In a preferred embodiment, an inverted V-shaped isolation groove is utilized so as not to complicate the fabrication process. In order to merge a large plurality of devices in a single DI tub, a plurality of isolation grooves may be utilized to divide the single DI tub into a number of separate isolated sections.

1. Field of the Invention
The present invention relates to an inverted groove structure for use in association with dielectrically isolated devices which allows two or more independently active devices that share a common terminal to be formed in a single, area-saving, dielectrically isolated (DI) island, or tub. The groove, or grooves, extend upward from the bottom of the island towards the common diffusion region so as to cut off the conductive channel between the active devices.
2. Description of the Prior Art
Integrated semiconductor structures were first fabricated using PN junction isolation in order to electrically isolate various active devices from each other. Such a structure usually has a substrate of one conductivity type and regions of opposite conductivity type located in the substrate and biased with respect to the substrate in a manner to utilize the PN junctions between the substrate and these regions as a form of electrical isolation. Other techniques were subsequently developed for isolating devices in an integrated circuit structure. One of these techniques includes the concept of dielectric isolation. In this technique of isolation, the various semiconductor devices are formed in "pockets", of tubs, of semiconductor material wherein the tubs are isolated from an underlying substrate, and also from each other, by means of a dielectric layer of material, usually of silicon dioxide. For many applications, this technique is preferable over PN junction isolation. For example, in the case of high voltage integrated circuits, the dielectric layer reduces the area overhead associated with device isolation, that is, the additional semiconductor material needed to support, without breakdown, the electric field of a reverse biased isolating junction. Also, dielectric isolation is well-suited for high speed integrated circuits, since this type of isolation avoids the added delays associated with charge redistribution in the depletion region of a reverse biased isolating junction that would otherwise occur as a result of voltage level changes during circuit operation.
A basic description of the dielectric isolation technique can be found in U.S. Pat. No. 3,579,391 issued to J. L. Buie on May 18, 1971. Here, the method of producing dielectric isolation for one or more regions in the substrate includes the steps of cutting a groove in a semiconductor wafer surrounding the region to be isolated, establishing an insulating layer on the surface of the wafer and on all surfaces of the groove, and providing mechanical supporting substrate material to fill the groove. Later work in this area developed a structure wherein a V-shaped groove was used in the process described above. U.S. Pat. Nos. 3,913,124 and 3,956,033 issued to D. K. Roberson on Oct. 14, 1975 and May 11, 1976, respectively, describe both a V-groove dielectrically isolated structure and method of forming the same. As disclosed, the V-groove structure is formed by masking and anisotropically etching the monocrystalline substrate. After depositing a layer of silicon dioxide, silicon nitride, or other dielectric material, the groove is filled with mechanical supporting material. A problem with this V-groove isolation technique, however, is that a separate dielectrically isolated island, or tub, is needed for each independently active device of the circuit, even if many of these devices share a common terminal and thus could conceivably share a common diffusion region. U.S. Pat. No. 4,467,344 issued to G. Chang et al on Aug. 21, 1984 discloses a technique for achieving area reduction in a dielectrically isolated circuit by forming two devices which share a common terminal in the same DI tub. In particular, two gated diode switches are formed in a single tub and isolated from one another by a high resistance JFET channel formed between a deep n diffusion extending down from the top surface of the tub and a second such diffusion extending up from the floor of the tub. Although this technique allows for devices to be combined in a single tub, additional masking and diffusion steps must be added to the device fabrication process to form the high resistance JFET channel.
Therefore, a need remains for a technique of combining active devices, which share at least one common terminal, in a single DI tub which is fairly simple in implementation and will not significantly alter the device fabrication process.

Inverted groove isolation technique for merging dielectrically isolated semiconductor devices


An actuator latch apparatus for locking a swing arm of a disk drive is described. The apparatus includes a notch provided at an end portion of the swing arm; a latch lever rotatably installed on the base member and including a hook formed to interfere with the notch when the actuator is locked; a first latch pin applying a torque to the latch lever due to a magnetic force of the magnet in a first direction; a second latch pin extending from the latch lever; an attraction part protruded from an edge of the yoke, the attraction part being magnetized by the magnet and adsorbing the second latch pin when the actuator is locked; and a solenoid coil winding around the attraction part and offsetting a magnetism of the attraction part due to a supply of power when the actuator is unlocked.

1. Field of the Invention
The present invention relates to a disk drive, and more particularly, to an actuator latch apparatus for a disk drive, in which an actuator is locked in a specified position when a disk is not rotating, such that the actuator is prevented from arbitrarily rotating due to an impact to the disk drive.
2. Description of Related Art
A hard disk drive (HDD) is a device for reproducing/recording data from/on a disk using a read/write head. In such an HDD, the read/write head moves to a desired position while moving above a recording surface of a rotating disk by means of an actuator and executes the reproducing/recording functions.
When the HDD is not in operation, that is, when the disk is not rotating, the head is parked off the recording surface of the disk in order to prevent a collision with the recording surface of the disk. Such head parking systems can be classified into a contact start-stop (CSS) system and a ramp loading system. In a CSS system, a parking zone in which data is non-recordable is provided in an inner circumference of the disk and the head is parked in close contact with the parking zone. In the ramp loading system, the head is parked on the ramp, which is located outside the disk.
While the head is parked on the parking zone or the ramp, the actuator may arbitrarily rotate due to an impact to or vibration of the HDD, such that the head is forced out of the parking zone or the ramp and on the recording surface of the disk. In this case, the head may make forceful contact with the recording surface of the disk, such that the head and the recording surface may be damaged. Therefore, when the head is parked on the parking zone or the ramp, the actuator must be locked in a specified position so that it cannot rotate arbitrarily. For this purpose, various kinds of actuator latch apparatuses are provided in the HDD.
FIGS. 1A through 1C illustrate a single lever type inertial latch apparatus according to the conventional art.
Referring to FIG. 1A, a HDD includes an actuator 10 for moving a read/write head to a specified position on the disk. The actuator 10 includes a swing arm 12 rotatably mounted on a pivot 11, and a suspension 13 installed in one end portion of the swing arm 12 to elastically bias the slider 14 toward a surface of the disk, in which the head is mounted on the slider 14.
The HDD further includes an inertial latch apparatus 20 for locking the actuator 10 when the head is parked in the ramp 15. The inertial latch apparatus 20 includes a latch lever 21 rotating due to inertia, a latch hook 22 provided on a front end of the latch lever 21, a notch 23 provided at the swing arm 12, a crash stop 24 limiting a clockwise rotation relative to the apparatus 20 as depicted in that figure of the swing arm 12, and a latch stop 25 limiting a clockwise rotation of the latch lever 21.
According to the conventional inertial latch apparatus 20, as shown in FIG. 1B, when a rotational force impacts the HDD in a clockwise direction relative to the apparatus 20 as depicted in that figure, the swing arm 12 and the latch lever 21 rotate in a counterclockwise direction due to inertia. Thus, the latch hook 22 is caught by the notch 23, such that the swing arm 12 cannot rotate further. Conversely, as shown in FIG. 1C, when a rotational force impacts the HDD in a counterclockwise direction relative to the apparatus 20 as depicted in that figure, the swing arm 12 and the latch lever 21 rotate in a clockwise direction due to inertia. At first, the swing arm 12 rotates in a clockwise direction, but it collides with the crash stop 24 with a reaction, resulting in the swing arm 12 rotating in a counterclockwise direction. The latch lever 21 collides with the latch stop 25 with a reaction, resulting in the latch lever 21 rotating in a counterclockwise direction. The latch hook 22 is engaged with the notch 23, thereby locking the actuator 10.
Such a single lever type inertial latch apparatus 20 operates correctly when the swing arm 12 of the actuator 10 rotates in a counterclockwise direction due to a clockwise rotational force impacted to the HDD. However, when a rotational force impacts the HDD in a counterclockwise direction, both the swing arm 12 and the latch lever 21 rebound, such that the latch hook 22 and the notch 23 are locked to each other. In this case, if the rebounding timing of the swing arm 12 and the latch lever 21 do not match correctly, the notch 23 is not locked to the latch hook 22. As a result, the actuator 10 is not locked. In other words, the conventional art inertial latch apparatus has a drawback in that a locking reliability of the actuator 10 cannot be guaranteed.
FIGS. 2A through 2C illustrate a dual lever type inertial latch apparatus, which is an improvement of the single lever type inertial latch apparatus.
Referring to FIG. 2A, an inertial latch apparatus 40 for locking an actuator 30 includes two latch levers 41 and 42 rotating due to inertia, a latch pin 43 provided at the first latch lever 41, a latch hook 44 provided at the second latch lever 42, a notch 45 provided at a swing arm 32 of the actuator 30, and a crash stop 46 limiting a clockwise rotation of the swing arm 32.
According to the dual lever type inertial latch apparatus 40, when a rotational force impacts an HDD in a clockwise direction relative to the apparatus 40 as depicted in that figure, the swing arm 32 and the first and second latch levers 41 and 42 rotate in a counterclockwise direction relative to the apparatus 40 as depicted in that figure due to inertia, as shown in FIG. 2B. Therefore, the latch hook 44 is locked to the notch 45, such that the swing arm 32 does not rotate further. On the contrary, as shown in FIG. 2C, when a rotational force impacts an HDD in a counterclockwise direction relative to the apparatus 40 as depicted in that figure, the swing arm 32 and the first latch lever 41 rotate in a clockwise direction due to inertia. At first, the swing arm 32 rotates in a clockwise direction relative to the apparatus 40 as depicted in that figure, but it collides with the crash stop 46 with a reaction, resulting in the swing arm 32 rotating in a counterclockwise direction. The first latch lever 41 rotates in a clockwise direction and the latch pin 43 causes the second latch lever 42 to rotate in a counterclockwise direction. The latch hook 44 of the second latch lever 42 interferes the notch 45 such that a counterclockwise rotation of the swing arm 32 is limited.
The dual lever type inertial latch apparatus 40 operates stably with respect to the rotational force impacting the HDD in the clockwise and counterclockwise directions. However, since the dual lever type inertial latch apparatus 40 requires two latch levers 41 and 42, its structure is complex and its size is large, such that it occupies a large area. Also, a manufacturing cost is increased and much time is necessary to assemble it. Therefore, the dual lever type inertial latch apparatus 40 is difficult to apply to a small-sized mobile disk drive.
The above-described conventional inertial latch apparatuses 20 and 40 operate with respect to a relatively strong rotational force enough to rotate the latch lever. That is, when a relatively weak impact or vibration is applied to the HDD, the latch lever operating due to inertia does not rotate, such that the actuator is not locked but rotates arbitrarily. Therefore, a locking reliability of the actuator cannot be guaranteed when a weak impact is applied to the HDD.

Disk drive actuator latch apparatus with solenoid coil offsetting magnetism of attraction part


A polyamide resin for use in peptide and protein synthesis, and a method of preparing and using same. The polyamide resin is prepared by cross-linking a dimethylacrylamide monomer by co-polymerization with a functional monomer in an aqueous solution, emulsifying the aqueous solution in an organic solvent and isolating the polyamide resin beads formed by adding an initiator and a promoter. The beads are used as a solid phase for peptide and protein synthesis according to methods known in the art. The conjugate of the polyamide resin and the synthesized peptide or protein is used directly for immunoassays or immunization without the need for separation of the peptide or protein from the resin and subsequent purification.

The present invention relates to the synthesis and use of synthetic peptides and proteins to induce an immune response in experimental animals. More particularly, the present invention relates to a polyamide resin, a method of making that polyamide resin, a method of inducing an immune response in an experimental animal using a conjugate of a peptide or protein synthesized on that resin, and the the use of the resin for immunodiagnostic purposes.
Solid phase peptide synthesis is a valuable tool for investigating the structure and mechanism of action of proteins. Most such synthetic methods involve the use of a cross-linked polystyrene based resin as the solid phase to which the peptide is anchored during assembly, usually through a linker molecule. Assembly is accomplished by a repetitive cycle of adding a protected amino acid to the solid phase, selectively removing (deprotecting) a protective group on that amino acid, and adding additional suitably protected amino acids (for a review, see Merrifield, R.B., "Solid-phase Peptide Synthesis", 32 Adv. Enzymology 221 (1969)).
Although cross-linked, polystyrene based resins are most commonly used as supports in solid phase peptide synthesis, their relatively hydrophobic character in comparison to the polar organic media required to solubilize reactants can be problematic in peptide chain assembly. Such media may freely solvate the growing peptide, yet incompletely swell the polystyrene matrix. Within the polymer lattice, impaired diffusion of reagents and steric hindrance can contribute to lowered efficiency during coupling cycles, which, on a repeated basis, lowers final yields appreciably. During the early stages of assembly, when the resin to peptide mass ratio is high and the physical properties of the support dominate, this lowered efficiency is particularly acute.
Those shortcomings led to the development of a cross-linked, polydimethylacrylamide based support which is highly polar in character and is freely permeated by the requisite solvents for peptide synthesis. Atherton, E., D.L.J. Clive and R.C. Sheppard, "Polyamide Supports For Polypeptide Synthesis", 97 J. Amer. Chem. Soc. 6584 (1975); Arshady, R., E. Atherton, M.J. Gait, K. Lee and R.C. Sheppard, "Easily Prepared Polar Support For Solid Phase Peptide And Oligonucleotide Synthesis". 1979 J.C.S. Chem. Comm. 425 (1979). The polyamide resin, as the amino methyl derivative, can accommodate synthetic schemes incorporating alternate protection strategies through selection of the appropriate linker molecule, which links the C-terminal residue to the support. The peptide or protein thus synthesized, which will be referred to throughout the present disclosure as a "protide", can be used in a number of investigative applications.
Of particular interest to the present invention is the use of the protide as an immunogen. It has previously been demonstrated that synthetic peptides analogous to sequences contained in viral encoded proteins have proven useful for identification of native antigen determinants associated with such proteins. Several laboratories have reported studies on the antigenic activity of various HBsAg synthetic peptides. Dreesman, G.R., et al., 295 Nature 158 (1982); Lerner, R.A., et al. 78 Proc. Natl. Acad. Sci. USA 3403 (1981); Prince, A.M., et al., 79 Proc. Natl. Acad. Sci. USA 579 (1982). The induction of an antibody response to HBsAg, using such peptides, proved to be relatively weak, but could be enhanced through coupling of peptides to a carrier protein prior to immunization. Lerner, et al., supra; Sanchez, Y., et al., 18 Intervirology 209 (1982). Because the prediction of potential antigenic determinants of immunogenic proteins based on primary sequences analysis is not exact, the identification of putative epitopes through trial and error can be laborious. A method which involves the delineation of native antigenic sequences with synthetic peptides which does not require purification of the synthetic peptide and coupling of the peptide to carrier proteins offers significant advantages. It is, therefore, an object of the present invention to provide a method of preparing a polyamide resin upon which a protide can be synthesized using solid phase synthetic methods which can be injected into an experimental animal to induce an immunogenic response without separation of the protide from the resin.
It is another object of the present invention to provide a polyamide resin for solid phase protide synthesis, and a conjugate of that polyamide resin and synthesized protide, which can be injected into an experimental animal to induce an immunogenic response.
It is another object of the present invention to provide a polyamide resin-protide conjugate for use in in vitro immunological assays.
Another object of the present invention is to provide a method of preparing a polyamide resin for solid phase protide synthesis comprising cross-linking a dimethylacrylamide monomer with a molecule containing a functional group by free radical co-polymerization in an aqueous solution which has been emulsified by a detergent when added to an organic solvent medium.
Another object of the present invention is to provide a method of inducing an immunogenic response in an experimental animal with a synthetic peptide or protein comprising preparing a polyamide resin, synthesizing a peptide or protein on that polyamide resin, and immunizing an experimental animal with the polyamide resin-synthetic peptide or synthetic protein conjugate.
Another object of the present invention is to provide an assay for detection of proteins such as antigens and antibodies using the polyamide resin-protide conjugate of the present invention.
Another object of the present invention is to provide a method of inducing an immunogenic response in an experimental animal using the polyamide resin-protide conjugate of the present invention.
Another object of the present invention is to provide a polyamide resin for solid phase protide synthesis which does not require the separation of the protide from the resin and the subsequent purification of the protide before the use of that protide to, for instance, induce an immunogenic response.
Another object of the present invention is to provide a polyamide resin for solid phase protide synthesis which is particularly useful in the mapping of the antigenic determinants of a protein as a result of the elimination of the steps of separation of the protide from the resin and the subsequent purification of the protide before the use of the protide in a binding assay.
These and other objects and advantages of the present invention will be clear to those skilled in the art from the following description.

Polyamide resin and method for preparation of reagents for immunodiagnostic use

Southwest Foundation for Biomedical Research


A programmable document includes a physical document having at least one sheet of material and information recorded thereon and a computer attached to the physical document. The computer includes an input/output device, a processor and a memory storing the recorded information in digital form and metadata pertaining to the physical document. By attaching small, inexpensive, computing devices to paper documents, various electronic information associated with the physical document can be retained, updated and modified.

Despite the availability and convenience of electronic media, the promise of the "paperless" office has not yet come to pass. It is still true, for example, that almost all important documents are printed at least once during their life because paper is still the most convenient medium for reading, annotating and sharing documents. However, once the electronic document is printed almost all "meta" information (such as the version number, last date of modification, date of printing, change history, comments, authors, reviewer's ratings, etc.) is lost unless such information is explicitly printed on the document.
If a user wishes to copy a paper document, then the paper document must be photocopied, or the electronic version must be obtained and a new physical document generated. Copying a paper document generally results in a lower quality copy than would be obtained by printing a new version of the electronic document. However, no record of the copying is retained on either physical document. If a user wishes to modify a paper document, modifications can be written directly on the paper document or the electronic version can be obtained, modifications made and a new version printed out.
Written comments on a paper document cannot be processed automatically using current optical character recognition (OCR) technology. For these reasons, most users choose to retrieve the electronic document. However, this may not be possible, because the electronic copy may no longer exist. If the electronic copy exists, it may not be accessible. For example, the electronic copy may be located behind a corporate firewall or on a storage device (such as a floppy disk) that is not network accessible. If the device is network accessible, the network may be so busy that downloading the document takes a prohibitive amount of time, or the person wishing to obtain it might not have a network connection at all.
Even if the meta information is printed on the document it may be intrusive (in the case of a long change history) and it will normally not be machine readable. Various technologies have been developed for the purpose of storing meta information with a paper document. These technologies essentially are a way to place the meta information or metadata as machine readable code on the paper document and include barcodes, DataGlyphs and magnetic strips. Bar codes are well known and a large infrastructure of readers exits. However, bar code storage density is so low that storing anything more than the document identifier would be impractical. DataGlyphs are essentially high-density, two dimensional codes that can store up to 1000 bytes per square inch. However, with current printing technology, DataGlyphs are visible to the user. While DataGlyphs can store enough information to represent an entire document, the resulting size of the DataGlyph requires a large amount of the paper document be devoted to the DataGlyph, which many users may find intrusive. Magnetic strip technology has been around for many years and is relatively inexpensive. However, it too suffers from low storage density (only on the order of 100 bytes can be stored on the magnetic strip of a bank card, for example). In addition magnetic strips are relatively fragile and can be damaged by contact with other magnetic strips or magnetic material. If a document with a magnetic strip is photocopied, the information in the magnetic strip is not duplicated. Even if the meta information is machine readable it is certainly not modifiable on the physical document.
Various other solutions have been developed to overcome the limitations of printed machine readable code. For example, radio frequency (RF) tags have been associated with objects and are used, for example, for tracking of items in commerce. Copending, coassigned U.S. patent application Ser. No. 09/404,734 filed Sep. 24, 1999, "N-space Indexing of Digital Data Representations Using Physical Tags" describes a small version of an RF tag, called a "smart staple" which is attached to a paper document. The smart staple includes an electronic ID stored in the staple for interfacing with an electronic information system. Copending, coassigned U.S. patent application Ser. No. 09/276,085 filed Sep. 25, 1999, "Marking Medium Area with Encoded Identifier for Producing Action Through Network" describes a system for interacting with paper and retrieving an electronic copy of written notes (by tracking a user's pen as it moves over a paper document). Many Personal Digital Assistants and or palmtop computers enable tracking of handwritten notes, but such systems require access to bulky computing equipment or a network connection.
It would be beneficial to combine the advantages of electronic media with the convenience of paper. It would be beneficial to be able to quickly retrieve the electronic version of a document and all associated meta information in any situation where the paper document is available. It would also be beneficial to be able to store comments about a paper document and modifications to the document in such a way that they could be retrieved and processed electronically, without having to access expensive computer equipment or a network.


This is simple and efficient rotary machine that can be implemented as compressor, pump, motor and mainly as internal combustion engine. The engine comprises a housing, a rotor(s) with a radial blade(s), a chamber(s) swept by the blade(s), an intersecting planar valve(s) with slot, and a combustion chamber. Blades and slots have matching shapes that allow the traversal of the blades through the slots with negligible loss of air/gases. After traversing the slot, the blade aspires air into one side of the chamber while compresses air on the other side. Fuel is injected in the compressed stream in its way to the combustion chamber, where it is ignited. In a double-rotor implementation, combustion gases are then introduced in the second rotor chamber, just after its blade has traversed the corresponding slot. One side of this blade is pushed by the expansion while the other expels gases from the previous stroke.

1. Field of the Invention
This invention relates to a rotary machine that can be implemented as a compressor, pump, motor or combustion engine. This machine is mainly intended for use as an internal combustion engine.
2. Description of the Prior Art
Most internal combustion engines nowadays use reciprocating pistons. This design has severe inherent limitations: pressure and torque arm out of phase, high "inertial" forces between components due to acceleration/deceleration of pistons and change of trajectory of connecting rods, and expansion ratio tied to the compression ratio. Such limitations reduce performance, increase friction and wear, and reduce energy efficiency.
Many rotary designs have been proposed to overcome the inherent limitations of reciprocating engines. Although relegated to niche markets, the Wankel engine has probably been the most successful in commercial terms. Technically speaking, the Wankel engine has not completely solved old problems like friction and wear, and has problems of its own, especially low torque and troublesome sealing.
My invention is more related to toroidal engines, recent examples of which are found in U.S. Pat. No. 5,645,027 (Esmailzadeh); U.S. Pat. No. 6,276,329 (Archer); and U.S. Pat. No. 6,546,908 (Pekau).
Toroidal engines use pistons revolving in a toroidal chamber intersected by walls or valves. Generally speaking, compression is achieved by advancing the pistons against said walls/valves while deviating the compressed fluid to a separate chamber. At the end of the compression stroke, the intersecting wall/valve briefly retracts/opens to allow the piston pass by/through. In the meantime, combustion is started in the separate chamber. Combustion gases are then released behind the piston.
A key problem in prior art toroidal engines is the loss of compressed fluid during the opening and closing of the walls/valves. Such loss has an important toll on power output and energy efficiency, as it reduces the fuel-burning capacity of the engine, and at the same time increases the pumping power requirements for the compression and exhaust strokes.
Recent designs, disclosed in the already mentioned patents to Archer and to Pekau, have seemingly reduced compression losses to manageable levels. Archer's approach consists of very short pistons and an intersecting valve made of two counter-rotating discs. Pekau has instead modified the shape of the pistons in order to better match the intersecting valve, which is a single rotating disc.
The starting point of my approach has been to develop a simple method for "seamlessly" traversing one body through another moving in an intercepting trajectory. The result is the "blade-thru-slot" (BTS) concept. The application of this concept in a rotary machine leads to blades that orbit circularly inside a chamber and traverse intersecting planar valves through small slots. This approach virtually eliminates compression losses in a mechanically simple way; the slots are not only small in area but also remain "plugged" by the traversing blades while said slots are inside the chamber.
Although the Archer and Pekau engines have lower compression losses than previous toroidal designs, reduced fuel-burning capacity and excessive pumping power requirements are still present. Design limitations do no allow for positive removal of exhaust gases; instead, these remain in the toroidal chamber, between the revolving pistons, and are carried along until they get mixed with the intake charge. Similarly, there is no positive intake of air; an external charger is required to provide fresh air for the compression stroke. Consequences of these limitations are reduced intake of fresh air, excessive amount of exhaust gases in the intake charge, increased pumping losses, and ultimately lower power output.
The BTS engine provides complete removal of exhaust gases from the chamber, and positive intake of air, thus no external charger is required. This comprehensive "breathing" allows the BTS engine to achieve its full power potential.
Generally speaking, the BTS engine has the following advantages over prior art rotary engines: mechanical simplicity, very low friction (as no contact sealing is used), internal lubrication not needed, reduced pumping losses, comprehensive breathing and increased power output.
The above discussion is by extension applicable to other implementations of the BTS machine. Regarding compressors and pumps, main advantages of the BTS machine over reciprocating piston machines are lower friction and wear, no internal lubrication required and reduced power demand. In the case of prior art rotary compressors and pumps, the BTS machine is generally superior in terms of mechanical simplicity, reduced internal friction and no internal lubrication. Regarding pneumatic motors and similar compressed-fluid motors, the general advantages of the BTS machine over conventional and prior art machines are again mechanical simplicity, reduced internal friction, and no internal lubrication.

Blade-thru-slot combustion engine, compressor, pump and motor


A method and system for providing on-line game competition are provided. Players select their favorite teams, join with other fans of the team, and compete against players on the opposite team. Teams compete against each other in matches, where matches are based on schedules of real-life events, such as sports schedules or entertainment schedules. Players are grouped with other players associated with their favorite teams, and matches are organized. Various trivia questions may be presented, and players have a predetermined period of time to answer the questions. Points may be awarded based on a player""s success in competition and the overall teams success in matches. Further, prizes are awarded based on points received by a player.

The present invention relates generally to games, and more specifically to online electronic team games of trivia scheduled based on real-life events.
Competitive games are a well known form of recreation. These games may include physical activities, such as basketball or baseball, or more inactive games, such as xe2x80x9cboard gamesxe2x80x9d like Monopoly(trademark) and Trivial Pursuit(trademark) Advances in technology have added new games and altered existing games. These advances in technology allow games such as basketball, baseball, or Monopoly(trademark) to played in an electronic format.
Competitive games may be enjoyable because participants can interact with others in friendly competition. Electronic games, however, may suffer from the drawback of reducing the number of people who can participate together in a game. Many current electronic video games are limited to two players competing against each other. This limits who can participate.
Additionally, many conventional games are limited by geography. Players may only compete with other players nearby. To participate, a player may have to travel large distances at great expense to reach a competition. This may discourage players from competing in various contests.
Conventional electronic games may also have a drawback of not establishing competition among a community of players with common interests. Many electronic games are limited to a schedule(s) created by the game manufacturer. These games do not incorporate real-life competition and/or preexisting loyalties held by players. While a player may have a preexisting loyalty to a college football team, for example, existing electronic games do not specifically use these loyalties to promote competition in the electronic games.
These and other drawbacks exist.
An object of the present invention is to overcome these and other drawbacks in existing systems and methods.
Another object of the invention is to provide systems and methods for allowing a plurality of players to electronically compete in contests against each other.
Another object of the invention is to provide systems and methods for allowing a plurality of players to be teamed together, based at least in part on player profiles, and matching teams of players against each other in a competition.
Another object of the invention is to provide systems and methods for matching teams of players against each other in competition based on real-life events.
Another object of the invention is to provide systems and methods for grouping players into teams based on player-selected sports teams and matching teams according to a real-life sports schedule.
Another object of the invention is to provide systems and methods for creating a compelling multi-player experience as well as foster a community of like-minded sports fans.
Another object of the invention is to provide systems and methods for fostering player loyalty driven by pre-existing, strongly held loyalties to sports teams.
Another object of the invention is to provide systems and methods for allowing a player to receive a score for a contest based on the performance of the player in the contest and based on the performance of the player""s team in the contest.
Another object of the invention is to provide systems and methods for allowing a plurality of players to compete in a trivia based competition by presenting players with a series of questions and tallying the responses provided by the players.
Another object of the invention is to provide systems and methods for providing the opportunity for players to accumulate chances to win prizes while participating in competition with and against a plurality of other players.
Another object of the invention is to provide systems and methods for providing branding opportunities for partners and clients who sponsor player competition.
Another object of the invention is to provide systems and methods for providing a sizable value-added content to existing online sports content providers who sponsor player competition.
These and other objects of the invention are accomplished according to various embodiments of the invention. According to one embodiment of the invention, a plurality of players register to compete. Players are placed on teams based on a player""s indication of team preferences. Teams are matched based on real-life events. The score of the competition is tallied, and the players are awarded scores based on the player""s individual performance and teams performance.
Other objects and advantages exist for the present invention.

System and method for interactive game-play scheduled based on real-life events


A method of manufacturing a semiconductor device including forming a gate oxide layer, a first conductive layer, a capacitor dielectric layer, and a second conductive layer on a semiconductor substrate. The method also includes patterning the first and second conductive layers, the gate oxide layer, and the field oxide layer so as to form a gate pattern and a capacitor pattern; selectively wet-etching the first and second conductive layer so as to project out an outward part of the capacitor dielectric layer; implanting ions into the semiconductor substrate using the gate pattern and the protruding portion of the capacitor dielectric layer as an implantation mask; and removing the protruding portion of the capacitor dielectric layer so that the patterned capacitor dielectric layer has the same width as the gate electrode and the first capacitor electrode.

(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device for forming a source/drain region of an analog CMOS.
(b) Description of the Related Art
Generally, transistors of semiconductor devices may be classified into an NMOS, a PMOS, and a CMOS according to their channel type. An NMOS is formed with an N-channel, and a PMOS with a P-channel. In addition, the CMOS (complementary metal oxide silicon) has the NMOS and the PMOS, and thus both an N-channel and a P-channel are formed therein.
A conventional CMOS manufacturing method will hereinafter be described in detail with reference to FIG. 1A to FIG. 1D.
FIG. 1A to FIG. 1D are cross-sectional views showing principal manufacturing stages of a conventional semiconductor device.
As shown in FIG. 1A, a well 2 is formed on a semiconductor substrate 1 by implanting ions, and a field oxide layer 3 is formed thereon. The well 2 is classified as a p-well or an n-well according to the type of ions implanted into the semiconductor substrate 1. The p-well is formed on a semiconductor substrate for forming an NMOS, and the n-well is for forming a PMOS.
Then, as shown in FIG. 1B, a gate oxide layer 4 is formed on the semiconductor substrate 1. Subsequently, a conductive layer such as a polysilicon layer is formed on the field oxide layer 3 and gate oxide layer 4, and it is patterned by a photolithography and etching process so as to form a first capacitor electrode 5b and a gate electrode 5a of an analog CMOS.
As shown in FIG. 1C, a capacitor dielectric layer 6 such as an oxide-nitride-oxide (ONO) layer is formed on the first capacitor electrode 5b, and a second capacitor electrode 7b is formed thereon so as to form a capacitor stack. Subsequently, impurity ions are implanted at a low concentration into the semiconductor substrate 1 using the gate electrode 5a as an implantation mask.
Then, as shown in FIG. 1D, spacer layers 10a and 10b are respectively formed on sidewalls of the gate electrode 5a and sidewalls of the capacitor stack. Subsequently, impurity ions are implanted at high concentrations into the semiconductor substrate 1 using the gate electrode 5a and the insulation layer spacer 10a as an implantation mask. Then, a source region 8a, a drain region 8b, and lightly doped drain (LDD) regions 9a and 9b are formed. The lightly doped drain regions 9a and 9b are located between the source/drain regions 8a, 8b and a channel region, and are used for suppressing device degradation such as a hot carrier effect.
As described above, in order to form the conventional lightly doped drain regions 9a/9b and the source/drain regions 8a/8b, the ion implantation process for forming a source/drain should be performed at least twice.
The above information described in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that is not prior art to the present invention.

Manufacturing method of semiconductor device


A programmable bus hold circuit which may find application in programmable logic devices, memories and other I/O devices may include a first element for receiving a voltage from an I/O pad and programmable circuitry coupled to the first element for controlling whether the voltage at the pad is to be held its current logic level. The first element may be a logic gate (such as a NOR gate) the programmable circuit may include a tristatable buffer (e.g., under the control of a memory cell or other programmable bit capable of enabling or disabling the programmable bus hold circuit) or a switch (e.g., a transistor).

Conventional input/output ("I/O") devices commonly used in computer systems are often required to quickly drive I/O buses that are connected to I/O pins in order to meet various timing specifications. To meet these requirements, I/O devices are typically equipped with output drivers that have high signal switching strengths. When the output driver is turned off there is a potential problem on the bus. A user may pull the bus either high or low with external circuitry, but this may cause excess noise due to many outputs switching simultaneously. Accordingly, a conventional solution of preventing bus contention is to add a bus hold circuit (e.g., configured as a weak latch).
Although using bus hold circuits reduces the bus noise level, bus hold circuits are not always needed or desirable. For example, if an application requires that multiple I/O pins be tied together, a number of individual bus hold circuits associated with these pins may consume a large amount of operating current. Consequently, a voltage level held by the multiple bus hold circuits may tend to be more difficult to override. Further, some users may wish to purchase I/O devices that are not constructed with bus hold circuits because of the expected cost savings which may result. Unfortunately, it would be cost prohibitive for a manufacturer to produce two identical devices with one version having bus hold circuits and another without such circuits. Thus, a solution is needed.

Programmable bus hold circuit and method of using the same


A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (219); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (229); and (c) using the first and second masks to create a semiconductor device.

The characteristics of certain semiconductor fabrication processes are found to vary considerably from one device to another. For example, the rate and uniformity of chemical mechanical planarization (CMP) techniques employed in conjunction with shallow trench isolation (STI) processes varies considerably as a function of feature pattern density. As a result, the application of such trench CMP processes to substrates that contain active regions of different population densities can give rise to significant and undesirable non-uniformities in topography.
This problem is sometimes addressed through the incorporation of dummy features or "tiles" into less populated active regions of a semiconductor device so as to even out the pattern density between the two regions, thereby achieving greater process uniformity in the trench CMP process. Such dummy features or tiles are typically placed in the "white space" between active device features, and are thus independent of the circuit design of the semiconductor device.
The characteristics of epitaxial growth processes are also found to vary significantly with pattern density. For example, when epitaxial growth processes are used to form silicon germanium alloy films on CMOS substrates, the growth rate, quality, composition and thickness of the resulting films are all highly sensitive to pattern density.
Some attempts have been made in the art to compensate for the effect of pattern density on epitaxial growth. For example, in one known approach, a fraction of the dielectric tiles used to control topographical uniformity in the chemical mechanical polishing (CMP) attendant to shallow trench isolation (STI) are reused for density matching in subsequent epitaxial growth processes. However, this approach is found to produce suboptimal results in terms of compensating for differences in pattern densities during epitaxy.
There is thus a need in the art for a process which overcomes the aforementioned infirmities. In particular, there is a need in the art for a tiling scheme which addresses the needs of both trench CMP and epitaxy. These and other needs may be addressed with the methodologies and devices described herein.

Integrated assist features for epitaxial growth


Two sets of independent armature windings and two sets of control units are provided; a single power-source connector branches into at least four lines in the vicinity of a power-source terminal; a power source relay, a filter, and an inverter circuit are connected, in that order, with a line where a large current flows; a control circuit unit is connected with a line where a small current flows and a detection circuit for detecting an abnormality in the control circuit unit is provided in that line.

To date, in electric power steering apparatuses in each of which an electric motor produces assist torque for assisting steering torque produced by a vehicle driver, there exists an electric power steering apparatus in which there is provided an electric motor having two sets of armature windings that are formed substantially in the same manner and in which an inverter circuit that can separately drive the two sets of armature windings is provided in a control unit. At a normal time, the conventional electric power steering apparatus configured in such a manner as described above makes two sets of inverter circuits collaborate with each other so as to control the electric motor; however, in the case where an abnormality occurs in one of the two sets of inverter circuits, only the other normal inverter circuit continues driving of the electric motor.
To date, there has been disclosed an electric power steering apparatus in which the control-unit constituent elements, other than the inverter circuit, are made to be a double system so that the redundancy is raised and hence the countermeasure for a failure is further enriched (for example, refer to Patent Document 1). In the conventional electric power steering apparatus disclosed in Patent Document 1, not only two sets of armature windings of an electric motor are provided but also two sets of control units, each of which has a +B power source to be connected with the positive-polarity electrode of a vehicle battery, an input circuit, a CPU, an output circuit, and the like, are provided; in the case where an abnormality occurs in one of the two sets of control units, the other normal one thereof can continue driving of the electric motor.


There is provided a bank note processing machine in which a discrimination sensor can be formed compactly even when bank notes are discriminated using a light source having a plurality of wavelengths and in which the bank note transport path is shortened to achieve compactness. A bank note processing machine in which bank notes placed on an insert tray are sequentially delivered one by one to be fed to a discrimination sensor section; the bank note types and the genuineness or falsehood of bank notes are discriminated based on signals detected by a discrimination sensor at the discrimination sensor section; and the discriminated bank notes are sent to an accumulating section, wherein the discrimination sensor is formed by a light projecting section for irradiating over a slit area substantially the entire passing width of the bank notes and a light receiving section constituted by a photodiode array; the light projecting section is formed by a light guide plate and at least one LED provided on a side of the light guide plate; and the light projecting section and light receiving section are provided in a face-to-face relationship with the transport path of the bank notes sandwiched therebetween or provided in parallel on one the of the transport path.

1. Field of the Invention
The present invention relates to a bank note processing machine having a function of discriminating the bank note types and the genuineness/falsehood of bank notes, and more particularly to a compact bank note processing machine in which a compact discrimination sensor for irradiating bank notes with light having a plurality of wavelengths in the form of slits is provided such that the entire region of bank notes transported therethrough can be scanned to discriminate the bank note types and genuineness/falsehood of the bank notes based on light transmitted or reflected by the bank notes.
2. Description of the Prior Art
Various bank note processing machines (bank note discriminators) having a discriminating function for discriminating the bank note types and genuineness/falsehood of bank notes have been proposed including, for example, that disclosed in Japanese Patent Application Laid-open No. 312480/1998.
In the bank note processing machine disclosed in the above-cited publication, as shown in FIG. 1, a red LED array 102a and an infrared LED (Light Emitting Diode) array 102b are disposed in parallel to form a light source on one side of a transport path of a bank note 100, and a linear image sensor as a light receiving section 101 is formed on the other side opposite thereto to sandwich the same path. The red LED array 102a and infrared LED array 102b have a length that is substantially equal to the width of the bank note 100 passing by them. The output of the light receiving section 101 is inputted to a bank note genuineness/falsehood discrimination process section 104 to discriminate the genuineness/falsehood of the bank note 100. The reason for the use of the light source having a plurality of wavelengths is that there is a difference between the wavelengths of beams of light transmitted by a genuine bank note and a counterfeit bank note that is a color copy and the genuineness/falsehood can be determined based on the a difference between ratios of transmittance.
In the above-described conventional bank note processing machine, since the plurality of LED arrays 102a and 102b are disposed in parallel to form a discrimination sensor, the dimension of the light source section of the discrimination sensor inevitably becomes great in the direction in which bank notes are transported. As a result, it is necessary to provide the bank note transport path with a great dimension, which has resulted in a problem in that effort to make the bank note processing machine more compact is hindered. It is considered desirable to discriminate bank notes using a light source having many wavelengths from the viewpoint of improvement of accuracy of discrimination of the bank notes. For example, let us assume that a discrimination sensor is configured by disposing an array of LEDs in four rows having different wavelengths in parallel in order to perform discrimination with a light source having four wavelengths. Then, the sensor occupies considerably large dimensions. The sensor size (length) is increased further when a sensor having a light source with five wavelengths is used.
The present invention has been made in view of the above-described situation, and it is an object of the present invention to provide a bank note processing machine in which a discrimination sensor can be formed with a compact size even when bank notes are discriminated using a light source having a plurality of wavelengths and in which a bank note transport path is made short to achieve compactness.
The present invention relates to a bank note processing machine in which bank notes placed on a insert tray are sequentially delivered one by one to be fed to a discrimination sensor section; the bank note types and the genuineness/falsehood of said bank notes are discriminated based on signals detected by a discrimination sensor at said discrimination sensor section; and said discriminated bank notes are sent to an accumulating section, and the above-described object of the present invention is achieved by forming said discrimination sensor with a light projecting section for irradiating the substantially entire passing width of said bank notes in the form of slits and a light receiving section constituted by a photodiode array, forming said light projecting section with a light guide plate and at least one LED provided on a side of said light guide plate and providing said light projecting section and light receiving section in a face-to-face relationship with a transport path of said bank notes sandwiched therebetween or providing them in parallel on one side of said transport path.
Further, the above-described object is achieved by: forming said discrimination sensor with a light projecting section for irradiating over a slit area substantially the entire passing width of said bank notes and a light receiving section constituted by a photodiode array, forming said light projecting section with a light guide plate and an infrared light LED, a red light LED, a green light LED, and a blue light LED provided on a side of said light guide plate, and providing said light projecting section and light receiving section in a face-to-face relationship with a transport path of said bank notes sandwiched therebetween; or disposing a pair of light projecting and receiving sections with a transport path of said bank notes sandwiched therebetween, forming said light projecting and receiving sections with a light guide plate for irradiating substantially the entire passing width of said bank notes over a slit area, an infrared light LED, a red light LED, a green light LED, and a blue light LED provided on a side of said light guide plate, and a photodiode array disposed in parallel with said light guide plate, and detecting information on the top and bottom of the same part of said bank notes passing through said transport path simultaneously with said pair of light projecting and receiving sections using reflected light; or disposing a light projecting section and a light projecting and receiving section with a transport path of said bank notes sandwiched therebetween, forming said light projecting section with a first light guide plate for irradiating over a slit area substantially the entire passing width of said bank notes and an ultraviolet light LED, an infrared light LED, and a first green light LED provided on a side of said first light guide plate, forming said light projecting and receiving section with a second light guide plate for irradiating over a slit area substantially the entire passing width of said bank notes, a red light LED, a second green light LED, and a blue light LED provided on a side of said second light guide plate, and a photodiode array disposed in parallel with said second light guide plate; and detecting information on the top and bottom of the same part of said bank notes passing through said transport path with said photodiode array using reflected light and transmitted light; or disposing a light projecting section and a light projecting and receiving section with a transport path of said bank notes sandwiched therebetween, forming said light projecting section with a first light guide plate for irradiating over a slit area substantially the entire passing width of said bank notes, an infrared light LED and a first green light LED provided on a side of said first light guide plate, and a first ultraviolet light LED array disposed in parallel with said first light guide plate, forming said light projecting and receiving section with a second light guide plate for irradiating over a slit area substantially the entire passing width of said bank notes, a red light LED, a second green light LED, and a blue light LED provided on a side of said second light guide plate, a second ultraviolet light LED array disposed in parallel with said second light guide plate, and a photodiode array disposed in parallel with said second light guide plate, and detecting information on the top and bottom of the same part of said bank notes passing through said transport path with said photodiode array using reflected light and transmitted light. A UV lamp or a barrier discharge fluorescent lamp may be used instead of said first ultraviolet light LED array and second ultraviolet light LED array.
Further, the above-described object is achieved by disposing a light projecting section and a light projecting and receiving section with a transport path of said bank notes sandwiched therebetween; forming said light projecting section with a first light guide plate for irradiating over a slit area substantially the entire passing width of said bank notes and an infrared light LED and a first green light LED provided on a side of said first light guide plate, forming said light projecting and receiving section with a second light guide plate for irradiating over a slit area substantially the entire passing width of said bank notes, a red light LED, a second green light LED, and a blue light LED provided on a side of said second light guide plate, and a photodiode array disposed in parallel with said second light guide plate, and detecting information on the top and bottom of the same part of said bank notes passing through said transport path with said photodiode array using reflected light and transmitted light.
A display section may be provided integrally with or separately from said bank note processing machine to irradiate said bank notes with ultraviolet light from said light projecting section or light projecting and receiving section, thereby displaying images of said bank notes on said display section based on fluorescent light that is visible light generated as a result of transmission or reflection of said ultraviolet light at least when said bank notes react to said ultraviolet light; images of said bank notes may be displayed on said display section based on reflected light or transmitted light of infrared light obtained by irradiating said bank notes with said infrared light from said light projecting section or light projecting and receiving section; and said accumulating section may be a single accumulating section.


The present invention relates to a DNA profiling assay comprising the following steps, providing a sample to be analyzed, providing reagents, enzyme and primeroligonucleotides which are necessary for simultaneous polymerase chain reaction amplification of at least 20 loci, amplifying the loci, detecting the amplification products, wherein the amplification products and the loci to be amplified are characterized by the following features, each locus to be amplified is characterized by at least one deletion-insertion polymorphism known to be present in the population, wherein the two alleles from each locus differ in size by more than 2 nucleotides and less than 100 nucleotides, a first set of at least two amplification products ranging in size from about 20 nucleotides to about 300 nucleotides stemming from at least two different loci carries a first label, a second set of at least two amplification products ranging in size from about 20 nucleotides to about 300 nucleotides stemming from at least two different loci carries a second label, a third set of at least two amplification products ranging in size from about 20 nucleotides to about 300 nucleotides stemming from at least two different loci carries a third label, label one, label two and label three are each different fluorescent labels which can he differentiated and simultaneously detected by a multi-color detector in combination with, e.g. a DNA sequencing device.

DNA typing is commonly used to identify the parentage of human children and to confirm the linage of horses, dogs and other animals, and agricultural crops. DNA typing is also commonly employed to identify the source of blood, saliva, semen, and other tissue found at a crime scene or other sites requiring identification of human remains. DNA typing is also employed in clinical settings, for example the therapy of certain leukaemia, to determine success or failure of bone marrow transplantation in presence of particular cancerous tissues. DNA typing involves the analysis of alleles of genomic DNA with characteristics of interest, commonly referred to as "markers". Most typing methods in use today are specifically designed to detect and analyse differences in the length and/or sequence of one or more regions of DNA markers known to appear in at least two different forms in the population. Such length and/or sequence variations are referred to as "polymorphism". Any region, i.e. "locus" of DNA in which such variation occurs is referred to as "polymorphic locus".
When speaking about polymorphic DNA sequences one must distinguish in particular between the so called repeated polymorphic DNA sequences and non-repetitive polymorphic elements. In the study of DNA sequences one can distinguish two main types of repeated sequences; tandem repeats and interspersed repeats. Tandem repeats include satellite DNA. Satellite DNA consist of highly repetitive DNA and is so called because repetitions of short DNA sequence tend to produce different frequency of the nucleotides adenine, cytosine, guanine and thymine and thus, have different density from bulk DNA—such that they form a second or a "satellite" band in genomic DNA separated on a density gradient. A mini-satellite is a section of DNA that consists of short series of bases 10 to 100 bp. These occur in more than 1,000 locations in the human genome. Some mini-satellites contain a central (or core) sequence of letters "GGGCAGGANG" (where N can be any nucleotide) (N=UPAC code for A, C, G, T) or more generally a strand bias. It has been shown that the sequence per se encourage chromosomes to swap DNA. In alternative models, it is the presence of a neighbouring, cis-acting myotic double-strand break hotspot which is the primary cause of minisatellite repeat copy number variations.
Indispersed repetitive DNA is found in all eukaryotic genomes. These sequences propagate themselves by RNA mediated transposition and they have been called retroposons. Such retroposons are substantially larger than the repetitive elements discussed above.
So-called short indispersed nuclear elements (SINEs) are a further class of repetitive DNA elements. A particular type of SINEs are the so-called ALU-sequences. These are about 300 base pairs in length. Therefore, also these elements are not particularly useful for a simple and straight forward profiling assay.
Microsatellites are simple sequence repeats (SSRs) or also short tandem repeats (STRs) or polymorphic loci present in nuclear DNA and organelle DNA that consist of repeating units of 1 to 6 base pairs in length. They are used as molecular markers which have wide-ranging applications in the field of genetics including kinship and population studies. Microsatellites can also be used to study gene dosage (looking for duplications or deletions of a particular genetic region). One common example of microsatellite is (CA)n repeat, where n is variable between alleles. These markers are often present in high levels of inter- and intraspecific polymorphism. Particularly when tandem repeats number 10 or greater appear. The repeated sequences often simple, consisting of two, three or four nucleotides (di-, tri-, tetranucleotide repeats respectively) and can be repeated 10 to 100 times. CA nucleotide repeats are very frequent in human and other genomes, and are present every few thousand base pairs. As there are often extremely many alleles present at an STR locus, genotypes within pedigrees are often fully informative and the progenitor of a particular allele can often been identified. However, making use of these so-called STRs in genetic assays has the fundamental effect that due to the large variation within the population one may find in extremely high amount of alleles and said alleles when analyzing these on, e.g. in electrophoretic gel system will differ substantially in size.
When using, e.g. RFLP, the theoretical risk of a coincidental match is 1 in 100 billion (100,000,000,000). However, the rate of laboratory error is almost certainly higher than this, and often actual laboratory procedures do not reflect the theory under which the coincidence probabilities were computed. For example, the coincidence probabilities may be calculated based on the probabilities that markers in two samples have bands in precisely the same location, but a laboratory worker may conclude that similar—but not precisely identical—band patterns result from identical genetic samples with some imperfection in the agarose gel. However, in this case, the laboratory worker increases the coincidence risk by expanding the criteria for declaring a match. STRs have the same problem. This is due to the fact that many alleles exist for each locus and this complexity may lead to ambiguous amplification products which are than incorrectly assigned.
Systems containing several loci are called multiplex systems and many such systems containing up to more than 11 separate STR loci have been developed and are commercially available. Although, amplification protocols with STR loci can be designed which produce small products generally from 60 to 500 base pairs (bp) in length and alleles from each locus are often contained within range of less than 100 base pairs. The substantial drawback with using STR loci is that due to the high variability within the population with respect to particular loci certain alleles may have a high number of repeats and thus, result in large amplification products. Design of these systems is limited, in part, by the difficulty in separating multiple loci in a single gel or capillary. This occurs, because there is spatial compression of fragments of different sizes, especially longer fragments in gels or capillaries, i.e. commonly used means for separation of DNA fragments by those skilled in the art. Although, the analysis of multi-allelic short tandem repeats (STRs) still has the largest impact on forensic genetics and case work, it must be said, that the systems are limited especially for DNA evidences of low quality and quantity. For example degraded DNA samples represent one of the major challenges of the major STR analysis as amplicon sizes within multiplex assays often exceed 200 base pairs. Degraded samples are extremely difficult to amplify.
At the same time focus has been put on so-called single nucleotide polymorphisms (SNPs), however, these SNPs are difficult to analyze because a given system must be able to identify a single nucleotide polymorphic position.
The present invention represents a significant improvement over existing technology, bringing increased power of discrimination, position and throughput the DNA profiling for linkage analysis, criminal justice, paternity testing and other forensic or medical and genetic identification applications. This is in particular due to the fact that the present invention makes use of a combination of a different type of polymorphic markers, i.e. the so-called frequent biallelic deletion-insertion polymorphisms (DIP).

Substances and methods for a DNA based profiling assay


A method for etching a copper layer in dry process includes the steps of forming a copper layer on a substrate, heating the substrate, etching the copper layer while using an etching gas. The etching gas includes iodine halide such as pentafuluoride, ioeine heptafuluoride, iodine monochloride and iodine trichloride. The copper layer is etched while sublimating cuprous iodide of a reaction product.

Recently a semiconductor tends to become high integration and high performance such as Very Large Scale Integration (VLSI) or Ultra Large Scale Integration (ULSI). Therefore a design rule of wiring pattern also tends to become fine such as submicron or quartermicron. Aluminum (Al) has been used as a wiring material in a semiconductor device. In this specification, aluminum (Al) means pure aluminum or a material, mainly including Aluminum. But aluminum wiring is easy to deteriorate a reliability owing to a deterioration of an electro-migration durability and/or a stress-migration durability when a wiring width is smaller than 0.5 .mu.m. Further a layer of a wiring becomes thick in order to get a low resistance. It makes an aspect ratio of a wiring pattern large such as from 1 to 2. It makes difficult to flat by a insulation layer in the latter process.
Thus because aluminum wiring has some problems as stated above, copper (Cu) wiring is used preferably. In this specification, copper (Cu) means pure copper or a material mainly including copper. Copper has a high electro-migration durability. The electric resistivity of pure copper is about 1.4 .mu..OMEGA.cm. It is about a half of the electric resistivity of pure aluminum. Therefore even though a wiring pattern of copper has the same width as a wiring pattern of aluminum has, a thickness of a copper film becomes thinner than a thickness of a aluminum film. It is advantageous to form a multi-film wiring.
But there are some problems to etch copper in dry process. The research for fine processing of copper is on the way.
Copper is very easy to be oxidized. A surface of copper is always covered by copper oxide (CuO) and a passive state. When copper oxide exists on a surface of copper, copper oxide obstructs a reaction between an etching gas and copper. It declines an etching velocity. And because copper oxide acts on copper as a mask, a spot of copper and/or copper oxide on a wafer is remained after an etching.
Further it is difficult for chloric gas used as an etching gas of aluminum to etch copper, because a vapor pressure of cuprous chloride being a reaction product is very low.
Some ideas have been suggested in order to solve these problems until now.
For instance, Japanese Journal of Applied Physics., Vol. 28, No. 6, p. L1070-1072 (1989) shows a reactive ion etching that a copper thin film is etched by a mixed gas of silicon tetrachloride (SiCl4) and Nitrogen (N2) while heating a wafer at the approximate temprature of 250.degree. C. This heating prevents a spot of copper and/or copper oxide from remaining on a wafer after an etching. The reactive product silicon nitride (SixNy) in a gaseous phase is utilized as a side wall protector, and anisotropic processing is performed.
Japanese laid open patent Hei 1-234578 shows that hydrogen (H2) of some percentages is added into an etching gas. Though copper oxide is produced at a surface of copper by a reaction with residual oxide at a high temperature, copper oxide is reduced by H2 added into an etching gas. Therefore copper is smoothly etched in dry process.
Further Japanese laid open patent Hei 3-295232 shows that a mixed gas of nitrogen (N2) and oxygen (O2), a gas having an oxygen atom and a nitrogen atom in a molecule and/or fluorine gas is added into an etching gas while heating a wafer at the temperature of less than 200.degree. C. Copper is sublimated in the form of copper nitrate ( Cu(NO.sub.3).sub.2 ) and removed in this process.
However the ideas stated above have some problems which must be solved.
At first, silicon nitride (SixNy) may be possible to be a particle contamination source when silicon nitride (SixNy) is utilized as a side wall protector.
Further when silicon nitride (SixNy) is utilized as a side wall protector or the copper oxide is reduced by H2 added into an etching gas, it is necessary to heat a wafer at a high temperature. It is impossible to use a resist mask as a etching mask at the high temperature. So heat-resisting material such as silicon dioxide (SiO.sub.2) is utilized as an etching mask. But it is difficult to remove the mask of silicon dioxide after etching because there is few solvent to have a selectivity between silicon dioxide and a interlaminar insulating film. If the mask of silicon dioxide is utilized as a part of a interlaminar insulating film without removing of the mask, surface steps of the wafer increase. A forming of an etching mask is an extra process itself. Further a heating of a wafer at a high temperature accelerates forming of a copper oxide film by residual oxygen in a chamber.
Meanwhile in the method of removing copper as copper nitrate, there is no active material of halogen in an etching reaction system. It means that a selective rate between a mask pattern and a interlaminar insulating film becomes large. Further it is advantageous that a resist mask is utilized as a etching mask, because a wafer is heated at a low temperature. But because an etching gas includes oxygen, a copper oxide film is formed on a surface of copper. An oxygen atom diffuses inside at the place formed a copper oxide film. It causes problems that a spot of copper and/or copper oxide remains on a wafer after an etching and a wiring resistance increases.


According to one embodiment, a semiconductor memory device includes a memory cell array and a controller. The memory cell array includes first, second, and third memory cells each of which stores k-bit data (where k is a natural number not smaller than 1). The first and second memory cells are adjacent to each other, and the second and third memory cells are adjacent to each other. Data is stored into the memory cells in an order of the first, second, and third memory cells. When reading data from the second memory cells, the controller reads data from the first and third memory cells, and changes read conditions for the second memory cell in accordance with the read data.

In a NAND flash memory, all or half of plural cells arranged in a row direction each are connected to write and read latch circuits through a bit line. A write or read operation is performed on all or half of the plural cells arranged in the row direction (for example, cells equivalent to 2 to 8 kB) at one time.
Units of writing and reading are referred to as pages, and one block is constituted by plural pages. Erasure of memory cells is performed in units of blocks. In an erase operation, electrons are pulled out of memory cells, thereby making threshold voltages negative. In a write operation, electrons are injected into memory cells, thereby setting threshold voltages to be positive.
Recently, a multi-level memory has been developed in which one of plural threshold voltages (hereinafter also referred to as threshold levels) is set to enable storage of data constituted by multiple bits. For example, when four threshold levels are given, 2-bit data can be stored in one cell. When eight threshold levels are given, 3-bit data can be stored in one cell. Further, when sixteen threshold levels are given, 4-bit data can be stored in one cell.
Meanwhile, there is a tendency that capacitive coupling between adjacent cells increases as elements are more micronized. Therefore, there is a problem that a threshold level of a cell which is written first changes when an adjacent cell is written. Therefore, there has been proposed that, when data is read from a word line WLn, data from a word line WLn+1 which is written after a word line WLn is read, and a read voltage for the word line WLn is corrected depending on a level of the data (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2004-326866).
However, an erasure level of cells connected to the word line WLn varies depending on a level of the word line WLn−1 written before the word line WLn. Therefore, there is a problem that a read margin for cells connected to the word line WLn decreases. Therefore, there is a demand for a semiconductor memory device which can suppress any influence of capacitive coupling with adjacent cells and accurately read even when an erasure level changes.

Semiconductor memory device capable of accurate reading even when erasure level changes