An operating system may be more efficiently initiated and restarted by making a virtual image of the configuration settings for a base system configuration. These settings may be stored and may be used to quickly initiate the system in its base configuration, for example, using an executive. The base configuration may be automatically modified in response to system hardware or software configuration changes. These changes may be stored with the base configuration information. When a crash occurs, the virtual image may be used to quickly restore the system without the necessity for rebooting the operating system.

This invention relates generally to operating systems and particularly to initializing and restarting those operating systems, for example, after power is initially turned on or after a crash has occurred.
When a computer system is initially turned on, a basic input/output system or "BIOS" begins to operate. The BIOS controls many important functions of the personal computer, such as how it interprets key strokes, how it puts characters on the screen, and how it communicates with other devices. The BIOS typically instructs the computer to test itself every time the user turns the computer on. To do this, the BIOS uses a power on self test or "POST".
When the personal computer starts, it typically first enters what is called the "real mode". The computer accesses a special memory location holding program instructions including a jump instruction pointing to the BIOS code. Initially, the BIOS instructs the system microprocessor to run through components of the system and determine whether they are operating properly. Next, any expansion boards which have been installed are checked, and thereafter, the microprocessor begins the actual bootup process. During the bootup process, the BIOS code may instruct the microprocessor to jump to a section of code instructing the microprocessor how to read the first sector of the system floppy, hard disk or CD-ROM drive. The microprocessor then loads the operating system to start actual computer operations.
The Windows.RTM. operating system is perhaps the most common operating system used in personal computers. It is an "open" system in that it is adaptable to different computer systems and it is adaptable to changing hardware on any given computer system. At least, in part, due to this openness, it takes a considerable amount of time for the Windows.RTM. operating system to start up. To some users, this delay may be an annoyance and, in some instances, the start up process may interfere with the way a system operates.
For example, set top personal computers are personal computers associated with television systems which combine television capabilities, both analog and digital, and computer capabilities, such as internet access. It is expected that users of set top personal computers will consider those computers to be akin to normal electronic appliances. Thus, the users may not be willing to accommodate delays in initiation or error messages on their television screens. For example, a user might simultaneously, in a picture-within-picture system, play a game running on the Windows.RTM. operating system and simultaneously watch television. If the game were to crash, an error message could appear on the screen which would interfere with normal television viewing and at least for a short period, the television picture would be affected by the computer crash.
In substantially all cases, users would benefit by a quicker initiation of program operations. This could occur in at least three areas. Initially, when the computer turns on, it would be desirable to begin operations as quickly as possible. Secondly, when a program error or crash occurs, it would be desirable to restart the computer as soon as possible. Similarly, when a variety of issues come up during the course of computer operation, some users may desire to simply restart the computer to avoid dealing with and identifying the source of the problem.
Current computer systems have some capabilities to speed the initiation of the computer system. For example, it is known to use a "fast on" capability which bypasses all or part of the POST routine. Similarly, some laptop computers have a suspend/resume operation. When desired, the user can press a suspend button and all the settings on the computer are stored. When the computer powers up thereafter, the computer recognizes that a suspend had occurred and immediately resumes operations exactly where the computer left off before. In addition, some computer systems work in an "always on" mode whereby it is never necessary, absent a problem, to reboot the computer system. For example, Windows.RTM. 98 will have an Advanced Configuration and Power Interface (ACPI) function which is akin to a computer system which is never turned off. Some simple computer systems, such as personal data assistants (PDAs), use what is known as a Real Time Operating System (RTOS) to allow the computer to start quickly.
None of the techniques described above help when a program has crashed. In each of these cases at least a substantial part of the startup operation must be re-done after a crash. This can result in substantial delay and it is an impediment to creating a seamless appearance to the system user. Thus, there is a continuing need for methods that enable operating systems to initiate and restart more quickly, for example, after a crash or when initially turned on particularly with open operating systems. Similarly in connection with specialized computer systems, such as a set top personal computer, it would be desirable make normal computer operations invisible to the user.

Initializing and restarting operating systems


An imaging device determines an in-focus position by contrast autofocus. The device includes a first optical system including a first lens and a first image sensor, a second optical system including a second lens and a second image sensor, a signal processing unit to read an image signal from at least one of the first image sensor and the second image sensor and generate an image for display, and a display unit to display the generated image. In the contrast autofocus, the signal processing unit reads a part of the image signal from the first image sensor and calculates a contrast value based on the read part of the image signal, and generates the image for display from the image signal read from the second image sensor.

Several types of AF function of an imaging device are known. One of them is contrast autofocus. The contrast autofocus is to move a focus lens of a main optical system having an image sensor, calculate a contrast value of a subject image from the image sensor in each lens moving step, and determine the position of the focus lens with the maximal contrast value as an in-focus position.
There has been a demand for increasing an autofocus speed. A known technique is to heighten the speed at which a subject image is read for calculation of a contrast value and thereby increase contrast AF speed.
To heighten the image read speed, for example, not image data of the entire image area but that of a part of the image area needed for a contrast value calculation is read from the image sensor (hereinafter, partial read process). Assumed that the read speed for the entire image area is 30 fps (30 images per second), the read speed for the partial image area can be 120 fps, for example.
The imaging device includes a main display unit on the back of a body to display a subject image acquired via an optical system. Users can take photos while viewing subject images on the display unit. Further, users can know the optimal shutter timing by visually checking an indication for the completion of AF process superimposed on the subject image. Thus, it is preferable to constantly display a subject image on the display unit during shooting operation.
However, there is a problem in the partial read process that a partially read image is not suitable for the user's visual check and image display may be disordered. In view of this, Japanese Patent No. 4050385 discloses an imaging device to temporarily stop the image display on the display unit during the contrast AF process and resume it after the completion of the process, for example.
Such an imaging device, however, still faces a problem that a subject image may move to outside the display area when the image display is resumed after completion of the AF process since the image display is stopped during the contrast autofocus process in which no image data is read from the entire image area.


A technique uses file system indirection to manage solid state devices (SSDs). Based on relocation of data on the SSDs from a first SSD storage block to a second SSD storage block, a flash translation layer (FTL) driver may update a per-volume indirection file to reference the second SSD storage block and no longer reference the first SSD storage block. Based on a mismatch between the per-volume indirection file and a buffer tree, the buffer tree is updated to reference the second SSD storage block. Alternatively, the FTL driver may create and insert an entry into a mapping table, wherein the entry may reference the first SSD storage block and also reference the second SSD storage block. The buffer tree may then be updated to reference the second SSD storage block based on the new entry, and the new entry may then be deleted after the buffer tree is updated.

Field of the Invention
The subject matter herein relates to management of solid state devices and, more specifically, to a technique for using file system indirection to directly manage the devices.
Background Information
To improve the performance and longevity of solid state devices (SSDs), such as flash devices, of a storage array, a flash translation layer (FTL) driver of a storage system (i.e., Peripheral Component Interconnect Express (PCIe) flash) may be utilized to perform one or more functions, such as wear leveling, garbage collection, and write amplification. To perform such functions, the FTL driver may relocate data from an original SSD storage block on the array to a new SSD storage block. As data is relocated on the SSDs, the FTL driver typically updates a FTL data structure, such as a FTL mapping table, maintained in memory of the storage system to keep track of the relocation of the data. The FTL mapping table typically translates a logical address associated with the data (e.g., as provided by an indirection data structure managed by a file system of the storage system) to a physical address associated with the SSDs (e.g., as provided by the FTL driver). However, updating and maintaining multiple data structures, including the mapping table, in memory with logical and physical addresses is costly in terms of computer resources (e.g., consumption of memory and translation processing).

File system indirection technique for directly managing solid state devices


A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.

A ferroelectric material refers to a material that can maintain electrical polarization in the absence of external electrical field. The electrical polarization in a ferroelectric material has a hysteresis effect, enabling encoding of a data bit as a polarization direction within the ferroelectric material. In a ferroelectric tunnel junction device, a change in the direction of polarization causes a change in tunneling resistance, which can be employed to measure the direction of the electrical polarization and extract the value of the data bit stored in the ferroelectric tunnel junction.

Gated ferroelectric memory cells for memory cell array and methods of forming the same

Taiwan Semiconductor Manufacturing Company Limited


The gas is preheated by means of at least one screen disposed transversely relative to the flow of gas penetrating into the enclosure. The screen is provided with passages for the flow of gas and is fixed inside a peripheral wall to define a channel to enable the gas to flow through the preheating apparatus, it is also provided with fins which project from its surface, the screen and the fins being made of a refractory sheet material, in particular a sheet of laminated graphite.

Chemical vapor infiltration is a method used, in particular, in the fabrication of composite materials, and in particular composite materials having a matrix of carbon or of a ceramic. A fiber reinforcing substrate or "preform" having substantially the same shape as a composite material part to be fabricated is placed inside an enclosure. The substrate is densified by progressively filling its pores by injecting a flow of gas into the enclosure. Under determined conditions of temperature and pressure existing inside the enclosure, a solid deposit of matrix material is formed on the fibers of the substrate, right into the core of the substrate, by one of the components of the gas decomposing or by a reaction taking place between components of the gas in contact with the fibers. Chemical vapor infiltration is continued until a desired degree of substrate densification by the matrix is achieved.
Chemical vapor infiltration techniques for densifying a fiber substrate with a carbon matrix or with a ceramic matrix are well known. A carbon matrix is generally obtained by cracking alkanes, in particular methane or mixtures of methane and heavier alkanes. Chemical vapor infiltration of refractory materials other than carbon is described in Document FR-A-2 401 888. For example, a silicon carbide matrix can be obtained by decomposing methyltrichlorosilane (MTS) CH.sub.3 SiCl.sub.3 in the presence of hydrogen H.sub.2.
In order to form a deposit of the desired nature (composition and crystal structure) on the surface of the substrate fibers, it is necessary for the gas to be at the required temperature when it comes in contact with the substrate. Otherwise, undesirable secondary species may be deposited. Thus, in the above-outlined example of a silicon carbide matrix being formed by decomposing MTS, gas at too low a temperature can cause a deposit of silicon to be formed.
That is why proposals have already been made to bring the gas into contact with a preheater apparatus prior to diffusing it into the substrate. Thus, in the installation described in document FR-A-2 594 119, the flow of gas that penetrates into the enclosure comes initially into contact with superposed and perforated preheating plates. Since the preheating plates are inside the enclosure, they are permanently at the inside temperature of the enclosure, which temperature is determined to provide optimum infiltration conditions. The gas flow is thus raised to the desired temperature while it is passing through the preheating plates and prior to coming into contact with the substrates to be densified. The preheater plates also have the function of trapping parasitic deposits since these deposits tend to form on the surfaces first encountered by the gas flow on penetrating into the enclosure.
However, the preheating plates of that prior installation are made of graphite, and are therefore heavy and bulky. Because of the considerable mass of those plates, the time taken to heat the enclosure and to stabilize its internal temperature to the desired value is increased. In addition, because of their bulk, the preheating plates significantly reduce the working volume inside the enclosure. However, it is necessary to obtain optimum filling of the inside of the enclosure with the substrates to be densified because of the very high cost of fabricating composite material pans by chemical vapor infiltration. This cost is the result, in particular, of the extremely long duration (generally several hundreds of hours) required by the infiltration process to achieve the desired degree of substrate densification.
In addition, it has been observed that varying degrees of densification within pans or between different parts densified simultaneously are obtained in composite material parts fabricated by means of an installation such as that described in above-mentioned document FR-A-2594 119. The densification gradient seems to be caused, at least in pan, by non-uniformity of the gas in the working volume of the enclosure and/or by non-optimum flow conditions for said gas. It is desirable for the densification gradient within a part made of composite material to be reduced to as small a value as possible so as to obtain a matrix with as little anisotropy as possible, thereby improving the properties of the composite material. When a plurality of parts are densified simultaneously, it is desirable to avoid too great a dispersion in the characteristics of the resulting composite materials.
An object of the invention is thus to provide improved preheating apparatus capable of preheating a flow of gas penetrating into an enclosure of an installation for chemical vapor infiltration.
More particularly, an object of the invention is to provide preheating apparatus which is less heavy and bulky than the graphite plates used in the prior art, and which provides gas that is more homogeneous throughout the working volume of the enclosure.

Apparatus for preheating a flow of gas in an installation for chemical vapor infiltration, and a densification method using the apparatus


When a nylon cord is used as a cutter for mowing weeds and lawns, extraction and replacement of the nylon cord are facilitated. A reel (5) having a cylindrical member (6) is inserted on a bearing (4) of a case body (1). A through hole (12) extends through the cylindrical member (6) to be perpendicular to the axis of rotation of the cylindrical member (6) outside the inner diameter portion of the cylindrical member (6). A guide member (14) having pawls (13) and a pin press (16) having pawl presses (15) are provided in the cylindrical member (6). End portions (15b) of the pawl presses (15) corresponding to trough portions (13b) are inclined with respect to the upper surface of a support flange (11) at an appropriate acute angle. A main shaft (20) is inserted in the bearing (4). A stopper pin (22) to engage with the guide member (14) is provided in the main shaft (20). A coil spring (25) is provided between the main shaft (20) and a cap (23) to bias the main shaft (20), thereby enabling guiding and engagement of the stopper pin (22).

To mow weeds and lawns around a wall, a fence, an iron pole, or the like, or at a place where many obstacles exist, if a metallic (usually stainless steel) blade is used, sometimes the blade is chipped or pieces of an object cut by the blade are scattered to pose a danger. Hence, a cord, e.g., a nylon cord, is used as the cutter.
When a nylon cord is used as the cutter, in this manner, the wearing degree of the wound nylon cord is high, and the nylon cord is replaced every time it is worn. To replace the nylon cord, however, in a conventional rotary cutter, the nylon cord is taken out through a notched portion formed in the flange of the reel. Thus, when the nylon cord is to be replaced, all the components of the rotary cutter must be removed, the reel must be taken out from the case, a new nylon cord must be wound on the reel, and the reel must be set in the case. It is very cumbersome to perform this operation during mowing.
In the conventional rotary cutter, the nylon cord is extracted from the reel by the centrifugal force which is generated upon rotation of the rotary cutter when the mowing machine is operated. Thus, when the nylon cord is to be extracted because it has become short, a terminal member must always be pressed during rotation of the rotary cutter. During the extraction operation, the rotary cutter is not stably supported because it is rotated. When the terminal member is struck against a hard ground, not only the terminal member but also the case body is undesirably struck to damage the case body and the terminal member, causing a crack in or damaging them. Then, the rotary cutter becomes defective before it is fully utilized.
If the rotary cutter is not stably supported when the terminal member is struck, stones and lumps of soil are scattered upon striking to endanger the operator or people nearby.
It is an object of the present invention to provide a rotary cutter for a mowing machine in which a cord can be easily replaced, and when a nylon cord as the cutter is worn in an early stage, a necessary amount of nylon cord can be reliably extracted while rotation of the rotary cutter is stopped.

Kaminoho-mura, Mugi-gun, Gifu-ken 501-36


A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the gate electrodes. A first oxide is then formed over the structure and the n-type silicon regions are implanting with a p+ type dopant through the first oxide to form the source and drain regions of the p-channel transistor. A second oxide is formed over structure. The two oxide layers are then etched to provide sidewall spacers, having an inner portion formed from the first oxide and an outer portion formed from the second oxide. The p-type silicon regions are implanted with an n+ type dopant to form the low resistivity regions of the n-channel transistor. The p+ implants in the source and drain of the p-channel transistor typically outdiffuse toward the gates during further thermal processing of the device. The resulting integrated circuit has an LDD n-channel transistor and a p-channel transistor without an LDD region.

The present invention relates to CMOS integrated circuit device structures and fabrication methods, and more particularly to transistor doping profiles in self-aligned gate processes.
FIG. 1 shows a portion of a prior-art CMOS integrated circuit device formed on a substrate 10 and including representative p-channel and n-channel transistors 1, 3. The p-channel transistor 1 has a gate electrode 2 and the n-channel transistor 3 has a gate electrode 4, both electrodes formed over a gate oxide 24 and both separated by isolation dielectric 16. The gate oxide 24 and the isolation dielectric 16 overlie n-type 12 and p-type 14 silicon regions of the silicon substrate 10. Using conventional fabrication techniques, the n-type silicon region 12 is masked off and an n+ type dopant is implanted in the p-type silicon region 14 not covered by the gate electrode 4 or isolation oxide 16 to form the source and drain regions 6 of the n-channel transistor 3. Then, the n-type silicon region 12 is unmasked and the p-type silicon region 14 is masked. P+ type dopant is then implanted in the n-type silicon region 12 not covered by the gate electrode 2 or isolation oxide 16 to form the source and drain regions 5 of the p-channel transistors 1. The mask is then removed and the device formation is completed typically by depositing a dielectric over the transistors and forming connections to the source, drain, and gate of each of the transistors using conventional metallization layers.
As device size, and particularly channel length, is reduced, conventional drain structure MOS devices can become unreliable due to short channel effects, such as hot carrier effects. Conventional drain structure n-channel MOS devices 3 can become unreliable at longer channel lengths due to short channel effects than conventional drain structure p-channel MOS devices 1.
One way to overcome this problem is to modify the conventional drain structure such that the peak electric field at the drain edge is reduced. This can be done by reducing the drain doping density at the drain edge to produce a lightly doped drain (LDD) structure in the device. The LDD structure in the device may be formed by employing a sidewall spacer of silicon dioxide on the gate material.
FIG. 2 shows complementary n-channel 19 and p-channel 17 MOSFETs with LDDs 8, 11, which are typical of a plurality of such MOSFETs in a CMOS IC device. In a conventional process for forming LDD MOSFETs using CMOS technology, n-type 12 and p-type 14 wells are defined in a silicon substrate 10 and are isolated by isolation oxide 16. The gate oxide 24 is then formed and polysilicon gate electrodes 20, 22 are patterned on the gate oxide 24. The p-type silicon region 14 is then masked off and p-type dopant is then implanted into the n-type silicon region 12 to form the LDD regions 8 of the p-channel source and drain regions 7. The p-type silicon region 14 is unmasked and the n-type silicon region 12 is then masked off. N-type dopant is implanted into the p-type silicon region 14 to form the LDD regions 11 of the n-channel source and drain regions 9. The mask is then removed. A layer of silicon dioxide 2000-5000 xc3x85 thick is deposited over the device and then the silicon dioxide is anisotropically etched back to form oxide sidewall spacers 13, 15 on the gate electrodes 20, 22. The p-type silicon region 14 is again masked off and p+ dopant is implanted into the n-type silicon region 12 to form the p-channel source and drain regions 9. The mask is then removed. The n-type silicon region 14 is masked off and n+ dopant is implanted to form the n-channel source and drain regions 9. The device processing is completed using conventional techniques to form conductive interconnect and insulating layers.
A problem in employing the known sidewall spacer technology in the manufacture of an LDD device is that the p-channel devices must be masked during the LDD processing of the n-channel devices, and the n-channel devices must be masked during the LDD processing of the p-channel devices, since the LDD implant penetrates all unmasked areas of the CMOS device being fabricated. Accordingly, an extra masking layer is required to protect areas of the n-channel devices during the manufacture of the p-channel devices and another extra masking layer is required to protect areas of the p-channel devices during the manufacture of the n-channel devices.
FIGS. 3 shows two of a plurality of complementary n-channel 23, and p-channel 21, MOSFETS with LDDs 8, 11 manufactured according to a conventional method of manufacturing LDD devices using removable sidewall spacers. The n-type and p-type wells 12, 14 are defined in the silicon substrate 10 and are isolated by isolation oxide 16. Gate oxide 24 is then formed and polysilicon gate electrodes 20, 22 are patterned on the gate oxide 24. A layer of oxide or nitride is deposited over the device and is then anisotropically etched back to form sidewall spacers adjacent to the gate electrodes 20, 22. The p-type silicon region 14 is masked off and p+ dopant is implanted into the n-type silicon region 12 to form the p-channel source and drain regions 7. The mask is removed and the n-type silicon area 12 is masked off. N+ dopant is implanted to form the n-channel source and drain regions 9. The mask is removed and then the sidewall spacers are removed. The p-type silicon region 14 is then masked off and p-type dopant is implanted into the n-type silicon region to form the LDD regions 8 of the p-channel source and drain regions 7. The p-type silicon region 14 is unmasked and then the n-type silicon region 12 is masked off. N-type dopant is implanted into the p-type silicon region 14 to form the LDD regions 11 of the n-channel source and drain regions 9. The mask is then removed. The device processing is completed using conventional techniques to form conductive interconnect and insulating layers.
One problem with using the removable sidewall spacer technology in the manufacture of an LDD device is that again the p-channel device must be masked during the LDD processing of the n-channel device, and the n-channel device must be masked during the LDD processing of the p-channel device. Another problem is that the sidewall spacers must be removed by an etch process before the LDD implants. Accordingly, in addition to the two extra masking layers required during the manufacture, one in the manufacture of the p-channel devices, and one in the manufacture of the n-channel devices, an extra etch is also required in the manufacture of the device.
Alternatively, the removable sidewall spacer technology can be used with only two masking steps, as described in Campbell et al., xe2x80x9cMOSFET and Fabrication Method,xe2x80x9d U.S. Pat. No. 5,087,582, assigned to Inmos Ltd. Still referring to FIG. 3, after the p+ dopant is implanted into the n-type silicon region 12 to form the p-channel source and drain regions 7, while the p-type silicon region 14 is masked off, the sidewall spacers above the n-type silicon region 12 are removed and p-type dopant is then implanted into the n-type silicon region 12 to form the LDD regions 8 of the p-channel source and drain regions 7. The mask is removed and then the n-type silicon area 12 is masked off. N+ dopant is implanted to form the n-channel source and drain regions 9. The sidewall spacers above the p-type silicon region 14 are removed. N-type dopant is implanted in to the p-type silicon region 14 to form the LDD 11 regions of the n-channel source and drain regions 9. The mask is then removed. The device processing is completed using conventional techniques to form conductive interconnect and insulating layers.
A problem with using this alternative removable sidewall spacer technology in the manufacture of an LDD device is that the sidewall spacers must be removed from the p-type silicon region by an etch process before forming the LDD implants in the n-channel transistor, and the sidewall spacers must be removed by a separate etch from the n-type silicon regions before forming the LDD implants in the p-channel transistor. Accordingly, an extra etch is required during the manufacture of the p-channel devices and another extra etch is required during the manufacture of the n-channel devices.
A method of fabricating an integrated circuit having n-channel and p-channel transistors in a CMOS device is provided in accordance with the present invention. The method includes forming gate electrodes over n-type and p-type silicon regions that define isolated active areas of the device, implanting an n-type dopant into the p-type silicon to form LDD regions of the n-channel transistor. A first insulating layer is then formed over the gate electrodes and the n-type silicon regions are then implanted with a p+ type dopant impurity to form the low to resistivity source and drain regions of the p-channel transistor. A second insulating layer is formed over the first insulating layer. The first and second insulating layers are then etched to provide the sidewall spacers. The p-type silicon regions are then implanted with an n+ type dopant impurity to form the low resistivity regions of the n-channel transistor.
The resulting CMOS integrated circuit has a plurality p-channel transistors formed in active surface areas of n-type regions and a plurality of n-channel transistors formed in isolated active surface areas of p-type regions. Each of the p-channel and n-channel transistors has a gate electrode which overlies and is insulated from the respective active surface. The integrated circuit further contains p-channel source and drain regions each consisting of a low resistivity region, and n-channel source and drain regions, each having a low resistivity region and an LDD region. Each gate electrode having a pair of sidewall spacers having an inner and an outer portion each corresponding to an underlying source and drain region. Each p-channel low resistivity region is located under the outer portion and at least a part of the inner portion of its respective sidewall spacer. Each n-channel low resistivity region is located under at least a part of the outer portion and a part of the inner portion of its respective sidewall spacer. Each n-channel LDD region extends from its respective low resistivity region to underlie the inner portion of its respective sidewall spacer.

CMOS integrated circuit device with LDD n-channel transistor and non-LDD p-channel transistor


An apparatus and method for rapid fractionation of hydrocarbon phases in a sample fluid stream are disclosed. Examples of the disclosed apparatus and method include an assembly of elements in fluid communication with one another including one or more valves and at least one sorbent chamber for removing certain classifications of hydrocarbons and detecting the remaining fractions using a detector. The respective ratios of hydrocarbons are determined by comparison with a non separated fluid stream.

There is a need for a real-time, in-situ determination of the relative ratios between volatile (VOC) and semi-volatile (SVOC) hydrocarbons in sample fluid streams.
For example, increasingly stringent emissions regulations for diesel engines are resulting in tighter engineering targets for engine components. Exhaust gas recirculation (EGR) is a means for reducing NOX production by re-circulating a portion of exhaust gases from an engine back into the combustion chambers of the engine to reduce combustion temperatures. Such EGR streams are frequently cooled by use of a gas-to-water heat exchanger to enhance the cooling effect of the EGR gases on the overall combustion process. Historically, EGR coolers have not required high heat exchanger effectiveness. This is changing, however, because the low target temperatures for engine exit gases are being driven down even lower because of more stringent NOX emissions standards. This downward shift has resulted in similarly and related stringent requirements regarding heat exchanger effectiveness and issues with fouling of EGR coolers caused by particulate matter (PM) and (SVOC) deposition within gas flow paths.
Calibration to meet modern efficiency and emissions targets for diesel and other engines involves complex optimization of a large number of control parameters. Rapid assessments of PM emissions are already possible by, for example, the use of a tapered-element oscillating microbalance or an optical smoke meter. Relatively rapid total hydrocarbon measurements are possible by using a heated flame ionization detector (HFID). However, HFID measures all of the hydrocarbons present when in fact only a fraction of the overall hydrocarbons are culprits with regard to the fouling of EGR coolers. Historically, obtaining more information than is available with an HFID typically required speciation of the hydrocarbons using gas chromatography (GC). GC analysis provides much more information about the hydrocarbons than an HFID, but GC cannot be accomplished rapidly enough to support activities such as, for example, real-time engine calibration.
What is needed, therefore, is an apparatus and method for rapidly determining the relative ratios between VOCs and SVOCs in a sample fluid stream such as an exhaust gas mixture. More specifically, what is needed is an apparatus and method for rapidly determining the relative ratios between VOCs and SVOCs in the exhaust gas mixture of modern compression ignition and spark ignition engines.

Apparatus and method for rapid separation and detection of hydrocarbon fractions in a fluid stream


A process for continuous manufacturing of moisture-curable polyurethane formulations used as sealants and adhesives. The process is characterized by the fact that the reactive components are introduced independently, and without the need for a prepolymer, to a mixer. Solid or liquid raw materials can be either pre-blended or fed directly to the mixer, a twin-screw extruder, which provides the requisite energy to homogenously mix the raw materials and drive the chemical reaction. The process is designed so that the extruder barrel and screw allow variable feed addition and heat exchange down the length of the machine. This allows various operations to be performed at different points in the extruder, including reaction, dispersive mixing, distributive mixing and devolitization.

The present invention relates to a continuous process for production of moisture-curable polyurethane sealants and adhesives. The process is achieved using raw or preblended ingredients fed to a twin-screw extruder, but does not require the additional production resources involved in processing a prepolymer (i.e. pre-mixed reactive components).
Manufacturing polyurethane materials using a continuous process is not novel. The concept is covered in various articles, textbooks and patents. The current literature, however, is limited to processes that either include a pre-polymer manufacturing step (see U.S. Pat. Nos. 5,905,133 and 5,795,948), have a different polyurethane chemistry than moisture-cure sealants/adhesives with resultant performance characteristics that classify them as thermoplastics, elastomers or foams (see U.S. Pat. Nos. 6,624,278, 6,623,676, 6,040,381, 5,908,701, 4,661,531, 4,250,292, 3,963,679, and 3,642,964) or both (see U.S. Pat. Nos. 6,916,390, 6,294,637, 5,905,133, 5,795,948, 5,037,864, 4,879,322, 4,857,565, 4,742,095, and 4,342,847). The novelty of the proposed process lies in the use of a single machine to mix and react the moisture-curing formulation in-situ.
Polyurethanes are formed through the reaction of a multi-functional (functionality >1.0) polyol (—OH) with a multi-functional (functionality >1.0) isocyanate (—NCO). There are many applications and types of polyurethanes (elastomer, foam, thermoplastic, etc.), but this invention relates particularly to polyurethanes used as sealants and adhesives. In these formulations, the NCO/OH molar ratio can range from 1.5 to 3.0 in order to achieve the proper performance characteristics and maintain their liquid and/or thermoplastic state. In addition to these reactive components, most polyurethane adhesive formulations utilize ingredients that include but are not limited to fillers, tackifiers, plasticizers, antioxidants, catalysts, desiccants, pigments and viscosity modifiers.
The most common manufacturing method for polyurethane sealants and adhesives is to charge the raw materials, either manually or through an automated handling system, into a high-intensity batch mixer. Often a two-step or moisture-curable prepolymer approach is used. In the first step the polyol and isocyanate are pre-mixed in the desired ratio, possibly with several other ingredients, to form the prepolymer. In the second step this prepolymer is mixed with the remaining raw materials to achieve the final formulation. The prepolymer is typically formulated so that it can be used in several different finished products. As a result, while both production steps may occur in the same mixer, often a large quantity of the prepolymer is manufactured in the mixer for the first step then transferred to one or more secondary mixers to make several finished batches.
As an alternative to the prepolymer process, a one-step manufacturing approach may also be used. In the one-step approach, all of the raw materials are sequentially charged (again, either manually or through an automated raw material handling system) to a single, high-intensity batch mixer. In this approach the order of addition of the ingredients is important in order control the finished product quality. Once the product is complete it is transferred directly to the final packaging form and there is no need for a secondary mixing step.
While efficient mixing of the raw materials through energy transfer from the mixer is a primary requirement for adequate product quality, there are several other important process requirements for these formulations. Since the final product is moisture-curable, control of water in the process is critical. Moisture finds its way into the product either as a natural part of the raw materials as provided from the supplier or through exposure to environmental conditions, such as absorption of the moisture from humid air into the raw materials and/or finished product. For this reason, vacuum and/or chemical desiccation are used to remove excess moisture in the product and prevent premature curing in the packaging container. The application of vacuum in the mixing process is also used to remove the carbon dioxide gas, which is a natural by-product of the water and Isocyanate reaction.
Process temperature is another important control variable in manufacturing these materials. In either the single or two-step approach product temperatures can run from 125° F. to 250° F. depending on the nature of the raw materials and their thermal stability. These temperatures are selected to drive the urethane reaction (with or without the presence of a catalyst) and/or promote mixing depending on the stage of the process. High shear mixing blades are frequently used, which add heat to the process. Batch temperature is typically maintained by means of a heating and/or cooling medium (oil, water, etc.) that is circulated through an internal or external enclosure on the mixing vessel (coil, jacket, etc.) to add or remove heat depending on the process requirements.
Typical commercial process times depend on variables such as the formulation, raw material feed rates, scale of the equipment, manpower limitations, and heat transfer capabilities. In the two-step approach, standard batch times for each step can range from 2 to 6 hours. In a one-step approach, batch times may run between 4 to 12 hours.
Once the mixing process is complete the fully formulated product is transferred to the packaging line. To package the product, pressure is applied that allows the material to be injected into the container (typically cartridges, sausage-packs/chubs, pails or drums) for delivery to the customer.
The complexity of the polyurethane formulations and process make the batch manufacturing approach outlined above inefficient and undesirable. Several factors combine that cause the process to be labor and/or capital intensive:    a. The number of raw materials in the formulation and the limitations related to their order of addition requires a significant amount of automated material handling equipment or dedicated labor to manually charge the ingredients. When labor is used to fill this need, undesirable safety issues may be introduced such as operator exposure to chemical and/or ergonomic hazards. In some cases, manufacturers use a combination of automated equipment and labor to process the materials, depending on the nature of the raw material supply (bulk vs. non-bulk).    b. Product quality requirements often necessitate in-process quality testing to ensure critical product parameters, including but not limited to moisture content, are within specifications to proceed to the next process step. This is accomplished either through on-line instrumentation or by manually sampling the batch in the middle of the process. The former requires a high degree of capital investment and sophistication. The latter involves batch delays as samples are taken by the operator and brought to plant's QC laboratory for evaluation.    c. By their nature, moisture-curable polyurethanes quickly and easily build up and cure on equipment surfaces, particularly once the product is transferred and machinery is exposed to the moisture in the ambient air. Keeping equipment surfaces clean is a constant battle and cleaning must occur on a regular basis either to prevent contamination (for example from a cured piece of polyurethane coming loose in a subsequent batch or in the case of a product color change) or maintain equipment performance (such as keeping agitator blades clean for sufficient mixing). As a result, a fair amount of time and energy is often invested in cleaning the equipment. This is not only an issue in terms of the operator time invested in cleaning, but also creates the undesirable environmental and economic consequences related to solvent disposal.
In addition to the negative cost impact of the factors outlined above, there are additional productivity limitations associated with the batch process that further affect the manufacturing economics. These include but are not limited to:    a. The low surface area/volume ratio present in batch mixers. As the size/scale of batch mixers increases, there is more volume of the product in the mixer and less surface area (per unit volume) that is in contact with the walls (for heat transfer) or the exposed to the vacuum in the headspace (for mass transfer of moisture and/or carbon dioxide as outlined above). Since heat and mass are only transferred at these interfaces, the poor surface area/volume ratio in batch mixers will adversely affect batch times. The result is lower throughput and higher manufacturing costs per pound for the finished product.    b. In-process testing. If on-line instruments are not installed, the equipment must be shut down occasionally to check the quality. Idle time on the equipment while the sample is taken, brought to the lab and evaluated reduces the production capacity for the equipment.    c. Equipment cleaning. As outlined above, manufacturing moisture-curable sealants and adhesives requires frequent equipment cleaning. Since the equipment sits idle whenever it is being cleaned, this further reduces the production capacity and increases manufacturing costs.
These limitations combine to make the batch process unattractive from a capital or operational cost perspective, and possibly both. There are significant economic, safety, environmental and productivity gains that can be realized from an alternative production method that addresses the concerns outlined above.

Continuous process for the production of moisture-cure, polyurethane sealants and adhesives


The invention relates to a transmission arrangement (10) for a hybrid vehicle, comprising a housing (11), a transmission input shaft (12) and at least one transmission output shaft (13), a first planetary transmission set (PG1) having a first sun gear (zs1), a first ring gear (zr1) and a first planet carrier (c1) for a first planetary gear set (zp1) meshing with the first sun gear (zs1) and the first ring gear (zr1), also comprising a second planetary transmission set (PG2) having a second sun gear (zs2), a second ring gear (zr2) and a second planet carrier (c2) for second planetary gear set (zp2) meshing with the second sun gear (zs2) and the second ring gear (zr2), wherein the transmission input shaft (12) is rotationally fixed to the first planet carrier (c1), and the first ring gear (zr1) and the second ring gear (zr2) are permanently connected to one another and are rotationally fixed to the transmission output shaft (13), further comprising a first electric machine (E1) and a second electric machine (E2), wherein the first electric machine (E1) is in permanent driving engagement with first sun gear (zs1) and the second electric machine (E2) is in driving engagement with the second sun gear (zs2) in at least one operating mode, and wherein the first sun gear (zs1) can be connected to the housing (11) via a first switching element (S1). According to the invention, the second planet carrier (c2) is fixedly connected to the housing (11) and the second electric machine (E2) is drivingly engaged or can be drivingly engaged to the second sun gear (zs2).

The invention relates to a transmission arrangement for a hybrid vehicle, comprising a housing, a transmission input shaft and at least one transmission output shaft, a first planetary transmission set having a first sun gear, a first ring gear and a first planet carrier for a first planetary gear set meshing with the first sun gear and the first ring gear, a second planetary gear set having a second sun gear, a second ring gear and a second planet carrier for a second planetary gear set meshing with the second sun gear and the second ring gear, wherein the transmission input shaft is rotationally fixed to the first planet carrier and the first and second ring gear are permanently connected to each other and are rotationally fixed to the transmission output shaft, further comprising a first electric machine and a second electric machine, wherein the first electric machine is in permanent driving engagement with the first sun gear and the second electric machine is driving engagement with the second sun gear in at least one operating mode, and wherein the first sun gear can be connected to the housing via a first switching element.
Furthermore, the invention relates to a method for operating a hybrid vehicle with a transmission arrangement of the aforementioned type.
From DE 10 2013 113 344 A1 a power transmission system for a hybrid electric vehicle having a first and a second planetary transmission set is known, one of which is designed as a minus gear and the other as a plus gear. A first electric machine and a second electric machine are arranged coaxially to the transmission input shaft, wherein the first electric machine is firmly connected to the sun gear of the first planetary transmission set and the second electric machine is firmly connected to the sun gear of the second planetary transmission set. The planet carriers of the two planetary transmission sets can be rotatably connected to each other via a friction clutch. The sun gear of the first planetary transmission set can be held by a first friction brake and the planet carrier of the second planetary transmission set by a second friction brake.
DE 10 2013 226 472 A1 describes a power transmission system for a hybrid vehicle with a first planetary gear set and a second planetary gear set. The planet carrier of the first planetary gear set is connected to the output shaft of an internal combustion engine. The ring gears of the two planetary gear sets are interconnected and act on a drive unit. The planet carrier of the second planetary gear set can be held by a brake. The planet carrier of the first planetary gear set can be connected to the ring gears via a coupling. Furthermore, the sun gear of the first planetary gear set is connected to a first electric machine and the sun gear of the second planetary gear set is connected to a second electric machine.

Transmission arrangement for a motor vehicle and method for operating a hybrid vehicle


An apparatus for providing electrooptic modulation. The apparatus includes electrical contacts, a waveguide coupled between the electrical contacts, and a nonlinear optical material positioned in the slot region. The waveguide includes a first arm and a second arm that are each arranged to define a slot region for confining an optical mode. The slot region has a height, t1, and each of the first arm and the second arm include a strip load region having a height that is less than the height, t1, of the slot region. Each of the first arm and the second arm is configured to provide an electrical signal to the slot region via at least one of the electrical contacts. In one embodiment, the nonlinear optical material includes a χ2-based material. In another embodiment, each of the first arm and the second arm have an “L”-type shape.

A slot waveguide is an optical waveguide that guides light and strongly confines the guided light by capitalizing on the discontinuity of an electric field at high-refractive-index-contrast interfaces. A slot waveguide typically includes two regions of high-refractive-index material separated by a gap, or slot, having a low-refractive-index. The high-refractive-index material is typically covered by a cladding material.
Nonlinear electrooptic polymers can be used as a cladding material and can also be simultaneously incorporated into the slot of the slot waveguide. Basically, the use of such materials allows for a sufficiently high power flux (or "fluence," a term of art) in the material by exciting nonlinear behavior, meaning that the properties of the material change with the input optical power. This kind of effect is very often described through the use of, for instance Chi2 (χ2) and Chi3 (χ3) which are material dependent constants that describe the strength of two of the relevant nonlinear optical activities of a material. Some nonlinearities, which are material dependent, will work at the full optical frequency, while others are slower. Recently, engineered organic materials have begun to be used for nonlinear optics, because they can be designed to have extremely large χ2 and χ3 moments.

Geometries for electrooptic modulation with χ

University of Washington through its Center for Commercialization


A buffering portion of boundary layer flow along a flight vehicle surface diverted into an internal cavity at a downstream edge of a surface mounted window isolating recirculating flow of the diverted fluid through the cavity while it is cooled therewithin. Outflow of the cooled buffering fluid from at an upstream edge of the window is conducted into the buffering portion of the boundary layer flow to cool the window and prevent damage thereof by aerodynamically generated heating of the surface under high velocity flight conditions.

This invention relates generally to the cooling of windows placed on high speed flight vehicles.
Certain modifications of flight vehicle surfaces for aerodynamic drag reducing purposes have been proposed and tested, involving in common diversion of boundary layer flow into a surface cavity to establish a passive internal circulating flow for drag reduction purposes. One of such modifications includes the use of a porous cavity partition within a surface recess through which circulating flow is conducted to reduce surface drag by control of internal cavity flow. According to another of such surface modifications, a pivoted drag head mounted flush with the surface is utilized to control circulating flow within the cavity. An important discovery of the present invention resides in the use of certain diverse aspects of the foregoing surface drag reducing techniques to provide for windows cooling in a novel and unexpectedly beneficial manner.
It is therefore an important object of the present invention to provide a method and means for cooling windows in flight vehicle surfaces, otherwise subjected to aerodynamic heating damage, in a less expensive manner and without excessive addition of burdensome weight to the flight vehicle.

The United States of America as represented by the Secretary of the Navy


A system for estimating a parameter selected from the group consisting of a current, a magnetic field, or combinations thereof comprises a resonant frequency tunable magneto-optical loop resonator, wherein the loop resonator comprises a magneto-optical sensing element coupled to an optical waveguide, and wherein the loop resonator is configured for receiving an originating optical signal from a broadband light source and providing a modulated signal indicative of the estimated parameter.

The invention relates generally to sensors. The invention particularly relates to magneto-optical current and magnetic field sensors.
Conventional transformer-based current sensors are large in size for field operations and tend to saturate at high voltages or currents. Alternative current sensors, such as optical current sensors, typically rely upon the Faraday effect of the magnetic field created by the current to alter the polarization of light propagating in a fiber near the conductor. The method for extracting this information from the fiber is very intricate and costly. In one example, complex active power supplies are located at line potential. Fiber-optic current sensors based on polarimetric methods require stringent control on the polarization state. The components for polarization measurement are usually based on costly bulk optical components and maintaining the alignment through a number of these types of components becomes a challenging task. Furthermore, cascading polarimetric current sensors for distributed sensing applications may not be practical due to system complexity.
Measurement of currents flowing in high-voltage environments is also highly desirable, especially in power transmission and distribution systems. Transmission and distribution systems react dynamically to changes in active and reactive power. For power transmission to be economical and the risk of power system failure to be low, reactive compensation systems are desirable, particularly systems capable of simultaneously monitoring current flow at several points on a grid.
There is a need therefore for low cost current metering and instrumentation. There is a particular need for a current measuring system that allows for multiplexing, which can be economically scaled and used in applications where instrumentation of multiple channels is required.


An adjunct part can be secured to a host part, where the host part defines a recess configured to allow a threaded fastener to secure the host part to a further part. The adjunct part has a resilient boss projecting therefrom and adapted to enter the recess, the boss having an axially extending opening to receive a threaded tightening member. The boss and the threaded tightening member have configurations which allow the tightening member, as it advances into the boss along the opening, to resiliently urge portions of the boss radially outward into binding contact with the interior of the recess, thereby fastening the adjunct part to the host part.

This invention has to do generally with moulded enclosures of the kind widely used for industrial or home devices, such as telephones, radios, etc.
It would be of advantage to be able to attach an adjunct enclosure to an existing set which lacked any pre-designed features to allow attachment. In the past, additional hardware would have to be provided to co-locate the two parts, thus adding to the cost and complexity of the installation.
The main feature of this invention allows an adjunct enclosure to be attached to a host enclosure utilizing a common detail on the host enclosure, that detail being the recessed screw hole employed to hide the screws that hold the host enclosure together. This can be accomplished without requiring any change to the host enclosure or disassembly of the screws on the host enclosure.
More particularly, this invention provides, to facilitate the attachment of an adjunct part to a host part, in which the host part exhibits a recess with an internal surface:
the combination, with the adjunct part, of a resilient boss projecting from the adjunct part and adapted to enter said recess, the boss having an axially extending opening to receive a threaded tightening member, the boss and the threaded tightening member further having configurations which allow said tightening member, as it advances into the boss along said opening, to resiliently urge portions of said boss radially outward into binding contact with the internal surface of the recess, thereby fastening the adjunct part to the host part.
Further, this invention provides a method of attaching an adjunct part to a host part, in which the host part exhibits a recess with an internal surface, the adjunct part having a resilient boss projecting from the adjunct part and adapted to enter said recess, the boss having an axially extending opening to receive a threaded tightening member, the boss and the threaded tightening member further having configurations which allow said tightening member, as it advances into the boss along said opening, to resiliently urge portions of said boss radially outward,
the method including the steps:
a) inserting the boss into the recess, and
b) screwing said threaded tightening member into said opening, so that as the tightening member advances into the boss along said opening, said portions of the boss are urged radially outward into binding contact with the internal surface of the recess, thereby fastening the adjunct part to the host part.
Finally, this invention provides, in combination, a host part exhibiting a recess with an internal surface,
an adjunct part having a resilient boss projecting from the adjunct part and received within said recess, the boss having an axially extending opening in which is screwed a threaded tightening member, the boss and the threaded tightening member having configurations such that said tightening member, screwed fully into said opening, resiliently urges portions of said boss radially outward into binding contact with the internal surface of said recess, thereby fastening the adjunct part to the host part.

Method and apparatus for attaching moulded enclosures


Reflection type blank masks are provided. The blank mask includes a substrate, a reflection layer substantially on the substrate, at least one fiducial mark substantially on the reflection layer, an absorption layer substantially on the at least one fiducial mark and the reflection layer, and a resist layer substantially on the absorption layer.

1. Technical Field
Various embodiments of the present disclosure generally relate to photo masks used in fabrication of semiconductor devices, and to reflection type blank masks, methods of fabricating the same, and methods of fabricating reflection type photo masks using the same.
2. Related Art
As semiconductor devices become more highly integrated, sizes of circuit patterns constituting the semiconductor devices have been continuously reduced. Thus, there may be some limitations in realizing the fine patterns with a photolithography process utilizing ultraviolet (UV) rays. Accordingly, an extreme ultraviolet (EUV) lithography process has been proposed to form the fine patterns of the semiconductor devices. The EUV rays may have relatively short wavelengths. For example, the EUV rays may have a wave length of about 0.2 nanometers to about 100 nanometers.
A reflection type mask may be used in the EUV lithography process. The reflection type mask may include a laminated reflection layer formed on a transparent substrate and absorption layer patterns (e.g., metal patterns) formed on the laminated reflection layer. The laminated reflection layer exposed by absorption layer patterns may reflects the EUV rays and the absorption layer patterns may absorbs the EUV rays. Planar images of the absorption layer patterns (or planar images of the exposed portions of the reflection layer) may be transferred on a wafer using a EUV lithography apparatus (e.g., an exposure apparatus) with the reflection type mask. During the EUV lithography process, the EUV rays may be irradiated on the reflection type mask. The absorption layer patterns may absorb the EUV rays while the EUV lithography process is performed. In contrast, the EUV rays irradiated onto the exposed portions of the laminated reflection layer may be reflected toward a resist layer coated on the wafer through a mirror optical system.
There are many issues in the development of the EUV lithography process. For example, the EUV lithography process may be affected by substrate defects of the reflection type masks used in the EUV lithography process. In particular, it may be difficult to fabricate blank masks without any defects because the laminated reflection layer of the EUV mask is formed by stacking a plurality of layers, for example, about eighty layers of molybdenum/silicon. In order to minimize the influence of the substrate defects (e.g., blank defects) on the lithography process, the coordinates and sizes of the blank defects should be accurately recognized.
Fiducial marks may be formed in the transparent substrate to increase the accuracy of the substrate defect inspection, and the fiducial marks may be used as reference position marks during inspection of the substrate defects. The fiducial marks may be formed by etching the mask substrate before the laminated reflection layer is formed. Thus, the fiducial marks may be formed to have a recessed shape. Meanwhile, the fiducial marks may be formed by coating a resist layer on the mask substrate, exposing the resist layer, developing the exposed resist layer, etching the mask substrate using the developed resist layer as an etch mask, removing the developed resist layer, and cleaning the etched mask substrate. Accordingly, additional substrate defects may be formed while the fiducial marks are formed. These substrate defects may be transferred on the wafer even through laminated reflection layer is formed on the mask substrate having the substrate defects. That is, the substrate defects may degrade the quality of the reflection type masks.

Reflection type blank masks, methods of fabricating the same, and methods of fabricating reflection type photo masks using the same


The stator is made of laminated stampings having congruent outlines defining the central opening for a rotor and also defining pole pieces which include horn-like portions spaced from the main body of the stamping to define winding slots for the coil. Each end of the assembly has a terminal board which has an outline generally congruent with the laminations. Two terminals are mounted in the supports carried by the terminal board adjacent each pole piece. The ends of the wire of each coil are led across the adjacent terminal, then back between the terminal and a tang formed from the terminal. Then the tang is pressed against the terminal and wire, and fused to complete the connection.

The field coil wires in the present type of electric motor are wound on the pole pieces and the ends are connected to terminals supported by the terminal block. The coil is wound and the connection of the wire to the terminals is handled by robotic machines. The final connection of the wire to the terminal is secured by crimping the terminal tang into the wire, and the connection is then fused by known technology to securely fix the wire to the terminal.
Most motors are not subjected to significant vibration but when the motor is used in certain kinds of hand tools the motor is subjected to substantial vibration or shock caused by the nature of the tool, such as hammer-drills, impact wrenches and rotary hammers. This impact or vibration causes relative movement between the terminal and the coil and this results in small but damaging flexure of the wire, leading to breakage of the wire which, of course, shuts down the motor and the tool. The breakage occurs approximately where the wire enters the tang. The wire enters the space between the tang and the terminal at essentially 90.degree.. The fusing process heats the copper wire enough so that it hardens and the pressure of the fusing tool against the tang coupled with the heat causes the wire to melt down a little bit at the point where the wire enters the space between the tang and the terminal. The combination of necking down and heating and hardening the wire, coupled with the vibration, sets up a combination of factors leading to breakage of the wire.


Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.

Phase locked loops (PLLs) are widely used in a variety of electronic applications and circuits including, but not limited to, telecommunications, computers, clock and data recovery circuits, frequency synthesizers, and analog-to-digital converts. PLLs may be implemented using analog components, digital components, and combinations thereof. Analog PLLs occupy large circuit areas, are susceptible to process, voltage and temperature variations, and have substantial power requirements as compared to digital PLLs. Digital PLLs, however, also suffer from certain disadvantages. For example, large loop gain factors are needed to guarantee loop stability and achieve high bandwidths in the digital PLL. Large loop gain factors, however, translate into high quantization noise and high jitter performance.
A technique for improving the performance of the digital PLLs is to use time to digital converters (TDC) as the phase detector. There are multiple drawbacks with using TDCs in digital PLLs. TDCs are very expensive in terms of power and area and performance of the PLL is limited by the resolution of the TDC. In addition, implementing the TDC in the digital PLL is complex. To achieve performance similar to analog PLLs, tens of femtoseconds of accuracy is required, which is very hard to achieve in advanced complementary metal-oxide-semiconductor (CMOS) technologies.
The conventional digital PLLs include low pass filters which use complex voltage domain adders, multipliers, and data to analog converters (DACs). These components are very expensive in terms of power and area. Moreover, the multipliers and DACs are high speed designs which are challenging to implement effectively and efficiently. In addition, the control signal produced from the low pass filter by these designs is in the voltage domain so either a varactor based narrow band LC oscillator is used or a coarse resolution digital voltage-controlled oscillator is used. These types of oscillators provide limited bandwidth controllability or have limited frequency resolution. In addition, non-linearity is high in digital voltage-controlled oscillators.
Fractional mode PLLs allow for the use of parameters with a wider range to fine control the filter bandwidth to minimize the quantization noise and optimize the overall output jitter. Known solutions result in unsatisfactory jitter, power, and area budget.

Apparatus and methods for digital fractional phase locked loop with a current mode low pass filter


A paper currency receiving system is constructed to include a paper currency take-up unit adapted for taking up paper currency inserted therein, a paper currency storage cabinet mounted in the paper currency take-up unit to collect paper currency, a paper currency holding down mechanism installed in the paper currency take-up unit and controlled to hold down inserted paper currency onto a spring-supported bearing plate in the paper currency storage cabinet, the paper currency holding down mechanism including a rack set driven by a motor through a transmission gear train to move a linkage in an out of the paper currency storage cabinet for setting collected paper currency in a stack, and a transmitter receiver module, which automatically cuts off power supply when a predetermined amount of paper currency collected in the paper currency storage cabinet.

1. Field of the Invention
The present invention relates to a paper currency receiving system for use in a ticket vending machine, money exchange machine, or the like and, more particularly to such a paper currency receiving system, which comprises a paper currency take-up unit, a paper currency storage cabinet installed in the paper currency take-up unit, a motor-driven paper currency holding down mechanism installed in the paper currency take-up unit controlled to set collected paper currency in a stack inside the paper currency storage cabinet, and a transmitter receiver module adapted to detect the amount of collected paper currency.
2. Description of the Related Art
A variety of ticket vending machines have been disclosed, and intensively used in parking lots, stations, public facilities for receiving paper currency and vending tickets. FIGS. 9, 10, and 11 show a paper currency receiving system used in a conventional ticket vending machine. The paper currency receiving system is generally comprised of a paper currency take-up unit adapted for taking up inserted paper currency, the paper currency take-up unit having a paper currency insertion slot and a paper currency transferring mechanism, a paper currency verification unit adapted for verifying the authenticity of inserted paper currency, and a paper currency storage cabinet adapted for collecting verified paper currency. When paper currency inserted through the paper currency insertion slot to the paper currency transferring mechanism in the paper currency take-up unit, the paper currency verification unit verify the authenticity of received paper currency. When verified, the paper currency transferring mechanism is started to transfer accepted paper currency to a paper currency holding down mechanism in the paper currency take-up unit. The paper currency holding down mechanism uses a motor to rotate an eccentric block, causing the eccentric block to move a follower plate into the paper currency storage cabinet to hold down received paper currency. This design of paper currency holding down mechanism is still not satisfactory in function. Due to limited contact area between the eccentric block and the follower plate, the follower plate may not be kept in balance when moved, thereby causing the received piece of paper currency to be wrinkled or jammed. Because much torsional force is needed to drive the eccentric block to move the follower plate, the motor bears much load during its operation, resulting in short service life. Further, this design of paper currency receiving system has no means to detect the amount of received paper currency. The worker must regularly visually check the paper currency storage cabinet to see if the paper currency storage cabinet has been in full or not. It is inconvenient to check the paper currency storage condition of the paper currency storage cabinet visually.
The present invention has been accomplished to provide a paper currency receiving system, which eliminates the aforesaid drawbacks. According to one aspect of the present invention, the paper currency receiving system comprises a paper currency take-up unit adapted for taking up paper currency inserted therein, a paper currency storage cabinet mounted in the paper currency take-up unit to collect paper currency, and a paper currency holding down mechanism installed in the paper currency take-up unit and controlled to hold down inserted paper currency onto a spring-supported bearing plate in the paper currency storage cabinet. According to another aspect of the present invention, the paper currency holding down mechanism comprises a motor, a transmission gear train, a linkage, and a rack set driven by the motor through the transmission gear train to move the linkage in an out of the paper currency storage cabinet for setting collected paper currency in a stack. According to still another aspect of the present invention, a transmitter receiver module is provided inside the paper currency storage cabinet to detect the amount of collected paper currency and, to automatically cut off power supply when a predetermined amount of paper currency collected in the paper currency storage cabinet.

Structure of paper currency receiving system for ticket vending machine or the like

International Currency Technologies Corp.


In one general aspect, a computer-implemented method includes identifying current choices with different verbosity levels for a current turn in a conversation; normalizing multi-dimensional verbosity vectors for each of the current choices to obtain a normalized value for each of the current choices; determining a state definition for the current turn in the conversation, utilizing the normalized values for each of the current choices; providing the state definition for the current turn in the conversation and the normalized values for each of the current choices to a trained reinforcement learning module; receiving, from the trained reinforcement learning module, a score associated with each of the current choices for the current turn in the conversation; and selecting one of the current choices to be entered for the current turn in the conversation, based on the score associated with each of the current choices for the current turn in the conversation.

The present invention relates to textual analysis, and more specifically, this invention relates to optimizing a verbosity of a response to a received question.
Automated question and answer (Q and A) systems are commonly used to perform a variety of customer service actions, from product and service purchases to customer support. It is desirable to have these Q and A systems provide natural, human-sounding responses to questions from users. Appropriate level of verbosity can improve conversation efficiency and reduce the cost of potential repairs caused by confusion. However, current Q and A systems are not able to analyze appropriate level of verbosity of their responses to provide such a natural response, in order to keep verbosity as low as possible while making sure that such response does not confuse the user that receives it, thereby requiring additional follow-up responses to address such confusion.

Adjusting a verbosity of a conversation turn

International Business Machines Corporation


A display driver system having a plurality of series-coupled display drivers which are synchronized by using the same conductor between adjacent display drivers for communicating display data and synchronization control signals. The display driver serially receives display information at a predetermined clock rate. One of the display drivers becomes a master over the remaining display drivers and provides synchronization data for the system. Each display driver selectively outputs either display information or control information at a single output terminal.

Various display drivers exist for controlling and driving a large class of electronic display devices, such as liquid crystal displays (LCDs), light emitting diodes (LEDs), and vacuum flourescent displays (VFDs). As a family of devices, these display drivers can be configured to accommodate many different applications. For example, commercially available LED display drivers can interface to individual lamps, to seven-segment LED displays, or to combinations of both. Furthermore, display drivers are often capable of retaining data, thereby reducing control overhead. Despite design enhancements, single display drivers are often constrained by a limited number of output terminals per display driver. As a result, display drivers are commonly cascaded to expand drive capacity when driving large electronic displays with many display elements. To further increase drive capacity, display data is multiplexed onto the output terminals.
As an example of previous techniques for increasing drive capacity, consider a driver display having a ten digit, seven segments per digit, LED display. In one previous system, the LED display is driven by a single display driver which contains seventy output terminals. However, the single display driver has an inordinately high package pin count and is cost effective only in very large displays. By applying cascading techniques, the LED display can be driven in a second known system by ten separate display drivers, each driver containing seven output terminals. This second system has an added advantage of employing smaller display drivers which are cheaper to manufacture and which have increased display flexibility when driving smaller displays. By further employing multiplexing techniques in addition to the cascading technique of the second mentioned system, the LED display can be driven in a third known system by two display drivers. Each display driver contains seven output terminals which are driven in a multiplexed by five fashion. If the multiplex or display refresh rate is sufficiently fast to escape human visual detection, the ten digit LED display appears to be driven continuously. Thus, by employing multiplexing and cascading techniques, large displays with many display elements have been driven by a relatively small number of display driver devices.
For proper operation, cascaded chains of display drivers must interface with a control unit, most likely a microprocessor or microcontroller, in order to load new display data. Further, in display systems which employ cascading to increase display capacity, data display refresh rates of individual display drivers must be synchronized prior to displaying data. This synchronization process has been accomplished by circuitry either internal or external to the display drivers.
A known synchronization technique which minimizes the number of control lines and allows limited autonomy in the cascaded display driver system utilizes a synchronous serial interface. In this technique, each display driver is connected to the control unit via an enable input and a data clock signal, while communication occurs between display drivers through both data out/in signals and a synchronization signal in separate signal paths. Generally, display data is loaded into the cascaded display driver chain by the control unit during an initial configuration period, followed by independent operation of the cascaded display drivers. During independent operation, data from internal display registers are placed on the output terminals and driven onto the display array. Synchronization of individual display driver rates occurs through a dedicated synchronization signal which is fed into all display driver devices.
In the aforementioned synchronization technique, five control signals are required to implement the synchronous serial interface. In medium sized packages of approximately twenty pins, the manufacturing cost for five control signals becomes prohibitively large due to a direct relationship between pins per device and packaging costs. Continued cost reduction of display drivers has become paramount because display drivers are typically high volume, low cost devices.

Synchronization method and circuit for display drivers


To prevent the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a small strength. A package for semiconductor devices is formed as a laminate (20) of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole regions or some regions of the insulating resin layers (20d to 20f) of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.

1. Field of the Invention
The present invention relates to a package, for semiconductor devices, for mounting semiconductor elements. More specifically, the invention relates to a package for semiconductor devices formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other and having, on one surface thereof, a portion for mounting a semiconductor element, or, further, having one or a plurality of insulating resin layers on the upper surface of the laminate of many layers and having, on the upper surface of the uppermost insulating resin layer thereof, a portion for mounting a semiconductor element, featuring improved junction strength in the junction portion between the semiconductor element and the semiconductor package. The present invention further relates to an interposer disposed between the semiconductor element and the semiconductor package.
2. Description of the Related Art
In many cases, in the conventional art, an insulating resin has been used alone as a material of insulating resin layers for a multi-layer package for semiconductor devices, comprising a laminate of many layers obtained by alternately laminating a plurality of conducting layers and insulating resin layers and, particularly, as a material of insulating resin layers for a multi-layer semiconductor substrate or a semiconductor package of which all the layers are formed by a build-up process. Therefore, the package for mounting the semiconductor element by itself has a small strength but a large coefficient of linear thermal expansion. In particular, if the coefficient of linear thermal expansion of the insulating resin layer is greatly different from the coefficient of linear thermal expansion of the semiconductor element that is mounted, thermal stress occurs between the semiconductor element and the package at the time of mounting the semiconductor element on the package in the step of reflowing the solder, causing a problem in that the package or the semiconductor element is damaged.
In order to enhance the strength of the semiconductor package, further, a multi-layer substrate is often produced by using an insulating resin layer by incorporating a glass cloth therein. When the multi-layer resin substrate incorporating the glass cloth is used, however, the via-holes or through holes tend to be deformed at the time of being perforated in the package by the irradiation with a laser beam. When the through holes are to be plated, further, the plating is not favorably accomplished. In such a case, too, the coefficient of linear thermal expansion of the insulating resin layer is about 15 ppm at the smallest which, however, cannot be brought close to the coefficient of linear thermal expansion of the semiconductor element itself any more.
In order to reinforce the semiconductor package, further, the package may be surrounded by a reinforcing material (stiffener). In general, however, the package has a coefficient of linear thermal expansion which is greater than that of the conventional reinforcing member. Therefore, when the semiconductor element is to be mounted on the package by reflowing the solder, the central portion of the package expands more than the outer peripheries making it difficult to accomplish a favorable electric connection to the semiconductor element.
If viewed from the side of the semiconductor element, further, the material used as the semiconductor element, usually, has a low dielectric constant and is very brittle and tends to be easily broken. Therefore, the stress must be decreased as much as possible in the junction portion between the semiconductor element and the package.
Related arts have been disclosed in the following documents. For example, Japanese Unexamined Patent Publication (Kokai) No. 11-163208 discloses the use of a prepreg obtained by using a nonwoven fabric of a liquid crystal polyester as a base material of multi-layer printed board, and impregnating it with a thermosetting resin component. Japanese Unexamined Patent Publication (Kokai) No. 2000-31642 discloses the use of a liquid crystal polyester or a polyarylate as a resin for forming an insulating layer on the built-up multi-layer circuit board, and roughening of the surface of the insulating resin sheet by sand-blasting. Further, Japanese Unexamined Patent Publication (Kokai) No. 2002-16173 discloses the insulating layer of the semiconductor device that is constituted by using a resin and a glass cloth, a nonwoven fabric of a glass, a polyamide-type nonwoven fabric or a liquid crystal polymer-type nonwoven fabric.
Japanese Unexamined Patent Publication (Kokai) No. 2000-323613 discloses a multi-layer substrate for semiconductor devices contriving the shape of the via-holes for interlayer connection in order to flatten the surface for mounting the semiconductor element as much as possible and to decrease the thickness as much as possible. Japanese Unexamined Patent Publication (Kokai) No. 2001-36253 discloses an insulating resin layer that is partly constituted by using a resin layer of a low elasticity to absorb stress generated due to a difference in the coefficient of thermal expansion from an electronic part such as a semiconductor element that is mounted. Further, Japanese Unexamined Patent Publication (Kokai) No. 2001-274556 discloses laminating a thermally expanding buffer sheet having a coefficient of thermal expansion of 6 to 12 ppm integrally on a printed wiring board on which a surface-mounting part is to be mounted to obtain a printed wiring board for surface mounting maintaining excellent reliability in the connection to the surface-mounted part. Japanese Unexamined Patent Publication (Kokai) No. 2002-83893 discloses a multi-layer wiring structure film having improved flatness using a metal base as a reinforcing material, laminating a multi-layer wiring structure film on a metal base made of a metal plate and having an opening for inserting a semiconductor element, inserting the semiconductor element in the opening of the metal base, and connecting a flip chip.
According to the prior art, as described above, problems have not been solved to a sufficient degree in regard to forming via-holes and through holes by using a laser beam, adhesion of plating in the through holes and strength of the semiconductor package itself. In the step of producing a semiconductor device, further, when the semiconductor element is to be mounted on the package by reflowing the solder, the central portion of the package expands more than the outer peripheries thereof due to a difference in the coefficient of linear thermal expansion between the central portion of the package on where the semiconductor element is mounted and the outer peripheries thereof due to the temperature, and stress occurs between the semiconductor element and the package, thus leaving problems. The problem has not been fully solved, either, concerning the stress between the semiconductor element and the package as a result of thermal expansion when the semiconductor element is in operation.


In some examples, a hysteresis comparator includes a series resistor portion including a plurality of resistors for dividing a power supply voltage, the series resistor portion generating a first midpoint voltage and a second midpoint voltage higher than the first midpoint voltage, a first comparator configured to compare the first midpoint voltage and a reference voltage, a second comparator configured to compare the second midpoint voltage and the reference voltage, and a flip-flop having a clock terminal to which an output signal of the first comparator is applied and a reset terminal to which an output signal of the second comparator is applied. In some examples, a hysteresis comparator further includes an OR gate to which output signals of the first comparator and the second comparator are applied, and an AND gate to which output signals of the first comparator and the second comparator are applied.

1. Field of the Invention
The present invention relates to, inter alia, a reset signal generator for microcomputers and a hysteresis comparator for use in such a reset signal generator.
2. Description of the Related Art
The following description sets forth the inventor's knowledge of related art and problems therein and should not be construed as an admission of knowledge in the prior art.
In an electronics device equipped with a controller using a microcomputer, in order to prevent an abnormal power-on operation of the device, it is always necessary to activate the microcomputer at a constant state by supplying a reset signal for resetting the operation to the microcomputer. Conventionally, a comparator is used as a reset signal generating circuit in which a power supply voltage which rises from when the power supply is turned on and a predetermined reference voltage are compared, an "H" level signal is generated when the power supply voltage reaches the reference voltage or above.
In an electronics device, etc., using a battery as a power source, however, the power-on voltage may sometimes rise insufficiently and fluctuate. In such a case, if the power voltage to be applied to the comparator fluctuates around the reference voltage, an "H" level signal and an "L" level signal will be generated alternately, resulting in repetition of reset signals. Thus, the reset of the microcomputer would not be established. Conventionally, in order to prevent the aforementioned false reset operation, a comparator circuit having hysteresis characteristics with respect to the power supply voltage was used in a reset signal generation circuit.
FIG. 3 shows a circuit diagram showing a structure of a conventional comparator circuit having hysteresis characteristics. In FIG. 3, the reference numeral "1" denotes a series resistor portion consisting of a plurality of resistors 1a to 1f connected in series between the power supply voltage Vdd and the ground potential, the reference numeral "2" denotes a reference voltage supply for generating a reference voltage Vref, the reference numeral "3" denotes a comparator for comparing the voltage of the connecting midpoint of the resistors 1c and 1d and the reference voltage Vref, the reference numeral "4" denotes an inverter for inverting the output of the comparator 3, the reference numeral "5" is an inverter for inverting the output of the inverter 4, the reference numeral "6" denotes a switch MOS transistor which is turned on/off by the inverted output of the comparator 3, and the reference numeral "7" denotes an output terminal for outputting the output of the inverter 5 to the subsequent stage. In this example, it is assumed that the resistors 1a to 1f constituting the series resistor portion are equal in resistance with each other.
In the initial condition, if the power supply voltage Vdd is 0 V, the comparator 3 outputs an "L" level signal, which in turn makes the switch MOS transistor 6 turn off. In this state, since the switch MOS transistor 6 is turned off, the midpoint voltage of Vdd/2 is generated at the aforementioned connecting midpoint.
After the power source is turned on, the power supply voltage starts to rise. In accordance with the rising of the power supply voltage, the midpoint voltage at the connecting midpoint of the resistor 1c and the resistor 1d also rises. When the midpoint voltage becomes higher than the reference voltage Vref, the output of the comparator becomes an "H" level. The output of the comparator 3 is inverted by the inventors 4 and 5, and thus an "H" level reset signal will be outputted from the output terminal 7. On the other hand, the "L" level output of the inverter 4 is applied to the gate of the switch MOS transistor 6 to thereby turn on the switch MOS transistor 6. Since the ON resistance value of the turned-off state switch MOS transistor 6 is very small as compared with the values of the resistors 1a and 1b, it can be assumed that the power supply voltage Vdd is applied to the connecting midpoint of the resistor 1b and the resistor 1c. Thus, the power supply voltage Vdd will be divided by a total of four resistors 1c to 1f, and the voltage of the connecting midpoint of the resistors 1c and 1d becomes 3 Vdd/4.
As will be understood from the above, as the output of the comparator 3 changes from the "L" level to the "H" level, the midpoint voltage of the resistors 1c and 1d changes from Vdd/2 to 3 Vdd/4, or rises from Vdd/2 to 3 Vdd/4. In other words, the reference voltage Vref drops seemingly. As a result, even if the power voltage fluctuates after the generation of the reset signal, generation of false reset signals can be prevented (see, e.g., Japanese Unexamined Laid Open Patent Publication No. H05-48014).
In the meantime, in a conventional circuit as mentioned above, low power consumption of the reset signal generating circuit can be attained by increasing the resistance of the resistors 1a to 1f which exerts a large influence on the reset signal generating circuit. A conventional circuit generally employs a resistor such as a silicon resistor having resistance of about KΩ. In order to attain the low power consumption, however, it is required to employ a resistor having a resistance of about MΩ. On the other hand, the reset signal generating circuit is integrated together with a microcomputer. Generally speaking, such integration causes a larger resistance area of a resistor having large resistance. Accordingly, in a conventional circuit, it is necessary to increase the area of the poly silicon resistor to attain the low power consumption, which in turn causes an increased area of the IC chip.
In order to solve the aforementioned problems, it can be considered to employ a device such as a MOS transistor or a diffused resistor having a larger resistance per unit area as the resistors 1a to 1f. In such a case, however, the impedance of the MOS transistor or the diffused resistor as a resistor and that of the switch MOS transistor do not always coincide with each other to satisfy the specification of the reset signal generating circuit, and therefore the change in resistor voltage dividing due to the switching between the ON state and the OFF state of the switch MOS transistor 6 becomes small. Accordingly, after the generation of the reset signal, the midpoint voltage of the resistors 1c and 1d does not become high sufficiently. In other words, the reference voltage does not seemingly become low sufficiently. This may cause false reset signals due to the fluctuation of the power supply voltage.
The description herein of advantages and disadvantages of various features, embodiments, methods, and apparatus disclosed in other publications is in no way intended to limit the present invention. For example, certain features of the preferred embodiments of the invention may be capable of overcoming certain disadvantages and/or providing certain advantages, such as, e.g., disadvantages and/or advantages discussed herein, while retaining some or all of the features, embodiments, methods, and apparatus disclosed therein.

Hysteresis comparator and reset signal generator