Described herein is a roller contact device wherein, upon moving a drive arm into a contact closing position, a pair of roller contacts are pressed across a pair of stationary contacts through a pair of bridge links and a pair of roller shafts by a pair of support shafts which are each forwardly pressed by a compression spring, thereby closing the contacts. In the event if there is a difference in height between the contacting surfaces of the two stationary contacts, the bridge links are inclined to hold the roller contacts securely in the contact closing positions.

1. Field of the Invention
This invention relates to a roller contact device suitable for use in a tap changer or the like, and more particularly to improvement in a roller contact device having a couple of roller contacts in parallel.
2. Description of the Prior Art
Illustrated in a sectional view in FIG. 1 is a conventional roller contact device as disclosed in Japanese Utility Model Publication No. 52-25638, in which indicated at lA and lB are a pair of stationary contacts and at 2 is a roller contact which is to be bridged to connect the two stationary contacts and rotatably fitted on a roller shaft 3. Denoted at 4A and 4B are a pair of support shafts which are supported in bores 5a and 5b for movements toward and away from the stationary contacts lA and lB, respectively. The support shafts 4A and 4B are provided with bores 4c and 4d respectively in the fore end portions to support the opposite ends 3a and 3b of the roller shaft 3 tiltably and rotatably therein. Indicated at 6 are stop rings which are fitted on rear end portions of the support shafts 4A and 4B, and at 7A and 7B are compression springs which are provided in the bores 5a for urging the support shafts 4A and 4B toward the stationary contacts lA and lB, respectively.
The above-described conventional device operates in the manner as follows.
In the contact closing position, the support shafts 4A and 4B are constantly pushed forward by the compression springs 7A and 7B due to the existence of a gap space between the drive arm 5 and each stop ring 6. Consequently, the roller contact 2 is pressed against the stationary contacts lA and lB through the roller shaft 3.
The roller shaft 3 is tiltably supported on the support shafts 4A and 4B, so that, in case there is a difference in height between the contacting surfaces of the stationary contacts lA and lB, the roller contact 2 is tilted to contact invariably both of the stationary contacts lA and 1B.
As the drive arm 5 is turned (in a direction perpendicular to the face of the drawing) by a contact opening operation, the roller contact 2 is disengaged from the stationary contacts lA and lB, and the support shafts 4A and 4B are each moved forward into a position where the stop ring 6 is abutted against the drive arm 5.
Although a single roller contact 2 is shown in the above-described conventional device, a pair of roller contacts are mounted in parallel as shown in FIG. 2 in a case involving an increased current capacity, using two sets of paired support shafts 4A and 4B and two sets of the compression springs 7A and 7B of FIG. 1.
The conventional roller contact device having a pair of roller contacts arranged in such a manner has problems or drawbacks that it requires an increased number of component parts as a result of the provision of two sets of support shafts 4A and 4B and two sets of compression springs 7A and 7B, which cause a number of steps in the machining process for forming bores in the drive arms to redouble and accordingly the assembling time to increase.


A device for aligning a vehicle with a next pass through a field comprises a camera which takes a corresponding natural picture. A receiver is provided for receiving a navigational signal from a navigational satellite system. A central processing unit is connected to the camera for receiving the natural picture and the receiver for receiving the natural satellite signal. The CPU generates a master signal comprising a video signal of the navigational picture, an actual indicator signal representing the actual position of the vehicle, and a desired indicator signal representing the desired position of the vehicle. A display is connected to the CPU for receiving the master signal and generating a master image comprising a natural picture image, an actual indicator image, and a desired indicator image. The vehicle is driven to cause an alignment of the actual indicator image with the desired indicator image.

This invention pertains to a method and apparatus for guiding a vehicle and more particularly to a method and apparatus for guiding a vehicle along sequential paths through a work area.
Many off-road vehicles, especially farm vehicles, utilize GPS guidance systems. In a farm vehicle, such a system can help an operator guide the vehicle in consistent paths across a working area. Generally these systems utilize abstract virtual images to represent the working area. An actual position icon may be superimposed on the virtual working area image to represent the vehicle's position within the working area. A desired path indicator image may be superimposed on the working area virtual image to show the desired path for the vehicle. The relative positions of the actual position icon and the desired path indicator indicate whether the vehicle is on the correct path, and what adjustment needs to be made to move towards the desired path.
These abstract virtual displays can be useful and satisfactory for guiding an operator down a straight path, in order for the operator to remain on the desired path. However, because the virtual display does not visually correspond closely with what the operator is seeing in the real world, it can be very difficult for an operator to correlate the virtual display on the screen with what the operator is seeing outside of the vehicle. Therefore, when it is necessary to maneuver the vehicle around an obstacle, or to turn the vehicle back to make a next path along the previous path, it can be difficult for the operator to correctly position the vehicle.

Method and apparatus for guiding a vehicle


A triggerable composition for two-stage, controlled release of a functional active chemical includes a trigonelline ester of a functional active with at least one hydroxyl group configured to release the functional active through a hydrolysis reaction upon contact with an aqueous medium, and an encapsulation material for encapsulating the trigonelline ester including a functional active, the encapsulation material triggerable to release the trigonelline ester upon the occurrence of an environmental stimulus. In other aspects, a viscous liquid or an absorbent article includes a triggerable composition for two-stage, controlled release of a functional active chemical, the composition including a trigonelline ester of a functional active with at least one hydroxyl group configured to release the functional active through a hydrolysis reaction upon contact with an aqueous medium, and an encapsulation material for encapsulating the trigonelline ester including a functional active.

The present disclosure pertains to a composition that controls the chemical release of functionally active components from a previously inactive and modified state. In particular, the present disclosure pertains to a composition that gradually or rapidly releases active chemical components upon the occurrence of specific environmental stimuli. The composition can be used in bandages, hygiene products, health care products and skin-contacting beauty products, as well as in consumer product applications. The present disclosure also relates to such bandages, hygiene products, health care products, beauty products and consumer products incorporating such chemistry.
A large number of functionally active chemicals are known for use with personal care and beauty products, hygiene products, health care related products, and skin-contacting products. For example, such actives include antimicrobial or antibacterial agents, antioxidant agents, antiseptic-type agents, skin-repairing agents, and fragrances. Unfortunately, many of these functionally-active chemicals are not stable or do not have ideal properties under various environmental conditions. For example, if such actives include volatile components such as those found in fragrances, they can dissipate into the surrounding environment upon exposure to air and humidity conditions. Therefore, such chemicals can demonstrate short shelf lives when in use, and can present serious packaging/storage concerns. As a result, costly packaging can be necessary for products incorporating such chemicals. This instability creates a significant limitation on the wide adoption of the potentially useful chemistry and limits the long-term efficacy of products incorporating such chemistry. Further, processing challenges such as elevated temperatures can exist, and, as a result, can present a need to limit exposure to environmental stimuli during manufacture.
Additional challenges presented by the use of such active chemicals include the difficulties involved with gradually controlling the release of such active chemicals, as well as the potential side effects and costs resulting from use of chemically degraded products. Other actives, such as antioxidants, are also often not stable when exposed to ambient conditions, such as the air of a user's pantry or storage closets. Antioxidants can readily be oxidized by oxygen in the air. Some skin-repairing chemicals are also not stable when exposed to the surrounding environment. For example, the skin-repairing agent retinol is not stable under ambient conditions without protection from the environment. In fact, it can become a skin irritant when its concentration is relatively high. Currently no proactive technology has emerged to be very effective to achieve both property modification and at the same time release-on-demand under mild conditions. For example, anti-oxidants such as vitamin C and vitamin A are often stabilized through the ester forms which are hydrolyzed into the active forms through enzymes when digested into bodies. In many cases, a large portion of the actives are wasted because they are not hydrolyzed and released to the desired locations. A need therefore exists for a versatile composition that effectively stabilizes functional chemical actives, and releases such actives upon demand, at a desirable rate and profile.
Attempts have been made to overcome the stability and storage limitations presented by such actives. For example, some have suggested stabilizing retinol by encapsulating it in pH-sensitive polymers and then releasing it at a later time by changing the solubility of the encapsulating matrix through a pH change. The encapsulated retinol still suffers significant degradation, presumably from oxidation. Others have suggested converting retinol into an ester as a proactive (a precursor to the retinol active), and then at a later time converting the ester into the active form by use of enzymes present in a user's body after delivery through a user's skin. With such methodology, however, only a small portion of the ester is used effectively by the skin layer and a majority of the esters are wasted by the system. Such a system can also actually lead to side effects when too much retinol ester is used to achieve effective dosages on the skin. Therefore, a need still exists for delivery compositions for skin-repair actives.
In connection with the delivery of fragrances (such as in connection with personal care absorbent products), it has been suggested to encapsulate fragrances in polymeric matrices for stabilization and delivery benefits. Even with such encapsulation technology, however, there is a further need for fragrance encapsulation technology that offers effective protection for such volatiles as well as a controlled release. Existing encapsulation chemistries for consumer products often leak or release prematurely. A continuing need exists for a material composition that both provides stability for unstable actives, and that provides for release of actives in a controlled manner.

Triggerable compositions for two-stage, controlled release of proactive chemistry


A tape cutter for cutting postage imprinted tape is disclosed. The tape cutter includes a cutting wheel which is moved by a motor from one side of the tape across the tape to the other side of the tape to cut it. The motor moves the cutting wheel across the tape in a given direction regardless of the direction of rotation of the motor shaft.

The invention disclosed herein relates generally to tape handling apparatus, particularly tape cutting systems and components thereof, and more particularly to tape cutting systems and components thereof for cutting tape in a mailing machine after imprinting thereof.
It s desirable for a mailing machine to process different sizes and types of mail quickly and efficiently. It is also desirable for a mailing machine to imprint postage and like indicia either directly on the mail piece or on a tape strip which is thereafter affixed to a mail piece that may be too large or too irregularly shaped to imprint postage indicia directly thereon. Moreover, for high-speed operation, it is desirable that the mailing machine selectively imprint either the mail piece or a tape without shutting down the machine to changeover from imprinting mail pieces to tape and vice versa. It is also desirable for a mailing machine to imprint different types of tape, for example, a tape having a water-activate adhesive and a tape having a pressure-sensitive adhesive.
The present invention is an improvement over the tape cutting module disclosed in U.S. application Ser. No. 135,107.


An optimum molding condition setting system for an injection molding machine comprises a molten material flow analysis component for analyzing resin flow, resin cooling and the structure/stength of molded products by using a designed mold model and also comprises an analysis result evaluation component for determining an initial molding condition and its permissible range in accordance with the analysis results. The initial molding condition is set into the injection molding machine and a test shot is carried out in order to check for a deficiency of a molded product. If a deficiency of the molded product is detected, a data of the deficiency is entered into a molding defect elimination component. After performing a convenient data processing based on the entered data, a cause of the molding defect can be inferred and a measure for the cause can be obtained with high efficiency and accuracy. Consequently, the molding condition can properly and immediately be corrected in accordance with data obtained by the molten material flow analysis component.

Conventionally, in case of molding a molten material such as resin and the like, a molding engineer has set an optimum molding condition by repeating a trial and error molding technique based on his previous experiences. For this reason, such a setting of the optimum molding conditions depends considerably on the engineer's ability, so that it is necessary to train the engineers to be skillful.
There has also been proposed such an engineer-supporting system that the optimum molding condition is theoretically obtained by analyzing a resin flow under a predetermined molding condition in a model mold which is designed on a computer and by evaluating the molding condition.
In case of carrying out an analysis of a resin flow to evaluate a molding condition in the system used for theoretically obtaining the optimum molding condition by such a model mold, it is essential to use knowledge based on previous experiences of an engineer skilled in a molding technique. There has been a problem how to introduce the engineer's knowledge into such a system and the problem has not yet been solved.

Optimum molding condition setting system for injection molding machines


A radar apparatus includes a transmitter, a receiver, and a signal processor. The transmitter outputs a radar wave. The receiver includes a plurality of receiving antennas and a plurality of receiving devices. Each of the receiving devices mixes a reception signal from the corresponding receiving antenna with a local signal and outputs a beat signal. The signal processor samples the beat signal while selecting one of the receiving devices in order with a selecting period that is less than a half of a sampling period. The signal processor samples the beat signal with the sampling period and derives position information of a target by pair matching of peaks of a rising-modulation signal and a falling-modulation signal of the beat signal.

A radar apparatus is disposed in a vehicle and is used as a safety device for collision prevention. As an example of a radar apparatus disposed in a vehicle, a frequency-modulated continuous wave radar apparatus (FWCW radar apparatus) is used. The FWCW radar apparatus can detect both a distance to and a relative speed of a target. The FWCW radar apparatus has a simple configuration and is appropriate for reducing a dimension and a cost.
The FM-CW radar apparatus transmits a transmission signal Ss, which is frequency-modulated with a triangular wave to have a frequency increased and decreased gradually in a linear fashion, and receives a wave reflected by a target as a reception signal Sr.
The reception signal Sr delays for a time Td for which the transmitted and received wave takes to travel from the radar apparatus to the target and back, that is, time depending upon the distance to the target, and the reception signal Sr is Doppler-shifted in frequency by Fd depending upon the relative speed of the radar apparatus and the target.
The reception signal Sr and the transmission signal Ss are mixed together by a mixer to produce a beat signal B, whose frequency is equal to a difference in frequency between the reception signal Sr and the transmission signal Sb. If the frequency of the beat signal B (hereafter, referred to as an upbeat signal Bu) when the frequency of the transmission signal Ss is increased (hereafter, referred to as a beat frequency in a modulated frequency-rising range) is defined as fu, and the frequency of the beat signal B (hereafter, referred to as a downbeat signal Bd) when the frequency of the transmission signal Ss is decreased (hereafter, referred to as a beat frequency in a modulated frequency-falling range) is defined as fd, a distance R to and a relative speed V of the target may be expressed as:
                    R        =                                            c              ·              T                                                      8                ·                Δ                                                                                F                                ·                      (                          fu              +              fd                        )                                              (        1        )                                V        =                              c                                          4                ·                F                                                                                0                                ·                      (                          fu              -              fd                        )                                              (        2        )            where c is a propagation speed of a radio wave, T is a period of the triangular wave for modulation of the transmission signal Ss, AF is a variation in frequency of the transmission signal Ss, and Fo is a central frequency of the transmission signal Ss.
In a radar apparatus disposed in a vehicle, it is important to measure the azimuth or angular direction of a target as well as the distance R to and the relative speed V of the target.
Japanese Patent No. 3,622,565 (corresponding to U.S. Pat. No. 6,292,129) discloses a radar apparatus capable of detecting an azimuth of a target. The radar apparatus includes a plurality of receiving antennas and a receiver. The receiver includes a receiver switch, a switching control circuit and a receiving circuit. The receiving antennas are divided into a plurality of receiving group. The receiver switch selectively establishes communication between one of the receiving antennas in each receiving group and the receiving circuit. The switching control circuit controls an operation of the receiver switch so as to change the communications between the receiving antennas and the receiving circuit in sequence in a cycle shorter than a cycle of a change in a frequency of a transmission signal. The receiving circuits mix the reception signals from the receiving antennas in each receiving group with a local signal to generate a reception signal Sr. The radar apparatus acquires azimuth information as well as a distance and a relative speed by pair matching of peaks of an upbeat signal Bu and a downbeat signal Bd output from a mixer and an arrangement of the receiving antennas which are selected at the time.
In a radar apparatus that derives information including a position of a target by pair matching of peaks of an upbeat signal Bu and a downbeat signal using a FMCM method, when a digital signal processing such as fast Fourier transformation (FFT) is carried out, a reception signal of a target that is present at a distance greater than a Nyquist frequency to a sampling frequency of the reception signal may be folded to a position less than the Nyquist frequency, the target at a long distance may appear at a short distance, and erroneous detection may be caused.


In an approach for debugging and simulating application runtime execution, a processor loads source code and logs into a debug tool. A processor generates log debug information including a log map, a log variable cross reference table, and a method call stack tree. A processor determines a plurality of log blocks based on log context in the logs and the method call stack tree. A processor maps the source code to the logs for each log block. A processor suggests a starting point and a breakpoint based on the log variable cross reference table and the log blocks. A processor compares a source code variable value to a log variable value and a source code execution path to a log execution path based on the mapping set between the source code and the logs. A processor simulates the source code variable value with the log variable value.

The present disclosure relates generally to the field of software debugging, and more particularly to debugging and simulating an application runtime execution by associating source code with logs.
In computer programming and software development, debugging is the process of finding and resolving bugs (i.e., defects or problems that prevent correct operation) within computer programs, software, or systems. Debugging tactics can involve interactive debugging, control flow analysis, unit testing, integration testing, log file analysis, monitoring at the application or system level, memory dumps, and profiling. Many programming languages and software development tools also offer programs to aid in debugging, known as debuggers.

Debugging and simulating application runtime execution

International Business Machines Corporation


A system and method for monitoring the use of consumable materials in packaging machines is provided. The system generally includes a plurality of packaging machines that are configured to selectively operate in first and second modes to perform different packaging operations, e.g., by using consumable materials at different consumable usage rates to form different packaging devices. A controller in each machine controls the operation of the machine in the different modes and is configured to communicate the consumable usage data via a port. A portable module can be electronically connected to each machine during a connection session to communicate with the controller and receive the consumable usage data. The data from the module is then received by a user interface that provides an indication to a user of the usage of the machines in the first and second modes, e.g., to indicate to the user which machines are being used to form which packaging devices and/or how much of the operation of the machines is being used to form each of the packaging devices.

The present invention generally relates to a system and method for monitoring packaging machines and, more particularly, to monitoring the use of consumables in packaging machines, such as foam dispensing machines, that are configured to selectively use consumable materials at various consumable usage rates for forming different types of packaging devices in different modes of operation.
Foam dispensing machines are conventionally used for a variety of packaging operations, such as for packaging an object in a container so that the foam provides a cushioned protection on one or more sides of the object during subsequent handling. One common packaging operation that is used for on-demand protection of packaged objects is foam-in-place packaging. In one foam-in-place packaging operation, a foam-forming composition is injected from a dispensing machine into a container, such as a corrugated board box, and the object, which is typically wrapped to prevent direct contact with the rising (expanding) foam, is surrounded by the foam as the foam expands to fill the void space between the object and the container. The foam-forming composition can be formed by mixing an isocyanate compound with a hydroxyl-containing material, such as a polyol (i.e., a compound that contains multiple hydroxyl groups), typically in the presence of water and a catalyst. The isocyanate and polyol precursors react to form polyurethane. At the same time, the water reacts with the isocyanate compound to produce carbon dioxide. The carbon dioxide causes the polyurethane to expand into a foamed cellular structure, i.e., a polyurethane foam, which serves to protect the packaged object.
A conventional automated apparatus for performing foam-in-place packaging produces foam-in-bag cushions by making bags from flexible plastic film and dispensing a foam-forming composition into the bags as they are being formed. As the composition expands to form a foam within a bag, the bag is sealed shut and typically is then dropped into a container holding the object to be cushioned. The rising foam again tends to expand into the available space, but does so inside the bag. Because the bags are formed of flexible plastic, they form individual custom foam cushions around the packaged objects. Exemplary types of such packaging apparatus are assigned to the assignee of the present application, and are illustrated, for example, in U.S. Pat. Nos. 4,800,708; 4,854,109; 5,027,583; 5,376,219; and 6,003,288, the entire disclosures of each of which are incorporated herein by reference. For example, foam-in-bag cushions can be formed using the SpeedyPacker™ foam-in-bag packaging system available from Sealed Air Corporation (Saddle Brook, N.J.). Packaging apparatuses, including the SpeedyPacker™ foam-in-bag packaging system, are further described in U.S. application Ser. No. 10/692,579, "Perforation Mechanism for a Foam-in-Bag Cushion and Method of Use," the entire disclosure of which is incorporated herein by reference.
In some cases, the same apparatus or equipment can be used to dispense foam for different types of packaging operations. For example, a single packaging machine can be configured to operate in multiple modes according to the type of packaging to be performed. In a first mode, the machine can be used to form single bags of foam, commonly referred to as wet bags. In this mode, the machine can use a continuous supply of a plastic film sheet to form individual bags. Each bag has a bottom edge and side edges that are sealed, and the bag is filled with foam-forming materials before the top edge is sealed and simultaneously cut, thereby freeing the single bag from the remaining sheet of plastic film. The width of the wet bag is dependent upon the width of the roll of plastic film being used. Common widths for use with the SpeedyPacker™ system are 8, 12, and 19 inches. The length of the bag is determined by the machine operator and can vary depending upon the specific application. The same machine can also be operated in a second mode for producing continuous foam tubes (CFTs). A CFT is a length of multiple foam-filled bags that are still connected, the bags comprising the CFT being generally smaller in size than a typical wet bag. For example, a typical CFT pattern using 19-inch wide film would comprise bags that are approximately five inches in length. A CFT is prepared similarly to a wet bag with the exception that when the top of the bag is sealed after introduction of the foam-forming components, it is not cut free from the remaining length of plastic film. Instead, the bag remains attached to the advancing plastic film and another bag is formed immediately thereafter (i.e., the bottom seal for the next bag is made immediately above the top seal of the previous bag). In this manner, a series of interconnected foam-filled bags is produced. The foam-filled bags are connected by lengths of plastic film that are not foam filled, each length of film connecting the foam-filled bags typically being between about 0.25 inches and about 1 inch.
The same film and foam-forming materials are typically used by the machine in the different modes of operation. That is, the machine can be loaded with a supply of film and a supply of foam-forming materials to be used when forming either wet bags in the first mode of operation or the CFTs during the second mode of operation. Thus, the machine may be so versatile that the type of operation of the machine cannot readily be determined by merely observing the rate of use of the film or the foam-forming materials. Further, the machines may be operated in numerous and/or remote locations such that data cannot easily be collected from the machines by merely observing the operation of the machines.
Thus, there exists a need for an improved system and method for monitoring the use of consumable materials in a plurality of packaging machines and thereby providing an indication of the use of the machines in the different packaging modes.

System and method for monitoring consumable usage in packaging machines


A method for sending a message from one host (16) to at least one other host, both of which are attached to a hardware subsystem (12) that is bidirectionally coupled to a mass data storage unit (14) includes (a) transferring a Send Message command through a channel (18) from a first attached host to the hardware subsystem, the Send Message command having at least one second attached host as an intended recipient; (b) buffering (20) at least a message payload portion of the Send Message command at the hardware subsystem and generating an unsolicited interrupt in the at least one second attached host; and (c) in response to the unsolicited interrupt, transferring a Request Message command through a channel from the at least one second attached host to the hardware subsystem for obtaining at least the message payload portion buffered at the hardware subsystem. The Send Message command may be a point-to-point message having a single other attached host as an intended recipient, or it may be a point-to-multipoint message having a plurality of other attached hosts as intended recipients. The hardware subsystem need have no knowledge of the message contents sent between hosts.

In a multiple processor environment it is typically the case that some mechanism exists for providing inter-processor communication (IPC). Reference in this regard can be had, as an example, to U.S. Pat. No.: 5,459,836, "Inter-Processor Communication Net", by Bruce E. Whittaker et al. In this approach each processor in a network of processors is provided with a hardware IPC unit that connects via an IPC signal network to the IPC hardware units of each of the other processors. Each IPC hardware unit provides equal access to the IPC signal network, and also permits multiple signal messages to be received and buffered until serviced by the software of the receiving processor. The software of the receiving processor is made aware of the arrival of a message through an interrupt that is generated by the receiving processor's IPC hardware unit.
Other message passing techniques, in particular interrupt-driven message passing techniques, can be found in commonly-assigned U.S. Pat. No.: 6,105,071, as well as in U.S. Pat. Nos.: 4,633,392, 5,999,969 and 6,321,289.
The use of interrupt-driven message passing techniques is generally preferred over the alternative of polling some status register or flag for an indication that a new message has arrived, especially in real-time, event-driven data processing systems where low latencies are desired.
As may be appreciated, the approach adopted by Whittaker et al. and others exhibits a number of disadvantages. For example, each processor is required to be burdened with carrying the IPC hardware unit, thereby increasing cost, complexity and power consumption. Second, this approach requires the use of a separate signalling bus for implementing the IPC signal network that is connected between the IPC hardware units, thereby further increasing cost and complexity. Third, and related to the first disadvantage, the ability to connect different types of processors from different manufacturers, or even different models of processors from one manufacturer, can become problematic, as each processor must include a compatible IPC hardware unit.
A further layer of non-trivial complexity would be added if it were desired to bidirectionally connect the processors to another hardware unit, e.g., if each processor were to connected to an associated one of a host adapter interface of a common mass storage controller, such as a disk or a tape controller. This is especially true if the messages sent between these processors related to the common shared resource. In this case real-time synchronization issues may exist, making the use of some separate and independent inter-processor signalling bus and IPC units less than desirable.
It is presently known in the art that processors, also known as hosts, can be connected to an associated one of a host adapter interface of a common direct access storage device (DASD), and that a shared DASD dataset can be used for sending a message to the attached hosts from the DASD, in conjunction with polling of the DASD dataset by the attached hosts to discover the existence of the message. However, and as was noted above, the use of polling is not an efficient use of software or the processing power of the host CPU.
Prior to this invention, a satisfactory solution to the problem of sending messages between processors, when the processors are all bidirectionally connected to a common hardware unit, was not known to exist.

Method and apparatus using attached hardware subsystem to communicate between attached hosts


Setting items in a print setting screen are updated and displayed in response to a changing operation. It is determined whether or not print settings are changed from the initial state. If it is determined that print settings are changed from the initial state, a test print button is displayed. If it is determined that print settings are not changed from the initial state, a full print button is displayed.

1. Field of the Invention
The present invention relates to an information processing apparatus for printing output information from software applications (ex. word processors) operating on computers.
2. Description of the Related Art
In conventional printing systems, when printing image data (data files created by applications) saved in secondary storage devices of computers, users execute printing through the following procedure.
A description will be made, for example, to a case where Windows® is used as Operating System (OS) of computers. On this operating system, data to be printed is saved in the form of file data.
A user finds the file data to be printed and then starts the application that created the file data (for example, a word processor that is a document editing application, spreadsheet software, or the like) to open the file data to be printed.
Then, a print instruction provided as a service of the application is executed to do printing.
More specifically, a printing process in a computer is performed by starting a document editing application on a computer, performing such processing as creating a new document or opening a saved document file for editing, and then activating a printing processing function of the document editing application for performing the printing process.
Upon execution of the printing process, the document editing application invokes a printer driver through an intermediate module (GDI (Graphical Device Interface) under the OS on the computer, so that the invoked printer driver creates PDL (page description language) that can be interpreted by a controller of an image forming apparatus for doing printing.
When the user clicks on a print menu during processing on the document editing application, a user interface for print settings concerning printing appears.
Specifically, a variety of items concerning print settings, such as paper size, resolution, paper orientation, and number of copies, can be set.
Meanwhile, in recent years, in order to enhance efficiency and quality in a copy processing operation, a function of executing test printing is provided, in which when large volume printing is done, only one page is experimentally printed without doing full printing. Then, after the result of test printing is examined and whether desired quality is achieved or not is checked, and if satisfactory, then only the required amount of copy is executed. In this respect, Japanese Laid-Open Patent Publication No. 8-095436 discloses a technique of finely adjusting print settings after test printing on an interface screen of an image forming apparatus.
On the other hand, when test printing is done, in consideration of resource saving and visibility improvement, there is a possibility of making print settings different from a preset format set as print settings for full (actual) printing. For example, 2-in-1 layout may be executed or color print may be set to monochrome print. If print settings are changed, it is necessary to reset the print settings to those in accordance with the original preset format in order to do full printing. However, it is necessary to grasp which item was changed, which is cumbersome.

Information processing apparatus, method, and recording medium controlling the display of printing options

Konica Minolta Business Technologies, Inc.


In designing a layout for a deep-submicron semiconductor integrated circuit, a violational wire involving a violation of the delay limitation is extracted based on information representing a layout result obtained in a layout step. In order to extend a wire spacing between such an extracted wire and its neighboring wire to above a predetermined wire spacing, the neighboring wire is subjected to parallel displacement. If such a parallel displacement causes a distance of separation between the parallelly-displaced wire and its neighboring component to fall below a predetermined distance of separation, the component in question is shifted in order of extending the separation distance. Accordingly, even if the delay time of wire is dominant in comparison with that of element in regard to the signal propagation delay time, violations of the delay limitation occurring when the signal propagation delay time is less than a predetermined delay time can be canceled by a less number of steps.

The present invention relates to a method of laying out a semiconductor integrated circuit (SIC) with the aid of a computer. It more particularly pertains to an SIC layout technique for placing and interconnecting digital logic circuits or like components of a semiconductor integrated circuit.
In the design of large-scale integrated circuits (LSIs), it is required to meet limitations on the propagation delay time taken for a signal to propagate from one circuit to another and it is also very important to provide a semiconductor integrated circuit of minimum layout area, for the aspects of performance and costs. As the circuit scale of SIC increases the operating frequency thereof likewise increases. This results in an increase in the severity of a delay limitation imposed on the propagation delay time in a design phase. In an initial layout of a semiconductor integrated circuit, it is very important to modify the initial layout by reducing the signal propagation delay time of a wire involving a violation of the delay limitation, in order to cancel the delay limitation violation.
A conventional technique is discusses. When a layout is completed, the capacitance and resistance values of laid-out wires are exactly grasped and, based on the values, the signal propagation delay time of each wire is calculated. When a violation of the delay limitation is found, i.e., when any wire is found to have a signal propagation delay time in excess of a predetermined delay time, there are two ways of achieving a reduction of the signal propagation delay time. In the first way, a transistor in charge of driving a wire involving a violation of the delay limitation is replaced by another transistor having greater driving performance. In the second way, a violational wire is rerouted in order to reduce the length thereof.
The world of SIC enters now the deep-submicron age. As the cross-sectional area of wires is reduced, the resistance thereof increases. Additionally, the reduction of wire width and the reduction of wire spacing result in an increase in interwire capacitance (the capacitance between two adjacent wires), which therefore increases the total wire capacitance. Such increases in the total wire capacitance and in the wire resistance result in a longer signal propagation delay time. In regard to the signal propagation delay, wire delay becomes dominant in comparison with circuit component delay.
Accordingly, the foregoing conventional technique of making a change in the transistor driving performance may not be a very effective way of canceling violations of the delay limitation when wire delay becomes dominant.
For the case of rerouting a wire involving a violation of the delay limitation, it is also necessary to reroute its neighboring wires even when they are conformable to the delay limitation. Further, such rerouting may produce new violations of the delay limitation. Accordingly, the number of times such rerouting is carried out is increased. This is very time consuming. Much time is required to complete a design, and there is the possibility that repetition of the processing of rerouting will not make every wire free from a violation of the delay limitation.

Semiconductor integrated circuit layout method

Matsushita Electric Industrial Co., Ltd.


A method and a device for operating an internal combustion engine having a mass-flow line are provided, which allow the actual charge to be adapted to the setpoint charge of the internal combustion engine at a desired dynamic. A mass flow is supplied to the internal combustion engine via the mass-flow line. A setpoint value is specified for a characteristic quantity of the mass flow to the internal combustion engine. The setpoint value of the characteristic quantity of the mass flow is formed starting from a balance of the mass flow flowing into the mass flow line and the mass flow discharged from the mass flow line according to a predefined time characteristic.

1. Field of the Invention
The present invention is based on a method and a device for operating an internal combustion engine having a mass flow line.
2. Description of Related Art
From published German patent document DE 10 2005 007 057 A1, for example, a charge control is known which seeks a dynamically precise control. In so doing, a characteristic value of the dynamic behavior of a parameter is determined. This allows for an exact adjustment of a charge of a cylinder. A corresponding air model may be used to determine the instantaneously aspirated air quantity or the air quantity that is imminently going to be aspirated, based on the current setting variables in conjunction with the pressure, the temperature and mixture status in the intake manifold, and the rotational engine speed. The inverted function may be used to selectively modify the influence quantities of the aspirated volume in order to adjust an appropriate air quantity for the target value of the torque.

Method and device for operating an internal combustion engine having a mass flow line


A water heater with reduced nitrogen oxides output utilizing NO.sub.x reducing water conduits to cool a laminar flame and thereby reduce production of nitrogen oxides, The water heater has a partially aerated burner using a partially premixed combustion method to produce the laminar flame wherein a plurality of NO.sub.x reducing water conduits are disposed above the partially aerated burner in such a manner that water is supplied from a cold water conduit or a hot water conduit of the water heater into the plurality of NO.sub.x reducing water conduits through a water introducing portion by means of branching or serial connections. The water absorbs heat while flowing through the plurality of NO.sub.x reducing water conduits and is returned to the cold water conduit or the hot water conduit through a water receiving portion by means of and branching or serial connections.

The present invention relates to a water heater with reduced nitrogen oxides output.
Most water heaters adopt a so-called Bunsen combustion system which carries out partially premixed combustion at the primary air ratio of 0.1-0.7 which is followed by combustion with secondary air. In cases where this method is used, the amount of generated nitrogen oxides (hereinafter called NO.sub.x) is approximately 100-150 ppm when corrected to 0% of O.sub.2 (the same correction is hereinafter applied). In such a case, known examples for reducing NO.sub.x generated include a fully premixed combustion system, a flame cooling system using a radiation rod and an exhaust gas recycling system.
Although the fully premixed combustion system is capable of reducing NO.sub.x to less than 60 ppm by increasing an excess air ratio and consequently lowering the temperature of the flame, a problem exists in that it is necessary to precisely control the excess air ratio and prevent oscillating combustion and backfiring, which tends to occur in the method. This causes the manufacturers to incur a large cost increase due to their efforts to implement countermeasures.
The flame cooling method using a radiation rod calls for inserting a radiation rod in the flame so that the rod is heated until it glows red and emits radiation heat, thereby reducing the temperature of flame and, thus, the generation of NO.sub.x. Output of carbon monoxide (hereinafter called CO) is prevented by heating of the radiation rod. For this reason, however, it is necessary to use ceramics or heat resistant steel for the radiation rod In addition to the fact that such materials are costly and their durability is insufficient, there is a limit to which the radiation is able to lower the temperature and reduce NO.sub.x with this method. And, it is very difficult to reduce NO.sub.x by more than about 30% without CO emission.
As for the exhaust gas recycling method, it is widely known that the amount of NO.sub.x emission can be reduced to a half when the recycling ratio of exhaust gas is 10-15%. For the capacity of Bunsen burners of conventional water heaters, however, it is impossible to recycle exhaust gas at such a high recycling ratio as 10-15%; this may otherwise result in a lifted flame. Therefore, under the present conditions, such conventional water heaters are able to reduce NO.sub.x only to approximately 90 ppm by this method. Furthermore, it is necessary to take measures to prevent exhaust gas from causing corrosion in conduits used for recycling exhaust gas, fans and burner units; such extra efforts result in cost increases. Because of the above reasons, there is strong demand for development of a water heater which is capable of greatly reducing NO.sub.x and restricting an output of CO while maintaining a relatively simple construction and avoiding cost increases to the greatest extent possible.

Water heater with reduced NO.sub.x output


A control apparatus which controls an image sensing apparatus, includes a determination unit, a command generating unit and a command sending unit. The determination unit determines whether or not verification data has been added to an image file, the verification data being used to determine whether or not a digital image in the image file has been altered. The command generating unit generates a command that requests the image sensing apparatus to change the contents of the image file. The command sending unit sends the command to the image sensing apparatus if the determination unit determines that the verification data has not been added to the image file, the command being not sent to the image sensing apparatus if the determination unit determines that the verification data has been added to the image file.

At present, there is proposed a system which verifies alteration of image data generated by an image sensing apparatus such as a digital camera (see, e.g., U.S. Pat. No. 5,499,294 and Japanese Patent Application Laid-Open No. 2002-244924).
Japanese Patent Application Laid-Open No. 2001-78142 (reference 1) discloses an image sensing apparatus having a function of embedding verification data (data necessary to determine whether an image file has been altered: called "feature data" in reference 1) in a sensed image file, and an apparatus which inhibits any change of the contents of an image file when verification data is embedded in the image file.
However, reference 1 does not consider any arrangement which prevents the image sensing apparatus from changing the contents of an image file (with verification data) in accordance with an instruction from an external control apparatus.

Control apparatus and control method for image sensing apparatus


Provided is a concrete form system that may include a first panel, a first connection assembly, a first retaining member, and a lath. The first panel may include a first plurality of apertures. The first connection assembly may include a first bearing structure on a first side of the first panel and a first plurality of cross members penetrating the first plurality of apertures. The first plurality of cross members may include a first plurality of retaining portions exposed on a second side of the first panel. The first retaining member may extend through the first plurality of retaining portions and the lath may be between the first retaining member and the first bearing structure.

1. Field
Example embodiments relate to a form system having a lath covering and a method of fabricating a form.
2. Description of the Related Art
FIG. 8 is a view of a conventional form 50. As shown in FIG. 8, the conventional form 50 includes a first panel 10, a second panel 20, and a wire grid 30 between the first panel 10 and the second panel 20. In the conventional art, the wire grid 30 includes a plurality of cross rods 32 which are perpendicular to the first and second panels 10 and 20. The conventional form 50 also includes a plurality of outer rods 34 which extend substantially parallel to each other, are disposed against interior surfaces of the panels 10 and 20, and are welded to the plurality of cross rods 32. The form 50 also includes a plurality of inner rods 36 welded to the cross rods 32.
In the form 50, the cross rods 32 have ends that are bent to form retaining portions 32-1. Retaining rods 40 may be threaded into the retaining portions 32-1 to lock the cross rods 32 in place. The retaining rods 40 are configured to reside in longitudinally extending grooves 42 formed in the first and second panels 10 and 20. The retaining portions 32-1 reside in short grooves 44 that are also formed in the first and second panels 10 and 20.
A lath is a wire mesh that is applied to a framework, such as a wood or metal framework. In the conventional art laths serve as a matrix over which building materials, for example, plaster or stucco, is applied. One of the key elements of lath is the openings or gaps in the mesh. The openings allow the plaster or stucco to ooze behind the lath and form a strong bond thereto. Conventional methods of attaching a lath to a wall include using screws and/or anchors.


A fall and/or concussion prediction system includes: (i) a measurement assembly configured to receive a subject having a surface for receiving at least one portion of a body of a subject and at least one measurement device, the at least one measurement device configured to sense one or more measured quantities and output one or more signals that are generated based upon the subject's contact with the surface; (ii) a visual display device, the visual display device configured to display a task, an interactive game, a virtual reality scenario, and/or an immersive graphic environment that is visible to the subject; and (iii) a data processing device operatively coupled to the at least one measurement device of the measurement assembly and the visual display device. In one embodiment, a dual-task protocol is used to assess a person's risk for falling and/or predict whether or not a person has sustained a concussion.

1. Field of the Invention
The invention generally relates to a system and method for fall and/or concussion prediction. More particularly, the invention relates to a system that utilizes an interactive game, a virtual reality scenario, and/or an immersive graphic environment controlled by the motion of a subject in order to assess the probability that the subject will fall and/or has sustained a concussion. The invention further relates to a method comprising a dual task protocol used to assess the probability that the subject will fall and/or has sustained a concussion.
2. Background
People maintain their upright posture and balance using inputs from proprioceptive, vestibular and visual systems. During normal daily activity, where dynamic balance is to be maintained, other factors also matter. These factors are visual acuity, reaction time, and muscle strength. Visual acuity is important to see a potential danger. Reaction time and muscle strength are important to be able to recover from a potential fall.
There is a direct correlation between a person's risk of falling and the aforementioned factors that contribute to maintaining dynamic balance. For example, if an individual has decreased visual acuity and a slower reaction time, then he or she is more likely to sustain a fall. In addition, if an individual has reduced muscle strength, he or she is also more likely to fall.
Moreover, concussed people have a reduced ability to maintain balance, as well as a reduced capacity to respond to mental challenges. Typical tests for concussion involve either counting number of "falls" or errors in a challenging standing position, or assessing the person's ability to process mental tasks. It is also established that combining the two types of tests known as "dual tasking" gives more reliable results. Each subject is scored in comparison to a baseline performance.
What is needed, therefore, is a system and method for fall and/or concussion prediction that can be used to accurately assess a person's risk for falling and/or predict whether or not a person has sustained a concussion. Moreover, a system and method for fall and/or concussion prediction is needed that measures the ability of a person to move his or her feet and shift his or her weight in response to visual cues. Furthermore, a need exists for a system and method for fall and/or concussion prediction that tests the dynamic balance of an individual by requiring the person to maintain his or her balance by shifting his or her weight in response to visual inputs that require mental processing.

System and method for fall and/or concussion prediction


The invention relates to a method for determining properties of a negative sequence component of a space vector quantity in an electrical network. The method according to the invention includes the steps of determining on the basis of the properties of an ellipse formed by a space vector of the space vector quantity in the electrical network the magnitude of the negative sequence component of the space vector quantity in the electrical network and the location of the negative sequence component of the space vector quantity in the electrical network in relation to a positive sequence component.

The invention relates to determining properties of a negative sequence component of a space vector quantity in an electrical network.
A three-phase unbalanced network can be presented with the aid of three symmetrical three-phase components, i.e. the zero sequence system (ZSS), the positive sequence system (PSS) and the negative sequence system (NSS).
The negative sequence system is defined by means of negative sequence components of quantities in an electrical network. Negative sequence components of quantities can be utilized in monitoring and controlling the electrical network.

Method for determining a negative sequence component


Disclosed are laser scribing systems for laser scribing semiconductor substrates with backside coatings. In particular these laser scribing systems laser scribe opto-electric semiconductor wafers with reflective backside coatings so as to avoid damage to the opto-electric device while maintaining efficient manufacturing. In more particular these laser scribing systems employ ultrafast pulsed lasers at wavelength in the visible region and below in multiple passes to remove the backside coatings and scribe the wafer.

Opto-electric devices such as light-emitting diodes are typically manufactured by making multiple identical copies of a device in parallel on a substrate. Substrates typically used to manufacture opto-electric devices include wafers of sapphire, gallium arsenide, indium phosphide, silicon, germanium, diamond, or ceramics. These substrates typically need to be singulated into individual devices. Singulation can be performed by first scribing the substrate with a diamond saw or laser. Scribing is defined as creating a modified region on the surface or within the volume of a substrate which facilitates cracking and thereby the separation of the substrate proximate to the scribe. U.S. Pat. No. 6,580,054 SCRIBING SAPPHIRE SUBSTRATES WITH A SOLID STATE UV LASER, inventors Kuo-Ching Liu, Pei Hsien Fang, Dan Dere, Jenn Liu, Jih-Chuang Huang, Antonio Lucero, Scott Pinkham, Steven Oltrogge, and Duane Middlebusher, issued Jun. 17, 2003 describes the basic process of scribing substrates to prepare them for singulation by cleaving, wherein scribed substrates are subjected to localized stress at the scribe location to create cracks in the substrate which propagate through the thickness of the substrate thereby separating the wafer along the scribe. Substrates are often adhesively attached to a die attach film or plastic sheet attached to a surrounding frame called a tape frame during singulation to keep the singulated devices in place in spite of being separated. Laser scribing is distinguished from laser dicing where the substrate is completely or nearly through cut with the laser or saw to perform singulation without the cleaving step.
Problems with laser scribing include selecting laser parameters to process materials with widely varying laser energy absorption characteristics, avoiding damage to substrates and devices and maintaining acceptable system throughput. Opto-electric devices are particularly difficult to laser scribe or dice because the performance of the device can be dependent upon the manner in which the device was singulated. In particular, some opto-electric devices are constructed with a backside coating which reflects stray light back out of the device thereby increasing the device output efficiency as measured in candelas per ampere. The article "Nitride-Based LEDs With a Hybrid Al Mirror+Tio2/Slo2 DBR Backside Reflector," authors S. J. Chang, C. F. Shen, M. H. Hsieh, C. T. Kuo, T. K. Ko, W. S. Chen and S. C. Shei, describes the construction of these types of opto-electric devices. Laser scribing techniques which cause an undesirable heat affected zone adjacent to the scribes can reduce device output efficiency, as can damage which causes the reflective coating to "lift-off" or separate from the substrate. U.S. Pat. No. 7,804,043 METHOD AND APPARATUS FOR DICING OF THIN AND ULTRA THIN SEMICONDUCTOR WAFER USING ULTRAFAST PULSE LASER, inventor Tan Deshi, issued Sep. 28, 2010, describes using ultrafast lasers to scribe wafers but does not consider the need to remove coatings such as a DBR. U.S. Pat. No. 6,992,026, LASER PROCESSING METHOD AND LASER PROCESSING APPARATUS, inventors Fumitsugu Fukuyo, Keshi Fukumitsu, Maoki Uchiyama and Toshimitsu Wakuda, issued Jan. 31, 2006 discusses damage to substrates caused by pulsed lasers while scribing. This patent teaches using laser beams focused deep within the substrate to create altered zones unconnected to either the frontside or backsides of the wafer to permit cleaving while preventing damage to the substrate. U.S. Pat. No. 7,494,900, BACKSIDE WAFER DICING, inventors Richard S. Harris and Ho W. Lo, issued Feb. 24, 2009, discusses the advantages of performing backside processing of substrates but does not discuss scribing in the presence of a coating nor does it discuss methods of preventing damage to the substrate while scribing. U.S. patent application Ser. No. 2006/0220183 SEMICONDUCTOR WAFER HAVING MULTIPLE SEMICONDUCTOR ELEMENTS AND METHOD FOR DICING THE SAME, inventors Makoto Asai, Muneo Tamura, Kazuhiko Sugiura and Tetsuo Fujii, published Oct. 5, 2006 describes a two step process for scribing wafers having two layers where the layers have different refractive indices with respect to the laser wavelength being used. This application discusses only frontside scribing rather than backside scribing and does not discuss applications where the layer to be processed does not have a refractive index, but is in fact opaque to the wavelengths in question. Further this application does not discuss ways to avoid damage to the singulated devices as a result of the laser energy applied.
There remains a continuing need for a laser scribing process that scribes the backside opto-electric device substrates with reflective coatings in an efficient fashion without damaging the substrate using ultrafast laser pulses.

Method and apparatus for improved laser scribing of opto-electric devices


A pavement marker recognition device for recognizing a pavement marker accurately is provided, the device being capable of recognizing an object even when it is difficult to be recognized only from tones or color information. A pavement marker candidate extraction unit extracts an image area having a feature similar to that of a pavement marker from an image captured by a car-mounted camera as a pavement marker candidate area, a road shape analysis unit analyzes the road shape from the image captured by the car-mounted camera, and a pavement marker verification unit determines whether the road shape analyzed by the road shape analysis unit and the pavement marker candidate area extracted by the pavement marker candidate extraction unit are in a correspondence relationship indicated by a road shape and pavement marker correspondence table, and based on the determination result, recognizes the pavement marker candidate area as a true pavement marker.

Art for supporting driving of vehicles by recognizing images captured by car-mounted cameras have been well known. Such art includes devices which notify presence of junctions by recognizing stop lines painted on roads from images captured by car-mounted cameras, and devices which recognize pavement markers from images capture by car-mounted cameras and identify and display detailed current positions of the traveling vehicles.
Such art requires highly accurate image recognition for supporting safe driving of vehicles, and related art is disclosed in Patent Documents 1 and 2.
Patent Document 1 discloses a pavement marker detection device which recognizes running road of a vehicle from an image captured by a camera, sets a detection line within an image area of the vehicle running road recognized in the image captured by the camera, and detects a pavement marker according to changes in tones in the pixels on the detection line. In the pavement marker detection device disclosed in Patent Document 1, a range for performing recognition processing of a pavement marker within the captured image is limited to the self vehicle traveling area, to thereby reduce the processing time and prevent erroneous detection of an image area in a similar shape to that of the pavement marker, which is present outside the running road area.
Patent Document 2 discloses an image recognition device including a plurality of image capturing device for photographing various directions from a vehicle. The device selects one of the image capturing device according to self vehicle positional information, information regarding position and type of a pavement marker painted on the pavement near the self vehicle, weather information, brightness information, and vehicle speed information, and performs recognition of a pavement marker with respect to the image captured by the selected image capturing means. For example, in the case of a road in dark at night, a front-camera image in which a clear image can be captured by means of vehicle headlights is selected, and when the vehicle speed is high, a front-camera image in which can an object in an image can be captured for a long time is selected.
Patent Document 1: Japanese Unexamined Patent Publication 2006-24105
Patent Document 2: Japanese Unexamined Patent Publication 2007-147564

Pavement marker recognition device, pavement marker recognition method and pavement marker recognition program


A testing device for LCD driver LSIs, includes: a voltage generator which generates a multiple number of expected voltages to be compared to each output voltage output from each of the output terminals and can selectively output multiple sets of reference voltages required for testing multiple kinds of semiconductor integrated circuits; a multiple number of differential amplifiers, each having two input terminals, one for receiving the output voltage output from each of the output terminals and the other for receiving the reference voltage from the reference voltage generator; and a comparator that receives the amplified output voltages from the multiple number of differential amplifiers and judges whether the amplified output voltage from each differential amplifier falls within the given voltage range.

(1) Field of the Invention
The present invention relates to a testing device and testing method for a semiconductor integrated circuit (e.g., a LCD driver IC, etc.) that incorporates a multiple number of D/A converters and outputs voltages from the D/A converters via the associated output terminals, and particularly relates to a testing device and testing method which can examine the output voltages from the D/A converters, very quickly with high accuracy.
(2) Description of the Prior Art
With the development of LCD panels into a high precision configuration, LCD driver LSIs incorporated in LCD panels have become developed to deal with a greater number of outputs and a greater number of tones. For such tonal display, each output circuit in the LCD driver LSI incorporates its own D/A converter to output a tonal voltage. For example, a 6 bit D/A converter can display 64 levels of tones while a 8 bit D/A converter can display 256 levels of tones.
Upon the test for such a LCD driver LSI, it is checked if all the tonal voltage levels output from individual D/A converters fall within respective correct ranges and if the values of a tonal voltage level for all D/A converters meet the predetermined uniformity.
FIG. 1 is a conceptual view illustrating a conventional testing method by using a test example of an LCD driver LSI 51 incorporating xe2x80x98mxe2x80x99 output D/A converters 52 each having xe2x80x98nxe2x80x99 tonal levels.
A semiconductor testing device (tester) is used to supply an input signal to an LCD driver LSI 51 so that each D/A converter 52 outputs a voltage level corresponding to the first tonal level. The voltage levels corresponding to the first tonal level are output from associated output terminals (Y1, . . . , Ym) of LCD driver LSI 51 and input to input channels (1ch, . . . , mch) of tester 53. In tester 53, matrix switches 54 are sequentially turned on and off so that the outputs corresponding to the first tonal level are sequentially measured from the first output to the m-th output, one by one, using a high accuracy analog voltage measuring device 55 incorporated in the tester. The measured results are sequentially stored in an incorporated data memory 56. This process is repeated for xe2x80x98nxe2x80x99 tonal levels until all pieces of data relating to all the outputs (m outputs) for all tonal levels (n levels) can be stored into memory 56. As a result, mxc3x97n pieces of data will be stored into memory 56. The data stored in this memory 56 is subjected to a series of logical and arithmetical operations through an unillustrated processing unit incorporated in tester 53 so as to check each tonal voltage value of each output and the uniformity of each tonal voltage level between all the outputs.
In the testing of an LCD driver LSI 51, with the development towards a greater number of outputs and a greater number of tones, the amount of data to be picked up and the time required for data processing increase, so that the testing time increases sharply. Further, increasing the number of tonal levels requires a greater precision for measuring the voltage of each tonal level, needing longer testing time and also an expensive semiconductor testing device incorporating a high precision voltage measuring device.
As stated above, as LCD driver LSIs have become developed to deal with a greater number of outputs and a greater number of tones, the conventional testing method needs a much longer testing time and also needs an expensive semiconductor testing device incorporating a high precision voltage measuring device. Thus, the test cost is increasing more and more.
As a conventional semiconductor testing device to solve the above problems, Japanese Patent Application Laid-Open Hei 9 No.312569 has proposed a semiconductor testing device.
FIG. 2 is a block diagram showing the configuration of the semiconductor testing device disclosed in Japanese Patent Application Laid-Open Hei 9 No.312569.
The D/A converter testing device of this disclosure includes: a digital signal generator 60 for generating n-bit digital data; a clock generator 61; a D/A converter DUT 62 of a device under test which receives the data from digital signal generator 60 and a clock signal from clock generator 61 and outputs an analog signal Vg; a reference (REF) D/A converter 63 which receives the data branched from digital signal generator 60 and the clock signal branched from clock generator 61 and outputs a reference voltage Vref; a differential amplifier 64 receiving the output from D/A converter DUT 62 of the device under test at its one input and the output from reference D/A converter 63 at the other input to effect differential amplification; and a dual comparator 65 which receives the differential amplification output from differential amplifier 64 and checks if the signal in question falls in the allowable range between the upper and lower boundaries. With the above configuration, it is possible to provide a D/A converter testing device that provides a high throughput.
However, the semiconductor testing device (D/A converter testing device) disclosed in Japanese Patent Application Laid-Open Hei 9 No.312569 has suffered from the following difficulties. In the D/A converter testing device shown by Japanese Patent Application Laid-Open Hei 9 No.312569, since the same signals are input to both D/A converter DUT 62 of the device under test and reference D/A converter 63, it is necessary to use a non-defective D/A converter of the device under test for reference D/A converter 63. This is because the number of terminals is different depending upon the number of tones reproduced by the D/A converter of the device under test. Therefore, if a different type of D/A converter is to be tested, there is a need to have an extra non-defective D/A converter of the same type as the D/A converter as a reference D/A converter. The difficulties of the testing device depicted by Japanese Patent Application Laid-Open Hei 9 No.312569 are that there is a need to have a non-defective high-quality reference D/A converter for each type of D/A converter of the device to be tested or for each type of semiconductor integrated circuit incorporating a D/A converter to be tested.
The present invention has been made in view of the above prior art difficulties, and it is therefore an object of the present invention to provide a testing device and testing method for semiconductor integrated circuits which can markedly reduce the test time and enables a conventional inexpensive testing device to perform highly accurate testing without the necessity of providing a separate reference voltage generator for each type of semiconductor integrated circuit to be tested.
In order to achieve the above object, the present invention is configured as follows:
In accordance with the first aspect of the present invention, a testing device, for a semiconductor integrated circuit which incorporates a multiple number of D/A converters and outputs voltages from the D/A converters via associated output terminals, includes:
a reference voltage generator which generates a multiple number of reference voltages to be compared to each output voltage output from each of the output terminals and can selectively output multiple sets of reference voltages required for testing multiple kinds of semiconductor integrated circuits;
a multiple number of differential amplifiers, each having two input terminals, one for receiving the output voltage output from the associated output terminal and the other for receiving the reference voltage from the reference voltage generator; and
a comparator that receives the amplified output voltages from the multiple number of differential amplifiers and judges whether the amplified output voltage from each of the differential amplifiers falls within a given voltage range.
In accordance with the second aspect of the present invention, the testing device for semiconductor integrated circuits having the above first feature is characterized in that the reference voltage generator is a D/A converter which receives a digital data signal different from that of the D/A converters incorporated in the semiconductor integrated circuit to generate the multiple number of reference voltages and can selectively output a necessary set of reference voltages from the multiple sets of reference voltages required for testing multiple kinds of semiconductor integrated circuits, in accordance with the selection of the digital data signal.
The third aspect of the present invention resides in a testing method for a semiconductor integrated circuit which incorporates a multiple number of D/A converters and outputs voltages from the D/A converters via associated output terminals, wherein a testing device for semiconductor integrated circuits is used which comprises:
a reference voltage generator which generates a multiple number of reference voltages to be compared to each output voltage output from each of the output terminals and can selectively output multiple sets of reference voltages required for testing multiple kinds of semiconductor integrated circuits;
a multiple number of differential amplifiers, each having two input terminals, one for receiving the output voltage output from the associated output terminal and the other for receiving the reference voltage from the reference voltage generator; and
a comparator that receives the amplified output voltages from the multiple number of differential amplifiers and judges whether the amplified output voltage from each of the differential amplifiers falls within a given voltage range, wherein the reference voltage generator includes a D/A converter which receives a digital data signal different from the signals to the D/A converters incorporated in the semiconductor integrated circuit to generate the multiple number of reference voltages and can selectively output a necessary set of reference voltages from the multiple sets of reference voltages required for testing multiple kinds of semiconductor integrated circuits, in accordance with the selection of the digital data signal,
the method comprising:
the first step for calculating the difference between the reference voltage generated from the reference voltage generator of the testing device and the output voltage output from each output terminal, for all the output terminals;
the second step for amplifying the values obtained from the first step; and
the third step for judging at one time whether all the amplified differential values obtained in the second step in association with respective output terminals fall within the first given voltage range.
In accordance with the fourth aspect of the present invention, the testing method for semiconductor integrated circuits having the above third feature, comprises the above first through third steps and is characterized in that even if the output from the device under test varies, the first given voltage range can be kept at constant by computing the difference between the output from the device under test and the associated reference voltage generated from the above reference voltage.
In accordance with the fifth aspect of the present invention, the testing method for semiconductor integrated circuits having the above third feature, further comprises:
the fourth step for decreasing the width of the first given voltage range by a multiple of the predetermined voltage width to set up a second given voltage range; and
the fifth step for judging at one time whether all the amplified differential values associated to respective output terminals fall within the second given voltage range, and is characterized in that the fourth and fifth steps are repeated until the judgment at the fifth step changes.
In accordance with the sixth aspect of the present invention, the testing method for semiconductor integrated circuits having the above fifth feature is characterized in that, based on the value of the second given voltage range when the judgment at the fifth step changes, the devices under test are classified into a plurality of ranks.
In accordance with the seventh aspect of the present invention, the testing method for semiconductor integrated circuits having the above fifth feature is characterized in that the width of the second given range is made narrower as the above fourth and fifth steps are repeated.
The eighth aspect of the present invention resides in a storage medium for storing the program for a computer to execute a testing method for a semiconductor integrated circuits which incorporates a multiple number of D/A converters and outputs voltages from the D/A converters via associated output terminals, wherein a testing device for semiconductor integrated circuits is used which comprises:
a reference voltage generator which generates a multiple number of reference voltages to be compared to each output voltage output from each of the output terminals and can selectively output multiple sets of reference voltages required for testing multiple kinds of semiconductor integrated circuits;
a multiple number of differential amplifiers, each having two input terminals, one for receiving the output voltage output from the associated output terminal and the other for receiving the reference voltage from the reference voltage generator; and
a comparator that receives the amplified output voltages from the multiple number of differential amplifiers and judges whether the amplified output voltage from each of the differential amplifiers falls within a given voltage range, wherein the reference voltage generator includes a D/A converter which receives a digital data signal different from the signals to the D/A converters incorporated in the semiconductor integrated circuit to generate the multiple number of reference voltages and can selectively output a necessary set of reference voltages from the multiple sets of reference voltages required for testing multiple kinds of semiconductor integrated circuit, in accordance with the selection of the digital data signal,
the method comprising:
the first step for calculating the difference between the reference voltage generated from the reference voltage generator of the testing device and the output voltage output from each output terminal, for all the output terminals;
the second step for amplifying the values obtained from the first step; and
the third step for judging at one time whether all the amplified differential values obtained in the second step in association with respective output terminals fall within the first given voltage range, wherein even if the output from the device under test varies, the first given voltage range can be kept at constant by computing the difference between the output from the device under test and the associated reference voltage generated from the above reference voltage.
The ninth aspect of the present invention resides in a storage medium for storing the program for a computer to execute a testing method for a semiconductor integrated circuits which incorporates a multiple number of D/A converters and outputs voltages from the DIA converters via associated output terminals, wherein a testing device for semiconductor integrated circuits is used which comprises:
a reference voltage generator which generates a multiple number of reference voltages to be compared to each output voltage output from each of the output terminals and can selectively output multiple sets of reference voltages required for testing multiple kinds of semiconductor integrated circuits;
a multiple number of differential amplifiers, each having two input terminals, one for receiving the output voltage output from the associated output terminal and the other for receiving the reference voltage from the reference voltage generator; and
a comparator that receives the amplified output voltages from the multiple number of differential amplifiers and judges whether the amplified output voltage from each of the differential amplifiers falls within a given voltage range, wherein the reference voltage generator includes a D/A converter which receives a digital data signal different from the signals to the D/A converters incorporated in the semiconductor integrated circuit to generate the multiple number of reference voltages and can selectively output a necessary set of reference voltages from the multiple sets of reference voltages required for testing multiple kinds of semiconductor integrated circuit, in accordance with the selection of the digital data signal,
the method comprising:
the first step for calculating the difference between the reference voltage generated from the reference voltage generator of the testing .device and the output voltage output from each output terminal, for all the output terminals;
the second step for amplifying the values obtained from the first step;
the third step for judging at one time whether all the amplified differential values obtained in the second step in association with respective output terminals fall within the first given voltage range, wherein even if the output from the device under test varies, the first given voltage range can be kept at constant by computing the difference between the output from the device under test and the associated reference voltage generated from the above reference voltage;
the fourth step for decreasing the width of the first given voltage range by a multiple of the predetermined voltage width to set up a second given voltage range; and
the fifth step for judging at one time whether all the amplified differential values associated to respective output terminals falls within the second given voltage range,
wherein the fourth and fifth steps are repeated until the judgment at the fifth step changes.
In accordance with the tenth aspect of the present invention, the storage medium for storing the program for a computer to execute the testing method for semiconductor integrated circuits having the above ninth feature is characterized in that, based on the value of the second given voltage range when the judgment at the fifth step changes, the devices under test are classified into a plurality of ranks.
In accordance with the eleventh aspect of the present invention, the storage medium for storing the program for a computer to execute the testing method for semiconductor integrated circuits having the above ninth feature is characterized in that the width of the second given range is made narrower as the above fourth and fifth steps are repeated.
According to the testing device and testing method for semiconductor integrated circuits of the present invention, the output voltage output from the output terminal of each D/A converter in a semiconductor integrated circuit is compared to the reference voltage in each differential amplifier. The results, i.e., the amplified output voltages from the individual differential amplifiers are input in parallel to a comparator. In the comparator, it is judged as to whether the amplified output voltage from each of the differential amplifiers falls within the given voltage range.
According to the testing device and testing method for semiconductor integrated circuits of the present invention, it is possible to markedly reduce the test time by using a comparator which effects simultaneous judgements of all the amplified output voltages, in testing a semiconductor integrated circuit such as a LCD driver LSI which has been developed to deal with a greater number of outputs and a greater number of tones. Further, the testing device of the present invention enables high accuracy testing using a conventional inexpensive tester without the necessity of a high accuracy analog voltage measuring device for voltage measurement as in the conventional configuration, thus making it possible to sharply reduce the testing cost. It is possible to classify the quality of each device based on the variation in voltage output, so that applications of the LCD panel to which the device is applied can be enlarged, thus making it possible to improve the production yield and reducing LCD drivers to fair price. Further, since the reference voltage generator is commonly used for testing multiple kinds of semiconductor integrated circuits, it is no longer necessary to provide a separate reference voltage generator for each type of semiconductor integrated circuit under test. Consequently, the present invention enables only a single testing device to achieve efficient testing of multiple kinds of semiconductor integrated circuits.
The width of the first given voltage range is made narrower by a multiple of the predetermined voltage width to set up a second given voltage range, and it is judged at the same time whether all the differential amplified values from all the associated output terminals fall within the second given voltage range. The devices under test are classified into multiple ranks, based on the second given voltage range which is determined by checking the change in the pass/reject judgement result. Therefore, it is possible to classify the quality of each device based on the variation in voltage output, so that usage of the LCD panel to which the device is applied can be enlarged, thus making it possible to improve the production yield and reducing LCD drivers to fair price.

Testing device and testing method for semiconductor integrated circuits


Disclosed herein is a combination of genomic sequences whose methylation patterns have utility for the improved detection and differentiation between colorectal neoplasms. Further disclosed herein are methods, nucleic acids and kits for detecting or differentiating between colorectal neoplasms.

Colorectal cancer (CRC) is the third most common form of cancer and the second leading cause of cancer-related deaths in the western world. Its natural evolution (adenoma-carcinoma sequence is believed to occur in most patients) and accessibility by non-surgical methods makes it suitable for early detection and prevention.
Early detection greatly improves the chances of curing CRC. Colonoscopy is an extremely specific and sensitive test, however, it is an invasive test which requires bowel preparation and patient cooperation. It is also associated with a minor risk of serious complications, reducing its generalized use. There exists a need for non-invasive detection of pre-malignant and malignant neoplastic alterations of the colon with high sensitivity and excellent specificity.

Methylated markers for colorectal cancer

Quest Diagnostics Investments Incorporated


A liquid crystal display device includes: a first gate line and a second gate line on a first substrate; a first data line and a second data line crossing the first and second gate lines to define a pixel region; a first thin film transistor connected to the first gate line and the first data line; a second thin film transistor connected to the first gate line and the second data line; a first pixel electrode in the pixel region and connected to the first thin film transistor; a second pixel electrode in the pixel region, connected to the second thin film transistor and including at least one opening therein; a common electrode on a second substrate; and a liquid crystal layer between the second pixel electrode and the common electrode.

1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of driving the same.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, many efforts and studies are being made to develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays, and electro-luminescence displays (ELDs), as a substitute for CRTs. Of these flat panel displays, LCD devices have many advantages, such as high resolution, light weight, thin profile, compact size, and low voltage power supply requirements.
In general, an LCD device includes two substrates that are spaced apart and face each other with a liquid crystal material interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal material. Alignment of the liquid crystal molecules in the liquid crystal material changes in accordance with the intensity of the induced electric field into the direction of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the induced electric field.
FIG. 1 is a perspective view illustrating an LCD device according to the related art.
Referring to FIG. 1, the LCD device includes an array substrate 10, a color filter substrate 20 and a liquid crystal layer 30. The array substrate 10 includes a gate line 14 and a data line 16 on a first substrate 12 that cross each other to define a pixel region P. A pixel electrode 18 and a thin film transistor Tr, as a switching element, are positioned in each pixel region P. The thin film transistors Tr, which are disposed adjacent to where the gate lines 14 and the data lines 16 cross, are disposed in a matrix form on the first substrate 12. The color filter substrate 20 includes a color filter layer 26 including red (R), green (G) and blue (B) color filter patterns 26a, 26b and 26c in respective pixel regions P on a second substrate 22, a black matrix 25 between the color filter patterns 26a to 26c, and a common electrode 28 on the color filter layer 26 and the black matrix 25.
Although not shown in the drawings, a sealant is formed along peripheral portions of the array substrate 10 and the color filter substrate 20 to attach the array substrate 10 and the color filter substrate 20 and prevents liquid crystal molecules of the liquid crystal layer 30 from leaking. Further, a lower alignment layer and an upper alignment layer are formed on inner surfaces on the array substrate 10 and the color filter substrate 20, respectively. Further, polarizing films may be formed on outer surfaces of the array substrate 10 and the color filter substrate 20. Further, a backlight supplying light is located below the array substrate 10.
Recently, the LCD device is equipped into electronic devices such as a personal digital assistant (PDA), laptop computer and mobile station. The electronic devices are much used in public places. Generally, users with the electronic devices need information displayed on the electronic devices not to be seen by others. According to the users' needs, an LCD device having two viewing angles, which are different, is proposed. This type LCD device may be referred to as a viewing angle image control (VIC) mode LCD device.
FIG. 2 is a plan view illustrating a VIC mode LCD device according to the related art, and FIG. 3 is a cross-sectional view taken along a line III-III. In FIG. 2, one image display unit includes four pixel regions P1 to P4 which are arranged adjacently into vertical and horizontal directions.
Referring to FIGS. 2 and 3, the LCD device 30 includes an array substrate, a color filter substrate facing the array substrate, and a liquid crystal layer 90 between the array substrate and the color filter substrate.
In the array substrate, gate and data lines 32 and 40 cross each other on a first substrate 31 to define the pixel regions P1 to P4. A thin film transistor Tr is located near the crossing portion of the gate and data lines 32 and 40, and connected to the gate and data lines 32 and 40. A common line 36 is spaced apart from and in parallel with the gate line 32.
The thin film transistor Tr includes a gate electrode 34, a semiconductor layer 39, and source and drain electrodes 42 and 43. A gate insulating layer 36 is on the gate electrode 34.
A plurality of first pixel electrodes 52 each having a bar shape are formed in each of the first to third pixel regions P1 to P3 and connected to the drain electrode 43 of the thin film transistor T through a drain contact hole 48 in a passivation layer 46. A plurality of first common electrodes 38 each having a bar shape are formed in each of the first to third pixel regions P1 to P3 and connected to the common line 36. The first pixel and common electrodes 52 and 38 are alternately arranged. In the fourth pixel region P4, a second pixel electrode 53 having a plate shape is formed and connected to the drain electrode 44 of the thin film transistor Tr.
In the color filter substrate, a color filter layer 76 and a black matrix 73 are formed on a second substrate 70. The color filter layer 76 includes a red (R) color filter pattern, a green (G) color filter pattern, and blue (B) color filter pattern 76c in the first to third pixel regions P1 to P3, respectively. In the fourth pixel region P4, separate color filter pattern is not deposited, and instead, a transparent overcoat layer 79 functions as a white (W) color filter pattern. The overcoat layer 79 is formed over the entire surface of the color filter substrate. A second common electrode 82 made of a transparent conductive material is formed in the fourth pixel region P4. The second common electrode 82 has a plate shape.
In the above-described LCD device 30, each of the first to third pixel regions P1 to P3 is operated according to an in-plane electric field induced between the first pixel and common electrodes 52 and 38. Accordingly, a wide viewing angle of the LCD device 31 can be obtained.
The fourth pixel region P4 is operated according to a vertical electric field induced between the second pixel and common electrodes 53 and 82. This causes a viewing angle of the LCD device 30 to be narrow. In other words, the fourth pixel region P4 is used to control the viewing angle of the LCD device 30 thus the viewing angle can become narrow.
In a case that the LCD device 30 displays texts usually seen in black and white, because of the operation of the fourth pixel region P4, the viewing angle of the LCD device 31 can be effectively controlled such that people around the LCD device 30 does not recognize information displayed on the LCD device 31.
However, in a case that the LCD device 31 displays images usually seen in various colors, since the fourth pixel region P4 does not have separate color filter pattern thus merely displays grays such as black and white, the viewing angle of the LCD device 30 cannot be effectively controlled.
Further, since the fourth pixel region P4 is used for a narrow viewing angle mode of the LCD device 30, when the LCD device 30 is required to be operated in a wide viewing angle mode, the fourth pixel region P4 is not operated thus displays black. Accordingly, brightness of the LCD device 30 is reduced.

Liquid crystal display device and method of driving the same