A hierarchical wireless network is comprised of two levels, a first level configured for wired coupling to an IP network and comprised of a gateway configured for wired coupling to the IP network, a WiARP server and a data store; and a second level, wired to the first level by a distribution system, and comprised of at least two access points, each configured for wireless association with a respective plurality of mobile stations and having a WiARP proxy residing therein. For each mobile station associated with the second level, the WiARP server maintains an IP address of the mobile station and a MAC address for the access point with which the mobile station is associated. Conversely, each WiARP proxy maintains, on behalf of the associated access point, IP and MAC addresses for each mobile station associated therewith.

In recent years, the number of intelligent mobile devices, for example, pagers, smart wireless telephones, laptop computers and personal digital assistants ("PDAs"), has increased dramatically. Together with the increasing number of intelligent mobile devices has come increased interest in the delivery of internet protocol ("IP") data and services to such devices. However, there remain significant network architecture issues which affect the delivery of IP data packets over wireless networks such as wireless local area networks ("WLANs"). One such issue relates to the ability of the wireless network to locate the desired recipient of an IP data packet. Heretofore, the problems experienced by the wireless network when attempting to locate a mobile station have resulted in significant waste of wireless resources. Because the wireless network is often unsure of the location of a mobile station, the mobile station must be paged by plural access points even though the mobile station is in communication with only one such access point. Such an approach to locating mobile stations unnecessarily consumes wireless resources since bandwidth which could be dedicated to delivering IP data packets must instead be used to page the mobile stations. This approach also contributes to a shortened battery life for mobile stations. When inactive, a mobile station will often enter a power-save mode to conserve battery life. However, whenever a page is broadcast by its access point, the mobile station must wake-up and check each such page to determine if it is directed to them. As a result, the mobile station must consume much more power than if it was allowed to stay in the power-save mode.
Because of these shortcomings in current wireless IP techniques, many wireless IP applications have not been implemented. Accordingly, by configuring a wireless network into a hierarchical architecture having plural levels and implementing selected WiARP functionality in each level, a wireless network in which an IP data packet can be delivered to a mobile station without the need to resort to the broadcasting functions which characterized prior wireless network architectures may be achieved.

Hierarchical wireless network and an associated method for delivering IP packets to mobile stations


A computer system includes a computer case, a receiving tray, and a bracket. The computer case includes a front plate with a plurality of air intakes and a first side plate. The receiving tray includes a retaining wall. The bracket includes a first mounting plate and a second mounting plate. A plurality of first through hole is defined in the first mounting plate, and a plurality of second through hole is defined in the second mounting plate. The airflow guiding duct includes a first guiding plate and a second guiding plate. The first guiding plate is located between the front plate and the first mounting plate, the second guiding plate is located between the bracket and the first side plate; the plurality of air intakes, the airflow guiding duct, the plurality of first through hole second through hole together form a path for the air to flow.

1. Technical Field
The present disclosure relates to computer systems, and more particularly to a computer system with an airflow guiding duct.
2. Description of Related Art
Heat dissipating devices perform a critical function of removing heat from an electronic device. The heat dissipating device often includes one or more fans received in a bracket. Airflow from outside of the electronic device is directed inside and then back out of the electronic device by the fan, for dissipating heat generated in the electronic device. However, if the air flows in a disorderly manner in the electronic device, a heat dissipating efficiency of the electronic device may be decreased. Therefore, computer systems with improved heat dissipating efficiencies may be desired within the art.

Computer system with airflow guiding duct

Hong Fu Jin Precision Industry (WuHan) Co., Ltd.


The present invention presents an angular velocity sensor having a self diagnosis function. An angular velocity sensor of the present invention includes a driving part for stably vibrating a driving part of a sensor element having a driver part and a detector part for detecting an angular velocity. The angular velocity sensor also includes a detection means for detecting the angular velocity of the sensor element. The angular velocity sensor obtains a self diagnosis signal for a malfunction by detecting a mechanical coupling signal obtained at the detection means.

The present invention relates to an angular velocity sensor having a self diagnosis function.
A conventional tuning fork type angular velocity sensor has a detecting part comprising detector plates 13 and 14 and a driving part comprising driver plates 11 and 12. As shown in FIG. 19, detector plates 13 and 14 are located at the top of the driver plates 11 and 12, respectively. Each detector plate 13 and 14 is joined orthogonally to a respective driver plate 13 and 14. When an angular velocity is applied to the angular velocity sensor and while keeping the driving part in continuous tuning fork vibration, the angular velocity is detected by the output of the detector plates 13 and 14, which vibrate in opposite directions to each other corresponding to the applied angular velocity.
In an angular velocity sensor in accordance with the prior art, a tightly sealed space is formed by a lid 2, which is made of resin. Lid 2 is attached at an aperture of a case 1, also made of resin, of which one end is open, as shown in FIG. 18.
Inside the tightly sealed space, a circuit board 3 and a metallic weight plate 4 are contained. Supporting pins 5 are attached at four corners inside the case 1, and weight plate 4 and circuit board 3 are elastically supported and fixed by the supporting pins 5. Dampers 6 made of rubber are attached at the four corners of weight plate 4 for the elastic support. Supporting legs 7 made of resin are put between damper 6 and circuit board 3. Supporting pins 5 are compressed at the tips toward the circuit board 3 side after penetrating dampers 6, supporting legs 7 and circuit board 3. Thus, circuit board 3 and weight plate 4 are elastically supported and fixed. A metallic supporting pin 8 is inserted and fixed vertically to weight plate 4, on the circuit board 3 side, as shown in FIG. 19. One end of a metallic supporting pin 9, laid parallel to weight plate 4, is inserted and fixed to supporting pin 8. The diameter of supporting pin 9 is about one fifth of the diameter of supporting pin 8. Furthermore supporting pin 9 is made of metallic material having elasticity, such as a piano wire, wherein the other end of supporting pin 9 is fixed to a metal plate 10 by soldering.
One end of each of metallic driver plates 11 and 12, which are sandwiching supporting pins 8 and 9 therebetween, is fixed to each side of metal plate 10. Plate-shaped piezoelectric elements 11a and 12a are fixed on the surfaces of metallic driver plates 11 and 12, respectively. In this way, the tuning fork type driving part is formed. The other ends of driver plates 11 and 12 are twisted orthogonally relative to piezoelectric elements 11a and 12a to form detector plates 13 and 14. Other plate-shaped piezoelectric elements 13a and 14a are fixed on detector plates 13 and 14, as shown in FIG. 19. In this way, the detecting part is formed. The angular velocity sensor is composed of the driving part and the detecting part.
There is a problem with the conventional angular velocity sensor however. Namely, the conventional sensor has no ability to detect information about the occurrence of a malfunction of the components, nor the ability to send such information, judged to be a malfunction of the components, to the outside (e.g., such that an operator can be notified of the malfunction).
The present invention provides a sensor that allows detection from outside the sensor of a malfunction in the sensor, resulting from partial damage to the sensor, that prevents the sensor from performing accurate angular velocity detection. Accordingly, the present invention provides a highly reliable angular velocity sensor.
To achieve the stated purpose, an angular velocity sensor of the present invention includes (1) a sensor element having a driver part and a detector part for detecting an angular velocity, (2) drive means including a driver circuit for supplying a driving signal to the driving part of the sensor element and a monitor circuit to which a monitor signal is supplied from the sensor element and stably driving and vibrating the driver part of the sensor element by applying the output of the monitor circuit to the driver circuit through an AGC (automatic gain control) circuit, (3) detection means including a charging amplifier to which an output of the detector part of the sensor element is supplied and a synchronous detector to which an output of the charging amplifier is supplied through a band pass filter and detecting an output of the band pass filter synchronizing with a driving signal from the drive means and outputting an angular velocity signal, and (4) self diagnosis means receiving a mechanical coupling signal obtained from the detection means other than an angular velocity signal, detecting abnormality of the sensor element and outputting a self diagnosis signal.
Also, an angular velocity sensor according to another aspect of the present invention includes, (1) a sensor element with a vibrating part and detector part for detecting an angular velocity, (2) drive means including a driver circuit and a monitor circuit similar to that mentioned above, (3) detection means including a pair of current amplifiers, a differential amplifier and a synchronous demodulator, in which the pair of current amplifiers receive outputs from the detector part of said sensor element, the differential amplifier amplifies a difference in outputs from the pair of current amplifiers and in which the synchronous demodulator detects an output from the differential amplifier in synchronous with the driving signal from the drive means and outputs an angular velocity signal, and (4) self diagnosis means for outputting a diagnosis signal to detect an abnormality of the sensor element by coupling a signal synchronized with the driving signal to the synchronous demodulator.
According to the above composition, by making the mechanical coupling signal always obtained from the detection means as a signal for self diagnosis, whether the angular velocity signal is in a state to be detected normally or not can be easily checked. Also as the mechanical coupling signal is always generated, it is unnecessary to independently provide means for generating the mechanical coupling signal. Accordingly, not only is the composition very simple and highly reliable for self diagnosis, but it also makes it possible to know when the characteristics of the sensor become stable after the sensor starts to work so that sensor output information can be utilized at its earliest possible time.

Matsushita Electric Industrial Co., Ltd.


A circuit with low noise and reduced offset that feeds an input of an opamp with a programmable feedback resistor that provides variable gain settings. Input biasing currents are varied using control bits that are also used to adjust the gain. When the input signal is small (gain at higher setting), a minimum bias current is provided to source the input voltage swing. This scheme reduces the noise and offset generated by the lower transconductance of a biasing transistor while maintaining a constant SNR and fixed offset even in the presence of relatively small input swings. Also, when the input signal is large (gain at lower setting), a maximum bias current can be provided to accommodate the relatively large input swing level. Although the overall noise and offset current are increased for large input swings, the overall SNR and offset is maintained for relatively lower input swings.

The present invention is directed to a variable gain voltage amplifier, and more particularly, to a current conveyor type voltage amplifier circuit that employs a gain dependent biasing scheme to reduce offset and noise to maintain the signal integrity when amplifying a varying input signal.
In the past, different types of circuits have been employed to improve the performance of variable gain amplifiers that employ automatic gain control (AGC) circuits. AGC amplifiers are widely used in communication channels to automatically adjust gain in response to a varying peak to peak swing of an input signal. A typical AGC circuit detects an outputted signal""s peak-to-peak swing, and then adjusts the gain by varying the feedback impedance network which is connected across an opamp to maintain a relatively constant level for the swing of the outputted signal. For example, when an inputted signal swings (rises) to a relatively high level, the AGC circuit will adjust the feedback impedance of the amplifier so that its gain is reduced. Similarly, when the inputted signal""s swing is at a relatively low level, the AGC circuit adjusts the feedback impedance to provide more amplifier gain.
However, an unfortunate side effect of increasing amplifier gain in current conveyor type voltage amplifiers for a faint/weak input signal with a relatively small swing is an increase in noise and the offset voltage due to an increase in the feedback impedance that multiplies noise and offset contributions from the current conveyor""s biasing (current sources) circuits. Thus, for relatively faint/weak signals, the operation of an AGC amplifier can degrade the signal to noise ratio (SNR). Accordingly, it would be advantageous to provide a variable gain amplification circuit that retains the benefits of an AGC circuit without degrading the SNR for weak/faint input signals with a relatively small swing.
The present invention is directed to an apparatus for amplifying a signal. A variable feedback resistance is coupled between the input and output terminals of an opamp. The input terminal of the opamp is connected to the output of the current conveyor circuit (the high impedance node). The input signal is converted into input current by a fixed resistor which connects to the input of the current conveyor circuit (low impedance node). The signal current then is conveyed (directed) to the input of the opamp and, through the feedback resistor to produce output voltage. Due to the high output impedance of the current conveyor circuit, the feedback factor of the amplifier remains close to unity and thus, operating at a loop gain which is close to the open-loop performance. This also results in reduction of power consumption by the opamp since the feedback factor remains close to unity across the AGC range. The current conveyor circuit consists of sink and source currents that are provided partly to bias the input signal swing current. In particular, the source current is scaled such that for a given input swing current, sufficient biasing current is available to maintain signal integrity. The sink current is scaled according to the source current to maintain the biasing conditions. The (sink and source) current sources produce noise and offset contributions that are proportional to the Gm (transconductance) of the transistors. To minimize the offset and noise for a given drain-to-source voltage the transistors are biased such that minimum Gm is achieved while the transistors remain in saturation region. The sink and source current sources are then scaled by the gain control setting of the amplifier to provide sufficient current for the required input current swing. In other words, when the input swing current is at minimum (maximum feedback resistance), the current sources provide minimum bias currents such that maximum SNR is achieved. On the other hand, when the input swing current is at maximum (minimum feedback resistance), the current sources provide large bias currents such that the overall signal-to-noise ratio is relatively constant. Thus, the SNR remains constant across the range of the ADC.
For one embodiment, the invention is directed to at least one switch for disabling at least a portion of the source current source if the high swing of the signal is small. The operation of the switch causes noise produced by at least a portion of the source current source to be reduced. Also, at least another switch is directed to disabling at least a portion of the sink current source if the low swing of the signal is small. The operation of this switch causes noise produced by at least a portion of the sink current source to be reduced.
For yet another embodiment, the invention is directed to at least one of a plurality of PMOS transistors that is employed by the source current source to provide the selected amount of current. Also, at least one of a plurality of NMOS transistors is employed by the sink current source to provide the selected amount of current.
For yet still another embodiment of the invention, the controller includes an automatic gain control component. Also, the controller can be used to determine the size of a peak-to-peak swing in the signal.

Apparatus and method for employing gain dependent biasing to reduce offset and noise in a current conveyor type amplifier


The present invention relates to a multiferroic material capable of freely controlling magnetic field size at room temperature, and to a method of manufacturing the same. Said multiferroic material includes hexaferrites containing magnetic iron ions partially substituted by non-magnetic ions. Said non-magnetic ions act to change the magnetic anisotropy of said hexaferrites.

Multiferroics mean the materials that have ferroelectric and ferromagnetic properties. Studies for multiferroic materials that can control electric property with magnetic field or control the magnetic property with electrical field and their applications for devices using the multiferroic properties have been actively conducted.
However, the control of the electric polarization of the known multiferroics is so far induced by a low magnetic field at very low temperature or by very high magnetic field at room temperature. Accordingly, there is a limitation in applying the known multiferroic materials to room temperature multiferroic devices.

Multiferroic material and method of manufacturing the same


An endoscopic method and system are provided which include a guide member, or sheath, open at both ends and having a continuous opening in the sheath along its entire length. A trocar proportioned to fit within the sheath includes a prominence which fits within the opening of the sheath to provide a smooth surface on the exterior of the sheath for insertion into, for example, a hand for the endoscopic release of the carpal ligament. The trocar is removed and a videoarthroscope is inserted in one end of the sheath while a cutting instrument or other instrument is inserted in the opposite end to permit direct observation of the procedure.

1. Field of the Invention
The present invention relates to surgical apparatus, and more particularly, to apparatus for performing endoscopic surgery.
2. Description of the Prior Art
Over the past decade, arthroscopy has become one of the most rapidly developing techniques in orthopaedic surgery. Arthroscopic meniscectomy has largely replaced conventional meniscectomy. Carpal tunnel syndrome, or tardy median nerve palsy, which is caused by the compression of the median nerve within the carpal tunnel, requires the surgical release of the transverse carpal ligament. Until recently, the procedure was performed by open surgery. An incision of several centimeters in the wrist area was necessary to avoid injury to the median nerve.
Endoscopic approaches to carpal tunnel surgery are emerging as satisfactory replacements for the open surgical procedures. A subcutaneous endoscopic procedure is described in I. Okutsu et al., "Endoscopic Management of Carpal Tunnel Syndrome," Arthroscopy: The Journal of Arthroscopic and Related Surgery 5(1):11-18 (1989). The Okutsu et al. procedure employs a clear plastic outer tube, or sheath, and a standard arthroscope. The tube has a bevel-shaped barrel about 100-175 mm in length and about 6 mm in diameter. The arthroscope is used in conjunction with a video-camera, recorder and light source. Following the incision of the wrist area, an obturator is inserted into the carpal tunnel from the radial side of the palmaris longus tendon to help guide insertion of the videoarthroscope. The obturator is then removed and the clear plastic tube inserted. The videoarthroscope is then advanced into the tube. The endoscope is removed and reinserted on the opposite side of the palmaris longus tendon. A retrograde hook knife is thereafter inserted along the side of the clear plastic tube to cut the transverse carpal ligament. The clear plastic tube is described more fully in Okutsu, U.S. Pat. No. 4,819,620. The tube has a closed, generally rounded distal end and an open proximal end through which the videoarthroscope and/or a knife may be inserted. A slot is provide along a portion of its length through which the cutting edge of the knife projects to cut the desired site. It is believed that visualization may be distorted because of the curved clear wall of the tube.
Another endoscopic procedure, known commercially as the Agee Carpal Tunnel Release System, employs a videoscope, a disposable knife cone, a hand piece with a trigger, three curved obturators and one freerer. The obturators are used consecutively to make a channel. The hand piece, which has an elongate shaft portion, is then inserted into the channel via the hook of hamate. When in the desired position, the trigger is pressed to activate a knife blade which pops up through a window in the elongate shaft. The hand piece is then drawn back to cut the ligament. The exposed blade cannot be viewed during the procedure.
Storz, U.S. Pat. No. 4,656,999 describes an endoscope in which there is a strip blade at the distal end which can be moved in a slideway at a relatively small distance in front of the lens. Boebel, U.S. Pat. No. 4,620,547 describes an instrument which includes an outer shaft which is closed at its distal end and has an opening in its side wall close to the distal end, and an inner shaft which is movable axially within the outer shaft, for carrying an endoscope. The endoscope may have a cutting edge at its distal end so that tissue drawn through the side opening of the outer shaft may be severed while being observed through the endoscope.
An object of the present invention is to provide an endoscopic procedure and a system for performing the procedure which permits the direct, undistorted visualization of the incision site while the cut is being made. It is a further object of the present invention to provide such a procedure and system for performing the procedure which creates a clearly defined unobstructed work space to enhance visualization and accuracy of the endoscopic procedure.

Cutting instruments for endoscopic surgery


It is provided a burner for automotive lamps, particularly HID lamps, comprising a discharge vessel for generating light by means of a discharge arc. A glass body for protecting the discharge vessel comprises a shaft for being inserted into a socket. The shaft comprises at least one insulation pocket for receiving a rib of the socket and for insulating the first electrode outside the glass body. Due to the insulation pocket the glass body may provide an umbrella-like dielectric increasing the minimum necessary way for a high voltage discharge arc to the uncovered part of the first electrode at the proximal end of the shaft. Due to the improved insulation effect by means of the insulation pocket, the height of the shaft of the glass body may be significantly reduced leading to a reduced height of the burner without impairing the insulation of the burner.

A known HID lamp 10 as illustrated in FIG. 1 for use in an automotive headlight comprises a burner 12 with a discharge vessel 14 where light is generated by means of a discharge arc provided between the tips of a first electrode 16 and a second electrode 18 both terminating in the discharge vessel 14. The discharge vessel 14 is protected by a glass body 20. The glass body 20 of the burner 12 comprises a shaft 22 which is inserted into a socket 24. The first electrode 16 is led out of the proximal end of the shaft 22 in axial direction. Due to the shaft 22 a sufficient insulation is provided preventing a high voltage discharge between the first electrode 16 at the proximal end of the shaft 22 and the second electrode 18 which is also led into the socket 24 (not illustrated). A comparable burner is known from U.S. Pat. No. 6,731,076 B1.
There is a permanent need of optimizing the required building space of automotive headlights.

Burner with reduced height and method of manufacturing a burner


A display device includes a display panel and a frame body that has a lower frame, a mold member, and an upper frame, wherein the upper frame has a box shape with one surface opened along a side wall surface and the other surface forming an opening part, the mold member includes a mounting part that mounts a peripheral part of the display panel and a catching part formed in correspondence with an end surface of the display panel, the catching part of the mold member includes a first catching part having a top part opposite to the mounting part in contact with an inner surface of the upper frame and a second catching part with a projection height from the mounting part lower than a projection height of the first catching part.

1. Field of the Invention
This invention relates to a display device, and specifically to a technology of improving reliability with respect to adhesion of droplets or the like from the front surface of a display panel.
2. Description of the Related Art
A liquid crystal display device of related art includes a lower frame that houses a backlight unit having a light source, a light guide plate, a diffuser plate, etc. and a mold member for positioning an optical sheet and a liquid crystal display panel placed in front of the light guide plate or the diffuser plate. Further, the device includes an upper frame being a picture frame shape whose opening part corresponding to a display area of the liquid crystal display panel formed therein, fitting in the lower frame, holding the liquid crystal display panel, and protecting its peripheral edge. On the other hand, polarizers are respectively provided on the front surface and the rear surface of the liquid crystal display panel, and the optical sheet such as an optical film (viewing angle improving film) for improvement of the viewing angle etc. is provided on the image display surface side of the liquid crystal display device, i.e., on the front surface of the liquid crystal display panel. The optical sheet etc. are held in the picture frame area of the upper frame.
Accordingly, there have been problems that, in the case where a liquid like water droplets etc. enters the inside of the liquid crystal display device, when the liquid attaches to the formation region of signal lines, display defects may occur because of the short circuit of the signal lines, or when the liquid enters the region between the backlight unit and the liquid crystal display panel, display defects of display irregularities or the like may occur.
As a method for solving the problems, for example, there is a thin display device described in JP 2010-134168 A, for example. In the thin display device described in JP 2010-134168 A, entry of a liquid like droplets etc. entering from an intake and exhaust port formed on the rear surface side is prevented.


Digital design of an area is provided by obtaining input parameters for designing the area, comparing the input parameters to a design profile for the user, in which the design profile indicates user preferences regarding design elements, identifying design element(s) to be included in digital design(s) for the area based on correlating the input parameters with design element(s) from the design profile, generating the digital design(s), each of which incorporates at least one of the identified design elements, and displaying a digital design for potential selection to guide designing the area.

There are many resources available for obtaining inspiration to improve the aesthetics of a room, home, office, or other areas. Such sources of inspiration can include images of configured and designed rooms and homes. Often times these images are shared and viewed on social media platforms, enabling users of these platforms to select and save, pin, favorite, etc. these images for future reference. These saved images can later be referred to by the user when designing a room, either as part of a new setup or a renovation, rearrangement, or redesign of the room.

INTERNATIONAL BUSINESS MACHINES CORPORATION


A lithographic apparatus includes an illumination system for conditioning a beam of radiation, and an article support for supporting a substantially flat article to be placed in a beam path of the beam of radiation. The article support includes a plurality of supporting protrusions that define a support zone for providing a substantially flat plane of support. The apparatus also includes a backfill gas feed for providing an improved thermal conduction between the article and the article support. The backfill gas feed includes a backfill gas discharge zone for feeding backfill gas to a backside of the article when supported by the article support. The backfill gas discharge zone substantially encloses the support zone.

A lithographic apparatus is a machine that applies a desired pattern onto a target portion of a substrate. Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that circumstance, a patterning device, such as a mask, may be used to generate a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. including part of, one or several dies) on a substrate (e.g. a silicon wafer) that has a layer of radiation-sensitive material (resist). In general, a single substrate will contain a network of adjacent target portions that are successively exposed. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion in one go, and so-called scanners, in which each target portion is irradiated by scanning the pattern through the projection beam in a given direction (the "scanning"-direction), while synchronously scanning the substrate parallel or anti-parallel to this direction.
In the conventional lithographic projection apparatus, during photolithographic processes, an article, such as a wafer or reticle is clamped on an article support by a clamping force, that may range from vacuum pressure forces, electrostatic forces, intermolecular binding forces or just gravity force. The article support defines a plane, in the form of a plurality of protrusions defining an even flat surface on which the wafer or reticle is held. Tiny variations in the height of these protrusions may be detrimental to image resolution, because a small deflection of the article from an ideal plane orientation may result in rotation of the wafer and a resulting overlay error due to this rotation. In addition, such height variations of the article support may result in a height variation of the article that is supported thereby. During the lithographic process, such height variations may affect image resolution due to a limited focal distance of the projection system. Therefore, it is desirable to have an ideal flat article support.
European patent application EP0947884 describes a lithographic apparatus that has a substrate holder in which protrusions are arranged to improve the flatness of the substrate. These protrusions have a general diameter of 0.5 mm and are located generally at a distance of 3 mm away from each other, and thereby form a bed of supporting members that support the substrate. The height of the protrusions lies in the range 1 mu m-15 mu m. Due to the relative large spaces in between the protrusions, contaminations that may be present generally do not form an obstruction for the flatness of the substrate, because these tend to lie in between the protrusions and should not lift the substrate locally.
In the context of this application, the "article" may be any of the above mentioned terms of wafer, reticle, mask, or substrate, or more specifically, may be a substrate to be processed in manufacturing devices employing lithographic projection techniques, or a lithographic projection mask or mask blank in a lithographic projection apparatus, a mask handling apparatus such as mask inspection or cleaning apparatus, or a mask manufacturing apparatus or any other article or optical element that is clamped in the light path of the radiation system.
In lithographic processing, passing of the projection beam through gas compositions present between the illumination system and the articles to be illuminated, in particular non-homogenous gas compositions, may cause undesired effects such as diffraction, refraction and absorption. These effects may have an adverse effect on illumination quality, in particular, on a required resolution to be reached for the ever increasing demand in imaging performance. A new generation of lithography, the EUV-lithography, which uses a projection beam in the Extreme UltraViolet area, therefore operates in (near) vacuum conditions in order to allow the projection beam of radiation to pass substantially unhindered to the article to be placed in the beam. In this context, the term vacuum pressure is relative to particular gasses that are present in the environment. For example, for carbonhydrogens and water, the allowable background pressure is typically very low, in the order of 1e-9-1e-12 millibar. For inert gasses, the requirements may be less strict, for example, for Ar, an allowable background pressure ranges from 1e-4 mbar-1e-2 mbar, in particular, a pressure of 1e-3 mbar. Also, the relative background pressure may vary in terms of the environment of the apparatus. For example, where the article support functions in the environment of a wafer support, the vacuum requirements for certain components may be less strict than in an environment where the article support functions as a reticle support. That is, the partial pressures for contaminants (such as CxHy and H2O) may differ by a factor of 100 between the optics compartment (including reticle support) and the wafer compartment, and may be much lower than the total pressure (typical numbers are 1e-9 to 1e-12 mbar).
This vacuum technology offers challenges in terms of temperature control. For example, in some cases, the article support may have only a very small part (ranging from 0.1 to 3% of a total area) of the bottom side of the article that actually makes physical contact with the article support when being supported thereby, because the protrusions are shaped to provide only a very small contact area, and the protrusions are furthermore spaced relatively wide apart. In the vacuum pressure ranges that are used, thermal conductivity is substantially proportional to the pressure, which means that the thermal energy absorbed by the article when placed in the projection beam may no longer be adequately diverted, so that unwanted thermal heating of the article support may lead to thermal expansion, and may also lead to projection inaccuracies or potentially to even the loss of the article. To overcome this problem, in some instances, use is made of a so-called back-fill gas, which offers a thermal conduction from the article to the article support to divert the thermal energy absorbed by the article. The article support may be further provided with a cooler such as cooling ducts having cooling media etc. However, to confine the back-fill gas to the bottom side of the article, the conventional approach typically provides a so-called "hard rim", which is a boundary wall that substantially seals off the backfill gas from the vacuum by forming a gas seal between the bottom side of the article and the upper side of the article support.
It has been found, however, that, in terms of illumination performance, such a hard rim may cause problems. The presence of a sealing rim provides additional support to carry the article. Such additional support may disturb the pressure load of the article, which may cause local bending of the article. Such bending introduces rotation of the article surface, which may cause overlay effects that are undesired. Furthermore, a sealing rim provides almost a doubling of the contact area between the article and article support. This may be undesirable because it is an aim to minimize such contact area in order to prevent contamination particles to come in between the contact zones, which may create unevenness of the support and any corresponding bending problems of the article.
Furthermore, the presence of such a hard rim defines a definite outer area of the article where no backfill gas is present to provide thermal conductivity. This may cause local overheating or undesired temperature gradients in the article.

Lithographic apparatus and device manufacturing method


A semiconductor circuit device is disclosed in which an impurity ion implanted region is formed in a substrate, a Schottky junction type gate electrode is formed above the impurity ion implanted region, and a source electrode and a drain electrode are formed on both sides of the gate electrode. In this device, an InGaP barrier layer is formed between the substrate and the electrodes, a cap layer comprising a semiconductor free from In as a constituent is formed between the InGaP barrier layer and the electrodes, and the gate electrode is formed of a refractory metal.

1. Field of the Invention
This invention relates to a semiconductor circuit device called a Schottky junction Field-Effect Transistor, or a Schottky gate FET, or a MEtal-Semiconductor Field-Effect Transistor (MESFET), and a method for production thereof.
2. Description of the Prior Art
As is well known, the semiconductor circuit device is a transistor having a basic structure as illustrated in FIG. 1. A relatively high resistant n type semiconductor layer 2 serving as a channel is formed on a semi-insulating substrate 1. Onto the n type semiconductor layer 2 are joined a metal gate 3 making a Schottky contact with a channel 2c, and a source 4 and a drain 5 making an ohmic contact with the channel 2c with the gate 3 being interposed therebetween.
The operating principle for the semiconductor circuit device is that a depletion region 6 occurs at the junction between the gate 3 and the channel 2c owing to a reverse voltage applied to the gate 3, thereby narrowing the width of the channel 2c, the path for electrons. In this device, therefore, the channel width is varied by a gate voltage to control a drain current.
So far, three methods have been known for producing such a semiconductor circuit device.
A first method will be explained hereinbelow with reference to the formation of two transistors on one substrate. This method is composed of the following 5 steps as shown in FIGS. 2A through 2E:
A) A semi-insulating semiconductor substrate 1 comprising a III-V compound semiconductor is made ready for use. A GaAs substrate is used, for example.
B) A patterned mask layer 10A is formed on the substrate 1. With the mask layer 10A used as a mask, n type impurity ions 11A are implanted to form an ion implanted region 2A.
C) After the mask layer 10A is removed, a patterned mask layer 10B is formed on the substrate 1. With the mask layer 10B used as a mask, n type impurity ions 11B are implanted to form an ion implanted region 2B.
D) After the mask layer 10B is removed, the substrate is annealed to activate the implanted ions and convert the ion implanted regions 2A, 2B into active layers (n type semiconductor regions). On the ion implanted regions 2A, 2B are formed metal gates 3 which make a Schottky contact with these regions.
E) On the ion implanted regions 2A, 2B and on both sides of the gate 3 are formed a source electrode 4 and a drain electrode 5 which make an ohmic contact with these regions.
A second method will be explained hereinbelow with reference to the formation of two transistors on one substrate. This method is composed of the following 5 steps as shown in FIGS. 3A through 3E:
A) A semi-insulating semiconductor substrate 1 comprising a III-V compound semiconductor is made ready for use. A GaAs substrate is used, for example. A conductive semiconductor layer 2 is grown on the substrate 1.
B) A patterned mask layer 10A is formed on the conductive semiconductor layer 2. With the mask layer 10A used as a mask, the conductive semiconductor layer 2 is etched to a desired thickness.
C) With the mask 10A being retained, a patterned mask layer 10B is formed on the remaining surface of the conductive semiconductor layer 2. With the mask layers 10A, 10B used as masks, those portions of the conductive semiconductor layer 2 which are other than the portions covered by these mask layers 10A, 10B are removed by etching.
D) After the mask layers 10A, 10B are removed, metal gates 3 which make a Schottky contact with the conductive semiconductor layers 2, 2 are formed on these layers.
E) On each conductive semiconductor layer 2 and on both sides of the gate 3 are formed a source electrode 4 and a drain electrode 5 which make an ohmic contact with the layer 2.
A third method will be explained hereinbelow with reference to the formation of one transistor on one substrate. This method is composed of the following 5 steps as shown in FIGS. 4A through 4E:
A) A semi-insulating semiconductor substrate 1 comprising a III-V compound semiconductor is made ready for use. A GaAs substrate is used, for example.
B) A patterned mask layer 10A is formed on the substrate 1. With the mask layer 10A used as a mask, n type impurity ions 11A are implanted to form an ion implanted region 2A.
C) With the mask 10A being retained, a patterned mask layer 10B is formed on the remaining surface of the substrate 1, i.e. on the ion implanted region 2A. With the mask layer 10B used as a mask, n type impurity ions 11B are implanted on both sides of the ion implanted region 2A to form ion implanted regions 2B, 2B.
D) After the mask layers 10A, 10B are removed, the substrate is annealed to activate the implanted ions and convert the ion implanted regions 2A, 2B into active layers. On the ion implanted region 2A is formed a metal gate 3 which makes a Schottky contact with this region.
E) On the ion implanted region 2B and on both sides of the gate 3 are formed a source electrode 4 and a drain electrode 5 which make an ohmic contact with this region.
The above-described first method and second method are both capable of producing two transistors with different characteristics on a single substrate. Compared with the second method involving etching done twice, the first method using the ion implantation technique is evidently easier to carry out.
The third method, on the other hand, is advantageous in that the n type semiconductor region connected to the source electrode and the n type semiconductor region connected to the drain electrode can have a sufficiently high n type impurity concentration, and source electrode resistance and drain electrode resistance can be lowered. Such a semiconductor circuit device of a structure with a low source electrode resistance and a low drain electrode resistance can be prepared by a method employing etching, like the second method. Clearly, however, the third method is easier to perform than the method using etching.
Of the conventional methods, the first and third methods are thus superior to the other method. However, the two methods and semiconductor circuit devices obtained by them pose the following problems:
In semiconductor circuit devices obtained by the first and third methods, the n type semiconductor region serving as the active layer is formed by implanting ions into the semi-insulating semiconductor substrate. Therefore, the characteristics of the active layer formed depend on the material characteristics of the semi-insulating semiconductor substrate, the matrix. The semi-insulating semiconductor substrate material often contains impurities, undesirable for the characteristics of the active layer, in amounts that cannot be neglected. Consequently, these conventional methods involve the first problem that the semiconductor circuit device produced cannot exhibit the intended characteristics.
Furthermore, the n type semiconductor region serving as the active layer is formed by implanting ions into the semi-insulating semiconductor substrate, as has been stated previously. Thus, the semi-insulating semiconductor substrate portion and the active layer are integral and have no interface therebetween. That is, the surface of the n type semiconductor region that functions as the active layer and the surface of the semi-insulating semiconductor substrate are coplanar. This means that there is no layer which will prevent electrons in the n type semiconductor region from migrating onto the surface of the semi-insulating semiconductor substrate. On the surface of the semi-insulating semiconductor substrate, on the other hand, a defect layer is often formed during or after the production of the device. In the presence of this defect layer on the surface of the semi-insulating semiconductor substrate, electrons in the n type semiconductor region easily arrive at the defect layer, because there is no layer which will prevent such electrons from migrating onto the surface of the semi-insulating semiconductor substrate, as has been described. As a result, when the transistor becomes operative, noises occur in the defect layer, deteriorating the performance of the device noticeably. This is a second problem with the aforementioned conventional methods, and semiconductor devices produced by them.
No solutions have been proposed to the first problem, while the following solution has been put forward to the second problem:
The solution is in the method described in the three publications: Japanese Patent Application Laying-open No. 216636/1992 (Japanese Patent Application No. 411177/1990), "GaAs SURFACE PASSIVATION BY InGaP THIN FILM," Mat. Res. Soc. Symp. Proc. Vol. 240, pp. 777-781, and "Si-implanted InGaP/GaAs metal-semiconductor field-effect transistors," Appl Phys Lett 60(16), 20 Apr. 1992. The method described in these publications comprises forming on a substrate comprising GaAs an InGaP layer having a wider energy bandgap than that of the substrate, and implanting impurity ions into the GaAs substrate through the InGaP layer to form an impurity ion implanted region which will function as an active layer. This method is free from the above-described drawback that electrons in the impurity ion implanted region serving as the active layer move and reach the defect layer present on the substrate surface, since the InGaP barrier layer with a wide energy bandgap is interposed between the substrate surface and the impurity ion implanted region.
An attempt to attain further improvements in efficiency and performance in that method and the semiconductor circuit device obtained thereby, however, causes anew the problems described below.
A method for producing a semiconductor circuit device efficiently using a refractory metal as a gate electrode material has been proposed which comprises implanting impurity ions into the substrate through the gate electrode as a mask, annealing the substrate as such to activate the impurity ion implanted region. This method is introduced, say, in "Reactively sputtered WSiN film suppresses As and Ga outdiffusion,"J. Vac. Sci. Technol. B 6(5), Sept./Oct. 1988, pp. 1526-1529. This literature also reports that WSiN is ideal as a refractory metal for a gate electrode.
When such a method involving the use of a refractory metal as a gate electrode material and the implantation of impurity ions through the gate electrode as a mask is applied to the production of the aforementioned semiconductor circuit device having an InGaP barrier layer, the following problem appears, making the method impracticable.
That is, annealing causes a reaction between the gate electrode and the InGaP layer, deteriorating the Schottky junction characteristics, thus bringing about an ohmic junction. This problem occurs likewise in the presence of heat subsequently applied to the device, even if a gate electrode is formed after the implantation of impurity ions into the substrate is completed and the impurity ion implanted region is activated by annealing.
This invention aims to solve both of the above-mentioned problems: The first of them is that when there is formed an InGaP layer suitable as a barrier layer for preventing the migration of electrons from the impurity implanted region serving as the active layer into the defect layer present on the substrate surface, the Schottky junction deteriorates and becomes an ohmic junction, if the gate electrode making a Schottky contact with the InGaP layer undergoes heat. The second problem is that the active layer is influenced by the material characteristics of the substrate, thus failing to give the desired characteristics. Through this solution, the invention is intended to provide a semiconductor circuit device with high performance.

Semiconductor circuit device and method for production thereof

Nippon Telegraph and Telephone Corporation


The present invention provides a computer that includes a processor part having a top side and a bottom side. A keyboard part, having a key side and back side, is pivotally connected to the processor part. The computer of the present invention includes a display part having a screen side and a back side. In some embodiments, the display part is pivotally connected to the processor part. In other embodiments, the display part is pivotally connected keyboard part. The keyboard part is configured to lie against the processor part in a closed position, with the key side of the keyboard part facing away from the top side of the processor part. The display part is configured to lie against and cover the keyboard part in the closed position, with the screen side of the display part facing toward the key side of the keyboard part. The display part is movable from the closed position to a first open position in which the keyboard part remains lying against the processor part with the key side of the keyboard part exposed. The keyboard part and the display part are movable to a second open position in which the display part lies against the processor part and the display part lies against the processor part.

1. Technical Field
The present invention relates generally to the field of portable computer, such as notebook or laptop computers, and more particularly to a trifold laptop computer that is well suited for use with an external display monitor.
2. Description of the Related Art
Portable computers, such as notebook computer and laptop computers, have become very popular. Laptop computers have provided a very convenient way for computer users to work away from their offices. With the increase in power and memory in laptop computers, many users use their laptop computers as their primary computer rather than using separate desktop computers in their offices.
Many users prefer to use a large desktop monitor when they are working in their offices rather than the smaller display of a laptop computer. Some users use docking stations or port replicators to connect their laptop computer to an external mouse, keyboard, and monitor. However, the docking station or port replicator is an extra piece of equipment and many users would prefer to use their laptop keyboard and point device rather than an extra keyboard and mouse. Users can open their laptops and use that onboard keyboard and pointing device while the laptop computer is connected to a monitor. However, the laptop display obscures their view of the monitor. A user can place the laptop to the side of the monitor, but this results in an uncomfortable and non-ergonomic working position.

International Business Machines Corporation


A light guide plate (300) includes a light incidence surface (310) for receiving light beams, a light-emitting surface (320) for guiding light beams out of the light guide plate, and a bottom surface (330) reflecting and scattering light beams in directions toward the light-emitting surface. The bottom surface includes scattering-dots (341), and a predetermined region of the bottom surface also includes sub-scattering-dots (342). At least one sub-scattering-dot is disposed around each scattering-dot. The sub-scattering-dots are smaller than the scattering-dots. With this micro-configuration, intensities of light beams output from the light guide plate are uniform and bright.

1. Field of the Invention
The present invention relates to light guide plates, and particularly to a light guide plate used for a liquid crystal display.
2. The Prior Art
In a typical liquid crystal display, a backlight module provides a surface light source for illuminating the liquid crystal display. Generally, the backlight module includes a light guide plate and a light source arranged adjacent to one side of the light guide plate. The light guide plate changes light beams received from the light source into surface light beams, and directs the surface light beams to a liquid crystal panel of the liquid crystal display.
FIG. 8 shows a conventional backlight module 100. The backlight module 100 comprises a light source 110, a light guide plate 120, a diffuser 130, and a prism sheet module 140. The light guide plate 120 includes a light incidence surface 121, a light-emitting surface 122, and a bottom surface 123.
Referring to FIG. 9, a distribution of scattering-dots 124 on the bottom surface 123 of the light guide plate 120 is shown. To improve the uniformity of the surface light beams of the backlight module 100, the scattering-dots 124 are evenly arranged on the bottom surface 123 of the light guide plate 120.
With this configuration, when light beams from the light source 110 enter the light guide plate 120 from the light incidence surface 121, the scattering-dots 124 reflect and diffract the light beams. The light beams are thus changed into uniform surface light beams, which are output from the light-emitting surface 122 of the light guide plate 120. However, in one or more predetermined regions of the light guide plate 120, especially one or more small regions, it is difficult to control and micro-adjust the configuration of the scattering-dots 124 to ensure uniformity and brightness of the output light beams.
FIG. 10 is a simplified view of a plurality of scattering-dots 230 on a bottom surface 210 of another conventional light guide plate 200. Sizes of the scattering-dots 230 progressively increase with increasing distance away from a light incidence surface 220. With this configuration, the uniformity and brightness of light beams output from a light-emitting surface (not shown) can be improved overall. However, in one or more predetermined regions of the light guide plate 200, especially one or more small regions, it is difficult to control and micro-adjust the configuration of the scattering-dots 230 to ensure uniformity and brightness of the output light beams.
A new light guide plate with a new distribution of scattering-dots on a bottom surface thereof is desired in order to overcome the above-described problems.

Light guide plate including sub-scattering-dots


A method of controlling a unipolar semiconductor laser in the 4-12 xcexcm mid-infrared range. This is an optical control method, unlike a purely electrical, power control method which injects a relatively large flux of electrons. The optical control method may advantageously include two optical beams of the same wavelength and a device for making those beams interfere in the active layer of the laser, the optical control beams having a much shorter wavelength than the wavelength of the unipolar laser and having a frequency capable of being modulated more rapidly than that of the laser.

1. Field of the Invention
The field of the invention is that of unipolar semiconductor lasers, particularly that useful for generating wavelengths in the 4-12 xcexcm mid-infrared range.
2. Discussion of the Background
The operation of this type of laser is illustrated in FIG. 1. Such a unipolar laser is produced from a stack of layers of semiconductor materials, of calibrated thickness so as to produce quantum-well structures having discrete energy levels. This type of laser has already been described in the literature, and especially in the following references: F. Capasso, A. Y. Cho, J. Faist, A. L. Hutchinson, S. Luryi, C. Sirtori and D. L. Sivco xe2x80x9cUnipolar semiconductor laserxe2x80x9d EP 95 302112.8. J. Faist, F. Capasso, D. L. Sivco, C. Sirtori, A. L. Hutchinson and A. Y. Cho, Quantum cascade laser, Science, vol. 264, p. 553, J. Faist, F. Capasso, C. Sirtori, D. L. Sivco, J. N. Baillarjeon, A. L. Hutchinson, S. N. G. Chu and A. Y. Cho xe2x80x9cHigh power mid-infrared (xcexxcx9c5 xcexcm) quantum cascade laser operating above room temperaturexe2x80x9d, Appl. Phys. Lett., vol. 68, p. 3680. C. Sirtori, J. Faist, F. Capasso, D. L. Sivco, A. L. Hutchinson and A. Y. Cho, xe2x80x9cQuantum cascade laser with plasmon enhanced waveguide operating at 8-4 xcexcm wavelengthxe2x80x9d, Appl. Phys. Lett., vol. 66, p. 3242. Unipolar lasers, which are generally cascaded lasers, involve transitions between discrete energy levels within the conduction band, that is to say for example between the levels E1 and E2 illustrated in FIG. 1. When a flux of electrons is injected into the structure, during the transition of the electrons from the energy level E2 to the energy level E1 there is an emission of photons hxcexd=E2xe2x88x92E1. The energy levels involved in this type of structure thus generate wavelengths in the mid-infrared, which is difficult to obtain using other more conventional methods.
At the present time, in order to achieve power control, or even amplitude modulation, in such lasers, a purely electrical control method is used which consists in injecting a relatively large flux of electrons into the said laser.
In electrical modulation, it can be difficult to obtain very high modulation rates. The power supplies able to rapidly switch the high currents for supplying these lasers are in fact xe2x80x9ctop-of-the-rangexe2x80x9d power supplies.
This is why the invention proposes an optical method of controlling a unipolar laser. This method uses optical control beams of much shorter wavelength than the wavelength of the unipolar laser and therefore of a frequency that can be modulated very rapidly.
More specifically, the subject of the invention is a method of controlling a unipolar semiconductor laser comprising a stack of semiconductor layers so as to create a quantum-well structure having, in at least one of the semiconductor layers called an active layer, at least a first discrete energy level E1 and a second discrete energy level E2 in the conduction band, so as to create an electrically excited laser emission with a photon energy corresponding to the difference in energy levels between the said first energy level and the said second energy level, characterized in that it comprises the optical pumping of the said active layer or of another layer in the stack by optical means emitting at least one control beam at a wavelength, of photon energy greater than or equal to the band gap of the optically pumped layer.
In general, semiconductor lasers are lasers having a large number of optical modes, as shown schematically in FIG. 2. One way of making such lasers monomode consists in creating, within the active layer, a diffraction grating whose period fixes the emission wavelength and therefore the mode. At the present time, the diffraction grating may be obtained by a grating etched into the structure as the article by J. Faist et. al. in Proceedings of the CLEO conference, 1997 illustrates.
This is why the invention advantageously proposes to implement the optical control of the unipolar laser using two optical beams capable of interfering, the optically created diffraction grating making it possible to produce an optically controlled monomode unipolar laser which is easier to fabricate than that requiring etching operations.
More specifically, the subject of the invention is also a method of optically controlling a unipolar semiconductor laser, characterized in that the optical control means comprise two optical beams of the same wavelength and means for making the said beams interfere in the stack of semiconductor layers making up the laser, so as to create an interference fringe grating within the said stack.
According to one embodiment of the invention, the optical control fringe grating may be obtained from a single control laser and from means for recombining the said beams, using conventional interference methods.

Method for controlling a unipolar semiconductor laser


In the output circuit, at a subsequent stage of a gate circuit operating with a power supply voltage related to a first power supply voltage, a latch circuit formed of an inverter circuit and a MOS transistor is arranged, and is supplied with a second power supply voltage as an operating power supply voltage. An output buffer circuit is driven in accordance with an output signal of the latch circuit. When the first power supply voltage is powered down, the latch circuit receiving and operating with the second power supply voltage holds a signal voltage to be attained in a standby state and thus the output buffer circuit is reliably held in an output high impedance state. In a semiconductor device of a double power supply configuration, even when one power supply is powered down, the output buffer circuit can reliably be set to an output high impedance state.

1. Field of the Invention
The present invention relates generally to semiconductor devices and particularly to a configuration of an output circuit driving an external bus signal line in response to an internal signal. More specifically, the present invention relates to a configuration of signal output circuitry of a semiconductor device supplied with an output power supply voltage used for outputting a signal and an external power supply voltage used for driving an internal circuit, separately.
2. Description of the Background Art
FIG. 11 schematically shows a configuration of a main portion of a conventional semiconductor device. The semiconductor device 900 includes an internal power supply circuit 901 generating various kinds of internal voltage from an external power supply voltage EXVDD, a memory circuit 902 operating in accordance with the various kinds of internal voltage generated by internal power supply circuit 901, and an output circuit 903 receiving an externally supplied output power supply voltage VDDQ as an operating power supply voltage to buffer data read from memory circuit 902 and externally output the data.
Internal power supply circuit 901 generates an internal power supply voltage used by memory circuit 902 as an operating power supply voltage, an intermediate voltage, a reference voltage and others. For the purpose of simplifying the figure, however, FIG. 11 typically shows a peripheral power supply voltage VDDP generated by internal power supply circuit 901. Normally, external power supply voltage EXVDD is, for example, not lower than 2.5V and output power supply voltage VDDQ is, for example, 1.8V. When external power supply voltage EXVDD is 2.5V, external power supply voltage EXVDD is used as peripheral power supply voltage VDDP. In this case, an array power supply voltage used by a memory cell array included in memory circuit 902 is generated by down-converting external power supply voltage EXVDD. Peripheral power supply voltage VDDP is indicated so as to distinguish peripheral power supply voltage VDDP from external power supply voltage EXVDD in the description.
Memory circuit 902 includes the memory cell array, a row and column select circuit selecting a memory cell of the memory cell array, an internal data read circuit and others.
By applying output power supply voltage VDDQ exclusively to output circuit 903, memory circuit 902 can be stably operated with internal power supply voltage VDDP generated from external power supply voltage EXVDD, even if the output power supply voltage VDDQ varies due to an operation of output circuit 903 consuming output power supply voltage VDDQ. Even when multi-bit data DQ is generated to be transferred, memory circuit 902 can be operated stably without affect due to variation of output power supply voltage VDDQ.
Furthermore, with output power supply voltage VDDQ exclusively supplied to output circuit 903, output circuit 903 can be supplied with an operating power supply voltage with sufficiency, and output circuit 903 can thus be operated in stable manner.
FIG. 12 schematically shows a configuration of a portion of output circuit 903 that is related to outputting of one bit of data. In FIG. 12, output circuit 903 includes an NAND circuit 906 receiving internal read data RD read from an internal read circuit 905 included in memory circuit 902 and an output enable signal OEM, a gate circuit 907 receiving internal read data RD and output enable signal OEM, a level conversion circuit 908 converting the amplitude of a signal output from NAND circuit 906 to the level of output power supply voltage VDDQ, a level conversion circuit 909 converting the amplitude of a signal output from gate circuit 907 to the level of external power supply voltage EXVDD, an inverter circuit 910 inverting a signal output from level conversion circuit 909, and an output buffer circuit 912 driving an output node 920 in response to a signal output from level conversion circuit 908 and a signal output from inverter 910.
Internal read circuit 905 is included in memory circuit 902 shown in FIG. 11, includes a preamplifier circuit and others, and receives peripheral power supply voltage VDDP as an operating power supply voltage and generates internal read data RD having the amplitude of the peripheral power supply voltage VDDP level.
NAND circuit 906 and gate circuit 907 receive peripheral power supply voltage VDDP as an operating power supply voltage. When output enable signal OEM is at a logical low level or L level, NAND circuit 906 outputs a signal of a logical high level or H level. When output enable signal OEM attains an H level, NAND circuit 906 operates as an inverter to invert internal read data RD.
When output enable signal OEM is at L level, gate circuit 907 outputs a signal of the H level and when output enable signal OEM attains the H level, gate circuit 907 operates as a buffer circuit and generates an output signal in accordance with internal read data RD.
Level conversion circuit 908 receives output power supply voltage VDDQ as an operating power supply voltage and level conversion circuit 909 receives external power supply voltage EXVDD as an operating power supply voltage.
Level conversion circuits 908 and 909 simply perform the voltage level (or amplitude) conversion and do not perform conversion in logical level.
Output buffer circuit 912 includes a p-channel MOS transistor (an insulated gate field effect transistor) TP connected between an output power supply node and an output node 920 and having a gate thereof receiving a signal output from level conversion circuit 908, and an n-channel MOS transistor TN connected between output node 920 and a ground node and having a gate thereof receiving a signal output from inverter circuit 910.
When output enable signal OEM is at L level, NAND circuit 906 and gate circuit 907 each output a signal of the H level, and level conversion circuit 908 outputs a signal at the output power supply voltage VDDQ level and level conversion circuit 909 outputs a signal at the external power supply voltage EXVDD level. Inverter 910, receiving external power supply voltage EXVDD as an operating power supply voltage and inverting a signal output from level conversion circuit 909, outputs a signal of the L level.
MOS transistors TP and TN in output buffer circuit 912 are both turned off and thus output buffer circuit 912 attains an output high impedance state.
When output enable signal OEM attains the H level, NAND circuit 906 operates as an inverter, while gate circuit 907 operates as a buffer circuit. When internal read data RD is at H level, NAND circuit 906 outputs a signal of L level and gate circuit 907 outputs a signal of H level. Thus, level conversion circuit 908 outputs a signal of L level and inverter circuit 910 outputs a signal of L level. Thus, MOS transistors TP and TN in output buffer circuit 912 are turned on and off, respectively. In this state, output node 920 is driven to the output power supply voltage VDDQ level via MOS transistor TP.
When internal read data RD is at H level, NAND circuit 906 outputs a signal of H level and gate circuit 907 outputs a signal of L level. In response, inverter 910 outputs a signal of the external power supply voltage EXVDD level and output buffer circuit 912 has MOS transistors TP and TN turned off and on, respectively, and output node 920 is driven via MOS transistor TN to the ground voltage level. By applying a signal of the external power supply voltage level to the gate of MOS transistor TN via inverter circuit 910, the current driving capability of MOS transistor TN is increased to quickly discharge output node 920 to the ground voltage level.
FIG. 13 shows an exemplary configuration of level conversion circuit 908. In FIG. 13, level conversion circuit 908 includes an inverter 908a receiving a signal SIN output from NAND circuit 906, an n-channel MOS transistor 908b connected between an internal node NA and a ground node and having a gate thereof receiving signal SIN output from the NAND circuit, an n-channel MOS transistor 908c connected between an internal node NB and a ground node and having a gate thereof receiving a signal output from inverter 908a, a p-channel MOS transistor 908d connected between an output power supply node and internal node NA and having a gate thereof connected to internal node NB, and a p-channel MOS transistor 908e connected between an output power supply node and internal node NB and having a gate thereof connected to internal node NA. A signal SOUT output from level conversion circuit 908 is generated at internal node NB.
When signal SIN is at H level, MOS transistors 908b and 908c turn on and off, respectively. Thus, internal node NA is discharged via MOS transistor 908b to reduce in voltage level. In response, MOS transistor 908e turns on to charge internal node NB, and internal node NB is increased in voltage level to the output power supply voltage VDDQ level.
When internal node NB attains the output power supply voltage level, MOS transistor 908d turns off. Signal SIN of the peripheral power supply voltage VDDP level is thus converted to signal SOUT of the output power supply voltage VDDQ level.
When signal SIN is at L level, MOS transistors 908b and 908c turn off and on, respectively. In this state, internal node NB is discharged via MOS transistor 908c and is reduced in voltage level. In response, MOS transistor 908d turns on to charge internal node NA to the output power supply voltage VDDP level, and MOS transistor 908e responsively turns off. Thus, in this state, internal node NB outputs the signal SOUT of L level.
As described above, level conversion circuit 908 converts signal SIN of the peripheral power supply voltage VDDP level in amplitude to a signal of the VDDQ level in amplitude and does not perform logical level conversion.
The use of level conversion circuit 908 allows an internal circuit to be driven with the peripheral power supply voltage VDDP level and output buffer circuit 912 to generate a signal of the output power supply voltage level.
Furthermore, if peripheral power supply voltage VDDP is equal to external power supply voltage EXVDD and higher than output power supply voltage VDDQ, a signal applied to output buffer circuit 912 is converted in amplitude to the output power supply voltage level to equalize the rising and falling characteristics of the signal to the output buffer circuit. It is aimed to equalize the rising and falling characteristics in driving the output node by the output buffer circuit 912.
FIG. 14 schematically shows a configuration of a data processing system by way of example. In the processing system shown in FIG. 14, a processing unit 950, a semiconductor memory device 952 storing data used by processing unit 950 and a memory 954 separate from semiconductor memory device 952 are interconnected together through a bus 956.
Processing unit 950 receives power supply voltage VDDL and VDDQ as operating power supply voltages. Semiconductor memory device 952 receives power supply voltage EXVDD and VDDQ as operating power supply voltages. Memory 954 receives power supply voltage VDDL as an operating power supply voltage. When processing unit 950 transmits data to semiconductor memory device 952 through bus 956, processing unit 950 transfers a signal in accordance with output power supply voltage VDDQ to adapt the signal interface with semiconductor memory device 952.
In such a data processing system, if no access is made to semiconductor memory device 952 for a long period of time, processing unit 950 stops supplying external power supply voltage EXVDD at least to semiconductor memory device 952, via a power supply management unit (not shown). Processing unit 950 uses data stored in memory 954 to execute a processing.
As data/a signal is transferred between memory 954 and processing unit 950 through bus 956, output buffer circuit 912 shown in FIG. 12 is required to maintain an output high impedance state even when semiconductor memory device 952 is stopped of supplying external power supply voltage EXVDD while being supplied with output power supply voltage VDDQ. A MOS transistor turns off when its gate to source voltage goes below a threshold voltage in absolute value. Thus, for example in the configuration of FIG. 13, if peripheral power supply voltage VDDP generated from external power supply voltage EXVDD drops in level in response to stopping of supplying external power supply voltage EXVDD, there may be caused a case where the signal SIN set to H level in a standby state thereof is not discharged to the ground voltage level and the signal SIN is held at an intermediate voltage level. Similarly, the output signal from the inverter 908a might be held at an intermediate voltage level.
In this case, if level conversion circuit 908 has MOS transistors 908b and 908c both turned on or both turned off, internal nodes NA and NB has voltage at an uncertain level, and level conversion circuit 908 outputs an signal SOUT that is not held at output power supply voltage VDDQ level but at an intermediate voltage level. If such state is caused, MOS transistor TP in output buffer circuit 912 would possibly supply a current to output node 920.
Similarly also in the arrangement of FIG. 12, if supplying of external power supply voltage EXVDD is stopped, the output signal of inverter 910 could not discharged fully to the ground voltage level, and level conversion circuit 909 would have the output signal floating in level to an intermediate voltage level. In response, inverter 910 enters a state of outputting a signal held at an intermediate voltage level and the discharging MOS transistor TN turns conductive. Thus, in this state also, output buffer circuit 912 has MOS transistor TN turned conductive and drives output node 920 towards the ground voltage level, and output buffer circuit 912 thus does not enter the output high impedance state.
In semiconductor memory unit 952, if output buffer circuit 912 is set into a state different from the output high impedance state, a signal/data transferred in between memory 954 and processing unit 950 would be adversely affected by data outputted from output buffer circuit 912, and thus, a signal/data can not be transferred accurately.
The following state is considered. Processing unit 950 and semiconductor memory device 952 are interconnected together via bus 956 and processing unit 950 is interconnected to memory 954 via a different bus. In addition, the bus interconnecting processing unit 950 and semiconductor memory device 952 has a signal line terminated to a voltage different in level from output power supply voltage VDDQ. Even in such state, if output buffer circuit 912 is set to a state different from the output high impedance state, a current would flow between output buffer circuit 912 and a terminating power source and current consumption thus disadvantageously increases.
An object of the present invention is to provide a semiconductor memory device having an output buffer circuit reliably is held at an output high impedance state even if an output power supply voltage is interrupted while an output power supply voltage is supplied.
A semiconductor device according to a first aspect of the present invention includes: a first output drive signal generation circuit receiving a first power supply voltage as an operating power supply voltage and for generating a first output drive signal in response at least to an internal signal; a first latch circuit receiving a second power supply voltage as an operating power supply voltage and latching and transferring the first output drive signal; and a first output transistor receiving the second power supply voltage as an operating power supply voltage and in response to a signal output from the first latch circuit for driving an output node.
A semiconductor device according to a second aspect of the present invention includes first circuitry receiving a first power supply voltage as an operating power supply voltage thereof and generating a first signal in accordance with a received signal, and second circuitry receiving a second power supply voltage as an operating power supply voltage thereof and generating a second signal in accordance with the first signal. The second circuitry includes a latch circuit receiving the first signal at an input and latching a signal voltage at the input.
According to the arrangement of the present invention, the latch circuit is provided which receives the second power supply voltage as the operating power supply voltage and the output transistor or an output driving circuit is driven in accordance with the output signal of the latch circuit. Even if supplying of the first power supply voltage is interrupted, the latch circuit latches the state of the signal immediately before the interruption of supply of the first power supply voltage. Thus, the output transistor or the output driving circuit can be held in the state immediately before the interruption of the first power supply voltage to hold the output high impedance state. Accordingly, the output circuit can be reliably held in the output high impedance state upon interruption of the supply of the first power supply voltage, to prevent the collision of a signal/data on an external bus from occurring.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


A system for identifying dental objects, visualizing a dental image, and method for identifying dental anomalies are described. The system for identifying dental objects comprises a 3-D dental image, a database, a digital processing component, and an interactive graphical user interface is described. The 3-D dental image is generated by a medical imaging device. The database has data fields that include locations for teeth, locations for each section of tooth, standard shapes associated with individual teeth, standard shapes associated with each of the sections of tooth, and bone density data for each section of tooth. The digital processing component is configured to process the 3-D image and is in operative communication with the database. The digital processing component is configured to identify an object by combining a plurality of voxels having a common density and tagging the object. The interactive graphical user interface (GUI) permits the user to interact with the object.

1. Field of Invention
The invention is related to analyzing three dimensional (3-D) images. More particularly, the invention is related to systems and methods for identifying objects associated with the 3-D images.
2. Description of Related Art
Generally, dental images are displayed in two-dimensions using light tables, e.g. X-rays. These two dimensional views provide a single perspective of the image. Three-dimensional (3-D) imaging systems have also been developed. These systems provide high-definition digital imaging with relatively short scan times, e.g. 20 seconds. The image reconstruction takes less than two minutes. The X-ray source is typically a high frequency source with a cone x-ray beam, and employs an image detector with an amorphous silicon flat panel. The images are 12-bit gray scale and may have a voxel size of 0.4 mm to 0.1 mm. Image acquisition is performed in a single session and is based on a 360 degree rotation of the X-ray source. The output data are digital images that are stored using conventional imaging formats such as the Digital Imaging and Communications in Medicine (DICOM) standard.
The 3-D volumetric imaging system provides complete views of oral and maxillofacial structures. The volumetric images provide complete 3-D views of anatomy for a more thorough analysis of bone structure and tooth orientation. These 3-D images are frequently used for implant and oral surgery, orthodontics, and TMJ analysis. There are a variety of different software solutions that can be integrated into the 3-D dental imaging systems. These third party solutions are generally related to implant planning, and assist in planning and placement of the implants. Additionally, the 3-D dental images can be used for developing models to assist in planning an operation.
In spite of the advances in the 3-D imaging systems and the 3-D imaging software, the software techniques for visualization of the dental images do not provide a dentist with sufficient flexibility to manipulate the 3-D image. Additionally, the visualization features provided by current third party solutions lack the ability to detect objects, detect irregularities, and detect anomalies.

System and method for object identification and anomaly detection


A heating system includes: an alkaline secondary battery and a controller. The alkaline secondary battery includes: a power generating element configured to be charged or discharged; and a battery case that accommodates the power generating element in a hermetically sealed state. The controller is configured to control charging and discharging of the alkaline secondary battery, and, when an internal pressure of the alkaline secondary battery is higher than or equal to a first threshold, execute a heating process for heating the alkaline secondary battery by decreasing the internal pressure through discharging of the alkaline secondary battery. The heating process is a process of raising a temperature of the alkaline secondary battery.

1. Field of the Invention
The invention relates to a heating system, and a battery system that raise the temperature of an alkaline secondary battery.
2. Description of Related Art
In Japanese Patent Application Publication No. 2003-102133 (JP 2003-102133 A), the SOC of a secondary battery, at which the amount of heat generated by the secondary battery is maximum, is calculated. The secondary battery is charged or discharged such that the SOC follows the calculated SOC. Thus, the secondary battery is heated.


The debarking chain includes a quick disconnect for attaching the debarking chain to a drum. A connecting link is releasably attached to the drum. A chain comprised of closed links is attached to the drum via the connecting link by an open link which connects the connecting link to the end closed link on the chain. The open link includes an opening for receiving a reduced cross-section of one side of the end closed link. A terminal end is formed on the open link by the opening which will prohibit the end closed link from passing over the terminal end until the end closed link is rotated such that the length of its interior aperture is aligned with the longer dimension of the terminal end of the open link. Upon such alignment, the terminal end will pass through the aperture of the end closed link to connect the chain to the drum.

This invention pertains to chains in general and in particular to chains used for removing the bark from logs by flailing or beating.
Chains attached to rotating drums or cylinders have proven to be an efficient means for removing bark from trees. These chains wear out quickly because of high stress from repeatedly striking wood and other links of the chain. The chains must be replaced frequently.
The present method of attaching the chains to the drum is to slip one link of the chain into a slot or hole in the drum and slide a rod through an opening in the drum parallel to the drum axis and through the chain link. A problem with this is that a number of chains are attached to each drum and not all of the chains may need to be replaced at the same time. Also the attachment rod itself may become deformed during use and there may be difficulty inserting the rod through the drum for reattachment of the new chain.
Changing and rearranging flail chains is labor intensive and usually requires a two man crew. A man in the flail chamber positions new and rearranged chains in the rotor holes. A second man, on the outside of the flail debarker, reinserts the attachment rods through a small opening in the drum. Communication between the two men is necessary to avoid finger injuries. A two man crew can change and rearrange chains in about 30-45 minutes.
A major drawback to this chain servicing system is that not all the chains will normally need to be changed or rearranged. Flail chains also wear at different rates depending on their position on a rotor. Usually the chains attached to the center half of the drum will wear twice as fast as the chains attached near the end. The standard chain servicing system requires the attachment rods to be pulled completely out of the rotor to service the chains at the end of the rotor. Therefore, all the chains in a row have to be handled and reinserted in the rotor holes, even though some may be in good condition.
An additional problem with the debarking apparatus presently in use is that chains must be discarded before they are worn out. A new 9 link chain may be used until it has lost an end link. The service crew may then flip it to wear the other end until it has lost two more links. The chain is then discarded because it is too short to effectively debark logs; however, it still has 5-6 good links.


A method and apparatus for consolidating a plurality of applications into one or more servers. The method and apparatus organizes consolidation constraints representing preferences about placing applications into the one or more servers, and allocates the applications into the one or more servers in a manner that maximally satisfies the consolidation constraints.

Server consolidation is becoming one of the top priorities for many IT departments because the traditional way of dedicating one server to a single application will leave many servers under-utilized for most of the time. By aggregating workloads from separate machines into a small number of servers, we can boost the resource utilization rate, which in consequence save the power and space for enterprise data centers. With the recent resurgence of virtualization technology, the server consolidation can now be achieved by hosting multiple virtual machines (VM) in one physical machine, each of which encapsulates one application separately. The virtualization provides an abstract layer between the operating system and the hardware, which enables multiple VMs to share the same physical machine fairly with the minimum impact of system performance.
While server consolidation through virtualization brings a lot of advantages, some of the benefits are offset by the added system management complexity introduced by the consolidation. Instead of managing numerous physical machines, administrators are now facing a large number of virtual machines concentrated in a much dense, complex, and shared environment, in which the impacts of hardware failures, human errors, and security breaches can be vastly magnified. For example, any situation that requires a physical server re-boot, such as the hardware failure or system maintenance, will affect all the virtual machines in that physical machine rather than a single application. Similarly, the increased sharing of hardware by multiple applications may enhance the possibilities of revealing sensitive information to potential adversarial applications, which will compromise the security and privacy requirements of the system.
Accordingly, a method and an apparatus are needed to achieve server consolidation under multiple constraints.

Virtualization and consolidation analysis engine for enterprise data centers


A method of prioritizing a media stream belonging to a plurality of media streams associated with a communication session. The method includes: a first control entity generating or obtaining from a session control message priority information giving a relative priority to the stream within the session relative to the other streams of the plurality of media streams; and a second control entity inserting the priority information into a resource control message for sending to a media entity.

Several stream management methods are known in the prior art. In Internet protocol (IP) type networks, it is known in particular to combine the session description protocol (SDP) as defined in document RFC 4566 of the Internet engineering task force (IETF) with the session initiation protocol (SIP) as defined in document RFC 3261 likewise by the IETF, so as to set up, modify, or indeed terminate a multimedia communication session between two entities. In particular, the SDP protocol makes it possible to describe a set of data streams associated with one such multimedia communication session.
IETF document RFC 3264 entitled "An offer/answer model with the session description protocol" also describes a mechanism enabling two entities to use the SDP protocol in order to negotiate parameters relating to desired data streams for a session that is to be set up or modified. In that model, in order to set up or modify a session, a first entity submits an offer to a second entity, which offer is referred to as an "SDP offer" and is in the form of a session description. The offer comprises a list of media stream descriptions specifying, for each stream, in particular a type of medium (audio, video, text), a destination port number, a transport protocol, or indeed encoding information. The entity that submits the offer can thus inform the entity to which the offer is sent about the various media and characteristics (e.g. type of coding) associated therewith that it is capable of handling. The destination entity of the offer, e.g. as a function of the media and the codings that it is capable of handling, accepts the offer by sending an answer referred to as an "SDP answer" informing the entity that sent the offer about the media streams that it is capable of handling. The destination entity of the offer can also send a new offer to the first entity, e.g. corresponding to other media that it desires to add to the session. The two entities are thus equally capable of acting as the sender of an offer and as the destination of an offer. That offer/answer mechanism is also equally applicable to communication sessions involving more than two participants (e.g. a video conference having more than two participants).
When the network is saturated, the media streams as negotiated in this way while setting up or modifying a multimedia communication session are likely to be processed on a priority basis by an entity of the network. To do that, document RFC 4412, entitled "Communications resource priority for the session initiation protocol (SIP)" defines a "resource-priority" SIP header enabling a SIP request to be identified as requesting priority access to certain network resources (e.g. network gateways, routers, SIP proxies). The "resource-priority" SIP header field contains one or more domain names. When an entity of a control plane of the network receives an SIP message including the "resource-priority" SIP header, it verifies that the message is valid, and it identifies the services associated with the domain names of the "resource-priority" SIP header field. When the resources are saturated, the entity can preempt the other ongoing communication sessions that are not associated with an identified domain name, or it can put the SIP request including the "resource-priority" header field into a queue of requests for priority treatment. The mechanism described in document RFC 4412 thus makes it possible to give priority treatment to a communication session, and indirectly to all of the media streams associated with that session. Nevertheless, that priority is identical for all of the media streams associated with the session. Specifically, the mechanism described does not make it possible to specify relative priorities between streams of a given session.
Specification document TS 129 214 v.7.4.0 by the European Telecommunications Standards Institute (ETSI) entitled "Universal mobile telecommunications system (UMTS); policy and charging control over Rx reference point" also describes a mechanism enabling priority to be given to an IP stream within an application session between an application function (AF) application entity and a policy and charging rule function (PCRF) entity via a "reservation-priority" attribute inserted in a Diameter message. This attribute makes it possible, in a stream descriptor, to specify a relative priority for that stream within a session in which the stream is associated. Nevertheless, the prior art does not make provision for a mechanism enabling the application entity to determine or to be informed about the existence of a priority for the stream within the session relative to any possible other streams of the session. The priority of a stream within a session is unknown to the controlled entities of the network, which means that they cannot take account of the importance of one stream relative to other streams in a single session, e.g. in the event of network congestion, nor can they transmit such information to other entities of the network. End-to-end processing of the priority of a stream is thus impossible, at present.

Method for prioritising media streams in a communications network