A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

In recent years, reduction of a supply voltage for semiconductor integrated circuits has been pursued. In logic devices and memories mounted on portable devices and driven by batteries, in particular, lower power consumption (dissipation) is required.
In the semiconductor integrated circuit and the like, a delay circuit is employed so as to obtain signal timings required for operating respective circuits therein. On the other hand, in asynchronous, dynamic-type semiconductor memory devices that are not driven by an external clock signal, various timing signals are generated inside the semiconductor memory devices. More specifically, for various signals for controlling a memory core unit, a pulse signal is generated based on detection on a change in an address signal, a predetermined input signal, or the result of decoding of it, and a control signal in pulse form, which rises being delayed by a predetermined time and having a predetermined pulse width is generated from the pulse signal and its delayed signal.
As the background art of the present invention, an overview of an asynchronous dynamic RAM will be described below with reference to FIG. 6, which will be referred to in the embodiments of the present invention. Referring to FIG. 6, a peripheral circuit 10 controls driving of a word line driver 13 for driving a word line based on a signal indicating the result of operation by a logic circuit 12 that receives a signal supplied to a delay circuit 11 and the output of the delay circuit. A step up voltage (boost voltage) is supplied to a driving power supply of the word line driver 13 from a step-up converter (booster circuit 40). As the step-up voltage, a voltage obtained by adding a voltage exceeding a threshold voltage Vth of an NMOS transistor to a power supply voltage VDD is provided. It is noted that a reference voltage source 30 in FIG. 6 is specific to the embodiments in the present invention and is not included in the conventional dynamic RAM. In an NMOS transistor 203 of a memory cell 200 provided at an intersection between a word line and a bit line in a cell core unit 20, a high voltage not less than VDD+Vt is supplied to the gate connected to a selected word line 201 so that the output voltage of the NMOS transistor 203 can rise up to the power supply voltage VDD.
FIG. 7 is a diagram for explaining timing operations in the asynchronous dynamic RAM. When a transition in an address in memory cycle is detected by an ATD circuit not shown, an ATD signal is activated and then, a strobe signal φ p for activating a row address is generated based on this signal, the result of decoding the address signal, and a control signal not shown for controlling access to the memory. By a signal generated based on this signal φ p and its delayed signal, a word line rise timing and/or its pulse width are/is controlled. Likewise, a signal φ SE for controlling activation of a sense amplifier 14 for amplifying a signal read onto a bit line 16 or a Y switch enable signal not shown, a control signal for precharging the bit line to ½ VDD, and the like are generated.
As the delay circuit 11 of this type, an inverter-chain constituted by connecting a plurality of inverters in cascade, for example is employed. The number of the inverters constituting the delay circuit is set to an even when the delay circuit outputs a delayed signal in phase with the input signal, and the number of the inverters is even when the delay circuit outputs a delayed signal having a phase reversed from the input signal is output.
FIG. 15 shows a configuration example of a conventional delay circuit using a CMOS inverter-chain. As shown in FIG. 15A, the conventional delay circuit is constituted from a plurality of inverters JV1 to JV4 connected in cascade, and load capacitors constituted from MOS capacitors JN1 to JN4 are connected to respective outputs of the inverters. As shown in FIG. 15B, each inverter is constituted from an PMOS transistor MP301 having its source connected to a high-potential power supply VDD, an NMOS transistor MN301 having its gate and drain connected to the gate and drain of the PMOS transistor MP301 respectively, and having its source connected to a low potential power supply GND. When a signal input to common gates undergoes a transition from a low level to a high level, electric charge on the load capacitance connected to the common drain is discharged to the power supply GND through the NMOS transistor MN301 which is in an on state, so that its output goes low. When the signal input to the common gate undergoes a transition from the high level to the low level, the load capacitance connected to the common drains is charged from the power supply VDD through the PMOS transistor MP301 which is in an on state, so that the output of the inverter goes high. As described above, by charging and discharging the load capacitances of the outputs of the inverters, signal propagation is performed.
The fall tf and rise times (delays) tf and tr of a CMOS-type inverter (which are delay times required for 10 to 90% transition of an amplitude) are derived from formulas that depend on a load capacitance, power supply voltage, transconductance, and a ratio between the power supply voltage and its threshold value, based on a drain current-voltage characteristic in the nonsaturation region and the saturation region of a MOS transistor. The characteristic between drain-to-source current and voltage in the nonsaturation region is defined by gate-to-source voltage, drain-to-source voltage, threshold voltage, and transconductance, while the characteristic between drain-to-source current and voltage in the saturation region is defined by gate-to-source voltage, threshold voltage, and transconductance. Roughly, as is well known, the rise time tf and the fall time tr are approximated by:tf=k1×CL/(βn×VDD)tr=k2×CL/(βp×VDD)where CL indicates the load capacitance, β p and β n indicate respective transconductances of the PMOS transistor and the NMOS transistor of the CMOS inverter, VDD indicates the supply voltage, and k1 and k2 are constants.
When the power supply voltage VDD is high, the rise time tr and the fall time tf of the inverter are both reduced, so that a propagation delay time tpd of the inverter decreases. The propagation delay time tpd includes a propagation delay time tpHL from rise of an input signal to fall of an inverted output signal and a propagation delay time tpLH from the fall of the input signal to the rise of the inverted output.
On the other hand, when the power supply voltage VDD is reduced, the rise time tr and the fall time tf of the inverter are both increase, so that the propagation delay time of the inverter increases.
Due to increases in delay times of the inverters JV1 to JV4 constituting the delay circuit in FIG. 15, the propagation delay time of the delay circuit also increases. Further, as in the delay circuit constituted from the inverter chain, the propagation delay time of other circuit as well decrease/increase due to elevation and lowering of an operation supply voltage. Thus, the operation speed of the device becomes fast or slow.
Recently, due to the demands in regard to a breakdown voltage with the progress in miniaturization of devices and for lower power consumption, a configuration in which the supply voltage of the semiconductor device is stepped down and internal circuits are operated at a low voltage is generally employed. In the dynamic-type semiconductor memory device as well, an internal power supply voltage VINT obtained by reducing the power supply voltage VDD supplied externally by a voltage step-down circuit is employed as the supply voltage for a peripheral circuit and a cell core section (which is also referred to as a "memory cell array"). However, the semiconductor memory device that uses the stepped-down supply voltage sometimes cannot accommodate the reduction of the power supply voltage VDD. It is because if the internal power supply voltage VINT obtained by further stepping down the reduced power supply voltage VDD is employed, the operation speed of the device becomes slow, thereby making an access time slow, so that it sometimes happens that functional specifications are not satisfied.
The conventional circuit shown in FIG. 15 also has a problem: when the power supply voltage VDD is reduced, the delay time increases more compared with an increase in the amount of the delay of an ordinary logic circuit, so that it sometimes happens that timing relationship among signals is not satisfied. This is caused by the following reason: since wiring connected to the output sections of the respective inverters is short, substantial wiring resistance is not present. Thus, the on resistance of each transistor is dominant as a resistive component which, together with the MOS capacitors, contributes to the time constant.
On contrast therewith, the signal line of the ordinary logic circuit is driven in a circuit configuration as shown in FIG. 16. Rise and fall of a signal line SL having a wiring resistance (parasitic resistance) R and a parasitic capacitance C is defined by the time constant stipulated by the parasitic resistance R of the signal line, the output resistance of a driver (output circuit) D, and the parasitic capacitance C of the signal line. In a circuit for driving a wiring having a wiring parasitic resistance as a load, the delay time of a signal is not so dependent on the power supply voltage as the inverter chain in FIG. 15.
Accordingly, the delay time of the delay circuit shown in FIG. 15 excessively increases when the supply voltage is reduced, on contrast with the ordinary logic circuit.
In order to solve the problem as described above, the inventor of the present application already proposed a delay circuit of a configuration as shown in FIG. 17 in the priority claim (U.S. patent application Publication No. US 2002/0021159 A1) based on JP Patent Application No. 2001-097083. This delay circuit is the delay circuit of which the delay time does not excessively increase, compared with the ordinary logic circuit even if the supply voltage is reduced and can suppress the increase of the delay time.
Referring to FIG. 17, the delay circuit includes a plurality of inverters V11, V12, V13, and V14 connected in cascade. PMOS capacitors P11 and P12 are provided between the output of the inverter V11 and the high potential power supply VDD and the output of the inverter V13 and the high potential power supply VDD, respectively. NMOS capacitors N11 and N12 are provided between the output of the inverter V12 and the low potential power supply GND and the output of the inverter V14 and the low potential power supply GND, respectively.
The PMOS capacitors P11 and P12 become from an off state to the on state (inversion state) in response to falling transition of the outputs of the inverters V11 and V13 from the high level to the low level, respectively. The NMOS capacitors N11 and N12 become from the off state to the on state (inversion state) in response to rising transition of the outputs of the inverters V12 and V14 from the low level to the high level, respectively. As is well known, the NMOS capacitor is in an accumulation state when its gate voltage Vg is negative or a ground voltage GND (0 V), and its capacitance value is constituted from a capacitance Co of a gate oxide film therein alone. When the gate voltage Vg is larger than 0, a depletion layer is formed in the surface of a substrate, so that its capacitance value becomes a capacitance C obtained by series synthesis of the gate oxide film capacitance Co and a capacitance Cd of the depletion layer formed in the surface of the substrate, which is smaller than Co. When the gate voltage Vg is positive and increases (Vg>Vt, in which Vt is the threshold voltage), an inversion layer resulting from polarity inversion of the surface of the p-type substrate is formed. If so-called strong inversion occurs, its capacitance value becomes closer to Co. Likewise, the PMOS capacitor is in the accumulation state when its gate voltage is the power supply voltage VDD. Then, when the gate voltage falls below the supply voltage and transitions toward the ground voltage GND, the PMOS capacitor becomes a depletion state and then an inversion state.
In the inverter chain shown in FIG. 17, assume that the power supply voltage VDD is reduced, the driving currents of the MOS transistors are reduced and then the on resistances of the MOS transistors constituting the inverters increase in appearance. Then, the capacitance values of the MOS capacitors relatively decrease. An increase in the amount of the delay is thereby suppressed. This delay circuit suppresses an excessive increase in the delay time due to lowering of the power supply voltage VDD, in response to rise (transition from GND to VDD) of an input SIN to the inverter V11 in the first stage.
The inventor of this application already proposed a delay circuit of a configuration as shown in FIG. 18 in JP Patent Application No. 2001-097083. This delay circuit is the delay circuit of which the delay time does not excessively increase and which can suppress an increase in the delay circuit, even if the supply voltage is reduced. Referring to FIG. 18, the threshold value of a PMOS transistor P81 of an inverter V81 is set to be high, and the threshold value of an NMOS transistor N81 of the inverter V81 is set to be low. The threshold value of a PMOS transistor P82 of an inverter V82 is set to be low and the threshold value of an NMOS transistor N82 of the inverter V82 is set to be high. The input threshold value of the inverter V81 tends to decrease as the power supply voltage is reduced, while the input threshold value of the inverter V82 tends to rise as the power supply voltage is reduced. The input threshold value of the delay circuit thereby decreases in a region in which the power supply voltage VDD is low, and the propagation delay time tpd from the rise of the input signal to the rise of the output signal becomes relatively shorter than the propagation delay time from the fall of the input signal to the fall of the output signal. As a result, the delay time in the rise of the signal can be reduced, so that dependency of this delay time on the power supply voltage is suppressed.
As described above, the delay circuits shown in FIGS. 17 and 18, respectively, suppress an excessive increase in the delay time caused by reduction of the power supply voltage VDD in the configuration as shown in FIG. 15. However, the delay circuits do not have a reverse sensitivity characteristic in which the delay time thereof decreases with reduction of the power supply voltage. For this reason, with respect to reduction of the power supply voltage of the semiconductor memory device, when edges and pulses of a control signal are generated for using the delay circuits shown in FIGS. 17 and 18, respectively, the delay of the control signal does not decrease as the power supply voltage is reduced. Thus, a constraint is imposed on the lower power consumption.
Accordingly, it is an object of the present invention to provide a semiconductor memory device in which by speeding up access to the cell core unit while reducing a power supply voltage for driving, reduction of a combined access speed to the cell core unit and the peripheral circuit caused by the reduced power supply voltage is suppressed, and its control method.
Still other object of the present invention is to provide a semiconductor device in which due to its simple configuration, an increase in the delay time caused by the reduction of the power supply voltage is further suppressed, so that the delay time shows a tendency of decreasing.

Semiconductor memory device and semiconductor device and semiconductor memory device control method


A screening assembly for screening material includes an assembly frame, a multi-deck screening device, a transfer conveyor and a drive means. The drive means is operable to shift at least one of the discharge ends of the screening device and the receiving end of the conveyor relative to the assembly frame to allow the transfer conveyor to selectively receive material from an upper screen and from both screens of the screening device at their respective discharge ends. A mobile material processing plant incorporating the screening assembly is included.

A variety of different types of screening units have been developed for sizing or sorting bulk material, such units are usually equipped with vibration generating means for imparting circular or reciprocating vibratory motion on screen decks. Screening units are commonly combined with a crushing device to build an integral material processing machine, optionally it may be demountably set up on a mobile crusher.
FIG. 1 shows an existing screening assembly, which has a screen box 16 containing two vertically-stacked screen decks. The assembly mounts a first transfer conveyor 13 located at the discharge end of screen box 16 which is used for diverting material flow sidewards and subsequently onto laterally arranged recirculation conveyor 11. A second transfer conveyor 14 is placed beneath the first transfer conveyor 13 for transferring material from a lower screen deck. As the belt of the second transfer conveyor 14 may run in two optional directions, depending on its belt running direction, the second transfer conveyor may serve either the recirculation conveyor 11 or a stockpile conveyor 15 when in operation.
EP3061533 describes multi-deck screening assembly comprising a plurality of vertically-stacked downwardly inclined screen decks (6, 8, 10), the lower screen decks (8, 10) deliver from their discharge ends over-sized material onto a respective stockpile conveyor (18, 20), a transfer conveyor 28 is provided to deliver material from the discharge end of the upper deck 6 onto a loading end of the third stockpile conveyor 22 located laterally on one side of the chassis but opposite to stockpile conveyor 20, as shown in its FIG. 4/5.
CA2960739 describes a mobile bulk material processing apparatus in which a transfer conveyor 134 configured to transfer oversized material from the screen 112 to the recirculation conveyor 114. The transfer conveyor is adjustably mounted at carrier frame 110 and configured to pivot about a transverse horizontal axis (FIG. 8b/8c) or be moveable between a widthwise inclined working position and a substantially horizontal position to allow maintenance access.
However, in conventional screening assembly, a transfer conveyor is always dedicated to transport material discharged from a corresponding screen, this structure is not flexible, cost-saving or energy-efficient. Accordingly, what is required is a screening assembly that addresses these problems.

Screening assembly and mobile material processing machine


An earth crust breaker drawn by a tool bar on a tractor is provided and consists of an elongated U-shaped frame having an angularly upwardly extending front end attached to the bottom of a vertical member of the tool bar. A post extends vertically from each side of the frame to the free end of a horizontal member of the tool bar. A plurality of specifically placed knife blades extend from the bottom of the frame to penetrate the ground and make slices into the crust thereby chopping it up.

The instant invention relates generally to agricultural implements and more specifically it relates to an earth crust breaker.
Numerous agricultural implements have been provided in prior art that are adapted to be pulled by tractors to cultivate or break up the earth's surface in preparation for planting and the like. For example, U.S. Pat. Nos. 2,361,605 to Cross; 3,077,231 to Hamilton and 3,464,498 to Hornung all are illustrative of such prior art. While these units may be suitable for the particular purpose to which they address, they would not be as suitable for the purpose of the present invention as hereafter described.


A transmitter modulator that is operable to modulate signals according to multiple modulation formats includes a first modulator, a second modulator, and a polarization beam combiner. The first modulator encodes a first signal according to a first modulation format. The second modulator encodes a second signal according to a second modulation format, the first signal orthogonally polarized with respect to the second signal. The polarization beam combiner combines the first signal and the second signal for transmission.

Signals may be modulated using phase-shift keying (PSK) and amplitude-shift keying (ASK) modulation. In PSK modulation, changes in the phase of a signal are used to represent data, and in ASK modulation, the amplitude levels of a signal are used to represent data.
PSK-ASK communication, however, may experience difficulties. As an example, PSK-ASK communication typically uses a non-optimal extinction ratio. An extinction ratio refers to the ratio of the optical power of a "1" pulse to that of a "0" pulse. In general, a higher ASK extinction ratio improves ASK communication, but degrades PSK communication. For example, ASK communication may be optimal at an extinction ratio of 10 decibels, but PSK communication may not be optimal. Typically, a compromise extinction ratio between the optimal extinction ratio for ASK communication and the optimal extinction ratio for PSK communication is used. For example, an extinction ratio of 7 decibels may be used. The compromise extinction ratio, however, is typically not optimal for either ASK or PSK communication.
As another example, PSK-ASK communication may suffer from crosstalk between the ASK and PSK signals. The ASK signal may induce a non-linear phase shift on the PSK signal. The non-linear phase shift introduces non-linear phase noise to the PSK signal, degrading the PSK signal. In addition, self-phase modulation may induce a phase shift that introduces a frequency chirp, which may degrade the ASK signal.

Communicating a signal according to ASK modulation and PSK modulation


A method in which a sample of a gas mixture to be analyzed via gas chromatography is conducted through a chromatographic separating device via a carrier gas, separated components of the gas mixture are subsequently quantitatively determined in an absorption spectrometer having a wavelength-adaptable light source, and in order to increase the speed of analysis and to be able to also determine components that cannot be measured via absorption spectroscopy, the wavelength of the light source can be adapted to an absorption line of the carrier gas, where the individual components of the gas mixture are determined indirectly via a concentration reduction of the carrier gas.

1. Field of the Invention
The invention relates to a gas chromatograph comprising a chromatographic separating device and a downstream absorption spectrometer, containing a wavelength-tunable light source, for quantitative determination of separated components of a sample of a gas mixture conveyed through the separating device via a carrier gas.
2. Description of the Related Art
The invention furthermore relates to a method for analyzing a gas mixture via gas chromatography, where a sample of the gas mixture is passed through a chromatographic separating device by means of a carrier gas and separated components of the gas mixture are quantitatively determined in a downstream absorption spectrometer having a wavelength-tunable light source.
A gas chromatograph and method are known from U.S. Pat. No. 7,511,802 B2. In the known gas chromatograph and method, after leaving the separating device each individual component is introduced through a switch valve into an analysis cell of the absorption spectrometer. The light of the wavelength-tunable light source is passed through the analysis cell onto a photodetector, the wavelength of the light source being tuned to an absorption line of the component to be determined. The light absorption of the component is dependent on its concentration in the analysis cell, so that the output signal generated by the photodetector is a measure of this concentration. Since the light absorption is very weak, the light beam is conveyed via reflection several times through the analysis cell before it strikes the photodetector. After each determination of a component, the analysis cell is flushed with the carrier gas via the switch valve. Insufficiently separated components may be passed together into the analysis cell and determined there, if they have non-overlapping absorption lines to which the wavelength of the light source can be tuned. In the case of overlapping absorption lines, there is the possibility of separating the components by gas scrubbing and then delivering them individually to the analysis cell. Nitrogen, argon or helium, which are not infrared-active and therefore do not interfere with the absorption spectra of the components to be determined, may be envisioned as the carrier gas.
WO 2008/061949 A1 and WO 2011/026924 A1 respectively disclose an absorption spectrometer in which the analysis cell is configured as a waveguide, in which the gas to be analyzed is contained. The light of the light source is input into the waveguide at one end thereof and output at the other end onto the photodetector. The light is guided by reflection in the optionally internally mirrored waveguide, so that the waveguide may be curved and therefore formed as a hollow fiber. In order to reduce artefacts, such as interference, the waveguide may be set in vibration. The advantage of this known absorption spectrometer resides in the small measurement volume and the long optical measurement path.
In connection with the known determination via absorption spectrometry of components previously separated via gas chromatography, as already mentioned above, the following problems arise:                With wavelength-tunable light sources commercially available at present, generally lasers or laser diodes, only a very restricted number of gas components can be determined; for example, noble gases or nitrogen in principle and higher hydrocarbons in practice cannot be measured.        The tuning of the light source to the absorption lines of the various components is elaborate and time-consuming.        The carrier gases used are expensive.

Gas chromatograph having an absorption spectrometer and method for analyzing a gas mixture via gas chromatography


The present invention relates to one pot process for the preparation of 4-(1,2-dihydro-2-oxobenzo[d]imidazol-3-yl)butanoic acid of Formula-I, which is a key intermediate and its use in the preparation of Zilpaterol, which comprises condensation of methyl-4-chloro butyrate with 1-(prop-1-en-2-yl)-1H-benzo[d]imidazol-2(3H)-one in presence of a base and suitable solvent to give corresponding ester derivative, further hydrolyzation and acidification in presence of inorganic solvent to obtain Formula-I.

The 4-(1,2-dihydro-2-oxobenzo[d]imidazol-3-yl)butanoic acid of formula (I) is a benzimidazole derivative,

and is one of the key intermediate in zilpaterol manufacturing process.
Zilpaterol code named as RU 42173 is a β2 adrenergic agonist under its trade name Zilmax, it is used to increase the size of cattle and the efficiency of feeding them. Zilmax is produced by Intervet, a subsidiary of Merck & Co., and marketed as a "beef-improvement technology". Zilapterol is chemically represented as 4,5,6,7-tetrahydro-7-hydroxy-6-(isopropylamino)imidazo[4,5,1-jk][1]benzazepin-2(1H)-one having a structural formula as follows:

U.S. Pat. No. 4,900,735 describes zootechnical compositions of racemic trans Zilpaterol and its derivatives which can be used to increase the rate of weight gain, and improve the feed efficiency and increase carcass leanness in livestock, poultry and fish.
US 2008/0103130 assigned to Pharmacia & Upjohn discloses the preparation of Zilpaterol, and 4-(1,2-dihydro-2-oxobenzo[d]imidazol-3-yl)butanoic acid (compound-iv) also known as buzolic acid (in page 7-8), wherein the said intermediate is prepared by multiple steps: by reacting compound-i (1-(prop-1-en-2-yl)-1H-benzo[d]imidazol-2(3H)-one) with 4-Bromobutyric acid methyl ester in presence base K2CO3 and acetone to form ester derivative of compound ii; ester derivative converted to acid derivative of compound-iii by hydrolyzing in presence of NaOH in THF. An acid derivative of compound-iii is acidified with hydrochloric acid in presence THF to obtain compound-iv.
The Process is Schematically Represented as Below in Scheme-1:

The process for the preparation of Zilpaterol and it's intermediate preparation has been disclosed in Edward J. Salaski, Div. Bio-Org. Chem., Inst. Org. Chem., Syntex Discovery Res., Palo Alto, Calif. 94304, USA; EN)" Synthesis of Imidazobenzazepinethiones: A New Series of HIV-1 Reverse Transcriptase Inhibitors, Tetrahedron Lett. 36 (1995) 9, 1387-1390; wherein the said Compound-6 (4-(1,2-dihydro-2-oxobenzo[d]imidazol-3-yl)butanoic acid) intermediate is prepared by deprotonation of compound-3 (1-(prop-1-en-2-yl)-1H-benzo[d]imidazol-2(3H)-one) with strong base such as sodium hydride in DMF and alkylation of the anion with ethyl 4-bromobutyrate provided the ester compound-4, which was treated with 15% aq NaOH solution in THF to give the acid derivative of compound-5, which is acidified with aq.HCl in presence of DME to produce Compound-6.
The Process is Schematically Represented as Below in Scheme-2:

The above mentioned routes for preparation of 4-(1,2-dihydro-2-oxobenzo[d]imidazol-3-yl)butanoic acid have considerable disadvantages, which involve the use of hazardous chemicals which are harmful to the environment and toxic in nature. Further, the isolation of all the intermediates at different stages of preparation makes the process tedious and leads to low yield.
Considering the short comings in the prior art methods, it is imperative to develop an improved method for the preparation of Zilpaterol intermediate of formula (I), which is cost effective, eco-friendly and high yielding with high purity.
Advantageously, the process of the present invention provides a product with significant improvement in the purity i.e. not less than 97% and yield not less than 95%. Further, the one pot process of the present invention uses water as a solvent which effectively contributes to the reduction of overall cost of the process and is also environment friendly.
The present inventors have now found a much simpler, cost effective process with shorter reaction time when compared to the prior art methods.

One pot synthesis of 4-(1,2-dihydro-2-oxobenzo[d]imidazol-3-yl)butanoic acid, a key intermediate of zilpaterol


A cooling plate for a metallurgical furnace comprising a body (12) with a front face (18) and an opposite rear face (20), the body having at least one coolant channel (14) therein; the front face (18) being turned towards the furnace interior and preferably comprises alternating ribs (22) and grooves (24). The cooling plate includes wear detection means comprising: a plurality of closed pressure chambers (26, 28) distributed at different locations in said body, said pressure chambers being positioned at predetermined depths below the front face (18) of said body; and a pressure sensor (30) associated with each pressure chamber (26, 28) in order to detect a deviation from a reference pressure inside said pressure chamber when the latter becomes open due to wear out of said body.

Cooling plates for metallurgical furnaces, also called "staves", are well known in the art. They are used to cover the inner wall of the outer shell of the metallurgical furnace, as e.g. a blast furnace or electric arc furnace, to provide:
                (1) a heat evacuating protection screen between the interior of the furnace and the outer furnace shell; and        (2) an anchoring means for a refractory brick lining, a refractory guniting or a process generated accretion layer inside the furnace.Originally, the cooling plates have been cast iron plates with cooling pipes cast therein. As an alternative to cast iron staves, copper staves have been developed. Nowadays, most cooling plates for a metallurgical furnace are made of copper, a copper alloy or, more recently, of steel.The refractory brick lining, the refractory guniting material or the process generated accretion layer forms a protective layer arranged in front of the hot face of the panel-like body. This protecting layer is useful in protecting the cooling plate from deterioration caused by the harsh environment reigning inside the furnace. In practice, the furnace is however also occasionally operated without this protective layer, resulting in erosion of the lamellar ribs of the hot face.As it is known in the art, while the blast furnace is initially provided with a refractory brick lining on the front side of the staves, this lining wears out during the campaign. In particular, it has been observed that, in the bosh section, the refractory lining may disappear relatively rapidly. While an accretion layer of slag and burdening then typically forms on the hot side of the cooling plates, it actually continuously builds-up and wears out, so that during certain periods of time the cooling plates are directly exposed to the harsh conditions inside the blast furnace, conducting to the wear of the cooling plate body.The principal causes of wear to the accretion layer, and of course to the lining and cooling plate, are the upward flow of hot gases and the rubbing of the sinking burden (coal, ore, etc.). Regarding the flow of hot gases, the wear is not only due to a thermal load, but also to abrasion by particles carried in the ascending gases.Document JP-A2-61264110 discloses a cooling stave comprising a wear detection system using an ultrasonic probe in contact with the rear face of the stave body to detect erosion thereof. This appears as a cumbersome technique to be implemented in the blast furnace environment.

Blast furnace cooling plate with integrated wear detection system


An optical waveguide device is provided which can efficiently guide undesired light to the outside of a substrate or the outside of the overall optical waveguides even when optical waveguides are integrated. In the optical waveguide device, an optical waveguide is formed on a substrate, the optical waveguide includes a main waveguide in which signal light propagates and an undesired-light waveguide for removing undesired light from the main waveguide, and the undesired-light waveguide is separated by the main waveguide interposed therebetween at an intersection in which the undesired-light waveguide and the main waveguide intersect each other.

1. Field of the Invention
The present invention relates to an optical waveguide device, and more particularly, to an optical waveguide device in which an optical waveguide formed on a substrate includes a main waveguide having signal light propagating therein and an undesired light waveguide used to remove undesired light from the main waveguide.
2. Description of Related Art
In the fields of optical communications, optical measurements, and optical information processing, optical waveguide devices have been used in which an optical waveguide is formed on a dielectric substrate of lithium niobate or the like. In the optical waveguide used in the optical waveguide devices, portions branching or combining the optical waveguide are formed, like Mach-Zehnder type Optical waveguides widely used in optical modulators, optical switches, or the like.
In the portion combining the optical waveguides, out-phase light is radiated into the substrate as a radiation mode light, as described in Japanese Laid-open Patent Publication No. 2006-301612. Therefore, in order to cause the radiation-mode light not to be re-coupled to signal light, shielding means is provided or an optical waveguide guiding the radiation-mode light to the outside is provided.
As shown in Japanese Laid-open Patent Publication No. 2008-089875, when higher-mode light is included in signal light at the time of branching the optical waveguide, there is a problem in that that a branching portion of an optical waveguide has a difficulty in branching the signal light at a predetermined branching ratio. Therefore, unnecessary higher-mode light is removed from signal light in front stage of the branching portion. As this removal method, an optical waveguide that guide the higher-mode light to the outside is provided.
On the other hand, as described in Izutsu et al. "Integrated Optical SSB Modulator/Frequency Shifter", IEEE Journal of Quantum Electronics, vol. QE-17, No. 11, 1981, pp. 2225-2227, an integrated modulator structure is proposed in which plural optical waveguides are integrated. Plural branching portions or combining portions are formed in such an optical waveguide device. Accordingly, undesired light from the optical waveguides arranged along the outside of the overall optical waveguides can be easily removed, but it is very difficult to remove undesired light from branching portions or combining portions arranged inside the overall optical waveguides.
In order to achieve an increase in frequency bandwidth of a modulation signal or a decrease in driving voltage of an optical modulator or the like, a substrate of an optical waveguide device is formed of a thin plate with a thickness of 30 μm or less. In this thin plate, undesired light such as radiation-mode light radiated into the substrate propagates with the substrate itself as a slab waveguide, the probability of re-coupling of the undesired light with signal light increases a lot.


A method and an apparatus for data management through timer compensation in a wireless communication system are provided. In the method, when a data loss occurs at a first point, whether a data loss has occurred previously and so whether a timer is being driven are determined. Whether the driven timer stops or expires at a second point is determined. When the timer stops or expires at the second point, a timer value is compensated for with consideration of a time difference between the first point and the second point. A timer for the data loss of the first point is restarted based on the compensated timer value. Therefore, a delay of a retransmission request time for lost data in an RLC (Radio Link Control) layer may be minimized.

1. Field of the Invention
The present invention relates to a method and an apparatus for data management through timer compensation in a wireless communication system. More particularly, the present invention relates to an apparatus and a method for compensating for a timer in order to minimize delay of a retransmission request for lost data.
2. Description of the Related Art
To guarantee in-sequence delivery of data in a Media Access Control (MAC) layer and a Radio Link Control (RLC) layer, an HSPA+ (HSPA evolution) has a structure in which the MAC layer performs reordering of the received data and then delivers sequential data to the RLC layer. At this point, when data is not received sequentially, the MAC layer buffers received data for in-sequence delivery of the data using a receiver window and a timer T1.
When data are not sequentially received in the MAC layer and the RLC layer, a reception end waits for reception of missing data for a predetermined time using a reordering release timer (referred to as a "timer T1" hereinafter). Data includes a unique Sequence Number (SN) for identifying between data. The SN is used for determining whether data is sequentially received or whether data lost in the midway exist.
The timer T1 controls stall avoidance in a reordering buffer of the reception end. An operating method of the timer T1 may be divided into four kinds as illustrated in FIG. 1A-1D.
FIG. 1A illustrates an exemplary start of a timer T1 according to the conventional art.
Referring to FIG. 1A, in the case where a Transmission Sequence Number (TSN) of received data is greater than a Next_Expected_TSN (NET) to be received next, the timer T1 is started when it is not activated, and T1_TSN is set to TSN of the received data. The T1_TSN is an SN of data arranged in order by a receiver window to trigger the timer T1 and not received. For example, when User Equipment (UE) receives data whose TSN is 0 and data whose TSN is 1 from a base station (Node B), a NET value becomes 2. After that, when the UE cannot receive data whose TSN is 2 from the Node B (that is, the data whose TSN is 2 is lost) and receives data whose TSN is 3, the UE compares the TSN of the currently received data with a current NET=2 to recognize that the data whose TSN is 2 has been lost and start the timer T1 (100). When the timer T1 is already activated, the timer T1 is not started and the existing already activated timer T1 is maintained. Since a 3 Generation Partnership Project (3GPP) specification defines that "only one timer T1 should maintain an activated state during a given time", an additional timer is not started.
FIG. 1B illustrates an exemplary stop of a Timer T1 according to the conventional art.
Referring to FIG. 1B, when lost data (data whose TSN=2) exists and so the timer T1 starts (102) as in FIG. 1A and then UE receives data whose TSN=3, 4, a NET value maintains 2 and waits for next data. After that, when the UE receives data whose TSN=2 before the timer T1 expires, the UE stops the timer T1 and transmits data whose TSN is 2 to 4 to an upper layer (104). At this point, a NET value is updated as 5 and the UE waits for reception of data whose TSN=5.That is, when receiving lost data, the UE stops the activated timer T1.
FIG. 1C illustrates an exemplary expiration of the timer T1 according to the conventional art.
Referring to FIG. 1C, when lost data is not received for a predetermined time after a timer T1 is started (106) due to the lost data, the timer T1 expires (108). At this point, when T1_TSN is greater than NET, UE transmits received data (data whose TSN is 3 to data whose TSN is 9) having a TSN value between T1_TSN=9 and NET=2 to an upper layer. In addition, a NET value is set to a TSN value of data not received yet (for example, since up to data whose TSN is 9have been received, a NET becomes 10).
FIG. 1D illustrates an exemplary restart of a timer T1 according to the conventional art.
Referring to FIG. 1D, when the timer T1 is stopped or expires and in-sequence delivery of data to an upper layer is impossible, the timer T1 is restarted and T1_TSN is set to largest TSN of data which cannot be sequentially delivered.
For example, when data whose TSN=2 transmitted from a Node B is lost and UE receives data whose TSN=3, a NET value becomes 2 and T1_TSN indicating TSN of currently received data becomes 3. At this point, the timer T1 starts (110).
After that, UE receives data whose TSN=4 and TSN=8 (Here, it is assumed that data whose TSN=6 has been lost). At this point, a NET value maintains a TSN value (TSN=2) of lost data.
When the timer T1 stops or expires after the UE receives data whose TSN=8, currently received data (TSN=8) that cannot be sequentially delivered due to other lost data (TSN=6) is stored in a reordering buffer, so that the timer T1 is restarted with respect to TSN=6 (112). At this point, for the UE to expect retransmission of the lost data (TSN=6), a NET value is set to 6 and T1_TSN is set to 8. In addition, only data whose TSN=3 to TSN=5 are delivered to an upper layer.
As described above, the MAC layer of the HSPA+ starts/stops/expires/restarts the timer T1 using an SN of data in order to sequentially deliver packet data. At this point, for a T1 timer value, a value received from the upper layer is used.
Therefore, referring to the T1 timer restart procedure of FIG. 1D, when data whose TSN=2 is not received and data whose TSN=3 is received, the timer T1 starts. At this point, the timer T1 is set to a T1 timer value (for example, 100 ms) received from the upper layer. After that, when data whose TSN=2 is not received until the timer T1 expires, UE transmits relevant data (TSN=3,4,5) to the upper layer and restarts the timer T1 according to specification. At this point, the timer T1 is set with respect to data whose TSN=6. Even in this case, the timer T1 is set to a T1 timer value (for example, 100 ms) with respect to data whose TSN=2. That is, the T1 timer value should be applied and operated from a point where data whose TSN=6 has been lost but a timer T1 waits until a timer T1 that has been applied from a point where data whose TSN=2 has been lost expires, and then the timer T1 for the data whose TSN=6 operates, so that a retransmission request for the data whose TSN=6 is delayed.
Therefore, a method and an apparatus for reducing a delay in a retransmission request for other lost data at a point of starting a timer T1 after stoppage or expiration of the timer T1 in a wireless communication system are required.

Method and apparatus for data management through timer compensation in a wireless communication system


In an information reproduction apparatus, a recording/reproducing unit reproduces a plurality of program data on a recording medium. The program data and identification information for the program data are stored on the recording medium. An operation/display unit displays the identification information and reproduction frequency information, and allows an user to select one of the program data to be deleted. An controller for controlling the recording/reproducing unit in accordance with an instruction from the operation/display unit. The controller calculates the reproduction frequency information for each of the program data by employing a variety of information obtained by reproducing each of the program data. The controller controls the recording/reproducing unit to erase from the recording medium the program data identified by the operation/display unit.

1. Field of the Invention
The present invention relates to an information reproduction apparatus and to a method for erasing program data. In particular, the present invention relates to an information reproduction apparatus that provides, for a user, information for requesting a user to select program data to be erased from a large capacity recording medium, such as a hard disk.
2. Description of the Related Art
Information reproduction apparatuses are presently available that record, and reproduce, program data on large capacity recording media, such as hard disks. When fitted with a hard disk, by employing a variety of formats one of these information reproduction apparatuses can be used to compress program data stored as music content on a recording medium, such as a CD, and to load the compressed data on the hard disk for later reproduction.
Current, typical compression methods include MP3 (MPEG: Moving Picture Experts Group; audio layer III) and ATRAC3, an improved version of ATRAC (Adaptive Transform Acoustic Coding) that when uses to process data requiring one minute to produce yields compressed data equivalent to a storage capacity of 1 M bytes. Thus, assuming that this compression method is employed for musical renditions having reproduction times of five minutes, and assuming that the hard disk in this case has a storage capacity of 10 G bytes, an information reproduction apparatus can record the data for 2000 pieces of music.
As is described above, an information reproduction apparatus for reproducing program data stored on a large capacity medium, such as a hard disk, can be usefully employed for recording a large quantity of program data.
However, since a large quantity of program data can be stored on a hard disk, unnecessary data, including music content that is seldom reproduced, may be retained for an extended period of time. Further, if unnecessary program data is permitted to accumulate, even when a large capacity recording medium is used a point will be reached at which a shortage of space precludes the further storage of data, including the latest music content.
To avoid the occurrence of this problem, a user must manipulate a predetermined key to erase from a hard disk program data such as unnecessary music content.
That is, in order to delete program data recorded on a hard disk, a user must first select an erase mode. The user must then manipulate a track select key, or a forward or backward key, to search for program data to be deleted; and when such program data is found, to erase that data from the hard disk the user must manipulate an execute key.
As is described above, in order to find program data for deletion from a hard disk, a user must search for the program data to be deleted through a large amount of data. Thus, when at first no relevant program data is found, the user must repeat the manipulation of the track select key, or of the forward or backward key, a process requiring the expenditure of a great deal of time and effort.
Further, when a shortage of hard disk capacity has occurred, the user cannot quickly delete unnecessary data to obtain additional free space, so that program data, such as the latest music content, can not be promptly recorded on the hard disk.
To resolve the shortcoming, it is an object of the present invention to provide an information reproduction apparatus and program data deletion method that calculates information to be used as an index for erasing program data such as reproduction frequency, to permit the user to efficiently select for deletion program data recorded on the hard disk.
To achieve this objective, according to the present invention, an information reproduction apparatus, for reproducing program data stored on a recording medium, comprises:
reproducing means for reproducing program data on a recording medium on which are stored the program data and identification information for the program data;
erasing means for erasing the program data from the recording medium;
reproduction frequency calculation means for calculating reproduction frequency information for each set of program data by employing a variety of information obtained by reproducing the program data; and
control means for displaying, at the least, the identification information and the reproduction frequency information, and for erasing from the recording medium program data that has been identified by referring to the identification information selected by a user.
The variety of information includes reproduction time data, which is obtained by the addition of each set of program data each time the program data is reproduced by the reproducing means, and total reproduction time data, which is obtained by adding the reproduction time data.
The variety of information includes reproduction count data, which is obtained by the addition of data, for each set of program data, each time the program data is reproduced by the reproducing means, and total reproduction count data, which is obtained by adding the total reproduction count data.
The reproduction frequency calculation means employs the reproduction time data and the total reproduction time data to obtain a reproduction time ratio for each set of the program data.
The reproduction frequency calculation means employs the reproduction count data and the reproduction count total to obtain the reproduction count ratio for each set of the program data.
The reproduction time data and the reproduction count data are obtained by the incrementation of the program data up to the final position of it.
According to the thus arranged information reproduction apparatus of the invention, the reproduction frequency information is calculated for each set of program data by using a variety of information that is obtained (updated) when the program data is reproduced by the reproducing means. When the reproduction frequency information and the identification information for identifying the program data that are displayed on the display means, the user is requested to select the program data to be erased.
With this arrangement, the user need only visually confirm the reproduction frequency information to efficiently select the program data that are to be deleted.
Therefore, when a shortage of hard disk capacity has occurred, unnecessary program data can be immediately selected and deleted, and program data, such as the latest music content, can be promptly stored on the hard disk.
Further, since reproduction frequency information is obtained based either on the time whereat the program data was reproduced or the number of times whereat the program data was reproduced, appropriate information to be used as a determination reference for erasing data from the hard disk can be provided for the user.
In addition, to achieve the objective according to the invention, a method for erasing program data stored on a recording medium comprises the steps of:
reproducing program data to calculate a variety of information; and
based on the variety of information, displaying on display means reproduction frequency information for each set of program data, and erasing from the recording medium program data that is selected by a user employing the reproduction frequency information.
According to the thus arranged program data erasing method of the invention, reproduction frequency information is calculated for each set of program data by using a variety of information that is obtained (updated) when the program data is reproduced by the reproducing means. After the reproduction frequency information and the identification information for identifying the program data have been displayed on the display means, the user is requested to select the program data to be erased.
With this arrangement, the user need only visually confirm the reproduction frequency information to efficiently select program data to be deleted.
Therefore, when for the hard disk a shortage of record capacity on the hard disk has occurred, unnecessary program data can be immediately selected and deleted, and program data, such as the latest music content, can be promptly stored on the hard disk.

Information reproduction apparatus and method for erasing program data


A method for fabricating a nonvolatile memory device includes forming a substrate structure having a tunnel dielectric layer and a floating-gate conductive layer formed over an active region defined by a first isolation layer forming a first inter-gate dielectric layer and a first control-gate conductive layer over the substrate structure, forming a trench by etching the first control-gate conductive layer, the first inter-gate dielectric layer, the floating-gate conductive layer, the tunnel dielectric layer, and the active region to a given depth, forming a second isolation layer to fill the trench; and forming a second control-gate conductive layer over the resultant structure having the second isolation layer formed therein.

1. Field
Exemplary embodiments of the present invention relate to a method for fabricating a nonvolatile memory device, and more particularly, to a method for fabricating a nonvolatile memory device including an isolation layer.
2. Description of the Related Art
A nonvolatile memory device refers to a memory device which maintains data stored therein even though power supply is cut off. Currently, a variety of nonvolatile memory devices, for example, a NAND-type flash memory and on the like, have been widely used.
Recently, with the increase in integration degree of semiconductor devices, the importance of device isolation technology for electrically isolating adjacent devices has been further increased. A shallow trench isolation (STI) method is typically used as one of device isolation technologies of a semiconductor process and in the STI, a trench defining an active region is formed in a semiconductor substrate, and then filled with a dielectric material to form an isolation layer.
Meanwhile, as the distance between semiconductor devices is reduced, there may be a limitation in increasing the integration degree through the conventional technology which forms only one device in the left and right sides of the isolation layer having an STI structure. Furthermore, as the aspect ratio of the trench increases, a burial characteristic may be degraded. For example, a void may occur in the STI structure.

Method for fabricating nonvolatile memory device


Disclosed is a multi-staged desiccant refrigeration device which employs an evaporator combined with a multi-staged vapor desiccant/heat sink module which absorbs water vapor from the evaporator. A plurality of stage vapor desiccant/heat desiccant modules are incorporated in the device, the automatic staged opening and closing of the modules allowing for a continuous and more efficient refrigeration process.

The vapor pressure of refrigerants, particularly water, decreases as the temperature decreases, so that the operating pressure is small near the end of discontinuous refrigerant operation.
Vapor desiccants also have higher vapor pressures at higher temperatures and thus have a decreasing capacity for water vapor as the temperature of the system increases.
Therefore, as the cooling process proceeds in a conventional desiccant refrigeration system, the available vapor supply pressure falls, the vapor absorption pressure rises and the capacity of the desiccant decreases, so the characteristics of the evaporation and the desiccant/heat sink portions of the system are not ideally matched. This inequality provides the principal limitation on minimizing the size of such a refrigerant system, and contributes to the time required to cool the system to the designed temperature.
If a portion of the released heat is transferred to a heat sink material, the desiccant temperature is lessened, so that the desiccant can absorb more water vapor. There is an optimum choice of ratio of heat sink mass-desiccant mass which for a given combination of materials gives a minimum total mass and volume for a given short time water absorption which can be determined easily.
Three physical characteristics affect the amount of water vapor which a desiccant can absorb in a short period of time.
The first characteristic is the relationship between desiccant water vapor capacity and desiccant temperature. The amount of water which all common desiccants can contain decreases with temperature due to their decreasing capacity for water vapor due to their higher vapor pressure at higher temperatures.
The second characteristic which affects performance of the desiccant is the amount of chemical reaction energy released when the water is bound into the desiccant. Any water vapor absorption process releases the latent heat of vaporization of the water into the desiccant when the molecule is bound into the desiccant structure of molecular motions.
However, most desiccants also react chemically with the water in an exothermic process. Two commercially available desiccants, Drierite (a calcium sulphate desiccant available from W.A. Hammond Drierite Co. Xenia, OH and Multiform molecular sieve 4A, (a synthetic zeolite molecular sieve available from Multiform Desicants, Inc., Buffalo, New York) exhibit an exothermic chemical reaction when reacting with water. In the case of the Multiform desiccant, the reaction heat is 80% of the water vapor latent heat. Therefore, 1.8 calories of heat are released into the desiccant for every calorie of heat absorbed from the cooled material in the refrigerator evaporator.
The final characteristic is the vapor pressure over the desiccant in a conventional single-use desiccant refrigerator apparatus. In such an apparatus, the desiccant is analogous to both the pump and condenser found in the conventional refrigeration cycle. This value, which increases with temperature, is equivalent to the suction pressure in a compressor refrigerant process at the refrigerator compressor inlet.
This increased pressure (reduced suction) reduces the refrigeration efficiency of the apparatus as the single-use, non-cyclical desiccant refrigeration process proceeds. As the temperature of the material being cooled falls, the refrigerant (e.g. evaporating water) vapor pressure decreases, thereby reducing the pressure of the vapor supplied to the desiccant. Simultaneously, the temperature of the desiccant rises, thereby increasing the vapor pressure of the desiccant and water absorption rises so that vapor flow from water to desiccant becomes small. Conventional desiccant refrigerant devices have not breached the issue of modifying the evaporator pressure decrease with decreasing temperature.

Multi-staged desiccant refrigeration device


A bipolar transistor, connected between a high voltage source and a low voltage source, has a base connected to an input terminal. A clamp circuit is connected between the high voltage source and the base of the transistor. A first resistor is connected in parallel with the clamp circuit. An output terminal is connected to the emitter of the bipolar transistor. In one embodiment, the clamp circuit is formed by two diodes connected in series. In another embodiment, a second resistor for limiting current is provided between the input terminal and the base of the transistor. In yet another embodiment, the resistance value of the first resistor is smaller than the ON resistance of a pMOS transistor in the output circuit of a CMOS circuit connected to the input terminal. A high level from the output terminal produces a high level ECL level output with a potential that depends on V.sub.BE of the bipolar transistor, while a low level output depends on the level of the clamp circuit. High speed operation is obtained without fluctuation of the duty ratio and reduction of high potential level of the output signal from the output terminal.

This invention relates to a CMOS/ECL level converting circuit for converting a binary voltage level of a CMOS circuit into a binary voltage level of an ECL circuit. More particularly, this invention provides a CMOS/ECL level converting circuit having a more simple structure, outputting a signal having a fixed output level and a fixed duty ratio, and switching more quickly.
With rapid progress in the processing speed and integration density of computer systems, an ECL circuit which ensures high speed operation and a CMOS circuit which ensures high integration density and low power consumption are often formed in the same hybrid circuit. In such a hybrid circuit, a circuit for converting a voltage between the ECL level and CMOS level is provided in an input/output interface for high speed transfer of signals using the ECL level.
FIG. 4 illustrates a structure of a conventional CMOS/ECL level converting circuit 10X which is formed of a Bi-CMOS circuit to ensure high speed operation. This CMOS/ECL level converting circuit 10X is connected between a CMOS circuit 20 and an ECL circuit 30 and is mounted on the same chip as the CMOS circuit 20 to convert a binary voltage level of the CMOS circuit into a binary voltage level of the ECL circuit on the occasion of transferring a signal to the ECL circuit 30 from the CMOS circuit 20.
Referring to FIG. 4, MP1 designates a pMOS transistor; MN1 to MN3 are nMOS transistors; Q1 to Q6 are NPN transistors; D1 and D4 are diodes; R4 to R6 are resistors; VCC is a power supply line for high voltage; and VSS is a power supply line for low voltage. When a potential of the power supply line VCC for high voltage is set to 0.0 V, a potential of the power supply line VSS for low voltage is -5.0 V.
When an input signal VC to be supplied to the CMOS/ECL level converting circuit 10X from CMOS circuit 20 is set to a high level (0.0 V), pMOS transistor MP1, nMOS transistor MN3 and NPN transistor Q1 turn OFF, while nMOS transistors MN1, MN2 and NPN transistor Q2 turn ON and an output signal VE is supplied to the ECL circuit 30 from the CMOS/ECL level converting circuit 10X. The output signal VE has the base potential of the NPN transistor Q3 which is about -4.2 to -4.3 V. This potential can be calculated from a formula, VSS+V.sub.BE (Q2)+(voltage drop by ON resistance at NM2). This potential is also equal to Vcc-(voltage drop at R4)-V.sub.CB (Q3).
When an input signal VC is set to a low level (-5.0 V), the pMOS transistor MP1, nMOS transistor MN3 and NPN transistor Q1 turn ON, while nMOS transistors MN1, MN2 and NPN transistor Q2 turn OFF and the output signal VE becomes about -1.6 V. This potential is equal to VCC-V.sub.BE (Q1)-(voltage drop at D1). Therefore, a reference voltage of -2.9 V which is an intermediate level of the high and low levels is applied to the base of the NPN transistor Q4.
However, since a structure of the CMOS/ECL level converting circuit 10X is complicated, chip area required is large. Moreover, the duty ratio of input signal VC does not match the duty ratio of output signal VE due to fluctuation of ON resistance of pMOS transistor MP1. For example, in FIG. 5, when a threshold voltage of the CMOS/ECL level converting circuit 10X is VTH0 for the input signal VC having the duty ratio of 50% as shown in (A), an output signal VE has the duty ratio of 50% as shown in (B), but when a threshold voltage of the CMOS/ECL level converting circuit 10X becomes VTH1 due to fluctuation of ON resistance of the pMOS transistor MP1, the duty ratio of an output signal VE is deviated from 50% as shown in (C).


A reactive power compensation system includes a distributed energy resource situated at a local location configured to also receive power from a remote location by a distribution feeder line. The distributed energy resource includes an inverter including power semiconductor switching devices and an inverter controller configured for controlling the power semiconductor switching devices so as to provide reactive power support to the distribution feeder line.

The invention relates generally to distributed energy resources.
Electric power is delivered to residential consumers through power distribution systems that typically have radial topologies. In such power distribution systems, feeders branch out from a substation and reach a residential consumer through a step down transformer. Conventional power flow in such axial embodiments is unidirectional from the substation to the residence.
In a typical radial distribution system, voltage sag (drop) along the feeder is proportional to the reactive power on the feeder according to the formula:
            Δ                                      V        =                  PR        +        QX            V        ,wherein ΔV is the voltage drop, P, Q are the real and reactive power, V is the bus voltage; and R, X are feeder resistance and reactance respectively. The resistance R of the feeder line is typically orders of magnitude smaller than the reactance X. Therefore, the voltage drop on the feeder line can be depicted approximately as follows.
      Δ                          V    ≈            QX      V        .
For a long feeder line, voltage sag emerges as a significant issue when the reactive load is heavy. One proposed approach to solve the problem is to install capacitor banks at the substation or at pole top capacitors along the feeder line. The theory is that the capacitance load will offset the reactive power consumption on the feeder and that the voltage level at the end of the long feeder can thus be restored. However, this approach often requires extra capital expenditure by the utility. In addition, the capacitor banks are typically switched on and off incrementally. Therefore, continuous coverage of the reactive power compensation can be a challenge.
With emerging distributed energy resources such as residential photovoltaic (PV) systems bi-directionality is becoming more important. As distributed energy resources have increased presence in power distribution systems, advanced functions will be useful to leverage these assets. One such functionality which would be desirable is reactive power (or VAR) support.

System and method for providing reactive power support with distributed energy resource inverter


A sheath composition and a cable using the sheath composition are disclosed. The sheath composition contains a polyolefine resin and flame-retardant particles containing a metal hydrate. The flame-retardant particles are provided with a coating layer on the surfaces thereof and have a volume average particle diameter in a range from 1 to 500 nm.

1. Field of the Invention
The present invention relates to a sheath composition containing a polyolefine resin and flame-retardant particles mixed therein, as well as a cable using the sheath composition.
2. Description of the Related Art
Halogen based flame-retardant agents containing halogen atom have conventionally been added to sheath compositions for cables to add flame resistance thereto. Although halogen based flame-retardant agents exhibit superior flame retardancy, they may generate harmful halogenated dioxins when burned. Therefore, various flame-retardant agents for replacing the halogen based flame-retardant agents have been studied.
Typical examples of flame-retardant agents that replace the halogen based flame-retardant agents are metal hydroxides (metal hydrates) such as magnesium hydroxide, as described in Japanese Patent Application Laid-Open (JP-A) Nos. 2001-302851, 2004-168878 and 2003-34793. However, when cables using sheath compositions containing magnesium hydroxide are left in a highly humid atmosphere, magnesium carbonate may deposit on the surfaces of the cables through a reaction between the magnesium hydroxide and carbon dioxide in the air. This deposition of magnesium carbonate is known as a whitening phenomenon, and may lead to deterioration of flexibility, windability and flame resistance of cables.
Further, since flame retardancy of the metal hydrates is lower than that of the halogen based flame-retardant agents, and the like, it is necessary to blend a large amount of metal hydrate in a resin to obtain necessary flame resistance of the resin. However, if a large amount of metal hydrate is blended in a resin, problems arise such as deterioration of dynamic performances of the resin and lowering of moldability of the resin.

Sheath composition and cable using the same


A method for decoding a (n, k, d) cyclic code is disclosed. The method includes: receiving a word corresponding to the cyclic code; constructing a look-up table, wherein the look-up table includes k syndrome vectors and k error patterns; computing a syndrome vector of the received word by a hardware processor; comparing the weight of the syndrome vector of the received word with an error-correcting capacity; decoding the received word by adding the received word and the syndrome vector if the weight of the syndrome vector of the received word is not more than the error-correcting capacity; decoding the received word by inverting bits in the message section in sequence and re-compute a syndrome vector of the inverted received word if the weight of the syndrome vector of the received word is more than the error-correcting capacity.

In today's digital era, a wide variety of signals—such as video and audio signals—are digitalized. A few examples of products that use digital signals include digital TV, Bluetooth headphones, DVD players, WAP mobile phone handsets, etc. To ensure that the signals used in digital products may be read properly, enabling the products to present high-definition video and audio even when the signals have been transmitted over long distances, the signals are typically encoded and decoded. However, since transmission media and channels are easily corrupted by interference during data access and transmission, error detection and correction become more and more significant. Generally, error-correcting codes are widely used for enhancing reliability of data access and transmission. In the error-correcting codes, application of a cyclic code is not uncommon.
A finite field (also known as a Galois field) is a field composed of a finite number of elements. The number of elements in the field called the order or cardinality of the field. This number is always of the form pm, where p is a prime number and m is a positive integer. A Galois field of order q=pm will be designated either as GF (pm) or as Fq in the following. These symbols GF (pm) and Fq are fully synonymous. A polynomial over an arbitrary field (including a finite field) will be designated as p(x), or a similar symbol. A element in which the polynomial is to be evaluated will be designated by lower-case Greek letters such as α, β or γ, in the following. The definitions and properties of finite fields are described in many standard textbooks of mathematics, and reference is made to such standard textbooks for details.
In conventional cases, the error correction method of a cyclic code involves the use of an algebraic decoding method to eliminate syndromes from among the Newton's identities so as to obtain the error polynomial coefficient, which in turn may be used to obtain the error polynomial. However, with the increasingly higher requirements of communication in post-Internet era, the length and the kinds of cyclic codes increases, it becomes increasingly difficult for the high order equations produced when using an algebraic method to find a solution over a Galois field, making it difficult to obtain the error polynomial.
To solve the problems discussed above, which typically arises in the realm of computer networks and post-Internet era communication need, the present disclosure provides an error correction system applicable to all cyclic codes.

Methods, systems and computer-readable media for decoding cyclic code

CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS


A novel scanning microscope is described that uses near-field evanescent electromagnetic waves to probe sample properties. The novel microscope is capable of high resolution imaging and quantitative measurements of the electrical properties of the sample. The inventive scanning evanescent wave electromagnetic microscope (SEMM) can map dielectric constant, tangent loss, conductivity, complex electrical impedance, and other electrical parameters of materials. The quantitative map corresponds to the imaged detail. The novel microscope can be used to measure electrical properties of both dielectric and electrically conducting materials.

1. Field of the Invention
This invention relates generally to scanning probe microscopy and more specifically to scanning evanescent near field microwave and electromagnetic spectroscopy.
2. Description of the Related Art
Scanning probe type microscopes have typically been used to create visual images of a sample material. The image obtained may reflect any of a number of distinct electrical or magnetic properties of the sample material, depending on the parameter measured by the probe tip. For example, the tip may image electron tunneling, atomic force, absorption and refraction of propagating or evanescent electromagnetic waves, or other parameters. The tip may be in contact with the sample or it may be a short distance above the sample. A thorough discussion of scanning probe microscopes is presented by R. Wiesendanger, "Scanning Probe Microscopy and Spectroscopy: Methods and Applications" Cambridge University Press, 1994. Efforts in improving Scanning Probe Microscopes (SPMs) have focused almost entirely on increasing their resolution and sensitivity. While it is generally recognized that obtaining quantitative data to associate with the image detail would be highly desirable, two major technological barriers have prevented such instruments from being developed.
First, microscopy signals, as obtained from SPMs often are a combined function of topography and physical properties of the material. Separating them requires measuring at least two independent signals. For example, in scanning tunneling microscopy, the tunneling current is a function of both the tip to sample distance and the density of states. A recently developed scanning near-field optical microscope can measure optical signals such as luminescent spectra or optical index of refraction in addition to shear force, which can be used to determine the distance between tip and sample.
Second, to obtain quantitative information regarding the physical sample being imaged, complicated electromagnetic field equations in the region of the tip and sample must be solved. A review of this work is discussed by C. Girard and A. Dereux in Rep. Prog. Phys., vol. 657, 1996. Although numerical methods based on finite element analysis have been used to solve the field distribution around a near-field optical microscope tip, the complicated computational process involved, such as solving the Maxwell equations under real boundary conditions on a scale of a wavelength or less, is not practical in routine applications. The problem has been complicated for the work done in the past, because the microscopes were required to operate below a cut-off frequency and so suffered severely form waveguide decay, having a typical attenuation of 10.sup.-3 to 10.sup.-6 (R. F. Soohoo, J. Appl. Phys. 33:1276, 1962; E. A. Ash and G. Nichols, Nature, 237:510, 1972). In aperture or tapered waveguide probes, a linear improvement in resolution causes an exponential reduction in sensitivity. M. Fee, S. Chu, and T. W. Hansch, improved sensitivity and resolution to the micron level (Fee, M. et al., Optics Commun., 63:219, 1988) by using a transmission line probe with a reduced cross-section. However, further improvement in resolution was still accompanied by significant transmission line decay. The unshielded far-field wave propagation components around the tip of the transmission line probe significantly limited the resolution of the microscope, and particularly interfered with its use for quantitative analysis.
It would be highly desirable to have a scanning probe microscope capable of making images of features having submicron resolution and additionally capable of making quantitative measurements of the physical properties of the imaged features.

Scanning evanescent electro-magnetic microscope

The Regents of the University of California


A system and method for controlling a damper of vehicular suspension in which when the vehicle runs on a paved road and a frequency at which the detected sprung mass acceleration exceeds a dead zone is below a set value, the damping force characteristic is optimally controlled in a predetermined variable range. When the vehicle runs on a rough road and a frequency at which the detected acceleration exceeds the dead zone is above the set value, a minimum damping force limit of the predetermined variable range of the damping force characteristic is shifted toward a relatively high damping force side, The dead zone is set with an average value of the acceleration of sprung mass as a center. Hence, when the vehicle turns and zigzags, the vehicular body is inclined so that an absolute value of the sprung mass acceleration is largely changed. In this case, when an average value of the acceleration of the sprung mass is accordingly changed and the dead zone is accordingly shifted. Thus, the frequency at which the sprung mass acceleration exceeds the dead zone accurately corresponds to a situation on a road surface and the damping force characteristic is accurately controlled according to the road surface condition.

(1) Field of the invention
The present invention relates to a system and method for controlling a damping force characteristic of a shock absorber (hereinafter referred to as a damper) installed between an unsprung mass and a sprung mass of an automotive vehicle and particularly relates to the controlling system and method with a countermeasure against noise signals.
(2) Description of the Background Art
Japanese Patent Application First (unexamined) Publication No. Showa 61-163011 exemplifies a previously proposed damping force controlling system with the countermeasure against noise signals.
The disclosed previously proposed damping force controlling system generally includes: damping force detecting means for detecting a damping force of the vehicular damper; relative displacement calculating means for calculating a relative displacement between a vehicular body and tire wheel from a detected damping force; road running state determining means for determining a state of the road on which the vehicle runs according to a period of the relative displacement which is larger than a predetermined displacement from the calculated relative displacement; and damping force switching means for switching the damping force of the damper in response to a signal derived from the road state determining means.
That is to say, the damping force of the vehicular damper is detected by the damping force detecting means and the relative displacement between the vehicular body and tire wheel is estimated by the relative displacement calculating means.
Then, a controller determines whether the road condition is paved or rough according to a period during which a larger displacement occurs than a predetermined displacement from the estimated relative displacement and a damping force of the damper is switched by means of the damping force switching means. Thereby, the road surface condition such as paved road, rough road, and projection is determined so that an appropriate damping force control according to a road surface condition can be carried out.
However, in such a previously proposed damping force controlling system as described above, the determination of the road surface condition such as paved road, rough road, and projection is carried out by the comparison of the relative displacement between a tire wheel and vehicular body with a stationary predetermined reference quantity so that a condition in which the calculated displacement exceeds the reference quantity is maintained when the vehicle turns or zigzags.
Therefore, the appropriate damping force control according to the running road surface condition is not carried out so that a vehicular comfort and steering stability are reduced.

System and method for controlling damping force characteristic of shock absorber applicable to automotive suspension


A data processing apparatus may include a data conversion unit that arranges the input data in each transfer data in the conversion unit using one transfer data as one transfer unit and a predetermined number of transfer units as one conversion unit when converting a plurality of input data input sequentially into transfer data having a bit number identical to a predetermined bit number of a data bus and sequentially transferring the converted transfer data. The data conversion unit may include a data generation unit and a first data arrangement changing unit. The first data arrangement changing unit may include a bit change number calculating unit, a bit change number analysis unit, a first data sorting unit, and a data coupling unit.

1. Field of the Invention
The present invention relates to a data processing apparatus and a data processing method.
Priority is claimed on Japanese Patent Application No. 2011-066056, filed Mar. 24, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
An image pickup device, such as a still camera, a video camera, a medical endoscope camera, or an industrial endoscope camera, processes image data containing data of a great number of pixels (hereinafter referred to as "pixel data") with the increase of the number of pixels and speed of the image pickup device. In such an image pickup device, a memory for temporarily storing image data obtained by photographing is used when each processing block in the image pickup device processes the image data. Image data in each processing step is temporarily stored in the memory.
FIG. 13 is a block diagram illustrating a schematic configuration of an image pickup device in accordance with the related art. For example, image data processing in a photographing operation of the image pickup device shown in FIG. 13 is performed in the following order.
(Step 1)
First, an image pickup processing unit, for example, transmits image data obtained by a CCD (Charge Coupled Device) solid-state image pickup device to a memory via an output DMA (Direct Memory Access) unit to temporarily store the image data.
(Step 2)
Subsequently, an image processing unit reads the image data temporarily stored in the memory via an input DMA unit. The image processing unit performs image processing for recording or display on the read image data. The image processing unit then transmits the processed image data to the memory via the output DMA unit to temporarily store the image data.
(Step 3)
Subsequently, a display processing unit reads the image data subjected to image processing for display via an input DMA unit and causes a display device to display the image data.
Thus, in the image pickup device, the preceding processing block temporarily stores the image data in the memory. The subsequent processing block reads the image data stored in the memory and performs a next process. Thus, as respective processing blocks in the image pickup device perform delivery of the image data, which is a processing target, through the memory, processes of the image pickup device are sequentially performed.
In recent years, it has been desirable for an image pickup device such as a still camera, a video camera or the like to be able to be continuously used for a long time. Accordingly, there is a need for a technique for reducing power consumption of an electrical circuit of the image pickup device. One method of reducing the power consumption of the image pickup device includes a method of increasing a transfer rate for image data between each processing block (electrical circuit) and a memory. The increase of the transfer rate for image data, for example, may be realized by increasing a frequency of an operation clock of the image pickup device or shortening a transfer period of time of the image data between the processing block and the memory. This method reduces power consumption due to transfer of the image data by increasing the transfer rate of the image data.
As a technique of shortening a transfer period of time of image data between the processing block and the memory, a packing technique as disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 (hereinafter referred to as Patent Document 1) is known. The packing technique disclosed in Patent Document 1 is a technique of extending a bus width of a data bus used when each pixel data in the image data is transferred to a memory and arranging (packing) a plurality of adjacent pixel data in the data bus to transfer a plurality of pixel data at a single time. Using this technique, the number of data transfers required to transfer all pixel data can be further reduced as compared with conventional data transfer in which pixel data is transferred pixel by pixel, and the period of time for data transfer of the image data can be shortened. FIG. 14 is a diagram illustrating an example of an arrangement of image data. For example, when pixel data as shown in FIG. 14 obtained from a 16×16 Bayer arrangement CCD is transferred to a memory, in the packing technique disclosed in Patent Document 1, pixel data for 4 pixels is one transfer unit, thus reducing a transfer period of the image data to ¼. Accordingly, it is possible to reduce power consumption of an electrical circuit in the image pickup device, unlike a case in which pixel data is transferred to the memory pixel by pixel.
As a technique of further shortening the transfer period of image data, a packing method using burst transfer of DMA is considered. This is a method in which one burst, which is a memory access unit at a prescribed certain number of cycles, is considered a pixel data packing unit. FIGS. 15A and 15B are diagrams illustrating an example of pixel data packing in accordance with the related art. FIG. 15A illustrates a packing method disclosed in Patent Document 1. An example in which the pixel data shown in FIG. 14 is packed is shown in FIG. 15A. FIG. 15B illustrates an example in which the pixel data shown in FIG. 14 is packed in a burst unit. An example in which a bus width (hereinafter referred to as "memory bus width") of a data bus used when the pixel data is transferred to the memory (hereinafter referred to as "memory bus") is 32 bits, and memory access for one cycle in burst transfer (hereinafter referred to as "one transfer") is performed four times, that is, one burst transfer is performed through four transfers, is shown in FIGS. 15A and 15B. An example in which resolution of pixel data of one pixel, that is, a bit number of the pixel data is 9, 10, 12, and 14 from top to bottom, is shown in FIGS. 15A and 15B.
In the packing method disclosed in Patent Document 1 shown in FIG. 15A, pixel data for two pixels per one transfer can be arranged on a memory bus, and pixel data for 8 pixels per one burst can be transferred to the memory. On the other hand, in the burst unit-based packing method shown in FIG. 15B, pixel data for 14, 12, 10, and 9 pixels can be transferred to the memory. In the packing method disclosed in Patent Document 1, since pixel data is arranged (packed) in the memory bus width, that is, in a unit of one transfer, a sum of bit numbers of a plurality of arranged pixel data must not exceed the memory bus width. Accordingly, in the packing method disclosed in Patent Document 1, there are bits to which pixel data cannot be allocated (hereinafter referred to as "unused bits") within the memory bus width. On the other hand, in the burst unit-based packing method, since pixel data is arranged (packed) in units of bursts, even when a sum of bit numbers of a plurality of arranged pixel data exceeds the memory bus width, the pixel data can be arranged (packed) in a next transfer as long as the sum does not exceed one burst, as in FIG. 15B. That is, in the burst unit-based packing method, even when the memory bus width is not an integer times the resolution of pixel data, the pixel data can be arranged (mapped) over one transfer unit, which can reduce the number of unused bits. Accordingly, in the burst unit-based packing method, much pixel data can be transferred to the memory in the same time, that is, the transfer period of time of the image data can be shortened, and the power consumption of the electrical circuit in the image pickup device can be further reduced, as compared with the packing method disclosed in Patent Document 1.
In general, when data change (change (inversion) of data "0"→"1" or "1"→"0") is less, power consumption is known to be lower. Accordingly, reducing the power consumption of the image pickup device by reducing the data change on the memory bus between each processing block (electrical circuit) and a memory in an image pickup device is also considered. FIGS. 16A, 16B, 16C and 16D are diagrams illustrating a relationship between the data change on the data bus (memory bus) between the processing block and the memory in the image pickup device and the power consumption. FIG. 16A illustrates an example in which a bus width of a memory bus between the image pickup processing unit and the memory in the image pickup device shown in FIG. 13 is 32 bits. The data change on the memory bus is schematically shown in FIGS. 16B to 16D. In the example of FIGS. 16A, 16B, 16C and 16D, power consumption is lowest in the case of FIG. 16B in which there is no data change on the memory bus, and highest in the case of FIG. 16D in which there are the most data changes on the memory bus.
It can be seen from the above that if there is a great amount of change in pixel data between two continuous transfers (e.g., pixel data in first and second transfers of each burst transfer shown in FIGS. 15A and 15B) in the burst transfer between each processing block and the memory in the image pickup device, power consumption due to the transfer of the image data increases. That is, the power consumption due to the transfer of the image data varies in proportion to the number of the same bits (bit number) on the memory bus changing between the two transfers.
In general, there is expected to be a small amount of change in data between adjacent pixels in image data, and bits whose values are being inverted are expected to be less than bits whose values are not being inverted when the same bits of each pixel data of adjacent pixels are compared. FIGS. 17A and 17B are diagrams illustrating an example of a data arrangement state in a pixel data packing method in accordance with the related art. Here, when the packing method disclosed in Patent Document 1 and the burst unit-based packing method, which are shown in FIGS. 15A and 15B, are compared with each other, the power consumption due to the transfer of the image data is lower in the packing method disclosed in Patent Document 1 in which the same bits are aligned in pixel data with the same colors, as shown in FIGS. 17A and 17B. Further, FIGS. 17A and 17B show a case in which the bit number of pixel data of one pixel is 9 in the packing method disclosed in Patent Document 1 and the burst unit-based packing method shown in FIGS. 15A and 15B.
More specifically, in the packing method disclosed in Patent Document 1 shown in FIG. 17A, least significant bits of the memory bus shown in a range A are all the same bits (least significant bits) of pixel data with the same colors. On the other hand, in the burst unit-based packing method shown in FIG. 17B, least significant bits of the memory bus shown in a range B are all different bits of pixel data having different colors. It can be seen from this that, when locations of bits of pixel data arranged on the memory bus are made different between two continuous transfers by packing the image data in a burst unit, a change amount of the same bits on the memory bus becomes great and the power consumption due to the transfer of the image data increases.
That is, in the packing method disclosed in Patent Document 1 shown in FIG. 17A, the power consumption due to the transfer of the image data is low, but data transfer efficiency is low. In the burst unit-based packing method shown in FIG. 17B, the data transfer efficiency is low, but the power consumption due to the transfer of the image data is high.
Thus, more pixel data is arranged on the memory bus when packing the pixel data into the burst units. As a result, the transfer period of time of the pixel data can be shortened and the power consumption due to transfer of the image data can be reduced. However, since locations of bits of the pixel data arranged on the memory bus are different between two continuous transfers, sufficient reduction of the power consumption due to the transfer of the image data cannot be obtained.
FIG. 18 is a diagram illustrating another example of a data arrangement state in the pixel data packing method in accordance with the related art. In the packing method disclosed in Patent Document 1, for example, pixel data for 3 pixels can be arranged (packed) in one transfer to pack the pixel data, as shown in FIG. 18. However, in this case, for example, least significant bits of a memory bus shown in a range C are the same bits (least significant bits) of the pixel data, but are pixel data having different colors. Pixel data having different colors is highly likely to be greatly different in value, and even in the packing method disclosed in Patent Document 1, the power consumption due to the transfer of the image data is not reduced due to the pixel data arrangement in one transfer.

Data processing apparatus and data processing method


Various embodiments may provide an electrical connection structure. The electrical connection structure may include a first substrate having a first surface defining a cavity, and an inner wall defining a via extending from the cavity. The electrical connection structure may also include an interconnect structure provided in the via so that at least a portion of the interconnect structure protrudes into the cavity. The electrical connection structure may further include a second substrate having a second surface facing the first surface. The electrical connection structure may additionally include a connection element on the second surface. At least a portion of the connection element may be received in the cavity so that the connection element is in electrical connection with the interconnect structure.

Fan-out wafer level packaging is becoming more popular in recent years, due to low cost, good reliability and ease of multi-chips integration. Fan-out packages are widely adopted in mobile applications due to the low package profile because such packages do not involve the use of a ball grid array (BGA) substrate. First generation fan-out wafer level packages involve laterally connecting embedded chips using re-distribution layer (RDL) layers on the surrounding mold compound. Second generation and third generation of fan-out wafer level packages include vertical interconnects in the mold area for package on package (PoP) stacking application.
For mobile applications, the desirable package height should be lower than 1 mm. However, conventional PoP stacks are very high due to BGA substrate and thick solder balls used to connect top and bottom package. Fan-out wafer level packages have been effective in reducing the package height, but considerable efforts are required to further reduce the stacked package height.

Electrical connection structure, semiconductor package and method of forming the same

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