A graphic display processing apparatus which includes having a CPU, a VRAM and a display controller, a data operation unit, an access cycle generator, an address generator and a sequential transfer sequencer. The graphic display processing apparatus also includes a mask pattern generator, dot mask generator and data position transformer. In the graphic display processing apparatus block transfer and character drawing are performed at high speeds, thereby making a window system more practical and offering comfortable operational environment to the user.

The present invention relates to a graphic display processing apparatus for performing control of drawing in the graphic display processing apparatus.
With the recent development of semiconductor technology, the function and performance of an information processing apparatus such as personal computer and work station have been improved significantly year by year. Speedup of the central processing unit (hereinafter referred to as CPU), increased capacity of the storage unit such as memory and external memory unit and improvements in man-machine interface can be mentioned as factors of the improved performance. Under this background, a so-called window system has been practiced which is operated by displaying one or more rectangular frames called windows on the screen and assigning an application program to each of the windows. This type of window system features the full graphics display processing wherein not only images and figures but also characters are displayed through graphics. In the past, too, there was a window system, which required too much processing time to be practical because of the performance of CPU and the capacity of storage unit. As is known in the art, the performance of the whole window system is affected significantly, especially by the processing performance of the following drawing primitives:
(1) Bit Block Transfer PA1 (2) Character Drawing PA1 (3) Line Segment Drawing PA1 a: averaged one access time for VRAM PA1 b: fixed overhead of transfer processing of horizontal one raster PA1 c: fixed overhead of bit block transfer processing PA1 m: overhead of processing necessary for one-word transfer PA1 n: the number of VRAM accesses necessary for one transfer of data of one word PA1 p: plane coefficient PA1 x: the number of words transferred in the horizontal direction PA1 y: the number of words transferred in the vertical direction PA1 *: arithmetic multiplication sign PA1 +: arithmetic addition sign PA1 (1) Provided common to all the planes of the VRAM are a data structure transformer for transforming the format of external data by using mirror image inversion and swap separately or in combination, a bit mask register for controlling writing to the VRAM in unit of bit, an AND circuit for ANDing the contents of bit mask register and the data of data structure transformer bit by bit, a bit mask shifter for shifting data of the bit mask register, data structure transformer or AND circuit, a third merge register for holding the previous contents of data of the data structure transformer, a third shifter for shifting data of the data structure transformer and data of the third merge register, and a read data synthesizer for ORing bits of the contents of a read data selector of each plane to be described later so as to synthesize read data supplied to the CPU. PA1 (2) There is provided an address generator including a source address register for holding an address of a source area on the VRAM, a destination address register for holding an address of a destination area, a pattern address register for holding an address of a pattern area, a source offset register for holding a value added to the contents of the source address register to update the same when a read access cycle by the access cycle generator to be described later ends, a destination offset register for holding a value added to the contents of the destination address register to update the same when a write access cycle by the access cycle generator to be described later ends, a pattern offset register for holding a value added to the contents of the pattern address register to update the same when the read access cycle by the access cycle generator to be described later ends, a first address adder for adding the contents of source address register and that of source offset register, the contents of destination address register and that of destination offset register or the contents of pattern address register and that of pattern offset register so as to update the value of each register, and a second address adder for adding the write data of CPU and the contents of source address register, destination address register or pattern address register so as to update the value of each register. PA1 (3) There is provided an access cycle generator which, when receiving a request for reading the VRAM from the CPU or a sequential transfer counter to be described later, a read access request containing at least one of access operations to source, destination and pattern areas by using the address generator and when receiving a request for writing the VRAM from the CPU or the sequential transfer counter to be described later, generates a write access or the combination of read access and write access to a destination area by using the address generator and drives the memory controller for the VRAM. PA1 (4) There is provided a sequential transfer counter which starts the access cycle generator by the designated number of sequential operations of write cycle or combination of read cycle and write cycle. PA1 (5) There is provided a sequential transfer mask pattern generator which generates bit mask patterns respectively designated during the first and final write transfer processings by the sequential transfer counter and supplies the bit mask patterns, as external data, to a bit mask controller through the data structure transformer of data operation unit and during write transfer lying between the first and final write transfer processings, generates a bit pattern which permits writing of all the bits and supplies the bit mask pattern, as external data, to the bit mask controller through the transformer. PA1 (1) Provided common to all the plane of the VRAM are a data structure transformer for transforming the format of external data by using mirror image inversion and swap separately or in combination, a bit mask register for controlling writing to the VRAM in unit of bit, an AND circuit for ANDing the contents of bit mask register and the data of data structure transformer bit by bit, a bit mask shifter for shifting data of the bit mask register, data structure transformer or AND circuit, a third merge register for holding the previous contents of data of the data structure transformer, a third shifter for shifting data of the data structure transformer and data of the third merge register, and a read data synthesizer for ORing bits of the contents of a read data selector of each plane to be described later so as to synthesize read data supplied to the CPU. PA1 (2) There is provided an address generator including a source address register for holding an address of a source area on the VRAM, a destination address register for holding an address of a destination area, a pattern address register for holding an address of a pattern area, a source offset register for holding a value added to the contents of the source address register to update the same when a read access cycle by the access cycle generator to be described later ends, a destination offset register for holding a value added to the contents of the destination address register to update the same when a write access cycle by the access cycle generator to be described later ends, a pattern offset register for holding a value added to the contents of the pattern address register to update the same when the read access cycle by the access cycle generator to be described later ends, a first address adder for adding the contents of of source address register and that of source offset register, the contents of destination address register and that of destination offset register or the contents of pattern address register and that of pattern offset register so as to update the value of each register, and a second address adder for adding the write data of CPU and the contents of source address register, destination address register or pattern address register so as to update the value of each register. PA1 (3) There is provided an access cycle generator which, when receiving a request for reading the VRAM from the CPU or a sequential transfer counter to be described later, generates a read access request containing at least one of access operations to source, destination and pattern areas by using the address generator and when receiving a request for writing the VRAM from the CPU or the sequential transfer counter to be described later, generates a write access or the combination of read access and write access to a destination area by using the address generator and drives the memory controller for the VRAM. PA1 (4) A data position transformer is provided which, when the number of bits of data from the CPU differs from the number of bits of the VRAM data bus, puts the data of the CPU to the left or right on the VRAM data bus through an image on the screen and supplies the thus put data, as external data, to the data structure transformer of data operation unit. PA1 (1) Provided common to all the planes of the VRAM are a data structure transformer for transforming the format of external data by using mirror image inversion and swap separately or in combination, a bit mask register for controlling writing to the VRAM in unit of bit, an AND circuit for ANDing the contents of bit mask register and the data of data structure transformer bit by bit, a bit mask shifter for shifting data of the bit mask register, data structure transformer or AND circuit, a third merge register for holding the previous contents of data of the data structure transformer, a third shifter for shifting data of the data structure transformer and data of the third merge register, and a read data synthesizer for ORing bits of the contents of a read data selector of each plane to be described later so as to synthesize read data supplied to the a CPU. PA1 (2) There is provided an address register including a source address register for holding an address of a source area on the VRAM, a destination address register for holding an address of a destination area, a pattern address register for holding an address of a pattern area, a source offset register for holding a value added to the contents of the source address register to update the same when a read access cycle by the access cycle generator to be described later ends, a destination offset register for holding a value added to the contents of the destination address register to update the same when a write access cycle by the access cycle generator to be described later ends, a pattern offset register for holding a value added to the contents of the pattern address register to update the same when the read access by the access cycle generator to be described late ends, a first address adder for adding the contents of source address register and that of source offset register, the contents of destination address register and that of destination offset register or the contents of pattern address register and that of pattern offset register so as to update the value of each register, and a second address adder for adding the write data of CPU and the contents of source address register, destination address register or pattern address register so as to update the value of each register. PA1 (3) There is provided an access cycle generator which, when receiving a request for reading the VRAM from the CPU or a sequential transfer counter to be described later, generates a read access request containing at least one of access operations to source, destination and pattern areas by using the address generator and when receiving a request for writing the VRAM from the CPU or the sequential transfer counter to be described later, a write access or the combination of read access and write access to a destination area by using the address generator and drives the memory controller for the VRAM. PA1 (4) There is provided a sequential transfer counter which starts the access cycle generator by the designated number of sequential operations of write cycle or combination of read cycle and write cycle. PA1 (5) There is provided a sequential transfer mask pattern generator which generates bit mask patterns respectively designated during the first and final write transfer processings by the sequential transfer counter and supplies the bit mask patterns, as external data, to a bit mask controller through the data structure transformer of data operation unit and during write transfer lying between the first and final write transfer processings, generates a bit pattern which permits writing of all the bits and supplies the bit mask pattern, as external data, to the bit mask controller through the transformer. PA1 (6) There is provided a dot mask generator which generates a bit pattern for permitting write of only one bit on the VRAM data bus, supplies as external data the bit pattern to the bit mask controller through the data structure transformer of data operation unit, selectively renders, upon completion of write cycle to the VRAM, the bit pattern unchanged or rotated by one bit clockwise or counterclockwise, and when an overflow takes place as a result of the rotation, increments the value of destination of the address generator by +1 for clockwise rotation and decrements by -1 for counterclockwise rotation.
The bit block transfer is a generalized processing for transferring data in an area defined by a rectangle to another rectangular area and is an important drawing primitive which occupies 50% or more of the processing of the whole window system. The character drawing occupies 20% to 30% of the processing in a general window system. Importance of the processing performance of the drawing can be understood readily when taking into consideration the fact that an application program principally containing character display for use in word processors is executed during the drawing. The line segment drawing occupies, in general, 10% to 30% of the overall processing. It should be understood that the drawing is also an important drawing primitive, by taking into account the fact that the percentage of processing will be further increased when a sophisticated figure is displayed using an application program of, for example, computer-aided design (CAD).
Improvements in the performance of the CPU and increase in the capacity of the storage unit are mentioned hereinbefore but they merely provide background techniques for causing the window system to approach the practical base. In other words, it is the point of the above processings (1) to (3) how data, which has experienced the pre-processing such as calculation of coordinates to be drawn, can be stored at a high speed in the memory for display, i.e., video random access memory (hereinafter referred to as VRAM). In order to speed the drawing processing per se up, the display system has to be provided with a drawing speedup mechanism. Under the circumstances, many expedients for high-speed drawing have hitherto been contrived.
In a conventional system as disclosed in Japanese Patent Application Laid-open No. JP-A-59-119385, coordinates of a pixel are designated and an address is calculated through hardware to carry out bit block transfer. In a conventional system as disclosed in Japanese Patent Application Laid-open No. JP-A-01-107295, read/write operation from the CPU is expanded to perform bit block transfer. In accordance with a conventional system as disclosed in Japanese Patent Application Laid-open No. JP-A-01-140196, an address of the VRAM is generated by means of an address register and an address offset register.
A display system having a VRAM of plane type is considered. Another structure of VRAM called a packed pixel type is also available but the plane type is suitable for speedup of bit block transfer. In the plane type, the VRAM as viewed from the CPU is constructed of one or more planes and the CPU accesses plane by plane. The number of planes determines the number of colors which can be displayed simultaneously or the number of gradations of gray scale which are displayed simultaneously. For example, two colors or gradations can be displayed with one plane, 16 colors or gradations can be displayed with 4 planes and 256 colors or gradations can be displayed with 8 planes. When the transfer processing of horizontal one raster is effected repetitively by the number of rasters necessary to complete the whole processing, time t for bit block transfer processing can generally be expressed by the following equation: EQU t=p*y*(b+(a*n+m)*x)+c (1)
where each parameter has the meaning as below:
Firstly, the presupposition of the graphic display processing apparatus considered. In bit block transfer, when data representative of a plurality of pixels read out of a transfer originator, i.e., source area is written into a desired position of a transfer destination, i.e., destination area, data of one word of the source is so written as to cross two words of the destination at a high probability. For example, in the case of a graphic display processing apparatus having a hardware construction capable of reading 16 pixels by one VRAM access, data can be written into the destination without resort to shift processing through one write operation at a probability of 1/16 and data subject to shift processing crosses two words at a probability of 15/16. Therefore, without any support by hardware, the value of the number n of VRAM accesses in bit block transfer changes with the presence or absence of shift processing, resulting in different values of processing time t. Contrarily, with the merge function provided, the value of n can be kept to be constant regardless of shift processing of data to be transferred. The merge function is a technique disclosed in, for example, Japanese Patent Application Laid-open No. JP-A-63-231548. The outline of the function is as follows. When a shifter is used during bit block transfer, data is overflowed by shifting to leave a remainder of data which is not drawn in a transfer destination word during a first round. In order to permit the remainder to be drawn during the next round of word transfer, a register is provided which holds the data during one preceding round, whereby the next transfer data is merged with the held data to provide data of 2-word length from which a portion necessary for the next transfer is cut out and drawn. With the aim of further increasing the speed of the graphic display processing apparatus capable of keeping the value of n constant regardless of the presence or absence of shift processing through the use of the merge function, it is possible to presupposes realization of a graphic display processing apparatus having the merge function.
The parameter p called plane coefficient will now be described. The parameter p is determined by how many planes a VRAM of a graphic display processing apparatus in question has and how many planes of the VRAM can be handled for drawing processing simultaneously. When all the planes of the VRAM can be processed simultaneously, the value of parameter p is 1 regardless of the number of planes of the VRAM. When the processing is permitted to be carried out only plane by plane, the value of parameter p is 4 in the case of, for example, 16-color display (4 planes) and is 8 in the case of 256-color display (8 planes). When the CPU reads the contents of the VRAM to store it in the main memory, the VRAM must be read plane by plane and the value of parameter p cannot be made to be 1 regardless of the number of planes. But in the drawing processing within the VRAM according to the present invention, each plane is provided with a control circuit for support of drawing to permit drawing processings of all the planes to be effected in parallel. Aiming at further speedup of the graphic display processing apparatus capable of keeping the value of parameter p one regardless of the number of planes, the present to presuppose realization of a drawing processing apparatus capable of processing all the planes simultaneously.
In order to reduce the processing time t, it is necessary to reduce the transfer word number x in the horizontal direction by increasing the number of bits of data to be processed at a time or making the parameters a, b, and m small. The transfer word number x may be reduced by increasing the number of memory chips constituting the VRAM, widening the data bus width of the VRAM and increasing the amount of hardware of control circuits needed therefor. But at present, because of physical and economical restrictions, the data bus width per VRAM plane is often 16 to 32 bits. In addition, bit block transfer for small area is affected by other parameters.
The parameter a is a basic parameter for determining not only the bit block transfer but also the drawing speed of display unit. Since the parameter a signifies averaged access time for the VRAM, the value of this parameter may be decreased by using a memory element for VRAM such as a multi-port memory, accessing the VRAM with a plurality of words in high-speed page mode, or reducing the access time per se by adopting a device of higher access time; or by eliminating a synchronous overhead due to the difference between operation period of the CPU and that of the VRAM. The parameter c is an overhead related to the pre-processing of drawing such as application program, operating system and device driver and cannot be made to be sufficiently small by means of hardware of the apparatus. Generally, the ratio of c to t is often small and therefore, the absolute value of parameter c is a factor which is automatically reduced through improvements in the performance of the CPU.
The parameter b is multiplied by the integer number of rasters necessary for bit block transfer processing. Therefore, when the ratio of parameter b becomes large to the term a *n *x as in the case of bit block transfer of a vertically elongated area, the influence of this parameter becomes eminent and so the parameter b must be minimized as possible. Factors dominating the parameter b will be described later. The parameter m represents time required for raster operation to be effected between transfer originator data read out of the VRAM and transfer destination data. When processed through software, the parameter m becomes about 15 times as large as the term a *n, causing significant speed reduction. It is to be noted that in equation (1), the coefficient concerning transfer word number is liable to have the greatest influence upon the whole processing time t.
Problems encountered in the conventional system will now be clarified based on equation (1). In the technique shown in Japanese Patent Application Laid-open No. JP-A-59-119385, only a simple transfer processing of a rectangular area such as source copy can be carried out and this technique cannot be utilized for transfer requiring overlap of graphic forms which needs an operation between an original graphic at the transfer originator and a graphic to be drawn. "Source copy" is a kind of bit block transfer processing for copying a graphic at the transfer originator (source) onto an area of the transfer destination (destination). The operation processing effected between the original graphic and the graphic to be drawn is called raster operation. In both the processing of overlapping two graphic forms or adding patterns and the processing of displaying graphic cursors by means of a mouse or a pointing device, drawing is done using bit block transfer accompanied by the raster operation. In the window system, the bit block transfer can be considered to be accompanied by the raster operation excepting particular cases. The prior art in question is effective to only a particular instance of bit block transfer which does not include any raster operation. Also, the prior art of interest needs a control unit such as a microprocessor for the sake of updating a read address register and a write address register, though not clearly described in Japanese Patent Application Laid-open No. JP-A-59-119385. Even if the control unit is dedicated to the apparatus of Japanese Patent Application Laid-open No. JP-A-59-119385, it takes obviously a long time to update the read address register and write address register. This sets up a factor of increasing the parameters m and b. Additionally, in the technique of the literature, x component and y component of coordinates of a given dot are used as upper and lower terms, respectively, to combine y and x so as to determine a VRAM address. Accordingly, if a lateral bit map of the VRAM has a structure of other than the power of 2, the VRAM address cannot be calculated from the coordinates. This sets up a factor of increasing the parameter c.
A technique disclosed in Japanese Patent Application Laid-open No. JP-A-01-107295 is capable of effecting a raster operation between an original graphic and a graphic to be drawn and causing read/write operation by the CPU to perform transfer of data. But, in this prior art, the read cycle of the CPU is expanded to perform bit block transfer, so that the synchronous overhead occurs between cycle time of the CPU and cycle time of the VRAM, failing to give full play to the performance. This sets up a factor of increasing the parameter a.
An address generator shown in Japanese Patent Application Laid-open No. JP-A-01-140196 is comprised of an address register and an address offset register. This address generator can perform address calculation even when the VRAM has a lateral bit map of other than the power of 2 but disadvantageously, when the capacity of the VRAM is increased and the number of bits of an address necessary for accessing is increased, it must sometimes perform register setting twice in a general information apparatus having a data bus of 16 bits. For example, in order to designate, in unit of word, an address of a VRAM having a bit map of 2048.times.1024 pixels, there needs an address of 17 bits. Then, to set an address register of 17 bits, a total of two write operations into registers must be done, including one write operation into a register of 16 bits and the other write operation into a register of one bit. Generally, setting of control register and the like is effected with the I/O cycle by the CPU and consumes time. In order to reduce the number of setting operations of the control register, the control program is also required to hold an address of an area to be transferred onto the VRAM and only a lower value of the address which is required to be changed is set. This method, however, uses registers of the CPU for the purpose of holding address and disadvantageously, the number of registers of the CPU which would otherwise be utilized for other types of control is decreased. In performing bit block transfer, these address control registers are rewritten frequently, with the result that the number of setting operations is increased and the program is sophisticated to give rise to factors of performance degradation. This leads to an increase of the parameter b.
When data of a rectangular area of a desired size is transferred, it is frequent that opposite ends of the rectangle respectively begin with a midway and end in a midway of a word which is the unit of accessing the VRAM. Accordingly, in performing transfer in unit of raster, a separate processing is needed for drawing the beginning and end of transfer processing in portions within the word, giving rise to a decrease in processing speed. According to specific measurement results, the processing time required for the processing of the opposite ends amounted, in average, up to about 40% of the processing time for the whole bit block transfer. This sets up a factor which increases the parameter b remarkably.
In addition, for each application program, a data structure of a general memory constituting the main memory sometimes differs from that of a memory constituting the VRAM and the control program is required to include conversion, leading to a decrease in processing speed. This sets up a factor of increasing the parameter m.
Since equation (1) is a general expression, equations which indicate processing time t in typical different processings in bit block transfer will now be described.
In the case of drawing consisting of only write to the VRAM such as paint-out drawing, only an operation of writing color information into the VRAM generally proceeds and hence the value of n is one. Therefore, the processing time t is given by equation (2): EQU t=y*(b+(a+m)*x)+c (2).
In the case of source copy which is simple transfer from the transfer originator to the transfer destination, VRAM read at the transfer originator and VRAM write at the transfer destination are needed and so the value of n is 2. Therefore, the processing time t is given by equation (3 EQU t=y*(b+(2a+m)*x)+c (3).
In case where data at the transfer originator and data originally present at the transfer destination undergo operation processing and are written into the transfer destination, VRAM read at the transfer originator, VRAM read at the transfer destination and VRAM write at the transfer destination are needed and so the value of n is 3. Therefore, the processing time t is given by equation (4): EQU t=y*(b+(3a+m)*x)+c (4).
In case where data at the transfer originator, data originally present at the transfer destination and a pattern undergo operation processing and are written into the transfer destination, VRAM read at the transfer originator, VRAM read at the transfer destination, VRAM read of the pattern and VRAM write at the transfer destination are needed and so the value of n is 4. Therefore, the processing time t is given by equation (5): EQU t=y*(b+(4a+m)*x)+c (5).
There are these kinds of basic operations in bit block transfer. In the prior art, the value of parameter m in equations (2) to (5) cannot be made to be constant. This accounts for the fact that even when means is provided which makes the value of parameter m zero or makes it nearly zero in comparison with the value of parameter a to achieve speedup in the simple processing such as source copy pursuant to equation (3), load on the CPU is increased as soon as bit block transfer with raster operation pursuant to equation (4) or (5) begins and the value of parameter m is increased to about 5 to 20 times the value of parameter a. Disadvantageously, the processing speed therefore differs significantly depending on the kind of bit block transfer.
Problems encountered in character drawing will now be described. The character drawing signifies the processing of writing a character font (the form of a character) to a desired position on the screen of full bit map. Generally, the address of VRAM increases in the horizontal direction of display. On the assumption that the data bus of VRAM is of, for example, 16 bits, data of the VRAM having the plane structure is arranged horizontally in unit of 16 pixels and therefore drawing must be carried out after the character font is suitably shifted for positioning. The thus shifted character font sometimes exceeds the word boundary of VRAM and in some cases write operation must be effected twice.
While the VRAM address increases in the horizontal direction of display as described previously,character font data results from slicing a character in unit of dot and slices are sequentially stored in the vertical direction. The conventional system disclosed in Japanese Patent Application Laid-open No. JP-A-1-140196 is capable of addressing the VRAM vertically and therefore, when combined with the other conventional systems, it may be considered to be suitable for expanding the character font data vertically. But this is possible only when the number of bits of the character font data equals the number of bits of the VRAM data bus. Take the case where the font data is of 8 bits and the VRAM data bus is of 16 bits, for instance. When a character font is to be transferred to the VRAM by using a byte (8 bits) data transfer instruction by the CPU, the VRAM address increases vertically but the character font data from the CPU develops on upper 8 bits and lower 8 bits of the VRAM data bus alternately. This is because the CPU address is assigned in unit of byte and in the 16-bit bus, the lower 8 bits and upper 8 bits are defined as even and odd addresses, respectively. Accordingly, without any expedient applied, the conventional systems in combination fail to draw the character font at an expected position.
Incidentally, due to the fact that in the display system of personal computers, the VRAM data bus of 8 bits is leading internationally, the character font is also designed as to have an 8-bit width in many applications. On the other hand, in a display system of the class having 1000 dots in the horizontal direction, the VRAM data bus is often of 16 bits or more in order to increase the drawing speed. Therefore, in conveniences set forth so far will in general occur in the future. The character drawing faces the problems described as above.
To describe line segment drawing, a straight line is considered as a line segment. Many kinds of algorithm for generating coordinates of dots constituting a straight line have been contrived but a unit for drawing a line segment at a high speed has in general a different construction as that of the aforementioned unit for increasing the speed of bit block transfer and must be provided separately.

Graphic display processing apparatus and method for improving the speed and efficiency of a window system


A method and system for administering calls on a voice network allows a user to selectively determine which calls will be accepted and assists the user in placing calls to other users on the network. The user may establish a list of users whose calls will be accepted and may also establish a list of users whose calls will not be accepted. The method and system may provide unwanted callers with an option to speak with the user for a fee. The method and system may also display phone or other messages to the user on a video display.

This application is co-pending with related patent applications entitled xe2x80x9cAutomated Communications Assistant and Methodxe2x80x9d Ser. No. 10/253,306 and xe2x80x9cFee Collection System and Method for Call Completionxe2x80x9d Ser. No. 10/253,755, each having at least one co-inventor and assignee in common with the instant application, and both being filed concurrently herewith and incorporated by reference herein in their entirety.
The systems and methods relate to communication networks, and more particularly to administering and displaying messages on the network.
Voice networks in current use may provide a range of features for administering calls on the network. For incoming calls, a caller identification feature can display the caller""s name or number to a user to allow the user to screen unwanted calls. Additional features may allow a user to block selected callers or to accept calls only from selected callers. Unidentified calls may be intercepted and the callers may be requested to identify themselves. The information is recorded and provided to the user, who may decide to accept or decline the call. When the user is not able to accept a call, the caller may leave a message, or the call may be forwarded to a number selected by the user. The user may also dial a code to return a missed call, or to reconnect to a previous incoming call. For outgoing calls, the user may have the network repeatedly dial a number that the user could not access and provide the user with a signal when the number has been reached. Network users may also choose to block their own caller identification information from being displayed to the receiver.
While the above features may provide increased functionality and convenience for the networks in which they are employed, there may be a number of instances where these networks do not provide the functionality and convenience that some users may require. As an example, the features may be difficult to implement, requiring a user to remember access codes and/or requiring substantial user input. Other limitations may exist when users block their own caller identification information, in that the block may prevent all call recipients from access to the information. Also, a user may not be available to respond to the signal when the network has finally connected with a number that could not be accessed. Oftentimes, the caller identification information is insufficient for the user to make an intelligible decision to receive the call or not. These limitations and others as perceived by the users of current networks may decrease the overall number of subscribers to such networks.
A method and system for administering communications on a network allows a user to selectively determine which calls will be accepted and assists the user in placing calls to other users on the network. The user may establish a list of users whose calls will be accepted and may also establish a list of users whose calls will not be accepted. The method and system may provide unwanted callers with an option to speak with the user for a fee. Users may establish xe2x80x9cbusiness cardxe2x80x9d headers, or profiles, which serve to identify the user to a called party. The user may also maintain profiles for received calls by using the xe2x80x9cbusiness cardxe2x80x9d header provided by the caller, or by inputting caller profiles. The method and system may also be used in conjunction with a scheduling system, such that calls amongst two or more users will be initiated at an agreed upon time.
Embodiments of the method and system may include a method for displaying messages by connecting to a network to receive messages from the network, determining identification information for the messages received, converting the identification information to output video signals corresponding to the identification information and displaying the output video signals to a user of the system on a television. The messages may be phone messages, email messages and/or connectivity messages to inform the user when other users selected by the user may be connected to the network. The method and system may convert voice messages to text messages and combine the text messages with the identification information. The user may select between the television signal display and the identification information video signal display. The method and system may record the television signals interrupted when the user selects the video signal display. The method and system can maintain a listing of messages received and the listing can indicate actions taken by the user with respect to the messages on the message listing, which can include acknowledgement, message response, message transfer and message deletion.


A perpendicular magnetic recording medium, such as a perpendicular magnetic recording disk, has a magnetic “torque” layer (MTL) that exerts a magnetic torque onto the perpendicular magnetic recording layer (RL) in the presence of the applied perpendicular write field. The MTL thus acts as a write assist layer in reversing the magnetization of the RL. A coupling layer (CL) is located between the MTL and the RL and provides the appropriate ferromagnetic coupling strength between the MTL and the RL.

1. Field of the Invention
This invention relates generally to perpendicular magnetic recording media, and more particularly to a disk with a perpendicular magnetic recording layer for use in magnetic recording hard disk drives.
2. Description of the Related Art
Perpendicular magnetic recording, wherein the recorded bits are stored in a perpendicular or out-of-plane orientation in the recording layer, is a promising path toward ultra-high recording densities in magnetic recording hard disk drives. The most common type of perpendicular magnetic recording system is one that uses a "probe" or single pole recording head with a "dual-layer" media as the recording disk. The dual-layer media comprises a perpendicular magnetic data recording layer (RL) formed on a "soft" or relatively low-coercivity magnetically permeable underlayer (SUL), with the SUL serving as a flux return path for the field from the pole recording head. This type of system is also called "Type 1" perpendicular magnetic recording. A schematic of such a prior art system with a read element for reading the recorded data is shown in FIG. 1.
FIG. 2 is a schematic of a cross-section of a prior art perpendicular magnetic recording disk showing the write field H acting on the recording layer RL. The disk also includes the hard disk substrate, a seed or onset layer (OL) for growth of the SUL, an exchange break layer (EBL) to break the magnetic exchange coupling between the magnetically permeable films of the SUL and the RL and to facilitate epitaxial growth of the RL, and a protective overcoat (OC). As shown in FIG. 2, the RL is located inside the gap of the "apparent" recording head (ARH), which allows for significantly higher write fields compared to longitudinal or in-plane recording. The ARH comprises the write pole (FIG. 1) which is the real write head (RWH) above the disk, and a secondary write pole (SWP) beneath the RL. The SWP is facilitated by the SUL, which is decoupled from the RL by the EBL and produces a magnetic mirror image of the RWH during the write process. This effectively brings the RL into the gap of the ARH and allows for a large write field H inside the RL. However, this geometry also results in the write field H inside the RL being oriented nearly parallel to the surface normal, i.e., along the perpendicular easy axis of the RL grains, as shown by typical grain 10 with easy axis 12. The parallel alignment of the write field H and the RL easy axis has the disadvantage that relatively high write fields are necessary to reverse the magnetization because no torque is exerted onto the grain magnetization. Also, a write-field/easy-axis alignment increases the magnetization reversal time of the RL grains (M. Benakli et al., IEEE Trans. MAG 37, 1564(2001)). For these reasons, "tilted" media have been theoretically proposed, in which the magnetic easy axis of the RL is tilted at an angle of about 45 degrees with respect to the surface normal, so that magnetization reversal can be accomplished with a lower write field and without an increase in the reversal time. (K.-Z. Gao and H. N. Bertram, IEEE Trans. MAG 39, 704(2003)). However, there is no known fabrication process to make high-quality recording media with a tilted easy axis.
What is needed is a perpendicular magnetic recording media that displays a magnetization reversal behavior similar to tilted media and is fully compatible with conventional fabrication processes.

Perpendicular magnetic recording medium with magnetic torque layer coupled to the perpendicular recording layer

Hitachi Global Storage Technologies Netherlands B.V.


A filter system including a designated filter cartridge having a geometric projection, a flow restriction valve that controls fluid flow out of a filter system, and a priming pump configured to prime the filter. The flow restriction valve. The flow restriction valve includes at least on fluid flow check valve configured to allow the priming pump to prime the filter system.

In many applications, it is desirable to have a fuel filtration system in which the flow of fuel to an engine is prevented if no filter cartridge is installed, or if an incorrect filter cartridge is installed. The operation of an engine with no filter cartridge installed or with an incorrect filter cartridge installed may result in a degradation of engine performance or permanent damage to the engine. Tampering with a no filter no run fluid filtration system may allow the operation of an engine with no filter cartridge installed or with an incorrect filter cartridge installed. Fluid filtration systems may also include a priming mechanism configured to move fluid through the fluid filtration system for the purposes of priming the fluid filtration system for operation.
As shown in FIG. 1, some conventional fluid filtration systems may include both a priming pump system and a flow restriction valve configured to prevent fluid flow through the fluid filtration system when no filter cartridge or an incorrect filter cartridge is installed in the system. In such conventional fluid filtration systems, the fluid filtration system may include a flow restriction valve body 10, a priming pump valve body 20, and a priming plunger assembly 30. The flow restriction valve body 10 and the priming pump valve body 20 are formed as separate components. The flow restriction valve body 10 of the pre-existing fluid filtration systems is susceptible to tampering, which may result in fluid flow through the fluid filtration system in the absence of a designated filter cartridge.

No filter no run fluid filtration system


An intake valve for a high pressure pump for internal combustion engine fuel having a valve body having a seat with which cooperates a shutter kept closed by a first spring of substantially constant pressure and by a second spring varying in pressure during at least part of the stroke of the piston. The springs are helical compression types and their pressures are summed on the shutter, which has a plate and a stem. The first spring is located between the valve body and a flange integral with a sleeve fitted to the stem in an adjustable position. The second spring is located between the plate and the piston.

1. Technical Field
The present invention relates to an intake valve for a high-pressure pump, in particular for internal combustion engine fuel.
2. Background Art
As is known, the fuel injected into internal combustion engine cylinders must be compressed to around 1600-bar pressure. Modern feed systems comprise a high-pressure piston pump for feeding the compressed fuel to a common rail communicating with the various engine injectors, and which in turn is supplied with fuel at around 5-bar pressure by a low-pressure pump.
Each pump cylinder has an intake valve comprising a shutter normally closed by a spring, and which opens the valve when the difference in the fuel supply pressure in the cylinder exceeds the force or pressure exerted by the spring on the shutter.
The pump normally comprises a group of radial pistons, e.g. three pistons spaced 120° apart, which are activated by a common cam actuator fitted to a shaft; and each shutter spring is appropriately calibrated, but so located that its pressure is unaffected by the position of the relative piston.
The above known intake valve (valve 1) has various drawbacks, by resulting in unbalance of both the operating shaft and the delivery pressure of the cylinders when low flow, e.g. less than 30% of maximum flow, is demanded of the pump.
That is, the delay with which the various valves open varies, so that the pistons compress different amounts of fuel. In very low flow conditions, as when the engine is run at idling speed, some of the valves may not even open at all, so that unbalance of the operating shaft of the pump is considerable and greatly reduces the working life of the pump. Moreover, given its high elastic constant, the spring can only be calibrated within a tolerance range relatively wide.
To reduce the unbalance on the pump caused by the intake valve described above, a high-pressure pump has recently been proposed in which the shutter spring is located between the shutter and the piston (valve 2), so that, during the intake stroke of the piston, the pressure of the spring is reduced rapidly, while still allowing the valve to open.
The above known valve 2 has a valve body with a substantially truncated-cone-shaped lateral surface. The valve body is fixed to the cylinder by a ring nut acting on the lateral surface, and has an intake conduit sloping with respect to the valve body axis.
This known valve 2 also has several drawbacks. In particular, the shutter spring has a high elastic constant and therefore requires a considerable pressure drop to open; on account of its location, the spring cannot be calibrated, so that numerous versions of the spring must be provided for different applications; the shape of the valve body makes automated preassembly of the valve difficult; and, finally, location of the intake conduit weakens the valve body, which, in use, is subject to cracking.
From document U.S. Pat. No. 5,701,873, it is also known a piston pump having a coaxial intake valve, the shutter of which is kept closed by the sum of pressures of two different helical compression springs. One of these springs is relatively strong and permanently exerts a closing pressure on the shutter, whereas the other spring is relatively weak and is supported on a spring plate, which is axially displaceable in a chamber communicating with the intake fluid for damping purpose.

Intake valve for a high-pressure pump, in particular for internal combustion engine fuel

Centro Studi Componenti per Veicoli S.p.A.


Embodiments of the present disclosure provide a plasma processing system, comprising: a transfer chamber, the transfer chamber including a plurality of sidewalls, each sidewall being connected with a plurality of process chambers; each process chamber including a base therein, the base including a central point; wherein at least two process chambers connected to a same sidewall form one process chamber group, wherein a first distance is provided between the central points of two bases in a first process chamber group, and a second distance is provided between the central points of two bases in a second process chamber group, the first distance being greater than the second distance; and the transfer chamber comprises a mechanical transfer device; a rotating pedestal includes two independently movable robot arms thereon, the two robot arms; and the two robot arms both include a plurality of rotating shafts and a plurality of rotating arms, wherein a remote rotating arm of each robot arm further includes an end effector for holding a substrate. The mechanical transfer device according to the present disclosure may simultaneously retrieve and place the substrate in the process chamber group with the first distance and the substrate in the process chamber group with the second distance.

Semiconductor chips are increasingly applied in various kinds of electronic devices, while manufacturing of semiconductor chips needs a considerable number of plasma processors that perform processing such as plasma etching and CVD (Chemical Vapor Deposition) on to-be-processed substrates. Various kinds of process chambers are needed during plasma processing. For example, the etching and CVD mentioned above all need corresponding process chambers to execute such processing; other processing such as stripping and coating of photoresist also need special process chambers. A load lock is also needed to load a substrate into/out of a vacuum environment from atmosphere; a transfer chamber is also needed to transfer the substrate between different process chambers and the load lock; inside the transfer chamber is further provided at least one robot arm for accurately transferring and disposing the unprocessed and processed substrates in the vacuum environment. The process chambers having the above functions are all required to be arranged around the transfer chamber. To make the entire plasma reactor more compact, i.e., mounting more process chambers to a same transfer chamber, the prior art provides a chamber body layout structure shown in the U.S. Pat. No. 6,486,444. In the prior art, two process chambers are integrated into one process chamber group, the two process chambers being connected to a same transfer chamber sidewall, and the other side facets being also used by other process chamber groups. The last side facet is occupied by the load lock available for two substrates to transfer simultaneously.
Compared with earlier prior arts, although the layout structure may accommodate more process chambers, it has only limited processing functions, where only one processing can be performed, such as plasma etching. With development of processing, it is desired to perform multiple functions within one plasma processing system, so as to save the time for transiting the substrate between different processing systems and prevent potential contaminations during transiting in the atmosphere, thereby improving the overall processing efficiency. However, a new problem arises when process chambers of different functions are arranged in a same plasma processing system. Process chambers with different functions will differ in internal spaces and external sizes, which will cause different central point distances of two juxtaposed plasma process chambers mounted to different sidewalls of the transfer chamber. Because the original robot arms in the transfer chamber are designed for retrieving and placing two process chambers with a fixed central point distance, it is impossible to perform a new task of the plasma processing system using the original robot arms.
Therefore, it is desired to develop a new robot arm in the industry to retrieve and place, with only one robot arm, a plurality of substrates between process chamber groups having different central point distances. Optimally, the robot arm should have a simple structure and a low cost and may be applied to various kinds of plasma processing systems.

Plasma processing system and operating method of the same

ADVANCED MICRO-FABRICATION EQUIPMENT INC. CHINA


Methods and systems are provided for a secured electronic communication in a network that includes a verification station, a registration station, and a authentication station. At the registration station, a request for a digital certificate is received from a user. The registration station instructs the verification station to forward to the user a message associated with the request. The message is compared against the user at the authentication station to determine whether the message properly identifies the user. A first signal indicating the result of the comparison is sent to the verification station. If the first signal indicates that the message properly identifies the user, a second signal is sent to the registration station. Based on the second signal, the registration system then generates a digital certificate.

Presently, consumers and businesses exchange vast amounts of information in order to engage in a business transaction or sale. In traditional business transactions, consumers use accepted means of payment to purchase items at a store or another place of business. In exchange, businesses offer goods or services in consideration of the payment by the consumers. In many instances, businesses use security methods to verify the method of payment, for example verifying through a driver's license that a consumer is the same as the individual identified on a credit card.
As electronic communication becomes more popular as a means for transacting business, through for example the Internet, consumers and businesses desire a more secured form of electronic communication. For example, it is desired that a credit card number electronically sent to a business is not intercepted or used improperly. For e-business transactions to become more widely accepted, consumers must use the electronic services provided by businesses, and businesses must be able to ensure the security of such electronic transactions. Otherwise, the advantages of an electronic commerce environment will not be realized, due to a lack of participation or demand by consumers and businesses. Therefore, businesses and consumers who communicate electronically need to know that their respective messages are private and need to verify the identity of a sender.
To ensure that transactions take place smoothly between parties, it is essential that the parties not only trust the communication path but also have assurances regarding the integrity of the information transmitted and the identity of the party transmitting the information. Without this assurance, the possibility of fraud, either unintentional or purposeful, could undermine the ability of parties to effectively engage in electronic commerce.
In modern electronic commerce environments, digital certificates are used to prevent interception of transactions and to allow authentication and verification of the transactions. For example, a digital certificate makes it possible to verify someone's claim that they have the right to use a given key in a key-based security scheme, which helps prevent unauthorized users from impersonating a rightful user. Digital certificates, used in conjunction with encryption, provide a more complete security solution by assuring the identity of all parties involved in an electronic transaction.
It is therefore desirable to provide systems and methods to allow for the secure and reliable exchange of information between parties utilizing electronic communication.

System and method for providing secured electronic transactions


The disclosure is directed to a well system environment communication system comprising of an acoustic communicator capable of communicating encoded data with a first wireless transceiver through a fluid medium and the first wireless transceiver capable of communicating encoded data with a second transceiver through a non-fluid medium. In one example, an acoustic communicator is communicatively coupled with a downhole tool allowing the downhole tool to communicate indirectly with a well system controller. In another aspect of the disclosure, a method is described wherein an acoustic communicator located in a wellbore can encode data from a downhole tool and communicate the data through a fluid medium to a first wireless transceiver and the first wireless transceiver can communicate with a second transceiver through a non-fluid medium.

Hydrocarbons, such as oil and gas, are located in subterranean formations. To obtain the oil or gas, various oil and gas operations, such as drilling, logging, and completion, are performed. Communication up and down the wellbore between the various equipment and controllers at the surface of the wellbore and the tools, components, and sensors located within the wellbore are beneficial for the performance of the various oil and gas operations. Reliable communications uphole and downhole in the harsh environment of a wellbore is challenging in the various operations.

Acoustics through fluid communication system


An azomethine dye is disclosed, represented by the general formula (I), (II) or (III): ##STR1## wherein R.sup.1, R.sup.2, R.sup.3 and R.sup.4 each independently represents a hydrogen atom or nonmetallic atom group; X represents --OH or --NR.sup.5 R.sup.6 ; R.sup.5 and R.sup.6 each independently represents a hydrogen atom, alkyl group, aryl group or heterocyclic group; R.sup.7, R.sup.8, R.sup.9, R.sup.10, R.sup.11, R.sup.12 and R.sup.13 each independently represents a hydrogen atom or nonmetallic atom group; and R.sup.1 and R.sup.2, and/or R.sup.2 and R.sup.5, and/or R.sup.5 and R.sup.6, and/or R.sup.6 and R.sup.3, and/or R.sup.3 and R.sup.4, and/or R.sup.7 and R.sup.8, and/or R.sup.9 and R.sup.10, and/or R.sup.11 and R.sup.12, and/or R.sup.12 and R.sup.13 may be connected to each other to form a cyclic structure. A heat transfer dye providing material is also disclosed, comprising a support having thereon a dye providing layer containing a heat migrating dye, the dye providing layer comprising at least one azomethine dye represented by the general formula (I), (II) or (III).

An azomethine dye, particularly an azomethine dye in which p-dialkylaminophenyl group is conneced to a nitrogen atom in imine is produced by the oxidative coupling reaction of an active methylene or phenol with an N,N-dialkyl-p-phenylenediamine. Such an azomethine dye has a wide range of tones such as yellow, red, magenta, blue and cyan and thus has been widely used as an image forming dye for silver halide color photographic materials for use in the subtractive color process with three colors, i.e., yellow, magenta and cyan. Blue and cyan dyes are produced from phenols, naphthols and 2,4-diphenylimidazoles. Magenta and blue dyes are produced from 5-pyrazolones, acylacetonitriles, 1H-pyrazolo[1,5-a]benzimidazoles, 1H-pyrazolo[5,1-c]-1,2,4-triazoles, and 1H-pyrazolo[2,3-b]-1,2,4-triazoles. Yellow dyes are produced from acylacetanilides, diacylmethanes and malondianilides. These dyes are further described in JP-A-60-186567, JP-A-63-145281 and JP-A-63-113077 (the term "JP-A" as used herein means an "unexamined published Japanese patent application").
In recent years, new color image forming methods such as color electrophotography, ink jet process and heat-sensitive transfer process have been proposed. On the other hand, the increasing demand for filters for solid image pickup tube and color liquid crystal television coupled with the development of electronic imaging has caused azomethine dyes to be applied and studied not only in color photography but also in various systems or merchandises. Further, dyes which exhibit absorption in the infrared region are disclosed in JP-A-3-81192, JP-A-3-81193, JP-A-3-81194, and JP-A-2-172794.
However, these azomethine dyes have many disadvantages. For example, they exhibit a low fastness to heat, moisture, light, chemicals, air, etc., can hardly be synthesized and are expensive.
In particular, many of azomethine dyes which exhibit absorption in the near infrared region have a low fastness. Thus, the development of azomethine dyes having a high fastness have been keenly desired.
Moreover, these known azomethine dyes show a broad absorption wavelength or exhibit unnecessary absorption. Thus, they leave much to be desired as image forming dyes or filter dyes,
Besides the above mentioned disadvantages, these known azomethine dyes have further disadvantages that when used as heat transfer dyes, they can hardely heat-migrate, they exhibit a low fastness to heat, light, moisture, air, oxygen, chemicals, etc., they are susceptible to a drop in the image sharpness, they can easily be retransferred, they can hardly form a heat transfer dye providing material (that is, they have a low solubility), they are susceptible to image bleeding with time, and they can deteriorate the light fastness of other dyes.

Pyrrole ring-or condensed pyrrole ring-containing azomethine dye


A method for determining the displacement of or the tampering with a device is provided. The method includes determining an effective displacement in an X direction of a device, determining an effective displacement in a Y direction of the device, and determining an effective displacement in a Z direction of the device. The method also include determining if any one of the effective displacement in the X direction, the effective displacement in the Y direction, or the effective displacement in the Z direction is greater than a predetermined threshold, and when at least one of the effective displacement in the X direction, the effective displacement in the Y direction, and the effective displacement in the Z direction is great then the predetermined threshold, determining that the device has been displaced.

Alarm systems are known in the art. For example, an alarm system can include a fire detection system or a life safety system. Wireless alarm systems throughout the world require monitoring for integrity and reporting tampering with individual devices in the system.
Specifically, for fire detection systems, section 62.2.1 of the Ninth Edition of UL (Underwriters Laboratories) 864 requires that removal of an initiating device transmitter from its installed location shall cause the immediate transmission of a tamper signal. Accordingly, wireless sensor devices employed in known fire detection systems have been equipped with systems to detect the displacement of the wireless device from an intended mounting location.
To achieve compliance with industry requirements, known alarm systems typically mount wireless sensing devices to a permanently fixed object. For example, many known alarm systems use screws to mount a wireless sensing device to grid work supporting removable ceiling tiles rather than to a ceiling tile itself. The wireless sensing device is equipped with an electromechanical limit switch that detects the removal of the cover over the mounting hardware within the device. However, the use of electromechanical devices adds additional cost as well as engineering design time.
In known alarm systems, the placement of the wireless sensing device is restricted, for example, to the grid work. However, the ideal placement of a sensing device may instead be on a ceiling tile for esthetic reasons or for a variety of environmental reasons. For example, it may be preferable to keep the sensing device away from an air duct, in the center of a space, or away from metallic objects. In architecturally significant or historical structures, the use of damaging mounting devices, such as deep screws, may be restricted.
There is thus a continuing, ongoing need for low-cost systems and methods that eliminate mounting restrictions of wireless sensing devices in an alarm system. Preferably, such systems and methods use acceleration vector analysis and filter algorithms, radio frequency triangulation, acoustic ultrasonic ranging, and/or light ranging to detect the displacement of a device or the tampering therewith.

Systems and methods for detection of device displacement and tampering


The present invention is to provide a notification system for timed power supply, which includes a timed power supply device and a wireless notification device. The timed power supply device is able to receive a set time inputted by a user and stores the set time into a memory module, and then starts timing, providing power supply and generating an elapsed time, respectively. When the timed power supply device determines that the difference between the elapsed time and the set time reaches a threshold value, the timed power supply device issues a notification signal through a wireless transmitter module to the wireless notification device carried by the user, so as to ensure that the user will be notified, via an alert signal generated by the wireless notification device according to the notification signal, that the set time is coming to an end.

Barbecue is a very popular activity worldwide. Family and friends gather together at a barbecue not only to enjoy the fun of cooking but also to strengthen interpersonal bonds.
Conventionally, barbecuing involves putting hot charcoal in a charcoal pan, placing a barbecue rack above the charcoal, and laying food on the rack. Thus, the food is spaced from the charcoal and gradually cooked by the heat thereof. During the grilling process, it is common practice to turn the food with tongs so that the food is heated evenly. Alternatively, the food to be cooked is held by a spit provided above hot charcoal and is turned, during the roasting process, by rotating the spit. To prevent the food from charring or being overcooked, it is necessary to turn the food on a regular basis, which is very inconvenient.
As a solution to the aforesaid problem, electric barbecue apparatuses were developed and are now commercially available. Basically, an electric barbecue apparatus uses a motor to rotate a spit, thus allowing the food secured on the spit to rotate along with the spit and be exposed uniformly to the heat of charcoal. By doing so, the food is heated evenly and kept from burning. As the user need not use tongs or other tools to turn the food being cooked, electric barbecue apparatuses are effective in saving time and energy, thus making barbecue more convenient. However, if the user has other things to tend to during the roasting process and must leave the electric barbecue apparatus, the food being roasted is very likely to be forgotten and eventually become scorched or overcooked, which is highly undesirable.
To prevent such undesirable situations, an experienced user would use a timer with an alerting function, predetermine the required roasting time according to the type and thickness of food, set the roasting time with the timer, and place the timer around the electric barbecue apparatus. When the roasting time is up, the timer issues a sound alert to notify the user. Nonetheless, if the user is away from the electric barbecue apparatus at this moment, it will be impossible for the user to hear the sound alert. As a result, the best time at which to remove the food from the electric barbecue apparatus is missed, and the food may end up burned or overcooked.
Therefore, the issue to be addressed by the present invention is to solve the various problems described above and design a notification system for timed power supply whereby a user will be notified in a remote manner that a preset time is about to be up, thus allowing the user to remove food from an electric barbecue apparatus timely.

Notification system for timed power supply


An end wall arrangement for an engine compartment of a motor vehicle is provided that includes an end wall, at least one component mounted on the end wall, and a planar covering element having sound-absorbing properties. The covering element is provided with at least one flap having heat-insulating properties and being configured optionally to cover the at least one component or to render the component accessible.

1. Field of the Invention
The present invention relates to an end wall arrangement.
2. Description of the Background Art
In some motor vehicles, additional heat shielding plates are used for particularly high-performance engines and diesel engines in order to protect the brake lines and the air conditioning lines for refrigerant and feed and replenishing water. The abovementioned components are typically mounted in an end wall region of the engine compartment. There are numerous components in this respect, serving to shield against high temperatures, in the end wall region of the engine compartment.
DE 10 2004 022 895 A1 discloses a sound-absorbing and planar covering element. The depicted covering element is provided for installation below the engine compartment and is equipped with a service flap which can be opened, for example, for service work (changing the engine oil, etc.). The service flap means that it is unnecessary to remove the entire covering element for service work.
However, a covering element of this type is not suitable or provided for installation on the end wall of an engine.

End wall arrangement for an engine compartment of a motor vehicle


A combined greenhouse has a foundation bed, an outer wall assembly, a temperature control assembly, a roof and a plant bed. The foundation bed has multiple stands and a reinforcing device. The outer wall assembly is mounted on the foundation bed and has four walls and an outer frame. Each wall has a base frame and a transparent device. The outer frame is mounted outside the wall that is mounted on the front stand of the foundation bed. The temperature control assembly is mounted in the foundation bed and has a ventilating device, a water-wall device and an air-sucking device. The roof is mounted on the outer wall assembly and has multiple roof mounts. The plant bed is mounted on the reinforcing device and each has two end frames, at least one linking frame, a baseboard, a plant net and multiple resisting boards.

1. Field of the Invention
The present invention relates to a greenhouse, and more particularly to a combined greenhouse that can be assembled quickly and easily to grow plants or to cultivate organisms.
2. Description of Related Art
Climate change will directly influence the agriculture and the aquaculture. Planting or cultivating in a conventional greenhouse can reduce the impact of climate change. According to the characteristics of the plants or the organisms, different kinds of conventional greenhouses are built.
The conventional greenhouse is designed to simulate the nature to grow plants or to cultivate organisms, is mounted with multiple glass windows to enable the sunshine to transmit into the conventional greenhouse and has a ventilating device to enable air to flow in the conventional greenhouse to adjust the temperature of the conventional greenhouse.
In order to increase the space of the conventional greenhouse to grow more plants or to cultivate more organisms, the pipes or studs of the conventional greenhouse are connected to each other by welding and this will consume a lot of time in assembling the conventional greenhouse. Furthermore, the large space of the conventional greenhouse will increase the costs for manufacturing and transporting the conventional greenhouse. In addition, the errors of the welding operation between the pipes or studs of the conventional greenhouse will affect the structural strength of the conventional greenhouse.
The combined greenhouse in accordance with the present invention mitigates or obviates the aforementioned problems.


A pilot channel signal for time-division multiplexing with one or more traffic channel signals in a broadcast/multi-cast signal and for code-division multiplexing with a continuously transmitted pilot channel signal is described. In an exemplary method for transmitting a broadcast/multicast signal, a pilot symbol sequence is obtained for each slot of one or more frames of the broadcast/multicast signal, so that the pilot symbol sequence varies for each slot of a given frame. The pilot symbol sequence for each slot is spread with a channelization code, and the spread pilot symbol sequence for each slot is scrambled, using a scrambling code, to form a first pilot channel signal. The first pilot channel signal is transmitted so that it is time-division multiplexed with one or more traffic channel signals transmitted during each slot and code-division multiplexed with a second pilot channel signal transmitted during all slots of the one or more frames.

The 3rd-Generation Partnership Project (3GPP) has recently developed specifications, applicable to Release-7 Universal Terrestrial Radio Access (UTRA) systems, for delivering so-called Multimedia Broadcast Multicast Services (MBMS) using a single-frequency network (SFN). MBMS over SFN (MBSFN) provides significantly higher spectral efficiency compared to the MBMS approach in earlier systems (e.g., Release 6 systems), and is primarily intended for broadcasting mobile television services that demand high bit-rates on carriers dedicated to MBMS. Since MBMS services are broadcast only, MBSFN is inherently suited for transmissions in unpaired frequency bands.
With SFN transmissions, multiple base stations transmit the same waveform at the same time. A mobile terminal can receive signals from two or more of these base stations and treat the received signal as if it was transmitted by a single base station serving a large cell. For UTRA systems, SFN transmission implies that a cluster of time synchronized base stations (Node B's, in 3GPP terminology), transmit the same data, using the same channelization and scrambling codes.
Mobile terminals developed for use in Wideband Code-Division Multiple Access (W-CDMA) systems generally use a continuously transmitted, code-multiplexed pilot signal (known as the common pilot channel, or CPICH, in 3GPP specifications) for channel estimation. Although a code-multiplexed pilot channel performs well in unicast radio environments, the MBSFN channel has a much larger delay spread and thus a larger number of paths to estimate in the radio receiver. Accurate channel estimation requires long averaging over many slots. This is difficult to realize in situations where a small duty cycle is used, i.e., where a mobile terminal's receiver is only operational during intervals that are as short as possible. Thus, improved pilot signals are needed.

Time-division multiplexed pilot signal for integrated mobile broadcasts


A leg exerciser includes a casing having a slot in a top thereof, a transmission mechanism mounted in the casing, a legrest, and at least one massage rod. The transmission mechanism includes a motor and a movable block extending through the slot of the casing. The movable block moves reciprocatingly along the slot of the casing when the motor is turned on. The legrest is fixed to the movable block to move therewith. The legrest has two recessed portions for supporting a user""s legs. The massage rod is attached to the movable block to move therewith and includes at least one massage portion for providing a massaging function. At least one wheel is mounted to the massage rod and in rolling contact with the casing.

1. Field of the Invention
The present invention relates to a leg exerciser with a massaging function. In particular, the present invention relates to a recumbent leg exerciser with a massaging function.
2. Description of the Related Art
A typical recumbent leg exerciser includes a legrest that moves reciprocatingly. The legs and a waist area of a user are exercised when the legs of the user are on the legrest. However, the recumbent leg exerciser could not provide a massage function.
An object of the present invention is to provide a recumbent leg exerciser that provides a massage function while exercising the legs of the user.
A leg exerciser in accordance with the present invention includes a casing having a slot in a top thereof, a transmission mechanism mounted in the casing, a legrest, and at least one massage rod. The transmission mechanism includes a motor and a movable block extending through the slot of the casing. The movable block moves reciprocatingly along the slot of the casing when the motor is turned on. The legrest is fixed to the movable block to move therewith. The legrest has two recessed portions for supporting a user""s legs. The massage rod is attached to the movable block to move therewith and includes at least one massage portion for providing a massaging function. At least one wheel is mounted to the massage rod and in rolling contact with the casing.


A push switch comprising: a button made of a flexible material having a cap shaped top operation part, a flat part formed extending laterally from an edge of an opening in the top operation part, and a side wall formed extending downward from an outer edge of the flat part; a switch substrate fitted in close contact with the inner circumference of the side wall and abutting the bottom face of the flat part of the button; and a switch arranged inside the button, on the switch substrate, wherein the outer circumferential face of the side wall of the button and the bottom face of the switch substrate are covered by integrally molded resin.

1. Field of the Invention
The present invention relates to a push switch.
2. Description of the Related Art
Conventional push switches include, for example, switch operation devices that are installed in vehicles and operated by pressing from the exterior (Japanese Patent Laid-Open Publication No. 2008-10360). As shown in FIG. 10(a) and FIG. 10(b), this push switch comprises a switch case 101, made from hard resin, a switch button 102, made from soft resin, and a main switch unit 107.
This switch case 101 is formed as a rectilinear box having a space at the interior for receiving the switch button 102. The main switch unit 107 is assembled at the interior of the switch button 102, and a thermosetting resin 111 is applied at the interior of the switch case 101. This thermosetting resin 111 solidly fixes the main switch unit 107 in place in the switch case 101 and the switch button 102, and allows for waterproofing of the main switch unit 107.
However, in methods where the resin is applied (injected) into the switch case, it is difficult to fill the interior of the switch case without gaps, and thus gaps may occur between the resin and the inner side of the switch case. In this event, if drops of water adhere to the bottom of the switch case, there is a risk that these drops of water will infiltrate the main switch unit, which reduces the waterproofness of the push switch.
Furthermore, the work of applying the thermosetting resin requires much time and skill, which greatly reduces productivity.

Push switch and method of manufacturing the same


The present invention provides processes for the preparation of Tasimelteon (1), as well as processes for the preparation of intermediates of Formulas (2), (3) and (4) useful in the preparation of Tasimelteon (1).

Tasimelteon, marketed in the United States as HETLIOZ® for the treatment of Non-24-Hour Sleep-Wake Disorder, is a melatonin receptor agonist having the chemical name N-{[(1R,2)-2-(2,3-dihydro-1-benzofuran-4-yl)cyclopropyl]methyl}propanamide, and the following structural formula (1):

A preparation of Tasimelteon is described in WO 98/25606 A1, which discloses a family of substituted benzodioxole, benzofuran, dihydrobenzofuran and benzodioxanes and their derivatives that are useful as melatonergic agents. Tasimelteon is prepared by the reaction of amine (3) and propionyl chloride, as shown in Scheme 1.

In WO 98/25606 A1, amine (3) is prepared as the fumarate salt (III) by a lengthy sequence, shown in Scheme 2, that includes an asymmetric cyclopropanation using (−)-2,10-camphorsultam as a covalent chiral auxiliary and 1-methyl-3-nitro-1-nitrosoguanidine as a cyclopropanating agent. However, neither the basic chiral auxiliary nor many of the reagents, including the cyclopropanating agent, employed in this process is particularly suitable for use in industrial scale production.

Prasad, J. S et al. in Org. Process. Res. Dev. 2003, 7, 821, discloses two approaches for the preparation of epoxide (V), which can be used as an intermediate in the preparation of carboxylic acid (VII) (see Scheme 3). In both approaches, chiral epoxide (V) is prepared from olefin (X), either by Jacobsen asymmetric epoxidation (AE) or a Sharpless asymmetric dihydroxylation (AD) and epoxidation of intermediate diol (IV). If required, chiral enrichment of the intermediates is performed using acid (VII).

The optimized AE process in Prasad et al. is reported to yield epoxide (V) with 70-74% ee, which was further enriched to >99% ee by crystallization of a (+)-dehydroabietylamine (DAA) salt of the downstream acid (VII). The optimized AD process in Prasad et al. is reported to produce 99% of the desired enantiomer of epoxide (V). Cyclopropanation of epoxide (V) obtained by the AD and AE processes was converted sequentially to ester (VI), acid (VII) and, in several additional downstream steps, Tasimelteon (1) in 22% (AE) and 43% (AD) overall yields from olefin (X).
CN 102675268 A discloses a further process for the preparation of Tasimelteon starting from chiral carboxylic acid (VII), as depicted in Scheme 4. In this process, carboxylic acid (VII) is activated with thionyl chloride before being converted to an amide, which is then reduced and coupled with propionyl chloride to yield Tasimelteon.

Carboxylic acid (VII) is prepared according to the procedures reported in US 2007/0270593 A1 and Singh, K. A. et al. (Org. Process Res. Dev. 2002, 6, 618). The preparation of acid (VII) reported in US 2007/0270593 A1 involves stereoselective cyclopropanation of olefin (X) using chiral ruthenium catalysts comprising salen (2,2′-ethylenebis(nitrilomethylidene)diphenol or N, W-ethylenebis(salicylimine)) and alkenyl ligands. In this procedure, carboxylic acid (VII) is produced having 83.6% ee. The Singh publication provides an alternative process involving reaction of chiral epoxide (V) with the anion of triethyl phosphonoacetate (TEPA) to form carboxylic acid (VII). Chiral epoxide (V) is prepared by the AD method reported above, which is capable of producing 99% of the desired enantiomer.
CN 104327022 A discloses a resolution of racemic acid (VIIa) using (R)-1-(α-amino-benzyl)-2-naphthol through the formation of diastereomeric amides, as described in Scheme 5. After resolution of the diastereomeric amides, the desired amide is cleaved to provide carboxylic acid (VII). Carboxylic acid (VII) is then activated, converted to an amide, reduced with borane, and coupled with propionyl chloride to produce Tasimelteon.

WO 2015/123389 A1 discloses a process for the preparation of Tasimelteon involving an asymmetric cyclopropanation of olefin (X) with ethyl diazoacetate in the presence of a chiral catalyst, as depicted in Scheme 6. Following hydrolysis of the resulting ester to provide carboxylic acid (VII), the chiral purity of carboxylic acid (VII) is enhanced through the formation of a salt with (+)-dehydrobietylamine (DAA). After hydrolysis of the salt, the enantiomerically enriched carboxylic acid (VII) is converted to Tasimelteon through the methods described above.

Each of the above processes for the preparation of Tasimelteon suffers from the use of toxic and/or sensitive reagents often requiring specialized handling techniques such as thionyl chloride, borane and lithium aluminum hydride. As a result, it is desired to avoid the use of these reagents during commercial scale manufacturing of pharmaceuticals. Furthermore, in the above processes, chiral enrichment is often obtained through the resolution of carboxylic acid (VII) with a chiral amine, necessitating hydrolysis of the corresponding ester, formation and purification of the salt, hydrolysis of the acid, and re-activation of the acid for the subsequent coupling steps. Alternatively, resolution is obtained through the formation of diastereomeric amides of carboxylic acid (VII), which are then hydrolyzed to reform carboxylic acid (VII).
Owing to the length and complexity of the existing processes for the preparation of Tasimelteon, there remains a need for improved processes for the preparation of Tasimelteon and the intermediates used in such preparations.

Processes for the preparation of Tasimelteon and intermediates thereof


A system for processing calls with a time division multiplexing (TDM) network and routing the calls via an internet protocol network is disclosed. The system may receive a call from a call originating device. The call may then be routed to a time division multiplexing switch at which call processing is performed to determine routing information for the call. The routing information may then be received at a first VoIP media gateway, and the call may then be routed by the first VoIP media gateway. Once the call is answered, the connection between the time division multiplexing switch and the VoIP media gateway may be terminated to enable the total number of terminations to be reduced, thereby creating a more efficient system.

Currently, long distance calls may be handled by systems associated with a Time Division Multiplexing (TDM) network or may be handled by systems associated with a Voice Over Internet Protocol (VoIP) network. Frequently, these systems have services that are not present in the other system. For instance, there exists TDM call processing and functionality that is not available in the VoIP system. Nevertheless, the same call processing and functionality of the TDM network is desired for calls carried by the VoIP network.

System for processing a call with a TDM network and routing the call with an IP network


A method and system to allow wireless devices, such as wirelessly-equipped digital cameras, to gain wireless packet-data connectivity and to interact with a media management server, such as a photo server. A wireless carrier distributes multiple devices all having the same set of radio access data (e.g., mobile identification number and electronic serial number), and all having shared or unique pre-registration data. Any such device can then readily use the shared radio access data to acquire radio connectivity and can then use the pre-registration data to gain access to the media management server. The first time such a device connects with the media management server using the pre-registration data, the server will engage in a online account registration session with the device and provision the device with post-registration data that the device can thereafter use to access the online account.

1. Field of the Invention
The present invention relates to wireless communications and, more particularly, to providing RF access and packet network access to wireless devices, such as wireless digital cameras, camera phones, personal digital assistants (PDAs), scanners, voice recorders, etc.
2. Description of Related Art
a. Cellular Wireless Communications
Cellular wireless, like other forms of wireless communication, is an increasingly popular means of personal communication in the modern world. People are using cellular wireless networks for the exchange of voice and data over cellular telephones, PDAs, cellular telephone modems, camera-phones, and other devices. In principle, a user can communicate over the Internet or call anyone over the Public Switched Telephone Network (PSTN) from any place inside the coverage area of the cellular wireless network.
In a typical cellular wireless system, an area is divided geographically into a number of cell sites, each defined by a radio frequency (RF) radiation pattern from a respective base transceiver station (BTS) tower. Each BTS in a cell is in turn coupled with a base station controller (BSC). And the BSC is then coupled to or functionally integrated with a switch (e.g., a mobile switching center (MSC)) and/or gateway (e.g., a packet data serving node (PDSN)) that provides connectivity with a transport network such as the PSTN or a public or private IP network (e.g., the Internet).
When a wireless device, such as a cell phone, PDA or wirelessly-equipped personal computer, is positioned in a cell, the wireless device may communicate via an RF air interface with the BTS of the cell. A communication can thus be established between the wireless device and another entity on the transport network, via the air interface, the BTS, the BSC and the switch or gateway.
b. Acquisition of RF and Packet Network Connectivity
Traditionally, each wireless device in a cellular wireless system will have a unique Electronic Serial Number (ESN) and a unique Mobile Identification Number (MIN). The ESN, which is typically hard-coded into the device, identifies the device as a unique physical device and usually includes a manufacturer code and a manufacturer-assigned serial number. The MIN, on the other hand, is typically assigned to the device by a wireless carrier and can function as a subscriber ID. Further, each wireless device may be assigned a special authentication key (A-key), for use in validating its identity.
In typical practice, the MIN, ESN and A-key are used in combination to facilitate authentication of a wireless device when the wireless device seeks to gain access to a wireless carrier's RF resources. For instance, when a wireless device seeks to register in a wireless carrier's network or to initiate a communication via the network, the device may programmatically send into the carrier's network a message that carries (i) its MIN, (ii) its ESN and (iii) an "authentication result" that the device has computed as a predefined function of the MIN, the ESN, and its A-key, among other parameters. One or more entities in the carrier's network may then confirm that the MIN/ESN pair is not currently in use and compare the authentication result provided by the device with a network-computed authentication result, to authenticate the device. If the MIN/ESN pair is not currently in use and the authentication results match, the carrier may allow the device to access the RF network, i.e., to communicate via the RF network. Otherwise, the carrier may deny RF access.
In addition, a wireless device that is capable of engaging in packet-data communication (e.g., IP communication) may have a username and password that the device can use to gain packet network connectivity and to engage in packet-data communication. Typically, the username will be assigned by the wireless carrier and will be programmed into the wireless device. The username may take the form of a "network access identifier" (NAI), and the password may be a predefined hash based on the device's unique ESN.
When such a wireless device seeks to gain packet network connectivity, typically after the device first acquires RF connectivity, the device may programmatically send into the carrier's network a message that carries the device's username and password, among other information. An authentication server or other entity in the carrier's network may then validate the username/password (e.g., ensuring that the password is correct, and ensuring that the username is not already in use on the network) and, upon successful validation, may assign an IP address for the device to use. The device may then commence packet-data communication via the carrier's network.
c. Setting up a Wireless Device
Typically, when a user first acquires a wireless device, in order to use that device the user must first subscribe to service with a wireless carrier, and the wireless carrier will activate the user's wireless device for service. Usually, this involves assigning a MIN and A-key to the device, programming the device with the MIN and A-key, and recording the MIN and A-key in the carrier's network for use in authenticating and granting RF access to the device. Further, if the device is capable of engaging in packet-data communication, this may also involve assigning a username and password to the device, programming the device with the username and password, and recording the username and password in the carrier's network for use in authenticating and granting packet network access to the device.
This activation process can be carried out at the point of sale, such as at a retail store where the user buys the wireless device and subscribes to service. In that scenario, a sales technician may collect subscriber billing information such as name, address and credit card number, and establish an account for the device. The carrier may then assign a MIN, username and other activation data to the device and record that data in connection with the account, and the technician may program that data into the "Number Assignment Module" (NAM) block of the device for later use.
Alternatively, the activation process can be carried out over the air. In a conventional over-the-air service provisioning (OTASP) process, the user would call a customer service center, and a customer service representative would collect subscriber billing information. An entity in the carrier's network would then wirelessly request and receive from the device certain pre-configured parameters. In turn, an authentication server and the device may wirelessly communicate with each other to establish a common secure A-key and other data for use in authenticating the device. And an over-the-air function (OTAF) in the network may then wirelessly transmit other provisioning parameters, such as an assigned MIN and username for instance, to the device, which the device may then programmatically store in its NAM block for later use.
Typically, any wireless device that does not engage in voice communication but seeks to gain RF connectivity merely as a way to get onto a packet network has to be activated for service much the same way as a cell phone. Devices primarily used for packet-data communications thus have to have unique RF access data, subscribe to wireless service, and go through third-party activation to be able to use an RF network even if just for the purpose of getting onto a packet network.
Unfortunately, the above-described process of activating a wireless device requires a user to set up a cellular account with the carrier, and does not provide an efficient way to activate wireless devices used primarily for data communications. It would therefore be desirable to provide a more efficient activation mechanism for wireless devices not engaging in voice communications. Ultimately, it would be desirable to provide a better way for wireless devices engaging primarily in data communication to gain RF connectivity and to connect with and communicate over a packet network.

This patent is subject to a terminal disclaimer.

Method and system for use of shared data to gain wireless packet data connectivity