Vertical cavity light emitting sources that utilize patterned membranes as reflectors are provided. The vertical cavity light emitting sources have a stacked structure that includes an active region disposed between an upper reflector and a lower reflector. The active region, upper reflector and lower reflector can be fabricated from single or multi-layered thin films of solid states materials (“membranes”) that can be separately processed and then stacked to form a vertical cavity light emitting source.

There is a need to improve the interconnectivity between the photonics domain and the electronics domain in order to effectively integrate multi-functional photonic/electronic systems. However, the mismatch in physical scaling between photonic components and electronic components presents a significant challenge to the high density integration of photonics and silicon-compatible optoelectronics. One of the most challenging technical barriers to the development of photonics on silicon is the lack of a practical silicon-integrated light source which is (a) highly efficient; (b) ultra-compact; (c) electrically controllable; (d) CMOS process/integration compatible; and (e) reliable.
Vertical-cavity light emitting sources, including light emitting diodes and lasers could be ideal compact light sources for large-scale silicon-based photonics if they could be directly built on a silicon wafer because vertical cavity light emitting sources: (1) can be wafer-scale fabricated and probed; (2) can be fabricated in high-density 2D arrays; and (3) have low diffraction output beams for efficient coupling. However, conventional vertical-cavity light emitting source technology utilizes thick distributed-Bragg reflector (DBR) mirrors which limit the device performance and integration density.

Hybrid vertical cavity light emitting sources

Board of Regents, The University of Texas System


A semiconductor device may include a substrate and a fin shaped semiconductor region on the substrate. The fin shaped semiconductor region may include a channel region and first and second junction regions on opposite sides of the channel region. A gate electrode may be provided on the channel region of the fin shaped semiconductor region, and a stress inducing layer on the fin shaped semiconductor region.

It is known that the performance of a transistor may depend on an operation current of the transistor. Therefore, efforts have been made to provide high operation currents for transistors. In particular, strained silicon channel (SSC) techniques have been studied wherein stress is applied to a channel region.
SSC techniques may provide a strained channel layer on an upper part of a metal oxide silicon field effect transistor (MOSFET) by forming a stress inducing layer. SSC techniques have been disclosed in the article by T. Ghani et al. entitled "A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS Transistor" (IEEE in 2003).
However, even if a stress inducing layer covers a bulk type MOSFET, stress provided by the stress inducing layer may be distributed in a substrate since the body area (or thickness of the substrate) of a MOSFET is relatively large compared to the thickness of the stress inducing layer. Accordingly, it may be difficult to obtain a high mobility of carriers and there may be a limit in obtaining a high operating current of the MOSFET.

Semiconductor devices including stress inducing layers


In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.

As semiconductor device feature sizes have decreased to sizes smaller than the wavelength of light used in photolithographic processes, the diffraction of light at feature pattern edges formed on the reticle causes a loss of resolution in transferring the reticle pattern to the wafer photoresist. To increase the resolution of photolithographic pattern transfer, phase shift masks have been developed where the phase of the wavefronts of light passing through alternating portions of the reticle pattern are shifted out of phase with respect to light passing through adjacent portions to produce destructively interfering wavefronts to reduce undesired exposure of the wafer photoresist due to diffraction of light at feature edges of the reticle pattern. As a result, the contrast, and therefore transferable resolution of the reticle pattern is improved.

Method of manufacturing phase shift photo masks

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.


A lighting system is disclosed which includes a light source unit and a projection system for producing a desired light distribution pattern in a target area, especially for use in an automotive head lighting, studio and theater lighting, indoor spots with adjustable beam width or direction, architectural dynamic lighting, disco lighting and other. The lighting system is especially suitable for a light source unit having one or more Lambertian light sources, especially a plurality of LEDs. For generating a desired light distribution pattern in the target area, the light source unit may include a plurality of collimators that are configured especially such that the curved focal plane (P) of the projection system intersects with or tangentially touches the exit apertures of the collimators.

U.S. Pat. No. 6,909,554 discloses an optical system that includes an array of opto-electronic devices in the form of an array of light emitters like LEDs or an array of light detectors like CCDs, wherein the array is substantially extending along a planar plane. Further, the optical system includes an array of micro lenses and a fore optic having a non planar focal field. Each opto-electronic device is provided with one of the micro-lenses which each have a focal length and/or a separation distance between them and their respective opto-electronic device such that it compensates for the non planar focal field of the fore optic, so that light which is provided by the fore optic is reconfigured by the micro-lenses to be substantially focused along the planar plane of the array of opto-electronic devices, and vice versa.
One disadvantage of this optical system is that in case of using LEDs as light emitting opto-electronic devices, a great part of the emitted light cannot be captured by the related micro-lens but is lost. This is due to the fact, that an LED is usually a Lambertian light source having a pattern of the radiation intensity which is more or less proportional to the cosine of the angle between the observer and the centerline or surface normal in which the LED lies.
US 2007/0211473 discloses a light source especially for traffic lights and other signal heads, comprising a housing in which an LED module is positioned for emitting light through a Fresnel lens and a spreading lens to the outside of the housing, wherein an improved uniformity of the light distribution across the surface of the spreading lens shall be achieved by positioning around each LED a reflector cup having either a tilt angle such that more light is directed toward the outer perimeter of the spreading lens, or having a non symmetrical curvature or being fanned out in order to achieve the effect of the tilted reflector cup without tilting the same.

Lighting system and light source unit for such a system


Bar code scan data is corrected for spot-speed variation by processing the data to determine a spot-speed profile having non-zero acceleration within at least some of the characters of the bar code symbol being scanned, and then using the speed profile to normalize the scan data. Preferably, average spot speeds across individual characters are determined, and a speed profile is fit to these average spot speed data points in such a manner that the curve is not forced to pass through every data point. In this way, a spot-speed profile is derived that does not incorrectly attribute, to speed variation, errors due to other sources, e.g., random edge errors from printing. Preferably, the spot-speed profile consists of a plurality of straight line segments. The segments may be slightly disjoint, and each segment is from two to four characters in length, depending on the density of the bar code symbol.

This invention relates to bar code scanning.
A bar code symbol is a coded pattern of indicia comprising a series of bars and spaces, called elements, which are typically rectangular and have a variety of possible widths. A specific arrangement of elements defines a character represented according to a set of rules and definitions specified by a symbology. To encode a desired sequence of characters, groups of elements are concatenated to form the complete bar code symbol, with each character being represented by a corresponding group of elements. In some symbologies, start and stop characters are used to indicate where the bar code begins and ends. A number of different bar code symbologies exist, such as UPC/EAN, Code 39, Code 128, Codabar, and Interleaved 2 of 5.
The number of characters per inch represented by the bar code symbol is referred to as the density of the symbol. High density symbols, which have line widths of about 5 mils or less, may be used for small parts such as integrated circuits, or in symbols with high information density. Low density symbols, which have line widths greater than about 50 mil, may be used, for example, for coding packages and containers in warehouses.
In typical scanning systems, a light source, such as a laser or laser diode, produces a beam which is directed by a lens or similar optical components along a light path toward a target that includes a bar code symbol on its surface. The beam produces a spot on the target. In order to scan in a laser system, the spot is mechanically or manually moved to produce a line or series of lines across the symbol. A sensor, such as a photodetector, is positioned in the scanner. A portion of the light which is reflected off the symbol is detected by the sensor which provides an analog signal. The analog signal is converted to a pulse width modulated digital signal, in which the pulse widths correspond to the physical widths of the elements in the time domain, i.e. how long the elements were scanned.
The decoder receives the digital signal and attempts to decode the scan. If start and stop characters and the data characters between them can be decoded successfully, the decoding process is finished. Otherwise, the decoder receives a next scan and attempts to decode it. The process continues until a scan is completely decoded or until no more scans are available. The signal is decoded according to a specific symbology into a binary representation of the data encoded in the symbol.
Scanning systems are available for a variety of applications. A laser scanner may be mounted in a fixed position so that products with a bar code are moved past the scanner mechanically or manually, as in a warehouse or a supermarket. Laser scanners typically have an oscillating motor or other means for causing a laser beam spot to trace a scan line across the bar code. In some other scanner systems, the scanner is hand-held and portable. Some scanners resemble a gun, others are wands which are manually passed over the bar code.
In either fixed or portable systems, the spot speed of the scan line varies as the line is traced across a target. With a hand-held wand, the spot speed varies due to manual motion. Typically, the spot accelerates quickly then slows down. Ideally, a user would start the movement of the wand well in advance of encountering the bar code, but it is not possible to train all users in this procedure and to rely on compliance. For a scanner with an oscillating motor, the motor causes the spot speed to increase and then decrease, thus causing a profile which is generally sinusoidal. Still another cause of spot-speed variation is the orientation of the bar code. If the code is applied to a curved object, the speed of the spot crossing it can vary depending on the degree of curvature.
If a scanning system determines time domain widths of elements, i.e., how long it takes the spot to cross the elements, elements that are spatially equal will produce inconsistent time domain widths if the speed varies. Variation in spot speed may be sufficient to cause a decode failure, which is an inability to decode, or a misdecode, which is an incorrect determination. The error introduced by spot-speed variation combined with other errors, such as printing defects or ambient light, may also cause failure or misdecode, even if the error from spot speed is tolerable.
This variation in spot speed has long been appreciated. The bar codes, themselves, have typically been designed to accommodate the variation in speed. Information is encoded as relative variations in width of the bars and spaces making up the code. During decoding, the relative widths of the elements within a character are used to decode the character. Thus, while speed variation from character to character is not a significant difficulty, speed variation within a character is a problem. Such variation can, if severe, produce an inaccurate decode. E.g., a speed change of 25% from the start to the finish of a character will make bars at the end of the character appear 25% narrower than bars at the start, enough of a difference to affect the decoding.
It has been known that such variation is a source of error in decoding, but a practical solution to the problem has not been available. A difficulty perceived by the art in attempting to solve the problem is that printing errors, and other decoding errors, produce variation in element widths, and there has not heretofore been a practical way of correcting error due to speed changes.
Bar code verifiers (such as the Symbol Technologies LaserCheck II verifier), which are used to measure the quality of printed bar codes, have been designed to subtract out the effect of scan speed variation to give a better measurement of printing quality. Such verifiers compensate for spot-speed variation by fixing the bar code scanner on a stand to hold its location fixed, and placing a calibration bar code in the path of the scan. The calibration bar code has a series of elements with identical width, from which the verifier determines speed variation across the bar code. A bar code to be verified is then placed in the same exact location as the calibration bar code, and the stored speed variation is used to adjust the raw scan data produced.

Bar code scanning with correction for spot speed variation


A wild game dressing tool comprising two outwardly spaced apart hooks for field dressing a deer or the like, eliminating the need for reaching up into an animal's rib cage blindly, consequently eliminating excessive blood on the field dresser's arms and clothing, and most importantly reduces the risk of contracting lymes disease,

The present invention relates generally to the art of dressing out big game wildlife, and in particular to the art of holding the ribs of the carcass apart while cleaning out the internal organs and while hanging the carcass for cooling.
In this art it is necessary to hold the carcass apart to stabilize the carcass to keep it from rolling and hold the rib cage apart in order to remove the internal organs. This allows the field dresser to see what is needed to be done and eliminates the need for the field dresser to reach up into the rib cage blindly thus eliminating excessive blood on the field dresser's arms and clothing. This is of considerable value to the field dresser as it reduces the risk of contracting lymes disease.
Techniques, such as the use of wooden sticks found in the near by brush, etc. have been used in effectively. Also, other methods have been to use two people, with each holding a leg which is also in-effective and combersome. Often times hunters are by themselves when they are hunting and would not have another person to help.
The present invention represents a major advance in the art of field dressing big game animals. In the past, hunters have not been able to field dress an animal without the help of another, or by use of archaic methods such as near by sticks, or by simply getting messy with blood from reaching up into an animal's internal rib cavity to remove the internal organs.
A disclosure document has been filed in the U.S. Patent Office under receipt number 277801.


A source-address independent, multi-path routing method for use in a communication network is disclosed. A network node uses an information packet's destination address to determine a plurality of neighbors it has a proportional likelihood to forward that packet to, such that packets can be sent over multiple paths to a destination node without undesirable looping. Multiple-neighbor proportional forwarding routing tables are determined by computing a directed graph of multiple optimal paths to each destination node. Optimal paths and forwarding proportions are based on link capacities. The multi-path routing method provides maximized throughput, reduced congestion and superior load balancing over single-path routing. Source-address independence also overcomes a major problem of more traditional source-address dependent multi-path routing methods. The source-address independent, multi-path routing method can be implemented in mixed networks where some nodes do not implement the method. Data structures and methods for determining the optimal paths and parameters are provided.

FIG. 1 (Prior Art) shows a strongly connected directed graph 100 representing a network of routers and allowed links between adjacent routers for an information packet directed to network router H 108. The directed graph 100 illustrates the use of Source-Independent Single-Path routing according to traditional routing schemes like minimum hops or shortest path. Oval shapes represent network routers, also referred to as hosts or "nodes", that forward information packets from a source device, such as a home computer connected to a node, to a destination device, such as another home computer connected to a node. Shown are node A 101, node B 102, node C 103, node D 104, node E 105, node F 106, node G 107 and node H 108. Also shown are an example information packet source device 109 connected to node E 105 and an example information packet destination device 110 connected to node H 108.
Where an information packet originates from a given source device, it must always first pass through the node to which the source device is connected. This first node will be referred to here as the source router. Where the information packet is destined for a given destination device, the last node the information packet passes through is the node to which the destination device is connected. This last node will be referred to here as the destination router. The destination router can be determined from the packet's destination address using well known network topology protocols. Accordingly, where an information packet originates from source device 109 destined for destination device 110, the source node is node E 105, and the destination node is node H 108. An information packet typically includes destination data from which can be determined the destination device and destination node, as well as source data from which can be determined the source device and source node.
In the directed graph 100, darkened arrows indicate allowed links between nodes for forwarding an information packet to destination node H 108. For any given node which is to forward an information packet to destination node H 108, the information packet will always be forwarded to the same next adjacent node. The next adjacent node forwarded to is also referred to as a "next hop".
Arrow 111 indicates the link by which node A 101 forwards the information packet to node B 102. Arrow 112 indicates the link by which node B 102 forwards the information packet to node F 106. Arrow 113 indicates the link by which node C 103 forwards the information packet to node G 107. Arrow 114 indicates the link by which node D 104 forwards the information packet to node E 105. Arrow 115 indicates the link by which node E 105 forwards the information packet to node F 106. Arrow 116 indicates the link by which node F 106 forwards the information packet to node H 108. Arrow 117 indicates the link by which node G 107 forwards the information packet to node H 108. Non-darkened arrows illustrate links which are not allowed when the destination node is node H 108. A directed graph of paths to a different destination node would have a different set of allowed and non-allowed links.
Thus, an information packet originating at source device 109 and destined for destination device 110 will first pass to node E 105. Node E 105 will always forward the information packet to next hop node F 106 via link 115. Node F 106 will always forward the information packet to next hop node H 108 via link 116. Node H 108 (the destination node) will then forward the information packet to destination device 110.
As can be seen from the darkened link arrows, there is always a single route from a given node to a given destination node when using this Single-Path routing method. Because the route is determined based on the destination of the information packet, and not determined based on the source of the information packet, the method is referred to as Source-Independent Single-Path routing.
FIG. 2 (Prior Art) is a simplified view of an example node E 105 implementing Source-Independent Single-Path routing. Node E 105 includes a processor 200 and a memory 201. Processor 200 and memory 201 communicate via buses 202 and 203. Memory 201 stores network topology information 204 according to a well-known protocol such as Open Shortest Path First (OSPF) or Intermediate System to Intermediate System (ISIS). An algorithm 205 running on the processor 200 uses the network topology information 204 to determine which adjacent node should be the next hop an information packet takes from node E 105 given the destination node of the information packet. These destination-dependent next hops are stored in memory 201 as the routing table 206 for node E 105.
The algorithm 205 that builds the routing table uses a traditional routing scheme such as minimum hops or shortest path. These traditional routing schemes rely on forwarding a given information packet to a single neighboring router based on its destination for several reasons.
First, the cost of each link between neighboring routers is constant. This link cost is also known as a link metric. Link costs can be based on a link delay or a link transmission time. In the case of hop counting, every link cost is set to be equal. When the link costs change for any reason, so do the routing tables that determine forwarding neighbors. In the algorithm 205 that builds the routing table 206, the cost of a path between the forwarding node 105 and a destination node is determined by adding the costs of the intervening path links. And, the dynamic programming principle of optimality applies, meaning that all sub-paths of a path between the forwarding node 105 and a destination router must be optimal. Determining the cost of a path by adding the costs of the path links is known as the Link Metric Model.
Additionally, it is simple to avoid creating undesirable looping paths or "directed cycles" using Single-Path routing methods. FIG. 3 (Prior Art) is a an expanded view of simplified routing table 206 for node E 105. Row 300 indicates that the next hop when an information packet is destined for destination router H 108 is node F 106. Row 301 indicates that the next hop node when an information packet is destined for destination router F 106 is node F 106.
FIG. 4 (Prior Art) is a simplified view of an example routing table 400 for node F 106, shown for comparison with the example routing table 206 for adjacent node E 105, illustrating the lack of looping, also known as a "directed cycle", between node E 105 and node F 106. Row 401 indicates that the next hop node when an information packet is destined for destination router H 108 is node H 108. Row 402 indicates that the destination router has been reached when an information packet is destined for destination router F 106. By comparing routing table rows 300 and 301 with routing table rows 401 and 402, it is seen that for instances when the next hop node from node E 105 is node F 106, the next hop node from node F 106 is never node E 105.
In this way, routing tables for adjacent nodes are constructed such that information packets do not follow directed cycles in the Single-Path routing methods. And, because routing table next hops in Single-Path routing methods depend only on the destination of the information packet, and not the source, Single-Path routing methods can be referred to as Source-Independent Single-Path routing. However, problems inherent in Source-Independent Single-Path include over-utilizing, and therefore congesting, the links along optimal paths. Conversely, other links can remain largely underutilized.
In contrast, Multi-Path routing methods can utilize more available links and better avoid link congestion. Known Multi-Path routing methods calculate a set of "best" disjoint paths for an information packet from a particular source to a particular destination node and channel traffic between those two nodes along those paths, in inverse proportion to their costs. Disjoint paths do not share the same set of nodes or links. In a network, this has to be done for every possible pair of source and destination nodes. FIG. 5 (Prior Art) is a directed graph 500 of the network of routers of FIG. 1 (Prior Art) and links between adjacent routers illustrating the use of Source-Dependent Multi-Path routing.
Darkened arrows in the directed graph 500 of a network indicate allowed links between nodes for forwarding an information packet according to Multi-Path routing when the source node is node A 501 and the destination node is node H 508. A Multi-Path routing method would, for example, use not only the path from node A 501 to node B 502 via link 511, then from node B 502 to node F 506 via link 512, and then from node F 506 to node H 508 via link 514, but also the disjoint path from node A 501 to node C 503 via link 517, then from node C 503 to node G 507 via link 513, and then from node G 507 to node H 508 via link 515 to transport packets from source node A to destination node H. Non-darkened arrows illustrate links which are not allowed when the source node is node A 501 and the destination node is node H 508.
Because routing in known methods of Multi-Path routing requires consideration of the source of the information packet in order to prevent paths with directed cycles, known Multi-Path routing methods can be referred to as Source-Dependent Multi-Path routing. As can be seen from the darkened link arrows, additional paths to the destination router are available when using Source-Dependent Multi-Path routing rather than Source-Independent Single-Path routing method. Directed cycles are prevented because routing tables under Source-Dependent Multi-Path routing methods refer to both the source and the destination of an information packet to determine the next hop.
However, in a network with thousands of nodes, Source-Dependent Multi-Path routing presents at least two obstacles. Calculating a set of best disjoint paths from every possible source node to every possible destination node can be computationally intractable. Further, the memory requirements for storing a Source-Dependent Multi-Path routing table can be impractical.
FIG. 6 (Prior Art) shows a portion of a simplified Source-Dependent Multi-Path routing table 600 for node E 505 of FIG. 5 (Prior Art). The source-dependent entries cause the routing table 600 to balloon in size, even in our small example network of only eight routers. In a real network of thousands of routers and hundreds of thousands of destination addresses, the Source-Dependent Multi-Path routing table can approach terabyte size.


A method for processing a ceramic powder suspension includes providing a dispersant having the following structure:

1. Field of Invention
The present invention relates to a method for preparing a ceramic powder suspension. More particularly, the present invention relates to a method for processing a ceramic powder suspension in which an amphoteric copolymer is provided and used as a dispersant to disperse powder and stabilize the resulting the suspension.
2. Description of Related Art
Fine ceramics refer to ceramic materials that use highly refined powder ingredients and are precisely processed to provide the particular microstructure and exceptional functions. Functionally, these materials are more thermal resistant, more durable, etch-resisted than the conventional ceramic materials. Further, they also comprise optical, electrical and magnetic properties. The fine ceramics are thus widely used and is becoming a significant industrial material in the future.
As the particle size of ceramic powder reduces from a micrometer level to a sub-micron level or even to a nanometer level, particle agglomeration in a suspension becomes a serious issue. An effective dispersing agent thereby plays an important role in the processing of ceramic powder. For a barium titanate water based slurry, the current industry often uses PMAAN(Darvan ® C) as a dispersing agent. The chemical name of PMAAN (Darvan ® C) is ammonium polymethacrylate, which can provide a certain degree of dispersing effect. However, there is still room for improvement. When PMAAN is used as a dispersing agent for a barium titanate slurry, barium titanate in water reacts with hydrogen ions to dissociate barium ions, and the physicochemical property at the surface of barium titanate becomes similar to that of titanium dioxide. The dissociated barium ions are re-absorbed onto the surface of the powder. The ratio of barium to titanium of the powder not only changes, the thickness of a Ba-depleted, TiO2-rich surface layer of the powder also becomes greater due to the dissolution of the barium ions. The surface structure is thereby less dense and an abnormal grain growth is resulted during sintering. The quality of the product is adversely affected.

Method for processing ceramic powder suspension

Abstract: wherein R1 is an H+ ion, an Na+ ion, an NH4+ ion or other cationic group; R2 is an H+ ion, an Na+ ion. an NH4+ ion or other cationic group; m is an integer from 10 to 5000 ; and n is an integer from 10 to 3000 . The dispersant is dissolved in a solvent. Ceramic powder is further added into the solvent with the dispersant.


A data receiving device is provided enabling a reduction in the time required for extracting a partial band signal, and capable of being easily made in a simple structure as an LSI device without requiring a plurality of analog circuits having the same characteristics. The data receiving device includes: a first sampler for sampling an in-phase signal I(t) at every predetermined sampling period and outputting the sampled in-phase signal; a second sampler for sampling a quadrature signal at every predetermined sampling period and outputting the sampled quadrature signal; a partial band extracting section structured by a complex filter for extracting partial band signals IBr, QBr from frequency components included in the sampled in-phase signal and the sampled quadrature signal; and first and second delay detection operating sections for performing a delay detecting process based on the partial band signals and outputting detection signals.

1. Field of the Invention
The present invention relates to data receiving devices for demodulating a modulated signal and, more specifically, to a data receiving device for obtaining a detection signal from a phase-modulated signal through digital signal processing.
2. Description of the Background Art
Conventionally, devices for extracting at least a partial band signal from a received modulated signal for demodulation have been known. Examples of such devices include a data transmitting and receiving device disclosed in Japanese Patent No. 3161146 and a device disclosed in "A Wireless Modem using SR-chirp Spread Spectrum Scheme", Technical Report of IEICE (The Institute of Electronics, Information and Communication Engineers), RCS95-102.
FIG. 25 is an illustration showing the configuration of a data receiving device disclosed in Japanese Patent No. 3161146. In FIG. 25, the data receiving device includes a frequency mixer 1301, a band-pass filter (denoted as BPF in the drawing) 1302, a local oscillator 1303, a reception state determining section 1304, a delay unit 1305, a multiplier 1306, a low-pass filter (denoted as LPF in the drawing) 1307, and a decoder 1308.
The local oscillator 1303 outputs a local oscillation signal whose frequency can be changed at every interval of an integral multiple of a symbol frequency of the data to be received. The frequency mixer 1301 converts an input spread spectrum signal r(t) into a frequency band representing a difference in frequency band between the input spread spectrum signal r(t) and the local oscillation signal from the local oscillator 1303. Here, it is assumed that this spread spectrum signal r(t) is a phase-modulated signal which can be demodulated by extracting at least one partial band from the signal's frequency band.
The band-pass filter 1302 extracts and then outputs an intermediate signal b(t), which is part of frequency components of the spread spectrum signal r(t) frequency-converted by the frequency mixer 1301.
FIGS. 26A and 26B are illustrations showing signal spectra observed in the data receiving device illustrated in FIG. 25. FIG. 26A is an illustration showing an outline of spectra of the received spread spectrum signal r(t). The local oscillation signal output from the local oscillator 1303 can have three frequencies. Each frequency of the local oscillation signal is an integral multiple of the symbol frequency of the data signal to be received. The center frequency of the local oscillation signal is any one of center frequencies of three partial bands denoted as B1, B2, and B3, respectively.
FIG. 26B is an illustration showing an outline of a spectrum of the intermediate signal b(t). The intermediate signal b(t) is any one of partial bands of B1, B2, and B3 that is obtained by frequency-converting the input spread spectrum signal r(t) and then band-limiting the frequency-converted signal.
The reception state determining section 1304 outputs a band switching signal in accordance with a data reception state so as to switch the frequency of the local oscillation signal output from the local oscillator 1303. Based on the band switching signal output from the reception state determining section 1304, the local oscillator 1303 switches the frequency of the local oscillation signal for output. With this, any one of the partial bands of B1, B2, and B3 is selected. Therefore, the band-pass filter 1302 outputs the intermediate signal b(t) corresponding to the partial band after selection.
The multiplier 1306 multiplies the intermediate signal b(t) by an intermediate signal b(t-Ts) obtained by the delay unit 1305 delaying the intermediate signal b(t) by a symbol period Ts, and then supplies the resultant signal to the low-pass filter 1307. The low-pass filter 1307 performs a low-pass filtering process on the received signal, and then outputs a detection signal c(t). The decoder 1308 decides the polarity of the detection signal c(t), and then outputs a data signal dat(t).
FIG. 27 is a block diagram illustrating the general configuration of a receiving unit in a wireless modem disclosed in "A Wireless Modem using SR-chirp Spread Spectrum Scheme", Technical Report of IEICE, RCS95-102. In FIG. 27, the receiving unit includes a splitter 1501, a first frequency mixer 1502, a second frequency mixer 1503, a first local oscillator 1504, a second local oscillator 1505, a first band-pass filter 1506, a second band-pass filter 1507, a first gain controller (denoted as AGC1 in the drawing) 1508, a second gain controller (denoted as AGC2 in the drawing) 1509, a first quadrature detector 1510, a second quadrature detector 1511, and a baseband signal processing section 1512.
The receiving unit receives a spread spectrum signal as an input signal, extracts two partial bands simultaneously, and then outputs the received data in accordance with the reception state. This receiving unit has two receiving systems identical in structure to each other, one starting from the first frequency mixer 1502 to the baseband signal processing section 1512 and the other starting from the second frequency mixer 1503 to the baseband signal processing section 1512. The operation of the receiving unit illustrated in FIG. 27 is described below.
The splitter 1501 splits a received spread spectrum signal r(t) into two signals, one being supplied to the first frequency mixer 1502 and the other being supplied to the second frequency mixer 1503. The first local oscillator 1504 and the second local oscillator 1505 output local oscillation signals whose center frequencies are of bands of different band characteristics. The local oscillation signal output from the local oscillator 1504 is supplied to the frequency mixer 1502. The local oscillation signal output from the local oscillator 1505 is supplied to the frequency mixer 1503.
The frequency mixer 1502 converts the split spread spectrum signal r(t) into a signal of a frequency band representing a difference between the split spread spectrum signal and the local oscillation signal output from the local oscillator 1504, and then supplies the resultant signal to the first band-pass filter 1506. The first band-pass filter 1506 extracts a partial signal from the received signal for output to the first gain controller 1508 as a partial band signal b1(t). The first gain controller 1508 controls the amplitude of the partial band signal b1(t) for output to the first quadrature detector 1510. The first quadrature detector 1510 outputs an in-phase component I1(t) and a quadrature component Q1(t) of a first complex baseband signal output from the first gain controller 1508.
The other receiving system starting from the second frequency mixer 1503 operates in the same manner as described above. As a result, the second quadrature detector 1511 outputs an in-phase component I2(t) and a quadrature component Q2(t) of a second complex baseband signal output from the second gain controller 1509. The baseband signal processing section 1512 performs a delay detecting process on a set of I1(t) and Q1(t) of the first complex baseband signal and a set of I2(t) and Q2(t) of the second complex baseband signal. The baseband signal processing section 1512 then outputs the received data of one of the receiving systems which is determined as having less errors based on, for example, the reception state of these receiving systems. Alternatively, the receiving system can be selected based on the reception level for outputting the received data.
FIG. 28 is an illustration showing one example of a structure of a delay detector provided in the baseband signal processing section 1512. In the baseband signal processing section 1512, one delay detector is provided correspondingly to each of the quadrature detectors. In FIG. 28, only one delay detector is representatively illustrated. In FIG. 28, the delay detector includes a first sampler 1101, a second sampler 1102, a delay detection operating section 1103, a first post-detection filter 1104, and a second post-detection filter 1105.
The first sampler 1101 samples the in-phase component i(t) of the complex baseband signal (I1(t) or I2(t) in FIG. 27) to output an in-phase component data string I(nT) of the sampled complex baseband signal to the delay detection operating section 1103. Here, n is an integer (n= . . . −1, 0, 1, . . . ), and T is a sampling period. Similarly, the second sampler 1102 samples the quadrature component q(t) of the complex baseband signal (Q1(t) or Q2(t) in FIG. 22) to output a quadrature component data string Q(nT) of the sampled complex baseband signal to the delay detection operating section 1103.
FIG. 29 is an illustration showing the structure of the delay detection operating section 1103. In FIG. 29, the delay detection operating section 1103 includes a first selector 1201, a second selector 1202, a delay unit 1203, a sign changer 1204, a first multiplier 1205, and a second multiplier 1206. The first selector 1201 alternately selects the data strings I(nT) and Q(nT) for each sampling period, and then outputs the selected data string as S1(nT). The second selector 1202 alternately selects a data string −I(nT) output from the sign changer 1204 by reversing the sign of the data string I(nT) and the data string Q(nT) for each sampling frequency T, and then outputs the selected data string as S2(nT).
It is set so that, upon a selection of I(nT) by the first selector 1201, the second selector 1202 always selects Q(nT). It is also set so that, upon a selection of Q(nT) by the first selector 1201, the second selector 1202 always selects −I(nT).
The delay unit 1203 receives the data string S1(nT) as an input signal, and then outputs a signal by delaying S1(nT) by one symbol time length kT. Here, k represents the number of samplings per symbol. With this, the first multiplier 1205 alternately outputs, for each sampling period T, I(nT)I{(n−k)T}, which is the product of the in-phase component data string of the sampled complex baseband signal and the delayed in-phase component data string thereof, and Q(nT)Q{(n−k)T}, which is the product of the quadrature component data string of the sampled complex baseband signal and the delayed quadrature component data string thereof. The output from the first multiplier 1205 is referred to as a signal F1(nT). The second multiplier 1206 alternately outputs, for each sampling period T, I{(n−k)T}Q(nT), which is the product of the delayed in-phase component data string of the sampled complex baseband signal and the quadrature component data string thereof, and −I(nT)Q{(n−k)T}, which is the product of the sign-changed in-phase component data string of the sampled complex baseband signal and the delayed quadrature component data string thereof. The output from the second multiplier 1206 is referred to as a signal F2(nT).
The first post-detection filter 1104 performs a low-pass filtering process on the received signal F1(nT) to output a signal D1(nT), which is equivalent to a signal obtained by adding I(nT)I{(n−k)T} and Q(nT)Q{(n−k)T}. Similarly, the second post-detection filter 1105 performs a low-pass filtering process on the received signal F2(nT) to output a signal D2(nT), which is equivalent to a signal obtained by adding I{(n−k)T}Q(nT) and −I(nT)Q{(n−k)T}.
D1(nT) corresponds to an in-phase component of the multiplication result obtained by multiplying a complex number of A(nT)=I(nT)+jQ(nT) and a complex conjugate of A{(n−k)T}, which is delayed from A(nT) by one symbol time length kT. D2(nT) corresponds to a quadrature component of the above-stated multiplication result. Here, I(nT) represents an in-phase component, Q(nT) represents a quadrature component, and j represents an imaginary unit. Therefore, a phase represented by D1(nT) and D2(nT) shows a difference in phase between A(nT) and A{(n−k)T}. For this reason, by using D1(nT) and D2(nT), the received data can be demodulated through a decision circuit (not shown), for example.
As such, in order to obtain a plurality of demodulating signals for a plurality of partial band signals, the receiving unit illustrated in FIG. 27 obtains different complex baseband signals from partial band signals of different frequency band characteristics, and then performs a delay detection operation on each complex baseband to obtain the demodulating signals. Then, based on the reception state, the receiving unit outputs the received data.
In FIG. 27, a case is illustrated in which the number of partial bands to be extracted is two. If three or more partial bands are to be extracted, receiving systems are required as many as the number of partial bands to be extracted, the receiving systems each having the same structure as described above starting from a frequency mixer to a baseband signal processing section.
However, if the data transmitting and receiving device disclosed in Japanese Patent No. 3161146 is used to extract different partial band signals, the frequency of the local oscillator has to be changed. The changing operation disadvantageously takes a certain time.
On the other hand, in the receiving unit disclosed in "A Wireless Modem using SR-chirp Spread Spectrum Scheme", Technical Report of IEICE, RCS95-102, a plurality of local oscillators are provided in advance. Therefore, the operation of switching the partial band signal to be extracted does not take a long time. However, the receiving unit requires a plurality of analog receiving systems having the same structure starting from a frequency mixer and a baseband signal processing section. In order to equalize the characteristics of these receiving systems, analog circuits included in these systems are required to have approximately the same characteristics. Moreover, the requirement of a plurality of receiving systems causes an increase in hardware structure.
Still further, the hardware structure of the delay detection operating section 1103 in the baseband signal processing section 1512 (refer to FIG. 29) has some disadvantages. For example, signals undesired for demodulation have to be eliminated in advance by using an analog circuit from the complex baseband signal, which is an input signal of the delay detection operating section 1103.
Also, the delay detection operating section 1103 requires one sign changer, two selectors, one delay unit, and two multipliers. Moreover, the delay detector requires two post-detection filters. Therefore, the size of gates is large for LSI, for example, which is not suitable for reduction in size and weight.

Matsushita Electric Industrial Co., Ltd.


Component mounting system 1 includes electronic component mounting device 10, control device 100, image processing device 110, memory device 115, and display 120. Electronic component mounting device 10 includes mounting head 26, supply device 28, and component camera 90, and is configured to use mounting head 26 to pick up an electronic component supplied by supply device 28 and to image the held electronic component using component camera 90. When saving the captured image data on memory device 115, it is determined whether a condition for using a first format is satisfied (S1, S2). When the conditions for using the first format are satisfied (S2: yes), the captured image data is saved on memory device 115 in the first format that is a lossless compression format (S5). When conditions for using the first format are not satisfied (S2: no), the captured image data is saved on memory device 115 in the second format, which is a lossy compression format.

Conventionally, it is typical to configure a board production line by using a conveyance device to connect various pieces of equipment used to produce a board mounted with many components, the equipment including a screen printer, a component mounting device, a reflow device, and so on. With component mounting devices and the like used to configure a board production line, a component is picked up by a pickup nozzle and mounted at a specified position on the board.
With a component mounting system including a component mounting device, to mount components with high accuracy at specified positions on the board, image processing is performed on image data captured of the component picked up by the pickup nozzle and a determination made about the position of the component and whether the component is good. Because such image data is used as valuable material to adjust mounting work and work processes including the mounting work, the data is saved on a memory device or the like.
Devices such as that disclosed in patent literature 1 related to such technology are known. An inspection machine disclosed in patent literature 1 includes an inspection machine main body for inspecting a board on which electronic components are mounted, and is configured to acquire, from among the inspection result data obtained by inspection by the inspection machine main body, defective board data of a board determined to include a defective portion. The inspection machine extracts, from the defective board data, image data of the entire board captured by the camera and image data of a defective portion captured by the camera, performs high-level compression on the image data of the entire board and saves that data on a memory device, and performs low-level compression (including no compression) on the image data of the defective portion and saves that data on the memory device.

Component mounting device and component mounting system


A reversibly slide-swingable balance-training apparatus includes a base unit, a transmission unit mounted in the base unit and providing a movement-constraining eccentric shaft and a power-maintaining rotary member for rotating the movement-constraining eccentric shaft continuously, one or a pair of linkages each having a first link pivotally connected to the movement-constraining eccentric shaft of the transmission unit, a second link pivotally coupled between the first link and the base unit and a third link pivotally connected to the second link, and a platform pivotally connected to the first link and third link of each linkage. Subject to the oscillation motion of the links of the linkage counteracting the postures of the user and the functioning of the movement-constraining eccentric shaft and the continuation of the energy of the power-maintaining rotary member, the platform is reversibly slide-swinging for best balance training.

1. Field of the Invention
The present invention relates to physical training apparatus and more particularly, to a balance training platform, which is reversibly slide-swingable subject to user's control.
2. Description of the Related Art
The structural designs of conventional balance-training equipments commonly emphasize the functioning of balance training without combining the functioning of continuous muscle training, i.e., conventional balance-training equipments cannot be controlled to provide a continuously reciprocating motion subject to the user's posture and energy. In consequence, conventional balance-training equipments may be unable to achieve the expected training effects.
Therefore, there is a room for improvement on conventional balance-training equipments. In view of the aforesaid situation, the invention has been created.

Reversibly slide-swingable balance-training apparatus


A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes word lines and source lines that connect together control gates and source regions from memory cells contained in row within the array. The strap regions include word line strap cells through which the word lines traverse, wherein the word lines completely traverse across the strap regions, and source line strap cells in which the source lines terminate without completely traversing across the strap region. The control gate polysilicon is formed over the substrate, and protected by a layer of protective material, before the formation of other polysilicon elements associated with the memory array, to ensure the proper remove of residual polysilicon stringers.

The present invention relates to a method of forming strap regions to make electrical contacts with memory cells in an array of semiconductor non-volatile memory cells, and more particularly, in the preferred embodiment, to an array of floating gate memory cells of the split gate type. The present invention also relates to a method of forming a logic or peripheral region on the same semiconductor substrate adjacent the memory cell array, where the structure has a simplified topography, box shaped word poly""s, and logic polysilicon elements formed separately from those of the memory cells.
Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, self alignment minimizes the number of masking steps necessary to form memory cell structures, and enhances the ability to scale such structures down to smaller dimensions.
In the manufacture of memory cell arrays, it is also known to form cell elements that extend across the entire array of memory cells. For example, with an array having interlaced columns of isolation and active regions, with a plurality of memory cells in each active region, memory cell elements such as control gates, source regions, drain regions etc. can be formed to continuously extend across an entire row or column of memory cells. In order to ensure an equalized voltage on such elements for all the memory cells in the target row/column, strap regions have been used to provide multiple electrical connections along the length of continuously formed memory cell elements, so that uniform voltages are applied to all the memory cells in the affected row/column.
FIG. 1 illustrates a known strap region design. Strap region 1 is formed along side a memory cell array 2. The memory cell array 2 includes columns of active regions 3 interlaced with columns of isolation regions 4. Rows of memory cell pairs 5 are formed with word lines 6 and source lines 7 extending along the memory cell rows, with each pair of memory cells having two word lines 6 and sharing a single source line 7. (Those of skill in the art will recognize that the term source and drain may be interchanged. Further, the word line is connected to the control gate of the floating gate memory cell. Thus, the term control gate or control gate line may also be used interchangeably with the term word line). Typically, the word line and the source lines are made of polysilicon or polysilicide or salicide material. Thus, pure metal lines are used to strap these lines. Strap cells 8 are formed on the control gates 6 and source lines 7 as they traverse the strap region 1. Electrical contacts 9a and 9b are then formed onto the control gate (word) lines 6 and source lines 7 respectively by metal lines (not shown) traversing in the word line direction positioned above the array shown in FIG. 1 and electrically insulated therefrom for supplying the desired voltages to the various rows of control gates 6 and source lines 7.
Ideally, for larger memory arrays, a plurality of strap regions are interlaced within the memory cell array (e.g. one strap region for every 128 cells in the word line direction). Preferably, the strap regions are formed simultaneously with the process steps used to make the memory cell array.
As device geometries get smaller, it is increasingly difficult to reliably form electrical connections to the strap regions 8. The word lines 6 are very close to the source lines 7, and get even closer with smaller device geometries. As the distance between the control gate lines 6 and source line 7 shrinks, it becomes more difficult to form contacts 9a and 9b properly. For example, just a small shift of one of the control gate line 6 contacts toward an adjacent source line 7 would result in the contact being formed over both a word line 6 and a source line 7, thus shorting the two together. Further, there is simply no room to enlarge and separate the strap cells to increase the tolerance of the contact formation steps.
One or more logic or peripheral regions are formed adjacent to the memory cell array on the same silicon substrate. Logic devices (i.e. MOS FET""s, etc.) are formed in these regions to operate the memory cell array or perform logic functions related to the memory cell array. In order to form such logic devices along side the memory cell array, the topography of the resulting structure can be complex, resulting in the formation of unwanted layers and spacers that are difficult to remove once the structure formation is complete. Further, certain elements of the logic devices and memory cells are often formed with the same processing steps, thus coupling the formation of these elements together. This can make it difficult to optimize elements of the logic devices without adversely affecting elements of the memory cells, and vice versa.
Thus, there is a need for a strap cell design, and a manufacturing method thereof, that minimizes the risk of shorting source lines 7 and word lines 6 together during the formation of the strap cells, and/or during the formation of electrical contacts connected thereto. There is also a need to form such strap cells using the same processing steps that are used to form the memory cells in the active regions. Further, there is a need to form a logic/peripheral region adjacent the memory cell array where the structure has a simplified topography, box shaped word line poly""s, and logic poly""s formed separately from those in the memory cells.
The present invention provides a memory cell array with a strap region that minimizes the risk of shorting the source and word lines together, maximizes the spacing of contacts in the strap region to enable further scaling of device geometries, and provides for logic devices formed in a decoupled manner and in a manner such that the structure has a simplified topography.
The method of the present invention includes the steps of forming a plurality of memory cells in a memory portion of a semiconductor substrate, forming a layer of protective material over control gates of the memory cells, forming a plurality of logic devices that includes forming residual conductive material on the layer of protective material, and removing the residual conductive material. The formation of each of the memory cells includes the steps of forming a floating gate of conductive material disposed over and insulated from the memory portion of the substrate, and forming a control gate of conductive material disposed over and insulated from the memory portion of the substrate. The layer of protective material is formed over the control gates. The plurality of logic devices are formed in a peripheral region of the semiconductor substrate after the formation of the protective material layer. The formation of each of the logic devices includes the step of forming a block of conductive material disposed over and insulated from the peripheral region of the substrate. The formation of the blocks of conductive material includes the formation of the residual conductive material on the layer of protective material. The residual conductive material is removed without removing the conductive material of the control gates.
Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.

Method of forming a semiconductor array of floating gate memory cells and strap regions, and a memory array and strap regions made thereby


A system is provided an enzyme donor (“ED”) fused a surrogate of a mammalian protein of interest, where the fusion protein has the function of the natural protein. A vector is provided comprising a regulatory region functional in a mammalian host cell, a sequence encoding the ED joined to a multiple cloning site, an enzyme acceptor (“EA”) protein or enzyme acceptor sequence encoding such protein, and substrate for the enzyme formed by ED and EA.

1. Field of the Invention
The invention relates generally to the cellular monitoring of protein expression and processing.
2. Background Information
The elucidation of the human genome and that of other species has greatly accelerated with the interest in proteomics, that is, the study of naturally occurring proteins and their intra- and extracellular interactions and activities. The ability to determine the status of a protein in a cell has far ranging opportunities in understanding the intracellular pathways, the intracellular movement of proteins into different compartments, the regulation of transcription and expression, the regulation of protein content and protein modification, and the like. Not only will this provide greater insight into how a cell operates, but it also allows for the determination of when a cell is aberrant or diseased. In addition, one can determine the effect of changes in the environment of the cell on the cellular function, as evidenced by changes in protein profiles, modification of proteins and transport of proteins.
Various approaches have been used to study protein-protein interactions, particularly using yeast as a host. While this can provide information concerning whether two proteins will interact, it gives no information about what happens in a native cell. The use of yeast as a host may also provide information about compounds that interfere with the interaction, but in an environment substantially different from the mammalian natural environment where the interaction may occur.
Other techniques have involved tagging a protein with a peptide fluorescer, e.g., green fluorescent protein, where degradation of the fusion protein can be followed by the loss of the fluorescence. This has many disadvantages in requiring a very large tag that may interfere with the folding of the native protein, its binding to other proteins, its susceptibility to degradation and its overall regulatory activity.
In studying the effect of drugs, both as to efficacy and differences in individual responses, it would be helpful to understand the differences in the individual hosts that result in the different responses. In understanding diseased states, it would be advantageous to be able to compare the changes in protein activity as a result of the cellular diseased state. By providing the capability to monitor changes in one or more proteins, therapeutic, diagnostic and scientific information can be developed.

This patent is subject to a terminal disclaimer.

Genetic construct intracellular monitoring system


An efficient virus detection, malware detection, and packet filtering system in a mobile device by providing optimized hash functions from a server to a mobile device that reduce hash collisions during the virus detection, malware detection, and packet filtering in a system-on-chip configuration.

1. Field
Methods and apparatuses consistent with exemplary embodiments relate to an anti-malware device, a server, and a method of matching malware patterns, and more particularly, to an anti-malware device, a server, and a method of matching malware patterns capable of minimizing hash collisions in virus pattern matching.
2. Description of the Related Art
Malware is software designed to harm a computer system, such as computer viruses, Trojan horses, malicious codes, and the like. Attention is needed for malware since undesired software is installed and a system can be hijacked only by clicking a link or an image of a famous search page, unlike a conventional concept that an attached file is opened or software is downloaded and installed.
Less emphasis is placed on an operating system and a file system than on a computer, and importance of used data is relatively low, and thus mobile viruses on a wireless communication system are not greatly recognized up to now.
However, as hardware of a mobile terminal becomes high-ranking, and application programs executed therein become various and complex, it is highly possible malware that has attacked a computer may also cause a serious damage to the mobile terminal. In particular, as a wireless mobile Internet service such as WiBro tends to spread, mobile malware that attacks vulnerabilities of a service and a portable terminal application program such as Bluetooth, a multimedia messaging system (MMS), etc. appears, in addition to malware that attacks a vulnerability of a computer application program. These various mobile malware may cause serious damages of inducing a malfunction of a portable terminal, deleting data, or leaking out user private information.

Anti-malware device, server, and method of matching malware patterns


An apparatus and method for enhancing data integrity during router recovery using dual-homed host configuration are disclosed. A process of routing resumption, in one embodiment, is able to recover or reset a network element (“NE”) such as a primary router from system failure. A first link configured to transmit data packets between the NE and a network device is reestablished. Upon reestablishing a second link configured to transmit data packets between the NE and other NEs, a network discovery process utilizing network reachability protocol is initiated to identify routing paths associated with the NE. A routing table in the NE is updated in accordance with the routing paths. A ready message is issued from the NE to the network device when the routing table is at least partially completed.

A high-speed network environment typically includes network devices such as routers and bridges used for facilitating delivery of information packets and/or data traffic from source devices to destination devices. Information pertaining to the transfer of packet(s) through the network is usually embedded within the packet itself. Each packet traveling through one or more communications networks such as Internet and/or Ethernet can typically be handled independently from other packets in a packet stream or traffic. For example, each router which may include routing, switching, and/or bridging engines processes incoming packets and determines where the packet(s) should be forwarded.
A problem associated with a high-speed computing network is data (or packet) loss due to data connection(s) (or data link) and/or device failure. For example, when data packets are sent to a recipient, the recipient router may drop the data packets because the router is not ready to process and route the data packets. As such, data loss can occur when the link and router are not fully functional at the same time.

Method and apparatus for improving data integrity during a router recovery process