A thermostat control for use in conjunction with a boat dock de-icer, wherein the thermostat control includes an electrical outlet, a plug for connecting the control to a source of electrical energy, a set point controller for controlling the operation of the thermostat, and a temperature sensor for sensing a fluid. A conventional boat dock de-icer is plugged into the thermostat control and the thermostat control is connected to a source of electrical energy. The temperature sensor is placed in water in the vicinity of a boat dock, and the set point is set to any desired temperature, but preferably to a temperature about freezing. When the control temperature of the water is reached, the thermostat control permits operation of the boat dock de-icer, so that the de-icer operates only when needed, instead of continuously.

This invention relates to a control device, and in particular, to a thermostat control for a boat dock de-icer. While the invention is described with respect to its application with a boat dock de-icer, those skilled in the art will recognize the wider applicability of the inventive principals disclosed hereinafter.
Boat owners who operate their pleasure craft, for example, in lakes or rivers subject to freezing, are limited in their choices for preventing cold weather from causing damage to the boat because of low temperatures. In the past, boats have been removed from the water and placed in storage. More recently, pneumatic lifts are employed in some boat docks to hoist the boat above water, essentially using the boat dock itself as the storage shed.
A second recent option has been to leave the boat in the water but use a de-icer with it during the cold months. The de-icers essentially are electrically powered pumps which blow a air/water mixture into the boat dock around the hull of the craft. The turbulence thus created prevents water in the vicinity of the boat from freezing. Pleasure craft in which the present invention finds application often are kept at or in conjunction with second homes or weekend retreats that are not inhabited continuously. Heretofore, an owner of a de-icer who suspected that temperatures might fall below freezing was required to turn the de-icer on and leave it running continuously. The continuous operation of a de-icer increases the cost of operation and reduces the de-icers useful life.
The invention disclosed hereinafter overcomes these prior art deficiencies by providing a control for the de-icer which provides for energization of the de-icer only when the water temperature at the boat dock falls into a danger zone, and removes the source of electricity to the de-icer when the sensed temperature exceeds the predetermined limit. The unattended, intermittent operation of the de-icer reduces operating costs and increases the useful life of the de-icer.
One of the objects of this invention is to provide a temperature control circuit for a de-icer used in conjunction with a boat dock.
Another object of this invention is to provide a low cost device for operating the de-icer.
Still another object of this invention is to provide a control device for a de-icer which includes a temperature sensor and a means for controlling the set point for operating a boat de-icer.
Another object of this invention is to provide for operating a boat dock de-icer when needed.
Another object of this invention is to reduce the operating costs of a boat dock de-icer.
Still another object of this invention is extend the useful life of a boat dock de-icer.
Yet a further object of this invention is to provide a low cost, simple to construct and easily maintained control for a boat dock de-icer.
Other objects will be apparent to those skilled in the art in light of the following description and accompanying drawings.

Thermostatically controlled boat de-icer


A structure having a surface to which an adhesive, fed from a movable nozzle, is applied before connecting an object to the surface. The structure includes a guide groove provided on the surface in which the adhesive is to be applied, such that the nozzle may be moved along the guide groove to introduce the adhesive into the groove.

1. Field of the Invention
The present invention relates to a connecting apparatus using an adhesive. More precisely, the invention relates to an improved surface structure which is to be coated with an adhesive.
2. Description of Related Art
In a known connecting mechanism which uses an adhesive, an appropriate quantity of adhesive is fed from a nozzle which is manually moved to coat a surface with the adhesive. If an excessive amount of adhesive is fed from the nozzle, upon adhering an object to the surface on which the adhesive is applied, the excess adhesive may exude from between the adhered surfaces onto surrounding surfaces or elements, resulting in an undesirable appearance or a deterioration of quality or function of the adhered objects. This problem becomes particularly serious when the elements to be adhered are small.


A method and structure for switching data is provided. An output port scheduler obtains state information of VOQs and available state information of input port data channels and output port buffers. The output port scheduler sends scheduling request information to a FIC of an input port whose input port data channel is ready in input ports corresponding to non-empty VOQs pointing to an output port. After receiving the scheduling request information sent by the output port schedulers, the FIC of the selected input port selects to respond to a scheduling request of one output port scheduler, and sends the VOQ pointing to the output port in the selected input port to the output port buffer. The output port scheduler schedules the VOQ received by the output port buffer out of a switch chip. Buffer resources are saved and the switching performance is improved.

The variable-length switching technology is a packet switching technology that directly processes a variable-length packet in a structure for switching data instead of segmenting the variable-length packet into cells for transmission. The variable-length switching technology is characterized in that on data channels in the structure for switching data, when an input port begins to switch a packet to an output port, a data channel from the input port to the output port is connected and is not released until the whole variable-length packet is transferred to the output port. To improve the efficiency of variable-length switching and overcome the defects brought about by packet segmentation and reassembly, generally, the packet is not really physically segmented when the variable-length packet arrives at the input port. Instead, the packet is logically segmented into fixed-length cells and the fixed-length cells are transmitted back to back. In this way, the packet remains complete during the transmission and when being received upon arriving at the output port, thereby avoiding the operation of reassembling the cells.
The implementation of the variable-length switching technology requires a reasonable structure for switching data and a reasonable method for switching data. Common structures for switching data in the prior art are listed below.
I. Arbiter Crossbar (ArbiterXB) Switch Structure (a Buffered Arbiter Crossbar Switch Structure)
FIG. 1 shows an N×N switch structure in which both the number of input ports and the number of output ports are N. The ArbiterXB adopts a space division structure and uses a centralized arbiter to determine a connection state of each cross-point and determine an output port data channel to which each input port data channel in an switched fabric should be connected, so as to implement the function of transferring data from an ingress of the switched fabric to an egress of the switched fabric. The problem of the architecture lies in that, the switch capacity is limited by, the complexity of the centralized arbiter. The centralized arbitration needs to determine the connection state of each cross-point according to sending requests of all the input ports and sending states of all the output ports, and the computational complexity is in direct proportion to the square of the number of the ports. When a huge number of ports need to be supported, such a centralized arbiter is hard to implement.
II. Combined Input and Crossbar Queued (CICQ) Switch Structure (Also Referred to as a Buffered Crossbar Switch Structure)
FIG. 2 shows an N×N switch structure in which both the number of input ports and the number of output ports are N. The CICQ switch structure (buffered crossbar) has one First-In-First-Out (FIFO) buffer at each cross-point. In total N2 (a square of N, where N is a natural number greater than or equal to 2, the same below) FIFOs exist. A centralized arbiter is not required, and each output port uses a simple output port scheduler to schedule N FIFO output port buffers. Each FIFO output port buffer sends back pressure information to a corresponding input port according to a queue depth, and each input port may decide whether to send data to the FIFO output port buffer according to the back pressure information.
The problem of the structure for switching data lies in that, although the defect of the centralized arbiter is overcome, in total N2 buffers are required for implementing the N×N switch structure since each cross-point of the CICQ has one buffer. In case of a large number of input ports and output ports, the demands for on-chip Random Access Memory (RAM) capacity resources increase sharply, so that the implementation cost is too high.
III. Switch Structure Combining Advantages of CICQ and Arbiter XB
FIG. 3 shows an N×N switch structure in which both the number of input ports and the number of output ports are N. Each vertical column (corresponding to one output port data channel) of the CICQ has N cross-point buffers in total, which are replaced by k FIFO buffers having a fixed number irrelevant to the number of the input ports (k is a natural number greater than or equal to 1). The k FIFO buffers are dynamically shared by N cross-points. Generally, k=4.
The structure, similar to ArbiterXB, uses a centralized arbiter to process a scheduling request of each line card. The arbitration algorithm of the structure is simpler than that of the conventional ArbiterXB. Each output port of the conventional ArbiterXB only can receive data of one input port each time, an average pass rate of one time of iteration is only about 60%, and 3-4 times of iteration are required to achieve a high pass rate. In the new structure, each output port can receive data of k input ports at the same time, and it can be calculated that the pass rate of one time of iteration is as high as 99.7% when k=4.
Meanwhile, since each output port can receive data of k input ports at the same time, the probability of collision and conflict between the input ports is greatly reduced, so the input ports do not need to keep strict synchronization in reception with each other to reduce the conflict probability. In this way, variable-length switching can be implemented easily.
Although the structure saves buffer resources, the centralized arbiter is still used, and the improvement of the performance of variable-length switching is still limited to a certain degree.
In view of the above, the problem of the existing structures for switching data lies in the difficulty of improving the performance of variable-length switching while saving buffer resources.

Method for switching data and structure for switching data


A folded blank includes a bottom panel, side panels, and end panels. The bottom panel has opposite side edges and opposite end edges defining a length and width sized to support a deceased human body in the supine position. The side panels are connected to the opposite side edges of the bottom panel, and extend outward from and substantially parallel to the bottom panel. The end panels are foldably connected to the opposite end edges of the bottom panel, and are folded to extend inward from the corresponding opposite end edges. The folded blank also includes at least one gusset foldably connected to a side panel along a first fold line and connected to an end panel along a second fold line. The gusset has a diagonal fold, and has a first surface disposed adjacent to and coupled to the side panel in an additional location away from the first fold line.

While many caskets are formed of hard materials such as wood, brass and other metal, other caskets are formed of corrugated paper and similar materials. Paper-based caskets have reduced manufacturing cost, reduced shipping costs, and are particularly suitable for cremation. Paper caskets generally have reduced shipping costs due to their reduce weight compared to metal, brass or hardwood. Moreover, paper caskets can have further reduced shipping costs if they can be shipped flat, in bundles.
One of the most basic paper casket designs is a Kraft cremation box. The Kraft cremation box is formed from a die-cut blank, which is folded into a box shape for use as a casket. Today, the blanks for typical plain Kraft cremation boxes measure approximately 42″×93″, and the corresponding blanks for lids measure 30″×81″. The dimensions of an assembled Kraft cremation box and lid (for use to contain and fit a deceased human adult body) is 73″ long, 22″ wide and 10″ deep. These boxes are assembled with cable ties as commonly used to bundle multiple electrical wires in complex installations.
The Kraft cremation boxes are often shipped as blanks. In particular, cremation box blanks and lids are often placed on large wooden skids and delivered to distribution warehouses for resale in smaller quantities to crematories. The Kraft cremation boxes, with or without lids, are shipped to crematories (or other funerary establishments) as blanks, or in other words, lying down flat.
The problem with shipping these types of large flat products on common carrier vehicles is their size. As discussed above, the typical cremation box blank is about 42″×93″. For tractor-trailers, which have a width of typically at least 99″, the skids can be loaded either lengthwise or widthwise. However, the skids with the blanks can only be loaded into delivery trucks lengthwise, because smaller delivery trucks are often limited to approximately 89″ in width. Regardless of how the skids are loaded, different delivery destinations (loading docks, etc.) have different geometries. Based on the geometry of the loading dock or other factors, it can be advantageous or even necessary to rotate and move the skid within the truck using a pallet jack. Because the 42″×93″ cremation blanks have a hypotenuse of over 102″, the skid cannot be rotated within either truck, but particularly not the delivery truck.
One solution to the size problem would be to ship the Kraft cremation boxes fully assembled. Because the assembled 73″×22″ box has a hypotenuse well under 80″, the fully assembled cremation boxes can easily be rotated and manipulated with delivery truck for ease of unloading. The drawback to shipping assembled cremation boxes is that fewer boxes can be stacked vertically, since they are at least 10″ high (with lids), as opposed to blanks that are on the order of 1″ high.
U.S. Pat. No. 8,104,151 teaches another cremation container that has a reduced height and is otherwise partially assembled for shipment such that it has a narrow hypotenuse. While this design addresses the issues of shipment discussed above, the design nevertheless has some interior space for transport of casket interior products, which increases the volume occupied by each cremation box.
There is a need for a paper casket design and shipment method for simple cremation boxes that have reduced height (where few or no interior components need not be shipped with the box), and which can be readily rotated within standard and smaller sized delivery trucks.

Collapsible casket with reduced shipping and/or storage footprint


A method and system are disclosed for creating an interface between a packet-switched network and an IN, which is based on an interface between an associated circuit-switched network and an IN/CAMEL service. Meanwhile, the CAMEL application can also provide IN services to mobile subscribers while they are roaming in other networks (e.g., international roaming).

1. Technical Field of the Invention
The present invention relates in general to the telephony field and, in particular, to a method and system for attaining interoperability between an Intelligent Network (IN) and Packet Data Network (PDN).
2. Description of Related Art
Packet-switched communications standards have been specified for digital cellular telecommunications systems in both Europe and Japan. For example, standards for the General Packet Radio Service (GPRS) have been specified for the Pan-European Global System for Mobile Communications (GSM) by the European Telecommunications Standards Institute (ETSI), the Packet Personal Digital Cellular (PPDC) System by the Nippon Telephone and Telegraph Company (NTTC) in Japan, and packet-switched standards are being specified for the International Mobile Telecommunications-2000 (IMT-2000) System. These packet-switched communications systems being developed are considered more efficient than conventional circuit-switched communications systems in transferring information such as audio, video and data in a mobile radiotelephone system environment. Albeit, the efficiency is likely higher for circuit-switched voice, but the efficiency is higher for packets than the same coding used for circuit-switched data. However, it is assumed that in the initial operational years, the packet-switched communications systems will be used primarily for accessing and transferring Intranet (e.g., companies"" local networks) and Internet (e.g., World-Wide Web or WWW) data, while the conventional circuit-switched systems will still provide the traditional bearer services (e.g., voice calls).
For some time now, mobile communications network operators (e.g., GSM, PDC and IMT-2000 network operators) have been providing certain value-added services such as, for example, the new IN/Customized Applications for Mobile network Enhanced Logic (CAMEL) service. CAMEL is a feature in the GSM Standard that integrates support of operator-specific IN services into the GSM architecture. Essentially, the CAMEL services are overlaid on top of the GSM circuit-switched traffic (e.g., voice calls). However, a problem that exists is that there is currently no known capability for overlaying these value-added services on packet-switched traffic. The main reason for this problem is that this capability is expected to be provided by the Intranet operator or Internet Service Provider (ISP), and not as part of the value-added service (e.g., IN/CAMEL) itself.
Currently, no international standard is being promulgated for an interface between an IN and packet-switched network, and as mentioned earlier, there is no known solution for the problem of how to provide value-added services (e.g., CAMEL) for packet-switched communications. As such, this is an immediate problem for mobile communications network operators who are currently providing IN services, such as, for example, the popular pre-paid services being offered for mobile subscribers"" circuit-switched calls (e.g., voice calls and G3 facsimile calls). Such pre-paid IN services monitor the elapsed time of the circuit-switched call for a mobile subscriber, and translate that time into charges that are billed to the subscriber in proportion to the communications time used. However, there is currently no method or system available that enables a pre-paid IN service application to monitor the elapsed communications time for a subscriber using packet-switched communications.
Consequently, a pressing need has arisen for a PDN/IN interface and interoperability which will enable such services as IN/CAMEL to be overlaid on top of packet-switched traffic as a complement to conventional Intranet and Internet value-added services. As described in detail below, the present invention successfully meets this need and resolves these and other related problems.
In accordance with a preferred embodiment of the present invention, a method and system are provided for creating an interface between a packet-switched network and an IN, which is based on an interface between an associated circuit-switched network and an IN/CAMEL service. Meanwhile, the CAMEL application can also provide IN services to mobile subscribers while they are roaming in other networks (e.g., international roaming).
An important technical advantage of the present invention is that mobile network operators providing IN/CAMEL services to offer a pre-paid subscription to mobile users, which will cover traditional voice calls and also Intranet and Internet usage through a packet-switched communications standard.
Another important technical advantage of the present invention is that a mobile user of circuit-switched and packet-switched communications can subscribe with one network operator to provide a pre-paid service and pay in advance only once for the subscription. The network will subtract payments from the user""s account for both the circuit-switched and packet-switched traffic.
Still another important technical advantage of the present invention is that a viable interface and interoperability are provided between a packet data node and an IN/CAMEL node, which can be used to overlay CAMEL services on packet communications as a service complement to Intranet and Internet value-added services.

Intelligent network and packet data network interoperability


A display device including a display; a first external device interface configured to receive an image signal and an audio signal output from a first external input device; a second external device interface configured to receive an image signal and an audio signal output from a second external input device; and a controller configured to display a graphic user interface including a first external input item describing at least one of the first external device interface and the first external input device connected to the display device via the first external device interface, a second external input item describing at least one of the second external device interface and the second external input device connected to the display device via the first external device interface, a first audio output menu for selecting at least one of a plurality of audio output devices for outputting audio included in the audio signal received from the first external input device, and a second audio output menu for selecting at least one of a plurality of audio output devices for outputting audio included in the audio signal received from the second external input device.

Field of the Invention
The present disclosure relates to a display device and an operating method thereof.
Discussion of the Background Art
Digital TV services using wired or wireless communication networks are becoming common. The digital TV services can provide various services that conventional analog broadcasting services cannot provide. For example, Internet Protocol Television (IPTV) and smart TV services, that is, types of digital TV services, provide interactivity that allows users to actively select the types, watching times, and so on of watching programs. The IPTV and smart TV services can provide various additional services, for example, internet search, home shopping, and online game, based on such interactivity.
Further, recently, an image on an external device connected to a display device can be viewed through the large screen of the display device by using a list. However, in relation to a typical display device, if an external input item is selected from a list, the audio of the external input corresponding to the selected external input item is output through only a speaker provided to the display device, so that it is not able to provide an optimized sound to a user.

Display device and operating method thereof


Reflectionless transmission line filters, as well as a method for designing such filters is disclosed. These filters preferably function by absorbing the stop-band portion of the spectrum rather than reflecting it back to the source, which has significant advantages in many different applications. The insertion of additional transmission line sections that change the phase response of the circuit without altering the amplitude response preferably allows follow-up transmission line identities to be applied in order to arrive at a more easily manufacturable filter topology. This facilitates their application over a higher frequency range the solely lumped-element circuits.

1. Field
The invention is directed toward electronic filters and methods of their use. Specifically, the invention is directed toward reflectionless electronic filters and methods of their use.
2. Background
Virtually all electronic systems use some kind of filtering to reject unwanted frequency components. In most conventional filters, the rejected signals are bounced back to the source, eventually dissipating in the generator itself, or in the interconnecting wires/transmission lines, or being radiated into the instrument housing. This manner of rejecting unwanted signals can sometimes lead to harmful interactions with other components in the system, either by spurious mixing in non-linear devices, unintentional re-biasing of sensitive active components, or cross-talk between various signal paths. A solution was sought for a filter that would absorb these unwanted signals before they could compromise performance. This led to a novel absorptive filter topology which was patented in 2013 (U.S. Pat. No. 8,392,495) as well as pending U.S. patent application Ser. No. 14/724,976 the entirety of both of which are incorporated by reference herein. These absorptive filters solved many problems encountered with conventional filters, such as the sensitivity of mixers to poor out-of-band terminations, detrimental and difficult-to-predict non-linear effects from reactive harmonic loading, leakage or cross-talk due to trapped energy between the filter and other poorly-matched components, and numerous other problems associated with out-of-band impedance matching. They also realized superior performance and manufacturability when compared to other approaches to absorptive filters, such as terminated diplexers and directional filter structures employing quadrature hybrids.
None of these prior embodiments, however, adequately taught how to implement such designs using transmission lines rather than lumped elements. The inability to easily convert these into transmission line form constrained the frequencies at which they could be effectively implemented to the cm-wave range and below. Recent efforts to address this issue have yielded a practical transmission line solution which extends the frequency range easily into submillimeter-waves while maintaining the benefits of the original reflectionless filter topology.

Transmission line reflectionless filters


A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.

The present disclosure herein relates to methods of manufacturing three-dimensional semiconductor devices and related three-dimensional semiconductor devices.
Recently, demand for higher integration of semiconductor devices has increased to obtain improved performance and/or low price for user needs. In semiconductor memory devices, higher integration may be particularly required, since integration is a significant factor in determining prices. In two-dimensional or planar semiconductor devices, since the integration degree mainly depends on an area occupied by a unit memory cell, integration is affected by the technique(s) used to form fine patterns. In order to realize minute patterns, however, an increase in integration of the two dimensional semiconductor devices may be restricted since it may be necessary to install expensive equipment.
In order to overcome these restrictions, there have been suggested three-dimensional semiconductor devices including memory cells arranged three-dimensionally. In order to realize mass production of the three-dimensional devices, however, a manufacturing technique may be required to achieve reliable product characteristics while reducing a manufacturing cost per bit more than that of two dimensional semiconductor devices.

Methods of manufacturing three-dimensional semiconductor devices and related devices


The invention is in the field of molecular diagnosis of medical diseases and their treatment. More in particular, it provides methods and means for detecting hypertension, more in particular essential primary hypertension, even more in particular NOX5-dependent hypertension. The invention also provides methods for the treatment of hypertension, in particular essential primary hypertension, more in particular NOX5-dependent hypertension. The invention also provides theragnostics, wherein therapy is combined with diagnosis, more in particular wherein the level of NOX5 is determined in a sample from a subject and wherein the subject is treated with NOX5 inhibitors or compounds that decrease the levels of NOX5 if the NOX5 levels are above a certain threshold value. Further, the invention also provides theragnostics, wherein diagnosis is combined with therapy, more in particular wherein the (plasma) level of NOX5 is determined in a sample from a subject and wherein the subject is treated with NOX5 inhibitors or compounds that reverse the result of NOX5 activity in the subject, when the determined NOX5 level is exceeding a predetermined threshold level. Finally, the invention relates to an animal model suitable for developing diagnostic methods and therapeutic treatments for NOX5-dependent hypertension.

Hypertension is of major medical relevance as a risk factor for myocardial infarction, stroke and other chronic conditions and death [1]. With the exception of 5% of patients with secondary hypertension (due to renal artery stenosis, adrenal adenomas, pheochromocytomas and numerous single gene mutations involving renal transporters [2]), in the remaining 95% of all cases the cause of hypertension is not known. In these cases of so-called 'essential primary hypertension', treatments have to focus on symptomatic vasodilatory drug therapy and lifestyle management. Even this symptomatic antihypertensive therapy is sometimes ineffective, i.e. in treatment-resistant hypertension, and requires high number to treat with many patients still experiencing adverse outcomes such as stroke and myocardial infarction [3]. Resistant hypertension (RH) is defined by the American Heart Association [104] as: above-goal elevated blood pressure (BP) in a patient despite the concurrent use of three anti-hypertensive drug classes, commonly including a long-acting calcium channel blocker, a blocker of the renin-angiotensin system (angiotensin-converting enzyme inhibitor or angiotensin receptor blocker), and a diuretic. The antihypertensive drugs should be administered at maximum or maximally tolerated daily doses. RH also includes patients whose BP achieves target values on more than four anti-hypertensive medications. The diagnosis of RH requires assurance of anti-hypertensive medication adherence and exclusion of the "white-coat effect" (office BP above goal but out-of-office BP at or below target).
One molecular mechanism of hypertension that has been suggested for decades is oxidative stress, i.e. an unphysiological production of reactive oxygen species (ROS), which in blood vessels interferes with vasodilation by the endothelium-derived relaxing factor, nitric oxide (NO) [4]. No hypertension-relevant cellular source of ROS, however, has been identified to either prove this hypothesis or exploit it for a mechanism-based or even curative clinical therapy.
Recent genome-wide association studies (GWAS) [5] in search for hypertension risk genes point towards NADPH oxidases (NOX), the only known enzyme family dedicated to ROS formation, in particular the genes Nox4 and Nox5. This matches preclinical studies, excluding other vascular NOX isoforms i.e. NOX1 and NOX2 with respect to causing hypertension, unless animals are infused with pro-hypertensive agents [6-8]. With respect to NOX4, this isoform is widely expressed, but appears irrelevant for blood pressure or hypertension [9] but is rather vaso-protective [10]. With respect to NOX5, this enzyme is physiologically expressed in vascular endothelial cells of human blood vessels and may be associated with diabetic nephropathy [11-13]; mice expressing human NOX5 in vascular smooth muscle cells are, however, normotensive [14]. Thus, the role of NOX5 in hypertension remains as yet unclear.
In moving away from single targets, network medicine [15] predicts that for most in particular complex diseases not a single protein but protein modules, i.e. sub-graphs of the interactome, are in fact relevant [16-18]. Therefore, we set out to reinvestigate the association of NOX with hypertension and NO-dependent vasodilation using three complementing unbiased in-silico approaches and to validate any prediction both in mice and, if possible, also human patient samples.

Method for the diagnosis and treatment of essential primary hypertension


Dual action sunscreen compositions capable of both moisturizing the skin and protecting it from sunburn are made from a cationic guar, a cationic acrylic polymer and an ultraviolet absorbing sunscreening agent.

The field of art to which this invention pertains is topical sun or radiation screening or tanning preparations.
Although the potentially damaging effects of sunlight on human skin have been well publicized, many people have occupations which require them to be exposed to the sun for long periods of time. Many others choose to spend their leisure time outdoors playing tennis or golf, swimming, fishing, skiing, or sunbathing. To protect human skin against erythema-causing radiation from the sun, a variety of sunscreening compositions have been developed which contain compounds which absorb ultraviolet light in the erythemal region.
Commercially available sun screen and sun block formulations provide excellent protection against severe sun burning of exposed skin for extended periods so long as they remain on exposed areas and are not washed off when contacted with water or perspiration. Unfortunately, bathing in pool water or ocean water will usually result in most conventional sun screen and sun block formulations being washed away from the skin thereby leaving exposed areas of skin.
In U.S. Pat. No. 4,781,914, sun screen compositions which are also moisturizer compositions are described. Such compositions are made in the form of a sprayable oil-in-water emulsion which when applied to the skin and rubbed in inverts to a water-in-oil creamy nongreasy film.
Water resistant sunscreen compositions which contain a water insoluble acrylate polymer are described in U.S. Pat. No. 4,172,122.
Substantive PABA (para-aminobenzoic acid) formulations which contain water soluble cellulosics are disclosed in U.S. Pat. No. 4,254,102.
Water-proof sunscreen compositions which contain ethyl hydroxyethyl cellulose polymers are described in U.S. Pat. No. 4,671,955.
In U.S. Pat. No. 4,559,225, water-proof sunscreen compositions which contain a cellulose polymer, a solvent, an ultra-violet sunscreening agent, and an emollient are disclosed.
Cosmetic manufacturers are constantly striving to improve personal skin care products, which not only offer protection from the sun, but also contribute to the smoothing and softening of the skin.


A mold temperature control system comprises a mold section having a cavity, a fluid circuit to distribute a flow of a conditioning fluid, the fluid circuit being positioned spaced apart from the cavity, a temperature sensor positioned in the mold to generate a signal representative of a temperature in the mold, a controllable supply of the conditioning fluid, and a controller for automatically initiating flow of the conditioning fluid through the fluid circuit in response to an initiation temperature and for automatically terminating flow of the conditioning fluid through the fluid circuit in response to a termination temperature.

This invention relates in general to controlling mold temperature in a casting system to produce a cast article. Pressure pouring of molten metal from a furnace to fill a mold cavity has been used for several decades. At room temperature, the metal is solid and becomes fluidic when melted with sufficient heat.
It is known to use a low pressure countergravity casting apparatus to cast molten metal into a mold. One example of such an apparatus is described in U.S. Pat. No. 5,215,141. Basically, in a low pressure countergravity casting apparatus, molten metal is supplied to a machine furnace. The machine furnace includes a supply conduit for introducing a gas under pressure into the machine furnace. As the gas is introduced into the machine furnace, the molten metal in the machine furnace is forced through a submerged feed tube, or evacuation conduit, into the mold. The evacuation conduit is commonly referred to as a stalk tube. The mold receives the molten metal through holes in the bottom of the mold.
The molten metal must cool in the mold and harden to produce the cast article. Cooling of the molten metal is generally done by cooling the mold using a cooling fluid flowing through cooling channels in the mold. Conventionally, cooling of the mold has been controlled by a skilled human operator who adjusts the flow of the cooling fluid, which has been rather imprecise. Insufficient cooling times can lead to an improperly formed cast article. Excessive cooling time leads to decreased cycle times and economic inefficiency.
In order to make a solid cast article with the best possible structural properties in the least amount of time, the mold temperature during metal filling and during cooling must be accurately controlled regardless of environmental conditions (e.g., ambient air temperature, humidity, and temperature and pressure of the cooling fluid). During casting, the heat energy of the molten metal (e.g., aluminum) flows into the mold and then into the cooling fluid. Preferably, a temperature profile is achieved such that a directional solidification of the cast article occurs wherein the article solidifies from the outside and then in towards the filling area (i.e., stalk tube). After a solidified article is removed from the mold, it is prepared as quickly as possible for casting another part. This includes ensuring that the mold starts the next cycle at a predetermined temperature. Thus, it is desired to cool a mold as quickly as possible while maintaining acceptable structural properties of the article and providing directional solidification.
The above advantages as well as other advantages not specifically enumerated are achieved by a mold temperature control system comprising a mold section having a cavity, a fluid circuit to distribute a flow of a conditioning fluid, the fluid circuit being positioned spaced apart from the cavity, a temperature sensor positioned in the mold to generate a signal representative of a temperature in the mold, a controllable supply of the conditioning fluid, and a controller for automatically initiating flow of the conditioning fluid through the fluid circuit in response to an initiation temperature and for automatically terminating flow of the conditioning fluid through the fluid circuit in response to a termination temperature.
Various advantages of this invention will become apparent to those skilled in the art from the following detailed description of the preferred embodiment, when read in light of the accompanying drawings.

Mold temperature control for casting system


An input and output operation device includes an actuator 165 including an operation unit 850; a movable unit having the operation unit and at least one attraction magnet mounted thereon and including a concaved portion in a part thereof; a secured unit including a convexed spherical surface loosely engageable with at least one magnetic member and the concaved portion of the movable unit, the convexed spherical surface being point-contactable or line-contactable with the concaved portion of the movable unit by a magnetic attraction force, the secured unit supporting the movable unit such that the movable unit is freely rotatable as centered around a spherical center of the convexed spherical surface; a first driving unit rotating the operation unit as centered around an X-axis passing the spherical center; a second driving unit rotating the operation unit as centered around a Y-axis perpendicular to the X-axis; a third driving unit rotating the movable unit as centered around a Z-axis that is perpendicular to the X-axis and the Y-axis and is a central axis of the operation unit; and a detector detecting a first rotation angle and a second rotation angle of the operation unit around the X-axis and the Y-axis; and also includes a detection circuit unit 360 generating first and second rotation angle signals; a control computation processing unit 94 generating first and second target rotation angle signals; and a driving circuit unit 350 generating a signal usable to drive the first and second driving units.

Recently, electronic devices mounted on an automobile are increased in the level and the variety of functions for the purpose of improving safety, security and comfortableness. This complicates the operation procedure to be performed by a driver. For the purpose of simplifying such a complicated operation, an HMI (Human-Machine Interface) that is matched well with the sense of the driver and is highly easy to operate is desired to operate, for example, a navigation device, an air conditioner, an audio device, a radio or the like.
An HMI proposed as having a high affinity is a haptic device including an input device operable in three-axial directions or having a feedback function.
For example, Patent Document 1 discloses a three-axial input operation device that restricts the direction of movement of an operation unit such that the operation unit is movable only in X-, Y- and Z-axis directions and detects the position of the operation unit in the X-, Y- and Z-axis directions.
Patent Document 2 discloses an input operation device that holds an operation unit such that the operation unit is rotatable in three-axial directions and is capable of detecting the rotation angle.
Patent Document 3 discloses a haptic device that rotates an operation device in X- and Y-axis directions, detects an amount of relative positional change around each of the axes, and provides a haptic sense to the operation unit by a motor mounted on a rotation mechanism for each of the axes.

Panasonic Intellectual Property Management Co., Ltd.


A mixture of air and fuel is compressed in a compressor of a gas turbine system. The gas turbine system includes components that define one or more fuel leak locations, and leaked fuel is directed from the one or more leak locations to a reaction chamber of the gas turbine system. At least a portion of the leaked fuel is oxidized in the reaction chamber. The energy released by oxidation of the leaked fuel can be converted to mechanical motion.

This disclosure relates to managing fuel-containing leaks in a gas turbine system. In a conventional gas turbine system, fuel is combusted as it is injected into pressurized air, thereby heating and increasing the energy of the gas. The energy is then extracted from the heated gas with a turbine that converts the energy into kinetic energy. The kinetic energy may be used to drive another device, for example, a generator. In some systems, fuel can leak internally within the gas turbine system or externally to an atmosphere of the gas turbine system, for example, due to pressure differentials across imperfect seals in the gas turbine system. In some instances, fuel leaks can be wasteful and/or hazardous.


A non-volatile semiconductor memory device which simultaneously possesses a non-volatile memory cell region which possesses an isolating insulation film which has been formed selectively within a semiconductor substrate, which also possesses a first electroconductive film (floating gate electrode) via a first gate insulating film which has been formed on the semiconductor substrate surface, and which also possesses a metal film (control gate electrode) via a second gate insulating film which has been formed above said electroconductive film and a peripheral transistor region which possesses a metal film (gate electrode) via a third gate insulating film which has been formed above the semiconductor substrate surface.

Regarding semiconductor memory devices such as simple flash memories and EEPROMs (electrically re-writable non-volatile memory cells), one-chip products with added values which are endowed with the functions of peripheral circuits (e.g., logic device, etc.) have generated considerable demand in recent years in relation to the applications of the respective devices rather than to applications whereby their respective functions are customized for users' utilities. Single gate-type transistor elements, however, become the central circuit elements for the logic device, and since they are constituted in certain combinations which are capable of meeting the essential circuit logic requirements, the transistor elements within the circuit are not necessarily configured in an orderly fashion. In contrast, a memory device is provided by configuring memory cell transistors which serve as memory elements at intersections of word lines and bit lines, and therefore the memory cell transistors within the circuit are normally configured in an orderly fashion. In the cases of semiconductor memory devices such as simple flash memories and EEPROMs (electrically re-writable non-volatile memory cells), furthermore, double gate-type transistors are generally embodied as memory cells, whereas single gate-type transistors are generally employed as logic devices. In the context of providing common and abbreviated processes for forming transistor gates, therefore, it is necessary to develop unprecedented processes.
In addition to the foregoing factors, further attempts are beginning to be made to alter gate electrode formation processes innovatively by forming gate electrodes with an electroconductive metallic material for the purposes of lowering the intrinsic gate electrode resistance and accordingly upgrading the device speed. In order to adapt such a novel technology to a heterogeneously-mounted semiconductor device, a correspondingly novel scheme for abbreviating and streaming its manufacturing processes as much as possible becomes necessary.
Next, two examples of the prior art, namely a method for manufacturing a flash memory and a method for manufacturing a device which consists of single gate-type transistors based on the drama scene gate process, will be explained.
FIGS. 1 through 3 are diagrams provided for explaining the respective processes of a method of the prior art for manufacturing a flash memory. FIGS. 1(a)-1(c) show the processes in proper order along the α-α′ cross section in the upper plane representation of the diagram shown at the top of FIG. 1(a). A peripheral transistor is shown on the left side of the diagram at the top, whereas a non-volatile memory cell region is shown on its right side, as shown in FIG. 1(a).
First, a thermal oxide film (SiO2) and an insulating film (e.g., Si3N4, etc.) are grown at thicknesses of 12 nm and 200 nm, respectively, above a semiconductor substrate of a given electroconductivity type (P+), and a sufficiently deep channel is formed in an isolating region by means of dry etching by using a hard mask obtained by patterning it. An oxide film whose thickness is large enough for completely filling this channel is deposited, and a portion of the oxide film protruding from the channel is removed by means of CMP (chemical mechanical polish) for the purpose of flattening the surface. Next, the thermal oxide film (SiO2), which serves as a stopper film, and the insulating film (Si3N4) are removed, as a result of which a buried oxide film structure of the STI (shallow trench isolation) modality is obtained as shown in FIG. 1(b).
Next, referring to FIG. 1(c), an impurity ion is implanted into the peripheral transistor region and then thermally diffused, as a result of which a well of a desired shape is formed. Next, a thin oxide film which is to become the first gate insulating film (tunnel gate insulating film, TNOX) of the non-volatile memory is formed on the entire plane of said semiconductor substrate based on the thermal oxidation method.
Next, referring to FIG. 2(a), a first polycrystalline silicon film is formed on the entire plane based on the CVD (chemical vapor deposition) method. Next, a resist is preliminarily patterned based on the photolithographic method for the purpose of forming a resist mask in the context of the isolation of the floating gate of the non-volatile memory. Next, the first polycrystalline silicon film is dry-etched and patterned by using this resist mask. An oxide layer (or an ONO film [silicon oxide film/silicon nitride film/silicon oxide film]) is then formed on the first polycrystalline silicon film as a second gate insulating film (PA (first wire layer)-PB (second wire layer) gap interlayer insulating film). The resist film which blankets the entire plane is subsequently patterned based on the photolithographic method.
Next, referring to FIG. 2(b), the second gate insulating film (PA (first wire layer)-PB (second wire layer) gap interlayer insulating film) and first polycrystalline silicon film (floating gate) are dry-etched and patterned in proper order by using the obtained resist pattern as a mask, whereas the aforementioned second gate insulating film and first polycrystalline silicon film remain partially unetched in such a way that a gate pattern will be selectively formed in the non-volatile memory cell region alone and that the second gate insulating film and the first polycrystalline silicon film will be completely removed from the remainder.
Next, referring to FIG. 2(c), the first gate insulating film in the peripheral transistor region is removed by means of a preliminary treatment, and a thin third gate insulating film (GOX) is grown on the corresponding site.
Next, referring to FIG. 3(a), a thick second polycrystalline silicon film is formed on the entire plane, and an SION film which serves not only as an anti-reflection film but also as a dry etching stopper film during subsequent processes is deposited on a site immediately above it, and a photoresist is subsequently formed patternwise. A floating gate electrode and a control gate electrode within the non-volatile memory cell region are patterned based on the photolithographic method. Next, the prevailing mask is substituted with a new pattern mask, and the gate electrode within the peripheral transistor region is patterned based on the photolithographic method.
Next, referring to FIG. 3(b), a source-drain diffusion layer (n+ diffusion layer) for the non-volatile memory cell region is formed in a self-matching fashion by implanting arsenic whose electroconductivity is the opposite of that of the substrate as an impurity ion.
Referring to FIG. 3(b), after a thick oxide film has subsequently been grown based on the chemical vapor deposition method, the entire plane is anisotropically etched in such a way that side wall insulating films will remain on the gate electrode side wall of the peripheral transistor region and the side walls of the floating gate electrode, second gate insulating film, and control gate electrode of the non-volatile memory cell region and that the oxide film will be removed from the remainder. Next, the isolating insulation film is partially removed by using a resist pattern on which a pattern of the source region of the non-volatile memory cell region has been formed negatively while the second polycrystalline silicon layer is being employed as a partial mask portion, as a result of which a common source region (so-called "self-aligned source (SAS) region") is formed in a self-matching fashion. Next, a peripheral transistor source-drain diffusion layer (n+ diffusion layer) is formed by ionically implanting arsenic the electroconductivity of which is the opposite of that of the substrate in a self-matching fashion. Arsenic is concomitantly introduced to the site from which the isolating insulation film has been removed previously. A transistor source region and a common source wire layer are formed in a self-matching fashion. Next, the SiON film above the gate electrode is removed by means of a liquid chemical treatment. Next, a thin Co (cobalt)-TiN (titanium nitride) layer is grown over the entire plane, and subsequently, a high-melting-point metal silicide layer (CoSi (cobalt silicide) layer in this case) is formed by means of RTA (rapid thermal annealing), whereas unreacted [Co (cobalt)+TiN (titanium nitride)] is dry-etched and removed. The obtained product is further subjected to annealing based on the RTA. As a result, a high-melting-point metal silicide layer (so-called "salicide layer") is formed above the gate electrode and source-drain diffusion layer in a self-matching fashion.
Next, a sufficiently thick interlayer insulating is formed blanketwise on the entire plane. Although subsequent processes are not graphically shown, a non-volatile semiconductor memory device is obtained by drilling a contact hole on the interlayer insulating film and by then forming an electrode wire. The foregoing processes comprise the method of the prior art for manufacturing a flash memory.
Next, a method of the prior art for manufacturing a single-layer gate element based on the damascene gate process will be explained.
FIG. 4 is a schematic demonstrational diagram which shows the method of the prior art for manufacturing a single-layer gate element which possesses a damascene gate, where FIG. 4(a) through FIG. 4(h) show cross-sectional views of the respective processes in proper order. The diagram for each process shows cross-sectional views of a first transistor (left in the figure) and a second transistor (right in the figure), which possess distinct gate insulating films and gate electrodes during the corresponding process. The method shown in FIG. 4 is described in Japanese Patent Application Publication No. Kokai Hei 11-74369, and explanations will be provided below with reference to it.
First, a well region and an isolating region characterized by the STI structure are formed above the semiconductor substrate (201) (not shown in the figure). Subsequently, a thin layer is formed as the gate oxide layer (203) based on the thermal oxidation method, followed by the depositions of the polysilicon film (204) and the silicon nitride film (205) above it in proper order based on the CVD (chemical vapor deposition) method. Next, the laminate structure constituted by the polysilicon film (204) and the silicon nitride film (205) is patterned into a shape suitable for a gate electrode pattern based on the photolithographic method. Next, an electroconductive impurity is introduced to the interior of the semiconductor substrate (201) by using the patterned gate electrode as a mask based on the ion implantation method, and the obtained structure is designed to function as an LDD (lightly doped drain) layer on a later occasion. Subsequently, the side wall insulating film (207), which consists of a silicon oxide film, is formed on the side wall of the patterned gate electrode. An electroconductive impurity is ionically implanted by using as a mask a dummy gate structure constituted by the dummy gate electrode and side wall insulating film (207). The source-drain diffusion region (206) is subsequently formed by means of a thermal annealing. Next, the silicon oxide film (208) is formed on the entire plane based on the CVD method, as a result of which the entire dummy gate structure becomes blanketed. The silicon oxide film (208) is subsequently etched back based on the CMP (chemical mechanical polish) method by using the silicon nitride film (205) as an etching stopper, as a result of which its entire surface becomes planarized, as shown in FIG. 4(b).
Next, referring to FIG. 4(c), a region on which a first transistor is to be formed is covered with the photoresist (209), and the silicon nitride film (205) and the polysilicon film (204) are removed in proper order, as a result of which the channel unit (210) is formed.
Referring to FIG. 4(d), a channel ion implantation operation is effectively carried out through the gate oxide layer (203), which has been bared on the bottom plane of the channel unit (210), and the gate oxide layer (203) of this bared region is subsequently removed. Next, the gate oxide film (211) is formed on the surface of the semiconductor substrate (201) in the bared region based on the thermal oxidation method, and the tungsten film (212) is ether formed over the entire plane.
Next, referring to FIG. 4(e), the tungsten film (212) which has been formed outside the channel unit (210) is removed based on the CMP (chemical mechanical polish) method, as a result of which the tungsten film (212) remains within the channel alone.
Referring to FIG. 4(f), the silicon nitride film (205) above the polysilicon film (204) is peeled, as a result of which the polysilicon film (204) becomes bared, and the channel unit (213) is formed.
Next, referring to FIG. 4(g), the tungsten film (214) is deposited on the entire plane.
Next, referring to FIG. 4(h), the tungsten film (214) is polished based on the CMP (chemical mechanical polish) method, as a result of which the tungsten film (214) remains only within the first transistor channel.
Next, a thick interlayer insulating film is formed, and after a contact hole has been formed on it, an electrode wire is further formed, as a result of which a non-volatile memory is obtained.
First, problems specific to the logic unit transistor of the prior art and the flash unit transistor of the prior art will be individually explained, and subsequently, problems that must be solved when both the logic and flash units are heterogeneously mounted will be discussed.
It is indispensable to lower the resistance of the gate electrode and to improve the current drive capacity for the purpose of upgrading the speed of a transistor. The thickness of a silicate film may be increased in order to lower the gate resistance. In such a case, the gate height becomes excessive in relation to its length in the context of size reduction, which is problematic in that it becomes difficult to process a gate. It is necessary to ensure the formation of a sufficient channel even at a lower voltage which becomes unavoidable as a result of such a size reduction attempt for the purpose of improving the current drive capacity, and therefore, the thickness of the gate insulating film needs to be minimized. When the thickness of a silicon oxide film is reduced to 5 nm or less, however, the leak current increases, which is problematic in that the transistor performances deteriorate. Major problems specific to the logic unit transistor can be thus characterized.
Problems associated with a case where the resistance of a flash memory cell gate is lowered will be explained. In the case of an LSI on which a flash memory and a logic device have been heterogeneously mounted, it is indispensable to increase the speeds of not only the logic unit but also the flash memory cell. As in the case of the logic unit, it is necessary to increase the thickness of the silicide film for the purpose of lowering the gate resistance, but in such a case, the height of the gate becomes excessively great in relation to its length, as a result of which it becomes difficult to process a gate. In the case of a flash memory characterized by a laminate structure of a floating gate and a control gate, such a tendency is more conspicuous than in the case of the logic unit.
Next, problems associated with the coupling ratio and data retention capacity of the flash memory will be explained. When the potential of the floating gate is defined as VFG, the potential of the control gate as VCG, the capacitance between the semiconductor substrate and floating gate as C0, and the capacitance between the floating gate and control gate as C1, the following relationship can be ascertained between VFG and VCG:VFG=1/(1+C0/C1)×VCG; VFG/VCG=1/(1+C0/C1); VFC/VCG will be referred to as the "coupling ratio."
C0/C1≈0 should ideally hold when C0<<C1 holds, and the potential which has been impressed on VCG should be undepletedly impressed on VFG under the co-pervasion of C0/C1≈1.
When the coupling ratio is low, it becomes impossible to lower the voltage impressed on the control gate electrode during data encoding and erasure operations vis-à-vis the flash memory despite the reduced element size. The electricity consumption may be minimized in the logic unit, but since a high voltage becomes necessary for the flash memory cell, it becomes impossible to reduce the electricity consumption for the entire chip. The chip area, furthermore, becomes inevitably enlarged in that a circuit for converting a low power source voltage into a high voltage becomes necessary. This tendency becomes more conspicuous as the power source voltage diminishes as a result of the progressive size reduction of the logic unit.
The thickness of the insulating film may be reduced for purposes of elevating the aforementioned C1 and accordingly of improving the coupling ratio. In such a case, however, the leak current inevitably increases, as a result of which the data retention capacity deteriorates.
It may also appear feasible to increase the contact area between the floating gate and control gate for the purpose of elevating the aforementioned C1. In such a case, however, the enlargement of the cell area and the complication of the structure become problematic.
Finally, problems associated with an operation for manufacturing a heterogeneously flash memory-mounted logic LSI will be explained. Regarding transistors to be used for the logic unit, transistor test results based on a format wherein a film of W (tungsten), whose resistance is lower than that of the silicide film, is formed based on the CMP (chemical mechanical polish) method while a gate insulating film constituted by Ta2O5, whose permittivity is higher than that of the silicon oxide film, is being concomitantly used have been reported, as described in A. Yanagishita, et al., IEDM Tech. Dig., 1998, pp. 785-788; A. Chatterjee, et al., IEDM Tech. Dig., 1998, pp. 777-780.
These reports, however, are each limited to disclosures of test samples constituted by unintegrated transistors, and accordingly they fail to mention methods applicable to heterogeneously flash memory-mounted logic LSIs.
When the aforementioned high-permittivity film and metal gate are simply used for the logic unit alone, however, the number of processes and the cost increase in that a process separate from that for preparing a flash memory unit is required.
The height of the flash memory cell, furthermore, becomes greater than that of the logic unit transistor by a margin corresponding to the height of the floating gate electrode. Due to the concomitantly incurred step differential, processing safety margins for opening a contact hole and for forming a metal wire, which are to be formed on later occasions, diminish, as a result of which the reliability and yield deteriorate.
The foregoing analyses can be summarized as follows:
1): When the gate lengths of a flash memory cell and a logic region transistor are reduced in a heterogeneously flash memory-mounted logic LSI of the prior art, it is problematic in that it becomes impossible to reduce the resistance of the gate electrode under the pervasion of a silicide film alone.
When the thickness of the aforementioned silicide film is increased for the purpose of lowering the gate electrode resistance, furthermore, the ratio of the longitudinal dimension in relation to the lateral dimension (channel direction) increases to an excessive level, which is problematic in that it becomes difficult to process the gate electrode.
2): Either ON or ONO is employed as an insulating film between the floating gate and control gate of the non-volatile memory cell of the heterogeneously flash memory-mounted logic LSI of the prior art, and therefore, the coupling ratio can be elevated only by reducing the thickness of said insulating film or by enlarging the area of the aforementioned C1 capacitor. The reliability, however, deteriorates at a reduced film thickness, whereas said area enlargement entails a memory cell area gain and/or a process complication. As a result, it is impossible to lower the voltage impressed on the control gate electrode, which is problematic in that it becomes impossible to minimize the electricity consumption.
3): Regarding the method for manufacturing the heterogeneously flash memory-mounted logic LSI of the prior art, when a high-permittivity film is employed as a gate insulating film while a metal (e.g., W, Al, etc.) is used as a gate electrode material for the purpose of upgrading the performances of the transistor within the logic region, it becomes impossible to share processes with the non-volatile memory cell, as a result of which the number of processes increases, and it is also problematic in that reliability loss and cost increase are incurred.
The height of the flash memory cell, furthermore, exceeds that of the logic unit transistor by a margin corresponding to the floating gate height. Due to the concomitantly incurred step differential, processing safety margins for opening a contact hole and for forming a metal wire, which are to be formed on later occasions, diminish, as a result of which the reliability and yield deteriorate.

Semiconductor device and its manufacturing method


A current controller includes a current control circuit and a current detection circuit, which detects a current flowing through a solenoid of an electromagnetic proportional relief valve. The current control circuit sets a current command to a sum of a value obtained by multiplying a feedforward gain by a target current value, a value obtained by multiplying a proportional gain by a current deviation, and a value obtained by multiplying an integral gain by a current deviation integral value. The current control circuit then controls the current flowing through the solenoid in accordance with the current command. When the current detected by the current detection circuit is less than or equal to the predetermined value, the current control circuit resets the current deviation and the current deviation integral value and sets the current command based on the reset values.

The present invention relates to a current controller that is configured to control a current flowing through a solenoid of an electromagnetic proportional relief valve.
For example, a forklift is known as an industrial vehicle that includes an engine and a hydraulic pump driven by the engine. A forklift operates a hydraulic actuator with hydraulic oil discharged from a hydraulic pump. The forklift, for example, includes hydraulic cylinders that are hydraulic actuators configured to move the fork upward or downward and hydraulic cylinders that are hydraulic actuators configured to tilt the mast assembly. The forklift also includes a control valve that controls supply and drainage of hydraulic oil, which is supplied from the hydraulic pump, to and from the hydraulic cylinders. When the hydraulic pump is driven by the engine, the engine torque may become insufficient as the load on the hydraulic pump increases, which may cause the engine to stall. Thus, conventionally, configurations for avoiding such engine stalls have been proposed. For example, refer to Japanese Laid-Open Patent Publication No. 2015-187026.
The industrial vehicle described in the above publication employs an electromagnetic control valve to supply and drain hydraulic oil. When the hydraulic actuators are not being operated, the industrial vehicle is always determined to be in the off-load state. In the off-load state, the pressure in the hydraulic mechanism is released to the oil tank, so that the pressure in the hydraulic mechanism is low. If load is applied to the engine and the on-load period at that time is less than a predetermined time, the hydraulic mechanism is controlled to be in the on-load state to increase the pressure in the hydraulic mechanism. Thereafter, the industrial vehicle is returned to the off-load state to prevent an abrupt increase in the pressure, so that the engine is prevented from stalling.
Also, an engine may be prevented from stalling by using an electromagnetic proportional relief valve to maintain the pressure acting on the hydraulic pump (the pressure of the hydraulic oil) at a value less than or equal to a relief pressure. The relief pressure of the electromagnetic proportional relief valve is regulated by current flowing through the solenoid. The current flowing through the solenoid is controlled by a current controller in accordance with a current command calculated based on the current deviation, which is the difference between a target current value corresponding to the relief pressure and the current flowing through the solenoid (the actual current). The actual current is detected by a current detection circuit. Thus, if a wire is broken or instantaneous interruption occurs in the current detection circuit, the current flowing through the solenoid cannot be detected. In such a case, the current deviation is increased, and the current command is increased, accordingly.


Embodiments of the present disclosure provide systems and methods for estimating gain and phase error in a wireless transmitter. Embodiments of the present disclosure provide a gain and phase controller that uses a digital gain and phase estimator to jointly estimate both gain and phase. The forward and feedback signals of a wireless transmitter are digitized using analog to digital (ADC) converters. The digital signals are correlated with each other to dynamically extract gain and phase estimates of the loop. The gain and phase estimates are used to correct gain and phase errors in the wireless transmitter.

Wireless transmitters can be used to transmit wireless signals via a wireless medium, and wireless receivers can be used to receive and recover transmitted wireless signals from the wireless medium. During transmission over the wireless medium, wireless signals may be distorted and/or otherwise degraded. This distortion and/or degradation may occur as a result of channel impairments such as noise, signal interference, intersymbol interference, co-channel interference, etc. To mitigate the effects of any actual and/or perceived channel impairments, some wireless transmitters code and/or otherwise process information contained in the transmitted wireless signals.
The structure of wireless transmitters and/or wireless transmitted signals can vary based on the wireless communication standard supported by the host wireless communications device. For example, IEEE 802.11a defines an orthogonal frequency division multiplexing (OFDM) wireless transmission protocol that comprises eight 20 MHz spaced channels in the lower band (e.g., 5.15 gigahertz to 5.35 gigahertz) and five 20 MHz spaced channels in the upper band (e.g., 5.725 gigahertz to 5.825 gigahertz). The analog and radio frequency (RF) sections of a conventional wireless transmitter include a baseband analog filter, an up-conversion mixer, a power amplifier driver (PAD), external filters, and a power amplifier (PA) capable of driving an antenna.
Measurement and control of RF power is a critical consideration when designing a wireless transmitter. Various factors, such as regulatory requirements on power transmitted, network robustness, and the need to co-exist with other wireless networks demand that there be tight control of transmitted power. Moreover, precise RF power control can result in improved spectral performance and can save cost and energy in the transmitter's power amplifier. Wireless standards such as Worldwide Interoperability for Microwave Access (WiMAX) and Long Term Evolution (LTE) require the wireless transmitter to operate at a specified transmit power (e.g., 23 dBm), with some allowance for output power variation as a function of device variation and load conditions (e.g., +/−2 dB). For device operation in the field, lower output power causes degradation of the link quality between the mobile station and the base station due to reduced signal-to-noise ratio (SNR) and hence range of operation. Conversely, if the power varies above the rated power of the PA, the signal quality is degraded due to non-linearities in the PA. Increased non-linearity causes signal degradation in error vector magnitude (EVM) which degrades link quality, or spectral emissions mask (SEM), which may result in violation of specifications (e.g., emission specifications).
The transmit power at the antenna of a wireless transmitter can vary due to several factors. For example, differences in gain among stages in a wireless transmitter can impact transmit power. While the nominal gain of each of the stages in a wireless transmitter may be known, the analog components (e.g., filters, mixers, power amplifier drivers, and power amplifiers) of the transmitter can have a significant variation in gain from part to part, and temperature effects can also impact these gain differences. RF transmitters are designed to support a span of RF frequencies (e.g., in WiMAX 2300 MHz to 2700 MHz). The gain of RF stages can vary as a function of the frequency at which the device is operated.
In addition, external filters on the board can filter out transmit noise in adjacent bands. These filters are usually designed to have a flat gain in the intended passband of operation (e.g., 2500 to 2700 MHz), while suppressing noise in the neighboring bands (e.g., 2400 to 2500 MHz). These filters have gain variation (e.g., 2 to 3 dB) due to ripple in their intended pass band. Another important factor impacting PA gain variation is the load presented by the antenna to the PA, which can vary as a function of reflections seen at the antenna. To maintain a constant output power delivered by an RF transmitter to the antenna, some conventional transmitters use a feedback loop (e.g., using a power detector circuit and/or an RF coupler to couple a fraction of the power to the input of a power detector circuit).
Conventional transmitters have several deficiencies. For example, in a conventional transmitter having a feedback loop, the power detector transfer function is dependent on the signal characteristics of the particular signal being transmitted (e.g., a QPSK signal vs. an OFDM signal), and hence the power detector needs to be characterized over a variety of signal characteristics. A short sample of the output (e.g., 5 in duration) may not have the same statistical distribution of the signal over a full transmit frame. Hence, in order to sense the average output power the PA accurately, the power detector output needs to be averaged over a substantial portion of the transmit frame. In wireless standards such as LTE, the peak to average power ratio (PAPR) of the transmit signal is different for different periods in time, within one subframe. In systems that use an OFDM-like transmit signal (e.g., WiMAX-OFDM, LTE-SCFDMA), it is also desirable to have the output power accurately regulated during a cyclic prefix of the transmit signal to avoid inter carrier interference. Similarly, phase estimation of a transmit signal can be useful for some special transmitter architectures such as the Cartesian Feedback Amplifier or an advanced transmitter that is used in an uplink beam forming system. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present disclosure as set forth in the remainder of the present application with reference to the drawings.
What is needed therefore are systems, apparatuses, and methods for fast and accurate gain and phase error estimation for wireless transmitters.
Features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

Closed loop power control for a wireless transmitter


The present invention relates to liquid detergent compositions wherein the detergent active mixture of the compositions comprises 65 to 99% of a glyceroglycolipid compound having an amine linkage and 1 to 35% of a nonionic surfactant. Unexpectedly, applicants have discovered a synergy in the mixture of these surfactants which leads to enhanced detergency.

The present invention relates to detergent or personal product compositions comprising glyceroglycolipids having an amine linkage as surfactants or cosurfactants in the compositions. In particular, the glyceroglycolipid compounds are compounds having 1 to 4 saccharide units.
Natural glycolipids are known in the art and these structures have been elucidated. The term glycolipid refers to any of a class of lipids that, upon hydrolysis, yield a sugar (e.g., galactose or glucose), and a lipid (e.g. substituted glycerol group). One major class of these glycolipids belong to the glacier glycolipids, i.e., a glycolipids based around a glycerol frame structure. For example, the compound may have a sugar structure at one end of the glycerol structure instead of an --OH group and an ester linkage at one or both of the other --H groups that would normally be found on glycerol.
U.S. Pat. No. 3,729,461 to Pomeranz et al., for example, teaches mono- and di-galactosyl glyceride compounds isolated from wheat flour. On one end of the glycerol frame is found a sugar group (i.e., the mono- or di-saccharide group) and the two other OH groups normally found on a glycerol are esterified.
In Kobayashi et al., J. Chem Soc. Perkin., Trans. p. 101-103 (1989), there are again taught mono- and di-galactosyl diacylglycerols similar to those taught in Pomeranz et al. Again, there is a sugar group on one end and a mono- or diester where the remaining two --OH groups on a glycerol would normally be found.
Other ester functionalized mono- and diacyl galactosylglycerols are taught in Baruah et al., Phytochemistry, 22(8):1741-1744 (1983) and in U.S. Pat. No. 4,859,589 to Godfretsen et al.
Another example of a glyceroglycolipid is a compound having a sugar structure at one end of a glycerol structure instead of an --OH group and ether linkage on one or both of the other --OH groups that would normally be found on glycerol.
A glyceroglycolipid containing an ether linkage (where the --OH group on the glycerol would normally be found) is disclosed in Coulon-Moulec, Bull. Soc. Chem. Biol., 49(7):825-840 (1967); and in Alvarez et al., J. Lipid Res., 31(6):1073-1081 (1990).
These references are concerned, however, only with the synthesis of various lipid glycosides and contains absolutely no teaching or suggestion that glyceroglycolipids having an ether linkage can be used as surfactants or cosurfactants in detergent or personal product compositions.
EP No. 232,851-A (Assigned to National Starch) also appears to teach a glyceroglycolipid with an ether linkage. However, this reference is clearly concerned with compounds used as paper strength additives and neither teaches nor suggests that these compounds may be used as surfactants in detergent or personal wash compositions.
Other examples of glyceroglycolipids having an ether linkage are found in copending application filed on the same date as the present application.
William et al., Archives of Biochemistry and Biophysics, 195(1):145-151 (1979) teach certain alkyl bionamide compounds which are formed by linking aldobionic acids to an alkylamine through an amide bond. The compounds of the invention contain no such amide bond.
Scardera et al. (U.S. Pat. No. 5,023,008) teach a glycerol like frame structure with an amine group on one end. However, this structure has no sugar group on the other end.
Yet another example of a glyceroglycolipid might be a compound with a sugar group on one end of the glycerol structure instead of an --OH group and an amine group (i.e., NRR.sup.1) at one or both of the other --OH groups normally found in glycerol, and in particular amines wherein one or both of R and R.sup.1 are alkyl chains sufficient in length to confer surfactancy properties on the molecule.
U.S. Pat. No. 4,011,169 to Diehl et al., for example, teach enzyme containing compositions comprising certain aminated polysaccharides as stabilizing agents for enzymes. It is clear from this reference that the polysaccharides used have at the very least 5 or more saccharide units and, preferably, well over 100 (the application notes at column 7, lines 50-52, that natural polysaccharides smaller than this are rare). Further, there is a limitation to the amount of elemental nitrogen in the compound and it seems that compounds with fewer saccharide units would not meet this limitation.
U.S. Pat. No. 3,931,148 to Langdon teaches hydroxyalkylamino glycoside compounds which appear to be similar to those of the invention. However, there appears to be no teaching or suggestion that these compounds can be used in the specifically claimed detergent and personal product compositions of the invention.
Finally, because the compounds of the invention are derived from naturally occurring carbohydrates, the use of these compounds can provide a source of renewable raw materials that are synthetically versatile and environmentally friendly.
Accordingly, it is an object of this invention to provide novel surfactants and cosurfactants derived from carbohydrates and the use of such compounds in detergent and personal product compositions.

Compositions comprising glyceroglycolipids having an amine linkage as a surfactant or cosurfactant

Lever Brothers Company, Division of Conopco, Inc.


A dynamic transaction card that includes a transaction card having a number of layers, each of which may be interconnected to one another. For example, a dynamic transaction card may include an outer layer, a potting layer, a touch sensor layer, a display layer (including, for example, LEDs, a dot matrix display, and the like), a microcontroller storing firmware, Java applets, Java applet integration, and the like, an EMV chip, an energy storage component, one or more antenna (e.g., Bluetooth antenna, NFC antenna, and the like), a power management component, a flexible printed circuit board (PCB), a chassis, and/or a card backing layer.

Transaction cards, such as credit cards or debit cards, have limited capabilities. Transaction cards may include a magnetic stripe capable of storing data by modifying the magnetism of magnetic particles on the stripe. The magnetic stripe may include several tracks of data (typically track 1, track 2, and track 3) storing data about the transaction card owner or data about the account number or expiration date of an associated account.
Transaction cards may also include EuroPay-MasterCard-Visa ("EMV") cards having an integrated circuit, or EMV chip. The EMV chip in an EMV card may communicate with EMV-compliant terminals to conduct secure transactions. For example, information may be exchanged between the card and the terminal via the EMV chip, which may also require the entry of a PIN to complete a transaction. The EMV chip may dynamically store data previously stored on a magnetic strip, allowing for increased security associated with transaction cards.
However. EMV and magnetic stripe cards have limited capabilities, such as limited display capabilities, limited transaction capabilities, and limited processing capabilities. These and other drawbacks exist.

Dynamic transaction card for visual impairment and methods thereof


A method of testing a digital-to-analog or analog-to-digital converter including coarse and fine voltage dividers corresponding respectively to more and less significant bits of the digital signal. Reference input signals are applied corresponding to a first selection of the fine resistor elements with each selection of the coarse resistor elements in succession, corresponding output signals of the converter are measured, and differential non-linearity values and integral non-linearity values for these selections of fine and coarse resistor elements are calculated. Similar measurements and calculations are made for a first selection of the coarse resistor elements with each of the selections of the fine resistor elements in succession. Differential non-linearity values and integral non-linearity values for other combinations of the coarse resistor elements with the fine resistor elements are then calculated using combinations of the calculated differential non-linearity values and the calculated integral non-linearity values.

The present invention is directed to a method of testing digital-to-analog and analog-to-digital converters and to an integrated circuit including a digital-to-analog converter or an analog-to-digital converter that is adapted for testing the converter.
Digital-to-analog converters ('DACs') convert a digital input signal to an analog output signal. Analog-to-digital converters ('ADCs') convert an analog input signal to a digital output signal. One technology that is used for DACs and ADCs, known as resistor ladder, uses a set of repetitive resistor elements across which a reference voltage is applied to form voltage or current dividers. The successive taps of the divider generate successive stepwise varying voltages. In a DAC, the taps are selected by switches controlled as a function of the digital input signal to generate the DAC analog output signal. A successive approximations register ADC may include a resistor ladder DAC, to which a digital signal is applied and adjusted until the analog output of the resistor ladder DAC becomes equal to the analog input signal to be converted, the digital signal applied to the resistor ladder DAC then becoming the output of the ADC.
The DAC or ADC may include a single set of repetitive resistor elements of identical resistance. However, the DAC or ADC may include two sets of repetitive resistor elements, the resistor elements of one set having a different resistance from the elements of the other set. The coarse steps defined by the resistor elements of one set are larger than the fine steps defined by the resistor elements of the other set. The taps of the fine step set are selected by less significant bits of the digital input signal in order to interpolate between the voltages at the taps of the coarse step set, which are selected by more significant bits of the digital input signal. The DAC or ADC may even include more than two such sets of repeating resistor elements of respective different resistances. A DAC or ADC of this kind is referred to as a coarse-fine DAC or ADC.
The accuracy and functionality of such circuits requires testing at design verification stages, system verification stages and also during production of integrated circuits ('ICs') including the DACs or ADCs. Testing such mixed-signal circuits presents difficulties and, in particular is both expensive and time-consuming. To facilitate testing, the ICs including the DACs or ADCs may include built-in self-test ('BIST') features enabling stimulus generation and measurements to be performed in the IC. The main purpose of BIST is to reduce the complexity, and thereby decrease the cost of the tests and to reduce reliance upon external (pattern-programmed) test equipment. BIST features reduce test-cycle duration and reduce the complexity of the test/probe setup, by reducing the number of input/output ('I/O') signals that must be driven or examined under tester control. Both lead to a reduction in the cost of automated test equipment ('ATE') service.

Method of testing digital-to-analog and analog-to-digital converters


A toner image forming method is disclosed. In the method a photoreceptor having a shorter circumferene than length of a toner image to be transferred is used. The photoreceptor is exposed with an exposing light according to an image information to form a latent image and is processed with a step of removing residual toner particles on a non-image portion on the photoreceptor and developing a latent image on the photoreceptor with toner particles at a same time or successively to form the toner image. The toner particles have a specral characteristics which allows tho exposing light to pass through the toner particles. The method allows to provide a compact copying apparatus.

This invention relates to an image forming method using an electrostatic latent image and, more particularly, to an image forming method in which transparent toner, through which exposing light can pass, is used.
Recently, a compact copier has been developed and development is proceeding briskly. In a series of image forming means in which a photoreceptor with a small circumference is used, a compact image recording apparatus is proposed in which the residual toner is electrically removed from the photoreceptor in the developing area. This type of image forming apparatus is disclosed in Japanese Patent Publication Open to Public Inspection No. 133179/1988, 133180/1988, and 133171/1988.
However, problems stemming from residual toner on the photoreceptor can be found, such as uneven charging in the charging process, light decay in the exposure process, and ghosting, and color muddiness in the image forming process. Because the circumference of the photoreceptor is shorter than the length of the toner image, a portion of the photoreceptor's circumference Is used twice to form a toner image and some portions of a toner image are periodically printed. For that reason, part of the toner is left on the photoreceptor without being cleaned off and the residual toner particles on the circumference of the photoreceptor obstruct image formation.
Especially when a coherent laser beam is used to expose an image, a defective image tends to appear in the portion shaded by opaque residual toner. Especially when the residual toner is scattered in spots, image quality is remarkably damaged.
Photoconductive semiconductors which have been used in conventional electrophotography are; inorganic photoconductive materials such as selenium, zinc oxide, cadmium sulfide, and cadmium selenide; photoconductive pigments such as phthalocyanine, copper phthalocyanine, cobalt phthalocyanine, and nickel phthalocyanine; and organic photoconductive materials such as poly-N-vinyl carbazole, anthracene, and triallyl amine derivative. These compounds are dispersed in the binder resin to form a photoreceptor. In order to rapidly make a plurality of copies in a short time, a highly sensitive photoreceptor which has very rapid light decay characteristics was developed. For that reason, a photoreceptor has been used which has high sensitivity in the low magnitude of light exposure region, wherein its light decay is sensitive even in low magnitude of light exposure and its light decay curve sharply declines in the low illuminance region.
It is known that there are two methods of forming a latent image on a photoreceptor by image exposure. One is the positive exposure system in which the non-image area is exposed to erase electrical charge on the photoreceptor and a latent image is formed. The other is the negative exposure system in which the image area is exposed to erase electric charge on the photoreceptor.
The digital image forming method is conveniently used to convert images freely, adjust images, and send images by facsimile. The light distribution of the spot of light which is used in dot exposure of the digital image forming method, is similar to a normal distribution curve in which the peak is the center of the spot, even though the spot of light is modulated by the method of pulse-duration modulation. The light energy distribution curve has long gentle slopes on both sides with wave patterns of light intensity caused by diffraction. In the case of the positive exposure system, these wave patterns are so remarkable that they can be the cause of photographic fog. That is the reason why the negative exposure system is suitable for dot exposure. However, it is necessary for the negative exposure system to be combined with reversal development and toner must be prepared which can be electrostatically charged with the same polarity as the photoreceptor. When dot exposure is used, the photoconductive semiconductor of the a photoreceptor must have a light decay curve which is suitable for the above-described spot of light's distribution curve.
Accordingly, when low magnitude of exposure, in the gentle slope portion of the spot of light's distribution curve, wherein the spot of light is for erasing electrostatic charge of the photoreceptor, is picked up by the electrostatic charge erasing action in the region of low magnitude of exposure, the electric potential distribution curve of the formed latent image of a spot becomes funnel-shaped, with a broadly extended edge. Therefore, the peripheral portion of the image developed by the toner becomes blurred and fog also occurs.
Accordingly a photoreceptor must be designed to meet the requirements to form a clear peripheral image.
When the subsequent image is developed, the potential of the photoreceptor surface is not reduced to the non-development level because of absorption of light by the deposited toner on the photoreceptor which was not transferred to a transfer paper when the previous image was developed. Image density is decreased at the portion where the potential is not reduced to the non-development level.


The invention relates to a switch box for producing freely selectable optical connections between the LWGs of incoming optical cables and the LWGs of outgoing optical cables by means of optical shunting lines. The production of any connection is made possible in an ordered and certain way in an arrangement in which LWG groups of the incoming optical cables are connected to a first group of adjacent termination units, LWG groups of the outgoing optical cables are connected to a second group of adjacent termination units, the individual LWGs of the incoming and of the outgoing cables are connected to optical plug connector elements provided on the terminal units, the shunting lines are connected on both sides to mating connector elements, and excessive lengths of the shunting lines not required for producing a connection are stored in storage elements.

Such an arrangement is known from No.EP-A 250 900. In this arrangement the shunting lines are inseparably spliced at one end to the individual light waveguides of the LWGs of the outgoing optical cables terminating in the termination units. The connector element of the free end of the shunting lines can be connected as desired to plug connector elements of the LWGs of the incoming optical cables which also terminate in the termination units. The shunting lines are freely suspended. They form loops corresponding to the excessive length which is not necessary for a switching path.
In particular in building up a LWG local area network switch, boxes must be available by means of which a multiplicity (for example 100) of LWGs of incoming optical cables (main cable) can be connected in a free combination possibility to a usually larger number (for example 200) of LWGs of outgoing optical cables. It must be possible to change the connections as frequently as posssible.
Such connections are customarily produced by means of the shunting lines. However, the shunting lines are subject to considerable mechanical stresses. It is particularly difficult to prevent damage in those cases when the shunting lines are provided in a disordered and freely suspended manner.
Moreover, having a number of freely suspended disordered shunting lines impedes the subsequent connection activities.
When a spliced connection of the shunting lines to the LWGs of an optical cable is made on one side, it is necessary to make a new splice place when it is required to exchange the shunting line. As a result, the length of the LWGs of the optical cables is automatically reduced. It is not possible to perform such after-splice-processes unrestrictedly and, moreover such after-splice-processes adversely affect the substance of the optical cables which are very expensive.

Switch box for producing freely selectable optical plug connections