A content transmission device for transmitting content, whose copying is controlled, includes an authentication section for performing an authentication procedure between the content transmission device and a content receiving device, a first copy-control-information processing section for processing first copy control information describing copy control information concerning the content, a second copy-control-information processing section for processing second copy control information including content information different from the first copy control information, and a content transmission section for generating and transmitting, to the content receiving device, a packet including a header including the first copy control information and the second copy control information, and a payload obtained by encrypting the content with a predetermined content key.

1. Field of the Invention
The present invention relates to content transmission devices and content transmission methods for transmitting content, which is encrypted for copyright protection or other purposes, and computer programs used therewith. In particular, the present invention relates to a content transmission device and method for use in executing an encrypted content transmission procedure between DTCP (Digital Transmission Content Protection) compliant devices, and to a computer program used therewith.
More specifically, the present invention relates to a content transmission device and method for transmitting content in a form in which attribute information and copy control information concerning the content are inserted in each packet, and a computer program used therewith. In particular, the present invention relates to a content transmission device and method for transmitting content in a form in which attribute information and copy control information concerning the content are inserted into each packet in a form that is not dependent on the format of the content, and a computer program used therewith.
2. Description of the Related Art
With widespread use of information technology, most audio-visual (AV) content has become digitized, and digital content recording/playback media, such as compact discs (CDs) and digital versatile discs (DVDs), have become widely used. Also, recently, devices for digitally recording content, such as hard disk drive (HDD) recorders and DVD recorders, have started to be used even in homes. In addition, distribution and delivery services of content such as video and audio via networks have become popular. Accordingly, content is delivered between remote terminals via a network without transfer of a medium such as a CD or a DVD.
Obviously, in the case of Japan, in Japanese Copyright Law, AV content can be protected as a copyrighted work from unauthorized use such as unauthorized duplication and alteration. In Japanese Copyright Law, under Article 30, it is permissible for a user to reproduce a work forming the subject matter of copyright for the purpose of personal use, family use or other similar uses within a limited circle, while, under Article 49(1), it is prohibited to use a reproduction except for private use.
However, for digitized content, unauthorized manipulations, such as copying and alteration, can be easily performed. Accordingly, not only from a viewpoint of development of laws but also from a technical viewpoint, protection against unauthorized use is necessary while permitting personal or family use of content. In particular, in Japan, with the approaching cessation of analog terrestrial television broadcasting in 2011, replacement of digital terrestrial television receivers for analog broadcast television receivers is rapidly proceeding. Accordingly, for digitalization of AV content in homes, it is very necessary to technically realize content protection.
Many technologies intended to protect copyright of digital content have been developed. For example, industry standards concerning protection of digital transmission content include the Digital Transmission Content Protection (DTCP) developed by the Digital Transmission Licensing Administrator (DTLA). DTCP prescribes a mechanism for content transmission in a copyright-protected form (see, for example, Digital Transmission Content Protection Specification Volume 1 (Informational Version), Revision 1.4) (http://www.dtcp.com/).
DTCP includes provisions concerning an authentication protocol in content transmission between devices and a transmission protocol for encrypted content. In brief, a DTCP compliant device may not send, to the exterior, in an uncompressed state, easy-to-manipulate compressed content complying with a standard such as MPEG (Moving Picture Experts Group). Key exchange necessary for decrypting encrypted content is performed in accordance with a predetermined mutual authentication and key exchange algorithm, that is, the Authentication and Key Exchange (AKE) algorithm. In addition, the range of devices which use AKE commands to exchange keys is restricted.
A server (DTCP_Source) that is a content provider and a client (DTCP_Sink) that is a content receiver share a key after performing an authentication procedure by transmitting and receiving AKE commands, and use the key to encrypt a transmission path before performing content transmission. Accordingly, it is difficult for a client to acquire an encryption key unless the client and the server succeed in mutual authentication with each other. Thus, it is difficult for an unauthorized client to enjoy content. Moreover, by limiting the number and range of devices that can transmit and receive AKE commands, use of the content can be limited to personal or family use according to Japanese Copyright Law.
DTCP primarily makes prescriptions concerning transmission of digital content on a home network in which an IEEE (Institute of Electrical and Electronics Engineers) 1394 bus is used as a transmission path. However, recently, as is typified by the Digital Living Network Alliance (DLNA), there has been an increasing trend toward distributing digitized AV content in a home by using an Internet Protocol (IP) network. Accordingly, development of DTCP technology for IP networks, that is, DTCP mapping to IP (DTCP over Internet Protocol), is in progress. Regarding many home networks, it is pointed out that unauthorized copying and alteration of content may occur when the home networks are connected to external IP networks such as the Internet via routers. It is an urgent need that, by establishing DTCP-IP technology, flexible and efficient use of the digital content is achieved by using an IP network while protecting digital content.
Basically, DTCP-IP is included in DTCP standards and is similar to DTCP technology, and is a technology in which DTCP technology is implanted in the IP network. However, DTCP-IP differs from the original DTCP prescribed on the IEEE 1394 basis in that DTCP-IP uses an IP network and that DTCP-IP uses protocols such as the Hyper Text Transfer Protocol (HTTP) and the Real Time Protocol (RTP). In addition, in DTCP-IP, various types of devices, mainly such as personal computers, are connected to the IP network, so that there is a high possibility that data may be easily sniffed and altered. Accordingly, DTCP-IP prescribes a further method for transmitting content through a network while protecting the content (see, for example, DTCP Volume 1 supplement E Mapping DTCP to IP (Informational Version), Revision 1.1 (http://www.dtcp.com/).
Content transmission complying with DTCP-IP is described below. When content transmission is performed by using the HTTP protocol between source and sink devices complying with DTCP-IP, encrypted communication is performed while changing a content key in the middle of transmission of a very long byte stream such as a Transmission Control Protocol (TCP) stream, and a content key confirmation procedure is performed when an encrypted content decrypting process and another content process are implemented. In addition, a TCP connection is established for each of procedures of mutual authentication and key exchange (AKE), content transmission, and content key confirmation.
Specifically, when an AKE procedure is successfully performed, the DTCP_Source device and the DTCP_Sink device can share authentication key Kauth. The DTCP_Source device generates seed key Kx, which serves as a content key seed, uses authentication key Kauth to encrypt the generated key, and sends the encrypted key to the DTCP_Sink device. After using a random number to generate nonce Nc, the DTCP_Source device generates content key Kc on the basis of seed key Kx, nonce Nc, and an extended encryption mode indicator (E-EMI) representing an encryption mode. After using content key Kc to encrypt content requested by the DTCP_Sink device, the DTCP_Source device transmits, to the sink device, on a TCP stream, packets in each of which a header includes the encrypted content, nonce Nc, and the E-EMI. By extracting nonce Nc and the E-EMI from the TCP stream, the DTCP_Sink device can use the extracted items and key Kx to similarly calculate content key Kc, and can decrypt the encrypted content.
In such a manner, in DTCP-IP, by performing authentication between DTCP compliant devices, sharing a key between the devices which have successfully completed DTCP authentication, and performing encryption and decryption when content is transmitted, a content transmission technique which is also secure on an IP network and which prevents content from being sniffed and altered in the middle of a transmission path can be provided.
For example, when content is requested in accordance with an HTTP procedure, the DTCP_Source and DTCP_Sink devices respectively serve as an HTTP server and as an HTTP client to create a TCP/IP connection for HTTP, and initiate content transmission. The HTTP client requests content on an HTTP server in an operating process which is identical to that of normal HTTP. In response thereto, the HTTP server sends back the requested content as an HTTP response. The DTCP_Source uses content key Kc to encrypt the content requested by the DTCP_Sink, and transmits, on a TCP stream, packets which each include a header including a payload formed by the encrypted content, nonce Nc, and an E-EMI.
In addition, when the same encryption key is continuously used for the entirety of a very long stream, a possibility that the key may be decrypted increases. Accordingly, the DTCP_Source device updates content key Kc by incrementing nonce Nc by one in units of 128-MB content. Since, in the middle of a byte stream, nonce Nc is greatly changed, a content key confirmation procedure is necessary, and, for the DTCP_Source device, the DTCP_Sink device performs a procedure for confirming nonce Nc.
In addition, in a content transmission system for supporting copyright protection, it is necessary to specify a content attribute concerning content protection. In DTCP-IP, by using two mechanisms, that is, an E-EMI and Embedded CCI which are described in a protected content packet (PCP) header, transmission of copy control information associated with content can be realized.
Embedded CCI is copy control information that is transmitted as part (i.e., in a form embedded in a PCP payload) of a content stream to be encrypted. Although many content formats include fields allocated for CCI in a form associated with a stream, a CCI definition and format are unique for each content format. Embedded CCI is interpreted as having a meaning such as "Copy Never", "Copy One Generation", "No More Copies", or "Copy Free". Since tampering of a content stream is implementation of false decryption, the integrity of embedded CCI can be guaranteed.
E-EMI enables easy access and realizes security by representing copy control information concerning the content stream in the PCP header. By locating an E-EMI in an easily accessible location of a particular bit position of a PCP header in a plaintext state, the device can immediately identify the copy control information of the content stream, whereby it is not necessary to extract embedded CCI by decrypting the content transmission format. E-EMI is important to enable the realization of a bit-stream-storage device that is unable to recognize and decode a special content format such as that of digital VCR.
A proper source device complying with DTCP-IP selects a correct encryption mode in accordance with the characteristics of a content stream, and sets an E-EMI on the basis of the selected encryption mode. Also, a proper sink device selects a correct encryption mode which is specified by an E-EMI in a PCP header. Since the E-EMI is used for generating content key Kc, tampering of the E-EMI causes mismatch between content keys Kc in encryption and decryption modes. Thus, content decryption fails, thus maintaining security.
FIG. 31 illustrates an internal structure of a PCP header (see, for example, DTCP Volume 1 Supplement E Mapping DTCP to IP (Informational Version), Revision 1.1, V1SE.4.22 Modification to 6.3.3 Content Encryption Formats). In this structure, an E-EMI is a 4-bit field describing an encryption mode. Values of the E-EMI correspond to types of copy control information. The definitions of bit values are shown in the following table (see, for example, DTCP Volume 1 Supplement E Mapping DTCP to IP (Informational Version), Revision 1.1, V1SE.4.7 Modifications to 6.4.2 Encryption Mode Indicator (EMI)). In the table, nine E-EMI values unused are reserved for future extension.
TABLE 1E-EMIEncryptionValueModeCopy Control Information1100A0Copy never (CN)1010B1Copy-one-generation (COG) [Format-cognizant recording only]1000B0Copy-one-generation (COG) [Format-non-cognizant recording permitted]0110C1Move mode (Audiovisual)0100C0No-more-copies (NMC)0010D0Copy-free with EPN asserted (CF/EPN)0000N.A.Copy-free (CF)
As described above, the PCP header includes an E-EMI specifying the encryption mode and copy control information of content. These parameters are insufficient as copy control information for the purpose of content protection. That is, necessary copy control information may not be written in the 4-bit E-EMI field. For example, pieces of output control information, such as a parameter (Analog Protection System (APS)) concerning analog output control of content and a parameter (Image Constraint Token (ICT)) concerning a picture size in an output mode, are treated as elements of copy control information in DTCP. In this specification, the output control information is additional or extended copy control information and is also called "super-extended copy control information". The pieces of copy control information are not written in the E-EMI. Thus, it is only possible to embed the pieces of copy control information as part of Embedded CCI.
Also, as one of copy control functions in DTCP, the "Cognizant Function" in which, instead of controlling copying simply in accordance with an E-EMI, when a device correctly recognizes the format of content and Embedded CCI (that is, in a "cognizant" case), a content processing method is controlled in accordance with the Embedded CCI is provided. By using the cognizant function, it is necessary to compare the E-EMI extracted from the PCP header and the Embedded CCI extracted from the PCP payload. Relationship between the Embedded CCI and the EMI are shown in the following table.
TABLE 2Embedded-CCIE-EMICFCF/EPNNMCCOG-AVCOG-AudioCNA0AllowedAllowedAllowedAllowedAllowedAllowedB1AllowedAllowedProhibitedAllowedAllowedProhibitedB0AllowedAllowedProhibitedAllowedProhibitedProhibitedC1ProhibitedProhibitedAllowedProhibitedProhibitedProhibitedC0AllowedAllowedAllowedAllowedAllowedProhibitedD0AllowedAllowedProhibitedProhibitedProhibitedProhibitedN.A.AllowedProhibitedProhibitedProhibitedProhibitedProhibited
However, DTCP-IP only prescribes that Embedded CCI is transmitted as part of a content stream. In the current DTCP-IP, there is no provision concerning an Embedded CCI configuration method other than a provision (see, for example, Digital Transmission Content Protection Specification Volume 1 (Informational Version), Revision 1.4, Appendix B DTCP_Descriptor for MPEG Transport Streams) in which a DTCP descriptor corresponding to Embedded CCI is inserted concerning MPEG transport streams. Although fields for transmitting an CCI in a form associated with a stream are allocated in many content formats including an MPEG format, it is actual that the definition and format of CCI are unique or differs for each content format.
Embedding of copy-control information in a PCP payload is insertion of copy-control information in content. Thus, inevitably, the description method of the copy control information is dependent on a content format and differs for each format. Therefore, when AV content is transmitted in encrypted form complying with DTCP-IP, it is necessary for the DTCP_Source device to perform transmission while changing copy control information for each format, and it is necessary for the DTCP_Sink device to prepare software or hardware for analyzing copy control information for each format. This results in an increase in device costs. In addition, when copy control information is embedded in an encrypted PCP payload, a problem occurs in that, at a receiving end, the copy control information is not extracted unless it is decrypted.

Content transmission device, content transmission method, and computer program used therewith


An input signal having a logic low level at a first voltage and a logic high level at a second voltage is received by a Schmitt trigger. A voltage generator outputs a reference voltage generated from a third voltage that is higher than the second voltage. A first transistor coupled between the third voltage and a power supply node of the Schmitt trigger is biased by the reference voltage to apply a fourth voltage to the power supply node of the Schmitt trigger that is dependent on the reference voltage. The reference voltage has a value which causes the fourth voltage to be less than or equal to the second voltage. A second transistor coupled between the input signal and the input of the Schmitt trigger circuit is also biased by the reference voltage to control the logic high level voltage of the input signal at the Schmitt trigger.

Reference is made to FIG. 1 which shows a simplified block diagram of an integrated circuit device 10. The integrated circuit device 10 includes a central region 12, also referred to a core region, including functional integrated circuits (of either or both analog or digital type; for example, amplifiers, filters, oscillators, logic circuits, processors, etc.). The integrated circuit device 10 further includes a peripheral region 14 including input/output (I/O) circuits. The integrated circuit device 10 interfaces with the outside environment through electrical connection pads (or pins) 16 which are arranged in the peripheral region 14. The pads 16 may, for example, include pads for connection to an external power supply (such pads including, for example, positive/negative supply voltage pads 16s and ground/reference voltage pads 16g) as well as pads associated with the transmission/reception of analog and/or digital signals (such pads including, for example, input/output pad 16tr for importing and exporting signals). The I/O circuits of the peripheral region 14 include a transmit (TX) circuit 18 which interfaces the functional integrated circuits of the central (core) region 12 with the input/output pad 16tr, and a receive (RX) circuit 20 which interfaces the input/output pad 16tr with the functional integrated circuits of the central (core) region 12.
The TX and RX circuits 18 and 20 may, for example, be powered from a power supply domain that is unique to the peripheral region 14. In other words, the I/O circuits of the peripheral region 14 may utilize supply voltage levels which are different from the supply voltage levels used by the functional integrated circuits of the central (core) region 12. As an example of this, the power supply domain for the peripheral region 14 may be a 3.3V/ground domain while the power supply domain for the central (core) region 12 may instead be a 1.8V/ground domain (or 1.2V/ground domain). The positive/negative supply voltage pad 16s and ground/reference voltage pad 16g may thus be connectable to a power supply (external) providing the 3.6V/ground voltages, with the TX and RX circuits 18 and 20 receiving their power (Vdde and Gnde) from the pads 16s and 16g. The 1.8V/ground voltages used by the central (core) region 12 may be supplied in a similar manner from off-chip (in which case further positive/negative supply voltage pads and ground/reference voltage pads would be needed in the peripheral region 14—not shown), but in a more common case the power supply (Vdd and Gnd) for the central (core) region 12 is generated on-chip by a voltage regulator (Vreg) circuit which is powered from the pads 16s and 16g.
Reference is now made to FIG. 2 which shows a circuit diagram for an RX circuit 20. The RX circuit 20 includes a Schmitt trigger circuit 21. The Schmitt trigger 21 has a first inverter stage including PMOS transistors P1 and P2 and NMOS transistors N1 and N2 that are coupled in series with each other through their source-drain paths. The source of transistor P1 is coupled to the high supply voltage Vdde. The drain of the transistor P1 is coupled to the source of the transistor P2. The drain of the transistor P2 is coupled to the drain of the transistor N2. The drains of the transistors N2 and P2 correspond to the output node 24 of the first inverter stage of the Schmitt trigger 21. The source of the transistor N2 is coupled to the drain of the transistor N1. The source of the transistor N1 is coupled to the low supply voltage Gnde. The gate terminals of the transistors P1, P2, N1, N2 are all coupled to receive an input signal In at an input node 22 from the pad 16tr. Although not specifically illustrated, the body terminal of transistor P1 is coupled to Vdde, the body terminal of transistor P2 is coupled to the source of transistor P2, and the body terminals of the transistors N1 and N2 are coupled to Gnde.
The Schmitt trigger 21 further includes feedback circuitry formed by PMOS transistor P3 and NMOS transistor N3. The gate electrodes of the PMOS transistor P3 and the NMOS transistor N3 are coupled together at the output 24 of the first inverter stage (where the output 24 is at the drain terminals of the transistors P2 and N2). The drain terminal of the transistor P3 is coupled to Gnde. The source terminal of the transistor P3 is coupled to the node at the series connection of the drain terminal of the transistor P1 and the source terminal of transistor P2. The drain terminal of the transistor N3 is coupled to Vdde. The source terminal of the transistor N3 is coupled to the node at the series connection of the source terminal of the transistor N2 and the drain terminal of transistor N1. Although not specifically illustrated, the body terminal of the transistor P3 is coupled to the source of transistor P3 and the body terminal of the transistor N3 is coupled to Gnde.
The Schmitt trigger 21 has a second inverting stage including PMOS transistor P4 and NMOS transistor N4 coupled in series with each other through their source-drain paths. The gate terminals of the transistors P4 and N4 are coupled to the output 24 of the first inverter stage. The source terminal of the transistor P4 is coupled to Vdde. The drain terminal of the transistor P4 is coupled to the drain terminal of the transistor N4 at the output node 26 of the second inverting stage. The source terminal of the transistor N4 is coupled to Gnde. Although not specifically illustrated, the body terminal of the transistor P4 is coupled to Vdde and the body terminal of the transistor N4 is coupled to Gnde.
The Schmitt trigger 21 further has a third inverting stage including PMOS transistor P5 and NMOS transistor N5 that are coupled in series with each other through their source-drain paths. The gate terminals of the transistors P5 and N5 are coupled to the output 26 of the second inverter stage. The source terminal of the transistor P5 is coupled to Vdde. The drain terminal of the transistor P5 is coupled to the drain terminal of the transistor N4 at the output node 28 of the third inverting stage (which is also where the output signal Out of the Schmitt trigger 21 is generated). The source terminal of the transistor N5 is coupled to Gnde. Although not specifically illustrated, the body terminal of the transistor P5 is coupled to Vdde and the body terminal of the transistor N5 is coupled to Gnde.
The Schmitt trigger 21 functions in the following manner: when the input In has a logic high state, the first inverting stage brings the output 24 at the drains of transistors P2 and N2 to Gnde. This is because the voltage of the logic high state causes the transistors P1 and P2 to be nonconducting and causes the transistors N1 and N2 to be conducting. With transistors N1 and N2 conducting, the drain of the transistor N2 is electrically connected to Gnde through the source of the transistor N1. The second inverting stage receives the Gnde voltage from the drains of the transistors P2 and N2 at the gate terminals of the transistors P4 and N4. This Gnde voltage causes the transistor P4 to be conducting and the transistor N4 to be nonconducting. As a result, the voltage at node 26 is brought to Vdde. The third inverting stage receives the Vdde voltage from the drains of the transistors P4 and N4 at the gate terminals of the transistors P5 and N5. This Vdde voltage causes the transistor P5 to be nonconducting and the transistor N5 to be conducting. The output terminal 28 of the Schmitt trigger 20 is therefore electrically connected to Gnde through the source of the transistor N5. Thus, when the input In of the Schmitt trigger 21 receives the voltage at logic high state, the output Out of the Schmitt trigger 21 is at the voltage Gnde for the logic low state. In like manner, when the input In has a voltage at the logic low state, the first inverting stage brings the output 24 at the drains of transistors P2 and N2 to the voltage Vdde. This is because the voltage at the logic low state causes the transistors P1 and P2 to be conducting and the transistors N1 and N2 to be nonconducting. The drain of the transistor P2 is therefore electrically connected to Vdde through the source of the transistor P1. The gate terminals of the transistors P4 and N4 are therefore connected to Vdde. The transistor P4 is thus nonconducting and the transistor N4 is conducting. As a result, the voltage at the output 26 is brought to Gnde. In response, the gate terminals of the transistors P5 and N5 are therefore connected to Gnde. This causes the transistor P5 to be conducting and the transistor N5 to be nonconducting. The output terminal 28 of the Schmitt trigger 21 is therefore connected to Vdde through the source of the transistor P5. Thus, when the input In of the Schmitt trigger 21 receives the voltage at the logic low state, the output Out of the Schmitt trigger 21 is at the voltage Vdde for the logic high state.
Hysteresis is introduced to the Schmitt trigger 21 by means of the transistors P3 and N3 of the feedback circuit. Consider, for example, the case where the input In is at the voltage for the logic low state and the output Out is at the voltage Vdde for the logic high state. The voltage of the logic low state for the input In causes transistors P1 and P2 to be conducting while causing transistors N1 and N2 to be nonconducting. In this case, the drain terminals of the transistors P2 and N1 are at Vdde. This causes transistor N3 to be conducting and transistor P3 to be nonconducting. Because the circuit 21 is formed using conventional CMOS technology, transistor N1 exhibits a body biased effect as its bulk to source voltage is not zero. Thus, transistors N1 and N2 have different threshold voltages from each other. In particular, the threshold voltage of the transistor N2 is increased with respect to the threshold voltage of the transistor N1. Now, if the voltage of the input signal In begins to rise from the logic low state, transistor N1 turns on first when the voltage of the input signal In reaches the threshold voltage of transistor N1. Transistor N2, however, does not turn on as its threshold voltage is higher due to the body biased effect. Hence, the output of the first inverter remains at the voltage Vdde for the logic high state. Transistors N1 and N3 form an inverter having a feedback effect with transistor N3 acting as the pull up device. The source of the transistor N2 is thus connected to the voltage Vdde minus the threshold voltage of transistor N3. As the voltage of the input signal In rises and becomes greater than the threshold voltage of transistor N1, the voltage at the source of transistor N2 begins to fall. When the gate to source voltage of transistor N2 becomes greater than the threshold voltage of transistor N2, then transistor N2 turns ON. The voltage on drain of the transistor N2 begins to decrease, thereby causing the transistor N3 to be less conductive. At this point, the voltage on the drain of the transistor N2 rapidly transitions to the voltage Gnde. The voltage level for the rising input signal In at which the drain of the transistor N2 goes to Gnde is referred to as the high threshold (VIH) voltage value for the circuit 21. This high threshold voltage is set by the width/length (W/L) ratios of transistors N1 and N3.
Because the drains of the transistors N1 and N2 are now at the voltage Gnde, the transistor N3 is entirely nonconducting and the transistor P3 is conducting. In this case, the drain terminals of the transistors P2 and N2 are at Gnde. Because the circuit 21 is formed using conventional CMOS technology, transistor P2 shows a body biased effect as its bulk to source voltage is not zero. Thus, transistors P1 and P2 have different threshold voltages from each other. In particular, the threshold voltage of transistor P2 is increased with respect to the threshold voltage of the transistor P1. As the voltage of the input signal In begins to fall from the voltage of the logic high level, transistor P1 turns on first when the voltage of the input signal In reaches the threshold voltage of transistor P1. Transistor P2 does not turn on as its threshold voltage is higher than the threshold of transistor P1 due to the body biased effect. Hence, the output of the first inverter remains at the logic low level voltage Gnde. This causes transistor P3 to be conducting and transistor N3 to be nonconducting. The transistors P3 and P1 form an inverter having a feedback effect, with transistor P3 acting as the pull down device. When the voltage of the input signal In decreases to a point where transistor P1 begins to conduct, the voltage on the source of transistor P2 begins to rise. When the gate to source voltage of transistor P2 is greater than the threshold voltage of transistor P2, then the transistor P2 turns ON. The voltage on the drain of the transistor P2 begins to increase, causing the transistor P3 to be less conductive. At this point, the voltage on the drain of the transistor P2 rapidly transitions to the voltage Vdde. The voltage level of the input signal In at which the drain of the transistor P2 goes to Vdde is the low threshold (VIL) voltage value for the circuit 21. This low threshold voltage is set by the width/length (W/L) ratios of transistors P1 and P3.
The high and low threshold (VIH, VIL) voltage values can be selected by carefully selecting the width to length ratios of the transistors N1, N3, and transistors P1, P3. As the width to length ratio of the transistor P1 increases with respect to the width to length ratio of the transistor P3, the low threshold value VIL increases from the voltage Gnde. As the width to length ratio of the transistor N1 increases with respect to the width to length ratio of the transistor N3, the high threshold value VIL decreases from the voltage Vdde. Thus, by carefully selecting the width to length ratios of the transistors P1, P3, and transistors N1, N3, appropriate high and low threshold values can be achieved. The high and low threshold values implement hysteresis into the Schmitt trigger 21, thereby reducing the sensitivity of the circuit to noise and jitter.
The RX circuit 20 further includes a level shifter circuit 30. The level shifter circuit 30 is powered from the power supply domain for the peripheral region 14 (power supply voltages Vdde and Gnde) and the power supply domain for the central (core) region 12 (power supply voltages Vdd and Gnd). The level shifter circuit 30 receives the signal Out from the Schmitt trigger 21, shifts the logic high voltage of that signal from Vdde to Vdd, and outputs a level shifted signal Out(ls) for processing by the functional integrated circuits of the central (core) region 12.
It is often the case that the input signal In at the input node 22 from the pad 16tr is at a different voltage domain than the power supply domain for the I/O circuits of the peripheral region 14 (power supply voltages Vdde and Gnde). This can occur, for example, in the case where the pad 16tr is coupled to a data bus whose logic high voltage for a certain data bus standard is less than the supply voltage Vdde. As an example, consider the case where Vdde is 3.3V and the logic high voltage for the input signal In at the input node 22 is 1.2V (or 1.8V). In this situation, there is a direct current path from supply voltage Vdde to ground Gnde through the series connected transistors P1, P2, N1 and N2 of the first inverting stage of the Schmitt trigger 21 through which a not-insignificant static current consumption is present. As an example, this static current consumption may, for example, be about 20 μA or perhaps 100 μA (depending, of course, design, sizing of transistors and technology). The presence of this static current consumption can make it difficult for the RX circuit 20 of the I/O circuits in the peripheral region 14 to meet certain required operating specifications (like high threshold switch level (VIH), low threshold switch level (VIL), and hysteresis) and/or meet certain required transient specifications (such as duty cycle and static current consumption).
To address these concerns, FIG. 3 shows a modification of the Schmitt trigger circuit 21 of FIG. 2 to include a diode-connected transistor 32 coupled in series with series connected transistors P1, P2, N1 and N2 of the first inverting stage. In particular, the diode-connected transistor 32 is coupled between the supply voltage Vdde and the source of the PMOS transistor P1. The diode-connected transistor 32 may, for example, be formed by an NMOS transistor N6 having a gate and drain coupled to the supply voltage Vdde and a source coupled to the source of transistor P1. The presence of the diode-connected transistor 32 in the direct current path from supply voltage Vdde to ground Gnde will reduce, but not eliminate, the static current consumption. As an example, this static current consumption may be reduced from the consumption of the circuit shown in FIG. 2, for example. However, the Schmitt trigger circuit 21 of FIG. 3 can still fail to meet the required operating specifications and/or transient specifications across process, voltage and temperature (PVT) variation. Because the receiver circuit is used in a low power application, the static power dissipation is an important specification to be met. Still further, the inclusion of diode-connected transistor 32 has an impact on occupied circuit area.
Another option, as shown in FIG. 4, is to provide a voltage regulator circuit 34 on-chip to generate a supply voltage Vddi for the Schmitt trigger circuit 21 from the power supply voltage Vdde. The generated supply voltage Vddi is selected to be at the same voltage level as the logic high voltage for the certain data bus standard of the signals at pad 16tr. As an example, if the logic high voltage for the input signal In at the input node 22 is 1.2V, the voltage regulator circuit 34 would generate Vddi=1.2V. Advantageously, the solution of FIG. 4 substantially addresses the concerns with the circuits of FIGS. 2-3. However, this solution introduces a different problem in that there will be some level of static current consumption in the voltage regulator circuit 34 itself and there is a significant circuit area impact from the inclusion of the voltage regulator circuit 34.
There is accordingly a need in the art for a receiver circuit that addresses the foregoing and other problems.

Low power input receiver using a Schmitt trigger circuit


A structural member 10 includes a hat member 1 and a closing plate 2. The length LY of the tubular portion formed by the hat member 1 and the closing plate 2 is 6 or more times the height H of a pair of side walls 11 and 12. Each of the side walls 11 and 12 includes a high-strength portion 11A or 12A and low-strength portions 11B or 12B. The high-strength portion has a yield strength not less than 500 MPa. The low-strength portions have a yield strength of 60 to 85% of that of the high-strength portion. Each high-strength portion extends a distance not less than (⅔)H and not more than 3H as measured in the direction in which the ridges extend, and is provided such that the high-strength portions of the pair of side walls face each other. A pair of low-strength portions sandwich the associated high-strength portion.

Structural members including a tubular portion composed of a hat member having a hat-shaped cross section and a closing plate joined to the hat member are used in various applications. Applications include structural members in vehicles, buildings, or large containers, for example. Especially structural members used in automobiles are required to have impact resistance.
For example, WO 2005/058624 (Patent Document 1) discloses a metal pipe mounted on the vehicle body of an automobile with both ends supported thereon to provide impact resistance. This metal pipe has a bent portion that runs its entire length or just a portion of its length. The metal pipe is disposed such that the outer side of the bent portion is generally oriented toward the direction of a possible impact applied to the vehicle body. This metal pipe has better impact resistance than a reinforcement member made of straight pipe to reinforce the vehicle body.

Structural member and structural member for vehicle


A method for producing a molded plastic and copper flat rotary switch or commutator with parts of the segments lying in a cylindrical surface is disclosed. A cup-shaped unfinished piece is formed by modification of a flat material, having an outside annular flange and a number of axial grooves which are radially open on the inside as well as distributed uniformly around the periphery corresponding to the number of segments in the cylindrical part of the unfinished piece, on the outside of the cylindrical wall of the unfinished piece, a layer with a thickness which corresponds to the radial thickness of the material parts occluding the grooves radially on the outside is pushed, beginning at the flat part corresponding to the subsequent brush contact surface, toward the free end of the casing with formation of the annular flange and opening of the grooves.

The invention relates to a method for producing a flat rotary switch or commutator of molded plastic and copper and a flat switch made therefrom.
One known method of this type disclosed in U.S. Pat. No. 3,812,576 requires a relatively great number of individual work steps, which in turn, requires transfer between several machines. Such a method can lead to impairment of the secure joining between the segments and the molded plastic.
A primary object of the present invention is to provide a method of the aforementioned type but which allows for cost-effective manufacture of the switch without impairment of the quality of the switch. Other objects and advantages will become apparent from the description which follows.

Method for producing a molded plastic flat rotary switch


A bicycle operating device basically includes an operating member and a click mechanism. The click mechanism includes an input part, an output part and an intermediate part. The intermediate part is movable between the input and output parts to transmit movement from the input part to the output part in accordance with movement of the operating member. The intermediate part contacts the input part at a first contact point, and contacts the output part at a second contact point. The intermediate part and the output part define a first angle that decreases as the operating member moves from the first position toward the second position. The first angle has an apex at the second contact point, a first leg extending from the second contact point to a center of the pivot of the output part and a second leg extending from the second contact point to the first contact point.

Field of the Invention
This invention generally relates to a bicycle operating device. More specifically, the present invention relates to a bicycle operating device having a click mechanism to indicate to a rider that the bicycle operating device has been operated to a predetermined position.
Background Information
Bicycles are often provided with one or more bicycle components that can be operated and/or adjusted by a rider while riding. Examples of some these bicycle components include a gear changing device (e.g., a derailleur or an internally geared hub), a suspension and a seatpost. A bicycle operating device is usually provided on a bicycle (e.g., on a bicycle handlebar) for a rider to operate and/or adjust these bicycle components. Sometimes these bicycle operating devices are provided with an indicating device such as a click mechanism to indicate to the rider that the bicycle operating device has been operated to a predetermined position.


A firearm having a barrel and a whistle, wherein when the firearm is discharged a bullet traveling down the barrel forces air through the whistle to cause a whistle sound. The whistle comprises a barrel port, a channel, and a whistle port and wherein when the firearm is discharged a bullet traveling down the barrel forces air through the barrel port, the channel, and the whistle port to cause a whistle sound. The whistle may be associated with a firearm attachment and the firearm attachment is removably couplable to the firearm. The whistle may also be modifiable and modification of the whistle is configurable to eliminate or change the whistle sound. The whistle sound may also be associated with a signal that is transmitted to another device or central location for analysis, wherein the signal comprises a firearm identification or locational information.

It is difficult to remotely identify a discharged firearm and distinguish that discharged firearm from other proximately discharged firearms. For example, when law enforcement officers are engaging one or more suspects, it is difficult for those law enforcement officers to distinguish between friendly and hostile fire. This is important because law enforcement officers must make safety decisions that depend upon the source of any discharged firearm. Unfortunately, without reliable information on the source of a discharged firearm, it is common for law enforcement officers to err on the side of caution and unnecessarily discharge firearms without fully understanding the situation. This phenomenon is known as "contagious gunfire", which describes the concept that when one person in a standoff discharges a firearm others will also discharge their firearms without understanding the source of the original shot. This result escalates conflict and increases the risks of injury, death, and property damage. Thus, the ability to identify a discharged firearm and distinguish that discharged firearm from other proximately discharged firearms would reduce or eliminate the chance of contagious gunfire occurring.
Accordingly, while desirable results have been achieved, there exists much room for improvement. What is needed then is a firearms safety mechanism to identify a discharged firearm.

This patent is subject to a terminal disclaimer.


Apparatus is provided for welding a stud to a workpiece. The stud is positioned against the workpiece in such a manner that the stud retracts from an extended first position to a second position against the workpiece. The stud is then retracted away from the workpiece to a fully retracted third position. Welding current is provided so as to establish a welding arc between the stud and the workpiece as the stud is being retracted to the third position. The stud is then plunged toward the workpiece to make contact therewith. The displacement of the stud from its initial first position to the second position is measured during the time that the stud is in engagement with the workpiece and before the stud is retracted therefrom to the third position. The plunging of the stud toward the workpiece is controlled as a function of the measured displacement in such a manner as to control the point in time at which the stud makes contact with the workpiece.

1. Technical Field
The present invention is directed to the art of welding a stud to a workpiece and, more particularly, to improvements in controlling the welding to compensate for variations in arc length as a result of workpiece variations or stud length variations.
2. Prior Art
Welding tools for welding studs, sometimes referred to herein as fasteners, to a metal workpiece are known in the art. Typically, a welding tool caries a stud, which is resiliently urged to an extended position. The stud is retracted slightly to a work position when the stud is pressed against a workpiece to place it in good electrical contact therewith. A trigger is then actuated to initiate a welding operation. The stud is then withdrawn from the workpiece toward a fully retracted position and a pilot arc is established. Thereafter, when the stud is in its fully retracted position, a main welding arc is established between the stud and the workpiece. Then the stud is plunged toward the workpiece and, upon making electrical contact therewith, the welding arc is extinguished. Welding tools that perform the above functions are described in my previous U.S. Pat. Nos. 3,291,958; 3,136,880 and 3,392,257.
It has been determined that the arcing time in stud welding will vary due to changes in arc length caused by variations in workpiece or stud length. Unless compensation is provided, there will be a tendency to have inconsistent weld quality from weld to weld. In my previous U.S. Pat. No. 3,392,257, provisions are made for sensing the position of a stud to be welded prior to the beginning of a weld cycle. If a stud is not in a proper position, the welding circuit is rendered inoperative until a proper stud position is attained. No provisions are made for controlling the plunging of the stud toward the workpiece as a function of measured displacement in order to control the point in time at which the stud makes contact with the workpiece.

Apparatus for controlling a welding tool


Systems and methods for leveraging Internet-of-Things devices in security systems are provided. Such systems and methods can include receiving an alarm signal from a first IoT device responsive to the first IoT device detecting a sound indicative of an intrusion, requesting data from a second device responsive to receiving the alarm signal from the first IoT device, determining whether the data from the second device confirms the intrusion, and triggering an alarm responsive to the data from the second device confirming the intrusion.

Security systems are known to detect threats within a secured area, and such threats can include events that represent a risk to human safety or a risk to assets.
Security systems typically include one or more security sensors that detect the threats within the secured area. For example, smoke, motion, and/or intrusion sensors can be distributed throughout the secured area in order to detect the threats. Typically, the one or more sensors must be newly installed and added to the secured area, but such installation of the one or more security sensors can be burdensome.
In view of the above, there is a continuing, ongoing need for improved systems and methods.

Systems and methods for leveraging internet-of-things devices in security systems


A wireless communication system including first and second wireless devices, and first and second access points to synchronize the first and second wireless devices, wherein the first access point determines whether the second access point exists in a neighboring area, periodically checks communication states of the second access point, sends an access point replacement command to the second wireless device linked to the second access point in response to determining the second access point is communication-disabled, and forms a new communication channel with the second wireless device according to an association request signal received from the second wireless device in response to the access point replacement command.

1. Field of the Invention
The present invention relates to a wireless communication system and a method thereof, and, more particularly, to a wireless communication system and a method thereof in wireless infrastructure networking environments.
2. Description of the Related Art
Recently, wireless networking environments, together with wireless communication technology developments, have become widespread in everyday life. For example, as an alternative technology for a conventional wired LAN, Wireless Local Area Network (WLAN) technologies such as IEEE 802.11 are being used more and more. The IEEE stands for the Institute of Electrical and Electronics Engineers.
The IEEE 802.11 wireless LAN features the use of a wireless Radio Frequency (RF) technology using the 2.4 GHz band called the "Industrial Scientific Medical(ISM) band," instead of the use of cable, thereby enabling the networking capability to be equal to that of the wired LAN. There are two transmission modes of infrastructure networking and Ad-hoc networking for the IEEE 802.11 wireless LAN. Here, the Ad-hoc mode, in which a network is constructed with only devices mounting a wireless LAN therein, is not connected to external networks. That is, communications are performed among the wireless LAN devices in the Ad-hoc mode, so that the Ad-hoc mode is used for small-sized offices or small-scaled networks.
The infrastructure mode can be used in offices with environments that are equal to that of the existing wired LAN, and wireless networks for the infrastructure mode are constructed with access points, which are wired/wireless interfacing devices, connected to wired networks (Ethernets). An access point serves as a bridge between a wireless LAN device and a wired LAN device, enabling mutual data transmissions and receptions.
A wireless device has to exist in a wireless communication range of an access point to communicate with wired devices through the access point, and has the same ID as a basic service set identifier (BSSID) and a service set identifier (SSID) assigned to the access point. To do so, the wireless device receives a beacon frame that an access point periodically sends when a wireless LAN channel is changed. The wireless device, having received the beacon frame, sends a response message for an association request to the access point sending the beacon frame.
The access point, having received the association request from the wireless device, sends an association response message to the corresponding wireless device, including a BSSID and an SSID assigned to the access point. The wireless device receives and registers the association response message for its own network information, so that a communication channel is linked between the access point and the wireless device.
If a communication channel is linked between an access point and a wireless device, the wireless device can form one network with wired devices through the access point, and share the network resources. However, if the access point does not perform normal operations due to system defects such as a system failure, wireless devices connected to the access point cannot participate in the network any more. In this case, the wireless devices connected to the access point temporarily stop their data transmission/reception operations, and wait for an arbitrarily set period of time. Thereafter, the wireless devices attempt to associate with the access point, but cannot connect to the corresponding network until the access point performs its normal operations. Accordingly, there exists a problem in that the communication efficiency between the wireless devices and the access point is reduced.

Communication system and method in wireless infrastructure network environments


Dual polarity source/drain extensions are formed simultaneously in both PMOS and NMOS devices of a CMOS architecture using a common set of implants, so to be contiguous with one or both of source and drain regions of both the PMOS and the NMOS structures. The complementary conductivity lateral extension region configuration may be either an N over P or a P over N structure. The dual implant methodology can be carried out with no explicit masking steps, yielding MOS device which have source/drain extension regions that are self aligned to the gate and have minimal overlap capacitance.

U.S. Pat. No. 4,823,173, entitled "High Voltage Lateral MOS Structure with Depleted Top Gate Region," issued Jan. 7, 1989, assigned to the assignee of the present application and the disclosure of which is herein incorporated, describes the formation of a drain-extension drift region in a lateral MOS structure in order to increase reverse breakdown voltage and reduce on-resistance. By adding such a lateral drift region to what is otherwise a low voltage structure, the device can be effectively transformed into a substantially increased (reverse breakdown) voltage MOS device.
The incorporation of such a drain extension region into a PMOS device is diagrammatically illustrated in FIG. 1 as comprising an `N over P` lateral drift, drain-extension region 11, which is contiguous with a (P+) drain region 13 and extends along the surface 14 of an N type semiconductor (e.g. silicon) body 10 toward a (P+) source region 12. By an `N over P` lateral drift region is meant that the lateral drift region 11 comprises an upper or topside N-type conductivity portion 11N, which adjoins a lower P-type conductivity portion 11P, so that, in effect the N portion is `over` the P portion. Conversely, by a `P over N` lateral drift region is meant that the lateral drift region comprises an upper P-type conductivity portion which adjoins a lower N-type conductivity portion, so that the P portion is `over` the N portion.
The lateral drift region 11 may extend beneath a thick oxide layer 15 (typically formed by local oxidation) or under a thin (gate) oxide layer 17, with the lower P-type drain extension portion 11P of the N over P region extending to the surface 14 of the N body 10 beneath a gate electrode 16. In effect, the upper N region 11N may be considered as an upper gate and the N body 10 as the lower gate of a JFET, the channel of which is defined by P drain extension portion 11P.
The parameters of the lateral drift region 11 (e.g. doping profile in ions per square centimeter) are predefined such that, in the presence of a reverse bias applied between the drain region 13 and the body 10, P-drift region 11P becomes depleted of charge carriers prior to the occurrence of breakdown field in the depletion layer 19 that spreads from a reverse-biased drain-to-body PN junction 21, particularly at the sharp curvature portion 23 of the junction beneath gate electrode 18, where the total electrical field strength is increased by the presence of the bias applied to the gate. Typically, the doping per unit area of the P drift region portion 11P is a value on the order of 1 to 2.times.10.sup.12 ions/cm.sup.2, while N region portion 11N has a doping on the order of 1.times.10.sup.12 ions/cm.sup.2, in order to satisfy this fully depleted requirement.
The increased doping of P extension portion 11P reduces its resistance by about a factor of two, resulting in a PMOS device having lower on-resistance, since the drain current flows through the P extension portion 11P. The reduction in on-resistance in a PMOS device employed in an analog switching circuit is particularly important, since PMOS switching devices typically occupy approximately three times the semiconductor real estate as NMOS devices. Reducing PMOS size thus decreases die area. It also diminishes the mismatch in capacitance between P and N channel switch devices, because their sizes are more nearly equal, so that charge transfer errors which result from mismatched capacitances are also reduced.
In addition to signal processing applications having a need for high reverse breakdown MOS devices, there are also a number of applications which require CMOS devices having respectively different reverse breakdown characteristics (e.g. moderate voltages on the order of 20-80 volts for analog functions, such as analog switches and multiplexers, and high voltages on the order of 200-1000 volts for analog switching circuits). Because of the diversity of both the types and parametric variations of the device structures, the processes used to form such combined technology architectures are often complex, sometimes requiring upwards of fifteen masking steps to pattern and layout the topology of the wafer. Moreover, since there is both an increase in cost and a decrease in yield as the number of mask steps increases, it is desirable to reduce the number of steps required to incorporate all of the various types of devices that make up a multifunctional signal processing architecture. Unfortunately, conventional wafer processing to provide lateral drift regions customarily involves the use of both a special mask and a special doping step (e.g. ion implantation) exclusively dedicated to the formation of the drift region. As a consequence, there is an increase in both cost and complexity of the manufacturing process.

Formation of dual polarity source/drain extensions in lateral complementary channel MOS architectures


An optical transmitting/receiving apparatus capable of suppressing electrical crosstalk and magnetic crosstalk, includes: a laser diode/photo diode (LD/PD) integrated module that terminates a single-core bidirectional optical fiber; a circuit board electrically connected to a lead pin led out of the LD/PD integrated module; and a plastic case that accommodates the circuit board. At least a part of the plastic case abuts against the LD/PD integrated module, and impedance of the plastic case is controlled by mixing a conductive filler into the plastic case.

The present invention relates to an optical transmitting/receiving apparatus including a laser diode/photo diode (LD/PD) integrated module housed therein. Specifically, the present invention relates to an optical transmitting/receiving apparatus capable of suppressing electrical crosstalk and magnetic crosstalk.
Owing to a rapid widespread of a fiber to the home (FTTH) technology, it is becoming possible to easily stay connected to the Internet all the time at general homes. With the widespread of the fiber, an optical subscriber terminal apparatus (optical transmitting/receiving apparatus) is becoming downsized and low-priced (low-costed).
Up to now, an apparatus including a laser diode LD that transmits light (optical signal) and a photo diode PD that receives light as separate modules is in the mainstream, so the optical transmitting/receiving apparatus itself is large in size.
In view of the above, a small-sized LD/PD integrated module that terminates a single-core bidirectional optical fiber (optical fiber cable) is proposed (Patent Document 1). With regard to such a single-core bidirectional LD/PD module, the LD/PD integrated module is accommodated in a metal housing obtained by processing a metal plate into a box shape.
In the meantime, such an LD/PD integrated module has a structure in which a CAN package of an LD module and a CAN package of a PD module are electrically connected to the metal housing owing to an adhesive technique such as laser welding and have a common ground.
However, in a case where the LD module is driven at high frequency (LD modulation), owing to parasitic effects of stray capacitance (Cf) of lead pins and inner structural components of optical devices of the LD and the PD, stray inductance (Lf) of the metal housing portion, and the like, the ground (GND) of the LD/PD integrated module does not become ideal.
As a result, an electrical crosstalk path is formed between a transmission side (light emitting side) and a reception side (light receiving side) of the integrated module, and a magnetic noise (magnetic crosstalk) generates, with the result that reception sensibility deteriorates. FIG. 11 exemplifies a mechanism how such electrical crosstalk generates.
As a countermeasure against the above, it is considered to stabilize a ground potential by accommodating a circuit board mounted with the LD/PD integrated module in a metal case, fixing the metal housing of the LD/PD integrated module to the metal case, and allowing the metal housing electrically contact the metal case.
However, the following problems are pointed out. That is, the metal case makes the entire optical transmitting/receiving apparatus larger in size and is complicated in processing steps and heavyweight, and material cost of the metal plate increases.
Accordingly, there is proposed an optical transmitting/receiving apparatus in which an LD/PD module is accommodated in a plastic case which can be downsized, and is processed easily, lightweight, and low in cost.
However, in the case where an LD/PD module is accommodated in a plastic case, problems concerning electrical crosstalk and magnetic crosstalk come up again. In other words, the above-mentioned problems come up again as follows. That is, because there is employed a structure in which the LD/PD integrated module including an LD module accommodated in a metal housing and an PD module accommodated in a metal housing is fixed to the plastic case, ground of the LD/PD integrated module does not become ideal, an electrical crosstalk path is formed between the transmitting and receiving sides, and a magnetic noise (magnetic crosstalk) generates, with the result that reception sensibility deteriorates.
The following are related arts to the present invention.    [Patent document 1] Japanese Patent Laid-Open Publication No. 2000-180671    [Patent document 2] Japanese Patent Laid-Open Publication No. 06-138347    [Patent document 3] Japanese Patent Laid-Open Publication No. 2001-268020


A pixel circuit of an organic light emitting diode (OLED) display device is provided, which supplies a small current to an organic light emitting diode during stoppage of a display operation. The pixel circuit includes a second driving transistor, which is coupled in parallel with a first driving transistor. A gate control line is used to control the second driving transistor so that a small current can flow into the organic light emitting diode during the stoppage of the display operation. The small current is supplied through the second driving transistor to the organic light emitting diode during the stoppage of the display operation. Thus, the pixel circuit of the OLED display device can reduce or prevent an electric shock applied to the organic light emitting diode at the beginning of the display operation, thereby reducing or preventing deterioration of the characteristics of the organic light emitting diode.

1. Field of the Invention
The present invention relates to an organic light emitting diode (OLED) display device and, more particularly, to a pixel circuit of an OLED display device.
2. Description of the Related Art
Among flat panel displays (FPDs), an organic light emitting diode (OLED) display device is quite appropriate for displaying moving images irrespective of size because it has a fast response time of 1 ms or less, consumes low power, and is an self-emissive display, therefore having a wide viewing angle. Also, the OLED display device can be fabricated at a low temperature and in a simple process based on conventional semiconductor manufacturing technology. For these reasons, the OLED display device has attracted considerable attention as an advanced FPD.
In general, the OLED display device is a display device that emits light by electrically exciting a fluorescent organic compound, and displays an image by voltage programming or current programming N×M organic light emitting diodes (OLEDs) arranged in a matrix. The OLED display device may be classified as a passive matrix type or an active matrix type using a thin film transistor (TFT) depending on a driving method. The passive matrix type OLED display device includes anodes and cathodes arranged at right angles, and is driven through line selection. On the other hand, the active matrix type OLED display device has a TFT connected to each pixel electrode, formed of indium tin oxide (ITO), and is driven according to a voltage maintained by a capacitor connected to a gate of the TFT.
FIG. 1 is a circuit diagram of a pixel circuit of a conventional OLED display device.
Referring to FIG. 1, the pixel circuit includes a switching transistor MS, a capacitor Cgs for storing a data signal received through the switching transistor MS, a driving transistor MD for generating a driving current in response to the data signal stored in the capacitor Cgs, and an OLED that emits light in response to the driving current.
The switching transistor MS transmits a data signal output from a data line Dm in response to a scan signal output from a scan line Sn. The capacitor Cgs stores a data signal received through the switching transistor MS and maintains a gate-source voltage Vgs of the driving transistor MD for a predetermined duration of time. A gate electrode of the driving transistor MD is connected to the switching transistor MS. The driving transistor MD supplies a driving current corresponding to the data signal transmitted through the switching transistor MS to the OLED. The OLED includes an anode, a cathode, and an emission layer interposed between the anode and the cathode. The anode is connected to a drain terminal of the driving transistor MD and coupled to a power supply voltage line Vdd through the driving transistor MD. The cathode is connected to a reference voltage line Vss and emits light with a brightness corresponding to the current supplied from the driving transistor MD.
In the OLED, holes transported from the anode combine with electrons transported from the cathode in an organic layer to form hole-electron pairs, i.e., excitons, and light is emitted by the energy generated when the excitons transition from an excited state to a ground state.
When the OLED display device including the above-described OLED begins a display operation, a high voltage is applied to a display panel in a short period of time. Thus, a large current is supplied to the OLED suddenly. As a result, sudden transport of a large number of holes and electrons electrically shocks an organic layer of the OLED, so that the characteristics of the OLED may deteriorate.

Pixel circuit and organic light emitting diode display device using the same


A ROM device provides a double density memory array. The word line array is composed of transversely disposed conductors sandwiched between two arrays of bit lines which are orthogonally disposed relative to the word line array. The two arrays of bit lines are stacked with one above and with one below the word line array. A first gate oxide layer is located between the word line array and a first one of the array of bit lines and a second gate oxide layer is located between the word line array and a the other of the arrays of bit lines. The two parallel sets of polysilicon thin film transistors are formed with the word lines serving as gates for the transistors.

1. Field of the Invention
This invention relates to Read Only Memory (ROM) devices, and more particularly to improved structural arrangements thereof, and to methods of manufacture thereof.
2. Description of Related Art
ROM devices are standard components of modern computer systems. A ROM comprises an array of Metal Oxide Semiconductor Field Effect Transistor (MOSFET's) arranged in columns and rows, wherein predetermined MOSFET's are either permanently conductive or nonconductive as a function of the variety of transistor. The alternative on/off operation with changes in the states of operation of the MOSFETs is adapted to use for storage of data, which remains in the device when the external power supply is off.
A ROM device includes an array of parallel, closely spaced lines regions formed of a heavily doped impurity in a semiconductor substrate having an opposite type of background impurity. On the surface of the substrate an insulating layer is formed thereon. Another array of closely spaced conductive lines formed on the surface of the insulating layer is arranged at right angles to the spaced lines in the substrate. Insulating layers are formed on the upper array of conductive lines. A metallurgy layer connects the two arrays of lines to circuits to address the lines and to read the data stored in the ROM, as is well known in the art.
At the intersection of a conductive line in the upper array which is commonly referred to in most cases as a "word line" and a pair of adjacent lines in the substrate, known in most cases as the "bit lines", a MOSFET is formed. The spaced lines in the substrate comprise the source and drain of the MOSFET. The conductive word line serves as the gate electrode of the MOSFET. Certain predetermined MOSFET's can be made permanently non-conductive (turned off).
A problem with the trend in the semiconductor industry is the ever increasing density of circuits on a device. Accordingly, an object of this invention is to provide an improved design for a very high density ROM device.
Another objective ever desirable in electronic devices and other technologies is the simplification of the structure and operation of devices. In the case of the very large number of circuits in the state of the art ROMs the need for simplification of structure and operation is as desirable as ever. Accordingly, it is an important object of this invention is to provide for simplification of the structure and the operation of ROM devices.

Ulsi mask ROM structure and method of manufacture


A polypeptide comprising a polypeptide consisting of an amino acid sequence shown in SEQ ID NO: 5 of Sequence Listing or a polypeptide consisting of an amino acid sequence having deletion, addition, insertion or substitution of one to several amino acid residues in the sequence, the polypeptide being capable of constituting an HLA-A24-restricted, MAGE-A4143-151-specific T cell receptor together with a polypeptide consisting of an amino acid sequence shown in SEQ ID NO: 2 of Sequence Listing.

Cytotoxic T cells (CTLs) include those capable of recognizing a complex by a specific T cell receptor (hereinafter simply referred to as "TCR"), the complex that is a conjugate of a major histocompatibility gene complex (hereinafter simply referred to as "MHC")-encoding major histocompatibility antigen molecule (MHC molecule; in a case of human, it is called "human leukocyte antigen," hereinafter simply referred to as "HLA") and an antigen peptide, and killing a cell in which the complex is presented on a cell surface. Therefore, in order to establish the cytotoxic reaction, it is necessary that 1) a CTL having a TCR specific to HLA Class I type of a target cell exists, and 2) an antigen peptide so that a complex formed by binding to the HLA molecule is capable of being recognized by the TCR exists.
The antigen peptide as described above is generated by, for example, processing an antigen or the like synthesized in a cell of a mammalian cell in a cytoplasm, thereby degrading into small peptides. The small peptides are further associated with an HLA molecule to be presented on the cell surface. In other words, in the proteasome complex consisting of numerous subunits, a protein is degraded into peptides consisting of 8 to 15 amino acids, some of which are transported from the cytoplasm to the endoplasmic reticulum by a TAP transporter. Once these peptides can be bound to a heterodimer of Class I/β2 microglobulin, they are stabilized in the form of a trimolecular complex, and transported to the cell surface through the Golgi apparatus. A tumor cell expressing a tumor-associated antigen or tumor-specific antigenic protein is supposedly capable of presenting an HLA-restricted antigenic peptide recognized by a T cell.
It has been known that the HLA Class I molecules are mainly HLA-A, -B, and -C, that the antigen peptides which are presented by binding to these molecules consist of 8 to 10 amino acids, and further that there are given different structural features for each of the HLA molecules. For example, as a peptide binding to an HLA-A2.1 molecule which is most frequently found worldwide, a peptide consisting of 9 to 10 amino acids, the peptide having Leu at a second position from an N-terminal, and Leu or Val at a C terminal has been most well known. In addition, as a peptide binding to an HLA-A24 molecule which is found more richly in the Asians such as the Japanese, a peptide consisting of 9 to 10 amino acids, the peptide having any one of Tyr, Phe, Met, and Trp at a second position from an N-terminal, and any one of Leu, Ile, Trp, and Phe at a C-terminal has been most well known.
Tumor antigens for which antigen peptides have so far been identified are MAGE-A1, MAGE-A3, and MAGE-A4 against HLA-A1; MAGE-A3, MART1, tyrosinase, gp100, HER2/neu, CEA and the like against HLA-A2.1; MAGE-A3 against HLA-Cw1; MAGE-A3 against HLA-B44; MAGE-A4 against HLA-B37; and MAGE-A1, MAGE-A2, MAGE-A3, MAGE-A4, NY-ESO-1, CEA, HER2/neu, tyrosinase, β-catenin, and the like against HLA-A24. In many of these tumor antigens, first, a cell line is established for a Class I-restricted CTL recognizing a tumor cell, a tumor antigen recognized by the CTL is identified, a minimum unit in tumor antigen proteins is subsequently found by a genetic engineering method, and peptides in the minimum unit are further found on the basis of the information regarding the binding motif to the HLA Class I molecules. In addition, first, peptides binding to the HLA Class I molecules are found in the tumor antigen proteins on the basis of the motif structure commonly shared between the above-mentioned peptides binding to the HLA Class I molecules, those peptides from which CTLs are inducible are subsequently selected utilizing an antigen presenting cell, and finally antigen peptides are then determined depending upon whether or not a CTL having toxicity against a tumor cell can be induced.
On the other hand, the HLA Class I molecules are classified into some subtypes, and the kinds of owned subtypes greatly differ among races. Worldwide, HLA-A2 is most often found, and 45% of the Caucasians are HLA-A2-positive. Moreover, the identification of this HLA-A2-restricted antigen peptide is most advanced. In the Japanese, HLA-A2-positive is found in 40%, and when their subtypes are studied, HLA-A*0201-positive, which is the same as the Caucasians, is 20%, and much of the remaining are A*0206-positive. The binding peptides to these subtypes are different, so that HLA-A2 that is mainly studied is HLA-A*0201. On the other hand, in the Japanese, HLA-A24-positive is found in 60% or more, and an HLA-A24-positive percentage is higher in the Asians than other races. Therefore, the finding of an HLA-A24-restricted antigen peptide plays an important role in providing a CTL that is useful in the treatment of tumor by inducing a CTL acting specifically to a tumor cell in the Asians, especially the Japanese.
Since antigen peptides differ on the basis of the difference in the HLA even with the same antigen, the induction of a CTL utilizing antigen peptides is complicated. Although various contrivances have been made in order to solve this disadvantage, a satisfactory fruit has not yet been obtained. One contrivance is a method including the steps of transducing an antigenic gene into an antigen presenting cell derived from a patient him/herself (self), and inducing a T cell utilizing the transformed gene. As the antigen presenting cell, B cell, macrophage, and dendritic cell have been studied, and a clinical test has been carried out using as an adjuvant or the like for a vaccine centering about dendritic cell which is known as a professional antigen presenting cell. However, there is a disadvantage that much labor is required in furnishing these antigen presenting cells in an amount necessary for immune induction. B cell can be mass-produced by immortalization by EB virus; however, there is a disadvantage in safety from the viewpoint of use of a virus.
As tumor antigen-specific TCR genes, for example, genes such as HLA-A2-restricted, MART1-specific TCR [Non-Patent Publication 1], MAGE-A3-specific TCR [Non-Patent Publication 2],CAMEL (CTL-recognized antigen on melanoma)-specific TCR [Non-Patent Publication 3], gp100-specific TCR [Non-Patent Publication 4], NY-ESO-1-specific TCR [Non-Patent Publication 5], HLA-24-restricted WT1 (Wilms tumor 1)-specific TCR [Non-Patent Publication 6], HLA-Cw16-restricted MAGE-A1-specific TCR [Non-Patent Publication 7] have been cloned.
It can be expected to give a specific cytotoxic activity to an intended antigen by transducing TCR gene into a given CTL. Based on the above, gene therapies with TCR gene targeted to MART1 [Non-Patent Publication 8], gp100 [Non-Patent Publication 4] and mHAG HA-2 antigen [Non-Patent Publication 9] have been tried.
MAGE-A4 is an antigen belonging to a MAGE subfamily of a cancer-testis antigen family, which is expressed in various cancers and has a high antigenicity (positive in 60% of esophageal cancer, 50% of head and neck cancers, 24% of non-small cell pulmonary cancer, 33% of stomach cancer, and 21% of Hodgkin disease), so that the antigen is expected to serve as a target antigen in cancer vaccine therapy. An HLA-A24-restricted MAGE-A4143-151 peptide-specific CTL clone has been obtained [Non-Patent Publication 10].    Non-Patent Publication 1: Cancer Res., 54, 5265-5268 (1994)    Non-Patent Publication 2: Anticancer Res., 20, 1793-1799 (2000)    Non-Patent Publication 3: Int. J. Cancer, 99, 7-13 (2002)    Non-Patent Publication 4: J. Immunol. 170, 2186-2194 (2003)    Non-Patent Publication 5: J. Immunol., 174, 4415-4423 (2005)    Non-Patent Publication 6: Blood, 106, 470-476 (2005)    Non-Patent Publication 7: Int. Immunol., 8, 1463-1466 (1996)    Non-Patent Publication 8: J. Immunol., 163, 507-513 (1999)    Non-Patent Publication 9: Blood, 103, 3530-3540 (2003)    Non-Patent Publication 10: Clin. Cancer Res., 11, 5581-5589 (2005)

T-cell receptor and nucleic acid encoding the receptor


Novel fusion proteins capable of self-assembling into regular structures, as well as nucleic acids encoding the same, are provided. The subject fusion proteins comprise at least two oligomerization domains rigidly linked together, e.g. through an alpha helical linking group. Also provided are regular structures comprising a plurality of self-assembled fusion proteins of the subject invention, and methods for producing the same. The subject fusion proteins find use in the preparation of a variety of nanostructures, where such structures include: cages, shells, double-layer rings, two-dimensional layers, three-dimensional crystals, filaments, and tubes.

1. Technical Field
The field of this invention is nanotechnology and biomaterials.
2. Background of the Invention
A central goal of nanotechnology research is to design and fabricate novel materials with sizes or length scales in the nanometer range. These materials fall into a variety of architectural classes, such as compact clusters, hollow shells, tubes, two-dimensional layers, and three-dimensional molecular networks. In recent years, a wide combination of chemical building blocks and synthetic strategies have been investigated. Numerous specific methods have produced interesting new materials, but a single general strategy for fabricating materials having many different architectures and symmetries has not been developed. Furthermore, most of the recent work has focused on inorganic and organic synthetic materials as building blocks, while biological molecules such as proteins offer some special advantages that have not yet been exploited. As such, there is continued interest in the development of new materials and systematic methods for producing nanostructures, especially using biological macromolecules
Relevant Literature
Various nanostructures and methods for their preparation are described in: Collier, et al., Ann. Rev. Phys. Chem. (1998) 49: 371-404 (compact clusters); Rao, et al., Current Opinion in Solid State and Materials Sci. (1996) 1:279-284 and Kroto, Nature (1987) 329:529 (hollow shells); Iijima, Nature (1991)354:56-58, Ghadiri, Nature (1993)366:324-327 and Ajayan et al., Reports on Progress in Physics (1997) 60:1025-1062 (tubes); Stange, et al., Biophys. Chem. (1998) 72:73-85 (molecular networks); and Li, et al., Science (1999) 283: 1145-1147; Seeman, Trends in Biotechnology (1999)) 11:437-443 (DNA); and Chui, et al., Science (1999) 283:1148-1150 (two-dimensional layers). Also of interest is: Wukowitz et al., Nature Struct. Biol. (1995) 2:1062-1067.
Novel fusion proteins capable of self-assembling into regular structures, as well as nucleic acids encoding the same, are provided. The subject fusion proteins comprise at least two oligomerization domains rigidly linked together, e.g. through an alpha helical linking group, where the oligomerization domains are derived from naturally occurring proteins. Also provided are regular structures comprising a plurality of self-assembled fusion proteins of the subject invention, and methods for producing the same, where the structures may be homogenous or heterogeneous with respect to their fusion protein components. The subject fusion proteins find use in the preparation of a variety of regular structures, where such structures include: cages, shells, double-layer rings, two-dimensional layers, three-dimensional crystals, filaments, and tubes.

The Regents of the University of California


Disclosed herein are novel solid forms of FXR agonists. The disclosure also relates to pharmaceutical compositions containing one or more of the solid forms disclosed herein, as well as methods of using the solid forms in the treatment of conditions mediated by FXR. The disclosure also relates to methods for obtaining such solid forms.

The present disclosure relates to solid forms of compounds that bind to the NR1H4 receptor (FXR) and act as agonists or modulators of FXR. The disclosure further relates to the use of the solid forms of such compounds for the treatment and/or prophylaxis of diseases and/or conditions through binding of said nuclear receptor by said compounds.
Compounds that bind to the NR1H4 receptor (FXR) can act as agonists or modulators of FXR. FXR agonists are useful for the treatment and/or prophylaxis of diseases and conditions through binding of the NR1H4 receptor. One such FXR agonist is the compound of Formula I:

Although numerous FXR agonists are known, what is desired in the art are physically stable forms of the compound of Formula I, or pharmaceutically acceptable salt thereof, with desired properties such as good physical and chemical stability, good aqueous solubility and good bioavailability. For example, pharmaceutical compositions are desired that address challenges of stability, variable pharmacodynamics responses, drug-drug interactions, pH effect, food effects, and oral bioavailability.
Accordingly, there is a need for stable forms of the compound of Formula I with suitable chemical and physical stability for the formulation, therapeutic use, manufacturing, and storage of the compound.
Moreover, it is desirable to develop a solid form of Formula I that may be useful in the synthesis of Formula I. A solid form, such as a crystalline form of a compound of Formula I may be an intermediate to the synthesis of Formula I. A solid form may have properties such as bioavailability, stability, purity, and/or manufacturability at certain conditions that may be suitable for medical or pharmaceutical uses.


Cutout object merge techniques are described. In one or more embodiments, a cutout object is identified for insertion into a scene. The cutout object may, for instance, be selected from a library of cutout objects, each of which was extracted from an already-captured image. Before capturing an image of the scene, the selected cutout object may be placed in a substantially real-time display of the scene, such as that which is displayed via a camera's view finder. Using an image capturing device, an image of the scene may then be captured. Once an image of the scene is captured, the cutout object and the captured image may be merged to form a composite image that includes the cutout object at a location in the scene specified by the placement.

The capabilities with which mobile devices can be configured have led many users to carry around just a single device capable of performing functions previously performed by multiple different devices. A single mobile device can, for instance, function as a cellular telephone, portable media player, portable gaming console, remote control, garage door opener, flashlight, camera, and so on.
Use of mobile devices as cameras, in particular, has become largely commonplace. The portability that enables mobile devices to fit conveniently in pockets, purses, and the like, also makes them an attractive camera option to carry around for taking pictures at practically any time, e.g., on trips. When on a trip, however, one person in a group of people (or a small subset of the group) is oftentimes designated as, or takes the initiative to be, the group's photographer. By doing so, photographers are often left out of the photographs, e.g., because he or she is behind the camera. Although conventional techniques may enable a user to add photographers back into photographs as part of post-processing, doing so may be time-consuming. Consequently, users may avoid adding photographers back into their photos.


An assembly comprising a pair of multifocal ocular implants, wherein each implant has a TFMTF curve, for a pupil of diameter less than or equal to 4 mm, preferably less than 3 mm, having a peak corresponding to the distance vision of the wearer, as well as an asymmetrical peak which spreads between intermediate vision and near vision without discontinuity;                for a first implant, the TFMTF value is greater in intermediate vision than that of near vision;        for the second implant, the TFMTF value is greater in near vision than that of intermediate vision;        the rising edge of the asymmetrical peak of the first implant has, as an absolute value, a mean slope greater than that of its falling edge, whereas the rising edge of the asymmetrical peak of the second implant has, as an absolute value, a mean slope less than that of its falling edge.

For many years now, people suffering from opacification of the crystalline lens (cataract) have been offered a procedure consisting of the destruction and removal thereof, and its replacement with an intraocular implant.
Thus, it is conventional to position on both eyes of a presbyopic patient (whether he is emmetrope or ametrope) two intraocular implants (implants of the crystalline lens capsule, of the anterior chamber or intracorneal) with multifocal optical surfaces (refractive or preferably diffractive).
The choice of implant can be made according to the living habits of the patient and his requirements. Priority is generally given to distance (far) vision (for example in a situation of driving of a vehicle) and near vision (for example in a situation of reading of a book). But with the ever-increasing use of computers, tablets and smartphones, prioritizing intermediate vision is also an aim (notably illustrated by a situation in which a screen is viewed).
An implant with multifocal optical surfaces (refractive or preferably diffractive) can be characterized by its TFMTF (Modulation Transfer Function Through Focus) curve.
Such a curve represents the quality of the lens (in percentage or in the form of a ratio between 0 and 1of contrast of the image for an initial object having a contrast of 100%) as a function of the distance of vision (which is described in addition in Diopters: 0D=distance vision; +1 to +2D=intermediate vision; 3D=near vision).
Such curves are simulated with an optical simulation software program such as the software program Zemax (trademark) of the company of the same name for intraocular implants placed in a mean eye model.
A TFMTF curve is established for a given spatial frequency. Usually for multifocal implants, the TFMTF at 50 cycles/mm is advantageous. But TFMTF at 25 cycles/mm (coarser objects) and 100 cycles/mm (finer objects) are also advantageous.
A TFMTF curve at 50 cycles/mm (for example) of a given optical profile depends on the pupil of the optical system and the wavelength of the light used.
Thus, preference may be given to a wavelength corresponding to the color green (546 nm), but it can also be advantageous to plot the photopic TFMTF curve corresponding to the integral of the wavelengths of daylight, and also to the scotopic TFMTF curve (night vision).
Similarly, preference is given to a pupil of 3 mm in diameter (corresponding to well-lit vision such as a situation of reading or daytime vision), but the complementarity of TFMTF can be advantageous for pupils of 2 to 6 mm in diameter.
A TFMTF value greater than or equal to 0.15 is considered to provide vision that is nearly satisfactory to the wearer, whereas a TFMTF value greater than or equal to 0.30 is considered to provide distance vision satisfactory to the wearer.
Near vision "VP" is typically +3D (in corneal plane addition) but can be between +2D and +4D.
Intermediate vision "VI" is typically +1.5D (in corneal plane addition) but can be between +1D and +2D.
If the TFMTF curves of an implant placed in an eye make it possible to provide information about the optical quality of the implant, the physical quantity that translates the correct vision of the wearer is its visual acuity.
Visual acuity depends on the TFMTF of the implant, but also other parameters such as the sensitivity to contrast of the wearer. In binocular vision, visual acuity also depends on the neuronal processing of the patient who combines the information coming from his two eyes.
Thus, even if it is not possible to directly simulate the visual acuity (AV) of a wearer as a function of the implant used, it is known that the AV curve has a shape that follows that of the TFMTF curve, but with a wider envelope.
In binocular vision, the superimposition of two peaks present on the TFMTF curves for one and the same addition makes it possible to slightly improve the visual acuity.
Thus, for example, a near visual acuity of 8/10 on one eye and of 8/10 on the other eye can give a binocular visual acuity of 10/10.
This is illustrated in the appended FIG. 1, wherein are shown in solid lines the superimposed TFMTF curves of two identical implants of +3D addition, for a pupil of 3 mm in diameter and a wavelength of 546 nm (on the abscissa: addition expressed in Diopters/on the ordinate: TFMTF at 50 cycles/mm), whereas the estimate of the TFMTF curve in binocular vision is shown in broken lines.
On the other hand, when both eyes have a slightly shifted TFMTF peak (for example with implants of additions of +2.5D and +3D respectively), the binocular AV combines the peaks giving 8/10 at 2.5D and 8/10 at 3D. It is the well-known principle of "Mix and Match" in intraocular implants where two implants identical but with a different addition (same curve shape but shifted near vision peaks) are used.
This is illustrated in the appended FIG. 2 wherein the parameters are the same as those used above with reference to FIG. 1, the characteristic curves of the two implants being referenced A and B.
But the limitation of this practice is that the difference between the two apices of the VI (intermediate vision) and VP (near vision) peaks must be limited to be well-tolerated by the wearer. This difference is usually at 0.5D or even 0.75D (for additions of approximately 2.5D), as the area of overlap between the two curves in near vision is small.
When both eyes have implants with differences in addition greater than 0.75D, there is, among most wearers, a suppressive effect (the "defocused" eye therefore having a very low TFMTF) in VI which will make the VI peak of the adapted eye decrease, and vice versa).
Again, this situation is illustrated in FIG. 3 wherein the parameters are the same as those used above with reference to FIG. 2, the overly large difference between the apices of the peaks being referenced EA.
The present invention aims to palliate these difficulties, by proposing multifocal implants which, when worn together, not only allow the wearer to have good distance vision, but also to enjoy continuous depth of field in binocular vision between intermediate vision and near vision.

Assembly consisting of a pair of multifocal ocular implants