A two-phase paint and ink stripper composition comprises an aqueous phase containing a basic activator in the form of an amino-alkyl-alkanol and an organic phase which contains an alkylene carbonate and organic solvents. The paint stripper composition of the present invention is free from methylene chloride and does not contain monoethanol amine.

The present invention relates to a method of stripping paint and ink from a substrate. The stripper comprises an aqueous phase and an organic phase.
With the introduction of new and more durable types of synthetic resins and polymers in protective and decorative coatings, the problem of stripping has become increasingly difficult. Prior art paint removers typically contain blends of aromatic solvents, ketones, paraffin, methanol and diluents, for example, mineral spirits in order to reduce raw material costs. Those prior art strippers made with the foregoing solvents focused industry attention on the flammable and toxic characteristics.
As an alternative, improved prior art solvents utilize chlorinated solvents as a way to extend the usefulness of paint strippers while simultaneously reducing fire hazards associated with their use. Methylene chloride (dichloromethane) has been almost universally used as the solvent of choice, although some compositions have been formulated with ethylene dichloride and trichloroethylene, among other chlorinated hydrocarbon solvents. Many of the chlorinated hydrocarbons including methylene chloride are suspected carcinogens and methylene chloride is designated a hazardous substance under the Federal Hazardous Substance Act (FHSA). In addition, methylene chloride, as a high vapor pressure chlorinated solvent, probably contributes to atmospheric ozone depletion. Methanol is a poison if ingested and the U.S. Consumer Products Safety Commission requires a warning designating it as a poison when its concentration in consumer products exceeds 4 percent by weight. Toluene contains trace quantities of benzene, a known carcinogen, and acetone with its high vapor pressure and low flash point is highly flammable.
Paint strippers which include methylene chloride can be formulated to soften, lift and blister paint films. The stripper which is applied to the substrate by brush, immersion or spray and allowed to loosen the paint or varnish has an available work life of only several minutes because of the tendency of the methylene chloride to evaporate rapidly. Because of the high vapor pressure of methylene chloride, in an effort to extend the work life of the stripper made with that solvent, paraffin is often included as an evaporation suppressant. The paraffin functions by forming a thin film at the surface of the paint remover which retards evaporation. This thin film formation and resultant evaporation suppressant activity of paraffin is produced by the evaporation and surface chilling which occur when methylene chloride or mixtures containing methylene chloride are exposed to air. However, methylene chloride strippers must be handled carefully since they are highly toxic and can cause severe skin irritation. Further, even with the incorporation of paraffin, the volatility of the methylene chloride is still very high and when methylene chloride is formulated with, for example, toluene, the resulting high levels of hydrocarbon emissions necessitate the provision of good ventilation to safely use the methylene chloride paint strippers.
A further disadvantage of paint strippers formulated with methylene chloride is that the short work life compromises the ability of the stripper to function efficiently in many applications. For example, many industrial uses of paint strippers involve stripping accumulated paint from equipment and walls. Paint strippers utilizing methylene chloride suffer from the disadvantage that the short work life prevents the stripper from entering crevices in the accumulated paint layers thus creating the necessity, in some cases, of applying a large number of applications of stripper to remove a number of accumulated paint layers.
U.S. Pat. No. 6,348,107, issued Feb. 19, 2002, discloses a new method of stripping paint from a painted substrate surface. According to the invention, the surface is contacted with the aqueous phase of a two-phase liquid stripper composition comprising an aqueous phase which comprises water, dissolved water-soluble activator compound, and an organic solvent which has a solubility in water in the range 0.1 to 10% by weight at 20° C., the organic solvent being present in the aqueous phase at a concentration of about the saturation level (as at the ambient conditions for the method) and comprising also an organic phase comprising the said organic solvent, which organic phase is in interfacial contact with the aqueous phase. The organic solvent may include chlorinated hydrocarbons, for instance in combination with other organic solvents.
Suitable organic solvents for use in U.S. Pat. No. 6,348,107 include benzyl alcohol, methylene chloride, dibasic ester, which is an oxygenated solvent composed of a mixture of methyldiesters of glutaric, succinic and adipic acids, or ethyl-3-ethoxy propionate. The dissolved activator compound present in the aqueous phase of the composition may be any compound which increases the paint stripper activity. Such compound may often be a pH modifying compound in the form of an acid. Acid activators are usually organic acids, for instance trichloroacetic, alkyl benzene sulphonic acid, benzoic or lactic acid. The pH modifying compound can also be an alkali, for instance, alkali metal hydroxides, alkaline earth metal hydroxides, alkali metal silicates, and organic basic compounds such as amines or ammonium compounds. Another category of activator compound is an oxidizing agent. Examples of an oxidizing agent include hydrogen peroxide and potassium permanganate.
It is known to use water as an activator compound in organic solvent based paint strippers. Such compositions tend to have low levels of water, for instance less than 10%. Other paint stripper compositions comprising both water and organic solvents which are immiscible with water have been described. Generally emulsifiers are added in quantities such that an emulsion of one phase in the other phase is formed. Such emulsions are storage stable and are required not to separate before use. Alternatively, co-solvents may be added to create a homogeneous single phase system.
Single phase paint strippers containing ethylene carbonate or propylene carbonate and additional solvents such as esters, ethers, alcohols, or pyrrolidones such as N-methylpyrrolidone are known and exemplified by U.S. Pat. Nos. 5,288,335 and 5,449,474. Alkylene carbonate solvents, along with hydrogen peroxide, in an aqueous-based system are disclosed in a series of patents assigned to Huntsman Petrochemical Corporation. Examples of these are U.S. Pat. Nos. 6,040,284; 6,162,776; 6,369,009; and 6,608,012, among others.


An embodiment of this invention provides a zoom lens, which primarily includes, in order from an object side to an image-forming side, a first lens group having positive refractive power; a second lens group having negative refractive power; a third lens group having positive refractive power; a fourth lens group having positive refractive power; a fifth lens group having negative refractive power; and a sixth lens group having positive refractive power; wherein the first lens group comprises a prism, and the second lens group, the fourth lens group, and the fifth lens group are moved toward the third lens group along an optical axial for zooming from a wide-angle end to a telephoto end.

1. Field of the Invention
The present invention relates to zoom lenses, especially to zoom lenses with low cost, high zoom ratio, small size, and good image quality.
2. Description of Related Art
Image-capturing devices, such as digital cameras or digital camcorders, employ a zoom lens and an image sensor to collect an image beam of an object, in which the zoom lens focuses the image beam on the image sensor, which then turns the image beam into digital signals for following processing, transmitting, and storage.
Typically, the zoom lens of the image-capturing devices consists of several lenses. To offer competitive prices, one or more plastic lenses are employed in the zoom lens; however, the plastic lenses come with the disadvantages of moisture and light absorption, and conflict may appear between small size, high zoom ratio, and good image quality when reducing the cost.
Therefore, it would be advantageous to provide a novel zoom lens having advantages of compact size, high zoom ratio, and good image quality when reducing the cost.


A device for mounting double-glazing onto a fixed frame is formed by two distinct members, the first of which at which is mechanically bonded to the double-glazing and the second is secured to the frame. The two members are coupled together by a pivotal connection. This device enables any stress applied to the glass to be considerably reduced, thus prolonging the life thereof and reducing the quantity of adhesive required.

1. Field of the Invention
The present invention relates to insulating double-glazing glass and refers in particular to a device for the mounting thereof on a fixed frame, more preferably onto a preformed border structure defining an opening in a building.
In the following description, the expression "insulating glass" will be also used to include "insulating double-glazing".
Double-glazing according to the present invention is intended to be applied on fixed windows, always to be kept locked shut.
2. Description of the Prior Art
Insulating windows known in the art are conventionally constructed by two sheets of glass between which a metal frame is interplaced and bonded together by a sealant along their peripheral edges.
The frame serves to define an air space between the sheets of glass and also contains dehydrating substances on the inside. The frame is usually employed as a spacer and this term will be used in the following description.
The sheets of glass and the spacer are bonded together by two sealing agents. The first sealant is butyl-based in order to prevent moisture seepage into the air space and avoid internal misting of the sheets of glass. The second sealant acts to bond together the components of the insulating glass and protect them from the outside atmospheric conditions.
Insulating double-glazing thus prepared is then mounted, by methods already known in the art, on pre-constructed frames which are in turn mounted on building walls.
In a modified embodiment, the double-glazing can be fixed directly onto the window structure with fastening members, thereby improving its appearance in that none of the components of the structure are shown apart from the glass.
The sealant used for securing the insulating glass onto the building structure is a commercially available high-strength adhesive, particularly suited to such applications, which is commonly known as structural silicone. This term will hereinafter used.
As said hereinbefore, the inner sheet of the insulating glass is secured to the building structure by bonding, whereas the outer sheet is held fast by the cohesive force exerted by the structural silicone inserted into the peripheral cavity between the outer edges of the two sheets of glass and the spacer.
Consequently, under particularly severe environmental conditions, such as a strong winds or heavy rain, or in the event of excessive structural strain impairted there to by the building, a partial or total breaking of the structural silicone junctions between the sheets could occur thereby detaching the insulating glass from the building face.
It should also be noted that following the above indicated assembly procedure, the quantity of structural silicone required to hold together the sheets forming the insulating glass and to bond the insulating glass to the building structure is rather large. In fact, each element is bonded to the adjacent one and these bonds must also ensure the required sealing.

Device for mounting insulating double-glazing onto a fixed frame


A detachable large-bore regular barrel of a shotgun is replaced by a light-weight, thin-walled, carrier barrel having a bore in which a smaller-bore tube and an adapter are mounted. This enables the shotgun to fire a smaller-gauge shotgun shell without changing the weight and balance of the gun, since the combined weight of the carrier barrel, tube and adapter matches that of the regular barrel and those parts are designed to provide the same balance. The carrier barrel is provided with the same kind of shell ejector/extractor as the regular barrel. The adapter comprises a tubular member which defines a firing chamber for the smaller-gauge shotgun shell and is disposed in the breech end of the carrier barrel bore, being threadedly connected to the tube therein. The tubular member of the adapter prevents inadvertent insertion of a larger gauge shotgun shell into the carrier barrel and thus provides a safety feature. The adapter further comprises a slidable component which is slidably mounted on the breech end of the tubular member and engages a flange on the base end of the smaller gauge shotgun shell in the firing chamber of the tubular member. The slidable component is engaged with the ejector/extractor on the carrier barrel and is responsive to movement thereof from retracted to either eject or extract position to effect ejection or extraction of the smaller gauge shotgun shell.

1. Field of Use
This invention relates to replacement means for replacing a detachable regular barrel of a shotgun to enable firing of a smaller-gauge shotgun shell without altering the weight and balance of the shotgun.
In particular, it relates to improved shell ejector/extractor means in such replacement means.
2. Description of the Prior Art
One type of shotgun comprises a receiver, a shoulder stock connected to the rear of the receiver, a fore-end iron pivotally connected to the front of the receiver, and a regular barrel detachably connected to the fore-end iron. The regular barrel may have a single bore or a double-bore (side-by-side or over-and-under). In any case, each bore has a predetermined gauge and is adapted to have a shotgun shell of the same gauge fired therein. The regular barrel has a shell ejector/extractor which is operated by an ejector/extractor operating mechanism which is mounted on the shotgun, either in the receiver or on the fore-end iron. This mechanism is constructed so as to ascertain whether or not a shotgun shell in a barrel bore has been fired. This mechanism is actuated when the regular barrel is swung or pivoted downwardly from breech-closed to breech-open position to effect forceful ejection of a spent shell casing or to effect slight movement of an unfired live shell to a position wherein it can be manually removed.
A 12 gauge double-barrel over-and-under shotgun of the aforedescribed type, designated as a Model K-80 Skeet Gun, is manufactured by Krieghoff International, Inc., of West Germany, and is commercially available in the U.S.A. through P.O. Box 549, Ottsville, Pa., 18942.
Heretofore, if a shooter using a shotgun of the aforesaid type desired to fire shotgun shells of smaller gauge than the predetermined gauge, either to comply with the rules of a different class of sport shooting or for reasons of economy, he had two options. First, he could replace the detachable regular barrel with a compatible replacement barrel of the desired smaller gauge. However, this required having available one or more replacement barrels, each of which is extremely expensive. However, the advantage of this first option is that a replacement barrel of smaller gauge can be constructed to have the same weight and balance as the regular barrel so as not to affect the aim or technique of the shooter. Second, instead of replacing the regular barrel with a replacement barrel he could insert therein a tube having a firing chamber and bore of the desired smaller gauge. Such tubes are commercially available individually or in sets of different smaller gauges. While this second option is more economical than the first, the major disadvantage is that the use of the tube in the bore of the regular barrel added to the overall weight of the shotgun and changed its balance, thereby adversely affecting the aim and technique of the shooter.

Shotgun shell ejector/extractor means for skeet gun carrier barrel having smaller gauge tube therein


A video projector including a plurality of light sources is configured to project and display an image using light emitted from at least one of the light sources so that each light source is replaceable while other light sources are lit. The video projector includes a light source replacement detection unit that detects replacement of one or more light sources, a memory unit that stores information related to a combined lighting state of the light sources, and a control unit that changes the combined lighting state of the light sources when the replacement of at least one light source is detected without displaying, on the projected image, a setting screen used to change the combined lighting state.

The present invention relates to a video projector including a plurality of light sources.
Japanese Laid-Open Patent Publication No. 2009-31715 discloses a video projector including a plurality of light sources. The video projector combines the light emitted from the light sources. In such a structure that combines the light emitted from the light sources, for example, when one of four light sources cannot be lit, an image can still be entirely displayed using the remaining three light sources.
A projector such as a video projector generally includes an on-screen display (OSD) function used to set various items (refer to Japanese Laid-Open Patent Publication No. 2009-192711). The OSD is an image presented to the user to set various items, and the OSD function of the video projector is used to project and display such an OSD as an image.
In the video projector described in Japanese Laid-Open Patent Publication No. 2009-192711, when the life of a light source comes to an end and the light source can no longer be lit, the light source can be replaced with a new one.
In a video projector including a plurality of light sources, for example, when one of four light sources cannot be lit, an image can still be continuously displayed using three light sources by changing the lighting state of the light sources, that is, the number of light sources that are lit. By replacing the light source that cannot be lit with a new light source while the other light sources are lit, the number of light sources that are lit to display an image can be changed from three to four.
However, after replacing a light source, when changing the number of light sources from, for example, three to four, an image is presented to the user to set the lighting state of the light sources, that is, an OSD is displayed as an image used to select the combination of the lighting sources that are lit. In such a case, at least part of an image cannot be displayed.


A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

This invention relates to dynamic random access memory devices, and, more particularly, to a method and system for allowing a memory device to be quickly and easily switched into and out of a low power, half density, operating mode.
As the use of electronic devices, such as personal computers, continue to increase, it is becoming ever more important to make such devices portable. The usefulness of portable electronic devices, such as notebook computers, is the limited by the limited length of time batteries are capable of powering the device before needing to be recharged. This problem has been addressed by attempts to increase battery life and attempts to reduce the rate at which such electronic devices consume power.
Various techniques have been used to reduce power consumption in electronic devices, the nature of which often depends upon the type of power consuming electronic circuits that are in the device. For example, electronic devices, such a notebook computers, typically include dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) devices that consume a substantial amount of power. As the data storage capacity and operating speeds of DRAM devices continues to increase, the power consumed by such devices has continued to increase in a corresponding manner.
A variety of operations are performed in DRAM devices, each of which affects the rate at which the DRAM device consumes power. One operation that tends to consume power at a substantial rate is refresh of memory cells in the DRAM device. As is well-known in the art, DRAM memory cells, each of which essentially consists of a capacitor, must be periodically refreshed to retain data stored in the DRAM device. Refresh is typically performed by essentially reading data bits from the memory cells in each row of a memory cell array and then writing those same data bits back to the same cells in the row. This refresh is generally performed on a row-by-row basis at a rate needed to keep charge stored in the memory cells from leaking excessively between refreshes. Since refresh essentially involves reading data bits from and writing data bits to a large number of memory cells refresh tends to be a particularly power-hungry operation. Thus many attempts to reduce power consumption in DRAM devices have focused on reducing the rate at which power is consumed during refresh.
The amount of power consumed by refresh also depends on which of several refresh modes is active. A Self Refresh mode is normally active during periods when data are not being read from or written to the DRAM device. Since portable electronic devices are often inactive for substantial periods of time, the amount of power consumed during Self Refresh can be an important factor in determining how long the electronic device can be used between battery charges.
One technique that has been used to reduce the amount of power consumed by refreshing DRAM memory cells is to vary the refresh rate as a function of temperature. As is well known in the art, the rate at which charge leaks from a DRAM memory cell increases with temperature. The refresh rate must be sufficiently high to ensure that no data is lost at the highest temperature in the specified range of operating temperatures of the DRAM device. Yet, DRAM devices normally operate at a temperature that is substantially lower than their maximum operating temperature. Therefore, DRAM devices are generally refreshed at a rate that is higher than the rate actually needed to prevent data from being lost, and, as a result, unnecessarily consume power. To address this problem, some commercially available DRAM devices allow the user to program a mode register to select a lower maximum operating temperature. The DRAM device then adjusts the refresh rate to correspond to the maximum operating temperature selected by the user.
Although adjusting the refresh rate as a function of temperature does reduce the rate of power consumed by refresh, it nevertheless still allows power to be consumed at a significant rate for several reasons. For example, although the refresh rate may be reduced with reduced maximum operating temperature, the refresh may still result in refreshing a large number of memory cells that are not actually storing data.
Another approach to reducing the rate at which power is consumed by a refresh operation is to refresh less than all of the memory cells in the DRAM device in attempt to refresh only those memory cells needed to store data for a given application. As described in U.S. Pat. No. 5,148,546 to Blodgett, a software program being executed in a computer system containing the DRAM devices is analyzed to determine the data storage requirements for the program. The DRAM device then refreshed only those rows of memory cells that are needed to store data. In another approach, the DRAM device may be operated in a partial array self refresh (xe2x80x9cPASRxe2x80x9d) mode. In the PASR mode, a mode register is programmed by a user to specify a bank or portion thereof of memory cells that will be used and thus must be refreshed. The remaining memory cells are not used and thus need not be refreshed during at least some refresh modes. Although these techniques for refreshing less than all of the memory cells in a memory device can substantially reduce the rate of power consumption, it can nevertheless require a substantial amount of power to refresh the cells that are to be refreshed.
Still another technique that can be used to reduce the rate of refresh involves operating DRAM devices in a half density mode. A DRAM device that may be operated in a half density mode is described in U.S. Pat. No. 5,781,483 to Shore. In the half density mode, the low order bit of each row address, which normally designates whether the addressed row is even or odd, is ignored, and both the odd row and adjacent even row are addressed for each memory access. In a folded digit line architecture, activating an odd row will couple each memory cell in the row to a respective digit line, and activating an even row will couple each memory cell in the row to a respective complimentary digit line. Thus, for example, writing a xe2x80x9c1xe2x80x9d to an addressed row and column would result in writing a logic xe2x80x9c1xe2x80x9d voltage level to the memory cell in the addressed odd row and writing a logic xe2x80x9c0xe2x80x9d logic level to the memory cell in the addressed even row. Reading from the addressed row and column results in a logic xe2x80x9c1xe2x80x9d voltage level being applied to the digit line for the addressed column and a logic xe2x80x9c0xe2x80x9d voltage level being applied to the complimentary digit line for the addressed column. Therefore, in the half density mode, a sense amplifierlifier coupled to the digit line and complimentary digit line for each column receives twice the differential voltage that it normally receives when reading a memory cell at an addressed row and column.
The patent to Shore describes the use of the half density mode for the purpose of allowing the DRAM device to be used despite the presence of defective memory cells. If a memory cell in an addressed row and column is defective, the data bit stored in that memory cell can still be recovered from the other memory cell in the addressed row and column. However, it has been recognized that the half density mode can be used to reduce that rate at which power is consumed during refresh. Although a refresh in the half density mode requires twice as many memory cells to be refreshed for a given amount of stored data, the required refresh rate is less than half the required refresh rate when the DRAM device is operating in the full density mode. The substantially lower refresh rate required in the half density results from the increased differential voltage that is applied to the sense amplifierlifiers in the half density mode, as previously explained. As a result, the memory cells can be allowed to discharge to a greater degree between refreshes without the data bits stored therein being lost. Therefore, storing data in the half density mode can reduce the rate of power consumption during refresh
In conventional DRAM devices, the density mode, i.e., either half or full, is generally determined prior to sale of the device. If the power consumption of the DRAM device is of concern, the half density mode can be selected. Otherwise, the full density mode can be selected. Yet many power management algorithms for electronic devices containing DRAM devices, such as notebook computers, switch to a low power mode when the electronic device is inactive and back to a high power mode when the electronic device is active. It is therefore necessary for electronic devices to be able to frequently switch back and forth between low power and high power modes.
In conventional DRAM devices, it is not possible to switch between a full density mode and a half density mode. This limitation may be due to the difficulty in making this transition. The difficulty of being able to rapidly switch between the full density mode and the half density mode primarily results from two requirements. First is the need to first free-up alternate rows of memory cells into which data from an adjacent row of memory cells can be transferred for half density storage. The second requirement is the need to transfer data from the memory cells in a row storing data to a memory cell in the adjacent row once the adjacent row has been freed up by transferring data to another row. More particularly, if the DRAM device is operating in the full density mode, generally data will be stored in both even rows and odd rows of memory cells. To switch to the half density mode would require that the data stored in the even rows of memory cells, for example, be transferred to empty odd rows of memory cells. It would then be necessary to read the data stored in each odd row, and write the read data to corresponding memory cells in the adjacent even row. Transferring data between memory cells in this manner by conventional read/write operations would require a great deal of time and would therefore preclude quickly switching back and forth between the full density mode and the half density mode. Also, transferring approximately half of the data stored in the DRAM device by conventional read/write operations, which would be necessary to switch from the full density mode to the half density mode, would itself consume a great deal of power. While more efficient row copy schemes have been proposed for test purposes, such as the row copy scheme described in U.S. Pat. No. 5,381,368 to Morgan et al., these row copy schemes are generally suitable only when the same data or a repeating pattern of data are to be written to the entire array of memory cells. Yet switching from the full density mode to the half density mode would require transferring many rows of disparate data bits to respective adjacent rows after freeing up the adjacent rows by transferring the disparate data bits to other rows. It therefore does not seem possible to easily transition between the half density mode and the full density mode.
There is therefore a need for a power-saving technique that would allow switching into and out of a half density, low refresh rate mode without requiring time and power consuming reading and writing of data to a second set of memory cells.
A system and method according to the invention allows a DRAM device to be easily and quickly switched back and forth between a full density mode consuming power at a relatively fast rate and a half density mode consuming power at a relatively slow rate. The row addresses applied to the DRAM device are reordered by remapping the most significant bit of each row address to the least significant bit of the row address during all operating modes. As a result, all of the odd (or even) rows of the DRAM array are populated with data before any of the even (or odd) rows are populated with data. As long as the data stored in the DRAM device uses less than half of the capacity of the DRAM device, data will then be stored only in alternate rows, and the row adjacent each row in which data are stored will be free to store data. When the DRAM device is to be switched from the full density mode to the half density mode, data stored in each row is simply transferred to the adjacent row. Thereafter when operating in the half density mode, the row corresponding to each row address and the adjacent row are accessed at the same time. Although the data stored in each row can be transferred to the adjacent row by a variety of techniques, it is preferably transferred by transferring the data from each row to the adjacent row during the first refresh of the row. More particularly, when a row is first refreshed after the DRAM device has been switched to the half density mode, the sense amplifierlifiers are left active so that the voltage levels corresponding to the data stored in the memory cells being refreshed are maintained on the respective digit line pairs. The adjacent row is then activated thereby transferring the voltage on the digit lines to the memory cells in the adjacent row. Once the data have been transferred to the adjacent rows during refresh at the full density refresh rate, the refresh rate can be significantly reduced during operation in the half density mode.

Method and system for low power refresh of dynamic random access memories


Techniques for de-modulating a high-supply-domain differential signal and a common-mode clock in a front-end receiver are described herein. In one embodiment, a method for receiving a signal comprises receiving the signal via a receiver input, the received signal comprising a differential signal and a common-mode clock signal. The method also comprises shifting the received signal from a first voltage range to a second voltage range that is lower than the first voltage range, and providing the shifted received signal on a first level-shifted signal line and a second level-shifted signal line. The method further comprises sensing voltage differences between the first and second level-shifted lines to recover the differential signal, and sensing common-mode voltages on the first and second level-shifted signal lines to recover the common-mode clock signal.

1. Field
Aspects of the present disclosure relate generally to receivers, and more particularly, to systems and methods for de-modulating a high-supply-domain differential signal and a common-mode clock in a front-end receiver.
2. Background
A device may include a front-end receiver for receiving an incoming signal from another device. The front-end receiver may perform front-end processing on the received signal before forwarding the signal to other components in the device for further processing. The other components in the device may include core devices (e.g., core transistors) that are not capable of handling the voltage levels of the incoming signal. Therefore, it may be difficult to receive the incoming signal without creating reliability issues at the core devices.
In some applications, the incoming signal may comprise a differential data signal and a common-mode clock signal. An example of such a signal is a multimedia high-definition link (MHL) signal in which a high-speed differential data signal is modulated with a low-frequency common-mode clock signal. In these applications, it may be difficult to separately process the differential data signal and the common-mode clock signal in the incoming signal.

System and method for de-modulating a high-supply-domain differential signal and a common-mode clock in a front-end receiver


A structured scintillator and a detection system employing structured scintillators. More specifically, a structured scintillator comprising a scintillator material having a plurality of isolated structures is disclosed. The structures may be conical in shape. The structures may be formed on a substantially transparent material layer which has been patterned to form a plurality of isolated regions. The structures may be formed on top of the isolated regions to provide isolated scintillator structures having space therebetween. The isolated regions and scintillator structures may be aligned with underlying detection devices.

The invention relates generally to radiation detection systems. More specifically, it relates to a structured scintillator which may be employed in an x-ray detection system.
Many digital photo detection systems employ scintillators to convert incident radiation into light for detection at a light detection device, such as a photodiode. A scintillator is a device or substance that absorbs high energy (ionizing) electromagnetic or charged particle radiation then, in response, fluoresces photons at a characteristic Stokes-shifted (longer) wavelength, releasing the previously absorbed energy. Scintillators are defined by their short fluorescence decay times and optical transparency at wavelengths of their own specific emission energy, characteristics which set them apart from phosphors.
As will be appreciated, scintillator crystals are widely used in detectors for x-rays, gamma rays, cosmic rays, and particles characterized by an energy level of greater than about 1 keV. From such crystals, it is possible to manufacture detection systems, in which the crystal is coupled with a light-detection device, such as a photodetector. When ionizing radiation impacts the crystal, the crystal emits light. The photodetector produces an electrical signal proportional to the number of light pulses received, and proportional to the intensity of the light pulses. Photodetectors are commonly used for many applications, such as medical imaging equipment, e.g., positron emission tomography (PET) devices, well logging for the oil and gas industry, and various digital imaging applications. However, there are numerous problems associated with the use of conventional detection systems in typical applications, as described further below.
In flat panel detection systems, light is generated and detected isotropically. In order to achieve good image quality, the position of incoming light should be accurately recorded. Accordingly, it is desirable to minimize the lateral spreading of photons generated in the scintillator. In certain applications, it may be advantageous to employ x-ray detection arrays, which allow bending such that the detector can be conformed to various non-planar shapes. In such applications, the scintillator may also be flexed. Because of the typical construction of scintillators, the bending of the scintillator may damage the scintillator of conventional devices.
Therefore there is a need for improved scintillators that may be employed in x-ray detection systems.

Structured scintillator and systems employing structured scintillators


This infrared imaging element includes: a substrate which has a front surface and a back surface and to which a circuit unit is provided; a support leg wiring line that is disposed above the front surface of the substrate; and an infrared-ray detection unit which is held on the support leg wiring line and to which a diode electrically connected to the circuit unit via the support leg wiring line is provided, wherein the temperature change of the infrared-ray detection unit is detected as an electrical signal change of the diode by the circuit unit. The substrate, the support leg wiring line, and the infrared-ray detection unit are laminated at intervals in a direction perpendicular to the front surface of the substrate.

In a general thermal infrared solid-state imaging element, pixels having a heat insulation structure are two-dimensionally arranged, and an infrared image is captured by using a change in temperature of the pixels due to incident infrared ray. In the case of a thermal infrared solid-state imaging element, for example, a semiconductor element such as a diode is used as a temperature sensor constituting a pixel. In the case of using a semiconductor element, the variation in the electric characteristics and the temperature dependence between elements is very small, so that the characteristic of each pixel can be made uniform.
In a thermal infrared solid-state imaging element using a diode as a temperature sensor, pixels are two-dimensionally arrayed, connected to drive lines for each row, and connected to signal lines for each column. The drive lines are selected in order by the vertical scanning circuit and the switch, and power is supplied from the power source to the pixels through the selected drive lines. The output of the pixel is transmitted to an integration circuit through a signal line, integrated and amplified by the integration circuit, and sequentially output to an output terminal by a horizontal scanning circuit and a switch (for example, see Non-Patent Document 1).

Infrared imaging element, infrared imaging array, and method for manufacturing infrared imaging element


The present invention relates to poly(ester-ether) compositions and to a process for their preparation. In particular, the invention relates to poly(ester-ether) compositions obtained by reacting a polyester which is prepared from a dicarboxylic acid and an aliphatic diol with a dihydroxy aromatic compound in the presence of a metal catalyst. Incorporation of the dihydroxy aromatic compound into the polyester chain causes an increase in the Tg value and increases the thermal stability of the polyester. These poly(ester-ether) compositions are useful in molded articles of all types.

When a polyester is treated at elevated temperatures with a diol, the expected reaction is a transesterification reaction in which diol moieties of the polyester chain are liberated and new diol moieties are inserted into the polyester chain. In contrast, the present inventors have unexpectedly discovered that where the diol reactant is different from that of the diol moieties in the starting polyesters, copolymers are obtained. More specifically, the present inventors have determined that dihydroxy aromatic compounds inserted into the chain of a polyester which is prepared from a dicarboxylic acid and an aliphatic diol, have predominantly ether linkage rather than ester linkages. Thus, poly(ethylene terephthalate) treated with hydroquinone, for example, has mono- and diether linkages. Incorporation of the dihydroxy aromatic compounds into the polyester chain causes an increase in the glass transition temperature (Tg) value and the thermal stability of the polyester. For example, the Tg value of poly(ethylene terephthalate) has been increased from 72.degree. C. to 100.degree. C. by modification with certain dihydroxy aromatic compounds.

Poly(ester-ether) compositions having increased thermal stability


A fuel tank filler port cap assembly having an adapter for use with a vapor recovery dispensing nozzle to aid in filling a fuel tank of a motorcycle such as to allow complete filling of the tank while reducing spills and allowing the safety and environmental features of the vapor recovery dispensing nozzle to work is herein disclosed. The adapter includes a cylindrical cover base that engages the opening on the fuel tank and forms a vapor tight seal. A tubular inner sleeve is extendably from the cover base and has a top having an opening which engages the accordion-like collar on the fuel dispenser nozzle equipped with vapor recovery or vapor conservation nozzles. In such a manner, the tank and nozzle connection remain intact, but the nozzle remains mostly out of the tank allowing the fuel tank to be completely filled.

In order to reduce atmospheric pollution, fumes displaced from an automobile gasoline tank during filling at a filling station are often recovered. In order for the vapor recovery process to work reliably, it is important that a good seal be made between the vapor recovery shroud of the nozzle and the opening of the fill tank. While this is typically easy to accomplish on a motor vehicle with a long fill neck, it is difficult on a motorcycle fuel tank due to the fact that the opening is on the surface of the vessel with no neck. As such, the nozzle must be pushed a considerable way inside the tank body for the shroud to seal against the tank. However, the nozzle then senses the rising fuel during filling and shuts off the flow long before filling is complete. This means that the interval between tank fill ups is decreased and trip range is decreased as well.

Fuel tank filler port cap with nozzle adapter


A method of laying up a segment on a layup surface using a layup head that is mobile with respect to the layup surface, the layup head supporting a spool of a tape of material which includes at least one layer to be laid up from which said segment is cut and at least one interliner, the method including applying the tape of material against the layup surface and removing the interliner using a separator. The tape of material is pressed firmly by a press roller against the layup surface before the interliner is removed as the layup head moves in an advancing movement. A layup head for implementing the method and a layup machine including the layup head are also described.

In the field of aeronautics, parts made of composite and used to create an aircraft fuselage comprise lightning protection at their exterior surfaces. This lightening protection comprises at least one layer made of a material suited to affording lightening protection, such as, non limitingly, at least one layer of fiber glass fabric and/or a fine metal gauze.
This layer providing lightning protection is obtained by laying up a plurality of segments of tape, in juxtaposed manner, on a layup surface.
According to one way of packaging, the tapes comprise an interliner, for example made of paper, on one of their faces and are stored in spools. They have a given width of the order of 150 mm or 300 mm. These tapes are generally precut to form segments of tape which have a length and cuts at each of their ends that are suited to allowing the various segments of tape to be laid up one after another and/or one beside the next so that they cover the entire exterior surface of the component that is to be produced.
According to one procedure, the various segments of tape are laid up manually by operators on the layup surface which may be the surface of a tool or the surface of the last layer laid. To make the task easier, a laser projection assistance system is used to project the outlines of the various juxtaposed segments onto the layup surface.
This layup operation proves to be difficult to carry out on a layup surface of large surface area, such as a wing panel for example, and/or one which has a significant curvature, such as a fuselage segment for example.
The problem is that, for long length segments, it is essential that they be correctly oriented from the outset otherwise there will be a gap or an overlap with respect to the next segment which will increase as the laying of the segment processes. If the operator attempts to correct the orientation of the segment during the process of laying it up, creases may appear in the segment.
In the case of large surface areas, the operators cannot work ergonomically. In some instances, they are obliged to walk over the layup surface and possibly on the segments already laid up.
In order to create parts made of composite from carbon fiber pre-impregnated with resin, it is known practice to use layup machines for automatically laying up carbon fiber tapes which have been pre-impregnated with resin, packaged in the form of spools with an interliner on one of their faces. According to one embodiment illustrated in FIG. 1, a layup machine comprises a layup head 10 and a mechanism (not depicted) that allows the layup head 10 to be moved with respect to a layup surface 12 in a layup direction embodied by the arrow 14. The layup head 10 comprises a support configured to support a spool 16 from which a tape 18 to be laid up on the layup surface 12 is paid out, a layup roller 20 allowing the tape 18 to be pressed firmly against the layup surface 12. The layup head 10 also comprises a separation roller 22 that allows the interliner 24 to be removed from the tape 18 and a roller 26 that allows the interliner 24 to be stored in the form of a spool. The separation roller 22 is positioned between the spool 16 and the layup roller 20 and allows the interliner 24 to be removed before the tape 18 is compressed between the layup roller 20 and the layup surface 12. Thus, the tape 18 comprises a zone between the separation roller 22 and the layup roller 20 in which there is no interliner 24.
With this embodiment, the combination of the advancing movement of the layup head 10 and the action of compacting the tape 18 performed by the layup roller 20 allows tension to be applied to the tape 18, causing the paying-out from the spool 16.
This type of layup head is perfectly well suited to carbon fiber tapes which have a certain rigidity and good tensile strength.
Because lightning protection tapes do not have the same characteristics as carbon fiber tapes, this type of layup head is not suitable for laying them up automatically on a layup surface, the reasons being as follows:
In the absence of the interliner 24, the lightning protection tapes may deform locally, or even tear in the event of excessive tension. Now, as illustrated in FIG. 1, there is a zone 28 of tape between the separation roller 22 and the layup roller 20 which is separated from the interliner 24 and may undergo excessive tensile loading.
In addition, in the absence of the interliner 24, the lightning protection tape 18 does not have a certain rigidity. As a result, when a segment of the tape is completely separated from the interliner 24, a part 30 of said segment finds itself unsupported ahead of the layup roller 20. Insofar as this part 30 does not have a certain rigidity, it has a tendency to curl on itself ahead of the layup roller 20 and so is not correctly pressed firmly against the layup surface 12, as illustrated in FIG. 2.

Method for laying up a tape of material and device for implementing same


Food products, typically having a moisture content above 50% by weight, are prepared which contain polysaccharide hydrocolloid and insoluble fiber at a weight ratio of 1:0.2-3.5:1.1-4.5. These materials are preferably added to the food product as an aqueous dispersion. The aqueous dispersion preferably also contains a protein material. This invention is particularly useful in the preparation of fat-free food products.

Many prior art disclosures recite the-incorporation of materials such as gums, cellulosic fiber or protein into food products in a manner to either partially or fully replace fat. Among such prior art disclosures are U.S. Pat. Nos. 4,143,163 to Hutchinson et al.; 4,308,294 to Rispoli et al.; 4,734,287 to Singer et al.; and published EPO application 340,035 and published PCT application 89/01813 both to Chen et al.

Polysaccharide hydrocolloid-containing food products


The present invention relates to oxocarbon-, pseudooxocarbon- and radialene compounds as well as to their use as doping agent for doping an organic semiconductive matrix material, as blocker material, as charge injection layer, as electrode material as well as organic semiconductor, as well as electronic components and organic semiconductive materials using them.

The present invention relates to oxocarbon-, pseudooxocarbon- and radialene compounds as well as to their use as organic doping agent for doping an organic semiconductive matrix material for changing its electrical properties, as blocker material as well as charge injection layer and as electrode material. The invention also relates to organic semiconductive materials as well as to electronic components in which the oxocarbon-, pseudooxocarbon- and radialene compounds are used.
In the present application alicyclics in which all ring atoms are sp2-hybridized and to the extent possible carry exocyclic C—C double bonds are designated as radialenes, see also H. Hopf and G. Maas, Angew. Chem. (1992), 8, 955. Oxocarbon- and pseudooxocarbon compounds are sufficiently known as non-benzoid aromatics, see, e.g., G. Seitz, Nachr. Chem. Tech. Lab. 28 (1980), pages 804-807. The first oxocarbon compound, potassium croconate, was produced by L. Gmelin in 1825 from potash and coal. Those compounds, in which at least one oxygen atom is replaced by another heteroatom, are designated as pseudooxocarbons, as is readily known to an expert in the art.
It has been known for several years that organic semiconductors can be heavily influenced regarding their electrical conductivity by doping. Such organic semiconductive matrix materials can be built up either from compounds with good electron donor properties or from compounds with good electron acceptor properties. Strong electron acceptors such as tetracyanoquinonedimethane (TCNQ) or 2,3,5,6-tetrafluoro-tetracyano-1,4-benzoquinonedimethane (F4TCNQ) have become known for the doping of electron donor materials (HT), M. Pfeiffer, A. Beyer, T. Fritz, K. Leo, Appl. Phys. Lett., 73 (22), 3202-3204 (1998). and J. Blochwitz, M. Pfeiffer, T. Fritz, K. Leo, Appl. Phys. Lett., 73 (6), 729-731 (1998). They generate so-called holes by electron transfer processes in electron donor-like base materials (hole transport materials) by the number and mobility of which holes the conductivity of the base material is more or less significantly changed. For example, N,N′-perarylated benzidines TPD or N,N′,N″-perarylated starburst compounds such as the substance TDATA, or, however, also certain metal phthalocyanines, such as in particular zinc phthalocyanine ZnPc are known as matrix material with hole transport properties.
However, the previously described compounds have disadvantages for a technical use in the production of doped semiconductive organic layers or of corresponding electronic components with such doped layers since the manufacturing processes in large-scale production plants or those on a technical scale can not always be sufficiently precise, which results in high control—and regulating expense within the processes for achieving a desired product quality or in undesired tolerances of the products. Furthermore, there are disadvantages in the use of previously known organic donors with regard to electronic components such as light-emitting diodes (OLEDs), field effect transistors (FET) or solar cells themselves since the cited production difficulties in the handling of the doping agents can lead to undesired irregularities in the electronic components or in undesired ageing effects of the electronic components. However, it should be considered at the same time that the doping agents to be used have extremely high electron affinities (reduction potentials) and other properties suitable for the application case since, e.g., the doping agents also co-determine the conductivity or other electrical properties of the organic semiconductive layer under given conditions. The energetic positions of the HOMO of the matrix material and of the LUMO of the doping agent are decisive for the doping effect.
The present invention has the task of overcoming the disadvantages of the state of the art, in particular to make new organic mesomeric compounds available that can be used in particular as doping agent for the doping of organic semiconductors, that can furthermore be more readily handled in the production process and that result in electronic components whose organic semiconductive materials can be reproducibly manufactured
This task is solved, at least in part, by the following organic mesomeric compound and/or the use of the organic mesomeric compound as organic doping agent for the doping of an organic semiconductive matrix material, as blocker layer, as charge injection layer or as organic semiconductor itself, characterized in that the mesomeric compound is an oxocarbon-, pseudooxocarbon- or radialene compound with the following formula:
in which n=1-4; each X1, X2, X3, X4, and X5 is independently selected from the group consisting of C(CN)2, (CF3)C(CN), (NO2)C(CN), C(halogen)2, C(CF3)2, NCN, O, S, NR1,
in which Y═CN, NO2, COR1 or is perhalogenated alkyl; aryl or Ar is a substituted or unsubstituted, aromatic hydrocarbon or biaryl, optionally polycyclic; hetaryl is a substituted or unsubstituted aromatic heterocyclic compound or biheteroaryl, preferably electron-poor, optionally polynuclear or partially or completely hydrogenated or fluorinated; and R1-R8 are independently selected from hydrogen, halogen, CN, NO2, COR1, alkyl, alkoxy, aryl and heteroaryl. In one embodiment, Y is perfluoroalkyl, including, for example, CF3. In another embodiment, aryl or Ar is partially or completely hydrogenated, or partially or completely fluorinated. In a further embodiment, hetaryl is selected from pyridyl, pyrimidyl, triazine, or oxadizole. In a still further embodiment, R1-R8 are independently selected from perhalogenated and/or partially halogenated alkyl groups, including, for example, perfluorinated alkyl groups.

This patent is subject to a terminal disclaimer.

Oxocarbon-, pseudooxocarbon- and radialene compounds and their use


The present invention provides a method of forming a split gate type flash memory. After exposure of a floating gate layer between silicon nitride layers, a conductive layer spacer is formed on a sidewall of the silicon nitride layer pattern. The conductive layer spacer is formed in a floating gate of a later-completed flash memory to form a tip on which tunneling is centralized in an erase operation. That is, the spacer is formed on a sidewall of the silicon nitride layer pattern over the floating gate layer to form the tunneling tip.

This application relies for priority upon Korean Patent Application No. 2001-80483, filed on Dec. 18, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a method of forming a flash memory and, more particularly, to a split gate type flash memory.
Flash memories are non-volatile memory devices with a structure that is suitable for high integration density. Accordingly, recently, the flash memories are intensively studied and developed. In a conventional flash memory device, a memory cell gate pattern is made of a floating gate, a control gate, and a dielectric film interposed therebetween.
A novel dual gate type non-volatile memory is being developed, in which an erase operation is performed toward wordlines from a floating gate to generate a relatively lower erase voltage. Since the floating gate and a control gate of the novel memory are horizontally disposed, an opposite side thereof is relatively reduced and F-N tunneling is centralized to a tip of the floating gate (U. S. Pat. No. 5,029,130).
FIG. 1 and FIG. 2 are cross-sectional views illustrating programming and erasing methods performed in a cell transistor of a non-volatile memory device having a floating gate and a control gate that are horizontally separated with a dielectric film interposed therebetween.
Referring now to FIG. 1, for programming, a high voltage Vdd is applied to a common source line 21 and a threshold voltage Vth is applied to a control gate line 120. Further, a zero voltage (0V) is applied to a drain region 109 and a substrate 100. Thus, electrons are moved from the drain region 109 to a source region 110. By passing a tunneling gate insulating layer 15, the electrons are accumulated into the floating gate 130. That is, the programming is performed.
Referring now to FIG. 2, for erasing, a zero voltage (0V) is applied to the common source line 21 and a high voltage Vdd is applied to the control gate line 120. Further, a zero voltage (0V) is applied to the drain region 109 and the substrate 100. Thus, the electrons accumulated into the floating gate 130 are induced to the high voltage Vdd of the control gate line 120. The induced electrons are moved to the control gate line through the tunneling gate insulating layer 15. That is, the erasing is performed. Since an electric field is centralized to a tip 23 of the floating gate 130, the electrons of the floating gate 130 are moved to the control gate line 109 through an insulating layer adjacent to the tip 23.
FIG. 3 is a top plan view showing a layout in the case where a transistor device is realized in a cell area of a conventional split gate type flash memory. FIG. 4 through FIG. 8 are cross-sectional views, taken along a line Axe2x80x94A of FIG. 3, showing the steps of forming the layout of FIG. 3.
Referring now to FIG. 3, a device isolation layer 103 is formed to define an active region 101 that is formed along line Axe2x80x94A. A common source region or a common source line 21 is formed along a line Cxe2x80x94C. A spacer oxide layer 115, a control gate line or a wordline 120, a spacer nitride layer 125, and a substrate-exposing part are formed parallel to both sides of the common source region 21 or the common source line.
At an intersection of the active region 101 and the substrate-exposing part, a drain region 109 is formed at a substrate. In the drain region 109, a bitline contact 107 will be formed in a subsequent process. As illustrated by bold lines, bitlines 105 are formed along the line Axe2x80x94A to cover the active region 101. At an intersection of the active region 101 and the spacer oxide layer 115, a floating gate 130 is formed under the spacer oxide layer 115.
Referring now to FIG. 3 and FIG. 4, after stacking a tunneling gate insulating layer 15 and a floating gate layer on a substrate 100, a trench type field oxide layer (trench type device isolation layer 103 of FIG. 3) is formed. The floating gate layer is partially removed to remain as a floating gate pattern 131. Alternatively, a tunneling gate insulating layer and a floating gate layer are formed on a device-isolated substrate and by a patterning process, the floating gate pattern may remain only over the active region. A silicon nitride layer 115 is formed on an entire surface of the substrate 100, and then a patterning process is carried out to form a silicon nitride pattern 135 exposing the common source region 110 and the spacer oxide layer 115 of FIG. 3. The floating gate pattern 131 exposed between the silicon nitride patterns 135 is partially subjected to the thermal oxidation. An upper part of the floating gate pattern 135 is then oxidized to cause a bird""s beak where an oxide layer 133 penetrates into a lower part of the silicon nitride pattern 135 at an interface between the patterns 131 and 135.
Referring to now FIG. 3 and FIG. 5, a silicon oxide layer for a spacer is conformally formed on an entire surface of a substrate where the oxidized upper part of the floating gate pattern 131 is removed or unremoved. The silicon oxide layer is etched back to make the spacer oxide layer 115 remain on a sidewall of the silicon oxide layer pattern 135. An unoxidized floating gate pattern 131 is exposed between the spacer oxide layers 115. Using the spacer oxide layer 115 and the silicon nitride pattern 135 as an etch mask, the floating gate pattern 131 is continuously etched to remove the exposed floating gate pattern 131. Concurrently, a tunneling gate insulating layer 15 is removed to expose the substrate 100. Afterwards, impurities are implanted to form a source region 110 at an exposed substrate 100. In one embodiment, this is performed with a dose of 1015 ions/cm2. In a subsequent annealing process, the source region 110 will be extended to partially overlap with a floating gate region.
A section of the floating gate pattern 131 is exposed to a lower part of the spacer oxide layer 115 at a substrate 100 exposed to the source region 110. After/before the implantation of the impurities, a thermal oxidation process is performed or a thin CVD oxide layer is formed to cover the section of the floating gate layer 131.
Referring now to FIG. 3 and FIG. 6, the silicon oxide layer of the source region 110 is removed. A polysilicon layer is then stacked on an entire surface of the substrate to fill a space between the spacer oxide layers. By means of a CMP or an etch-back technique, the polysilicon layer is removed on an upper surface of the silicon nitride pattern 135. As a result, the polysilicon layer remains only in the space between the spacer oxide layers 115 to form a common source line 21.
Referring now to FIG. 3 and FIG. 7, the silicon nitride pattern 135 is removed by phosphoric acid or the like. By means of an anisotropic etch using the spacer oxide layer 115 as an etch mask, the floating gate pattern 131 is removed to form a floating gate 130. Concurrently, an upper part of the common source line 21 may be partially removed. Further, the tunneling gate insulating layer 15 may be concurrently removed to expose the substrate 100. A thin CVD oxide layer is conformally formed on an entire surface of the substrate 100. Alternatively, a thermal oxidation process is carried out to form an oxide layer 116 covering a sidewall of the floating gate 130 exposed below the spacer oxide layer 115 and the exposed substrate 100. During this procedure, the sidewall of the floating gate 130 may be partially oxidized to be laterally protruded.
Referring now to FIG. 8, a polysilicon layer 143 and a silicon nitride layer 145 are conformally formed on an entire surface of the substrate 100 in order to form a control gate or a wordline. The silicon nitride layer 145 may be substituted by a silicon oxynitride layer or the like.
Referring now to FIG. 9, an entire surface of the resultant structure of FIG. 8 is planarized by a CMP process to be even with a top surface of the common source line 21. Thus, the polysilicon layer 143xe2x80x2 is exposed toward the side of the spacer oxide layer 115. On the other hand, the polysilicon layer 143xe2x80x2 covered with a silicon nitride layer 145xe2x80x2 is not exposed. An exposed common source line 21 and the exposed polysilicon layer 143xe2x80x2 are thermally oxidized to form a silicon oxide layer 147.
Referring now to FIG. 10, using the silicon oxide layer 147 and the space oxide layer 115 as an etch mask, the silicon nitride layer 145xe2x80x2 and the polysilicon layer 143xe2x80x2 are sequentially removed. Thus, a polysilicon pattern remains on an opposite side of the common source line 21 of the spacer oxide layer 115 to form a wordline 120.
Alternatively, in the steps of FIG. 8, the polysilicon layer 143 is conformally stacked and anisotropically etched back to make a spacer-shaped polysilicon pattern remain on a sidewall of the spacer oxide layer 115.
Referring now to FIG. 11, another silicon nitride layer is stacked and anisotropically etched back to make the spacer nitride layer 125 remain on the opposite side of the spacer oxide layer 115 of the wordline 120. Heavily doped impurities are implanted into an exposed active region of the substrate 100 to form a drain region 109. In a subsequent annealing process, the drain region 109 may be extended toward a lower part of the spacer nitride layer 125.
After stacking and planarizing an interlayer insulating layer on an entire surface of a resultant structure, a bitline contact hole is formed. A conductive layer, i.e., a metal layer, is stacked on the bitline. The conductive layer is then patterned to form a bitline contact and a bitline.
A cell transistor of a flash memory formed by the foregoing procedure has a few drawbacks. For example, in order to expedite an erase operation, a tip of a floating gate is formed with an acute angle so that an electric field may be concentrated on the tip, as shown in FIG. 2. With reference to a procedure of forming the floating gate in FIG. 4 through FIG. 8, key steps of forming the tip with an acute angle lie in FIG. 4 and FIG. 8. In the step of partially oxidizing the floating gate pattern 131 of FIG. 4, a bird""s beak of both ends of an oxide layer 131 must be short and steep-sloped. In the etching step of FIG. 8, the floating gate pattern 131 must be anisotropically etched.
But in the oxidizing step of FIG. 4, only an upper part of the floating gate pattern 131 must be oxidized because a lower part thereof is to be a floating gate. Due to this restriction, it is hard to form a thick oxide layer by thermally oxidizing the upper part of the floating gate pattern 131. It is also hard to form a steep-sloped bird""s beak at an interface between the floating gate pattern 131 and the silicon nitride pattern 135. As a result, it is hard to form a tip (23 of FIG. 1) with an acute angle.
Furthermore, when the floating gate pattern 131 is partially oxidized (FIG. 4), the oxidization is not limited thereto. As shown in FIG. 12A taken along a line Bxe2x80x94B of FIG. 3, an upper part of the floating gate pattern 131 as well as a lateral part 134 adjacent to the device isolation layer 103 is exposed. Therefore, as shown in FIG. 12B, a lateral part 134 and a lower part 151 are oxidized by oxygen that is introduced through the lateral part when an upper oxide layer 133 of the floating gate pattern 131 is formed.
When a lower part of the floating gate pattern 131 is oxidized near the device isolation layer 103, the tunneling gate insulating layer 15 is to be thick at both lateral parts of a channel (see 151 of FIG. 12B). In a program operation, it is difficult for electrons to pass the thick tunneling gate insulating layer. Therefore, it takes a longer time to accumulate electrons in a floating gate. That is, a program operation speed is lowered in a cell memory transistor.
Moreover, when the lateral part 134 of the floating gate pattern is oxidized, an active region is partially covered with the oxidized lateral part 134, as partially shown in FIG. 12B. In the etch-back for forming the spacer oxide layer 115 of FIG. 5, the oxidized lateral part 134 is removed to expose the substrate 100 adjacent to the floating gate pattern 131. When the floating gate pattern 131 is etched for exposing a source region, the exposed substrate 100 is etched.
As a result, in FIG. 13 taken along a line Cxe2x80x94C of FIG. 3, a substrate 20 contacted with both edges of the source region 110 is removed to form grooves 161, which is called a pitting phenomenon. If implantation of ions into the common source region 110 is not sufficiently deep, a common source line part filling the groove 161 is in direct contact with a neighboring substrate 100 to cause a leakage current.
An object of the invention is to provide a method of forming a split gate type flash memory where a tip is formed with an acute angle.
Another object of the invention is to provide a method of forming a split gate type flash memory that prevents a gate insulating layer below a floating gate from becoming thick.
Still another object of the invention is to provide a split gate type flash memory that prevents a pitting phenomenon and a leakage current in a source region.
The present invention provides a method of forming a split gate type flash memory. The invention comprises exposing a floating gate layer between silicon nitride patterns. A conductive layer spacer is formed on a sidewall of the silicon nitride pattern, and subsequent processes are carried out. In the flash memory, the conductive layer spacer forms a tip of the floating gate. Conventionally, the exposed floating gate layer is oxidized to form a bird""s beak. This part is anisotropically etched to a tunneling tip of the floating gate. However, in this invention, a spacer is formed on the sidewall of the silicon nitride pattern to form a tunneling tip over the floating gate layer.
According to an aspect of the invention, in a method of forming a split gate type flash memory, a tunneling gate insulating layer and a first conductive layer are formed on a substrate. An auxiliary layer pattern is formed on the first conductive layer. The auxiliary layer pattern includes a linear gap along a first direction, and has an etch selectivity with respect to the first conductive layer. A second conductive layer is conformally stacked and etched back to form a second conductive layer spacer on a sidewall of the auxiliary layer pattern. The second conductive layer spacer is coupled to the first conductive layer. A first insulating material layer is conformally stacked on the second conductive layer spacer. The first insulating material layer has an etch selectivity with respect to the first conductive layer and the auxiliary layer. The first insulating material layer is anisotropically etched back to form a first spacer so that the linear gap is partially filled and the first conductive layer is exposed to the center of the linear gap.
In one embodiment, the first and second conductive layers include polysilicon. The auxiliary layer includes silicon nitride. The first insulating material layer includes CVD oxide.
In the present invention, a trench type device isolation layer is generally formed after stacking the tunneling gate insulating layer and the first conductive layer. In this case, a second conductive layer pattern is formed, and then a surface thereof is oxidized.
Alternatively, the device isolation layer may be formed before formation of the tunneling gate insulating layer. If the first conductive layer is formed after formation of the device isolation layer, the first conductive layer is patterned. In the case where the first conductive layer is patterned, the first conductive layer and the second conductive layer spacer are removed along a second direction across the first direction. Thus, isolation is clearly accomplished between neighboring floating gates.
As described above, a second conductive layer spacer is formed when a first conductive layer is exposed between auxiliary layer patterns. Alternatively, a surface of the first conductive layer for forming a bird""s beak is first oxidized. After removing an oxidized part of the first conductive layer, the second conductive layer spacer is formed to strengthen the tip. Preferably, the surface of the first conductive layer is oxidized after forming the second conductive layer spacer.
Processes following formation of the first spacer may be the same as those in a conventional method of forming a split gate type flash memory. That is, using the first spacer and the auxiliary layer pattern as an etch mask, the first conductive layer is etched to be removed. Using the first spacer and the auxiliary layer pattern as an ion implanting mask, impurities are implanted to form a source region at a central substrate of the linear gap. A conductive layer is stacked and planarized to form a common source line coupled to the source region. After the auxiliary layer pattern is etched and removed, the first conductive layer below the auxiliary layer pattern is anisotropically etched and removed to form a floating gate. The floating gate includes a first conductive layer remaining below the fist spacer and a second conductive layer spacer. A fourth conductive layer pattern, which is contacted with a sidewall of the first spacer exposed by removing the auxiliary layer pattern, is formed to constitute a wordline. As a subsequent process, impurities are implanted into a drain region. In addition, before formation of the drain region, a second spacer may be formed on a sidewall of the wordline. The second spacer is made of a second insulating material such as, for example, silicon nitride.
In order to form the wordline, a fourth conductive layer is conformally stacked. A second auxiliary layer is conformally stacked on the fourth conductive layer. An entire surface of the substrate is planarized to be upper than the fourth conductive layer. The exposed common source line and a surface of the fourth conductive layer are thermally oxidized to form an oxide layer. Using the oxide layer as an etch mask, the second auxiliary layer and the fourth conductive layer are anisotropically etched. The fourth and third conductive layers are made of polysilicon. The second conductive layer includes silicon nitride or silicon oxynitride.


The interlayer dielectric film made of a three-dimensionally polymerized polymer is formed by polymerizing: first cross-linking molecules having three or more sets of functional groups in one molecule providing a three-dimensional structure; and a second cross-linking molecule having two sets of functional groups in one molecule providing a two-dimensional structure. In the three-dimensionally polymerized polymer, dispersed are a number of molecular level pores formed by the polymerization of the first and second cross-linking molecules.

The present invention relates to an interlayer dielectric film that is low in relative dielectric constant and good in mechanical strength, thermal resistance, and adhesion to a substrate, a method for forming such an interlayer dielectric film, and a method for forming an interconnection on such an interlayer dielectric film.
As organic polymer films usable as the interlayer dielectric film of VLSI, known are polymer films formed by polymerizing aromatic molecules, which exhibit good thermal resistance, polymer films made of polyimide derivatives, polymer films made of polyallylether derivatives, polymer films made of polyquinoline derivatives, polymer films made of polyparaxylene derivatives, and the like.
The above organic polymer films, which contain carbon as a main component, are low in polarizability of component molecules and thus low in relative dielectric constant, compared with silicon oxide films that have been conventionally used as the interlayer dielectric film of VLSI. Due to this feature, polymer films have received attention as interlayer dielectric films having a low relative dielectric constant. The relative dielectric constant of an organic polymer film containing carbon as a main component is about 2.4 to about 3.0, which is lower than that of a silicon oxide film that is about 3.3 to about 4.5. As an exception, however, among the silicon oxide films there is known a kind of organic SOG film containing an organic component that has a relative dielectric constant of about 2.9.
In recent years, further reduction in the relative dielectric constant of the interlayer dielectric film has been desired, and for this purpose, porous interlayer dielectric films have been examined.
When an interlayer dielectric film is porous, the relative dielectric constant of the film is low. However, a porous interlayer dielectric film has a new problem that the mechanical strength, the thermal resistance, and the adhesion to a substrate of the interlayer dielectric film are lowered.
The above problem arises due to the structural defect of the conventional porous interlayer dielectric film that it is obtained by reducing the density of cross-linking of an organic polymer. This structural defect will be discussed as follows.
The mechanical strength of an organic polymer film is greater as the density of cross-linking of the film is higher. However, the conventional organic polymer film is made porous by cutting cross-linked sites of the organic polymer, resulting in partially cutting the network of molecules by which the mechanical strength of the organic polymer film is maintained. This inevitably lowers the mechanical strength. The interlayer dielectric film having a reduced mechanical strength causes a problem of destroying an interconnection structure when the interlayer dielectric film is flattened by chemical mechanical polishing (CMP).
The cutting of cross-linked sites of the organic polymer also causes the following problem. An interlayer dielectric film made of such an organic polymer film becomes softened when it is subjected to heat treatment at a later stage. This causes deformation or destruction of a multi-layer interconnection structure.
In addition, the cutting of cross-linked sites of the organic polymer also cuts cross-linked sites between the organic polymer film and a substrate. This results in reducing the adhesion of the interlayer dielectric film to the substrate.
Moreover, in the conventional porous organic polymer film, statistical variation in the size (size distribution) of pores in the film is unavoidable and the dispersion of the pores is not uniform. Accordingly, the resultant interlayer dielectric film is no more uniform in quality, and thus fails to respond to the demand for finer VLSI.
If VLSI is made finer while using the conventional porous organic polymer film, there will inevitably exist pores having a size close to a design rule. Existence of such pores will cause a problem of pattern defect.
Furthermore, a number of pores are formed continuously in the conventional porous organic polymer film. This unavoidably causes a trouble of water, etching gas, a cleaning solution, or the like entering the interlayer dielectric film, thereby deteriorating the quality of the film.

Interlayer dielectric film, and method for forming the same and interconnection

Matsushita ELectrical Industrial Co., Ltd.


The current invention includes methods and apparatuses for processing, that is, altering and imaging, a sample in a high pressure charged particle beam system. Embodiments of the invention include a cell in which the sample is positioned during high pressure charged particle beam processing. The cell reduces the amount of gas required for processing, thereby allowing rapid introduction, exhaustion, and switching between gases and between processing and imaging modes. Maintaining the processes gases within the cell protects the sample chamber and column from contact with the gases. In some embodiments, the temperature of the cell walls and the sample can be controlled.

In a scanning electron microscope ("SEM"), a primary beam of electrons is scanned onto a region of a sample that is to be investigated. The energy released in the impact of the electrons with the sample causes the liberation of other charged particles in the sample. The quantity and energy of these secondary particles provide information on the nature, structure and composition of the sample. The term "secondary electron" as used herein includes backscattered primary electrons, as well as electrons originating from the sample. To detect secondary particles, a SEM is often provided with one or more secondary electron detectors. The term "sample" is traditionally used to indicate any work piece being processed or observed in a charged particle beam system and the term as used herein includes any work piece and is not limited to a sample that is being used as a representative of a larger population.
In a conventional SEM, the sample is maintained in a high vacuum to prevent scattering of the primary electron beam by gas molecules and to permit collection of the secondary electrons. However, wet samples such as biological specimens are not suitable for observation in a high vacuum. Such samples experience evaporation of their fluid content in the vacuum before an accurate image can be obtained, and the evaporated gas interferes with the primary electron beam. Objects that outgas, that is, solids that lose gas at high vacuum, also require special consideration.
Electron microscopes that operate with the sample under a relatively high pressure are described, for example, in U.S. Pat. No. 4,785,182 to Mancuso et al., entitled "Secondary Electron Detector for Use in a Gaseous Atmosphere." Such devices are better known as High Pressure Scanning Electron Microscopes (HPSEM) or Environmental Scanning Electron Microscopes. An example is the Quanta 600 ESEM® high pressure SEM from FEI Company.
In an HPSEM, the sample that is to be investigated is placed in an atmosphere of a gas having a pressure typically between 0.1 Torr (0.13 mbar) and 50 Torr (65 mbar), and more typically between 1 Torr (1.3 mbar) and 10 Torr (13 mbar) whereas in a conventional SEM the sample is located in vacuum of substantially lower pressure, typically less than 10−5 Torr (1.3×10−5 mbar). The advantage of an HPSEM as compared to a conventional SEM is that the HPSEM offers the possibility of forming electron-optical images of moist samples, such as biological samples, and other samples which, under the high vacuum conditions in a conventional SEM, would be difficult to image. An HPSEM provides the possibility of maintaining the sample in its natural state; the sample is not subjected to the disadvantageous requirements of drying, freezing or vacuum coating, which are normally necessary in studies using conventional SEMs. Another advantage of an HPSEM is that the ionized imaging gas facilitates neutralization of electrical charges that tend to build up on insulating samples, such as plastics, ceramics or glasses.
In an HPSEM, secondary electrons are typically detected using a process known as "gas amplification," in which the secondary charged particles are accelerated by an electric field and collide with gas molecules in an imaging gas to create additional charged particles, which in turn collide with other gas molecules to produce still additional charged particles. This cascade continues until a greatly increased number of charged particles are detected as an electrical current at a detector electrode. In some embodiments, each secondary electron from the sample surface generates, for example, more than 20, more than 100, or more than 1,000 additional electrons, depending upon the gas pressure and the electrode configuration.
HPSEM limit the region of high gas pressure to a sample chamber by using a pressure-limiting aperture (PLA) to maintain a high vacuum in the focusing column. Gas molecules scatter the primary electron beam, and so the pressure limiting aperture is positioned to minimize the distance that the electron beam travels in the high pressure region to reduce interference with the primary beam, while providing a sufficient travel distance for adequate gas amplification of the secondary electron signal.
An HPSEM as described in U.S. Pat. No. 4,785,182 comprises a vacuum envelope having a pressure limiting aperture, an electron beam source located within the vacuum envelope and capable of emitting electrons, focusing lens located within the vacuum envelope and capable of directing an electron beam emitted by the electron beam source through the pressure limiting aperture, beam deflectors located within the vacuum envelope and capable of scanning the electron beam, and a sample chamber including a sample platform disposed outside the high vacuum envelope and capable of maintaining a sample enveloped in a gas at a desired pressure.
While an HPSEM can observe moist biological sample, problems still exist with such observations. For example, when hydrated materials are observed at room or body temperature, water tends to condense on all surfaces within the sample chamber. Such condensation can interfere with the operation of HPSEM, as well as cause corrosion and contamination.
Charged particle beams, such as electron beams or ion beams, can also be used to induce a chemical reaction to etch a sample or to deposit material onto a sample. Such processes are described, for example, in U.S. Pat. No. 6,753,538 to Mucil et al. for "Electron Beam Processing." The process of a charged particle beam interacting with a process gas in the presence of a substrate to produce a chemical reaction is referred to as "beam chemistry." The term "processing" as used herein includes both processing that alters the sample surface, such as etching and deposition, as well as imaging. The term "processing gas" is used to include a gas that is used for imaging or a gas that is used together with the charged particle beam to alter the sample. The term "imaging gas" is used to include a gas that is used for imaging. The classes of gasses are not mutually exclusive, and some gases may be used for both altering the sample and for forming an image. For example, water vapor can be used to etch a sample that includes carbon and can be used to form an image of samples that include other materials.
Conventional HPSEMs are not well adapted for efficient beam chemistry. One problem with using a HPSEM system for beam chemistry is the considerable time required to introduce and evacuate gases from the sample chamber. The sample chamber in a conventional HPSEM includes a gas inlet through which a gas is introduced through a leak valve. The gas then migrates throughout the sample chamber. Some of the gas molecules escape through the PLA into the column, where they are removed by a vacuum pump that maintains the column at a low pressure. The inlet leak valve is adjusted so that a desired equilibrium pressure is achieved, with the gas escaping through the PLA into the column just matching the gas introduced through the leak valve. The HPSEM typically begins processing a sample only after equilibrium is achieved. It takes a considerable amount of time for the gas to reach an equilibrium pressure, particularly if the vapor pressure of the beam chemistry precursor is similar to the desired operating pressure of the sample chamber. For a large sample chamber volume of 30 liters, such as that used in a typical dual-beam system, it can take up to 30 minutes for the partial pressure of the process gas to reach equilibrium.
This problem is compounded when a process entails injecting multiple process gases into the sample chamber. Typically, there is a pressure gauge downstream of the needle valve on the chamber side. The pressure gauge measures the total pressure in the sample chamber and is incapable of separately measuring the partial pressures of multiple process gases in a mixture. Thus, it is difficult to know when the desired partial pressure of each of the gases has been achieved.
When performing beam chemistry processing in a conventional SEM, FIB, or dual beam system, the system operator will typically obtain a charged particle beam image of the sample to navigate to an area that is to be processed by etching or depositing material. After performing the beam processing operation, the operator will typically obtain another charged particle beam image of the sample to evaluate the results of the process. Because different gases are typically used to process and image in an HPSEM, the sequence of image, process, and image would require multiple changes of the gas in the chamber. If some process gas remains in the chamber during imaging, the sample may be unintentionally modified by the beam during the imaging operation. Because of the considerable time required to fully evacuate one gas and then to reach equilibrium pressure with another gas, such multiple step operations are not practical in an HPSEM. The time is further increased in some cases because the molecules of some gases used in beam chemistry tend to have very long adsorption times on the vacuum chamber walls, and take longer to fully evaporate.
GB2186737 to Shah describes a specimen chamber for use in a scanning electron beam instrument. A sample sits atop a specimen support including a moisture absorbing pad. An inlet duct connected to a source of ambient gas brings moisture from the pad into the chamber to keep the sample from drying out. An electrode positioned close to the sample allows charged carriers of either sign to be removed from the chamber to improve contrast of an image derived from current detected at the specimen support.
Another reason why HPSEMs are not generally used for beam chemistry is that corrosive process gases can degrade the HPSEM components. For example, certain process gases associated with beam chemistry can react spontaneously with plastic tubing and are very dangerous to human health. A gas like XeF2 can make plastic gas tubing brittle and eventually cause leaks of dangerous gases into the surrounding environment.

High pressure charged particle beam system


A saddle tree for a horse saddle has an arched body portion shaped to fit across a horse's back,. a pair of laterally-spaced fork members which project downwardly from opposite sides of the arched body portion so as to extend downwardly on opposite sides of a horse's body when in use, and a pair of laterally-spaced independently resiliently deflectable spring members projecting rearwardly from the arched body portion. The spring members are of blade-like shape curved to conform with the shape of a horse's back and have a length sufficient to extend along at least eight vertebrae when in use and a lateral spacing causing at least laterally-inner rear-edge portions thereof to rest on the relevant vertebrae when in use.

Saddle trees have been used in horse saddles for very many years and many different designs have been proposed, it being necessary to consider the anatomy of the horse, the anatomy of the rider and the balance of the saddle and the rider on the horse's body. Typical saddle trees are shown, for example, in U.S. Pat. No. 4,965,988 (Anderson), PCT Application No. PCT/GB97/02192 (Huggins), and PCT Application No. PCT/US97/20013 (Coffin). However, known saddle trees do not satisfactorily meet all of the above-mentioned desired criteria with respect to the rider.
It is therefore an object of the present invention to provide an improved saddle tree which enables a saddle incorporating the tree to more clearly meet such desired criteria.


A plant for building tires includes a plurality of working locations, at least one first working location being associated with at least two loading/unloading locations, a proximal one and a distal one, each of said working locations and loading/unloading locations being associable with a forming drum. The production cycle is controlled by the method of: (i) loading a first forming drum into the at least one first working location; (ii) loading a second forming drum into the loading/unloading location; (iii) at the end of the working provided in the at least one first working location, unloading the first forming drum into the proximal loading/unloading location.

1. Field of the Invention
The present invention relates to a process and a plant for building tyres. In greater detail, the invention concerns a method, a process and the equipment used for building the green tyre, to be subsequently submitted to a curing cycle for obtaining the final product.
2. Description of the Related Art
A tyre for vehicle wheels generally comprises a carcass structure including at least one carcass ply having respectively opposite end flaps in engagement with respective annular anchoring structures, integrated into the regions usually identified with the name of "beads", and having an inner diameter substantially corresponding to a so-called "fitting diameter" of the tyre on a respective rim.
Associated with the carcass structure is a belt structure comprising one or more belt layers, disposed in radial superposed relationship relative to each other and to the carcass ply, and having textile or metallic reinforcing cords with a crossed orientation and/or substantially parallel to the circumferential extension direction of the tyre. At a position radially external to the belt structure, a tread band is applied which is of elastomeric material too, like other semifinished products constituting the tyre.
In addition, respective sidewalls of elastomeric material are applied at an axially external position to the side surfaces of the carcass structure, each extending from one of the side edges of the tread band until close to the respective annular anchoring structure to the beads. In tyres of the "tubeless" type, an airtight coating layer, usually named "liner" covers the inner surfaces of the tyre.
After building of the green tyre, carried out through assembly of respective components, a curing and molding treatment is generally carried out which aims at determining the structural stabilisation of the tyre by cross-linking of the elastomeric compounds, and impressing a desired tread pattern on the tyre as well as possible distinctive graphic marks at the tyre sidewalls.
EP 1 312 462 discloses a building system wherein along a production line there is a ply-feeding station, a carcass-building station, an assembling station and a belt-building station equipped with respective drums. Transport members movable along the production line carry out transfer of the workpieces from a work station to another, removing the workpiece from a drum for placing it on the drum of the following station.
EP 1 481 791 discloses a tyre production system comprising a plurality of carcass-building stations distributed to a given mutual distance for forming the carcass structures on respective carcass-building drums sequentially transferred along a carcass-building line. Along a belt-producing line the belt structures provided with tread band are formed on respective belt-building drums sequentially moved between belt-building stations to a predetermined distance from each other. The carcasses and belts are mutually assembled within a curing mold.
WO 2009/040594, in the name of the same Applicant, discloses a plant and a process for producing tyres, comprising the following steps: a) forming a carcass structure of a green tyre on a first building drum in at least one carcass-building line; b) forming a crown structure on an auxiliary drum in at least one crown structure-building line; c) shaping the carcass structure into a toroidal configuration for coupling it to the crown structure in at least one assembling and shaping station of the tyre being processed. Operation of the assembling and shaping station is synchronised with that of the carcass-building line and the crown structure-building line. Each carcass structure is maintained in engagement on the respective building drum at least until completion of the shaping step. The built tyre is cured and molded in a curing and molding line separated from the assembling and shaping station.