A method and apparatus for scheduling threads on a multiprocessor utilize an unlocked local queue for each processor in the multiprocessor and a lockable global dispatch queue accessible by all processors. Threads are selected for movement from the unlocked local queue to the global dispatch queue only when the unlocked local queue contains too many threads that are waiting for a processor. Threads are selected to run on an available processor only after repeated checks to make certain no threads in the processor""s unlocked local queue should be run first. As a result, threads assigned to a processor tend to stay with that processor unless the system load is severely unbalanced, thereby improving system performance by increasing cache hits and decreasing lock assertions.

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. The copyright owner does not hereby waive any of its rights to have this patent document maintained in secrecy, including without limitation its rights pursuant to 37 C.F.R. xc2xa7 1.14.
The present invention relates to the allocation and scheduling of processors in a multiprocessing computer system, and more particularly to a thread-scheduling invention which creates a strong affinity between each thread and the processor which is initially allocated to the thread.
Many computing systems contain a single central processing unit (xe2x80x9cCPUxe2x80x9d or xe2x80x9cprocessorxe2x80x9d), a primary storage unit directly accessible to the processor, and a secondary storage unit for long-term bulk storage of information. The primary storage typically includes random access memory (xe2x80x9cRAMxe2x80x9d) and the secondary storage typically includes a magnetid disk, optical disk, or similar-device.
To create more powerful computing systems, these individual architectural componentsxe2x80x94processors, memories, and disksxe2x80x94have been and are being combined and connected in various ways. A major goal of these alternative architectures is to support parallel processing, that is, processing performed by several processors which are working on different pieces of a given problem at the same time. A parallel processing system is said to be xe2x80x9cscalablexe2x80x9d if adding additional processors clearly improves the system""s performance.
Some parallel processing architectures are generally termed xe2x80x9cmultiprocessorsxe2x80x9d or xe2x80x9cmultiprocessing systems.xe2x80x9d Multiprocessors contain at least two processors which communicate with one another through a xe2x80x9cshared memory.xe2x80x9d Shared memory makes a single virtual address space available to multiple processors, allowing each processor to read and write values at address locations that are accessible to all processors and addressed identically by each processor. Each processor in a multiprocessing system may also have a local private memory, known as its xe2x80x9ccache,xe2x80x9d which is not shared with the other processors.
Multiprocessors may be connected to each other and/or to single processor systems in a local area network, wide area network, on the Internet, or by other means. Processors which communicate with each other but do not have a common shared memory form a xe2x80x9cmulticomputing system.xe2x80x9d Thus, a local area network is one of many possible types of multicomputing systems. Multiprocessing systems and multicomputing systems are known collectively as xe2x80x9cdistributed systems.xe2x80x9d
Multiprocessors may be xe2x80x9cbus-basedxe2x80x9d or xe2x80x9cswitched.xe2x80x9d One bus-based multiprocessor is illustrated in FIG. 1. The multiprocessor, which is indicated generally at 10, includes four processors 12, each of which has its own cache 14. The caches communicate through signal lines 15 using MESI or another familiar protocol. The processors 12 communicate with one another through a shared memory unit 16 which is on a common bus. 17 with the processors 12. The shared memory unit 16 typically includes a memory bus controller and RAM.
The bus 17 also provides communication between the processors 12 and/or shared memory 16, on the one hand, and a drive 18 capable of reading a medium 19, on the other hand. Typical drives 18 include floppy drives, tape drives, and optical drives. Typical media 19 include magnetic and optical computer-readable media.
To read the value of a word from the memory 16, a particular processor such as CPU 1 puts the memory address of the desired word onto the bus 17 and signals that a read is desired. In response, the memory 16 places the value of the addressed word onto the bus 17, thereby allowing the processor CPU 1 to read the value. Writes to the shared memory 16 are performed in a similar way.
Unfortunately, if shared memory 16 reads and writes are performed only by using this simple approach, then performance of the multiprocessor 10 drops dramatically as additional processors 12 are added. When too many processors 12 are present, the bus 17 cannot transfer information between the processors 12 and the shared memory 16 as rapidly as requested by the processors 12. System performance then drops because some of the system""s processors 12 are idle while they wait for access to the shared memory 16.
To reduce the load on the bus 17, copies of the values read or written by a given processor such as CPU 1 may be kept in that processor""s cache 14. Each value is stored in the cache 14 with some indication of the address at which that value is kept in the shared memory 16. Addresses corresponding to values stored in the cache 14 are called xe2x80x9ccached addresses,xe2x80x9d while the values stored in the cache 14 are called xe2x80x9ccached values.xe2x80x9d If the address specified in a read request is a cached address, the corresponding cached value is read from the cache 14 and no request is placed on the bus 17.
Although caching may dramatically reduce the load on the bus 17, it also introduces potential inconsistencies. Imagine that processors CPU 1 and CPU 2 each read the word at address A0 from the shared memory 16 and that the value read is zero. Then the cache of CPU 1 and the cache of CPU 2 will each indicate that the value stored at address A0 is zero. Suppose CPU 1 then writes the value one to address A0 of the shared memory 16. Then the cache of CPU 1 and the shared memory 16 will each indicate that the value stored at address A0 is one, while the cache of CPU 2 will still indicate that the value stored at A0 is zero.
Using one or both of two approaches, known as xe2x80x9cwrite-through cachesxe2x80x9d and xe2x80x9csnooping caches,xe2x80x9d will prevent such inconsistencies on bus-based multiprocessing systems unless the number of processors is too large. If the number of processors grows too large, alternative architectures may be used. One alternative multiprocessing architecture, known as a xe2x80x9ccrossbar switch,xe2x80x9d is indicated generally at 20 in FIG. 2. A shared memory is divided into modules 22 which are connectable to processors 24 by signal lines 26. The signal lines 26 may be connected as needed by actuating appropriate crosspoint switches 28.
Another alternative multiprocessing architecture, known as an xe2x80x9comega switching network,xe2x80x9d is indicated generally at 30 in FIG. 3. Shared memory is again divided into modules 32 which are connectable to processors 34 by signal lines 36. The signal lines 36 may be connected as needed by actuating appropriate 2xc3x972 switches 38. In either the crossbar switch multiprocessor 20 (FIG. 2) or the omega multiprocessor 30 (FIG. 3), some or all of the processors 24, 34 may have a cache similar to the caches 14 in the bus-based multiprocessor 10 (FIG. 1). The multiprocessors 20, 30 may also include a drive such as the drive 18 (FIG. 1) for reading computer-readable media such as the medium 19.
Although its underlying hardware limits the theoretical performance of a multiprocessor, in practice limitations imposed by an xe2x80x9coperating systemxe2x80x9d are more frequently encountered. The operating system is software which (among other duties) controls access to the processors. The presence of multiple processors that are capable in theory of working in parallel on a given computational problem does not, in and of itself, make parallel processing a practical reality. The problem must be broken into appropriate parts, the parts must then be efficiently distributed among the processors, and the results of the separate computations must finally be combined to provide a solution to the problem.
Computational problems may be divided into xe2x80x9ctasks,xe2x80x9d each of which in turn contains one or more xe2x80x9cthreads.xe2x80x9d Each task has its own address space; the address spaces of separate tasks are typically disjoint. Tasks often have other components as well, such as global variables, associated files, communication ports, semaphores, and accounting information. Each thread has some executable code and a set of register values. The register values include a program counter value that indicates which point the thread has reached in its progress through the executable code. Threads may also have associated state information such as a function call stack.
A variety of approaches have been tried for allocating processors to tasks and threads. When the processing requirements of a problem are precisely known before computation to solve the problem is performed, deterministic approaches such as certain graph-theoretic algorithms can be used to efficiently allocate processors to threads or tasks which will collectively solve the problem. However, in most cases the information needed by deterministic approaches is not available until after the computations have finished.
Because deterministic approaches are rarely practical, a variety of non-deterministic xe2x80x9cheuristicxe2x80x9d approaches are used to allocate processors to threads and/or tasks. One centralized approach tries to allocate processors fairly among all waiting users. Under this approach, a user who is not currently using any processors but has been waiting a long time for a processor will always be given the next available processor. The usage information needed to allocate processors fairly is maintained in one central location. To increase the fairness of processor allocation, this approach sometimes stops a thread or task before it has finished using a given processor, saves appropriate state information, and then gives that processor to a different thread or task.
Under many allocation schemes, a given processor may be allocated to a group of threads rather than being dedicated to an individual thread. In such cases, steps must be taken to schedule the use of that processor by the individual threads in the group, since only one thread can run at a time on any particular processor. Deterministic scheduling approaches exist which theoretically optimize efficiency, but which are not practical because they require more information than is typically available.
One heuristic approach to processor scheduling in a multiprocessor system is embodied in the Mach operating system presently under development at Carnegie-Mellon University and elsewhere. Each processor is assigned to exactly one xe2x80x9cprocessor set.xe2x80x9d Processor sets are then allocated to threads. Each processor set therefore has a set of threads to execute, and steps must be taken to schedule use of the processors by the threads. Goals of Mach scheduling include assigning processor cycles to threads in a fair and efficient way while nonetheless recognizing different thread priorities.
Each thread has a priority level ranging from 0 (highest priority) to 31 (lowest priority). Each processor set has an associated array of global run queues. FIG. 4 illustrates an array 40 of global run queues 42 for a processor set P1. Each run queue 42 contains zero or more threads 44 waiting to use a processor in the processor set. Mach defines similar arrays for each of the other processor sets.
Each global run queue 42 corresponds to a different priority level. When a thread at a given priority is ready to run, it is placed at the end of the corresponding run queue. Threads which are not ready to run are not present on any of the run queues 42. In the example shown, a priority-three run queue 46 contains two priority-three threads 48 that are ready to run, and a priority-eight run queue 50 contains two priority-eight threads 52 which are ready to run. Two other run queues 42 also contain at least one thread 44; the remaining run queues 42 are presently empty.
Each Mach array 40 has three associated variables: an array mutex, a thread count, and a hint. The array mutex (derived from xe2x80x9cmutual exclusionxe2x80x9d) is used to lock the array 40 so that only one processor can access the run queues 42 at a time. The thread count holds the total number of threads 44 currently in the run queues 42 of the array 40. The hint holds a priority level indicating where a Mach scheduler should start looking for the highest priority thread. The highest priority thread will be located either in the run queue for the hint priority level or in a lower priority run queue.
The global run queues 42 may be used by each of the one or more processors in the processor set. In addition, each individual processor Pn has its own local run queues. The local run queues are similarly arranged in priority levels from zero through thirty-one. Each local run queue for processor Pn holds xe2x80x9cboundxe2x80x9d threads, namely, threads that are permanently bound to processor Pn. Typical bound threads include device drivers for I/O devices that are physically accessible only to processor Pn. Bound threads are never placed in one of the global run queues 42.
Mach utilizes the run queues 42 and other structures to perform processor scheduling as follows. Each thread 44 is allocated a maximum quantum of time during which it can have continual use of a processor. When a thread 44 blocks or exits voluntarily, or is preempted because it has run continually for one quantum, the scheduler searches certain run queues to locate the next thread 44 that will be given the processor. If a thread 44 is found at any time during this search, the processor is allocated to that thread 44 and the search ends.
The Mach scheduler looks first in the processor""s local run queues. If any threads 44 are found, the first thread 44 in the highest priority local run queue is given the processor. The check for threads 44 in the local run queues begins by checking to see whether the local thread count is zero. If it is, the local run queues are all empty. Otherwise, the scheduler uses the local hint value to find the first thread 44 in whichever non-empty local run queue has the highest priority.
If all of the local run queues are empty, then the same steps are repeated to search the global run queues 42 for the processor set that contains the processor. If there are no threads 44 in either the local run queues or the global run queues, and if a non-scheduler thread was not preempted to perform the search, then the scheduler repeats the search, possibly after waiting for some predefined period of time. If a ready-to-run thread 44 is located, that thread 44 is allowed to run for at most one time quantum. Then it is stopped and the whole search process is repeated.
Mach regularly decreases the priority of the currently running thread 44. Thus, the longer a thread 44 runs, the less successful it is likely to be when competing with other threads 44 for a processor. However, some threads 44 have a limited ability to temporarily increase their own priority, after which their original (lower) priority is restored. A thread 44 may also name another thread 44 as its successor. If a successor thread 44 is named, the local and global run queues are not searched. Instead, the processor is simply given to the successor for at most one quantum of time.
Mach""s approach to scheduling has two major drawbacks. First, Mach continually preempts threads which are doing useful work, sets them to one side, and then spends valuable processor time performing the searches just described. From a user""s perspective, the time spent searching is undesirable administrative overhead that decreases the overall performance of the multicomputing system.
The processor made to do the search is prevented from working on the user""s problem during the search. Moreover, the scheduler must lock the global run queues 42 while the search is performed. If other processors in the same processor set try to access the locked global run queues 42, they must wait until the first processor finishes. Thus, the search may reduce the efficiency of several processors even though it seeks a thread to run on just one processor.
The second drawback to Mach""s approach is even more destructive of multiprocessor efficiency. Under Mach, threads 44 tend to migrate from one processor to another processor over time. Bound threads (those in local run queues) only run on a particular processor, but load-balancing concerns traditionally limit such bound threads 44 to device drivers and other threads 44 that simply will not run on other processors. Most threads 44 are not bound, but are allowed to run on any available processor in the processor set.
Unfortunately, moving threads 44 between processors may severely degrade system performance because it undercuts the performance gains that would otherwise arise from processor cache usage. With reference to FIGS. 1 and 4, those of skill in the art will appreciate that running a thread 44 on a given processor 12 tends to fill that processor""s cache 14 with the data needed by the thread 44. Over time, the thread 44 therefore tends to receive data from the cache 14 rather than the shared memory 16. As discussed, the cache 14 thereby improves performance of the system 10 by reducing the load on the bus 17. Similar performance gains arise when local processor caches are used in other multicomputing systems, including the systems 20 and 30 shown in FIGS. 2 and 3, respectively.
Moving a thread 44 to a new processor forces the thread 44 to reacquire needed data from the shared memory 16, 22, 32. The data must be reloaded into the processor""s cache before the benefits of caching become available again. Indeed, the processor not only acts as though it had no cache during this reloading process, but actually performs worse than similar cache-less processors because of the need to reload the cache.
Thus, it would be an advancement in the art to provide a method and apparatus for thread scheduling which reduces the movement of threads between processors in a multiprocessor.
It would also be an advancement to provide such a method and apparatus which reduces the time during which processors in a multiprocessor are unable to work because thread scheduling is underway.
Such a method and apparatus for multiprocessor scheduling are disclosed and claimed herein.
The present invention provides a method and apparatus for scheduling the execution of a plurality of threads on a plurality of processors in a multiprocessor computer system. One method of the present invention includes associating an unlocked local queue of threads with each of the processors and maintaining a global dispatch queue of threads which are not presently associated with any processor. The unlocked local queue is accessed only by the processor in question and therefore requires no corresponding mutex or other semaphore to maintain its data integrity. Thus, the number of locks asserted by the multiprocessor""s operating system under the present invention is significantly less than under different approaches, and provides the multiprocessor with a corresponding performance increase.
The method of the present invention also includes selecting movable threads from the unlocked local queues according to predetermined criteria which tend to restrict the mobility of threads. A thread is moved from its unlocked local queue to the global dispatch queue only if different processors are facing very disparate loads. This creates a strong affinity between processors and threads, which in turn provides the multiprocessor with a performance boost by increasing processor cache usage and decreasing shared memory accesses.
In one embodiment of the present invention, the global dispatch queue is a lockable queue to prevent it from being changed by more than one thread at a time. Moving a selected thread is accomplished by locking the global dispatch queue, by then deleting the selected thread from its unlocked local queue and inserting it in the global dispatch queue, and finally unlocking the global dispatch queue. Locking and unlocking involve obtaining and releasing, respectively, a mutex variable that is associated with the global dispatch queue.
The selection of movable threads includes identifying a busiest processor among the plurality of processors. Movable threads are selected only from eligible-to-run threads in the unlocked local queue of the busiest processor. One embodiment identifies the busiest processor as that processor which has received the smallest number of sleep requests of any of the processors during a sampling period. Another embodiment identifies the busiest xe2x80x9cpopularxe2x80x9d processor among the plurality of processors. A processor is xe2x80x9cpopularxe2x80x9d when its unlocked local queue contains at least two threads which are eligible to run. The movable threads are then selected only from the eligible threads in the unlocked local queue of the busiest popular processor.
Selection of a thread to which control of an available processor will be yielded is accomplished by searching for a suitable thread until one is found and then switching the processor""s context to the new thread. One method of the present invention searches, in a predetermined order, at least a portion of the union of the global dispatch queue and the unlocked local queue of the processor to locate at least one eligible thread. Control of the processor is given to an eligible thread found during the search. One embodiment requires that control be yielded to at least one thread that was not found in the global dispatch queue between each pair of instances in which control is yielded to threads found in the global dispatch queue.
According to the present invention, one approach to searching includes checking the global dispatch queue for an eligible thread. If no eligible thread is found in the global dispatch queue, the searching step checks the unlocked local queue of the processor.
A second approach to searching may be used in embodiments of the present invention which associate a lockable local queue of threads with each of the processors. The lockable local queue is used rather than the unlocked local queue when other processors need to bind a thread, such as a device driver, to the given processor. The unlocked local queues are still present; use of the lockable local queues is typically rare. This alternative approach to searching includes checking the lockable local queue of the processor for an eligible thread, checking the global dispatch queue if no eligible thread is found in the lockable local queue, and then checking the unlocked local queue if no eligible thread is found in the global dispatch queue.
Under either approach, searching may also include determining whether checking the global dispatch queue will exceed a predetermined relative frequency for global dispatch queue accesses. The global dispatch queue is checked only if checking will not exceed the predetermined relative frequency for global dispatch queue accesses and, under the second approach, if no eligible thread is found in the lockable local queue.

Method and apparatus for strong affinity multiprocessor scheduling


Processes for reducing fraud risk in credit transactions, particularly those involving airline ticket purchases, include collecting the following additional transaction variables and their use in real-time authorization decisions: credit card holder name, reservation code, passenger name, origin city, destination city, travel date, routing description, class of service, e-ticket indicator, number of passengers traveling and carrier code. The additional transaction variables received during a transaction involving the purchase of airline tickets are passed, in addition to the transaction variables traditionally included in a real-time authorizations request, to a fraud risk evaluation model maintained by a financial institution or other entity responsible for authorizing a payment for the transaction. The fraud-risk models use historical behavior and optimal risk decision-making factors to authorize or reject the transaction in real time, without slowing standard authorization processing times.

Fraudulent airline ticket purchases have occurred on all types of credit and charge card products and other payment vehicles since they were introduced in the industry as a form of payment. Unscrupulous individuals frequently utilize charge or credit cards belonging to other parties to make unauthorized purchases of airline tickets and services. These individuals cause substantial harm to merchants (such as airlines, travel agencies and online travel web sites) in the form of increased costs, because merchants are generally "charged back" for the cost of the ticket by the card issuer. Merchants are also harmed through loss of revenue since controls introduced to eliminate fraudulent transactions also cause some legitimate transactions to be refused. In addition, fraud generates additional operations costs related to processing charge backs and generates security risks by having these individuals utilizing airline services. Affected card members and other types of account holders are harmed since they must deal with the discomfort of realizing their cards or financial accounts were compromised, and must have their affected cards reissued. Financial institutions are harmed by the behavior of these individuals due in part to costs of processing charge backs, and also since they may be ultimately responsible for any fraudulent charges where proper merchant card acceptance procedures were followed. The occurrence of fraud on airline transactions also has negative impacts on the brand reputations of both the card and airline industries.
In order to combat this type of fraud, credit and charge card companies (collectively, card issuers) and other types of financial institutions (such as banks providing debit cards to account holders) have performed risk screening for all financial transactions in two general manners: (1) "real-time authorization" in which an authorization request is sent real time to the card issuer and only the specific behaviors of the card member and the merchant involved in a transaction are examined; and (2) "offline authorization" in which risky patterns are identified in a transaction after its completion, and an affected card member or account holder is contacted to verify a purchase. However, these measurements, while reducing the incidence of fraudulent transactions, leave in place a substantial residual level of fraud in the industry.
Currently, the transaction data provided by merchants to financial institutions for real-time authorization include only the purchase amount, vendor identification, credit card account number, credit card expiration date, and transaction date. Due to this limited data, a financial institution has limited modeling capabilities to protect themselves and airline vendors from fraudulent activity. Additional data is provided in the subsequent submission to the issuer however the delay between authorization and submission limits the ability of financial institutions to use this additional data to make optimized risk decisions in any given transaction.
Accordingly, there is a need for introducing fraud control measures in financial transaction processes that address the above-described problems with respect to timeliness of data availability and the shortcomings in existing and related technologies.

System and method using enhanced authorization data to reduce travel-related transaction fraud

American Express Travel Related Services Company, Inc.


The invention relates to a method for the production of images with high resolution jacquard fabric comprising the following steps: colour scanning of an output image to be reproduced on a fabric, video visualisation of said image with the largest number of colours possible with the means employed for said visualisation. The invention is characterised in that the method comprises further steps: selection of a number of base colours to be used for forming said image on said fabric, said number of base colours is related to the number of warp and weft threads which may be used in the loom and which are to be applied in the weaving of said fabric, reducing the original colours of the output image to a number of reduced colours which it is possible to produce by mixing the base colours of the warp and weft threads.

EP 0 692 562 describes a method for the optical illustration of a fabric consisting of warp and weft threads with a pattern. In this method, the patterns are recorded by a data processing system and displayed on a video screen, the patterns being scanned in from an original. Thereafter, by means of CAD, the warp and weft threads forming the fabric are assigned an intersection diagram, the weaves of which the fabric is to consist being defined. These are known regular weaves, such as linen weaves, satin weaves, twill weaves and basket weaves. Subsequently, the run of the warp and weft threads is determined, the thread-specific parameters and fabric parameters being taken into account. In light of the dynamic behavior and run of warp and weft, the predetermined run of the warp and weft threads is corrected. This corrected warp/weft thread run is illustrated by means of an output unit, for example by means of a video screen or printer. After the correction, various colors are assigned to the individual warp and weft threads.
It is considered a disadvantage that the colors are selected as a function of the colors capable of being illustrated in the output unit, for which purpose a person skilled in the art with experience of weaves is necessary. The output unit is a video screen or a printer which operate on the basis of the ground colors (RGB) and with additive color mixing. It is known, however, that an exact reproduction of an illustration cannot be achieved in the fabric in the ground colors by means of textile weft threads. Since the colors capable of being illustrated by the output unit also contain mixed colors, threads with such mixed colors have to be provided.
DE 44 38 535 discloses a method for the jacquard weaving of a colored cloth. In this method, an image copy to be woven is broken down by means of the screen method known from printing technology. In this method, an original is transferred into a computer by scanning and is displayed on the video screen, a very large number of color shades being present. Subsequently, the colors are reduced to an illustratable or a desired number of colors. Finally, this number of colors is broken down into screen dots having the colors red, yellow and blue and also black and white, the screen dot having the size of a weavable point. After the color breakdown, the weaving program is set up by means of computer technology, each screen dot corresponding to a weaving point. These weaving points are tied off according to the classic jacquard method, that is to say regular weaves with repeat repetitions are used.
The known method has substantial disadvantages. To carry out the method, it is absolutely necessary to have an experienced person skilled in the art with experience of weaves. To be precise, it has become clear that, in the case of woven colored image copies in the colors yellow, red and blue, the color mix is deficient, that is to say they do not have all the color shades of the original. As a rule, corrections are necessary in order to improve the woven image copy. However, corrections of this kind can be carried out only by an experienced person skilled in the art with experience of weaves. In the color breakdown for reprography, it is to be assumed that a color mix occurs in the region between the print colors during the printing operation. In other words, the printed color dots are not clearly delimited, but, instead, the print colors of the adjacent color dots flow partially one into the other in the edge region. In the known method, the illustration is broken down into screen dots which form a weaving point with clear delimitation. The mixing effects are to be generated as a result of the low resolution of the human eye.
It is therefore known that the introduction of jacquard weaving machines has made it possible to produce differently worked patterns, but the production times for more complex patterns are very long and the work to be carried out is extremely complicated. The introduction of the CAD systems in the area of jacquard weaving has led to a considerable simplification of the necessary work and at the same time has reduced the possibility of error during the planning and production of different thread interlacings for the purpose of obtaining various effects. The CAD systems nevertheless also force the workers to carry out special additional work on the images in order then to produce on the final fabric a structure which is as similar as possible to the initial image to be reproduced on the fabric.
In actual fact, the work for preparing the images and their respective treatment, quite apart from the weaving system which is used later, take place as set out below:
First, a color scanning of any desired initial image is carried out (the initial image may be of any desired type, without any restriction); scanning may take place with the aid of a scanner or by means of any other reading system.
The initial image read in this way is visualized by video by means of an appreciable number of colors. Said number of colors is closely related to the performance of the hardware system used and consequently to the configuration of the latter.
In professional configurations, an image with millions of image colors can be read and visualized by video. In actual fact, this is primarily a theoretical performance, since the possibility of visualization of this kind is very rare: normally, images coming from the scanner have thousands of image colors which are selected automatically, during the reading operation, from a spectrum consisting of millions of colors. It is necessary, however, to ensure that each image read by the scanner contains a specific color palette or, put better, a color palette which contains the colors of the image itself in a specific way.
At this point, said image undergoes a first operation for reducing the number of existing image colors, that is to say the initial colors of the initial image. The processes of color reduction may be carried out by means of different methods, such as by the use of special mathematic algorithms which, to be precise, vary on the basis of the way in which the colors are eliminated and/or are replaced by other colors within the image.
In any event, quite apart from the nature of the reduction used and, consequently, of the mathematic algorithm used, the initial image having a large number of initial colors is brought, for example, to 256 reduced colors. This is a step which takes place by virtue of the fact that the images which are subsequently processed by CAD for jacquard textiles do not require a large number of colors, and, as a rule, it is assumed that 256 colors are sufficient for the final objective and for the treatment of the image itself, specifically on the basis of the respective conversion to a pattern for jacquard textiles.
The image treated in this way (reduced in terms of the number of colors), is subsequently transferred into the jacquard CAD system in which all the operations are coordinated which make it possible to convert the image itself into a pattern for jacquard textiles. One of the first steps in this respect is a further reduction of the remaining, already reduced colors. In fact, the number of existing colors is reduced in the image on the basis of the type of fabric and on the basis of the effects to be achieved. Normally, in a fabric pattern, each individual color illustrates a specific type of interlacing and, consequently, a specific type of final effect on the fabric.
At this point, the following steps are linked to the additional work on the available image. On the other hand, the image then available has passed through a considerable series of steps in terms of the reduction, as regards the number of colors and consequently also as regards the information obtained from the image, and, consequently, as soon as the number of selected colors is reached, an image is available which necessarily has to undergo the additional work, so that it is as far as possible similar to the initial image.
The time necessary for the "additional work" on the images is in close interrelationship with the complexity of the pattern. This clearly and markedly implies that, even today, despite the use of highly developed systems, the complex patterns require long times for the complete and final additional work. At the present time, therefore, there is no mathematic algorithm available which makes it possible to convert automatically an image which is read by a scanner (and which is consequently rich in information in terms of the number of existing colors and the nuances, etc.) and at the same time to achieve the exact reproduction of the initial image, without the additional work having to be carried out.
In practice, the different steps described above, which are performed with the purpose of reducing the number of colors present in the read initial image, do not make it possible to maintain, unchanged, the nuances, color shades and different color variations which the image initially has. All this takes place to the disadvantage of the image processing times, but also to the disadvantage of the quality of the final fabric; by "quality" is meant in this case the difference existing between the initial image at the time of reading and the converted image reproduced on the jacquard fabric.
Of course, the number of colors which the image to be reproduced on the jacquard fabric possesses at most may be limited, specifically also by the maximum number of colors of the weft thread which are capable of being used in the weaving machine. Normally, what can be achieved, at least at the present time, in textile weaving machines is that these use up to a maximum of 12 weft thread colors, and therefore the number of reproducible colors is necessarily limited.

Method and unit for the production of images with high resolution in jacquard fabric

Brevitex Etablissement pour l'Exploitation de Brevets Textiles


A fuse circuit (11) having a plurality of terminals (22, 23) provided on a common joint plate (21) and a fuse circuit (11xe2x80x2) having a plurality of terminals (22xe2x80x2, 23xe2x80x2) provided on a common joint plate (21xe2x80x2) are incorporated into a housing (12), thereby constituting a fuse link assembly (10). The plurality of fuse circuits (11, 11xe2x80x2) are provided with circuit connection portions (27, 27xe2x80x2) which share a power input portion. The fuse circuits (11, 11xe2x80x2) are incorporated into the housing (12) in parallel. As a result, the number of circuits is increased, by means of only enlargement of widthwise direction Y which is easy to increase while enlargement of longitudinal direction X stemming from packaging of circuits is minimized.

1. Field of the Invention
The present invention relates to a fuse link assembly designed so as to incorporate, into a housing, a plurality of terminals while being connected in a chain manner, as well as to a layout method for the fuse link assembly.
The present invention is based on Japanese Patent Application No. 2001-133553, the entire contents of which are incorporated herein by reference.
2. Related Art
In association with recent developments in electronic control, the number of electronic components used in a vehicle, such as an automobile, has increased. Such an increase in the number of electronic components has in turn led to demand for a large-current fuse. In this case, in order to enhance the efficiency of housing a fuse, there has been proposed a fuse link assembly 1 such as that described in Japanese Patent Application No. 133114/2000 and shown in FIG. 16.
In the fuse link assembly 1, a fuse circuit 5 is constituted by providing a plurality of first terminals 3 and a second terminal 4 on a straight joint plate 2. The fuse circuit 5 is incorporated into a housing 6. The housing 6 is closed with a cover 7 while housing the fuse circuit 5.
However, since a number of the electronic components to be used in a vehicle tend to be increased recently, such the fuse link assembly is required to pack a larger number of circuits. In the fuse link assembly 1 shown in FIG. 16, the first terminals 3 and the second terminal 4 are arranged in a straight line along the joint plate 2. When an attempt is made to increase the number of circuits, the first terminals 3 and the second terminal 4 are increased in number by extending merely the joint plate 2.
When the number of circuits is increased by extending the joint plate 2, the fuse link assembly 1 is gradually extended in a longitudinal direction thereof. The number of circuits to be packed is significantly limited for such the fuse link assemblies due to the layout on the vehicle or restrictions on the geometry and mountability of a relay box.
The present invention has been conceived to solve the problem of the related art and aims at providing a fuse link assembly which enables packing of an increased number of circuits while miniaturizing the overall fuse link assembly and saving space when a fuse circuit having a plurality of terminals provided in a chain manner is incorporated into a housing, as well as providing a layout method for the fuse link assembly.
To achieve the object, there is provided a fuse link assembly comprising: at least two fuse circuits, each having a plurality of terminals, a common joint plate and a circuit connection portion, the terminals being be arranged longitudinally in a chain manner and connected to the joint plate with fusible portions; and a housing in which the fuse circuits are mounted; wherein the fuse circuits are mounted in the housing in parallel with each other and share a power input portion.
In the invention, the fuse circuits, each having a plurality of terminals provided thereon in a chain manner, are mounted in parallel in a housing. As a result, the number of circuits can be increased, by means of enlargement of the width of the housing in which the fuse circuits are provided in parallel, without involvement of an increase in the length of the housing in which terminals are to be connected. The fuse circuits arranged in parallel are connected to a power input portion by means of connecting a common circuit connection portion. Since separate joint plates can share the circuit connection section, the connection of I/O sections can be set efficiently.
More specifically, the plurality of terminals may be cut depending on the presence or absence of a circuit to be connected to the terminals.
By the above construction, the number of terminals to be provided in a chain manner can be changed arbitrarily in accordance with the number of circuits to which the fuse link assembly is to be attached. Hence, one type of fuse link assembly can be used for different circuits.
Further, the housing in which the fuse circuits are mounted may be connected directly to a relay box main body.
By the above construction, there can be omitted a block member which would otherwise be interposed between a housing having a plurality of use circuits incorporated therein and a relay box main body.
The invention provides a layout method for a fuse link assembly comprising the steps of: providing at least two fuse circuits, each having a plurality of terminals and a common joint plate, the terminals being be arranged longitudinally in a chain manner and connected to the joint plate with fusible portions; providing with a circuit connection portion sharing a power input portion; fastening the circuit connection portion together; and mounting the fuse circuits in the housing in parallel with each other.
According to the invention, a plurality of fuse circuits, each having a plurality of terminals provided in a chain manner, are incorporated into a housing in parallel while shared circuit connection portions are fastened. As a result, there can be effected fastening of a plurality of fuse circuits simultaneous with incorporation of the fuse circuits into a housing. Thus, ease of assembly operation can be simplified. Further, the number of fuse circuits can be increased in the widthwise direction in which the fuse circuits are juxtaposed, without involvement of an increase in the longitudinal direction in which terminals are linked.

Fuse link assembly and layout method therefor


A notification system to display notifications at a client device by performing operations that include: coupling, via a communication pathway, a client device with an auxiliary device, the auxiliary device comprising a receiver configured to receive data packets from a pager network; receiving, at the auxiliary device, a data packet that comprises a reference to a data object; and causing the auxiliary device to transmit the reference to the data object to the client device via the communication pathway.

Pagers are typically one-way radio communication systems which operate through a robust network of high-power pager towers. The pager network provides a number of benefits over cellular and Wireless-Fidelity (Wi-Fi) networks, including far greater range, and higher signal penetration. Pagers are therefore often used in geographic locations where other networks are unavailable, and in applications where reliability is of tantamount importance. While the existing pager systems provide the above-mentioned advantages over cellular and Wi-Fi options, they typically lack the significant processing power of modern smartphones, along with the accompanying rich media interfaces.
Accordingly, there is a need for a system which combines the benefits of all of the above systems into a single unified platform, which provides the robust network reliability of the pager network, and the ability to effectively convey information to users through graphical user interfaces.

Messaging system comprising an auxiliary device communicatively coupled with a client device


The invention relates to a method and device for the conversion of digital signals comprising a phase involving modulation with the aid of a vector lattice encoder. The inventive method comprises iterative steps which are performed on N output candidates, consisting in filtering (Hx, Hq), determining the difference between the filtered signals calculating two possible evolutions for said options, pre-selecting the candidates that minimise the difference, weighting the difference with a cost function (W), marking the candidates eliminated for a subsequent iteration, and selecting the best candidate over a period determined by a historical decision dimension. The invention also relates to the use thereof in relation to a digital audio signal amplifier.

Digital amplification, by virtue of its architecture and its mode of operation, brings undeniable advantages as compared with classic analog amplification. The main advantage is its high efficiency; the heat released by a digital amplifier is minimal, enabling far more compact and hence more advantageous construction.
Another advantage of digital amplification is its appropriateness in the use of input digital signals, which naturally prevents resorting to a digital-analog conversion stage known as a "low-level" stage.
Methods and devices have therefore been proposed in the prior art, enabling this digital amplification. More specifically, two main types of digital amplifiers have been proposed, each resorting to a particular modulation method, namely respectively the types of modulation known as PWM and PDM modulation (see Table 1).
PWM-type amplifiers are the most widely used category. They generate pulses whose duration is modulated by a signal to be reproduced. FIG. 1, placed at the end of the present description, represents a simplified exemplary drawing of a standard PWM amplifier referenced 1.
The amplifier 1 comprises a modulator stage 10 proper, of the above-mentioned PWM type. This modulator 10 itself has the following elements in a cascade connection: an over-sampling circuit, typically x8, a circuit known as a pre-distortion circuit 101, a circuit called a noise shaper 102, and a PCM-PWM type conversion circuit 103. The input e1 of the PWM modulated 10 receives a PCM-encoded digital signal. These circuits are the digital part proper of the amplifier 1.
The output s10 of the modulator 10 is transmitted to a switching stage 11, forming a boundary between the digital and analog paths of the amplifier 1.
The signal, which is henceforth an analog signal, present at the output s11 of the switching stage 11 is filtered by an output filter 12 before being transmitted to use circuits (not shown) through the general output of the amplifier s1.
More specifically, the switching stage 11 may be a two-level or three-level or logic-state switching stage, this depending on the precise configuration of the modulator 10. It is generally implemented in the form of an H bridge or H semi-bridge, made as an integrated circuit or in the form of discrete components.
The output filter 12 is a low-pass filter, typically a second-order or fourth-order filter. It is designed to eliminate the switching noises from the output signal
The pre-distortion module 101 is used to counter-balance the distortion introduced by the PCM-PWM converter 103, generally known as the U.PWM type converter.
The working and characteristics, in more precise detail, of an amplifier implementing PWM technology are well known to those skilled in the art, and it is unnecessary to describe them any further.
The main disadvantage of PWM digital amplifiers is related to the production of high-frequency residues known as tonal residues which furthermore are of high amplitude. This dysfunction is due to the repetitive cycle of the PWM approach. These residues pose problems in terms of electromagnetic compatibility for certain environments in which they are used, especially for automobile-related applications.
By way of an example, FIG. 2, placed at the end of the present description, represents a frequency spectrum, ranging between 0 and 2.5 MHz, resulting from a typical implementation of the PWM amplifier of FIG. 1, when it is supplied with a high-amplitude 1 kHz sine signal. In particular, major tonal residues are seen to appear at a level close to the fundamental frequency. These residues could present problems of electromagnetic compatibility.
FIG. 3, placed at the end of the present description, is an example of a simplified drawing of a standard PDM amplifier, referenced 2.
The PDM type amplifiers have been the subject of numerous theoretical studies but there are only a few apparatuses on the market implementing this technology, all of them produced by the firm Sharp (registered mark). These amplifiers rely on the same encoding method as the SACD amplifiers (see Table 1), this method being called the DSD method (see Table 1).
The general architecture of the amplifier is similar to that of the amplifier 1 of FIG. 1: a modulator 20, receiving a PCM-format digital signal at its input e2, a switching stage 21 receiving the signal present at the output s20 of the modulator 20 and an output filter 21 receiving the signal present at the output s21 of the selector switch 21. The signal delivered at the general output s2 of the digital amplifier 2 is transmitted, as here above, to use circuits (not shown).
The basic difference between the two amplifiers of FIG. 1 and 2 lies in the nature of the modulator, namely a PDM type modulator 20 in the present case, comprising, in a cascade connection, an over-sampling circuit 200, typically x64 or x128, and a circuit known as a noise shaper circuit 201, which is typically a seventh-order circuit.
Again as here above, the switching stage 21 may be a two-level or a three-level stage, depending on the precise modulator implemented. It is generally implemented in the form of an H bridge or H semi-bridge, made as an integrated circuit or in the form of discrete components. The output filter 22 is no pass filter, typically a second-order or fourth-order filter, a low-pass filter designed to eliminate the switching noises from the output signal delivered on the general output s21.
The working and characteristics, in more precise detail, of an amplifier implementing PWM technology are well known to those skilled in the art, and it is unnecessary to describe them any further.
Although they do not have significant tonal characteristics, the high frequency residues prompted by this type of digital amplifier are very great and are endowed with high energy. This characteristic raises no problems as regards low-level conversions may but, on the contrary, represent a technological challenge for higher power values, generating an additional cost. Indeed, the high switching frequency of the output stage may be detrimental to the efficiency of the amplifier.
FIG. 4, placed at the end of the present description, represents the frequency spectrum, ranging between 0 and 2.5 MHz, resulting from a typical implementation of the PDM amplifier 2 when it is supplied with a simple, high-amplitude sine signal. It can be seen in particular that the noise level which is elevated in terms of high frequency, bears witness to a high switching frequency of the output stage.
Despite the theoretical interest represented by the use of the digital methods of the above description, it can be seen that digital amplifier implementations with digital inputs, compliant with the prior art, continue to present drawbacks which may rule out the use of the devices in certain fields of application.

Method and device for the version of digital signals with heterogeneous formats and application thereof to the digital amplification of audio signals


The present invention relates to the use of protein expression profiles of sPLA2 isoforms with clinical relevance to osteoarthritis (OA). In particular, the invention provides methods for diagnosing OA or determining risk factors for development of OA based on expression of sPLA2-IIA.

Osteoarthritis (OA) is a progressive joint disease, which is characterized by the breakdown of joint cartilage. It may affect one or more joints in the body, including those of the fingers, neck, shoulder, hips, knees, lower spine region, and feet. OA can cause pain and severely impair mobility and lower extremity function (E. Bagge et al., Age Ageing, 1992, 21: 160-167; D. Hamerman, Ann. Rheum. Dis., 1995, 54: 82-85; J. Jordan et al., J. Rheumatol., 1997, 24: 1344-1349; S. M. Ling and J. M. Bathon, J. Am. Geriatr. Soc., 1998, 46: 216-225), which can lead to disability and difficulty maintaining independence (A. A. Guccione et al., Am. J. Public Health, 1994, 84: 351-358; M. A Gignac et al., J. Gerontol. B: Psychol. Sci. Soc. Sci., 2000, 55: 362-372; M. C. Corti and C. Rignon, Aging Clin. Exp. Res., 2003, 15: 359-363). OA is associated with aging: the prevalence of radiographic osteoarthritis is less than 1% in people under 30 years of age but, with increasing age, the prevalence rises sharply and was found to be approximately 80% in individuals over 65 (R. C. Lawrence et al., J. Rheumatol., 1989, 16: 427-441; E. Bagge and P. Brooks, Drugs Aging, 1995, 7: 176-183; N. J. Manek and N. E. Lane, Am. Fam. Physician., 2000, 61: 1795-1804). Despite being a condition that causes most problems to populations after retirement age, OA is also rated the highest cause of work loss in the U.S. and Europe. In addition to age, risk factors known to be associated with OA include obesity, traumatic injury and overuse due to sports or occupational stresses. However, the precise etiology of osteoarthritis is still unknown.
Currently, diagnosis of OA is typically based upon radiological examination as well as clinical observations including localized tenderness, use-related pain, bony or soft tissue swelling, joint instability, limited joint function, muscle spasm, and crepitus (i.e., cracking or grinding sensation). While the diagnosis of OA is often suggested on physical examination, radiographic evaluation is generally used to confirm the diagnosis or assess the severity of the disease. The radiographic hallmarks of OA include non-uniform joint space loss, osteophyte formation, cyst formation, and subchondral sclerosis. While these characteristic features are generally present in X-ray images of "severe" or "late" OA, patients with "early" OA may not show radiographic evidence of bony changes, joint space narrowing and/or osteophytosis, making the diagnosis unclear or difficult to establish. In the absence of a reliable diagnosis, physicians cannot intervene early in the course of the disease, i.e. before signs of joint destruction arise. Magnetic resonance imaging (MRI) is used for delineating articular cartilage morphology and composition, particularly in large joints such as the knee, and can reveal cartilage defects and thinning regions of the joint not visible with radiography (K. Ott and J. Montes-Lucero, Radiol. Technol., 2002, 74: 25-42; F. Eckstein and C. Glaser, Semin. Mucculoskelet. Radiol., 2004, 8: 329-353; G. A. Tung, Med. Health R. I., 2004, 87: 172-175). However, recent studies indicate that MRI may not be very useful in diagnosing OA, due to the frequent incidence of meniscal tears, which may appear both in the presence or absence of knee pain and/or other symptoms of osteoarthritic disease (M. Englund, et al., The New England Journal of Medicine, 2008, 359; 11: 1108-1115).
An additional diagnostic method for OA is arthroscopy, in which a small incision in the patient's skin is made and fiber optic instruments are inserted into the joint. This procedure allows the visualization of the interior of the joint through this very small incision rather than a large incision needed for surgery. However, this technique is invasive, expensive, and may lead to additional pain in the joint. Therefore, alternative, less costly and invasive diagnostic procedures are desirable.
There is currently no cure for OA, and available osteoarthritis therapies are directed at the symptomatic relief of pain, and at improving and maintaining joint function. Furthermore, in the context of the recent withdrawals of COX-2 inhibitors, physicians are even more limited in their choice of treatments for OA. The demand for disease-modifying drugs for OA has grown considerably as awareness of the profound social and economic impact of this prevalent and debilitating disorder has become widespread. However, clinical trials of such drugs rely on the assessment of changes in joint space observed using plain X-rays (S. A. Mazzuca et al., Osteoarthritis and Cartilage, 1997, 5: 217-226). Since changes caused by articular cartilage loss are small (1-2 mm per year), a minimum of one year is required before sufficient changes have occurred to be detectable and, therefore, before a drug's efficacy can be assessed.
Clearly, there is a great need for biological markers of OA and OA progression. In particular, biomarkers that would allow reliable diagnosis and monitoring in the early stages of the disease and permit early intervention to potentially prevent pain and long-term disability are highly desirable. Also needed are biomarkers and design assay systems that could evaluate the efficacy of disease-modifying OA drugs in a time frame significantly shorter than the year currently required for assessment of radiological changes.

Secreted phospholipase A2 biomarkers for arthritis


Systems, methods and articles for automating the process of registering a product purchased by a consumer from a merchant in a purchase transaction. Product data including product identification data is obtained from a merchant electronic point of sale system as the consumer checks out. The product data is then automatically transmitted to a product registration system, such as via a consumer's mobile communication device having a product registration app. An auto-registration database is accessed to see if auto-registration is available for the product. If auto-registration is available for the product, then a request is made to the consumer to authorize auto-registration for the product. If the consumer accepts the auto-registration, then consumer data, such as the consumer name and contact information, is sent to the product registration system. The product registration system then creates a product registration record using the product data and the consumer data.

The invention relates to registration of products to a particular consumer, such as product registration of software or a television; and more particularly, to new systems and methods for automating, at least in part, the process of registering products to a respective consumer.
Many companies that sell products provide a process for allowing a consumer to register a purchased product with the company which documents the consumer as the owner and user of a particular product purchased by the consumer. For instance, a product provider, such as a manufacturer, seller, distributor, and/or retailer, may provide a website where a consumer can register a product. The product will typically include information describing how the product can be registered, such as by filling out a registration card and mailing it to the provider, or completing an online registration form. The registration will include product data, such as the make and model of the product and in some cases a serial number identifying the particular product. The registration will also request consumer data from the consumer, such as the consumer's name, address, contact information, such as email address and/or phone number. The consumer data may also include more personal information such as age, gender, income, and other personal information. Thus, the product registration gives the product provider a record of the relationship between a product and the consumer that purchased the product, in addition to other data that can be obtained regarding the consumers, such as consumer demographics.
Product registration can provide many benefits to the product providers, and to the consumers. For example, product registration allows the product providers to contact the consumer with product information, such as product updates, recalls, and warranty information. The registration can also allow the consumer to provide feedback and reviews of the product. In addition, registration can serve as a verification of ownership if the product is stolen or lost. From a marketing perspective, product registration allows product providers to communicate with their customers, providing an opportunity to up-sell their products, cross-sell other products such as warranties and service agreements, and market new products. The information obtained from product registration also allows the providers to maintain a database of their customers and obtain marketing data about their customers which can be used to develop and implement marketing plans and maintain a relationship with their customers. For instance, special offers and promotions may be offered to registered consumers.
However, many consumers forego product registration for various reasons. Some consumers prefer not to register their products because of privacy concerns, and they prefer not to be contacted and/or solicited as a result of product registration. In addition, some consumers avoid product registration because it is time consuming and a hassle to register. Registering can be a painful experience because the consumer needs to manually enter a lot of information, such as the product data and consumer data described above.
Nowadays, most point of sale ("POS") purchases of products are processed electronically using a computerized cash register system, also called an electronic point of sale system. The cash register system typically has a "cash register," which is now quite commonly a standalone computer with point of sale software, having a cash drawer for storing cash and coins. Usually, the cash register is operably coupled to some form of product scanning device, such as a barcode scanner. The individual cash registers may also be networked to a central database and back office system capable of processing payment transactions, tracking inventory, etc. In order to process a purchase, the product is entered into the electronic point of sale system, such as by scanning a barcode on the product, or otherwise entering a product identification code into the POS system. The cash register system will typically also have an electronic payment device, such as a credit/debit card terminal.
Indeed, electronic payments have become more and more common for consumers to pay merchants for goods or services. Electronic payments come in various forms, the most common being financial account cards such as credit cards and debit cards, but also include gift cards, ATM cards, payments such as ACH, e Check, PayPal®, and other forms of payment capable of being electronically executed. In addition to fixed location credit card terminals, payment applications (software programs) have been developed for accepting electronic payments on mobile communication devices, such as smartphones, tablet computers, and laptop computers. In this way, electronic payments can be accepted almost anywhere.
While financial account cards are quite convenient, even more convenient electronic payment forms are becoming available, such as near field communication (NFC) devices and "mobile wallets" implemented on mobile communication devices like smartphones. NFC devices are small tags (sometimes referred to as RFID tags, radio-frequency identification) having encrypted identification information for referencing a financial account. The mobile wallet enabled smartphones also have an NFC device incorporated into their electronics. The NFC device or smartphone need only be placed in close proximity (as used herein, close proximity includes being in contact with) to a merchant NFC reader in order to establish a communication connection. The NFC reader then communicates with the NFC device or smartphone in order to exchange sufficient information to complete a purchase transaction. For example, the NFC device or smartphone may transmit encrypted financial account or customer identification information to the NFC reader, which can then be used to process the purchase transaction. As with a typical credit/debit card transaction, the customer may also have to input a personal identification number (PIN) or other verification data in order to authorize and complete the transaction.
In order to process an electronic payment transaction, a merchant enters financial account data tendered by the customer into the electronic payment device, be it a payment terminal, mobile communication device, NFC reader or the like. For example, the customer may tender a credit card, and the merchant may enter the credit card data into the payment terminal by swiping the card in a card reader of a payment terminal to read the data from the magnetic strip on the credit card. The merchant also enters the amount of the transaction into the payment terminal, which may be automatically executed by an electronic POS system. Certain verification information may also be entered, such as a card verification value ("CVV") and/or card expiration date.
The transaction data, including the card number, purchase amount and verification information are transmitted to a merchant account provider, or a third party payment processor, such as First Data, which then sends the data to a merchant account provider. A merchant account is part of merchant services provided by a debit/credit card payment processor and/or independent sales organization ("ISO") (also referred to as the merchant services provider) based on an agreement (referred to as the merchant service agreement) between a merchant (e.g., a retailer), a financial institution (e.g., a merchant bank that issues the debit/credit card), the payment processor and/or ISO, for the settlement of debit/credit card transactions. In particular, the payment processor and/or ISO may be a bank or underwritten by a bank. The merchant account provider is the account provider that provides the electronic payment processing services to the merchant. The merchant account provider then sends the financial account transaction, within batched transactions, through one of the electronic payment networks, such as Visa®, Mastercard®, or American Express®, to the prepaid card issuer (or the bank of the card issuer). Typically, the credit/debit card issuer then pays the merchant account provider the purchase amount less a transaction fee, and the merchant account provider then pays the merchant the amount of the electronic payment, minus a fee for processing the transaction. Alternatively, the prepaid card issuer may directly pay the merchant the amount of the electronic payment, minus a fee for processing the transaction. In summary, the transaction steps in settling debit/credit card transactions include authorization, clearing, funding, and the handling of any chargebacks.
The computers systems and communication systems required to process the above-described electronic payments is called an electronic payment processing system. The electronic transaction flow is similar to the credit card transaction described above for the other forms of electronic payments, such as debit cards, eChecks, ACH, NFC tag payments, and mobile wallet payments.

Methods and systems for automated product registration


A hinged two piece structure to remind an operator that a valve is on is disclosed. The valve shut-off flag is retained to a valve by a simple clamp and is therefore readily adaptable for use on many different types of valves, although the preferred embodiment has application on oxygen-acetylene torch sets. One piece of the structure acts as a support column for a hinge and a second piece of structure. The second structure piece partially covers the valve when the valve is in the closed or shut position. In order to turn on the valve, a user must lift the second structure piece to an upright position where it extends substantially beyond the valve. The second structure piece is of sufficient surface area and colored appropriately so as to catch the eye of a user.

1. Field of the Invention
The present apparatus pertains generally to fluid control valves such as might commonly be found in water control or gas canisters, and specifically to indicator devices which signal the on or off state of the valve.
2. Description of the Related Art
Valves used to control the movement of fluids often times exist in an environment where it is not possible to view the fluid to determine motion of that fluid. This might occur in a water main where by the location of the main underground no sighting of water flow is possible from above ground. Another similar situation arises in the case of pressurized gas canisters due to potential transparency and lack of odor of the gas. In the particular case of the pressurized gas canister, even if a downstream valve is closed, the gas may still seep through. A resultant slow leak may pose health hazards dependent upon the gas type. The slow leak will also prove annoying and expensive in the replacement cost of the gas.
Several systems have been devised to indicate to a viewer or listener that a valve has undesirably been left in the open or on position. One system is disclosed by Furtney in U.S. Pat. No. 2,015,398. Furtney discloses a waterglass valve which, when in the off position, prominently displays a "differently" colored "shut" sign. The Furtney system requires that the valve be designed to accomodate the "shut" flag, and will not operate as a retrofit. Further, the Furtney valve would have to be substantially redisigned to be of any use on a system different than the boiler type system for which it was designed.
Another system is shown by Haws in U.S. Pat. No. 4,665,386. Haws discloses an electromechanical annunciating device. The device readily attaches to a pressurized gas canister at the valve. When rotated in the opening direction, a timer starts and will activate a bell if the valve is not closed. While the Haws system is readily retrofitted to any type of hand actuated valve, the operation and effectiveness of the device is questionable. If an explosive gas were to be left on and unattended for some reason, the activation of the device could cause a dangerous explosion. Additionally, if a user of the tank finishes hurriedly and leaves, the annunciater will ring without anyone being around to hear it. Then the user will not only have to replace the gas, but also the batteries.


A plug-in socket for coupling to a corresponding standard plug and for connection of an electrical terminal device to a primary voltage. The plug-in socket improves the use of mains units with voltage converters. The plug-in socket comprises a socket housing, a first electrical contact arranged in the socket housing for coupling to a corresponding standard plug electrical contact, a voltage converter integrated in the socket housing and converting a primary voltage into at least one secondary voltage for the electrical terminal device, a second electrical contact arranged on the socket housing for electrical contacting of the secondary voltage, wherein the voltage converter is integrated in the socket housing so that the external dimensions of the socket housing are substantially predetermined by the dimensions of the corresponding standard plug.

a) Field of the Invention
The invention concerns mains units for voltage conversion for electronic terminal devices. The invention concerns in particular a plug-in socket for coupling to corresponding standard plugs and for connecting an electrical terminal device to a voltage supply. The invention also concerns means for voltage conversion for a plug-in socket.
b) Description of the Related Art
Voltage converters in the form of what are referred to as mains units have been known for some time. They convert a primary voltage (for example a mains voltage) into a secondary voltage. In a wide-spread form those mains units are disposed in a separate housing and connected to the mains network by means of a cable. A further cable connects the mains unit and the terminal device to be supplied.
In another wide-spread form as is known for example from laid-open EP 0 085 802 A1 the mains unit has a housing which is fixedly connected to the housing of a mains plug.
DE 93 208 93 U1 discloses a mains plug with incorporated mains unit, a so-called plug mains unit. The electronic system for converting a primary voltage into a secondary voltage is disposed with other electronic components on a circuit board.
DE 42 27 629 A1 also discloses a mains plug for the connection of electrical terminal devices. In order to dissipate the heat loss from voltage transformation away from the plug housing it is proposed that the plug pins are used for cooling purposes.
Wolski, Gerhard B: Komplettes Netzteil in einem Chip. EN: DE/Der Elektromeister+deutsches Handwerk. 1990, DE 22/90, pages 1673, 1674, 1679 describes a complete mains unit which is implemented in a single chip.
Mains units are therefore known in which the voltage converter is disposed in a separate housing outside the item of equipment to be supplied. Electrical coupling to the mains network as well as electrical coupling of the terminal device which is to be supplied are effected by means of separate electric lines.
Mains units are frequently also embodied in the form of part of the electronic device system. They are disposed for example on the same printed circuit board as the rest of the electronic components of the terminal device. Mains units are also known which are specifically suitable for use in computers. They are disposed in their own housing which in turn is incorporated into the housing of the terminal device to be supplied. Those mains units are not hermetically sealed and in addition involve artificial convection, for example they have a possible way of dissipating waste heat, for example by way of slots and their own electrical ventilation.
When using separate mains units, for example in the configuration of a plug mains unit, but also in relation to the mains units in a separate housing within a larger housing of the terminal device, considerable limitations in terms of operating comfort and convenience and a high level of complication and expenditure in terms of installation and contacting of those mains units with the mains network have to be accepted. External mains units which have cable connections on both sides also considerably restrict the level of convenience of use. A problem which frequently occurs is that the weight of the mains unit which in fact is arranged centrally in the cable pulls on the cable in such a way that either the plug connection to the terminal device comes loose or the terminal device can even be pulled down off a support and destroyed.

Plug-in socket provided with a voltage converter


A dynamically addressable master-slave system and a method for dynamically addressing slave units includes a master unit and a plurality of slave units, such that the slave units are interconnected with the master unit via a bus system. The respective network addresses of the slave units are assigned to the respective serial numbers of these slave units in a table in the master unit according to the position thereof in the system according to a determined order. Upon replacement of slave units, a list of serial numbers of the units to be replaced is transferred to the master unit in the sequence of the acquisition of the serial numbers, which master unit replaces these serial numbers in the table with the serial numbers of the replaced slave units transmitted to the master unit.

The statements in this section merely provide background information related to the present disclosure and several definitions for terms used in the present disclosure and may not constitute prior art.
There are diverse methods for address allocation in a network in the prior art, for example, manual IP address allocation in the case of network devices (computers, printers, etc.), auto-addressing based on serial numbers, address allocation according to a defined wiring plan, or shift register address allocation. For example, DE 103 36 301 A1 proposes an automated addressing procedure. A bus-based addressing method of slave units is known from EP 2 287 689 EP.
Bus systems are used, for example, for data transmission between multiple users in a facility network. Bus systems of greatly varying types have been known for some time. The master-slave bus systems on which the present invention is based usually have the property that all slave units have to have unique network addresses to be able to be individually addressed. Individual slaves can thus be addressed individually and intentionally by means of a bus system, wherein in addition the settings of the slave can be changed or items of status information can be requested from the slave. In a facility in which devices based on serial numbers, such as motors, fans, or other units having a serial number are present, in which one or more defective devices are to be replaced, the replacement devices to be installed are to identically take over the logical addresses of the devices removed from the facility, so that the respective new device is recognized by the network as the original device and has precisely the same logical network address which the device previously located at this facility position had.
A master unit is thus capable in the case of a specific slave unit, and accordingly in the case of a replaced slave unit, of actuating a system component activated by this slave unit, or assigning received messages to such a slave unit and thus a very specific system component. To ensure such a functionality, the replaced slave unit requires, on the one hand, a system-wide unique address, on the other hand, the unique address and the association of the replaced slave unit with a system component or its position in the bus system have to be known to the master unit.
This is conventionally achieved, for example, in that an addressing or orientation phase is carried out during the initialization of a bus system. In this phase the slave units are, for example, assigned system addresses in a specific sequence, or the master unit is given the option of successively requesting stored device identifiers of individual slave units at various positions. However, in the case of a replacement of defective devices, this type of address allocation does not offer a solution for achieving the above-mentioned goal that the respective new device having a changed serial number is recognized by the network as the original device, which has a different serial number, and precisely the same logical network address now has had to be linked to a different serial number than the device previously located at this facility position had.
A master-slave system is proposed in DE 10 2014 117 797.5 A1, which is configured in such a way that at the input of the closest slave unit, a signal (signal change), which is provided by the digital output, of a serial signal sequence is detected to increase the address of the corresponding slave unit by the value "1" in each case, to store the signal change in the memory, and to output a signal corresponding to the content of the memory at the output of the memory. This addressing method has the disadvantage that a clock signal from the master is required for addressing via shift register and thus a linkage to the serial number cannot be established. A replaced device does receive the address defined in the series of the slave units, without the master unit and the central controller knowing, however, which device was installed or replaced having which specific serial number. If multiple such replacement measures take place over time, the data in the system thus no longer correspond at all to the serial numbers upon startup.
Another method is known from U.S. Pat. No. 8,856,413 B2, comprising an interface bus, an enable circuit having a switch, and two control ports, which are connected via the enable circuit. The system is configured in such a way that the address assignment is only possible when the bus interface control signal is applied to one of the ports and is thus open to control the enabling of the signal switch. Otherwise, the release circuit locks the slave unit. This method has the disadvantage that the above-described problem of the device replacement also cannot be solved thereby.

Wireless allocation of network addresses


The present invention relates to a system and method of organic thin-film transistors (OTFTs). More specifically, the present invention relates to employing a flexible, conductive particle-polymer composite material for ohmic contacts (i.e. drain and source).

(1) Technical Field
The present invention relates to a system and method of fabricating organic thin-film transistors (OTFTs). More specifically, the present invention relates to the employment of a flexible, conductive particle-polymer composite material for ohmic contacts (i.e. drain and source).
(2) Description of Related Art
Organic electronics have recently attracted tremendous interest within the microelectronics industry for potential use in a wide range of commercial applications, such as large area flexible displays as well as other consumer electronics applications including smart cards, radio frequency identification (RFID) tags and electronic paper. This technology utilizes molecular and polymeric semiconducting compounds in place of traditional materials such as silicon. Thin-film transistors (TFTs) and organic light-emitting diodes (OLEDs) can be fabricated from different organic and polymeric compounds using a variety of low-temperature, low-cost processing techniques including solution casting, spin coating and ink jet printing.
Steady improvements in materials and processes over the last few years have brought the performance of organic-TFT (OTFT) devices in line with that of amorphous silicon devices. Unlike amorphous silicon, however, the organic semiconducting layers can be deposited at room temperature, allowing the organic semiconducting layers to be printed directly onto heat-sensitive structures. These TFTs can be used in applications where low-cost or mechanical flexibility is required.
Beyond the aforementioned commercial applications, development of robust organic electronics for extreme environmental conditions is also of interest for space and military applications. Possible applications to human exploration of space include flexible displays, flexible health sensing electronics, and chemical/biological sensing electronics which could be incorporated into protective clothing. Potential applications for robotic missions include distributed sensors for large area surface diagnostics and metrology on inflatable/deployable structures. Examples of distributed sensors include temperature sensors, strain sensors, shape sensors, tear detection sensors or even sensors to control piezoelectric actuators. In the case of sensors distributed on large-area surfaces of inflatable/deployable structures, integration of rigid silicon-based chips within such a structure is impractical due to problems with assembly, die thinning, mechanical stresses, thermal mismatch and die attach. For these applications, very high-density electronics are not required (due to the very large areas available) and could benefit from the integration of flexible (OTFT) based sensor and sensor electronics.
Previous work in the area of organic transistors has focused on the use of either 1) vacuum-deposited noble metal contacts or 2) solution-deposited intrinsically conducting molecular or polymeric contacts to the form the drain and source contacts.
Use of vacuum-deposited noble metal contacts, such as gold or platinum, obviates one of the main benefits of organic electronics, i.e., low-cost processing based on solution or printing techniques. Vacuum deposition requires the use of techniques, such as sputtering or evaporation, instead of less expensive solution-based processes such as spin coating, casting or printing. Second, the use of gold or platinum for coating large area devices is potentially expensive, both from a stand point of materials and processing equipment. Again, this approach runs counter to the perceived low-cost benefit of organic electronics. Furthermore, the adhesion of gold to many organic materials is very poor.
Some recent work has been carried out regarding intrinsically conducting molecular-based or polymeric-based contacts such as polyaniline and TTF-TCNQ, examples of such work include C. J. Druru, C. M. J. Mutsaers, C. M. Hart, et al., "Low-cost All-polymer Integrated Circuits, Applied Physics Letters, vol. 73, pp. 108-110, July 1998 and K. Saito and S. Kobayashi, "Deposition of Organic Electrodes Based on Wet Process for Organic Devices," Applied Physics Letters, vol. 80, pp. 1489-1491, February 2002. Unfortunately, these materials tend to exhibit high resistivities and poor overall performance, are prone to reaction with the surrounding environment, and are potentially unstable over time.
Within the field of organic electronics, the search continues for molecular and polymeric semiconducting materials, which are soluble in common solvents, stable under ambient conditions and exhibit high carrier mobilities. In addition, within the field of organic electronics, studies are being conducted regarding materials that can be used as the gate dielectric and as the drain and source contact layers for organic-thin-film transistor (OTFT) devices. The drain and source contacts are particularly critical, as they form a direct ohmic contact with the organic semiconductor. Furthermore, it is desirable that these contacts be stable over time with respect to the semiconductor and dielectric interfaces as well as the ambient environment, particularly when biased at high voltages (up to a 100 V differential between drain/source and source/gate). Finally, for many emerging applications, it is desirable that these contacts be flexible, and may be able to be processed at low temperatures while maintaining adequate adhesion to the underlying substrate.
To achieve an ohmic contact to the organic semiconductor, the work function of the contact should be well matched to that of the semiconductor. Previous work has focused on the use of noble metal contacts and conducting polymers to form these contacts. However, this type of processing can be expensive and can result in poor quality devices. What are needed are contacts which are inexpensive, flexible, stable, form ohmic contacts to common organic semiconductors, and can be readily processed without the need for expensive processing equipment, such as vacuum deposition equipment.

Flexible carbon-based ohmic contacts for organic transistors


The invention provides a combination of a source of a CD39 and of a source of a CD73.

Rheumatoid arthritis (RA) is a chronic inflammatory disease that affects ˜1% of the population. It is a complicated auto-immune disease and its etiology is unclear, however there are a number of factors (genetic, environmental, etc) that can contribute to the pathology1. Several treatments are already known to treat an inflammatory disease such as RA. However, each of these treatments has drawbacks. In the case of confirmed diagnosis the recommended gold standard is to initiate methotrexate (MTX) treatment. Methotrexate is the most commonly prescribed drug for rheumatoid arthritis. It acts by inhibiting the enzyme dihydrofolate reductase, thus interfering with the folate processing machinery of the cell and affecting cell division2. MTX is often used in combination with other conventional disease modifying anti-rheumatic drugs (DMARDs) and/or corticosteroids. MTX side effects include gastrointestinal effects and an increased chance of liver damage, leading to 16-18% of patients withdrawing from treatment′. If disease activity cannot be controlled by conventional treatment, biological treatment is considered. Biologicals like anti-TNF therapies (infliximab, etanercept), CTLA4-Ig (abatacept), anti-CD20 (rituximab), and anti-interleukin 6 (IL6) receptor (tocilizumab), have the potential to reduce toxic side effects due to their specificity4, however these treatments come with their own side effects, including increased risk of infection and increased risk of heart disease. It is now possible to reach 20% improvement in about 60% of the RA patients using this approach. However, biologicals have limited effects in many patients and the need for repetitive therapy remains.
Therefore there is still a need for designing new treatments for inflammatory diseases such as RA which do not have all the drawbacks of existing treatments.

Combination for treating an inflammatory disorder


A fence post extractor includes a sleeve for receiving a fence post and a clamping bar that is pivotable with respect to the sleeve at a pivot joint. The clamping bar pivots between a first position where the fence post is clamped between a second end of the clamping bar and the sleeve, and a second position where the fence post is released with respect to the second end of the clamping bar. A powered lifting apparatus has an engaging portion that is engaged with the clamping bar. The engaging portion is moved under power between a raised position and a lowered position to move the clamping bar between the first and second positions.

Fence post removal can be a laborious and time-consuming task. In most cases, a very large pulling force must be applied to the fence post in order to remove it from an installed condition in the ground. Removal of fence posts is further complicated by the fact that it is difficult to securely grasp certain fence posts, either manually or using tools.
In order to overcome the challenges presented by fence post removal, a large number of tools have been previously proposed. The great majority of these tools rely on manual application of force in order to remove a fence post. Such tools may be suitable for removal of a small number of posts but are not well-suited for larger jobs, as the workers tasked with removing the fence posts will quickly become fatigued. A limited number of previous designs have attempted to apply some manner of powered lifting means to removal of a fence post. Some of these designs rely on leverage induced by rotation of a sleeve in which a pole is inserted. Such devices have no active clamping mechanisms but rather require that torque be applied to the fence post in order to grip the post and remove it from the ground. This requires a lifting means that can produce a very high degree of lifting force. As a result, the post may become damaged during removal to an extent that prevents reuse of the post.
Other designs have attempted to grip posts by use of a pawl-type arrangement or other mechanical catch that engages an irregular surface on the post itself. These designs are particularly adapted to remove fence posts of the well-known "T" post design. Such fence posts have a T-shaped cross-section and projections on one surface to which fencing can be attached. The projections provide an engagement surface for the pawl-type engaging member. In these designs, release of the fence post with respect to the tool may require operation of a release mechanism that causes the pawl-type engagement structure to disengage from the fence post. The need for manual disengagement, as well as the complexity associated with such a design, serve as impediments to widespread adoption and use of such a design.
It would be desirable to have a fence post extractor that could be operated by a powered lifting means, is capable of engaging the fence post without the need for application of a high degree of torque or lifting force, and may be released from engagement with the fence post without operation of a separate release mechanism.