A method and device for maintaining data coherency in a semiconductor memory device, having two or more memory chips combined into one chip and operated according to a late select synchronous pipeline type input/output protocol. A method includes the steps of generating first and second bypass summation signals by utilizing a chip block select address signal inputted in a latest write operation and comparison signals obtained from comparison between a latest write address and a current read address; and generating first and second bypass control signals having logic values contrary to each other by utilizing the first and second bypass summation signals and an internal clock signal, wherein a bypass operation is performed in one of read paths associated with the memory chips and a normal read operation is performed through other read paths when all the comparison signals are same.

1. Field of the Invention
The present invention relates to a semiconductor memory device; more particularly, to a system and method for maintaining data coherency in synchronous pipeline type semiconductor memory devices.
2. Description of the Related Art
Synchronous pipeline type semiconductor memory devices generally use a common input output (IO) mode in which input/output signal busses are shared to reduce package complexity, cost of chip, and ease of system mount on board, etc. However, such a common IO mode may cause a data contention problem between output data being outputted from memory cells and input data that are recorded in memory cells in a back-to-back operation such as a write-to-read operation or a read-to-write operation.
Therefore, to prevent the data contention problem, a dead cycle, that is, a no-operation period (NOP) should be added while a read operation is changed to a write operation. For this reason, many synchronous pipeline type semiconductor memory devices tend to employ the late write mode during write operations in which input data is input about 1 cycle to 2 cycles later than input addresses, thereby minimizing the number of NOP cycles.
Conventional synchronous type semiconductor memory devices for high-speed operation are disclosed, for example, in U.S. Pat. No. 5,717,653 to Suzuki, issued on Feb. 10, 1998, xe2x80x9cLate-write type SRAM in which address decoding time for reading data differs from address-decoding time for writing data.xe2x80x9d Suzuki describes a late-write type SRAM wherein the total time required to write data can be reduced.
The late-write type memory device in a late write operation delays write addresses inputted from the outside for several cycles to input the write address to an address decoder and select word lines and bit lines. A data input signal inputted from the outside after being delayed by several cycles from write address input is transmitted to a write driver, thereby a write operation starts after several cycles. That is, the write operation after 2 cycles in a late-write type memory device means that data to be written is input 2 cycles after a write address is input.
In such a late write method, when a write operation is changed into a read operation, data inputted in a final write operation are not written in a predetermined memory cell in a cell array, but stored in an input register only. Accordingly, if a read operation for an address corresponding to the final write operation is performed, the semiconductor memory device directly transmits data in an input register, not in a memory cell, to an output driver. This is called a bypass operation.
Recent semiconductor memory devices employ the bypass operation to maintain data coherency other than the late write mode. That is, in such semiconductor memory devices, when write order is input several cycles before read order is input and a write address is the same as a read address, a prior write data is output through an output buffer without a normal read operation from a memory cell.
FIG. 1 shows a conventional circuit block performing a bypass operation to maintain data coherency in a synchronous type semiconductor memory device. Where the address SAx register 10 samples and stores an external address SAx every cycle according to the internal clock signal KAI. The stored external address SAx is output as an input address RSAx. The input address RSAx is output as a read address signal ADDRESS T through the multiplexer 14 responding to the internal clock KAR in a read operation, and stored in the write address register 12 responding to the internal clock KAW in a write operation. The input address stored in the write address register 12 is output as a write address WSAx, and output as a write address signal ADDRESS C through the multiplexer 14 responding to the internal clock KAW in a next write operation. The read address signal ADDRESS T and write address signal ADDRESS C are input to column and row address decoders (not shown).
A comparator 16 compares the input address RSAx with the write address WSAx to determine whether the write address is the same as the input address. Here, the input address RSAx is a read address in a late write mode. Bypass comparison signals BYP1_SAx being outputted from the comparator 16 is input to a bypass summator 17. The bypass summator 17 sums the bypass comparison signals BYP1_SAx to output a summation signal BYPSUMB to a bypass control part 24. The bypass control part 24 receives and logically gates the bypass summation signal BYPSUMB and the internal clock signal KFLAG to output a bypass control signal KBYP and a core control signal KCORE. When the bypass control signal KBYP is enabled, the core control signal KCORE is disabled, thereby stopping an operation in a first transmission part 22. Accordingly, the output data of a sense amplifier amplifying data in a memory cell in a memory array cannot be transferred to a data output buffer 30. On the other hand, when a second transmission part 28 is operated, the write data WDIN that has not been stored in the memory cell but stored in a data input register 26 is input to the data output buffer 30. That is, the bypass operation is performed. The data output buffer 30 outputs the write data WDIN to the off-chip driver OCD 32 in response to the buffer control signal KDATA. The off chip driver 32 drives and finally outputs the buffered write data WDIN as an external output data XDQ.
However, it is difficult to apply the data coherency maintaining circuit in FIG. 1 to late selection synchronous pipeline type semiconductor memory devices in which two or more memory banks or chips are incorporated into a single chip. The late selection synchronous pipeline memory has, for example as shown in FIG. 2, two cache memory chips 2, 4 combined in one chip and a multiplexer 6 for selecting one of the outputs of the cache memory chips 2, 4 in response to the selection signal SAS. It is difficult to realize a bypass operation by applying the data coherency maintaining circuit shown in FIG. 1 to the late selection synchronous pipeline type memory device in FIG. 2. The reason is that the conventional data coherency maintaining circuit in FIG. 1 is designed to perform the bypass operation for a single bank or memory chip.
The reason why the late selection synchronous pipeline memory devices as shown in FIG. 2 employ the scheme in which two separate memory chips are combined into a single chip is to reduce the board area in the system or the loading burden. The semiconductor memory device having the scheme as shown in FIG. 2 is designed to perform the late write operation in the timing view as shown in FIG. 3. It is desired that the data coherency maintaining method or the structure in the data coherency maintaining circuit is improved to be applicable to the late selection synchronous pipeline type memory devices.
As described, the conventional data coherency maintaining circuit is suitable for a single memory chip, but not for a semiconductor memory device of the late select synchronous pipeline type. Accordingly, a need exists for a data coherency maintaining method and system which is suitable for a semiconductor memory device having the scheme in which two or more memory banks or chips are packaged into one chip.
Accordingly, it is an object of the present invention to provide a late write type semiconductor memory device by which the aforementioned problems are solved.
It is another object of the present invention to provide a semiconductor memory device having a data coherency maintaining circuit that is appropriate for a semiconductor memory device having a scheme in which at least two memory banks or chips are packaged in a single chip.
It is still another object to provide a data coherency maintaining method and circuit which is appropriate to a late select synchronous pipeline type semiconductor memory device that is operated by a late select synchronous pipeline type input/output protocol and has at least two memory chips in which each of separate read paths is connected to a common input/output port.
It is still another object to provide a static random access memory with which data access operation is performed with various bypass operation in late select synchronous pipeline type semiconductor devices operating at high speed.
To accomplish the aforementioned and other objects, the present invention provides a method of maintaining data coherency in a semiconductor memory device that is operated according to a late select synchronous pipeline type input/output protocol and has at least two memory chip blocks each of which has a read path connected to a common input/output port. The method of maintaining data coherency includes the steps of generating first and second bypass summation signals by utilizing a chip block select address signal inputted in a latest write operation and comparison signals obtained from comparison between a latest write address and a current read address; and generating first and second bypass control signals having logic values contrary to each other by utilizing the first and second bypass summation signals and an internal clock signal, wherein a bypass operation is performed in one of read paths associated with the at least two memory chip blocks and a normal read operation is performed through other read paths when all of the comparison signals are same.
According to another aspect of the present invention, there is provided a data coherency maintaining circuit for a semiconductor memory device that is operated according to a late select synchronous pipeline type input/output protocol and has at least first and second memory chip blocks each of which has a read path connected to a common input/output port. The data coherency maintaining circuit includes a bypass summator for generating first and second bypass summation signals by utilizing a chip block select address signal and comparison signals obtained from comparison between a write address inputted in a latest write operation and a current read address; a bypass control part for generating first and second bypass control signals and first and second core control signals having logic values contrary to logic values of the first and second bypass signals, respectively, by utilizing the first and second bypass summation signals and an internal clock signal; a first switching part for shutting off a read path of the first memory chip block in response to a disable state of the first core control signal and bypassing write data stored in a data input register to a data output buffer in response to an enable state of the first bypass control signal; and a second switching part being operated contrary to an operation of the first switching part in a bypass operation such as transferring output data that is read from the second memory chip block to the data output buffer in response to an enable state of the second core control signal and preventing bypass of the write data stored in the data input register in response to a disable state of the second bypass control signal.
The present invention has advantages such that a bypass operation for maintaining data coherency is effectively performed in a semiconductor memory device having a scheme in which two or more banks or memory chips are combined into one chip.

Method of maintaining data coherency in late-select synchronous pipeline type semiconductor memory device and data coherency maintaining circuit therefor


Apparatus and associated methods relate to ranging object(s) nearby an aircraft using triangulation. A light projector mounted at a projector location on the aircraft projects pulses of polarized light onto the scene external to the aircraft. The projected pulses of polarized light are polarized in a first polarization state. A camera mounted at a camera location on the aircraft has a shutter synchronized to the projector output pulse and receives a portion of the projected pulses of polarized light reflected by the object(s) in the scene and polarized at a second polarization state orthogonal to the first polarization state. Location(s) and/or range(s) of the object(s) is calculated, based on the projector location, the camera location, and pixel location(s) upon which the portion of light is imaged.

Each year, significant time and money are lost due to commercial aircraft accidents and incidents during ground operations, of which significant portions occur during taxiing maneuvers. During ground operations, aircraft share the taxiways with other aircraft, fuel vehicles, baggage carrying trains, mobile stairways and many other objects. Aircrafts often taxi to and/or from fixed buildings and other fixed objects. Should an aircraft collide with any of these objects, the aircraft must be repaired and recertified as capable of safe operation. The costs of repair and recertification, as well as the lost opportunity costs associated with the aircraft being unavailable for use can be very expensive.
Pilots are located in a central cockpit where they are well positioned to observe objects that are directly in front of the cabin of the aircraft. Wings extend laterally from the cabin in both directions. Some commercial and some military aircraft have large wingspans, and so the wings on these aircraft laterally extend a great distance from the cabin and are thus positioned behind and out of the field of view of the cabin. Some commercial and some military aircraft have engines that hang below the wings of the aircraft. Pilots, positioned in the cabin, can have difficulty knowing the risk of collisions between the wingtips and/or engines and other objects external to the aircraft. An aircraft on-ground collision alerting system would be useful to survey the area forward and/or aft of the tail, wingtips and/or engines, to detect obstructions in a potential collision path, and to provide visual and audible alerts to the cockpit.
Optical systems that direct light to objects external to the aircraft and then detect light reflected by such external objects can use triangulation to determine a range to or location of these external objects. Various methods can be used to direct such light to the objects external to the aircraft. These methods for directing light can have some stray light misdirected from the intended direction. This stray light also can be reflected by objects external to the aircraft, resulting in detection. Because the range to or location of the external objects is based on the intended direction of the projected beam, detection of light corresponding to the stray portion of the projected beam can result in erroneous range and/or location computation. Because the stray light typically has a very low amplitude, compared with the light directed in the intended direction, reflections by specular objects can be more problematic in that specular objects produce reflections having amplitudes higher that those caused by Lambertian objects. Thus, reducing or eliminating light reflected by specular objects can improve such optical ranging systems.

Method and system for aircraft taxi strike alerting


A predictive analysis generates a predictive model (Padj(Y|X)) based on two separate pieces of information,                a set of original training data (Dorig), and        a “true” distribution of indicators (Ptrue(X)).

Predictive modeling is the process by which a model is created or chosen to try to best predict the probability of an outcome. Generally, the model is chosen on the basis of detection theory to try to guess the probability of an outcome given a set amount of input data (for example: given an e-mail determining how likely that it is spam). Thus, given a predefined set of features (indicators) X, predictive modeling aims at predicting the probability P(Y|X) of a specific outcome Y. This task can be seen as a search for a "true" probability distribution P(Y|X), which, however, is not directly observable. Rather, one has to try to generate an optimal distribution which should be chosen in such a way that the risk of false prediction over an underlying distribution P(X) of features X is minimized. As a consequence, achieving good predictions for combinations of features X that appear frequently in the application area should be given high attention, while combinations that are expected to occur very rarely can be ignored.
In reality, neither the "true" probability distribution P(Y|X) nor the "true" distribution of features P(X) are completely known. Rather, they are approximated based on a training set of examples. The underlying assumption is that the "true" distributions P(X), P(Y|X) will behave just like the ones of the training examples. This is, however, often not the case. Moreover, the training set of examples may be noisy; in this case, adapting the model perfectly to the training data would lead to "over-fitting" and would yield a model that does not accurately reflect the "true" distributions P(X), P(Y|X). On the other hand, it may be known beforehand that the "true" distribution of features P(X) differs from the distribution of the training data in an actual application domain. If, for example, a model predicting the spread of a given disease is to be generated, the training data may be erroneous since only a small fraction of the people testing positive may have been identified while it is known that the actual percentage is much higher. In this case, the distribution of the positive samples in the training data does not reflect the "true" distribution of the contagioned people.
If it is known that the training data exhibit a different distribution than the actual real-world data, this knowledge can be used to adapt the process of finding an optimal prediction model. Specifically, algorithms have been developed which are able to take a given distribution P(X) or P(Y) into account and combine it with the training data. The result is a model that obeys the constraints imposed by P(X) or by P(Y) and still approximates the training data as well as possible.
In the case of a given distribution P(Y) of labels Y, this may be achieved using a cost sensitive classifier, as described in US 2008/0065572 A1. Such classifiers are supported by most state-of-the-art predictive analytics tools, such as IBM® SPSS® software or IBM® INFOSPHERE® WAREHOUSE (IBM, INFOSPHERE, and SPSS are trademarks of International Business Machines Corporation in the United States, other countries, or both).
In the case of a given distribution P(X) of indicators X, this may be achieved by rejection sampling or by using example weights, as described in "Cost-Sensitive Learning by Cost-Proportionate Example Weighting", by B. Zadrozny et al., Proceedings of the Third IEEE International Conference on Data Mining (2003), p. 435 ff. Such methods are only supported for some algorithms on a product level; however, most algorithms can be extended accordingly.
All of these methods assume that the information about the actual "true" distribution P(X) or P(Y) is static and that it is known before the model training process starts. However, it is often desirable to be able to apply a single model to a variety of situations with different underlying "true" distributions P(X). Furthermore, an analyst would often like to interactively explore the consequences of different assumptions about a distribution P(X) of indicators X in terms of a what-if analysis. Using a single, global model in all of these situations would have severe disadvantages:                For one thing, the model would probably not be optimal in the sense of structural risk, as some cases may occur much more often in reality than in the training set and therefore should be given a higher attention than others.        Moreover, the model would probably be quite complex, even though in the application area only a small portion of the model may be relevant.
These problems could be solved by building a new model for each application area. This approach, however, requires a severe computational effort and, in the majority of cases, involves prohibitively long response times which renders the task non-interactive and does not allow the user to interactively try out different assumptions about the "true" distribution P(X). Also, it poses a security risk organizationally, since everybody who employs the model and adapts it to a new application would need to obtain access to the actual source data.
Thus, there is a need for a predictive modeling method which circumvents these problems.

Abstract: The predictive analysis begins by generating a base model distribution (Pgen(Y|X)) from the original training data set (Dorig) containing tuples (x,y) of indicators (x) and corresponding labels (y). Using the “true” distribution (Ptrue(X)) of indicators, a random data set (D′) of indicator records (x) is generated reflecting this “true” distribution (Ptrue(X)). Subsequently, the base model (Pgen(Y|X)) is applied to said random data set (D′), thus assigning a label (y) or a distribution of labels to each indicator record (x) in said random data set (D′) and generating an adjusted training set (Dadj). Finally, an adjusted predictive model (Padj(Y|X)) is trained based on said adjusted training set (Dadj).


A circuit for encoding a data stream is described. The circuit comprises a non-zero count circuit coupled to receive the data stream and output a count of non-zero coefficients of a block of data of the data stream; a trailing ones detection circuit coupled to receive the data stream and output a number of trailing ones of the block of data; and a memory coupled to the non-zero count circuit and the trailing ones detection circuit and storing encoded data values, the memory outputting an encoded data value for a non-zero coefficient of a block of data based upon the count of non-zero coefficients and the number of trailing ones for the block of data. A method of encoding a data stream is disclosed.

Receptors in the human eye are only capable of detecting light having wavelengths from 400 nm to 700 nm. These receptors are called cones and are of three different types, including one for red light, one for green light and one for blue light. If a single wavelength of light is observed, the relative responses of these three receptors allow us to discern what we call the color of the light. This phenomenon is extremely useful because it enables generating a range of colors by simply adding together various proportions of light from just three different wavelengths. The process, known as additive color matching, is utilized in color television systems. A resulting image to be displayed is broken down into an array of picture elements or pixels to be displayed.
Generally, each pixel displays a proportion of red, green or blue depending on the signals driven to the display. The representation of an image in red, green and blue is commonly referred to as RGB. However, transmitting or storing these RGB color components requires significant bandwidth. Accordingly, luminance and color difference coding is often used to reduce the bandwidth of an image to be displayed. For example, the YUV format contains a Y portion representing a luminance component (also known as Luma) associated with brightness and U and V portions representing chrominance components (also know as Chroma 1 and Chroma 2) associated with color. In addition to reducing bandwidth, the YUV format models human perception of color more closely than the standard RGB format.
As digital circuits become more prominent, more systems continue to migrate from analog systems to digital systems. However, as the bandwidth requirements for digital systems continue to increase, integrated circuits have a more difficult time processing the data. For example, analog television transmission is currently being replaced by high definition television (HDTV). Even with the reduced bandwidth provided by the YUV format, the HDTV format has significant data requirements. An HDTV image may have 1920×1080 pixels and may use six times the bandwidth of traditional standard-definition TV. Therefore, it is a challenge to economically distribute the new HDTV programming over existing satellite, cable, and IPTV networks.
Video compression is often used to reduce the amount of data to be transmitted in a data transmission network, such as a television broadcast network. One main video compression scheme may be found in the Motion Picture Experts Group (MPEG) standards. Video compression using one or more MPEG standards is currently implemented in a variety of video imaging devices, such as digital televisions, set-top boxes, digital satellite systems, HDTV decoders, DVD players, video conferences and web phones, for example. The MPEG standards employ a function called the Discrete Cosine Transform (DCT) that takes a square of pixel blocks, and removes redundant information that is imperceptible to the viewer. The received compressed data is then decoded using the Inverse Discrete Cosine Transform (IDCT) function.
A device designed to compress high definition advanced video coding (HD AVC) in real time may demand more than 500 billion operations per second. While conventional central processing units (CPUs) are extremely powerful, their architecture is not well suited to all video processing tasks. For example, block-based and pixel-level processing tasks require many compute cycles and are also very data-flow intensive. Therefore, implementing video processing in conventional CPUs requires complex register pipelines with fast memory access. Similarly, a programmable digital signal processor (DSP) is often limited by the number of instruction issues per cycle, the level of pipelining in the execution unit, and the maximum data width to fully feed the execution units. Video quality is often compromised as a result of the limited cycles available per task in a programmable DSP. Recursive algorithms such as infinite impulse response (IIR) filtering, variable-length coding (VLC) in the MPEG standards, and context-adaptive variable length coding (CAVLC) in the MPEG AVC standard are particularly inefficient when mapped to DSPs. That is, data recursion prevents inductive logic programming (ILP) from being used effectively. Finally, a DSP may not be suitable to incorporate a decoder and an encoder solution as required in some full duplexing implementations.
Accordingly, there is a need for an improved circuit for and method of a method of encoding a data stream.

Circuit for and method of encoding a data stream


A plasma display device is disclosed. The plasma display device has a first panel and a second panel parallel to each other. A dielectric layer is formed on the second panel, a plurality of barrier ribs are formed on the dielectric layer, and a plurality of buffer layers are formed opposite to the barrier ribs. The buffer layers have a first softening temperature, the barrier ribs have a second softening temperature, and the first softening temperature is lower than the second softening temperature. The buffer layers can be deformed and compressed at a temperature higher than the first softening temperature during a process for sealing the first and second panels, so as to unify heights of the barrier ribs.

1. Field of the Invention
The invention relates to a plasma display device, and more particularly to a plasma display device having uniform barrier ribs.
2. Description of the Related Art
Recently, flat panel displays, such as liquid crystal displays and plasma displays, become to replace traditional cathode ray tube displays. The plasma display is a flat panel displaying images by discharging gas, with lighter weight and thinner volume, a large viewable area, and no viewing-angle restriction.
The plasma display includes a front panel and a back panel, and a plurality of barrier ribs are formed on the back panel. These barrier ribs in the plasma display can be formed by a screen-printing method and/or a sandblasting method. These barrier ribs with different heights cause a serious problem. For example, a height difference between the highest and lowest barrier ribs is about 10 xcexcm, so that the highest barrier rib is easily cracked or broken because of the pressure formed during the assembly process of the front panel to the back panel.
A discharge display device is disclosed in U.S. Pat. No. 5,754,003. Referring to FIG. 6, a plurality of height adjusting layers 32 are formed on the front panel 101. These height adjusting layers 32 are corresponded with these barrier ribs 103. Each height adjusting layer 32 is made of a material having a low softening temperature. However, it is not easy to control the amount of the height adjusting layers 32, and some of the height adjusting layers 32 may overflow onto the phosphor layer 104 on the rear panel 102 at high temperatures, causing defects of the display.
To solve the above problems, it is an object of the present invention to provide a plasma display device to solve the problem of the height difference among the barrier ribs.
According to the object mentioned above, the present invention provides a plasma display device having a first panel and a second panel parallel to each other. A first dielectric layer is formed on the second panel, a plurality of barrier ribs are formed on the first dielectric layer, and a plurality of buffer layers are formed opposite to the barrier ribs. The buffer layers have a first softening temperature, the barrier ribs have a second softening temperature, and the first softening temperature is lower than the second softening temperature. The buffer layers can be deformed and compressed at a temperature higher than the first softening temperature during a process for sealing the first and second panels, so as to unify heights of the barrier ribs.
Each buffer layer can be disposed in the middle of each barrier rib or between the first dielectric layer and each barrier rib. Moreover, the width of each buffer layer is preferably not larger than the width of each barrier rib. Thus, the buffer layer has enough space to expand during a sealing process of the first panel and the second panel. The buffer layer will not easily overflow onto the phosphor layer of the plasma display device to produce defects.
Furthermore, the difference between the first softening temperature of the buffer layer and the second softening temperature of the barrier rib is about 20xc2x0 C. to 100xc2x0 C., and preferably about 20xc2x0 C. to 30xc2x0 C.
The material of the buffer layer is a mixture of oxide, such as a mixture of Bi2O3, Li2O, Na2O, CaO, . . . etc.
According to the present invention, the buffer layers can be formed on the first panel. A second dielectric layer is further formed on the first panel to cover the buffer layers. The dielectric layer includes a plurality of concave portions, and positions of the concave portions are corresponded with positions of the buffer layers. A protecting layer can be formed on the second dielectric layer.
According to the present invention, the buffer layers can be formed above the second dielectric layer, and the protecting layer can be formed to cover the buffer layers.


A multi-gate semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first gate stack having first spacers formed on opposing sides thereof. The second semiconductor structure includes a second gate stack having second spacers formed on opposing sides thereof. First elevated source/drain regions abut the first spacers to define a first effective S/D distance between the first gate stack and the first elevated source/drain regions. Second elevated source/drain regions abut the second spacers to define a second effective S/D distance between the second gate stack and the second elevated source/drain regions. The second effective S/D distance is equal to the first effective S/D distance.

The present invention relates to semiconductor device fabrication, and in particular, to elevated source/drain (ESD) semiconductor devices.
As semiconductor devices continue to be scaled down, various methods have been relied upon for preserving the channel length. A minimum channel length (Lmin) may be determined, which indicates the minimum length at which a channel may be formed before observing short-channel effects in the semiconductor device. The junction depth of the semiconductor device affects the minimum channel length. Thus, reducing the junction depth may allow for reducing the channel length while mitigating short-channel effects. However, reducing the junction depth may lead to an increase in intrinsic parasitic series resistances and undesirable junction leakage currents.
Conventional methods have relied upon elevating the source/drain regions to counter the effects that occur when reducing the junction depths. The elevated source/drain regions are typically formed by selectively growing an epitaxial (epi) structure over the source and drain regions. The epi structure forms an effective junction depth that is reduced according to the extent of the elevation without realizing an increase of intrinsic parasitic series resistances and undesirable junction leakage currents.
When fabricating semiconductor devices having two different doped channel regions (e.g., a p-type doped channel region and an n-type doped channel region) on a common substrate layer, separate epi growth processes (i.e., a dual epi process) must be used. The dual epi process, however, forms spacers on a first gate stack (a p-type semiconductor gate stack) having a greater thickness than spacers on a second gate stack (an n-type semiconductor gate stack). The thicker spacers cause the corresponding epi structure (i.e., the elevated S/D region) to be formed further away from the gate stack. The increased distance (i.e., the effective S/D distance) between the elevated S/D region and the corresponding gate stack inhibits doped ions of the epi structures from diffusing beneath the gate stack.

Dual epitaxial process including spacer adjustment


A hydraulic assembly for driving and controlling small hydraulic units, such as hydraulic cylinders of a brake and/or clutch of a forestry winch, is disclosed. The hydraulic assembly includes a means for establishing and also maintaining a pre-determined pressure of a hydraulic media. The hydraulic assembly is characterized by as low as possible hydraulic loss. Also, a quantity of hydraulic media required for a regular operation and maintaining the pressure within the hydraulic assembly is as low as possible.

The invention refers to mechanical engineering, namely to fluid pressure actuators and hydraulics, namely to fluid-pressure actuators. On the other hand the invention may also belong to performing operations, in particular to hydraulic control devices for rope or chain winding mechanisms of winches.
The purpose of the invention is to create a hydraulic assembly, which would enable driving and controlling of small hydraulic units, in particular hydraulic cylinders for controlling of brake and clutch of a forestry winch, with means to establish and also to maintain a pre-determined pressure of a hydraulic media within the hydraulic circuit, wherein at the same time the hydraulic loss should be as low as possible and the quantity of said hydraulic media required for regular operation and maintaining the pressure within the assembly should also be as low as possible.
As known to those skilled in the art, hydraulic assemblies are used also for the purposes of controlling and driving in the field of forestry winches. A winding drum is driven by means of the internal combustion engine of the belonging tractor via appropriate shaft and a chain reduction gear, and includes a clutch and a brake, which operate alternatively. When the brake is deactivated, the clutch is activated, which then enables turning and driving of a winding drum, upon which by deactivation of said clutch the brake is automatically activated in order to prevent said drum from any further turning. Controlling of said clutch and brake may commonly also be performed by means of electric or any other control units, which is however not always feasible or is much more complicated, when the winch is used in situ, where relevant energy sources are limited or not available at all. Since appropriate hydraulic assembly may no doubt be surmounted to such winch, the pump of which may easily be driven by means of each disposable tractor engine, such appliances for controlling of clutch and brake have already been realized also in the practical use. Appropriate hydraulic circuit comprises a pump, which charges the hydraulic media via appropriately arranged valves and depending on position and adjustment thereof either towards the brake controlling cylinder or a clutch controlling cylinder, by which the residual hydraulic media is then returned back to reservoir i.e. towards said pump. As known to the applicant, a geared pump has exclusively been used for such purposes. Such assembly may no doubt establish a required pressure of the hydraulic media within the hydraulic circuit, but the pump must be able to ensure a sufficient quantity of the media in a required time for the purposes of supplying each cylinder and in order to enable sufficiently short shifting time of control units of the clutch and brake, so that the pumping capacity must be relatively high. Accordingly, the pump must assure sufficiently high capacity all the time, by which the hydraulic loss due to leakage is relatively high, which then in correlation with high pressure results in heating or even overheating of the hydraulic system, which has essential impact to decreasing of quality of hydraulic media and wearing of sealing members, by which the risk of disturbances or damages during operation is then essentially increased. In addition to that, such assembly is pretty bulky when bearing in mind its overall dimensions, not only due to complex and bulky valves included therein, but also due to huge quantity of the hydraulic media and bulky reservoir for storage thereof. It is also obvious, that a hydraulic assembly containing such quantity of hydraulic fluid is not an environment-friendly one, especially when bearing in mind, that said damages may occur during operation in situ, e.g. in the forest or the like.
Various hydraulic circuits are described also in the patent literature, e.g. in FR 2.116.693, JP 58121306A, JP 60263710, JP63083405A, JP 2004176698 or JP 2004360300A, which belong to various devices and are all very complicated and include numerous components, so that the applicant is of opinion, that none of them solves the previously mentioned technical problem, which is however solved by the proposed invention.
A hydraulic assembly for driving and controlling of small hydraulic units, especially of gearbox clutch is described in DE 30 04 067 A1. Such assembly should comprise a reservoir for hydraulic media, a pump intended for producing a required pressure of hydraulic media, as well as a control unit consisting of at least one control valve and at least one hydraulic cylinder. A hydraulic circuit of the hydraulic assembly should include a piston pump, which is at the one hand connected with said control unit and reservoir via a non-return valve, which allows flowing in a direction away from the pump and not in the opposite direction, and on the other hand either via a switching valve with integrated non-return valve, which allows flowing towards the pump but not also in the opposite direction, in a serial manner into a hydraulic circuit together with a pressure storage tank and the non-return valve, or by exceeding a pre-defined pressure by means of automatically shifting of the switching value into a hydraulic circuit, which includes said pump, a switching valve, a control unit and said non-return valve, which are hydraulically interconnected in a serial manner. Such an assembly should enable generating servomechanism power in a sufficient quantity to control all available controlled units.

Hydraulic assembly for driving and controlling small hydraulic units

Tajfun Planina Proizvodnja Strojev, D.O.O.


A cardiovascular surgical clamp used for retaining, identifying and positioning surgical wire for patients on a sterile field without wire injury. Opposing members with opposing recessed surfaces and back end portions are provided having removable compressible inserts with large flat matching surface areas inserted into the recesses of opposing members. The opposing members have spring/s located between them for driving them together and for manually opening them apart and have hinges formed on projecting struts for allowing simultaneous contact of the large flat matching surface areas of the removable compressible inserts for frictional engagement of wire without injury. The projecting struts of the opposing members provide guide wire surfaces proximate where hinges are formed for guiding wire there through. The opposing members and the projecting struts are moved from a closed to open position and back by compression or release of back end portions of the opposing members.

1. Field of the Invention
This present invention relates generally to a clamp device used in the field of cardiovascular procedures, which includes vessels of the coronary arteries and heart, for retaining, identifying and locating surgical wire, individual wires and or coils of wire without damage to the wire and wires for patients on a sterile field and providing guiding surfaces for moving a wire or wires there through in a surgical procedure without injury to the wire or wires being used in the patient.
2. Background of the Invention
In cardiovascular procedures, such as coronary artery procedures, the patient is laid out under a sterile drape and a sheath is inserted into the patient through a round opening in the sterile drape at a location such as the lower right or left groin area of the patient. During the procedure a guide wire is inserted through a sheath into the patient and has its proximal end moved to a location within the body of the patient to an area for the particular treatment. This wire or wires is used as a control delivery system for moving treatment devices, such as a balloon catheter, over the wire to the locations in the body of the patient and the distal end of the guide wire remains outside the patient's body on the sterile drape. Many times the guide wire must be moved back and forth into and out of the patient to find the specific location in the patient's body where the treatment is to occur. This whole length of guide wire must be retained on the sterile drape at all times to keep it sterile during the procedure. This means the distal end of the guide wire may have to be coiled and secured for retention on the sterile drape and maintained in an identified and fixed location to keep the proximal end of the guide wire in its proper location in the patient. However any retention device for the guide wires must not crimp or put a bend in the wire less the wire be rendered useless and have to be replaced which is not desired in a surgical procedure.
In some cases it is necessary to run more than one guide wire into the same sheath located in a patient because the second wire must be advanced to a secondary blood vessel which will receive treatment in the same surgical procedure as the primary vessel. In such a case it is important both to identify the location of the guide wires in the primary and secondary vessel which have received a primary and secondary wire inserted into their respective locations in the patient based on the distal ends outside the patient. This means that the distal end of the guide wires have to be identified as the primary wire or the secondary wire so that the procedure such as a balloon catheter intended for primary blockage in a blood vessel can receive the proper catheter and the secondary vessel can receive the proper balloon catheter for it or just be available for a different purpose. The distal end of each of these guide wires must be identified to prevent errors as to which location in the patient the proximal end of the wire is located, because in many cases the wires are the same gauge and look the same. Also the distance of the wires and the location of their proximal ends in the patient need to be determined as well for the proper wire for delivery of the surgical devices being implanted by distribution over the wires to be achieved. If the distal end of the wire or wires are fixed at a location on the surgical drape after the proximal end is properly located in the patient, then the proximal end of the wire will be in the same location in the patient if the clamp is in a fixed position on the sterile drape, which is another reason for locating the distal end of the wire in a fixed location on the sterile drape.
In all these cases, the wire or wires must be easy to release for manipulation both into and out of the patient and must provide reserve lengths of wire if that becomes necessary for running the wire or wires and the reserves of wire into the patient. The reserves of wire or wires must be coiled and stored on the sterile field. Also the wires must be retained in such way that they are easy to release from a coil or from a fixed position and then moved through guiding devices to prevent bending or crimping the wires in the process of moving them both into the patient and back outward of the patient for either relocation or adjustment of their location in the patient. This process of going from a fixed position coil of wire being secured in a clamp and then into a guiding device for threading the wire or wires there through has created clutter on the sterile field and has required additional time for the surgical team to move from the release of the coiled wires to its insertion through a guiding device for further insertion into a patient.

Vascular surgical clamp for holding and guiding guide wire on a sterile field


The present invention pertains to a voltage reference circuit based on temperature compensation, comprising positive and negative temperature coefficient generating units, temperature compensation circuit, image circuit and voltage divider. In this circuit, Item T is compensated with Item T, and Item T ln(T) is compensated by Item T in (T), which features a well-targeted compensation performance. The circuit outputs a reference voltage with zero temperature coefficient, which is independent to T and T ln (T). The output voltage value could be defined by adjusting the ratio of resistance in voltage divider. The invention provides a voltage reference circuit featuring good compensation, zero temperature coefficient and adjustable output voltage. The invention has a better compensation than the conventional one and a fixed output voltage, and it totally eliminates the temperature coefficient. The invention has wide application in analog IC and digital/analog mixed IC.

A voltage reference circuit with low temperature coefficient is an essential part for analog IC. The circuit generates low temperature coefficient voltage by weighted summing of positive and negative temperature coefficient voltages to reduce variation of the reference voltage with temperature. The conventional voltage reference is generated by weighted summing of difference in PN junction voltages of bipolar transistors with positive and negative temperature coefficients, as shown in FIG. 1 (the temperature coefficient of resistor is neglected), and operational amplifier AO enables voltages at g0 and f0) to be equal, as ICQ10R30=ICQ20R20, then:
                              V          REF                =                              V                          BE                              Q                                                                                10                                              +                      Δ                                                                                V                                  BE                                                            Q                                                                                10                                        ,                                          Q                                                                                20                                                                                ·                                                R                  20                                                  R                  10                                                                                (        1        )
Where VBE is PN junction voltage of bipolar transistor Q10, and ΔVBEQ10,Q20 is the PN junction voltage difference between Q10 and Q20.
                              V          BE                =                                            V              T                                    ln                                                                                (                                                I                  C                                                  I                  S                                            )                                =                                    kT              q                                                  ln              (                                                I                  C                                                  b                  ·                                      T                    2.5                                    ·                                      ⅇ                                                                  -                                                  E                          g                                                                    kT                                                                                )                                                          (        2        )
Where k is Boltzmann constant, T is absolute temperature, q is the quantity of electron, IC is the collector current of bipolar transistor, b is a proportional coefficient and Eg is Si bandgap energy.
From Equation (2), the following could be derived:
                              Δ                                                                          V                          BE                                                Q                                                                                10                                ,                                  Q                                                                                20                                                                    =                                                            V                T                                                          ln                                                  (                                                            I                                              C                                                  Q                                                                                10                                                                                I                      S                                                        )                                                      -                                          V                T                                                          ln                                                  (                                                            I                                              C                                                  Q                                                                                20                                                                                n                        0                                                                                I                        S                                                                              )                                                              =                                                    V                T                                                          ln                                                  (                                                            n                      0                                                                                I                                                  C                                                      Q                                                                                10                                                                                I                                                  C                                                      Q                                                                                20                                                                                )                                                      =                                                            k                                                                                ln                                                              (                                                                        n                          0                                                                                R                            20                                                                                R                            30                                                                                )                                                                      q                            ·              T                                                          (        3        )
Where k is Boltzmann constant, T is absolute temperature, q is the quantity of electron, n0 is the ratio of the number of bipolar transistor Q20 to Q10.
From Equation (2) & (3), the following could be derived:
                                          V                          BE                              Q                                                                                10                                              =                                                    E                g                            q                        +                                          kT                q                                                          ln                                                  (                                      I                                          C                                              Q                                                                                10                                                                              )                                                      -                                                            2.5                                    k                                q                                          T                                                                                ln                                                  (                  T                  )                                                      -                                                            k                                                                                ln                                                              (                      b                      )                                                                      q                                          T                                                                                Where                            (        4        )                                                      I                          C                              Q                                                                                10                                              =                                                                      I                                      C                                          Q                                                                                20                                                                                R                  20                                                            R                30                                      =                                                                                Δ                                                                                V                                              BE                                                                              Q                                                                                10                                                    ,                                                      Q                                                                                20                                                                                R                    10                                                  ·                                                      R                    20                                                        R                    30                                                              =                                                                                kR                      20                                                                                ln                                                                    (                                                                              n                            0                                                                                R                              20                                                                                R                              30                                                                                )                                                                                qR                      10                                                                                R                      30                                                                      ·                T                                                                                Then          ,                                    (        5        )                                          V                      BE                          Q                                                                                10                                      =                                            E              g                        q                    +                                                    k                                                                                ln                  (                                                                                kR                        20                                                                                ln                                                                          (                                                                                n                              0                                                                                R                                20                                                                                R                                30                                                                                )                                                                                qbR                        10                                                                                R                        30                                                                              )                                            q                        ·            T                    -                                                                      1.5                                    k                                q                            ·              T                                                                                ln                                            (                T                )                                                                        (        6        )
From Equations (1),(3) and (6):
                              V          REF                =                                            E              g                        q                    +                                                    k                                                                                ln                  (                                                                                kR                            20                                                                                (                                                                                n                                0                                                                                R                                  20                                                                                R                                  30                                                                                )                                                                                R                            20                                                                                R                            10                                                                                ln                                                                          (                                                                                n                              0                                                                                R                                20                                                                                R                                30                                                                                )                                                                                qbR                        10                                                                                R                        30                                                                              )                                            q                        ·            T                    -                                                                      1.5                                    k                                q                            ·              T                                                                                ln                                            (                T                )                                                                        (        7        )
It can be seen from Equations (3) and (6), ΔVBEQ10,Q20 is related to T, and VBEQ10 is not only relevant to T, but also to T ln(T). Therefore, when ΔVBEQ10,Q20 is added to VBEQ10, only T-related item can be used to compensate for T ln(T)-related item, as shown in Equation (7). For conventional voltage reference circuits, the reference voltage VREF is always associated to T and T ln(T), which means that the temperature coefficient of the reference voltage can never be fully eliminated. Temperature coefficient of the conventional voltage reference source using standard process technology is 40 ppm/° C., namely, in the temperature range from −40° C. to 85° C., variation of the reference voltage can be calculated from:40 ppm/° C.×[85° C.−(−40° C.)]×100%=0.5% .
Therefore, a voltage reference circuit with zero-temperature coefficient based on temperature compensation is required to eliminate effects of T and T ln(T) and solve the problem of inability of temperature coefficient elimination due to the dependence of output reference voltage from the conventional voltage reference source on T and T ln(T).
Contents of Invention
The object of the present invention is to eliminate effects of T and T ln(T) and generate reference voltage with zero-temperature coefficient based on temperature compensation, so as to solve the problem of inability of temperature coefficient elimination due to the dependence of output reference voltage from the conventional voltage reference source on T and T ln(T).
The present invention accomplishes the object in the following way:
The present invention presents a voltage reference circuit based on temperature compensation, which comprises a positive temperature coefficient generating unit, a negative temperature coefficient generating unit, temperature compensaion circuit, mirror circuit and voltage divider circuit;
The positive temperature coefficient generating unit generates a positive temperature coefficient voltage with Item T ln (T), and outputs a positive temperature coefficient current with both Items T and T In (T);
The negative temperature coefficient generating unit generates positive temperature coefficient voltage with both Items T and T ln (T), and outputs positive temperature coefficient current with Item T;
The temperature compensation circuit converts the positive temperature coefficient current with both Items T and T ln (T) into positive temperature coefficient voltage with both Items T and T ln (T), and compensates the negative temperature coefficient voltage with both Items T and T ln (T) from negative temperature coefficient generating unit. The negative temperature coefficient generating unit, together with temperature compensation circuit, generates reference voltage with zero temperature coefficient;
Where T is absolute temperature;
The mirror circuit multiplies output current from the negative temperature coefficient generating unit by a factor of m, which is then input to the positive temperature coefficient generating unit;
The voltage divider adjusts output voltage and defines operating voltage of both positive and negative temperature coefficient generating units.
Furthermore, the temperature compensation circuit comprises resistor R5, the positive temperature coefficient generating unit comprises operational amplifier A1, bipolar transistors Q3 and Q4, resistors R6 and R4, where the positive input of A1 is connected to the base of Q4, while the negative input of A1 is connected to the collector of Q4, and the output of A1 is connected to the emitter of Q4, one end of R6 is connected to the negative input of A1 and the collector of Q4, and the other end of R6 is grounded, between emitters of both Q4 and Q3 is R4, the collector of Q3 is connected to mirror circuit, and the base of Q3 is connected to the base of Q4;
Furthermore, the negative temperature coefficient generating unit comprises operational amplifier A2, bipolar transistors Q1 and Q2, and resistors R1, R2 and R3, where the emitter of Q1 is connected to the positive input of A2, which is connected to R3, the emitter of Q2 is connected via R1 with the negative input of A2, which is connected to R2, the output of A2 is connected to resistor R5, of which the other end is connected with R2 and R3, the other end of R2 is connected to the emitter of Q3, collectors of both Q1 and Q2 are connected with mirror circuit, and the output of A2 is connected to voltage divider;
Furthermore, the mirror circuit comprises the first NMOS transistor M1 and the second NMOS transistor M2, of which the sources are grounded, the gates of both M1 and M2 are connected together, the gate of M2 is connected to its drain, the drain of Ml is connected to the collector of Q3, and the gate of M2 is connected to collectors of both Q1 and Q2;
Furthermore, the voltage divider comprises resistors R7 and R8, where R8 is connected with the output of operational amplifier A2, while the other end of R8 is connected with R7 and bases of Q1, Q2, Q3 and Q4, the other end of R7 is connected to the sources of M1 and M2, and the connection nodes of operational amplifier A2 with R5 and R8 are the output ports, Vo, of the voltage reference circuit;
Furthermore, the output reference voltage value is determined by the ratio of R7 to R8: Vo=(Eg/q)·(1+R7/R8) where (Eg/q) is Si bandgap voltage. Different output reference voltages can be obtained by adjusting the ratio of R7 to R8.
Furthermore, R4 and R5 has the following relation:
                    R        5                    R        4              =          3      2        ;
Furthermore, the negative temperature coefficient generating unit comprises at least one bipolar transistor Q1 and at least one bipolar transistor Q2, and the ratio of the number of Q2 to Q1 is n. The positive temperature coefficient generating unit comprises at least one bipolar transistor Q3 and at least one bipolar transistor Q4, and the ratio of the number of Q4 to Q3 is p. The mirror circuit comprises at least one first NMOS transistor M1 and one second NMOS transistor M2, where n>1 and p>1.
Compared with the conventional voltage reference source, the voltage reference circuit based on temperature compensation in this invention features:
1 . The conventional voltage reference uses Item T to compensate Item T ln(T), while the present invention uses Item T to compensate Items T, and T ln (T) to compensate T ln (T), which makes the compensation more specific.
2 . In the conventional voltage reference circuit, Item T ln(T) is compensated by Item T, so the output reference voltage is ralated to both T and T ln(T), which makes it impossible to completely eliminate temperature coefficient (about 40 ppm/° C.). The present invention outputs a reference voltage independent to T and T ln(T), so, it is capable of delivering a reference voltage with zero-temperature coefficient.
3 . The output voltage range of the conventional voltage reference circuit is the bandgap voltage of silicon, therefore, the output voltage is a fixed value. The present invenion offers a voltage reference Vo=(Eg/q)·(1+R7/R8), which is defined flexibly by adjusting the ratio of resistor R7 to R8, so the circuit is capable of delivering any output voltage value within a certain range.
To sum up, the present invention has the advantages of well-targeted compensation, zero-temperature coefficient and adjustable output voltage values.
Other advantages, objects and features of the present invention will be elaborated in the subsequent embodiments, and may be best understood by referring to the following description of the presently preferred embodiments, together with the accompanying drawings.

Voltage reference circuit based on temperature compensation

China Electronic Technology Corporation, 24th Research Institute


An improved boom adapted for use in or with a headset is disclosed. The boom generally comprises a voice tube having a first entry aperture, a light tube, and a noise reducer. The noise reducer is composed at least partially of a porous plastic material and partially or fully covers the voice tube, the noise canceling tube, and/or the light tube.

1. Technical Field
The present invention relates generally to communication apparatuses, and more particularly to headsets and booms adapted for use with or in headsets.
2. Description of Related Art
Traditional headsets have employed a design in which a microphone is extended from a boom and positioned close to a sound source, such as a user""s mouth, in an attempt to achieve sound reception clarity. By positioning the microphone in this manner, effective noise cancellation, which distinguishes between sound waves from a desired sound source versus background noise, may more easily be accomplished than if the microphone were positioned at a greater distance from the sound source.
To achieve noise cancellation, two sound ports are used, with one port facing the sound source and a second port facing away from the sound source. A number of issued patents show prior art relating to noise cancellation.
Increasing proximity of the microphone to the sound source, however, has required increasing or extending the length of the boom, which can lead to an increase the overall weight of the boom. This added weight can be undesirable from a user comfort perspective. In addition, opaque coverings for booms have traditionally been required so as to conceal the aesthetically unpleasant wires and connections between the microphone and earpiece.
Wind and background noise interfere with the proper operation of traditional microphones. To keep wind and background noise from interfering with microphone operation, traditional headsets have used a fabric or foam material as a windsock to filter or reduce some of the noise. This material may not satisfy the aesthetic desires of the user and may not achieve all desired acoustic properties.
Some form of in-use indication has also been a desired feature in headsets. A method for accomplishing this indication is to place a small light source or LED near the end of the boom. This placement can lead to a crowded area if the microphone is also housed in or near the end of the boom. The LED also adds to the overall weight of the boom.
Manufacturing costs for a boom increases with increasing complexity of the boom. Traditional booms are manufactured by placing the microphone and/or LED near the end of the boom. This placement complicates the manufacturing process because more manufacturing steps are required to properly house the microphone and LED.
Therefore, what is desired is a boom and microphone for a headset that has improved acoustic, weight, manufacturing cost and/or aesthetic properties.
In an aspect of the invention, an improved communication apparatus is disclosed. The communication apparatus includes a voice tube having a first entry aperture, a light tube, and a noise reducer. The noise reducer is composed at least partially of a porous plastic material and partially or fully covers the voice tube, the noise canceling tube, and/or the light tube. In a further aspect of the invention, the communication apparatus is a boom adapted for use in a headset.
In another aspect of the invention, the communication apparatus includes a noise canceling tube having a second entry aperture. The second entry aperture may be staggered in relation to the first entry aperture to achieve desired noise cancellation properties.
In another aspect of the invention, the light tube is adapted to transmit light from an online indicator light source.
In a further aspect of the invention, the porous plastic material includes a thinned, concave area that points toward the light tube so as to increase exposure to the transmitted light. In one embodiment, the porous plastic material includes between about 30 percent and about 50 percent void volume.
The porous plastic material may include one or more localized acoustic dampening areas. The localized acoustic dampening areas may be thickened to achieve increased acoustic dampening properties or thinned to achieve decreased acoustic dampening properties. In an embodiment, the porous plastic material includes two localized acoustic dampening areas, each of which is thinned to between about 2 mm and about 3 mm.
As is evident, these are merely examples of various implementations, and numerous other variations of these implementations may also be employed. These and other features and advantages of the present invention will be presented in more detail in the following detailed description and the accompanying figures that illustrate by way of example the principles of embodiments of the invention.


A percutaneous drainage device for draining a fluid collection located under the skin of a patient is disclosed. The percutaneous drainage device includes a penetration component slidably engaged with a cannula. The penetration component has a piercing end adapted to penetrate tissue of a patient and introduce an open end of the cannula to a subcutaneous fluid collection site. The cannula may be held in place in the patient by an anchoring means. The cannula provides a passage through which a fluid collection may be drained from a patient. The cannula may be in fluid communication with a collection vessel, which collects fluid collection transported away from the subcutaneous fluid collection site.

Each year several million patients present to emergency rooms seeking medical assistance for skin and soft tissue infections. A majority of these infections are subcutaneous abscesses, which are confined accumulations or collections of pus and dead tissue below the skin. Patients presenting with this common skin condition usually experience pain and can also present with fever or chills.
The treatment of abscesses is one of the most commonly performed hospital procedures. Some abscesses are 'simple' or 'pointing' and are almost ready to burst through the skin. These abscesses can typically be treated in an outpatient setting with local anaesthetic via an incision and drainage procedure. After administration of a local anaesthetic, a small incision is made at the site to puncture the skin. Contents of the abscess can then escape by draining out through the incision, sometimes assisted by manual expression of the contents by a clinician. Contents of the abscess may project upward and outward when excised and clinicians typically use personal protective equipment to mitigate risk of self-contamination.
Abscesses which are extensively large, deep, or which have thick or non-homogenous contents can be more challenging to drain. Some can be drained using imaging guidance to place a needle, catheter or other suitable drain through the skin into the abscess to remove or drain the fluid collection. However, the drains most commonly inserted often become occluded with abscess contents and stop flowing before the entire contents have been cleared. The patient then requires surgery to open the abscess using a larger incision.
Presently, the majority of complex abscess cases presenting to hospitals are treated in theatre with surgery and under a general anaesthetic. Whilst surgical treatment generally resolves the problem of the abscess, it generates a series of new problems. Patients undergoing surgical abscess treatment typically require a one to two day hospital stay. They must be fasted prior to surgery and face the risks associated with administration of general anaesthesia. Surgical treatment of abscesses requires an incision that needs to be long and deep enough to allow access to the abscess cavity. Typically, the incision will extend across the entire diameter of the abscess and, consequently, scarring may become of concern to the patient. Further, the use of longitudinal force to penetrate skin and tissue to reach the abscess carries a risk of inadvertently puncturing underlying tissue structures.
Surgical treatment of abscesses is thus financially costly for the health care system and patient and also carries risks associated with surgery and administration of general anaesthesia.
Other medical procedures may similarly require access to a fluid collection site in the body of a patient to drain a fluid, which may be liquid or gas. At least some of these medical procedures share similar problems and risks to abscess drainage procedures.
Any discussion of documents, acts, materials, devices, articles or the like which has been included in the present specification is not to be taken as an admission that any or all of these matters form part of the prior art base or were common general knowledge in the field relevant to the present disclosure as it existed before the priority date of each of the appended claims.


The feeding of web-shaped wound packaging material (reels) and/or prefabricated blanks to high-performance packaging machines has hitherto required considerable manual involvement. Above all, the sometimes considerable dead weight of the packaging material has an adverse effect here. To allow a virtually full automatic feed of the packaging machines with packaging material, a conveyor track (31) leads to the individual consumption points at the packaging machines is arranged above the packaging machines. Individual reels (26, 27, 28) or blanks (82) stacked in cassettes (84) are transported along this conveyor track (31) by means of respective material conveyors (41) which are each equipped with material holders (44) that consist solely of rigid immovable supporting members for the reels or cassettes (84). The feed and discharge of these material holders (44) take place automatically as a result of an appropriate relative movement of feed and discharge members.

The invention relates to an apparatus for transporting packaging material, especially reels of web-shaped packaging material, from a stock to at least one reception station, especially in the region of a packaging machine, with material conveyors which are movable along a conveyor track (rail line) extending above the packaging machines.
For the feeding of high-performance cigarette-packaging machines or so-called lines consisting of several packaging machines one following the other and performing different functions, there has already been proposed a conveying system for the packaging material, in which web-shaped packaging material in the form of reels is fed to the individual consumption points in the region of the packaging machines by a circular conveyor with a plurality of rotating supporting members, each receiving a reel. The reels are conveyed up to the circular track in the region of a loading station by a feed conveyor and are taken over automatically by reel carriers. The reels are taken over in reverse order in the region of the packaging machine by a discharge conveyor. For receiving the reels during transport, the rotating conveyor members are equipped with a supporting journal which enters a central orifice in the reel. The supporting journal is mounted on a supporting arm rotatable about a vertical axis (DE-A-3,632,237 corresponding to U.S. Pat. No. 4,907,689 issued Mar. 13, 1990).

Apparatus for transporting packaging material to a packaging machine


A canister is provided with a plurality of adsorbent chambers filled with adsorbent, and the adsorbent chambers are connected together so as to form a U-turn-shaped passage. The canister has a communication chamber through which both end portions of adjacent two adsorbent chambers communicate with each other; a middle chamber formed at the end portion of one of the adjacent two adsorbent chambers, which is positioned at a downstream side of the communication chamber, and connected to the communication chamber through a communication hole; a baffle plate set in the middle chamber with the baffle plate facing to the communication hole so that an incoming air flow from the communication hole strikes against the baffle plate and diffuses in the middle chamber; and a tubular portion protruding in the communication chamber from an opening edge of the communication hole along a longitudinal direction of the one adsorbent chamber.

The present invention relates to a canister used for an evaporative fuel treatment device of a vehicle, and more particularly to a canister having a structure of a series of flow passages which is formed by connecting a plurality of adsorbent chambers together to form a U-turn-shaped flow passage.
As a well-known technique, in a vehicle using an engine, in order to prevent evaporated fuel (or evaporative fuel) in a fuel tank from being released into the atmosphere, an evaporative fuel treatment device having a canister as a main component is provided.
With respect to the canister, an adsorbent such as an activated carbon fills an inside of a casing of the canister. The canister has the function of adsorbing, by the adsorbent, the evaporated fuel generated from the fuel tank in an engine halt state, and desorbing the evaporated fuel from the adsorbent and introducing it into an intake system of the engine by the atmospheric air introduced from an air port (also called a drain port) at engine start-up or in an engine operating state.
Since it is necessary for such canister to secure a sufficient length of a flow passage from a charge port and a purge port, which are provided at one end portion of the canister, to the air port which is provided at the other end portion, i.e. a sufficient length in a flow direction of the adsorbent, a structure in which two or three separate adsorbent chambers are connected in order so as to form a U-turn-shaped flow passage is generally employed, as disclosed in Japanese Patent Provisional Publication No. 2012-007501 (hereinafter is referred to as "JP2012-007501"). In an example shown in FIG. 4 in JP2012-007501, a canister has three adsorbent chambers. A first adsorbent chamber and a second adsorbent chamber, which are positioned at a charge port side, are fixedly connected to each other as one unit by a case, and communicate with each other by a communication passage formed at a part of the case. Then, a third adsorbent chamber is formed by a different case, and one end of the third adsorbent chamber and one end of the second adsorbent chamber are connected together through an external pipe such as flexible rubber tube.
On the other hand, Japanese Patent Provisional Publication No. 2008-106610 (hereinafter is referred to as "JP2008-106610") discloses a structure in which a baffle plate is provided in an opposing position to the air port in order that the atmospheric air coming from the air port widely diffuses upon purging.


An array substrate for an organic electroluminescent display device includes a substrate including a display area and a non-display area; a gate line and a data line; a thin film transistor including a semiconductor layer of polycrystalline silicon, a gate insulating layer, a gate electrode, an inter insulating layer, a source electrode, and a drain electrode; auxiliary lines formed of a same material and on a same layer as the data line; a passivation layer of organic insulating material and including a drain contact hole exposing the drain electrode, and an auxiliary line contact hole exposing one of the auxiliary lines; and a first electrode and a line connection pattern on the passivation layer, wherein the first electrode contacts the drain electrode and the line connection pattern contacts the one of the first auxiliary pattern.

1. Field of the Invention
The present disclosure relates to an array substrate for an organic electroluminescent display device, and more particularly, to an array substrate for an organic electroluminescent display device that includes a thin film transistor having polycrystalline silicon as a semiconductor layer and a method of fabricating the same.
2. Discussion of the Related Art
With rapid development of information technologies, display devices for displaying a large amount of information have been promptly developed. Recently, flat panel display (FPD) devices having a thin profile, light weight and low power consumption have been suggested and actively pursued.
Among these, organic electroluminescent display devices have been recently spotlighted because they have many merits as follows: organic electroluminescent display devices have high brightness and low driving voltages; because they are self-luminous, the organic electroluminescent display devices have excellent contrast ratios and ultra thin thicknesses; the organic electroluminescent display devices have response time of several micro seconds, and there are advantages in displaying moving images; the organic electroluminescent display devices have wide viewing angles and are stable under low temperatures; since the organic electroluminescent display devices are driven by low voltage of direct current (DC) 5V to 15V, it is easy to design and manufacture driving circuits; and a manufacturing process of an organic electroluminescent display device is very simple because substantially only deposition and encapsulation apparatus is required. In the organic electroluminescent display devices, active matrix type display devices have been widely
An organic electroluminescent display device includes an array substrate on which thin film transistors for turning on/off respective pixel regions are formed. Thin film transistors may have polycrystalline silicon as a semiconductor layer. An array substrate for an organic electroluminescent display device including polycrystalline silicon thin film transistors, generally, is fabricated through 10 mask processes: forming a semiconductor layer of polycrystalline silicon, forming a first storage electrode; forming a gate electrode; forming an inter insulating layer having a semiconductor contact hole; forming source and drain electrodes; forming a first passivation layer of inorganic insulating material; forming a second passivation layer of organic insulating material; forming an anode electrode; forming a bank; and forming a spacer.
After forming a material layer on a substrate, a mask process includes steps of forming a photoresist layer on the material layer, exposing the photoresist layer to light through a photo mask, developing the light-exposed photoresist layer to form a photoresist pattern, etching the material layer using the photoresist pattern as a mask, and stripping the photoresist pattern.
Therefore, to perform one mask process, apparatus and materials for each step are needed, and time for each step is also required. In manufacturing an organic electroluminescent display device, trials and efforts for reducing the mask processes have been made to reduce the manufacturing costs and to improve the productivity. A method of skipping one of the first and second passivation layers has been suggested, and in this case, there may be disconnection between signal lines or connection patterns.

Array substrate for organic electroluminescent display device and method of fabricating the same


The invention relates to a cover panel for an aircraft, comprising a decompression opening that can be closed by a decompression flap that comprises a membrane, and a ventilation opening that is provided separately in the cover panel and that is permanently open. Furthermore, the invention relates to an aircraft fuselage comprising such a cover panel.

The invention relates to a cover panel for an aircraft, comprising a decompression opening.
The fuselage of a normal passenger aircraft is divided into several regions, among others a passenger region and a cargo region. During cruise flights, the aircraft is surrounded by cold environmental conditions of low air pressure, which requires air conditioning and pressurisation of the aircraft fuselage. For this purpose, bleed air from the engines is normally introduced into the passenger cabin, which bleed air, when it has passed through the passenger region, can escape from the passenger region through ventilation openings that have been placed in the cover panels such that they are positioned in the area of the passenger foot space. Should the case arise where the fuselage is torn open or is connected to the environment of the aircraft, for example by way of a defective cargo compartment door, as a result of the large pressure differential between the ambient air of the aircraft fuselage and the interior region of the aircraft fuselage, which region is directly behind the opening that has arisen, air from this region escapes to the outside until finally in the region behind the opening that has arise, the pressure is similar to the ambient pressure of the aircraft. If for example the cargo compartment is the affected region, then as a result of the escaped air there is a large pressure differential between the passenger region and the cargo region that is separated from it. This would result in the cabin floor that separates the passenger region from the cargo region being subjected to large forces that might lead to damage to the cabin floor and thus to damage of air-safety-relevant system elements and structure elements.
For the purpose of bringing about rapid pressure compensation in such a case, so called decompression flaps are provided between the passenger region and the cargo region, which flaps in the case of a fast drop in pressure within the cargo region (or in some other region) open up and provide a flow path with an enlarged cross section.
Such a decompression flap arrangement is, for example, disclosed in WO 2007/073787 A1. However, this decompression device is associated with a disadvantage in that its design is relatively complex, which in turn results in greater weight, more expensive production, and high maintenance expenditure for the aircraft operator.