A method for removal of post reactive ion etch by-product from a semiconductor wafer surface or microelectronic composite structure comprising:

1. Field of the Invention
The invention relates to a process for post reactive ion etching (RIE) polymer removal on an organic low K dielectric through the use of reducing plasma chemistry. The process removes extensive post RIE polymer on an organic low K dielectric material by use of a reducing gas plasma and comprises either a forming gas mixture of (N2/H2) or an ammonia/hydrogen (NH3/H2) mixture to completely remove the post reactive ion etch by-product from a wafer surface or a Via structure prior to a wet chemical clean. The removal is achieved without significant removal of the organic, low K dielectric material that is exposed to the gas plasma.
2. Description of the Related Art
Existing post RIE plasma clean solutions use oxidizing chemistries; however, these chemistries cannot be utilized with organic low constant (K) dielectrics due to the extremely poor selectivity of the polymer strip/clean to the organic low K dielectric material.
In particular, a case in point is the accomplishment of post RIE polymer cleaning by utilizing a chromic-phosphoric acid tank bath or other solvent based chemistry. In this process, there is a certain time window of approximately 4 hours between completion of the RIE process and the wet cleaning step.
However, some drawbacks of currently existing wet chemical cleaning methods are as follows: an acid based chemistry (without any HF in it) is not efficient in removing polymer that have high silicon content (as found in metal pads located in the support region); and a solvent based chemistry generally takes a longer process time (approximately 10 minutes as compared to 2 to 4 minutes for a typical acid based clean) and typically is encumbered as a result of costs and environmental disposal requirements.
U.S. Pat. No. 5,780,359 disclose polymer removal from top surfaces and sidewalls of a semiconductor wafer by: initiating a flow of feed gas comprising fluorine-containing gases upstream from the process chamber; applying the feed gas means for producing a plasma; supplying effluents of the plasma in the form of reactive species separated from the plasma to the process chamber; applying radio frequency energy to the wafer in the process chamber to generate a lower intensity plasma therein and accompanying wafer self-biasing; applying a magnetic field that rotates slowly in the horizontal plane to the process chamber during the step of applying radio frequency energy to the wafer to enhance plasma generation; and stripping the photoresist and polymer residues from the top surfaces and sidewalls of the post metal-etch wafer with the reactive species and the lower intensity plasma; wherein the pressure in the process chamber is greater than 100 milliTorr
A process for removal of post-RIE polymer on Al/Cu metal line is disclosed in U.S. Pat. No. 5,980,770. The process entails: supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber in which the composite structure is supported to form a water soluble material of sidewall polymer rails left behind on the Al/Cu metal line from the RIE process; removing the water soluble material with deionized water; and removing photo-resist from the composite structure by either a water-only plasma process of the chemical down stream etching method; or forming a water-only plasma process to strip the photoresist layer of a semiconductor or microelectronic composite structure previously subjected to a RIE process; supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber on which the structure is supported to form a water soluble material of the sidewall polymer rails left behind on the Al/Cu metal line from the RIE process; and removing the water-soluble material with deionized water.
U.S. Pat. No. 6,009,888 disclose a method of stripping photoresist and polymer from a wafer after a dry etch, comprising: forming a photoresist pattern over a semiconductor structure; immersing the substrate in a bath comprising (a) peroxydisulfate (S2O82xe2x88x92) (bisulfate), (2) hydrochloric acid (HCl) and (3) water; and agitating the semiconductor structure in the solution; said bath being at a temperature in a range of between about 90 and 100xc2x0 C.; irradiating the semiconductor structure, and the photoresist pattern with a UV laser with a wave length between about 150 nm and 300 nm, and with an energy between about 4 and 8.0 eV and laser pulses in a range of between about 10 and 10,000 per wafer to remove the photoresist.
Previous approaches for removing RIE polymer from semiconductor materials used no post RIE clean, and this led to high contact resistance and reliability failures.
Alternatively, when previous approaches utilized wet chemical only clean, this caused severe contamination of the wet chemical bath from delaminating fluoropolymer on the wafer surface deposited during RIE processes.
There is a need in the art of cleaning RIE etched materials to remove fluoropolymer/hydrocarbon from the surface of an organic low k dielectric material without excessive removal of organic dielectric material.
One object of the present invention is to provide a process to completely remove post-reactive ion etch (RIE) by-product from a wafer surface or Via structure prior to wet chemical clean.
Another object of the present invention is to provide a process for removing post-reactive ion etch (RIE) by-product from a wafer surface or Via structure prior to a wet chemical clean by utilizing a reducing gas plasma incorporating a forming gas mixture of N2/H2.
A further object of the present invention is to provide a process to completely remove post-reactive ion etch (RIE) by-product from a wafer surface or Via structure prior to a wet chemical clean by utilizing a reducing gas plasma incorporating a forming gas mixture of NH3/H2.
A still further object of the present invention is to provide a process for completely removing post-reactive ion etch (RIE) by-product from a wafer surface or Via structure prior to a wet chemical clean without significant removal of an organic, low dielectric constant material which is exposed to either a reducing gas plasma incorporating either a forming gas mixture of N2/H2 or NH3/H2.
A yet further object of the present invention is to provide a process for completely removing post-reactive ion etch (RIE) fluoropolymer strip from either single or dual damascene structures by utilizing a reducing gas plasma incorporating either a forming gas mixture of N2/H2 or NH3/H2.

Abstract: supplying a reducing gas plasma incorporating a forming gas mixture selected from the group consisting of a mixture of N2/H2 or a mixture of NH3/H2 into a vacuum chamber in which a semiconductor wafer surface or a microelectronic composite structure is supported to form a post-RIE polymer material by-product on the composite structure without significant removal of an organic, low K material which has also been exposed to the reducing gas plasma; and

Abstract: removing the post-RIE polymer material by-product with a wet clean.


An electronic component mounting method is disclosed. The method includes the following steps: applying a paste remaining on a stamping pin to the bottom wall of at least one reservoir; forming the paste retained in the at least one reservoir to a predetermined film thickness by a clearance regulation section; causing the paste formed into a film to adhere to the stamping pin; stamping the paste to a substrate; and mounting the electronic components held by a mounting head to the substrate on which the paste has been stamped.

1. Field of the Invention
The present invention relates to an electronic component mounting apparatus that mounts electronic components on a substrate with a paste adhesive stamped thereto.
2. Description of the Related Art
In a field of electronic components being mounted on a substrate, stamping a paste adhesive affixed to a stamping pin provided on a stamping head to the substrate has hitherto been known as a method for supplying the substrate with the paste adhesive. The stamping pin has a stamp surface for letting the paste adhesive adhere and stamping the thus-adhering adhesive to a substrate. Projections appropriate for a shape desired to be stamped are formed on the stamp surface. Although the paste adhesive adhering to the projection is stamped to the substrate, the paste adhesive builds up in space between the projections with an increase in the number of times stamp is performed. The adhesive adheres to a substrate, which in turn becomes a cause for deteriorating stamp quality. A hitherto known apparatus has a cleaning unit disposed between a paste adhesive supply position and a stamp position. A stamp surface is brought into contact with a cleaning material, such as non-woven fabric, thereby cleaning the stamp surface and removing the built-up paste adhesive (see Patent Document 1).
Patent Document 1: JP-A-2001-7136
However, the cleaning unit is situated at a position where the cleaning unit occupies a location and does not interfere with another member. Therefore, the cleaning unit does not always situate at a position on a traffic line of the stamp head achieved during normal operation. For this reason, the stamp head is required to perform movement, which differs from movement performed during normal operation, for cleaning purpose. As a result, there arises a problem of movement of the stamp head involving consumption of time and deterioration of productivity.


A cutter includes a male blade, a female blade, an advancement and retraction controller and a suction device. The male blade includes: a linear cutting portion linearly shaped with a predetermined thickness in a center part; a rounded cutting portion where a radius having a substantially arc shape in planar view is continuously formed from the linear cutting portion; and an end provided adjacent to the rounded cutting portion. The female blade has a fitting portion that is a hole conforming to the profile of the male blade in planar view and to which the male blade is fitted. On a lateral side of the female blade, an elongated hole for inserting a base film from one lateral side to the other lateral side is formed as an insertion portion.

As a packaging material for packaging foods, pharmaceutical and medical products and groceries, a four-side-sealed packaging bag is known. Such a four-side-sealed packaging is provided by sealing two base films of a quadrangular bag body at four sides. The packaging bag has four sharp corners, which may hurt a hand or make runs in stockings and the like. Accordingly, a technique to cut the four corners in a substantially arc shape has been widespread.
For a manufacturing device of a packaging bag, an outline process in which devices are individually operated and an inline process in which devices are incorporated in a process line to manufacture a roll of packaging bags are available.
In the outline process, as shown in FIG. 10A, after sealing side seal portions 21 and a bottom seal portion 22 to form a quadrangular three-side-sealed packaging bag 1A, corners 11 on the side seal portions 21 and the bottom seal portion 22 are cut in two steps to form a packaging bag 1. Alternatively, as shown in FIG. 10B, after sealing the side seal portions 21 and the bottom seal portion 22 to form a quadrangular three-side-sealed packaging bag 1A, corners 11 on the side seal portions 21 and the bottom seal portion 22 are cut in one step to form a packaging bag 1. This outline process is time-consuming because of manual cutting and considerably costly because heavy equipment investment is required for using expensive machines.
In the inline process, as shown in FIG. 11A, in a base film 10 having a partition 181 sealed at every predetermined distances and partition 182 continuously sealed at one side, a part (chip 12) of the partition 181 is firstly cut off to form a rounded portion 13. Subsequently, the base film is cut along a straight line L located near a center part of the partition 181. As shown in FIGS. 11B and 11C, as a result of such a two-step operation, the straight line L and an end of the rounded portion 13 are not aligned to unfavorably form a protrusion P.
Accordingly, according to a technique, two cutting lines are provided and are respectively cut with two blades, thereby avoiding protrusion formation.
As disclosed in Patent Document 1, another technique using a blade capable of integrally forming four corners and a straight line of a packaging bag and cutting the four corners and the straight line in a one-step operation is also known.
[Patent Document 1] JP-A-05-8330

Device for cutting packing bag, device for producing packing bag and method for producing packing bag


There is provided an audio and/or video transmission system. That audio and/or video transmission system has a microphone unit for detecting an audio signal. The microphone unit has a first wireless transmitting unit for wirelessly transmitting an audio signal by way of a first transmission path and a second wireless transmitting unit for wirelessly transmitting the audio signal by way of a second transmission path. The second wireless transmitting unit is adapted to embed a time stamp in the audio signal to be transmitted by way of the second transmission path.

1. Field of the Invention
The present invention concerns an audio and/or video transmission system.
2. Description of Related Art
Reports outside a television center typically involve a cameraman operating a portable video camera while a reporter uses a wired or wireless microphone. In that case the audio signals detected by the microphone are transmitted wirelessly or wired to the camera unit and stored there. Then the video signal recorded by the camera and the audio signal recorded by the microphone can be transmitted together by the camera unit. As reports with such a camera unit and such a microphone have to be carried out at different locations and under widely differing conditions it is necessary to ensure that the audio signal picked up by the microphone is reliably transmitted to the camera unit.
As general state of the art attention is directed to DE 10 2005 042 904 B4, U.S. Pat. No. 6,788,751 B1, WO 2011/023723 A1 and JP 2007081686 A.


An electromagnetic relay diagnostic device includes: an operation detection unit including a first light-emitting unit emitting light when a current flows through a wiring line connected to a coil of an electromagnetic relay; an operation detection unit including a second light-emitting unit emitting light when a current stops flowing through the wiring line; an operation detection unit including a third light-emitting unit emitting light when detecting a change in conductive state of a wiring line connected to a contact of the electromagnetic relay; an operation detection unit including a fourth light-emitting unit emitting light when detecting that the change in conductive state of the wiring line has disappeared; an imaging unit capturing a moving image of the operation detection units; and a diagnostic unit calculating a contact-on operation time and a contact-off operation time using the moving image, and diagnosing whether an abnormality has occurred in the electromagnetic relay.

In a control circuit for controlling a breaker and a disconnector of a gas insulated device, two or more electromagnetic relays are used, and the control is performed in combination of the two or more electromagnetic relays. If a failure or an operation delay occurs in any of the electromagnetic relays, there may be a case where the control circuit cannot perform a normal control operation, thereby leading to poor control of the gas insulated device.
Therefore, each device is operated at the time of periodic inspection, and if the device operation is within a control range, every electromagnetic relay of the control circuit is determined to be normal. However, since the electromagnetic relay itself is not inspected in this manner, malfunction may possibly occur immediately after the inspection.
Regarding a defect caused by a factor of aging degradation, such as an excessive tightness of a mechanism part of the electromagnetic relay, it is useful to diagnose the defect by measuring a contact-on operation time, which is a time from when an electric current starts flowing through a wiring line connected to a coil of the electromagnetic relay to when a conductive state of a wiring line connected to a contact of the electromagnetic relay changes, and a contact-off operation time, which is a time from when an electric current stops flowing through the wiring line connected to the coil of the electromagnetic relay to when the change in the conductive state of the wiring line connected to the contact of the electromagnetic relay disappears. However, since it takes time to attach a measuring instrument, it is necessary to provide a simple measuring device.
Patent Literature 1 discloses a device that captures an image of a relay with an operation indicator light in a relay control device by using a camera with high-speed shutter, and observes a control state of the control device on the basis of a lighting state of the relay with an operation indicator light.


A gearless locking differential includes clutch housings containing V-shaped slots that cooperate with a cross pin to disconnect from the differential drive shaft an overrunning driven shaft, characterized in that the wall surfaces that define the V-slots extend parallel with the axis of rotation of the differential housing, and the cross pin has tapered convergent end portions. The frictions packs that releasably connect the side gears to the clutch members include annular friction plates that are arranged between pairs of reaction plates and include polygonal internal surfaces that slidably and non-rotatably engage a corresponding polygonal circumferential surface on the associated side gear. The locking lug and locking slot that cooperate to provided limited angular relative displacement between the clutch housings each have parallel side walls. As a consequence of the invention, the machining and finishing of the components of the differential are achieved in a simplified cost-effective manner.

1. Field of the Invention
A gearless locking differential includes clutch members having V-shaped slots that cooperate with a cross pin to disconnect from the differential drive shaft an overrunning driven shaft, characterized in that the wall surfaces that define the V-slots extend parallel with the axis of rotation of the differential housing, and the cross pin has tapered convergent end portions. The frictions packs that releasably connect the side gears to the clutch housings include annular friction plates that are arranged between pairs of reaction plates and include polygonal internal circumferential surfaces that slidably and non-rotatably engage a corresponding polygonal circumferential surface on the associated side gear. The locking lug and the locking slot which cooperate to provided limited angular relative displacement between the clutch housings each have parallel side walls. As a consequence of the invention, the machining and finishing of the differential components is achieved in a simplified cost-effective manner.
2. Description of the Related Art
Locking differentials for automotive vehicles are well known in the patented prior art, as evidenced by the patents to Lewis U.S. Pat. No. 2,555,044, Zentmyer U.S. Pat. No. 5,413,015, and Valente U.S. Pat. Nos. 5,590,572 and 5,727,430, and Dissett U.S. Pat. No. 5,715,733, and Dissett et al U.S. Pat. No. 6,6988,194.
In these known differentials, it is common to utilize a pair of annular coaxially-arranged axially-spaced clutch members arranged on opposite sides of a diametrically extending driving cross pin that extends within mating cam grooves contained in the adjacent faces of the clutch members. Spring means normally bias the clutch members apart, and a locking pin extends axially from one face into a recess contained in the adjacent face of the other clutch member, thereby to prevent relative rotational movement between the clutch members. The locking pins are generally separate components, used in connection with a plurality of biasing springs and spacer disks or plugs, thereby causing assembly of the differential to be relatively labor intensive and manually difficult.
In the original design shown in the Dissett et al U.S. Pat. No. 6,688,194, it was necessary o manufacture the "V" ramps on the clutch housing in a skewed manner in a very complicated three dimensional plane. This was required for the cylindrical shaped cross pin to make a full line contact on the "V" ramps of the clutch housing, at the point where all of the end-play from the clutch housing to the differential case was taken up, allowing a good distribution of the loading and full clutch pack lock-up. As the cross pin rotates relative to the clutch housing, it runs up the ramp on the clutch housing and moves the housing in an outward direction locking up the clutch pack. This movement allows the torque to be transferred from the clutch housing to the side gear and then to the axle shaft.
The present invention was developed to provide an improved locking differential that is less expensive and easier to produce and inspect, and which affords improved relative sliding movement between the components of the friction packs, whereby the possibility of binding of the components is greatly reduced. According to the present invention, the clutch housing and the side gears can be completely manufactured from powdered metal with no secondary machining required. These two major components can also be cold or warm forged for higher load applications with much less secondary machining that the prior art production design. The improved design of the friction and reaction plates as well as the inner spacer have been designed to simplify the manufacture thereof and to improve the smoothness of the energizing and de-energizing of the friction reaction plates by allowing them to slide easier on the side gear and in the clutch housing, respectively. For lower volume manufacturing needs, all the slots, keyways and keys have been designed with straight and parallel sides, thereby to allow for simple milling operations. It will also be easier to inspect these components.


A copper anode furnace includes a furnace drum which can be pivoted about a horizontal axis and in which copper melt is refined into anode copper by fire refining. The furnace drum is provided with a spout for pouring out the refined copper. A sliding closure is arranged on the spout of the furnace drum. The sliding closure includes at least one stationary, fireproof closing plate and a fireproof sliding plate which can be displaced relative to the closing plate. Through the displacement of the sliding plate, the outflow out the furnace drum can be regulated or closed and therefore the outflow amount of the copper can be controlled. A drawing of slag into the casting, which reduces the anode quality, can be prevented using the sliding closure.

Copper anode furnaces, in which copper melt is refined into anode copper by means of fire refining and then the copper is poured out in anode form, are known. The anodes are further processed by means of electrolysis. The quality of the anodes substantially affects the power consumption, i.e. the cost-effectiveness of the electrolysis.
The copper anode furnace is known to comprise a furnace drum which can be pivoted about a horizontal axis and in which the copper melt with 95-98% copper is brought in two stages to a purity level of approximately 99%, oxidation of the undesired accompanying elements (primarily the sulphur) taking place first of all, and then the oxygen content which has risen significantly due to the oxidation is reduced again in a reduction phase. The copper is poured out via a run-off hole disposed on the periphery of the furnace drum. When pouring out the furnace drum is turned bit by bit in order to regulate the casting speed and to take account of the falling molten bath level. A number of disadvantages arise from this. Due to the position of the run-off hole—very close to the surface of the bath—slag is also poured off, and this has a negative impact upon the anode quality. In addition, the fall height of the copper from the run-off into a channel system is very high, and so the oxygen which one had taken pains to remove is taken up again, and this also leads to worsening of the anode quality. Moreover, the environment is seriously contaminated by the sprayed copper, material losses also being observed.

Copper anode furnace and a method for operating the same


A multi-mode gain control loop for a PR4, ML data channel, such as one included in a magnetic disk data storage device, includes an input for receiving from a source an analog signal stream including coded data to be detected; a VGA for amplifying the analog signal stream; an analog to digital converter for receiving the analog signal stream and for generating and putting out data samples therefrom; an analog gain control loop connected to generate an analog gain control from the analog data stream during a data non-read mode of the channel, to store the analog gain control in a storage circuit, and to apply the stored analog gain control constantly to control the VGA; and a digital gain control loop connected to generate gain vernier correction values from the data samples and for applying the gain vernier correction values through a gain DAC to provide an offset control to the VGA during a data read mode of the channel.

Conventional disk drives have employed peak detection techniques in order to recover digital data written as saturation recording onto a magnetizable surface media of a rotating disk. With peak detection techniques, it is necessary to space flux transitions sufficiently apart so that analog peaks in the recovered data stream may be identified and the corresponding data recovered. In order to achieve reasonable bandwidths in data channels, it has been customary to employ data coding techniques. One such technique has been to use a (1,7) RLL code. In this code, flux transitions can be no closer together than every other clock bit time period ("bit cell") nor farther apart than eight clock bit cells. (1,7) RLL codes are known as "rate two-thirds" codes, in the sense that two data bits are coded into three code bits. Thus, with a rate two-thirds code, one third of the user storage area of the storage disk is required for code overhead.
One way to decrease the code overhead is to employ a code in which flux transitions are permitted in adjacent bit cells. One such code is a (0,4,4) code. The (0,4,4) code can be implemented as a rate eight-ninths code, meaning that nine code bits are required for eight incoming data bits. (Theoretically, the (0,4,4) code capacity is somewhat higher, approaching 0.961). Thus, this code is significantly more efficient than a rate two-thirds code, such as (1,7) RLL. Use of a (0,4,4) code results in a significantly greater net user data storage capacity on the disk surface, given a constant bit cell rate. However, when flux transitions occur in adjacent bit cells, as is the case with a (0,4,4) code, intersymbol interference ("ISI") results. Conventional peak detection techniques are not effective or reliable in recovering data coded in an eight-ninths code format, such as (0,4,4).
The zero in the (0,4,4) code denotes that flux transitions may occur in directly adjacent bit cells of the coded serial data stream. The first "4" denotes that a span of no more than four zeros occurs between ones in the encoder output. The second "4" signifies that the bit cell stream has been divided into two interleaves: an even interleave, and an odd interleave; and, it denotes that there can be a span of no more than four zeros between ones in the encoder output of either the odd interleave or the even interleave.
It is known that partial response signalling enables improved handling of ISI and allows more efficient use of the bandwidth of a given channel. Since the nature of ISI is known in these systems, it may be taken into account in the decoding/detection process. Partial response transmission of data lends itself to synchronous sampling and provides an elegant compromise between error probability and the available spectrum. The partial response systems described by the polynomials 1+D, 1-D, and 1-D.sup.2 are known as duobinary, dicode and class IV (or "PR4"), respectively, where D represents one bit cell delay and D.sup.2 represents 2 bit cell delays (and further where D=e.sup.-j.omega.T, where .omega. is a frequency variable in radians per second and T is the sampling time interval in seconds). The PR4 magnitude response plotted in FIG. 1 hereof and given the notation .vertline.1-D.sup.2 .vertline. emphasizes midband frequencies and results in a read channel with increased immunity to noise and distortion at both low and high frequencies. In magnetic recording PR4 is a presently preferred partial response system, since there is a close correlation between the idealized PR4 spectrum as graphed in FIG. 1, and the natural characteristics of a magnetic data write/read channel.
In order to detect user data from a stream of coded data, not only must the channel be shaped to a desired partial response characteristic, such as the PR4 characteristic, but also a maximum likelihood ("ML") sequence estimation technique is needed. The maximum likelihood sequence estimation technique determines the data based upon an analysis of a number of consecutive data samples taken from the coded serial data stream, and not just one peak point as was the case with the prior peak detection methods.
One maximum likelihood sequence estimation algorithm is known as the Viterbi detection algorithm, and it is well described in the technical literature. Application of the Viterbi algorithm to PR4 data streams within a magnetic recording channel is known to improve detection of original symbol sequences in the presence of ISI and also to improve signal to noise ratio over comparable peak detection techniques.
In an article entitled "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel" appearing in IEEE Trans. on Communications, vol. Com-34, No. 5, May 1986, pp. 434-461, authors Wood and Peterson explain the derivation of PR4 as being formed by subtracting waveforms two bit intervals apart, thereby forming an analog domain ternary "eye" pattern graphed herein in FIG. 2.
The Viterbi algorithm provides an iterative method of determining the "best" route along the branches of a trellis diagram, such as the one shown in FIG. 3 hereof, for example. If, for each trellis branch, a metric is calculated which corresponds to the logarithm of the probability for that branch, then the Viterbi algorithm may be employed to determine the path along the trellis which accumulates the highest log probability, i.e., the "maximum likelihood" sequence. Since the Viterbi algorithm operates upon a sequence of discrete samples {y.sub.k }, the read signal is necessarily filtered, sampled, and equalized.
While PRML has been employed in communications signalling for many years, it has only recently been applied commercially within magnetic hard disk drives. One recent application is described in a paper by Schmerbeck, Richetta, and Smith, entitled "A 27 MHz Mixed Analog/Digital Magnetic Recording Channel DSP Using Partial Response Signalling with Maximum Likelihood Detection", Proc. 1991 IEEE International Solid State Circuits Conference, pp. 136-137, 304, and pp. 96, 97 and 265 Slide Supplement. While the design reported by Schmerbeck et al. appears to have worked satisfactorily, it has drawbacks and limitations which are overcome by the present invention. One drawback of the reported approach was its design for transducers of the ferrite MiG type or of the magnetoresistive type which simplified channel equalization requirements. Another drawback was the use of a single data transfer rate which significantly simplified channel architecture. A further drawback was the use of a dedicated servo surface for head positioning within the disk drive, thereby freeing the PR4, ML data channel from any need for handling of embedded servo information or for rapid resynchronization to the coded data stream following each embedded servo sector.
Prior Viterbi detector architectures and approaches applicable to processing of data sample sequences taken from a communications channel or from a recording device are also described in the Dolivo et al. U.S. Pat. No. 4,644,564. U.S. Pat. No. 4,504,872 to Peterson describes a digital maximum likelihood detector for class IV partial response signalling. An article by Roger W. Wood and David A. Peterson, entitled: "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel" IEEE Trans. on Comm. Vol. Com-34, No. 5, May 1986, pp. 454-466 describes application of Viterbi detection techniques to a class IV partial response in a magnetic recording channel. An article by Roger Wood, Steve Ahigrim, Kurt Hallarnasek and Roger Stenerson entitled: "An Experimental Eight-Inch Disc Drive with One-Hundred Megabytes per Surface", IEEE Trans. on Magnetics, Vol. Mag-20, No. 5, September 1984, pp 698-702 describes application of class IV partial response encoding and Viterbi detection techniques as applied within an experimental disk drive. A digital Viterbi detector capable of withstanding lower signal to noise ratios is described in Matsushita et al. U.S. Pat. No. 4,847,871. These documents are representative examples of the known state of the prior art.
In sample based data detection systems, such as PR4,ML, the analog read signal is sampled by an analog to digital converter ("A/D"). The conversion process includes quantization according to the number of bits in the A/D so that, for optimal performance, it is desirable to adjust the amplitude of the analog read signal at the input to the A/D to a level that fully uses the available dynamic range thereof. This is best done with an automatic gain control ("AGC") circuit that senses amplitude as reported by the signal samples since they determine the recovered information content.
One prior approach to gain control within a PR4,ML channel has been proposed by workers at IBM. This prior approach is described in Hirt et al. U.S. Pat. No. 4,750,058 entitled: "Gain Control Circuitry for Readback Apparatus in a PRML Magnetic Recording System." Other facets of this approach are described in an article by Coker et al, entitled "Implementation of PRML in a Rigid Disk Drive", IEEE Trans. on Magnetics, Vol. 27, No. 6, November 1991, pp 4538-4543. This prior approach has several drawbacks. First, an analog loop filter is active during both non-read mode and during read mode when data samples are available. The use of an analog loop filter in the gain loop during read mode makes it somewhat cumbersome to change loop compensation "on the fly". In addition, the analog gain control loop is susceptible to amplitude offset errors. In other words, the DAC control word provides a gain error value that is put into the analog loop filter. If the DAC word that corresponds to zero gain error does not produce exactly zero input to the loop filter, the system is left with an inherent gain offset or bias. A system with a digital loop filter will not exhibit this drawback since the DAC output directly controls the VGA.
In addition, failure of this prior approach to employ update rate scaling techniques required that the gain DAC be capable of operating at the basic data sample clocking rate, thus requiring greater design complexity and power consumption, and leaving the gain loop more susceptible to noise and transients.
Thus, a hitherto unsolved need has arisen for an improved gain control loop for controlling a sampled data detection system, such as a PR4,ML channel within a high performance, very high capacity, low servo overhead disk drive data storage subsystem.

Multi-mode gain control loop for PRML class IV sampling data detection channel


An RFIC with memory is described where the memory can be used to house a look-up table for tuning components designed into the RFIC, providing a customized tuning circuit for antenna and transceiver front-end tuning applications. The look-up table can be loaded at wafer level during the manufacturing process to customize an RFIC design for a specific antenna system. The memory can be used to restrict or tailor the tuning range of tunable capacitors and switches within the RFIC to optimize performance in the end application. The resident memory will improve signaling latency when tuning for time critical applications such as channel tuning in a cellular communication system.

Field of the Invention
This invention relates generally to the field of wireless communication; and more particularly, to components used in tuning circuits and methods of dynamically adjusting RF communication system performance.
Description of the Related Art
As the need for higher data rates increases, communication systems are being designed to cover wider instantaneous frequency bandwidths. Also, with the introduction of 4G protocols such as Long Term Evolution (LTE), additional frequency bands are being used for cellular communication systems. In mobile communication systems, backward compatibility is required for cell phones being designed for 4G LTE applications such that the cell phone must be capable of operating at the 2G and 3G cellular bands as well as the 4G frequency bands. In addition, LTE as a protocol is configured to accommodate carrier aggregation, where multiple channels can be transmitted or received on simultaneously to increase instantaneous bandwidth. This aggregation of channels can cover up to five channels spread across multiple frequency bands. All of these trends point toward a growing need for more flexibility in the RF front-end of mobile communication systems to address the combining of multiple frequency bands and modes.
Dynamic tuning of antennas and RF front-ends of communication systems is picking up adoption in the commercial communications industry, and proper implementation of dynamic tuning methods can bring improvements to communication system performance as the number of frequency bands that can be accessed grows and the instantaneous bandwidths required increases. As antennas in mobile communication systems transition from passive types to active antenna systems, look-up tables and/or algorithms will be required to control the antenna tuning. Open loop antenna tuning will require a look-up table which contains tuning state information as a function of frequency, use case, and other sensor information. Closed loop antenna tuning will require an algorithm to control components to converge to a matched condition for impedance tuning, or will require an algorithm to select the optimal radiation pattern in a smart antenna or beam-steering antenna system. Look-up tables and algorithms require memory to store the information. The look-up table or algorithm can be stored in memory at a location within the host device that the active antenna system or RF front-end is integrated into. The latency of the signaling to control the active antenna system or RF front-end will be dependent on the location of the memory available for the look-up table or algorithm, and will also be dependent on the communication bus used in the communication to control functionality.
Integrating active antenna systems and/or tunable RF front-end systems require an added step of loading information in the form of a look-up table or algorithm in memory of the host device. The latency of the tuning function needs to be determined based upon the host system design and the location of the memory used for information storage. For more complex communication systems where there might be an active antenna system and multiple tuning functions associated with an RF front-end module, multiple components will require memory from the host device. There is a need for simplifying the memory requirements as more tuning type circuits are integrated into communication systems. The enclosed embodiments address this problem and provide a unique set of capabilities to improve system performance along with simplifying the integration process.

RF integrated circuit with tunable component and memory


A control device having a push to turn selector arrangement and method of making the same are provided, the control device comprising a support unit, a first selector member threadedly carried by the support unit so as to be rotatable and axially movable relative thereto, a second selector member rotatably carried by the support unit and being axially movable relative thereto, a coupling structure coupling the selector members together to cause the first selector member to rotate in unison with the second selector member when the second selector member is axially pushed inwardly and then rotated, and a spring unit disposed between the selector members to tend to maintain the second selector member axially away from the first selector member, the couping unit comprising a drive plate rotatably carried by the suport unit intermediate the selector members and having parts thereof respectively splined to the selector members to transmit rotatable movement of the second selector member to the first selector member while permitting axial movement of the selector members relative to the drive plate.

1. Field of the Invention
This invention relates to a new control device having a unique push to turn selector means and to a new method of making such a control device.
2. Prior Art Statement
It is known to provide a control device having a push to turn selector means and comprising a support means, a first selector member threadedly carried by the support means so as to be rotatable and axially movable relative thereto, a second selector member rotatably carried by the support means and being axially movable relative thereto, coupling means coupling the selector members together to cause the first selector member to rotate in unison with the second selector member when the second selector member is axially pushed inwardly and then rotated, and spring means disposed between the selector members to tend to maintain the second selector member axially away from the first selector member. For example, see the Decker et al, U.S. Pat. No. 3,999,442.

Control device having push to turn selector means and method of making the same


The invention relates to a pharmaceutical tablet for oral administration comprising ulipristal acetate together with the following excipients: at least one diluent in an amount of 50 to 98.5 wt %, at least one binding agent in an amount of 0 to 10 wt %, at least one disintegrating agent in an amount of 0.5 to 10 wt %, and at least one lubricant in an amount of 0 to 10 wt %.

Ulipristal acetate, formerly known as CDB-2914, designates within the context of this application 17α-acetoxy-11β-[4-N,N-dimethylamino-phenyl)-19-norpregna-4,9-diene-3,20-dione, represented by formula I:

Ulipristal acetate, and methods for its preparation, are described e.g., in U.S. Pat. Nos. 4,954,490; 5,073,548, and 5,929,262, as well as in international patent applications WO2004/065405 and WO2004/078709.
Ulipristal acetate possesses antiprogestational and antiglucocorticoidal activity, and has been proposed for contraception, in particular for emergency contraception, and for the therapy of various hormonal diseases. Properties of this compound are further described in Blithe et al, Steroids. 2003 68(10-13):1013-7. So far, clinical trials have been conducted using oral capsules of ulipristal acetate (Creinin et al, Obstetrics & Gynecology 2006; 108:1089-1097; Levens et al, Obstet Gynecol. 2008, 111(5):1129-36). In order to increase the properties and clinical benefit of this molecule, there is a need for improved formulations thereof.

This patent is subject to a terminal disclaimer.


An apparatus and method for the etching of semiconductor materials (14) is disclosed. The apparatus (10) includes a process chamber (12) having a remote generator (16) in fluid communication with the process chamber (12) for converting a noble gas (34) to a metastable gas (36). An etchant gas (40) is subsequently brought into the chamber (12) adjacent to the material (14), to mix and react with the metastable gas (36) at activation zone (38). The metastable gas (36) collides with the etchant gas (40) to cause the mixture to selectively etch the material 14.

When fabricating integrated circuits, a plurality of films are deposited onto a wafer. These films are selectively patterned, etched, doped, reacted, etc. to provide the desired functions for electronic devices. The patterning process can use a variety of well-known pattern transfer methods (e.g., using a pattern mask to transfer an image to the deposit film). After the deposited film is covered with a patterned mask, such as a photoresist layer, the exposed portion of the deposited film can then be removed.
Etching processes are used extensively in semiconductor manufacturing to remove exposed portions of the deposited film. One etching process that can be used to remove the exposed film is dry, or RF-plasma assisted, etching which uses plasma in the form of a low pressure gaseous discharge. This etching process provides a high fidelity transfer of resist patterns.
In some instance, etchant species are activated outside of the process chamber where the deposited film may potentially be damaged by plasma generated within the process chamber. When this excitation is provided outside of the process chamber, the process may be referred to as either after-glow, downstream or remote plasma etching. If additional excitation is required, it can be accomplished in the process chamber.
Defects are caused by the presence of particulates on a surface of the process materials. This is one of the reasons for the switch from wet etches to dry etches. Under certain conditions, however, remote plasma-etching can create particulates that are generated and carried to the surface of the etchant stream, thereby contaminating the surface of the process material.
One variety of remote plasma-etching activates the etchant by passing it through a microwave cavity. The process gases, including the etchant, flow through a discharge tube formed from a relatively inert insulating material (e.g., quartz) which passed through a microwave cavity. These activated process gases, in combination with high temperatures, can etch the internal surfaces of the quartz discharge tube, creating quartz particulates. Unfortunately, these generated quartz particulates are passed through process stream, to the face of the surface, and inevitably cause contamination to the surface of the semiconductor material.
Thus, there is a need for a remote plasma-etching process which does not contaminate the surface being processed. Consequently, it is desirable to activate the etchant, as close as possible to the surface of the wafer being etched, to eliminate any contamination caused when passing the activated gas through the quartz tubes of the process. Additionally, increased selectivity of activating the etchant would increase the control over the etching of the semiconductor materials.

Method and apparatus for etching semiconductor materials


An electronic device includes a targeted area within the electronic device. The targeted area includes a first side and a second side that is different from the first side. A first fan lies along the first side. Also, a second fan lies along the second side. The first fan and the second fan are both inlet fans or are both outlet fans. A method of using an electronic device is provided and includes directing a first fluid flow from the first fan along the targeted area. The method includes directing a second fluid flow from the second fan along the targeted area. The direction of the second fluid flow is different than the direction of the first fluid flow. Also, a turbulent fluid flow is created at least partially based on the first fluid flow, the second fluid flow, or a combination thereof.

Electronic devices, including organic electronic devices, continue to be used more extensively in everyday life. Examples of organic electronic devices include Organic Light-Emitting Diode ("OLED") displays. Due to the sensitivity to moisture and oxygen of the organic materials (e.g., transport materials, emissive materials) and the cathode materials used in organic electronic devices, these devices typically have rigorous package requirements for practical applications. Two types of packaging structures adopted for organic electronic devices include (1) a sealing can with an air gap and solid-state desiccants and (2) a thick metal solder layer directly attached to a common cathode. The sealing may include glass and ceramic materials, metals and metal alloys, other materials that prevent significant diffusion of moisture or oxygen, and combinations thereof. As will be described below, either or both packaging structures may not provide sufficient heat dissipation.
The radiation emission efficiencies of OLED pixels are typically in a range of approximately one to twenty candelas per ampere (1-20 cd/A). For a full-color display with a fifty percent (50%) aperture ratio and with a circular polarizer with approximately forty percent (40%) optical transmission, the pixel current density is in a range of approximately thirty to six hundred milliamperes per square centimeters (30-600 mA/cm2) for an emission intensity of approximately 400 cd/m2. At an operation voltage of approximately five volts (5 V), the corresponding input electric power density is in a range of approximately 0.15-3.0 watts per square centimeter (W/cm2). Aside from the conversion into light energy for light emission, much of the input electrical energy is converted into heat. When thermal conduction from the emission layer to the surroundings is not sufficient, substantial panel heating will occur.
A conventional active matrix ("AM") driven device includes a common cathode. This common electrode layer can be subjected to high current density when the display size is large or when the emission intensity increases above certain levels. In such cases, if the heat flowing from the radiation-emitting region to the ambient air is insufficient, a significant temperature rise will also take place in the device. In particular, the operation lifetime of OLED devices is dependent on operation temperatures. For example, devices with emissive layers using poly(phenylenevinylene) (PPV) derivatives with yellow or orange colors, the operation lifetime can be approximately 35 times shorter at 80° C. than at 25° C. Other electronic devices may experience reduced lifetimes due to higher operating temperature.
In a conventional OLED device, the common cathode can be covered by an epoxy layer and glass sheet. Another conventional OLED device can be covered by a metal cap that has a desiccant. The metal cap is attached using an adhesive. These OLED devices may have thermal resistance coefficients that are typically greater than 150° C. cm2/W . The corresponding temperature rise of the radiation-emitting electronic components could be higher than 10° C. when operating at 200 cd/m2 for a display having an area of approximately 3-6 cm2. Outdoor display applications and lighting panels can have emission intensities of 500-2000 cd/m2 and 2000-5000 cd/m2, respectively. AM-driven OLED displays in such applications may not be stably operated at such high brightness levels, and the device temperature may not even be stabilized due to insufficient heat flow out of the device (a phenomenon known as thermal run-off).
Heat dissipation issues are not unique to organic electronic devices. Inorganic (e.g., silicon-based) integrated circuits ("ICs") can generate significant amounts of heat. Most notable are microprocessors (e.g., Intel Pentium™, AMD Athlon™, IBM PowerPC™ processors) due to their power requirements.

Electronic device having a temperature control system


A method for producing laterally varying multiple diodes and their device embodiment are presented herein. As demonstrated, multiple resonant tunneling diodes are fabricated together utilizing a single epitaxial structure. Shallow, ion-implanted regions having varying depths, dx, define the collector contacts. Each diode is isolated electrically from the others by methods such as conventional mesa etching into the emitter layer. The varying depths, dx, provide means for varying the peak voltage of each individual diode. The peak voltage strongly depends on the depths, dx, because it comprises a space charge region where the electric field is high, and therefore the voltage drop is high. The invention disclosed herein is useful in applications such as high-speed circuits such as comparators, analog to digital converters, sample and hold circuits, logic devices, and frequency multipliers.

The present invention is concerned with apparatus including semiconductor devices such as diodes. In particular, this invention relates to integrated multiple diodes, and more particularly to resonant tunneling diodes and systems utilizing resonant tunneling diode circuits with multistable states.
A diode is a semiconductor device having a non-linear voltage-current relation. Diodes are important solid-state devices and have many electronic applications. The tunnel diode is a variety of diode with the unusual characteristic of negative differential resistance. Negative differential resistance is a voltage-current behavior where, over certain voltage ranges, increasing the voltage applied across the diode leads to decreased current carried through the diode. For certain voltage ranges, however, current flows relatively freely through the diode. In contrast, for most devices, increasing the voltage applied across the diode, within operating parameters, leads to increasing current regardless of the voltage range. Tunnel diodes, in general, have a number of applications, including high frequency oscillator circuits and high frequency electronic switches.
One type of tunnel diode is the double barrier tunnel diode, which generally includes a quantum well with thin barrier layers on either side. This structure is known as a double barrier structure and typically lies between two injection layers. The double barrier structure serves as an energy barrier to the flow of electrons that can be overcome only under certain conditions. Fulfillment of these conditions results in a negative differential resistance characteristic of interest over a range of external applied bias voltages. Electrons are injected into the double barrier structure from the conduction band of one of the injection layers under an internal electric field produced by the applied external bias voltage. The applied voltage increases the energy of the injected electrons such that they satisfy the resonant tunneling condition of the quantum barrier. Under such voltage conditions, the resonance condition is satisfied and an incoming electron has the same energy as an energy state of the quantum well. This condition enables electrons to tunnel through double barrier structure. As the bias voltage is increased further, the energy levels no longer match the energy state of the quantum well and the resonance condition is no longer satisfied. At this point the current decreases, resulting in the negative differential resistance effect.
Of particular interest are quantum well devices having current voltage characteristics including multiple negative differential resistance regions. Using traditional methods to achieve multiple negative differential resistance regions required complex circuitry. Therefore, development of a simpler, integrated circuit exhibiting multiple negative resistance regions was desirable. Such multiple regions may be obtained from a plurality of resonant states of a quantum well or from stacking several double barrier structures wells together. However, the resulting devices typically require much higher voltages corresponding to excited states as compared to the resonant voltage of a single quantum well.
In furtherance of the continuing trend towards miniaturization and increased functional density in electronic devices, much attention has been directed toward resonant-tunneling devices as characterized by operation involving a particular carrier energy coinciding with a particular quantized energy level in a potential well. Extensive literature has been developed surrounding both the theoretical and practical device aspects as surveyed, e.g., by:
F. Capasso et al., xe2x80x9cResonant Tunneling Through Phenomena . . . in Superlattices, and Their Device Applicationsxe2x80x9d, IEEE Journal of Quantum Electronics, Vol. QE-22 (1986), pp. 1853-1869.
Also, noting that resonant-tunneling devices may be made as diodes and as transistors; see, e.g.,
E. R. Brown et al., xe2x80x9cMillimeter-band Oscillations Based on Resonant Tunneling in a Double-barrier Diode at Room Temperaturexe2x80x9d, Applied Physics Letters, Vol. 50 (1987), pp. 83-85;
H. Toyoshima et al., xe2x80x9cNew Resonant Tunneling Diode with a Deep Quantum Wellxe2x80x9d, Japanese Journal of Applied Physics, Vol. 25 (1986), pp. L786-788;
H. Morkoc et al., xe2x80x9cObservation of a Negative Differential Resistance Due to Tunneling through a Single Barrier into a Quantum Wellxe2x80x9d, Applied Physics Letters, Vol. 49 (1986), pp. 70-72;
F. Capasso et al., xe2x80x9cResonant Tunneling Transistor with Quantum Well Base and High-energy Injection: A New Negative Differential Resistance Devicexe2x80x9d, Journal of Applied Physics, Vol. 58 (1985), pp. 1366-1368;
N. Yokoyama et al., xe2x80x9cA new Functional, Resonant-Tunneling Hot Electron Transistor (RHET)xe2x80x9d, Japanese Journal of Applied Physics, Vol. 24 (1985), pp. L853-L854;
F. Capasso et al., xe2x80x9cQuantum-well Resonant Tunneling Bipolar Transistor Operating at Room Temperaturexe2x80x9d, IEEE Electron Device Letters, Vol. EDL-7 (1986), pp. 573-575;
T. Futatsugi et al., xe2x80x9cA Resonant-Tunneling Bipolar Transistor (RBT): A Proposal and Demonstration for New Functional Devices with High Current Gainsxe2x80x9d, Technical Digest of the 1986 International Electron Devices Meeting, pp. 286-289;
T. K. Woodward et al., xe2x80x9cExperimental Realization of a Resonant Tunneling Transistorxe2x80x9d, Applied Physics Letters, Vol. 50 (1987), pp. 451-453;
B. Vinter et al., xe2x80x9cTunneling Transfer Field-effect Transistor: A Negative Transconductance Devicexe2x80x9d, Applied Physics Letters, Vol. 50 (1987), pp. 410-412;
A. R. Bonnefoi et al., xe2x80x9cInverted Base-collector Tunnel Transistorsxe2x80x9d, Applied Physics Letters, Vol. 47 (1985), pp. 888-890;
S. Luryi et al., xe2x80x9cResonant Tunneling of Two-dimensional Electrons through a Quantum Wire: A Negative Transconductance Devicexe2x80x9d, Applied Physics Letters, Vol. 47 (1985), pp. 1347-1693; and
S. Luryi et al., xe2x80x9cCharge Injection Transistor Based on Real-Space Hot-Electron Transferxe2x80x9d, IEEE Transactions on Electron Devices, Vol. ED-31 (1984), pp. 832-839.
Of particular interest are integrated devices having multiple negative differential resistance current-voltage characteristics in order to obtain circuits with multistable states. Multiple resonant tunneling diodes in series are a well-known circuit component for supplying multistable states for digital logic and signal processing. The total voltage can be distributed across the circuit elements in more than one way, depending on the history of the circuit, thus defining the multistable states. For some circuit applications it is preferable to control the total current instead of the total voltage. Also, the total of the voltages across the series of resonant tunneling diodes add together and can become too high for convenient processing by the rest of the circuit. It is natural to then consider a pair of resonant tunneling diodes in a parallel arrangement instead of in series. The most efficient way to do this is to grow one resonant tunneling diode epitaxial structure and then divide it up electrically using lithography. However, two such identical resonant tunneling diodes in parallel are basically equivalent to one resonant tunneling diode with a combined area of the two, unless something is done to differentiate them. The I(V) curves of the two or more resonant tunneling diodes must have different shapes, i.e., the peak and valley voltages differing, not just by a scale factor on the current. Then, they will naturally not behave similarly under the same bias. For example, a given bias voltage might put one resonant tunneling diode near its peak current while the other was near its valley current.
An example of previous methods for obtaining multiple stable solutions by putting two resonant-tunneling diodes in parallel is that of Capasso et al., U.S. Pat. No. 4,902,912 in which the two resonant-tunneling diodes are separated by a resistance consisting of a low doped region between the resonant-tunneling diodes. FIG. 1(a) provides a basic circuit diagram of this concept. Although the current out of the contact exhibits double peaks and multiple stable states for certain voltage differences, the required use of multiple voltage sources increases the complexity of the device. Additionally, the device is not easily adjustable or controllable. An attempt to improve on the concept developed by Capasso et al. was made by J. Soderstrom and T. Anderson, as discussed in Electron Device Letters, Vol. 9, No. 5, May 1988. FIG. 1(b) provides a basic circuit diagram of this concept. Soderstrom and Anderson introduced two resistors in series with the resonant-tunneling diodes. By choosing the resistors properly, they caused the circuit to produce a double peak curve. However, this concept has the disadvantage that the resistors introduce hysteresis, which causes the presence of different peak voltages for forward and backward voltage sweeps, and also decreases the speed of the device due to the RC time constant. The structure of Soderstrom and Anderson use lightly doped regions in order to vary the resistance for each of the diodes.
Accordingly, it is an object of the present invention to provide an integrated circuit including laterally varying diodes with multiple current-voltage characteristics that can be tailored for multiple stable solutions. Specifically, the diodes utilized for demonstration here are of the resonant tunneling type. It is another object of the present invention to provide apparatus in accordance with the invention, which give examples of its usage.
The present invention provides a plurality of laterally varying diodes and a method for producing them. The plurality of laterally varying diodes includes, in common, an nxe2x88x92 collector region formed on a diode region, with the nxe2x88x92 collector region having a contact surface opposite the diode region and a depth extending from the contact surface to the diode region. Each of the individual diodes includes an independently selectable portion of the depth with an ion-implanted portion. The plurality of laterally varying diodes further including means for substantially electrically isolating each individual diode.
The method for producing a plurality of laterally varying diodes includes the steps of providing a wafer having a diode region and a nxe2x88x92 collector region having a depth; masking the wafer to isolate the effects of ion-implantation to the desired portion of the nxe2x88x92 collector region; ion-implanting the desired portion of the nxe2x88x92 collector region to a desired depth; repeating the masking and ion-implantation steps a desired number of times to produce a desired number of ion-implanted portions in the nxe2x88x92 collector region; and providing means for electrically isolating the individual portions of the diode region and the nxe2x88x92 collector region corresponding to the ion-implanted portions in the nxe2x88x92 collector region.
A second method for producing a plurality of laterally varying diodes includes the steps of providing a wafer having a diode region and a nxe2x88x92 collector region having a depth; masking a portion of the nxe2x88x92 collector region; etching the non-masked portion of the nxe2x88x92 collector region to desired depth; repeating the masking and etching steps a for a desired number of portions of the nxe2x88x92 collector region; uniformly ion-implanting the desired nxe2x88x92 collector regions; and providing means for electrically isolating the individual portions of the diode region and the nxe2x88x92 collector region corresponding to the ion-implanted portions in the nxe2x88x92 collector region.
The present invention may be used to develop a variety of diode types. It is discussed herein in terms of the provision of a plurality of laterally varying resonant tunneling diodes.


A process control method for color quality control maintains a preselected developed mass per unit area (DMA) of black solid area by adjusting the development field during run-time operation. In order to estimate the DMA of a solid black control patch, which is outside the sensing range of an infra-red densitometer (IRD), an estimation technique is employed which accounts for system changes due to adjustment of the development field. The estimation technique includes generating two or more test patches, using a patch generator, which have DMA readings within the sensing range of the IRD. The DMA readings and corresponding development voltages of the test patches are sensed and used to calculate a developability curve. The developability curve is projected into a region beyond the sensing range of the IRD. From the developability curve, the DMA of the solid black control patch is estimated and employed in a closed feedback loop to return the system to the preselected DMA by adjusting the development field. Development field control provides faster response to toner density changes than toner concentration control, and thus, results in better color quality control.

The present invention relates to electrophotographic printing and more specifically to a method for maintaining a preselected developed mass per unit area (DMA) of black solid area in a xerographic printer by adjusting the development field of the system during run-time operation. More specifically, the invention relates to a method where the DMA of a black solid area control patch, which cannot be sensed directly using a toner density sensor, is estimated to allow for improved accuracy in the regulation of the DMA by adjusting the development field.
In the well-known process of electrophotographic printing, a charge retentive surface, typically known as a photoreceptor, is electrostatically charged, and then exposed to a light pattern of an original image to selectively discharge the surface in accordance therewith. The resulting pattern of charged and discharged areas on the photoreceptor form an electrostatic charge pattern, known as a latent image, conforming to the original image. The latent image is developed by contacting it with a finely divided electrostatically attractable powder, known as "toner". Toner is held on the image areas by the electrostatic charge on the photoreceptor surface. Thus, a toner image is produced in conformity with a light image of the original being reproduced. The toner image may then be transferred to a substrate or support member such as paper, and the image affixed thereto to form a permanent record of the image to be reproduced. Subsequent to development, excess toner left on the charge retentive surface is cleaned from the surface. The process is useful for light lens copying from an original document or for printing electronically generated or stored originals such as with a raster output scanner (ROS), where a charged surface may be imagewise discharged in a variety of ways.
In such electrophotographic printing, the step of conveying toner to the latent image on the photoreceptor is known as "development." The object of effective development of a latent image on the photoreceptor is to convey toner particles to the latent image in a controlled manner so that the toner particles effectively adhere electrostatically to the charged areas on the latent image. A commonly used technique for development is the use of a two-component developer material, which comprises, in addition to the toner particles which are intended to adhere to the photoreceptor, a quantity of magnetic carrier beads. The toner particles adhere tribolelectrically to the relatively large carrier beads, which are typically made of steel. When the developer material is placed in a magnetic field, the carrier beads with toner particles thereon form what is known as a magnetic brush, wherein the carrier beads form relatively long chains which resemble the fibers of a brush. This magnetic brush is typically created by means of a "developer roll." The developer roll is usually in the form of a cylindrical sleeve rotating around a fixed assembly of permanent magnets. The carrier beads form chains extending from the surface of the developer roll, and the toner particles are electrostatically attracted to the chains of carrier beads. When the magnetic brush is introduced into a development zone adjacent the electrostatic latent image on the photoreceptor, the electrostatic charge on the photoreceptor will cause the toner particles to be pulled off the carrier beads and onto the photoreceptor.
An important variation to the general principle of development is the concept of "scavengeless" development. In a scavengeless development system, toner is detached from a donor roll by applying an AC electric field to self-spaced electrode structures, commonly in the form of wires positioned in the nip between a donor roll and photoreceptor. This forms a toner powder cloud adjacent thereto. Because there is no physical contact between the development apparatus and the photoreceptor, scavengeless development is useful for devices in which different types of toner are supplied onto the same photoreceptor such as in "tri-level", "recharge, expose and develop", "highlight", or "image on image" color xerography.
Typically, area development control is established by creating toner control patches of single desired density. Control patches are created using an alternate light source, such as a patch generator, to properly discharge the photoreceptor to the proper development field. The actual developed mass per unit area (DMA) of the toner on the control patches is then optically measured to determine the effectiveness of the printing process in placing the toner on the print sheet. Typically, a reflection infra-red densitometer is used for determining the density of the toner on a control patch. Both solid area and halftoned control patches of varying densities, including a black solid area control patch, can be used to assure color quality control. Solid patches are represented on a Solid Area Developability Curve and halftoned patches are represented on a Tone Reproduction Curve (TRC).
Direct measurement of a black solid area control patch with a reflection infra-red densitometer (IRD) is problematic in many xerographic copiers and printers. The reflection IRD is limited in the range of DMA that it can sense on a control patch. The reflection IRD cannot sense the black full developed mass of toner on a control patch when the developed mass is beyond a given limit. Typically this limit is below the black mass necessary to achieve the desired image darkness. In response to this limitation, the DMA of black solid area control patches is often estimated using a single lower density test patch created by the patch generator.
With reference to FIG. 1, a plot of DMA versus development voltage V.sub.dev is provided to illustrate estimation techniques of the prior art. Typically, xerographic copiers and printers are equipped with a nominal developability curve, as illustrated in FIG. 1. The nominal developability curve provides the toner density target for the system at a given development voltage. Due to environmental conditions, such as changes in humidity, and/or consumption of toner, the developability curve often changes slope from the nominal curve. For example, regular consumption of toner at a rate greater than replenishment may result in a lower toner concentration (TC), and therefore, a higher triboelectrification of the toner. This condition results in a visibly "lighter" solid black area in printed images, i.e. a lower DMA at a given development voltage. Such a condition is represented by a developability curve with a slope which is less than the slope of the nominal developability curve. Because the reflection IRD cannot sense such a change in the DMA of the solid black control patch, the DMA of the control patch must be estimated using extrapolation.
The conventional method of adjusting toner density consists of adding or removing toner from the development housing, i.e. adjusting the TC. When the TC is adjusted and the development field is held constant, the developability curve is fixed at a development onset V.sub.DO, as shown in FIG. 1. Therefore, adjusting the toner concentration simply rotates the developability curve by changing its slope with a fixed development onset of V.sub.DO. Because the change in DMA of the solid black area control patch cannot be sensed directly with an IRD, the DMA at the reduced TC must be estimated. The estimation technique of the prior art consists of generating a test patch using the patch generator at a DMA that is within the sensing range of the IRD. The DMA of the test patch is sensed using the IRD and the development voltage V.sub.pgen of the test patch is sensed using an electrostatic voltmeter (ESV). The sensed DMA reading of the test patch is then compared to the preselected DMA reading of the nominal curve at the development voltage V.sub.pgen. From this data, the DMA of a solid black area control patch along the reduced TC developability curve is estimated. Based on the estimated DMA of the black solid area control patch, TC is adjusted to return the black solid area of the system to its preselected toner density.
Adjusting TC to correct the toner density of black solid area necessarily has a much slower response than adjusting other parameters, such as development field. Such a slow response especially adversely affects the maintenance of color quality control. Adjusting the development field in order to maintain toner density provides a much faster response. Accordingly, there is a need for a black solid area estimation technique which reliably compensates for system changes.
It is an object of the present invention to provide a new and improved method for maintaining a preselected DMA of solid black area by adjusting development field and estimating the DMA of a solid black control patch which overcomes the above-referenced problems and others.

Method and apparatus for adaptive black solid area estimation in a xerographic apparatus


In a bus circuit which includes a plurality of signal lines, insertion pattern xcex1, which provides repeaters in only an odd numbered series of signal lines, and insertion pattern xcex2, of which the segment length is equal to that of pattern xcex1 and which provides repeaters to only an even numbered series of signal lines, are arranged in an alternating manner in accordance with the length of the signal lines. As a result, the segments during which data signals on the neighboring signal lines run together in opposite phases become half the entire length of the signal lines. Therefore, this bus circuit can prevent the operational speed from becoming slowed.

1. Field of the Invention
The present invention relates to a bus circuit, in particular, to a bus circuit which includes a plurality of signal lines.
2. Description of the Background Art
A semiconductor integrated circuit device is formed of a plurality of circuit blocks represented by an operation unit or a memory. Data exchange among circuit blocks within the semiconductor integrated circuit device is, in general, carried out by using a signal line.
FIG. 11 is a block diagram of a conventional bus circuit within a semiconductor integrated circuit device.
Referring to FIG. 11, a plurality of circuit blocks 3, respectively, have input/output circuits 2. Respective input/output circuits 2 are connected to a signal line 1. Input/output circuits 2 include drivers 6 and receivers 7. Drivers 6 output data from circuit blocks 3 to signal line 1. Receivers 7 receive data from signal line 1. Here, though three circuit blocks are shown in FIG. 1, a plurality of additional circuit blocks may be included.
In order to prevent a plurality of circuit blocks 3 from transmitting data at the same time, circuit blocks 3 cannot transmit data unless the usage right for signal line 1 is acquired. Arbitration of the usage right of the signal line 1 among the circuit blocks is carried out by a dedicated control circuit (not shown).
In FIG. 11, circuit blocks 3 which have, respectively, one input/output circuit 2 are connected to one signal line 1. 1 bit of data is transmitted on one signal line. Conventionally, a data processing unit of a circuit block 3 is not 1 bit but is 32 bits, or more. Accordingly, in practice there are 32, or more, signal lines 1 within the bus circuit and a circuit block 3 has a plurality of input/output circuits 2 connected to respective signal lines.
In recent years the process dimensions of a semiconductor integrated circuit device have become scaled and, as a result, the amount of data which can be processed by a circuit block 3 within the bus circuit at one time has increased from 32 bits to 64 bits or, further, to 128 bits, or more.
FIG. 12 is a circuit diagram of a driver 6 in FIG. 11.
Referring to FIG. 12, driver circuit 6 includes inverters 62, 63, a NAND gate 61 and a NOR gate 64. Inverter 62 includes a P channel MOS transistor 621 and an N channel MOS transistor 622. A driver signal EN is a signal which is inputted to NAND gate 61 and is inputted to NOR gate 64 via inverter 63 and is a signal which is inputted from the outside in order to activate driver 6.
In a circuit block 3 which has acquired the bus usage right, driver activation signal EN is set to an active condition (H level). Therefore, driver 6 outputs a signal of H level from driver 62 when data signal D is at H level and outputs a signal of L level when data signal D is at L level. In addition, in a circuit block 3 which has not acquired the bus usage right, driver activation signal EN is set at L level. Therefore, P channel MOS transistor 621 and N channel MOS transistor 622 in driver 6 are both turned off and, as a result, driver 6 is converted to a high impedance condition.
On the other hand, a receiver 7 receives the entirety of the data on signal line 1. The received data is transmitted to circuit block 3 and the circuit block determines whether or not the received data is utilized. Through the above operation, data exchange is carried out among circuit blocks 3 within the bus circuit.
FIG. 13 is a circuit diagram showing 3 signal lines for transmitting data signals among a plurality of signal lines within the bus circuit.
Referring to FIG. 13, a signal line BUS2 is a signal line neighboring signal lines BUS1 and BUS3. Signal line BUS2 transfers a data signal D, signal lines BUS1 transfers a data signal Dnxe2x88x921 and signal lines BUS3 transfers a data signal Dn+1, respectively. In addition, drivers DR1 to DR3 are, respectively, connected to one end of signal lines BUS1 to BUS3. Furthermore, receivers RV1 to RV3 are, respectively, connected to the other end of signal lines BUS1 to BUS3.
Here, the wire capacitance which is driven when driver DR2 outputs data signal Dn to signal line BUS2 is described.
First, the case where data signals Dn+1 and Dnxe2x88x921 change while in a phase opposite to that of data signal Dn is described.
At this time, capacitance Cm between wires for data signal Dn and data signal Dn+1 appears twice as large as it actually is due to the Miller effect because when the potential of capacitance Cm between wires at one terminal C1 changes from power source potential VDD to ground potential GND, the potential of capacitance Cm between wires at the other terminal C2 changes from ground potential GND to power source potential VDD. Therefore, the amount of relative potential change from terminal C1 to terminal C2 becomes 2VDD.
In the same manner, capacitance Cm between wires for data signal Dn and Dnxe2x88x921 appears twice as large as it actually is.
From the above, a wire capacitance Cn that must be driven in order for driver DR2 to output data signal Dn onto signal line BUS2 is given in the following equation (1).
Cn=2Cm+2Cm+CL=4Cm+CLxe2x80x83xe2x80x83(1)
wherein CL is a capacitance between the signal line and the ground.
Next, the case where data signals Dn+1 and Dnxe2x88x921 change while in the same phase as that of data signal Dn is described.
At this time, potential difference between terminals of capacitance Cm between wires does not occur. Accordingly, wire capacitance Cn that must be driven in order for driver DR2 to output data signal Dn onto signal line BUS2 is given in the following equation (2).
Cn=CLxe2x80x83xe2x80x83(2)
Next, the case where data signals Dn+1 and Dnxe2x88x921 do not change and only data signal Dn changes is described.
At this time, the Miller effect does not occur with capacitance Cm between wires. Accordingly, wire capacitance Cn that must be driven in order for driver DR2 to output data signal Dn onto signal line BUS2 is given in the following equation (3).
Cn=Cm+Cm+CL=2Cm+CLxe2x80x83xe2x80x83(3)
In the conventional bus circuit, since capacitance CL between the signal line and the ground is larger than capacitance Cm between wires, the transmission speed of a data signal is not affected by a change of a data signal on the neighboring signal line. However, in recent years, miniature processing technology for signal lines has progressed and, therefore, signal line pitches have become narrower. As a result, capacitance Cm between wires has become larger than capacitance CL between the signal line and the ground.
Here, a change of transmission speed of a data signal in the case that a data signal on a neighboring signal line has changed relative to data signal Dn on signal line BUS2 in FIG. 13 is described.
The amount of time for data signal Dn to change from power source potential VDD or ground potential GND to VDD/2 is defined as a data signal transmission time xcex94t. Data signal transmission time xcex94t is approximated in the next equation (4).
xcex94t=VDDxc3x97Cn/ID/2xe2x80x83xe2x80x83(4)
wherein ID is an average current driving force of the driver.
For example, it is assumed that capacitance Cm between wires/ground capacitance CL is 2. In the case that data signals Dn+1 and Dnxe2x88x921 change while in a phase opposite to that of data signal Dn, a data signal transmission time xcex94t1 of data signal Dn is given in the following equation from equations (1) and (4).
xcex94t1=VDDxc3x97(4Cm+CL)/2ID=9VDDxc3x97CL/2IDxe2x80x83xe2x80x83(5)
In addition, in the case that data signals Dn+1 and Dnxe2x88x921 change while in the same phase as that of data signal Dn, a data signal transmission time xcex94t2 of data signal Dn is given in the following equation from equations (2) and (4).
xcex94t2=VDDxc3x97(CL)/2ID=VDDxc3x97CL/2IDxe2x80x83xe2x80x83(6)
From the above results, the maximum value of a data signal transmission time xcex94t of data signal Dn may be nine times larger than the minimum value thereof due to a change of the data signal on a signal line neighboring signal line BUS2.
The operational speed of a semiconductor integrated circuit device is determined by the slowest operation case.
As a result of the above, though scaled physical dimension of signal lines reduces the capacitance between the signal line and the ground, it increases the capacitance between wires and slows the operational speed.
A measure for solving this problem has been proposed in Japanese Patent Laying-Open No. 8-102491(1996).
FIG. 14 is a circuit diagram showing three signal lines for transmitting data signals among a plurality of signal lines within a bus circuit.
Referring to FIG. 14, in this bus circuit 100, a repeater RP0 is inserted only into signal line BUS2 of signal lines BUS1 to BUS3 of which the signal line length is L. Repeater RP0 is inserted into a place halfway from the start of the signal line length L. The other parts of the circuit configuration are the same as in FIG. 13. Repeater RP0 inverts and outputs inputted data signal Dn.
In bus circuit 100, segments where data signals of neighboring signal lines BUS1 to BUS3 are in opposite phases occupy half of the signal line length. Accordingly, a slowing of operational speed of the bus circuit can be prevented.
As described above, in the bus circuit proposed in Japanese Patent Laying-Open No. 8-102491(1996), at least one repeater is inserted into only an odd numbered series of signal lines or into only an even numbered series of signal lines from among a plurality of signal lines. The inserted repeater reduces segments where data signals in opposite phases run at the same time in neighboring signal lines. Therefore, the bus circuit can prevent a slowing of the operational speed.
However, since in the bus circuit proposed in Japanese Patent Laying-Open No. 8-102491(1996) a repeater is inserted into only an odd numbered series of signal lines or into only an even numbered series of signal lines from among a plurality of signal lines, only data signals in the signal lines into which repeaters are inserted are slowed. Accordingly, the timing of signal change shifts between a data signal of a signal line into which a repeater is inserted and a data signal of a signal line into which a repeater is not inserted.
By inserting amplifiers, of which the number is equal to the number of inserted repeaters, into a signal line into which no repeaters RP0 are inserted, the shift of the timing of the signal change can be eliminated. For example, by inserting one amplifier to, respectively, signal lines BUS1 and BUS3, the shift of the timing of the signal change of the data signal inputted from receiver RV1 to 3 is eliminated. However, the insertion of the amplifiers increases the power consumption of the bus circuit.
A purpose of this invention is to provide a bus circuit that can prevent a slowing of operational cycle time without a shift of the time of the signal change among the signal lines.
A bus circuit according to this invention includes a plurality of signal lines for transmittig data and repeaters for logically inverting data which are provided for respective signal lines wherein at least one repeater is provided for each signal line so that segments for transmitting data in the opposite phase is restricted to half of the signal line length in neighboring signal lines.
Thereby, capacitance between wires of signal lines is lowered. As a result, the operational speed of the bus circuit is prevented from being slowed.
Preferably, a plurality of signal lines include first segments wherein repeaters are provided only for an odd numbered series of signal lines and second segments, of which the segment length is equal to that of the first segments and wherein repeaters are provided only for an even numbered series of signal lines, and the first segments and the second segments are arranged in an alternating manner in accordance with the signal line length.
Thereby, the circuit design of a bus circuit becomes easy in accordance with the signal line length.
Preferably, the signal line transfers data in one direction.
Preferably, the signal line transfers data in two directions.
Preferably, the signal line is connected to a plurality of circuit blocks.
Preferably, the plurality of circuit blocks are operation units.
Preferably, the plurality of circuit blocks are memories.
A bus circuit design method according to this invention is a bus circuit design method for designing a bus circuit which includes a plurality of signal lines for transmitting data and includes the step of preparing first segments wherein repeaters for logically inverting data are provided only for an odd numbered series of signal lines and second segments, of which the segment length is equal to that of the first segments and wherein repeaters are provided only for an even numbered series of signal lines, the step of determining the numbers of the first segments and the second segments to be arranged in response to the set length of the signal line and the step of alternately placing the first segments and the second segments in accordance with the determined numbers of segments.
As described above according to the present invention, the operational speed of a bus circuit is not slowed by inserting repeaters into the signal lines so that the segments wherein data signals in the opposite phases that run together between neighboring signal lines become half of the signal line length. In addition, the slowing of the operational speed can be prevented by activating only the repeaters which correspond to the direction of the data signal flow even in bi-directional signal lines.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Bus circuit preventing delay of the operational speed and design method thereof


An image measuring system comprises a projection optical system, having a light source for emitting and projecting an illumination light through a light projection optical axis. The system further comprises a photodetection optical system, having an image pickup element, which receives a retroreflection light from an object to be measured through a photodetection optical axis, and a control arithmetic device for processing the data taken by the image pickup element. The projection optical system comprises a light projection unit for directing the light projection optical axis toward the object to be measured and projecting the illumination light, a projection angle changing means for rotating the light projection unit in an elevating and a horizontal direction and for changing a projection angle of the illumination light, and a direction detecting means for detecting a direction angle of the light projection optical axis with respect to the photodetection optical axis.

The present invention relates to an image measuring system for use in the indoor layout measurement or the measurement in the field of, e.g., the construction of buildings or the like.
As a system that performs the measurement in a predetermined target area or the measurement of an object to be measured, the acquisition of an image of a target area or the acquisition of an image of the object to be measured, and the association of a measurement result and an image, there is an image total station or a 3D image scanner.
Although the image total station has exclusive distance measuring function and angle measuring function and can superimpose the distance measurement and angle measurement data on an acquired image, a structure of the total station is fundamental, and the structure is complicated, for example, the total station has a vertical rotation axis or a horizontal rotation axis, and requires an angle detector that detects a rotational angle of the vertical rotation axis and the horizontal rotation axis or the like, hence the total station is an expensive apparatus.
Further, although the 3D image scanner can instantaneously measure a distance of a point, the 3D laser scanner requires a special light source that emits, e.g., a pulse laser beam or the like, also requires a vertical rotation axis and a horizontal rotation axis like the total station, has a complicated structure, and has a problem that the maintenance or the calibration is complicated.


A method and mechanism for managing data in a distributed computing system. A television system is configured to convey audio/video/interactive data to receiving devices. Data conveyed to the receiving devices are structured as modules, with a main directory module indicating those modules which make up, or are used by, a particular application. Changes to data being conveyed to receiving devices are initially indicated by conveying delta directory modules to the receiving devices which identify updates to a corresponding main directory module. Changes indicated by a delta directory module are applied to the corresponding main directory module, which in turn may effect changes in the data used by the application. Delta directories may generally only include sufficient information to identify the changes and may be smaller than the corresponding main directory.

1. Field of the Invention
The invention relates to distributed computing systems and, more particularly, to management of data which is delivered to and/or retrieved by an interactive television receiver.
2. Description of the Related Art
Interactive television systems provide a means to deliver interactive content as well as ordinary television audio and video to a large number of subscribers. Programs broadcast by these systems may incorporate television audio and video, still images, text, interactive graphics and applications, and many other components. They may also provide a number of services, such as commerce via the television, electronic program guides (EPGs), video-on-demand, and other interactive applications to viewers. The interactive content of the interactive television signal may therefore include application code, data associated with the audio and video, control signals, raw data and many other types of information. This information may be combined into one or more signals for transmission to subscriber receivers.
The interactive functionality of the television is generally controlled by an integrated receiver/decoder (IRD), or similar mechanism, which is frequently incorporated into a set-top box. The IRD receives the signal provided by a broadcast service provider or system operator and separates the interactive portion from the audio-video portion. The IRD uses the interactive information to, for example, execute an application while the audio-video information is transmitted to the television. The IRD may also combine interactive graphics or audio generated by the interactive application with the received audio-video information.
Interactive content such as application code or information relating to television programs may be broadcast in a cyclical or repeating format. The pieces of information which are broadcast in this manner form what may be referred to as a "carousel." A carousel may include multiple modules of data, including a directory module which identifies the particular modules which correspond to a given application. While a single carousel may be transported as a contiguous data stream, it is also possible to multiplex two or more carousels into a single data stream. As an alternative or adjunct to using a carousel format, some systems may utilize a return path to request and/or receive interactive content.
The pieces of information, or data objects, in a carousel may be intended to be combined in a single object data stream in order to form a program. This program may also contain, or be associated with, streaming data such as audio or video. For example, an interactive television game show may combine television audio and video with interactive content such as application code which allows users to answer questions. Another example would be a news program which combines audio and video with application code that inserts current stock prices in a banner at the bottom of the screen. Still further, an interactive application may provide services such as shopping or Web browsing.
As noted above, interactive television applications may consist of a set of program modules including a directory module which identifies the modules which are part of the application. Security for the executable application may include attaching a signed certificate to directory modules and signing the directory content. In addition, the integrity of modules may be monitored by including respective hash values in the directory module. At a receiver the certificate and hash values may then be checked using various verification procedures. Applications which have been verified may then be executed.
Because applications may include data which is dynamic in nature, managing such data presents a variety of challenges. In order to effectively manage changes to data modules, a number of approaches may be used. One approach includes tagging modules with version numbers. By monitoring the version numbers of modules, a receiver may detect a new version of a module has been received. However, given there may be many modules which must be monitored, such an approach is not particularly efficient. Further, if a particular module is no longer being broadcast (i.e., the change in this case is the removal of the module from the carousel), simply monitoring version numbers of received modules may not be an effective means of detecting such a change.
Another approach to managing changes to modules involves monitoring directories. For example, as noted above a directory module may identify the modules which make up a particular carousel. Such a directory may also indicate the current version of each of those modules. If a module changes, a new directory may be broadcast and processed by the receiver. Examination of the directory may then reveal changes to modules in the corresponding carousel. However, directory modules themselves may be relatively large and the processing, verification, and analyzing of such modules may not be trivial. In addition, in order to ensure receivers are notified of changes without undue latency, these directory modules must be broadcast with a relatively frequently. Consequently, such an approach may consume an inordinate amount of bandwidth.
In view of the above, an efficient method and mechanism for managing data is desired.

System for managing data in a distributed computing system