The liquid and gas volumetric flow rates of a multiphase fluid mixture are measured by pumping the fluid mixture with a positive displacement pump such as a multi-helical lobed rotor type pump, measuring the pressure differential, temperature differential and power input to the pump and calculating the liquid volumetric flow rate and gas volumetric flow rate based on the measured parameters, pump coefficients for friction horse power, fluid leakage and heat transfer, together with predetermined values of liquid and gas specific heat, density and polytropic compression exponent. Approximate flow rates of gas and liquid may be determined by monitoring the pump power input and fluid pressure and temperature changes across the pump with sufficient accuracy for applications such as in pumping crude oil and natural gas mixtures from production wells.

1. Field of the Invention
The present invention pertains to a method of measuring multiphase (liquid and gas) fluid flow based on pressure and temperature measurements taken across a pump which is pumping the multiphase fluid and based on the power input to the pump.
2. Background
My U.S. Pat. Nos. 4,852,395, issued Aug. 1, 1989, and 5,244,372, issued Jul. 6, 1993, both assigned to the assignee of the present invention, pertain to multiphase fluid flowmeters for measuring mixtures of gas, oil and water, for example, with a high degree of accuracy. In certain flowmeter applications, such as surface and subsea oil production wells and similar flow measuring requirements, the degree of accuracy required for the flow rates of the various fluid components is not as great as that provided for by the meters described in the above-mentioned patents. Moreover, in certain fluid flow measuring applications, such as remotely located and subsea oil production wells, the placement of a complex flowmeter in the production fluid flowline is difficult and expensive.
On the other hand, in many instances multiphase fluids require to be transferred by mechanical pumps, such as in crude oil production operations. The present invention provides an improved flow measurement method which utilizes measurements taken of multiphase fluid flow through a pump including power input to the pump. The method provides a suitable degree of accuracy which may be used as the primary fluid flow measurement technique in many fluid flow measuring applications.


A programming station for use in programming and servicing two-way radios that include replaceable hardware elements. Both user-only and programming station-assisted steps are simultaneously displayed in a predetermined order. The steps may only be accomplished in a fixed allowed order.

Two-way radios are becoming increasingly sophisticated. Many such radios now realize many operating functions and features through provision of an on-board microprocessor. For example, some models of the Spectra land mobile radio, manufactured by Motorola, Inc., do not include any internal adjustable components such as potentiometers or coils. Instead, all RF and signalling parameters are controlled by an on-board microprocessor.
These increasingly sophisticated radios have given rise to a concurrent need for a similarly sophisticated means of servicing the radio, particularly in conjunction with the replacement of hardware elements in the radio.

Radio component replacement/programming device


An example process described herein may involve capturing an image including a document; identifying a first part of the document, wherein the first part of the document is identified based on detecting an outline of the first part of the document; analyzing a first region of the image determined in relation to the first part of the document to detect a second part of the document based on an outline of the second part of the document; identifying the second part of the document based on detecting the first part of the document and analyzing the first region; combining the first part of the document with the second part of the document to generate object data associated with the document, wherein the object data includes data representative of a gap between the first part of the document and the second part of the document; and performing an action related to the object data.

A digital image may include an object that can be identified using one or more image processing techniques. The one or more image processing techniques may enable feature extraction, classification, pattern recognition, and/or the like to identify the object. The one or more image processing techniques may be configured to recognize the object by analyzing the digital image to detect particular features or known features of the object.

This patent is subject to a terminal disclaimer.

Detecting a fragmented object in an image


An anchor having a sleeve, a bolt which passes through the sleeve and at least one expansion element that is positioned in front of the sleeve and that is axially supported on the sleeve, whereby the bolt has an expansion area for the expansion element, is provided. According to the invention, it is provided for the sleeve to have a wavy shape with axial wave peaks in which the outer radius of the sleeve as well as the inner radius of the sleeve each have a maximum, and with wave valleys in which the outer radius of the sleeve as well as the inner radius of the sleeve each have a minimum.

German utility model DE 20 2009 013641 U1 shows an undercut anchor for fastening cladding panels made of natural stone to a substrate. This anchor has a wave-shaped, closed expansion ring as an expansion element.
German patent application DE 10 2007 060956 A1 discloses an expansion anchor for joining a stone slab to a concrete slab, whereby the expansion anchor has an expandable element that can be expanded when it is pushed onto an expansion body. The expansion anchor also has a force-transmitting element with which the force used to push the expandable element onto the expansion body can be transmitted, whereby the force-transmitting element is stiffer in the force-transmission direction than perpendicular thereto. For example, the force-transmitting element can be a sleeve with a cylindrical center hole and a wave-shaped outer circumference in the circumferential direction.
German utility model DE 8416683 U1 shows an expansion plug whose compressive zone is a plastic sleeve with external longitudinal ribs as the anti-twist protection means. Other compressible sleeves with external ribs are disclosed in German patent application DE 10 2006 053226 A1.
German patent application DE 10 2004 010727 A1 shows an expansion anchor in which expansion tabs separated by slits are provided as the expansion elements. At the edges of these expansion tabs, which are formed on the slits, the expansion elements run tangentially to the longitudinal axis of the anchor, that is to say, they project there towards the outside.
European patent application EP 2848825 A1 proposes that at least one web which projects into the interior of the sleeve and which forms a local wall thickening be provided on the expansion elements configured as expansion tabs, and it also proposes that a matching groove be provided on the bolt, said groove at least partially accommodating the web prior to the expansion of the expansion tabs. Since the wall is locally thicker at the web, a particularly large maximum radial extension of the expansion elements and thus a very good anchoring can be achieved during the expansion.
German patent specification DE 19538898 C2 discloses an impact anchor having an additional expansion sleeve. This expansion sleeve has a web that is inserted radially through the body of the plug. When the impact anchor is put in place, an impact tool is placed onto the web and the action of the impact tool onto the web pushes the expansion sleeve axially forward. For stabilization purposes, the web situated inside the body of the plug can be configured so as to be wave-shaped.
German patent specification DE 3336168 C2 shows a clamping plug, whereby the outer surface of the clamping area of the clamping plug can be provided with ribbing that can prevent the clamping plug from being pulled too easily out of the masonry since the ribbing gives rise to a higher friction factor. As an alternative, instead of ribbing, it is also possible to provide a wavy shape having wavy structures that encircle the plug like rings.
U.S. Pat. No. 4,753,559 A shows a two-shell expansion sleeve for a rock bolt having a wavy shape with wavy structures that encircle the expansion sleeve like rings.


An automatic transaction system has a cellular phone of a customer and an automatic teller machine (ATM) which can directly communicate with the cellular phone by infrared communication. When the customer performs a transaction by the ATM, transaction information such as transfer information registered in the cellular phone is directly inputted to the ATM and the ATM executes a transaction process by the transaction information which was directly received. When transaction data which is used in the transaction by the ATM is inputted once, transaction time in the ATM can be shortened by the simple operation.

1. Field of the Invention
The invention relates to an automatic transaction system for performing a transaction in an automatic transaction apparatus set in a service office of a financial institution or the like by using a personal digital assistant.
2. Related Background Art
In a conventional transaction by an automated teller machine (hereinafter, abbreviated to an ATM) using a cellular phone as a personal digital assistant (hereinafter, abbreviated to a PDA), a customer preliminarily registers a telephone number of his own cellular phone into a financial institution, when the transaction is performed, he preliminarily calls a nearest service office of the financial institution, inputs a kind of transaction, a transaction money amount, an account number, and the like by using a ten-key or the like of his cellular phone, and makes a reservation of the transaction. A main control unit of the service office transfers the inputted information and the telephone number which has automatically been identified to a host computer and inquires about the permission/inhibition of the transaction. If the transaction is permitted, the main control unit accepts the reservation and stores it as transaction reservation information into a memory.
When the customer arrives at the service office to which he had made the reservation, he is detected from the telephone number which is periodically transmitted from the cellular phone and notified of the ATM for performing the transaction by a display plate. When the customer inserts the cellular phone into the ATM, whether or not he is an authorized person is confirmed by the telephone number, the transaction is executed on the basis of the transaction reservation information stored in the memory, and transaction time in the ATM is shortened (for example, refer to JP-A-2001-175783 (page 3, paragraph No. [0012] to page 4, paragraph No. [0020], and FIG. 1)).
However, in the foregoing conventional technique, since the customer preliminarily calls the nearest service office of the financial institution from the cellular phone every transaction, inputs the kind of transaction, the transaction money amount, the account number, and the like, and makes the reservation of the transaction, there is such a problem that in the case where a specific money amount is paid a plurality of number of times or it is necessary to transfer a money amount to the same transfer destination many times, the same contents or the like have to be inputted many times.
Particularly, in the case of a transfer transaction, there is such a problem that since there are many items to be inputted, it takes time to input data and use convenience of the customer is deteriorated.


A method, disclosure relates to for improving detection of true coincidence events and differentiating them from events detected from scattered and random gamma photons, comprises receiving electromagnetic radiation at a plurality of photo detectors that was generated by a scintillating crystal impacted by a gamma photon, and processing data received at a subset of the plurality of photo detectors that are closer to a scintillating crystal, thereby improving a timing coincidence window for detecting a coincidence event.

1. Technical Field
In general, the present disclosure relates to nuclear medical imaging. More particularly, the disclosure relates to Positron Emission Tomography (PET) imaging and accurate estimation of a timing coincidence window in a PET system.
2. General Background of the Invention
Nuclear medicine is a unique specialty wherein radiation emission is used to acquire images that show the function and physiology of organs, bones or tissues of the body. The technique of acquiring nuclear medicine images entails first introducing radiopharmaceuticals into the body—by either injection or ingestion. These radiopharmaceuticals are attracted to specific organs, bones, or tissues of interest. The radiopharmaceuticals produce gamma photon emissions, which emanate from the body and are then captured by a scintillation crystal. The interaction of the gamma photons with the scintillation crystal produces flashes of light or electromagnetic radiation in a different spectrum, which are referred to as "scintillation events." Scintillation events are detected by an array of photo detectors (such as photomultiplier tubes (PMT) of avalanche photodiodes (APD)), and their spatial locations or positions are then calculated and stored. In this way, an image of the organ or tissue under study is created from detection of the distribution of the radioisotopes in the body.
One particular nuclear medicine imaging technique is known as positron emission tomography, or PET. PET is used to produce images for diagnosing the biochemistry or physiology of a specific organ, tumor or other metabolically active site. The measurement of tissue concentration using a positron emitting radionuclide is based on coincidence detection of the two gamma photons arising from a positron annihilation or coincidence event. When a positron is annihilated by an electron, two 511 keV gamma photons are simultaneously produced and travel in approximately opposite directions. Gamma photons produced by a coincidence event can be detected by a pair of oppositely disposed radiation detectors capable of producing a signal in response to the interaction of the gamma photons with a scintillation crystal. Coincidence events are typically identified by a time coincidence between the detection of the two 511 keV gamma photons in the two oppositely disposed detectors; i.e., the gamma photon emissions are detected virtually simultaneously by each detector. When two oppositely disposed gamma photons each strike an oppositely disposed detector to produce a time coincidence event, they also identify a line-of-response (LOR) along which the coincidence event has occurred. An example of a PET method and apparatus is described in U.S. Pat. No. 6,858,847, which patent is incorporated herein by reference in its entirety.
FIG. 1 is a graphic representation of a line of response. A coincidence event 140 occurring in imaged object mass 130 can emit two simultaneous gamma photons (not shown) traveling substantially 180° apart. The gamma photons can travel out of scanned mass 130 and can be detected by block detectors 110A and 110B, where the detection area of the block detector defines the minimum area or maximum resolution within which the position of an incident gamma photon can be determined. Since block detectors 110A and 110B are unable to determine precisely where the gamma photons were detected within this finite area, the LOR 120 connecting block detectors 110A and 110B can actually be a tube with its radius equal to the radius of block detectors 110A and 110B. Similar spatial resolution constraints are applicable to other types of detectors, such as photomultiplier tubes.
In commercial PET, detection of individual 511 keV gamma photons is accomplished by crystal photoelectric absorption whereby the gamma photon's energy is converted to light, or some other electromagnetic radiation having a different frequency, by scintillation crystals contained within a detector. The production of the electromagnetic radiation by the scintillation crystal is known in the art as a scintillation event. Typically, PET photon detectors (photo detectors) are shared amongst an area of crystals to allow a small number of photo detectors to support a larger number of scintillation crystals as shown in FIG. 2.
The detector scintillation crystals are not optimally coupled to the photo detectors in a 1:1 configuration since such an implementation is cost prohibitive for a commercial whole body system. Multiple scintillation crystals can be associated with one photo detector. For example, FIG. 2 illustrates a physical layout of photo detectors 0-8. The photo detectors 0-8 used in a PET block detector can be, for example, PMTs or APDs. In the example illustrated in FIG. 2, APDs are used; however, PMTs or other photo detectors can also be used. Each photo detector is numbered consecutively starting at APD0 at the top left corner of the block. Nine APDs are arranged for detecting light emitted by 100 scintillation crystals.
Ideally, each event detected can be correlated with a corresponding coincidence event; however, in real-world applications, coincidence events are often detected because of scattered gamma photons or other random events (randoms). Randoms result in spurious detection of coincidence events and thereby create noise in a finally rendered image. Therefore, the ability to differentiate randoms from true coincidence events is a long-felt and unresolved problem in the art.

Use of crystal location in nuclear imaging apparatus to minimize timing degradation in a photodetector array


A Replaceable Manual Pump Heating Personal Fluid Dispenser that instantaneously heats personal fluid as the fluid flows through a tube or tubes integral to the dispenser, replacing the off-the-shelf personal fluid plastic bottle or container's actuator, closure, pump, and intake assembly to one that mimics the same yet allows heating of the personal fluid, uses the standard mass produced off-the-shelf plastic bottle or container for the storage of the personal fluid, and thereby is inexpensive to the user, safe, and eliminates the need for any special apparatus, or cartridge, to hold the personal fluid, or require the personal fluid to be removed from the plastic bottle or container in order for the personal fluid to be heated, and ensures no chemical leaching into the personal fluid from prolonged heating of the personal fluid when in contact with the plastic personal fluid bottle or container.

In the most common personal lotion or gel or liquid dispensers, hence personal fluid dispensers, as an example, a hand lotion dispenser, the bottle or container holding the personal fluid, is uniformly round or oval, and the personal lotion or gel or liquid, personal fluid, is dispensed by a manual pump using a push actuator. By the user manually pushing the actuator downward, the personal fluid is pumped through a tube, either singular or a multitude of tubes, and dispensed onto the user's hand or body, hence, a manually operated pump personal fluid dispenser.
The most common method means to attach this manually operated pump personal fluid dispenser to the personal fluid bottle or container is a screw cap, plug cap, or snap cap, or as industry refers to them, a screw closure or plug fit closure or snap fit closure, or in general, a closure.
The most common personal fluid bottle or container composition is made of plastic. The most common type of this plastic is PolyEthylene Terephthalate plastic or PET.
And, most commonly, the personal fluid is not heated because the personal fluid bottle or container is made of plastic, PET, and according to Scientific Publications, Journal of Environmental Monitoring, Environmental Health Perspectives, prolonged heating of the personal fluid in contact with the plastic bottle or container, PET, may cause types of chemicals to leach out of the plastic, PET, and into the personal fluid which may be harmful to the user.
Present art, which allows heating of personal fluid, suffers from several disadvantages:
In present art, in order to heat the personal fluid, an attachment is placed onto or atop the personal fluid bottle or container and the user must endure a prolonged period of time to allow the entire personal fluid bottle or container to heat and transfer this heat into the entire volume of the personal fluid before dispensing the heated personal fluid.
Still in other present art, a heating element or means is inserted into the personal fluid within the personal fluid bottle or container and the user must endure a prolonged period of time to heat the entire volume of the personal fluid within the bottle or container before dispensing the heated personal fluid.
Still in other present art, the personal fluid has to be removed from its plastic bottle or container and poured into or placed within another apparatus or container and the user must endure a prolonged period of time to heat the entire volume of the personal fluid before dispensing the heated personal fluid.
Still in other present art, the personal fluid bottle or container must be placed within a water or other liquid based bath, and this water or liquid bath is then heated by some means and the user must endure a prolonged period of time to heat the water or liquid bath, then transfer this heat through the bottle or container to heat the volume of personal fluid before dispensing the heated personal fluid.
Still in other present art, the personal fluid bottle or container must be of a special size, a certain circular dimension, in order to fit into the heating apparatus, such that the plastic bottle or container is then heated and the user must endure a prolonged period of time for the heated bottle or container to transfer this heat into the personal fluid.
Still in other present art, the personal fluid must be urged into a holding reservoir by some means, by which the personal fluid becomes stagnant within the reservoir and thereby allows personal fluid heating, and the user must endure a prolonged period of time to allow this holding reservoir to heat the volume of the personal fluid within this reservoir before dispensing the heated personal fluid, and after each holding reservoir amount of personal fluid is dispensed, the cycle of urging the fluid into the holding reservoir, allowing the personal fluid to become stagnant, and then heating the personal fluid, the prolonged period of time must be repeated, or if the holding reservoir is of sufficient size to hold enough personal fluid for several or more dispenses of personal fluid, the user must endure even a longer prolonged period of time for the initial or first dispense of heated personal fluid.
Still in other present art, the personal fluid has to be of a special type or of a certain viscosity in order for the special heating apparatus to effectively heat the personal fluid, and the user must endure the cost and the availability of obtaining this special type of personal fluid to be used within that special apparatus.
Still in other present art, the personal fluid is contained within a special cartridge, or the personal fluid has to be poured or moved into this special cartridge and in some present art, the cartridge contains all or a portion of the heating means, and the user must not only endure the cost and availability of this special cartridge, the user must endure the prolonged time to heat the personal fluid within this special cartridge.
In all present art, in which the personal fluid heating dispenser suffers from one or more of the above disadvantages, present art suffers another disadvantage in that present art is not replaceable into a plurality of personal fluid bottles or containers and therefore cannot freely move from common, inexpensive, mass produced, off-the-shelf, personal fluid plastic bottle or container to another after the personal fluid of that plastic bottle or container has been fully dispensed, or empty, and none of the present art can utilize the existent plastic bottle or container, off-the shelf, without assuming the risk of heating the plastic bottle or container and potentially having chemicals leach from the plastic bottle or container into the personal fluid.
In all present art, suffers another disadvantage in that all present art cannot heat the personal fluid immediately, within tenths of a second, initially and continuously, unless an entire volume of the personal fluid is heated, or a special apparatus for heating is used, or a special cartridge is used, and again, the user must endure either an initial, or repeated, prolonged period of time to heat the personal fluid.
In all present art, does not detect or sense the personal fluid velocity, or flow rate, within the dispenser, because present art, the personal fluid is stagnant, not moving, because present art heats the personal fluid while the personal fluid is stagnant, and thereby requiring time to heat the volume or a portion thereof, of personal fluid.
In present art, may use sensors or sensing means to detect touch of the user, to detect temperature of the personal fluid, to detect the presence or absence of personal fluid, but present are does not sense or detect the malfunction of the heating means, for it is assumed by present art the user will detect the dispenser is not heating by application of non-heated personal fluid onto the hand or body and thereby the user assumes the heating means has malfunctioned.
In present art, does not take into account the heating dispenser will most likely be kept within the bathroom or bathroom area where water is present, and present art does not sense or detect if power, the AC wall outlet or other electrical source, to the heating dispenser, has come in contact with water causing a potential for an electric shock.
In present art, does not take into account the variety of personal fluids, a lotion or gel or liquid, and due to the different or varying viscosities of these personal fluids, without continuous user temperature adjustment, have a means for sensing the different viscosities, and automatically maintain a set user temperature adjustment from one viscous personal fluid to another.
In present art, does not have a means to determine when the actual volume of personal fluid to be heated has diminished, as in the case when the personal fluid is near empty, and a smaller than normal amount of personal fluid is within present art's heating means.
In present art, does not sense or detect the personal fluid at the point of dispensing the personal fluid onto the user, hence, present art does not sense or detect for the possibility of a clog or dam to the personal fluid, for again, present art assumes that if no personal fluid is being dispensed it is up to the user to ascertain a clog or dam of the personal fluid within the dispenser has occurred.

Replaceable manual pump heating personal fluid dispenser


An example method determines an error vector magnitude using automatic test equipment (ATE). The method includes demodulating data received at a first receiver to produce first symbol error vectors, where each first symbol error vector represents a difference between a predefined point on a constellation diagram and a first measured point on the constellation diagram generated based on at least part of the data received by the first receiver; demodulating the data received at a second receiver to produce second symbol error vectors, where each second symbol error vector represents a difference between the predefined point on the constellation diagram and a second measured point on the constellation diagram generated based on at least part of the data received by the second receiver; and determining the error vector magnitude for the data based on the first symbol error vectors and the second symbol error vectors.

Test systems are configured to test the operation of electronic devices, such as microprocessors and memory chips, Testing may include sending signals to a device and determining how the device reacted to those signals based on its response. For example, testing may include sending test signals to a device, such as an integrated circuit (IC), and receiving radio frequency (RF) signals back from the device. The RF signals are processed to determine whether the device is performing acceptably. An error vector magnitude (EVM) is a measure of signal quality in the test system.

Determining error vector magnitude using cross-correlation


A portable electronic device includes a main body, a display and a distance measuring device. The distance measuring device includes a first distance measuring member and a second distance measuring member. The first distance measuring member includes a first signal emitting/receiving module and an arithmetic module. The second distance measuring member includes a second signal emitting/receiving module and a control module. The first signal emitting/receiving module is for receiving an alignment signal, emitting a measuring signal, and receiving a feedback of a measuring signal. The arithmetic module is for calculating the distance between the first distance measuring member and the second distance measuring member. The distance is displayed. The second signal emitting/receiving module is for emitting the alignment signal, receiving the measuring signal, and emitting the feedback of the measuring signal. The present disclosure further provides a distance measuring method for a device.

1. Technical Field
The present disclosure relates to an electronic device, particularly to a portable electronic device and a distance measuring device thereof.
2. Description of Related Art
A portable electronic device, such as a mobile phone, a MP3, a tablet computer, is popular because of its small size. The many functions of the portable electronic device encourage us to carry it with us all the time.
A distance measuring tool, such as a meter scale, may be used to measure a distance. However, the dedicated distance measuring tool is inconvenient to carry, this function should be incorporated into a portable electronic device.
Therefore, there is room for improvement in the art.

Portable electronic device with distance measuring device

Fu Tai Hua Industry (Shenzhen) Co., Ltd.


The present invention discloses an ML (Maximum Likelihood) detector comprising: a search value selecting circuit selecting a first-layer search value; and an ML detecting circuit. The ML detecting circuit executes the following steps: selecting K first-layer candidate values according to the first-layer search value, one of a reception signal and a derivative thereof, and one of a channel estimation signal and a derivative thereof; calculating K second-layer candidate values according to the K first-layer candidate values; determining whether to add P second-layer supplemental candidate value(s) and generating a decision; when the decision is affirmative, adding the P second-layer supplemental candidate values, generating P first-layer supplemental candidate values according to the P second-layer supplemental candidate values, and calculating log likelihood ratios (LLRs) according to the (K+P) first-layer and (K+P) second-layer candidate values; and when the decision is negative, calculating LLRs according to the K first-layer and K second-layer candidate values.

1. Field of the Invention
The present invention relates to wireless signal reception technique, especially to wireless signal reception technique using maximum likelihood detection.
2. Description of Related Art
Nowadays wireless communication technique is widely spread and users have more and more demand for data throughput. Therefore, this industry field keeps studying how to increase bandwidth usage efficiency under limited system bandwidth and raise system throughput. A market trend is using a spatial multiplexing transmission manner of multiple-input multiple-output (MIMO) technique which can greatly raise system throughput without engaging more bandwidth. This transmission manner gets a lot of attention recently.
The spatial multiplexing transmission manner uses a plurality of antennas of a transmitter to transmit signals independent of one another through the same frequency band at the same time, while a receiver uses a plurality of antennas to receive and detect these signals. In order to achieve better demodulation efficiency, the receiver may use a maximum likelihood algorithm (ML algorithm). The ML algorithm could be understood as an algorithm in search of an optimum solution. The ML algorithm makes use of an exhaustive search manner to estimate an optimum solution of transmission signals among all possible solutions according to reception signals. However, the exhaustive search manner is not an efficient manner because it computes all of the possible solutions and takes a long time to measure processing latency, complexity and computation power.
People who are interested in the prior arts may refer to the following literatures:    (1) China patent application of publication number CN101582748A; and    (2) Massimiliano Siti, Michael P. Fitz, "A Novel Soft-Output Layered Orthogonal Lattice Detector for Multiple Antenna Communications", IEEE International Conference on Communications (ICC), 2006.

Maximum likelihood detector and wireless signal receiver with maximum likelihood detection function


An apparatus, method, and computer program product are provided for software development testing utilizing one or more minimal testing features. An acceptance testing system receives one or more first minimal testing features for a first software development component to be developed by a first provider, and one or more second first minimal testing features for a second software development component to be developed by a second provider. Before completion of the second software development component, it is determined whether the first software development component is complete. If it is determined that the first software development component is complete, testing is performed on the first software development component utilizing the one or more first minimal testing features, before the completion of the second software development component.

Customers within the world of software development require prompt value and safe, properly tested software products. In response to this challenge, many development teams have moved to an "agile" code delivery model in which a full scope of a project is broken down into several "code drops." The definition of each drop is either determined by the customer based on business value, or is defined by developers who consider mainly criteria that makes it simple for them to deliver code in an expedited manner.
For relatively small projects, a single code provider can define the code drops as meaningful packages. On the other hand, for relatively larger, more complex projects, multiple code providers are typically required to deliver a solution. When each of such providers tries to define their own code drops, the software delivered to an acceptance testing organization does not necessarily exhibit any business value, since the delivered drops are not synchronized between providers. Further, as a result of such lack of synchronization, a first code provider may produce first code in accordance with a first timetable (by T=1), while a second code provider may produce second code in accordance with a second timetable (by T=2, after T=1). Thus, by virtue of the fact that both the first code and the second code must be delivered before testing can begin, final production code cannot be delivered to the customer until the completion of later-delivered second code.
There is thus a need for addressing these and/or other issues associated with the prior art.

Apparatus, method, and computer program for software development testing utilizing one or more minimal testing features


A radio transmission system includes: antenna pairs, each antenna pair being a combination of a transmitting antenna and a receiving antenna in one-to-one correspondence. A radio signal from the transmitting antenna in one of the antenna pairs reaches the receiving antenna of the one antenna pair as a desired wave directly, and a radio signal from the transmitting antenna of another antenna pair different from the one antenna pair reaches the receiving antenna of the one antenna pair as an unnecessary wave directly. A transfer characteristic correction section which performs a correction operation based on the transfer characteristic of a transmission space between the transmitting antenna and the receiving antenna for a transmission-target signal corresponding to the transmitting antenna, and a modulation functional section which modulates a carrier signal with a corrected signal after having been corrected by the transfer characteristic correction section and transmits the modulated carrier signal from the corresponding transmitting antenna, are provided in correspondence with each antenna pair.

1. Field of the Invention
The present invention relates to a radio transmission system (also including a radio communication apparatus which is realized in a single housing), a transmission-side radio communication apparatus, and a radio transmission method. In particular, the present invention relates to a mechanism for transmitting a plurality of transmission-target signals by radio using space division multiplex.
2. Description of the Related Art
For example, as a method which realizes high-speed signal transmission between electronic instruments arranged at a comparatively short distance (for example, within several centimeters to ten-odd centimeters) or within an electronic instrument, an LVDS (Low Voltage Differential Signaling) is known. However, recent increases in the capacity and speed of transmission data have led to problems, such as an increase of power consumption, an increase of the effect of signal distortion due to reflection or the like, an increase of unnecessary radiation, and the like. For example, when a signal, such as a video signal (including a captured signal) or a computer image, is transmitted at a high speed (in real time) within the instrument, the LVDS has limitations.
In order to cope with a problem regarding the high speed of transmission data, it is possible to increase the number of wirings or to reduce the transmission speed per signal line through signal parallelization. However, such a countermeasure results in an increase in the number of input/output terminals. As a result, a printed substrate or a cable wiring is complicated, or a semiconductor chip increases in size. Further, high-speed and large-capacity data is routed through wirings, thus so-called electromagnetic interference becomes problematic.
The problems in the LVDS or the method in which the number of wirings increases are due to signal transmission through electrical wirings. Thus, as a method which resolves the problems due to signal transmission through electrical wirings, it is possible to transmit signals by radio without using electrical wirings.
When a plurality of communication sections are provided on the transmission side and the reception side to perform multiplex transmission, it is also possible to apply space division multiplex. However, when space division multiplex is applied, it is necessary to provide a countermeasure against interference between channels. As one method which resolves this problem, it is possible to apply MIMO (Multi-Input Multi-Output) (for example, JP-A-2009-055228, JP-A-2009-049632, and JP-A-2009-033588).
JP-A-2009-055228, JP-A-2009-049632, and JP-A-2009-033588 are intended for radio transmission at a comparatively long distance with respect to radio transmission within an instrument or between instruments, and describe the application of MIMO processing in combination with an OFDM modulation scheme. That is, the MIMO processing described in JP-A-2009-055228, JP-A-2009-049632, and JP-A-2009-033588 depends on the OFDM modulation scheme.

Radio transmission system, radio communication apparatus, and radio transmission method


An information control pipeline (13) parallels the processor""s instruction pipeline (3), contains digital control information in respect of the instruction placed in the instruction pipeline and accompanies that instruction until all component operations prescribed within the instruction have been executed. When at the end of the pipeline, the instruction is presented for execution to a respective functional execution unit (7) of the processor, the respective functional execution unit accesses and uses the control information as a condition to instruction execution. Depending upon the processor, the control information may contain one or more bits, referred to as enable bits, as may be set enabled, indicating that an associated operation in the instruction is to be executed, or by software set disabled, indicating that the associated operation is masked, such as by an exception handler (9) when returning from a resolved exception.

The present invention relates to digital computers, and, more particularly, to a novel method and apparatus for increasing the speed with which a micro-processor handles excepted instructions during program execution.
A digital computer includes a central processing unit, such as a microprocessor, several types of memory, input-output devices and the like. The operation of a computer is controlled by computer programs, such as operating systems and application programs. Those programs provide instructions to those functional units of a central processor responsible for handling and execution as binary information. Different binary sequences represent different instructions for a particular machine and the instructions tend to be peculiar to a particular processor or processor family. Thus, typically, different families of processors have different instruction sets, unless they are specifically designed to utilize an instruction set of another processor family.
The instructions of one processor typically cannot be understood directly by any of the other types of processors. The difference in instruction sets is often due to the format chosen by the designer for presenting instructions to the processor. In general, a designer may chose to design a processor for a complex instruction set computer (CISC) or reduced instruction set computer (RISC) or for a newer very long instruction set (VLIW) computer.
CISC processors provide special hardware for executing an entire operation. For example, an ADD instruction may provide one operand to an integer unit register, fetch a second operand from memory and place it in a second register, and combine the two operands in a third register. Because it does so, instruction formats are very complicated. Such structure takes a large amount of hardware and processing effort to tell one instruction from another.
A RISC processor, on the other hand, is much simpler and treats each part of an ADD operation as a separate element. By providing consistently sized instructions, a RISC processor eliminates significant hardware and reduces the processing time needed to decode instructions.
A newer type of processor called a very long instruction word (VLIW) processor attempts to make use of the best attributes of both CISC and RISC. It uses consistent sized instructions (herein called xe2x80x9catomsxe2x80x9d) as do RISC processors, but groups a number of those instructions together in a VLIW word (herein called a xe2x80x9cmoleculexe2x80x9d) and provides processing units to execute the individual atoms in parallel.
The execution of most operations by a processor requires a number of steps. For example, instructions must be fetched from memory, sometimes a second instruction must be fetched from memory, the instruction is decoded and finally it is executed. This takes a number of operational cycles of the processor. In order to produce results as fast as possible, computers are designed so that each sequential instruction is begun (as far as is possible) on the next operation cycle after the preceding instruction has already begun the steps leading to its execution. This causes the steps leading to execution of subsequent instructions to overlap. In this manner, an instruction may often be executed each cycle.
The manner in which this starting and carrying out the steps leading to the execution of instructions so that an instruction executes each operation cycle is referred to by those skilled in the art as an instruction pipeline, which is included within processors. In operation to process an application program, the instructions of the application are serially entered into the pipeline by a pipeline control unit. The pipeline control unit includes a program counter, that loads instructions in a serial order into the pipeline.
Instructions do not always execute in the ideal order provided by the pipeline. Often things happen which interfere with the process. For example, a memory page at which an instruction resides cannot be found in main memory, creating an exception. To resolve that exception, the memory page must be paged in before the instruction can execute. Exceptions, such as the foregoing, occur for a wide variety of reasons. When such exception occurs, further internal processing activity of the application program is temporarily halted, until that exception is resolved. The excepting functional unit issues a stop signal, herein called a xe2x80x9ckillxe2x80x9d signal, which pauses all other functional units in the microprocessor, until the exception is resolved, empties the pipeline of any instructions and immediately prompts an exception handler into action.
The exception handler fixes the problem which has arisen. An exception handler is a software routine conventionally designed to deal with such exceptions; and different exception handlers (i.e., different routines) are prepared to handle each different kind of exception. Thus, every computer contains a library of such software handlers in its associated memory. The pipeline control unit calls up an appropriate exception handler and executes that routine.
As an example, if a memory exception is due to the failure to locate data referenced by a load instruction within main memory, the exception handler is one that pages in that data and then returns back to the original excepted instruction. Processing of the application recommences with re-execution of the same instruction. However, this time the instruction is executed without generating that memory exception. In rare instances an exception handler of a RISC or CISC processors may emulate the instruction that caused the exception and then execute the emulated instruction to achieve the result desired. In other instances, an exception handler may only note that an exception occurred and return control to the excepted instruction or may decide to skip the excepted instruction and have execution resume at the next instruction. The exception handler thereafter returns control to the instruction pipeline controller by issuing a xe2x80x9creturn-from-exceptionxe2x80x9d (RFE) signal. The latter signals the pipeline counter in the pipeline control unit to reissue and execute the instruction that was subject to the exception or, alternatively as called for by the exception handler, signals to advance the next instruction into the pipeline, that is, insert the memory address of the succeeding instruction into the pipeline, thereby moving pipeline activity beyond the instruction that generated the exception. In either event, the return-from-exception procedure is a very simple step.
Such a simple step of skipping past an excepted instruction is not possible for VLIW processors. In VLIW processors it is frequently desired for exception handlers to emulate an excepting instruction. Although re-execution of the excepting atom instruction is not desired, other instructions in the VLIW instruction must be executed. For example, one VLIW computer system is described U.S. Pat. No. 5,832,205 to Kelly et al, granted Nov. 3, 1998, entitled, Memory Controller For A Microprocessor For Detecting A Failure of Speculation On The Physical Nature of A Component Being Addressed (the xe2x80x9c205 Kelly patentxe2x80x9d), assigned to Transmeta Corporation, assignee of the present invention, the content of which patent is incorporated by reference herein in its entirety. The present invention has particular application to VLIW computers, and, in particular, to VLIW computers described by the ""205 Kelly patent, although it should be understood that the invention may be found to also be applicable to other types of computers.
The ""205 Kelly patent discloses a novel microprocessor formed by a combination of hardware processing portion, much simpler in structure than competitive prior state of the art microprocessors, and an emulating software portion, referred to therein as xe2x80x9ccode morphing softwarexe2x80x9d. Among other things, in the Kelly system the code morphing software carries out a significant portion of the functions of processors in software, thereby reducing the hardware required for processing and the greater electrical power that such hardware requires. For a better understanding of the foregoing and other functions accomplished by the code morphing software, the interested reader is invited to study the ""205 Kelly patent.
A VLIW processor constructed in accordance with the ""205 Kelly patent also contains an instruction pipeline. However, because a VLIW instruction (xe2x80x9cmoleculexe2x80x9d) is packed with a number of individual instructions (xe2x80x9catomsxe2x80x9d), which are to be executed in parallel, what is generally referred to as the instruction pipeline in a processor prescribed in the ""205 Kelly patent is actually a composite of multiple parallel pipelines. The stages of the instruction pipeline in the latter processor number, typically, five. Those stages comprise, as example, first and second stages (cycles) to fetch an instruction from an instruction cache, two register operations and, ultimately, the execution stage, at which an instruction is executed (or is found subject to an exception).
The pipeline formatting of a molecule rarely contains a single atom prescribing an operation, but, typically, comprises two and as many as four separate atoms prescribing different operations. All those atoms pass along the instruction pipeline as a collective group constituting the molecule. Since individual atoms are intended to be executed by separate functional units and execute in parallel, i.e., simultaneously, the VLIW processor comprises multiple instruction pipelines, one for each functional unit in the computer that may be called upon during the processing steps to execute atom instructions. In making reference herein to the VLIW processors pipeline, it should be understood that reference is being made collectively to the multiple pipelines, unless the context of the statement indicates that reference is made only to a specific individual pipeline, as example, to the memory pipeline, the ALU1 pipeline and so on.
At the respective pipeline""s execution stage, the atomic instructions are executed by separate non-conflicting functional units in the computer, ideally concurrently for optimal speed of processing. If execution of one of those component instructions causes an exception, which, as a consequence, halts further application processing and forces clearance of the instruction pipeline, as many as three atomic instructions in the VLIW molecule are also halted and cleared from their respective instruction pipelines.
In VLIW computers an exception handler cannot simply advance the pipeline control unit""s instruction counter another step, as occurs in the prior CISC computers as earlier described, since the remaining operation atoms in the same molecule also must be accounted for and require execution. Instead the VLIW computers exception handlers are required to either emulate all the atoms in the molecule before returning control back to the pipeline control unit or otherwise store, retrieve and execute those remaining atoms.
The foregoing exception handling process is very expensive in terms of VLIW processor time (clock cycles) and is likely to dramatically slow execution of the program. It also requires the software comprising the exception handlers to be significantly more complex than that for the CISC type processors. Neither result is attractive. Both detract from inherent advantage of the VLIW processor.
The present invention offers a better approach for handling those atoms in the event of an exception. As an advantage VLIW computers, such as those constructed in accordance with the ""205 Kelly patent, are no longer required to increase the complexity of exception handling software to account for and/or handle the other atoms in the VLIW molecule. As a further advantage, the invention permits continued reassertion of a VLIW instruction (molecule) that generated the exception within the execution pipeline for execution of remaining atomic instructions within the molecule by disabling the atom (or atoms) responsible for the exception (or exceptions), permitting the remaining atoms to execute. A VLIW molecule is repeatedly asserted into the pipeline until all the individual atoms within the molecule have been executed or excepted.
Accordingly, an object of the invention is to improve the internal operating efficiency of a microprocessor, more particularly, a VLIW microprocessor.
A further object of the invention is to provide a new more efficient process and apparatus internal to a VLIW microprocessor for handling atoms in a molecule (VLIW instruction), both those atoms responsible for generating an exception and the remaining atoms, that ensures that any atom requiring execution is executed.
A still further object of the invention is to minimize the time (system clock cycles) required to process a VLIW instruction in the event the instruction is responsible for an exception.
And an ancillary object of the invention is to reduce the need for complex exception handling software in those computers that execute complex instructions, defining multiple independent operations there within, and permit use of exception handling software of the complexity level inherent in those computers which execute ordinary instructions.
In accordance with the foregoing objects and advantages, the improved VLIW processor defined by the invention provides a separate information control pipeline to parallel the instruction pipeline. The control information pipeline is provided with control information about the VLIW instruction that was input into the instruction pipeline. That control information accompanies that VLIW instruction until all the component operations prescribed in the VLIW instruction have been executed, effectively linking the control information with the corresponding VLIW instruction. When the atoms within a VLIW instruction are presented for execution to the respective functional execution units of the processor, the respective functional units are able to access and use that control information.
In a more specific aspect to the invention, the respective functional unit determines whether the atom that is presented for execution is to be executed or masked.
In accordance with a more specific aspect to the invention, the control information, defining an instruction pipeline control packet for the VLIW processor, comprises extra bits, herein referred to as xe2x80x9cenable bitsxe2x80x9d. Each enable bit is associated with a respective one of the plurality of different functional units of the processor responsible for executing an atom (operation), such as the memory unit, Arithmetic and Logic units, the floating point unit and the like. The enable bits permit software to specify which parts of a VLIW instruction are subsequently to be executed (enabled) and which parts are to be masked (disabled) when returning from an exception. The VLIW instruction may then be reasserted in the instruction pipeline for execution of the unmasked atoms.
In accordance with the latter, the VLIW processor includes a pipeline control unit that includes a source to generate the enable bits and link those bits to a VLIW instruction; an instruction pipeline for the VLIW instruction; and an enable bit pipeline or xe2x80x9csidebandxe2x80x9d pipeline through which the enable bits are advanced in synchronism with the instruction""s step-by-step advance through the instruction pipeline. The pipeline control unit further includes a register, herein referred to as the error register, for saving both instruction address of a VLIW instruction that is subject to an exception and the companion enable bits linked thereby. The latter register serves within the control unit as an alternate supply of the enable bits that the control unit""s source provides. Each functional unit""s decode logic is expanded to first decode and interpret the respective enable bit and some of the processor""s exception handler""s are modified to carry out the additional task of modifying the respective enable bit, changing that bit from enabled to disabled when appropriate.
The group of enable bits, one per computational pipeline, thereby tracks or follows each VLIW instruction as it is executed. By default, all the enable bits associated with each VLIW instruction are set, that is, enabled, resulting in the normal execution of all operations specified by the multiple atom instructions in the VLIW molecule. If an exception or interrupt occurs during the execution of an individual instruction (atom) contained in the VLIW molecule, the pipeline control units saves both the instruction address of the molecule and the accompanying group of enable bits in the error register. The exception handler called up to handle the exception is free to modify any of those enable bits. The exception handler can change the state of each from enable to disable (or vice-versa, if desired).
Should the exception handler for any reason determine to disable an atom that was subject to an exception, the bit associated with that atom is disabled. Upon resolving the exception, the exception handler issues a return-from-exception (xe2x80x9cRFExe2x80x9d) instruction, which returns control via the pipeline control unit to the original molecule. The pipeline control unit restarts the same VLIW molecule instruction along with the companion enable bits, as so possibly modified, retrieved from the error register, placing them into the respective pipelines.
The disabled atom is masked and will not be executed. Since the enable bits effectively track the VLIW molecule instruction as it executes, changes made to the enable bits by the exception handlers are cumulative, until the entire molecule instruction (all the atom instructions) completes successfully.

Use of enable bits to control execution of selected instructions


A low voltage, low power versatile and compact delay circuit for CMOS integrated circuits. The biasing circuit and comparator of the delay circuit are implemented with a relatively few simple transistor stages. This approach makes the circuit compact and allows for operation at very low supply voltages (e.g., 1.5 volts). The time delay of the delay circuit is made to depend only on passive resistive and capacitive components. The time delay is thus insensitive to fluctuations in the supply voltage, as well as fluctuations in temperature. This configuration is particularly advantageous in circuits where several timing elements need to track with one another, as they can all be formed with resistors and capacitors of the same construction. The design also makes the circuit insensitive to process parameters, as well as later environmental effects due to operating temperature, circuit aging, and the like. A common signal is used to control both a trip point voltage of a comparator and a voltage change rate of a clock ramp signal in the delay circuit, such that variations in voltage supplied to the clock during normal operation does not substantially affect the clock period.

The present invention relates to CMOS delay circuits suitable for use in on-chip clocks or oscillators and timing delay circuits, and more particularly, to a low voltage low power compact CMOS delay circuit for use in low voltage low power devices.
Delay circuits are commonly utilized in on-chip clocks or oscillators as well as timing delay circuits. Conventional CMOS delay circuits use ramps, comparators, and voltage references to ensure that the delay will not vary with supply voltage and operating temperature. However, these circuits are complex and require a significant amount of chip area, and are difficult to design for low supply voltages.
There are numerous examples of devices which can benefit from circuits incorporating low voltage low power delay circuits. One example of such a device is a displacement measuring instrument, such as a hand-held electronic caliper that can be used for making precise geometric measurements, such as that shown in U.S. Pat. No. 5,901,458, which is commonly assigned and hereby incorporated by reference in its entirety. Another example of such a device is shown in U.S. Pat. No. 5,886,519, which is commonly assigned, and incorporated herein by reference in its entirety. The ""519 patent discloses an inductive absolute position transducer for high accuracy applications, such as linear or rotary encoders, electronic calipers and the like. It is obvious that the less power such instruments use, the fewer batteries (or other power sources) they will require and the longer they will operate before the batteries (or other power sources) need to be replaced or replenished. However, reducing the power requirements of such devices is a complex task. Such devices are required to make highly accurate measurements, and the signal processing techniques that have been developed for such are required to both accomplish the desired accuracy and operate at low voltage and power levels, and be relatively insensitive to reasonable variations in supply voltage and operating temperature.
The present invention is directed to a versatile and compact delay circuit that is relatively insensitive to reasonable variations in supply voltage and operating temperature, for inclusion in CMOS integrated circuits that are used in low voltage low power devices.
The present invention provides a low voltage low power versatile, compact and stable delay circuit for CMOS integrated circuits. In accordance with one aspect of the invention, a common signal is used to control both a trip-point voltage of a comparator and a voltage change rate of a clock ramp signal input to the comparator, such that variations in a voltage supplied to the delay circuit during normal operation will not substantially affect the clock period of the delay circuit.
In accordance with another aspect of the invention, the biasing circuit and a biased transistor comparator of the delay circuit are implemented with a relatively few simple transistor stages. This approach makes the circuit compact and allows for operation at very low supply voltages.
In accordance with another aspect of the invention, the delay circuit may be used in a device that is operable from a power supply providing a voltage less than 1.75 volts (e.g., a single 1.5 volt watch battery or solar cell providing a voltage as low as 1.5 volts nominal, 1.35 volts minimum), and has a current drain compatible with devices which require an overall current drain of a few microamps or less.
In accordance with another aspect of the invention, the delay circuit may be used in systems with voltages higher than 1.5 volts, such as one that is operable from a power supply providing a voltage less than 3.5 volts (e.g., two 1.5 volt watch batteries or solar cells in series). The invention is also advantageous in some applications operating with voltages higher than 3.5 volts.
In accordance with another aspect of the invention, certain components are selected to reduce the sensitivity of the overall system to process parameters. More specifically, by using resistors and capacitors of the same type in circuitry such as a clock/oscillator generator, and by charging the capacitors with scaled bias currents, certain factors (e.g., scale factors) of the system are made to be independent of process parameters, as well as later environmental effects due to operating temperature, circuit aging, and the like.
In accordance with another aspect of the invention, the time delay of the delay circuit is made to depend only on certain passive components, such as resistors and capacitors. The time delay is thus made to be insensitive to variations in supply voltage and reference voltage levels. This enables the circuit to be implemented with simple transistor stages without introducing excessive variations in the time delay that could otherwise be caused by changes in operating temperature or changes in voltage levels. This is particularly advantageous in circuits where several timing elements need to track with one another, since these different timing elements can be constructed with similar resistors and capacitors.
In accordance with another aspect of the invention, the ramp generator of the present invention can be implemented with relatively simple circuitry, and consequently be of a small size and operable from low voltage. An operating speed limitation of the system is due to the nature of the ramp itself, since a ramp inherently takes time to transition. However, since high-speed operation is not a critical factor in the signal processing of a variety of devices (e.g., certain portable or handheld measuring instruments), this implementation provides an effective tradeoff of a slower system for one that uses less power, is of a smaller size and is operable from low voltage.

Compact delay circuit for CMOS integrated circuits used in low voltage low power devices


An exemplary cochlear implant assembly includes a cochlear implant configured to apply electrical stimulation to the recipient by way of an electrode array, a cochlear implant antenna communicatively coupled to the cochlear implant, and an encapsulant that covers the cochlear implant and the cochlear implant antenna, the encapsulant impregnated with a dielectric material that is configured to confine an electric field around the cochlear implant antenna. Corresponding methods for manufacturing cochlear implant assemblies are also described.

Cochlear implant systems are used to provide, restore, and/or improve the sense of hearing to recipients with severe or profound hearing loss. Conventional cochlear implant systems include various components configured to be implanted within a recipient (e.g., a cochlear implant, an antenna, and an electrode lead) and various components configured to be located external to the recipient (e.g., a sound processor, a battery, and a microphone).
When the components of the cochlear implant system are implanted within the recipient, the implanted antenna of the cochlear implant system is positioned in close proximity to surrounding tissue, which has a large dielectric constant (also referred to as relative permittivity) and a large dissipation factor. These attributes of the surrounding tissue may cause the electric field near the antenna to penetrate into the surrounding tissue capacitively pulling the inductance associated with the antenna and adding loss. To confine the electric field around the antenna, a guard wire may be provided (e.g., spirally wrapped) around the antenna of a cochlear implant system. In so doing, the electric field around the antenna is dominated by the presence of the guard wire and the effects of the surrounding tissue are mitigated.
Unfortunately, installing and connecting (e.g., welding) a guard wire to a cochlear implant system includes various manually intensive manufacturing operations. For example, to properly position and space spiral windings of a guard wire, an intermediate molding operation is typically performed in which the antenna is covered with a molded encapsulant (e.g., silicone). The guard wire is then manually wrapped around the molded encapsulant, which is a time consuming and manually intensive process. In addition, guard wires used to confine the electric field around an antenna of a cochlear implant typically have a small diameter, which makes them susceptible to impact damage. These aspects associated with guard wires undesirably increase unit costs and/or reduce the durability of implanted components included in a cochlear implant system.

Cochlear implant assemblies and methods of manufacturing the same


A woodturning tool for creating containers has a first rigid arm, and a second rigid arm. The first rigid arm has two ends with a cutting blade at the first end. The second rigid arm has two ends with a guiding device at the first end. The cutting blade and the guiding device are operatively aligned. The first and second rigid arms are adapted to move relative to one another.

Woodturning is a form of woodworking that is used to create wooden objects (e.g. a bowl or a table leg) on a lathe using cutting tools. Woodturning differs from most other forms of woodworking in that the wood is moving while a relatively stationary tool is used to cut and shape the wood. Many intricate shapes and designs can be made by turning wood or woodturning.
Despite the advances in technology for manufacturing wood products, hand turned products are more highly valued and sought after than mass-produced products. This creates a high demand for hand turned products. Also, woodturning products by hand is a hobby enjoyed by many. Accordingly, there is a need for tools for creating hand turned products.
One area of hand turned products is hand turned containers. Hand turned containers include, but are not limited to, bowls, platters, cups, goblets, dishes, plates, saucers, pots, tumblers, teacups, tasters, etc.
There are many problems and difficulties with creating a hand turned container. These problems may include: creating a uniform or controlled wall thickness, the strength of the walls, the aesthetic appearance of a hand turned container, the time it takes to create a hand turned product, the amount of skill required, and the amount of time it takes to cure a hand turned product.
Accordingly, there is a need for a woodturning tool for creating hand turned containers that addresses all of these problems.

University of North Carolina at Charlotte


A solid-state imaging device for enlarging an operating margin of a pixel portion and achieving complete transfer of a signal charge by using a plurality of power supply voltages, wherein a plurality of power supplies having different power supply voltage values are supplied to portions of a semiconductor chip 1. For example, as a first power supply system, a first digital power supply voltage (DVDD1) is supplied from a power supply terminal 45, a first digital ground voltage (DVSS1) is supplied from a power supply terminal 46, a second digital power supply voltage (DVDD2) is supplied from a power supply terminal 47, a second digital ground voltage (DVSS2) is supplied from a power supply terminal 48, a third digital power supply (DVDD3) is supplied from a power supply terminal 49, and a third digital ground voltage (DVSS3) is supplied from a power supply terminal 50, and as a second power supply system, a first analog power supply voltage (AVDD1) is supplied from a power supply terminal 40, a first analog ground voltage (AVSS1) is supplied from a power supply terminal 41, a second analog power supply voltage (AVDD2) is supplied from a power supply terminal 42, and a second analog ground voltage (AVSS2) is supplied from a power supply terminal 43.

Conventionally, an amplification type (CMOS sensor type) solid-state imaging device for example as shown in FIG. 1 to FIG. 7 has been known. Below, an explanation will be given of the configuration and operation of the conventional example using these drawings.
FIG. 1 is a schematic plan view of an example of the configuration of the conventional solid-state imaging device.
This solid-state imaging device is comprised of a semiconductor chip 1 on which a pixel portion 2 having a large number of unit pixels arranged in a two-dimensional array, a timing generator portion 3 for generating various types of timing signals, an output column portion 4 such as a column CDS for performing correlated double sampling (CDS) for each pixel column (column) of the unit pixels or a column AD for performing A/D conversion, a horizontal drive portion 5 for selecting and driving this output column portion 4 in a horizontal direction, a vertical drive portion 6 for selecting and driving each pixel row, a signal processing portion (DSP) 7 for performing signal processing with respect to pixel signals read out from the pixel portion 2, etc. formed thereon.
This solid-state imaging device is driven by two power supply systems of a first power supply system (hereinafter, referred to as a "digital power supply" for convenience) and a second power supply system (hereinafter, referred to as an "analog power supply" for convenience) as the power supply system. The semiconductor chip 1 has a power supply terminal 8 supplied with a digital power supply voltage DVDD as the first power supply system, a power supply terminal 9 supplied with a digital ground voltage DVSS, a power supply terminal 10 supplied with an analog power supply voltage AVDD as the second power supply system, and a power supply terminal 11 supplied with an analog ground voltage AVSS.
In this way, in the conventional solid-state imaging device, the digital power supply voltage (DVDD) and the analog power supply voltage (AVDD) have the same voltage value (for example 1.8V, 2.5V, or 3.3V), therefore even if a plurality of electrode pads PAD are arranged on the semiconductor chip 1, one type of power supply voltage is supplied from the outside of the chip 1, and it is operating with a single power supply voltage.
FIG. 2 is a cross-sectional view of a stack structure of the pixel portion 2 of the conventional example shown in FIG. 1.
As illustrated, a silicon substrate 12 has a P-well 13 formed on it. This P-well 13 has an element isolation area (LOCOS element isolation in the present example, but sometimes STI etc.) 14, a power supply area (AVDD) 15, a reset gate (Reset) 16 of a reset transistor, a charge detection unit 17 referred to as a floating diffusion (FD) portion, a transfer transistor (transfer gate TG) 18 for transferring a signal charge of a photodiode 23 to the FD portion 17, a P+ type light receiving layer 19 and an N-type photo-electric conversion layer 20 configuring the photodiode 23, etc. formed on it.
In such a solid-state imaging device, with each succeeding generation of semiconductor process, the used power supply voltage has become smaller, for example, 3.3V in a 0.35 μm process, 2.5V in a 0.25 μm process, and 1.8V in a 0.18 μm process.
On the other hand, the solid-state imaging device is a mixed analog-digital device requiring a circuit portion driven by a second power supply system (hereinafter referred to as an "analog circuit portion") and a circuit portion driven by the first power supply system (hereinafter referred to as a "digital circuit portion"). Accordingly, the above digital circuit portion operates even if the power supply voltage is lowered. However, a reduction of voltage of the analog circuit portion is difficult.
Especially, for the pixel portion 2 in the analog circuit portion, the signal charge (Qsig) must be completely transferred from the photodiode 23 to the charge detection unit 17, so reduction of the voltage is difficult.
FIG. 3 to FIG. 7 are explanatory views of potential levels corresponding to the cross-sectional view shown in FIG. 2, wherein the ordinates correspond to a potential level PTN (V), and the abscissas correspond to a location for forming each element on the substrate surface of FIG. 2.
Below, an explanation will be given of a conventional read operation of the signal charge.
First, in FIG. 3, while the signal charge 24 is being stored in the photodiode (PD) 23, a drain terminal 15 of the reset transistor 16 becomes the power supply voltage AVDD1. In the illustrated example, AVDD1=2.5V (indicated by 26 in the figure). At this time, the gate voltage (ΦTG) of the transfer gate 18 is 0V.
Further, the potential level (ΦR) when the reset transistor 16 is "OFF" is for example about 1V (indicated by 27 in the figure). This reset transistor 16 becomes a deep depletion type transistor.
Next, as shown in FIG. 4, the gate of the reset transistor 16 is made the "ON" state. That is, ΦR=2.5V. Then, the potential under the gate of the reset transistor 16 is deeply reset (reset to 3V in the illustrated example) (indicated by 28 in the figure), and the FD potential becomes the same potential (indicated by 26 in the figure) as the power supply voltage 15 (AVDD1=2.5V). That is, the FD potential is reset to the power supply voltage by using the deep depletion type transistor for the reset transistor 16.
Next, FIG. 5 shows the potential when making the reset transistor 16 the "OFF" state, and the FD potential is the same as the potential of AVDD1 as it is. The FD potential actually becomes slightly smaller than AVDD1=2.5V due to a parasitic capacitance with the gate of the reset transistor 16 (indicated by 25 in the figure).
Further, FIG. 6 shows the potential when reading. By applying an "ON" voltage to the transfer gate 18, the signal charge (Qsig) 24 is read out to the FD portion 17.
Here, most of the signal charge (Qsig1) of the signal charge (Qsig) 24 is read out to the FD portion 17, but part of the signal charge (Qsig2) 29 remains in the photodiode 23.
These remaining signal charge becomes a residual image and causes the image characteristics to deteriorate.
Here, the cause of the occurrence of a residual image is that the voltage applied to the transfer gate 18 is relatively small, so a potential barrier 31 is generated under the gate of the transfer gate 18 and the signal charge of the photodiode 23 cannot be completely read out.
In this way, in the conventional amplification type solid-state imaging device, the smaller the voltage driving the pixel portion, the larger the possibility of the occurrence of a residual image and the greater the deterioration of the image quality.
FIG. 7 shows the potential after making the transfer gate 18 "OFF". As illustrated, the gate voltage (ΦTG) of the transfer gate 18 becomes 0V (indicated by 32 in the figure), and a signal charge (Qsig2) 29 remains in the photodiode 23.
As described above, in the conventional amplification type solid-state imaging device, the voltage driving the pixel portion is small, so the signal charge of the photodiode cannot be completely read out. This becomes the cause of occurrence of a residual image.
Further, the problem arises that due to such a background, a large operating margin of the pixel portion cannot be obtained. Further, the problem arises that the structure etc. of the pixel portion becomes restricted, the production process becomes troublesome, and a large power supply voltage becomes necessary.


Method and system for temperature-dependent frequency compensation. For example, the method for temperature-dependent frequency compensation includes determining a first frequency compensation as a first function of temperature using one or more crystal oscillators, processing information associated with the first frequency compensation as the first function of temperature, and determining a second frequency compensation for a crystal oscillator as a second function of temperature based on at least information associated with the first frequency compensation as the first function of temperature. The one or more crystal oscillators do not include the crystal oscillator, and the first frequency compensation as the first function of temperature is different from the second frequency compensation as the second function of temperature.

Certain embodiments of the present invention are directed to real-time clocks. More particularly, some embodiments of the invention provide systems and methods for frequency compensation of real-time clocks. Merely by way of example, some embodiments of the invention have been applied to temperature-dependent frequency compensation. But it would be recognized that the invention has a much broader range of applicability.
Real-time clocks (RTCs) often are used in electronics products to provide clocking or time-setting. These electronic products include mobile phones, digital cameras, computers, alarm clocks, electricity meters, watches, and/or smart home appliances. For real-time clocks, crystal oscillators often serve as driving sources, and frequency precision of the crystal oscillators usually determine precision of the real-time clocks. Conventional crystal oscillators often have a frequency precision error in the range of ±20 ppm at the room temperature and in the range wider than ±100 ppm at a higher temperature (e.g., at 70° C.) or at a lower temperature (e.g., at −30° C.). Specifically, ±20 ppm represents an error range of ±2 seconds per day, and ±100 ppm represents an error range of ±10 seconds per day. Such precision error ranges may not be acceptable under certain circumstances.
Frequency changes of crystal oscillators with temperature often can be curve-fitted, and the corresponding fitting coefficients can be obtained (e.g., through multiple iterations). For example, the desired frequency minus the actual frequency is represented by the frequency compensation. In another example, for a crystal oscillator, its frequency compensation as a function of temperature is as follows:Δf=aT3+bT2+cT+d  (Equation 1)where Δf represents the frequency compensation for the crystal oscillator, which is the desired frequency minus the actual frequency. Additionally, T represents the temperature of the crystal oscillator, and a, b, c and d represent coefficients.
Usually, the coefficients a, b, c and d are predetermined by measuring actual frequencies of the crystal oscillator at four different temperatures, and calculating the corresponding frequency compensation values at these four temperatures. For example, at each of these four temperatures, a real-time-clock system that contains the crystal oscillator is placed at that particular temperature (e.g., as measured by a temperature sensor) for a period of time in order to achieve thermal equilibrium of the system. Such period of time needed for each measurement often renders the calibration process inefficient. Each crystal oscillator needs to be measured at four different temperatures to determine its coefficients a, b, c and d as shown in Equation 1, and these four measurements need to be repeated for different crystal oscillators that may have different coefficient values.
In contrast, temperature-compensated crystal oscillators (TCXOs) usually have smaller frequency precision errors, but they often are much more expensive. The temperature-compensated crystal oscillators often are not feasible for low-cost designs.
Hence it is highly desirable to improve the techniques of temperature compensation for real-time-clock (RTC) systems.

Systems and methods for frequency compensation of real-time-clock systems

Guangzhou On-Bright Electronics Co., Ltd.


A vehicle front structure includes a cross member installed across right and left front side frames. The left front side frame has a frame bending section provided above a left suspension arm. The frame bending section is formed so as to be bendable when subjected to a frontal impact load. A left reinforcing member is disposed below the frame bending section and is mounted across the cross member and the dash cross member. The left reinforcing member is fastened to a rear fastening portion. The left reinforcing member has a bending section that is bendable downward when subjected to an impact load.

1. Field
The present disclosure relates to a vehicle front structure that has front side frames provided on right and left sides thereof and suspension arms supported below the front side frames.
2. Description of the Related Art
Some vehicle front structures have subframes provided below right and left front side frames and have engines or other power sources supported by the subframes. A subframe is a highly rigid member that supports an engine or other power source. When subjected to a frontal impact load, such a highly rigid subframe bends, thereby absorbing the impact load (see, for example, Japanese Unexamined Patent Application Publication No. 2005-271810).
Some vehicle front structures, however, have no subframes. In other words, they have a Γ (gamma in uppercase) shaped or A shaped lower arm for independent suspension directly supported by the vehicle body with no subframe therebetween. Such vehicle front structures are not capable of absorbing a frontal impact load through subframes. In addition, such a highly rigid Γ (gamma in uppercase) shaped or A shaped lower arm, when subjected to an impact load, does not collapse in a preferred manner. This arrangement may impede the absorption of a frontal impact load through the deformation of front side frames.


An improved memory addressing system has a CPU having both an address bus and a multiplexed data/address bus. A reduced PIN out companion chip is coupled to the multiplexed data/address bus for decoding data and low order address information. Memory storage is coupled to a high order address bus for receiving a high order address from the CPU, and to the low order address bus and data bus for receiving decoded low order address and data information from the companion chip.

Architecture
In a traditional computer system, the Central Processing Unit (CPU) will generate an address on an address bus and then read or write data on a separate data bus. This is denoted as a parallel bus architecture and is depicted in FIG. 3. A control bus from the CPU runs parallel to the address bus and the data bus to provide signals for such things as ADDRESS_VALID and control whether the cycle is a READ or a WRITE operation. The control bus and data bus then typically connect to a controller, or companion chip, which is designed to communicate to devices such as ROM, SRAM, DRAM or other peripherals such as graphics cards and modems. A companion chip is required in most systems because even though a CPU can communicate with many different devices, it cannot do so well, nor can a CPU communicate with all types of devices. A typical timing diagram for a parallel bus architecture is shown in FIG. 1. If the CPU can directly support ROM accesses, (for instance the Pentium can not), the parallel bus architecture, as shown in FIG. 3, can significantly reduce the size of the companion chip because an address bus does not need to be routed via a companion chip as is required in a multiplexed system. The parallel bus method also results in a flexibility in designing how much ROM address space can be attached to the CPU.
The disadvantage to a parallel bus architecture is a reduction of flexibility in the memory map. This reduction in this configuration occurs because it is not possible for the companion chip to see the addresses when the CPU communicates with the ROM thus resulting in a loss of the ability to control how far into ROM space the CPU is addressing.
In an alternative design, some CPUs have their architecture designed to eliminate the separate address bus in order to reduce the PIN count. This method is attractive due to the smaller numbers of PINs which translate directly to a less expensive device due to cheaper package, smaller die etc. This alternative design uses a multiplexed address/data bus. The multiplexed address/data bus has multiple cycles with the first cycle being address and command, the second being data. A typical timing diagram for a multiplex bus architecture is shown in FIG. 2, and a multiplexed bus architecture is depicted in FIG. 4. This method has the advantage of a smaller PIN out count from the CPU, and also results in the ability of the companion chip to see the entire address space as the CPU accesses it and can thus use the CPU address space efficiently by allocating it to other devices. For example, if the ROM space is greater than 2 Mbytes in size, but ROM is 2 Mbytes is size, other devices can be mapped at the address 2 MEG+1.
This design also has its disadvantages however. When dealing with devices that cannot operate in a multiplex mode and which require a parallel bus architecture, such as ROM and FLASH memory, the companion chip must now have an address bus included in the package to be able to communicate to the ROM. This results in a larger companion chip die and package size due to the number of PINs required to generate an address bus and the cost per companion chip goes up. For example, 2 Megabytes of ROM, addressed as a byte addressable ROM, requires that 21 PINs be added to the companion chip package, and if an extremely large ROM space existed, such as on the order of 64 MEG, as many as 26 address PINs would need to be added to the companion chip in order to actually address the ROM. An additional drawback to a multiplexed bus architecture is that once the size of the address bus from the companion chip is set, larger address ROMs or devices that would require additional PINs for the increase in the address bus width cannot be used.
A modification to the multiplexed bus design is to add an address bus from the CPU to the ROM, and program the CPU so that when communicating to the ROM, the CPU will not use the multiplex mode, but instead will function in a parallel bus mode. This modification creates a number of its own problems however. As previously discussed, while communicating to the ROM in this mode, the companion chip is not receiving nor decoding the address information. So, again, this results is a loss of having a flexible memory map, thus losing the ability to control how far into ROM space the CPU is addressing.
Therefor, a need existed to provide an improved system and method of addressing memory and other peripheral devices, such as ROM. The improved system and method of addressing memory and other peripheral devices would make it possible for the companion chip to see the addresses when the CPU communicates with the ROM thus resulting in the ability to control how far into ROM space the CPU is addressing. Additionally, a need existed to limit the number of PINs required to be added to a companion chip for the multiplex mode of operation while still providing for an acceptable and flexible address space from a CPU to ROM and other peripheral devices.

Memory addressing system and method therefor


A computer data processing system executing a method for selecting an auction methodology for a buyer/supplier procurement process, wherein the method comprises determining an auction scope in the data processing system, determining an auction interaction in the data processing system, determining an auction control in the data processing system, determining an auction pricing in the data processing system, determining a set of auction closing rules in the data processing system, determining an auction iteration in the data processing system, and selecting an auction methodology based on the auction scope, the auction interaction, the auction control, the auction pricing, the auction closing rules, and the auction iteration.

1. Field of the Invention
The present invention generally relates to automated auction systems and methods, and more particularly to an automated auction system for use in buyer/supplier procurement processes.
2. Description of the Related Art
Customarily, buyers request bids on various types of products or services from suppliers. For example, companies routinely provide their suppliers with public and directed requests for information (RFI), requests for quotations (RFQ), and requests for proposals (RFP). In an effort to provide the requested information, companies often utilize web-based systems such as International Business Machine's Internet Quoting Tool (IQT), available from IBM, Armonk, N.Y., USA. Once the buyer receives all of the information, quotations, and/or proposals (i.e., bids) from the suppliers, the buyer analyzes the various bids to determine which supplier to select.
For example, IBM's IQT system provides the following. It provides a company's ability to respond to business opportunities by making relevant requests for products and services more visible. It provides an effective tool to create responses. Also, it brings web-based efficiency to the procurement process.
Specifically, the current IBM IQT system reduces administrative costs and cycle times because it eliminates the need to use conventional communication tools such as mailing or faxing. Furthermore, because buyers (companies) make more detailed and concise requests, the supplier knows exactly what the buyer (company) is asking and, consequently, the response is clearer and more accurate.
Generally, in a procurement process, a supplier is an entity responsible for providing quotations for products and/or services requested by a buyer. A buyer generates requests and evaluates responses to identify the most competitive supplier(s) to provide specific products or services. A request is a document created by a buyer for procuring products and/or services. The request is either in the form of a Request for Quote (RFQ), Request for Proposal (RFP), or a Request for Information (RFI). A response is an answer provided by a supplier to a request for products and/or services from a buyer.
A Request for Quote is a type of request whereby the buyer has the intention to award the work after completing the evaluation process. Usually, this type of request requires a standard response from the supplier(s) such as pricing and delivery information. Similarly, a Request for Proposal is a type of request whereby the buyer has the intention to award the work after completing the evaluation process. Usually, this type of request is more complex than an RFQ and requires more detailed information of the supplier(s) other than just pricing and delivery information. However, a Request for Information is a type of request whereby the buyer has no intention to award the work after completing the evaluation process. This type of request is usually for information gathering, market intelligence, and benchmarking.
Furthermore, there are two broad categories of requests, directed and public. A directed request is a request that is posted to specific companies to review or respond to, whereas a public request is a request that is posted to any and all suppliers. For example, public requests are posted on the Public Requests page on IBM's IQT web-based system. In the IQT system, a supplier does not have to be registered with the IQT to view a public request, but the supplier must be registered to respond.
The concept of receiving bids from suppliers is well-known in business. It is also known that reviewing each bid and comparing them against other bids often results in unnecessary increases in cycle times and administrative costs. Thus, it is critical that a structured methodology become available to aid professionals in reducing cycle times and administrative costs, as well as achieving other efficiencies in the procurement process.
While the conventional IQT process provides a valuable system of providing and gathering information, and consolidating requests for buyers, there remains a need for a new automated system which can be used in conjunction with the current IQT processes and which provides an auction methodology to be used during RFQ, RFP, or RFI processes.

Process for determining an auction methodology

International Business Machines Corporation