In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.

The present invention relates to a semiconductor device, particularly to a multi-chips module (MCM) type semiconductor device adapted to be mounted on a board and to be electrically connected to the board.
JP-A-11-220077 discloses that a coefficient of thermal expansion and so forth is adjusted to restrain a crack of a semiconductor element and/or an under-fill in a flip-chip type semiconductor device. JP-A-2000-40775 discloses a shape of an oblique surface of the under-fill is adjusted to restrain the crack of the semiconductor element.
An object of the present invention is to provide a semiconductor device in which an excessive stress, for example, an excessive thermal stress is restrained to maintain a reliability of the semiconductor device.
In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.
Since the thickness of the each of the semiconductor electric chips in the direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than the thickness of the substrate in the direction, a bending rigidity of the each of the semiconductor electric chips is kept small while a bending rigidity of the substrate is kept great. Therefore, a stress in and on the each of the semiconductor electric chips is kept small when the semiconductor device is bent with a thermal deformation thereof and/or an external force applied to the semiconductor device.
When a Young""s modulus of the semiconductor electric chips is larger than a Young""s modulus of the substrate, it is more important that the bending rigidity of the each of the semiconductor electric chips is kept small, because, the greater the Young""s modulus of the semiconductor electric chips is, the greater the stress in and on the each of the semiconductor electric chips is. When a linear expansion coefficient of the semiconductor electric chips is smaller than a linear expansion coefficient of the substrate, it is more important that the bending rigidity of the each of the semiconductor electric chips is kept small. The semiconductor electric chips may be distant away from each other in a direction perpendicular to the direction.
The semiconductor device may further comprise a synthetic resin layer connected to the each of the semiconductor electric chips and the substrate so that the each of the semiconductor electric chips is connected to the substrate through the synthetic resin layer. When the Young""s modulus of the semiconductor electric chips is larger than a Young""s modulus of the synthetic resin layer, it is more important that the bending rigidity of the each of the semiconductor electric chips is kept small, because, the greater the Young""s modulus of the semiconductor electric chips is, the greater the stress in and on the each of the semiconductor electric chips is. When the linear expansion coefficient of the semiconductor electric chips is smaller than a linear expansion coefficient of the synthetic resin layer, it is more important that the bending rigidity of the each of the semiconductor electric chips is kept small. When the semiconductor device further comprises an electrically conductive member through which the each of the semiconductor electric chips is electrically connected to the substrate, it is preferable for reinforcing effectively the electrically conductive member that the electrically conductive member is surrounded by the synthetic resin layer. When the semiconductor device further comprises the electrically conductive member through which the each of the semiconductor electric chips is electrically connected to the substrate, and an electrically insulating layer including synthetic resin arranged between the synthetic resin layer and the semiconductor electric chips so that the synthetic resin layer is connected to the semiconductor electric chips through the electrically insulating layer and including a surface extending perpendicular to the direction, it is preferable for restraining the excessive stress on the electrically conductive member when the semiconductor device is bent that the electrically conductive member extends on the surface between the electrically insulating layer and the synthetic resin layer. It is preferable that a Young""s modulus of the synthetic resin layer under DMA measuring is not more than 10 GPA, and a linear expansion coefficient of the synthetic resin layer under TMA measuring is not more than 35xc3x9710xe2x88x926Kxe2x88x921.
When the semiconductor device further comprises a metallic member connected to the semiconductor electric chips, and an adhesive through which the metallic member connected to the semiconductor electric chips, it is preferable for restraining the excessive stress on the semiconductor electric chips that a Young""s modulus of the adhesive is smaller than a Young""s modulus of the semiconductor electric chips.
When the each of the semiconductor electric chips includes a first surface facing to the substrate and a second surface as a reverse surface with respect to the first surface, it is preferable for restraining a crack on the semiconductor electric chips that the second surface of at least one of the semiconductor electric chips is a grinder-finished surface, because a maximum principal stress is generated on the second surface when the semiconductor device is bent by the internal thermal deformation or the external force.
The thickness of the each of the semiconductor electric chips may be not more than 50% of the thickness of the substrate. It is more preferable that the thickness of the each of the semiconductor electric chips is not more than 30% of the thickness of the substrate. It is preferable that 12 less than As (xc3x9710xe2x88x926Kxe2x88x921)xe2x89xa620 and tc/tsxe2x89xa6xe2x88x92xe2x88x920.04As+1.1 when a linear expansion coefficient of the substrate under TMA measuring is As, and a thickness of the each of the semiconductor chips is tc and a thickness of the substrate is ts.
It is proved on the basis of theoretical calculations as follows that the present invention is effective in various cases. A thermal stress on and in the semiconductor electric chip in a temperature variation range between xe2x88x9255xc2x0 C. and 125xc2x0 C. was calculated by two-dimensional elasticity analysis of finite element method. FIG. 2 shows a model of a semiconductor device to be analyzed. Principal stresses at a point A (central position of reverse surface of semiconductor chip) and at a point B (upper end of oblique surface of under fill joining surface of semiconductor chip) are calculated as important values by which whether or not a crack occurs in the semiconductor device is judged. A size of finite element of the semiconductor electric chip is set at 0.1 mmxc3x970.05 mm for the calculation, because the point B is a stress concentration point at which the stress has a singularity.
As shown in FIG. 3 showing a calculation result, the principal stresses at the point A and B do not changed significantly in accordance with a number of the semiconductor electric chips on the substrate and/or a distance between the semiconductor electric chips. As shown in FIG. 4 showing a calculation result, the principal stresses at the point A and B do not changed significantly in accordance with a width of the semiconductor electric chip. As shown in FIG. 5 showing a calculation result, the principal stresses at the point A and B do not changed significantly in accordance with a width of the substrate. FIG. 6 shows dimensions of the under fill oblique surface in the model of a semiconductor device to be analyzed. As shown in FIG. 7 showing a calculation result, the stress at the point A does not change in accordance with the shape of the under fill oblique surface, and the stress becomes the maximum value at the point B when the point B (upper end of under fill oblique surface) is formed at the lower end of the semiconductor electric chip and an angle between the under fill oblique surface and the upper surface of the substrate is 45 degrees (h=1). As shown in FIG. 8 showing a calculation result, the principal stresses at the point A and B do not changed significantly in accordance with a difference in shape between the under fill oblique surfaces. As shown in FIG. 9 showing a calculation result, the principal stresses at the point A and B do not changed significantly in accordance with whether or not the under fills under the semiconductor electric chips are connected to each other.
Therefore, the principal stress at the point B formed at the lower end of the semiconductor electric chip with the angle of 45 degrees between the under fill oblique surface and the upper surface of the substrate as the maximum value of the principal stress in the semiconductor device was calculated as follows, while a number of the semiconductor electric chip on the substrate is 1, a width of the semiconductor electric chip is about 7 mm, a width of the substrate is about 25 mm, the thickness of the semiconductor electric chip is changed, the thickness of the substrate is changed, the coefficient of linear expansion of the substrate is changed, the coefficient of linear expansion of the under fill is changed, the Young""s modulus of the under fill is changed, the Young""s modulus of the semiconductor electric chip is fixed to about 190 GPA as the average Young""s modulus value of semiconductor materials such as silicon, the coefficient of linear expansion of the semiconductor electric chip is fixed to about 3xc3x9710xe2x88x926Kxe2x88x921 as the average Young""s modulus value of semiconductor materials such as silicon, and the Young""s modulus of the substrate is fixed to about 20 GPA as the average Young""s modulus value of resin substrate materials such as glass-epoxy. The stress in and on the semiconductor electric chip changes significantly in accordance with the coefficient of linear expansion of the substrate, but does not change significantly in accordance with the Young""s modulus of the substrate.
As shown in FIG. 10a showing a principal stress calculation result at the point A, and FIG. 10b showing a principal stress calculation result at the point B, when a critical principal stress is a value of principal stress on the semiconductor chip at which value a crack occurs on the semiconductor chip in a cyclic temperature change test, the Young""s modulus of the under fill is about 10 GPA, and the coefficient of linear expansion of the under fill is about 35xc3x9710xe2x88x926Kxe2x88x921, the principal stress at the point A decreases abruptly in accordance with a decrease of a ratio of semiconductor chip thickness/substrate thickness when the ratio is less than 1, and the principal stress at the point B decreases abruptly in accordance with the decrease of the ratio of semiconductor chip thickness/substrate thickness.
As shown in FIG. 11a showing a principal stress calculation result at the point A, and FIG. 11b showing a principal stress calculation result at the point B, when the coefficient of linear expansion of the substrate is 15xc3x9710xe2x88x926Kxe2x88x921, the Young""s modulus of the under fill is changed between about 10 GPA and about 6 GPA of the Young""s modulus of the usually used under fills, and the coefficient of linear expansion of the under fill is changed between about 35xc3x9710xe2x88x926Kxe2x88x921 and about 30xc3x9710xe2x88x926Kxe2x88x921 of the coefficient of linear expansion of the usually used under fills, the principal stress at the point A does not change significantly in accordance with the coefficient of linear expansion and Young""s modulus of the under fill, and the principal stress at the point B decreases in accordance with the decreases of each of the coefficient of linear expansion and Young""s modulus of the under fill.
It is understood from the principal stress calculation results as shown in FIGS. 10a, 10b, 11a and 11b that the smaller the thickness of the semiconductor chip is, the smaller the principal stress in the semiconductor device is, when the ratio of semiconductor chip thickness/substrate thickness when the ratio is less than 1. Further, it is preferable for each of the coefficient of linear expansion of the substrate, the coefficient of linear expansion of the under fill and the Young""s modulus of the under fill to be as small as possible. In order to decrease the principal stress in the semiconductor device to less than the critical principal stress so that the crack in the semiconductor device is restrained from occurring, it is necessary that the thickness of the semiconductor chip is not more than 50% of the thickness of the substrate when the Young""s modulus of the under fill is not more than about 10 GPA, the coefficient of linear expansion of the under fill is not more than about 35xc3x9710xe2x88x926K-1, and the coefficient of linear expansion of the substrate is not more than about 20xc3x9710xe2x88x926Kxe2x88x921, or it is necessary that the thickness of the semiconductor chip is not more than 30% of the thickness of the substrate when the Young""s modulus of the under fill is not more than about 10 GPA, the coefficient of linear expansion of the under fill is not more than about 35xc3x9710xe2x88x926Kxe2x88x921, and the coefficient of linear expansion of the substrate is not more than about 15xc3x9710xe2x88x926Kxe2x88x921. For example, 12 less than As (xc3x9710xe2x88x926Kxe2x88x921)xe2x89xa620 and tc/tsxe2x89xa6xe2x88x920.04As+1.1 when the linear expansion coefficient of the substrate is As(xc3x9710xe2x88x926Kxe2x88x921), and the thickness of the semiconductor chip is tc and the thickness of the substrate is ts.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.


Rare-earth-Ba-Cu-O superconductors having improved critical current density are described, as are methods of making same. These superconductors comprise a drop in Jc of less than a factor of about 7 at a temperature of between about 30K to about 77K, and at a magnetic field of about 1 Tesla, when the magnetic field is applied normal to the surface of the superconductor, as compared to a Jc in the presence of no magnetic field. These superconductors, when a magnetic field is applied perpendicular to the HTS surface have a peak Jc that is about 50-90%, and when a magnetic field is applied in any orientation with respect to the HTS surface have a Jc value that is at least about 50%, of the peak Jc that exists when the magnetic field is applied parallel to the surface of the superconductor.

Initially, the first generation of superconductors included materials that exhibited superconducting properties at temperatures only below about 20K. These were known as low temperature superconductors. New, second-generation high temperature superconductors (HTS) are now being developed. These second-generation HTS are resistance-free conductors made of ceramic materials that exhibit superconducting properties at temperatures between about 25-130 K, which therefore require less expensive cooling systems than those needed for low temperature superconductors.
Several commercial electric power and military applications would benefit from the use of second-generation high temperature superconductors. However, there are presently several hurdles that need to be overcome before high temperature superconductors can be successfully utilized in such applications. One obstacle that needs to be overcome is that the superconducting material must be able to operate in the high magnetic fields that such devices operate at. The magnetic field that the superconducting material will experience in many such devices (i.e., commercial generators and motors, and most military applications) may be in the range of 1-5 Tesla. In a typical coated superconductor tape, when a magnetic field of 1 Tesla is applied perpendicular to the tape's surface, the critical current density decreases by a factor of about seven to about ten from its self-field value. As a result, in order to achieve 100 A/cm in a magnetic field of 1 Tesla at 77K, a critical current density of 1 MA/cm2 needs to be achieved in a 1 micron thick film at 1 Tesla and 77K. Such high levels of critical current densities have not yet been demonstrated, not even in short lengths of coated superconducting tape.
In attempts to increase the performance of high temperature superconductors in high magnetic fields, some present high temperature superconductor prototype devices are being cooled to about 30K. However, cooling these devices to this low temperature increases the operational costs of the superconductor, and decreases the reliability thereof.
Other attempts to increase the performance of high temperature superconductors in high magnetic fields involve utilizing thick films. However, making thick films is a complex and expensive process, and only limited success has been achieved by utilizing this technique. Essentially, to achieve 100 A/cm at 1 Tesla and 77K, a critical current of 700 to 1000 A/cm width has to be achieved at zero applied field and 77K, and this level of performance has not yet been achieved in thick films. Furthermore, increasing the film thickness reduces manufacturing throughput and increases material costs.
Therefore, there is a need for high temperature superconductors that can operate at high temperatures and high magnetic fields. Such high performance HTS materials would ideally comprise rare-earth-Ba—Cu—O coated superconductors. It would be desirable to have such HTS materials comprise yttrium (Y) and/or heavy rare earth materials such as samarium (Sm), ytterbium (Yb), neodymium (Nd), gadolinium (Gd), europium (Eu), lanthanum (La), dysprosium (Dy), holmium (Ho), and/or mixtures thereof. It would be desirable to have such HTS materials have a superior critical current density. Ideally, these HTS would possess superior performance in the presence of a magnetic field (i.e., achieve 100 A/cm at 1 Tesla and 77K). It would be further desirable to have such HTS materials have minimal degradation of Jc when a magnetic field is applied normal to the surface of the HTS. For example, it would be desirable to have such HTS materials have a drop in Jc of less than a factor of about 7 at a temperature of about 30-77K, and at a magnetic field of about 1 Tesla, when the magnetic field is applied normal to the surface of the HTS. It would be yet further desirable to have such HTS materials have a peak Jc when a magnetic field is applied perpendicular to the surface of the HTS that is at least about 50% of the peak Jc that exists when the magnetic field is applied parallel to the surface of the HTS. It would be even further desirable to have such HTS materials have a Jc value when a magnetic field is applied in any orientation with respect to the HTS surface that is at least about 50% of the peak Jc that exists when the magnetic field is applied parallel to the surface of the HTS. It would be yet further desirable to have such HTS materials comprise kilometer lengths of metal tape as the substrate. It would be still further desirable to be able to make such HTS materials in a manner that allows suitably high manufacturing rates to be achieved. Many other needs will also be met by this invention, as will become more apparent throughout the remainder of the disclosure that follows.

Rare-earth-Ba-Cu-O superconductors and methods of making same


An internal combustion engine includes a cylinder head including an intake port, an exhaust port, a water jacket, an intake valve, an exhaust valve, an intake valve seat, and an exhaust valve seat. The water jacket is positioned between the intake port and the exhaust port. The intake valve includes an intake valve head, and the exhaust valve includes an exhaust valve head. The intake valve contacts an intake valve seat surface of the intake valve seat. The exhaust valve head contacts an exhaust valve seat surface of the exhaust valve seat. The shortest distance between the water jacket and the intake valve seat surface is shorter than the shortest distance between the water jacket and the exhaust valve seat surface.

1. Field
The disclosure relates to an internal combustion engine having an intake valve and an exhaust valve.
2. Description of Related Art
In a cylinder head of an internal combustion engine, a valve seat, which a head of a valve contacts, is provided in a connecting part in which an intake port is connected with a combustion chamber. Also, in a connecting part in which an exhaust port is connected with the combustion chamber, a valve seat is provided. A head of a valve contacts the valve seat.
As a valve seat provided in a cylinder head as stated above, there is known a seat that is formed by performing cladding on the above-mentioned connecting part of the cylinder head. For example, Japanese Patent Application Publication No. 2008-188648 (JP 2008-188648 A) discloses a valve seat cladded on the connecting part by feeding metal powder in the connecting part of the cylinder head while irradiating the connecting part with a laser beam. This type of valve seat has a high a degree of adhesion to the cylinder head, and heat transfer efficiency to the cylinder head is high. Therefore, it is possible to favorably restrain an increase in temperature of the valve seat and the head of the valve.
In the cylinder head disclosed in JP 2008-188648 A, the intake valve seat and the exhaust valve seat are both formed by cladding.


A polishing apparatus includes: a turntable for supporting a polishing pad; a turntable rotation mechanism configured to rotate the turntable; a dresser configured to dress the polishing pad; and a scanning mechanism configured to cause the dresser to scan between a first position and a second position on the polishing pad, wherein Ttt/Tds and Tds/Ttt are a non-integer where the Ttt is a rotation cycle of the turntable during dressing, and the Tds is a scanning cycle during which the dresser scans between the first position and the second position.

A polishing apparatus represented by a chemical mechanical polishing (CMP) apparatus polishes a substrate surface by relatively moving both of a polishing pad and the substrate surface to be polished in a contacted state. Consequently, the polishing pad is gradually worn away, and fine roughness on a surface of the polishing pad is crushed, which may decrease a polishing rate. Therefore, the fine roughness needs to be reformed on the polishing pad surface by dressing the polishing pad surface by a dresser in which a plurality of diamond particles is electrically deposited on a surface and a dresser having a brush on a surface (for example, JP 9-300207 A and JP 2010-76049 A).
Conventionally, dressing is usually performed by using a dresser having a size which can cover a whole polishing pad (for example, JP 9-300207 A). However, in recent years, a substrate is increased in size, and to prevent a related increase in size of a polishing apparatus to the extent possible, a small-sized dresser is used (for example JP 2010-76049 A). In the case where a dresser is smaller than a polishing pad, there is a problem that it is difficult to uniform the polishing pad.
Therefore, it is desirable to provide a polishing apparatus capable of uniforming a polishing pad by a small dresser, a method for controlling the same, and a dressing condition output method.
According to one embodiment, a polishing apparatus includes: a turntable for supporting a polishing pad; a turntable rotation mechanism configured to rotate the turntable; a dresser configured to dress the polishing pad; and a scanning mechanism configured to cause the dresser to scan between a first position and a second position on the polishing pad, wherein Ttt/Tds and Tds/Ttt are a non-integer where the Ttt is a rotation cycle of the turntable during dressing, and the Tds is a scanning cycle during which the dresser scans between the first position and the second position.
According to another embodiment, a polishing apparatus including: a turntable for supporting a polishing pad; a turntable rotation mechanism configured to rotate the turntable; a dresser configured to dress the polishing pad; a pressing mechanism configured to press the dresser against the polishing pad; and a scanning mechanism configured the dresser to scan between a first position and a second position of the polishing pad, wherein V(t)A(t)/r(t) is substantially constant where the V(t) is a relative speed between the dresser and the polishing pad at a time t, the r(t) is a distance between a center of the turntable and a center of the dresser at a time t, and the A(t) is a pressing force or a pressure of the dresser against the polishing pad at a time t.
According to another embodiment, a control method for a polishing apparatus, the method including: providing a turntable for supporting a polishing pad, a turntable rotation mechanism, a dresser, a scanning mechanism, and a controller; and controlling the turntable rotation mechanism and the scanning mechanism such that Ttt/Tds and Tds/Ttt become non-integers in a case where a rotation cycle of the turntable during dressing is denoted by Ttt, and a scanning cycle in which the dresser scans between a first position and a second position on the polishing pad is denoted by Tds.
According to another embodiment, a control method for a polishing apparatus, the method including: providing a turntable for supporting a polishing pad, a turntable rotation mechanism, a dresser, a pressing mechanism, a scanning mechanism, and a controller; and controlling the turntable rotation mechanism, the pressing mechanism, and the scanning mechanism such that V(t)A(t)/r(t) becomes substantially constant where the V(t) is a relative speed between the dresser and the polishing pad at a time t, the r(t) is a distance between a center of the turntable and a center of the dresser at a time t, and the A(t) is a pressing force or a pressure of the dresser against the polishing pad at a time t.
According to another embodiment, a dressing condition output method for a polishing apparatus, the method including: preparing a turntable for supporting a polishing pad, a turntable rotation mechanism a dresser, a scanning mechanism, and a controller; receiving a restriction condition; first referring to a database previously storing a first condition which is a dressing condition capable of uniformly dressing the polishing pad and a second condition which is a dressing condition incapable of uniformly dressing the polishing pad, and outputting the first condition in a case where the first condition satisfying the restriction condition is stored in the database; calculating a dressing condition in a case where the first condition satisfying the restriction condition is not stored; and second referring to the database to output the calculated dressing condition in a case where the calculated dressing condition and the second condition are not matched, wherein, upon calculating the dressing condition, the dressing condition is calculated such that Ttt/Tds and Tds/Ttt become non-integers where the Ttt is a rotation cycle of the turntable during dressing, and the Tds is a scanning cycle during which the dresser scans between a first position and a second position on the polishing pad.
According to another embodiment, a method for outputting a dressing condition for a polishing apparatus, the method including: supplying a turntable for supporting a polishing pad, a turntable rotation mechanism, a dresser, a pressing mechanism, a scanning mechanism, and a controller; and receiving a restriction condition; first referring to a database preliminary storing the first condition which is a dressing condition capable of uniformly dressing the polishing pad and a second condition which is a dressing condition incapable of uniformly dressing the polishing pad, and outputting a first condition in a case where the first condition satisfying the control condition is stored in the database; calculating a dressing condition in a case where the first condition satisfying the restriction condition is not stored; and second referring to the database to output the calculated dressing condition in a case where the calculated dressing condition and the second condition are not matched, wherein, upon calculating the dressing condition, the dressing condition is calculated such that V(t)A(t)/r(t) becomes substantially constant where the V(t) is a relative speed between the dresser and the polishing pad at a time t, the r(t) is a distance between a center of the turntable and a center of the dresser at a time t, and the A(t) is a pressing force or a pressure of the dresser against the polishing pad at a time t.

Polishing apparatus, method for controlling the same, and method for outputting a dressing condition


A bottle opener for opening a bottle in an efficient manner. The bottle opener includes a substantially rigid panel having a first surface, a second surface, a third surface and a fourth surface wherein the first and second surfaces are opposite surfaces. The third and fourth surfaces have a length greater than a length of the first and second surfaces. The panel has a first portion, a middle portion and a second portion wherein the first portion is adjacent to the first surface and the second portion is adjacent to the second surface. The panel has a first opening therein positioned in the middle portion. The first opening has a generally rectangular shape. A bottle cap is positioned in the opening and the panel biased against the bottle cap to remove the bottle cap.

1. Field of the Invention
The present invention relates to bottle openers and more particularly pertains to a new bottle opener for opening a bottle in an efficient manner.
2. Description of the Prior Art
The use of bottle openers is known in the prior art. More specifically, bottle openers heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art includes U.S. Pat. Nos. 4,805,238; 5,133,233; 5,261,299; 4,894,866; 4,967,622; and Des. 407,283.
While these devices fulfill their respective, particular objectives and requirements, the aforementioned patents do not disclose a new bottle opener. The inventive device includes a substantially rigid panel having a first surface, a second surface, a third surface and a fourth surface wherein the first and second surfaces are opposite surfaces. The third and fourth surfaces have a length greater than a length of the first and second surfaces. The panel has a first portion, a middle portion and a second portion wherein the first portion is adjacent to the first surface and the second portion is adjacent to the second surface. The panel has a first opening therein positioned in the middle portion. The first opening has a generally rectangular shape. A bottle cap is positioned in the opening and the panel biased against the bottle cap to remove the bottle cap.
In these respects, the bottle opener according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of opening a bottle in an efficient manner.
In view of the foregoing disadvantages inherent in the known types of bottle openers now present in the prior art, the present invention provides a new bottle opener construction wherein the same can be utilized for opening a bottle in an efficient manner.
The general purpose of the present invention, which will be described subsequently in greater detail, is to provide a new bottle opener apparatus and method which has many of the advantages of the bottle openers mentioned heretofore and many novel features that result in a new bottle opener which is not anticipated, rendered obvious, suggested, or even implied by any of the prior art bottle openers, either alone or in any combination thereof.
To attain this, the present invention generally comprises a substantially rigid panel having a first surface, a second surface, a third surface and a fourth surface wherein the first and second surfaces are opposite surfaces. The third and fourth surfaces have a length greater than a length of the first and second surfaces. The panel has a first portion, a middle portion and a second portion wherein the first portion is adjacent to the first surface and the second portion is adjacent to the second surface. The panel has a first opening therein positioned in the middle portion. The first opening has a generally rectangular shape. A bottle cap is positioned in the opening and the panel biased against the bottle cap to remove the bottle cap.
There has thus been outlined, rather broadly, the more important features of the invention in order that the detailed description thereof that follows may be better understood, and in order that the present contribution to the art may be better appreciated. There are additional features of the invention that will be described hereinafter and which will form the subject matter of the claims appended hereto.
In this respect, before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not limited in its application to the details of construction and to the arrangements of the components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting.
As such, those skilled in the art will appreciate that the conception, upon which this disclosure is based, may readily be utilized as a basis for the designing of other structures, methods and systems for carrying out the several purposes of the present invention. It is important, therefore, that the claims be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the present invention.
Further, the purpose of the foregoing abstract is to enable the U.S. Patent and Trademark Office and the public generally, and especially the scientists, engineers and practitioners in the art who are not familiar with patent or legal terms or phraseology, to determine quickly from a cursory inspection the nature and essence of the technical disclosure of the application. The abstract is neither intended to define the invention of the application, which is measured by the claims, nor is it intended to be limiting as to the scope of the invention in any way.
It is therefore an object of the present invention to provide a new bottle opener apparatus and method which has many of the advantages of the bottle openers mentioned heretofore and many novel features that result in a new bottle opener which is not anticipated, rendered obvious, suggested, or even implied by any of the prior art bottle openers, either alone or in any combination thereof.
It is another object of the present invention to provide a new bottle opener which may be easily and efficiently manufactured and marketed.
It is a further object of the present invention to provide a new bottle opener which is of a durable and reliable construction.
An even further object of the present invention is to provide a new bottle opener which is susceptible of a low cost of manufacture with regard to both materials and labor, and which accordingly is then susceptible of low prices of sale to the consuming public, thereby making such bottle opener economically available to the buying public.
Still yet another object of the present invention is to provide a new bottle opener which provides in the apparatuses and methods, of the prior art some of the advantages thereof, while simultaneously overcoming some of the disadvantages normally associated therewith.
Still another object of the present invention is to provide a new bottle opener for opening a bottle in an efficient manner.
Yet another object of the present invention is to provide a new bottle opener which includes a substantially rigid panel having a first surface, a second surface, a third surface and a fourth surface wherein the first and second surfaces arc opposite surfaces. The third and fourth surfaces have a length greater than a length of the first and second surfaces. The panel has a first portion, a middle portion and a second portion wherein the first portion is adjacent to the first surface and the second portion is adjacent to the second surface. The panel has a first opening therein positioned in the middle portion. The first opening has a generally rectangular shape. A bottle cap is positioned in the opening and the panel biased against the bottle cap to remove the bottle cap.
Still yet another object of the present invention is to provide a new bottle opener that allows a user, such as a bartender, the ability to open up a plurality of bottles in a quick manner with little risk of injury.
Even still another object of the present invention is to provide a new bottle opener that has an adjustable strap for fitting many sized hands for allowing the user to use the leverage of their entire arm when opening a bottle.
These together with other objects of the invention, along with the various features of novelty which characterize the invention, are pointed out with particularity in the claims annexed to and forming a part of this disclosure. For a better understanding of the invention, its operating advantages and the specific objects attained by its uses, reference should be made to the accompanying drawings and descriptive matter in which there are illustrated preferred embodiments of the invention.


A demodulation circuit for demodulating a frequency diverse complex modulated carrier comprises an A/D converter generating a series of samples representing the modulated carrier, a mixer operating to mix the series of samples with a sine wave of one fourth the sampling frequency represented by a series of sine wave values occurring at the sampling frequency, and a decimation filter operating at a decimation factor equal to the sampling frequency divided by the frequency difference between adjacent sub-spectra for folding the sub-spectra and retaining a portion of the mixed down series of samples.

The present invention relates generally to network interfacing, and more particularly, to an apparatus and method for mixing down and spectrum folding a frequency diverse modulated carrier to baseband in a network communications receiver.
The transmission of various types of digital data between computers continues to grow in importance. The predominant method of transmitting such digital data includes coding the digital data into a low frequency baseband data signal and modulating the baseband data signal onto a high frequency carrier signal. The high frequency carrier signal is then transmitted across a network physical transmission medium such as electrical cable, fiber optic, RF, or other medium to a remote computing station.
At the remote computing station, the high frequency carrier signal must be received and demodulated to recover the original baseband signal. In the absence of any distortion across the network medium, the received signal would be identical in phase, amplitude, and frequency to the transmitted carrier and could be demodulated using known mixing techniques to recover the baseband signal. The baseband signal could then be recovered into digital data using known sampling algorithms.
One problem with such networks is that the physical medium and network topology tend to distort the high frequency carrier signal. Branch connections and different lengths of such branches cause reflections of the transmitted signal. Such problems are even more apparent in a network which uses home telephone wiring cables as the network physical medium. The typical wiring of the telephone network is designed for the xe2x80x9cplain old telephone servicexe2x80x9d (POTS) signals in the 3-10 kilohertz frequency and are not designed for transmission of high frequency carrier signals in a frequency range greater than 1 MHz. The high frequency carrier signal is also distorted by transients in wiring characteristics due to on-hook and off-hook switching and noise pulses of the POTS (e.g. ringing). The high frequency carrier is further distorted by spurious noise caused by electrical devices operating in close proximity to the xe2x80x9ccablexe2x80x9d medium.
Such distortion of frequency, amplitude, and phase of the high frequency carrier signal degrades network performance and tends to impede the design of higher data rate networks. Known techniques for compensating for such distortion and improving the data rate of a network include complex modulation schemes and frequency diversity.
Utilizing a complex modulation scheme such as quadrature amplitude modulation (QAM), both the amplitude and phase of the high frequency carrier are modulated to represent I and Q components of a baseband signal. Referring to FIG. 1, a 4-QAM modulation constellation 10 is shown. In operation, each data symbol is represented by an I-value of +1 or xe2x88x921 and a Q-value of +1 or xe2x88x921 such that the data symbol can be represented by one of the four states 12(a)-(d) in constellation 10. Each constellation pointy 12(a)-12(d) represents a unique combination of carrier amplitude and phase. For example, constellation point 12(a) represents a carrier amplitude of 14 and a carrier phase 16.
FIG. 2 illustrates the utilization of frequency diversity by transmitting the same data in three mutually exclusive sub-spectra 18(a)-(c) of the transmission band 20. Therefore, if a portion of the band is distorted (e.g. one or more of the sub-spectra 18(a)-(c)), the data may still be recovered at the receiver from a less distorted portion of the sub-spectra 18(a)-(c). For example, a data signal modulated onto a 7 MHz carrier utilizing 6 MHz of bandwidth may include three mutually exclusive sub-bands 18(a)-(c) centered at 5 MHz, 7 MHz and 9 MHz.
One approach to demodulating such complex signals is to use filters implemented by digital signal processing (DSP), which provides for a convenient way of varying filter coefficients for each transmission to accommodate carrier distortion as detected in the particular time frame in which the data is being transmitted. Using such approach, the receiver compares the distorted received signal representing a known preamble transmission (prior to the data transmission) to the undistorted waveform of the preamble and determines the appropriate filter coefficients for recovery of the received signal. Such filter coefficients are then used for receiving the data transmission.
In accordance with DSP technology, the high frequency carrier is typically sampled with an A/D converter at a rate that is at least 4 times the carrier frequency. Assuming a carrier frequency on the order of 7 MHz, the sampling rate will be on the order of 30 MHz. A problem associated with processing digital samples at such rates to demodulate a complex modulated carrier, and to process mutually exclusive sub-bands of a frequency diverse system, is that very large and costly digital signal processing systems would be required. Therefore, based on recognized industry goals for size and cost reductions, what is needed is a device and method for recovering data signals from a received modulated carrier that do not suffer from the complexity disadvantages of known systems.
A first objective of the present invention is to provide a demodulation circuit comprising: a) an A/D converter running at a sampling frequency and generating a series of samples representing a frequency diverse modulated carrier; b) a mixer operating to mix the series of samples with a sine wave of one fourth the sampling frequency, represented by a series of sine wave values occurring at the sampling frequency, the mixer generates a mixed down signal of a series of samples occurring at the sampling frequency; and c) a decimation filter operating at a decimation factor equal to the sampling frequency divided by the frequency difference between adjacent sub-spectra for folding the sub-spectra and retaining a portion of the mixed down series of samples. The portion of the mixed down series of samples may occur at a slow sampling rate equal to the sampling rate divided by the decimation factor of the decimation filter.
The sine wave may have the same frequency as the modulated carrier such that the mixed down series of samples represents the original frequency diverse baseband signal. Alternatively, the sine wave may have a frequency other than that of the modulated carrier and the circuit may further comprise a second mixer operating to mix the portion of the mixed down series of samples with a second sine wave represented by a second series of sine wave values occurring at the slow sampling rate, the second mixer generating the baseband signal.
The mixed down series of samples may represent the I-channel of a system having complex constellation points. The system may further comprise: d) a Q-channel mixer operating to mix the series of samples with a cosine wave of one fourth the sampling frequency represented by a series of cosine wave values occurring at the sampling frequency, the Q-channel mixer generating a mixed down series of samples occurring at the sampling frequency; and e) a Q-channel decimation filter operating at a decimation factor equal to the sampling frequency divided by the frequency difference between adjacent sub-spectra for folding the sub-spectra and retaining a portion of the mixed down series of samples. Both the sine wave and the cosine wave may have the same frequency as the modulated carrier such that both the sine mixed down series of samples and the cosine mixed down series of samples represent the I-channel and the Q-channel of a frequency diverse baseband signal respectively. Alternatively, both the sine wave and the cosine wave may have a frequency other than that of the modulated carrier and the circuit may further comprise: f) a second mixer operating to mix the portion of the mixed down series of samples with a second sine wave represented by a second series of sine wave values occurring at the slow sampling rate, the second mixer generating a baseband signal; and g) a second Q-channel mixer operating to mix the portion of the cosine mixed down series of samples with a second cosine wave represented by a second series of cosine wave values occurring at the slow sampling rate, the second Q-channel mixer generating a baseband Q-channel signal.
Preferably, the sample frequency is 32 MHz, both the sine wave and the cosine wave have a frequency of 8 MHz, the decimation filter has a decimation factor of 16:1, and both the second sine wave and the second cosine wave have a frequency of 1 MHz.
A second objective of the present invention is to provide a method of folding adjacent sub-spectra of a frequency diverse modulated carrier signal, the method comprising: (a) selecting a sample frequency that is a multiple of the difference between adjacent sub-spectra; (b) sampling the modulated carrier at the sampling frequency to generate a series of samples; and (c) decimating the series of samples utilizing a decimation filter with a decimation factor equal to the sample frequency divided the difference between adjacent sub-spectra to generate a decimated series of samples. The method may further comprise mixing the series of samples with a sine wave with a frequency equal to that of the modulated carrier and represented by a series of values occurring at the sample frequency to down mix the modulated carrier to a baseband signal. The method may further yet include mixing the decimated series of samples with a second sine represented by a series of values occurring at the same frequency as that of the decimated series of samples to mix the decimated series of samples to baseband.

Method and apparatus for mixing down and spectrum folding frequency diverse modulated carrier


A method includes forming a hard mask over an epitaxy layer of a substrate; forming a patterned mask over the hard mask; etching the hard mask and the epitaxy layer to form a trench in the epitaxy layer, in which a remaining portion of the hard mask covers a topmost surface of the epitaxy layer, and the trench exposes a sidewall of the epitaxy layer; forming a P-well region by directing p-type ion beams into the trench along an oblique direction that is non-parallel to a normal line of the topmost surface of the epitaxy layer, in which the topmost surface of the epitaxy layer is protected from the p-type ion beams by the remaining portion of the hard mask during directing the p-type ion beams into the trench; and after directing the p-type ion beams into the trench, forming a gate structure in the trench.

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. Such advances have increased the complexity and challenges of processing and manufacturing of ICs.
Vertically-conducting trench MOSFETs (metal oxide semiconductor field effect transistors) can be used as power electronics. When a trench MOSFET is biased in the on state, current flows vertically between source regions and substrate. Reducing cell pitch of MOSFETs is crucial in reducing the device sizes and in increasing the number of active devices on a semiconductor chip. In addition, cell pitch also affects device performance, such as the resistivity between source and drain when the device is on (Rdson). Reducing cell pitch is limited by the manufacturing process technology, such as the capability of lithographical tool in resolving minimum critical dimension and in aligning different patterning layers. It is within this context the following disclosure arises.

Semiconductor device and manufacturing method thereof

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.


A method, computer program product, and a data processing system for maintaining object configuration data in a data processing system is provided. A first set of attribute entries is stored in a database. The first set of attribute entries is associated with a first object classification and a second object classification. A second set and a third set of attribute entries each including at least one attribute entry are stored in the database. The second set of attribute entries is associated with the first object classification, and the third set of attribute entries are associated with the second object classification. A first object of the first object classification is configured with the first set of attribute entries and the second set of attribute entries, and a second object of the second object classification is configured with the first set of attribute entries and the third set of attribute entries.

1. Technical Field
The present invention relates generally to an improved data processing system and in particular to a data processing system and method for maintaining attributes of multiple devices in association with a single device identifier. Still more particularly, the present invention provides a mechanism for overriding device default values within a data structure of device attributes with a single device identifier maintained in association with devices of different device classifications.
2. Description of Related Art
A conventional operating system implementation utilizes a group of device attributes to define attributes of system objects, such as peripheral adapters and devices. For example, the AIX operating system uses a group of device attributes implemented as predefined attribute objects (PdAt) that are managed by an object data manager (ODM). Attributes of a particular device classification are collectively grouped together based on a unique device identifier—for example, a uniquetype value associated with a classification of devices.
A uniquetype may support more than one device by way of model_map stanza. Devices that share a uniquetype all share the same initial values for the attributes defined by default entries of the PdAt. Devices requiring one or more different default values for a common attribute must be defined with separate uniquetypes. Thus, the performance of such a device is limited during system boot, install and operation until vendor specific ODM data, e.g., a PdAt entry for the device, is supplied.
It would be advantageous to provide a mechanism for maintaining attributes of multiple device types or classifications in association with a single device classification identifier. It would be further advantageous to provide a mechanism for maintaining attributes of multiple device classification having identical attribute sets in association with a single device classification identifier. It would still be further advantageous to provide a mechanism for overriding device default values within a data structure that supports association of device attributes with multiple device classifications via a single device classification identifier.

System and method for maintaining multiple devices with a single device identifier

International Business Machines Corporation


A knock sensor comprises a sensor body having a metallic shell including a cylindrical portion and a flange portion formed at an end of the cylindrical portion, an annular piezoelectric element fitted around the cylindrical portion and an annular weighting member fitted around the cylindrical portion to hold the piezoelectric element between the weighting member and the flange portion, and a resin-molded sensor casing arranged circumferentially around the sensor body. The resin-molded sensor casing includes a weighting portion located nearer to the weighting member than to the piezoelectric element with respect to an axial direction of the cylindrical portion, and at least the weighting portion of the resin-molded sensor casing is made of a resin containing at least one of metal powder and metal oxide powder and has a density of 2.0 g/cm3 or higher.

The present invention relates to a nonresonant type knock sensor that detects the occurrence of knocking in an internal combustion engine.
A knock sensor with a piezoelectric element is commonly used in an ignition control system of an internal combustion engine so as to detect the occurrence of knocking in the engine and thereby allow the control system to provide optimal ignition timing for the engine. There are two types of knock sensors: a resonant type and a nonresonant type. In the case of the nonresonant type knock sensor, the piezoelectric element receives a mechanical load due to engine vibrations caused by the knocking, converts the mechanical load into an electrical signal and outputs the electrical signal to the control system via a band-pass filter so that the control system reads the signal output in a frequency band corresponding to the knocking vibrations to find the occurrence of knocking in the engine.
Recently, there have been strict environmental regulations. When the piezoelectric element is made free from lead so as to be compliant with such strict environmental regulations, there is a possibility that the signal outputted from the lead-free piezoelectric element is so weak that the control system cannot determine whether the knocking is actually occurring in the engine. In order to avoid such a possibility, it is desired to improve the signal output characteristic of the nonresonant type knock sensor.
In consideration of the fact that the intensity of the output signal from the piezoelectric element depends on the mechanical load applied to the piezoelectric element, one conceivable way to improve the signal output characteristic of the sensor would be to increase the size of any part or portion of the sensor that weights down the piezoelectric element (such as a weighting member or resin-molded sensor casing) so as to add to its weight and thereby increase the mechanical load on the piezoelectric element as disclosed in Japanese Laid-Open Patent Publication No. 2-173530. However, this results in upsizing of the sensor. As there is only a limited space for mounting the knock sensor in the engine, it is difficult to improve the signal output characteristic of the sensor to a sufficient degree in the above-mentioned way.
The present invention has been made allowing for the above-mentioned circumstances, and an object of the present invention is to provide a nonresonant type knock sensor that has an increased mechanical load on its piezoelectric element without upsizing of the sensor for improvement in signal output characteristic.
According to a first aspect of the invention, there is provided a knock sensor, comprising: a sensor body having: a metallic shell including a cylindrical portion and a flange portion formed at an end of the cylindrical portion; an annular piezoelectric element fitted around the cylindrical portion; and an annular weighting member fitted around the cylindrical portion to hold the piezoelectric element between the weighting member and the flange portion; and a resin-molded sensor casing arranged circumferentially around the sensor body, wherein the resin-molded sensor casing includes a weighting portion located nearer to the weighting member than to the piezoelectric element with respect to an axial direction of the cylindrical portion, and at least the weighting portion of the resin-molded sensor casing is made of a resin containing at least one of metal powder and metal oxide powder and has a density of 2.0 g/cm3 or higher.
According to a second aspect of the invention, there is provided a knock sensor, comprising: a metallic shell including a cylindrical portion and a flange portion formed at an end of the cylindrical portion; an annular piezoelectric element fitted around the cylindrical portion; and an annular weighting member fitted around the cylindrical portion to hold the piezoelectric element between the weighting member and the flange portion, wherein at least the flange portion of the metallic shell is made of a material having a lower specific gravity than that of iron.
According to a third aspect of the invention, there is provided a knock sensor, comprising: a metallic shell including a cylindrical portion and a flange portion formed at an end of the cylindrical portion; an annular piezoelectric element fitted around the cylindrical portion; and an annular weighting member fitted around the cylindrical portion to hold the piezoelectric element between the weighting member and the flange portion, wherein the flange portion has at least one cut formed therein to reduce the weight of the flange portion.


A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.

1. Field of the Invention
The invention relates generally to the field of stacked integrated circuits.
More specifically, the invention relates to using conductive stud bumps while processing bare integrated circuit die during neolayer lamination and potting for use in fabricating a stackable layer comprising one or more integrated circuit chips.
2. Description of the Related Art
The ability to fabricate very thin, stackable layers containing one or a plurality of homogeneous or heterogeneous integrated circuit chips is desirable and allows high density, high speed electronic systems to be assembled for use in military, space, security and other applications.
Examples of such layers and modules are disclosed in U.S. Pat. No. 6,072,234, Stack of Equal Layer Neo-Chips Containing Encapsulated IC Chips of Different Sizes; U.S. Pat. No. 6,797,537, Method of Making Stackable Layers Containing Encapsulated Integrated Circuit Chips With One or More Overlying Interconnect Layers; U.S. Pat. No. 6,784,547, Stackable Layers Containing Encapsulated Integrated Circuit Chips With One or More Overlying Interconnect Layers; U.S. Pat. No. 6,117,704, Stackable Layer Containing Encapsulated Chips; U.S. Pat. No. 5,953,588; Stackable Layers Containing Encapsulated IC Chips; and U.S. Pat. No. 7,768,113, Stackable Tier Structure Comprising Prefabricated High Density Feed-through.
The stacking and interconnection of very thin microelectronic layers permits high circuit speeds in part because of short lead lengths with related reduced parasitic impedance and reduced electron time-of-flight. These desirable features combined with a very high number of circuit and layer interconnections allow relatively large I/O designs to be implemented in a small volume.
The present invention provides a stackable integrated circuit chip (which integrated circuit chip is also herein referred to as an "IC" or "die") for use in multi-layer, microelectronic modules such as are disclosed in the above referenced patents. The use of potted and thinned stacked layers having rerouted die therein permits die having different functions, and therefore different areas, to be stacked as if they were same size die.
A prior art process for making a "neo-chip" or "neo-layer" involves the "potting" of individual IC chips in a encapsulant or compound which supports and insulates each chip and which can be cut or diced to provide equal area layers so that chips having different sizes can be stacked as layers whose edges are coplanar with one another. The individual chips, in die form, may be incorporated into neo-wafer form for processing. Thereafter, layers are cut out of the neo-wafer and incorporated into stacks.
The prior art neo-layer processes may include the processing and stacking of chips purchased as individual die. Beneficially, chips purchased as individual die are generally "known good" die which have been "burned in" and are therefore pre-tested prior to stacking.
Prior to stacking, one or more known good die are used to create the "neo" wafer by locating those known good die in a potting fixture. Potting material is flowed into the fixture, which is enclosed and then the potting material is cured. The resulting "neo-wafer" is removed from the fixture and then subjected to pre-stacking process steps including spinning on a layer of dielectric material, forming vias through the dielectric material to reach the terminals on the die in the wafer, and then forming electrical conductors in the form of metal traces that lead from the die terminals on the surface of the dielectric layer or layers. Thereafter the neo-wafer is diced into one or more layers suitable for stacking, each layer containing at least one known good die.
Each layer of a completed stack has electrical leads in the form of conductive metal traces used to connect the IC circuitry of the embedded chip (or chips) to one or more access planes, where the traces are available for connection to exterior circuitry.
Major cost-saving benefits can be obtained by the sole use of "known good" die, and the use/of a neo-wafer in processing one or more of such die.
Neo-stacking offers significant improvements over silicon bare die stacking, but it also proved troublesome under certain market circumstances. In particular, it is often difficult to buy bare die because many manufacturers will only sell packaged die.
For instance, when trying to buy bare DRAM die from a particular manufacturer, it was discovered that the manufacturer would not sell bare DRAM die, but would sell the DRAM die already pre-tested and installed in prepackaged integrated circuit packages.
Because of the demand for die and the high capital investment necessary to be a mass manufacturer of them, it is difficult to induce a mass fabricator of die to supply only die as opposed to the usual finished product which is a packaged or encapsulated integrated circuit chip. Such mass fabricators are typically fully occupied with the manufacture of finished and packaged integrated circuits. Individual IC chips are not typically offered for sale either in wafer or in die form.
Even in those cases where a mass fabricator can be induced to manufacture and sell a bare functional die, the die may be delivered in wafers or diced without testing. In other words, a die is normally tested after it is connected to its lead frame and packaged on a lead frame or in an encapsulant to ascertain whether it is operable as intended. Mass testing of bare die is not a procedure that many mass fabricators are equipped or even inclined to do. Therefore, a purchaser of bare die must test each die individually in order to determine its operability or the yield. Bare die testing is too limited to ensure acceptable yields, while comprehensive testing and burn-in renders bare die production cost-ineffective. These problems are sometimes referred to as the "known good die" or "KGD" problem.
Because prepackaged die are burned in and therefore contain known good die, it is desirable to depackage the known good die within a prepackaged IC package for use in certain applications such as for use in the above neo-processes.
Unfortunately, for both die obtained as bare die and depackaged die, during the processing steps of neowafer fabrication, certain elements of the bare die, particularly the aluminum contact pads, are prone to corrosion caused by chemicals used during lithography or elsewhere in the process; particularly corrosion on the side aluminum walls of the IC contact pads when nickel and palladium are present on the surface of the aluminum contact pads.
Additionally, some circuit elements on the bare die that are used in the neolayer process are sensitive to the radiation used in certain process steps and can be damaged by exposure thereto.
What is needed is a neolayer fabrication method that protects the aluminum IC pads from corrosion and any active IC circuit elements from radiation during processing and that provides a neolayer for use as a stackable layer in a multi-layer electronic module.

Method for fabricating a neo-layer using stud bumped bare die


Aluminophosphate compounds and compositions as can be used for substrate or composite films and coating to provide or enhance, without limitation, planarization, anti-biofouling and/or anti-microbial properties.

Advanced alloys, including nickel-based superalloys, intermetallics of titanium-aluminum, niobium-aluminum, titanium-silicon, molybdenum-silicon-boron and others are used extensively for high temperature applications due to their desirable mechanical properties. However, their environmental durability in oxidizing or harsh environments is limited and various surface modification techniques, including protective coatings are employed to extend their lifetimes and/or use temperatures. Due to presence of surface pits, scratches, pores, or other abnormal surface features (more commonly known as pitting or crevice corrosion), accelerated oxidation or corrosion is initiated in these areas which eventually degrades the entire surface. If the surfaces are prepared adequately, advanced alloys, that contain aluminum for example, will form a uniform protective alumina scale which limits further oxidation. However, if the thermally grown scale is not uniform or contain other oxides, besides that of aluminum, the protection is compromised and the alloys are subject to rapid degradation at elevated temperatures. In addition, surface grain boundary junctions are compositionally different compared to the bulk composition which may also cause the oxide scale in those regions to be different and perhaps less protective. Therefore, there is a need for a suitable surface modification method that will allow for the slow and steady formation of predominantly alumina-rich (more preferably pure alumina scale) scale for aluminum-containing alloys.
Similar arguments are valid for chromium-based steels and other chromium-based alloys which are used in applications for boilers, heat exchangers, recuperators, interconnect for solid oxide fuel cells, automotive catalytic converters, and others as apparent to those skilled in the art. In these applications, it is desired to form a protective chromia scale which requires a minimum level of chromium content in the alloy. Higher chromium content makes the alloy more expensive and also results in compromise of other important mechanical, thermal, and electrical properties of alloys. Thus, there is a need for a protective coating for chromium-based alloys and steels which will allow for the formation of a dense and uniform protective scale of chromium oxide, especially if it can be implemented for low chromium-containing alloys.
Metal or alloy honeycomb structures are used in many applications such as catalytic converters, radiators and heat exchangers, and exterior bodies of space vehicles for thermal protection. U.S. Pat. Nos. 5,411,711 and 5,146,743, among others, discuss the metal foil catalytic converters for automotive systems. Currently, most catalytic converters used in automotive exhaust systems in the U.S. use a ceramic honeycomb substrate loaded with a precious metal catalyst. The ceramic honeycomb is used because it can tolerate the hot exhaust environment without degradation. Alloy foil honeycombs offer advantages over ceramic honeycombs in weight and electrical conductivity. Most auto pollution occurs when the engine is cold, generally after the engine is started. At low temperatures the catalysts are not effective at reducing nitrogen and oxidizing residual hydrocarbons. To alleviate this problem and achieve overall reduced emissions, alloy foil catalytic converters can be resistively heated to ensure that the catalysts are kept at a temperature that allows them to function optimally. However, these thin foils are prone to oxidation and corrosion in the exhaust stream. Foils are particularly sensitive to oxidation because the original alloy is so thin, that the buildup of a thick oxide scale results in dimensional changes and changes in mechanical properties. For this reason, expensive oxidation resistant alloys are required. A thin oxidation resistant coating that will not substantially increase the thickness of the foil will be useful to reduce oxidation and corrosion, allowing the use of less expensive alloys, while still allowing the use of resistive heating to reduce emissions. Another such application is the potential use of alloy foils is for thermal protection systems for next-generation reusable launch vehicles for space travel. Present inventive material can be used as the oxidation protection coatings for these applications.
Currently, there are many ways to combat corrosion of aluminum and ferrous alloys. They include painting, electroplating, composite coverings, use of more corrosion resistant alloys, anodizing and chromating the surfaces of metal. Many of these processes are not environmentally friendly, cannot be maintained or repaired in the field, are expensive, require significant preparation of the substrate, and none offer the required long-term, low maintenance protection. Past coating efforts have primarily used relatively thick coatings (1-20 mils thick) to combat salt corrosion. Anodizing of aluminum and chromate conversion coating of aluminum and ferrous alloys are the most effective technologies, but both are environmentally unfriendly and require the use of toxic chemicals. Corrosion often occurs in areas of surface defects of the alloy substrate. Pits and inhomogeneities in the alloy composition cause accelerated corrosion. High strength aluminum alloys in particular are subject to pitting corrosion because of the influence of Cu-containing intermetallic particles. The inhomogeneous distribution of Cu in the alloy microstructure has been shown to be a major cause for low resistance to pitting or stress corrosion cracking. Heterogeneous microstructures are intentionally developed in commercial aluminum alloys to optimize mechanical properties. Unfortunately, such microstructures make aluminum alloys susceptible to localized corrosion during service and complicate aqueous surface finishing processes. The standard coating system uses a chromate conversion layer covered by organic paints. Short term corrosion protection of metals and alloys from corrosion due to moisture and other environmental factors is currently achieved using organic layers. Time-consuming and arduous, these organic coatings need to be removed before the processing of metals and alloys like heating or melting or for painting and other surface modifications.
Many metals, alloys and ceramics used in various applications require a smooth surface finish which is often accomplished by mechanical or chemical mechanical polishing means. In addition to passivation of coated surfaces, it is also desired to protect them from any environmental attack during processing or surface modification or during service. Typically, anodization of the surface with the formation of an alumina or chromia film is done to passivate the surfaces. However, the aforementioned procedures are expensive, labor intensive, and are environmentally unsafe releasing toxic substances and generating toxic waste.
Physical vapor deposition (PVD) grown amorphous silicon nitride film on metallic substrates are used for growth of single crystal magnesium oxide films using ion-beam assisted deposition (IBAD) whereby the growth is induced by e-beam evaporation, sputtering or other PVD method with another ion-beam to induce crystallographic alignment. Using this technique, biaxial texture of magnesium oxide is attained over thicknesses within 100 Angstroms as opposed to direct IBAD growth of yttria stabilized zirconia (YSZ) on highly polished polycrystalline metal or alloy substrates (hereafter referred to as metal substrates) which required growing much thicker films (over 1000 Angstroms) to attain similar quality biaxial texture. The IBAD magnesium oxide films served as good templates for further heteroepitaxial growth of functional oxide films such as ferroelectrics, superconductors, piezoelectric films, or other electronic films of the like. Thus, the IBAD MgO approach served as a much faster and economical way of producing biaxially textured or single crystal films on polycrystalline metal substrates with amorphous interlayers (also known as nucleation or adhesion layers).
It has been recently demonstrated that yttria served as a much better amorphous template layer (grown by PVD) than silicon nitride on highly polished metal/alloy substrates. Specifically, the yttria/IBAD MgO approach was used to demonstrate the architecture for growth of high quality High Temperature Superconductor (HTS) films suitable as HTS coated conductors. Specific disadvantages of this approach include: an expensive (vacuum deposition process) low deposition rate process is required for yttria amorphous layer formation, the use of thin yttria layer is not an adequate diffusion barrier against diffusion of oxygen and other metals to diffuse into the superconducting layer; thus, a separate diffusion barrier layer is still required (currently strontium ruthenate is being used as diffusion barrier), and prior to deposition of yttria, the substrate roughness needs to be tailored below 40 angstroms (preferably below 10 Angstroms) through mechanical or electrical polishing methods. Thus there is a need for an alternative material and associated thin film process (preferably non-vacuum, low-cost, and high deposition rate) to replace yttria and silicon nitride or other layers which is multifunctional and performs better and can be deposited at lower costs using a simple deposition process.
Low friction surfaces are required for many applications, including bearings, bearing races, and gears. Low friction surfaces can be imparted by depositing a low-friction material as a coating or reducing the overall surface roughness of the substrate. Although surface finish of metallic and ceramic parts can be improved through mechanical polishing, pits and defects contained on the surface cannot be effectively removed through any of the standard polishing techniques. Deposition of extremely thin amorphous films that exhibit low surface energy and provide hermetic coverage with adequate thermal and microstructural stability can be beneficial in maintaining a low friction surface whereby the defects on the metal surfaces are effectively sealed.
Biofouling of ship hulls is caused by microorganisms such as slime, algae and bacteria, and macroorganisms such as barnacles, mussels, clams and oysters which adhere to the hull of the ship. Fouling increases drag on the hull, decreasing ship speed and often significantly reducing fuel economy. One of the promising emerging technologies is the nontoxic "foul-release" coating. These coatings are based on the hypothesis that in surfaces with the weakest attraction for bio-organisms, fouling will be slow and likely to require the least amount of effort to release from the surface. Fouling organisms adhere to the surfaces by secreting proteinaceous adhesives. Materials with low surface energy will offer low adhesion strength, resulting in poor attachment and easy to remove fouling. The feasibility of this approach has been established by researchers using fluorinated polymers, epoxy based and silicone-based coatings. These coatings did foul, but fouling bio-mass can be easily removed by fast-flowing water. However, these polymer-based coatings have limited heat and UV light resistance. Therefore, an inorganic coating with smooth and low friction surface properties are highly desirable.
Microarrays are arrays of biomolecules such as oligonucleotides that are spatially arranged and stably attached to a surface of a solid support. Microarray technology is used for parallel analysis of genes in a large scale, and has emerged as the universal genetic analytical tool for use in a wide range of biomedical applications. Commercial production of DNA chips has been implemented by many companies while, in parallel, medical researchers report exciting advances across many disciplines within the field of medicine. These developments in microarray technology offer tremendous promise to solving long-standing problems in public health worldwide and also provide new avenues to combat the more recent threats of bioterrorism.
The starting point or the basic building block for producing biomolecular microarrays is a suitable solid template surface (solid support material) upon which biological molecules can be anchored or immobilized. Several patents have been issued on functionalizing silicate glass and other surfaces. Numerous other surface coatings have also been disclosed. Patents are also awarded for novel solid supports, e.g. aluminosilicate, for immobilizing nucleic acids. Characteristics of DNA microarrays are determined by the surface properties such as chemical homogeneity, interaction between surface and bio-molecules, surface roughness, density of surface functionality, spacing between surface functional moieties, amenability to DNA hybridization, and so forth. While the current methods employ the use of soda-lime glass substrates, they are prone to degradation over the long term and the surface chemistry is not tailored to allow for suitable organic attachments. An organic linker is used to attach the DNA or other biomolecule to the surface of the substrate. Polylysine is a coating material currently recommended and one of several used for glass slide preparation, as known in the art. However, polylysine-coated glass slides suffer from poor stability, extended curing cycles, and poor reliability such that new surface methodologies are critically needed to support the rapidly growing field of microarray technology. For example, polylysine-coated slides need to be stored for 14 days after coating for curing purposes and should be used within four months due to degradation from oxidation. Typically, in a batch of polylysine-coated slides, several are rejected because of non-uniformity or opacity. In addition, the hybridized microarrays cannot be stored over long time periods. Stability of polylysine coating under UV light is also a concern.
Many alternative coatings to replace polylysine are being investigated including aminosilanes, epoxy derivatives, aldehydes, and others. While aminosilanes or their derivatives offer superior stability, their low binding capacity has been a problem. Many of these limitations stem from the lack of desirable inorganic surface chemistry for bonding with organics. Organic groups functionalized on soda-lime glass surfaces are not stable under even slightly harsh conditions or chemical treatments and will degrade over time. Organic molecules interact only weakly with soda-lime-silica surfaces. Under humid or other conditions, sodium ions diffuse to the surface of the glass and interact with organic molecules resulting in degradation. Borosilicate or aluminosilicate glasses have also been proposed, but they do not offer the ideal surface chemistry for organic absorption.
Disinfecting and antimicrobial chemicals are commonly employed to eradicate microbial growth and improve hygiene. The adhesion of micro-organisms to surfaces is influenced by the bio-adhesive characteristics of the fouling organism and surface properties, such as its chemical composition and physical characteristics of the surfaces like surface roughness. Fungi, such as molds, yeasts and algae are visible in mass, but it can be advantageous to eliminate them earlier, when contamination and the consequential substrate deterioration has not yet become obvious. Highly active cleaning chemicals may be toxic and aggressive and, after repeated applications, degrade the surface and inactivate bioactive systems. Another major problem is the evolution of microbial strains which are resistant to disinfectants and antimicrobial agents that are being used now. The issue of hygiene is especially critical to contact surfaces present in food processing, supply and catering chains, health and medical establishments, animal husbandry, water and sewage operations as well as in heating, ventilation and air conditioning systems.
The performance factors of antimicrobial coatings include durability, retention of activity, and minimal degradation of surface characteristics and appearance. The coatings must also show resistance to heat, chemicals, solvents, staining, scratching, and moist environments. They should preferably be non-toxic, odorless, smooth, non-porous, easy or self clean, crack-free, avoid discoloration, have good color retention and be UV resistant. Several potential novel techniques are being developed to overcome these problems. These include albumin affinity surfaces, surface modification with blue dextran, silver ion incorporation in a porous matrix, photocatalytic titanium dioxide, silicone quartemary ammonium compounds and sacrificial coatings that are alkali soluble or strippable and recyclable films. A multi-layer film, fluoro/silicon containing resins, a dry paint film with additive coating or additives incorporated, the incorporation of cleaning agent activators, the design of surface and cleansing system in tandem, tuned ultraviolet, ultrasound and ozone could also be of value.
Among these antimicrobial techniques, there is a renewed interest in silver ion incorporation into coatings and substrates by researchers and companies. Several patents and publications have recently appeared on the use silver ion incorporated substrates like zeolites, polymers, ceramic sheets and polyelectrolyte films. Silver compounds have been exploited for their medicinal properties for centuries. It is an effective agent with low toxicity. Although silver salts are effective antimicrobial agents, their use likely results in unwanted adsorption of silver ions in epidermis cells and sweat glands. To reduce the likelihood of silver-ion adsorption into tissue, silver ions need to be incorporated into stable substrates.
The hydrophobic effect plays an important role in the defense against pathogens. In addition to the unfavorable surface energy on the hydrophobic surfaces, microorganisms are also deprived of the water necessary for germination and growth. Very few microorganisms are known to survive in the absence of water. Hence, hydrophobic property imparted on inventive material coated surfaces may be regarded as the additional defense against microbes. The combined effect of both bactericidal and hydrophobic properties of inventive material coating will act as two lines of defense against harmful microorganisms. A hydrophobic layer will prevent or reduce the adhesion of microbials and help in easy cleaning. In case of damage occurring to this hydrophobic layer during service the antimicrobial agent loaded second layer will act as second line of defense against microbes. Fiberglass insulation is used extensively in building construction. Fiberglass is an effective insulation, but is susceptible to moisture and can become a point for bacteria and mold to grow. Mold and bacteria growth in building materials causes indoor air pollution and can cause sickness in the inhabitants of the building. A water-repellent coating is desired to maintain dry conditions of the fiberglass insulation. If the fiberglass is dry, then biological growth can be prevented. Therefore, the combination of both hydrophobic and antibacterial property in one embodiment will greatly help in situation like this and others.


A buffered skin cream containing a linear polydimethylsiloxane polymer, a non-ionic emulsifier, aloe vera, mineral oil, sodium citrate, citric acid, a blend of propylene glycol, diazolidinyl urea, methyl paraben and propyl paraben, and water. The buffering capacity of the cream is provided through the incorporation of citric acid and sodium citrate in the composition. The buffering system results in the cream having a preferred pH in the range of about 4.5 to 6.0, and most preferably a pH of about 5.2 which neutralizes acidic and basic by-products of urine and fecal matter. The cream has a preferred viscosity in the range of 100,000-2,000,000 centipoise and a most preferred viscosity of about 250,000 to 1,000,000 centipoise. The cream is easily washed off with soap and water and is useful in the protection and treatment of diaper rash.

One of the most common skin problems with infants relates to diaper rash, also known as diaper dermatitis. One study conducted with infants less than two years of age concluded that almost two-thirds of all infants suffer from diaper rash of some degree. Approximately 10% of all infants can have their diaper rash classified as being moderate, with another 5% of the infants having diaper rash which could be classified as severe.
The primary contributors to the development of diaper rash have long been thought to be infant urine and feces. For example, infants under two months of age can urinate up to 20 times per day. Thereafter, infants can urinate up to 8 times a day. In addition, infant defecation typically occurs several times a day.
It had been theorized that the breakdown of the urine to yield ammonia primarily contributed to the formation of diaper rash by increasing the alkalinity of the skin. However, more recent studies have concluded that the primary contributor to the development of diaper rash is feces. As opposed to the alkaline pH associated with urine, feces typically exhibits an acidic pH due to bile. In fact, studies have shown that diaper rash is more prominent in the presence of feces than in the presence of urine, thereby providing a plausible explanation for the problems with diaper rash associated with infants who have diarrhea or frequent stools.
Diaper rash may predispose an infant to irritation and infection. The two most common types of infection are those associated with yeast and bacteria. The most common yeast infection is caused by Candida albicans. Meanwhile, the most common bacterial infection is caused by Staphylococcus aureus.
Treatment for diaper rash involves removing the source of irritation, reducing the immediate skin reaction, relieving the discomfort and preventing secondary infection and other complications. Frequent diaper changes and keeping the area as dry and clean as possible normally prove helpful. However, merely keeping the area clean and dry does not protect the irritated skin from the chemical irritation associated with the by-products of infant urine and feces.
In response to the problems associated with diaper rash, a number of products have been made available. The principle function of these products has been to act as a protectant, such that any affected area is protected against further direct contact with urine or feces. The most widely used protective ingredient has been zinc oxide. While many preparations contain zinc oxide in concentrations of approximately 10% by weight, some of the more popular brands have zinc oxide concentrations of approximately 40% by weight. Unless otherwise stated, the percentage concentrations of ingredients is understood to refer to percent by weight. Typically the zinc oxide is formulated with an oily substance such as petrolatum. Consequently, although such a diaper rash compound provides an effective protective layer, it is greasy, messy to apply, and not easily removed from the hands or the baby's bottom. Although removal can be affected with mineral oil, having to wash one's hands with mineral oil is inconvenient. Additionally, zinc oxide products have a distinctive smell due to their oil base, with this smell being offensive to some users of the product.
Most of the diaper rash products currently available are in the form of an ointment or a water-in-oil emulsion. The high viscosity associated with these products keeps the diaper rash product from being washed away by urine or feces. In many cases, the high viscosity is the result of the inclusion of zinc oxide. Thus, the typical anhydrous, hydrophobic ointment prevents urine or feces from coming into direct contact with the skin by their being repelled from the ointment surface. As such, the product acts as a barrier, inhibiting any penetration into the diaper rash product by any liquid.
An example of a diaper rash product is British Patent No. 1,357,731. That patent discloses a unique powder composition, which can be incorporated into a hydrophobic ointment. A buffer system is provided to buffer the composition at a pH of from 5.5 to 7.5, and preferably from 6 to 7. That patent discloses that a citric acid/sodium citrate buffering system does not have superior buffering capacity when compared with other buffering systems. This patent further discloses that "succinic acid/sodium succinate has 30% more buffering capacity than a citric acid/sodium citrate" buffer system. Thus this patent differs from the instant invention in that it claims use of a powder formulation having buffering capacity in the alkaline range of pH 5.5 to 7.5, and teaches away from the use of citric acid buffering system in view of the aforenoted comments related to the preferred use of a succinic acid buffer.
Another example of prior art is U.S. Pat. No. 4,556,560 issued on Dec. 3, 1985 to Buckingham. This patent discloses and claims the use of lipase inhibiting agents, such as the water soluble metallic salts including zinc chloride, in the treatment of diaper rash. This patent purports to treat diaper rash by inhibiting the deleterious effects of the enzyme lipase action on the skin, said inhibition being achieved by incorporating a inhibitory agent of said lipase action into a barrier like carrier, said carrier having the characteristics of being relatively hydrophobic in nature thereby forming an effective barrier to the skin against urine and feces. The instant invention does not disclose nor claim use of lipase inhibitory agents. The instant invention is further distinguished from the Buckingham patent in that the present invention specifically claims use of a buffering system to neutralize acidic conditions. Buckingham neither teaches nor claims any buffering system. Further the instant invention is set apart from the Buckingham patent in the nature of the carrier material employed in the formation of the so-called skin barrier. In the case of Buckingham, specifically disclosed are water-in-oil types of emulsions. In contrast to Buckingham, the instant invention specifically discloses and claims use of oil-in-water type emulsions in the formation of the barrier material.
Yet another example of the prior art is U.S. Pat. No. 4,996,238 issued on Feb. 26, 1991 to Matravers. This patent discloses and claims a skin protective composition exhibiting enhanced water repellency and skin conditioning effects and contains aliphatic waxes and hydrophobic silicones. Matravers' specifically discloses and claims the use of an admixture consisting of a fatty acid admixed with one or more hydrophobic silicones. This composition is devoid of water and further no buffering system is claimed. In contrast, the instant invention claims a water-based liquid product which contains a buffering system effective in acidic conditions.
Another example of the prior art is U.S. Pat. No. 4,904,524 issued on Feb. 27, 1990 to Yoh. This patent discloses and claims the encapsulation and microbead formation and use thereof of the active silicon agent (Dimethicone) in the preparation of cloth wipes in the treatment of diaper rash. This patent specifically discloses the need for an elevated concentration of encapsulated beads containing the active agent at the surface of the wipe. The stability, presence and delivery of the active agent within the wipe is directly linked to, and dependent on the process used to form and adhere the encapsulated beads to the paper wipe. In contrast, the instant invention claims a water-based liquid product which contains a buffering system effective in acidic conditions. Further, the instant invention does not require, teach nor claim encapsulation of Dimethicone, one of the ingredients in the claimed composition.
Other studies, such as one published in The Practitioner, Vol. 210:824-828 (1973), discuss a boric acid/borax buffer system for use as a diaper rash product. However, studies conducted during the 1970's brought about concerns of boron toxicity such that products containing boric acid had to be reformulated thereby eliminating boric acid as an ingredient.
Still another approach to products containing anhydrous, hydrophobic zinc oxide was the incorporation into such products of alkoxylated ether/esters such as polypropyleneglycol myristyl ether propionate. Although this approach rendered the diaper rash products less greasy, it did not completely resolve the problem associated with the zinc oxide content.
It is thus apparent that a need exists for an improved diaper rash product which provides a safe system, which is easy to apply as well as easy to remove by simple cleaning agents such as soap and water.