An improved animal trap 10 includes a housing 12 with a hinged lid 14 that may be locked in a closed position by way of a latch 18 and a pin 20. When the lid 14 is closed, a non-linear passageway is formed within the trap 10 with two rectangular cross-sectional passageways 22, 24 that are secured at a right angle to each other. External access to the non-linear passageway is made through an opening 26 in a wall of the housing 12. Each of the two passageways 22, 24 maintains a door 36, 38, respectively, that opens only inwardly with respect to the interior of the housing 12. The doors 36, 38 are substantially prevented from being opened from the inside of the housing 12 by way of the non-linear characteristic of the passageway and a corresponding pair of slotted pivot regions 32, 34, respectively. Animals are attracted to the trap 10 with bait that is confined within a protruding cylinder 42 having a mating cap 44. A plurality of holes 46, 48 are formed in the mating cap 44 and in the wall of the housing 12, respectively, so as to allow the aroma of the bait to emanate external to and within the housing 12.

1. Field of the Invention
The present invention relates to animal traps and, more particularly, to an improved animal trap that is simple and inexpensive to manufacture and that requires only minimal maintenance.
2. Description of the Prior Art
Traps for the capture and confinement of animals have been used for many years. Consequently, there have been many animal trap designs and/or refinements thereof produced over the years. For example, U.S. Pat. Nos. 4,887,381, 2,787,082, 1,911,919, 1,726,493, and 371,693 all disclose various animal trap designs. To familiarize the reader with some of the relevant prior art, a brief description of these prior art designs is now given.
In U.S. Pat. No. 4,887,381, Tieben discloses an animal trap that includes a housing with an entry port and a pair of animal-actuated, gravity-lowered doors that are successively mounted within the entry port such that each door opens inwardly only. The pair of successively mounted doors are coupled to each other to substantially prevent the innermost door from opening when the outermost door is in a closed position, thereby preventing an animal confined within the housing from escaping.
In U.S. Pat. No. 2,787,082, Paschen discloses a rat trap that includes a container with an open end where a one-way gate is located which is adapted to be pushed aside by an entering rodent and then returned to its original position so as to prevent egress of the rodent from the container. The gate includes a flexible wire mesh curtain and a several independently movable stiffening rods upon which the curtain lays. When the rodent enters the container the curtain forms to the contour of the rodent so as to prevent the escape of any previously captured rodents.
In U.S. Pat. No. 1,911,919, Molls discloses a trap that may be collapsed into a small compass for transportation and storage purposes. When the trap is deployed in its operable fashion it consists of a rectangular housing with at least one open end having a pair of animal-actuated, gravity-lowered doors that open inwardly only. One of the doors maintains a plurality of fines so as to prevent an animal from backing out of the housing.
In U.S. Pat. No. 1,726,493, Kelley discloses an animal trap that employs a depressible platform to control the movement of certain doors in a trap housing. When an animal is drawn onto the platform with bait, the platform effects the closure of a door in a manner such that the door may only be reopened when the animal advances further into the trap housing through a series of interacting doors which prevent the animal from escaping.
In U.S. Pat. No. 371,693, McKay discloses an animal trap that includes a rectangular housing with an open end. At the closed end of the housing bait is displayed on a lever that is connected to a plate by a rod. The plate holds a pair of inwardly opening doors in an open position until an animal enters the trap and moves the lever when trying to remove the bait. When the lever is moved, the plate releases the doors such that they are closed, thereby preventing the animal from escaping.
Although all of the above-mentioned prior art traps provide certain means of capturing animals by employing a series of inwardly opening doors within a housing, none provide for the capture of animals by employing a series of inwardly opening doors in a non-co-linear manner within a housing so as to greatly limit the egress of a captured animal. Furthermore, none of the above-mentioned prior art traps combine this non-co-linear door placement concept in an easily constructed and maintained trap housing along with doors that are substantially prevented from being opened by the captured animal through the use of a unique slotted pivot region concept. It would therefore be desirable to overcome the shortcomings of the above-mentioned prior art traps in these areas, while providing an inexpensive and easily constructed and maintained animal trap.


An amplifying circuit includes an amplifying stage for receiving input signals to generate output signals. A swing detect unit detects signal levels of the output signals. A clamp unit variably limits signal levels of the input signals based on the signal levels of the output signals detected by the swing detect unit to improve the speed of the amplifying circuit.

The present invention relates generally to electronic circuits, and in particular to amplifiers with input and output signals control.
Many electrical circuits have amplifiers for amplifying input signals to produce amplified output signals.
In most applications, the signal levels of the output signals depend on the signal levels of the input signals. And the speed of the amplifier depends on the switching of the output signals. Thus, the speed of the amplifier indirectly depends on the signal levels of the input signals.
In some applications, the input signals of the amplifier are limited to some fixed signal levels to improve the speed of the amplifier. However, in some cases, fixing the signal levels of the input signals may cause the output signals to differ from specified signal levels.
The various embodiments of the present invention provide methods and circuits for variably limiting signal levels of input signals of amplifiers based on signal levels of output signals of the amplifiers to improve the speed of the amplifying circuit.
In one aspect, a circuit includes an amplifying stage for receiving input signals to generate output signals. A swing detect unit detects signal levels of the output signals. A clamp unit variably limits signal levels of the input signals based on the detection by the swing detect unit.
In another aspect, a method of operating an amplifying circuit includes receiving input signals to generate output signals. The method further includes limiting signal levels of the input signals based on signal levels of the output signals.


In a method for monitoring strain variations of a strain responsive element of a micromachined sensor device while subjected to outside parameter conditions, at least two oscillation resonance modes of said element are activated and interrogated optically. Thereby correspondingly at least two resonance frequencies are obtained. From parameter/frequency characteristics of said device correspondingly at least two parameter values are derived.

1. Field of the Invention
The present invention relates to a micromachined sensor device for determination of parameters affecting said device. In particular, the present invention relates to a method for monitoring strain variations of a strain responsive element of a micromachined sensor device.
2. Description of Related Art
A method for using a micromachined device is taught in "A pressure responsive device having a resonantly vibrating element in an elastic tube", GB 2 223 582. The method monitors strain variations of a strain responsive element of a micromachined sensor device and comprises the steps of:
(a) irradiating said strain responsive element by a beam of light with at least a frequency swept modulated intensity for activating said element in order to oscillate in a corresponding oscillation resonance mode at its resonance frequency; PA1 (b) determining frequency characteristics of said device when subjected to predefined parameter conditions; PA1 (c) subjecting said element to outside parameter conditions; and PA1 (d) detecting the beam of light after being modified correspondingly by said activated element. PA1 (a) irradiating said element by a beam of light with at least frequency swept modulated intensity for activating said element such that at least two oscillation resonate modes are activated subsequently at their resonance frequencies; PA1 (b) determining frequency characteristics of said device when subjected to predefined parameter conditions by measuring the corresponding resonate frequencies of two said resonate modes at said predefined parameter conditions; PA1 (c) determining correspondingly two parameter values for said device by fitting the measured resonate frequencies upon the corresponding frequency characteristics; PA1 (d) subjecting said element to outside parameter conditions; and PA1 (e) detecting the beam of light after being modified correspondingly by said activated element. PA1 a micromachined sensor device having a strain responsive element, said strain responsive element responding to strain variations resulting from the varying outside parameter conditions; PA1 a light beam supply means functional for irradiating said element with light; PA1 a frequency oscillator means functional for generating a beam of light with frequency swept modulated intensity in order to activate said element in at least two oscillation resonance modes at their resonance frequencies, whereby the oscillator means supplies the beam supply means with an intensity modulated light beam; PA1 detecting means functional for detecting a modified beam of light, said modified beam being light modified by said activated element; PA1 measuring means functional for measuring the resonance frequencies from said modified beam; and PA1 processing means functional for processing resonance frequency values and deriving therefrom at least correspondingly two outside parameter values. PA1 These and other objects and advantages of the present invention will no doubt become apparent to those of skill in the art after having read the following detailed description of the preferred embodiments which are contained herein and illustrated by the various figures.
The method of GB 2 223 582 clearly addresses a micromachined pressure responsive device. For example, it is to be used as a "down well" pressure sensor in oil drilling and exploration. Only pressure response is known for this device. In particular, this method teaches that said micromachined sensors are made from single crystal silicon.
In an article by Andres et al., "Sensitivity and mode spectrum of a frequency-output silicon pressure sensor" Sensors and Actuators 15 (1988) pages 417-426, different vibrational modes of a so-called micromachined, butterfly silicon sensor integral with a thin diaphragm are shown. The modes are investigated by activating electrically and interrogating optically. In particular, for said modes, relationships between resonance frequency and pressure are determined. The modes M.sub.nm are classified in accordance with position and direction of node-axes.
In an article by Uttamchandani et al., "Optically excited resonant beam pressure sensor", Electronic Letters, 3rd December 1987, Vol. 23, No. 25, pages 1333-1334, resonance frequency/pressure and resonance frequency/temperature relationships for the fundamental mode of vibration of a beam-type micromachined silicon resonator are determined. No further interrelationships or dependencies are shown.
Moreover, from the above documents, the usual way of driving such resonators and detecting resonance frequencies by optical activation/interrogation techniques is known. In particular, two light sources, i.e., a pulsed mode source for activation and a continuous-wave source for interrogation are employed. Light transmitted by said sources is joined and guided in one fiber to the sensor, thus avoiding complex instrumental arrangements at the measuring position.
Whereas from the above advantageous use of one single fiber for activation and interrogation of the vibrational modes of such sensors, only a determination of the corresponding one parameter responsible for operation conditions, as mentioned, is realized.
However, in most cases, it is necessary to determine a set of parameters to qualify accurately working conditions in hostile environmental situations. For example, in the above mentioned downhole circumstances, exploration and production activities should be carried out at operation conditions as safe as possible. Especially pressure/temperature combinations should be monitored closely and reliably. Moreover, with respect to production activities, permanently installed sensor devices have to be used for long time periods.
To remedy the shortcomings, as addressed above, several solutions are proposed For example in the article by Vincent et al "An All-optical Single-fibre Micromachined Silicon Resonant Sensor: Towards a Commercial Device", Sensors and Actuators A, 25-27 (1991), pages 209-212, both the use of a set of sensors, called multiplexing sensors, with different resonance frequencies, and mechanical temperature compensation are disclosed.
A further compensation method is shown in "Sensors using Vibrating Elements" EP 371 592. Also, one fiber communication linkage is applied in this reference. The sensor device shown comprises a couple of strain responsive silicon beams, with one being affected by both pressure and temperature variations, the other having a free end only being subjected to temperature variations. Thus temperature corrections can be made.
However, the solutions and options as presented in the documents discussed, either seem to represent only a device development stage, or employ multicomponent sensor devices and related complex or incomplete parameter monitoring programs.

Micromachined sensor device using a beam of light with a frequency swept modulated intensity to activate at least two resonance modes of the sensor element


A compressor for an internal combustion engine is provided. The compressor includes a compressor shaft having compressor blades attached thereto, positioned in an intake air duct, and rotating about an axis during compressor operation and a magnetic bearing positioned upstream of the compressor blades in the intake air duct, including a ring positioned around the compressor shaft, stator electrics arranged in the ring, and at least two magnets arranged on the compressor shaft configured to exert a magnetic force on the stator electrics to form an air gap between the ring and the compressor shaft.

Turbochargers are used in internal combustion engines to increase combustion efficiency and/or engine power output. Therefore, boosting an engine via a turbocharger enables engine power and efficiency to be increased or enables the engine to be downsized while providing the power output of a larger naturally aspirated engine. Bearing are used in turbochargers to facilitate rotation of a shaft attached to turbine and compressor blades. For example, DE 102013203042 A1 shows a turbocharger for an internal combustion engine, with an oil-lubricated bearing, a supply line for the oil and a flow limiter for the oil. This type of oil bearing has power losses resulting from friction in the bearing. Heat is also an unwanted byproduct of the bearing friction. The power losses and heat generation both serve to decrease turbocharger performance.
To address at least some of the aforementioned problems, a compressor for an internal combustion engine is provided. The compressor includes a compressor shaft having compressor blades attached thereto, positioned in an intake air duct, and rotating about an axis during compressor operation and a magnetic bearing positioned upstream of the compressor blades in the intake air duct, including a ring positioned around the compressor shaft, stator electrics arranged in the ring, and at least two magnets arranged on the compressor shaft configured to exert a magnetic force on the stator electrics to form an air gap between the ring and the compressor shaft.
The above advantages and other advantages, and features of the present description will be readily apparent from the following Detailed Description when taken alone or in connection with the accompanying drawings.
It should be understood that the summary above is provided to introduce in simplified form a selection of concepts that are further described in the detailed description. It is not meant to identify key or essential features of the claimed subject matter, the scope of which is defined uniquely by the claims that follow the detailed description. Furthermore, the claimed subject matter is not limited to implementations that solve any disadvantages noted above or in any part of this disclosure.


Provided is a technology for further reducing a loss in a semiconductor device including a semiconductor substrate in which an IGBT region and a diode region are provided. This semiconductor device includes a semiconductor substrate in which at least one IGBT region and at least one diode region are provided. The IGBT region and the diode region are adjacent to each other in a predetermined direction in a plan view of the semiconductor substrate. In the plan view of the semiconductor substrate, a first boundary plane where the collector region and the cathode region are adjacent is shifted from a second boundary plane where the IGBT region and the diode region are adjacent on the front surface side of the semiconductor substrate either in a direction from the cathode region toward the collector region or in a direction from the collector region toward the cathode region.

Japanese Patent Application Publication No. 2008-053648 discloses a semiconductor device (a so-called RC-IGBT) including one semiconductor substrate in which a plurality of IGBT regions and a plurality of diode regions are provided. In each of the IGBT regions, a front surface structure of an IGBT is provided on a front surface side of the semiconductor substrate, and a collector region is provided on a back surface side of the semiconductor substrate. In each of the diode regions, a front surface structure of a diode is provided on the front surface side of the semiconductor substrate, and a cathode region is provided on the back surface side of the semiconductor substrate. The IGBT regions and the diode regions are alternately adjacent to each other in a predetermined direction. In a plan view of this semiconductor substrate, each boundary plane between the front surface structure of the IGBT and the front surface structure of the diode is in the same position as each boundary plane between the collector region and the cathode region.

Semiconductor device having adjacent IGBT and diode regions with a shifted boundary plane between a collector region and a cathode region


The present invention is an anti-vibration actuator (10) for moving an image stabilizing lens (16), having: a fixed portion (12); a movable portion (14) to which an image stabilizing lens is attached; a movable support member (18) for supporting this movable portion so that it is movable within a plane perpendicular to the optical axis of the image stabilizing lens; drive coils (20) attached to one of either the fixed portion or the movable portion; drive magnets (22) attached to the other of either the fixed portion or the movable portion so as to respectively face these drive coils; and at least one yoke (26) disposed on the side of the drive coils not facing the drive magnets; whereby magnetic force suppressing cutouts (26a) are provided on the yoke in a position overlapping the drive coils in order to suppress magnetic force received from the drive coils.

An anti-vibration actuator is set forth in Published Unexamined Patent Application 2011-22269 (Patent Citation 1). In this anti-vibration actuator, an image stabilizing lens is attached to a moving frame, and three drive magnets are attached to this moving frame. At the same time, three drive coils are attached to a fixed plate so as to face each of the drive magnets. Three steel balls are placed between the moving frame and the fixed plate, and by these three steel balls the moving frame is supported so as to be movable within a plane perpendicular to the optical axis. Furthermore, by sourcing current to the drive coil, a drive force is generated between the mutually facing drive magnets, and the moving frame can be moved in a predetermined direction. Note that the magnetism applied to the drive magnets is selected so that a predetermined drive force can be obtained between the drive magnets and the drive coils.
Furthermore, the pulling yokes are disposed on the rear side of the drive coils, i.e., the side of the drive coil facing the drive magnets. The moving frame is pulled to the fixed plate by the magnetic force acting between this pulling yoke and the drive magnet. Through the pulling of the moving frame to the fixed plate, the three steel balls placed between the moving frame and the fixed plate are sandwiched and held there-between.

Anti-vibration actuator and lens unit and camera furnished with same


A rotary press having a dispensing device for dispensing granular material on to a rotary table. The dispensing device has a frame located on the table and into which granular material is discharged from a discharge port connected to a vessel containing the granular material. The vessel and thereby the discharge port is arranged to be raised or lowered by a drive unit so as to vary the feed of the granular material from the discharge port into the frame. Guide fingers projecting internally from the frame guide the granular material into a die cavity as the table rotates.

When feeding granular material with poor flow characteristics into dies of a rotary press, difficulties are usually encountered in ensuring uniform filling of the dies. It may be difficult to maintain a uniform feed rate of granular material on to the table of the rotary press. Spillage and wastage of the granular material, or underfilling of the die may result. This can lead to variable filling of the die with variations in density of the compacted granular material.

c/o British Nuclear Fuels plc, Patents Section, Legal Department


A stylus is arranged on a coordinate measuring machine. A method for aligning a component in relation to the coordinate measuring machine includes positioning the stylus and the component in relation to one another according to a defined arrangement. The method includes acquiring at least one coordinate of the component. The method includes changing at least one of a position and an orientation of the component in relation to the coordinate measuring machine while maintaining the defined arrangement.

Coordinate measuring machines serve in a known way for measuring objects such as for example industrially produced workpieces. This may in particular involve determining coordinate values of locations of an object (known as scanning points) and combining them for example in the form of a 3D point cloud. On the basis of these measured values it is possible to deduce for example the dimensions, the three-dimensional shape and/or the maintaining of predetermined desired properties of the object (for example admissible deviations of shape).
In order to acquire coordinate values, the object may be scanned for example in a tactile or contactless (for example optical) manner. For this purpose, a tactile or contactless sensor device (for example a measuring sensor with a tactile stylus attached to it) is positioned and moved by the coordinate measuring machine in relation to the object. The positioning takes place by means of machine kinematics, which comprise multiple machine axes that are movable by means of a respective drive device. For acquiring the coordinate values, the axial positions (i.e. axial values) of the individual machine axes that are adopted can be acquired and/or evaluated.
Unless otherwise stated or evident, the invention is directed both to optical styli and tactile styli. Individual embodiments may however be restricted to the use of tactile styli.
It is also known that, for measuring objects (i.e. for acquiring their coordinates) by a coordinate measuring machine, additional components may be arranged in the working space of the coordinate measuring machine. These may be for example so-called counterholders, which are used for fixing long workpieces in particular, and are used in particular for measuring applications with a rotary table. Examples and background information on such counterholders can be found in the applicant's WO 2015/014398 A1.
To be more precise, for measuring long cylindrical workpieces, the latter are often placed on a rotary table and during the measurement are rotated about the axis of rotation of the rotary table, with the sensor device, for example a tactile sensor device, generally stationary. Typical workpieces are crankshafts, camshafts and gearwheels. These workpieces are best measured in an upright position, in order to eliminate the possibility of them bending under their own weight. For measuring, the workpieces are clamped onto a precision rotary table and rotated, in order to be able to acquire all of the test features. In this case, the workpieces may be clamped on the rotary table at the lower end, for example by means of a tip (cone tip) and a three-jaw chuck. Counterholders are used in the case of such measuring in order to fix the workpiece at the opposite upper end and keep it in position. An upper centering tip (cone tip) in the counterholder can be adjusted in height along a displacement axis, in order to be able to clamp workpieces of different lengths. In order to obtain great measuring accuracy, it is preferred that the centering tip of the counterholder is always located exactly over the centering tip of the rotary table, irrespective of the vertical position of the centering tip. Both centering tips lie for example on the Z axis of the coordinate system of the CMM. This alignment of the counterholder is carried out during the installation or fitting of the counterholder in the CMM.
As described, certain components must therefore be adjusted or positionally adjusted in relation to a coordinate measuring machine (CMM), which can generally be understood as meaning a relative alignment of the position and/or orientation of the component in relation to the coordinate measuring machine. To put it another way, in the course of an adjustment, the spatial position (or attitude) of an object in relation to the CMM may be changed, the position comprising the location and orientation of the object in space. This may generally be with reference to a coordinate system of the CMM, of which at least some axes may preferably run parallel to the axes of motion or machine axes of the CMM.
Previously, the component has preferably been measured by the CMM itself in order to determine a current position and/or orientation of the component in relation to the CMM (i.e. to determine this information for example in CMM coordinates). If an adequate match is not established, the position and/or orientation of the component is changed. This generally takes place manually and by estimating a required extent of the change of position and/or orientation. After this intervention, the component is measured once again and it is determined whether a desired (intended) position and/or (intended) orientation has been achieved. This therefore provides an iterative procedure with multiple manual interventions and a respective subsequent measurement. This requires experience and is time-consuming.
In the mentioned WO 2015/014398 A1, according to some exemplary embodiments additional sensors are provided, in order to obtain positional information for components of a counterholder. Using such additional sensors may however be undesired for reasons of expenditure or cost.

Aligning components in relation to a coordinate measuring machine

Carl Zeiss Industrielle Messtechnik GmbH


A magnet system for nuclear spin resonance spectroscopy, in particular for in-vivo spectroscopy and tomography on a limb or a shoulder of a human body (partial-body tomography) comprising a superconductive magnet coil arrangement having coil sets (2a, 3a; 2b, 3b) arranged at an axial spacing one from the other, for generating a static homogeneous magnetic field in an examination volume, and further a coil frame (6) carrying the coil sets and a cryostat intended for cooling the windings, is characterized by the fact that the windings are rigidly interconnected by the coil frame at low temperature and that there is provided a transverse room-temperature access (50) to the examination volume which extends over approximately 180.degree. in circumferential direction, related to the axis (4) of the magnet coil arrangement. This enables examinations to be carried out at ease.

The present invention relates to a magnet system for nuclear spin resonance spectroscopy, in particular for in-vivo spectroscopy and tomography on a limb or a shoulder of a human body (partial-body tomography) comprising a superconductive magnet coil arrangement having coil sets arranged at an axial spacing one from the other, for generating a static homogeneous magnetic field in an examination volume, and further a coil frame carrying the coil sets and a cryostat intended for cooling the windings.
Superconductive magnet systems for partial-body tomography that have been manufactured heretofore have a geometry similar to magnet systems used for whole-body tomography, except that their dimensions are smaller. The measuring possibilities of such systems are severely limited by the relatively big distance between the field center and the outer flange. Compare for example the Bruker Biospec Systems. If such a conventional magnet system, which displays a substantially circular cylindrical shape and a room-temperature bore, is to be used, for example, for examining a patient's leg, the patient must bend his other leg or spread it off so as if he were to do the splits--an attitude which is rather uncomfortable or even impossible. There have been certain attempts at reducing the length of the systems, or at generating adequately homogeneous field areas outside the magnet structure proper (e.g. Michael Marls et al. in "New Approach to Limb Exercise-Short Magnet" in Society of Magnetic Resonance in Medicine, Book of Abstracts, Vol. 2, Eighth Annual Meeting Aug. 12-18, 1989, page 539; U.S. Pat. No. 4,721,914; EP-A-0 160 350).


An integrated circuit device includes a CMOS image sensor and a MIM capacitor therein. The CMOS image sensor includes a transfer gate electrode on a semiconductor substrate and a P-N junction photodiode within the semiconductor substrate. The photodiode is located adjacent a first side of the transfer gate electrode. A floating diffusion region is also provided within the semiconductor substrate. This floating diffusion region is located adjacent a second side of the transfer gate electrode. An interlayer insulating layer is provided on the semiconductor substrate. The interlayer insulating layer extends opposite the transfer gate electrode, the P-N junction photodiode and the floating diffusion region. An optical shielding layer of a first material is provided on the interlayer insulating layer. The optical shielding layer has a single opening therein, which extends opposite the P-N junction photodiode. This single opening inhibits optical crosstalk between adjacent unit cells within the sensor. A metal-insulating-metal (MIM) capacitor is also provided on the interlayer insulating layer. The MIM capacitor has an electrode (e.g., lower electrode) formed of the first material.

CMOS image sensors can be manufactured at relatively low manufacturing costs as compared to Charge Couple Devices (CCDs), and thus are frequently used as the preferred type of solid-state image device. Because a unit pixel of a CMOS image sensor is formed with MOS transistors, a CMOS image sensor typically can be embodied within a smaller footprint area than that of a CCD. Furthermore, signal processing logic (e.g., circuits such as Correlated Double Sampling (CDS), Analog Digital Converter (ADC), and a ramp generator), can be formed simultaneously with the MOS transistors that constitute a unit pixel. Accordingly, the CMOS image sensor supports system-on-a-chip manufacturing.
A unit pixel of a CMOS image sensor includes a photodiode for sensing images, and transistors for transferring the signal sensed by the photodiode to a signal processing circuit. Such a unit pixel of the CMOS image sensor is shown in FIG. 1. Referring to FIG. 1, a transfer gate 15 is formed on a semiconductor substrate 10 where an active region is defined by an isolating layer 11. A photodiode 20 is formed in the active region on one side of the transfer gate 15, and a floating diffusion region 25 is formed in the active region on another side of the transfer gate 15. When the transfer gate 15 is formed, a gate of a reset transistor for resetting the floating diffusion region 25, a gate of a source follower transistor, and a gate of a select transistor may be simultaneously formed. The transfer gate 15 and the floating diffusion region 25 are respectively connected to a metal interconnect 30 and an external power source. The metal interconnect 30 includes multiple-layered metal interconnects 30a, 30b, and 30c. The metal interconnects 30a, 30b, and 30c are insulated from one another by respective interlayer insulating layers 35. The metal interconnect 30 are formed of a light blocking material and are disposed to surround a periphery of the photodiode 20. By allowing the metal interconnect 30 to surround the periphery of each photodiode 20, the pixels can be partitioned and somewhat shielded from each other.
However, as the resolution of the CMOS image sensor is increased, optical crosstalk may occur even though the metal interconnect 30 surrounds each photodiode 20 and acts as an optical shield.
More specifically, as shown in FIG. 1, the crosstalk is caused by obliquely incident light 50 that is incoming to an adjacent photodiode 20 through an interval among the metal interconnects 30a, 30b, and 30c disposed on the same plane, or due to mutual reflection among the upper and lower metal interconnects 30a, 30b, and 30c. Furthermore, when viewed from the same plane, the metal interconnects 30a, 30b, and 30c are spaced apart from the photodiode 20 by a predetermined distance. Therefore, the light is scattered and the quantity of the obliquely incident light is increased, so that the degree of crosstalk can be severe. Such crosstalk may mix data to cause color blurring, and brighten surrounding pixels when a bright image is scanned. In FIG. 1, a reference character {circle around (e)} denotes charge generated by the photodiode 20, in response to receipt of optical information. Accordingly, obliquely incident light cannot be thoroughly blocked by the metal interconnect 30 surrounding the photodiode 20.

CMOS image sensors for preventing optical crosstalk


A first adding circuit sums an input image signal of a target pixel and a value that is derived by multiplying respective display errors of three pixels, which are before the target pixel by one line, by weighting factors. A gradation candidate converter converts the gradation of the summed image signal to a plurality of available gradation candidates that are convertible when an error of the immediate left pixel is added. A delaying circuit delays the summed image signal. A second adding circuit sums the delayed image signal and a value that is derived by multiplying the error generated in the immediate left pixel by a weighting factor. A gradation selector selects a gradation closest to the gradation of the image signal to which the error is added from a plurality of gradation candidates, and outputs it as an image signal of the target pixel. A differencing circuit determines a display error of the target pixel.

When a display device where the number of displayable gradations is small performs multiple gradation display, smooth variation of brightness cannot be displayed. The brightness varies in steps, a contour-like pattern appears, and the image quality is reduced.
For example, a display device such as a plasma display panel (PDP) or a digital mirror device (DMD) displays multiple gradations by dividing one field to a plurality of subfields having different luminance weights and combining light emission and non-emission in each subfield. It is known that specific noise, known as a motion picture pseudo-outline, occurs in a motion picture part in this display device. For preventing the occurrence, the image display may be performed using not the gradations where the motion picture pseudo-outline is apt to occur but the gradations (hereinafter referred to as "available gradations") where the motion picture pseudo-outline hardly occurs. Here, an error diffusing method can be used for artificially displaying all gradations using available gradations. For example, Japanese Patent Unexamined Publication No. 2000-276100 discloses a method having a gradation converting means for converting a gradation to be displayed to an available gradation. In this method, when the gradation to be displayed is not available, this gradation is converted to an available gradation closest to itself, and the error occurring at this time is diffused to surrounding pixels and summed up. Thus, the gradation to be displayed is artificially displayed using only the available gradation.
It is advantageous from the aspect of the cost and mounting that a memory element such as a static random access memory (SRAM) is used as a gradation converting means. However, the access time of the SRAM is relatively slow, and an error cannot be diffused to the immediate right pixel when the access time exceeds one-data period. The SRAM cannot therefore be employed as the gradation converting means. Here, the one-data period is about 41 ns when one frame is 852×480 pixels, for example.
For addressing this problem, Japanese Patent Unexamined Publication No. 2000-276100 also discloses a method of using a lower bit of an image signal as a temporary error and diffusing the error to the immediate right pixel.
However, the error diffused to the immediate right pixel is not an accurate value in this method, so that the image quality is disadvantageously reduced compared with a case of correct error diffusion processing.
The present invention addresses the problems discussed above. The present invention provides an image signal processing device and an image signal processing method that can perform error diffusion processing to accurately diffuse an error to the immediate right pixel even when the access time of a means for converting the gradation exceeds one-data period.

Image signal processing device and image signal processing method

Matsushita Electric Industrial Co., Ltd.


A memory cell array has a unit formed from one memory cell and two select transistor sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one gate. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

The present invention relates to a nonvolatile semiconductor memory capable of changing memory cell data in units of bytes.
EEPROMs are conventionally known as nonvolatile semiconductor memories for changing memory cell data in units of bytes.
Reference 1 (W. Johnson et al., "A 16 Kb Electrically Erasable Nonvolatile Memory," ISSCC Digest of Technical Papers, PP. 152-153, February 1982) has proposed an EEPROM which changes memory cell data in units of bytes using FLOTOX (Floating Gate Tunnel Oxide) cells.
FIG. 65 is a plan view showing an example of a memory cell section of an EEPROM capable of byte erase. FIG. 66 is a sectional view taken along a line LXVI-LXVI in FIG. 65.
This EEPROM uses FLOTOX cells in the memory cell section. As a characteristic feature of a FLOTOX cell, an about 10-nm tunnel oxide film 22a is formed between an N+ drain 20a and a floating gate 21a, and charges are transferred between the N+ drain 20a and the floating gate 21a by applying an electric field to the tunnel oxide film 22a.
A current flowing to the tunnel oxide film 22a is an F-N (Fowler-Nordheim) tunneling current generated by the F-N tunneling phenomenon.
FIG. 67 is a view showing the energy band of a MOS capacitor section.
When an electric field is applied to the MOS capacitor (N+ drain—tunnel oxide film—floating gate), an F-N tunneling current flows to the tunnel oxide film (SiO2) on the basis of equation (1):I=S·α·E2exp(−β/E)  (1)                S: area, E: electric field        α=q3/8πhΦB=6.94×10−7 [A/V2]        β=−4(2 m)0.5 ΦB1.5/3hq=2.54×108 [V/cm]
As is apparent from equation (1), the electric field with which the F-N tunneling current starts flowing is about 10 MV/cm. This electric field theoretically corresponds to a case wherein a voltage of 10V is applied to a tunnel oxide film of 10 nm.
Referring to FIGS. 65 and 66, assume that when a voltage is applied between the N+ drain 20a and a control gate 23a, the capacitance ratio (coupling ratio) between the control gate 23a and the floating gate 21a is 0.5.
In this case, to apply a voltage of 10V to the tunnel oxide film 22a between the N+ drain 20a and the floating gate 21a, a voltage as high as 20V must be applied between the N+ drain 20a and the control gate 23a.
For example, in the erase mode, the N+ drain 20a is set at 0V and the control gate 23a at 20V to move electrons from the N+ drain 20a to the floating gate 21a. In the "1" program mode, the N+ drain 20a is set at 20V and the control gate 23a at 0V to move electrons from the floating gate 21a to the N+ drain 20a.
The disadvantage of the EEPROM using FLOTOX cells is that two elements, a memory cell and a select transistor, are required to store 1-bit data, as shown in FIGS. 65 and 66.
FIG. 68 shows another example of the memory cell section of the EEPROM capable of byte erase.
As characteristic features of this EEPROM, FLOTOX cells are used in the memory cell section, and a byte control transistor Tr is prepared in correspondence with memory cells of 8 bits (1 byte).
Table 1 shows bias conditions in each mode of this EEPROM.
TABLE 1Unselected ByteUnselected ByteConnected to theConnected toSame Word Linethe Same BitSelectedas That ofLine as That ofModeByteSelected ByteSelected ByteEraseWord LineHighHighLow("0" pro-ByteHighLowHighgramming)ControlBit LineLowLowLow"1" Pro-Word LineHighHighLowgrammingByteLowLowLowControlBit LineHigh orLowHigh or Low*2Low*1*1= Data Dependent*2= Don't Care
When such a memory cell section is used, various operation errors (disturbances) can be avoided. However, since 2+(⅛) transistors are required to store 1-bit data, the cell area increases to result in an increase in cost.
Flash EEPROMs aim at eliminating this problem. A conventional EEPROM is very convenient because data can be erased or programmed in units of 1-bit data.
However, when a computer hard disk requiring a large memory capacity is to be formed from an EEPROM, the EEPROM need not have a function of erasing or programming data in units of 1-bit data. In most hard disks, data is often erased or programmed in units of sectors (or in units of blocks).
It is more advantageous to attain a large memory capacity by cell area reduction and reduce the cost of products while omitting the function of changing data in units of 1-bit data. On the basis of such an idea, flash EEPROMs have been developed.
Details of a flash EEPROM are described in, e.g., reference 2 (F. Masuoka et al., "A new Flash EEPROM cell using triple polysilicon technology," IEDM Technical Digest, pp. 464-467 December 1984).
FIG. 69 shows the structure of a memory cell of a flash EEPROM.
The memory cell of the flash EEPROM has a control gate and floating gate, like a memory cell of a UV erase EPROM. In the flash EEPROM, data is programmed by injecting hot electrons to the floating gate, as in the UV erase EPROM. Data is erased by removing electrons from the floating gate using the F-N tunneling phenomenon, like a byte EEPROM.
In the flash EEPROM, the erase operation for the individual memory cells is the same as in the byte EEPROM. However, the operation for the entire memory cell array is completely different from that in the byte EEPROM. More specifically, the byte EEPROM erases data in units of bytes while the flash EEPROM erases all bit data at once. Employing such an operation method, the flash EEPROM realizes a memory cell section with one transistor per bit and achieves a large memory capacity.
In the flash EEPROM, data can be programmed in units of bits, like the UV erase EPROM. More specifically, the flash EEPROM is the same as the UV erase EPROM in that all bit data are erased at once, and data can be programmed in units of bits.
To realize a memory chip with a large memory capacity, a NAND flash EEPROM has been proposed on the basis of the above-described flash EEPROM.
Reference 3 (F. Masuoka et al., "New ultra high density EPROM and Flash EEPROM with NAND structured cell," IEDM Technical Digest, pp. 552-555 December 1987) discloses a NAND flash EEPROM.
The memory cell array portion of a NAND EEPROM has a NAND unit in which a plurality of (e.g., 16) memory cells are serially connected to form a NAND series with select transistors connected to its two ends, respectively, as shown in FIGS. 70 and 71.
In the NAND EEPROM, a bit line contact section and source line need be formed not for each memory cell but for one NAND unit. Two adjacent memory cells of the plurality of memory cells forming the NAND series share one diffusion layer. For this reason, the memory cell size per bit can be largely reduced, and a memory chip having a large memory capacity can be realized.
FIG. 72 shows a NOR flash EEPROM. In the NOR flash EEPROM, a 1-bit (one) memory cell is formed between a bit line and a source line.
In terms of cost, the above-described NAND flash EEPROM has a characteristic feature suitable to a large-capacity file memory: the cost per bit is low because the cell size can be reduced as compared to the NOR flash EEPROM. In terms of function, the NAND flash EEPROM has a higher data change rate and lower power consumption than those of the NOR flash EEPROM.
In terms of function, the NAND flash EEPROM is characterized in the scheme for changing data. More specifically, the NAND flash EEPROM achieves program and erase by charge transfer between the silicon substrate (channel) and the floating gate.
To transfer charges, the F-N tunneling phenomenon is used. A current necessary for programming is an F-N tunneling current flowing from the silicon substrate (channel) to the floating gate. Unlike the NOR flash EEPROM that uses hot electrons for programming, the NAND flash EEPROM has very small current consumption.
In a 64-Mbit NAND flash EEPROM, data of one page (512 bytes) can be programmed in 200 μs. This programming time is shorter than that for one block in the NOR flash EEPROM.
Table 2 shows comparison between the characteristic features of the NAND flash EEPROM and those of the NOR flash EEPROM.
TABLE 2NANDNORAdvantage{circle around (1)} Programming rate is{circle around (1)} Random accesshighrate is high{circle around (2)} Erase rate is high{circle around (2)} Data can beprogrammed{circle around (3)} Block size is smallin units of bytesand file management isat randomeasyDisadvantage{circle around (1)} Random access rate is{circle around (1)} Random accesslowrate is low{circle around (2)} Data cannot be{circle around (2)} Erase rate is lowprogrammed in units ofbytesApplicationReplacement for hard diskReplacement forPurposeand floppy disk, and dataconventional EPROM,recorder for portableand control memoryterminal (handy terminal,for control device,voice recording,BIOS of PC,electronic still camera)portable telephone,and Fax/modemand HDD
As shown in Table 2, the advantages and disadvantages of these memories are complementary to each other.
For the application purpose, the NAND flash EEPROM is used aiming at changing data in units of blocks. For example, in a digital camera having 300,000 pixels requires a memory capacity of about 0.5 Mbit for a photograph of one shot. When one block of the NAND flash EEPROM has a memory capacity of about 0.5 Mbit or more, photograph data of one shot can be stored in one block. In this case, data is erased in units of blocks. More specifically, photograph data of one shot is erased by erasing data of memory cells in one block.
On the other hand, the NOR flash EEPROM is capable of random access at a high speed of 100 ns and is widely used as a control program memory for, e.g., a portable telephone.
As described above, nonvolatile semiconductor memories have been developed as EEPROM (conventional type)→flash EEPROM→NAND flash EEPROM. The memory size, i.e., the cost per bit (bit cost) is reduced by sacrificing the function of changing data in units of bytes.
However, for, e.g., a nonvolatile memory embedded LSI which has received a great deal of attention recently, the function of changing data in units of bytes is required. For example, when an IC card used in a system for managing income and expenditure uses a flash EEPROM as an internal memory, data must be erased in units of blocks even when the data need a partial change. For this reason, the function of changing data in units of bytes is essential for such a system.
To cope with this situation, a byte EEPROM capable of changing data in units of bytes is required. However, the byte EEPROM has the large number of elements per bit, as described above, and therefore, is disadvantageous in increasing the memory capacity or reducing the bit cost.
Nonvolatile semiconductor memories of the current mainstream are flash EEPROMs (e.g., NOR type and NAND type). Hence, development of a byte EEPROM having the same process and scheme for changing data as those of a flash EEPROM makes it possible to produce EEPROMs meeting the requirements of the market at low cost.


Silica-coated nanoparticles functionalized with biologically active molecules such as antibodies and nucleotides are used to label cells, to detect and isolate nucleic acid molecules having specific nucleotide sequences, and to separate a mixture of different nucleic acid molecules.

Nanoparticles are very small particles typically ranging in size from as small as one nanometer to as large as several hundred nanometers in diameter. Their small size allows nanoparticles to be exploited to produce a variety of products including, for example, tools useful in many different biological and medical applications.

This patent is subject to a terminal disclaimer.

Functionalized nanoparticles and methods of use

University of Florida Research Foundation, Inc.


To keep down deterioration in picture quality caused by an AC driving method to enable image display with high quality to be achieved. In the invention, each of the pixels in a first frame just after the phase inversion for a predetermined starting time period is driven so that each of the pixels would be in a driving state of the polarity opposite to the polarity in the driving state in a last frame before the phase inversion, and then, each of the pixels is driven so that each of the pixels would be in a driving state of the polarity same as the polarity in the driving state in a last frame before the phase inversion when the driving circuit changes a driving state of each of the pixels from a positive polarity to a negative polarity or from the negative polarity to the positive polarity in every m (m≧1) frame and inverses a phase of the driving state of each of the pixels in every N (N≧m) frame wherein it is assumed that an image voltage having a potential higher than an opposite voltage applied to the opposite electrode is applied to the pixel electrode in a driving state of the positive polarity and that an image voltage having a potential lower than the opposite voltage applied to the opposite electrode is applied to the pixel electrode in a driving state of the negative polarity.

1. Field of the Invention
The present invention relates to a liquid crystal display device, particularly, a liquid crystal display device capable of keeping picture quality from deterioration caused by an AC driving method to achieve image display with high quality.
2. Description of the Related Art
A liquid crystal display module is used as a display device for a highly addressable color monitor of a computer and other information apparatuses or a TV set.
A liquid crystal display module basically includes a so-called liquid crystal display panel having a liquid crystal layer held between two (a pair of) substrates at least one of which is made of transparent glass. A voltage is selectively applied to various kinds of electrodes for forming a pixel, the electrodes formed on a substrate of the liquid crystal display panel, to switch a predetermined pixel on and off. A liquid crystal display module is superior in contrast performance and high-speed display performance.
FIG. 4 is a block diagram showing a schematic structure of a conventional liquid crystal display module.
The liquid crystal display module shown in FIG. 4 comprises a liquid crystal display panel 1, a gate driver part 2, a source driver part 3, a display controlling circuit 4 and a supply circuit 5.
The gate driver part 2 and the source driver part 3 are provided on the periphery of the liquid crystal display panel 1. The gate driver part 2 is formed from plural gate driver ICs provided on one side of the liquid crystal display panel 1. The source driver part 3 is formed from plural source driver ICs provided on another side of the liquid crystal display panel 1.
The display controlling circuit 4 performs timing adjustment for a display signal inputted from a display signal source (on a host side) such as a personal computer and a television receiving circuit so as to be suitable for display of the liquid crystal display panel 1 such as current alternation of data and converts the display signal into display data in a display form to be inputted to the gate driver part 2 and the source driver part 3 together with a synchronizing signal (a clock signal).
The gate driver part 2 and the source driver part 3 supply a scanning line with a scanning voltage on the basis of control of the display controlling circuit 4 and supply an image line with an image voltage to display an image. The supply circuit 5 generates various kinds of voltages necessary for the liquid crystal display device.
FIG. 5 illustrates an equivalent circuit of a pixel part of the liquid crystal display panel 1 shown in FIG. 4. FIG. 5 corresponds to geometrical arrangement of actual pixels. Plural sub pixels arranged in the shape of a matrix in a viewing display area (a pixel part) are formed from thin film transistors (TFTs), every one of which is used for one sub pixel.
In FIG. 5, DR, DG and DB denote image lines (also referred to as drain lines or source lines), G denotes a scanning line (also referred to as a gate line) and R, G and B denote pixel electrodes (ITO1) for respective colors (red, green and blue) Further, ITO2 denotes an opposite electrode (a common electrode), C1c denotes liquid crystal capacity equivalently indicating the liquid crystal layer and Cstg denotes holding capacity formed between a common signal line COM and a source electrode.
In the liquid crystal display panel 1 shown in FIG. 4, drain electrodes of thin film transistors (TFTs) of the respective pixels provided in a column direction are respectively connected to image lines (DR, DG and DB). The respective image lines (D) are connected to a source driver part 3 for supplying pixels provided in a column direction with an image voltage corresponding to display data.
Gate electrodes of thin film transistors (TFTs) of the respective pixels provided in a row direction are respectively connected to scanning lines (G). The respective scanning lines (G) are connected to a gate driver part 2 for supplying gates of the thin film transistors (TFT) with a scanning voltage (a positive or negative bias voltage) for one horizontal scanning period.
In displaying an image on the liquid crystal display panel 1, the gate driver part 2 selects the scanning lines (G0, G1, . . . Gj, Gj+1) from the upper part to the lower part (in the order of G0→G1) while the source driver part 3 supplies the image lines (DR, DG and DB) with an image voltage corresponding to the display data to apply the voltage to a pixel electrode (ITO1) during the selection period of a certain scanning line.
It is premised here that an operation is carried out in a so-called normally black-displaying mode in which the larger the image voltage supplied to the respective pixels is, the higher the luminance is.
A voltage supplied to the image line (D) is applied to the pixel electrode (ITO1) via a thin film transistor (TFT), and finally, holding capacity (Cstg) and liquid crystal capacity (Clc) are charged with electric charge and liquid crystal molecules are controlled to display an image.
The above-mentioned operation is described hereinafter with reference to a timing waveform.
FIG. 6 illustrates a voltage waveform outputted from the gate driver part 2 to the scanning line (G) and a voltage wavelength on an image line of an image voltage (VD) outputted from the source driver part 3 in a liquid crystal display module shown in FIG. 4.
A clock (CL1) shown in FIG. 6 is a clock for controlling output timing. The source driver part 3 outputs an image voltage (VD in FIG. 6) corresponding to the display data to the image lines (DR, DG and DB) from a point of falling time of the clock (CL1). FIG. 6 shows a voltage waveform of the image voltage (VD) in the case of displaying white.
The image voltage (VD) supplied to the image lines (DR, DG and DB) is AC-driven by switching the polarity between an image voltage with high potential with respect to a common voltage (VCOM) applied to the opposite electrode (ITO2) (referred to as an image voltage of the positive polarity (+), hereinafter) and an image voltage with low potential with respect to the common voltage (VCOM) (referred to as an image voltage of the negative polarity (−), hereinafter) for every horizontal scanning period (1H) in order to prevent the current voltage from being applied to liquid crystal capacity (Clc) in FIG. 5. FIG. 6 shows a case of using a dot inversion method, which is one of a common symmetry method, as an AC driving method.
On the other hand, a scanning voltage (VG) at a high level (referred to as an H level, hereinafter) is applied from the gate driver part 2 for one horizontal scanning period (1H) in the order of vertical scanning of the scanning lines (G0, G1, . . . Gj, Gj+1). Turning on, that is, selecting all the thin film transistors (TFTs) connected to the scanning line allows the image voltage (VD) outputted from the source driver part 3 to be applied to the liquid crystal capacity (Clc) and the holding capacity (Cstg).
Contrary to the above, in the case of the scanning voltage (VG) at a low level (referred to as an L level, hereinafter), all of the thin film transistors (TFTs) connected to the scanning lines (G0, G1, . . . Gj, Gj+1) are turned off, that is, not selected.
The waveform of the image voltage (VD) becomes dull in rising and falling processes of the image voltage (VD) in accordance with wiring resistance of the image lines (DR, DG and DB) and a time constant of the liquid crystal capacity (Clc), as shown in FIG. 6. Accordingly, the scanning voltage (VG) is changed from a voltage at the H level in a selection period to a voltage at the L level in a non-selection period after the image voltage (VD) is sufficiently saturated.
In the horizontal scanning period (N) in FIG. 6, for example, a slight difference in time (Tgd) is given from a point of time when the image voltage (VD) having the positive polarity is sufficiently saturated to a point of falling time of the clock (CL1) when the image voltage (VD) in a preceding horizontal scanning period (N+1) is outputted so as to change the scanning voltage (VG) from a voltage at the H level to a voltage at the L level.
Tgd is referred to as gate delay time in the following specification.
FIG. 7 is a simplified view simply showing pixel polarity and a pixel voltage level of a certain pixel in the case that white and black are alternately displayed for every vertical scanning period (referred to as a frame, hereinafter) in the conventional liquid crystal display module.
The pixel voltage shows a pattern that it is biased to a positive polarity side (a plus side) with respect to the common voltage (VCOM) and direct current is applied to the liquid crystal as an effective value when the image voltage changes in accordance with an AC cycle of the liquid crystal such as "white display" in negative polarity and "black display" in positive polarity, as shown in FIG. 7.
The pattern, especially, often occurs in the case of displaying a moving picture image and a direct current signal is always applied to the liquid crystal in the pattern. This causes deterioration in display quality as well as great deduction in life of the liquid crystal per se.
Further, display data in which white and black images alternately change in every frame often occurs in conversion from an interlaced (jump) scanning signal such as a television signal into progressive (sequential) scanning in liquid crystal driving. In the case of viewing a television image or a DVD image, which is displayed on the liquid crystal display module, for example, occurs a bias of a driving voltage of the liquid crystal. This causes deterioration in picture quality.
FIG. 8 shows pixel polarity in every frame in the case of inversing a phase of the pixel polarity in a certain fixed cycle (Period A and Period B) in the AC driving method shown in FIG. 7.
The pixel voltage in a first frame in Period A has a positive polarity (+) in accordance with a phase inversion signal shown in FIG. 8 while the voltage starts from the negative polarity (−) in Period B. Accordingly, the pixel polarity in the respective sections in Periods A and B is all opposite to each other such as positive (+) and negative (−) polarity.
Such an AC driving method is referred to as a phase inversion driving method in the specification hereinafter.
FIG. 9 is a simplified view simply showing pixel polarity and a pixel voltage level of a certain pixel in the case that white and black are alternately displayed in every frame in the phase inversion driving method.
As shown in FIG. 9, the pixel voltage biased to a negative polarity side (a minus side) with respect to the common voltage (VCOM) is to be biased to the positive polarity side (the plus side) after the inversion of the phase in accordance with the phase inversion driving method. As described above, carrying out an AC drive so that a bias of the pixel voltage would be on the positive polarity side or on the negative polarity side in a certain fixed cycle allows an effective direct current voltage applied to the liquid crystal to be reduced, as a result.
On the other hand, seeing the pixel polarity in the N-th frame and the pixel polarity in the first frame after a phase inversion switch, which are shown in FIG. 9, it is found that the positive (plus (+)) pixel polarity continues. In continuance of the same pixel polarity, there is sometimes a case of {(−)→(−)} or {(+)→(+)} in accordance with the timing of a switch in the phase inversion.
In the case of continuance of the pixel polarity, a condition for driving the liquid crystal (current alternation) is changed in appearance, so that flicker occurs on a display screen as a side effect.
The flicker occurs in the first frame with switch timing of the phase inversion signal shown in FIG. 8, that is, just after rising or falling of the phase inversion signal. As a result, the phase inversion drive has an effect of preventing the direct current voltage from being applied to the liquid crystal as well as a side effect of occurrence of flicker, which causes a problem that display quality is deteriorated, on the other hand.

Panasonic Liquid Crystal Display Co., Ltd.


In a method of forming micro traces, stamping techniques are employed to define a target pattern of the micro traces. The stamping is applied to electrically conductive material and may be limited to pressure, but a thermal stamping approach may be utilized. Following the stamping, a portion of the conductive material is removed, leaving the target pattern of conductive micro traces. In the pressure-application step, the pressure or the combination of pressure and temperature is sufficient to at least weaken the integrity of the bulk conductive material along the area of contact. Typically, this step causes shearing of the conductive material. Following the pressure-application step, excess conductive material is removed. In some embodiments of the invention, the thickness of the micro traces is not determined in a single step. The original thickness may be formed using a “seed” material. The subsequent material buildup may occur after the target pattern is established.

There are a number of applications which would benefit from the use of conductive micro traces on a substrate, where the width of a micro trace as measured parallel to the surface of the substrate is 25 μm or less. In some of these applications, only the electrical properties of the conductive micro traces are significant, but others require consideration of the optical properties. Optical properties are significant if the micro traces are to be formed on vehicle or refrigeration windows to provide controlled window defogging and deicing or are to be formed on a plasma display panel (PDP) to control the level of electromagnetic radiation.
U.S. Pat. No. 5,071,206 to Hood et al., which is assigned to the assignee of the present invention, describes a filter arrangement which may be used for vehicle, housing and office windows. The Hood et al. patent states that the arrangement of layers for an optical filter should provide color correction, heat reflectivity and infrared reflectivity. The complexity in achieving a desired optical property is increased if the optical filter is combined with conductive micro traces for deicing or defogging.
Factors which must be considered within the design of an optical filter for a PDP include the degree of neutrality of transmitted color, the level of reflected light, the color shift with changes in the incidence angle of a viewer, and the transmission levels of infrared and electromagnetic radiation. FIG. 1 is one possible arrangement of layers to provide a filter for a PDP, which includes a module or separate glass sheet 10. An Etalon filter 12 is formed on a polyethylene terephthalate (PET) substrate 14 that has been affixed to the glass sheet by a layer of adhesive 16. Because a plasma display generates infrared radiation and electromagnetic radiation that must be controlled in accordance with legislated regulations, the filter layers 12 are designed to reduce undesired radiation from the display. Etalon filters based on multiple filter layers are used to screen infrared wavelengths and electro-magnetic waves. Interference between adjacent filter layers can be tuned to cause resonant transmission in the visible region, while providing desirable screening. FIG. 1 also includes an antireflection (AR) layer stack 18 that was originally formed on a second PET substrate 20. Antireflection layer stacks are well known in the art. A second adhesive layer 22 secures the PET substrate 20 to the other elements of FIG. 1.
The formation of conductive micro traces on a substrate for application to a PDP may be used to further reduce electromagnetic radiation. The tradeoff is that the presence of the micro traces may adversely affect the overall optical properties. A second concern is cost. A process for forming conductive micro traces is preferably able to achieve a small width dimension in a cost-efficient manner.

Fabrication of conductive micro traces using a deform and selective removal process


A method and apparatus for forming a high conductance, high aspect ratio structure in a single low temperature copper chemical vapor deposition step. A trench for a winding of a coil is formed by forming a first length of the trench in the insulation layer. The first length of the trench forms a first portion of the winding of the coil in a confined area proximate a yoke region. A second length of trench is formed in the insulation layer extending away from the first length of the trench and the yoke region. The second length of trench includes parallel trenches for forming a second portion of the winding in a nonconfined area. A metal is deposited into the first length of the trench and the second length of the trench to form the first and second portions of the winding of the coil.

1. Field of the Invention
This invention relates in general to magnetic transducers, and more particularly to a method and apparatus for forming a high conductance, high aspect ratio structure in a single low temperature copper chemical vapor deposition step.
2. Description of Related Art
Magnetic recording is a key and invaluable segment of the information-processing industry. While the basic principles are one hundred years old for early tape devices, and over forty years old for magnetic hard disk drives, an influx of technical innovations continues to extend the storage capacity and performance of magnetic recording products. For hard disk drives, the areal density or density of written data bits on the magnetic medium has increased by a factor of more than two million since the first disk drive was applied to data storage. Since 1991, areal density has grown by the well-known 60% compound growth rate, and this is based on corresponding improvements in heads, media, drive electronics, and mechanics.
Magnetic recording heads have been considered the most significant factor in areal-density growth. The ability of these components to both write and subsequently read magnetically recorded data from the medium at data densities well into the Gbits/in2 range gives hard disk drives the power to remain the dominant storage device for many years to come.
A disk drive includes a rotating magnetic disk, write and read heads that are suspended by a suspension arm above the rotating disk and an actuator that swings the suspension arm to place the read and write heads over selected circular tracks on the rotating disk. The read and write heads are directly mounted on a slider that has an air bearing surface (ABS). The suspension arm biases the slider into contact with the surface of the disk, or a non-contact location, when the disk is not rotating. However, when the disk rotates, air is compressed by the rotating disk adjacent the ABS causing the slider to ride on an air bearing a slight distance from the surface of the rotating disk. The write and read heads are employed for writing magnetic impressions to and reading magnetic impressions from the rotating disk. The read and write heads are connected to processing circuitry that operates according to a computer program to implement the writing and reading functions.
Prior to 1991, heads were designed with a single inductive sensor performing both reading and writing functions. The decreasing signal amplitude resulting from areal densities exceeding 500 Mbits/in2 promoted the development of magnetoresistive and giant-magnetoresistive read sensors merged with an inductive head, which now performed a write function only. While write track widths can be wider than the corresponding read widths, i.e. "write wide and read narrow", inductive sensors must be redesigned with narrower gaps and pole geometries. At these higher data densities, pole edge effects become more significant. Coil widths and numbers of turns, all attained by advanced photolithographic techniques over large topographies, must be optimized to achieve adequate inductance focused within a very small writing area on the medium. Finally, it is a consequence of increased areal density that the media or internal data rate, i.e. the rate at which information is written and read within a disk drive, is increased.
A write head includes a coil layer embedded in insulation layers (insulation stack), the insulation stack being sandwiched between first and second pole piece layers. A write gap layer between the first and second pole piece layers forms a magnetic gap at an air bearing surface (ABS) of the write head. The pole piece layers are connected at a back gap. Current conducted to the coil layer induces a magnetic field across the magnetic gap between the pole pieces. This field fringes across the magnetic gap for the purpose of writing information in tracks on moving media, such as the circular tracks on the aforementioned rotating disk or a linearly moving magnetic tape in a tape drive.
The drive for micro mechanical structures to consume less area demands high aspect ratios (height over width). The simplest illustration of this is the coil. To allow the same current to be passed through the coil the cross sectional area of the turns must be held constant. As the line width of the coil turns becomes smaller the height must increase to maintain the cross sectional area. Fabricating high aspect ratio copper coils, as used in the magnetic inductive write head, is becoming increasingly more difficult to create using tradition electroplating on top of a copper containing a seed layer. Further, it is difficult to use electroplating to produce a conformal seed layer that minimizes discontinuities. These seed layers are not always continuous or plating tends to produce voids in high aspect ration structures.
These coils were traditionally produced via plating through a resist mask over a full film copper seed layer where the seed layer would be physically removed in a later process. However, removal of the seed has become difficult with sub-micron spacing between the coils. Thus, an alternate method is to use a damascene process to produce the coils. Nevertheless, this process is dependent on seed layer, plating without voids, and planarization of the wafer.
It can be seen that there is a need to introduce a structure or mechanism that maintains a void free deposition of a conductive material to increase conductance of a coil structure.

Method and apparatus for an enhanced coplanar conductance structure for inductive heads

International Business Machines Corporation


A raised access floor panel with a replaceable insert is provided. The panel includes a cross-braced framework constructed of four side rail members, and at least one cross-brace member. The cross-brace member is connected to the rail members so that the cross-brace member spans an area defined by the rail members. A plate frame is connected to an upper edge of the framework. The plate frame has a centroid void area which is surrounded by a peripheral portion. The peripheral portion includes an inner margin and an outer margin. The outer margin has right-angled corner forming portions. The inner margin is formed with a Z-section profile having a web portion which is capable of receiving the panel insert in fitment with the plate frame so that the insert and the peripheral portion are capable of providing a co-planar working surface.

1. Field of the Invention
The present invention relates to raised access floor panels. In particular it related to an interchangeable raised access floor panel having replaceable inserts for use in data centers.
2. Description of the Related Art
Raised floors are commonly used to create a space between a sub-floor and the normal working environment of a data center. The raised floor creates a separation barrier having an upper air plenum, which supports the server equipment, and a lower air plenum for receiving cooling air, which is recycled through the entire room of the data center. The lower air plenum is also used to contain the valves, pipes, fittings, gauges, fiber-optic cables, as well as the other design elements required for the efficient operation of the servers.
Raised floor panels are generally designed with a solid surface, a perforated surface, or with an air-grate. The air-grate panels are used to assist in circulating the cooling air through the plenums. The raised floor is supported on a matrix of pedestals, with one-each positioned under each corner of a floor panel. In a typical system, the support pedestal is a vertically disposed threaded rod. A first end of the support pedestal is threaded into a pedestal head, which supports a corner of the floor panel, and a second end of the pedestal support is threaded into a pedestal support base which is fastened to a floor of the building. In this manner, the support pedestal operates as a turnbuckle so that, by rotating the pedestal support, a vertical adjustment of the pedestal head, in relation to the subfloor, is achieved. The pedestal heads are connected in a matrix with horizontal stringers, and the stringers are used to support the edges of the floor panel plate.
In operation, data centers generate a great deal of revenue. Thus, it is often cost-prohibitive to shut down an entire facility in order to replace an existing floor system with an entirely new system of different manufacturers. When replacing an existing floor with a new floor one is often required to completely replace the entire existing floor structure because of the differently sized elements making up the component parts of the floor systems made by different manufacturers. An alternative has been to have the replacement panels custom made to fit with the existing systems. However, this alternative has all of the problems inherent with the use of custom manufactured products, including the inability to sustain an inventory of floor panels for immediate shipment and use. Thus, the production of interchangeable floor panels for use with new or existing systems of differing manufacturers have become increasingly desirable.
U.S. Pat. No. 7,644,550, to Meyer discloses an example of one such interchangeable panel which has gained wide acceptance in the industry. There, an articulating raised access floor panel, for interchangeable fit on new or existing pedestal support systems, is provided whereupon the open corner portions of the floor panel plate include an articulating corner bracket for expanding the foot-print of the panel. The bracket has an upper surface slidably connected to the lower plenum surface, so that the point of connection varies linearly along a diagonal vector established with respect to the lateral edges of the panel. This feature allows for installation of the interchangeable panel on different raised floor systems without experiencing issues related to the panels misalignment with those adjacent panels and stringers installed by other manufactures prior to installation. An additional feature disclosed with the Meyer discovery is the incorporation and use of a panel top set leveling screw, threaded through a collar portion of each bracket so that the panel is vertically adjustable for co-planar alignment with the adjacent panels and stringers. However, with the foregoing panels, one must replace the entire panel to change the working surface from a solid surface to and air-grate, for example, or remove the entire panel to view the conditions of the under-floor working environment where one is desires to monitor the meters, valves, or associated electrical components which are housed in the lower plenum in order to ensure the efficient operation of the systems.
Thus, while the foregoing interchangeable floor panels offer a great deal of utility, what is needed is raised floor access panel with a replaceable insert so that one need not remove, replace and reset the panel when simply to change the working surface configuration or view the lower plenum meters, valves and associated electrical components of the raised floor systems. Moreover, a need exists for an raised access floor panel with replaceable inserts, but which is also interchangeable for fitment with new or existing raised floor of differing manufacturers. The present invention satisfies these needs.

Raised access floor panel with replaceable insert


An encapsulated breaker for a fracturing fluid for use in fracturing subterranean formations comprising: a hydrocarbon base; neutralized alkyl phosphate esters completed with metallic cations, to form a gel, in said hydrocarbon base.

In order to increase the productivity of oil and gas wells, or to bring back into production wells that have essentially gone dry, it is common practice to conduct a procedure known as fracturing the well. In such a procedure, fluids known as fracturing fluids, are injected into the well at very high hydrostatic pressures. The fluids are typically viscous gels, and act under pressure to open pores and cracks in the formation, thereby to increase the overall permeability of the well. Typically, the fluids also are used to transport proppants, such as sand or ground walnut shells into the cracks and pores, thereby to ensure that the pores and cracks formed during fracturing remain open under the lower pressures that will exist after fracturing, when the well is producing.
The fluid that has been used to fracture the formation is removed by the introduction of viscosity lowering agents into same, which permit the fluid to be more easily pumped from the formation. These agents are known as breakers because they tend to break down the fracturing gel. Breakers can act on a gel in a number of ways, such as by the random oxidation of polymers to shorten the chain length thereof. In the present invention, a breaker is utilized to adjust the pH of a gel, to break same by hydrolysis.
The fracturing fluid of the present invention is a phosphate alkyl ester gel. It is known that a gel can be produced by mixing trivalent cations, such as aluminum, with a phosphate alkyl ester. However, gels obtained with known phosphate alkyl esters have not been commercially acceptable, because the viscosity developed with same has been insufficient or slow to develop, and usually required tank mixing.
Phosphate alkyl esters may be mono-esters, di-esters or trimesters. In the mono-ester, one primary mono-hydric alcohol, of C.sub.5 -C.sub.16 length is ester linked to a phosphate. A di-ester has two such alkyl alcohols linked to a phosphate. A tri-ester has three alkyl alcohols linked to it. The applicants have discovered that commercially valuable gels are feasible with a di-ester content above 50%, preferably above 65%, and a tri-ester content below 5%. The remainder may be mono-ester.
The applicants enhance gel development in two important ways. First, the phosphal alkyl esters are neutralized with primary amines. Secondly, the applicants utilize a surfactant to enhance gel development. An appropriate surfactant is ammonium alkyl (C.sub.6 -C.sub.20) sulfate.
In order to break the gel described herein the preferred breaker of the present invention is a pH adjusting breaker, such as calcium oxide and sodium carbonate. It is preferred that the breaker be encapsulated in a porous inert substance, such as nylon.
In a broad aspect, then, the present invention relates to an encapsulated breaker for a fracturing fluid for use in fracturing subterranean formations comprising: a hydrocarbon base; and neutralized alkyl phosphate esters complexed with metallic cations, to form a gel, in said hydrocarbon base.


A device, system and method may enable the obtaining of in vivo images from within body lumens or cavities, such as images of the gastrointestinal (GI) tract, where the data such as mosaic image data may be transmitted or otherwise sent to a receiving system in a compressed format.

Devices, systems, and methods for performing in-vivo imaging, for example, of passages or cavities within a body, and for gathering information other than or in addition to image information (e.g. temperature information, pressure information, etc.), are known in the art. Such devices may include, inter alia, various endoscopic imaging systems and various autonomous imaging devices for performing imaging in various internal body cavities.
An in-vivo imaging device may, for example, obtain images from inside a body cavity or lumen, such as the gastrointestinal (GI) tract. Such an imaging device may include, for example, an illumination unit, such as a plurality of light emitting diodes (LEDs) or-other suitable light sources, an imager, and an optical system, which may focus images onto the imager. A transmitter and antenna may be included for transmitting the image and/or other data signals. An external receiver/recorder, for example, worn by the patient, may record and store images and other data Images and other data may be displayed and/or analyzed on a computer or workstation after downloading the data recorded. The number and size of image data per frame and/or other data to be transmitted may be limited by the time period, power, and/or bandwidth that may be required to transmit each image frame and/or other data. Transmission may be wireless, for example, by RF communication or via wire.
Methods for compressing image or video data may be known, for example, compression algorithms such as JPEG and MPEG may be used to compress image and video data.

In-vivo imaging device providing data compression


A packaged semiconductor device and a method for burn-in and testing are disclosed. The package comprises a carrier having a pattern of contact pads for electrical connection, and also a pattern of testing pads for electrical characterization such that their location, size and composition allows a conversion to contact pads after the device has been electrically characterized following burn-in. Furthermore, an adapter and a method for burn-in and testing are disclosed for use in testing a variety of different semiconductor devices. The adapter comprises a carrier having a pattern of testing pads bordering the carrier outline, and routing strips which are structured such that the carrier is adaptable to the package of the device being tested.

The trend in semiconductor technology to double the functional complexity of its products every 18 months (Moore's "law"), which is still valid today after having dominated the industry for the last three decades, has several implicit consequences. First, the cost per functional unit should drop with each generation of complexity so that the cost of the product with its doubled functionality would increase only slightly. Second, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink. Third, the increased functional complexity should be paralleled by an equivalent increase in reliability of the product. And fourth, but not least, the best financial profit rewards were held out for the ones who were ahead in the marketplace in reaching the complexity goal together with offering the most flexible products for application.
For semiconductor memory devices, historically the time span of at least three years has been needed between two generations of memory families. The new generation offers a four times larger memory capacity compared to the preceding generation. Again, shrinking circuit feature sizes and more complex memory hierarchies have been the prerequisite of the new product generation--at high development cost for chip design and fabrication processes, coupled with very expensive investment in costly new manufacturing equipment.
A number of technical advances have recently been achieved in an effort to obtain an advantage in this competitive marketplace. Within the semiconductor memory product families, one of the most promising concepts for shrinking the package outline and thus consuming less area when the device is mounted onto the circuit board, has been the so-called "board-on-chip" design replacing the traditional metallic leadframe. Patent application Ser. No. 9702348-5 entitled "Board on Chip--Ball Grid Array Chip Size Package" has been filed by Texas Instruments in Singapore on Jul. 02, 1997. This patent application for memory products successfully approaches the problem of reducing the area requirement by replacing the traditional leaded package design with a solder ball concept. In addition, it offers a reduction in the height requirement by replacing the leadframe-on-chip assembly with a thinner and more flexible board-on-chip design. Using the new concept, a high-density integrated circuit package has been described in patent application Ser. No. 9703963-0 entitled "High Density 3-Dimensional Stacked Ball Grid Array Integrated Circuit Module", filed by Texas Instruments in Singapore on Nov. 6, 1997. A new modification using thin board-on-chip devices entitled "Thin Board-on-Chip Integrated Circuit Unit" has been submitted by Texas Instruments in Singapore, also in 1997.
It is frustrating, though, that in spite of all this progress so much time and money has to be spent continuously for testing and burning-in each new package and each new device. Required are design and acquisition of dedicated burn-in and test sockets for each different input/output count and each different package configuration; dedicated sockets, boards, trays, tubes and handlers; lack of standardization of equipment and procedures for testing and burn-in; and limited comparison of accumulated data. Due to ever modified package outlines, testing and burn-in remain dedicated fabrication steps with no interchangeablity. Consequently, a need has arisen for package designs and methods of device fabrication that provide simple, low-cost designs for a universal fanout package concept with a configuration suitable for an entire device family. Preferably, these improvements should be accomplished using the installed equipment base so that no investment in new burn-in and testing facilities is needed.

Semiconductor device testing and burn-in methodology


The body (12) of a vehicle (10) is mounted on forward and rearward wheels (16, 18) by an elongated tie structure (20) extending along the lower elevations of the vehicle. The tie structure (20) is connected to the body (12) to pivot about longitudinal and transverse axes (21L, 21T) that intersect at a pivot point (22) located at an elevation above the center of gravity of the vehicle. The tie structure (20) is connected to the wheels (16, 18) by pivot arm assemblies (26). Resilient first load control devices (136), forming part of the pivot arm assemblies (26), are interconnected between the tie structure and the vehicle wheels, and second load control devices (28) are connected between the body and the wheels, with the capacities of the first and second load-carrying devices selected to cause the pitch and roll stiffness of the tie structure to be greater than the pitch and roll stiffness of the body.

When negotiating a curve with a typical automotive-type vehicle, the resulting centrifugal forces roll the vehicle body and associated chassis (hereinafter jointly referred to as "body") about its roll center relative to the underlying suspension system, and also displace the body and suspension system laterally outwardly tending to cause the vehicle to pivot about its outer wheels. This latter tendency is commonly known in the motor vehicle art as the "jacking effect". During braking and acceleration, the resulting longitudinal forces acting on a typical automotive-type vehicle tend to pitch the body about its pitch center relative to the underlying suspension system and also tend to displace the body and suspension system forwardly during braking and rearwardly during acceleration to cause the vehicle to pivot about its front or rear wheels, respectively.
The locations of the roll center and pitch center are functions of the construction of the vehicle body and the configuration of the vehicle suspension system. In a conventional vehicle, the center of gravity of the vehicle is located above the roll center and pitch center. Since the centrifugal forces caused by cornering and the longitudinal forces caused by accelerating and braking act through the center of gravity of the vehicle, the magnitude of the couple tending to cause the body to roll about its roll center is a function of the magnitude of the centrifugal force and the vertical distance separating the center of gravity from the roll center and the magnitude of the couple tending to cause the body to pitch about its pitch center is a function of the magnitude of the longitudinal force and the vertical distance separating the center of gravity from the pitch center. These vertical distances are commonly known as the "roll couple" and "pitch couple", respectively.
In a typical vehicle, as the body rolls outwardly about its roll center, it tends to compress the outer suspension springs (relative to the radial center of the curve about which the vehicle is traveling) thus increasing the weight on the outer wheels while simultaneously unloading the inward suspension springs thereby reducing the weight on the inside wheels. As a result, the cornering traction of the vehicle is reduced. Also, as the body pitches forwardly about its pitch center during braking, it tends to compress the forward springs thus increasing the weight on the forward wheels while simultaneously unloading the rearward springs thereby reducing the weight on the rearward wheels. This resulting imbalance in the weight being carried by the forward and rearward wheels decreases the maximum braking capacity of the vehicle. The foregoing loading changes on the vehicle wheels caused by cornering and braking will occur simultaneously when the vehicle's brakes are applied while cornering, thereby potentially causing even greater imbalance of the weights on the vehicle wheels than caused by cornering alone or braking alone. This imbalance may result in the loss of substantially all of the traction of one or more wheels.
The lateral force tending to cause a vehicle to pivot about its outer wheels, i.e., jacking effect, acts through the portion of the vehicle known as the roll reaction center. The longitudinal forces tending to cause a vehicle to pitch about its forward or rearward wheels acts through the pitch reaction center. In a conventional vehicle, the roll reaction center coincides with the roll center and the pitch reaction center coincides with the pitch center. As a result, the magnitude of the jacking effect is a function of the magnitude of the centrifugal force and the elevation of the roll reaction center above the ground, and the magnitude of the pitching effect is a function of the magnitude of the longitudinal braking/acceleration force and the elevation of the pitch reaction center above the ground. With respect to the effect of cornering forces on a vehicle, the height of the roll reaction center above the ground is commonly known as the jacking couple, and with respect to the effect of braking and acceleration forces on the vehicle, the height of the pitch reaction center above the ground is commonly known as the pitching couple.
In conventional vehicles, attempts have been made to design the suspension system to minimize the height of the roll reaction center, thereby to reduce the jacking effect. Placement of the roll reaction center at a low elevation, however, results in the center of gravity of the body being located at a substantial distance above the roll center, thereby increasing the magnitude of the roll couple. The increase in the roll couple results in decreased stability of the vehicle, especially since in typical suspension systems the body roll and jacking effect are cumulative, both reducing the cornering ability of the vehicle.