A method of canceling echoes in a telecommunications system wherein an exchange of information takes place between a local subscriber and a subscriber at the remote end of a transmission link and at least one subscriber is assigned an echo canceller, the parameters of which are set as a function of an echo delay time (i). The signs of the signal x(t) transmitted by a subscriber and the signal y(t) received by the subscriber can be determined at equidistant time intervals (Ti) so that sign sequences arise which are stored and compared with one another, and in the event of a direct correspondence or a correspondence as a result of an inversion of the sign sequences of the received signal y(t) and of the transmitted signal x(t) the received signal y(t) is detected as an echo and the echo delay time (i) is calculated.

The invention relates to a method of cancelling echoes in a telecommunications system wherein an exchange of information takes place between a local subscriber and a subscriber at the remote end of a transmission link and at least one subscriber is assigned an echo canceller, the parameters of which are set i.a. as a function of an echo delay time, and to an echo canceller for the execution of the method.
Disturbing echoes, so-called line echoes, occur due to undesired electric coupling between a receiving path and a transmitting path. In modern communications technology such couplings or echoes, caused by data reductions, junctions, frequent 2-wire/4-wire transitions etc., constitute an increasing problem. Therefore echo-cancelling measures, such as NLMS algorithms or compander algorithms, are used to improve the quality of speech- or data connections. In the case of these algorithms it is often useful to have knowledge of the delay time of the echo signals. To determine the echo delay time it must be ascertained when the transmitted signal arrives at the echo reception location. As telecommunications systems are generally operated bidirectionally, the echo signal can be superimposed with a signal fed-in at the remote end of the transmission link as useful signal. This occurs whenever speech takes place simultaneously at both ends of the transmission link. This is the so-called double talk situation. It is a general problem in all possible transmission situations to clearly identify an echo and distinguish it from useful signals in the double talk situation.
DE-A-42 29 0110 has disclosed a method of detecting an echo in which the transmitted signal is recorded and compared with the signal incoming at the reception location. For this purpose a correlation analysis is performed, in which the degree of correlation indicates the probability as to whether an echo or a mixed signal, produced by the double talk, is present. This decision is made by a threshold value. The greater the selected threshold value, the less often are existing echoes detected. False decisions therefore frequently occur. If on the other hand the threshold value is selected too low, the danger exists that useful signals will be filtered out in double talk. The computation outlay for the correlation analysis is very high while the echo detection reliability is unsatisfactory.
Additionally, DE-A-19 85 0272 has disclosed a method of detecting an echo wherein local extreme values are determined from the transmitted signal and the received signal. As the time difference between two local extreme values is dependent upon the curve formation of the transmitted signal, in the case of an echo the same time difference between consecutive extreme values occurs for the transmitted signal and the received signal. These extreme values are marked with a pulse, thereby giving rise to pulse trains which represent a characteristic of a speech sequence. A measure of the similarity is derived from the pulse train of the local extreme values of the transmitted signal and of the received signal. This method requires a high signal processing outlay, using similarity criteria to make a decision about the echo characteristic of a signal. The decision reliability is consequently relatively poor.
The object of the invention is to improve the reliability of the echo detection whilst endeavouring to achieve as low as possible a storage and computation outlay.
The signal received by the subscriber are determined at equidistant time intervals, so that sign sequences arise which are stored and compared with one another, and that in the event of a direct correspondence or a correspondence as a result of inversion of the sign sequences of the received signal and of the transmitted signal, the received signal is detected as an echo and the echo transmission time is calculated. In this way it is possible to make a very reliable decision as to whether an echo signal or a mixed signal is present without taking into account similarity criteria. The decision reliability is the better, the smaller the selected equidistant time intervals for the sign determination. For example a signal curve of the transmitted signal characterised by the following blocks can occur: 23 times positive sign, 40 times negative sign, 51 times positive sign, 24 times negative sign. Only when precisely this block classification is determined either exactly or in inverted form also for the received signal, is an echo signal present.
To determine the echo delay time from a determined correspondence of this type, it is provided that the time offset of the sign sequences and of the corresponding signal blocks is determined.
In accordance with an advantageous further development, the sign sequences of the transmitted signals are determined during a fixed time interval. This time interval is selected such that a sufficient number of signs for the unequivocal characterisation of the signal curve of the transmitted signal can occur within it. For example on average the time interval can comprise five sign blocks, the blocks being redetectably characterised by a sufficient number of sign determinations. In the event of a restriction to approximately five sign blocks, during this time interval at least one hundred sign determinations are to take place, i.e. the time interval is to amount to at least one hundred times the equidistant time interval between two sign determinations. The sign sequences of the received signals are determined during the maximum echo delay time. In this way, in spite of a reduced outlay, a reliable identification of echo signals occurs. A calculation of the echo delay time as a precondition of the echo cancellation naturally only takes place if the received signal exceeds a fixed threshold above the reception noise. After a delay time measurement, no further delay time measurement is to occur until the transmitted signal breaks off. The determination of the next sign sequence during the fixed time interval is not initiated until the commencement of the next speech-specific transmitted signal.
An echo canceller for the execution of the method. Means are provided for determining the sign sequences, as well as comparison means and a counter for determining the time offset between sign sequences which correspond directly or as a result of inversion, where the time offset forms a measure of the echo delay time.

Method of cancelling echoes in a telecommunications system and an echo canceller for the execution of the method


An effluent gas scrubbing system is disclosed having an improved scrubber inlet system including a transition tube having a fluted lower portion for directing particulate carrying gas into the mist saturated scrubbing chamber of a gas scrubber, a fluid reservoir affixed to the upper portion of the transition tube and having a plurality of fluid supply jets tangentially positioned along internal cavity forming walls of the reservoir so as to cause the fluid within the internal cavity of the reservoir to swirl, and a readily interchangeable gas inlet pipe which is co-axially positioned within the cavity and with respect to the transition tube so as to create a transition gap between the transition tube and the inlet pipe through which a swirling flow of fluid may exit the cavity and enter the upper portion of the transition tube so as to thoroughly coat the entire length of the transition tube with fluid, and so as to provide a smooth and abrupt transition between the dry-walled inlet pipe and the wet-walled transition tube.

1. Field of the Invention
The present invention relates generally to effluent scrubbers and more particularly to an improved scrubber inlet system for use with effluent scrubbers.
2. Brief Description of the Prior Art
In the semiconductor industry, exhaust gas scrubbers are used to cleanse the unreacted silicon gases that are exhausted from silicon deposition systems. These gas scrubbers typically operate by passing the exhausted gas through an environment permeated with a misted or atomized fluid, such as water, which reacts with the unreacted particles in the gas to form solid deposits which rain from the gas into a collection reservoir.
Cross-sectional views of prior art gas scrubbers having elements similar to some of the gas scrubber models manufactured by Shannon, Inc. and Airprotek, Inc. are illustrated in FIGS. 1a and 1b, respectively. Both of these scrubbers cleanse the silicon gas exhausted from the deposition system by reacting it with water from one or more scrubbing jets, so as to form solid Silicon Dioxide (SiO2).
The problem with these types of silicon gas scrubbers is that an SiO2 coating is constantly being formed within the inlet pipe and unwashed walls of the scrubbing chamber. For example, in both FIGS. 1a and 1b, gas 1 passes through the inlet pipe 2 into the open area or transition region 3, where some of the gas mixes with the fluid mist 4. Silicon gas 1, which has mixed with fluid mist 4, is then carried by gas turbulence 7 and diffusion back-up and deposited on the insufficiently washed inner walls of the scrubbing chamber, so as to form a build-up 5. This SiO2 build-up results in a significant problem which, until the present invention, remained unsolved.
As is shown in FIGS. 1a and 1b, the build-up of SiO2 results in the development of restrictions in the inlet flow pipe, as well as other places. These restrictions develop because the transition region between the inlet pipe and the scrubbing spray are dampened sufficiently so as to cause the silicon gas to react, but are insufficiently washed so as to prevent build-up. The transition region and inlet pipe are dampened for two reasons: first, because water mist from the scrubbing jet 6 is diffused back into the transition region 3 and entry pipe 2; and second, because an abrupt volume change occurs as gas exits the narrow inlet pipe and enters the large scrubbing chamber, thereby creating heavy gas turbulence 7 and causing water mist and precipitated solids to be swept back into the inlet pipe and onto the walls of the transition region.
The resulting restrictions cause back-pressure to be created in the reaction chamber of the silicon deposition system from which the gas is exhausted. Excessive back-pressure will result in loss of process control and require the deposition system to be shut down until the restriction can be removed. Silicon gas scrubbers presently require restriction removal between every 1 to 5 days, depending on specific conditions.
Restriction removal is performed by shutting the deposition system down, flushing the system and the scrubber out with nitrogen gas to make the surrounding environment safe to humans, unscrewing an access union 8 (FIG. 1b), mechanically plunging out the build-up, rinsing the inlet port with water, and then re-tightening the access union. In all, the average downtime for restriction removal is about 35 minutes: 10 minutes for a nitrogen gas pre-purge, 15 minutes devoted to the actual cleaning process, and 10 minutes for a nitrogen gas post-purge. At the present time, silicon deposition system downtime typically costs over $500.00 per hour.
One possible, but not completely effective, means of avoiding the solidification of SiO2 in the inlet port would be to use a venturi-type scrubbing system instead. Venturi scrubbers operate by passing uncleaned gas through a venturi and spraying or injecting water into the gas flow, thereby causing the solid particles in the gas to be impacted by the faster moving water droplets. This gas and water mixture is then passed into a cyclone or other apparatus which separates the dust-laden water droplets from the gas. The rapid and violent mixing of gas and fluid in venturi scrubbers, to some extent, helps to limit the amount of unclean gas which is exposed to unflushed walls.
Some examples of venturi-type scrubbers are shown in U.S. Pat. Nos. 3,620,510; 3,567,194; 3,638,925; 3,841,061; and 4,578,226. In these types of venturi scrubbers, the injected fluid is primarily used to scrub the incoming gas when forced through the venturi, and the fluid is given a rotational effect to improve the balance of the fluid/gas mixture. Since the overall purpose of a venturi scrubber is to inject cleaning fluid into the gas flow, no attempt is made by these scrubbers to introduce a mist free flow of fluid into the venturi. In addition, venturi scrubbers are generally not suitable for scrubbing silicon gas exhausted from silicon deposition systems because they develop restrictions rapidly and the venturi effect can adversely affect air pressure stabilization within the reaction chamber.
There are a number of other types of effluent gas scrubbing devices which utilize a centrifugal flow of fluid or gas to accomplish the scrubbing operation or to prevent particle adherence to internal surfaces of the scrubber. For example, U.S. Pat. No. 3,722,185, issued to Miczek, discloses a scrubber where water flows down the scrubbing chamber as a concentric sheet and tangentially introduced gas flows up the chamber in a helical path, such that dust particles, driven by centrifugal forces, are forced into the sheet of water and carried away. Use of a swirling sprayer within the scrubbing chamber (see FIG. 2) is disclosed in U.S. Pat. No. 2,281,254.
Another type of gas scrubber which uses a rotating film of fluid is the electro-inertial precipitator unit disclosed in Reif et al., U.S. Pat. No. 4,529,418. Reif et al disclose injecting a fluid film onto the inner surface of a collector tube through which gas passes. Electrostatic and centrifugal forces operating on the gas passing down the tube cause the dust particles within the gas to mix with the liquid and be washed away.
A system which is structurally similar to the present invention, but related to a non-analogous art, is the falling film heat exchanger disclosed in U.S. Pat. No. 2,545,028, issued to Haldeman. Haldeman discloses a heat exchanger in which a film of fluid adhering to the inlet pipe surface is used to absorb and retransmit heat between either two liquids, or a gas and a liquid, or perhaps even two gases. This patent does not concern itself with scrubbing uses, and is apparently not intended to prevent build-up of condensed material at the lower end of the inlet tube 17, (see FIG. 5).


A simplified pump system including a bellow (310) having a suction valve (312), a stem (320), a fluid lock (330), and a tube retainer (380) having a vent element wherein the product flow into and out of a pump chamber formed by the bellow (310) and stem (320) is controlled by the suction valve (312) and fluid lock (330).

Field of the Invention
The present invention relates to pump devices and in particular to bellow-type pumps for dispensing fluids or other pasty products.
State of the Art
Pumps and pump devices are known. In addition, pumps using bellows systems as springs and pistons are known. For example, U.S. Pat. No. 7,793,803, which is incorporated by reference herein in its entirety, discloses a bellow-type pump and pump system which is known.
Another type of pump is disclosed in PCT Application PCT/US11/066423, which is incorporated herein by reference in its entirety.
While various bellow-type pump systems are known, the use of bellows for new delivery requirements and improvements in such pumps are desirable.

SILGAN DISPENSING SYSTEMS NETHERLANDS B.V.


A phase synchronization circuit including a phase-locked-loop synchronizes a phase of a clock signal with a phase of a reference clock signal having a frequency desired by a user. The gates of an NMOS transistor and a PMOS transistors are connected in common to a resistor. The drain and the source of the NMOS transistor are both connected to a ground potential while the drain and the source of the PMOS transistor are both connected to a power source voltage. By changing a number of NMOS and PMOS transistors formed during a metallization process, the capacitance in a loop filter is easily changed.

1. Field of the Invention
The present invention relates to an electric circuit which incorporates a semiconductor transistor and in which a clock signal is used. The present invention is directed in particular to a phase-locked-loop circuit for synchronizing the phase of a signal which is derived by a voltage controlled oscillator to the phase of a reference signal.
2. Description of the Prior Art
Recent developments in semiconductor technology have made it possible for a plurality of equipments mounted in a semiconductor integrated circuit device (hereinafter "LSI") to operate at an increasingly faster speed. Hence, a technical challenge now encountered in enhancing the operation speeds is increasing the speed with which a clock signal which specifies the operation speeds of the equipments incorporated in an LSI is externally supplied to an LSI and distributed to the equipments incorporated in the LSI.
One approach to the problem is to use a phase-locked-loop circuit (hereinafter "PLL circuit") to eliminate a signal delay which is created during distribution of the clock signal to the respective equipments. The PLL circuit is mounted in the LSI and synchronizes the phase of a clock signal which has been supplied to the equipments included in the LSI to the phase of a clock signal which is supplied from outside the LSI.
An analog PLL circuit used for such an objective is shown in FIG. 9. The circuit of FIG. 9 is disclosed in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 22, No. 2, April 1987, pgs. 255 to 261.
The phase of an inner clock signal 12 to be distributed within the LSI needs to be synchronized to a reference phase of a reference clock signal 11, and therefore, is compared with the phase of the reference clock signal 11 in a phase frequency comparator 1. A charge pump circuit 2 outputs a predetermined electric charge in accordance with a phase difference between the two clock signals. The electric charge is accumulated and consequently smoothed in a loop filter 3 which comprises resistors 301 and 302 and a capacitor 303. A potential V.sub.VCO which corresponds to the phase difference between the inner clock signal 12 and the reference clock signal 11 is applied to a voltage controlled oscillator (hereinafter "VCO") 4. Based on the potential V.sub.VCO, the VCO 4 generates a basic clock signal which has a frequency corresponding to the phase difference between the inner clock signal 12 and the reference clock signal 11. Receiving the basic clock signal, a clock signal generator 5 generates various clocks including the inner clock signal 12. That is, the inner clock signal 12 is fed back and synchronized to the reference clock signal 11 to thereby stabilize the phase of the inner clock signal 12.
In such a conventional PLL circuit, first, the frequency of the reference clock signal 11 is determined according to a user's instruction, and then the loop filter 3, the VCO 4 and the other elements are designed to accommodate to the decided frequency. Following this, based on the design, mask patterns are formed which will be used in manufacturing the PLL circuit. Thus, the conventional PLL circuit is tailored especially for the user according to the user's instruction.
On the other hand, there is a demand for incorporating the PLL circuit in a semicustom semiconductor integrated circuit such as a gate array so that equipments formed by the gate array are provided with a signal which is synchronized to an external clock signal which is supplied from the PLL circuit. However, since different users use different external clock signal frequencies, if the PLL circuit is to be incorporated in the gate array, special design for the loop filter 3 and the like is necessary to attain the clock signal frequency which is demanded by the user. This directly contradicts the desired flexibility of the gate array, that is, the major blessing of the gate array.
In addition, a large area is needed to form the capacitor 303 in the loop filter 3, which makes it impossible to enhance the device density.

Phase-locked-loop circuit having adjustable reference clock signal frequency and filter capacitance compensation


Several aspects for resolving a device prompt are described. A processor detects a prompt at a first device connected to a network, wherein the prompt is configured to alert a user proximate to the first device. The prompt may also be configured to solicit one of a plurality of prompt responses from the user. A processor receives a user audio input at a second device connected to the network. A processor determines that the user audio input comprise a first prompt response of the plurality of prompt responses. Once the first prompt response is determined to be included in the user audio input, a processor transmits the first prompt response to the first device. Once received at the first device, a processor executes the first prompt response at the first device to resolve the prompt.

The present invention relates generally to the field of the Internet of Things (IoT), and more particularly to receiving a wake word-less voice input at a device to resolve a device prompt.
Electronic devices have new and emerging capabilities that extend further than only a few years ago. Adding wireless network connectivity to electronic devices has enabled the advent of internet-enabled or internet-connected devices, colloquially called Internet of Things (IoT). IoT refers to the concept of extending internet connectivity beyond conventional computing platforms, such as personal computers and mobile devices, and into any range of traditionally non-internet-enabled physical devices and everyday objects. Embedded with electronics, internet connectivity, and other forms of hardware (such as sensors), these devices and objects can communicate and interact with others over the Internet, and the devices and objects can be remotely monitored and controlled.
The definition of IoT has evolved due to convergence of multiple technologies, real-time analytics, machine learning, commodity sensors, and embedded systems. Traditional fields of embedded systems, wireless sensor networks, control systems, automation (including home and building automation), and others all contribute to enabling the IoT. Smart televisions (TVs) and other IoT devices are internet-enabled and also feature virtual assistants that allow users to interact with the devices via voice commands.
Consumer electronic devices feature pop-up screen notifications that solicit manual user interaction to perform certain tasks. A user may respond to the notification manually or via a virtual assistant. An alarm on a smartphone may sound off with a pop-up notification soliciting manual user input to either stop, silence, or snooze the alarm. The user can select either option by touching the touch screen. A smart TV may be executing a video streaming service when, after a period of time, a pop-up screen notification is displayed asking the user to "continue watching". A user can select the "continue watching" option by selecting the option using the smart TV remote control.
Natural language processing (NLP) engines assist computers in understanding and interpreting human language as it is spoken. NLP engines use two main techniques: syntax and semantic analysis. Syntax is the way in which words are arranged to form a phrase, clause, sentence, or paragraph. Common syntax techniques include parsing, word segmentation, sentence breaking, morphological segmentation, and stemming. NLP engines use syntax to assess the meaning of a word, phrase, clause, sentence, or paragraph. Semantic analysis is used to relate words, phrases, clauses, sentences, or paragraphs to their language-independent meanings. Semantic analysis is performed first by analyzing the context of the word, phrase, clause, sentence, or paragraph in its surrounding text and then by analyzing the structure of the text to identify its proper meaning. Common semantic analysis techniques used by NLP engines include word sense disambiguation, named entity recognition, and natural language generation.
Speech recognition, also known as automatic speech recognition (ASR), refers to the analysis and translation of spoken language into text (e.g., speech-to-text conversion (STT)) by a computer system. An analog-to-digital converter (ADC) is used to translate analog waves of a user's voice into data that a computer can understand. To translate the waves into data, the ADC takes precise measurements of the waves at frequent intervals. The signal produced by the ADC is then divided into short segments that are matched to known phonemes. A phoneme is a perceptually distinct unit of sound that distinguishes one word from another. Once matched, the known phonemes are examined in the context of the surrounding phonemes and compared to a library of known words, phrases, and sentences. Based on the findings of the examination and comparison, the user's spoken words are translated, and a response is produced in the form of text or a computer command.


An embedded chip package is provided. The embedded chip package includes a plurality of chips; encapsulation material embedding the plurality of chips; at least one electrical redistribution layer electrically connected to the plurality of chips; and a common terminal connected to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal.

Sensors of today must be extensively tested and calibrated. Different levels of pressure, in combination with different temperatures may be applied to each pressure sensor component for testing. Complex measurements are also required, particularly if testing also includes movement, such as testing gyro sensors at different angles, or with different accelerations. These complex measurements may be required if pressure sensors are combined with acceleration sensors or gyro sensors, such as those used as tire pressure sensors. Current tests are extensive and expensive as test conditions are administered serially on individual components. Current testing standards allow for only very few components to be tested in parallel. Electrical contacting of the chip for testing also presents a complex challenge.

Embedded chip package, a chip package, and a method for manufacturing an embedded chip package


An optical scanning apparatus includes a light source configured to emit a light beam, a scanning unit configured to deflect the light beam from the light source so as to scan a photosensitive member, an optical lens configured to guide the light beam scanned by the scanning unit onto the photosensitive member, and a lens supporting unit having a fixing portion configured to fix the optical lens, wherein the lens supporting unit includes a movable supporting portion configured to restrict movement of the optical lens in a direction perpendicular to a scanning direction of the light beam and an optical axis direction of the optical lens, to restrict movement of the optical lens in the optical axis direction, and to support the optical lens movably in the scanning direction.

1. Field of the Invention
The present invention relates to an optical scanning apparatus used in an image forming apparatus such as a copying machine, a printer, a facsimile, or a multifunctional peripheral thereof.
2. Description of the Related Art
An electrophotographic image forming apparatus forms an image on a recording medium by making a scan on a photosensitive member by a light beam, developing an electrostatic latent image formed thereby with toner, and transferring and fixing a toner image thereof onto the recording medium. The electrophotographic image forming apparatus is equipped with an optical scanning apparatus to make a scan on the photosensitive member by a light beam. The optical scanning apparatus includes a light source to emit a light beam, a scanning unit (for example, a polygon mirror or rotating polygon mirror, hereinafter called a polygon mirror) to cause the light beam to scan on the photosensitive member by deflecting the light beam emitted from the light source, and an image forming optical system to cause the light beam scanned by the polygon mirror to form an image on the photosensitive member. For the image forming optical system, a scanning speed of the light beam scanning the photosensitive member is stabilized and spot shapes of the light beam formed on the photosensitive member are equalized by one optical lens or a plurality of combined optical lenses.
These optical lenses used for an image forming optical system are mainly formed of resin. Resin lenses have, compared with glass lenses, a disadvantage of being more likely to thermally expand when the temperature rises. However, it is necessary to give special optical characteristics to the optical lenses used for an image forming optical system and thus, optical lenses are formed of resin that is easier to form into special shapes. Moreover, resin lenses can be constructed more inexpensively in terms of cost compared with glass lenses. Due to the above advantages, resin lenses are mostly used as the optical lenses for an image forming optical system.
After the installation position of an optical lens is adjusted by a lens supporting member so that a desired position is scanned by a light beam when installed in an optical scanning apparatus, the optical lens is firmly fixed to the lens supporting member by a fixing member such as an adhesive or screw to hold the position inexpensively with precision (see Japanese Patent Application Laid-Open No. 3-182708).
However, if the optical lens is firmly fixed, issues described below may arise. Heat from a driving device driving the polygon mirror raises the temperature of an optical lens arranged near the polygon mirror, which in turn expands the optical lens thermally. If the optical lens is firmly fixed to the lens supporting member, a portion whose thermal expansion is limited by the fixing and another portion whose thermal expansion is not limited by the fixing arise, thereby distorting the shape of the optical lens and generating a possibility of changing the optical characteristics thereof. Moreover, if the optical lens is fixed to the lens supporting member by an adhesive and a force generated by thermal expansion of the optical lens becomes greater than a restriction part force, there is a possibility that the optical lens peels off from the lens supporting member to change the position of the optical lens.
Confronted with such issues, bringing the thermal expansion amount of the optical lens into line with that of the lens supporting member that fixes and supports the optical lens by bringing the linear expansion coefficient of the optical lens into line with that of the lens supporting member can be considered. Accordingly, even if the temperature of the optical lens and the lens supporting member rises, the optical lens is less likely to be distorted because the difference between both thermal expansion amounts becomes smaller. However, in view of the function of each member, it is very difficult to perfectly match the linear expansion coefficient of the optical lens and that of the lens supporting member. Moreover, the number of revolutions of a rotating polygon mirror is set higher for faster image formation in an image forming apparatus in recent years and thus, when compared with a conventional image forming apparatus, a calorific value from a driving device such as a motor that rotates the rotating polygon mirror during image formation is greater. Therefore, even if the optical lens and the lens supporting member are formed of materials having linear expansion coefficients close to each other, the difference between both thermal expansion amounts becomes greater when the temperature rises, leading to distortion of the optical lens.


In a method of processing a compound semiconductor wafer to deposit or form a specific layer on a wafer surface, to partially remove the specific layer to partially expose the wafer surface, and to etch a partially exposed area of the wafer, etching is performed by irradiating an electron beam and a specific gas which may be, for example, chlorine gas, bromine gas, iodine, or their compounds. Portions subjected to irradiation of both the electron beam and the specific gas are etched from the wafer. The specific layer is deposited or formed in the form of an oxide layer on the wafer surface by spraying an oxygen gas onto the wafer surface with light irradiated on the wafer surface. Such an oxide layer may be either an adsorbed molecular layer of the oxygen gas or a chemically reacted layer which results from reaction of the oxygen gas with the wafer by the help of irradiation of the light. Alternatively, the specific layer may be either a sulphide layer or a nitride layer. The specific layer and the wafer may be removed and etched by the use of different gases which may be a hydrogen gas and a chlorine gas, respectively. In addition, the above-mentioned processing may be carried out without exposure of the wafer to air by the use of an apparatus which comprises a plurality of rooms or chambers airtightly coupled to one another.

This invention relates to a method of processing a wafer of a compound semiconductor to leave a pattern on the surface of the wafer. In addition, this invention relates to an apparatus for use in carrying out a method of the type described. It is to be noted throughout the instant specification that the wafer may have at least one deposition layer of a semiconductor.
In general, a wide variety of compound semiconductors have been proposed and applied to various kinds of devices. Among others, a III-V compound semiconductor is very useful for manufacturing a semiconductor laser device, a field effect transistor device, and the like. In order to manufacture such various devices of the III-V compound semiconductor, which may be called III-V compound semiconductor devices, a pattern should be formed or remain on a wafer of such a III-V compound semiconductor. For this purpose, the wafer is processed to deposit a layer on the surface of the wafer and to selectively etch the layer and/or the wafer.
A recent requirement is to establish high performance and an improved function of such a III-V compound semiconductor device. To this end, attention has been directed to accurately or controllably forming a very fine structure which has a pattern smaller in size than 10 nm.
In a conventional method which has been widely used to form a pattern on a wafer of a III-V compound semiconductor, an organic resist is coated on or applied to a wafer surface to form a resist layer. Subsequently, the resist layer is exposed by light or an electron beam and developed by the use of an alkaline liquid into a mask which has a mask pattern. The wafer is etched through the mask by the use of an etchant. Thus, the mask pattern is transferred to the wafer surface and remains as the pattern on the wafer. However, it is difficult with this method to accurately delineate a pattern which has a size smaller than 100 nm.
Alternatively, a focused ion beam (FIB) is recently used to directly etch a wafer of a III-V compound semiconductor to form a pattern on the wafer, without the organic resist. For example, a gas etching method has been proposed in an article contributed by Ochiai et al to Journal of Vacuum Science and Technology, B3, 657 (1985). Specifically, a specimen is etched by the use of both the focused ion beam and chlorine gas. This gas etching may be referred to as a FIB assisted chlorine gas etching.
With this method, it is possible to comparatively readily delineate a pattern which is smaller in size than 100 nm. However, the gas etching is disadvantageous in that a great number of crystal defects take place in the specimen due to irradiation of the focused ion beam. In order to reduce occurrence of such crystal defects, consideration might be made about using a low energy ion beam or about heating a wafer on forming a pattern. Such use of a low energy ion or heating the wafer is helpful to reduce the crystal defects to some extent. However, it is impossible to completely remove such crystal defects by the use of the above-mentioned gas etching.
In the meanwhile, it is to be noted that crystal growth and etching are repeated several times on manufacturing semiconductor devices formed by the use of a compound semiconductor. In addition, a diffusion process often becomes necessary to diffuse an impurity into a wafer on manufacturing such devices. In this event, the wafer is inevitably exposed to air each time when the crystal growth, the etching, and the diffusion are performed. This means that the wafer surface is exposed to air again and again during manufacturing the semiconductor devices. As a result, the wafer surface is undesirably contaminated by adhesion of oxygen, carbon, and the like. Such contamination of a wafer surface gives rise to degradation of characteriscs, such as an increase of a leak current, in semiconductor devices manufactured, as mentioned above.

Method capable of forming a fine pattern without crystal defects

Optoelectronics Technology Research Corporation


A temperature estimation device estimates a drive duty ratio by taking account of the influence of ambient temperature on the energization to a coil part, on the basis of a drive duty ratio and the ambient temperature, and estimates the power consumption of a motor when the coil part is energized with the estimated drive duty ratio, the power consumption of the motor, this power consumption being accompanied by the heat dissipation of the coil part, the power difference between both the power consumption values, the temperature time constant of the coil part, and a temperature variation during a period of the temperature time constant of the coil part, and estimates the temperature variation of the coil part from the ambient temperature on the basis of these estimated values and a last temperature variation of the coil part.

When a voltage is applied to a direct-current motor, heat is generated by the resistance of a coil thereof and it raises the temperature of the coil. Because there is a possibility that when the coil temperature rises excessively, the coating of the coil suffers a dielectric breakdown, it is necessary to limit the application of the voltage to the motor before the coil temperature exceeds an allowable upper limit temperature.
For example, Patent Literature 1 discloses a device that estimates the temperature of a motor on the basis of both a voltage between the terminals of the motor and a motor current. In this device, a limit is imposed on the maximum value of the current to be supplied to the motor, in accordance with the average or the integral of the value obtained by multiplying the voltage between the terminals of the motor by the motor current. The motor current is detected by a current sensor disposed for temperature estimation.

Temperature estimation device, motor control device, and temperature estimation method


In one embodiment, a braking apparatus includes a pair of brake shoes, a cam follower connected to at least one of the shoes, a compressible spring connected to the cam follower, and an actuation assembly including a motor, a ball screw and an electromagnetic clutch. The braking apparatus is operative to transition from a brake applied position where the brake shoes are closed and a brake release position where the brake shoes are separated. When the braking apparatus is in the brake release position, a brake application may be commenced to close the shoes by power no longer being supplied to the electromagnetic clutch. Additionally, when the braking apparatus is undergoing a brake release cycle to separate the brake shoes, the brake application cycle may also be commenced prior to completion of the brake release cycle when power is no longer supplied to the electromagnetic clutch and the motor.

Elevator cars and other vehicles and devices, such as hooks, buckets and material harnesses on cranes or launching apparatuses, are movable in two opposite directions, frequently by means of a cable or wire rope.
Generally speaking, elevator cars movable by hoist ropes are suspended by wire ropes which go over a traction sheave and down to a counterweight. The counterweight serves to reduce the power required to move the elevator, and also to create traction (prevent slippage) with respect to the traction sheave. The traction sheave is driven directly by a motor or indirectly by a motor through a geared machine. A normal brake is applied to the drive to stop and/or hold the elevator at a floor along the elevator shaft.
With elevator cars, specifically, the usual elevator codes require that an emergency brake be included, such brake arresting the descent of the elevator car when it is descending at a speed in excess of a predetermined speed. A known braking device for such purpose is a safety device which grips the car guide rails even in the event of breakage of the elevator hoisting rope.
With a high factor of safety for the wire ropes, at least one country has recognized that these ropes never break and is allowing other emergency brakes in lieu of the safety device which grips the guide rails. Also, since counterweights are generally heavier than the elevator, with a mechanical failure, such as that of the normal brake, there is danger of the elevator over speeding in the ascending direction. In addition, depending on the load in the elevator car when a mechanical failure occurs, the car could leave the floor in either direction with the doors open. Many countries require emergency devices to be activated in the event of the above, and also require ascending car overspeed protection. In addition, many countries are considering code changes to require protection against leaving the floor with the doors opened.
Known braking devices include brakes applied to the hoisting drum (traction sheave), to the hoisting ropes, or to the car or counterweight guide rails.
It is considered to be important that the braking force be substantially constant even with wear of various elements of the braking system, such as wear of the brake shoe linings. Additionally, the brake should be responsive to overspeed in either direction or to improper opening of doors during use. Thus, it would be advantageous to include as part of an elevator system an emergency brake capable of gripping the ropes to satisfy the above requirements. Even with such an emergency brake, however, the brake would need to be reset after it has been applied, and resetting of the brake may require at least several seconds to reach a fully open state during which the brake cannot be applied.
Thus, a need exists for an improved emergency elevator braking apparatus that can stop an elevator with a smooth and consistent braking force, even when the brake pads are worn, and also apply a braking force while resetting the brake.


A data processor capable of preventing a system from starting up improperly due to incomplete program updating. The data processor receives, by way of an external interface, a program which is sent by communicating medium such as a broadcast wave or a telephone network from an external device and stores the received program into a memory B which is different from a memory A storing a program for the system when a version of the received program is newer than that of a program currently executed by the data processor, thereby starting up an MPU at the next time with the program stored in the memory B.

1. Field of the Invention
The present invention relates to a data processor, a program updating method and a storage medium, and more specifically a data processor, a program updating method and a storage medium which update a program with data sent from outside.
2. Related Background Art
In a data processor which executes various kinds of application programs such as those for personal data management functions, it is general to write a program such as firmware for obtaining executing environments for the application programs into a nonvolatility memory.
The program written in the nonvolatility memory is rewritten when a bug exists in the program or when a version of the program is to be upgraded.
Japanese Patent Application Laid-Open No. 6-44064 discloses a method to rewrite the program stored in the nonvolatility memory. This method is configured by receiving and temporarily holding an updating program sent from outside by way of a broadcast wave or a telephone network, and automatically rewriting the program stored in the nonvolatility memory into the received program.
Furthermore, digital broadcast has a high possibility to provide new kinds of services one after another as compared with conventional analog broadcast. Accordingly, a receiver for the digital broadcast which is newly purchased may soon be out-of-date when its functions remain unchanged from those at a time of purchase and cannot cope with the new kinds of services.
In order to solve such a problem, there is a concept to modify a software program to cope with the new kinds of services without changing any hardware of the receiver. That is, there is a method which sends a program in a condition overlapped with a broadcast wave for downloading, thereby updating a program in an instrument which is capable of receiving the digital broadcast.
However, the method disclosed by Japanese Patent Application Laid-Open No. 6-44064 is configured by rewriting the program stored in the nonvolatility memory into a new program and may update the program incompletely when a power supply is intercepted due to power failure during the updating of the program, thereby resulting in a situation where a system cannot start up due to the incomplete updating of the program.
Furthermore, the method does not take an operating condition of the instrument into consideration for downloading and may update the program even while the receiving instrument is operating, thereby resulting in an erroneous operation of the instrument.
A primary object of the present invention is to provide a data processor, a program updating method and a storage medium which are capable of preventing a system from being started up improperly due to incomplete program updating.
Another object of the present invention is to provide a data processor, a program updating method and a storage medium which update a program on the basis of an operating condition on a receiving side.
In order to attain these objects, the data processor according to the present invention is a data processor operating on the basis of a program stored in first memory means, and comprising receiving means which receives an updating program sent from outside, comparing means which compares a version of the program stored in the first memory means with a version of the updating program, and control means which stores the updating program into second memory means different from the first memory means when the comparing means judges that the version of the updating program is newer than the version of the program stored in the first memory means.
Furthermore, the data processor according to the present invention is a data processor having processing means which processes data transmitted from outside on the basis of a program stored in the first memory means and outputs the data to an output device, and comprising receiving means which receives an updating program sent from outside, control means which stores the received updating program into second memory means different from the first memory means, and changing means which changes processing by the processing means on the basis of the program stored in the first memory means to processing by the processing means on the basis of the updating program stored in the second memory means.
Furthermore, the data processor according to the present invention is a data processor having processing means which processes data sent from outside on the basis of a program stored in memory means and outputs the data to an output device, and comprising judging means which judges whether or not processing is executed by the processing means, receiving means which receives an updating program sent from outside, memory control means which stores the received updating program into the memory means when the processing is not executed by the processing means and a processing control means which controls the processing means on the basis of the updating program stored in the memory means.
Moreover, the program updating method according to the present invention is a program updating method which updates a program in a data processor operating on the basis of a program stored in first memory means, and is configured to receive an updating program sent from outside using receiving means, compare a version of the program stored in the first memory means with a version of the updating program and store the updating program into second memory means different from the first memory means when the comparison indicates that the version of the updating program is newer than the version of the program stored in the first memory means.
Moreover, the program updating method according to the present invention is a program updating method which updates a program in a data processor having processing means for processing data sent from outside on the basis of a program stored in first memory means and outputting the data to an output device, and is configured to receive an updating program sent from outside using receiving means, store the received updating program into the second memory means different from the first memory means and change processing by the processing means on the basis of the program stored in the first memory means to processing by the processing means on the basis of the updating program stored in the second memory means.
Moreover, the program updating method according to the present invention is a program updating method which updates a program in a data processor having processing means for processing data sent from outside on the basis of a program stored in memory means and outputting the data to an output device, and is configured to judge whether or not processing is executed by the processing means, store an updating program sent from outside into the memory means when the processing is not executed by the processing means and control the processing means on the basis of the updating program stored in the memory means.
In addition, the storage medium according to the present invention is a memory means which is to be used in a data processor operating on the basis of a program stored in first memory means, and comprises a step to receive an updating program sent from outside using receiving means, a step to compare a version of the program stored in the first memory means with a version of the updating program and a step to store the updating program into second memory means different from the first memory means when the comparison indicates that the version of the updating program is newer than the version of the program stored in the first memory means.
In addition, the storage medium according to the present invention is a storage medium which is to be used in a data processor having processing means for processing data sent from outside on the basis of a program stored in first memory means and outputting the data to an output device, and comprises a step to receive an updating program sent from outside using receiving means, a step to store the received updating program into second memory means different from the first memory means and a step to change processing by the processing means on the basis of the program stored in the first memory means to processing by the processing means on the basis of the updating program stored in the second memory means.
In addition, the storage medium according to the present invention is a storage medium which is to be used in a data processor having processing means for processing data sent from outside on the basis of a program stored in memory means and outputting the data to an output device, and comprises a step to judge whether or not processing is executed by the processing means, a step to store an updating program sent from outside into the memory means when the processing is not executed by the processing means and a step to control the processing means on the basis of the updating program stored in the memory means.

Data processor, program updating method and storage medium


An integrated monitoring system and method are provided with the capability for monitoring ground surface movements of electric taxi drive system-driven aircraft, ground vehicles and personnel, and objects within airport ramp areas. Monitoring units may include a scanning LiDAR device with and without cameras or other sensing devices to transmit meshed real time encrypted data from multiple locations to an artificial intelligence-based processing system that generates a visual display of the monitored area for communication to aircraft cockpits and locations responsible for controlling ramp operations. Monitoring units may be mounted in single or multiple exterior locations on aircraft and/or in locations on ground vehicles and equipment, ground personnel, and the airside portion of an airport terminal.

Airport ground travel surfaces, particularly apron or ramp areas, can be very congested places at today's airport terminals. Multiple aircraft are simultaneously arriving and departing, ground-based service and support vehicles and personnel are servicing parked aircraft, and ground crews are directing the arriving and departing aircraft into and out of gates. In addition, the entrances and exits between taxiways and these congested ramp areas may themselves become congested as multiple aircraft move into and out of ramp areas to park and transfer passengers and cargo. The avoidance of collisions and similar adverse ground incidents in these areas requires careful monitoring and control of the locations and movements of aircraft, ground vehicles, equipment, and personnel as aircraft are maneuvered on the ramp surfaces. Whether the aircraft are maneuvering into a parking location or being pushed back at departure, ground crews currently guide the moving aircraft, largely because the pilot and flight crew are not able to see the entire ground environment or space surrounding the aircraft. The sides and rear of the aircraft exterior, from the ground surface to above the wings, are not visible to the pilot and flight crew from the cockpit. The use of cameras and sensors mounted on aircraft exterior locations has been helpful. However, despite the availability of these devices, incidents involving collisions during ground maneuvers within an airport ramp area, for example between moving and parked aircraft and moving aircraft and ground service vehicles and equipment, still occur all too frequently.
It has been proposed to attach ADS-B or other transponders to every ground vehicle to monitor the movements of these vehicles. While this may provide some data relating to the positions and movement of the ground vehicles with transponders, the cost of outfitting all of the ground vehicles at an airport with transponders is significant. In addition, the information that may be obtained from the transponders may be limited. For example, such monitors do not identify sizes and shapes of objects. Ramp areas may include many objects, including carts and tow bars, as well as luggage that has fallen off a cart, that do not move and could be the source of ground incidents involving moving ground vehicles and aircraft. Such objects are not likely to be detected by the proposed transponders.
The efficiency, speed, and safety of ramp surface operations, whether during aircraft taxi-in at arrival, push back at departure, or other aircraft movements within an airport ramp area, may be adversely affected by the ground congestion found in the ramp areas at most large airports. Multiple airlines concurrently conduct both push back and arrival operations for multiple aircraft, and aircraft often must park in parking locations with minimal safe clearance. This strains both the available ground personnel and the available equipment. Aircraft turnaround times may be increased significantly when ground personnel and tow bars, adapters, tugs or other equipment are not available when needed. Turnaround delays for these reasons have become all too common.
Driving an aircraft on the ground independently during taxi with pilot-controlled landing gear wheel-mounted electric taxi or other drive systems without reliance on operation of the aircraft's main engines or the use of tow vehicles has been proposed by Applicant and others. As the pilot controls operation of the electric taxi drive system to maneuver an aircraft independently of engines and tugs within the ramp area or during taxiing to and from the ramp area, pilot situational awareness may be increased compared to when aircraft are driven only with operating engines. Increased pilot situational awareness is likely to improve aircraft ground travel safety. Additional monitoring of the ground level environment external to the portions of the aircraft not readily visible to the pilot or crew driving the aircraft and analysis of the data obtained, however, would further improve pilot situational awareness, avoid potential collisions, and enhance safe operation of the aircraft as they are driven independently with electric taxi drive systems into and out of congested airport ramp areas. Facilitating the monitoring of the ramp environment by ground personnel and air traffic control personnel may also avoid potential collisions and enhance safe ramp operations.
Applicant has proposed a monitoring method useful during accelerated push back for aircraft driven with engines-off or electric taxi drive systems that includes a plurality of different types of sensing devices mounted on the exterior of the aircraft in U.S. Pat. No. 9,394,059. Scanning an aircraft's landing zone area to target obstacles while an aircraft is still in the air has also been proposed, for example in U.S. Pat. No. 6,665,063.
Some airport ramp area monitoring devices and systems are also available, including the Safedock docking system mounted on terminal gates that employs LiDAR technology to automatically guide pilots into assigned gate parking locations. Closed circuit television (CCTV) cameras may be supplied at gate locations in airport ramp areas at many airports. Such CCTV cameras may monitor gate security, among other uses. Employing these cameras in combination with a computer-based data collection and analysis system and associated software has been proposed to keep track of specific services rendered in gate areas in connection with an aircraft's turnaround. Such a system may monitor ramp areas as seen from the positions of the CCTV cameras on the gates and/or terminal buildings and may provide a record of various activities during aircraft turnaround; however, the extent of the ramp area monitored may be limited by the fixed locations of these cameras. Additionally, the information obtained by CCTV and other cameras is limited during low visibility weather conditions. It has not been suggested to mesh data obtained from these or other diverse airport sources to minimize ramp incidents and improve ramp safety.
Artificial intelligence (AI), very generally defined as machine intelligence, has received much attention lately, and its potential applications are currently the focus of significant research and discussion. A range of automated applications, including driverless cars, assisted medical diagnosis, and personal assistants, exemplify a few of the present suggested or actual uses of artificial intelligence. Airline and airport operations, of necessity, must focus on establishing and maintaining safety and have relied on human control and intervention to achieve an increasingly safer level of air travel. While airlines and airports have employed artificial intelligence to improve some aspects of passenger experience, such as answering common passenger questions with chatbots and verifying boarding and luggage with facial recognition, it has been thought difficult to continue to maintain safety, especially in the ramp area, while relinquishing human control and intervention in other operations.
That artificial intelligence might be useful in the airline industry has been recognized, and the airline industry's investment in artificial intelligence is expected to increase from about US$152 million in 2018 to an estimated about US$2.22 billion in 2025, with no suggestion of specific airline, aircraft, or airport operations or functions that could be coupled to artificial intelligence. It is estimated that global passenger traffic is likely to double over the next two decades, which will strain existing air traffic control and other airport, and airline, aircraft and passenger handling systems, as well as ramp surface operations. The constant monitoring of ground surface movements of aircraft, other vehicles, and personnel within airport ramp areas, both from monitoring systems on the aircraft and on the vehicles and from monitoring systems on airport structures, coupled with the transmission and meshing of data and the analysis and automatic control possible using intelligent algorithms and artificial intelligence, could improve the safety, efficiency, and security of airport ramp operations. The handling of the expected increase in global passenger traffic by airports and airlines may be facilitated by the implementation of such a monitoring system, and a need exists for an integrated monitoring system and method capable of achieving these objectives.

Airport ramp surface movement monitoring system


A process to form an ethylene-based polymer comprises polymerizing a reaction mixture comprising ethylene, at least one symmetrical polyene and at least one chain transfer agent system comprising at least one chain transfer agent (CTA) in the presence of at least one free-radical initiator and in a reactor configuration comprising at least two reaction zones, reaction zone 1 and reaction zone i (i≥2), wherein reaction zone i is downstream from reaction zone 1. The ratio of “the activity of the CTA system of the feed to the first reaction zone” to the “activity of the CTA system of the cumulative feed to the reaction zone i,” (Z1/Zi), is less than or equal to (0.8−0.2*log(Cs)), wherein Cs is from 0.0001 to 10.

Conventional low density polyethylene (LDPE) has good processability, but when used in film and/or extrusion coating applications, increased melt strength and higher G′ performance is still desired. U.S. Pub. No. 2008/0242809 discloses a process for preparing an ethylene copolymer in a tubular reactor at a peak temperature of 290° C.-350° C. The comonomer is a di- or higher functional (meth)acrylate WO 2007/110127 discloses an extrusion coating composition comprising an ethylene copolymer polymerized in a tubular reactor at a peak temperature of 300-350° C. The comonomer is a bifunctional α, ω-alkadiene. WO97/45465 discloses an unsaturated ethylene copolymer, method for producing it, and its use for producing crosslinked structures. The unsaturated ethylene copolymer comprises a polymer, obtained by radical polymerization through a high-pressure process, of ethylene, and at least one monomer that is copolymerizable with ethylene and includes a diunsaturated comonomer of the formula (I) H2C═CH—O—R—CH═CH2, where R=—(CH2)m-O—, —(CH2CH2O)n-, or —CH2-C6H10-CH2-O—, m=2-10, and n=1-5. Preferably, this comonomer is 1,4-butanediol divinyl ether. WO2014/003837 discloses an ethylene-based polymer made by reacting ethylene and at least one asymmetrical polyene having an "alpha, beta unsaturated end" and a "C═C double bond end" in the presence of a free-radical initiator. The impact of the above-described multifunctional components on the final polymer through coupling and/or branching reactions is complex, and depends on the type and reactivity of the functional groups. A vinyl functional group will act as a comonomer and incorporate into a polymer chain/molecule. Chain Transfer Agent (CTA) functionality will either start the formation of a new polymer molecule, or initiate, after incorporation of the monomeric group, the formation of a Long Chain Branch (LCB) or T-branch. For a multi- and/or bifunctional component to impact polymer rheology, it is important that (1) at least two functional groups of the component molecule react and (2) effective branches are formed in the polymer.
WO2013/059042 describes the use of ethylene and/or CTA feed distribution to broaden molecular weight distribution (MWD) and increase melt strength, while keeping all other process conditions constant The use of highly reactive multifunctional components is also subject to other process and/or polymer concerns, such as stability of the component, premature polymerization and fouling formation potential in the compression and preheating sections, reactor fouling, gel formation in polymer, process stability potentially leading to ethylene decomposition, and the like. Additional polymerizations are described in WO 2013/149699 and WO2013/149698. There remains a need for such processes in which low concentrations of coupling and/or branching components can be used to achieve the desired high G′ value products for film and extrusion coating applications, while avoiding or reducing undesired product and process issues, as product gels and process instability and/or fouling. Furthermore, the lower concentration of coupling and/or branching components leads to lower consumption and costs. These needs and others have been met by the following invention.

Process to make tubular ethylene based polymers with high G′ and broad MWD


A substrate provided with alignment marks, a display screen, a splicing screen and an alignment method of splicing screen, in which, the splicing screen includes at least two display screens with alignment marks. A substrate of the display screen is provided with at least two alignment marks, and different alignment marks have a height difference therebetween which is larger or equal to a standard difference value. A narrow bezel splicing of display screens can be achieved by setting the alignment marks with different heights.

The requirements on splicing technology of display screen and display device are progressively stricter as the increasingly wider application of Compact TV (i.e., narrow bezel TV) and Public Information Display (PID) splicing screen which are popular in recent years. A splicing screen is a large-framed screen constituted by a plurality of display screens which are arranged, as display units, in a matrix (e.g., 2×2, 3×3, 4×4 or even larger one based on freely unlimited splicing) for displaying a large-sized image with each display screen displaying a portion of the image or for respectively displaying different images on different display screens.
Input signals of a splicing screen are allocated to each of the display screens after completely processed by an image controller. The image displayed on each display screen can extend beyond a border of the display screen, which, however, usually needs to ensure a minimum gap between display screens. The display quality of an individual display screen will directly influence the display effect of the whole splicing screen which significantly varies depending on the type of the utilized display screen. An image processor, as one of the core devices of a splicing screen, serves for sending signals of computer, video and network to be displayed to an image splicing controller; the processed image signals are sent to corresponding display screens, respectively, with each display screen only displaying a portion of the entire image, so that a complete, large display frame can be established by combining all the portions on the display screens together. The resolution of the large display frame is a multiple of that of each display screens. However, the image processor can only make improvement in video processing, and the splicing effect presented by the splicing screen as obtained still involves a considerable wide splicing gap and can not meet the requirement of narrow splicing gap. As shown in FIG. 1, an example of a 2×2 splicing screen is illustrated, in which each display screen displays a small image.
The technology of narrow bezel splicing screen in conventional technology is to narrow the bezel width of each display screen to achieve an objective of narrowing the splicing gap between the spliced screens after completion of splicing. FIG. 2 is a schematic view showing the design of alignment marks disposed around the narrow bezel splicing screen according to a conventional technique. In the figure, A, B and C are representative of the upper left corner, lower left corner and lower right corner of a small display screen, respectively; 1A, 2A and 3A are representative of three alignment marks at the upper left corner; 1B, 2B and 3B are representative of three alignment marks at the lower left corner; 1C, 2C and 3C are representative of three alignment marks at the lower right corner. Each of the alignment marks has an exclusive area around it for excluding any image therein. The alignment mark has an area of 0.5 mm×0.5 mm, and its exclusive area has an area of 1.5 mm×1.5 mm. If there are other images extending into the scope of the exclusive area of the alignment mark, the production line will generate an alarm and fail to tape-out. As shown in FIG. 2, the three alignment marks at the upper left corner and their exclusive areas are not overlapped with each other, thus it will not result in a tape-out failure. However, the three alignment marks at the lower left corner, the three alignment marks at the lower right corner, and the respective exclusive areas of these alignment marks are overlapped one another, especially the exclusive areas of the alignment marks 1B, 2B and 3B at the lower left corner are considerably overlapped with each other. As shown in the enlarged view of FIG. 3, the lower left corner of the exclusive area of alignment mark 2B is partially overlapped with the alignment mark 1B, and the upper right corner of the exclusive area of alignment mark 2B is partially overlapped with the exclusive area of alignment mark 3B, resulting in that some of the images are extending into the exclusive areas of alignment marks, which leads to a tape-out failure.
For achieving a narrow bezel of a splicing screen, the existing process allowance has to be reduced to the minimum, so as to reduce the width of the display screen at the alignment mark and the width of the alignment mark on the substrate, so as to improve accuracy and standard. However, merely relying on reducing the existing process allowance contributes little to the narrowing of the bezel of splicing screen, and problems that influence the display effect of the splicing screen remains unsolved.

Substrate, display screen, splicing screen and alignment method of splicing screen


A vertical takeoff and landing (VTOL) aircraft design particularly suitable as a full-sized aircraft or remote controlled (RC) model aircraft is disclosed. The invention employs lightweight, high strength materials to reduce the power requirements of the propulsion plant. A preferred system of the invention comprises one internal combustion engine able to spit shaft power to four fan units. The fan units further employ counter rotating fan blades for stability. Separate horizontal and vertical tilting mechanisms delivered to the fan units are additionally disclosed. A variation in design is further included wherein electric motors provide the necessary shaft power.

1. Field of the Invention
The present invention pertains generally to vertical takeoff and landing (VTOL) aircraft. More particularly, the present invention pertains to aircraft having tilting propulsion systems for vertical takeoff. The present invention is particularly, but not exclusively, useful as a VTOL aircraft design for relatively small remote control (RC) aircraft and larger passenger aircraft.
2. Description of the Prior Art
Vertical Takeoff and Landing (VTOL) aircraft are generally any of numerous unconventional designs for aircraft including rotary wing helicopters, having rotatable or divertible propulsion systems that allow for vertical takeoff/landing and horizontal flight. Advancements in technology have long been desired to produce a more commercially viable design for VTOL aircraft. Current methods of travel have numerous constraints, particularly conventional air travel that requires expensive airports having long runways and vast airspace. Especially, transportation between small and medium cities could benefit from major improvements in aircraft design and within large cites where automobiles and current aircraft have not met the needs of the public.
The helicopter as a VTOL aircraft was once envisioned for public use as providing safe and efficient travel unsuitable for current automobiles and typical runway aircraft. For many reasons, however, the helicopter has remained a limited-use, special-purpose aircraft. Principally, the large rotating lift blades of the helicopter design must meet very stringent mechanical requirements and require a very complicated system for drive and control. Another disadvantage of the helicopter is that the angular moment caused by the lift blades requires the use of a tail rotor rotating about a horizontal axis. Loss of the tail rotor is thus a potentially devastating casualty. Helicopters also employ pitch adjustable blades resulting in extremely expensive construction and maintenance costs and a high level of pilot proficiency in flying and controlling the aircraft.
Certain additional designs for vertical takeoff and landing (VTOL) aircraft and for vertical and short takeoff and landing (V/STOL) are well known. Some designs are modifications of fixed wing aircraft to include vertical propulsion while maintaining stability in vertical lift mode. U.S. Pat. No. 4,474,345 "Tandem Fan Series Flow VSTOL Propulsion System" by R. G. Musgrove discloses a propulsion system for V/STOL that includes a jet engine for normal wing borne flight modified with additional fans having a diverter to exhaust thrust directionally downward. While this design is capable of supersonic speeds, an aircraft of this system will be very heavy and require a relatively powerful vertical thrust. Similarly, a design proposed by Moller, U.S. Pat. No. 5,115,996 employs directional vectoring of thrust to provide vertical lift capability. This design will also yield a relatively heavy aircraft as it employs multiple engines with large horsepower requirements. Furthermore, mobility and maneuverability are concerns especially at lower air speeds and transitioning between hovering and normal flight mode.
Additional designs of VTOL aircraft are known in the art each having certain advantages and drawbacks. One such design is a tilt-rotor type that is also referred to a "convertible" type, having rotors, which are capable of being tilted with respect to the aircraft structure. For example, during takeoff, the rotors are orientated almost vertically so as to operate like a rotary wing, in order to allow vertical takeoff in the manner of a helicopter. Next, the aircraft flight is transitioned from vertical to horizontal mode, thus the rotors are tilted horizontally so as to operate like airscrews.
Among the tilt-rotor type VTOL aircrafts there are some that employ multiple large engines to provide the necessary thrust. These designs however will be relatively heavy and will not have a particularly attractive power-to-weight ratio. Also, in vertical flight mode, a large weight proportioned at a distance from the aircraft's center of gravity will cause a moment of inertia adversely affecting stability and mobility. Also known, are VTOL designs of model aircraft or miniature remote controlled (RC) aircraft. One such design is disclosed in U.S. Pat. No. 5,836,545 Toy Aircraft And Method for Remotely Controlling the Same by D. Dixon. In the model aircrafts, weight is relatively less of a concern and stability is of greater concern. In all designs, weight, stability and power-to-weight ratio of the propulsion system are chief design concerns.
Heretofore, existing technology in power systems and strength in lightweight materials have encumbered the realization of a commercially viable VTOL design. Particular advancements in these areas have lead to the present invention that provides a lightweight VTOL design particularly suitable for passenger aircraft or an RC model aircraft. The present invention additionally provides a VTOL design that is easy to manufacture, relatively simple to use, and comparatively cost effective.


An extrusion puller which comprises an upper jaw, a lower jaw, and means for mounting the upper and lower jaw relative to each other. The upper jaw comprises a plurality of jaw fingers with radially extending gripping teeth circumferentially spaced around the bottom portion of the tooth wherein the attack angle between teeth and the spacing angle between adjacent teeth is selected so that substantially full penetration of at least one of the gripping teeth into the workpiece is achieved without interference from an adjacent tooth. The lower jaw comprises a serrated upper surface comprising a semi-circular scalloped configuration of a plurality of peaks and valleys. The combination of the upper jaw and lower jaw configuration allows for increased gripping strength to be exerted on the workpiece and thereby avoid defects within the extruded workpiece.

One known extrusion pulling apparatus incorporates extrusion puller jaws composed of an upper and lower jaw wherein the upper jaw comprises a plurality of multi-toothed fingers and the lower jaw comprises a flat serrated plate. One jaw moves relative to the other to allow for opening and closing movement of the jaws for gripping and releasing of an extruded workpiece. Typically, the upper jaw moves relative to a fixed lower jaw and a sufficient amount of gripping pressure is applied to the workpiece by the jaws so that the extrusion apparatus can pull the workpiece from the die.
FIG. 1 (prior art) and FIG. 1A (prior art) (hereinafter known as the "Smith Design") illustrate a known upper jaw finger 10A and a lower jaw 12A in an extrusion puller apparatus for gripping an extruded workpiece 14A. The upper jaw finger is comprised of a body l6A, means for mounting the finger 18A into the upper jaw and a plurality of gripping teeth 20A. Each of the teeth is comprised of a leading edge 22A and a trailing edge 24A. The angle created between the leading edge 22A of one tooth and the trailing edge 24A of the preceding tooth is the attack angle A.
The upper jaw typically is pivotably mounted relative to the fixed lower jaw 12A. The upper jaw pivots downward until the teeth of both jaws engage the workpiece 14A and applies force thereto to create sufficient gripping pressure on the extruded workpiece 14A. The pivotable movement of the upper jaw causes the teeth 20A to travel along an arc B during the gripping and releasing movement of the jaws. The teeth 20A of the jaw finger 10A may contact the workpiece 14A anywhere along arc B depending on the profile of the workpiece 14A.
Because of the large number of teeth 20A on each upper jaw finger 10A of the Smith Design, the attack angle A on the Smith Design is relatively small. Therefore as the upper jaw finger 10A pivots downward the teeth travel along arc B until a first tooth 23A enters the workpiece 14A. But, before all of the body of the first tooth 23A penetrates the workpiece 14A, the flat trailing edge 24A of the preceding tooth 25A contacts the workpiece 14A. The flat trailing edge 24A of the preceding tooth 25A cannot penetrate the surface of the workpiece 14A without a great amount of pressure from the upper jaw. Without this extremely large force, the gripping strength of the jaws may be inadequate and often results in slippage of the workpiece 14A within the jaws.
The lower jaw 12A of the Smith design comprises a plurality of serrations 26A which extend perpendicular to the extrusion axis and are spaced a short distance apart. The serrations 26A are composed of a plurality of peaks 28A and valleys 30A or may be a saw tooth design (not shown). The Smith design utilizes a plurality of small serrations as shown in FIG. 1 (Prior Art).
The U.S. Pat. No. 4,566,298 to Elhaus (issued Jan. 28, 1986) discloses an extrusion puller incorporating a plurality of clamping segments or puller fingers. This concept is also disclosed in the U.S. Pat. No. 3,188,539 to Harwood et al (issued Jan. 21, 1964), the U.S. Pat. No. 4,307,597 to Elhaus et al (issued Dec. 29, 1981) and the U.S. Pat. No. 3,881,339 to Mannell (issued May 6, 1975).
The Mannell patent also discloses the concept of providing springs or other biasing means to each of the individual fingers to allow for the gripping of a complex-shaped workpiece.
The concept of incorporating a plurality of serrated jaws for gripping a workpiece during extrusion is disclosed in the U.S. Pat. No. 4,522,091 to Toffolon (issued June 11, 1985) and the U.S. Pat. No. 3,078,984 to Baker (issued Feb. 26, 1963).


This invention relates to a memory cell array structure which comprises a low electric resistance semiconductor substrate and a number of memory cells. Each memory cell includes a capacitor portion and a switching element portion substantially provided thereon. The switching element portion comprises as one constituent region thereof one of electrodes, i.e., the second electrode of the capacitor portion. The second electrodes of all the memory cells are integrated altogether to constitute an integral common electrode which provides a separate region between the memory cells. With such a construction of the memory cell array structure, the area occupied by one memory cell is decreased and the cell-to-cell variation in the capacitor capacity is also decreased. This invention also relates to a process for producing such a memory cell array structure.

1. Field of the Invention
The present invention relates to a memory cell array structure comprising a number of memory cells having a structure adapted to attain a high scale of integration, and to a process for producing the same.
2. Prior Art
A high scale of integration of a memory cell array structure enables various electronic appliances such as information processing appliances to be miniaturized and improved in performance. Accordingly, intensive investigations have been made with a view to scaling up the integration of a memory cell array structure.
A brief description will be made of a few types of memory cell structures incorporated into conventional memory cell array structures of dynamic random access memory (DRAM) type as examples.
Memory cells constituting a memory cell array structure of DRAM type each comprise one switching element and one capacitor. Such memory cells are widely used since they are adapted to attain a high scale of integration. In each such memory cell, a switching transistor is used to store an electric charge in a capacitor or discharge an electric charge from the capacitor to thereby provide a certain level of an electric charge being present in the capacitor, which level corresponds to a certain piece of information.
In general, such a memory cell has a built-in structure wherein a capacitor comprising a silicon substrate, an insulating film (e.g., a silicon oxide film) and a polycrystalline silicon film is juxtaposed in a plan with a MOS transistor around the upper surface of the silicon substrate. In the case of this type of memory cell structure, however, since the area occupied by one memory cell as projected on the reverse surface of a substrate is large, the scale of integration in the production of a memory cell array structure comprising a number of such memory cells is inevitably restricted. Therefore, the above-mentioned type of memory cell structure is not preferable in order to scale up the integration of a memory cell array structure. In view of this, there has heretofore been proposed various memory cell array structures having a three-dimensional structure, such for example as will now be described while referring to FIGS. 1 to 3, wherein hatching to indicate cross sections, and the like are partially omitted to avoid too much complication of the drawings.
FIG. 1 is a schematic cross-sectional view of a conventional memory cell structure adapted to attain a high scale of integration in a memory cell array structure.
This memory cell structure comprises a so-called "trench capacitor" 15 formed by utilizing a trench 13 dug in a silicon substrate 11, and a switching transistor 25 constituted of a drain region 19 connected with a bit line 17, a gate electrode 21 as a word line, and a source electrode (not shown in FIG. 1) connected with the cell plate of the capacitor 15. According to this memory cell structure, the area occupied by the capacitor portion as projected on the reverse surface of the substrate can be decreased to enable a memory cell array structure to be greatly improved in the scale of integration of memory cells incorporated thereinto.
FIGS. 2 and 3 are schematic fragmentary cross sectional views of conventional memory cell array structures comprising a number of memory cells better adapted to attain a high scale of integration.
FIG. 2 shows part of a memory cell array structure as disclosed in Japanese Patent Laid-Open No. 239,658/1986. This memory cell array structure comprises a p.sup.+ -type silicon substrate 31; a plurality of insular p.sup.- -type semiconductor layers 35 provided thereon and separated from one another by a first trench 33 provided therebetween in matrix fashion and having an inner wall face having thereon an insulating layer 39; a capacitor electrode 37 embedded in a second trench formed inside the first trench by the insulating film 39 and ranging from the bottom to part of the height of the second trench; a plurality of n.sup.- -type semiconductor layers 41 embedded in lower inner side wall portions of respective insular p.sup.- -type semiconductor layers 35 and substantially confronting the capacitor electrode 37 through the insulating film 39 therebetween; a plurality of gate electrodes 43 embedded in the second trench on the upper side of the capacitor electrode 37 with the insulating layer 39 therebetween; a plurality of n.sup.+ -type semiconductor layers 45 covering the upper surface of the insular p.sup.- -type semiconductor layers 35; and p.sup. - -type semiconductor regions 47 constituting upper inner side wall portions of the respective insular p.sup.- -type semiconductor layers. The capacitor of each memory cell comprises part of the capacitor electrode 37, an n.sup.- -type semiconductor layer 41 as a partner capacitor electrode, and part of the insulating film 39, while the switching transistor of each memory cell comprises part of a gate electrode 43, part of an n.sup.+ -type semiconductor layer 45 as a drain region, a p.sup.- -type semiconductor region 47 as a channel region, and a source region (not shown in FIG. 1) connected with the n.sup.- -type semiconductor layer 41.
FIG. 3 shows part of a memory cell array structure as disclosed in IEEE, pp. 714-717 (1985). Each memory cell of this memory cell array structure comprises a p.sup.+ -type semiconductor substrate 51 having a p-type semiconductor layer 52 provided thereon and a trench 53 formed therein; a capacitor electrode 55 embedded in the trench 53 with a thin insulating film 57 therebetween (provided on the inner wall face of the trench 53 and substantially corresponding to the contour of the trench 53) and ranging from the bottom to part of the height of the trench 53; a drain region 59 provided on an upper outer side wall face of the trench 53 with an insulating film 58 therebetween and on the upper side of the p-type semiconductor layer 52; a channel region 61 constituting part of the p-type semiconductor layer 52 and existing along an upper outer side wall face of the trench 53 with the insulating film 58 therebetween but under the drain region 59; a source region 63 provided on an upper outer side wall face of the trench 53 with the insulating film 58 therebetween but under the channel region 61 and embedded in the p-type semiconductor layer 52; and a gate electrode 65 partially inserted into the trench 53 and substantially confronting the channel region 61. The capacitor of each memory cell comprises the capacitor electrode 55 and part of the p.sup.+ -type semiconductor substrate as a partner capacitor electrode, while the switching transistor of each memory cell comprises the drain region 59, the channel region 61, the source region 63, and the gate electrode 65.
Each memory cell of either one of the memory cell array structures as shown in FIGS. 2 and 3 has a capacitor and a switching transistor so three-dimensionally formed by utilizing a trench, particularly the side wall thereof, as to greatly decrease the area occupied by the memory cell as projected on the upper surface of a substrate. Therefore, the use of such a memory cell structure in the production of a memory cell array structure of DRAM type can attain a higher scale of integration than the use of a memory cell structure as shown in FIG. 1.
In the case of the conventional memory cell array structure as shown in FIG. 2, however, an anisotropic etching technique is employed to form gate electrodes on the inside and along the side walls of the second trench, resulting in a cell-to-cell variation in channel length, which is problematic in that the operational characteristics differ from switching transistor to switching transistor.
The conventional memory cell array structure as shown in FIG. 3 involves not only a problem as mentioned above that differences in the operational characteristics between switching transistors are caused by a cell-to-cell variation in channel length, but also problems that leaks of electric current are liable to occur between adjacent capacitors and that it is not easy to form electroconductive side portions connecting transistor portions with respective capacitor portions.
Further, in either one of the memory cell array structures as shown in FIGS. 2 and 3, the capacity is liable to differ from capacitor to capacitor because of cell-to-cell variations in the depth of trench and the depth of capacitor electrode embedded in a trench.

Method of making a memory cell array structure


A method of assembling a light source comprises the steps of inserting multiple lead wires of a light emitting element into an insertion hole formed in a circuit board from one side of the circuit board at once, striking tips of the multiple lead wires with corresponding multiple guides formed on a circumference of a pressing device serving as a jig from the other side of the circuit board, moving the pressing device toward the one side from the other side of the circuit board, and in a first stage guiding the multiple lead wires to corresponding terminals formed in an inner wall of the insertion hole of the circuit board, respectively.

1. Field of the Invention
This invention relates to a light source device, a method of assembling the light source device, an optical scanning device with the light source device, and an image forming apparatus with the optical scanning device, and in particular to a light source device having a light-emitting element and a circuit board, a method of assembling such a light source device, an optical scanning device provided with the light source device assembled by the method, and an image forming apparatus having the optical scanning device.
2. Description of the Background Art
In a light source device having a light-emitting element mounted on a circuit board, multiple lead wires of the light-emitting element are independently connected to multiple terminals provided on the circuit board, respectively, as described in Japanese Patent Application Publication Nos. 2006-72136 and 2005-70495 (JP-2006-72136-A and JP-2005-7045-A).
However, since the multiple lead wires are respectively guided and fixed (e.g., soldered) onto the corresponding terminals on the circuit board using a jig, such as a pair of tweezers, etc., when a conventional light source device is assembled, it was time consuming and workability is not good.

Light source device, method of assembling light source device, optical scanning device, and image forming apparatus


A colpotomy system includes an energy source and a uterine manipulator that is electrically coupled to the energy source. The uterine manipulator supports a colpotomy cup and extends to a conductive distal tip portion. The colpotomy cup includes a conductive surface. One or both of the conductive distal tip portion and the conductive surface of the colpotomy cup are configured to return monopolar energy to the energy source.

Colpotomy, one of the final steps in a laparoscopic hysterectomy, requires making a circular incision in vaginal tissue to separate the uterus from the vagina. This incision is typically performed with the aid of a uterine manipulator.
Uterine manipulators are conventionally used during laparoscopic hysterectomy procedures to mobilize and position the vagina and the cervix to facilitate separation and to enable removal of the uterus or other tissue specimens subsequent to performance of a colpotomy. Typically, uterine manipulators include a handle, a shaft extending distally from the handle, an inflatable balloon supported on the end of the shaft opposite the handle, and a cervical or colpotomy cup supported on the shaft proximally of the inflatable balloon. In use, the inflatable balloon is advanced through the vagina and cervix and is positioned within the uterus in a deflated position. Once positioned within the uterus, the inflatable balloon is inflated to secure the uterine manipulator within the uterus and the colpotomy cup is positioned about the cervix for effectuating the colpotomy.
To effectuate the colpotomy, the clinician is required to identify the in vivo location of the colpotomy cup and position a cutting tool, such as a surgical electrode instrument, so that it can be tracked around the circumference of the colpotomy cup. The insertion angle of the cutting tool, the small target area, and the lack of visual reference points often prevent clinicians from making a clean track and/or incision.

Colpotomy systems, devices, and methods with rotational cutting