An automated chemical synthesizer including plural reaction vessels, a plurality of liquid containers, at least one liquid dispenser, a liquid amount storage, a dispensing amount calculator, and a liquid shortage detector. The plurality of liquid containers are configured to contain liquid chemicals respectively. The at least one liquid dispenser is configured to dispense the liquid chemicals from the plurality of liquid containers to the plural reaction vessels according to a synthesizing protocol. The liquid amount storage is configured to memorize a present amount of each of the liquid chemicals in the plurality of liquid containers. The dispensing amount calculator is configured to calculate a dispensing amount of each of the liquid chemicals to be dispensed according to the synthesizing protocol. The liquid shortage detector is configured to detect shortages of the liquid chemicals in the plurality of liquid containers by comparing the present amount memorized in the liquid amount storage and the dispensing amount calculated by the dispensing amount calculator.

The present application claims priority under 35 U.S.C. xc2xa7 119 to Japanese Patent Application No. 11-27,321, filed Feb. 4, 1999, entitled xe2x80x9cAutomated Synthesizing Apparatus.xe2x80x9d The contents of that application are incorporated herein by reference in their entirety.
1. Field of the Invention
The present invention relates to an automated chemical synthesizer. Further, the present invention relates to a method for detecting a liquid shortage in the automated chemical synthesizer.
2. Description of the Background
Automated chemical synthesizers have been used for research in the fields of pharmaceutical, life science, chemistry and material science among others.
FIG. 12 shows a conventional automated chemical synthesizer. Referring to FIG. 12, the automated chemical synthesizer has a syringe 53 and a reaction block 51 which includes multiple reaction vessels 52 in which synthetic reactions take place. The syringe 53 dispenses liquid chemicals, i.e., solvents and reagents to each reaction vessel 52 according to a dispensing procedure of a synthesizing protocol. In the automated chemical synthesizer, an operator sets reagent and solvent containers next to the reaction block 51. The syringe 53 dispenses solvents and reagents from the reagent and solvent containers to each reaction vessel 52.
However, in this automated chemical synthesizer, shortages of the reagents or solvents in the containers may occur. An operator generally sets reagent and solvent containers which contain enough amount of reagents and solvents according to the synthesizing protocol. However, it is time-consuming to calculate the dispensing amounts with respect to all liquid chemicals and sometimes the operator may make mistakes.
If the shortages of the reagents or solvents occur, the automated chemical synthesizer does not recognize the shortages. Accordingly, the synthetic reactions may fail.
In order to detect shortages of the reagents or solvents by providing sensors, sensors and other hardware should be additionally provided. Accordingly, the automated chemical synthesizer becomes complicated.
According to one aspect of the invention, an automated chemical synthesizer includes plural reaction vessels, a plurality of containers, at least one liquid dispenser, a liquid amount storage, a dispensing amount calculator, and a liquid shortage detector. The plurality of containers are configured to contain liquid chemicals respectively. The at least one liquid dispenser is configured to dispense the liquid chemicals from the plurality of containers to the plural reaction vessels according to a synthesizing protocol. The liquid amount storage is configured to memorize a present amount of each of the liquid chemicals in the plurality of containers. The dispensing amount calculator is configured to calculate a dispensing amount of each of the liquid chemicals to be dispensed according to the synthesizing protocol. The liquid shortage detector is configured to detect shortages of the liquid chemicals in the plurality of containers by comparing the present amount memorized in the liquid amount storage and the dispensing amount calculated by the dispensing amount calculator.
According to another aspect of the invention, an automated chemical synthesizer includes plural reaction vessels, a plurality of liquid containers for containing liquid chemicals respectively, liquid dispensing means, liquid amount storage means, dispensing amount calculation means, and liquid shortage detecting means. The liquid dispensing means dispense the liquid chemicals from the plurality of liquid containers to said plural reaction vessels according to a synthesizing protocol. The liquid amount storage means memorize a present amount of each of the liquid chemicals in the plurality of liquid containers. The dispensing amount calculation means calculate a dispensing amount of each of the liquid chemicals to be dispensed according to the synthesizing protocol. The liquid shortage detecting means detect shortages of the liquid chemicals in the plurality of liquid containers by comparing the present amount memorized in the liquid amount storage means and the dispensing amount calculated by the dispensing amount calculation means.
Further, according to another aspect of the invention, a liquid shortage detecting system for an automated chemical synthesizer includes a liquid amount storage, a dispensing amount calculator, and a liquid shortage detector. The liquid amount storage is configured to memorize a present amount of each of liquid chemicals in a plurality of liquid containers. The dispensing amount calculator is configured to calculate a dispensing amount of each of the liquid chemicals to be dispensed according to the synthesizing protocol. The liquid shortage detector is configured to detect shortages of the liquid chemicals in the plurality of liquid containers by comparing the present amount memorized in the liquid amount storage and the dispensing amount calculated by the dispensing amount calculator.
Further, according to the other aspect of the invention, a method for detecting liquid shortages in an automated chemical synthesizer includes memorizing a present amount of each of liquid chemicals in a plurality of liquid containers. A dispensing amount of each of the liquid chemicals to be dispensed are calculated according to the synthesizing protocol. Shortages of the liquid chemicals in the plurality of liquid containers are detected by comparing the present amount memorized in the liquid amount storage and the dispensing amount calculated by the dispensing amount calculator.

Automated chemical synthesizer and method for detecting liquid shortages in the same


A retention device and system for securing a disc, such as a wheel cover, to a wheel rim is disclosed. A first embodiment of the retention device includes a fastening member with a turned upper lip that hooks over the wheel rim, an inturned flexible section that extends along the flange of the wheel, a flexible base portion snap-fits to the wheel and subjected to a pressing force that defeats the spring action created in a bend of the base portion which in turn locks the disc retention device to the wheel. An upturned lower flange of the lower arm fits into an end of the connecting member which is attached thereto by means of a retaining member. The retaining member has an upper bight portion that extends through the upper lip of the connecting member and a pair of side legs extending perpendicular to the plane of the upper bight portion. The connecting member has two inturned folds which face opposite each other at open ends and a top arcuate edge. The retaining member is fitted up into the folds and extends through the lip of the connecting member. The disc having a downturned edge fits over the arcuate top edge providing attachment to the connecting member. A screwdriver or other prying tool when placed through the whole accompanied by a force exerted along the tip of the object overcomes the spring action allowing separation of the disc from the wheel rim. A plurality of circumferentially spaced retention devices are used as a system to secure the disc to the wheel rim. Further embodiments and variations in the shape of the connecting member of the lower arm and the disc may have inside slots or outside slots forming connecting male and female releasable parts to readily remove and replace the discs.

There have been many efforts to develop fastening devices and systems providing for the attachment of a disc such as a wheel covering to a wheel. The prior art generally discloses a single-piece leaf spring type fastener that attaches to a wheel. An example of this device which is also referred to as a "spring clip" is described in U.S. Pat. No. 3,769,729 to Engler and U.S. Pat. No. 2,629,957 to Lyon. Both of these disclosures make use of the spring clip to secure a disc to a wheel rim, with both types differing primarily in geometrical configuration. A disadvantage of the devices of these disclosures is that the free end of the spring clip is not easily adaptable to connecting to a variety of forms of discs that may be used. The single geometrical shape of the free end can only attach to a geometrically compatible disc. Further, the disclosures of U.S. Pat. No. 3,769,729 and U.S. Pat. No. 2,629,957 require removal by a prying force making contact against the disc and spring clip fastener, which could create damage to the integrity of the disc.
Another technique for displaying wheel discs is found in Matthews U.S. Pat. No. 5,072,536. This technique is functional only for static displays and cannot readily be used for rotating wheels. In this technique, the disc is attached to the wheel rim by means of a clip which differs from the disc retention device of the present invention because the clip is only a hooking device and makes no use of a spring type force to retain the disc.

Snap-on retention device and system for wheel cover


A method of processing a substrate. In one embodiment, the invention can be a method of processing a substrate comprising: supporting the substrate in a horizontal orientation; rotating the substrate; providing a fluid dispensing apparatus adjacent a surface of the substrate, the fluid dispensing apparatus comprising a body having an outer surface and a first conduit terminating as a first hole in the outer surface of the body and a second conduit terminating as a second hole in the outer surface of the body, the first hole oriented at a non-normal angle relative to the substrate and offset a first radial distance from a rotational center-point of the substrate; and ejecting liquid out of the first hole into contact with the substrate at the rotational center-point and ejecting liquid out of the second hole into contact with the substrate at a second radial distance from the rotational center-point.

In the field of semiconductor manufacturing, it has been recognized since the beginning of the industry that maintaining the semiconductor wafers free of contaminants during the manufacturing process is a critical requirement to producing quality profitable wafers. As the size of the devices continue to become smaller, the number of semiconductor devices present on a single wafer continues to exponentially grow. As a result of the devices becoming more and more miniaturized, cleanliness requirements have also become increasingly important and stringent. When dealing with reduced size devices, the ratio of the size of a contaminant compared to the size of a device is greater, resulting in an increased likelihood that a contaminated device will not function properly. Thus, increasingly stringent cleanliness and PRE requirements are needed. As a result, improved semiconductor wafer processing techniques that reduce the amount and size of the contaminants present during wafer production are highly desired.
An example of a single-wafer cleaning system that utilizes megasonic energy is disclosed in U.S. Pat. No. 6,039,059 ("Bran"), issued Mar. 21, 2000. An example of a single-wafer cleaner and dryer is disclosed in U.S. Pat. No. 7,100,304 ("Lauerhaas et al."), issued Sep. 5, 2006. The entireties of Bran and Lauerhaas et al. are hereby incorporated by reference.
In single-wafer processing systems, such as the ones mentioned above, a semiconductor wafer is supported and rotated in a horizontal orientation. A desired processing chemical is then applied to one or both sides/surfaces of the wafer. Nozzles/dispensers are typically placed underneath the wafer and dispense fluid in an upward direction so as to apply the fluid on the bottom surface of the wafer. It is important that the level of contaminants and/or residues left on the surface of the wafer be minimized to the extent possible at all times.
While the dispensers serve the vital function of applying fluids to the surface of the wafer, they also present a problem in that fluid and contaminants will collect on the top surface of the dispenser and get re-deposited back on the wafer. Thereby re-contaminating the wafer and causing semiconductor device failure problems. Additionally, because the wafer spins during the application of fluid, turbulence is created between the bottom surface of the wafer and the top surface of the dispenser that may damage the wafer or may cause more contaminants to remain on the surface of the wafer.
Therefore, there is a need to provide an improved apparatus, system and method for processing substrates that prevents and/or minimizes the deposit of contaminants on the wafer.

Apparatus for ejecting fluid onto a substrate and system and method incorporating the same


A pressure relief tube or enclosure such as for an auger screw. In one embodiment, a pressure relief tube may comprise at least one hatch that is adapted to expand in response to force applied from within the tube. An example of the pressure relief tube may automatically adapt or adjust to potential problem material in the tube to allow for conveyance or clearance of the problem material. Another example of the pressure relief tube may be manually adapted or adjusted to facilitate conveyance or clearance of the problem material. Related systems and methods comprising a pressure relief tube are also provided.

Exemplary embodiments of the present invention relate generally to auger systems, which may also be known as extrusion or screw systems. Hereafter, such systems will be collectively referred to as auger systems. There are number of different types of auger systems. Examples of auger systems may include, but are not limited to, compactors, crushers, shredders, feeders, material handlers, bale breakers, briquetters, and autoclave sterilizers. Other applications of auger systems are also possible.
An example of an auger system may be comprised of a screw that is adapted to convey material through a tube or other type enclosure. In a typical auger system, bulk material is transferred into the auger system for processing. For example, the bulk material may be waste material or recycling, which may be input to the auger system in batch loads or as a continuous feed.
A problem arises when a portion of the bulk material is not suitable for processing by the auger system. For example, a component or components of the bulk material may too large or comprised of the wrong material to be processed by the auger system. This is a particular concern when processing a material such as trash or recycling, which may be more prone to be comprised of some random material that is unsuitable for processing in the auger system.
Certain types of auger systems may be more susceptible to this type of problem. For instance, some auger systems may be designed to crush or compress the material between the screw and the outer tube or enclosure through which the material is conveyed. In such systems, there may be a tight clearance between the screw and the outer tube or enclosure in order to achieve the desired compression or crushing of the material. However, the tight clearance may also lead to random undesired material becoming wedged or otherwise stuck or jammed between the screw and the outer tube or enclosure. At the least, this will limit the conveyance of the material or otherwise hinder the efficiency of the auger system. It could also damage or break the auger system. In fact, it could stop the auger system. The same or similar problems may also occur with other types of auger systems.
In order to clear the problem, the auger system will often have to be shut down in order to remove the unsuitable material. Removal of the problem may be difficult and may require some disassembly of the auger system. This downtime for maintenance further limits the efficiency of the auger system, as no material can be conveyed while the problem is removed.
In view of these shortcomings of the known art, there is a need for an improved auger system or component for clearing or preventing potential jams. There is also a need for an improved auger system or component that automatically adapts or adjusts to the potential problem material so that it may be conveyed through the auger system. A need also exists for an improved auger system or component that automatically adapts or adjusts so that the problem material may be cleared from the auger system. Another need exists for an auger system or component that may be manually adjusted to allow for conveyance of the problem material through the auger system or for clearance of the problem material. Related methods for solving the aforementioned problems are also needed.
An exemplary embodiment of the present invention may satisfy one or more of the aforementioned needs. One exemplary embodiment may be comprised of a pressure relief tube or enclosure (hereinafter collectively referred to as a pressure relief tube) such as for an auger screw. An example of the pressure relief tube may, for example, automatically adapt or adjust to potential problem material to allow for conveyance or clearance of the problem material. Another example of the pressure relief tube may be manually adapted or adjusted to facilitate conveyance or clearance of the problem material. Related systems and methods comprising a pressure relief tube are also provided.
In addition to the novel features and advantages mentioned above, other benefits will be readily apparent from the following descriptions of the drawings and exemplary embodiments.


A kit (10) includes a light source (12) and an optical system (14) equipped with a lens assembly (25) defining a magnification optical axis (X-X). A frame (16) is crossable by the light generated by the light source (12). The frame (16) is configured for supporting a sample holder (H), a portable electronic apparatus (S) equipped with an image acquisition device (C), and the optical system (14), which are interposable between the sample holder (H) and the image acquisition device (C). The optical system (14) is configured for being movable in a guided manner on the frame (16), to allow aligning the optical axis (X-X) with the image acquisition device (C). A carrying body (18) is configured for receiving in abutment the frame (16) and housing the light source (12) directing light towards the optical system (14) through the frame (16).

It is known to make microscopic observations through the use of kits or systems associable with image acquisition devices, in particular portable ones, e.g. smartphone cameras or other digital cameras.
In particular, the advantage of using smartphones as elements for collecting microscopic images lies in the exploitation of systems that, as a whole, are more easily transportable than standard microscopes and generally also less expensive, since much of the optics, electronics and software, is included in the smartphone. Thus, an attempt is made to reach a compromise in terms of optical performance, portability and overall cost of the equipment.
Several examples are known in the industry of system structures allowing the use of portable cameras or smartphones as microscopes.
Some of such examples consist of individual lenses suitably applied directly onto the camera; one example is described in patent application publication WO 2017/013553 A1.
Other examples also exist, which propose lens systems equipped with rigid supports making it necessary to position the sample in a predetermined manner relative to the image acquisition device, e.g. at a predefined working distance or on specific phone models, or that require dedicated support structures.
In particular, technical solutions are known which miniaturize and integrate the main elements of microscopes for their association with smartphones. This often implies limitations in terms of universality of use (they can only be adapted to specific phone models), or the use of rather bulky and complex components. As a consequence, such elements have to be carried in suitable cases, since when mounted aboard the phone they prevent the normal use of the device and may suffer damages. On the other hand, simpler systems suffer from performance limitations.

Kit for microscopic observation associable with an image acquisition device


A projector device is provided. The projector device includes a projector unit, an optical beam splitting module and a first image forming element. The projector unit forms a beam projecting image. The horizontal projection width of the beam projecting image is smaller than the vertical projection width of the beam projecting image. The optical beam splitting module projects one or multiple projection sub-images according to the beam projecting image. The projection sub-images are projected to the first image forming element to form one or multiple projection images. Thus, the projector device obtains multiple projection images from a single image source, and the placement of the image forming elements in the projector unit may be adjusted to obtain the projection images with the best image ratios and the best resolutions. The projector device may be suitable for a head up display.

When driving a vehicle, the driver needs to be aware of a variety of driver information when the vehicle is going at a high speed, so as to avoid accidents. Usually, the driver information is displayed on the dashboard of the vehicle. However, when the vehicle is going at a high speed, an accident may occurs because the driver needs to bow his/her head to check the driver information on the dashboard. Thus, many vehicles currently provide a head up display (HUD) mounted on the windscreen panel in the front of the vehicle to display the drive information, such as speed, gas consumption, navigation information, and around view, etc., so that the driver does not have to bow his/her head to see the important information for operating the vehicle and reduce the frequency of checking the dashboard, thereby preventing interruption of attention and loss control of situation awareness. By adopting the HUD technology for vehicles, driving security can be improved, and car accidents can be reduced. Thus, several advanced countries have been making efforts in the development of relevant fields.
When it comes to the current projection technology, the HUDs are categorized into "LED reflective" type and "LCD imaging" type. However, the two types of HUDs merely display the driver information with a single display screen, and is unable to provide a plurality of projection images having preferable aspect ratios and resolutions by using a single image source.

Industrial Technology Research Institute


A flat container may be produced by extruding a molten resin to form a parison, closing the bottom of the parison, preblowing the parison such that the inner surfaces do not contact together, drafting the parison in a molten state, expanding the parison with the outer edge of the parison extending beyond that of the cavity of a mold, pinching the expanded parison with the mold to fuse the outer edge portions together along the outer edge of the cavity, and forcing a pressurized fluid into the parison pinched by the mold so that the parison is shaped in close contact with the inside surfaces of the mold cavity.

The present invention relates to a method of producing a flat container that has a large wall thickness in the mouth and shoulder portions and a small wall thickness in the body and has a large area of flatness.
It is fairly difficult to produce containers, in particular flat ones, having a large wall thickness in the mouth and shoulder portions and, a small wall thickness in the body and none of the methods presently available are completely satisfactory. Such containers are currently produced by the following methods:
(1) a method using a flat parison in combination with a parison controller;
(2) a method using a lateral expander (Japanese Patent Public Disclosure No. 61-134224); and
(3) a sheet blowing technique.
These methods, however, have their own problems. The first method produces a flat mouth portion and incurs difficulty in providing a uniform wall-thickness distribution in the body. The second method involves difficulty in achieving a uniform wall-thickness distribution in the body. The third method presents difficulty in attaining a uniform wall-thickness distribution in the mouth portion.

Method of blow molding a flat container having portions with greatly varying wall thickness


A computer executable system and method analyzes a circuit design to extract a small set of signals for value collection using an emulator system. The collected signals are for specific purpose checkers such as assertions or interactive testbenches that are hard to emulate. A synthesizable monitor block is generated and added to the emulation environment to collect the signal value changes during emulation. The collected values are then used in localized logic simulation to perform the tasks that the original checkers intent to accomplish. This system leverages fast emulation speed and flexible logic simulation capabilities to perform the intended checker tasks much faster than using logic simulation alone.

Logic simulation is one of the most commonly used method for verifying circuit designs. It produces circuit signal values based on the current circuit state and inputs. More specifically, logic simulation takes a circuit design and the given input patterns to calculate values that will be produced by the design code. For example, logic simulation for an AND gate with inputs 0 and 1 will produce 0 on its output. Simulating the same gate with inputs 1 and 1 will produce 1 on its output.
Values produced by logic simulation can then be used to check whether the circuit behaves according to the specification. This is typically done using checkers to verify the correctness of the design. Checkers sample circuit signal values and then determine if the values are correct. Two common types of checkers are assertions and reactive testbenches. An assertion encodes logic relationships among signals using predefined logic rules. Testbenches are typically written using behavior code. Logic simulation is flexible and can handle various types of checkers like assertions and behavior testbench that can be reactive. However, for large designs logic simulation can be exceedingly slow.
Because logic simulation can take considerable time to perform for large designs, emulation has been designed to address this issue. Emulation uses FPGAs to implement the design in hardware, and it can produce signal values based on inputs and design states orders of magnitude faster than logic simulation. However, signal value visibility inside the emulator system is typically limited, and only the primary outputs of the design can be directly observed.
Checkers used in a design, such as assertions, typically only need access to a small number of circuit signals. Even though only a small number of signals is needed, generating those signals using logic simulation still requires simulating most if not the whole design, which is slow. Emulation can quickly generate values for those signals. However, extracting those values from emulation and then use them for the checkers is either difficult or time consuming.
To address this issue, some checkers may be synthesized and emulated with the rest of the design. However, in practice only a small number of checkers can be synthesized, and adding them to emulation impacts performance adversely. As a result, those checkers are typically not used in emulation environments, which greatly reduces the chance to find bugs using emulation and hurts final design quality.
Another way to address this issue is to obtain internal signal values in an emulated design and use those values on the checkers. One way to obtain internal signal values is to stop functional clocks and use scan chains to scan out flipflop values inside the design. This method can obtain most flipflop values without additional hardware added to the emulator. However, it can be exceedingly slow due to the large number of cycles needed to scan values out.
Dedicated hardware for obtaining emulation values can be used instead of scan chains to improve value collection speed. For example, one solution adds channels to monitor flipflop values and send the signals out to a logic analyzer. Such special hardware can provide better performance than using scan chain. However, dedicated hardware increases cost of the emulation system. Additionally, how to efficiently and easily replay the obtained logic values on the checkers remain a big challenge.

System and method for localized logic simulation replay using emulated values


A method is provided for attaching a hollow tubular member to a cast member. The cast member has a hollow socket cavity. A body of uncured adhesive is positioned in either the hollow socket of the cast member or the hollow interior of the hollow tubular member. The hollow tubular member is inserted in the hollow cavity. The adhesive is forced to flow into the space between the outside of the tubular member and the socket of the cast member, and the adhesive is then cured.

It is well known that automobile bodies and chassis can be constructed of tubular members that are connected together at cast nodes that have sockets for receiving the ends of the tubular members. The prior art has proposed various arrangements for attaching the tubular members within the sockets, such as welding, mechanical fasteners, adhesives, etc.
In the case of adhesive attachments, it is known to apply the adhesive to the outside of the tubular member and then insert the tubular member into the socket. It is also known to apply the adhesive to the inside side wall of the socket and then insert the tubular member into the socket. In either case, application of the adhesive must be carefully controlled and the insertion of the tubular member must be carefully centered in the socket in order to achieve uniform and consistent thickness and length of the adhesive bond.
It would be desirable to have an improved method for adhesive bonding a tubular member in the socket of a cast joint, including greater ease in applying the adhesive, improved centering of the tubular member, and assured uniform and consistent thickness and length of the adhesive bond.

Method for adhesive bonding of a tubular member to a casting


An engine including an exhaust bypass valve and an intake bypass valve. The exhaust bypass valve is disposed in an exhaust bypass channel connecting an outlet of an exhaust manifold and an exhaust outlet of a turbocharger to each other. The intake bypass valve is disposed in an intake bypass channel connecting an inlet of an intake manifold and an inlet of the turbocharger. An intake pressure sensor detects a pressure of the intake manifold. If an instruction value indicating an upper limit or a lower limit of the valve opening degree of the intake bypass valve is continuously output for a predetermined time or more, an engine control device determines that an abnormality occurs in at least one of the exhaust bypass valve and the intake bypass valve.

In a known engine, a bypass channel of a turbocharger is provided with a valve for adjusting the air volume. Patent Literatures 1 and 2 (PTLs 1 and 2) disclose engines of this type.
The engine of PTL 1 includes an intake manifold, an exhaust manifold, a main fuel injection valve that injects liquid fuel to the cylinder for combustion, a gas injector that mixes gaseous fuel with air supplied from the intake manifold, a turbocharger that compresses air, and an intercooler that cools the compressed air compressed in the turbocharger and supplies the cooled compressed air to the intake manifold. The engine of PTL 1 is configured such that a main throttle valve is provided at the connection between a turbocharger outlet and an intercooler inlet, and an exhaust bypass vale is disposed in an exhaust bypass channel connecting an exhaust manifold outlet and a turbocharger outlet to each other. This configuration of PTL 1 is intended to control the air volume responsively with respect to a load variation when the engine is operated in a gas mode.
The engine of PTL 2 includes a main turbocharger, a subturbocharger, an intake switching valve that opens and closes an intake passage disposed downstream of a compressor of the subturbocharger, and an exhaust switching valve that opens and closes an exhaust passage disposed downstream or upstream of a turbine of the subturbocharger. This engine includes a control device. The control device is configured as follows. The control device actuates only the main turbocharger by closing both the intake switching valve and the exhaust switching valve in a low-speed range, and actuates both the main turbocharger and the subturbocharger by opening both the intake switching valve and the exhaust switching valve in a high-speed range. When the low-speed range shifts to the high-speed range, the control device controls an exhaust bypass valve disposed downstream or upstream of the subturbocharger such that the exhaust bypass valve is open to a small degree and controls an intake bypass valve disposed in an intake bypass passage bypassing a compressor of the subturbocharger such that the intake bypass valve is closed before opening of the exhaust switching valve to thereby increase a run-up revolution speed of the subturbocharger. The engine of PTL 2 includes a first intake temperature sensor disposed at a compressor inlet of the subturbocharger and a second intake temperature sensor disposed at a compressor outlet of the subturbocharger and the intake switching valve. The engine includes a failure determination means for causing a display means to display that a failure of the intake bypass valve occurs at the closed valve side if the intake temperature value from the first intake temperature sensor is a predetermined first set value or more while the exhaust bypass valve is controlled to open to a small degree or if the intake temperature value from the second intake temperature sensor is a predetermined second set value or more while the exhaust bypass valve is controlled to open to a small degree. When a failure of the intake bypass valve occurs at the closed side, this configuration of PTL 2 enables early detection of this failure and issues an alarm of this failure to a driver of the vehicle.


In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.

The present invention relates to technology for increasing the speed of operation of a semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal. More particularly, the present invention relates to technology effectively used for a semiconductor integrated circuit device that has storage circuit blocks such as DRAM and logic circuit blocks on one semiconductor integrated circuit chip and is configured so that a data transfer within the chip is performed synchronously with a clock signal.
In a conventional logic LSI (large-scale semiconductor integrated circuit) in which a storage circuit and logic circuits are formed on a one semiconductor chip, generally a data transfer within the chip is often performed synchronously with a clock signal. For such LSI, when data is transferred from one function circuit to another, inputted data is properly processed before being stored in an internal storage circuit, or data read from the storage circuit is properly processed before being outputted to the outside of the chip, a circuit to receive the data is configured to latch the data synchronously with the rising edge or falling edge of a clock signal (hereinafter referred to simply as a clock). For this reason, it has been common that time required for a data transfer is an integral multiple of the cycle of the clock.
Data propagation delay time occurring during use of circuits such as function circuits may, in some cases, be shorter than one cycle of clock, or in other cases, be a little longer than one cycle of clock, depending on the characteristics of circuits concerned, or the distance of data transfer. Even in such cases, in conventional semiconductor integrated circuit devices, data receive has been performed by latching data on the rising edge or falling edge of a clock whose phase matches that of an internal clock. As a result, time required for data transfer or data transmission is an integer multiple of one cycle of clock, and data has been transferred about one cycle later than actual delay.
If all internal timing signals are adjusted at an optimum timing according to data transfer delay within the chip, the timing of output signals may not match the phase of clock. If such signals are outputted to the outside of the chip, other LSIs that receive the signals and operate synchronously with an external clock could not correctly get the signals. Accordingly, semiconductor integrated circuit devices operating synchronously with a clock must synchronize with the clock at an input end and output end of signal.
Moreover, in the design and development of LSI for which high speed operation is demanded, the LSI is designed so that the margins of setup time and hold time for a clock are minimized to increase its operation speed. However, if the margins are thus minimized, a slight timing lag occurs in an internal clock due to change of element characteristics and parasitic capacity caused by variations in processes, and the slight timing lag of the internal clock may cause circuits to malfunction. In such a case, the manufacturing yield of a semiconductor integrated circuit decreases or its design must be changed. Accordingly, it is desirable that the LSI chip is internally provided with a mechanism by which clock timing can be adjusted at a final stage of process.
As a prior art related to the present invention, according to the invention disclosed in Japanese Published Unexamined Patent Application No. Hei 6(1994)-52676, in a semiconductor integrated circuit device including a storage circuit, optimum setup time and write pulse width are adjusted using a fuse circuit to speed up processing. However, the prior invention, which relates to technology for adjusting signal timing within RAM used as a storage circuit, makes no disclosure of adjusting transmission timing of signals between the RAM and logic circuits comprised of gate arrays and the like on the periphery of the RAM by changing a clock delay. In the prior patent application, although a fuse circuit is used to adjust timing, no disclosure is made of a method of forming the fuse.
An object of the present invention is to reduce total signal propagation delay time from signal input to output and speed up processing in a semiconductor integrated circuit device that includes circuit blocks such as storage circuits and operates synchronously with an external clock.
Another object of the present invention is to provide a semiconductor integrated circuit device that becomes fewer in the number of design changes and the number of mask modifications, is greatly reduced in development period, and is increased in yield.
Another object of the present invention is to provide a semiconductor integrated circuit device which allows timing to be adjusted without using much time for process changes and clock timing adjustment, and causes no increase in costs.
The above described objects and other objects, and novel characteristics of the present invention will become apparent from the description of this specification and the accompanying drawings.
Of inventions disclosed in the present patent application, typical ones are outlined below.
In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks (131, 141, 132, and 142) that receive input signals in response to a first timing signal (xcfx861) based on a clock signal (CLK), and a second circuit block (110) that forms output signals in response to a second timing signal (xcfx862) based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.
According to the above described means, in any portion of the second circuit block in which signal transmission time is not an integral multiple of the cycle of clock, operation is performed based on a timing signal generated to conform to the signal transmission time, whereby total delay time from signal input to output can be reduced and the speed of operation can be increased.
Preferably, time from the acceptance of an input signal in the first circuit blocks to the output of a signal formed in the second circuit block is set to an integral multiple of the cycle of the clock signal. In other words, in a semiconductor integrated circuit device which has a signal input point, a signal output point, and plural circuit blocks provided in series between the signal input point and the signal output point and in which the timings of a signal input operation from the signal input point, a signal output operation at the signal output point, and a signal transmission operation among the plural circuit blocks are respectively controlled by timing signals, when the clock signal cycle is T1, the total of signal response periods of individual circuit blocks of the plural circuit blocks is T2, and the ratio T2/T1 between T1 and T2 is n+xcex1 (n is an integer and xcex1 is a positive number equal to or less than 1), a signal response period from the signal input point to the signal output point is set to n+1 times the clock signal cycle T1. This facilitates synchronization with other semiconductor integrated circuit devices to receive output signals from a semiconductor integrated circuit device to which the present invention is applied, and facilitates the design of a board system and the like.
Moreover, preferably, a timing signal forming circuit is provided which forms the first timing signal and the second timing signal, based on the clock signal, and the timing signal forming circuit has a program element and includes a delay circuit for adjusting the time difference between the first timing signal and the second timing signal by the program element. Thereby, even after the semiconductor integrated circuit device has been manufactured, internal timings can be adjusted, a large margin can be provided for the signal transmission system, and product yield can be increased. The above described program element, which can be formed in various forms, is preferably comprised of fuse devices in terms of circuit occupation area.
In the case where at least one of the above described circuit blocks has a circuit operation setting element and the setting of its circuit operations is changeable depending on the circuit operation setting element, the program element in the delay circuit and the circuit operation setting element in the first circuit blocks are configured with devices having the same configuration as each other. Thereby, a semiconductor integrated circuit device can be obtained which includes a delay circuit capable of adjusting timing without any change of processes.
In the case where the second circuit block is comprised of a random access memory having a defect relieving circuit, the program element in the delay circuit and a setting element for holding defect relief information in the defect relieving circuit in the second circuit block are configured with devices having the same configuration as each other. Thereby, in a semiconductor integrated circuit device including a memory having a redundant circuit, a delay circuit capable of adjusting internal timing can be mounted on an identical chip without any change of processes.
The program element in the delay circuit and the setting element for holding defect relief information in the defect relieving circuit in the second circuit block are provided adjacently to each other. Thereby, program processing such as disconnection by laser irradiation or the like can be performed easily and quickly.
In this case, the program element in the delay circuit and the setting element for holding defect relief information in the defect relieving circuit are nearly linearly juxtaposed. Thereby, program processing can be performed more efficiently.
According to the present invention, in a semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the plural circuit blocks include a first circuit block and a second circuit block that receive input signals in response to a first timing signal based on the clock signal, and a third circuit block that forms output signals in response to a second timing signal based on the clock signal; in a signal transmission system, the third circuit block is provided between the first circuit block and the second circuit block; and a time difference between the first timing signal and the second timing signal is set to a period of a non-integral multiple of the cycle of the clock signal.
According to the above described means, in any portion of the third circuit block in which signal transmission time is not an integral multiple of the cycle of clock, operation is performed based on a timing signal generated to conform to the signal transmission time, whereby total delay time from signal input to output can be reduced and the speed of operation can be increased. Moreover, signals can be outputted synchronously with the clock signal from the second block, facilitating synchronization with other semiconductor integrated circuit devices to receive output signals from a semiconductor integrated circuit device to which the present invention is applied, and easing the design of a board system and the like.
The third circuit block includes a local timing signal generating circuit that generates a third timing signal within the block, based on the second timing signal, and a time difference between the second timing signal and the third timing signal may be a non-integral multiple of the cycle of the clock signal. Since the constraint that a time difference is an integral multiple of the cycle of clock signal is eliminated, operation is performed according to timing reflecting actual delay time, whereby signals can be transmitted at high speed.
The local timing signal forming circuit has a program element and includes a delay circuit for adjusting the time difference between the second timing signal and the third timing signal by the program element. Thereby, even after the semiconductor integrated circuit device has been manufactured, internal timings can be adjusted, a large margin can be provided for a signal transmission system, and product yield can be increased.
The first circuit block and the second circuit block each include a latch circuit that gets input signals to the respective circuit blocks, based on the first timing signal, and the third circuit block includes a latch circuit that gets input signals to the third circuit block, based on the second timing signal. By providing a latch circuit at an input side of each circuit block, synchronization can be established in the signal transmission system by a simple circuit.
In the signal transmission system consisting of the first circuit block, the third circuit block, and the second circuit block coupled in series for signal transmission, one or two or more fourth circuit blocks may be provided in parallel with the third circuit block. Thereby, system functions within the chip can be made advanced, and even if such advanced functions have been achieved, total delay time from signal input to output can be reduced and the speed of operation can be increased.
In the case where the third circuit block and the fourth circuit block have the same circuit configuration, a signal selecting means for selectively transmitting one of output signals corresponding to the circuit blocks is provided in the second circuit block. Thereby, a semiconductor integrated circuit device can be easily achieved in which plural memory circuits such as RAM are mounted.
In the case where a timing signal forming circuit is which forms the first timing signal and the second timing signal, based on the clock signal, the timing signal forming circuit has a program element and includes a delay circuit for adjusting the time difference between the first timing signal and the second timing signal by the program element. Thereby, even after the semiconductor integrated circuit device has been manufactured, internal timings can be adjusted, a large margin can be provided for the signal transmission system, and product yield can be increased.
There are further provided two external terminals through which the clock signal is inputted, and a clock buffer circuit which receives a differential clock signal inputted to the two external terminals and generates a single-phase clock signal. Thereby, timing can be decided at cross points of positive-phase signal and negative-phase signal of differential clock signals, so that clock skew can be minimized and a highly reliable semiconductor integrated circuit device can be obtained.


An alloy for building up a valve according to the present invention comprises: with respect to the total weight of the alloy taken as 100%, 30 to 40% by weight of chromium; 15 to 31% by weight of nickel; 7 to 20% by weight of molybdenum; 0.7 to 2.2% by weight of carbon; 1.5% or less by weight of silicon; and balance of iron and inevitable impurities. The alloy is superior in hardness at high temperatures, PbO resistance and PbO+PbSO.sub.4 resistance. In addition, the alloy is suitable for powder buildup welding.

1. Field of the Invention
This invention relates to an alloy for building up valves of internal combustion engines, especially for building up exhaust valves of automobile engines.
2. Description of the Related Art
Many conventional valves of internal combustion engines have been used after buildup welding the portions thereof to be abraded with various surface-hardening alloys.
A cobalt-base alloy, consisting mainly of cobalt-chromium and small amounts of tungsten, molybdenum, carbon and so on, is often employed as a buildup alloy for exhaust valves of automobile engines since the cobalt-base alloy is superior in hardness at high temperatures and lead oxide corrosion resistance (hereinafter referred to PbO resistance). However, the cobalt-base alloy contains a large amount of expensive cobalt, and is a highly expensive material for buildup welding. Therefore a less expensive material which exhibits no less performance than that of the cobalt-base alloy has been required for buildup welding the exhaust valves of the automobile engines.
Japanese Unexamined Pat. Publication (KOKAI) No. 153872/1984 discloses an iron-chromium-nickel alloy for engine valves developed for solving the above mentioned problem. The iron-chromium-nickel alloy is employed for forming portions of the engine valve which are required to withstand abrasion by buildup by casting or by building up with a welding rod. To the iron-chromium-nickel alloy is added tungsten and titanium for controlling and refining the growth of the crystal grains of the base metal. To the iron-chromium-nickel there is further added manganese for deoxidizing and desulfurizing. The iron-chromium-nickel alloy furthermore contains aluminum for improving the PbO resistance. However, the inventors of the present invention have investigated and discovered that the iron-chromium-nickel alloy is inferior in its resistance to PbO. Further, instead of the buildup with the welding rod, a method for buildup with alloy powder has been drawing attention because of its operability, buildup efficiency and ease of automation. However, when the iron-chromium-nickel alloy is employed for the method for the buildup with alloy powder, the following drawbacks arise: i.e., a poor powder deposition rate, an uneven bead configuration, pin holes and plow holes in the buildup layer and oxide intrusions into the buildup layer. The above drawbacks are believed to be resulting from the titanium added for controlling and refining the growth of the crystal grains of the base metal and the aluminum for improving the PbO resistance.
Further, Japanese Unexamined Patent Publication (KOKAI) No. 179891/1987 discloses a nickel-chromium-molybdenum alloy for buildup, although it is not so cheap as the abovementioned iron-chromium-nickel alloy. The nickel-chromium-molybdenum alloy is superior in hardness at high temperatures and the PbO resistance, and the buildup method with alloy powder can be conducted favorably. However, the inventors have investigated and found that the corrosion of the exhaust valves is caused not only by lead oxide but also by lead oxide containing lead sulfate. The inventors have discovered that the nickel-chromium-molybdenum alloy is inferior in corrosion resistance against lead oxide containing lead sulfate (hereinafter referred to as PbO+PbSO.sub.4 resistance).


A pitching system will pitch either softballs or baseballs to a single station. At least one of the pitching machines in the system can have variable speed pitches. As the speed of the pitches changes, the angles at which the balls are thrown will be varied. In that manner, the strike zone at the batting station can be maintained. The pitching system includes a pitching machine with rotatable upper and lower wheels. Balls are fed to and thrown from these wheels. The speed at which the balls are thrown by the wheels can be adjusted. When the speed is adjusted, a control will actuate a tilting device for adjusting the angle at which the balls are thrown. This angle is decreased as the speed of the thrown balls is increased.

1. Field of the Invention
The instant invention relates to a system and method for pitching a ball. At least one pitching machine can be provided in the system. This pitching machine has rotatable wheels which will sequentially receive and throw balls. The speed at which the balls are thrown can be adjusted. When the speed is adjusted, a control means will change the angle at which the balls are thrown. Therefore, as the speed at which the balls are thrown is increased, the angle at which the balls are thrown is decreased.
2. Description of the Background Art
Various pitching devices are known. For example, dual wheel systems which will throw baseballs or softballs are known. In such systems, a batting station is normally designated for one speed of balls. This therefore limits the number of players which can utilize that station. If the speed at which the balls are to be received at that station is changed, this is normally a complicated procedure which must be performed by the owner or attendant.
Also, the existing pitching machines can not automatically accommodate different heights of users. Players with different heights have strike zones at different heights. In conventional systems, balls cross the strike zone at a particular height. If this zone is to change, the height at which balls are pitched is manually changed. If this adjustment is made, there is no provision to automatically return the balls to a different strike zone after completion of a first cycle. Therefore, it may be possible to accommodate a first player but the next different sized player will not automatically be accommodated.


A multimode optical fiber includes a central core having a graded-index profile with a delta value of about 1.9 percent or greater. The graded-index core profile has at least two different alpha parameter values along the core radius, namely a first value in an inner zone of the central core and a second value in an outer zone of the central core. The second alpha parameter value is typically less than the first alpha parameter value. The graded-index core profile and its first derivative are typically substantially continuous over the width of the graded-index core.

An optical fiber (i.e., a glass fiber typically surrounded by one or more coating layers) conventionally includes an optical fiber core, which transmits and/or amplifies an optical signal, and an optical cladding, which confines the optical signal within the core. Accordingly, the refractive index of the core nc is typically greater than the refractive index of the optical cladding ng (i.e., nc>ng).
For short-distance applications and for local networks, multimode optical fibers are frequently used. The core of a multimode optical fiber typically has a diameter of between about 50 microns and 62.5 microns, whereas the core of a single-mode optical fiber typically has a diameter of between about 6 microns and 9 microns. In a multimode optical fiber, for a given wavelength, several optical modes are propagated simultaneously along the optical fiber, conveying the same information. The bandwidth is directly linked to the group velocity of the optical modes propagating in the multimode core of the optical fiber. Thus, to guarantee a broad bandwidth, it is desirable for the group velocities of all the modes at a given wavelength to be identical. Stated differently, the intermodal dispersion should be zero, or at least minimized, for a given wavelength.
Multimode optical fibers having a diameter of 50 microns have been the subject of international standardization under the ITU-T G.651.1 recommendations, which, in particular, define criteria (e.g., bandwidth, numerical aperture, and core diameter) that relate to the requirements for optical fiber compatibility. The ITU-T G.651.1 standard (July 2007) is hereby incorporated by reference in its entirety.
For optical fibers, the refractive index profile is generally classified according to the graphical appearance of the function that associates the refractive index with the radius of the optical fiber. Conventionally, the distance r to the center of the optical fiber is shown on the x-axis, and the difference between the refractive index (at radius r) and the refractive index of the optical fiber's outer cladding (e.g., an outer optical cladding) is shown on the y-axis. The refractive index profile is referred to as a "step" profile, "trapezoidal" profile, "triangular" profile, or "parabolic" profile (e.g., a graded profile or an "alpha" profile) for graphs having the respective shapes of a step, a trapezoid, a triangle, or a parabola. These curves are generally representative of the optical fiber's theoretical or set profile. Constraints in the manufacture of the optical fiber, however, may result in a slightly different actual profile.
For the same propagation medium (i.e., in a step-index multimode optical fiber), the different modes have different group delay times. This difference in group delay times results in a time lag between the pulses propagating along different radial offsets of the optical fiber. This delay causes a broadening of the resulting light pulse. Broadening of the light pulse increases the risk of the pulse being superimposed onto a trailing pulse and reduces the bandwidth (i.e., data rate) supported by the optical fiber.
To reduce intermodal dispersion, the multimode optical fibers used in telecommunications generally have a core with a refractive index that decreases progressively from the center of the optical fiber to its interface with a cladding (i.e., an "alpha" core profile). Such an optical fiber has been used for a number of years, and its characteristics have been described in "Multimode Theory of Graded-Core Fibers" by D. Gloge et al., Bell system Technical Journal 1973, pp. 1563-1578, and summarized in "Comprehensive Theory of Dispersion in Graded-Index Optical Fibers" by G. Yabre, Journal of Lightwave Technology, February 2000, Vol. 18, No. 2, pp. 166-177. Each of the above-referenced articles is hereby incorporated by reference in its entirety.
A graded-index profile (i.e., an alpha-index profile) can be described by a relationship between the refractive index value n and the distance r from the center of the optical fiber according to the following equation:
                    n        =                              n            0                                                        1              -                              2                                                                                Δ                                                              (                                              r                        a                                            )                                                        α                                                                                (                  Equation                                                              1                )
wherein,
α≧1, and α is a non-dimensional parameter that is indicative of the shape of the index profile;
n0 is the maximum refractive index of the optical fiber's core;
a is the radius of the optical fiber's core; and
                    Δ        =                              (                                          n                0                2                            -                              n                cl                2                                      )                                2                                      n              0              2                                                          (                  Equation                                                              2                )
where nc1 is the minimum refractive index of the multimode core, which may correspond to the refractive index of the outer cladding (most often made of silica).
A multimode optical fiber with a graded index (i.e., an alpha profile) therefore has a core profile with a rotational symmetry such that along any radial direction of the optical fiber the value of the refractive index decreases continuously from the center of the optical fiber's core to its periphery. When a multimode light signal propagates in such a graded-index core, the different optical modes experience differing propagation mediums (i.e., because of the varying refractive indices). This, in turn, affects the propagation speed of each optical mode differently. Thus, by adjusting the value of the parameter α, it is possible to obtain a group delay time that is virtually equal for all of the modes. Stated differently, the refractive index profile can be modified to reduce or even eliminate intermodal dispersion.
Typically, a multimode optical fiber should have the largest possible bandwidth to perform well in a high-bandwidth application. The TIA-492AAAC-A standard, which is hereby incorporated by reference in its entirety, specifies the performance requirements for 50-micron-diameter multimode optical fibers used over long distances in Ethernet high-bandwidth transmission network applications. In particular, the OM3 and OM4 standards, each of which is hereby incorporated by reference in its entirety, have been adopted to meet the demands of high-bandwidth applications (i.e., a data rate higher than 1 GbE) over long distances (i.e., distances greater than 300 meters). The OM3 standard requires, at a wavelength of 850 nanometers, an effective modal bandwidth (EMB) of at least 2,000 MHz·km. The OM3 standard assures error-free transmissions for a data rate of 10 Gb/s (10 GbE) up to a distance of 300 meters. The OM4 standard requires, at a wavelength of 850 nanometers, an EMB of at least 4,700 MHz·km to obtain error-free transmissions for a data rate of 10 Gb/s (10 GbE) up to a distance of 550 meters.
For a given wavelength, the bandwidth of an optical fiber may be characterized in several different ways. In particular, the characterization of bandwidth depends on the source used with the optical fiber. On the one hand, determination of the overfilled launch bandwidth OFL-BW assumes the use of a light source exhibiting uniform excitation over the entire radial surface of the optical fiber (e.g., using a laser diode or light emitting diode (LED)). On the other hand, the effective modal bandwidth EMB is more appropriate for determining the optical fiber bandwidth in use with VCSEL sources (Vertical Cavity Surface Emitting Laser).
The effective modal bandwidth can be calculated by measuring the delay caused by modal dispersion (i.e., the dispersion mode delay, or DMD). An exemplary method of measuring DMD and calculating the effective modal bandwidth can be found in the FOTP-220 standard and the IEC 60793-1-49 standard, each of which is hereby incorporated by reference in its entirety. To carry out a DMD measurement, care is generally taken to use a source or an optical fiber length such that the chromatic dispersion is actually negligible, because the purpose is to characterize the modal dispersion of the fiber. The effective modal bandwidth corresponds to the smallest bandwidth for all the EMBs of Source-Optical fiber pairs when the chromatic dispersion is disregarded for all standardized sources in 10 GbE applications.
A DMD graph is obtained by successively injecting into the multimode optical fiber a light pulse having a given wavelength λ0 with a radial offset between each successive pulse. The delay of each pulse is then measured after a given length of fiber L. Multiple identical light pulses (i.e., light pulses having the same amplitude, wavelength, and frequency) are injected with different radial offsets with respect to the center of the multimode optical fiber's core. From these measurements a map 23 of the DMD, or "DMD graph," may be generated depicting the pulse delay (e.g., in nanoseconds) as a function of radial offset (e.g., in microns).
When the parameter a is set to an optimum value αoptimum, there is virtually no shift in the light pulse delay for a given wavelength λ0 regardless of the radius r along which the pulse propagates. Thus, the intermodal dispersion is low and the effective modal bandwidth is significant. Commonly-assigned European Publication No. EP 2144096, which is hereby incorporated by reference in its entirety, describes an exemplary DMD graphical representation and calculated EMB.
U.S. Patent Publication No. 2010/0154478, which is hereby incorporated by reference in its entirety, discloses graded-index profiles in which the core follows a modified power law equation. The inner part follows the standard Equation 1, while the refractive index profile deviates from the power law equation with smaller refractive index. Such refractive index profiles lead to DMD degradations and limited effective modal bandwidth.
U.S. Pat. No. 7,315,677, which is hereby incorporated by reference in its entirety, discloses "double alpha profiles" based on co-doping. Each dopant profile exhibits its own alpha. DMD performances are not disclosed. Based on calculations, the disclosed optical fibers have relatively small numerical apertures of about 0.2 or less.
International Publication No. WO 00/50936, which is hereby incorporated by reference in its entirety, discloses graded-index profiles in which the core's refractive index profile follows a modified power law equation providing a DMD plot at 1300 nanometers with two different slopes over two different regions of the core. This publication, however, fails to disclose the exponent controlling its power law equation or a DMD plot at 850 nanometers.
Japanese Publication No. 2007-272239, which is hereby incorporated by reference in its entirety, is related to the compensation of the deleterious effect of the tail/skirt at the core cladding interface inherent to VAD process. The publication, however, fails to disclose a central core maximum refractive index and is, therefore, likely a standard central core leading to a standard numerical aperture.
Japanese Publication No. 2001-235648, which is hereby incorporated by reference in its entirety, is related to the compensation of the deleterious effect of the tail/skirt at the core cladding interface inherent to VAD process. The publication, however, fails to disclose a central core maximum refractive index and is, therefore, likely a standard central core leading to a standard numerical aperture.
R. E. Freund, "High-Speed Transmission in Multimode Optical fibers," JLT, Vol. 28, No. 4, February 2010, which is hereby incorporated by reference in its entirety, discloses a double-alpha profile. However, this profile was set up to simulate manufacturing defects in the optical fiber. The continuity of the first derivative of this profile is not ensured and leads to poor DMD performances.
Graded-index multimode optical fibers are typically dedicated to high-speed data communications. They efficiently utilize low-cost high-speed sources based on VCSEL technology. Because these sources are divergent, multimode optical fibers are typically designed to provide a large numerical aperture—larger numerical apertures are generally better. Typical 50-micron-core multimode optical fibers dedicated to high-speed transmissions exhibit numerical apertures around 0.200.
Emerging optical-fiber applications like supercomputer or consumer electronic devices require additional flexibility that can be provided by an even larger numerical aperture. That said, conventionally a large numerical aperture generally leads to modal bandwidth degradation. Therefore, a need exists for a multimode optical fiber with high modal bandwidth and large numerical aperture.
Moreover, depending on applications, optical fibers with larger core size than a standard 50-micron core (e.g., an 80-micron core) may be used. Therefore, a need also exists for a multimode optical fiber having a large numerical aperture with high modal bandwidth regardless of core size, particular when the core size is increased beyond the standard 50-micron core.


A motor drive system capable of suppressing heat generation during a low speed operation may include: an inverter including a plurality of switching elements to convert direct current power to alternating current power having a plurality of phases; a motor driven with the alternating current power converted in the inverter; and a controller determines an operating point of the motor on the basis of a torque command of the motor and generates a d-axis current command and a q-axis current command corresponding to the operating point. In particular, when each of the switching elements is overheated, the controller changes the d-axis current command and the q-axis current command by changing the operating point to a different operating point corresponding to a torque of the same magnitude as the torque command.

The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
Generally, eco-friendly vehicles such as electric vehicles, hybrid vehicles, plug-in hybrid vehicles and hydrogen battery vehicles are vehicles powered by electric power motors. In particular, in vehicles such as electric vehicles and the hydrogen battery vehicles that use a drive motor as a main power source, only a reduction gear is often employed in place of a multi-stage transmission, and a torque converter is mostly omitted in order to increase torque transmission efficiency. As for such a vehicle, the speed of the drive motor and the speed of the vehicle are synchronized at a predetermined reduction ratio. Accordingly, when the speed of the vehicle is at a low speed close to zero '0', the speed of the motor is also close to zero '0'. In this state, a maximum driving force (torque) is desired to be generated. When a driving torque is generated in a state in which a rotational speed of the motor is '0', DC current is desired to flow in a motor winding coil even in the case of an alternating current motor and the DC current is desired to flow even in a power semiconductor device of an inverter, which supplies current to the motor.
We have discovered that when the DC current flows in the power semiconductor device of the inverter and the motor, the conduction loss of the power semiconductor device and the resistance loss of the motor winding coil are concentrated in a specific phase and thus heat is generated and sufficient cooling is not performed. Accordingly, when excessive heat is generated and temperature rises above a maximum temperature limit, the power semiconductor and the motor coil may be damaged by the overheating.
We have also found that a method of limiting a magnitude of current to prevent the power semiconductor device of the inverter or the motor coil from being damaged due to the overheating has causes a problem of decreasing an output torque of the motor instead of preventing the damage, thereby significantly lowering a vehicle performance, particularly, a slope climbing performance of a vehicle.
The foregoing is intended merely to aid in the understanding of the background of the present disclosure, and is not intended to mean that the present disclosure falls within the purview of the related art that is already known to those skilled in the art.

Motor drive system and method capable of suppressing heat generation during low speed operation


A control apparatus for internal combustion engine which controls running of an internal combustion engine by use of a microcomputer, and which is provided with a signal processing circuit with a higher operating voltage than that of the microcomputer and a control circuit which invalidates an output of the signal processing circuit or lowers the control level in response to this output when the voltage of the signal processing circuit becomes to have a predetermined low value. Even if the voltage of the signal processing circuit becomes so low that a wrong signal should be outputted, there occurs no disadvantage in running control of the internal combustion engine.

1. Field of the Invention
The present invention relates to a control apparatus for internal combustion engine which controls fuel supply to an internal combustion engine and ignition timing and the like therein by a microcomputer.
2. Description of Related Art
FIG. 1 is a block diagram illustrating a prior art ignition timing control device which is provided with a knocking detection circuit for detecting knocking of an internal combustion engine. In the figure, reference numeral 1 designates an acceleration sensor which is mounted in an internal combustion engine 13 and which detects vibrational acceleration of the internal combustion engine 13. The acceleration sensor 1 is connected to a frequency filter 2 which passes an frequency element indigenous to knocking among output signals of the acceleration sensor 1 and to an analogue gate 3 which kills noise, a disturbance wave, among output signals of the frequency filter 2 when knocking is detected, both being arranged in this order. Switching of the analogue gate 3 is controlled by a gate timing controller 4. An ignition signal being outputted by a phase shifter 8 is inputted to the gate timing controller 4. This ignition signal should generate ignition noise. According to a a timing to generate the ignition noise, a gate of the analogue gate 3 is closed for a predetermined period of time. A voltage signal from the analogue gate 3 is outputted both to a comparator 6 and to a noise level detector 5. The noise level detector 5 outputs slightly higher DC voltage than this voltage signal to the comparator 6. And the comparator 6 compares the output voltage from the analogue gate 3 to that from the noise level detector 5 so as to obtain its equation signal, that is, a knocking detection pulse, and then outputs it to an integrator 7. The integrator 7, then, integrates this output pulse, and outputs the integrated voltage corresponding to the strength of knocking to the phase shifter 8.
Reference numeral 9 designates a rotation signal generator, which generates an ignition signal corresponding to ignition lead angle characteristics of the internal combustion engine 13 in synchronism with its rotation, and outputs this ignition signal to a waveform shaping circuit 10. The waveform shaping circuit 10 changes the output signal from the rotation signal generator 9 into a keying pulses with a required closed angle, and outputs this as a reference ignition signal to the phase shifter 8. The phase shifter 8 shifts the phase of this reference ignition signal corresponding to the output voltage from the integrator 7, and outputs the keying pulse after the shift as an ignition signal both to the gate timing controller 4 and to a switching circuit 11. The switching circuit 11 controls an intermittent electric supply to an ignition coil 12 in response to the ignition signal from the phase shifter 8. In response to the ignition voltage of this ignition coil 12, the internal combustion engine 13 is ignited and run.
Now, functional operation of the prior art apparatus will be described below with reference to waveforms of output signals in each portion of FIG. 1.
FIG. 2 is a graph showing frequency characteristics of an output signal of the acceleration sensor 1, in which reference character A designates the case where there is generated no knocking of the internal combustion engine 13, so does B the case where there is generated knocking. The output signal of the acceleration sensor 1 includes a knock signal (signal being generated when knocking occurs), mechanical noise in the internal combustion engine, and such noise being caused in a signal path as ignition noise. In comparison with A to B in FIG. 2, distributions are apparently different whether there is generated knocking or not, and it can be seen that the knock signal has its own frequency characteristics. The frequency filter 2 passes only this frequency element indigenous to the knock signal, then, noise being caused by the other frequency element can be avoided and the knock signal can be effective detected.
FIGS. 3 and 4 show operating waveforms in each portion in FIG. 1, those alphabets named identically in those both figures show waveforms of the same portions. FIG. 3 shows the case where there is not generated any knocking of the internal combustion engine 13, and so does FIG. 4 the case where there is.
Now will be described below functional operation in the case where there is not generated any knocking with reference to FIG. 3. FIG. 3(a) shows the outputs signal of the acceleration sensor 1. This output signal does not include the knock signal when knocking occurs but does other mechanical noise or ignition noise being generatede at an ignition timing F of the internal combustion engine 13. FIG. 3(b) shows an output signal of the frequency filter 2. The output signal from the acceleration sensor 1 passes through the frequency filter 2, then, the mechanical noise is substantially eliminated. On the other hand, the level of the ignition noise is so high that the ignition noise should be outputted at its high lever even after it passes through the frequency filter 2, then, this ignition noise may be mistaken for the knock signal. In signal to an output signal of the gate timing controller 4 (FIG. 3(c)) which is triggered in response to the output signal (ignition signal) from the phase shifter 8, the gate of the analogue gate 3 is closed for a predetermined period of time after the ignition timing F, and during this predetermined period of time, signals from the frequency filter 2 will not pass through the analogue gate 3. As a result, the voltage signal from the analogue gate 3 (shown by C in FIG. 3(d)) includes no ignition noise but has mechanical noise of low level alone. And such a voltage signal as shown by C in FIG. 3(d) is outputted both to the comparator 6 and to the noise level detector 5.
In the noise level detector 5, there is generated slightly higher DC voltage (shown by in D in FIG. 3(d)) than an envelope level of the mechanical noise. FIG. 3(e) and (f) show output signals of the comparator 6 and the integrator 7, respectively. There being no knock signal, an output D from the noise level detector 5 is always larger than the output from the analogue gate 3, and the output signal from the comparator 6 is always 0, and so is the output voltage from the integrator 7. FIG. 3(g) and (h) show an output signal of the waveform shaping circuit 10 (reference ignition signal) and that of the phase shifter 8 (ignition signal), respectively. The output voltage from the integrator 7 being always 0, the phase shifter 8 will not shift the phase, then, the ignition signal has the same phase as the reference ignition signal.
Next will be described functional operation of the prior art apparatus in the case where there is generated knocking.
The output signal of the acceleration sensor 1 includes the knock signal at the point of a time lagged for a predetermined time after the ignition timing as shown in FIG. 4(a), then, the signal which has passed through both of the frequency filter 2 and the analogue gate 3 is the one shown by C in FIG. 4(d), in which the knock signal is largely overlapped with the mechanical noise. Among those signals which have passed through the analogue gate 3, rising of the knock signal is so steep that the level of an output voltage D of the noise level detector 5 does not react to the knock signal. As a result, inputs of the comparator 6 are shown as C and D in FIG. 4(d), then, there is generated a pulse in the output of the comparator 6 as shown in FIG. 4(e).
The integrator 7 integrates the pulse and generates an integrated voltage as shown in FIG. 4(f). Corresponding to the output voltage of the integrator 7, the phase shifter 8 shifts the output signal of waveform shaping circuit 10 (FIG. 4(g) (reference ignition signal)) to the side of the lag time, then, the phase of the output signal of the phase shifter 8 (ignition signal) lags behind the phase of the reference ignition signal and the switching circuit 11 is driven by the keying pulse (ignition signal) shown in FIG. 4(h). As result, the ignition timing lags and knocking is avoided.
As may be seen from the above description, operations in those states in FIGS. 3 and 4 are repeated to perform the most advantageous ignition timing control.
In the above-mentioned knocking detection circuit, such an acceleration signal being detected by the acceleration sensor 1 as shown in FIGS. 3 and 4 is handled in the frequency filter 2, the analogue gate 3, the noise level detector 5, and the comparator 6. As shown in (b)s and Cs of (d)s in FIGS. 3 and 4, in order to process the acceleration signal (AC signal), each of above those units sets an average value of each signal to be a predetermined bias so that the acceleration signal can be properly processed without having any distortion in either of positive and negative waveforms. This state is shown in a graph of FIG. 5, in which a bias voltage is set to be the point of 1/2 Vcc in a circuit power voltage (Vcc) being supplied from a power circuit (not shown in FIG. 1). In the figure, reference character C designates the output voltage of the analogue gate 3 (signal corresponding to C in FIG. 3(d) or C in FIG. 4(d)), so does D an output voltage of the noise level detector 5 (signal corresponding to D in FIG. 3(d) or D in FIG. 4(d)). Signals of both of those output voltages are processed on the basis of the bias voltage (1/2 Vcc), then, both of positive and negative waves of the signal C in FIG. 5 are properly processed without having any distortion.
When there are conditions that the circuit power voltage (Vcc)=8V, the power circuit is arranged by a serial regulator system, and the minimum voltage loss of the power circuit is 0.5 V, the power circuit is stabilized to supply the circuit power voltage (Vcc) when a battery voltage is more than 8.5 V. On the other hand, when the battery voltage becomes less than 8.5V, the circuit power voltage (Vcc) becomes not a specified voltage but a lower and unstable value. In that case, signals in each portion are so turbulent that a signal to be mistaken for a knock signal should be outputted.
Recently, there has been many cases that the internal combustion engine is electrically controlled and that the above-mentioned knocking detection circuit is integrated into the control apparatus for controlling fuel supply to the internal combustion engine.
Such a prior art control apparatus will be described with reference to FIG. 6. In the figure, reference numeral 21 designates a sensor group, which is comprised of such sensors for measuring or detecting various types of information required for the fuel control and ignition timing control as an flow meter for measuring air flow being inhaled in each cylinder of an engine, crank angle sensor for generating various types of reference signals in synchronism with rotation of a crank shaft, a temperature sensor for measuring the cooling water temperature, and an acceleration sensor for detecting an acceleration signal. The various types of running information being obtained in the sensor group 21 is transmitted to a control unit 22. The control unit 22 is comprised of a microcomputer 22c which is provided with a fuel control unit 22a for controlling fuel supply to the internal combustion engine and an ignition timing control unit 22b for controlling an ignition timing, and a knocking detection circuit 22d of such an arrangement as shown in FIG. 1. The driving signal from the control unit 22 is outputted to an actuator group 23. The actuator group 23 is comprised of various types of such actuators for the fuel control in the engine and for ignition timing control as an injector for supplying fuel, an ingition control for generating an ignition voltage, an air valve for controlling fast idle, and a waste gate for controlling a turbo supercharging pressure.
Now will be described below functional operation of those above-mentioned units. According to the running information from these various types of sensors in the sensor group 21, the control unit 22 operates to obtain driving parameters of the fuel supply and ignition timing in the fuel control unit 22a and the ignition timing control unit 22b, respectively and drives those various types of actuators in the actuator group 23 so that predetermined running states for the control can be obtained. Knocking being generated in the internal combustion engine is detected in the knocking detection circuit 22d by the output from the acceleration sensor in the sensor group 21, and corresponding to the result of the detected knocking, the ignition timing control unit 22b operates to obtain the ignition timing.
The microcomputer 23c is actuated with the circuit power voltage (Vcc)=5 V. If there are conditions that a power circuit (not shown) for supplying the circuit power voltage (Vcc) is arranged by the serial regulators system and that the minimum voltage loss of the power circuit is 0.5 V, the power circuit is stabilized to supply the circuit power voltage (Vcc)=5V when the battery voltage is more than 5.5 V. And the knocking detection circuit 22d, as mentioned above, is stabilized to be actuated when the battery voltage is more than 5.5V. Generally, the battery voltage when the internal combustion engine is on the start-up is about 6V because a starter is actuated. And in that case, the microcomputer 23c is stably actuated, but the knocking detection circuit 22d could not stably be actuated.
As a result, when the battery voltage has a value varying from more than 6V to less than 8V, the microcomputer 23c is normally actuated, but the knocking detection circuit 22d is not normally actuated. Then, there is a disadvantage that a wrong knock signal should be outputted from the knocking detection circuit 22d and, in response to this signal, the microcomputer 23c should perform its wrong control. Especially when a battery voltage E is varied with ripples as shown in FIG. 7, there is high possibility that the knock signal should be detected by mistake.

Control apparatus for internal combustion engine


A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

Circuits are known in the art for detection and characterization of a radiating particle comprising at least a first combinational logic circuit configured to propagate a pulse generated in the combinational logic circuit when it is hit by a radiating particle, and a second circuit configured to supply a signal representative of the duration of the generated pulse to characterize the particle. Indeed, when a particle hits the first circuit and when it generates therein a transient voltage pulse, generally designated with acronym SET ("Single Event Transient"), the duration of the pulse is representative of characteristics of the particle, for example, of its type and/or of its power.
In such circuits, an error with respect to the measurement of the duration of the pulse may result in an erroneous characterization of the particle.
There is a need in the art to decrease or correct errors in the measurement of the duration of a transient voltage pulse, particularly measurement errors due to manufacturing variations of the circuit performing the measurement.


A facility for use in handling dairy animals is provided which includes a service alley which is located below a platform on which the cow or other dairy animal stands during milking. A floor is located adjacent the platform and the service alley and defines an operator area where the herdsman can tend the milking equipment to be attached to the animal. Advantageously, the bulk of the electronic equipment and other milking apparatus is located in the service alley and thus environmentally isolated from the exposed area where the cows are milked. Parallel rows of platforms and service alleys are preferably provided, separated by a common operator area, and the service alleys may be joined to a common equipment room housing milk receivers, coolers, and the like. The service alley is preferably supplied with ventilation through subterranean ducts which provides air at moderated temperatures.

1. Field of the Invention
This invention broadly concerns a building which serves as a milking facility and includes three separate areas for accommodating a dairy animal, a herdsman or operator, and a service alley for access to milk receivers and other equipment requiring operator access. Advantageously, the dairy animal area or platform is positioned immediately above the service alley to isolate the milk receiver from the animals.
2. Description of the Prior Art
In a typical modern milking parlor, cows enter the parlor area and are positioned in side-by-side relationship in either a perpendicular or so-called herringbone pattern. The cows are located at one higher elevation, and the operators are located at a second, lower elevation in an operator area or "pit". The operators are free to move along the pit to service the animals during milking by attaching or removing the teat claws and performing other maintenance operations.
The operators, also known as herdsmen, must also attend to a variety of milk transfer equipment, much of it including a good deal of electronics. For example, the milk weigh meters are typically located in the pit, as are clean-in-place units, milk lines, vacuum lines, and pulsation lines. Other equipment may often be located in the pit. Unfortunately, this exposes the equipment to the cows, manure, urine, flies and other disease carriers as well as high or low ambient temperatures according to the local environment. This equipment must be not only cleaned and maintained, but also avoided when the herdsman is tending the cows.


A display is able to display 3D content in high resolution 2D by utilizing the many views contained in the 3D data and converting the 3D data into 2D data. In some embodiments, the 3D data is converted using shifts in different views of a pixel. In some embodiments, the 3D is converted using shifts in different views of a local pixel and global pixels as well. Displays implementing the 2D high resolution display in addition to a low resolution 3D display are able to display 3D and 2D data depending on a user's preference.

Three dimensional technology has been developing for over a century, yet has never been able to establish itself in the mainstream generally due to complexity and cost for the average user. The emergence of Liquid Crystal Display (LCD) and Plasma screens which are better suited to rendering 3D images than traditional Cathode Ray Tube (CRT) monitors and televisions in both consumer electronics and the computer world has spurred interest in the technology. 3D systems have progressed from being technical curiosities and are now becoming practical acquisition and display systems for entertainment, commercial and scientific applications. With the boost in interest, many hardware and software companies are collaborating on 3D products.
NTT DoCoMo unveiled the Sharp mova SH251iS handset which is the first to feature a color screen capable of rendering 3D images. A single digital camera allows its user to take two dimensional (2D) images and, then using an editing system, convert them into 3D. The 3D images are sent to other phones with the recipient able to see the 3D images if they own a similarly equipped handset. No special glasses are required to view the 3D images on the auto-stereoscopic system. There are a number of problems with this technology though. In order to see quality 3D images, the user has to be positioned directly in front of the phone and approximately one foot away from its screen. If the user then moves slightly he will lose focus of the image. Furthermore, since only one camera is utilized, it can only take a 2D image and then via the 3D editor, the image is artificially turned into a 3D image. Quality of the image is therefore an issue.
The display can be improved though by utilizing a number of images, each spaced apart by 65 mm. With a number of images, the viewer can move his head left or right and will still see a correct image. However, there are additional problems with this technique. The number of cameras required increases. For example, to have four views, four cameras are used. Also, since the sets of numbers are repeating, there will still be a position that results in a reverse 3D image, just fewer of them. The reverse image can be overcome by inserting a null or black field between the repeating sets. The black field will remove the reverse 3D issue, but then there are positions where the image is no longer 3D. Furthermore, the number of black fields required is inversely proportional to the number of cameras utilized such that the more cameras used, the fewer black fields required. Hence, the multi-image display has a number of issues that need to be overcome for the viewer to enjoy his 3D experience.
As 3D display devices are emerging in the consumer market, the content of 3D images/videos are used. New content is able to be generated using a 3D image acquisition camera. The focus recently has also been on 2D data conversion to 3D data.

Super-resolution from 3D (3D to 2D conversion) for high quality 2D playback