A plastic duct section is equipped with integral connections on its ends. Each duct has indicia along its running length to facilitate cutting of the duct to a desired length. In one embodiment, the indicia may take the form of equally spaced circumferential ribs spaced along the length of the duct. These ribs are engaged by sets of fingers extending toward each other from concentric walls spaced to receive the straight end of an adjacent duct section. The innermost end of the concentric walls is equipped with a layer of insulative material to enable sealing engagement between duct sections significantly reducing pressure loss. Attached straps permit duct sections to be easily suspended between adjacent joists. A floor-mounted elbow boot is equipped with a removable plastic cover to prevent dust, dirt and debris from accumulating in the installed heating duct during finish construction of the building.

Present day HVAC ducts suffer from a number of disadvantages. First, sections of duct are not easily connected one to another generally requiring the installation of as many as 8 screws around the periphery of the joined ducts at each joint. This is laborious and time consuming. Second, it is a problem to cut a section to a particular length, whether the duct section is rectangular or round, the duct must be measured and then a circumferential line drawn at the length desired so the tin snips have a guide to follow. Third, the cut edges are sharp and pose a significant risk to anyone handling the cut duct.
Fourth, most HVAC ducts experience significant amounts of leakage at the joints resulting in pressure drops at the vents. One conventional means of reducing leakage at the joints is to increase the lengths of the duct, thereby reducing the number of joints. This makes handling the duct more difficult. Another means to cope with leakage is to tape the joints using a tape and/or messy mastic. Fifth, most HVAC ducts are difficult to suspend or mount between joists since they lack any integral connecting means. Sixth, most ducts are made of sheet metal. It is estimated that losses in heating efficiency can be as high as 60% due to convective and radiative heating of the typically uninsulated air space surrounding the duct. Sheet metal ducts also pose a significant hazard to handlers, particularly when a burred or sharp edge has been created due to cutting to length.
Finally, in new construction, the use of floor-mounted boots can often cause problems since any dust and debris can fall into the grate and remain lodged in the duct. When the furnace is activated, the dust and small debris particles become airborne which becomes a nuisance to the home owner and frequently results in a service call for the HVAC supplier to identify the source of the objectionable odor.
It is among the objects of the present invention to overcome the deficiencies of the prior art HVAC ducts. The HVAC duct of the present invention is equipped with a quick connector for adjacent sections. This connector has opposing cylindrical surfaces equipped with inwardly protruding fingers which form a "chinese finger puzzle" gripper which can engage an end of another section of duct. Preferably, a separate connector may be equipped with two grippers, one on either end, to interconnect two sections of duct. Alternatively, each section of duct may have a connector integrally formed on a first end of the duct for engagement of an opposing end of the adjacent duct section.
The entire length of the duct of the present invention may have spaced there along at equal distances a series of peripheral ribs. These ribs serve to provide structural rigidity as well as enable cutting to particular length. The ribs provide a guide to the shears to enable more precise circumferential cutting to length. In addition, at least two circumferential ribs are engaged by the gripping fingers to ensure interconnection of the duct sections. Alternatively, indicia may be provided on the surface of the duct to provide the ready measurement feature if the gripping fingers provide adequate retention force without the ribs. Each recess is lined with a layer of insulative foam, such as foam rubber, or other insulative material, so that the received end of the duct seals in the material. The insulative foam results in retention of as much as 90% of the pressure at the duct inlet arriving at the outlet.
Each duct section is equipped with two eared circumferential bands which permit easy securement between floor or wall joists. The duct system of the present invention further includes a floor-mounted elbow boot which is equipped with a removable plastic cover which permits the duct to be protected from dirt, dust and debris settling into the vent before construction is complete.
While the duct of the present invention can be made of sheet metal, it is most preferably manufactured of plastic. Plastic is not as aggressive a conductor of heat as metal and hence, does not rob the system of as much heat through conductive, convective and radiative heat losses. Further, the cut edge of the plastic duct does not pose as significant a threat to its handler as the sheet metal duct.
Various other features, advantages and characteristics of the present invention will become apparent to one of ordinary skill in the art after a reading of the following specification.


The present invention discloses an optical IC including a photo-detector formed on a substrate, at least one light-blocking film layer formed in a portion of the main surface of the substrate other than the portion where the light-detector is formed, at least two insulator film layers formed so as to cover the light-blocking film layer, a clad layer formed consecutively over the photo-detector and the insulator film layers, and an optical wave-guide path layer formed on the clad layers, in which the insulator film layers are formed so as to form a plurality of staircase-like steps toward the photo-detector.

1. Field of the Invention
The present invention relates to an optical integrated circuit (IC) and method for manufacturing the same and, more particularly to, such an optical IC and method for manufacturing the same that can reduce a scatter loss of an optical signal.
2. Description of the Related Art
In a conventional optical IC practically used in optical pick-up or optical-fiber communication, typically an optical element such as a lens is used to guide a light which has propagated a space, to then detect it by a photo-detector.
Such a optical IC, however, is expected to be of a wave-guide path type so as to reduce the number of the optical elements used therein and hence the costs thereof as well as to have more functions by use of, for example, an electro-optic effect. FIG. 7 is a cross-sectional view for showing one example of a configuration of a wave-guide path type photo-detector which is manufactured on the optical IC substrate. As shown in FIG. 7, on the substrate of the optical IC, to avoid erroneous detection of stray light which hit a portion other than a photo-detector formed on the substrate to detect an optical signal which has propagated a space, to block light, typically a light-blocking film layer made of metal such as aluminum is provided at the portions other than the photo-detector. Moreover, avoid corroding of this light-blocking film layer, it is typically sandwiched by insulator film layers.
A wave-guide path type photo-detector construction by use of an optical IC substrate having such a configuration, however, has suffered from a problem that, as shown in FIG. 7, an insulator film layer and a light-blocking film layer are formed as stacked on the substrate to thereby form a steep step with a value on the micrometer order at a boundary between a photo-detecting portion and such a portion of the light-blocking film layer that surrounds the photo-detecting portion, so that the resultant bent portion has a large radiation loss of the light propagating an optical wave-guide layer.
Furthermore, since this step is step, a clad layer is liable to be cracked at its step portion, which constitutes another problem.
Further, to polish such a steep step at the boundary of the light-blocking film layer for improvement of the performance, the costs are increased, which constitutes a further problem.
Those problems become more remarkable as the numbers of the insulator film layers and the light-blocking film layers increase when the optical IC employs a multi-layer wiring configuration.
It is therefore an object of the present invention to provide an optical IC and method for manufacturing the same that can reduce the scatter loss of an optical signal easily and inexpensively.
The above object of the present invention can be achieved by an optical integrated circuit provided with: a photo-detector formed on a substrate; at least one light-blocking film layer which is formed in a portion of a main surface of the substrate other than the portion where the photo-detector is formed; at least two insulator film layers which are formed so as to cover the light-blocking film layer; a clad layer which is formed consecutively over the light-detector and the insulator film layers; and an optical wave-guide path layer formed on the clad layer, wherein the clad layer is formed in a smooth slope toward the photo-detector.
According to the present invention, the clad layer is formed as a smooth slope, so that the wave-guide path layer can have a smooth slope (that is, smooth step structure) formed thereon, to thereby guide a light with a low loss. It also makes it possible to reduce the scatter loss of an optical signal at the bent portion of the light-blocking film layer.
In one aspect of the optical integrated circuit of the present invention, the insulator film layers form a plurality of staircase-like steps, each of which has a horizontal length measuring at least xc2xd of a maximum film thickness of the light-blocking film layer. Namely, each of the steps is formed in an interval measuring at least xc2xd of a maximum film thickness of the light-blocking film layer.
According to this aspect, the inclination of the steps in a staircase is made moderate, so that the step can be buried smooth, to thereby form such an optical wave-guide path layer that has an even smoother slope (that is, smooth step structure).
In another aspect of the optical integrated circuit of the present invention, the insulator film layers each have a film thickness measuring at least ⅓ of the maximum film thickness of the light-blocking film layer.
According to this aspect, the inclination of the steps in a staircase is made moderate, so that the step can be buried smooth, to thereby form such an optical wave-guide path layer that has an even smoother slope (that is, smooth step structure).
In further aspect of the optical integrated circuit of the present invention, the insulator film layer have an inclined face having an inclination angle smaller than 90 degrees toward the photo-detector.
According to this aspect, the inclination of the steps in a staircase is made moderate, so that the step can be buried smooth, to thereby form such an optical wave-guide path layer that has an even smoother slope (that is, smooth step structure).
In further aspect of the optical integrated circuit of the present invention, the lowest one of the insulator film layers is formed so as to cover the photo-detector.
The above object of the present invention can be achieved by an optical integrated circuit provided with: at least one night-blocking film layer which is formed in a portion of a main surface of the substrate other than the portion where the photo-detector is formed; at least two insulator film layers which are formed so as to cover the light-blocking film layer; a clad layer which is formed consecutively over the light-detector and the insulator film layers; and an optical wave-guide path layer formed on the clad layer, wherein the insulator film layers form a plurality of staircase-like steps toward the photo-detector.
According to the present invention, a multi-layer film underlying the clad layer is adapted to form, in construction, steps in a staircase at the boundary between the photo-detector and any other portions, so that when the clad layer is formed thereon, the optical wave-guide path layer can have a smooth slope (that is, smooth step structure) formed thereon, to thereby guide light with a low loss. It also makes it possible to reduce the scatter loss of an optical signal at the bent portion of the light-blocking film layer.
Furthermore, it is unnecessary to polish the steep step at the boundary of the light-blocking film layer for improvement of the performance, so that this steep step at the boundary of the light-blocking film layer can be smoothed only by etching, thus manufacturing the optical IC simply and inexpensively.
In one aspect of the optical integrated circuit of the present invention, each of which has a horizontal measuring at least xc2xd of a maximum film thickness of the light-blocking film layer.
According to this aspect, the inclination of the steps in a staircase is made moderate, so that the step can be buried smooth, to thereby form such an optical wave-guide path layer that has an even smoother slope (that is, smooth step structure).
In another aspect of the optical integrated circuit of the present invention, the insulator film layers each have a film thickness measuring at least ⅓ of the maximum film thickness of the light-blocking film layer.
According to this aspect, the inclination of the steps 10 in a staircase is made moderate, so that the step can be buried smooth, to thereby form such an optical wave-guide path layer that has an even smoother slope (that is, smooth step structure).
In further aspect of the optical integrated circuit of the present invention, the insulator film layer have an inclined face having an inclination angle smaller than 90 degrees toward the photo-detector.
According to this aspect, the inclination of the steps in a staircase is made moderate, so that the step can be buried smooth, to thereby form such an optical wave-guide path layer that has an even smoother slope (that is, smooth step structure).
In further aspect of the optical integrated circuit of the present invention, the lowest one of the insulator film layers is formed so as to cover the photo-detector.
The above object of the present invention can be achieved by a method for manufacturing an optical integrated circuit provided with: a process of forming at least one light-blocking film layer in a portion of a main surface of a substrate other than the portion where a photo-detector is formed; a process of forming a insulator film layer having a staircase-like step so as to cover the light-blocking film layer toward the photo-detector; a process of forming a clad layer having a smooth slope by pouring a liquefied derivative material prepared to have appropriate viscosity onto the staircase-like step; and a process of forming an optical wave-guide path layer on the clad layer.
According to the present invention, the optical IC of the present invention can be manufactured.

Optical integrated circuit and method for manufacturing optical integrated circuit


The present invention relates to creating a layout of an electronic circuit from a netlist of interconnected components, wherein the components can be represented by planar geometric shapes in the layout. The advantages of the present invention are achieved by tightly coupling placement and routing. An initial placement of shapes of extended size is succeeded by a routing step that tries to create wires between shapes of reduced size. If that fails, it is tried to wire shapes of extended size instead. The wiring can be combined with a delta-placement of shapes within shapes of extended size such that wires connected to shapes of extended size also connect to the shapes.

The present invention generally relates to the design of electronic circuits such as semiconductor integrated circuit (IC) devices and printed circuit boards. Particularly, the present invention relates to a method, a tool and a computer program product for creating a layout for an electronic circuit.
An IC layout is the representation of an IC in terms of planar geometric shapes that correspond to patterns of shapes actually drawn on photo masks used in semiconductor device fabrication. A printed circuit board, hereinafter called board, consists of "printed wires" attached to a sheet of insulator. A board layout is the representation of a board in terms of planar geometric shapes that correspond to pattern of shapes actually drawn of photo masks used in the board device fabrication.
Optimal layouts cannot be found in a reasonable time. Even simplified versions of the problem have been proved to be NP-complete or NP-hard according to the computational complexity theory. In practice, the layout problem is broken up into several phases such as floorplanning, placement, and routing. With the large sizes of modern board and IC designs, the phases are usually performed with automatic or semi-automatic electronic design automation tools.
Floorplanning is a preparatory step of creating an IC die map showing the expected locations for various elements of the IC. Placement and routing, also called place and route, are similar at a high-level for both ICs and boards, but the actual details are very different. During place and route board components (blocks) are placed on a board design and the wires are drawn between them and for ICs a layout of a larger block of the IC or the whole IC is created from layouts of smaller sub-blocks. The type of blocks and the actual place and route process itself depends on design methodology.
Due to its complexity the place and route process is usually performed in two separate stages: placement, i.e., determining the positions of the sub-blocks in the design area, and routing, i.e., interconnecting the sub-blocks while keeping the positions of the sub-blocks. Placement is considered as the most important phase of the IC layout design because of its difficulty. The result of the placement directly affects IC area, routeability, and performance. However, also the importance of routing is increasing continuously.
There are three basic styles of routing tools on the market: grid-based routers, shape-based routers, and graph-based routers. A grid-based router superimposes a mesh-like template over the routing area of design with evenly spaced tracks, all grids, running both vertically and horizontally across the design area. Any routing operation that is performed must be cognizant of all the grid points as a whole. A shape-based router in contrast does not need such a grid. A graph-based router views a design similarly to a grid-based router in that there are both vertical and horizontal grids that can be followed, but it only considers these grids as a guideline for routing and is not mandated to use them.
The blocks and sub-blocks that form an IC or a board can be divided in different hierarchy levels: the device level comprising elements such as transistors, diodes, and capacitors, the book level comprising elements from a library such as gates (i.e. NAND and NOR circuits) and latches, the macro level comprising complex elements like adders and dividers, the unit level comprising elements from the macro level (i.e. adder) and the chip level comprising elements from the macro and the unit level (i.e. Floating Point Unit), and the board level comprising elements such as ICs.
Both placement and routing are usually performed incrementally. In an iteration step the layout is optimised for various goals while ensuring signal integrity and compliance to various design rules related to the semiconductor manufacturing process. Examples for placement optimisation goals are minimizing the wire-length between the various blocks as the signal delay increases with the wire length, and maximising the wire density to save chip area. Examples for routing optimisation goals are minimizing the wire length, and having the same or similar length for certain wires. If it is not possible to achieve the optimisation goals then the current layout is dropped, the design of the IC will be changed and the placement and routing process is started again.
With the enduring trend of devices (e.g. transistors) and books and macros (e.g. gates) becoming smaller and faster, IC designs are being limited by the delays of the wires connecting the devices and macros rather than by their area. For example, for semiconductor process geometries in the 130 nm range it is reported that wires account for nearly 75% of an IC's overall delay. And nearly 40% of the wires can attribute more than 50% of their total wire capacitance to the cross coupling between neighbouring wires. At smaller geometries (e.g. in toady's 90 nm range), the situation is becoming even more severe.
Another limiting factor for IC designs is the wiring density. As the devices become smaller the wires do not scale to the same amount. The density of the IC is therefore more and more limited by the wiring density and not by the density of the devices. It is necessary to increase the space between the devices to be able to route the IC.
Traditional design methodologies do not consider wire delays and capacitance until after placement since routing is performed after placement at the end of the design flow. Designers must iterate multiple times in hope of achieving design closure. And often, in order to meet a strict schedule for the IC release to manufacturing, designers are forced to accept a lower performing IC or the risk of potential failures due to unresolved signal integrity issues.

Method for creating a layout for an electronic circuit

International Business Machines Corporation


For use in a propulsion control system, a microprocessor based central processing unit board includes both Multibus I and Multibus II interfaces. Multibus I master interface and Multibus slave interface controllers are designed for high data throughput by using programmed logic design (PLD) technology. In addition, the need for latching of data transceivers used in conventional Multibus I designs is eliminated. The Multibus II interface is removable.

1. Field of the Invention
The invention relates to the field of propulsion control system central processing unit (CPU) boards, and more particularly, to bus interface controller design in a CPU board in an Intel 80386 based propulsion control system for use with subway cars or the like.
2. Background Information
A propulsion control system for an advanced design subway car requires high-speed data acquisition, an ability to communicate with a host computer, and an ability to communicate to control slave input/output (I/O) boards for controlling servo systems of the subway car. These varied requirements have caused compromises in communications bus design in the past, and thus limited overall system performance and efficiency.
There are known a variety of buses, bus interfaces, and bus controllers in various microprocessor systems. One known industrial bus standard is the IEEE 796, or Multibus I, and another is the IEEE 1296, or Multibus II. "Multibus" is a trademark of the Intel Corporation for its unified bus architecture, which uses a single integrated bus for data, address and control information. The Intel Multibus is used, for example, for connecting random access memory (RAM), read only memory (ROM) and input/output (I/O) boards in a microprocessor based system. The Multibus carries five types of signals, including data, address, control, multilevel interrupt and timing signals. Modules connected to the bus act as either masters or slaves, masters having the ability to control the bus. Arbitration logic is provided for on the bus to handle requests from multiple bus masters. Data rates on the bus are a factor of the master and slave devices data rates. The Intel bus is configured with two connectors, the primary (P1) and the secondary (P2) connector. P1 signals include the address, data, control and interrupt signals, as well as the power supply. Most of the signals on the bus operate with negative logic, i.e., they are true when low.
The Multibus I and Multibus II busses are both usable with Intel IAPX 86 CPU based systems, for instance an 80386 CPU based system. Various Multibus I and Multibus II interfaces are known. A device attached to a Multibus I interface has the capability to operate as a bus master and share a bus with other masters that reside on the bus. A device on the Multibus I interface also has the capacity to generate and receive both vectored and nonvectored interrupts as well as read/write references to input/output (I/O) and memory space. Because of the bus protocol used on the Multibus I, and other factors, it is suitable for communication with relatively slow slave I/O boards and the like. The Multibus II, on the other hand, allows interprocessor communications via message passing, and is suitable for high-speed communications.
In typical Multibus I designs, latching of data transceivers is required. Also, the existing devices, for instance the Intel 8288 and 8289 bus controller and arbiter respectively, limit the achievable data throughput of the bus system. Improved performance and a marriage of Multi-bus I and II capabilities in an integrated system are desirable.
Therefore, a propulsion control CPU board which overcomes the above limitations and provides system design flexibility by having both Multibus I and II interfaces on a single 80386 CPU board is proposed.

Propulsion control system central processing unit board


A pattern forming method comprising: (i) a step of forming a film from a chemical amplification resist composition, (ii) a step of exposing the film, and (iii) a step of developing the exposed film by using an organic solvent-containing developer, wherein the resist composition contains: (A) a resin, (B) a nonionic compound capable of generating an acid upon irradiation with an actinic ray or radiation, (C) a crosslinking agent, and (D) a solvent.

Since the advent of a resist for KrF excimer laser (248 nm), an image forming method called chemical amplification is used as an image forming method for resist so as to compensate for sensitivity reduction caused by light absorption. For example, the image forming method by positive chemical amplification is an image forming method of decomposing an acid generator in the exposed area upon exposure with excimer laser, electron beam, extreme-ultraviolet light or the like to produce an acid, converting an alkali-insoluble group into an alkali-soluble group by using the generated acid as a reaction catalyst in the baking after exposure (PEB: Post Exposure Bake), and removing the exposed area with an alkali developer.
As for the alkali developer used in the method above, various alkali developers have been proposed, but an aqueous alkali developer of 2.38 mass % TMAH (an aqueous tetramethylammonium hydroxide solution) is being used for general purposes.
Also, due to miniaturization of a semiconductor device, the trend is moving toward a shorter wavelength of the exposure light source and a higher numerical aperture (higher NA) of the projection lens, and an exposure machine using an ArF excimer laser with a wavelength of 193 nm as a light source has been developed at present. Furthermore, for example, a so-called immersion method of filling a high refractive-index liquid (hereinafter sometimes referred to as an "immersion liquid") between the projection lens and the sample, and EUV lithography of performing exposure to ultraviolet light at a shorter wavelength (13.5 nm) have been proposed.
However, it is actually very difficult to find out an appropriate combination of a resist composition, a developer, a rinsing solution and the like, necessary for forming a pattern with overall good performance, and more improvements are being demanded. In particular, as the resolved line width of resist becomes finer, improvement of the line edge roughness performance of a line pattern or the in-plane uniformity of the pattern dimension is being desired.
On the other hand, as well as the currently predominant positive resist, a negative chemical amplification resist composition for use in the pattern formation by alkali development is also being developed (see, for example, JP-A-2006-317803 (the term "JP-A" as used herein means an "unexamined published Japanese patent application"), JP-A-2006-259582, JP-A-2006-195050, JP-A-2000-206694). Because, in the production of a semiconductor device or the like, patterns having various profiles such as line, trench and hole need to be formed and some patterns are difficult to form by the current positive resist composition.
In the pattern formation by alkali development using a conventional negative resist composition, it is demanded to more improve the line width variation (LWR), focus latitude (DOF) and other various performances, which are presumed to be mainly governed by swelling at the development.
Also, a double developing technique as a double patterning technology for further raising the resolution is described in JP-A-2008-292975. In this technique, by making use of a property that when exposed, the polarity of a resin in a resist composition becomes high polarity in a high light intensity region and becomes low polarity in a low light intensity region, a high exposure region of a specific resist film is dissolved with a high-polarity developer and a low exposure region is dissolved with a low-polarity developer, whereby the medium exposure dose region is allowed to remain without being dissolved and removed by development and a line-and-space pattern having a pitch half the pitch of the exposure mask is formed.
Furthermore, a chemical amplification resist composition comprising a first resin containing an acid-decomposable repeating unit with a partial structure selected from specific alicyclic hydrocarbon structures and being capable of increasing the polarity by the action of an acid to decrease the solubility for a negative developer (a developer that selectively dissolves and removes the exposed area), and a second resin containing an acid-decomposable repeating unit and being capable of increasing the polarity by the action of an acid to decrease the solubility for a negative developer, with the average content of acid-decomposable repeating units being different from the average content of acid-decomposable repeating units in the first resin, is described in JP-A-2009-025707. It is demonstrated that according to this chemical amplification resist composition, a pattern with little line edge roughness and good performance in terms of pattern collapse is obtained.
However, more stable formation of a high-definition fine pattern for producing a high-precision electronic device with high integration is being demanded.

Pattern forming method, chemical amplification resist composition and resist film


A driving lane recognition system which can improve the lane recognition accuracy by stably detecting the various kinds of lane markers is disclosed. An image processing means 6 for image-processing a road image taken by a camera 5 has a plurality of different kinds of image processing algorithms 9 to 11. A driving lane is detected by selecting an image processing algorithm suitable for the driving lane out of the plurality of different kinds of image processing algorithms 9 to 11 corresponding to a road on which a vehicle is running.

The present invention relates to a driving lane recognition system for recognizing a driving lane of a vehicle by executing image processing of a road-surface image taken by a camera, and particularly to a driving lane recognition system for driving in a lane appropriately corresponding with a plurality of lane marker shapes (kinds).
A technology of recognition of vehicle driving lane is a technology necessary for a lane departure warning system of a vehicle, a lane keeping support system for executing steering assist control and so on. In regard to the driving lane recognition technology, there are a method that lane markers formed of magnet are embedded in a load to recognize a driving lane from the magnetic field positions; a method that a position of a vehicle is measured with high accuracy using a differential GPS or a kinematic GPS to calculate a driving lane from highly accurate road map data; and so on. However, any of these methods requires construction of the infrastructure, and accordingly the applicable area is limited.
On the other hand, a method of using image processing by detecting a driving lane from a camera image has an advantage in that the applicable area is wide because there is no need to construct the infrastructure.
In the lane recognition using the image processing, stable recognition is always required in taking various statuses of road surface into consideration. In Japanese Patent Application Laid-Open No.7-128059 disclosing a method in which a parameter or a threshold is changed corresponding to a road surface status, it is described that the threshold used for extracting an edge of a white line of lane maker is determined from the edge intensity. Further, in Japanese Patent Application Laid-Open No. 6-341821, it is described that recognition area is changed by independently setting thresholds from the edge intensities of right and left white lines. As described above, by changing a threshold or a parameter corresponding to a road surface status, stable recognition results can be obtained for various road surface statuses.
Although the conventional technologies cope with the various statuses of road surface by changing the threshold or the parameter, the recognition is made using the image processing algorithm which is created on the premise that the lane markers are white lines.
Most of the lane markers are white lines (yellow lines) in Japan, but raised pavement markers and post cones in addition to the white lines are used as the lane markers in various foreign countries. The detection of driving lane is performed in order to obtain a displacement of a vehicle and a curvature of the lane. When various kinds of the lane markers such as the white line, the raised pavement marker, the post cone and so on are image-processed using a common image processing algorithm, there is a problem in that the recognition accuracy of the resultant recognition rate is degraded.


A catadioptric optical system comprising a first imaging optical system including a concave mirror and forming an intermediate image of a first object, said first imaging optical system forming a reciprocating optical system that an incidence light and reflected light pass, a second imaging optical system for forming an image of the intermediate image onto a second object, and a first optical path deflective member, provided between the concave mirror and the intermediate image, for introducing a light from the first imaging optical system to the second imaging optical system, wherein said first optical path deflective member deflects a light in such a direction that a forward path of the first imaging optical system intersects a return path of the first imaging optical system, and wherein said intermediate image is formed without an optical element after a deflection.

The present invention relates generally to a projection optical system, and more particularly to a catadioptric projection optical system that projects an object, such as a single crystal substrate and a glass plate for a liquid crystal display ("LCD"), using a mirror. The present invention is suitable, for example, an immersion exposure apparatus (an immersion lithography exposure system) for exposing the object through a fluid between the projection optical system and the object.
The photolithography technology for manufacturing fine semiconductor devices, such as semiconductor memory and logic circuits, has conventionally employed a reduction projection exposure apparatus that uses a projection optical system to project a circuit pattern of a reticle (or mask) onto a wafer, etc. A more highly integrated and finer semiconductor device (circuit pattern) requires a projection optical system for a better specification and performance. Generally, a shorter wavelength of the exposure light and a higher numerical aperture ("NA") are effective to improve the resolution. Recently, an optical system with an NA of 1 or higher that utilizes an immersion optical system that fills a space with fluid between a final glass surface (in other words, the lens closet to the wafer) of the projection optical system and the wafer has been proposed, and a higher NA scheme is in progress.
For the exposure light with a short wavelength such as an ArF excimer laser (with a wavelength of approximately 193 nm) and a F2 laser (with a wavelength of approximately 157 nm) for higher resolution, lens materials are limited to quartz and calcium fluoride for reduced transmittance. An optical system that includes only lenses (refracting element) absorbs the large amount of light, and reduces an exposure dose on the wafer, causing a decrease in through put. Moreover, lens's heat absorption and resultant temperature rise disadvantageously fluctuate a focal position, (heat) aberrations, etc. Quartz and calcium fluoride possess similar dispersive powers, and have difficulties in correcting the chromatic aberration. Especially, the lens material can use only calcium fluoride for the exposure wavelength of 157 nm, and correcting the chromatic aberration becomes more difficult. In addition, a lens diameter increases as the NA becomes higher, and causes the increased apparatus cost.
Various proposals that use a mirror (reflecting element) for an optical system have been made to solve the disadvantageous reduced transmittance, difficult corrections to the chromatic aberration and large aperture of the lens. For example, a catadioptric projection optical system that combines a mirror with a lens has been disclosed. See, for example, U.S. Pat. No. 5,650,877 (reference 1), Japanese Patent Applications, Publication Nos. 62-210415 (reference 2), 62-258414 (reference 3), 5-188298 (reference 4), 6-230287 (reference 5), 2-66510 (reference 6), 3-282527 (reference 7), 8-304705 (reference 8), 2000-47114 (reference 9), and 2003-43362 (reference 10).
A projection optical system that includes a reflective optical system for a shorter exposure wavelength and a higher NA needs to correct the chromatic aberration, to maintain a large enough imaging area on an image surface, and to secure a sufficient working distance on the image side with a simple structure. The large enough imaging area on the image surface is advantageous to a scanning exposure apparatus to maintain the throughput, and reduce exposure fluctuations. The sufficient image-side working distance is desirable for an apparatus's auto-focusing system, a wafer-stage's transport system, and the like. The simple structure would simplify a barrel and the like, and facilitate the assembly production.
The optical system disclosed in the reference 1 arranges a Mangin mirror and a refractor in an optical system, and exposes a reticle image onto a wafer. Disadvantageously, this optical system blocks light on a pupil's central part for all the angles of view to be used (hollow illumination), and cannot enlarge an exposure area. An attempt to enlarge the exposure area results in the undesirable expansion of the light blockage on the pupil's central part. In addition, since a refractive surface of the Mangin mirror forms the light splitting surface that halves the light intensity when ever the light passes through its surface, and reduces the light intensity down to about 10% on the image surface (wafer surface).
The references 2 and 3 apply Cassegrain and Schwarzschild mirror systems, and each propose an optical system that has an opening at the center of the mirror to create a hollow illumination to the pupil and to image only the pupil's periphery. However, the hollow illumination on the pupil deteriorates the imaging performance. An attempt to lessen the hollow illumination to the pupil inevitably increases the power of the mirror and enlarges an angle incident upon the mirror. A high NA causes a mirror's diameter to grow remarkably.
According to the optical system disclosed in the references 4 and 5, the deflected optical path complicates an apparatus's configuration. A high NA is structurally difficult because the concave mirror is responsible for most powers in the optical units for imaging an intermediate image onto a final image. Since a lens system located between the concave mirror and the image surface is a reduction system and the magnification has a positive sign, the image-side working distance cannot be sufficiently secured. Since an optical path needs to be split, it is structurally difficult to secure an imaging area width. The large optical system is not suitable for foot-printing.
The references 6 and 7 first split an optical path using by the beam-splitter, and complicate the structure of a lens barrel. They need the beam-splitter with a large diameter and if the beam-splitter is a prism type, a loss of the light intensity is large due to its thickness. A higher NA needs a larger diameter and increases a loss of the light intensity. Use of a flat-plate beam splitter is also problematic, because it causes astigmatism and coma even with axial light. In addition to asymmetrical aberrations due to heat absorptions and aberrations due to characteristic changes on the beam splitting surface, accurate productions of the beam splitter is difficult.
The optical system disclosed in the references 8 to 10 propose a twice-imaging catadioptric optical system for forming an intermediate image once. It includes a first imaging optical system that has a reciprocating optical system (double-pass optical system) which includes concave mirrors to form an intermediate image of a first object (e.g., a reticle), and a second imaging optical system that forms the intermediate image onto a surface of a second object (e.g., a wafer). The optical system of the reference 8 arranges a first plane mirror near the intermediate image for deflecting an optical axis and light near the intermediate image. The deflected optical axis is made approximately parallel to a reticle stage and is deflected once again by a second plane mirror, or an image is formed onto a second object without a second plane mirror. In the optical system of the reference 9, a positive lens refracts light from a first object (e.g., a reticle), and a first plane mirror deflects the optical axis. A second plane mirror in a first imaging optical system again deflects the light reflected by a reciprocating optical system that includes a concave mirror to form an intermediate image. The intermediate image is projected onto a second object (e.g., a wafer) with a second imaging optical system. However, a magnification of the first imaging optical system serves as a reduction system more (corresponding to a paraxial magnification |β1| of about 0.625 of the first imaging optical system). Therefore, the first intermediate image enlarges the NA of the first intermediate image for an object-side NA in the first object by the reduction magnification. As a result, an incident angle range upon the plane mirror increases, and a higher NA scheme as in the immersion etc. encounters a serious problem. In other words, the first imaging optical system that controls a reduction magnification, a higher NA excessively increases the incident angle range upon the plane mirror, and a reflection film on the plane mirror causes a large difference in reflected light's intensity between the p-polarized light and s-polarized light. As a result, a critical dimension ("CD") difference undesirably increases in an effective image plane. In the optical system of the reference 10, a first plane mirror deflects light from a first object (e.g., a reticle), a second plane mirror deflects the light reflected by a reciprocating optical system that includes a concave mirror, and a positive lens forms an intermediate image. The intermediate image is projected onto a second object (e.g., a wafer) with a second imaging optical system. Thus, a distance from the second plane mirror to the intermediate image becomes long by forming the intermediate image via the positive lens, and a light diameter on the second plane mirror becomes large. Therefore, an influence to a quality of the image projected onto the image surface by a few flaws exited on the reflection surface can be disregarded. Moreover, an asymmetry contribution to an imaging error such as coma generated by heating to the lens is compensated by arranging the positive lens in before and after the middle image and symmetry. However, it is difficult to control reflection film properties because the incident angle upon the plane mirror is large. In other words, the light intensity difference between the p-polarized light and s-polarized light increases by the influence of the reflection film on the plane mirror, and the CD difference in the effective image plane will be increased.
On the other hand, the optical system shown in FIG. 4 of the reference 10 reflects light from a first object (e.g., a reticle) by a reciprocating optical system that includes a concave mirror, deflects light on a return path optical path of the light returned from the concave mirror of the reciprocating optical system in a direction that intersects with light on a forward path optical path of the light traveled to the concave mirror by a first plane mirror, and forms an intermediate image via a lens. The optical system deflects light from the intermediate image by a second plane mirror, and projects onto a second object (e.g., a wafer). However, the optical system only changes an arrangement of the plane mirror, without changing numerical example for the structure of the first embodiment of the reference 10, and the reference 10 does not advert about the influence to the reflection film by the incident angle upon the plane mirror. Moreover, all embodiments have a structure that arranges the positive lens between the first plane mirror and the intermediate image. Therefore, an incident angle range upon the second plane mirror increases by higher NA of the intermediate image, and a design of the reflection film on the mirror and control of forming film are difficult. An arrangement of the optical system becomes difficult by a physical interference between a marginal ray on the forward path of the reciprocating optical system and the lens according a higher NA. In addition, a distance from the first plane mirror to the intermediate image need to long, the light diameter on the first plane mirror becomes large, and light on the forward path is limited. Therefore, it is difficult to secure an enough effective imaging area. A higher first object point to secure the effective imaging area becomes a wide angle, and correcting the aberration becomes difficult. Moreover the chromatic coma aberration by the lens between the first plane mirror and the intermediate image becomes in the same direction as the chromatic coma aberration generated in the second imaging optical system. Therefore, the chromatic coma aberration increases, and it is difficult to obtain a desired imaging performance according a higher NA.

Catadioptric projection optical system, exposure apparatus having the same, device fabrication method


The present application provides an abradable bucket shroud for use with a bucket tip so as to limit a leakage flow therethrough and reduce heat loads thereon. The abradable bucket shroud may include a base and a number of ridges positioned thereon. The ridges may be made from an abradable material. The ridges may form a pattern. The ridges may have a number of curves with at least a first curve and a second curve and with the second curve having a reverse camber shape.

Generally described, the efficiency of a gas turbine engine tends to increase with increased combustion temperatures. Higher combustion temperatures, however, may create a variety of problems relating to the integrity, metallurgy, and life expectancy of the components within the hot combustion gas path and elsewhere. These problems are an issue particularly for components such as the rotating buckets and the stationary turbine shrouds positioned in the early stages of the turbine.
High turbine efficiency also requires that the buckets rotate within the turbine casing or shroud with minimal interference so as to prevent unwanted "leakage" of the hot combustion gas over the tips of the buckets. The need to maintain adequate clearance without significant loss of efficiency is made more difficult by the fact that centrifugal forces cause the buckets to expand in an outward direction towards the shroud as the turbine rotates. The bucket tips may erode, however, if the bucket tips rub against the shroud. Such erosion may cause increased clearances therebetween as well as reduced component lifetime. Other causes of leakage include thermal expansion and even aggressive maneuvering of the engine in, for example, military applications and the like.
Abradable coatings have been applied to the surface of the turbine shroud to help establish a minimum or optimum clearance between the shroud and the bucket tips, i.e., the bucket tip gap. Such a material may be readily abraded by the tips of the buckets with little or no damage thereto. As such, bucket tip gap clearances may be reduced with the assurance that the abradable coating will be sacrificed instead of the bucket tip material.
In addition to allowing for the tip-shroud contact, the use of an abradable surface as a pattern of ridges and the like thereon has been found to provide additional aerodynamic benefits in further reducing the leakage flow therethrough. Specifically, the ridges may provide direction to the mainstream flow away from the tip clearance gap. Known abradable patterns thus have been found to provide aerodynamic benefits in the reduction of the minimum tip clearance height and otherwise.
There is thus a desire for an improved abradable bucket shroud pattern so as to reduce the leakage flow through the bucket tip gap and elsewhere. Such an abradable bucket shroud pattern may be optimized for a specific bucket design in terms of the leakage flow therethrough and the heat loads thereon. Specifically, such a bucket shroud design would provide an adequate abradable shroud surface in the context of a flow reducing pattern for improved performance.


Disclosed herein is an apparatus that includes a clock generator configured to generate first, second, third, and fourth clock signals different in phase from one another, and first, second, third, and fourth clock drivers each configured to drive the first, second, third, and fourth clock signals, respectively. The first and second clock drivers are arranged symmetrically with respect to a first line extending in a first direction. The first and third clock drivers are arranged symmetrically with respect to a second line extending in a second direction. The first and fourth clock drivers are arranged symmetrically with respect to a point crossing the first and second lines.

A semiconductor device such as a DRAM (Dynamic Random-Access Memory) sometimes includes a parallel to serial conversion circuit that converts parallel read data into serial data, and a serial to parallel conversion circuit that converts serial write data into parallel data. The parallel to serial conversion circuit performs a parallel to serial conversion operation in synchronization with read clock signals different in phase from one another, and the serial to parallel conversion circuit performs a serial to parallel conversion operation in synchronization with write clock signals different in phase from one another. However, if the read clock signals or the write clock signals are generated from a clock signal for a command address, the paths of the read clock signals and the write clock signals become long. In this case, not only is current consumption large, there is also a problem that the phases of the read clock signals or the phases of the write clock signals are likely to be shifted.

This patent is subject to a terminal disclaimer.

Clock signal generator generating four-phase clock signals


A mold for vulcanizing a tire tread comprising a molding surface able to mold a tread surface of the tread of the tire and at least one bar of length L and of width W able to mold a groove in the tread. The bar comprises two lateral faces extending along the length of the bar and projecting from the molding surface and an upper face connecting the said lateral faces. The mold comprises in the bar at least two cavities respectively opening onto the two lateral faces of the bar without opening onto the upper face of this bar. These cavities overlap in the width of the bar. The mold further comprises a first element added into the bar beforehand, this first element separating the two cavities in the length of the bar.

1. Field
The present disclosure relates to the field of the manufacture of a mold for a tire comprising a plurality of cavities which are able to mold closure devices in one or more groove(s) of this tire. More particularly, the disclosure relates to the manufacture of a mold able to mold closure devices fixed to the lateral walls of the grooves.
2. Description of Related Art
Document WO 2010146180 discloses a vulcanizing mold for a tire comprising a plurality of molding elements. Each molding element is delimited by two edges in contact with two other adjacent molding elements so that once the molding elements are in contact with one another, all of these molding elements together allow all or part of the tread of the tire to be molded.
Each molding element comprises a base and a bar projecting from this base. The base is intended to mold the tread surface of the tread of the tire and the bar is intended to mold a groove in the tread of this tire, i.e. a cut of a width greater than or equal to 2 mm.
It is known that, in the contact patch in which the tread is in contact with the road surface, each groove forms a resonance tube with this road surface. This resonance tube amplifies the running noise of the tire, and this may be unpleasant for people situated inside the vehicle and/or outside this vehicle.
In order to limit the intensity of this resonant noise, it is known practice to provide the grooves with special closure devices also referred to as "flexible walls", or "flaps". These closure devices take the form of thin blades. These blades partially close off the cross section of the grooves when the tire is running on a dry road surface. When it is running on a wet road surface, the blades flex under the action of the flow of water, so that this water can be removed from the contact patch. The grip of the tire on the road surface is thus maintained even when running under severe wet conditions.
There are various types of devices for closing a groove. For example, document WO 2010063749 discloses closure devices which are fixed by their base to a bottom of a groove. It has been found that the flexibility of these devices changes over time. Thus, with tire wear, the height of these closure devices decreases, thus causing their rigidity to increase. These closure devices may therefore ultimately prevent water from circulating properly in the groove.
In order to improve the operation of the closure devices on a wet road surface, document FR2715891 has proposed closing the cross section of the groove using two closure devices belonging to one and the same transverse plane and each one covering approximately half the cross section of this groove. These closure devices are fixed respectively to lateral walls of the groove and not to the bottom of this groove. Thus, with tread wear, the region of attachment of each closure device to the associated wall of the groove decreases. The flexibility of the closure device is maintained over time, or even increased, until a certain degree of tread wear is reached.
However, in order to mold these closure devices into a groove, it is necessary to make slots in the lateral faces of a bar of a mold, it not being appropriate for these slots to open onto the upper surface of this bar. Now, creating these slots with the required degree of precision is accompanied by a great many difficulties.
FIG. 1 schematically depicts a perspective view of a known embodiment of a molding element 1 that can be used for molding a closure device fixed to a lateral wall of a groove.
The molding element 1 comprises a base 3 and a bar 5 projecting from the said base 3. The base 3 and the bar 5 are in this instance formed as one from the same substance and made of a material of the aluminium type.
More particularly, the base 3 comprises a molding surface 7 intended to mold part of the tread surface of a tire. The bar 5 for its part comprises an upper face 9 intended to mold the bottom of a groove and two lateral faces 11, just one of which is depicted here. These lateral faces 11 project from the molding surface 7 of the base 3 and extend along the length of the bar.
More specifically, the bar 5 comprises a recess 15. This recess is intended to accept raw rubber for molding a closure device in a groove of a tire. The recess 15 in this instance opens onto one of the lateral faces 11 of the bar 5 and onto a contact edge 17 of the molding element 1. By contrast, the recess 15 does not open onto the upper face 9 of the bar 5.
FIG. 2 shows an assembly of two molding elements 32a, 32b according to the embodiment of FIG. 1. More specifically, FIG. 2 is a view in cross section of this assembly on a plane substantially parallel to the molding surfaces 39a, 39b of the molding elements 1a, 1b.
Assembling the two molding elements 32a, 32b forms two cavities 33a, 33b which are offset from one another along the length of the bar 35, each cavity 33a, 33b opening respectively onto one of the lateral faces 37a, 37b of this bar 35. More specifically, each cavity 33a, 33b is formed by a recess belonging to one of the two molding elements 32a, 32b, this recess being delimited by a contact edge belonging to the other molding element 32a, 32b.
Now, such an assembly limits the design options for the closure devices. This is because with the assembly of FIG. 2, it is not possible to mold closure devices which are offset along the length of the bar and exhibit a certain overlap ("overlapping") as is notably depicted in document JP3276802, in FIG. 10 (A).

Mold for vulcanizing a tire tread, comprising at least one added element in a cord

COMPAGNIE GENERAL DES ETABLISSEMENTS MICHELIN


A handheld apparatus with touch input function is provided. The handheld apparatus includes a casing and a cover collectively defining an accommodation space for accommodating a control circuit chip and a touch-sensitive module. The touch-sensitive module includes a first and a second touch sensor set. The second touch sensor set includes separate sensor pads arranged in a column, and each sensor pad is connected to the control circuit chip through a respective trace. In a first mode, at least one of the sensor pads senses a first capacitance change thereof in response to an object positioned near or on the sidewall. In a second mode, the sensor pads are connected in parallel to form at least one sensor electrode, which cooperates with the first touch sensor set to sense a second capacitance change thereof in response to the object positioned near or on the cover.

Nowadays, smartphones with touch-screen interface have become the most popular personal mobile apparatuses. In a smartphone, a mobile operating system is used, and functions of the smartphone can be extended through installing various application programs. Furthermore, the essential functions of the smartphone such as network connection, identity authentication, multimedia presentation, digital camera and navigation make the smartphone to serve as a communication device based on a mobile node.
Please refer to FIG. 1, which is a schematic diagram illustrating a conventional smartphone. The main body 10 of the smartphone is held in one hand at its usual state as shown in FIG. 1. The display module 14 occupies the largest area of the main body 10. In addition to display function, touch input function is usually integrated to the display module 14 to provide a user interface of the smartphone.
Please refer to FIG. 2, which is a schematic diagram illustrating the interior of the conventional smartphone. The touch input function is provided by a touch-sensitive module 22 attached to a lower surface of the transparent cover 21. The touch-sensitive module 22 senses touch operations of finger(s) on an upper surface of the transparent cover 21. The touch-sensitive module 22 is bonded to the transparent cover 21 and the display module 23 by an optically clear adhesive (OCA) 24. The display module 23 may be a liquid crystal display (LCD), an organic light-emitting diode (OLED) display or other flat-panel display. Other circuit components 25 are disposed on a circuit board 26 located under the display module 23. The circuit board 26 is electrically connected to the display module 23 and the touch-sensitive module 22 through flexible printed circuit (FPC) boards 27.
The above-mentioned parts are disposed in a space defined by a lower casing 12 and the upper transparent cover 21. Related components and wires are disposed in the clearance between both sides 12S of the casing 12 and the display module 23. Therefore, light-shielding material is usually coated to hide the clearance. Further, proximity sensors 70 are disposed near both sides 12S of the casing 12 for specific sensing to enhance the user interface. However, the proximity sensors 70 additionally introduced near both sides 12S of the casing 12 need additional driver circuits, and increase complexity of the entire structure of the smartphone and production difficulty.

Touch input method and handheld apparatus using the method

PERFECT SHINY TECHNOLOGY (SHENZHEN) LIMITED


A method is provided for the integration of a low-volume liquid flow and ing system and a portable optical waveguide-based fluorescence detector for the chemical analysis of reagents in fluorescence-based reactions. The method is particularly applicable to the detection of enzyme inhibitors, modifiers, or ligands in cases where a fluorescent enzyme substrate or product exists. In a preferred embodiment, the presence and concentration of acetylcholinesterase inhibitors, such as chemical warfare nerve agents or certain insecticides, is determined by mixing aqueous samples with a dilute solution of n-methyl indoxyl acetate, and monitoring the formation of a fluorescent product (n-methyl indoxyl). The presence of an acetylcholinesterase inhibitor reduces the amount of fluorescent product formed in a given time period. The reaction product passes through a flow cell in which it is excited by the evanescent wave produced by light as the light undergoes total internal reflection within an optical rod or fiber, or by light coming out the end-face of an optical fiber or rod.

This invention relates generally to chemical analysis, and more particularly to a method for using a portable automatic sensing device for the detection of acetylcholinesterase inhibitors.
More specifically, the invention consists of the combination of a method involving liquid flow chemistry with fluorescence detection applied to the chemical analysis of very small sample volumes of acetylcholinesterase inhibitors.

Portable automatic sensor for toxic gases

The United States of America as represented by the Secretary of the Army


Technologies are generally described for protecting an edge of a container opening from material, such as container contents being moved into or out of the container, and for protecting container contents from contamination from the edge of the container opening, e.g., rust or debris at the edge.

Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Containers may be employed to store contents such as liquids, powders, or the like. The edge of a container opening may be undesirably contaminated with the contents of the container as they are moved in or out of the container. For example, a paint can may have an edge that becomes undesirably coated with paint. Subsequent application and/or removal of a paint can lid may become challenging. Also, the edge of the container opening may include foreign matter or contaminants. For example, some paint cans may tend to rust with age. One may create a painted surface using a supply of paint, and may store a color-matched sample of the paint for later "touch up" painting of the existing painted surface. However, the can used to store the color-matched sample may rust or become contaminated with debris. The rust or other debris on the paint can edge may fall into the paint, contaminating the paint and potentially leading to a poor quality "touch up" on the existing painted surface. This may be challenging, since it may be expensive, impractical, difficult, or the like to obtain a new paint sample of the correct color in a new, un-rusted can to "touch up" the existing painted surface.
The present disclosure appreciates that using containers may be a challenging endeavor in view of the potential contamination of container edges and container contents.


A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections.

1. Field of the Invention
The present invention relates to a package for a semiconductor device, and more particularly, to a package for a semiconductor device that does not require a molded body.
2. Description of the Prior Art
Semiconductor devices, especially MOSFET devices, generally desire very low package resistance (RDSon) with good thermal performance. It is also generally desirable to have simple, quick and efficient methods of packaging semiconductor devices. Thus, numerous packaging concepts and methods have been developed in the prior art.
An example of one such packaging concept involves a ball grid array (BGA). Such a concept involves an array of source, gate and drain solder balls that are connected directly to the printed circuit board (PCB). This requires a bumped die and a leadframe is used to facilitate the drain contact. Another packaging concept is commonly referred to as Flip Chip in Leaded Molded Package (FLMP), which comprises a molded leaded surface mount package where a bumped die is connected to gate and source terminals of the frame. The drain, which is the back side of the die, is exposed from the mold compound or body and is connected to the PCB via solder reflow during a standard board mounting process. Other packaging concepts use copper straps and/or wire bond technology.
These prior art concepts involve various components and may result in complicated manufacturing (packaging) processes.
The present invention provides a semiconductor device that includes a substrate and a die coupled to the substrate. Multiple solder balls are also coupled to the substrate adjacent to the die. The solder balls are substantially coplanar with a surface of the die when the semiconductor device is coupled to a printed circuit board. Thus, when the semiconductor device is coupled to a PCB, the surface of the die not coupled to the substrate serves as a direct drain connection while the substrate and solder balls serve as the source and gate connections in the instance when the semiconductor device is a MOSFET device.
In accordance with one aspect of the present invention, the substrate includes a base layer, a metal layer and an insulating layer between the base layer and the metal layer.
In accordance with another aspect of the present invention, the base layer comprises a metallized pattern and the metal layer comprises another metallized pattern or serves as a heat spreader.
In accordance with a further aspect of the present invention, the substrate is a metallized ceramic.
In accordance with yet another aspect of the present invention, the substrate comprises two layers of metallized ceramic which can facilitate attachment of two dies (silicon) on opposite faces.
The present invention also provides a method of packaging a semiconductor device that includes providing a substrate and a die. The solder, or any suitable electrically conductive interconnect in the case of MOSFET devices, is placed on at least one of the substrate and the die and the die is flipped onto the substrate. The solder balls are then placed on the substrate adjacent to the die.
Other features and advantages of the present will be understood and upon reading and understanding the detailed description of the preferred exemplary embodiments found hereinbelow, in conjunction with reference to the drawings, in which like numerals represent like elements.

Unmolded package for a semiconductor device


The present disclosure generally provides an emission treatment system for at least partial conversion of gaseous CO emissions. The exhaust gas treatment system includes various components such as a first catalyst component selected from a LNT or an oxidation catalyst for the abatement of HC and CO, which contains a catalyst composition such as a platinum group metal component impregnated into a refractory oxide material. Another component in the exhaust gas treatment system is an SCR catalyst for the abatement of NOx, which contains a catalyst composition such as a metal ion-exchanged molecular sieve and can be optionally absent when the first catalyst component is an LNT. A second oxidation catalyst for further abatement of CO is also part of the emission treatment system and includes a third catalyst composition selected from a platinum group metal component, a base metal oxide component, or combinations thereof disposed onto a carrier substrate.

Operations of lean burn engines, for example diesel engines, provide the user with excellent fuel economy due to their operation at high air/fuel ratios under fuel lean conditions. However, diesel engines also emit exhaust gas emissions containing particulate matter (PM), unburned hydrocarbons (HC), carbon monoxide (CO), and nitrogen oxides (NOx), wherein NOx describes various chemical species of nitrogen oxides, including nitrogen monoxide and nitrogen dioxide, among others.
Oxidation catalysts comprising precious metals, such as gold, platinum, palladium, rhodium, iridium, ruthenium and osmium, dispersed on a refractory metal oxide support are known for use in treating the exhaust of diesel engines in order to convert both hydrocarbon (HC) and carbon monoxide (CO) gaseous pollutants by catalyzing the oxidation of these pollutants to carbon dioxide and water. Such catalysts may be contained in diesel oxidation catalysts (DOC), which are placed in the exhaust flow path from a diesel powered engine to treat the exhaust gas stream. Typically, the diesel oxidation catalysts are prepared on ceramic or metallic carrier substrates upon which one or more catalyst coating compositions are deposited. In addition to the conversion of gaseous HC, CO and the soluble organic fraction of particulate matter, oxidation catalysts containing precious metals dispersed on a refractory oxide support may promote the oxidation of nitric oxide to nitrogen dioxide.
As is well-known in the art, catalysts used to treat the exhaust of internal combustion engines are less effective during periods of relatively low temperature operation, such as the initial cold-start period of engine operation, because the engine exhaust is not at a temperature sufficiently high for efficient catalytic conversion of noxious components in the exhaust. To this end, it is known in the art to include an adsorbent material, which may be a zeolite, as part of a catalytic treatment system in order to adsorb gaseous pollutants, usually hydrocarbons, and retain them during the initial cold-start period. As the exhaust gas temperature increases, the adsorbed hydrocarbons are driven from the adsorbent and subjected to catalytic treatment at the higher temperature.
As mentioned, oxidation catalysts comprising a precious metal dispersed on a refractory metal oxide support are known for use in treating exhaust gas emissions from diesel engines. Platinum (Pt) remains the primary platinum group metal for oxidizing CO and HC in a DOC, after high temperature aging under lean conditions. One of the major advantages of using palladium (Pd) based catalysts is the lower cost of palladium compared to platinum. However, while addition of palladium to platinum based DOCs does inhibit sintering of platinum and improve CO and HC oxidation performance after high temperature aging, having too much palladium may decrease the activity of platinum to convert paraffins and/or oxidize nitric oxide, especially when used with HC storage materials, and may also make the catalyst more susceptible to sulfur poisoning. These characteristics have typically prevented the replacement of Pt by Pd as an oxidation catalyst in lean burn operations especially for light duty diesel applications, where engine temperatures remain below 250° C. for most driving conditions.
In addition, current diesel engines utilizing new advanced combustion technologies such as Homogeneous Charge Compression Ignition (HCCI) are able to reduce engine output of NOx and particulate matter (PM) emissions by reducing the combustion flame temperature within the engine cylinder and by increasing the uniformity and mixing of the fuel charge prior to ignition. However, in the process of changing the combustion process to lower NOx and PM emissions, the overall quantity of CO and HC emissions can increase, the nature of the HCs formed can change, and the exhaust temperature may be lowered. In some instances, the CO and HC emissions from advanced combustion diesel engines is 50% to about 100% higher than the HC and CO emissions from traditional diesel engines. Furthermore, as vehicle manufacturers seek to meet long term worldwide fuel economy standards, the engine exhaust temperature is expected to decline significantly, thereby challenging the DOC to function at lower and lower temperature to oxidize CO, HC and NOx. DOC catalysts with lower light-off for CO and HC will be required.
These observations, in conjunction with emissions regulations becoming more stringent, has driven the need for developing emission gas treatment systems with improved CO and HC oxidation capacity to manage CO and HC emissions at low engine exhaust temperatures.

Zoned configuration for oxidation catalyst combinations


A thumb support is provided which both guides and limits thumb movement from the back of the hand while leaving the palm surfaces unobstructed for use. The support contains a moldable support member which can be shaped to conform to the back and sides of the thumb of the user.

The present invention relates to hand and thumb supports worn for protection and/or rehabilitation, and in particular to a moldable thumb brace which provides functional support to the thumb without obstructing the palm and impairing the ability to grasp an object by the hand.
Hand splints and similar devices for the fingers and thumb typically utilize a rigid splint which fixes the thumb or other body part in a single position and prevents any flexing or hyperextension of the splinted or supported appendage. Such rigid or fixed methods of support are modeled upon the rigid splints utilized in the setting of bone fractures, the object in setting bone fractures being complete immobilization of the limb to enable correctly aligned healing of the fracture. Such complete immobilization also is intended to protect the fractured limb and discourage its use during the healing process.
However, it is often desirable to support a sprained or strained or otherwise injured appendage, such as a finger or thumb, in a manner which does not completely immobilize the digit and which permits near normal, but guided and restrained use of the digit. Prior art devices generally do not permit such restricted and guided movement of the injured digit, but rather tend to fix the digit in a single immobilized position typical of a fractured finger or thumb splint. Furthermore, prior art supports or splints are generally of designs which obstruct the palm of the hand and the grasping surfaces of the fingers and thumb thus rendering the grasping ability substantially debilitated.
Additionally, a problem presented is that prior splints or supports are typically constructed in a generalized configuration and cannot be closely adapted to the individual size and shape of the digit to be supported. Another limitation is that flexing of the thumb or other digit of the hand is determined by the materials used and their inherent rigidity. No provision is made for the adaption of the splint or support to the abilities of the particular individual or the limitations of the particular injuries.
Therefore, it is an object of the present invention to provide a support for a thumb or other digit of the hand which permits movement of the digit in a reduced, but supported range of motion and which does not immobilize the digit.
Another object of the present invention is to provide a device for supporting and guiding movement of a thumb or other digit which does not obstruct the palm surfaces of the hand or the digits, but allows relatively unimpaired grasping of articles by the hand.
Yet another object of the present invention is to provide a support for a digit which is moldable to conform to the shape of the digit in order to guide movement in a defined direction.
Yet another object of the present invention is to provide a support for a hand digit which can be repetitively molded to conform to changes in hand dimensions or to be utilized by a second user.
Other objects and advantages of this invention will become apparent from the following description taken in connection with the accompanying drawings, wherein is set forth by way of illustration and example, an embodiment of this invention.


The invention relates to a method for arranging service management in a service management system, the method comprising: defining one or more device management commands on the basis of predetermined mapping instructions and a service management command, transmitting the device management commands to a managed device, specifying in the managed device one or more service management commands on the basis of the received device management commands, and carrying out the defined one or more device management commands.

As different data processing devices, such as mobile stations, become more complex, the significance of device management becomes more pronounced. Devices require several different settings, such as settings related to Internet access points, and setting them manually by the user is arduous and difficult. To solve this problem, for instance, device management solutions have been developed so that the administrator of a company's information system or a teleoperator can set an appropriate configuration for a device. Device management generally refers to actions by which a person typically not using a device can change the configuration of the device; for instance change the settings used by the device. In addition to device-specific settings, it is also possible to transmit user-specific data, such as user profiles, logos, ringing tones, and menus with which the user can personally modify the settings of the device, or the modification takes place automatically in connection with device management.
One of the device management standards is OMA (Open Mobile Alliance) DM (Device management), which is partly based on the SyncML (Synchronization Markup Language) protocol. For instance, a personal computer (PC) can act as a device management server in a device management protocol and a mobile station as a device management client. In terms of device management, the device management client, possibly on the basis of a triggering message from the device management server, transmits information concerning itself in a session initiation message to the device management server, and the device management server replies by transmitting its own information and server management commands. The device management client replies to these with status information, after which the server can end the session or transmit more server management commands. If the server transmits more server management commands, the client is to reply to them with status information. The server can always, after receiving status information, end the session or continue it by transmitting more server management commands. Device management can also be implemented by first transmitting queries to the user about what (s)he wishes to update, and information on the user's selections is transmitted to the server. Next, the server can in the next packet transmit the updates/commands the user desires.
As the number of functions on mobile handsets continues to grow, users find it increasingly difficult to configure their devices to be capable to connect or utilize services. As more services and software applications are implemented in mobile devices, a need for remote management can only grow.
Current device management systems enable manipulation of application and device specific configuration parameters, i.e. configuration management. In addition to configuration management, a need also exists for more sophisticated management capabilities enabling management of larger entities, for instance software management.


A fuser member for fusing thermoplastic resin toner images to a substrate has an aluminum base member and an elastomer fusing surface of a poly(vinylidenefluoride-hexafluoropropylene-tetrafluoroethylene) where the vinylidenefluoride is present in an amount less than 40 mole percent, the elastomer having been cured from a solvent solution thereof with a nucleophilic curing agent soluble in the solution and in the presence of 5 or less than 4 parts by weight of inorganic base per 100 parts of polymer, the inorganic base being effective to at least partially dehydrofluorinate the vinylidenefluoride, and an adhesive layer between the surface of said aluminum base member and the elastomer fusing surface, the adhesive layer having been cured from a solvent solution of a poly(vinylidenefluoride-hexafluoropropylene-tetrafluoroethylene) where the vinylidenefluoride is present in an amount less than 40 mole percent and from about 6 to 20 parts by weight per 100 parts by weight of said poly(vinylidenefluoride hexafluoropropylene-tetrafluoroethylene) of an amino silane represented by the formula: ##STR1## where R can be an alkyl group having 1 to 7 carbon atoms; R' can be an alkyl group having 1 to 7 carbon atoms or a polyalkoxyalkyl group of less than 7 carbon atoms; Y is an amino group or an amino substituted alkyl, or a polyamino substituted alkyl, or an alkenylalkoxy amino, or an aryl amino group of less than 15 carbon atoms, h is 1 to 3, b is 0 to 2, q is 1 or 2 and h+b=3.

In U.S. Pat. No. 5,017,432 to Eddy et al., commonly assigned to the assignee of the present application, a fuser member and fuser system are described wherein a polymeric release agent having functional groups is supplied to the surface of a fuser member which comprises a poly(vinylidenefluoride-hexafluoropropylene-tetrafluoroethylene) wherein the vinylidenefluoride is present in an amount less than 40 mole percent, a metal oxide is present in amount sufficient to interact with the polymeric release agent having functional groups to provide an interfacial barrier layer between fusing surface and the toner is substantially unreactive with the elastomer and wherein the elastomer is cured from a solvent solution thereof with a nucleophilic curing agent soluble in the solution and in the presence of less than 4 parts by weight of inorganic base per 100 parts by weight of polymer with the inorganic base being effective to at least partially dehydrofluorinate the vinylidenefluoride. U.S. Pat. No. 5,017,432 together with those patents described in the prior art section of that patent disclosure are hereby specifically and totally incorporated by reference into the instant specification. In the practice of the fuser member described in U.S. Pat. No. 5,017,432, at least one elastomeric layer is positioned between the base member and the outer layer and is typically also a poly(vinylidenefluoride-hexafluoropropylene-tetrafluoroethylene) wherein the vinylidenefluoride is present in an amount less than 40 mole percent, which is adhesively bound to an aluminum coated copper base in some instances and to an all aluminum base in other cases by an epoxy adhesive such as Thixon 300/301. Thixon is a trademark of Dayton Chemical Products Laboratories. While such a fuser member provides a relatively long life on the average having a copy count of 1.9 to 2.1 million copies for all failure modes in the Xerox 5090 printing machine, it does suffer a particular failure of the fluoroelastomer fusing surface debonding from the aluminum substrate. It has been determined that the bond between the aluminum surface and the fluoroelastomer fusing layer degrades as a function of time at the elevated temperatures involved in the fusing process which may exceed 400.degree. F. The Thixon epoxy adhesive degrades to the point where it no longer functions as an adhesive and failure is experienced with wholesale debonding of the fusing layer from the aluminum substrate in that the fusing surface may be manually peeled from the aluminum substrate.
In U.S. Pat. No. 5,049,444 to Bingham et al., entitled "Silane Adhesive System For Fusing Member" and commonly assigned to the assignee of the present application, an adhesive layer includes a copolymer of vinylidenefluoride and hexafluoropropylene and at least 20 percent by weight of a coupling agent which comprises at least one organofunctional silane and an activator. In a specific embodiment, the organofunctional silane is a mixture of about 4 parts by weight of ethenyl triethoxy silane to one part by weight of 3-(triethoxy silyl)-1-propanamine such as that available from Minnesota Mining and Manufacturing Company under the designation Dynamar 5150. This is a 6 percent mixture of the active ingredients and benzyl triphenyl phosphonium chloride curing activator in 94 percent methanol with a small amount of water. While this organofunctional silane coupling agent, when mixed with a copolymer of vinylidenefluoride and hexafluoropropylene having a relatively low molecular weight, provides a good adhesive between the base support member and the tie coat layer or elastomeric fusing surface, it is inadequate when used with the higher molecular weight fluoroelastomers such as Viton GF, a polymer of 35 mole percent vinylidenefluoride, 34 mole percent hexafluoropropylene and 29 mole percent tetrafluoroethylene. This is believed to be due to the fact that the organofunctional silane coupling agent and high molecular weight fluoroelastomer do not evenly coat the aluminum substrate, but rather provide a discontinuous (less than 50 percent of the surface is covered) layer on the aluminum substrate. This is believed to be due to the highly polar nature of the water and the alcohol which cause the relatively high molecular weight Viton GF to come out of solution, even forming clumps of the fluoropolymer and not uniformly coating the substrate.

Fuser member with an amino silane adhesive layer


A method for etching a polysilicon layer comprises the steps of providing a semiconductor wafer substrate assembly having at least first and second features therein in spaced relation to each other which define an opening therebetween. A blanket polysilicon is formed over the wafer assembly and within the opening. A patterned photoresist layer is formed over the polysilicon layer, then the polysilicon layer within the opening is etched with a first etch. Subsequent to said first etch, the polysilicon with the opening is etched with a second etch comprising a halogen-containing gas flow rate of from about 35 sccm to about 65 sccm and an oxygen-containing gas (for example HeO2) flow rate of from about 12 sccm to about 15.6 sccm.

This invention relates to the field of semiconductor assembly, and more specifically to a polysilicon etch which is particularly useful for removing polysilicon stringers.
During the manufacture of semiconductor devices such as dynamic random access memories (DRAMs), static random access memories (SRAMs), microprocessors, logic, etc., several structures are commonly formed. With reference to FIG. 1, a semiconductor wafer substrate assembly 10 is provided. The wafer assembly typically comprises a semiconductor wafer 12 having a transistor stack 14 formed thereon. With current technology, for example a 64 megabit DRAM manufactured with 0.18-micron line widths, each wafer stack comprises gate oxide 16 about 60 angstroms (xc3x85) thick, a polysilicon control gate (word line) 18 about 800 xc3x85 thick, a silicide layer 20 about 1,000 xc3x85 thick, a nitride cap 22 about 2,000 xc3x85 thick, and a pair of oxide spacers 24. The spacing between each stack (between adjacent spacers) is about 1,300 xc3x85. Such a structure is easily manufactured by one of ordinary skill in the art.
FIG. 1 further depicts a doped blanket polysilicon layer 26, for example about 3,500 xc3x85 thick which is provided to form a landing pad for a contact. A patterned photoresist mask 28 is formed over the polysilicon layer 26 and an anisotropic polysilicon etch is performed to define the landing pad. To etch the polysilicon layer depicted, a conventional etch comprises 90 standard cubic centimeters (sccm) Cl2 and 10 sccm NF3 at a pressure of 300 millitorr (mTorr) and 100 watts power to clear the majority of the exposed polysilicon, then the pressure is increased and SF6 is added toward the end of the etch in an attempt to clear any residual material from the exposed regions.
A desired resulting structure is depicted in FIG. 2 which depicts a clean removal of the exposed polysilicon and no undercutting of the resist. However, with severe topology having narrow spaces between the relatively high transistor gate stacks, a more common result is depicted in FIG. 3. Stringers 30 can form in the recesses as it is difficult to clear all the polysilicon from narrow, deep spaces found with high-density semiconductor devices, even with the increase in pressure and addition of SF6 in the conventional etch described above. Stringers, which form especially in corners, are well known in the art to cause shorting and result in malfunctioning semiconductor devices.
Another method used in an attempt to reduce stringers includes performing a series of alternating anisotropic and isotropic etches, with the anisotropic etches removing the polysilicon in a substantially vertical direction and the isotropic etches removing the polysilicon in both horizontal and vertical directions. One problem with this method is that the isotropic etches undercut the photoresist 28 and narrow the width of the polysilicon feature 26. Thus the critical dimension (CD) of the polysilicon feature is wider than would be required if the photoresist was not undercut, and thus the alignment tolerance is reduced. For example, with a device using 0.18 micron line widths a typical undercut is about 0.03 microns on each side (0.06 microns total). Thus the feature must be patterned for a 30% undercut tolerance. The additional space required for this allowance is a concern especially as the number of features on the device increases.
As device generations progress, the spaces between transistor stacks will decrease thereby exacerbating the problem of remaining stringers. A method which removes polysilicon, and particularly which removes stringers from severe topology, would be desirable.
The present invention provides a new method which reduces problems associated with the manufacture of semiconductor devices, particularly problems associated with etching polysilicon in narrow, deep openings associated with severe topology. In accordance with one embodiment of the invention, a semiconductor wafer substrate assembly is provided having adjacent structures which form an opening such as a trench or recess. A layer of polysilicon is formed over the wafer substrate assembly and within the opening, and a patterned photoresist layer is formed over the blanket polysilicon. An etch is performed using one of several embodiments of an inventive etch described in detail below. The inventive etch improves removal of the polysilicon from the opening and reduces the likelihood of stringers remaining after the etch.
Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.

Polysilicon etch useful during the manufacture of a semiconductor device