An opening is formed in the center of a base on which an input/output electrode pattern is formed. Meanwhile, a plurality of bumps are formed on two opposing sides of an active element surface of the semiconductor integrated circuit so as to mount the semiconductor integrated circuit in the center of the opening. The semiconductor integrated circuit is connected to the electrode pattern on the base through the plurality of bumps by ultrasonic bonding. In this way, a small and thin piezoelectric device which has superior bonding characteristics of the semiconductor integrated circuit and the base, which are subjected to flip-chip bonding, and which endures mechanical shock, thermal stress, etc., can be obtained at reduced cost.

1. Field of the Invention
The present invention relates to a piezoelectric device in which a semiconductor integrated circuit and a piezoelectric resonator element are included in a package, and to a method for manufacturing the same.
2. Description of Related Art
In recent years, hard disk drives (HDD), mobile computers, information apparatuses such as IC cards and portable communication apparatuses such as cellular phones, phones for automobiles have undergone dramatic miniaturization. Accordingly, piezoelectric devices such as piezoelectric oscillators, voltage-controlled oscillators (VCXO), temperature-compensated oscillators (TCXO), SAW oscillators, real time clock modules for use in these apparatuses are also required to be smaller and thinner. Also, surface-mounting type piezoelectric devices capable of being mounted on both sides of the circuit board of the device are desired.
An example of a conventional piezoelectric device will be explained using a quartz crystal oscillator shown in structural diagrams of FIGS. 16(A) and 16(B), the quartz crystal oscillator using a semiconductor integrated circuit of single-chip type having an oscillating circuit and an AT-cut quartz crystal resonator as a piezoelectric resonator element.
In the conventional quartz crystal oscillator in FIGS. 16(A) and 16(B), an IC chip 101 having an oscillating circuit is bonded and fixed by a conductive adhesive, etc., to the bottom face of a base 102 formed of a ceramic insulating substrate, is electrically connected by Au wire-bonding lines 103 to input/output electrodes 104 at the external periphery of the bottom face of the base 102. The input/output electrodes 104 are metallized by metal such as tungsten (W), molybdenum (Mo) and are plated in multiple layers by Ni plating and Au plating, etc. More specifically, a plurality of electrodes 108 are provided in the IC chip 101 and the electrodes 108 are electrically connected to the above-described input/output electrodes 104, etc., by the wire-bonding lines 103.
A rectangular-shaped AT-cut quartz crystal resonator 105 is electrically connected to a mounting portion 106 of the base 102 and is fixed thereto by a conductive adhesive or the like. A plated layer at the top portion of the base 102 and a metallic lid 107 are connected by melting a metallic cladding material such as solder formed on the lid 107 at a high temperature so as to provide a hermetic seal, while maintaining an N2 (nitrogen) atmosphere or to a vacuum atmosphere in the inner portion.
The above-described conventional quartz crystal oscillator requires an area around the IC chip 101 for wiring the Au wire-bonding lines 103, and a sufficient height in the direction of the package thickness must be secured to accommodate the loops of the Au wire-bonding lines 103. Also, a gap must be provided between the Au wire-bonding lines 103 and the AT-cut quartz crystal resonator 105. Such a configuration prevents further miniaturization of quartz crystal oscillators.
Objects of the present invention are to solve the above-described problems and to provide at reduced cost a small and thin piezoelectric device, such as a quartz crystal oscillator, which can withstand mechanical impacts and has a thickness of 1 mm or less, and to provide a method for manufacturing the piezoelectric device.
One exemplary embodiment of the present invention is a piezoelectric device including a semiconductor integrated circuit and a piezoelectric resonator element both included in a package, wherein an opening is formed in the center of a base provided with an input/output electrode pattern, the semiconductor integrated circuit is mounted in the center of the opening, and the semiconductor integrated circuit is connected to the electrode pattern on the base through a plurality of bumps.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, the plurality of bumps formed on the semiconductor integrated circuit are formed at regular intervals on the center portion of an active element surface of the semiconductor integrated circuit.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, the plurality of bumps formed on the semiconductor integrated circuit are concentrically formed about the center of an active element surface of the semiconductor integrated circuit.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, a dummy bump is formed on the active element surface of the semiconductor integrated circuit.
In another exemplary embodiment of the present invention in the piezoelectric device described above, the dummy bump formed on the semiconductor integrated circuit is connected to the electrode pattern on the base.
In another exemplary embodiment of the present invention, the piezoelectric device described above further includes a layered part, which surrounds the semiconductor integrated circuit, for mounting the piezoelectric resonator, the layered part including at least two layers, including a first layer and a second layer, wherein an opening of the first layer is formed to be larger than an opening of the second layer.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, each of the plurality of bumps formed on the semiconductor integrated circuit is shaped to have two levels, one having a diameter 0.8 to 0.9 times and the other having a diameter 0.4 to 0.45 times the length of a side of an opening in a pad provided on an active element surface of the semiconductor integrated circuit.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, the base may consist of a ceramic composite substrate.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, each of the plurality of bumps formed on the semiconductor integrated circuit is an Au bump.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, a protrusion is formed in at least one side wall of the base facing the side of the semiconductor integrated circuit.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, the protrusion is formed in each of the side walls of the base facing the two sides along the longitudinal direction of the semiconductor integrated circuit.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, the protrusion formed in the side wall of the base has substantially the same height as, or is higher than, the semiconductor integrated circuit.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, a gap between the protrusion formed in the side wall of the base and the semiconductor integrated circuit is set to a range between 0.05 and 0.15 mm.
Another exemplary embodiment of the present invention is a piezoelectric, device including a semiconductor integrated circuit and a piezoelectric resonator element included in a package, wherein an opening is formed in the center of a base provided with an input/output electrode pattern, a plurality of bumps are formed at two opposing sides of an active element surface of the semiconductor integrated circuit, the semiconductor integrated circuit is mounted in the opening, and the semiconductor integrated circuit is connected to the electrode pattern of the base through the plurality of bumps.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, the plurality of bumps formed on the semiconductor integrated circuit are formed at regular intervals at the center portion of the active element surface of the semiconductor integrated circuit.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, a dummy bump is formed on the active element surface of the semiconductor integrated circuit.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, the dummy bump formed on the semiconductor integrated circuit is connected to the electrode pattern on the base.
In another exemplary embodiment of the present invention, the piezoelectric device described above, further includes a layered part on which the piezoelectric resonator is mounted and which surrounds the semiconductor integrated circuit, the layered part including at least two layers including a first layer and a second layer, wherein an opening of the first layer is formed to be larger than an opening of the second layer.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, each of the plurality of bumps formed on the semiconductor integrated circuit is shaped to have two levels, one having a diameter 0.8 to 0.9 times and the other having a diameter 0.4 to 0.45 times the length of an opening in a pad provided on the active element surface of the semiconductor integrated circuit.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, the base includes a ceramic composite substrate.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, the plurality of bumps formed on the semiconductor integrated circuit are Au bumps.
Another exemplary embodiment of the present invention is a piezoelectric device including a semiconductor integrated circuit and a piezoelectric resonator element included in a package, wherein an opening is formed in the center of a base provided with an input/output electrode pattern is formed, a plurality of bumps are formed at two opposing sides of an active element surface of the semiconductor integrated circuit, the semiconductor integrated circuit is mounted in the center of the opening, and the semiconductor integrated circuit is connected to the electrode pattern through the plurality of bumps by ultrasonic bonding.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, a vibration direction of ultrasonic waves applied to the semiconductor integrated circuit is perpendicular to the two opposing sides of the active element surface of the semiconductor integrated circuit at which the plurality of bumps are formed.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, a printing direction of the electrode pattern on the base and a vibration direction of ultrasonic waves applied to the semiconductor integrated circuit are the same.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, each of the plurality of bumps formed on the semiconductor integrated circuit is shaped to have two levels, one having a diameter 0.8 to 0.9 times and the other having a diameter 0.4 to 0.45 times the length of an opening in a pad provided on the active element surface of the semiconductor integrated circuit.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, each of the plurality of bumps formed on the semiconductor integrated circuit is shaped to have two levels, one being 80 to 90 xcexcm in diameter and 30 to 35 xcexcm in height, and the other being 40 to 45 xcexcm in diameter and 30 to 35 xcexcm in height.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, the base consists of a ceramic composite substrate.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, the plurality of bumps formed On the semiconductor integrated circuit are Au bumps.
In another exemplary embodiment of the present invention, in the piezoelectric device described above, the longitudinal direction of the electrode pattern on the base and a vibration direction of-ultrasonic waves applied to the semiconductor integrated circuit are the same.
In another exemplary embodiment of the present invention, the piezoelectric device described above includes the semiconductor integrated circuit and the piezoelectric resonator element in included in the package, wherein a vibration direction of ultrasonic waves for ultrasonic bonding and for forming bumps on the semiconductor integrated circuit and a vibration direction of ultrasonic waves for performing ultrasonic bonding of the semiconductor integrated circuit to the package are different from each other.
Another exemplary embodiment of the present invention is a method for manufacturing a piezoelectric device including a semiconductor integrated circuit and a piezoelectric resonator element included in a package, the method may include: a step of forming a metallic bump on the semiconductor integrated circuit; a step of connecting the semiconductor integrated circuit on which the metallic bump is formed to the base by ultrasonic bonding; a step of detecting a height direction of the semiconductor integrated circuit during the ultrasonic bonding; a step of mounting the piezoelectric resonator element; and a step of hermetically sealing a metallic lid to the base.
Another exemplary embodiment of the present invention is a method for r manufacturing a piezoelectric device including a semiconductor integrated circuit and a piezoelectric resonator element included in a package, the method may include: a step of forming a metallic bump on the semiconductor integrated circuit; a step of connecting the semiconductor integrated circuit on which metallic bump is formed to the base by ultrasonic bonding; a step of detecting a height direction of the semiconductor integrated circuit during the ultrasonic bonding step; a step of filling an underfill material around the semiconductor integrated circuit so as to cover the entire semiconductor integrated circuit including a rear surface of the semiconductor integrated circuit; a step of mounting the piezoelectric resonator element; and a step of hermetically sealing a metallic lid to the base.

Piezoelectric device and method for manufacture thereof


A safety catheter insertion device configured to automatically retract a needle cannula following insertion of a catheter assembly and to inhibit release of the catheter assembly from the safety catheter insertion device until the needle cannula has been retracted for the purpose of inhibiting inadvertent needle sticks. The safety catheter insertion device including an advancement arm slidably coupled to a needle housing assembly and configured to shift between a first position in which a needle cannula traverses through a catheter hub coupling portion of the advancement arm to inhibit release of a catheter assembly, and a second position in which one or more tabs of the advancement arm interact with one or more retention arms of the needle housing assembly to enable a biasing mechanism to shift the needle assembly to a proximal position and enable release of the catheter assembly from the safety catheter insertion device.

Intravenous (IV) therapy is a versatile technique used for the administration of medical fluids to and withdrawal of bodily fluids from patients. IV therapy has been used for various purposes, such as the maintenance of blood and electrolyte balance, the transfusion of blood, the administration of nutritional supplements, chemotherapy, and the administration of drugs and medications. These fluids, collectively referred to herein as medicaments, may be administered intravenously by injection through a hypodermic needle, or intermittently or continuously by infusion using a needle or catheter. A common intravenous access device utilized by clinicians is the Peripheral Intravenous Catheter (PIVC).
A PIVC is made of a soft, flexible plastic or silicone, generally between fourteen to twenty-four gauge in size. In the conventional venipuncture procedure, a catheter is inserted into a vein in the patient's hand, foot, or the inner aspect of the arm or any vein in the body that will accept an IV catheter. Typically PIVCs are "over the needle" catheters, where a catheter is coaxially placed over an introducer needle of an intravenous catheter insertion device. In order to properly place the catheter into the patient's vein, the introducer needle is used to puncture the skin, tissue, and vein wall to provide a path for placement of the catheter into the vein.
Placement of the catheter generally includes preparation of a biological site of the patient. Often a tourniquet is applied proximal to the biological site and a variety of techniques can be used to dilate the patient's vein. While wearing disposable gloves, the clinician cleanses the biological site and a vein is retracted or anchored by placing a thumb over the vein about fifty to seventy five mm distal to the site. The introducer needle and catheter are introduced into the vein by inserting a beveled sharpened tip of the introducer needle into the vein at about a twenty to thirty degree angle, with the bevel facing up in order to pierce one wall of the vein. The catheter thus rides with the introducer needle through the skin, tissue, and vein wall into the patient's vein.
Various catheter insertion devices have been developed to provide a needle for catheterization. One such example of this type of catheter insertion device is marketed by Smiths Medical ASD, Inc. of St. Paul, Minn., under the TELCO and INTUITIV trademarks, and are described in U.S. Pat. No. 8,257,322 and U.S. Pat. Publ. Nos. 2011/0319838; and 2017/0095617, the contents of which are incorporated by reference herein. In other cases, the catheter insertion device provides a safety needle assembly that functions to house the sharpened tip of the needle to reduce the likelihood of an inadvertent needle stick. Examples of this type of catheter insertion device are marketed by Smiths Medical ASD, Inc. under the PROTECTIV and VIAVALVE trademarks, and are described in U.S. Pat. Nos. 5,000,740; 7,736,342 and U.S. Pat. Publ. No. 2016/0220791, the contents of which are incorporated by reference herein.
To finish placement, the introducer needle and catheter are lowered towards the skin to decrease the entry angle, and the catheter is advanced slightly into the vein. Once the catheter is satisfactorily positioned within the vein, the introducer needle is typically withdrawn from inside the catheter, and the connection between the catheter and the intravenous catheter device is loosened, so that the catheter can be advanced further into the vein as desired. The catheter can then be secured in place on the biological site by adhesive tape, while the intravenous catheter insertion device is properly disposed of in a sharps container.
It is well-known that an accidental needle stick from an introducer needle that has been in contact with a patient's blood and/or other bodily fluids, presents a risk of the transmission harmful contaminants and/or infectious diseases, including AIDS, hepatitis and other blood-borne illnesses. Because of this threat, attempts have been made to shield the sharpened tip of the introducer needle prior to release of the catheter from the catheter insertion device. However, further improvements could be made to enable a smooth release of the catheter from the catheter insertion device in a way that reduces or eliminates the risk of an inadvertent needle stick. Particularly, some of the safety features of previous attempts require cumbersome or two-handed manipulations to activate. Accordingly, Applicants of the present disclosure have identified a need for an intravenous catheter insertion assembly that addresses these concerns.


The present invention provides for an improved access, control and monitoring system for a facility with multiple apparatus that are activated by the customer. It provides a consolidated means to control the activation of each apparatus and interface with the customer. It provides a consolidated means to configuration operations on the facility and a consolidated means to record activities occurring at the facility. It provides for system reconfiguration and review of activity at the site or from a remote location and can automatically notify a remote site on the occurrence of a preset event.

The present invention relates to self service equipment generally found in laundromats and self service car wash facilities. Typically, a customer receives access to the various apparatus such as a washer, dryer or car wash equipment in these facilities by depositing money into each particular apparatus. Once sufficient money is deposited, the customer receives a specific time cycle or machine cycle from, for example, the washer, dryer or car wash. Alternatively, he might purchase a product from a vending machine on the premise.
A typical self service car wash facility comprises a single equipment room and several car wash bays. Each bay will have a money acceptor, wash function selector, high pressure wand and a foaming brush. To wash his car the customer first parks his car in one of the wash bays. The customer then deposits the required amount of money to start the wash cycle. Once the wash cycle is started, the customer can select any of the wash functions provided such as degrease, presoak, soap, foaming brush, rinse or wax. Once a wash function has been selected, the customer receives that specific service. While a function such as soap is selected, hot-high pressure water with a soap additive is dispensed from the high pressure wand. Using the high pressure wand, the customer applies the soap to his car. The customer continues to receive the function he selected until he selects another service or his wash cycle time expires. Regardless of the wash function selected, the customer receives the same total wash cycle time. Therefore all wash functions have the same cost per unit time. At any time during the wash cycle the customer can deposit additional money to add time to his wash cycle.
A typical laundromat comprises washers, dryers and dispensing machines. When the customer enters a sufficient amount of money to turn the apparatus on, it starts a machine cycle. In the case of a dryer a machine cycle is a specific drying time, for a washing machine it is a washing cycle, for a dispensing machine it is the dispensing of a product. The amount of money required to activate the apparatus is preset at the money accumulator and the time given with a dryer is preset at the dryer timer.
At some self service facilities the apparatus are activated by tokens rather than money. In these instances the customer can purchase tokens from a dispensing machine or a facility operator. These tokens have a specific redemption value in the various apparatus in the facility. By depositing these tokens in a token acceptor at a particular apparatus, the customer receives a product or service. These tokens can activate the apparatus by mechanical or electronic means
In addition to the accumulators and timers associated with each apparatus, there are typically mechanical or electronic counters on each apparatus in the facility to audit the total money and or tokens deposited or the total number of cycles activated on each apparatus. The mechanical or electronic counters are typically overlaid onto the existing equipment. Since these counters are not required to operate the system, they can be disconnected, thereby defeating their intended purpose.
These presently available activation and monitoring systems have several drawbacks. First, the amount of money or number of tokens required to activate each apparatus must be manually preset at each accumulator individually. Second, in the case of a time cycle apparatus, the amount of time given for each activation must be manually preset at each timer individually. These timers do not allow price differentiation for the various services provided at a self service car wash bay. Third, the audit counts used to verify that the operators are accurately collecting all of the money must be manually tabulated. These audit counts can also be defeated without disabling the car wash service. Fourth, the owner/operator must manually tabulate statistical information on the use of various apparatus at the facility. Fifth, the operator must visit the facility to determine if operator service is required to repair broken equipment, refill chemicals, and remove or refill money and or tokens. Sixth, the money and or tokens are housed in each machine and they must be protected from theft or vandalism at each apparatus with a money vault or other protection device. The presence of the money at each site significantly increase the degree of vandalism and damage to these devices. Seventh, the facilities operator must collect the money and or tokens from each machine individual. In the case of the self service car wash bay, the collection of the money from each wash bay can present a significant personal exposure.


At least one or more dark current reducing layers having a quantum well structure are provided at an end portion in a stacking direction of an infrared detecting section in which quantum dot layers are stacked.

1. Field of the Invention
The present invention relates to an infrared detector including quantum dot layers, and particularly relates to an infrared detector which realizes a reduction in dark current.
2. Description of the Related Art
In recent years, a quantum dot infrared photo detector (QDIP), which uses a quantum dot structure as an infrared absorbing section has attracted much attention as an infrared detector.
In the quantum dot infrared photo detector, by exciting an electron located at a conduction-band quantum level in an InAs quantum dot sandwiched between i-type GaAs layers by infrared light incident from the outside and catching it as a current, that is, a photocurrent, the infrared light is detected.
Quantum dots composing the QDIP are formed by a self-formation method in a molecular beam epitaxial apparatus, and therefore they are distributed in a plane perpendicular to a growth direction. Note that to increase the efficiency of detecting infrared light, in usual use, layers each including quantum dots are stacked in plural layers, for example, eight layers (See Journal of applied Physics, Vol. 92, No. 12, pp. 7462-7468, 15 Dec. 2002, for example).
FIG. 18 is a conceptual sectional view showing an example of a conventional QDIP. In this example, an n-type GaAs bottom electrode layer 52 is formed on a semi-insulating GaAs substrate 51, and quantum dot layers 53 are stacked approximately in 6 to 20 cycles (layers) on the n-type GaAs bottom electrode layer 52. Each of the quantum dot layers 53 is constituted by embedding plural InAs quantum dots 55 in an i-type GaAs layer 54. Further, an n-type GaAs top electrode layer 56 is formed on the uppermost quantum dot layer 53. Furthermore, electrodes 57 and 58 made of AuGe/Ni/Au are respectively formed on the n-type GaAs bottom electrode layer 52 and the n-type GaAs top electrode layer 56. Such a stacked structure can be obtained if the n-type GaAs bottom electrode layer 52, the quantum dot layers 53 approximately in 6 to 20 cycles, and the n-type GaAs top electrode layer 56 are formed in sequence on the semi-insulating GaAs substrate 51 and thereafter partially etching the n-type GaAs top electrode layer 56 and the quantum dots layers 53 so as to expose the n-type GaAs bottom electrode layer 52.
Next, the operation of the conventional QDIP shown in FIG. 18 will be described.
FIG. 19 is a diagram showing a conduction-band edge profile when no bias is applied to the conventional QDIP shown in FIG. 18. When no bias is applied, no impurity is added to the stack of the quantum dot layers 53, so that electrons are supplied from the n-type GaAs bottom electrode layer 52 and the n-type GaAs top electrode layer 56. However, quantum levels (a ground level 61 and an excited level 62) formed in the InAs quantum dot 55 is located at energy levels lower than a conduction-band edge of GaAS, so that the supplied electrons are relaxed to the quantum levels 61 and 62.
Since Fermi energy Ef is defined to be equal to energy at which the proportion of occupation of electrons in some state reduces to half, in this case, the ground level 61 corresponds to the energy.
When a system is kept in thermal equilibrium, the Fermi energy Ef is fixed in the entire system. Hence, conduction-band edges of the InAs quantum dots 55 rise such that conduction-band edges of the electrode layers 52 and 56, which are at a Fermi energy level, and the ground levels 61 of the InAs quantum dots 55 substantially match each other.
However, in the quantum dot layers 53 located near the n-type GaAs bottom electrode layer 52 and the n-type GaAs top electrode layer 56, excessive electrons are supplied from the electrode layers 52 and 56, so that the Fermi energy reaches the excited level 62. As a result, the rise of the conduction-band is small.
FIG. 20 is a diagram showing a conduction-band edge profile when a bias is applied to the conventional QDIP shown in FIG. 18. Here, it is assumed that an electric field is applied uniformly to the stack of the quantum dot layers 53. When a bias is applied, a difference in potential applied by a power source 59 exists between a pair of electrodes 57 and 58, and hence if infrared light is irradiated from the outside to excite electrons, these electrons flow between the n-type GaAs bottom electrode layer 52 and the n-type GaAs top electrode layer 56. Namely, a photocurrent is generated.
On the other hand, even in a state where the infrared light is not irradiated, due to a difference in potential applied between the n-type GaAs bottom electrode layer 52 and the n-type GaAs top electrode layer 56, an electron 63 located in the low-potential side electrode layer (n-type GaAs bottom electrode layer 52) flows between the electrode layers 52 and 56. Namely, the electron 63 which has flowed from the low-potential side electrode layer (n-type GaAs bottom electrode layer 52) regards a conduction-band edge of the i-type GaAs layer 54 which is several layers away therefrom as the highest barrier, and when the electron 63 goes over the conduction-band edge, a dark current flows. This dark current flows also when the infrared light is irradiated.
Since the performance of the photo detector is mostly dependent on the ratio of a photocurrent to a dark current, it is a requirement to reduce the dark current in order to improve the performance of the detector.
From the above-described mechanism, the higher the barrier, the smaller the dark current becomes, and therefore, heightening the barrier is a means of reducing the dark current. Hence, it is thought that if the barrier is heightened by embedding the InAs quantum dots 55 in a semiconductor layer such as an AlGaAs layer, which has a larger band gap than the i-type GaAs layer 54, in place of the i-type GaAs layer 54, the reduction in dark current becomes possible.
However, although in the growth of quantum dots, a growth temperature of about 500° C. is required, the AlGaAs layer is generally grown at about 600° C. Therefore, in terms of the optimization of the growth condition and so on, it is difficult to use the AlGaAs layer as the layer in which the quantum dots are embedded.


Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

The present invention is generally directed to a system for processing digital data in which data are processed in portions that are smaller than the word size, the size of the portions being optimally selected to maximize throughput efficiency, as that term is defined herein. More particularly, the present invention is directed to digital signal processing systems which are neither fully parallel nor fully serial in their architectures, but rather exhibit an intermediate architecture selected on the basis of optimizing a measure of performance based upon speed and circuit size.
The present applicants have discerned that in any given digital signal processing problem, optimal results in terms of throughput and chip real estate actually require an architecture which draws both upon serial and upon parallel computational philosophies. To this end, applicants have proven that, in general, optimal design requires the utilization of digit serial architectural circuit designs. In these designs, bits are grouped together in digits having 2, 3, 4, 5, 6 or more bits and these "parallel" digits are processed in serial fashion. Thus, in digit serial architecture, a data word is divided into a number of digits of fixed, but initially arbitrary width. Arithmetic data flow within the circuit is over digit-wide signal lines and is propagated with the least significant digit first. Thus, data arrives serially at each operator, one digit at a time. Arithmetic and logic operators perform digit-serial calculations on this data and provide digit-serial output.
In fully parallel (or word-parallel) digital signal processing architectures, all bits of a data word, n in number, are processed simultaneously by the circuitry. This architecture has the advantage of relatively high processing speed, but suffers from the disadvantage that fully parallel architectures for each bit of a word replicate circuit elements and interconnections between elements, each of which replications tends to consume a commensurate additional amount of die area in a monolithic integrated circuit. Interconnections between monolithic integrated circuits for parallel data are multi-wire and a considerable number of interconnection terminals or "pins" must be provided for each integrated circuit to implement those multi-wire connections.
On the other hand, fully serial digital signal processing architectures process one bit at a time in each clock cycle. These circuits have the advantage of simplicity, ease of design and, most importantly, they require minimal amounts of circuitry and so take up only a small amount of die area in a monolithic integrated circuit. Also single-wire interconnections between monolithic integrated circuits are made possible by serial digital signals, which is important when the restrictions upon the number of interconnection terminals or "pins" available for such connections are pressing. Within a monolithic integrated circuit the single-conductor interconnections between circuit elements tend to appropriate less chip area than the multi-conductor interconnections between elements that characterize fully parallel architectures.
Serial architectures also tend to exhibit a substantial amount of latency. That is, because of the serial design, a relatively large number of clock cycles can elapse between the time that an input bit is received and the time that output information related to the input bit is provided by the circuitry. However, circuit speed is generally sufficiently fast once the latency period has elapsed. Also, when a number of serial computations are to be performed in a data-flow pipeline, later computations can begin before earlier ones finish, which tends to reduce overall latency in the system. Accordingly, throughput is not so low as to preclude utilization of this architecture. The main advantage of serial computation is the need for only a small area for the processing elements and their electrical interconnections. The drawback, however, is that throughput is often lower than otherwise desired. Equivalent throughput can often be approached by more traditional non-pipelined Von Neumann architectures.
A widely used fully serial architecture employs bit-serial signals in which a serial stream of bits describes a succession of data words bit by bit, in order of increasing significance, where those data words represent two's complement numbers. This serial stream of data bits is accompanied by a signal indicating when one data word finishes and another commences, which signal can be a signal that is a ONE when the most significant bit of a data word occurs in the serial stream of data bits and that is otherwise a ZERO.
Data-flow pipeline architectures are recognized as being appropriate to the implementation of a large class of algorithms such as those that appear in digital signal processing applications. There have been two major approaches to data flow architecture, namely fully parallel and fully serial implementations. These architectures are discussed broadly above. Both of them have been studied extensively.
Many algorithms, especially in the areas of digital signal processing and graphics applications, have a constant throughput and can be performed with a constant latency. These algorithms are suitable for direct implementation in hardware using pipelined data-flow architectures. Unfortunately, many algorithms require more operations, and hence more individual operators than can be accommodated on a single very large scale integrated circuit (VLSI circuit) using fully parallel arithmetic or logic. On the other hand, bit-serial systems often do not provide a sufficiently high throughput. Furthermore, the structure of many algorithms makes it difficult to avoid these problems by decomposing the data processing so as to dispose different portions of the circuitry on separate integrated circuits.
Fully-parallel computational elements have been one of the main objects of study in computer arithmetic. Even with the advent of VLSI, fully-parallel computational elements are not well suited to data-flow architectural treatment, however, because their replicated digital hardware causes a tendency towards excessive size (as measured with respect to utilization of chip area). Furthermore, the multi-conductor interconnections within an integrated circuit are difficult to route unless the die size is allowed to be larger than one would wish.
Nonetheless, much work has been done on pipeline optimization for flow graphs of parallel computational elements. These aspects have been described in the works of Leiserson and others. These works include Digital Circuit Optimization by C. E. Leiserson, F. M. Rose and J. B. Saxe (MIT Report 1982), Optimizing Synchronous Systems by C. E. Leiserson and J. B. Saxe (Proceedings of the 22nd Annual Symposium on the Foundations of Computer Science, 1981), and in Models for VLSI Circuits by F. M. Rose (MIT Master's Thesis, 1982). Work on pipeline optimization for the flow graph organization of parallel computational elements is also described in the article Sehwa: A Program for Synthesis of Pipelines by Nohbyung Park and Alice Parker (IEEE Proceedings of the 23rd Design Automation Conference, 1986). Usually, however, parallel computational operators are used in a different architecture where they are time shared. Sharing of the operators decreases the throughput of the circuit, however. For example, see the article The VLSI Design Automation Assistant Prototype System by T. J. Kowalski and D. E. Thomas (Proceedings of the 20th Design Automation Conference, June 1983, pages 479-483).
Bit-serial computational models have also received attention. In particular, Jackson et al. and later Lyon have proposed a methodology which has essentially been followed for the design of at least three "silicon compilers". In this regard, see An Approach to the Implementation of Digital Filters by Leland B. Jackson, James F. Kaiser and Henry S. McDonald (IEEE Transactions on Audio Electronics, Vol. AU-16, No. 3, September 1968, pages 413-421) and the article A Bit-Serial VLSI Architectural Methodology for Signal Processing by Richard F. Lyon (VLSI 81, Academic Press, 1981).
In connection with fully-parallel computation in data flow architectures, a technique known to designers (particularly those engaged in the design of digital filters) is to employ plural-path networks for "plural-phase" or "polyphase" data processing. See the M. G. Bellanger, G. Bonnerot and M. Coudrese paper Digital Filtering by Polyphase Network Application to Sample Rate Alteration and Filter Banks. (IEEE Transactions Acoustics and Speech Signal Processing, Vol. ASSP-24, No. 2, pages 109-114, April 1976). See also pages 79-98 of the R. E. Crochiere and L. R. Rabiner book Multirate Digital Signal Processing, copyright 1983 by Prentice-Hall, Inc., Englewood Cliffs, N.J. 07632. In plural-phase data processing a stream of digital words supplied at an original sample rate is considered to comprise a succession of cycles, each cycle containing a plurality p in number of successive words. The p words in each cycle are considered as separate phases of the cycle. These phases may be identified by the consecutive ordinal numbers zeroeth through (p-1).sup.th assigned in accordance with occurrence of the words representative of those phases in the cycle. Each word phase is used to form a separate sample stream, the sample rate of which is one-p.sup.th that of the original sample rate; and calculations are performed at the lower sample rate on each of the sample streams. The results of these plural-phase calculations are then combined to generate results at the original sampling rate. Plural-phase data processing permits a relatively high throughput rate for a system, while calculations can be performed at reduced rates.
Another technique that is used by digital circuit designers to slow the rates at which data processing needs to be done is a procedure known as "banking". An operator that is to process a stream of data at a higher throughput rate is simulated by parallelly processing segments of that data stream in a plurality, p in number, of operators operating at a lower throughput rate one-p.sup.th as fast as the higher throughput rate. Successive segments of the data streams are displaced one sample word from each other in the banking procedure. When banking is employed in transverse filtering, each segment of the data stream spans the number of sample words in the filter kernel. The same filter kernel weights each segment of data to determine each successive sample word of filter response, and the component filter responses parallelly generated at the lower throughput rate are then sequentially polled at the higher throughput rate to supply the complete filter response at that higher throughput rate.
The present invention is particularly useful to those designers who employ software and hardware tools generally described as being "silicon compilers". These tools permit designers to specify arithmetic and logical functions in a relatively high level language, such as C or FORTRAN or a special hardware description language, and permit them to use the silicon compiler system to generate a set of masks which are employed in the fabrication of VLSI circuits that operate to carry out the function specified. For example, such silicon compilers are described in VLSI Signal Processing: A Bit-Serial Approach by Peter Denyer and David Renshaw (Addison-Wesley Publishing Company, Inc., Reading, Mass., 1985). Still other relevant material pertaining to silicon compilers may be found in Digit-Pipelined Arithmetic as Illustrated by the Paste-Up System: A Tutorial by Mary J. Irwin and Robert M. Owens (Computer, April 1987, pages 61-73). Other relevant material concerning silicon compilers may be found in the article Custom Design of a VLSI PCM-FDM Transmultiplexor from System Specification to Circuit Layout Using a Computer-Aided Design System by Rajeev Jain et al. (IEEE Journal of Solid-State Circuits, Volume SC-21, No. 1, February 1986, pages 73-85) and in the article A Bit-Serial Silicon Compiler by Jeffrey R. Jasica et al. (Proceedings of the International Conference on Computer-Aided Design, ICCADO85, Santa Clara, Calif. pages 91-93, 1985).
S. G. Smith and P. B. Denyer in a paper titled Radix-4 Modules for High Performance Bit-Serial Computation (IEE Proceedings, Vol. 134, Pt. E. No. 6, Nov. 1987, pages 271-276) present an outline of a number of methods for increasing the throughput of bit serial architectures. Among the methods mentioned therein is the pairing of bit-serial bits for parallel computation as radix-four digits. In this same regard, attention is also directed to the paper titled Techniques to Increase the Computational Throughput of Bit-Serial-Architectures, by Smith et al. (Proceedings of ICASSP 87, page 543, April 1987).
The Smith and Denyer articles are interesting also in regard to the radix-four adders and multipliers they describe for processing dual-bit digits, which can be modified to accommodate multiple-bit digits. Digit-serial addition and subtraction for plural-bit digits are described by R. I. Hartley and P. F. Corbett in U.S. patent application Ser. No. 265,210 filed 31 Oct. 1988, entitled "DIGIT-SERIAL LINEAR COMBINING APPARATUS" and assigned to General Electric Company. That application described structures for performing digit-serial comparison as well as programmed addition or subtraction, which structures can perform non-restoring division. Digit-serial multipliers suitable for plural-bit digits are known in the prior art. Such multipliers are also described by R. I. Hartley and P. F. Corbett in U.S. patent application Ser. No. 134,271 filed 15 Aug. 1988, entitled "BIT-SLICED DIGIT-SERIAL MULTIPLIER" and assigned to General Electric Company; and in U.S patent application Ser. No. 231,937 filed 15 Aug. 1988, entitled "BIT-SLICED DIGIT-SERIAL MULTIPLIER", and assigned to General Electric Company.
Of interest is the Irwin and Owens article Digit-Pipelined Arithmetic as Illustrated by the Paste-Up System: A Tutorial (cited above) with regard to its description of architecture using two-bit-wide signed digits to describe each arithmetic word. Signed digits are used to permit the more significant digits of a word to be supplied first. Signed digits introduce undesirable redundancy into arithmetic words, inasmuch as each digit carries its own sign indication, rather than one bit in each arithmetic word providing sign indication for the entire word. The use of signed digits undesirably impairs "throughput efficiency", because handling the redundancy in the signed digits requires either an increase in digital hardware or a reduction in throughput rate as compared to non-redundant arithmetics. "Throughput efficiency" is a measure of the relative performance of integrated circuits, which measure includes as factors the throughput rate and the reciprocal of the area of the digital circuitry required to support a particular operation or set of operations, for a given set of integrated-circuit design rules.
The present inventors perceive that the use of arithmetics that use non-redundant plural-bit digits including multiple-bit as well as dual-bit digits greatly expands the range of design alternatives, lying between fully parallel and fully serial architectures, that are available to the integrated circuit designer. One can design systems, using a small digit size where high throughput is not so stringent a requirement and the space available on an integrated-circuit die for digit hardware is at a premium, and using a larger digit size where higher throughput rate is necessary. One can change digit size to adjust to the number of pins available for interconnection between integrated circuits or to solve routing problems for connections within an integrated circuit die.
The particular arithmetic favored by the inventors is a digit-serial arithmetic in which each word is a two's complement number, of n bits, n being a positive integer that is a multiple of another positive integer m. The submultiple of m, is the number of bits in each digit of the word. The digits of a word are successively supplied to data flow architecture in order of their significance, least significant digit first and most significant digit last. The order of bits within digits is prescribed according to the significance of the bits within its digit. The sign bit is the most significant bit of the word and is contained in the last digit of the word. The flow of digits is accompanied by another signal that indicates how the flow of digits may be partitioned into individual words.
While the indication may be furnished during the first digits of words, the inventors find it is preferable to furnish the indication during the last digits of words. Different digit-serial operations may be controlled during the first digits of words and during the last digits of words, respectively. It is usually more economical of hardware to derive the former indications from the latter indications by unit digit-interval delay than it is to derive the latter indications from the former indications by [(n/m)-1]-digit-interval delay. Bit-serial processing may be considered to be a special case of digit-serial processing, where digit size is one bit wide.

Increased performance of digital integrated circuits by processing with multiple-bit-width digits


A reconfigurable apparatus for thermal management of an electronics module is described. The apparatus includes a pair of fans generating airflow along respective fan axes. The apparatus also includes a beat sink having one portion disposed in the airflow of the fans and another portion adapted for thermal coupling with the electronics module. The airflows from the fans are in the same direction when the apparatus is arranged in a front-to-back airflow configuration and the airflows are in opposite directions when the apparatus is arranged in a front-to-front airflow configuration. A removable flow director is included in the apparatus when the apparatus is in the front-to-front airflow configuration to direct the airflow from the first fan towards the second fan.

The invention relates generally to thermal management of electronics enclosures. More particularly, the invention relates to a reconfigurable apparatus for thermal management of horizontal enclosures.
Electronic equipment can generate significant heat during operation. The performance of the equipment is typically affected by temperature. Performance may become unreliable if the electronics are subject to high temperatures or large temperature variations. The thermal management of electronic enclosures is becoming increasingly challenging as the power density of the electronics increases. For example, a common form factor for communications equipment enclosures is the horizontal box or xe2x80x9cpizza boxxe2x80x9d. Such enclosures are particularly challenging because the only accessible surfaces for air cooling are the front and rear panels. For some applications, only the front panel is useful for air cooling due to the mounting of the enclosure relative to other enclosures or adjacent walls. Moreover, the enclosure size must be maintained to preserve the number of enclosures that can be deployed in a fixed space. The thermal management of these enclosures has to be effective, affordable and reliable.
Generally, cooling is achieved by providing airflow across the electronics to remove excess heat. The airflow can introduce dust and other contaminants into the electronics environment, potentially leading to failure of the electronic components. Air filters are sometimes used to limit the dust and particulates, however, the power, size and cost of the fans are generally increased to maintain the cooling efficiency. Moreover, air filters require periodic cleaning or replacement.
Accordingly, there exists a need for a thermal management apparatus that meets the requirements described above. The present invention satisfies these needs and provides additional advantages.
In one aspect, the invention features an apparatus for thermal management of an electronics module. The apparatus includes a first fan to generate an inlet airflow and an exhaust airflow along a first fan axis, and a second fan to generate an inlet airflow and an exhaust airflow along a second fan axis. A flow director is disposed on the first fan axis to redirect the exhaust airflow of the first fan to the second fan along the second fan axis. The apparatus also includes a heat sink having a first portion disposed in one or both of the exhaust airflow of the first fan and the inlet airflow of the second fan. The heat sink also has a second portion that can be thermally coupled with the electronics module. The apparatus also includes an enclosure surrounding the heat sink and the electronics module. The heat sink and the enclosure define a first volume and a second volume. The first volume includes the exhaust airflow of the first fan and the inlet airflow of the second fan. The second volume includes the electronics module and is isolated from the airflows generated by the first and second fans.
In one embodiment the apparatus also includes a first louver disposed in the inlet airflow of the first fan and a second louver disposed in the exhaust airflow of the second fan. The first louver is configured at a first angle with respect to the first and second fan axes and the second louver is configured at a second angle with respect to the first and second fan axes that is opposite the first angle. The inlet airflow of the first fan and the exhaust airflow of the second fan are thereby spatially separate.
In another aspect, the invention features a reconfigurable apparatus for thermal management of an electronics module. The reconfigurable apparatus includes a first fan and a second fan generating an airflow along a first fan axis and a second axis, respectively. The second fan axis is substantially parallel to the first fan axis. The airflow from the second fan is in the same direction as the airflow from the first fan when the reconfigurable apparatus is in a first configuration. The airflow from the second fan is in an opposite direction to the airflow from the first fan when the reconfigurable apparatus is in a second configuration. The reconfigurable apparatus also includes a removable flow deflector disposed on the first fan axis when the reconfigurable apparatus is in the second configuration. The removable flow director directs the airflow of the first fan to the second fan along the second fan axis. The reconfigurable apparatus also includes a heat sink having a first portion disposed in one or both of the airflow of the first fan and the airflow of the second fan. The heat sink has a second portion that can be thermally coupled to the electronics module.
In one embodiment the reconfigurable apparatus also includes an enclosure surrounding the heat sink and the electronics module. The heat sink and the enclosure define a first volume and a second volume. The first volume includes the airflows generated by the first and second fans and the second volume includes the electronics module. In another embodiment the heat sink includes a thermal spreader plate that separates the first volume and the second volume. In yet another embodiment the reconfigurable apparatus includes a first louver and a second louver. The first louver is disposed on the first fan axis and is configured at a first angle with respect to the first and second fan axes. The second louver is disposed on the second fan axis and is configured at a second angle with respect to the first and second fan axes that is opposite the first angle so that an airflow exhausted through the second louver does not interfere with the airflow received at the first louver.

Thermal management apparatus for horizontal electronics enclosures


An arrow fletching assembly is disclosed. An embodiment of the arrow fletching assembly may include a tubular sleeve about which a plurality of feathers or vanes may be attached. Another embodiment may include graphics printed on the tubular sleeve or on a sticker that is configured for application on the tubular sleeve. Embodiments of the arrow fletching assembly may be field adjustable according to the present invention.

1. Field of the Invention
The present invention relates generally to arrows. More particularly, the present invention relates to an arrow fletching assembly.
2. State of the Art
Arrows generally include an arrow shaft having an arrow head mounted on one end of the shaft and a nock on the opposite end of the arrow shaft. Arrows also typically include fletching mounted near the nock on the opposite end of the arrow shaft. Fletching typically includes three or four feathers or vanes which may be mounted helically along the arrow shaft to promote spinning of the arrow during flight.
Conventionally, the plurality of feathers or vanes of the fletching is adhered to the surface of the arrow shaft using epoxy or some other suitable adhesive. The feathers or vanes are typically evenly spaced around the circumference of the arrow shaft. For example, where three feathers are employed, each of the three feathers is approximately 120° apart from adjacent feathers. The nock is also generally fixed in place relative to the arrow fletching. Once the feathers or vanes and nock have been adhered to the arrow shaft, it is difficult to adjust their relative positions without removing one, the other or both. This makes field adjustment of the fletching unlikely. Additionally, there may be other instances where the ability to field tune the fletching for a particular broadhead or other arrow head may be desirable.
Conventional arrow fletching may include various colors. However, it would be advantageous to have bright and highly visible colors and arbitrary graphics associated with arrow fletching to make them more visible for retrieving or for displaying trademarks and other indicia.
Accordingly, there exists a need in the art for an arrow fletching assembly that is field adjustable and can accommodate a variety of arrow shaft configurations. There further exists a need in the art for an arrow fletching assembly that is highly visible for ease of locating after shooting in the field. There exists a further need for an arrow fletching assembly that is configured for graphics and other indicia.


A recording and/or reproducing apparatus and method with signal quality determining device and a method thereof, with the signal quality determining device including a signal estimator determining a level corresponding to a sample value of the RF signal using binary data obtained from the RF signal and generating a selection signal corresponding to the determined level, a channel identifier classifying the sample value into a plurality of levels according to the selection signal and obtaining an average value of the sample values classified into each level, and a quality calculator outputting a signal quality value representing quality of the RF signal using each sample value output from the channel identifier and the average value of the sample values classified into each level. Accordingly, quality of an RF signal can be determined more exactly, and focus compensation, tilt compensation, detrack compensation, and recording signal optimization can be performed using the determined signal quality.

1. Field of the Invention
Embodiments of the present invention relate to recording and/or reproducing apparatuses with signal quality determining devices and methods therefor, and more particularly, to methods devices for determining the quality of RF signals obtained from an optical disc.
2. Description of the Related Art
Binary data recorded on an optical disc can be reproduced by a recording and/or reproducing apparatus, having the capability to receive, convert, and analyze a reflected light beam, e.g., converting a light beam reflected from the optical disc into an electrical signal, performing a predetermined signal processing process on the electrical signal, and reproducing the information. The signal obtained by converting the light beam reflected from the optical disc into the electrical signal is called a radio frequency (RF) signal. Even though the data recorded on the optical disc is binary data, the RF signal obtained from the optical disc is an analog signal, due to the characteristics of the optical disc and optical characteristics. Therefore, a binarization process is required to convert the analog signal into a binary signal.
FIG. 1 is a block diagram of a conventional binarization device. This conventional binarization device includes a comparator 110 and a lowpass filter 130. The comparator 110 outputs a binary signal by binarizing an input RF signal based on a standard value provided by the lowpass filter 130. The binary signal output from the comparator 110 is provided to a phase locked loop (PLL) (not shown) to generate a system clock. Here, the RF signal and the system clock are not exactly synchronized, and there is a small phase difference between the RF signal and the system clock. This phase difference effect is called jitter.
FIGS. 2A and 2B illustrate jitter generated according to a conventional technology. In the ideal case, an edge of the system clock exactly meets a zero crossing point of the RF signal, as shown in FIG. 2A. However, in actuality, the edge of the system clock does not meet the zero crossing point of the RF signal, and the jitter is evident, as shown in FIG. 2B.
According to conventional techniques, the jitter value, which is the phase difference between an RF signal and a system clock, can be used as a barometer to evaluate the quality of the RF signal. That is, since the jitter value is larger when a large amount of noise is included in the RF signal, the quality of the RF signal can be obtained by measuring the jitter value.
However, as the data recording density of the optical disc increases, the magnitude of the RF signal has become smaller. In this case, since signal distortion is relatively large even when a small amount of noise is present, the jitter value will be large. Also, as the data recording density of the optical disc increases, more zero crossing points are included in the RF signal. Accordingly, a jitter circuit may malfunction.

Recording and/or reproducing apparatus and method with a signal quality determining device and method


A method for fabrication of passive electronic components includes disposing a sacrificial layer on a carrier and forming a curable resin layer on top of the sacrificial layer and patterning the curable resin to form a cured resin template having multiple pattern levels. A metal material is deposited into the first pattern level to form a first structure. A dielectric material is then formed on exposed portions of the first structure. A nonselective subtractive process is used to expose the sacrificial layer in a bottom of the second pattern level and metal material is deposited into the second pattern level and built up to include a portion which crosses over the dielectric material.

In traditional integrated circuit manufacturing on rigid substrates, passive devices such as capacitors and inductors are typically surface mounted as discrete components via soldering or as embedded integrated devices. These integrated devices can be created from thin films of materials deposited via standard vacuum processes with photolithographic patterning or from thick films which are deposited by screen printing of pastes which are then fired at high temperatures.
These approaches can be unsuitable for manufacturing passive devices on flexible polymer substrates for a number of reasons. For example, the high processing temperatures associated with soldering of discrete components or firing of ceramic pastes could cause significant thermal degradation of the polymer substrate. Additionally, the polymer substrate can undergo a significant amount of dimensional distortion (such as bending and stretching) during handling. This can create challenges in aligning the sequential deposition/subtraction steps during photolithography or other processes.
Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.

Fabrication of passive electronic components

Hewlett-Packard Development Company, L.P.


A gas turbine engine stator vane includes a groove extending laterally in an outer surface at one end thereof between leading and trailing edges for receiving a brazing material. The vane may be joined to an arcuate band having a complementary groove extending colinearly with the airfoil groove to collectively define therebetween an enlarged crevice for receiving the brazing material to form a reinforcing pin therein.

In a gas turbine engine, a combustor discharges hot combustion gases downstream through a high pressure (HP) stationary or stator turbine nozzle which directs the flow between rotor blades of a high pressure turbine (HPT) for extracting energy therefrom. The HPT may have a second stage of rotor blades disposed downstream from the first stage with an additional, second stage turbine nozzle disposed therebetween for channeling the combustion gases from the first stage rotor blades to the second stage rotor blades.
The HP first stage turbine nozzle and the second stage turbine nozzle each include a plurality of circumferentially spaced apart stator vanes or airfoils joined at their radially outer and inner ends to annular outer bands. The nozzles are typically made in arcuate segments with arcuate outer and inner band segments each having one or more vanes per segment. The segments are conventionally joined together to collectively form a complete 360.degree. turbine nozzle.
The HP stage one nozzle is typically supported in the engine at both its outer and inner bands for accommodating loads thereon including pressure forces from the combustion gases channeled between the vanes. However, the second stage nozzle is supported solely at its outer band since a conventional annular seal member is disposed between the first and second rotor stages preventing stationary support of the inner band as well. Accordingly, the vanes of the second stage nozzle are cantilevered from the outer band support which creates bending moments due to the combustion gases flowing between the vanes which must be suitably reacted or accommodated through the outer band.
Since the HP stage one nozzle is supported at both its inner and outer bands, it may be relatively simply manufactured by brazing the vanes at their outer and inner ends to the respective outer and inner bands. However, braze joints have acceptable shear strength but undesirable bending strength. Since the HP nozzle is supported at its outer and inner bands, bending moments from the combustion gases are insignificant, whereas the bending moments in the second stage nozzle are significant since it is supported solely at its outer band, with the inner band thereof being unsupported.
Accordingly, brazed turbine nozzles are typically not used where they cannot be supported at both their outer and inner bands which, therefore, requires alternate and typically more complex and expensive designs.
For example, the vanes may be integrally cast in groups to their outer and inner bands to form integral nozzle segments which do not require brazing between the vanes and bands. Alternatively, a single vane may be integrally cast to outer and inner band segments to avoid brazing therebetween, with the band segments themselves being brazed together at the circumferential joints therebetween. However, these methods of manufacture are not suitable for conventional, high strength, single crystal vanes which are desirable for use in second stage turbine nozzles of improved gas turbine engines.
Accordingly, a simpler and less expensive brazed turbine nozzle is desired for those stages wherein the nozzle is supported solely by its outer band, and which allows the use of single crystal vanes.

Stator vane having reinforced braze joint


A method for producing a workpiece from an elongated blank or intermediate product. The workpiece geometry is formed in a first method step, for example by forging the blank or intermediate product, a centering region for subsequent machining of the workpiece between centers being introduced in two oppositely situated sides of the workpiece with reference to the longitudinal axis thereof, and at least one of the centering regions having a desired deformation face. The workpiece is calibrated in a second method step, the desired deformation face being adapted in such a manner that the distance between the contact faces of the centering regions for the machining between centers being adjusted to a predetermined desired measurement. The invention also includes a corresponding workpiece with centering regions, at least one of which has at least one desired deformation face.

1. Field of the Invention
The invention relates to a method for producing a workpiece with centering regions or centers for machining between centers, said workpiece being produced from an elongated blank or intermediate product, as well as to a workpiece with corresponding centering regions.
2. Related Technology
It is known from the prior art to clamp elongated components for machining between centers in order to be able to machine said components over the entire surface, in particular when machining in lathes, in order to avoid machining defects or in order to make it possible to machine/turn in both directions. To this end, centers are provided in the workpiece to be machined at two oppositely situated (when viewed in the longitudinal direction of the workpiece) (end) faces; preferably cone-shaped centers. A driven tip of a lathe is introduced into the center on one side of the workpiece and an entrained tip of a lathe is introduced into the oppositely situated center and the workpiece is clamped at its oppositely situated (end) faces in this manner. On the machine side, the driven tip is clamped in the operating spindle of the lathe, whilst the entrained tip is clamped in the tailstock of the same.
During machining (turning, grinding etc.) between centers, it is necessary for the length tolerance between the contact faces of the centers or other types of centering regions to be as small as possible in order to make uniform finishing possible over several workpieces. Thus, for example, when providing toothing in a workpiece by means of machining between centers, the toothing can extend too far or not far enough in the longitudinal direction of the workpiece and can consequently impair other geometric contours of the workpiece or the region of the engagement of the toothing.
In addition, for the purchaser of prefabricated workpieces (for example blanks for constant velocity drive shafts) who wants to machine them further or finish them by machining between centers, it is, as a rule, very time-consuming and very costly to provide centers subsequently in the workpiece, for example through metal-cutting methods such as drilling.
On the part of the supplier and manufacturer of the prefabricated workpiece, the centers are generally able to be introduced at the same time directly during the manufacture of the workpiece. For example, when workpieces are produced by means of cold-forging, warm-forging or hot-forging (e.g. hot extrusion), length tolerances of the workpiece of approximately +/−2 mm are achieved. In the case of the workpiece produced by forging a blank or intermediate product, this means that during forging centers that were introduced at the same time—or better the actual measurement of the distance between the contact faces of the centers or other types of centering regions for the machining between centers—also lie in a high tolerance range, it only being possible to achieve minimum tolerances of +/−0.6 to +/−0.8 mm. If a workpiece of this type is further machined on the part of the purchaser, the tolerance per workpiece has to be determined individually in order to balance it out during machining. This, in turn, requires a high amount of expenditure of measuring and subsequently an individual adjustment of the machine for each workpiece, which means a high level of expenditure of time and money and makes automatic production almost impossible; at best in the case of workpieces with small tolerance defaults.
As an alternative to this, it is also possible, in a further method step, to compress the entire workpiece after production thereof and after the introduction of centers, however, as a rule, before further machine-cutting, which requires a high level of expenditure on labor, energy and costs. In addition, the compressing impairs the geometry of the workpiece over the entire workpiece length, which increases the risk of scrap.

Workpiece produced from an elongated blank or intermediate product and method for the production thereof