An electronic control apparatus includes an event portion, a cumulative number acquiring portion, a time series information acquiring portion, and a storing execution portion. The event portion acquires an event information item representing an occurrence of an event. The cumulative number acquiring portion acquires a cumulative number of the occurrence of the event each time the event information item is acquired. The time series information acquiring portion acquires a time series information item each time the event information item is acquired. The storing execution portion stores, corresponding to the cumulative number, the time series information item cumulatively acquired by the time series information acquiring portion using all area of an information storage portion each time the time series information item is acquired. The time series information item includes vehicle information entries arranged in chronological order. Each of the vehicle information entries represents a condition of the vehicle.

Conventionally, a control apparatus for a vehicle (i) repeatedly acquires vehicle information representing arbitrary information of a vehicle, such as an output value of a sensor attached to the vehicle, or a control value for an actuator and (ii) stores the vehicle information in a predetermined order according to an elapsed time, that is, in time series.
As disclosed in JP 2013-056589 A (corresponding to US 2013/0060418), when a predetermined event in the vehicle occurs, a control apparatus stores time series vehicle information in a memory.


A sewing apparatus such as a household sewing machine includes a needle bar, a needle bar vertically moving mechanism, a needle bar position changing operation unit operated via the needle bar vertically moving mechanism to change a vertical position of the needle bar, a thread cassette having a thread accommodating section accommodating a supply of thread, a cassette mount to which the thread cassette is detachably attached, a cassette detector detecting the thread cassette attached to the cassette mount, and a needle bar position changing control unit controlling the needle bar vertically moving mechanism so that in a case where the needle bar position changing unit has been operated, the needle bar is changed from an upper stop position to a lower stop position or vice versa according to a position of the needle bar at the time of operation of the needle bar position changing unit when the thread cassette is attached to the cassette mount according to a result of detection by the cassette detector, the needle bar position changing control unit further controlling the needle bar vertically moving mechanism so that the needle bar is changed to the upper stop position irrespective of the position of the needle bar at the time of operation of the needle bar position changing unit when the thread cassette is unattached to the cassette mount according to the result of detection by the cassette detector.

1. Field of the Invention
This invention relates to a sewing apparatus with a cassette mount to which a thread cassette is detachably attached, and more particularly to a technique for performing different needle bar position changing control manners depending upon whether or not the thread cassette has been attached to the cassette mount when a needle bar position changing means has been operated.
2. Description of the Related Art
There has conventionally been proposed a sewing apparatus which includes a cassette mount to which a thread cassette accommodating a thread spool is detachably attached and in which a thread drawn from the thread cassette serves as a needle thread. In the sewing apparatus, the thread drawn from the thread cassette attached to the cassette mount is caught between a pair of thread tension discs of a thread tensioning mechanism. The thread extending downstream from the thread tension discs is caught on a needle thread take-up lever, and the thread extending downstream from the lever is passed through an eye of a sewing needle mounted on a needle bar.
It is desirable that the above-described sewing apparatus be provided with a threading mechanism for passing a thread drawn from the thread cassette attached to the cassette mount through an eye of a sewing needle. Furthermore, in order that the thread may be passed through the needle eye, the threading mechanism needs to be operated while a needle bar vertically moved by a needle bar vertically moving mechanism is stopped at an upper stop position.
On the other hand, the assignee of this application filed a Japanese patent application assigned with Application No. 2002-91558 and relating to a sewing apparatus including a thread carrying mechanism and a threading mechanism each operated in synchronization with attachment of the thread cassette to the cassette mount. The thread drawn from the thread cassette is automatically passed through the needle eye by the thread carrying mechanism and threading mechanism. In the disclosed sewing apparatus, the thread drawn from the thread cassette is caught and carried near the needle eye by the thread carrying mechanism, and the carried thread is caught by the threading mechanism to be passed through the needle eye.
In the above-described sewing apparatus, the threading mechanism is operated in synchronization with the operation of attaching the thread cassette to the cassette mount. Accordingly, in order that passing the thread through the needle eye may be realized by the threading mechanism, the thread cassette needs to be attached to the cassette mount while the needle bar is stopped at an upper stop position.
Cloth to be sewn is set to the sewing apparatus while the needle bar is stopped at the upper stop position. While the needle bar is stopped at a lower stop position, the thread is stuck into the set cloth so that a positional relationship is maintained between the cloth and needle. The cloth can be turned about the needle in order that a sewing direction may be changed. In conventional sewing apparatus, a needle up-down key is provided which is operated to change the position of the needle bar between the upper and lower stop positions alternately. Furthermore, there are some conventional sewing machines in which the threading mechanism is not operated when the needle bar has a height lower than a predetermined one.
When a conventional sewing machine with the cassette mount to which the thread cassette is detachably attached includes a threading mechanism, a user has a difficulty in moving the needle bar to the upper stop position to stop it there by operating a spindle pulley or the like while viewing the needle bar. Threading sometimes fails when the threading mechanism is operated although the needle bar is stopped at any position other than the upper stop position. The threading mechanism or the like would be damaged depending in certain conditions. A trial-and-error operation would be required at many times until the needle bar reaches a suitable height. As a result, the working efficiency would be reduced.
In the sewing apparatus disclosed in aforesaid Japanese patent application No. 2002-91558, the thread cassette needs to be attached to the cassette mount while the needle bar is stopped at the upper stop position. The above-described problems also apply to the disclosed sewing apparatus. When threading has failed, the thread cassette would need to be re-attached to the cassette mount, and the preparation for threading needs to be re-executed, thereby resulting in troubles.
Furthermore, the aforesaid needle up-down key may be applied to the sewing apparatus with the cassette mount to which the thread cassette is attached. However, the needle bar is changed between the upper and lower stop positions alternately every time the needle up-down key is operated. Accordingly, even when the needle up-down key is operated before threading so that the needle bar is located at the lower stop position, the threading mechanism would sometimes be operated (or the thread cassette would be attached to the cassette mount in the sewing apparatus disclosed in Japanese patent application No. 2002-91558).
The location of the needle bar needs to be confirmed in order that the user may operate the needle up-down key to stop the needle bar at the upper stop position. Furthermore, in certain cases, the needle up-down key needs to be operated twice to stop the needle bar at the upper stop position. Thus, load applied to the user is increased and accordingly, the position change is troublesome. In order that the sewing apparatus may be improved in the convenience thereof, it is desirable that the needle up-down key be operated to change the needle bar between the upper and lower stop positions alternately.
Therefore, an object of the present invention is to provide a sewing apparatus in which when a needle bar position changing means is operated, the needle bar is changed to the upper or lower stop position according to the position at the time of operation of the needle bar position changing means in the case where the thread cassette is attached to the cassette mount, and the needle bar is changed only to the upper stop position when the thread cassette is unattached to the cassette mount, whereupon the thread cassette can desirably be attached to the cassette mount.
The present invention provides a sewing apparatus comprising, a needle bar, a needle bar vertically moving mechanism vertically moving the needle bar, a needle bar position changing operation unit operated via the needle bar vertically moving mechanism to change a vertical position of the needle bar, a thread cassette having a thread accommodating section accommodating a supply of thread, a cassette mount to which the thread cassette is detachably attached, a cassette detector detecting the thread cassette attached to the cassette mount, and a needle bar position changing control unit. The needle bar position changing control unit controls the needle bar vertically moving mechanism so that in a case where the needle bar position changing unit has been operated, the needle bar is changed from an upper stop position to a lower stop position or from the lower stop position to the upper stop position according to a position of the needle bar at the time of operation of the needle bar position changing unit when the thread cassette is attached to the cassette mount according to a result of detection by the cassette detector. The needle bar position changing control unit further controls the needle bar vertically moving mechanism so that the needle bar is changed to the upper stop position irrespective of the position of the needle bar at the time of operation of the needle bar position changing unit when the thread cassette is unattached to the cassette mount according to the result of detection by the cassette detector.
When the presence or absence of the thread cassette attached to the cassette mount has been detected by the cassette detector and the needle bar position changing operation unit has been operated, the needle bar position changing control unit controls the needle bar vertically moving mechanism on the basis of the result of detection by the cassette detector. In the control, when the thread cassette is attached to the cassette mount, the needle bar is changed from the upper stop position to the lower stop position or from the lower stop position to the upper stop position according to the position of the needle bar at the time of operation of the needle bar position changing unit. When the thread cassette is unattached to the cassette mount, the needle bar is changed to the upper stop position irrespective of the position of the needle bar at the time of operation of the needle bar position changing unit.
A space for set and removal of cloth to and from the sewing apparatus is defined below the needle bar when the needle bar is at the upper stop position. When the needle bar is at the lower stop position, the needle is stuck into cloth set to the sewing apparatus so that a positional relationship is maintained between the cloth and needle. In a case where the thread cassette has been attached to the cassette mount, the needle bar is changed between the upper and lower stop positions alternately every time the user operates the needle bar position changing operation unit once. On the other hand, when the thread cassette has not been attached to the cassette mount, the needle bar need not be changed to the lower stop position. Accordingly, the needle bar is changed to the upper stop position irrespective of the position of the needle bar when the user operates the needle bar position changing operation unit once.
The needle bar position changing control unit preferably controls the needle bar vertically moving mechanism so that when the thread cassette is unattached to the cassette mount according to the result of detection by the cassette detector and the needle bar is at the upper stop position, the needle bar is changed to the lower stop position once and subsequently to the upper stop position.
The sewing apparatus preferably further comprises a threading mechanism passing the thread drawn from the thread cassette through an eye of a needle attached to the needle bar when the thread cassette is attached to the cassette mount. In this case, the upper stop position is determined so that the threading mechanism is operable to pass the thread drawn from the thread cassette through the needle eye.

Sewing apparatus with needle bar position changing control


Managing ETL (extract-transform-load) operation execution by receiving an updated ETL (extract-transform-load) job flow, determining affected stages of a current ETL job flow, sending a message to stop data flow for all stages of the current ETL job flow, sending a switch message along the current ETL job flow through the affected stages, receiving notice of receipt of the switch message downstream from the affected stages of the current ETL job flow, moving an affected stage of the current ETL job flow from a first ETL section to a second ETL section; and resuming data flow according to the updated ETL job flow.

The disclosure relates generally to managing computing resources for extract-transform-load (ETL) execution. The disclosure relates particularly to the management of ETL operations across resources by implementing new ETL flows as needed.
Extract-transform-load (ETL) jobs are used to move data present in distributed file systems, such as HADOOP Distributed File System (HDFS) files, into database tables where the data can be searched using software such as the APACHE HIVE project. An ETL job is a set of stages that are responsible for different types of activities—reading data, writing data, transforming data, passing data and many others. An ETL job includes stages connected by links. A stage is some kind of action executed upon data, for instance—read from source, write into target, filter data, merge data or some other data transformation. A link is a representation of data flow from one stage to another. The stages may be executed on the same virtual machine (VM), different VMs, or even in multiple Clouds. For instance, reading from one database on one system, reading from another database located somewhere else, writing into HDFS of Hadoop deployed in a different cloud environment.
ETL engines carry responsibility for the execution of ETL job tasks. A single ETL job arrayed across multiple VMs or clouds includes multiple ETL engines, one engine per ETL job section, VM or cloud environment. ETL engines communicate to job stages or nodes by internode communication links.
(Note: the terms "HADOOP", "APACHE", "KAFKA", and "HIVE" may be subject to trademark rights in various jurisdictions throughout the world and are used here only in reference to the products or services properly denominated by the marks to the extent that such trademark rights may exist.).

International Business Machines Corporation


During manufacturing, a unique bi-directional IP communication device identifier, such as a gateway serial number, is assigned to a each bi-directional IP communication device, preferably a DSL gateway. Once an order for such a device is received from a user, the unique bi-directional IP communication device identifier is associated with the unique user that the device is shipped to. A request for basic configuration details is then broadcast, preferably to a DHCP server. The request contains the unique bi-directional IP communication device identifier. The user's basic configuration details are then determined based on the unique bi-directional IP communication device identifier. These basic configuration details, which preferably include an IP address, are then received from the DHCP server. The bi-directional IP communication device is then configured with these basic configuration details.

1. Field of the Invention
The present invention relates generally to broadband telecommunications, and particularly to a system and method for automatic configuration of a Bi-directional Internet Protocol (IP) communication device, such as a DSL gateway or modem.
2. Description of Related Art
While high-speed Internet connections to large businesses have been in existence for quite some time, high speed Internet connections to homes and small businesses have only recently become more commonplace. Bi-directional
IP communication technologies such as ISDN (Integrated Services Digital Network), Cable, Satellite, and DSL (Digital Subscriber Line), are all competing for market share. The two technologies at the forefront, DSL and Cable, offer much faster Internet access than dial-up modems, for a cost substantially lower than ISDN.
Analog modems over regular telephone lines are not fast enough for today's broadband multi-media content. In fact, so-called 56 Kbps modems actually move data at approximately 44 Kbps because of telephone-line imperfections. Furthermore, these modems only reach that speed when receiving data, not sending it.
Basic ISDN transfers data at 56 Kbps, while an improved form of ISDN has a maximum speed of 128 Kbps. ISDN is, however, expensive, running up to several hundreds of dollars a month. Furthermore, ISDN is only approximately four times the speed of a 33.6 Kbps modem.
Another option, satellite, which uses the same type of mini-dish antenna typical of broadcast television can receive data at up to 400 Kbps. However, transmitted data still has to be sent through a traditional analog modem at 33.6 Kbps or 56 Kbps.
Cable modems, enable one to hook up a PC to a local cable television line and receive data at about 1.5 Mbps. This data rate far exceeds that of both 56 Kbps analog modems, and the 128 Kbps of ISDN. The actual bandwidth for Internet service over a cable TV line is up to 27 Mbps for receiving data, and up to about 2.5 Mbps of bandwidth for transmitting data. However, since the local provider may not be connected to the Internet on a line faster than a T-1 at 1.5 Mbps, a more likely data rate will be closer to 1.5 Mbps. Cable, however, suffers the drawback that it is carried on existing cable television lines, which not all homes, and especially not all small businesses are equipped with. Furthermore, available bandwidth is shared with other cable users in the same geographic area.
DSL, on the other hand, is 20 times faster than satellite connections, 60 times faster than ISDN, and 250 times faster than 33.6 Kbps analog modems. DSL, as used herein, refers to different variations of DSL, such as ADSL (Asymmetric Digital Subscriber Line), HDSL (High bit-rate Digital Subscriber Line), and RADSL (Rate Adaptive Digital Subscriber Line).
Assuming that the location of one's home or business is close enough to a telephone company central office that offers DSL service, one can receive data at rates up to 6.1 megabits (millions of bits) per second. More typically, individual connections will provide from 1.544 Mbps to 512 Kbps downstream and about 128 Kbps upstream. Best of all, those bits are transmitted via the same copper wire one uses for telephone calls, but without the complex setup of ISDN. DSL does this by taking advantage of unused frequencies that exist on standard telephone lines. An added advantage is that the original POTS (plain-old telephone service) frequencies remain free to handle voice traffic over the same copper wires. Yet another advantage is that one does not share the line with others in the same geographical area. Within a few years, DSL is expected to replace ISDN in many areas and to compete with the cable modem in bringing multimedia to homes and small businesses around the world.
One of the major problems facing the rollout of DSL connections is the cost and complexity of initial setup of a DSL gateway (or modem) at a remote location. This is because most DSL technologies require a manual configuration of the gateway and client computer at a home or business, requiring the expense of a visit by a technician to the remote location for setup of the telephone line and installation and configuration of the DSL gateway and client computer. It has been estimated, that a typical service call to install and configure a DSL gateway, currently costs in the region of $300 for the DSL service provider.
The use of signal splitters has reduced the cost of rolling out DSL service, as they reduce the complexity of initial setup for DSL consumers. A signal splitter is a device for isolating voice and data signals transmitted on normal analog telephone wires. The splitter, essentially, comprises a low pass filter that differentiates between data and voice signals. As most homes and offices have at least two pairs of twisted copper wires (hereafter "twisted pairs"), the splitter typically divides data to an outer pair of the wires and voice to an inner twisted pair of the wires. Therefore, voice communication devices can only be plugged into communication-jacks that connect to the inner twisted pair, and data communication devices can only be plugged into communication-jacks that are connected to the outer twisted pair. The DSL consumer, however, must ensure that the correct devices are plugged into the correct communication-jacks, and ensure that line converters are installed between the devices and the communication-jacks to switch inner and outer pairs, if necessary.
More recently, micro-filters or μfilters for splitting data and voice signals have been developed. These μfilters are also low pass filters that are placed between each POTS device and a regular telephone jack. The μfilters, therefore, allow two copper wires to be utilized instead of four, as there is no division of data and voice at a central splitter. A typical double twisted pair analog telephone line can, therefore, support two independent data and/or voice communication lines.
However, even with the above described advances, DSL consumers typically still have to configure their DSL gateways themselves. Typically, the consumer must manually enter configuration information, such as their telephone numbers and other information supplied by the DSL service provider, into their client computers. In addition, the DSL service provider also typically spends a substantial amount of resources providing telephone assistance to talk DSL consumers through the installation and configuration process. Often, the service provider still needs to send technicians out to the consumer to install and configure the DSL system. This process is both costly and time consuming.
A need therefore exists for an automatically configurable DSL gateway that can be installed by a consumer with little, or no, technical skill or know-how.

System and method for automatic configuration of a bi-directional IP communication device


A method for absorbing cobalt within an olefinic feedstock which comprises the steps of introducing a volatile cobalt compound and an olefinic feedstock into an absorber to form a cobalt-containing olefin mixture, withdrawing the cobalt-containing olefin mixture from the absorber, introducing at least a portion of the cobalt-containing olefin mixture into a reactor, wherein a substantial portion of the volatile cobalt compound entrained within the cobalt-containing olefin mixture decomposes to its non-volatile cobalt compound species, and recycling this mixture back to the absorber so that it can be used to further absorb volatile cobalt such that a more concentrated cobalt-containing olefin solution is formed.

Hydroformylation reactions involve the preparation of oxygenated organic compounds by the reaction of carbon monoxide and hydrogen (a.k.a., syn gas or synthesis gas) with carbon compounds containing olefinic unsaturation. The reaction is performed in the presence of a carbonylation catalyst and resulting in the formation of a compound, for example, an aldehyde, which has one more carbon atom in its molecular structure than the starting olefinic feedstock. By way of example, higher alcohols may be produced in the so-called "oxo" process by hydroformylation of commercial C.sub.6 -C.sub.12 olefin fractions to an aldehyde-containing oxonation product, which on hydrogenation yields respective C.sub.7 -C.sub.13 saturated alcohols. The crude product of the hydroformylation reaction will contain catalyst, aldehydes, alcohols, unreacted feed, syn gas and by-products.
Before further processing of the crude product is possible, it is necessary to remove the catalyst therefrom. One conventional method of removing cobalt values from such a crude product is to treat the product with an alkali or acid wash technique. See U.S. Pat. No. 3,725,534 (Reisch), which issued on Apr. 3, 1973. However, this approach uses expensive raw materials and incurs problems associated with finally removing essentially all traces of cobalt from the water wash streams before being discharged.
Another conventional method involves the oxidation of the cobalt catalytic species followed by extraction as a cobalt salt in aqueous solution. See U.S. Pat. No. 2,744,921 (Mertzweiller et al.), which issued on May 8, 1956.
U.S. Pat. No. 4,625,067 (Hanin), which issued on Nov. 25, 1986, discloses still another method which involves the contacting of the crude product with a stream of stripping gas to entrain volatile cobalt, characterized in that the contacting is performed in the presence of water and aqueous acid to dissolve those cobalt values not entrained in the gas under the conditions of temperature and pressure employed for the contacting, and the aqueous phase is subsequently separated from the organic hydroformylation reaction product.
Although the stripping method disclosed in the Hanin patent overcomes the disposal and chemical additive costs of the caustic/acidification method of Reisch, it has the disadvantage that low concentrations of cobalt are absorbed into the olefinic feedstock per unit volume requiring the use of a large absorber unit and substantially all of the olefinic feedstock.
Therefore, conventional absorber systems are acceptable for applications where substantially all of the olefinic feedstock is fed through the absorber such that all of the available cobalt is returned to the oxo reactor together with the feedstock. However, instances where it is not desirable to pass all of the olefinic feedstock through the absorber section, conventional absorber systems have been found to be incapable of returning all of the available cobalt to the oxo reactor. This is because conventional absorbers operating under typical absorber conditions (i.e., 30.degree. C. and 0.8 atm CO partial pressure) are only capable of absorbing approximately 0.3 weight % of cobalt (i.e., 3,000 ppm by weight of cobalt metal).
In some instances it is highly desirable to preheat a portion of the olefinic feedstock prior to its introduction into the oxo reactor. The preheated feedstock allows the hydroformylation reaction to proceed immediately without the necessary heat-up period. This can substantially decrease the overall time that it takes for the oxo reaction to proceed. However, if the cobalt-containing olefinic feedstock from the absorber is preheated, then the volatile cobalt compound contained therein will tend to plate out as highly undesirable cobalt metal.
The present inventor has developed an absorber system that is capable of absorbing substantially more cobalt per unit volume of olefinic feedstock than convention absorber systems, i.e., a cobalt concentration of up to approximately 3.5 weight %. This cobalt concentration level is unattainable via conventional absorber systems.
The present inventor has developed a novel method and system for substantially increasing the cobalt concentration per unit volume of olefinic feedstock. This is accomplished by recycling a portion of the discharged liquid phase back to the absorber via a liquid hold-up reactor under predetermined operating conditions such that the concentration of non-volatile cobalt compound species in the liquid phase is increased due to the decomposition of the volatile cobalt compound.
The present invention attains such cobalt concentration levels by the incorporation of a means for passing the liquid phase discharged from the absorber unit through a liquid hold-up reactor and either returning the cobalt enhanced solution to the absorber or sending it on to the oxo reactor. The volume, temperature and pressure of the liquid hold-up reactor are adjusted so as to increase the rate at which volatile HCo(CO).sub.4 decomposes to a non-volatile species such acylcobalt carbonyl and/or Co.sub.2 (CO).sub.8. The present inventor has also discovered that the use of linear olefins as the feedstock also substantially increases the rate at which volatile cobalt compounds decompose to non-volatile cobalt compound species.
The present invention also provides many additional advantages which shall become apparent as described below.

Method and system for cobalt absorption in a hydroformylation process


A relief-valve device for an air pressure gauge has a casing, a relief-valve assembly, a valve shaft, and a push button. The casing has a connecting member, a pressure detecting member and a discharging member. The relief-valve assembly is mounted in the discharging member and has a valve seat, a first seal ring, a second seal ring and a mounting cover. The valve shaft is mounted axially slidably in the relief-valve assembly and has a shaft member and a valve head. The shaft member has a discharging notch selectively aligning with the second seal ring to allow high pressure air in an inflatable product connecting to the air pressure gauge to be discharged slowly and finely out of the relief-valve device.

1. Field of the Invention
The present invention relates to a valve device, and more particularly to a relief-valve device for an air pressure gauge; the relief-valve device can be further fabricated into an air pressure gauge for measuring internal pressure of an inflatable product, and is able to finely deflate the inflatable product for reducing excessive internal pressure thereof.
2. Description of Related Art
Conventional air pressure gauges are used for detecting and ensuring internal pressure in inflatable products such as basketballs and tires at a predetermined value. A conventional air pressure gauge has a relief valve for deflating the inflatable product for reducing the over high internal pressure thereof. However, the relief valve on the air pressure gauge always operates at a deflating speed too fast to finely and precisely adjust the internal pressure so that the inflatable product is usually over-deflated by the relief valve and a user needs to re-inflate the inflatable product for acquiring a precise internal pressure.
To overcome the shortcomings, the present invention provides a relief-valve device for an air pressure gauge to mitigate or obviate the aforementioned problems.

Relief-valve device for an air pressure gauge


An apparatus for driving a liquid crystal display device includes a liquid crystal display panel having liquid crystal cells in respective regions defined by a plurality of gate and data lines, a data driver providing video signals to the data lines, a gate driver providing scan signals to the gate lines, a timing controller controlling the gate and data drivers, and generates a plurality of dimming signals by resetting a dimming curve in accordance with input data, and a light emitting diode backlight unit driving light emitting diode groups in accordance with the plurality of dimming signals to provide light to the liquid crystal display panel.

1. Field of the Invention
The embodiments of the invention relate to a display device, and more particularly, to an apparatus and method for driving a liquid crystal display (LCD) device. Although embodiments of the invention are suitable for a wide scope of applications, it is particularly suitable for partially emphasizing brightness of an image.
2. Discussion of the Related Art
Generally, an LCD device displays an image on an LCD panel by controlling transmittance of light provided from a backlight unit. The LCD panel includes a plurality of liquid crystal cells arranged in a matrix configuration and a plurality of control switches to switch a video signal supplied to the liquid crystal cells. The backlight unit can have a fluorescent lamp as a light source. The trend in backlighting technology is toward smaller, thinner, and lighter backlight units. Based on this trend, light emitting diodes (LEDs) have been proposed as substitute for fluorescent lamps since LEDs have the advantage of low power consumption, light weight, and high brightness.
FIG. 1 is a schematic of an apparatus for driving an LCD device using an LED backlight unit of the related art. As shown in FIG. 1, the related art driving apparatus includes an LCD panel 2 having liquid crystal cells respectively formed in regions defined by n gate lines (GL1 to GLn) and m data lines (DL1 to DLm); a data driver 4 that supplies an analog video signal to the data lines (DL1 to DLm); a gate driver 6 that supplies a scan signal to the gate lines (GL1 to GLn); a timing controller 8 that controls the data driver 4 and the gate driver 6, and generates a dimming signal (DS) using input data (RGB); and an LED backlight unit 10 that generates light from a plurality of LEDs corresponding to the dimming signal (DS) and supplies the light to the LCD panel 2. A thin film transistor array substrate and a color filter array substrate are bonded together with a spacer between the two substrates to maintain a cell gap as well as liquid crystal in the space between the two substrates to form the LCD panel 2.
Liquid crystal cell are defined by the gate lines (GL1 to GLn) and the data lines (DL1 to DLm) on the thin film transistor array substrate. A thin film transistor (TFT) is formed in each of the liquid crystal cells. Each TFT supplies an analog video signal provided from the data line (DL1 to DLm) to a liquid crystal cell in response to the scan signal provided from the gate line (GL1 to GLn). Each liquid crystal cell can be equivalently expressed as a liquid crystal capacitor (Clc) because it is provided with liquid crystal between a common electrode and a pixel electrode connected with the TFT. Each liquid crystal cell also includes a storage capacitor (Cst) that maintains the analog video signal charged on the liquid crystal capacitor (Clc) until the next analog video signal is charged thereon.
The timing controller 8 arranges externally supplied source data (RGB) to be appropriate for the driving of the LCD panel 2, and provides the arranged source data to the data driver 4. Also, the timing controller 8 generates a data control signal (DCS) and a gate control signal (GCS) by using a dot clock (DCLK), a data enable signal (DE), and horizontally and vertically synchronized signals (Hsync and Vsync) externally inputted thereto, and provides the generated control signals to the data driver 4 and the gate driver 6, to thereby control driving timing of the data driver 4 and the gate driver 6. The timing controller 8 also generates the dimming signal (DS) to control the LED backlight unit 10 by using the input data (RGB).
FIG. 2 is a graph illustrating a dimming curve to control an LED backlight unit of the related art. To generate the dimming signal (DS), the timing controller 8 detects the average brightness of the input data (RGB). As shown in FIG. 2, the timing controller 8 then extracts a dimming value corresponding to the detected average brightness (Avg) from a dimming curve (A) set based on the brightness characteristics of the LED backlight unit 10, and generates the dimming signal (DS) based on the dimming value. In FIG. 2, the X axis shows the average brightness (Avg) of the input data (RGB), and the Y axis shows the dimming value corresponding to the dimming curve (A). The dimming curve (A) has an increased dimming value as the gray scale becomes brighter corresponding to the brightness properties of LED backlight unit.
Referring to FIG. 1, the gate driver 6 includes a shift register which sequentially generates the scan signal, that is, a gate high signal in response to the gate control signal (GCS) supplied from the timing controller 8. The gate driver 6 sequentially supplies the gate high signal to the gate lines (GL) of the LCD panel 2 such that the TFT connected with the gate line (GL) is turned-on.
The data driver 4 converts the data signal (Data) provided from the timing controller 8 to the analog video signal in accordance with the data control signal (DCS) supplied from the timing controller 8, and supplies the analog video signal for one horizontal line to the data lines (DL) in one horizontal period for supplying the scan signal to the gate line (GL). That is, the data driver 4 selects a gamma voltage having a predetermined level based on the gray scale value of the data signal (Data), and supplies the selected gamma voltage to the data lines (DL1 to DLm). Then, the data driver 4 inverts the polarity of the analog video signal supplied to the data lined (DL) in response to a polarity control signal (POL).
The LED backlight unit 10 includes an LED array 12 having a plurality of LEDs and an LED controller 14 that drives the LEDs in accordance with the dimming signal (DS) supplied from the timing controller 8. The LED controller 14 generates a pulse-width modulation signal (Vpwm) corresponding to the dimming signal (DS), and provides the generated pulse-width modulation signal (Vpwm) to the LED array 12. The LED array 12 is positioned opposite to the rear surface of the LCD panel 2. The LED array 12 can include a plurality of red, green and blue LEDs arranged repeatedly. The LEDs generate the light in accordance with the pulse-width modulation signal (Vpwm) supplied from the LED controller 14, and then the generated light is applied to the LCD panel 2.
In the above apparatus for driving the LCD device using the LED backlight unit of the related art, the scan signal is supplied to each gate line (GL), and the input data (RGB) is converted into the analog video signal and is then supplied to each data line (DL) in synchronization with the scan signals, to thereby drive the liquid crystal cells. Simultaneously, the plurality of LEDs are driven by the pulse-width modulation signal (Vpwm) corresponding to the dimming signal (DS) in accordance with the average brightness of input data (RGB) from one predetermined dimming curve (A). Accordingly, the apparatus for driving the LCD device using the LED backlight unit of the related art controls the transmittance of light supplied from the LED backlight unit 10 through the liquid crystal cell driven by the analog video signal, to thereby display the image on the LCD panel 2 corresponding to the input data. However, the apparatus for driving the LCD device using the LED backlight unit of the related art has the following disadvantages.
In the apparatus for driving the LCD device using the LED backlight unit of the related art, the dimming signal (DS) is generated based on one predetermined dimming curve (A) from the average brightness of input data (RGB). Accordingly, it is impossible to partially emphasize the brightness of the image displayed on the LCD panel 2 by using the LED backlight unit. Also, the brightness of the LED backlight unit is determined within one predetermined dimming curve (A), which limits variation of brightness in accordance with the input data (RGB), which can cause an unnecessary increase in power consumption.

Apparatus and method for driving liquid crystal display device


Authentication of a user to an electronic device in a communication network is described. The method comprises obtaining a biometric characteristic of the user, transmitting, to a social networking service, information that specifies at least one primary user of the device, receiving, from the social networking service, information that specifies a group of persons who have a social relationship with the at least one primary user, obtaining information that specifies a result from a biometric matching operation with the biometric characteristic of the user and biometric characteristics of persons in the specified group of persons, the result indicating whether or not the user is authenticated to the electronic device. By narrowing down the size of the searching space-needed during a matching operation by utilizing information regarding a group of persons in a social network, the false acceptance rate is reduced and biometric authentication of a user to an electronic device is thereby facilitated, e.g. to access desired functionality of the device or access a desired service.

With respect to consumer electronic (CE) devices, there is a trend that these are becoming more and more network online service enabled. For example, modern gaming consoles support online services (e.g. Xbox Live). Furthermore, soon TVs will be equipped with functionality such as web-browsing functionality to access services. Typically, service enabled CE devices are complemented with a network portal that provides access to the actual services (such as e.g. the architecture presented in Open IPTV Forum, Functional Architecture—V 1.1, Jan. 15, 2008).
Typically, CE devices have limited user interaction means and users expect that the devices are convenient and simple to use, requiring few operations to accomplish a result. For example, users are typically reluctant to use complex repetitive login procedures using username/passwords.
With respect to digital identity, CE devices take a limited approach, for example to meet the convenience argument as discussed above. For example, the Nintendo Wii gaming console supports multiple characters ("Mii's") but these are not used for transactions or accessing services. For transactions, the owner of the device can link just one account per console that will be used for performing online transactions such as buying downloadable games. Use of this account can be protected using, e.g., a PIN.
Needless to say, CE devices such as gaming consoles are very often used by multiple people, i.e. not only the owner of a gaming console uses the console. However, up to now the online services are non-personalized, or at the most associated with a fixed single user (e.g. for transactions).
The use of biometric characteristics, biometrics, provides a very convenient way for replacing usernames, passwords and pin-codes in situations where authentication and identification are needed. The biometrics is unique for a human being and can not be forgotten, stolen or lost. As such they are a good candidate for being used in access control and e-transaction systems. In many of these systems biometrics is used to perform convenient and secure one-to-one authentication. However, despite the enormous improvement that has taken place during the past decade, the recognition performance of almost all biometric modalities is still not sufficient to make biometrics a reliable tool for large scale one-to-many identification purposes, and it is expected that this will be true for many years to come.
The state-of-the-art performance in terms of today's biometric systems is in the order of 1% equal error rate (EER). The EER is defined as the operating point of biometric systems at a false acceptance rate (FAR) that is equal to the false rejection rate (FRR). Generally, the EER is a useful performance measure, and the lower the value the better the system. By slightly tuning such a system to a somewhat higher FFR than 1%, a minimum FAR of 0.1% seems possible. Consequently, if the FAR for a given recognition system is 0.1%, this means that an imposter has 0.1% probability that his biometrics "looks like" that of a genuine person. It can be shown that if identification is to be performed, i.e. a one-to-many comparison, the probability that a person will by wrongly recognized becomes FARtot=1−(1−FAR)n.
For example, if the FAR of a biometric recognition system is 0.1%, and a person is to be identified amongst a database of 30 persons, the probability FARtot of finding the wrong person is 1−0.99930=0.03, which might acceptable. However, if a database of 300 has to be searched, the FARtot becomes 26%, which makes this identification system essentially useless.
Additionally, as biometrics provides sensitive personal information about a human being, there is typically a privacy problem related to the storage and usage of biometric data. In order to solve this problem biometric data should never be stored in clear in a database but rather in an encrypted form to guarantee privacy and to avoid malicious database cross-matching attacks. By solving this problem the acceptance level of biometrics will be increased. Such privacy preserving techniques, often referred to as template protection systems, have been described in the prior art, for example in WO2005/122467.

Biometric authentication and identification


An apparatus for use by individual to repair and replace tread on the bottom of a pair of shoes is disclosed. The apparatus would have a heating grid attached to the top of the base, with the heating grid including a pair of grids for placement of a pair of shoes. The apparatus would further have a pair of front clamps and a pair of rear clamps for fixing the shoes in place once they have been placed on top of the grids. The apparatus would derive power from standard household current and would have an on/off switch and a plurality of gauges to measure temperature and downward pressure placed upon the shoes.

The present invention concerns that of a new and improved apparatus for use by individual to repair and replace tread on the bottom of a pair of shoes.
U.S. Pat. No. 3,102,286, issued to Minick, discloses a device for treating the soles of footwear.
U.S. Pat. No. 2,987,738, issued to Novotny, discloses a device for treating the soles of footwear.
U.S. Pat. No. 2,659,094, issued to Walls, discloses a portable device for attaching a resilient rubber tread to the worn bottom surface of an article of footwear using a heating element and adjustable screws to provide pressure.
U.S. Pat. No. 2,489,643, issued to Hunter, discloses an apparatus for applying both heat and pressure for the vulcanization of footwear.
The present invention concerns that of a new and improved apparatus for use by individual to repair and replace tread on the bottom of a pair of shoes. The apparatus would have a heating grid attached to the top of the base, with the heating grid including a pair of grids for placement of a pair of shoes. The apparatus would further have a pair of front clamps and a pair of rear clamps for fixing the shoes in place once they have been placed on top of the grids. The apparatus would derive power from standard household current and would have an on/off switch and a plurality of gauges to measure temperature and downward pressure placed upon the shoes.
There has thus been outlined, rather broadly, the more important features of a shoe repair apparatus that the detailed description thereof that follows may be better understood and in order that the present contribution to the art may be better appreciated. There are, of course, additional features of the shoe repair apparatus that will be described hereinafter and which will form the subject matter of the claims appended hereto.
In this respect, before explaining at least one embodiment of the shoe repair apparatus in detail, it is to be understood that the shoe repair apparatus is not limited in its application to the details of construction and to the arrangements of the components set forth in the following description or illustrated in the drawings. The shoe repair apparatus is capable of other embodiments and being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of descriptions and should not be regarded as limiting.
As such, those skilled in the art will appreciate that the conception, upon which this disclosure is based, may readily be utilized as a basis for the designing of other structures, methods and systems for carrying out the several purposes of the present shoe repair apparatus. It is important, therefore, that the claims be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the present invention.
It is therefore an object of the present invention to provide a shoe repair apparatus which has all of the advantages of the prior art and none of the disadvantages.
It is another object of the present invention to provide a shoe repair apparatus which may be easily and efficiently manufactured and marketed.
It is another object of the present invention to provide a shoe repair apparatus which is of durable and reliable construction.
It is yet another object of the present invention to provide a shoe repair apparatus which is economically affordable and available for relevant market segment of the purchasing public.
Other objects, features and advantages of the present invention will become more readily apparent from the following detailed description of the preferred embodiment when considered with the attached drawings and appended claims.


A mixture of waste, essentially cellulosic material and a fire proofing solution can be used to make building materials with exceptional qualities. These qualities include fire proofing, vermin proofing, water proofing and excellent insulative values, for example. Additionally, this process represents an excellent method for recycle of these waste materials. A sheetrock-like or wall-board material can be made therefrom, one which can be nailed, screwed, drilled and fastened without causing serious damage to the surface or the element itself.

1. Field of the Invention
This invention relates to a mixture that can be used for the manufacture of building materials such as wall-board and the like and to the composition thereof. More specifically, this invention also relates to the manufacture of wall-board from recovered, waste, essentially cellulosic material. Still more particularly, this invention relates to novel wallboard compositions that are fireproof, vermin free and insulative in nature.
2. Discussion of the Prior Art
Wall-board, a material of construction and also called "sheetrock", is generally manufactured by the compression of gypsum or other cementitious material between heavy cardboard or paper. This material is conventionally and commonly used in the building trades to form the first layer inside of a building. It may be conventionally installed over standard wooden or metal uprights to form the inside walls of a building, for example. Installation is generally accomplished by nailing the sheetrock to the uprights, or "studs", or by screws or other conventional fastening devices. Finish may the be applied in the form of spackling, or by painting or by the installation of wallpaper on the surface thereof or any combinations thereof. In between the studs, it is conventional to place insulation, especially if the wall is an outside of the building, since sheetrock itself has little or no insulative value. The problem with conventional sheetrock is that it is usually not fireproof and breaks easily during handling and the fastening steps mentioned above. For example, when sheetrock is nailed along the edges, the gypsum crumbles since it is relatively fragile. Thus, the defects caused by this crumbling must be covered prior to the application of finishes thereon. Additionally, as mentioned above, gypsum-type sheetrock has very little insulative value and is not fireproof per se, unless treated according to U.S. Pat. No. 4,886,548, for example or by other procedures as taught therein.
There is also a pressing need to recycle waste materials generated by industrial or household sites. These waste materials are mainly cellulosic in nature coming from paper, paper products and other cellulosic wastes. These wastes make up the bulk of the common waste stream in our society and are generally discarded by land-filling. However, the conventional methods of disposal are no longer acceptable and thus the need to recycle these products into some other useful material.

Mixture for the preparation of building materials


Ultraviolet light curing of a composition on a unit such as an aircraft canopy includes an ultraviolet light generator mounted for movement in at least three directions of motion relative to the unit. The generator is selectively movable in relation to the unit according to prerequisite procedure. A regulated environment cell is provided for the curing. The ultraviolet generator follows predetermined sequences and can be located partly within the canopy during curing. The canopy, after being mounted on a mobile fixture in the horizontal position is pivotally turned to be vertically located strategically relative to the ultraviolet light source during curing.

This invention relates to curing compositions under ultraviolet light. In particular, it relates to a device and method for curing compositions placed on aircraft canopies, which are conventionally made of different layers of a polymeric material, typically combinations of acrylic, polyurethane and polycarbonate.
It is essential in the formation of aircraft canopies, particularly for high speed fighter aircraft such as the F-16, that the material forming the canopy be precisely and uniformly cured so as to prevent irregularity and haze. For fighter pilots, any distortion of the canopy could have serious consequences. It is accordingly necessary to provide a system for layering different compositions for hardness on a canopy which are optically precise, while at the same time being resistant to scratches.
Conventionally, arcylic materials are used for this purpose and they can either be heat-cured or cured under ultraviolet light. Difficulty has presented itself in curing the internal surface of the canopy with a regularity sufficient to meet military specifications. This difficulty arises partly from the high degree of curvature of the canopy and the inability to provide an effective suitable ultraviolet curing process and procedure for such units. Other problems arise from the irregularity of the ultraviolet light source and from ambient conditions about and around the curing zone relative to the ultraviolet light source and also the operative requirements of the light source.
Many different compositions can be used on the canopy for providing different properties and these are illustrated, for instance, in the following patents, patent application and publications: U.S. Pat. No. 4,552,932; U.S. Pat. No. 4,544,466; U.S. Pat. No. 4,319,811; U.S. Pat. No. 4,707,586; U.S. Pat. No. 4,198,465; U.S. Pat. No. 4,263,366; and U.S. Pat. No. 4,308,120; U.S. patent application Ser. No. 158,579, filed Feb. 22, 1988 Applicants DeCamp, Raffo, Bimanand, assigned to Sierracin Corporation, entitled "Electrically Conductive Window and a Method for The Manufacture" and for which the declarations and assignments were signed on Feb. 17, 1988); Lyle H. McCarty, Design News, 102 (1986, September); E. C. Lupton, Plastics Engineering, 59 (1985, January); and C. F. Lewis, Materials Engineering, 40 (1987, November). The contents of the above patents, the patent application and publications are incorporated herein by reference.
It is an objective of the present invention to provide a device and method for curing units, particularly laminated polycarbonate aircraft canopies, and especially those which require great optical clarity. The invention seeks to overcome drawbacks with existing heat or ultraviolet light curing systems.

Curing compositions with ultraviolet light


Methods and systems for generating an optimal clearance schedule for inventory items in a retail enterprise. A method includes accessing historical sales data for a plurality of inventory items in a department of a retailer. A selection of an item is received and a set of possible discount schedules for the item are generated. Each schedule includes a set of prices and a price duration. A forecasting tool provides a sales performance of the item based on the historical sales data. An optimal clearance schedule is selected from the possible discount schedules.

Predicting sales for a retail enterprise system is useful to maximize revenue. At its most basic, forecasting sales may involve simply estimating future sales using historical sales data for similar inventory items. In more complex situations, historical sales data can be can be further analyzed to predict future sales using a variety of statistical models and algorithms. Such models and algorithms typically rely on past data including past sales of the same item as well as changes in circumstances between those past sales and a forecast sales period to predict future sales.
In the case of clearance items, it can be difficult to accurately predict sales of the item based on past sales of the same item. Because clearance items are items that will not be restocked, item demand changes over time, since selection for the item may decrease. In the case of apparel, specific sizes or colors may become unavailable over time, and as such demand will decrease for the remaining inventory. Additionally, because the goal for clearance items is not to maximize a profit margin on the item but instead to simply recoup as much revenue as possible on remaining stock, it may be difficult to develop an accurate model for pricing of items designated as clearance items. This may be particularly difficult where multiple clearance items have different likely demand lifespans (e.g., comparing a seasonal item to a general use item). This is further complicated for retailers offering a multitude of products, e.g. millions. There is a need for improved methods of determining a clearance schedule for inventory items within a retail enterprise.

Method and system for managing clearance items


A circuit and method thereof for sampling/holding signal is provided. The signal sampling/holding circuit comprises a first signal sampling/holding device, a second signal sampling/holding device, a target signal and a reference voltage. First, the first signal sampling/holding device is supplied with the reference voltage and the target signal. The reference voltage is disconnected from the first signal sampling/holding device before the target signal is. Similarly, the reference voltage is disconnected from the second signal sampling/holding device before the target signal is. Thus the target signal is respectively sampled and held in the first signal sampling/holding device and the second signal sampling/holding device.

1. Field of Invention
The present invention relates to a method and circuit thereof for signal sampling/holding, and more particularly, to a method of signal sampling/holding for lowering sampling noise.
2. Description of the Related Art
Signal sampling/holding is one of the major issues of electronic circuits. In order to capture signal characteristics efficiently, a proper signal sampling/holding is exerted. Taking an image sensor as an example, a signal sampling/holding circuit serves to sample and hold an image sensing signal precisely for further processing in back-end circuits. Increasing electronic products are featured with built-in video capturing function, for example, mobile phones, PDA and toys, etc. In order to be adapted to various requirements, especially portable electronic devices, an image sensor with lower power consumption and high resolution is desirable.
Referring to FIG. 1A, it illustrates a block diagram of a conventional image sensor. In FIG. 1A, the conventional image sensor comprises a pixel array 110, a row driver and a voltage reference 120, a sample and hold charge mode readout circuit 130, a gain stage 140 and an A/D converter 150. The row driver and voltage reference 120 provides a reference voltage VCL for each of the row driving signals 121 and the reference voltages 122. Each row electrode (not shown) of the pixel array 110 respectively receives a corresponding row driving signal 121, and the pixel array senses outputs column pixel signals 111 according to a timing signal of the row driving signal 121 after image is sensed by the pixel array 110. The sample and hold charge mode read out circuit 130 simultaneously receives, samples and holds each of the column pixel signals 111, and outputs the pixel signal 131 in cascade manner in response to the pixel signals. The gain stage 140 receives and amplifiers the pixel signal 131 and generates pixel signal 141. The A/D converter 150 is an A/D converter, e.g. a pipeline A/D converter, converting the analog pixel signals 141 into digital pixel signal 151 in response to the reference voltage 122, for further processing with the back-end circuits, e.g. a control logic 160 in this image sensor.
In the sample and hold charge mode readout circuit 130 of the image sensor, a pixel signal is captured to a sampling device (e.g. a capacitor) via a sampling switch. The charges that cause noise is transferred to the signal that is sampled during switching off the sampling switch, which is referred to random signal noise to the image, and image quality is thus lowered. Since the sampling switch noise of the pixel signal is randomly generated, it is hardly filtered out in the back-end circuits. For description purpose, a CMOS image sensor is illustrated as an example hereinafter. Referring to FIG. 1B, it illustrates a schematic circuit diagram of a sample and hold column circuit of a CMOS image sensor. For depicting purpose, one of the pixels in the pixel array is illustrated as a pixel 112 in FIG. 1B. Moreover, the sample and hold column circuit comprises a plurality of sample/hold circuits, wherein one circuit is illustrated as an example.
Referring to FIG. 1C, it illustrates a temporal waveform diagram of signals of the sample and hold circuit of the CMOS image sensor in FIG. 1B. Referring to FIGS. 1B and 1C, a CMOS image sensor requires a sampled pixel signal value and a sampled reset signal value, whereas a reference voltage VCL is required for sampling reference. A gate of a signal follower sf is coupled to a cathode of a photo diode PD. During period A for sampling pixel signal value, control signals row_en, clamp and samp_sig are switched to high logic level, whereas control signals rst_en, samp_rst, cb and col_addr are switched to low logic level. The photo diode PD is radiated by light, such that a reverse bias potential across the two terminals of the photo diode PD are lowered correspondingly, and a potential difference between the pixel signal value outputted via the signal follower sf and the reference voltage VCL is stored in the capacitor CS1. During period B for sampling reset signal value, the control signals row_en, rst_en, clamp and samp_rst are switched to high logic level, whereas the control signals samp_sig, cb and col_addr are switched to low logic level. Where the cathode of the photo diode PD is re-coupled to the system potential Vaa, from which a corresponding reset signal value of the signal follower sf is outputted. A potential difference between the reset signal value and the reference voltage VCL is thus stored in the capacitor CS2.
After pixel signal is sampled, the control signals samp_sig and samp_rst are switched to low logic level, and a sensing switch of the control signal clamp is switched off before entering period C for signal value holding. During period C for signal value holding, each of row pixel signals 111 is respectively held in one of the corresponding sample/hold circuits, where each of the sample/hold circuits sequentially switches on the sensing switches controlled by the control signals cb and col_addr in response to a timing signal, and pixel signals (including the pixel signal value and the reset signal value) 131 is outputted in sequence to the gain stage 140.
When period A for sampling pixel signal value is terminated, the sensing switch is turned off by the control signal samp_sig, i.e., the sensing switch is changed from on status to off status, an inevitable problem occurs. That is, the charges are distributed randomly along the sensing switch, and thus are transferred to the sampled pixel signal value as random noise. Moreover, before period B for sampling reset signal value is terminated, the sensing switch is turned off by the control signal samp_sig, i.e., the sensing switch is changed from open status to off status, an inevitable problem as well occurs. That is, the charges are distributed randomly along the sensing switch, and thus are transferred to the sampled pixel signal value as random noise. The foregoing random noise is referred as front-end noise of the data path, which is hardly filtered out by back-end circuits. When the pixel signal is amplified, the random noise is as well amplified with the pixel signal, thus a signal over noise ratio (S/N ratio) is lowered as well as image quality.

Method and circuit for sampling/holding a signal


A shift lever unit is disclosed, which comprises a shift lever; a housing of plastic having an upper cover portion, the upper cover portion being formed with a slot through which the shift lever passes; a position mark plate of transparent plastic mounted on the upper cover portion, the position mark plate having a plurality of position marks on an upper surface thereof; a light blocking layer covering the upper surface of the position mark plate except the positions where the position marks are located; a light source installed in the housing; a light conductive member of transparent plastic, the light conductive member including a horizontal part whose leading end is formed with a first light reflecting surface and located behind the position mark plate, a vertical part which is formed with a rounded recess from which the light rays from the light source enter the vertical part, and a jointed part at which the horizontal and vertical parts are jointed, the jointed part being formed with a second light reflecting surface by which the light rays from the rounded recess is reflected toward the first light reflecting surface; a plurality of raised window portions formed by the horizontal part of the light conductive member, the window portions being exposed to the outside of the housing at positions beside the position marks; and a pointer movably located within the housing below the raised window portions, the pointer being movable together with the shift lever, wherein the first light reflecting surface is granulated.

1. Field of the Invention
The present invention relates in general to shift lever units for automotive automatic transmissions, and more particularly to shift lever units of a type which is equipped with a shift position indicator.
2. Description of the Prior Art
In order to clarify the task of the present invention, one conventional shift lever unit will be described with reference to FIGS. 7 and 8 of the accompanying drawings.
As shown in FIG. 8, the conventional shift lever unit comprises a shift lever 51 which is pivotally supported by a support structure 46a secured to a base plate 46. The base plate 46 is tightly mounted on a vehicle floor (not shown) and has a housing structure mounted thereon, which structure includes generally a pair of U-shaped supporting brackets 45 and a shift lever position indicating device 40.
The position indicating device 40 comprises a stepped cover structure 41 of opaque plastic, which is mounted on the paired U-shaped supporting brackets 45 and formed with an elongate slot 41b through which the shift lever 51 extends.
As is understood from Pig. 7, the cover structure 41 is provided beside the elongate slot 41b with a transparent elongate part 41a which extends along the slot 41b. The transparent elongate part 41a comprises an elongate position plate 43 integrally molded with the cover structure 41. The position plate 43 is constructed of a transparent plastic, such as acrylate resin or the like, and has at a lower surface thereof engraved position marks 42, such as, "1", "2", "D", "N", "R" and "P". The engraved marks 42 are filled with white paint.
The lower surface of the position plate 43 is entirely coated with dark paint 43a except six limited portions 42a which are respectively located beside the position marks 42, as is seen from FIG. 8.
As is seen from FIG. 7, the position plate 43 has an inwardly projected portion 43b which is directed toward an electric lamp 52 mounted in a lamp housing secured to the cover structure 41. The position plate 43 has further a light reflecting surface 43c at a junction portion between the major part thereof and the inwardly projected portion 43b. Thus, upon energization of the lamp 52, the light emitted from the lamp 52 enters the position plate 43 from the inwardly projected portion 43b and is reflected by the light reflecting surface 43c toward the graved position marks 42. Thus, the position marks 42 are illuminated from within.
The position indicating device further comprises a pointer 44 which is colored red and movable together with the shift lever 51 along a given way which is defined below and along the aligned six limited transparent portions 42a. That is, when the shift lever 51 is moved to a certain position, for example, to the "reverse position" of the associated transmission, the pointer 44 assumes one paintless limited portion 42a which is located beside the position mark "R". Thus, the red color of the pointer 44 is viewed through the paintless limited portion 42a and thus the driver can easily recognize the position which the shift lever 51 has just assumed.
As shown in FIG. 8, a plurality of electric wires 49 extend from known electric devices mounted within the housing structure. These wires 49 are bundled into several groups each having an electric connector 50 connected thereto. The wires 49 are held by a resin-coated metal clip 47 which is welded to the base plate 46. That is, by bending the clip 47, the wire holding is achieved.
However, the above-mentioned conventional shift lever unit has the following drawbacks due to its inherent construction.
First, since the position plate 43 has an upper surface largely exposed to the outside of the cover structure 41, direct rays of the sun toWard the cover structure 41 causes a great reflection of the rays on the largely exposed upper surface of the position plate 43. This makes the recognition of the position marks and the pointer by the driver very difficult.
Second, upon energization of the electric lamp 52, part of the light rays from the lamp 52 reaches directly the pointer 44 without travelling within the position plate 43. This causes an extreme dazzling of the pointer 44.
Third, because the upper surface of the position plate 43 is largely exposed to the open air, the same is liable to flaw and crack due to increased possibility of being rubbed by something. This lowers the external appearance of the position plate 43 and thus that of the shift lever unit.

Shift lever unit for automotive automatic transmission


The present disclosure describes techniques and systems for wireless communication via a mobile relay. These techniques may include a user device that determines that a transceiver is unavailable for communicating with a base station via a wireless connection. The user device then uses a mobile relay to communicate with the base station while the transceiver is unavailable. The mobile relay may be used for transmitting or receiving data from the base station. Additionally or alternatively, the mobile relay may participate in the wireless connection as an external resource of the mobile device or may establish an independent wireless connection with the base station.

Wireless communication has become a leading medium for accessing and uploading data. With advances in wireless protocols, which facilitate improved upload and download speeds, wireless network providers are beginning to operate over signal waves at higher frequencies. The higher-frequency signal waves have an increased capacity for communicating data over a time interval based on an increased quantity of signal waves that can be communicated with a wireless device during the time interval. However, higher-frequency wireless networks, such as a 5th generation new radio (5G NR) wireless network, are more susceptible to fading, reflection off of an object, and signal distortion. This can lead to a decreased signal quality when compared with other wireless networks, such as a 4th generation long-term evolution (4G LTE) wireless network. For example, when a user's hand covers an antenna of a wireless device, a signal strength of a higher-frequency signal can be dramatically reduced.

Wireless communication via a mobile relay


A frequency multiplier device comprises a first signal combiner having a first port for receiving a first input signal having a first frequency f1 and a second port for receiving a second input signal having a second frequency f2, the first signal combiner configured to provide an output signal having either a sum of the first frequency and second frequency or a difference of the first frequency and second frequency; and a frequency divider having a dividing ratio N, the frequency divider configured to output a divided signal, wherein the output signal from the first signal combiner is coupled to the frequency divider, the divided signal from the frequency divider is coupled to the second port of the first signal combiner, and the output signal from the first signal combiner has a frequency of (N/(N±1))×f1.

1. Related Applications and Patents
U.S. patent application Ser. No. 11/621,357 (filed on Jan. 9, 2007) which is entitled "BROADBAND LOW NOISE COMPLEX REGENERATIVE FREQUENCY DIVIDERS" and Ser. No. 11/737,384 (filed on Apr. 19, 2007) which is entitled "BROADBAND LOW NOISE COMPLEX FREQUENCY MULTIPLIERS" are herein incorporated by reference. U.S. Patent Publication No. 20060057996 entitled "High frequency low noise phase-frequency detector and phase noise reduction method and apparatus" and U.S. Pat. No. 6,977,556 entitled "Rational frequency synthesizers" are also related to the subject matter and are herein incorporated by reference as well.
2. Field of the Invention
This invention relates to a device for performing frequency multiplication which exhibits low phase noise and low broadband noise. More particularly, the present invention employs integer, fractional and/or rational multiplication by using an array of Complex Frequency Shifters (CFS's) in combination with signal routing.
3. Background of the Related Art
Frequency multipliers along with frequency dividers are among the very essential building blocks in frequency generation and synthesis devices and are extensively used in these and many other applications. Signal sources with very low phase noise are increasingly more in demand as the frequencies utilized by such devices continue to increase along with the overall performance requirements. For example, the jitter of the clock caused by phase noise and broadband noise limits the achievable signal-to-noise ratio "SNR" in high speed ADCs/DACs. Reducing the clock jitter improves the achievable performance and allows higher frequency operation in demanding applications. This is one example among many where a low noise frequency multiplier allows for improved operating performance.
Numerous types of frequency multipliers are known in the art (e.g., frequency doublers), and include both analog and digital based devices. Generally speaking, analog multipliers have some advantages over digital multipliers in that they can operate at higher frequencies, achieve higher multiplication ratios, have lower phase noise and lower broadband noise, and consume less power. Analog multipliers can typically be divided in two categories: direct analog multipliers and the multipliers based on multiplying phase-lock loops or other schemes employing closed loop feedback systems or injection-locking mechanisms. As explained in detail below, the present invention falls within the category of direct analog multipliers.
Direct analog multipliers can further be divided into multipliers based on parametric nonlinearities of components, for instance nonlinear conductance or capacitive reactance and those using multiplying devices, such as mixers. Discrete circuits using nonlinearities of components such as diodes or transistors have been extensively used in the prior art, but typically need to be tuned to a specific frequency range or spectral component and are narrow-band. Mixer-based multipliers are a more systematic way of performing frequency multiplication, and provide wider bandwidth capabilities and have potential for larger multiplication ratios.
While devices for performing frequency multiplication by factorial of two (2) (for instance 2, 4, 8 . . . ) have been addressed in the prior art, that is not the case for frequency multiplication by an arbitrary integer factors. Also, generally speaking, devices for performing frequency multiplication by fractional or rational factor have not been addressed in the prior art. Further, the prior art fails to provide the rational frequency multiplier and synthesizer with low phase and broadband noise. Thus, there remains a need for a frequency multiplication device which provides for multiplication by integer, fractional and/or rational factors, which exhibits improved SNR and addresses the other limitations of the prior art devices noted above.


The embodiments herein describe a dynamic metal-oxide-semiconductor field-effect transistor (MOSFET) gate driver system architecture and control scheme. The MOSFET gate driver system dynamically adjusts both the gate driver turn-on-resistance and the gate driver turn-off resistance within a single (i.e., one) switching cycle to reduce electromagnetic interference (EMI) in the system and to minimize the conduction loss of a power MOSFET during operation.

1. Field of Technology
Embodiments disclosed herein relate generally to a gate driver system architecture and control scheme, and more specifically, to a gate driver system that dynamically adjusts drive current during a single switching cycle.
2. Description of the Related Arts
A power metal-oxide-semiconductor field-effect transistor (MOSFET) is a commonly used semi-conductor switching device in power electronics systems including switching-mode power supplies. The gate driver for the power MOSFET is critical to achieving high performance, such as low electro-magnetic interference (EMI), high efficiency and good control performance. FIG. 1 is a circuit diagram illustrating a conventional flyback type switching power converter 100 that uses a MOSFET Q1. The switching power converter 100 includes a power stage 105 and a secondary output stage 107. Power stage 105 includes the MOSFET Q1 and a power transformer T1. Power transformer T1 includes primary winding Np, secondary winding Ns, and auxiliary winding Na. Secondary output stage 107 includes diode D1 and output capacitor C1. Controller 101 controls the ON state and the OFF state of MOSFET Q1 using output drive signal 102 in the form of a pulse with on-times (TON) and off-times (TOFF). In other words, the controller 101 generates the output drive signal 102 that drives the MOSFET Q1.
AC power is received from an AC power source (not shown) and is rectified to provide the unregulated input voltage VDC. The input power is stored in transformer T1 while the switch Q1 is turned on, because the diode D1 becomes reverse biased when the MOSFET Q1 is turned on. The rectified input power is then transferred to an electronic device across the capacitor C1 while the switch Q1 is turned off, because the diode D1 becomes forward biased when the MOSFET Q1 is turned off. Diode D1 functions as an output rectifier and capacitor C1 functions as an output filter. The resulting regulated output voltage VOUT is delivered to the electronic device.
As mentioned previously, the controller 101 generates appropriate switch drive pulses 102 to control the on-times and off-times of MOSFET Q1 and regulate the output voltage VOUT. The controller 101 controls MOSFET Q1 using a feedback loop based on the sensed output voltage VSENSE and the sensed primary side current ID in previous switching cycles of the switching power converter, in a variety of operation modes including PWM (pulse width modulation) and/or PFM (pulse frequency modulation) modes. ISENSE is used to sense the primary current ID through the primary winding Np and switch Q1 in the form of a voltage across sense resistor RS.
The output voltage VOUT is reflected across auxiliary winding Na of transformer T1, which is input to controller 101 as the voltage VSENSE via a resistive voltage divider comprised of resistors R1 and R2. Based on the sensed output voltage, the controller 101 determines the operating frequency of the switching power converter 100 which dictates the frequency of the on-times (TON) and off-times (TOFF) in the output drive signal 102.
FIG. 2 illustrates a conventional gate driver system configuration included in the controller 101. The driver final stage comprises a high-side PMOS QP and a low-side NMOS QN. The high-side PMOS source is connected to Vcc, and the low-side NMOS source is connected to ground (GND). As shown in FIG. 2, the controller 101 comprises a gate driver control circuit 201. The gate driver control circuit 201 generates a switch control signal S, and the driver signals Sp and SN respectively for the PMOS QP and the NMOS QN.
FIG. 3 illustrates an equivalent circuit model often used for the analysis of MOSFET switching performance. The switching performance of a device is determined by the time required to establish voltage changes across parasitic capacitances of the device. RG represents the distributed resistance of the gate of the MOSFET. LS and LD respectively represent the source and drain lead inductances of the MOSFET. CGD represents the gate-to-drain capacitance (i.e., the miller capacitance) of the MOSFET and is a nonlinear function of voltage. CGS and CDS respectively represent the gate-to-source capacitance and the drain-to-source capacitance of the MOSFET. Lastly, the equivalent circuit model illustrates the body-drain diode across the drain and source of the MOSFET.
The MOSFET operation can be understood referring to detailed waveforms illustrated in FIG. 4. Generally, FIG. 4 illustrates the current ISENSE which corresponds to the drain current ID of the power MOSFET Q1, the switch control signal S, the gate driver signal SN for the driver low-side NMOS QN, the gate driver signal SP for the driver high-side PMOS QP, the gate-to-source voltage VGS of the MOSFET Q1, and the drain-to-source voltage VDS of the MOSFET Q1 at various times within a switching cycle.
At time t0, the controller 101 turns on Q1 by issuing a high 401 switch control signal S and turns off the low-side NMOS QN by issuing a low 403 gate driver signal SN. At time t1, after a short-time delay that prevents shoot through between the high-side PMOS QP and low-side NMOS QN, the controller 101 sets the gate driver signal SP to low 405 which turns on the high-side PMOS QP. During the time interval [t1, t2], the gate drive current charges the input capacitor of Q1. The current flows through the high-side PMOS QP, and the on-state resistance Rds(on)_P of the high-side PMOS QP serves as the gate resistance Rg that affects the drive current used to drive power MOSFET Q1. When the gate-to-source voltage VGS of Q1 rises 407 above the threshold voltage VTH for MOSFET Q1, Q1 starts to conduct. During the time interval [t1, t2], the drain-to-source voltage VDS of MOSFET Q1 still maintains high voltage 409, e.g., VDS=VDC. VDC can be ˜300V or higher depending on the system configuration.
During the time interval [t2, t3], the gate-to-source voltage VGS of Q1 reaches a plateau 411 and stays at this plateau 411. Furthermore, the drive current mainly charges the miller capacitor CGD of Q1. As shown in FIG. 4, the drain-to-source voltage VDS of Q1 decreases 413 during time interval [t2, t3] represented by dV/dt. The rate of change dV/dt of the drain-to-source voltage VDS of Q1 coupled with the drain-to-source capacitor CDS of Q1 and the parasitic capacitance of the transformer generates the current spike 415 in the drain current ID by means of C*dV/dt. During the time interval [t3, t4], when the drain-to-source voltage VDS of Q1 decreases to a low level 417, the miller capacitor CGD is fully charged, and the drive current mainly charges the gate-to-source capacitor CGS of Q1. During the time interval [t3, t4], the gate-to-source voltage VGS rises 419 and eventually reaches near VCC. The turn-on transition of Q1 is completed. During the time interval [t4, t5], the gate-to-source voltage VGS is maintained near VCC and the drain-to-source voltage VDS of Q1 remains at the low level 417. Furthermore, during the time interval [t4, t5], the drain current ID rises 421 towards the ideal peak.
At time t5, the controller 101 decides to turn-off Q1 shown by the switch control signal S going low 423, and the gate driver signal Sp is set high 425 which turns off the high-side PMOS QP. As shown in FIG. 4, the drain current ID reaches the ideal peak at time t5. At time t5, the gate driver signal SN remains low 403. Furthermore, at time t5 the gate-to-source voltage VGS is maintained near VCC and the drain-to-source voltage VDS of Q1 remains at the low level 417.
At time t6, after a short time delay that prevents the shoot through between the high side PMOS QP and the low side NMOS QN, the gate driver signal SN is set to high 427 which turns on the low side NMOS QN. During time interval [t6, t7], the low side NMOS QN provides the path to discharge capacitor CGS, and the on-state resistance Rds(on)_N of the low side NMOS QN affects the discharge current. As shown in FIG. 4, the gate-to-source voltage VGS of Q1 decreases 429 from VCC to a plateau 431 that is less than VCC but greater than VTH and the drain-to-source voltage VDS of Q1 stays at the low level 417.
During the time interval [t7, t8], the gate-to-source voltage VGS of Q1 remains at the plateau 431 and the drive current mainly discharges the miller capacitor CGD of Q1. Furthermore, the drain-to-source voltage VDS rises 433 towards the high voltage 409 during the time interval [t7, t8] which is represented by dV/dt. During the time interval [t8, t9], (without considering high-frequency ringing and other parasitic effects) the drain-to-source voltage VDS of Q1 reaches the maximum DC voltage 409 and the drive current mainly discharge the capacitor CGS. Furthermore, the gate-to-source voltage VGS of Q1 decreases 435. Once the gate-to-source voltage VGS decreases below the threshold voltage VTH, Q1 is turned off and the drain current ID reaches the actual peak at time t9 and decays 437 to zero. The turn-off transition of the Q1 is completed.


In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer periphery of each of the two insulation-filled trench regions. A ratio of a width of each of the insulation-filled trench regions to a width of the drift region is adjusted so that an output capacitance of the MOSFET is minimized.

Power field effect transistors, e.g., MOSFETs (metal oxide semiconductor field effect transistors), are well-known in the semiconductor industry. One type of power MOSFET is a DMOS (double-diffused metal oxide semiconductor) transistor. A cross-sectional view of a portion of a cell array of one known variety of DMOS transistors is shown in FIG. 1. As shown, an n-type epitaxial layer 102 overlies n-type substrate region 100 to which the drain contact is made. Polysilicon-filled trenches extend into the epitaxial layer 102 from the top surface. The polysilicon 106a, 106b in the trenches are insulated from the epitaxial layer by oxide layers 104a, 104b. Source regions 108a, 108b in p-type body regions 110a, 110b are adjacent the trenches at the top surface. A polysilicon gate 114 overlaps the source regions 108a,b, extends over a surface portion of the body regions 110a,b, and extends over a surface area of a region between the two trenches commonly referred to as the mesa drift region. Metal layer 116 electrically shorts source regions 108a,b to body regions 110a,b and polysilicon 106a,b in the trenches. The surface area of body regions 110a,b directly underneath gate 114 defines the transistor channel region. The area between body regions 110a and 110b under gate 114 is commonly referred to as the JFET region.
Upon applying a positive voltage to the gate and the drain, and grounding the source and the body regions, the channel region is inverted. A current thus starts to flow from the drain to the source through the drift region and the surface channel region.
A maximum forward blocking voltage, hereinafter referred to as "the breakdown voltage", is determined by the avalanche breakdown voltage of a reverse-biased body-drain junction. The DMOS structure in FIG. 1 has a high breakdown voltage due to the polysilicon-filled trenches. Polysilicon 106a,b cause the depletion layer formed as a result of the reverse-biased body-drain junction to be pushed deeper into the drift region. By increasing the depletion region depth without increasing the electric field, the breakdown voltage is increased without having to resort to reducing the doping concentration in the drift region which would otherwise increase the transistor on-resistance.
A drawback of the FIG. 1 structure is its high output capacitance Coss, making this structure less attractive for high frequency applications such as radio frequency (RF) devices for power amplifiers in the wireless communication base stations. The output capacitance Coss of the FIG. 1 structure is primarily made up of: (i) the capacitance across the oxide between the polysilicon in the trenches and the drift region (i.e., Cox), in series with (ii) the capacitance across the depletion region at the body-drift region junction. Cox is a fixed capacitance while the depletion capacitance is inversely proportional to the body-drain bias.
The breakdown voltage of power MOSFETs is dependent not only upon the cell structure but also on the manner in which the device is terminated at its outer edges. To achieve a high breakdown voltage for the device as a whole, the breakdown voltage at the outer edges must be at least as high as that for the cells. Thus, for any cell structure, a corresponding terminating structure is needed which exhibits a high breakdown voltage.
In most amplifier circuits a significant amount of heat energy is produced in the transistor. Only 50% efficiency is typical of the best class AB RF power amplifiers available. An important factor in designing power devices for high frequency applications is thus the thermal performance of the device. Because of the different device performance requirements, the cells in power MOSFETs are densely packed resulting in concentration of heat in active regions and poor heat transfer rates. The increase in temperature resulting from the poor heat transfer rate adversely effects the device performance.
Thus, a power MOSFET device with such improved characteristics as low output capacitance, high breakdown voltage, and improved thermal performance is desired.

Vertical charge control semiconductor device with low output capacitance


The present application relates to a wheel balancer which includes a stationary frame, a measuring shaft mounted rotatably about a shaft axis on the stationary frame and adapted to receive coaxially a rim/tyre assembly. The wheel balancer further includes an encoder configured to determine the angular positions of the measuring shaft or of the rim/tyre assembly, a load device configured to apply a load to the periphery of the rim/tyre assembly, a first measuring device configured to measure forces resulting from an unbalance of the rotating rim/tyre assembly, a second measuring device configured to measure forces acting between the load device and the periphery of the rim/tyre assembly, and a locking device configured to keep the distance between the shaft axis and a contact portion at which the periphery of the rim/tyre assembly contacts the load device constant during the measurement of the forces acting between the load device and the periphery of the rim/tyre assembly.

The invention concerns a wheel balancer adapted to measure forces resulting from an unbalance of a rotating rim/tyre assembly, in particular a vehicle wheel, and a method for determining tyre uniformity performed on the wheel balancer.
Such a wheel balancer and such a method are known from EP 1 731 891 A1 and from EP 1 742 031 A1. The known wheel balancers are equipped with a load roller which is pressed against the peripheral surface of the tyre with predetermined force. During the rotation of the rim/tyre assembly the movement of the load roller is measured to determine the loaded radial runout of the rim/tyre assembly. Radial force variation can be measured wherein the load roller is rigidly mounted. Further, tyre stiffness is determined by applying at least two different loads to the load roller and measuring the change in deflection. A matching operation during which the tyre is remounted on the rim is disclosed in order to minimize vibration of the rotating rim/tyre assembly.

Wheel balancer with means for determining tyre uniformity


A computer-implemented candidate assessment system is configured to identify the drive characteristics of a candidate having taken a personality test. The system includes a characteristic identification engine configured to identify at least a candidate achievement score, a candidate competitiveness score, and a candidate optimism score, a candidate assessment engine configured to determine a drive core skill score based on a combination of the candidate achievement score, candidate competitiveness score, and candidate optimism score. The drive score is determined with weighting using the achievement score. The system also includes a reporting engine configured to generate a profile report including the drive core skill score.

The present disclosure relates generally to the field of employment and/or aptitude assessment. More particularly, the present disclosure relates to a system and method for candidate assessment by identifying drive characteristics of an candidate.
Highly skilled sales representatives are an important part of many businesses. However, identifying job candidates and/or current employees that will become highly skilled sales representatives is a difficult task. Sales managers often specifically request a person that is driven, but they are unable to define what that means or how these characteristics can be recognized.
Personality tests are often administered to candidates to attempt to identify candidates having the necessary characteristics to become high performing salespeople. However, these personality tests do not always recognize and/or properly account for those characteristics that are indicative of a person that is likely to become a high performing salesperson.
Accordingly, there exists a need for a system and method for candidate assessment by identifying drive characteristics of an candidate. What is further needed is such a system and method configured to utilize an existing personality test.

System and method for candidate assessment