There is provided a data processing apparatus capable of increasing a number of general purpose registers while maintaining upper compatibility. Register designating information for designating a register is divided in two portions. The two portions are arranged in separate basic units on the basic units of an instruction code. When one instruction code is made ignorable and the ignorable instruction code is ignored, a control unit (CONT) executes register selecting operation by implicitly assuming predetermined register designating information. Thereby, when only a general purpose register (existing general purpose register) capable of being designated implicitly is used, the ignorable instruction code can be ignored and accordingly, the instruction codes are not increased. When an at least conventionally equivalent general purpose register is used, a conventionally equivalent instruction code may be used. By preventing the instruction codes from increasing, processing speed is not reduced.

1. Field of the Invention
The present invention relates to a data processing apparatus such as microcomputer, microprocessor, data processor, CPU (Central Processing Unit), particularly to register architecture, upper compatibility and expansion of operational function, for example, a technology effective by applying to effective utilization of software resources, expansion of operational function and promotion of usability in a single chip microcomputer.
2. Description of the Related Art
According to a microcomputer in the form of a semiconductor integrated circuit, expansion of an address space, enlargement of an instruction set and high speed formation have been achieved. According to CPU (Central Processing Unit) of a microcomputer, its function is defined by softwares and accordingly, even in a microcomputer achieving expansion of an address space, enlargement of an instruction set and high speed formation, it is preferable to be able to effectively utilize software resources of an existing microcomputer.
Therefore, as an example of realizing the expansion of an address space and the enlargement of an instruction set while maintaining compatibility at an object level, there is provided a microcomputer disclosed in, for example, Japanese Patent Laid-Open No. 51981/1994. The publication discloses that it is effective for achieving expansion of an instruction set to adopt a load store architecture such as a so-to-speak RISC (Reduced Instruction Set Computer) architecture.
According to the load store architecture, an operational processing is executed by using general purpose registers of CPU. That is, there is not executed an operation directly using data on a memory, the data on the memory is temporarily transferred to the general purpose registers, the operation is executed on the transfer data and thereafter, a result of operation on the general purpose registers is rewritten to the memory. Therefore, when there is a general purpose register which is not used in the processing, the data on the memory may be transferred to the general purpose register. However, a number of the general purpose registers is limited and depending on a processing situation at inside of the microcomputer, there also is a case in which all of the general purpose registers are used. When all of the general purpose registers are used, in other words, when contents of all the general purpose registers must be held, before executing an operation with regard to data on the memory, after saving the contents of the general purpose registers to stack areas or the like, a required processing is executed and after finishing the processing, in order to restart an interrupted processing, the saved contents of the general purpose registers must be returned.
(Study Problem A)
As study problem A, the inventors have studied to increase general purpose registers of CPU while enabling to effectively utilize software resources by maintaining compatibility. Further, although matters concerning the study problem A are constituted by a content which has already been disclosed in the specification of Japanese Patent Application No. Hei 11-123450 which is a first Japanese basic application related to the present application, the content is not publicly known yet. A description will be given of the study problem A.
According to CPU adopting the load store architecture, data processing is executed centering on general purpose registers of CPU and accordingly, it is convenient that a number of the general purpose registers is large. Thereby, easiness or high speed formation of program can be achieved.
However, at which of general purpose registers the processing is executed, is generally designated by an instruction code and accordingly, it is necessary to hold a register designating field in correspondence with a number of the general purpose registers at inside of the instruction code. For example, 4 bits of the register designating field are needed for 16 of the general purpose registers. When the general purpose registers are intended to increase, the register designating field is increased. When the general purpose registers are increased to 64 which is 4 times as much as 16, 6 bits of the register designating field are needed. A processing object generally comprises data of 2 (source and destination) and therefore, a doubled bit number is needed in the register designating field.
When a basic unit of instruction is constituted by, for example, 16 bits (hereinafter, referred to as xe2x80x9cwordxe2x80x9d), a rate of the bit number occupied by the register designating field is increased and as a result, a length of an instruction code is obliged to increase. Prolongation of the instruction code amounts to a reduction in the processing speed. The reason is that CPU executes operation after reading instruction and when a number of words (bit number) of instruction to be read becomes large, a number of reading the instruction per se is also increased. Further, enlargement of the register designating field is not compatible with existing instruction of existing CPU and compatibility with existing CPU becomes difficult to maintain.
As a technology of apparently increasing general purpose registers, there is provided a register bank system in which the general purpose registers are classified into groups referred to as bank and any of the banks are exclusively selected. Which bank is selected is designated by a control register or control instruction. Therefore, the instruction code is provided with only a register designating field in correspondence with the general purpose registers in the bank and the increase in the length of the instruction code can be restrained. However, there is needed an instruction for switching the register banks, further, in forming a program, which bank is to be selected must be conscious of and easiness of the program is liable to deteriorate. A number of the general purpose registers capable of being used at the same time is not increased and accordingly, when there is a task having a large amount of data and a task having a small amount of data, it is difficult to circulate each other allocation of the general purpose registers.
It is an object of the invention with regard to the study problem A to provide a data processing apparatus capable of increasing a number of general purpose registers while maintaining upper compatibility.
It is other object of the invention with regard to the study problem A to provide a data processing apparatus capable of increasing a number of general purpose registers without increasing overall instruction codes.
It is still other object of the invention with regard to the study problem A to provide a data processing apparatus capable of realizing easiness of program formation and promotion of processing function of CPU by increasing a number of general purpose registers while maintaining upper compatibility with regard to software resources.
(Study Problem B)
As study problem B, the inventors has studied capability of effectively utilizing software resources by maintaining compatibility with regard to an architecture of a load store type (achieving upper compatibility with regard to software resources) and capability of directly operating data on a memory while maintaining advantages of existing CPU such that a load store architecture or an RISC architecture is advantageous in improving operational speed. Further, although matters with regard to the study problem B have already been disclosed in the specification of Japanese Patent Application No. Hei 11-151890 which is a second Japanese basic application related to the present invention, the content has not been publicly known yet. A description will be given of the study problem B.
Advantages which seem to provide by making data on a memory directly operable are as follows.
When not only an operation is executed by loading data to a general purpose register but also the operation can be executed with regard to data on a memory without loading the data to the general purpose register, the operation can be executed with regard to all of the data which can be used by CPU or a microcomputer, in other words, all the data which a user of the microcomputer can designate on a program and accordingly, the usability, that is, the function of the microcomputer is promoted.
In this case, the instruction executed by CPU designates whereabouts of data and content of processing thereof. A way of designating whereabouts of data is referred to as addressing mode. When operation of data on a memory can be executed only by a specific addressing mode, a restriction in view of programming is brought about and easiness of use cannot sufficiently be promoted. It seems to be preferable that data on the memory can be operated by an arbitrary combination of addressing modes accessing data by existing CPU.
Further, even when data on the memory can directly be operable, it is preferable to process data having a high frequency of use by arranging the data on a general purpose register. A general purpose register is constituted physically as a portion of CPU and accordingly, the general purpose register can be accessed at a speed higher than that of the memory and accordingly, data on the general purpose register can be processed at a speed higher than that of the data on the memory. Data having a low frequency of use may be processed while arranging the data on the memory. A general purpose register having no direct relationship with processing of CPU may not be saved or returned from the general purpose register. Thereby, it seems that the processing speed of CPU can be promoted as a whole.
Normally, an amount of data processed by CPU or microcomputer is larger than a number of general purpose registers of CPU. Further, there are a plurality of tasks and the tasks are executed by time sharing and accordingly, in the case of switching the tasks, when data on the memory can directly be operated, the data is not saved to or returned from the general purpose register and a processing can be executed immediately with regard to the memory. A convenient method can be selected while interweaving a processing method of executing operation at high speed by using general purpose registers although being accompanied by processings of save and return. Similarly, also in the case of an interruption processing, without saving data to general purpose registers, a processing can be executed immediately with regard to a memory and response time until executing a desired processing in response to interruption can also be shortened. By shortening the response time of interruption, temporal accuracy in the case of controlling various apparatus, or so-to-speak real time performance can be promoted.
When a program of looping (repeating) the same processing routine is formed, in order to ensure a general purpose register necessary for an operational processing in the loop, further, reduce an overall program capacity and shorten a processing time period, by ensuring a register allocated with data used outside of the loop, even in the case in which the general purpose register is not provided with allowance, at any time, the operational processing can be executed with regard to the memory. Thereby, formation of the program is facilitated. Further, by shortening the processing in the loop, as a whole, it is anticipated that the processing time period can be shortened in proportion to a number of times of repetition.
Further, in developing a development apparatus such as C compiler, such various conditions need to consider, by enabling operation with regard to the memory, it seems that development time period and resources necessary for achieving a desired function of the C compiler can also be saved.
Further, high speed formation, high function formation and small size formation of apparatus, as described above, are requested also to CPU or microprocessor having comparatively small address space and comparatively small instruction set and accordingly, when there are present CPU having wide address space and CPU having narrow address space disclosed in Japanese Patent Laid-Open No. 51981/1994, it is preferable to add operation with regard to data on a memory to both of CPU""s.
However, in achieving upper compatibility with regard to software resources, as mentioned above, and making data on a memory directly operable, the following problem is posed as clarified by the inventors.
Existing instruction set is optimized within the specification and accordingly, there is only small room for allocating new instruction code to processing of various operations for making the data on the memory directly operable. That is, with regard to desired operation of addition or logical product, it is actually difficult to allocate the new instruction code such that the data on the memory can be operated with an arbitrary combination of addressing modes for accessing the data.
Further, alteration of a system of instruction codes by adding new instruction codes or new addressing modes, is incompatible with existing instruction in existing CPU and makes it difficult to maintain compatibility with existing CPU. Further, the merit of existing CPU is deteriorated.
Further, in the case of developing a system using a microcomputer, there is used a development apparatus referred to as an emulator. An emulator is mounted with a processor for emulation incorporating the function of the microcomputer and the processor for emulation outputs a signal for emulation such that an operational state of the microcomputer can be analyzed by the emulator. An emulator and a processor for emulation are disclosed in Japanese Patent Laid-Open No. 263290/1996. There has been clarified the problem in which when the constitution of the microcomputer is modified to make the data on the memory directly operable, in the case in which the signal for emulation is also modified, the hardware per se of the emulator must be modified, the emulator per se must newly be developed and provision of the development apparatus or a development environment of the microcomputer is delayed.
It is an object of the invention with regard to the study problem B to provide a data processing apparatus capable of directly executing operation with regard to data on a memory, apparently, while minimizing an increase in a logical and physical scale of the data processing apparatus and maintaining compatibility with existing CPU or microcomputer having an instruction set of a load store type.
It is other object of the invention with regard to the study problem B to promote a processing function of CPU by facilitating programming and restraining an undesired general purpose register from saving or returning by enabling an operation with regard to data on a memory, apparently.
(Study Problem C)
The inventors have further clarified the following as study problem C in realizing upper compatibility with regard to software resources which have been investigated as the study problem A and capability of directly operating data on a memory which has been investigated as the study problem B as described above. Further, although matters related to the study problem C have already been disclosed in the specification of Japanese Patent Application No. 11-191608 which is a third Japanese basic application related to the present application, the content is not publicly known yet. A description will be given of the study problem C.
An existing instruction set is optimized within the specification and accordingly, there is small room for allocating a new instruction code to processings of various operations for making the data on the memory directly operable. That is, with regard to desired operation of addition or logical product, it is actually difficult to consider to allocate a new instruction code such that the data on the memory can be operated by an arbitrary combination of the addressing modes accessing the data.
Further, alteration of a system of instruction codes by adding new instruction codes or new addressing modes is not compatible with existing instruction in existing CPU and makes difficult to maintain compatibility with existing CPU. Further, the merit of existing CPU is deteriorated.
Hence, the inventors have previously found usefulness in capability of operation on the memory by using a front instruction code combining and coupling a plurality of instruction codes in an existing ones of a single or a plurality of transfer instructions between the memory and a register and operation instructions between the registers. According thereto, instruction codes of the transfer instructions between the memory and the register and the operation instructions between the registers are existing and accordingly, a single one of them is operated similar to the conventional case and execution of the existing instructions is not hampered. Further, when only the existing instructions are used, existing software resources can effectively be utilized. The operational function can be expanded without deteriorating the merit provided to existing CPU such as general purpose register system or load store architecture.
Further, the inventors have also studied various requests with regard to a microcomputer having a wide application field. For example, there are an application field having a wide address space and an application field having a small address field, an application field mainly using programming by high-level language and an application field mainly using program by assembly language, an application field in which data processing is important and an application field in which control of bit operation is needed, or an application field in which processing function is needed and an application field in which a reduction in expense is needed more than the processing function and with regard to these, it is preferable to be able to provide CPU (Central Processing Unit) by an integrated architecture and commonly use a development apparatus of a software development apparatus (cross software) such as assembler or C compiler.
Hence, the inventors have studied with regard to CPU having lower compatibility. As described above, according to the previous proposal by the inventors, even with regard to existing CPU having a small address space, general purpose registers can be added and operation with regard to the memory can be added while maintaining compatibility. In the case of adding function, the inventors have found a necessity of a consideration to meet sufficiently various requests to a microcomputer, described above, such as pursuit of a reduction in expense.
Further, programming by assembly language is much dependent on an instruction set of CPU and there is so-to-speak preference by experience of a user and accordingly, all the requests cannot be met by one instruction set. For example, although it is easy to shift to other CPU or CPU having an instruction set preferred by the user, there is brought about a limit in CPU having the same instruction set.
There is a general purpose register system or an accumulator system in architecture of a microcomputer or CPU and accordingly, when there is provided CPU having an instruction set similar thereto respectively, it seems that a request with regard to instruction sets of most of the users can be met. At least, by preparing CPU having various kinds of instruction sets rather than a single instruction set, a range capable of dealing therewith can significantly be enlarged.
In this case, according to these CPU""s, even when a number of independent ones are prepared, in the case in which compatibility or transportability of software are deteriorated, for the user, software cannot be transported, software is modified, an overall development expense is undesirably obliged to increase or development time period is undesirably obliged to increase. On the other hand, for a provider of CPU or a microcomputer, in independent CPU""s, technologies used differ from each other, a technology provided by one CPU is difficult to apply to other CPU, development efficiency is deteriorated and promotion of function is difficult to achieve.
Further, when a system using a microcomputer is developed, a software development apparatus and a development apparatus referred to as emulator are used.
With regard to a software development apparatus such as an assembler, a C compiler or a simulator debugger, it has been clarified by the inventors that it is preferable that a plurality of CPU""s having compatibility, described above, can commonly be utilized including CPU which is not provided with instruction sets in which one of the instruction sets incorporates other thereof. Also for the user, when a software development apparatus is made common and is applicable to different CPU""s, when CPU is changed, undesirable expense is not brought about. Also for the supplier, only one development apparatus may be developed, the development efficiency can be promoted and promotion of function of the development apparatus and promotion of usability are easy to achieve pertinently. While enjoying easiness of programming by assembly language, successive shift to high-level language is made possible.
Although in Japanese Patent Laid-Open No. 198272/1997, there is a description with regard to an emulator and a processor for emulation capable of dealing with a plurality of CPU""s in which particularly, one of instruction sets or register constitutions incorporates other thereof, as described above, in the case of such a plurality of CPU""s, various requests of application fields cannot sufficiently be met. Although it is conceivable to prepare higher CPU incorporating both functions for a plurality of CPU""s in which one of instruction sets does not incorporate other thereof, with regard to a totally different plurality of CPU""s, the instruction codes differ, address spaces or methods of calculating effective addresses differ and accordingly, it is difficult to constitute higher CPU incorporating these. Further, even when the constitution is possible, it seems that large development resources are needed and there cannot be achieved an object of saving various resources necessary for development. Further, higher CPU is provided with redundant circuits to incorporate functions of the different plurality of CPU""s, which is difficult to use in an actual product and when it is used by being switched to individual CPU, it is not regarded as new CPU and there cannot be achieved an object of meeting various requests of application fields.
It is an object of the invention with regard to the study problem C, firstly, to provide a data processing apparatus capable of meeting wide request of application field or user. Specifically, it is the object of the invention to realize that fabrication expense of a semiconductor integrated circuit is reduced and accordingly, expense of the semiconductor integrated circuit of the user is reduced, request in view of software of an application field is easy to meet or programming by assembly language is also facilitated such that preference of the user to a microcomputer is met or a user is easy to shift from other CPU.
It is the object of the invention with regard to study problem C, secondary, to reduce development expense of a group of products of data processing apparatus such as a general microcomputer and to promote the development efficiency. In other words, the object is to provide a plurality of CPU""s suitable for individual application fields or systems, to reduce general development expense of the plurality of CPU""s and to promote the development efficiency. Specifically, it is the object to easily realize that compatibility or inheritance of software resources is maintained, the software development efficiency of the user is promoted, request of function or performance is met, request for promotion of the function or performance is made to be easy to meet further continuously, in shifting of CPU, undesirable expense of the user is prevented, an increase in an desirable expense of the user is prevented by enabling to utilize commonly a software development apparatus or a development environment such as an emulator or the development efficiency of the development environment is promoted and pertinently improved.
It is the object of the invention with regard to the study problem C, thirdly, to provide a data processing apparatus such as CPU having an address space preferable to a single chip microcomputer having a comparatively large program capacity and yet having a comparatively small data capacity, that is, a data processing apparatus such as CPU having a wide address space and a reduced logical scale.
(Study Problem D)
The inventors have studied with regard to a composite instruction contributing to shortening of a length of an instruction code and promotion of processing function in view of a branch instruction as new study problem D related to the study problem B. A description will be given of the study problem D.
According to a general microcomputer system, processing of CPU is executed to adapt to an outer input state. The processing is executed by branching a program in accordance with states of input and output ports and based thereon, in accordance with a state of bits held in built-in RAM.
As means for realizing such a processing of CPU in correspondence with outer input state, as described in U.S. Pat. No. 4,334,268, there is a data processor having instruction of so-to-speak bit test and branch. According thereto, a bit to be tested is designated by an absolute address of 8 bits and a bit number of 3 bits and whether a branch condition is brought into a logical value xe2x80x9c1xe2x80x9d state of the designated bit or a logical value xe2x80x9c0xe2x80x9d state is designated by 1 bit and an address of branch destination is designated by a displacement of 8 bits. In this case, in the case of an instruction code having a length of 3 bytes, designation of instruction must be executed by 4 bits. In this example, front 4 bits of an instruction code having the logical value xe2x80x9c0xe2x80x9d constitute bit test and branch. Therefore, in the case of an instruction other than thereof, front 4 bits must be constituted by values 1 through F and an overall instruction code length is liable to increase.
It has been found by the inventors that such an instruction is liable to increase a logical scale since instruction execution control is complicated as in reading and determining the designated bit and forming the branch address, further, promotion of operational frequency is liable to hamper by undesirable delay of a logical circuit.
Further, capability of designating by the 8 bit absolute address is restricted to 256 bytes and accordingly, when inner I/O registers are increased in accordance with high function formation of a microcomputer, a desired bit may not be present in a designatable range or address arrangement thereof becomes difficult in view of specification and design of the microcomputer. That is, although the microcomputer is made generally usable, there are provided a plurality of bits constituting determination objects, which differ from each other according to respective application fields or users and it is difficult to meet all of the requests of desired combinations with regard to the bits constituting the determination objects.
Further, when the control becomes complicated, there is brought about a case in which branch cannot be executed with a relative address of 8 bits. Branch can be executed only in a range of +127 through xe2x88x92128 bytes with an address where the relevant instruction is present or an address where successive instruction is present as a reference and accordingly, at least one of processing programs executed when the bit of the determination object is the logical value xe2x80x9c1xe2x80x9d and when the bit is the logical value xe2x80x9c0xe2x80x9d (processing program executed when the branch condition is not established), needs to be smaller than 127 bytes. When this cannot be satisfied, by using also other branch instruction, by executing two stages of branch instruction, branch must be executed to a required address. The inventors have found that this complicates the program and lowers also the processing speed.
When the absolute address or the displacement is constituted by 16 bits to avoid this, there is necessarily brought about an increase in the instruction code length and the processing speed is also lowered and the instruction execution control is further complicated. When there are provided a plurality of combinations of absolute addresses and the bit lengths of the displacement, the instruction execution control is further complicated. These amount to an increase of kinds of instruction to be added and make it difficult to maintain upper compatibility of existing CPU. Advantages of existing CPU (conciseness of logical constitution or high speed performance) is difficult to maintain.
It is an object of the invention with regard to the study matter D that an increase in the logical and physical scale is minimized, while maintaining compatibility with existing CPU, a state of bits of data of an arbitrary address on a memory is determined and branch and branch of subroutine are made possible. Further, it is an object thereof to realize promotion of usability of CPU, shortening of the instruction code length and promotion of the processing function.
(Study Problem E)
As study problem E, the inventors have studied to execute reading/writing with regard to a plurality of general purpose registers by single instruction. Further, although matters with regard to the study problem E have already been disclosed in the specification of Japanese Patent Application No. Hei 11-320518 which is a fourth Japanese basic application related to the present application, the content has not publicly known yet. A description will be given of the study problem E.
Information of packet command in data transfer is a set of a plurality of information and is constituted by, for example, 16 bytes which is larger than that of a data processing unit of CPU. CPU reads and analyzes individual information (command, transfer byte number, transfer location). For example, command is constituted by 8 bits, transfer byte number is constituted by 32 bits and transfer location (address) is constituted by 32 bits and these individual information is provided with a data length operable by CPU in many cases.
Further, print data of a printer is larger than the data length operated by CPU. These are a set of individual bits (dots, pixels). In operating these, not an arithmetic processing but a processing of a bit unit is executed and a logical processing is mainly needed. In processing such data, the processing is executed by being divided in plural times in a unit of data operated by CPU. That is, there are repeated reading data from a memory, processing the data on general purpose registers and writing a result to the memory.
The inventors have further studied a mode of utilizing general purpose registers. The packet command or print data is larger than a data unit of a data processing by CPU such as word. The inventors have found that it is convenient in view of achieving high speed formation of data processing when data of such a data unit larger than the data unit of the data processing by CPU can summarizingly read from a register or can be written to a register. The reason is specifically that according to CPU of a so-to-speak von Newmann type, in executing transfer instruction, it is necessary to read an instruction code, decode the instruction code and read/write data and accordingly, rather than repeating in plural times transfer of such data to a register by a unit of byte or word, reading/writing of a plurality of general purpose registers is executed by single instruction to thereby enable to reduce a number of times of reading instruction codes for data transfer.
Further, it has bee found that when combined with a technology of expanding general purpose registers by the ignorable word, it becomes easy to expand general purpose registers thereby and vacate the registers to summarizingly read/write a plurality of the general purpose registers.
Meanwhile, according to CPU disclosed in Japanese Patent Laid-Open No. 263290/1996 previously proposed by the inventors, there is fixed a combination of a plurality of general purpose registers which can be designated to controlling means for controlling executing means for executing instruction, there is provided save/return instruction with regard to stacks of the plurality of general purpose registers and the plurality of general purpose registers are successively saved/returned. This is limited to a processing having an object of preserving a state of the processing before a break point of the processing such as subroutine or exception processing. Therefore, an addressing mode is also limited to predecrement (save)/postincrement (return) of a stack pointer. Further, address calculation is executed by using an address functional unit at each time of save/return of a general purpose register.
When the technology disclosed in Japanese Patent Laid-Open No. 263290/1996 is intended to apply to other addressing mode, for example, according to transfer instruction between 4 of general purpose registers and a memory, in the case of reading of register indirect, it is necessary to form an effective address in a content of an address register by executing an address operation processing of +4, +8 and +12 for each of the general purpose registers of a second one and thereafter. Conversely, in the case of writing, it is necessary to form the effective address in the content of the address register by executing the operation processing of xe2x88x9212, xe2x88x928 and xe2x88x924 for each of the general purpose registers except a final one thereof. Therefore, there is needed the operation of the effective address for each of the registers and accordingly, an undesirable inner operational state is brought about.
Further, according to register indirect with displacement, it is necessary that after holding a result of adding the displacement and the content of the address register at inside thereof, there is a need of executing address calculation to the added result similar to the register in direct. These complicate the inner operation of CPU and is liable to increase the logical scale.
Generally, according to a microcomputer, it is preferable in view of the development efficiency to be able to use generally (to be able to deal with a plurality of application fields by one kind of chip). Particularly, with regard to CPU, a software development apparatus such as an assembler or a C compiler and a hardware development apparatus such as in-circuit emulator are needed and accordingly, it is not easy to modify the architecture of a microcomputer, further, in the case of modification, it is preferable that compatibility with existing CPU is maintained, the software and the hardware development apparatus can commonly be utilized and the development efficiency is promoted.
Further, there also is a microcomputer having instruction of continuously transferring a plurality of units of data on a memory such as block transfer instruction in an instruction set. According to such instruction, transfer data is not stored to general purpose registers of CPU and accordingly, the data cannot be operated directly or, at least, the data cannot be operated so fast as for the general purpose registers.
It is an object of the invention with regard to the study problem E to realize shortening of a CPU processing program and high speed formation of a data processing speed by CPU when it is necessary to process data larger than a length processed by CPU, for example, byte, word or long word while minimizing an increase in the logical scale in a data processing apparatus or a data processing system such as a microcomputer. In details, the invention enables to achieve high speed formation of the data processing by reducing a frequency of reading instruction with regard to reading/writing data.
It is other object of the invention with regard to the study problem E to provide a data processing apparatus capable of effectively utilizing software resources of existing CPU, capable of promoting the development efficiency of a new system, capable of appropriating a system development apparatus of existing CPU and capable of swiftly providing a development environment.
It is still other object of the invention with regard to the study problem E to provide a data processing apparatus capable of designating an increase in a number of general purpose registers by software with regard to existing CPU and capable of promoting processing function of CPU by facilitating program formation and efficient formation of register reading and register writing operation by utilizing thereof.
It is other object of the invention with regard to the study problem E to provide a data processing apparatus capable of achieving objects of shortening the CPU processing program and high speed formation of processing by CPU while maintaining compatibility at an object level or maintaining compatibility at the object level when there are present CPU having a wide address space and CPU having a small address space.
The invention with regard to the study problem A through the study problem E is provided with common problem to be resolved in view of expansion of operation function and promotion of usability of the data processing apparatus.
The above-described as well as other objects and new characteristic of the invention will become apparent from the description and the attached drawings of the specification.
A brief explanation will be given of an outline of representative aspects of the invention disclosed in the application as follows.
(Means for Resolving Study Problem A)
A first through a ninth aspect of the invention provide means for resolving the study problem A. As means for resolving the study problem A, register designating information for designating a register is divided in two portions. The two portions are arranged in separate basic units on a basic unit of an instruction code. When one instruction code is made ignorable and the ignorable instruction code is ignored, there is carried out register selecting operation by implicitly assuming predetermined register designating information.
The ignorable instruction code may be constituted by an instruction code which is provided with a field for holding a portion of the register designating information and which does not designate kind of operation. For example, the ignorable instruction code may be made common to that of existing CPU and the ignorable instruction code may be allocated to an undefined word of existing CPU.
There is provided means for holding information of the register designating field included in the ignorable instruction code and when the ignorable instruction is executed, the information of the register designating field included in the ignorable instruction code is stored to the holding means. Further, after finishing to execute the instruction, the holding means is set to a predetermined value in correspondence with the implicit designation.
According to the above-described means, when only an implicitly designatable general purpose register (existing general purpose register) is used, the ignorable instruction code can be ignored and accordingly, the length of the instruction code is not increased. When at least, a conventionally equivalent general purpose register is used, a conventionally equivalent instruction code may be used. By preventing the instruction code length from increasing, the processing speed is not reduced.
By adding the ignorable instruction code, all of general purpose registers can directly be selected by instruction and accordingly, a number of usable general purpose registers can be increased without deteriorating easiness of program. Further, by ensuring a portion of an arbitrary amount of general purpose registers for a desired task or for a desired interruption processing (the portion is not used in other task or processing), there is no need of saving the general purpose registers in the task and the interruption processing and high speed formation is achieved. Further, a number of the general purpose registers ensured for the task or the interruption processing can be made arbitrary and accordingly, it is easy to circulate the general purpose registers used to each other among the task and the processing.
By adding the ignorable instruction code, access to a designatable general purpose register can generally be made faster than access to a memory such as RAM and accordingly, by increasing the number of the general purpose registers, an amount of data capable of being processed at high speed is increased and accordingly, the processing speed of CPU can be promoted. Further, according to a processor having an instruction set of a so-to-speak load store type and incapable of directly operating with regard to content of a memory, by increasing the general purpose registers, an amount of data capable of being processed directly can be increased, further, an access frequency of the memory can be reduced and the processing speed can be promoted.
In the case in which there are present CPU having a wide address space and CPU having a small address space while maintaining compatibility therebetween at an object level, when the ignorable instruction code can be added by CPU having the wide address space, the word can be added also to CPU having lower compatibility and the small address space and accordingly, while maintaining the compatibility at the object level, general purpose registers can be added to CPU having the wide address space and CPU having the small address space. Both of an advantage of maintaining the compatibility at the object level and an advantage of adding the general purpose registers can be enjoyed.
A further detailed mode of the above-described means will be described. A data processing apparatus operated by reading an instruction code and having a plurality of registers (ER0 through ER31) capable of storing data or addresses, includes first instruction code holding means (IR1) for holding an instruction code and second instruction code holding means (IR2), instruction decoding means (DEC) for decoding the instruction code and selecting means (RSEL) for selecting the register. An output of the first instruction code holding means is coupled to the second instruction code holding means, the instruction decoding means and the register selecting means, an output of the second instruction code holding means is coupled to the register selecting means, an output of the instruction decoding means is coupled to the register selecting means and the second instruction code holding means and the output of the instruction decoding means to the second instruction code holding means includes a latch signal (LGRCL) with regard to the second instruction code holding means and a set signal (RSLGR) to a predetermined value. The latch signal with regard to the second instruction code holding means is generated when the instruction decoding means decodes a predetermined instruction code and the set signal to the predetermined value with regard to the second instruction code holding means is generated such that a set operation is executed after a processing of using a register designated by the predetermined instruction code has been finished.
The set signal to the predetermined value with regard to the second instruction code holding means may be generated by the instruction decoding means in response to finishing to execute the instruction. Or, there may further be included data holding means for holding the predetermined value, an output of the data holding means may be coupled to the second instruction code holding means and the second instruction code holding means may be set to a value in accordance with a value of the data holding means in response to generating the set signal to the predetermined value.
(Means for Resolving Study Problem B)
A tenth through a thirty-ninth aspect of the invention provide means for resolving the study problem B. As means for resolving the study problem B, among transfer instruction between existing ones of a memory and registers and operation instruction between existing ones of registers, a plurality of instruction codes are combined, for example, by using a front instruction code for coupling these, operation on the memory is enabled. In sum, when a predetermined front instruction code is added, a plurality of instruction codes successive thereto are interpreted and executed as one instruction. In this case, the one instruction can be defined such that, for example, a processing is not divided and is not disconnected by a factor other than reset or interruption (exception processing) is not received in the midway except a specific factor of reset or the like. In this case, by utilizing latching means which is not freed in view of a program such as a temporary register in CPU in place of a general purpose register or along with the general purpose register, direct operation with regard to data on the memory (or direct data transfer) is enabled. In this case, the direct operation with regard to the data on the memory is an operational processing executed by loading data from a memory to data latching means which is not made to explicit in the instruction code and using the data loaded to the data latching means. Further, the direct data transfer with the memory is a processing for loading data from the memory to data latching means which is not made to explicit in the instruction code and storing data of the data latching means to the memory.
In details, when a transfer instruction code between memory and registers is executed firstly successive to the front instruction code, data transfer is executed between not the general purpose register but the first latching means which is not freed in view of the program such as a temporary register in CPU and the memory. Further, when an operation instruction code between registers is successively executed secondly, a single or a plurality of data in an operation object is read on the first latching means. In this case, the latching means which is not freed in view of the program signifies latching means which cannot be designated by the user in view of the program, a temporary register or a buffer register which is not seen from the user on CPU or a microcomputer. Such a latching means is not freed in view of the program and accordingly, it is not naturally assumed that stored information thereof is saved, in many cases, it is assumed to use thereof in storing an intermediate result of operation and the state of using thereof is finished in executing one instruction on the premise. Therefore, under the premise, when the latching means is used, the saving operation may not be considered at all. In order to guarantee the premise, a consideration is given such that a front instruction code and a predetermined instruction successive thereto are regarded as one instruction and interruption is prevented from entering in the midway and a necessity of saving with regard to the latching means is excluded.
When the second operation instruction code is an instruction code requesting a processing of storing an operation result to a memory, an address of the memory used for the transfer instruction code is stored to separate latching means (second latching means) of a separate temporary register. The operation result of the operation instruction is stored to the first latching means. Successively, a transfer instruction code between memory and registers is generated by the microcomputer per se and with content of the second latching means stored with the address as an address, the content of the first latching means stored with the operation result as data, writing is executed to the memory.
A further explanation will be given. When instruction regarded as one instruction by the front instruction code is instruction for executing operation with regard to data on the memory and data on the general purpose register and storing the result on the general purpose register, the front instruction code, a memory/register transfer instruction code and an operation instruction code are executed, in executing the memory/register transfer instruction code, transfer data is stored not to the general purpose register but to the latching means and the operation instruction code executes operation with regard to data stored to the latching means and data on the general purpose register and the result is stored to the general purpose register.
When the instruction regarded as one instruction by the front instruction code is instruction for executing operation with regard to data on the general purpose register and the data on the memory and storing the result on the memory, the front instruction code, the memory/register transfer instruction code, the operation instruction code and the memory/register transfer instruction code formed at inside thereof are executed, in executing the memory/register transfer instruction code, transfer data is stored not to the general purpose register but the latching means, the operation instruction code executes operation with regard to data stored to the latching means and data on the general purpose register and stores the result to the latching means. The memory/register transfer instruction code executes writing to the memory with the content of the latching means stored with the address as an address and with the content of the latching means stored with the operation result as data. Also in the case of executing operation with regard to data on one memory as in increment, the operation is executed similarly thereto. Further, in executing the memory/register transfer instruction code, in other words, in the midst of processing by instruction regarded as one instruction, a change in a flag reflecting the operation result is restrained and a state of the flag of an operation result by previous operation instruction is held. The reason is as follows. In executing the operation instruction code, there is a case in which a reference must be given to the state reflected to the flag by executing the previous operation instruction and in that case, there is brought about inconvenience in the case of allowing all of change in the state of the flag even by executing the transfer instruction or the transfer instruction code. In further details, the inconvenience is prevented from being brought about by a difference between the change in the flag as the relevant instruction and a change in the flag of the transfer instruction per se. Specifically, when the operation is arithmetic operation, an overflow flag produced by a result of the arithmetic operation is prevented from being cleared by the transfer instruction code.
When the instruction regarded as one instruction by the front instruction code is instruction for executing operation by using two of data on the memory and storing the operation result on the memory, the front instruction code, the first and the second memory/register transfer instruction codes, the operation instruction code and the memory/register transfer instruction code formed at inside thereof are executed, in executing the first and the second memory/register transfer instruction codes, transfer data is stored not to the general purpose register but to the latching means and the operation instruction code executes operation with regard to data stored to the latching means and stores the result to the latching means. The memory/register transfer instruction code executes writing to the memory with the content of the latching means stored with the address as an address and with the content of the latching means stored with the operation result as data.
Meanwhile, when the instruction regarded as one instruction by the front instruction code is instruction for transferring data on the memory to a separate memory, the front instruction code, the memory/register transfer instruction code and the memory/register transfer instruction code are executed, in executing the memory/register transfer instruction code, transfer data is stored not to the general purpose register but to the latching means and the memory/register transfer instruction code executes writing to the memory with the content of the latching means stored with the operation result as data.
When the instruction regarded as one instruction by the front instruction code is operation with regard to immediate data and data on the memory, the instruction can be made similar to instruction for generally executing operation with regard to data on the general purpose register and data on the memory and storing the result on the memory.
When the instruction regarded as one instruction by the front instruction code is instruction for transferring immediate data to the memory, the front instruction code, the immediate/register transfer instruction code and the memory/register transfer instruction code are executed, in executing the immediate/register transfer instruction code, immediate data is stored not to the general purpose register but to the latching means and the memory/register transfer instruction code executes writing to the memory with the content of the latching means stored with the operation result as data.
When a plurality of instruction codes are combined and executed as a series thereof, an undesirable processing such as interruption is prohibited from being inserted between the respective instruction codes. A control signal therefor may be generated by decoding the front instruction code. The front instruction code can be provided with other information such as data size.
When the memory/register transfer instruction code is executed successive to the front instruction code, the memory/register transfer instruction code is not necessarily an instruction code quite the same as an instruction code of independent memory/register transfer instruction but as described in the eleventh and the twenty-ninth aspect of the invention, only bits signifying a method of designating a memory as in the addressing mode are made common and other bits may pertinently be changed.
According to the above-described means, the instruction codes of the transfer instruction between a memory and registers and the operation instruction between registers are existing ones and accordingly, single ones of the instruction codes are operated conventionally similarly and execution of existing instruction is not hampered. Further, when only existing instruction is used, existing software resources can effectively be utilized.
The above-described operational function can be expanded without deteriorating the merit provided to existing CPU such as the general purpose register system or the load store architecture.
The above-described front instruction code can commonly be used regardless of the addressing mode or the content of operation and accordingly, added instruction codes can be minimized. Further, by providing other information of data size or the like to the front instruction code, the overall instruction code length can be shortened.
In reading data from the memory to the latching means, the operation and writing to the memory based on the content of the latching means, only registers used differ from those of existing instruction and accordingly, existing instruction operation can be utilized without being modified significantly. Thereby, the increase in the logical scale caused by enabling the operation with regard to the data on the memory can be minimized.
By enabling to operate directly with regard to the data on the memory, an amount of data capable of being processed directly can be increased, further, saving/returning of the general purpose registers can be dispensed with and the processing speed can be promoted.
In the case of instruction for executing operation with regard to the data on the memory and the data on the general purpose registers and storing the result on the general purpose registers, since the front instruction code is included, the processing time is larger than total processing time in the case of individually executing the memory/register transfer instruction code and the operation instruction code, however, the total processing time can be improved since saving or returning of the general purpose registers is not executed. Further, in the case of instruction for executing operation with regard to data on the memory and data on the general purpose registers and storing the result on the memory, the register/memory transfer instruction code is generated at inside thereof, reading of the instruction code is not executed, the memory address calculated in reading can be reutilized by utilizing separate latching means (second latching means) and accordingly, the processing time can be shortened more than the total processing time in the case of individually executing the memory/register transfer instruction code, the operation instruction code and the register/memory transfer instruction code.
When there are present CPU having a wide address space and CPU having a small address space while maintaining compatibility at the object level, by adding the front instruction code and combining existing transfer instruction and operation instruction by CPU having the wide address space, direct operation with regard to data on the memory can be executed even by CPU having lower compatibility and the small address space. In other words, the data on the memory can directly be operated even by CPU having the wide address space and CPU having the small address space by the same method while maintaining compatibility at the object level. Both of the advantage by maintaining the compatibility at the object level and the advantage capable of directly operating the data on the memory can be enjoyed.
New instruction function is realized by combining existing instruction and accordingly, in further expansion and further high speed formation of the instruction set, a new problem is hardly posed with regard to existing CPU. In other words, when a technology of executing further expansion of the instruction set or further high speed formation thereof is present (invented) with regard to existing CPU, similar technology can be applied to CPU enlarging the instruction set with regard to existing CPU by applying the invention. The above-technology may be applied to respectives of existing instruction used for realizing new instruction function and may be recombined. Operation of the front instruction code is simple, further, by executing operation similar to existing instruction, alteration is facilitated.
Further, new instruction function is realized by combining existing instruction and accordingly, an interface for emulation can be made common with that of existing CPU and accordingly, the hardware of the same emulator can commonly be utilized. By making common the hardware of the emulator, the development environment can be prepared at an early stage, further, resources necessary for development of the emulator can be minimized.
(Means for Resolving the Study Problem C)
A fortieth to a sixty-second aspect of the invention provide means for resolving the study problem C. As means for resolving the study problem C, (1) with regard to a register constitution or a combination of instruction and an addressing mode or both of them, assume a plurality of data processing apparatus, for example, a plurality of lower CPU""s including different instruction sets in which one of them does not incorporate other thereof. In this case, there is constituted and provided higher CPU having an instruction set incorporating any of lower CPU""s with regard to the plurality of lower CPU""s in which one of them does not incorporate an instruction set of other thereof.
In the development, there is developed higher CPU in which constitutions of general purpose registers are expanded and a combination of instruction and an addressing mode is expanded with regard to existing CPU (one of the above-described lower CPU""s). The lower CPU is provided with a constitution of a subset or an instruction set of the higher CPU. A description will be given later of expansion of the general purpose register and expansion of the combination of instruction and an addressing mode.
Further, other of the lower CPU is realized by a mode of a separate subset of the higher CPU.
By providing a plurality of lower CPU""s including different instruction sets and pertinent higher CPU as described above, request on a software of an application field can be met, various preferences of the user can be met, further, also in view of a program by assembly language of separate CPU, CPU having a comparatively proximate instruction set can be made selectable and shift to higher CPU can be facilitated.
By preparing higher CPU having an instruction set incorporating any of CPU""s with regard to a plurality of lower CPU""s in which one of them does not incorporate an instruction set of other thereof, while enabling effective utilization of software resources, there can be prepared CPU promoting performance/function. By the effective utilization of software resources, the development efficiency of software development of the user can be promoted.
In the development, by developing higher CPU expanding general purpose registers as well as a combination of instruction and an addressing mode with regard to existing lower CPU""s and developing separate lower CPU having the subset, while minimizing the increase in the logical scale of higher CPU, the performance, the function and the usability can be promoted, development of the separate lower CPU is facilitated and the development efficiency can be promoted. In the case of developing CPU still higher than the higher CPU, when the compatibility with the higher CPU is maintained, the compatibility with the plurality of CPU""s can be automatically maintained by maintaining compatibility with the higher CPU and accordingly, while realizing effective utilization of software resources, CPU achieving promotion of future function or performance becomes easy to realize.
A program developed for lower CPU can be utilized by higher CPU according to the invention at least at a level of source program (description level in assembly language). Further, in this case, lower CPU designates CPU in which a register constitution thereof as well as an instruction set thereof are incorporated in a register constitution as well as an instruction set of CPU such as higher CPU according to the invention.
Further, in order to realize upper compatibility at an object program level, there may be prepared operational modes for switching a bit number of an effective address and unit sizes of vectors and stacks in accordance with a mode of utilizing the register, for example, a maximum mode and a minimum mode. In the minimum mode, CPU operates quite similar to at least one of lower CPU""s. In the maximum mode, CPU is operated as higher CPU by a maximum function provided thereto.
(2) In order to expand a general purpose register, as described in the means with regard to the study problem A, register designating information for designating registers is divided into two portions. The two portions are arranged to separate basic units on the basic unit of the instruction codes. When one of the instruction codes is made ignorable and when the ignorable instruction code is ignored, the register selection operation is executed by implicitly assuming predetermined register designating information.
(3) In order to expand a combination of instruction and an addressing mode, as described in the means with regard to the study problem B, among existing ones of transfer instruction between a memory and registers and operation instruction between registers, a plurality of the instruction codes are combined, for example, a front instruction code for coupling these is used to thereby enable operation directly using data of a memory. In sum, when the predetermined front instruction code is added, a plurality of instruction codes successive thereto are interpreted and executed as one instruction.
(4) In order to realize CPU having a wide address space and a reduced logical scale, there is provided a program counter having a bit length in correspondence with a total of the address space, the total or at least a large portion of address space is made linearly usable for a program, an addressing mode of data transfer is reduced to a degree capable of dealing with data of a comparatively small scale or a data size of transfer data is limited and in accessing data, usable address space is reduced and such an address space is divided in two.
According to the above-described, by providing a program counter having a bit length in correspondence with a total of the address space, for a program, the total or at least a large portion of the address space is linearly made usable, an addressing mode of data transfer is reduced to a degree dealing with data having a comparatively small scale or the data size of transfer data is limited and the logical scale can be reduced without deteriorating usability in a desired application field.
In accessing data, by reducing usable address space and dividing such an address space in two, compatibility in view of address space with higher CPU can be maintained without deteriorating usability and by previously preparing an operational mode of switching a method of calculating an effective address for upper CPU, compatibility in view of software can be maintained.
By widening an address space for a program, an aptitude with regard to programming using high-level language such as C language can be promoted. Further, by making a stack pointer switchable, undesirable increase in a capacity of a stack in controlling a task such as OS can be prevented. Even in a single chip microcomputer or a microcomputer system operated by using only a built-in memory, high-level language or OS is easily made usable and the development efficiency of software of the user can be promoted.
(5) Further, with regard to a development apparatus, there is prepared a software development apparatus with regard to an instruction set of the higher CPU, further, the software development apparatus is commonly made usable with regard to a plurality of CPU""s in which one of them does not incorporate an instruction set of other thereof to thereby enable the user to select CPU.
On the software development apparatus, a plurality of kinds of description of general purpose register having a general function such as assembly language are allowed.
With regard to an emulator, an interface for emulation of a processor for emulation to be mounted is made common. In order to analyze CPU, there is provided means for selecting object CPU on the emulator. Particularly, object CPU of a deassembler is made selectable.
By preparing a software development apparatus with regard to an instruction set of the higher CPU, further, making the software development apparatus commonly usable to a plurality of CPU""s in which one of them does not incorporate an instruction set of other thereof and enabling the user to select CPU, the development efficiency of the software developing apparatus can be promoted. For the user, even when a plurality of CPU""s as described above are used, since the software development apparatus is common, undesirable expense is not brought about. Shift from one CPU to other CPU in the plurality of CPU""s as described above is facilitated and the development efficiency can be promoted.
Further, interface for emulation can be made common for upper CPU and lower CPU, further, by developing a logical circuit for emulation of upper CPU, the logical circuit can also be utilized by lower CPU and development efficiency thereof including a processor for emulation can be promoted. Further, hardware of the same emulator can be made common, thereby a development environment can be prepared swiftly, further, resources necessary for development of the emulator can be minimized. With regard to the deassembler mounted to the emulator, by developing the deassembler for higher CPU and providing means for selecting object CPU on the emulator, substantially one deassembler is used and accordingly, the development efficiency can further be promoted.
(6) The above-described means with regard to the study problem C can be rearranged from view points of compatibility, a processor for emulation, an emulator, a software development apparatus, a data processing apparatus as in higher CPU and a data processing apparatus as in lower CPU.
(6-1) A data processing apparatus from a view point of compatibility executes instruction in accordance with a predetermined procedure, can execute an instruction code the same as an instruction code of a first separate microcomputer by incorporating an instruction executing function of a first separate data processing apparatus and can execute an instruction code the same as an instruction code of a second separate data processing apparatus by incorporating an instruction executing function of the second separate data processing apparatus. There is included instruction executing means by which with regard to both or either one of operand designation and operation designation which are not incorporated in the instruction executing function of the first separate data processing apparatus and which are incorporated in the instruction executing function of the second separate data processing apparatus, instruction combined with a plurality of the designations is executed, and with regard to both or either one of operand designation and operation designation which are not incorporated in the instruction executing function of the second separate data processing apparatus and which are incorporated in the instruction executing function of the first separate data processing apparatus, instruction combined with a plurality of the designations is executed.
The operand designation is a designation with regard to, for example, operation of an effective address, a general purpose register or an address space.
When the data processing apparatus is switchably provided with a first operational mode and a second operational mode having different bit numbers of effective addresses and different bit sizes of vectors and stacks, the bit number of the effective address and the unit sizes of the vector and the stack in the first operational mode are equivalent to those of the first separate data processing apparatus. The bit number of the effective address and the unit sizes of the vector and the stack in the second operational mode are equivalent to those of the second separate data processing apparatus.
A data processing apparatus from still other view point paying attention to the compatibility is a data processing apparatus for executing instruction in accordance with a predetermined procedure, can utilize a total of an area or the area divided in two in holding data information, further, is provided with a plurality of general purpose registers capable of being utilized also in holding address information by a bit number larger than a bit number on the lower side divided in two. The instruction executing means incorporates the instruction executing function of the first separate data processing apparatus such that a code of instruction having a bit number the same as that of a code of instruction of the first separate data processing apparatus having a predetermined plurality of the general purpose registers in correspondence with the bit number on the lower side divided in two can be executed and thereafter executes instruction utilizing the total of the general purpose registers dividable in two, further, incorporates the instruction executing function of the second separate data processing apparatus such that an instruction code having a bit number the same as that of a code of instruction of the second separate data processing apparatus having a number smaller than the predetermined plurality of the general purpose registers dividable in two can be executed.
According to a view point of a method of developing a data processing apparatus paying attention to the compatibility, a code of undefined instruction in the first data processing apparatus is made a front instruction code, the front instruction code changes the definition of the instruction code of the first data processing apparatus successive thereto and with regard to both or either one of operand designation and operation designation which are not defined in the first data processing apparatus, the front instruction code defines instruction combined with a plurality of the designations, to thereby realize instruction of the second data processing apparatus having instruction incorporating instruction of the first data processing apparatus. Instruction of the third data processing apparatus is realized by a portion of instruction of the second data processing apparatus.
The front instruction code makes exchangeable designation of a general purpose register designated by, for example, an instruction code successive thereto. Further, a separate front instruction code defines operation of data on the memory by a transfer instruction code successive thereto and two or more of instruction codes in a code of separate transfer instruction and a code of separate operation instruction.
(6-2)
According to a view point of a processor for emulation, there is constituted a processor for emulation including the data processing apparatus explained in view of the compatibility and emulation interface such that execution of instruction of the first and the second separate data processing apparatus can be replaced by execution of instruction of the data processing apparatus.
(6-3)
According to a view point of an emulator, there is constituted an emulator mounted with the processor for emulation such that the processor for emulation for executing a user program includes an emulation program area capable of storing a control program for controlling an inner state thereof and a control processor for storing the control program in the emulation program area.
The processor for emulation can substitute for execution of instruction of the first and the second separate data processing apparatus in accordance with an inner set state following the control program.
(6-4)
According to a view point of a software development apparatus (cross software), there is constituted a software development apparatus provided with means for selecting a data processing apparatus constituting an object of a program to be formed such that a program of the data processing apparatus, the first separate data processing apparatus or the second separate data processing apparatus explained on the view point of the compatibility can be formed.
(6-5)
According to a view point of higher CPU, a data processing apparatus is provided with a plurality of registers capable of storing data or addresses and is operated by reading an instruction code and decoding the instruction code by controlling means. The instruction code is constituted by a basic unit and register designating information for designating the registers can be held by being divided into a plurality of instruction code basic units. A transfer instruction code for executing data transfer between a memory and the registers and an operation instruction code executing operation with regard to data on the registers are included in an instruction set. The controlling means selects the registers based on a result of decoding the register designating information held by the instruction code and when the front instruction code having a divided one of the register designating information is ignored, the controlling means selects the registers by implicitly assuming predetermined register designating information in place of the ignored register designating information, further, successively reads the front instruction code, the transfer instruction code and the operation instruction code and interprets them as one instruction and executes direct operation with regard to the data on the memory.
The direct operation with regard to the data on the memory is an operation processing executed by, for example, loading data from the memory to a data latching means which is not made to explicit in the instruction code and using the loaded data for the data latching means.
Further, a data processing apparatus from other view point of upper CPU, is provided with a plurality of registers capable of storing data or addresses and is operated by reading an instruction code and decoding the instruction code by controlling means. The instruction code is constituted by a basic unit and register designating information for designating the registers can be held by being divided into a plurality of instruction code base units. A transfer instruction code for executing data transfer between a memory and the registers is included in an instruction set. The controlling means selects the registers based on a result of decoding the register designating information held by the instruction code and when the front instruction code having a divided one of the register designating information is ignored, the controlling means selects registers by implicitly assuming predetermined register designating information in place of the ignored register designating information, further, successively reads the front instruction code, the transfer instruction code and other transfer instruction code, interprets them as one instruction and executes direct data transfer with the memory.
The direct data transfer with the memory is a processing of loading data from the memory to the data latching means which is not made to explicit in the instruction code and storing the data of the data latching means to the memory.
(6-6)
A data processing apparatus according to a view point of lower CPU is provided with program counting means having a bit number in correspondence with a bit number of an address space, a plurality of general purpose registers capable of utilizing a total of an area or the area divided in two in holding data information and capable of being utilized also for holding address information by a bit number larger than a bit number of one of the area divided in two and instruction executing means. The instruction executing means can execute instruction of utilizing a total of the general purpose registers for holding data information and data transfer instruction between the general purpose registers and other storing apparatus, can make a bit number of transfer data of the data transfer instruction equal to or smaller than a bit number of the one of the area divided in two of the general purpose register, further, makes a portion of an addressing mode for designating data on the address space effective at a portion on the address space divided in a plural number.
One of the portions divided in a plural number on the address space, is made to include a vector for designation a starting address of executing instruction and other portion thereof can map an address of readable and writable separate storing apparatus.
(Means for Resolving the Study Problem D)
A sixty-third through a seventy-second aspect of the invention provide means for resolving the study problem D. As means for resolving the study problem D, according to instruction for executing branch in accordance with a state of bits of data on a memory, a field prescribing operation (operation field) is divided in a plural number and is realized by a separate word in view of a basic unit of an instruction code and such a word is made common with an instruction code of separate instruction capable of being used independently or a portion of the instruction code of the separate instruction. A first word of such an instruction code executes data transfer between latching means which is not freed in view of a program such as a temporary register and the memory. A second word executes branch by determining a desired state of bits of the latching means. The latching means such as a temporary register is provided with means for determining a designated state of bits and is made to be able to determine a predetermined state of bits without being read to an ALU. The first word of the instruction code is made to prohibit a change in a condition code and prohibit an interrupted exception processing at a finishing time point thereof.
According to a first example, a transfer instruction code (first word) for executing data transfer between lathing means which is not freed in view of a program such as a temporary register and a memory and a condition branch instruction code (second word), are combined, in executing the condition branch instruction successive to the transfer instruction code, the condition is constituted by a bit number and the state of bits in place of the condition code to thereby enable branch in accordance with the state of bits of the data on the memory. Further, the transfer instruction code may be common to a portion of bit test instruction.
According to other view point of the first example, a transfer instruction code for executing data transfer between latching means which is common to an instruction code such as bit test instruction and is not freed in view of a program such as a temporary register and the memory and an instruction code of the condition branch instruction are combined to thereby realize branch instruction for executing branch by determining a predetermined state of bits of data on an address space.
According to a second example, there is provided a front instruction code for combining an existing instruction code for executing transfer between a memory and registers and condition branch instruction and coupling these to thereby enable to execute branch in accordance with a state of bits of data on the memory. That is, when memory/register instruction is executed successive to the front instruction code, data transfer is executed between not the general purpose register but latching means which is not freed in view of a program such as a temporary register in CPU and the memory.
The second example can be realized by being made common to a method of realizing instruction which is disclosed in previous application by the inventors which has not been publicly known yet and in which a source is made the data on the memory and by replacing an operation instruction code by a branch instruction code.
In details, in the case of instruction for executing operation with regard to data on the memory and data on a general purpose register and storing the result on the general purpose register, a front instruction code, a memory/register transfer instruction code and an operation instruction code are executed, in executing the memory/register transfer instruction code, transfer data is stored not to the general purpose register but to latching means and the operation instruction code executes operation with regard to data stored to the latching means and the data on the general purpose register and stores the result to the general purpose register.
In the case of instruction executing operation with regard to the data on the general purpose register and data on the memory and storing the result on the memory, the front instruction code, the memory/register transfer instruction code, the operation instruction code and a memory/register transfer instruction code formed at inside thereof are executed, in executing the memory/register transfer instruction code, the transfer data is stored not to the general purpose register but to the latching means. The operation instruction code executes operation with regard to data stored to latching means and the data on the general purpose register and stores the operation result to the latching means. The memory/register transfer instruction code executes writing to the memory with the content of the latching means stored with the address as an address and with the content of the latching means stored with the operation result as data. Also in the case of executing operation with regard to data on one memory as in increment, operation similar thereto is executed. Further, in executing the memory/register transfer instruction code, a change in a flag is restrained and a change in the flag of the operation result is held.
In the case of instruction for executing operation with regard to data on two memories and storing the result on the memories, the front instruction code, a first and a second memories/register transfer operation code, the operation instruction code and a memory/register transfer instruction code formed at inside thereof are executed, in executing the first and second memory/register transfer instruction codes, transfer data is stored not to the general purpose register but to the latching means. The operation instruction code executes operation with regard the data stored to latching means and stores the result to the latching means. The memory/register transfer instruction code executes writing to the memory with the content of the latching means stored with the address as an address and the content of the latching means stored with the operation result as data.
Meanwhile, in the case of instruction for transferring the data on the memory to a separate memory, the front instruction code, the memory/register transfer instruction code and the memory/register transfer instruction code are executed, in executing the memory/register transfer instruction code, the transfer data is stored not to the general purpose register but to the latching means and the memory/register transfer instruction code executes writing to the memory with the content of the latching means stored with the operation result as data.
In the case of executing operation with regard to immediate data and the data on the memory, the instruction can be made similar to the instruction of executing generally operation with regard to the data on the general purpose register and the data on the memory and storing the result on the memory.
In the case of instruction for transferring immediate data to the memory, the front instruction code, an immediate/register transfer instruction code and the memory/register transfer instruction code are executed, in executing the immediate/register transfer instruction code, immediate data is stored not to the general purpose register but to the latching means and the memory/register transfer instruction code executes writing to the memory with the content of the latching means stored with the operation result as data.
According to the above-described means, instruction codes of the first word and the second word (condition branch instruction) are existing ones and accordingly, in the case of a single one thereof, operation is executed conventionally similarly and execution of existing instruction is not hampered. Further, when only the existing instruction is used, existing software resources can effectively be utilized. The merit of existing CPU such as general purpose register or the load store architecture is not deteriorated. When there are a plurality of kinds of bit lengths of absolute addresses or bit lengths of displacements respectively in the first word and the second word (condition branch instruction), these can be combined by the same method. By enabling these combinations, restriction in view of a program is dispensed with and the usefulness can be promoted. Further, by the same method, a combination with subroutine branch instruction is made possible and the usefulness can be promoted.
By providing means for determining a designated state of bits to the latching means such as a temporary register and enabling to determine a predetermined state of bits without reading to ALU, the means can be realized without modifying overall operation of the condition branch instruction and accordingly, a portion to be modified is reduced and an increase in the logical scale can be minimized.
The front instruction code can commonly be used regardless of an addressing mode or content of operation and accordingly, added instruction codes can be minimized. Further, by providing other information of data size or the like to the front instruction code, the overall instruction code length can be shortened.
Reading of data from the memory to the latching means, the operation and writing to the memory based on the content of the latching means differ from those of existing instruction only in registers to be used and accordingly, existing instruction operation can be utilized without being changed significantly. Thereby, the increase in the logical scale by enabling operation with regard to the data on the memory can be minimized.
When there are present CPU having a wide address space and CPU having a small address space while maintaining compatibility at the object level, by realizing the instruction in CPU having the wide address space, operation with regard to data on the memory can be executed even by CPU having lower compatibility and the small address space. In other words, the operation with regard to data on the memory can be executed even by CPU having the wide address space and CPU having the small address space by the same method while maintaining the compatibility at the object level. Both of the advantage by maintaining the compatibility at the object level and the advantage of enabling operation with regard to the data on the memory can be enjoyed.
Existing instructions are combined and new instruction function is realized and accordingly, in further expanding an instruction set or further high speed formation, a new problem is hardly posed with regard to existing CPU. In other words, when a technology of expanding further the instruction set or executing further high speed formation is present or newly developed with regard to existing CPU, by applying the invention, similar technology can be applied to CPU enlarging the instruction set compared with existing CPU. Respectives of existing instruction used for realizing new instruction function may be applied with the technology and may be combined again. Operation of the front instruction code is simple and can be modified easily by constitution operation by operation similar to existing instruction.
Further, existing instruction is combined, and new instruction function is realized and accordingly, existing CPU and interface for emulation can be made common and accordingly, hardware of the same emulation can be made common. By making common the hardware of the emulator, the development environment can be prepared swiftly and resources necessary for developing the emulator can be minimized.
(Means for Resolving Study Problem E)
A seventy-third aspect through an eighty-eighth aspect of the invention provides means for resolving the study problem E. As means with regard to the study problem E, (1) a data processing apparatus includes in an instruction set, transfer instruction for fixing a combination of a plurality of general purpose registers which can be designated to controlling means for controlling executing means for executing instruction for executing data transfer between the plurality of general purpose registers having the fixed combination and an address on an address space. Thereby, even data larger than a bit length of a general purpose register can be dealt with easily, the usefulness is promoted and in reading/writing data, a frequency of reading instruction is reduced and high speed formation of data processing can be achieved.
A calculation of an effective address of the transfer instruction by an address functional unit is executed only once and an address buffer is provided with an incrementing or decrementing function and a function of holding an increment result by which instruction operation is simplified, common formation thereof with control of existing transfer instruction can be achieved, the increase in the logical scale of an instruction decoder can be minimized. Further, the means can be utilized commonly to various addressing modes.
(2) In the case in which the general purpose register is dividable and there is a difference in view of function between divided portions thereof, transfer instruction using a total of the general purpose register and transfer instruction using a divided portion thereof may be provided. Thereby, in data processing, transfer with the general purpose register which is easy to use can be realized and accordingly, the processing is facilitated and high speed formation can be provided.
(3) In the case in which a number of states for executing operation instruction with regard to the general purpose registers differ according to respective general purpose registers, there may be provided transfer instruction between a plurality of general purpose registers having a predetermined combination and other plurality of general purpose registers. At this occasion, when the general purpose registers are increased, a register designating field for designating the general purpose registers is divided into two portions, the two portions are arranged to separate words in view of a basic unit of an instruction code, one word is made ignorable and when the ignorable word is ignored, predetermined register designating information may be designated implicitly. The ignorable word is made to be provided with only a portion of the register designating field and kind of operation is not designated thereto. When there is provided means for holding the register designating field included in the ignorable word and the ignorable word is executed, the register designating field included in the ignorable word is stored to the holding means. Further, in finishing to execute instruction, the holding means is set to a predetermined value in correspondence with the implicit designation. A word which cannot be ignored may be made common to existing CPU and the ignorable word may be allocated to undefined word of existing CPU.
When only a general purpose register which can be designated implicitly (for example, general purpose register of existing lower CPU) is used, the ignorable word can be ignored and accordingly, instruction codes are not increased. By preventing the instruction codes from increasing, the processing speed is not reduced.
By adding the ignorable word, all of general purpose registers can directly be selected by instruction and accordingly, a portion of deteriorating easiness of a program is inconsiderable. Further, by ensuring a portion of an arbitrary amount of general purpose registers in respective desired task or desired interruption processing (the portion is not used in other task or processing), there is no need of saving the general purpose registers in the task or the interruption processing and high speed formation is achieved. Further, a number of general purpose registers ensuring the task or the interruption processing can be made arbitrary and accordingly, it is easy to circulate general purpose registers used to each other among the task and the processing.
By adding the word, access to designatable general purpose registers can generally be made faster than access to memory such as RAM and accordingly, a number of general purpose registers is increased and transfer between a plurality of general purpose registers and a memory can be executed at high speed by which the processing speed of CPU can be promoted. Further, according to a processor having an instruction set of a so-to-speak load store type and incapable of executing operation directly with regard to the content of the memory, an amount of data capable of executing direct processing can be increased, further, access to the memory can be made fast and the processing speed can be promoted.
(4) In the case in which there are present CPU having a wide address space and CPU having a small address space while maintaining compatibility at the object level, in CPU having the wide address space, there are provided the transfer instruction with regard to a general purpose register in correspondence with address space and the transfer instruction with regard to a general purpose register having a size in correspondence with the address space of CPU having the small address space (for example, 16 bits ).
In the case in which there are present CPU having the wide address space and CPU having the small address space while maintaining the compatibility at the object level, by providing the transfer instruction with regard to the general purpose register having the size in correspondence with the address space (for example, 32 bits) in CPU having the wide address space and the transfer instruction with regard to the general purpose register having the size in correspondence with the address space (for example, 16 bits) in CPU having the small address space, the transfer instruction having the latter size can easily be realized even by CPU having lower compatibility and the small address space. In other words, there can be realized the transfer instruction of a plurality of general purpose registers even in CPU having the wide address space and CPU having the small address space while maintaining the compatibility at the object level by the same method. Both of the advantage by maintaining the compatibility at object level and the advantage by adding the transfer instruction can be enjoyed.