Clocked full-rail differential logic circuits are provided with shut-off devices. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the large pre-charge high or xe2x80x9cdipxe2x80x9d experienced by prior art full-rail differential logic circuits and is therefore more power efficient. In addition, the present invention provides a full-rail differential logic circuit with shut-off that is more resistant to noise than prior art full-rail differential logic circuits.

The present invention relates generally to logic circuits and, more particularly, to clocked full-rail differential logic circuits.
One example of a prior art full-rail differential logic circuit is presented and discussed at page 112, and shown in FIG. 3(c), in xe2x80x9cHIGH SPEED CMOS DESIGN STYLESxe2x80x9d by Bernstein et al. of IBM Microelectronics; Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Mass., 02061; ISBN 0-7923-8220-X, hereinafter referred to as the Bernstein et al. reference, which is incorporated herein by reference, in its entirety, for all purposes.
FIG. 1 shows a prior art full-rail differential logic circuit 100 similar to that discussed in the Bernstein et al. reference. As seen in FIG. 1, prior art full-rail differential logic circuit 100 included six transistors: PFET 105, PFET 107, NFET 109, PFET 115, PFET 117 and NFET 121. Prior art full-rail differential logic circuit 100 also included: differential logic 123 with inputs 151 and 153; out terminal 111; and outBar terminal 113. Prior art full-rail differential logic circuit 100 is activated from a delayed clock signal CLKA. As shown in FIG. 1, signal CLKA was supplied to: gate 116 of PFET 115; gate 118 of PFET 117; gate 129 of NFET 109; and gate 122 of NFET 121.
Prior art full-rail differential logic circuit 100 worked reasonably well, however, during the evaluation phase, prior art full-rail differential logic circuit 100 drew excess power unnecessarily as the relevant inputs, 151 or 153, to logic network 123 were transitioning low to shut off the path of one of the complementary output terminals, out terminal 111 or outBar terminal 113, to ground. The high output terminal, out terminal 111 or outBar terminal 113, therefore experienced a xe2x80x9cdipxe2x80x9d during the transition when the inputs 151 or 153 switched from high to low and a short circuit current, or crossbar current, path was established from Vdd 102 to ground. This xe2x80x9cdipxe2x80x9d was undesirable and resulted in significant power being wasted.
In addition, the structure of prior art full-rail differential logic circuit 100 was particularly susceptible to noise. This problem was extremely undesirable, and damaging, since, typically, multiple prior art full-rail differential logic circuits 100 were cascaded in long chains (not shown) of prior art full-rail differential logic circuits 100. In these chain configurations, the susceptibility of prior art full-rail differential logic circuit 100 to noise meant that each successive stage of the chain contributed additional noise and was even more adversely affected by the noise than the previous stage. Consequently, a few stages into a chain of prior art full-rail differential logic circuits 100, noise became the dominant factor in the chain.
What is needed is a full-rail differential logic circuit that does not experience the large xe2x80x9cdipxe2x80x9d experienced by prior art full-rail differential logic circuit 100 and is therefore more power efficient. In addition, it is desirable to have a full-rail differential logic circuit that is more resistant to noise than prior art full-rail differential logic circuit 100.
According to the present invention, clocked full-rail differential logic circuits include shut-off devices to minimize the xe2x80x9cdipxe2x80x9d at the high output node that was associated with prior art clocked full-rail differential logic circuits. The shut-off device of the invention isolates the high output terminal immediately from the input terminals when the complementary output terminal is pulled to ground. Consequently, according to the present invention, the window period, or path, for the short circuit current, or crossbar current, is significantly decreased and power is saved.
In addition, since clocked full-rail differential logic circuits with shut-off include a shut-off device, the high output terminal is isolated from the input terminals and the noise immunity of the clocked full-rail differential logic circuits with shut-off of the invention is significantly better than prior art clocked full-rail differential logic circuits because noise on the input terminal does not affect the high output terminal after evaluation. Consequently, the clocked full-rail differential logic circuits with shut-off of the invention are better suited for application in cascaded chains.
As discussed above, the clocked full-rail differential logic circuits with shut-off of the invention can be cascaded together to form the chains commonly used in the industry. When the clocked full-rail differential logic circuits with shut-off of the invention are cascaded together, the advantages of the clocked full-rail differential logic circuits with shut-off of the invention are particularly evident and the gains in terms of noise immunity, power efficiency, size reduction and flexibility are further pronounced.
In particular, one embodiment of the invention is a cascaded chain of clocked full-rail differential logic circuits with shut-off. The chain includes a first clocked full-rail differential logic circuit with shut-off. The first clocked full-rail differential logic circuit with shut-off includes: a first clocked full-rail differential logic circuit with shut-off clock input terminal; at least one first clocked full-rail differential logic circuit with shut-off data input terminal; and at least one first clocked full-rail differential logic circuit with shut-off data output terminal.
The cascaded chain also includes a second clocked full-rail differential logic circuit with shut-off. The second clocked full-rail differential logic circuit with shut-off includes: a second clocked full-rail differential logic circuit with shut-off clock input terminal; at least one second clocked full-rail differential logic circuit with shut-off data input terminal; and at least one second clocked full-rail differential logic circuit with shut-off data output terminal.
According to the invention, the at least one first clocked full-rail differential logic circuit with shut-off data output terminal is coupled to the at least one second clocked full-rail differential logic circuit with shut-off data input terminal to form the chain. According to the invention, a first clock signal is coupled to the first clocked full-rail differential logic circuit with shut-off clock input terminal and a second clock signal is coupled to the second clocked full-rail differential logic circuit with shut-off clock input terminal. According to the invention, the second clock signal is delayed with respect to the first clock signal by a predetermined delay time.
In one embodiment of the invention, a delay circuit is coupled between the first clocked full-rail differential logic circuit with shut-off clock input terminal and the second clocked full-rail differential logic circuit with shut-off clock input terminal to provide the predetermined delay time.
One embodiment of the invention is a clocked full-rail differential logic circuit with shut-off that includes a clocked full-rail differential logic circuit with shut-off out terminal and a clocked full-rail differential logic circuit with shut-off outBar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a first node, the first node is coupled to a first supply voltage.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a first transistor, the first transistor including a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode. The first node is coupled to the first transistor first flow electrode and the first transistor second flow electrode is coupled to the clocked full-rail differential logic circuit with shut-off out terminal. The first transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a second transistor, the second transistor including a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode. The first node is coupled to the second transistor first flow electrode and the second transistor second flow electrode is coupled to the clocked full-rail differential logic circuit with shut-off outBar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a third transistor, the third transistor including a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode. The first transistor control electrode is coupled to the third transistor first flow electrode and the clocked full-rail differential logic circuit with shut-off outBar terminal. The second transistor control electrode is coupled to the third transistor second flow electrode and the clocked full-rail differential logic circuit with shut-off out terminal. The third transistor control electrode is coupled to a clock signal CLKA.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a fourth transistor, the fourth transistor including a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode. The first node is coupled to the fourth transistor first flow electrode and the fourth transistor second flow electrode is coupled to the clocked full-rail differential logic circuit with shut-off out terminal. The fourth transistor control electrode is coupled to the clock signal CLKA. The fourth transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a fifth transistor, the fifth transistor including a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode. The first node is coupled to the fifth transistor first flow electrode and the fifth transistor second flow electrode is coupled to the clocked full-rail differential logic circuit with shut-off outBar terminal. The fifth transistor control electrode is coupled to the clock signal CLKA. The fifth transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a shut-off device coupled between the clocked full-rail differential logic circuit with shut-off out terminal and the clocked full-rail differential logic circuit with shut-off outBar terminal and the logic network out terminal and logic network outBar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off shut-off device includes a sixth transistor, the sixth transistor including a sixth transistor first flow electrode, a sixth transistor second flow electrode and a sixth transistor control electrode. The fourth transistor second flow electrode is coupled to the sixth transistor first flow electrode. The sixth transistor second flow electrode is coupled to the logic network out terminal. The sixth transistor control electrode is coupled to the third transistor first flow electrode and the clocked full-rail differential logic circuit with shut-off outbar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off shut-off device also includes a seventh transistor, the seventh transistor including a seventh transistor first flow electrode, a seventh transistor second flow electrode and a seventh transistor control electrode. The fifth transistor second flow electrode is coupled to the seventh transistor first flow electrode. The seventh transistor second flow electrode is coupled to the logic network outBar terminal. The seventh transistor control electrode is coupled to the third transistor second flow electrode and the clocked full-rail differential logic circuit with shut-off out terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a logic network, the logic network including at least one logic network input terminal, a logic network out terminal and a logic network outBar terminal. The logic network out terminal is coupled to the clocked full-rail differential logic circuit with shut-off out terminal and the logic network outbar terminal is coupled to the clocked full-rail differential logic circuit with shut-off outBar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a eighth transistor, the eighth transistor including a eighth transistor first flow electrode, a eighth transistor second flow electrode and a eighth transistor control electrode. The eighth transistor first flow electrode is coupled to the logic network. The eighth transistor control electrode is coupled to the clock signal CLKA. The eighth transistor second flow electrode is coupled to the second supply voltage.
The present invention provides a full-rail differential logic circuit with shut-off that does not experience the large xe2x80x9cdipxe2x80x9d experienced by prior art full-rail differential logic circuits and is therefore more power efficient. In addition, the present invention provides a full-rail differential logic circuit with shut-off that is more resistant to noise than prior art full-rail differential logic circuits.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.

Method for increasing the power efficiency and noise immunity of clocked full-rail differential logic


A vehicle control system includes a controller for generating a target path for the vehicle to change a lane from a main lane to a diverging lane in a diverging zone from a diverging start point to a diverging end point, and causing the vehicle to travel so as to follow the target path. Here, the diverging lane include a plurality of lanes divided into a first diverging lane farthest from the main lane and a second target diverging lane closer to the main lane than the first diverging lane. The controller is configured to generate the target path based on a diverging partition line that partitions the main lane and the diverging lane in the diverging zone when traveling from the main lane through the second diverging lane of the diverging lane toward a destination.

Japanese Patent Application Laid-Open No. 2015-191445 discloses a technique relating to a driving assistance apparatus capable of providing steering support based on lane marking even on diverging roads. In this technique, lane markings existing on the right and left in the traveling direction of the vehicle are detected, and the curvatures of these right and left lane markings are calculated. Then, out of the calculated curvatures of the left and right lane markings, the lane marking having a curvature with a small difference from the curvature of the course specified as the traveling direction is selected as the lane marking of the lane traveled by the vehicle. Thereby, steering assistance can be performed based on the lane marking in the traveling direction of the vehicle appropriately selected in the diverging roads.


Methods and apparatuses are disclosed for computer-based evaluation of a test-taker's performance with respect to a reward threshold. A performance assessment of the test taker can be standardized or customized, as well as relative or absolute. The system allows a parentally-controlled reward system such that children who reach specified objectives can claim an award that parents are confident was fairly and honestly earned without the parent being required to proctor the testing.

The present invention relates generally to methods and apparatuses for computer-based education.
Educational software that tests a user's knowledge, coupled with the immediate scoring of answers, is well known in the art. For home use, a wide range of software is directed to various age groups including school-grade children. Thus, many educational programs are designed to be quite entertaining, with built-in tests being played as games having an underlying educational purpose. Thus, terms such as "student", "player", or "test-taker," shall be understood to mean any participant in, or user of, educational software that tests the user's knowledge in a formal or informal manner.
Software which blends both fun and learning is often referred to as "edutainment" software. Some edutainment programs include "Mathblaster", "Where in the World is Carmen Sandiego," and "Word Munchers." These edutainment programs (as well as certain other educational programs generally) present players with a series of increasingly difficult tests or puzzles, wherein players must correctly solve the present round before they are allowed to continue to the next round of play.
In the above-mentioned edutainment software, each player exists in isolation from all other players. This arrangement is reasonably well suited to informal, isolated learning, but lacks the comprehensive data collection/comparison features needed for formal test administration.
Another drawback of the existing home education software is that standardized entertainment elements often become repetitive and boring after seeing them for the third or fourth time. Users often stop using the software once the novelty has worn off.

This patent is subject to a terminal disclaimer.

Method and apparatus for educational testing


A rescue helmet apparatus which protects the user from hazardous environments includes canisters that provide breathable air to the user. The apparatus features a helmet, reflective cape, and long-lasting lithium-powered lights in an integrated device.

The search for safety equipment that utilizes newer methods, features and a more proficient arrangement of the various elements thereof, is continual. The present invention incorporates means for providing breathable air, either through means for engagement to a self-contained source of air, or through means for chemically converting exhaled air into breathable air. The present invention also includes means for illumination, and a plurality of means for isolating the face of a user within a face shield airspace such as to provide a protected breathing space within the apparatus.
Further, this apparatus relates to an arrangement of the elements thereof, each having a function directed to the totality of the environmental requirements and having, concurrently, enhanced functionality as elements thereof work cooperatively to achieve the objects of the invention.
This invention relates to a molded helmet and overlying safety assembly that incorporates within itself a plurality of sub-assemblies providing for a diversity of individual element functioning while simultaneously directing each element of the apparatus, in cooperative arrangement, to the needs of individuals working within, or escaping from, smoke-filled or hostile environments, or environments that have low oxygen levels.


A shear pig assembly and method of use for severing a linear conductor within a surrounding tubular. A shear pig assembly includes a main body and a nose that radially surround the linear conductor within the tubular. The main body and nose are axially moveable with respect to each other to cause a shear plug to move radially within a shearing chamber, thereby severing the linear conductor.

1. Field of the Invention
The invention relates generally to systems and methods for severing a tube-wire or similar transmission conductor that is disposed in a surrounding tubular.
2. Description of the Related Art
Coiled tubing has become a popular means for running a bottom hole assembly ("BHA") into a subterranean wellbore. A wireline or tube-wire is sometimes run inside of the coiled tubing when realtime downhole data is required, such as during directional drilling or logging. Tube-wire is a tube that contains an insulated cable that is used to provide electrical power and/or data to the bottom hole assembly or to transmit data from the BHA to the surface. Tube-wire is available commercially from manufacturers such as Canada Tech Corporation of Calgary, Canada.
In the event that coiled tubing and the associated BHA become stuck in the wellbore, it is common practice to pump a ball or plug down through the coiled tubing in order to disconnect the BHA from the coiled tubing. If this fails to free the coiled tubing, then the contingency is to kill the well, cut the coiled tubing at the surface, and run a chemical cutter on wireline down through the coiled tubing in order to retrieve the coiled tubing from the well. If this problem occurs with TeleCoil, then it is necessary to retrieve the tube-wire before running the chemical cutter. The tube-wire in a TeleCoil string is comparatively weak compared to conventional braided cable, and using a tensile shear release mechanism in the BHA for the tube-wire is considered unreliable. Accordingly, the TeleCoil BHA incorporates a ball operated tube-wire release mechanism to facilitate retrieval of the tube-wire. There is no contingency available in the event of a failure of this mechanism. Conventional drop bars and "go devil" devices that are used to sever slickline rely upon gravity to be delivered to a point wherein they can sever the slickline. They are unsuitable for use in horizontal or deviated wellbores.

Devices and methods for severing a tube-wire


A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers.

In microprocessor based system designs, the processor, one or more I/O devices, and the system memory often share a common system bus. Accordingly, communication between the system components takes place over the common system bus. There are a number of different ways in which such communications may take place. However, in each instance, the microprocessor transfers data between the various components on the system bus under the control of application programs.
The manner in which the microprocessor is allowed to handle data transfers varies with the system design. In many systems, direct memory access (DMA) controllers may be employed to significantly reduce involvement of the microprocessor in the data transfer operations and thereby increase data transfer throughput. In a DMA transfer, the microprocessor programs the DMA controller with the source and destination addresses as well as the length of the data block that is to be transferred. The microprocessor then relinquishes control of the system bus to the DMA controller, which drives the system bus and generates the control signals to perform the data transfer. The DMA controller directs the reading of the data from the source address during, for example, a first clock cycle, and directs the writing of the data to the destination address during, for example, a second clock cycle. After each word of data is transferred, the source and destination addresses are automatically incremented (or decremented), and the value for the length of the data block is decremented. The data transfer operation then is repeated for the next word. The DMA controller ceases data transfer operations in response to an underflow of the value for the length of the data block. The DMA controller generates an interrupt to the microprocessor once all data transfers of the data transaction have been completed.
Although the DMA data transfer method reduces the need for intervention of the microprocessor in various data transfer operations, it still requires the microprocessor to set up each data transaction. Further, the microprocessor must perform an interrupt service routine upon completion of each data transaction. These operations still may place a significant burden on the microprocessor.

Direct memory access controller with multiple transaction functionality


A wireless communication system is able to balance load in a wireless network based on radio frequency (RF) utilization, signal strength, quality of signal (QoS), and other measures. The load may be dynamically moved to other wireless access points within the wireless network based on the amount of load on one or more of the access points and on the measures. As such, at different load conditions, the system can change the methods of how to determine which access point should handle a communication session. Further, the system provides methods for proactively adjusting the load in the wireless network before any one access point reaches its capacity.

Improving the quality of service for voice over internet protocol (VoIP) over wireless Local Area Networks (LANs) is on the critical path to achieving the vision of the unwired enterprise. Achieving high quality VoIP poses several challenges, particularly in heavily loaded systems. Wireless systems generally use signal strength as the determinant factor for which wireless access point should accept a communication session with a mobile device. In many situations, a small number of access points become overloaded as those access points are in high usage areas but have the best signal strength.
As a calling party or mobile user moves relative to an access point, the RF bandwidth requirements may change (increase or decrease) drastically, depending on the change in distance. Since this change is not accounted for by traditional call admission control algorithms, resource overload can result. Counting sessions as they arrive, for instance, and denying calls beyond a specific number requires over-engineering to account for bandwidth variability. RF-based connections, unlike wired connections, are subject to much more interference (i.e., other radios, noise sources, etc.), which can affect RF bandwidth requirements for the session. RF bandwidth is partitioned across different traffic classes, voice, video, and data, which may result in unused RF bandwidth, if not needed by one of the traffic classes. As callers move from one access point zone to the next access point zone, the likelihood of the adjacent access point taking over the call must remain high (almost independent of call volume) to prevent unexpected disconnections.
Presently, there are no good methods for balancing load based on other factors beyond signal strength and addressing the other issues mentioned above. Direct measurement of RF utilization is generally not available. Hybrid techniques for estimating RF utilization by applying mathematical models to partial measurements are relatively complex, particularly from modeling the behavior in the collision region, and therefore impractical. Further, user datagram protocol (UDP) traffic is not separately balanced for load. Finally, load balancing is generally accomplished only when bandwidth is completely allocated, which can cause errors when trying to quickly move loads to other systems.

Proactive load distribution for 802.111-based wireless LANs


Devices and methods for determining and indicating a source of power based on a characteristic of received power are disclosed. According to an aspect, a device includes a power line interface configured to receive power from multiple power lines. The device also includes a comparator module configured to compare one or more characteristics of the received power from the plurality of power lines. The comparator module is also configured to determine whether the received power on the power lines are from the same source based on the comparison. Further, the device includes a user interface configured to indicate whether the received power on the power lines are from the same source based on the determination.

Data centers are buildings with dedicated space for housing computer servers. For highly-available data centers, the power distribution infrastructure typically relies on redundancy at multiple levels to ensure reliable power delivery to servers. There can be multiple power supplies and multiple utility feeds into the data center. Such redundancy can ensure continued availability of full power demand in the event of failure of some of the power devices at each level.
At the server rack level, multiple power feeds may be used to support redundancy. The multiple feeds are each connected by a power line to a rack's power distribution unit (PDU), which is capable of supporting the full load of the rack's equipment. Also, a server of a chassis includes multiple power supply modules to provide redundancy in case of a module failure, or a power line or cable failure. However, even if a server has multiple power supply modules, the redundancy is affected if all its power inputs are connected to the same power source or power line/cable. For example, power lines to a server should be connected to different source lines of power, but there is no redundancy if an installer or other operator of the equipment mistakenly connects the power lines of the server to the same line of power. Therefore, it is desired to provide equipment and techniques to avoid misconfiguration of power line connections to a server or other computing equipment.

Lenovo Global Technology (United States) Inc.


An axial force resisting pipe coupling for coupling pipes in aligned end-to-end relation. The coupling is of a simplified, economical construction comprising a plurality of axially aligned spaced clamps, including a central clamp and two outrigger clamps, attached to a common bar, and the coupling may be formed by retrofitting an existing central clamp with the outrigger clamps and bar. Each of the clamps consist of a generally circular band terminating in opposed connecting end flanges and are attached to the bar at the flanges by fasteners which also facilitate circumferential contraction and expansion of the clamps. Projections may be formed on the bands for embedding into the pipe members to minimize the likelihood of the pipes pulling apart due to high tension forces.

Pipe couplings using circumferential bands are commonly employed in connecting aligned end-to-end pipes as shown in U.S. Pat. No. 4,473,246. However, such couplings do not provide high resistance to significant tension forces in the pipes, and it is known to resist high tension forces with this type of coupling by using outrigger clamps in conjunction with a central clamp as shown in U.S. Pat. No. 4,502,189. Such clamps comprise a generally circular band portion terminating in opposed connecting end flanges, and the outrigger clamps are attached to the central clamp by strap elements. Fasteners in the form of a nut and bolt are passed through the opposed connecting flanges and are tightened to draw the connecting flanges toward each other.
Although the aforementioned pipe couplings have proven to be dependable they have a relatively complicated and expensive construction or require a relatively large number of parts which makes for a time consuming assembly process and adds to the overall cost of the product. Also, the outrigger type clamp requires a specific configuration and cannot be modified to a non-outrigger type if the extra resistance to tension forces is not required.
An object of the invention is to provide an axial force resisting pipe coupling having outrigger clamps wherein the pipe coupling requires a small number of components, is of a simple construction, economical to manufacture, and simple and efficient to use.
A further object of the invention is to provide an axial force resisting pipe coupling having a central clamp and a pair of outrigger clamps wherein the outrigger clamps can be retrofitted to a conventional circumferential clamp and the invention permits a variety of clamp configurations to be assembled from a minimum number of inventoried parts.
Another object of the invention is to provide an axial force resisting pipe coupling having outrigger clamps wherein the outrigger clamps are provided with projections for embedding into the pipe members to increase the axial force resistance of the coupling.
An axial force resisting pipe coupling in accord with the invention consist of a central clamp and two axially spaced outrigger clamps. Each of the clamps are attached to a common outrigger bar and are fabricated by forming a piece of sheet metal into a generally circular configuration defining a circular band portion terminating in opposed connecting end flanges directed radially outwardly from the band. The flanges are rolled back defining loops which receive reinforcing bars and are provided with apertures which align with apertures defined in the outrigger bar. Each of the aligned apertures receive a carriage bolt on which a nut is threaded to mount the clamps to the outrigger bar and the same nut and bolt also facilitate circumferential contraction and expansion of the clamps.
In a typical application the central clamp overlaps the aligned ends of the pipe members to be joined while each of the outrigger clamps circumscribes one of the pipe members at an axially spaced distance from the central clamp. Tightening of the nuts and bolts is effective to draw the opposed flanges toward each other and thereby impart circumferential tension to the clamps sufficient to maintain the pipes together. If desired, the outrigger clamps may be fashioned with projections or dimples for embedding into the pipes to increase the friction of the outrigger clamps and minimize the likelihood of the pipes separating due to high tension forces.
If a leak resistant joint is specified, sleeve elements may be disposed within the central clamp to impart a leak resistant characteristic to the joint. These sleeve elements may include a metal sleeve disposed within the central clamp, and an elastomeric sleeve disposed within the metal sleeve. Each of the sleeves overlap the ends of the pipes and are tightened to the pipes simultaneously with the drawing together of the opposed flanges. The metal sleeve tightens the elastomeric sleeve to the pipe ends which provides leak resistance for the joint.
As the bar connecting the outrigger clamps to the central clamp is attached to the central clamp by its constricting fasteners, and the bar is likewise attached to the outrigger clamps, the bar and outrigger clamps may be easily retrofitted to existing central clamps and the practice of the invention minimizes inventories and provides a versatility of clamp availability not previously available.
The fact that the outrigger clamps and central clamps are attached to a common bar by fastening means which are also utilized to facilitate circumferential contraction and expansion of the clamps provides a coupling of a simple, economical construction which is readily assembled, convenient to install and capable of resisting high tension forces.


A thrust-bearing (1) disposed to face a thrust collar provided on a rotary shaft, including: grooves (5) formed at a bearing-surface (4b); a first-groove-group (6A) constituted by a plurality of first-spiral-grooves (6) formed at an inner circumferential side of the bearing-surface (4b); a second-groove-group (7A) constituted by a plurality of second-spiral-grooves (7) formed at an outer circumferential side more than the first-groove-group (6A) and wound in the same direction as the first-spiral-groove (6); and an annular-land-section (8) formed at the side, to which a fluid is drawn, among the inner circumferential more than the first-groove-group (6A) and the outer circumferential more than the second-groove-group (7A), wherein some of the first-spiral-grooves (6) of the first-groove-group (6A) and some of the second-spiral-grooves (7) of the second-groove-group (7A) are in communication with each other via a partial-communication-section (11), at least one side of which is in partial communication with the other side.

In the related art, a thrust bearing disposed opposite to a thrust collar installed at a rotary shaft is well known as a bearing for a high speed rotor. Among thrust bearings, for example, a thrust dynamic pressure bearing using a dynamic pressure effect has a spiral groove formed at a bearing surface of the bearing, and as a fluid lubricating film is formed between the thrust collar and the bearing surface, the rotary shaft is supported via the lubricating film.
A pump-in type (the structure type), a pump-out type, and a herringbone type are well known as spiral grooves of the thrust bearing, which are formed in the bearing surface of the thrust dynamic pressure bearing. In the spiral groove, for example, in the pump-in type or pump-out type, a plurality of spiral grooves (spiral-shaped grooves) are formed at the same pitch. All of the spiral grooves are formed to have the same inflow angle. One end of the spiral groove is closed by a land section in the innermost circumference or the outermost circumference of the bearing surface, and the other end is opened.
A type (a structure type) in which the land section is formed at the innermost circumference is referred to as the pump-in type, and a type in which the land section is formed at the outermost circumference is referred to as the pump-out type. When these are assembled to the thrust collar, which is rapidly rotated, a lubricating fluid sandwiched between the thrust collar and the bearing by rotation of the thrust collar is pulled to the thrust collar through viscosity thereof. As a result, the lubricating fluid flows along the groove. For example, in the case of the pump-in type, the lubricating fluid is drawn at the outermost circumference of the bearing surface. The drawn lubricating fluid is introduced (drawn) to the innermost circumferential side from the outermost circumference of the bearing along the groove. After that, the lubricating fluid runs on the innermost circumference land section at the closing end of the groove. Here, as a flow path is abruptly narrowed, a pressure (a film pressure) of the fluid lubricating film is increased.
As a result, the film pressure of the fluid lubricating film of the pump-in type becomes a mountain-shaped distribution in which a peak is formed at a boundary section (the closing end of the groove) between the innermost circumference land section and the groove. Similarly, the film pressure of fluid lubricating film of the pump-out type becomes a mountain-shaped distribution in which a peak is formed at a boundary section (the closing end of the groove) between the outermost circumference land section and the groove. In reality, all the lubricating fluid does not flow in the groove. Some of the lubricating fluid flows in a circumferential direction and runs on a spiral-shaped land section formed between groove rows. For this reason, in the pump-in type, the film pressure is also generated between the spiral groove of the outer circumferential side and the land section (between the groove closer to the outer circumferential and the land section). In the pump-out type, the film pressure is also generated between the spiral groove of the inner circumferential side and the land section (between the groove closer to the inner circumferential and the land section).
In addition to the pump-in type or the pump-out type, a bearing having a spiral groove in which the herringbone type, pump-in type, and pump-out type are assembled is well known (for example, see Patent Document 1 and Patent Document 2).


An inserter system including a first station operative to output personal inserts for inserting in envelopes, an inserter operative to insert the personal inserts in the envelopes, and a dynamic buffer operative to convey the personal inserts from the first station to the inserter, the dynamic buffer including a partition-less adjustable length conveyor and an inserter-interface conveyor, wherein the adjustable length conveyor conveys the personal inserts from the first station to the inserter-interface conveyor and the inserter grabs the personal inserts from the inserter-interface conveyor, and wherein the inserter grabbing the personal inserts determines a speed of operation of the inserter-interface conveyor, including a timing at which the inserter-interface conveyor grabs the personal inserts from the adjustable length conveyor.

Inserter systems are typically used to produce a large volume of specific mailings where the contents of each mail item are directed to a particular addressee, such as for banks, insurance companies, utility companies, municipalities and many more. In the type of inserter system relevant to the present invention, a personal insert is inserted in an envelope. A personal insert is a message intended for a particular addressee. The personal insert can be one or more sheets which come from a single source (e.g., continuous roll or fanfold paper or batches of sheets). The sheet or sheets are usually (but not necessarily) folded together and reach the inserter as one group for insertion into an envelope. Other mail items can be added afterwards in the enveloping process.
Inserter systems of this type work most efficiently when run at constant speed. However, the station (e.g., folder or cutter) that supplies the personal inserts cannot work at a constant speed due to the personal inserts having a different number of pages. As a result, the inserter system is forced to operate at varying speeds, which diminishes the efficiency of the system.


A programmable controller includes a CPU unit, a communication unit and peripheral units connected together through an internal bus. The communication unit has a bus master function, including a cache memory for recording IO data stored in the memory of an input-output unit. When a message is received, it is judged whether the IO data stored in the memory of the input-output unit specified by this message is updated or not. If the data are not updated, a response is created based on the IO data stored in the IO data stored in the cache memory. If the data are updated, the input-output unit is accessed and updated IO data are obtained and a response is created based on the obtained IO data.

This invention relates to a programmable controller and a communication unit therefor.
Network systems for factory automation (FA) are comprised of one or more programmable controllers (PLC) for controlling production equipments and apparatus of which the operations are controlled by the PLC, connected together to a control system network. These PLC and apparatus serve to control the production equipments by exchanging IO data among them by carrying out communications cyclically through the control network.
The PLC is formed by combining a plurality of units such as a CPU unit for carrying out calculations based on a control program, an input unit connecting to input devices such as sensors and switches for taking in their on-off signals as input signals, an output unit connecting to output devices such as actuators and relays for transmitting output signals to them, a communication unit for exchanging data with other devices connected to the network, and a power unit for supplying electric power to each unit.
There are situations in FA where a plurality of control devices such as programmable controllers are connected to the network for carrying out a cooperative control among them. For carrying out such a cooperative control, data on the input-output devices connected to the programmable controllers may be exchanged mutually among them through the network. Methods of thus exchanging data among the programmable controllers include the data exchange method of the command-response type whereby one PLC transmits a request message to another PLC for exchanging data and the data of the PLC input-output unit are received as a response, as well as the so-called datalink method whereby each PLC carries out transmission and reception of I/O data periodically, based on information that is preliminarily set.
When programmable controllers connected to a network exchange data among them, this is carried out through the communication units which are each one of the constituent units of a programmable controller. Since each communication unit is provided only with the function of transmitting and receiving data, it cannot execute any process in either of these methods requiring an access to the memory of an input-output unit such as the I/O access process of datalink and the process of getting I/O data by message transmission. Since the access to such a memory can be executed by the CPU unit which is a bus master, it was necessary for the communication unit to transmit to the CPU unit a request for I/O access.
Thus, since the I/C access process is carried out by the CPU unit whenever I/O data are exchanged, for example, the load on the CPU unit becomes heavy in the case of a high-frequency data exchange, and this may seriously affect the control which is the principal function of the CPU unit. In the case of a data exchange method which must be carried out through the CPU unit for accessing a peripheral unit such as the input-output unit, therefore, the user could not accomplish both a high-speed control of a programmable controller and a high-speed and high-frequency data exchange on the network at the same time.
Japanese Patent Publications Tokkai 5-173985 and 5-173986 have disclosed a programmable controller provided with a plurality of CPU units so as to have a multi-bus master function, these CPU units being capable of independently accessing the individual input-output units. These inventions can be utilized to provide a communication unit with the function of accessing the I/O memory of the input-output unit such that the load on the CPU units is reduced.
In view of the demand for increasing the speed of data exchange cycle and the data volume, however, there is a problem of sudden increase in the bus traffic due to the bus access by the communication devices at the time of data exchange, and both communication units and CPU units are thereby affected. This problem cannot be answered only with communication units with the capability of directly accessing peripheral units without going through the CPU unit.

Programmable controller and communication unit therefor


A toothbrush head which is effective for cleaning and polishing teeth and massaging and stimulating the gums, without injury to hard and soft tissue and is durable. The head includes a plurality of integral projections parallel to each other and extending outwardly from a pad. Each projection is constructed of a thermoplastic elastomer providing a high coefficient of friction between the projections and tooth enamel and cementum. The tip and side surfaces of the projections have substantially identical coefficients of friction between the respective surfaces and the tooth's enamel/cementum. At least a portion of the plurality of projections have beveled edges. The projections having beveled edges are preferably arranged in pairs. Each projection of each pair has a beveled edge oriented so as to be positioned in facing relationship with the other projection of the pair. The pairs are configured as facing truncated cylinders. A lip surrounds the perimeter of the head and serves as a bumper in order to protect the gums during brushing.

1. Field of the Invention
This invention relates to a durable toothbrush head which is effective for cleaning and polishing teeth, and massaging and stimulating the gums, without injury to the hard or soft tissues.
Conventional toothbrushes with nylon bristles have been used since the 1940's. Despite manufacturer's numerous attempts to improve nylon bristles, they continue to exhibit the same disadvantages as conventional toothbrushes. These disadvantages include: (1) rapid permanent deformation (matting and tapering of the bristles) of the brushing structure resulting in inefficient cleaning and limited toothbrush life: (2) poor polishing (inadequate coefficient of friction and surface area): (3) abrasion to hard and soft tissues: and (4) difficulty in cleaning and drying bristles and tuft retention apertures resulting in compromised hygiene and consequent bacterial/fungal growth.
A person generally uses his or her toothbrush for up to six months. However, for many brush heads, the effect of permanent deformation is manifest by a drop in the ability to remove plaque after only about three weeks of use. In areas where the tooth surface becomes more difficult to reach, such as lingual surfaces, the loss of effectiveness is greater. Both bristle matting and bristle tapering substantially reduce the ability of the brush to remove plaque. Studies have shown that toothbrushes with considerable wear were 50-100% less effective in removing plaque than new toothbrushes. Brush conditions deteriorate with length of use; however, length of use is not determinative in the amount of matting and tapering present. A brush resistant to matting would have markedly superior durability.
Studies have shown that thermoplastic elastomers manifest a polishing of enamel and cementum while the nylon head tends to track on the enamel and cementum and scratch the surface of the tooth. Additionally, thermoplastic elastomeric materials are resistant to fatigue, and thus, to bristle matting and tapering.
One study found that the only successful method for sterilization of a toothbrush is heating in a microwave oven. However, this method distorts nylon bristles so that it is not feasible for a nylon toothbrush.


A semiconductor structure and method for transmitting optical signals modulates an optical property of the semiconductor structure to selectively transmit portions of an externally supplied light beam as optical signals. The use of the externally supplied light beam eliminates the need to fabricate a light emitting device onto the semiconductor structure. Thus, the semiconductor structure can be based on an indirect bandgap material such as silicon. Consequently, the semiconductor structure can be readily integrated into a conventional silicon-based integrated circuit using conventional semiconductor manufacturing processes.

The invention relates generally to semiconductor structures, and more particularly to a semiconductor structure that can transmit optical signals.
The use of silicon to manufacture integrated circuits (ICs) is a well-developed technology. Since early years of IC development, silicon has dominated the field of electronics to become the most widely used material to fabricate and integrate various electronic devices, in particular transistors such as bipolar and metal oxide semiconductor (MOS) transistors. Consequently, silicon technology has significantly advanced in comparison to other alternative technologies. As a result, silicon-based ICs have a number of advantages over other technologies. For example, silicon-based ICs can be manufactured with relative ease using established semiconductor processes. In addition, an extremely high density of electronic devices can be fabricated on silicon-based ICs. Therefore, silicon-based ICs are currently the preferred embodiment for large-scale high-volume signal processing electronics.
The preference of silicon-based ICs makes silicon the material of choice for fabrication of light emitting devices so that optical functions can be added to signal processing ICs. Unfortunately, silicon is not well-suited for fabrication of light emitting devices. Due to the indirect bandgap of silicon, any light emitting device fabricated using silicon will not emit radiation with significant quantum efficiency. Nevertheless, there has been much effort to incorporate conventional light emitting devices such as GaAs lasers onto silicon-based signal processing ICs to provide optical interconnectivity.
A concern with incorporating conventional light emitting devices onto silicon-based signal processing ICs is that the manufacturing process of such ICs is significantly more complex than convention IC manufacturing process. The complexity of the manufacturing process translates into increase in the manufacturing cost of the ICs with light emitting devices.
In view of these concerns, there is a need for a semiconductor structure and method for transmitting optical signals that can be readily integrated into a silicon-based IC without significantly increasing manufacturing complexity and cost.
A semiconductor structure and method for transmitting optical signals modulates an optical property of the semiconductor structure to selectively transmit portions of an externally supplied light beam as optical signals. The use of the externally supplied light beam eliminates the need to fabricate a light emitting device onto the semiconductor structure. Thus, the semiconductor structure can be based on an indirect bandgap material such as silicon. Consequently, the semiconductor structure can be readily integrated into a conventional silicon-based integrated circuit using conventional semiconductor manufacturing processes.
A semiconductor structure in accordance with the invention includes a semiconductor substrate, a port positioned over the semiconductor substrate and an optically active region positioned between the port and the substrate. The optically active region has a controllable optical property to manipulate an externally supplied light beam, which is received through the port, such that portions of the light beam can be selectively transmitted through the port as optical signals. The semiconductor substrate may include an indirect bandgap material.
The optically active region includes a controllable layer having the controllable optical property, which is responsive to an electric field, to selectively retard polarization components of the externally supplied light beam, and a reflective element positioned below the controllable layer to reflect the polarization components. The controllable layer may be configured to substantially operate as a quarter-wave plate.
In an embodiment, the optically active region further includes a walk-off layer configured to displace a polarization component of the externally supplied light beam. The walk-off layer and the controllable layer may each include a birefringent material.
In an embodiment, the semiconductor structure includes a polarizing beamsplitter configured to selectively reflect a polarization component of the externally supplied light beam.
In an embodiment, the port includes a single aperture in an opaque layer positioned above the optically active region. In another embodiment, the port includes an input aperture and an output aperture in the opaque layer.
A method of transmitting optical signals in accordance with the invention includes receiving an externally supplied light beam at a port of a semiconductor structure, and modulating an optical property of the semiconductor structure to manipulate the externally supplied light beam so that portions of the light beam are selectively transmitted though the port as optical signals.
In an embodiment, the externally supplied light beam may be received at an input aperture of the port, while the portions of the externally supplied light beam may be transmitted through an output aperture of the port.
In an embodiment, the method further includes separating first and second polarization components of the externally supplied light beam, reflecting the first and second polarization components toward the port, and displacing one of the first and second polarization components depending on polarized orientations of the first and second polarization components. The separating of the first and second polarization components and the displacing of one of the first and second polarization components may be performed by a walk-off birefringent layer of the semiconductor structure.
In another embodiment, the method further includes transmitting a particular polarization component of the externally supplied light beam, reflecting the particular polarization component toward the port, and selectively reflecting the particular polarization component depending on polarized orientation of the particular polarization component. The transmitting of the particular polarization component and selectively reflecting the particular polarization component may be performed by a polarizing beamsplitter.
In an embodiment, the modulating of the optical property of the semiconductor structure includes controlling an electric field within the controllable layer of the semiconductor to change the optical property of the semiconductor structure to a first state. The controllable layer is configured to substantially function as a quarter-wave plate when the semiconductor structure is changed to the first state.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrated by way of example of the principles of the invention.

Semiconductor structure and method for transmitting optical signals using externally supplied light beam


Methods for converting, encoding, decoding and transcoding an acoustic field, more particularly a first-order Ambisonics three-dimensional acoustic field.

The production, transmission and reproduction of a three-dimensional audio signal is an important part of any audiovisual immersion experience, for example in the context of presentations of content in virtual reality, but also when viewing cinematographic content or in the context of recreational applications. Any three-dimensional audio content thus goes through a production or capture phase, a transmission or storage phase and a reproduction phase.
The production or obtainment phase of the content can be done through many very widespread and widely used techniques: stereophonic, multichannel or periphonic capture, or content synthesis from separate elements. The content is then represented either through a number of separate channels, or in the form of a periphonic sound field (for example in order 1 or higher Ambisonics format), or in the form of separate sound objects and spatial information.
The reproduction phase is also known and widespread in professional or general public fields: stereophonic headsets or headsets benefiting from binaural rendering, devices with stereophonic enclosures (optionally benefiting from transaural processing), multichannel devices or devices with a three-dimensional arrangement. The transmission phase can be made up of a simple channel-by-channel transmission, or a transmission of the separate elements and spatial information making it possible to reconstitute the content, or encoding making it possible, most often with losses, to describe the spatial content of the original signal. There are many audio encoding processes making it possible to preserve all or some of the spatial information present in the original three-dimensional signal.
Beginning in the 1960s, Peter Scheiber was one of the first to describe a stereophonic mastering process of a planar surround field and then provided for using what has since born the name "Scheiber sphere" as immediate correspondence tool for the magnitude and phase relationship between two channels and a three-dimensional spatial position.
For example, in "Analyzing Phase-Amplitude Matrices" (JAES, 1971), Scheiber introduced the concept of linear mastering using the phase and amplitude difference to encode and decode spatial positions, in two or three dimensions, defining what is now known as the "inter-channel domain" (i.e., the domain with two dimensions made up of amplitude differences between the two channels on the one hand, and phase differences on the other hand) and reveals an implementation thereof in U.S. Pat. No. 3,632,886. However, due to the linearity of the encoding and decoding operations, the separation performance between channels is then limited for this implementation.
A critical analysis of stereophonic mastering systems of type 4-2-4 (i.e., four original channels, mastered and transported on 2 channels, then decoded and reproduced on 4 channels) is provided by Gerzon in "Whither Four Channels" (Audio Annual, 1971). In "A Geometric Model for Two-Channel Four-Speaker Matrix Stereo System" (JABS, 1975), Gerzon studies and proposes several possibilities for 4-2-4 mastering, and again describes the possibilities for describing a three-dimensional field on the energy sphere (whose principle is identical to the "Scheiber sphere"), and therefore three-dimensional encoding on two channels. This last capacity is recalled by Sommerwerck and Scheiber in "The Threat of Dolby Surround" (MultiChannelSound, Vol. 1, Nos. 4/5, 1986).
In "A High-Performance Surround Sound Process for Home Video" and the corresponding implementation disclosed in U.S. Pat. No. 4,696,036, Julstrom uses the concepts developed by Scheiber and Gerzon to obtain an improved separation of the original signals in the favored directions corresponding to a placement of seven speakers in the horizontal plane. Techniques having a similar aim of improving the separation are presented in later publications, such as U.S. Pat. Nos. 4,862,502, 5,136,650, or WO 2002007481.
In 1996, in U.S. Pat. No. 5,136,650, Scheiber presents a hemispherical encoding system on two channels, which applies this principle in the temporal domain, in a mastered manner similar to the surround mastered techniques, and adding a decorrelation variable as an additional dimension making it possible to describe the distance of the sound source relative to the origin of the hemisphere; this decoder is, inter alia, provided to supply the matrix decoders then commercially available; the decorrelation prevents said decoders from determining a unique position for the source, which leads to spatial spreading during the decoding. The same patent presents decoders adapted to the encoder, allowing a broadcast on transducers arranged along a hemisphere.
It has been known since the 1970s and 1980s that the short-term Fourier transform, described for example in Papoulis, "Signal Analysis" (McGraw Hill, 1977 pp. 174-178), is a useful tool for processing the signal in separate frequency bands. Furthermore, the advantages of this transformation principle in the frequency domain are known in the context of source separation (which requires a spatial analysis of the signal), for example in Maher, "Evaluation of a Method for Separating Digitized Duet Signals" (JABS Volume 38 Issue 12 pp. 956-979; December 1990), then in Balan et al., "Statistical properties of STFT ratios for two channel Systems and applications to blind source separation" (Proc. ICA-BSS, 2000). It is also known that other types of transforms such as the complex wavelet transform (CWT), the modified discrete cosine transform (MDCT, used in MP3 or Vorbis codes), or the modulated complex lapped transform (MCLT) can advantageously be used in the context of processes for processing the digital audio signal. Thus, a direct application of the principle described by Peter Scheiber was made possible in the frequency domain, but as we will describe later, to within the knowledge of the phase.
In U.S. Pat. No. 8,712,061, Jot et al. again describe the correspondence (mapping) techniques between the Scheiber sphere (amplitude-phase) and the coordinates of the physical space, optionally via a surround or periphonic panoramic law that is next mastered traditionally, and while presenting an implementation in the frequency domain, based inter alia on the need to have, as input, a directional signal and a non-directional "ambient" signal. In addition to this last decomposition constraint of the incoming signal, this approach suffers, whether during the encoding or decoding phase, from a major problem of discontinuity of the phase representation: there is a spatial discontinuity of the phase with a temporally static correspondence of the phase introduced by a generic "panoramic law", introducing artifacts when a sound source is placed in certain directions of the sphere or moves over the sphere while performing certain trajectories. As will be apparent in the continuation of the present document, the present invention makes it possible to solve this discontinuity problem and does not require separation of the incoming signal into an ambient part and a direct part.
The matrix decoder described in US 20080205676 by Merimaa et al. copies the methods disclosed in U.S. Pat. No. 5,136,650 in the frequency domain. Like in the preceding patents, the issue of phase discontinuity is not addressed.
In WO 2009046223, Goodwin et al. describe a format conversion and binaural rendering device from a stereophonic signal, which is based on a primary source/ambient source decomposition similar to that disclosed in U.S. Pat. No. 8,712,061, and a direction of origin analysis using the methods disclosed by Scheiber in U.S. Pat. No. 5,136,650. Like in the preceding patents, the issue of phase discontinuity is not addressed.
In "A Spatial Extrapolation Method to Derive High-Order Ambisonics Data from Stereo Sources" (J. Inf. Hiding and Multimedia Sig. Proc, 2015), Trevino et al. propose a two-dimensional (planar) decoding system of an HOA field previously encoded on a stereophonic stream, still according to the principles of Scheiber. The main problems encountered by the authors are on the one hand the presence of a phase discontinuity (for values close to π) and on the other hand instabilities in the extreme stereo panoramic positions, for which the metrics used are indefinite. In "Enhancing Stereo Signals with High-Order Ambisonics Spatial Information" (IEICE, 2016), an encoding method making it possible to obtain said signal is specified, still with the same issues of phase and amplitude discontinuity. In both cases, the authors try to lessen said discontinuity problems by applying an empirical correction of the level and phase difference metrics, followed by a deformation of the inter-channel domain, at the cost of a compromise between stability and localization precision. The method disclosed in the present document makes it possible to settle these two problems without stability or localization precision compromise.
One of the aims of the present invention is to disclose a method that makes it possible, in the context of encoding toward a stereophonic stream or in the context of decoding of a stereophonic encoded stream, a continuity of the signal including its phase, irrespective of the position of the source and irrespective of the path it describes, without requiring a non-directional component in the input signal, or the matricial encoding of the signal, or compromise between stability and localization precision for the extreme positions in the inter-channel domain.
Another aim of the present invention is to provide decoding and transcoding from a stereophonic signal, optionally encoded with one of the implementations of the invention, or encoded with the existing matricial encoding systems, and to negate it on any broadcasting means and in any audio format, without requiring any compromise between stability and localization precision.
Another aim of the present invention is to provide a complete transport or storage chain for a three-dimensional acoustic field, in a compact format accepted by the standard transport or storage means, while retaining the relevant three-dimensional spatial information of the original field.

Method for conversion, stereophonic encoding, decoding and transcoding of a three-dimensional audio signal


A digital camera is provided with a data amount detector and a clock control circuit. The data amount detector detects the amount of image data stored in an SDRAM in capturing a moving image. The clock control circuit controls a transfer speed of the image data from the SDRAM to a memory card by changing a frequency of a system clock based on the detecting result from the data amount detector. When the data amount is less than a first threshold value set near a lower limit of a memory capacity of the SDRAM, the clock control circuit reduces the data transfer speed by lowering the frequency of the system clock; meanwhile, the data amount is more than a second threshold value set near an upper limit of the memory capacity of the SDRAM, the clock control circuit accelerates the transfer speed by raising the frequency of the system clock.

1. Field of the Invention
The present invention relates to an image capturing apparatus capable of controlling a recording speed of recording media during a capture of a moving image.
2. Description of the Related Arts
There is a widespread use of a digital camera in which a signal output from a solid-state imaging device such as a CCD is converted into image data of digital signal form by an A/D converter, and the image data is recorded in a recording medium such as a built-in memory or a removable memory card. This type of digital camera has a moving image capture function as well as a still image capture function.
In the digital camera, field images are sequentially output from the CCD at a constant frame rate (e.g. 30 frames/sec.) during the capture of the moving image. The field images are temporarily stored in a buffer memory. Subsequently, the filed images are read out from the buffer memory, and recorded in the recording media after various kinds of image processing including the YC conversion and the compression processing are applied thereto (see Japanese Patent Laid-Open Publications No. 2004-56741).
In the moving image capturing, many field images are recorded in the recording media, and the amount of the image data output from the CCD becomes very large. In some models or types of recording media, the recording (writing) operation might be so slow that the recording media may possibly store unwatchable moving images in which the frames are missed in parts.
As a method for solving the above problem, it is considered that a high frequency system clock for operating a CPU, the buffer memory, the recording media, and so forth is used to accelerate a transfer speed of the image data (a reading speed of the buffer memory, a recording speed of the recording media). However, if the high frequency system clock is used, it causes another problem that the power consumption is increased.

Image capturing apparatus that performs dynamic frequency control of buffer memory during moving image capture


The present invention is an improved apparatus and method for forming a retractable tower or column. The present invention includes pointed hooks wherein the hooks are attached to each section of a section chain, one in a horizontal direction and one in an off-set manner. The section chains are placed on a take up mechanism in an operable position and then raised utilizing a motor. As the section chains are raised, they are guided by a guide tower, rollers, shims, and gear racks into a position whereby hooks from adjacent sections of the section chains form coupled engagements. The coupled engagement of the hooks of the sections of each adjacent section chains thereby form the column.

Link structures that can be linked together to form a rigid structure are well known in the art. Structures of this kind may be used to form a platform to elevate a person or equipment, to form a bridge to permit a user to pass over an obstacle, or to form a dock. Additionally, such structures have been used in space applications to extend a flexible sheet of material or to form a tower as a structure in space. See U.S. Pat. Nos. 2,661,082, 3,397,546, 4,024,595, 4,089,147, and 4,237,662.
Retractable towers of this kind may be further utilized as a portable telecommunications tower, wherein various sights can be tested without constructing a costly test tower at a location to discover it was not effective for the intended purpose. Retractable towers may also be used as a temporary lighting systems for sporting events, emergencies, or on ships. Other applications may also be present in a variety of other fields and a variety of other situations.
The formation of retractable columns has been previously described. U.S. Pat. No. 4,920,710 to David L. Paine previously described a retractable support column for use in lifting and suspending overhead structures, which is herein incorporated by reference for everything it discloses. The structures that were formed using this apparatus and method, however, were subject to poor interconnection of the tower sections. The poor connection of the sides of the tower was caused in part by poor alignment of the section chains, and through the hooks, as the sides were raised. Poor alignment of the adjacent sections resulted in a poorly constructed tower; when a large amount of stress was placed on the poorly aligned tower, it sometimes resulted in the sheering of the pins holding the tower. The sheering of the pins resulted in a low structural integrity for the tower. These problems increased the difficulty in using towers systems of this type and also increased safety concerns and dangers.
Accordingly, there is a need for an improved retractable tower structure that provides greater structural integrity. There is a further need for a retractable tower which is more reliable, which provides a sturdier tower under adverse conditions, and which increases the load bearing characteristics of towers.

Retractable column and method of forming


A toner manufacturing process, includes: melting a kneaded composition, to thereby obtain a melted composition; and spraying the melted composition with a high pressure gas, to thereby form a fine particle. The kneaded composition is selected from the group consisting of the following <1>, <2> and <3>: <1> a first kneaded composition including a binder resin, a colorant, and a charge controlling agent, <2> a second kneaded composition including a binder resin, a colorant, a charge controlling agent, and a releasing agent, and <3> a third kneaded composition including a binder resin, a magnetic agent, a charge controlling agent, and a releasing agent.

1. Field of the Invention
The present invention relates to a toner which is preferably used for an electrophotography, an electrostatic recording process, an electrostatic printing process and the like. Moreover, the present invention relates to an effective process for manufacturing the toner. Furthermore, the present invention relates to a developer using the toner, a toner container, a process cartridge, an image forming apparatus, and an image forming process.
2. Description of the Related Art
In terms of the electrophotography, recently, with the digitization as well as the development of network and computer, a graphic copy printout (mainly using photographs) is increasing in addition to a conventional character copy printout.
Improvement in image quality by the electrophotography is more and more required, one measure therefor including toner's smaller sizing (namely, smaller diameter of toner particle).
For obtaining the above toner, a pulverizing process including a series of operations is conventionally used in which a plurality of materials constituting the toner are heated, melted and kneaded, and thereafter the thus obtained kneaded compositions are to be pulverized. Specifically, the above plurality of the materials include <1> a kneaded composition containing at least a binder resin, a colorant, and a charge controlling agent; <2> a kneaded composition containing at least a binder resin, a colorant, a charge controlling agent, and a releasing agent; <3> a kneaded composition containing at least a binder resin, a colorant, a charge controlling agent, a releasing agent, and a magnetic agent; and the like.
The above pulverizing process is, however, inconvenient due to its low energy efficiency which may be attributable to an increase in an energy spent on the pulverization, also due to increased fine particles in the pulverization. Moreover, the above pulverizing process may form angled particles and thereby decrease circularity of the particles, thus decreasing fluidity, supplying property, minor-dot reproducibility, which is also inconvenient.
For solving the above decreased circularity (due to the angled particles) and improving quality, a classifying operation is additionally carried out after the pulverization, so as to make a sharp distribution of particle diameters. In this case, however, product recovery may be decreased.
On the other hand, the image obtained in the electrophotography, recently, has been so improved in quality as to be comparable with that obtained in a silver salt photography. With this, it is required that graininess of the toner is in a range from 5 μm to 6 μm having a narrow distribution, which range is becoming a mainstream. The toner having the above graininess is more and more practical by a polymerizing process.
Compared with the conventional pulverizing process (including i. a kneading operation, ii. a pulverizing operation and a classifying operation, iii. a circulating mixing operation and a sieving operation), manufacturing the above polymerized toner is lower in carbon dioxide generation but higher in water consumption, bringing about an environmental protection issue and cost issue in water treatment. In terms of equipment, the above polymerized toner needs a huge plant, therefore, a mass production is necessary for reducing cost, increasing an initial capital investment.
The present inventors and others, for solving the above inconveniences, took a look at a spraying-granulating technology and studied it, which technology had not been conventionally proposed at all in the production of the electrophotographic toner.
As a spraying-granulating technology in the field other than the electrophotographic toner, the following technologies are proposed: i) A pamphlet of International Publication No. WO 02/089998 discloses a technology related to a production apparatus which is equipped with a supersonic gas spraying nozzle for spraying a liquid medium, so as to produce resin particles. ii) U.S. Pat. No. 4,575,325 discloses a technology using a spraying-granulating nozzle for producing metal particles by allowing a gas jet flow (causing an acoustic wave vibration with a toned frequency) to atomize melted metal. iii) U.S. Pat. No. 5,024,695 discloses a technology of atomizing melted metal in which a gas is dissolved by means of compressed air, to thereby produce metal particles or metal alloy particles having pores. U.S. Pat. No. 3,326,467 discloses an acoustic wave spraying nozzle for atomizing a fluid.
Any of the above conventional technologies, however, are for producing particles made of a single material, instead of a plurality of materials such as the electrophotographic toner, and therefore cannot be used, as they are, for the electrophotographic toner production. In other words, any of the above conventional technologies cannot solve the above production issues of the fine-particle toner, especially, productivity issue and energy consumption issue are yet to be solved.
Japanese Patent Application Laid-Open (JP-A) No. 1-182856, JP-A No. 9-146299 and JP-A No. 2000-19775 disclose the following technology: In melting and kneading a plurality of materials constituting the toner, i) a chemical foaming agent is added to the kneaded composition or ii) the chemical foaming agent is dispersed (inner dispersion) in advance in a binder resin, to be followed by adding thereto a temperature. Thereafter, a carbon gas or a nitrogen gas is to be caused for foaming the binder resin, to thereby form a cracked interface cracked by an inner bubble, thus improving a pulverizing efficiency at the next operation.
In the above processes, the chemical foaming agent used include i) inorganics such as hydrogen carbonate of an alkali metal (sodium, potassium, and the like), salt of carbon hydrogen of heavy metal (mercury, cadmium and the like); and ii) organics such as azide compound, azodi carbonamide, diamino benzene, flon 11, flon 12 and the like. Handling the above chemical foaming agents is dangerous, as the case may be, causing environmental pollution. Foaming the above chemical foaming agents may be in need of heating, applying a heat stress, especially, to a low temperature fixing toner which is attracting attention recently. Moreover, the above chemical foaming agents, as they are, may cause a harmful effect on the toner's properties such as physical property, fixing property, and chargeability.
Apart from the toner, JP-A No. 2003-10666 discloses a technology of suppressing discoloration and carbonization caused by heat deterioration at a kneading operation of a thermoplastic resin, so as to foam a binder resin for forming a foamed mold. Specifically, this technology injects and disperses a gasified carbon dioxide in the kneading operation, and thereby causes an inner foaming, thus forming a bubble.
Applying the technology of JP-A No. 2003-10666 to the production of the toner may use inactive gas, which may not cause a harmful effect on the toner's qualities. However, the air into the melted resin is likely to cause an uneven diffusion, thus the ratio of the bubble into the toner resin may become 60 volume % at highest. Summarizing the above, an effect given to the toner's pulverizing property at a latter operation (which effect is expected from the foaming) is intermediate at most, in other words, this effect is not sufficient for pulverizing the fine particles of the toner composition to about 5 μm to 6 μm.
The technology of JP-A No. 2003-10666 is, specifically, for the purpose of producing a foaming material and a foaming composition that have a small bubble by foaming a single polymer material. On the other hand, the toner is a composition containing the binder resin and other materials such as colorant and the like. The kneaded composition made of the plurality of the materials which composition prepared in the toner manufacturing operations is to be pulverized for producing the final object, that is, the toner, and therefore, cannot be used as it is for the electrophotographic toner. With this, the issues arising from the fine-particle toner production is yet to be solved, especially, the productivity issue and the energy consumption issue.
In the above conventional chemical foaming processes, enabling light weight of the foaming resin involves decreased strength, thus limiting usage as a molded part. Concerning this, JP-A No. 2000-19775 discloses a Micro Cellular Foaming (MCF) technology using a supercritical fluid developed by MIT (Massachusetts Institute of Technology). The above MCF technology enables production of a mold resin with minor bubbles (having particle diameter of 5 μm or less) foamed evenly. Moreover, Japanese Patent (JP-B) No. 2,625,576 discloses a technology of producing a foaming material and a foaming plastic composition which have a very small bubble.
Any of the above spraying-granulating technologies, however, are for the purpose of producing a particle that is made of a single material, instead of a plurality of materials as the toner, and therefore cannot be properly used, as they are, for the toner. In other words, the technology disclosed in JP-B No. 2,625,576 cannot be applied to the toner production.
As is disclosed in JP-B No. 2,625,576, forming of bubbles in the kneaded composition having a density of 109/foaming material cm3 or more and an average bubble diameter of 5 μm or less cannot improve drastically the pulverizing property, or cannot improve yield due to ultra-fine particles caused in the pulverization.
In terms of producing toner using a supercritical fluid, JP-A No. 2001-312098 discloses a technology of dissolving a binder resin composition in a supercriticality and then mixing and dispersing colorant compositions in the supercriticality. The above technology, however, does not use the supercriticality for the purpose of carrying out melting or kneading of the toner materials followed by a spraying-granulating with a high pressure.
To date, in the field of toner manufacturing technology, a granulating technology of injecting a supercritical fluid is not combined with a spraying-granulating technology, which combined technology is preferred to be provided as soon as possible.

Toner, process of manufacturing toner, developer, toner container, process cartridge, image forming apparatus, and image forming process


Structures for an optical component of a photonics chip and methods of forming a structure for an optical component of a photonics chip. The structure includes a slotted waveguide component having a first and second waveguide cores over a dielectric layer. The first waveguide core separated from the second waveguide core by a slot. The structure further includes a third waveguide core over the dielectric layer. The third waveguide core is positioned in a different level relative to the dielectric layer than the slotted waveguide component, and the third waveguide core and the first slot have an overlapping arrangement.

The present invention relates to photonics chips and, more specifically, to structures for an optical component of a photonics chip and methods of forming a structure for an optical component of a photonics chip.
Photonics chips are used in many applications and systems including, but not limited to, data communication systems and data computation systems. A photonics chip integrates optical components, such as waveguides, optical switches, optical power splitters, and directional couplers, and electronic components, such as field-effect transistors, into a unified platform. Among other factors, layout area, cost, and operational overhead may be reduced by the integration of both types of components on the same chip.
Silicon-based optical components may suffer from power-dependent loss because, for input optical powers exceeding a certain threshold, the output optical power begins to nonlinearly increase. As a result, silicon-based optical components may be prone to damage induced by high input optical powers. Despite this lack of robustness, a photonics chip requires certain silicon-based active optical components, such as optical modulators.
Improved structures for an optical component of a photonics chip and methods of forming a structure for an optical component of a photonics chip are needed.

Optical components with power-handling assistance


An apparatus includes a current source, an electronic circuit and a circuit board. The current source is configured to flow an electrical current having a selected frequency between a pair of electrodes coupled to a medical probe. The electronic circuit is configured to measure a single-ended voltage relative to ground that is formed on at least one of the electrodes in the pair in response to the electrical current, and, based on the measured voltage, to assess physical contact between the at least one of the electrodes and tissue. The circuit board includes the current source and the electronic circuit, and includes a layout that produces, at the selected frequency, a predefined capacitance between the current source and ground, thus forming a reference for measurement of the single-ended voltage.

In various medical procedures, such as in ablation of heart tissue, a physician needs to know the extent of physical contact between a medical probe and tissue when performing a medical procedure to the tissue. Various techniques for determining proximity and contact are known in the art.
For example, U.S. Patent Application Publication 2016/0143686 describes a method of determining the distance between an electrode catheter disposed in a body fluid adjacent an internal body surface, and the internal body surface, the method includes applying an alternating voltage or an alternating current, determining the impedance between at least one pair of electrodes on the electrode catheter, and determining the distance between the electrode catheter and the internal body surface based at least in part on the determined impedance.
U.S. Patent Application Publication 2016/0287137 describes a method and system for assessing electrode-tissue contact before the delivery of ablation energy. The method includes determining a difference between a maximum impedance magnitude at a low frequency for a given electrode and an absolute minimum impedance magnitude at the low frequency across all electrodes. The method further includes determining a difference between a maximum impedance magnitude at a high frequency for a given electrode and an absolute minimum impedance magnitude at the high frequency across all electrodes, and determining a difference between a maximum impedance phase at the high frequency for a given electrode and an absolute minimum impedance phase at the high frequency across all electrodes.

Assessing tissue contact with catheter using pairs of electrodes and common reference ground established using designed circuit-board capacitance


A system of stem wall foundation blocks is a set of reinforced precast, post-tensioned modular footing and stem wall foundation blocks with a unique interconnecting design optimized for both residential and commercial applications that eliminates the need for on-site manufacturing of a foundation mold. The apparatus provides a unique modular foundation design for a variety of applications within construction. A series of wall blocks of different shapes and arrangements interlock, thus enabling users to modify the dimensions of their foundation mold to a desired purpose. Engineered bolts and lapped connections enable the modular wall pieces to securely connect after they have interlocked. This arrangement enables construction workers to move the interlocking blocks into position and then begin pouring concrete inside to lay the foundation. The reinforced precast, post-tension modular footing, and stem wall foundation blocks are less expensive and more efficient for building and constructing residential and commercial foundations.

The advent of advancements in construction technology and processes has resulted in a corresponding increase in the demand for buildings of all shapes and sizes. Regardless of the type of building, it is common practice to begin construction by laying a foundation of concrete. In order to build such a foundation, the perimeter of the building must be outlined by a temporary border wall, which serves as a mold into which concrete may be poured. This tried-and-true method results in an even, consistently-shaped foundation that is prepared to support a larger structure.
However, the development of the temporary border wall requires a significant amount of time and resources. Each foundation is different depending on the different conditions and requirements set forth by the project. Currently, the best solution to this problem is to manufacture the appropriate foundation block on site and in the appropriate position. This is very time-consuming, not only to measure and execute on the dimensions of the necessary foundation mold, but also in terms of the time cost of failure, as starting over requires removal of the original failed foundation mold. Further, the mold walls must be put under tension, a process which ensures that they will retain their shape as the concrete foundation is poured and hardens, but which also requires additional time and resources to perform. What is needed is a set of modular blocks that are manufactured and assembled appropriately into the appropriate mold wall configuration. Further desirable is a set of building blocks which are already in a post-tension state, thus requiring only the adjustment of the blocks into the appropriate mold shape on the construction site.
The present invention addresses these issues. The system of stem wall foundation blocks is a set of reinforced precast, post-tensioned modular footing and stem wall foundation blocks with unique interconnecting design for residential and commercial application. A series of wall blocks of different shapes and arrangements interlock, thus enabling users to modify the dimensions of their foundation mold to a desired purpose. Engineered bolts and lapped connections enable the modular wall pieces to securely connect after they have interlocked. This arrangement enables construction workers to move the interlocking blocks into position and then begin pouring concrete inside to lay the foundation. The reinforced precast, post-tension modular footing, and stem wall foundation blocks are less expensive and more efficient for building and constructing residential and commercial foundations.

System of engineered post tensioned footing and stem wall foundation blocks