A multi-camera vision system for a vehicle includes first, second and third image capture devices having respective first, second and third fields of view exterior of the vehicle. The first field of view overlaps with the third field of view defining a first overlap zone, and the second field of view overlaps with the third field of view defining a second overlap zone. Responsive to processing of captured image data, a synthesized image is generated without duplication of objects present in the first and second overlap zones and the synthesized image approximates a view as would be seen by a virtual camera at a single location exterior of the vehicle. The synthesized image is displayed by a single display screen that is viewable by a driver of the vehicle and the synthesized image assists the driver in executing a maneuver of the vehicle with a trailer attached thereto.

This invention relates generally to vision systems for vehicles and, more particularly, to rearview vision systems which provide the vehicle operator with scenic information in the direction rearward of the vehicle. More particularly, the invention relates to a rearview vision system utilizing image capture devices, such as CMOS imaging arrays and the like.
A long-felt need in the art of vehicle rearview vision systems is to reduce the amount of time spent gathering information of the condition around the vehicle in order to safely carry out a vehicle maneuver, such as a turn or a lane change. It has been determined that up to about 50 percent of maneuver time is spent gathering information with conventional rearview mirrors. This typically requires viewing one or more mirrors, turning the head and body to check blind spots, and double-checking the mirrors prior to executing the maneuver. Some improvement has been obtained by adjusting mirror optics, for example, to increase the observed field of view rearward of the vehicle. However, this is achieved with an increase in image distortion which makes driver awareness of conditions to the side and rear of the vehicle even more difficult.
Another long-felt need in the art of vehicle rearview vision systems has been to eliminate exterior rearview mirrors by utilizing image capture devices, such as cameras, in combination with dashboard displays. This would be beneficial because it would reduce wind drag on the vehicle, wind noise and vehicle weight. Furthermore, rearview mirrors protrude a substantial distance from the side of the vehicle, which makes maneuvering in tight spaces more difficult. Image capture devices are capable of positioning in a greater variety of locations on the vehicle, providing more flexibility of vehicle styling. It is further expected that camera systems would greatly reduce the blind spots to the sides and rear of the vehicle common with vehicles equipped with conventional rearview mirror systems. The driver cannot perceive vehicles, objects, or other road users in such blind spots without turning his or her body, which interferes with forward-looking visual activities.
Camera-based rearview vision systems for vehicles have not obtained commercial acceptance. One difficulty with proposed systems has been that they present a large amount of visual information in a manner which is difficult to comprehend. This difficulty arises from many factors. In order to significantly reduce blind spots, multiple image capture devices are typically positioned at various locations on the vehicle. The image of an object behind the equipped vehicle is usually captured by more than one image capture device at a time and displayed in multiple images. This may confuse the driver as to whether more than one object is present. When multiple image capture devices are positioned at different longitudinal locations on the vehicle, objects behind the vehicle are at different distances from the image capture devices. This results in different image sizes for the same object. This effect is especially noticeable for laterally extending images, such as a bridge, highway crosswalk markings, the earth's horizon, and the like. Such images are at different vertical angles with respect to the image capture devices. This results in different vertical positions on the display causing the elongated image to appear disjointed.
A camera system provides a monocular view of the scene, compared to the binocular stereoscopic view obtained when the scene is viewed through a rearview mirror. This makes the ability to judge distances in a camera system a problem. This effect is most noticeable at distances close to the vehicle where stereoscopic imaging is relied upon extensively by the driver in judging relative locations of objects. Therefore, known camera systems fail to provide to the driver important information where that information is most needed at small separation distances from surrounding objects.
Another difficulty with camera systems is that, in order to provide a sufficient amount of information, the camera system typically presents the driver with a greatly increased field of view. This improves performance by further reducing blind spots at the side and rear of the vehicle. However, an increased field of view is often obtained by utilizing a wide-angle lens which introduces distortion of the scene and further impairs the ability of the driver to judge distances of objects displayed. The problem with such distortion of the scene is that the driver must concentrate more on the display and take a longer time to interpret and extract the necessary information. This further distracts the driver from the primary visual task of maintaining awareness of vehicles and other objects in the vicinity of the driven vehicle.
Yet an additional difficulty with camera systems is that flat panel displays present the image captured by the rearward-facing image capture device, or devices, at a focal length that approximates the arm length of the vehicle driver. In order to observe the condition of the vehicle utilizing the rearview vision system, the driver must change his or her gaze from the forward field of view of the vehicle to the display. Because the forward field of view of the vehicle is at a focal length that is much greater than the focal length of the displayed image, the eyes of the driver must refocus upon changing gaze. This refocusing further increases the amount of time for the driver to assimilate the information in the displayed image. Furthermore, when the gaze of the driver returns to the forward field of view, the eyes must, again, refocus to the greatly longer distance.
Yet an additional difficulty with camera systems is that of finding adequate space in the crowded area of the vehicle's dashboard for the components making up the display.

Multi-camera vision system for a vehicle


Systems, methods, and non-transitory computer readable media are configured to determine data for subcarriers of a cable modem signal. Values which characterize the cable modem signal can be generated. A plot can then be generated. The plot can depict one or more of the values which characterize the cable modem signal.

Homes and businesses have become increasingly reliant on high-speed access to the Internet. For example, in the past, many homes and businesses used one connection for voice/data connectivity, and another connection for reception of audio/video entertainment. Many of these homes and businesses now use a single high-speed Internet connection for all of these needs. A common way of providing a high-speed Internet connection to a home or business is by using a cable modem.

This patent is subject to a terminal disclaimer.


There is provided a semiconductive ceramic sintered compact that has a conductivity high enough to attain static electricity removal and antistatic purposes and, at the same time, has excellent mechanical properties or stability over time. The semiconductive ceramic sintered compact includes a main phase and a conductive phase, wherein the main phase is a ceramic sintered phase including Al2O3 particles, the area ratio of the conductive phase to the main phase is 0% (exclusive) to 10% (inclusive), and the conductive phase includes two or more metals selected from Mn (manganese), Fe (iron), and Ti (titanium) and has a composition meeting a relation of Mn/(Ti+Mn+Fe)>0.08 or Mn/Ti>0.15.

1. Field of Invention
The present invention relates to a semiconductive ceramic sintered compact that has a conductivity high enough to attain static electricity removal and antistatic purposes and has excellent mechanical properties or stability over time.
2. Background Art
Al2O3, ZrO2, SiC, Si3N4 and the like have been extensively used as structural members for semiconductor manufacturing apparatuses and liquid crystal manufacturing apparatuses by virtue of their excellent mechanical properties, abrasion resistance, and corrosion resistance. In particular, Al2O3 possesses excellent mechanical properties, abrasion resistance, and corrosion resistance and is low in cost and thus has been used in various portions of apparatuses.
An enhanced performance of semiconductor devices and liquid crystal devices in recent years has led to further microminiaturization of these devices, posing troubles of the devices caused by electrostatic discharge (ESD) that occurs in guides or the like during drive of stages in a manufacturing process. Further, static electricity should be rapidly released from around the devices. To meet this demand, ceramics, of which the surface resistivity and the volume resistivity have been lowered by adding conductive substances to alumina that is an insulator, or by using a special sintering method for static electricity removing and antistatic purposes, have hitherto been known (PTLs 1 to 4).
For example, JP 2004-099413 (PTL 4) discloses alumina ceramics that have antihalation and antistatic functions and have a specific rigidity which can maintain a large meter-size mount table with high accuracy. The ceramics include Al2O3 and three metal elements of Mn (manganese), Ti (titanium), and Fe (iron) each added in an amount of not less than 0.5% in terms of oxide to Al2O3, the total amount of the three elements being 2 to 11% in terms of oxide. As long as the present inventors know, the ceramics described in this patent publication leave room for an improvement in properties.


The present invention provides a SCC (Spinning Cone Column) equipped with a foam removal unit comprising: a housing having a rotation axis; a supply part of at least one reactant formed inside of the housing; at least two spinning cones that are installed so as to have a constant gradient from the upper part to the lower part to the rotation axis, move supplied reactants through the reactant supply part, and rotate around the rotation axis; a fixed cone that is fixed and formed on the inner side of the housing, and provides a pathway for sequentially moving reactant from a spinning cone at the upper part to a spinning cone at the lower part; a product collection part for collecting reactants moved through the spinning cone and the fixed cone; and a driving part for rotating the spinning cone, wherein a foam removal unit is installed on one side of the housing. The SCC according to the present invention solves the problems that foam is generated when separating material to be removed to decrease removal yield and lower stability of the product, and may improve removal yield and product stability because a foam removal unit is for removing generated foam is installed.

(a) Field of the Invention
The present invention relates to a SCC (spinning cone column) equipped with a foam removal unit, more particularly to a SCC equipped with a foam removal unit for removing foam generated in the SCC.
(b) Description of the Related Art
In general, to obtain a product through a chemical reaction, a reaction device is required. As the reaction device, a batch reactor where raw product is added to one reactor, and then, a reaction is conducted through agitation, and the like has been generally used. However, according to this method, sufficient reactions are not achieved for a reaction requiring rapid material transfer speed, thus generating a large amount of non-raw product, and if a catalyst is used, a catalyst separation process is required thus increasing a cost as a reactor has large-capacity.
Therefore, Korean Registered Patent No. 961,765 has suggested a spinning disc reactor, but it has a problem in that disc residence time of raw material is short because spinning discs are horizontally arranged, and thus, a spinning cone column (SCC) with improved residence time of raw materials by multistage installation of inclined discs, namely cones has been preferred. Meanwhile, the SCC may be applied for a gas-liquid contacting separation process. In case the SCC is applied for a gas-liquid contacting separation process, foam may be generated to lower stability of reactant and decrease yield in the process of removing material to be removed by contacting, and thus, there is a need to remove the foam.


Disclosed herein is a chemical mechanical polishing (CMP) method for manufacturing a semiconductor device, comprising performing partial ion implantation of dopants at different concentrations into a plurality of at least two divided regions of a wafer having a planarization-target film, and subjecting the partially ion implanted-wafer to a chemical mechanical polishing process. In accordance with the present invention, non-uniformity of the removal rate in a chemical mechanical polishing process is countervailed by dopants which are implanted at different concentrations via partial ion implantation, and thereby it is possible to polish the target film at a uniform removal rate.

1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a chemical mechanical polishing method for manufacturing a semiconductor device.
2. Description of the Related Art
Recently, with the increased degree of integration of semiconductor devices and introduction of various materials, the importance of planarization processes has increased. Among such processes, mechanical polishing results in the formation of deformed layers, causing product defects, while chemical polishing does not cause the formation of such deformed layers, it has a limitation in that precise flatness cannot be achieved. As such, chemical mechanical polishing (CMP) is primarily employed which has the advantages of both chemical and mechanical polishing methods.
In such a chemical mechanical polishing method, a wafer having a polishing-target film is polished by a pad and slurry. A polishing table, to which the pad is attached, is rotated, while a head part of the polishing table simultaneously rotates and fluctuates and applies given pressure to a wafer. The wafer is mounted on the head part of the polishing table by surface tension or a vacuum. Self-load of the head part and pressure applied thereto results in contact between the pad and wafer surface, and slurry flows through minute interstices defined between interfaces thereof, i.e., pores of the pad. Consequently, mechanical removing action is effected by slurry-constituting polishing particles and surface protrusions of the pad and at the same time, chemical removal is also affected by chemical components in the slurry.
Upon performing a planarization process via use of chemical mechanical polishing, a removal rate, which refers to the ratio of film material to be removed, is unfortunately non-uniform depending upon changes in the position of wafer. For example, when the wafer is planarized by removing a polysilicon film to a predetermined thickness or the planarization process of the wafer is performed until the film materials beneath the polysilicon film are exposed, the removal rate of polysilicon film varies depending upon the position of wafer. As a result, over-polishing beyond a conventional removal amount is caused and thereby a great deal of problems may occur in subsequent processes.
FIG. 1 is a view illustrating distribution of a removal amount of a polishing-target film with respect to the position of a wafer, in a general chemical mechanical polishing method.
As shown in FIG. 1, when comparing respective removal amounts at a central part and edge of a wafer 100 after a chemical mechanical polishing process was carried out on the polysilicon film, it can be seen that the removal rate at the edge of the wafer 100 is higher than at the central part of the wafer 100. That is, the rate at which the polysilicon film is removed at the edge of the wafer 100 is higher than the rate at which the polysilicon film is removed at the central part of the wafer 100. Consequently, over-polishing occurs at the edge of the wafer 100, or insufficient polishing is put into effect at the central part of the wafer 100.
FIG. 2 is a view showing state distribution of chips in a wafer to which a conventional chemical mechanical polishing method is applied.
As shown in FIG. 2, according to an image obtained from examination of the wafer to which the conventional chemical mechanical polishing method was applied, a central part of a wafer 200 is bright, while the edge of the wafer 200 is dark. These results denote a high probability of occurrence of defective chips at the edge of the wafer 200. One of causes responsible for the occurrence of such defective chips is non-uniformity of the target film removal rate in a chemical mechanical polishing process. As such, it is readily seen that the total yield of products may be reduced due to the non-uniform removal rate exhibited by the conventional chemical mechanical polishing method.

Chemical mechanical polishing method for manufacturing semiconductor device


A power transmission device includes a clutch that transmits power from a motor to an axle; a first pump that is driven by power from the motor to generate and output fluid pressure; a second pump that receives and is driven by a supply of electric power to generate and output fluid pressure; a pressure regulating valve that functions as a linear solenoid valve and is formed with an input port, an output port that is connected to the clutch, and a drain port; and a switching valve that switches between a first connection state.

The present invention relates to a power transmission device that is installed in a vehicle and provided with a clutch that transmits power from a motor to an axle, and a vehicle having the power transmission device.
This type of power transmission device conventionally has a first hydraulic pump (mechanical oil pump) that drives based on power from an engine; a manual shift valve that operates in association with a shift operation; a solenoid valve whose input port is connected to the first hydraulic pump through the manual shift valve; a selector valve that is interposed between oil passages and formed as a two-position electromagnetic valve (and includes a check valve), wherein at a first position the selector valve communicates with an oil passage that is interposed between and connects an output port of the solenoid valve to a friction engaging device (clutch) and at a second position the selector valve cuts off this oil passage; and a second hydraulic pump (electromagnetic pump) that directly delivers discharge pressure to the clutch. (See Japanese Patent Application Publication No. JP-A-2008-180303 for an example.)

Power transmission device and vehicle having the same


In a fluid pressure cylinder with a magnetostriction type position detecting device for detecting an operating position of a piston using the position detecting device, the fluid pressure cylinder is provided with a simple and rational design structure without providing it with a special conductive member as a current feedback conductor. In the fluid pressure cylinder with the magnetostriction type position detecting device having a permanent magnet attached to the piston and a magnetostrictive line accommodated in a hollow portion of a cylinder tube, the cylinder tube is formed of a non-magnetic conductive material, the magnetostrictive line composed of a ferromagnetic material is inserted into the hollow portion, and the extreme end of the magnetostrictive line is electrically connected to the cylinder tube through a support metal fitting, thereby the cylinder tube is also used as a current feedback conductor.

A patent document 1 discloses a technology for detecting an operating position of a piston of a fluid pressure cylinder using a magnetostriction type position detecting device. The position detecting device detects a position of a permanent magnet by using a magnetostrictive line composed of a ferromagnetic material and the permanent magnet, generating ultrasonic oscillation to the magnetostrictive line at a position corresponding to the permanent magnet by the mutual action between a magnetic field generated when a current pulse flows to the elastic layer and a magnetic field generated by the permanent magnet, and detecting the ultrasonic oscillation traveling in the magnetostrictive line by a receive coil (detection coil). Then, an operating position in the entire stroke of the piston is detected by attaching the permanent magnet to the piston and the magnetostrictive line to a cylinder tube.
Incidentally, in the technology disclosed in the patent document 1, the position detecting device has a metal probe in which the magnetostrictive line is accommodated, and the probe is fitted into a groove of the cylinder tube composed of aluminum alloy and the like in an electrically insulated state. That is, the probe is formed by inserting the magnetostrictive line into a cylindrical pipe composed of a conductive material such as metal and the like, electrically connecting the extreme end of the magnetostrictive line to the extreme end of the cylindrical pipe, and disposing the detection coil to the base end of the cylindrical pipe. The outer periphery of the probe is covered with an insulation tube, and the probe is fitted into the groove of the cylinder tube in the electrically insulated state through the insulation tube. Then, the cylindrical pipe functions as a feedback conductor of the current pulse supplied to the magnetostrictive line. Patent Document 1: Japanese Unexamined Patent Application Publication No. 9-329409

Fluid pressure cylinder with position detecting device


A chamber for reducing operating noise of a purge control solenoid valve (PCSV) for an evaporative emission control system comprises a first housing into which operating noise of the PCSV enters. The first housing has an inner space to change a cross sectional area of an operating noise path or an operating noise transfer direction at least once. A second housing has an upper portion coupled to a lower portion of the first housing to transfer the operating noise outside. At least one end of the chamber in a length direction thereof is connected with a vapor hose which connects a canister collecting fuel evaporation gas generated from a fuel tank with the PCSV to deliver the fuel evaporation gas to an engine and through which the fuel evaporation gas flows.

A vehicle has an emission control system in which a purge control solenoid valve (PCSV) is installed between an intake manifold and a canister to control fuel evaporation gas collected at the canister.
The canister collects the fuel evaporation gas to flow into a surge tank through the PCSV that is controlled by an engine control unit (ECU) which receives information from sensors, such as a coolant temperature sensor, an oxygen sensor, etc.
Then, the fuel evaporation gas, which is detrimental, is combusted and prevented from being discharged into the atmosphere.
The PCSV can be classified into a duty control type PCSV which is controlled by the ECU and an on/off control type PCSV which is controlled by negative pressure of an intake manifold and the ECU, and the PCSV is generally closed under low coolant temperature or engine idling.
When an engine operates in a normal temperature range, the PCSV is opened and the fuel evaporation gas collected at the canister flows through a vapor hose into the intake manifold to be combusted.
Whenever the PCSV is opened and closed by an actuator, operating noise is generated and transferred in the reverse direction to an inflow direction of the fuel evaporation gas through the vapor hose which connects the PCSV and the canister.
Further, pulsation noise is generated due to pulsating of the fuel evaporation gas passing through the PCSV and transferred through the vapor hose in the reverse direction to a pulsating direction.
In general, the operating noise of the PCSV and the pulsation noise transfer to a driver's seat through the vapor hose because the vapor hose connects the canister and the PCSV and transfers the noise to a dash panel disposed in front of the driver's seat.
Thus, during engine idling and driving at a low speed, noises are generated.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore, it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Chamber for reducing operating noise of purge control solenoid valve for evaporative emission control system


Disclosed are what I call “Reconfigurable Tactile Control Displays” particularly suited for applications such as automobile instrument panels where large displays and controls are desirable to provide a wide range of information, with minimal driver distraction and the safe input of data to vehicle subsystems or for communication based activities. Preferred embodiments utilize rear projection displays with electro-optically sensed controls and offer, at low cost, a maximum of reconfigurability to different car lines, drivers, and tasks. Also disclosed are novel implementations for military vehicles, and other applications such as control of appliances, heating and other household functions which may share common control and display presentation with those used in the vehicle.

The Automobile Dashboard or Instrument Panel (IP) as we know it today has evolved in the last 60 years or so, into a combination of control details such as knobs, switches, and sliders for actuation and selection of functions, together with analog or digital displays and light based tell-tales for communication of information to the driver. The actual provision of such components is governed in the USA by FMVSS (Federal Motor Vehicle Safety Standard) 101: Controls and Displays. In general, this standard specifies overall ground rules for the more critical functions operated by hand by the driver, leaving non-critical functions such as entertainment to the option of the manufacturer. Even some non-critical controls however, are specified as to their design goals, to avoid driver confusion. A particular stipulation of FMVSS 101 states that the Labelling (written or pictograph) for controls must be on or adjacent the control.
The Vehicle Instrument Panel is constrained as to available space for the instrumentation and control functions. Controls used by the driver cannot be so high as to obscure the drivers vision, or too low so as to require too much angular diversion of ones line of sight while in motion (the SAE guideline is 30 degrees max from normal line of sight out the windshield).
In a right—left, or cross-car context, the hand operated controls cannot be significantly behind the steering wheel used in present day vehicles, or too far to reach over to the passenger side by even the smallest driver using them.
In order to achieve added functionality made possible by modern electronics while at the same time reducing the ever increasing clutter of further controls required to achieve even present day functions, there is a big incentive to develop Instrument Panels which can fit in the available instrument panel space yet be reconfigured to serve multiple purposes, always with safe operation paramount. In particular, there is a need to provide such IP's which can not only be used on less critical control and informational functions, but for primary control functions as well, reducing cost and complexity and increasing justification.
Examples of prior art directed at some aspects of the problem are:
U.S. Pat. No. 6,246,935 by Buckley, Jun. 12, 2001 Vehicle instrument panel computer interface and display;
U.S. Pat. No. 6,344,793 Process for assisting a user of a motor vehicle . . . , Geck et al, assigned to Daimlerchrysler;
U.S. Pat. No. 5,757,268 Toffolo, et al. May 26, 1998 Prioritization of vehicle display features (on a reconfigurable display), assigned to Lear Corporation;
U.S. Pat. No. 6,373,472, Driver Control interface System, Palalau et al, assigned to Lear Corporation;
U.S. Pat. No. 5,539,429 Yano, et al. Jul. 23, 1996 Touch device panel, assigned to Mitsubishi;
U.S. Pat. No. 6,067,081 Hahlganss, et al. Method for producing tactile markings on an input surface and system for carrying out of the method, assigned to VDO;
U.S. Pat. No. 5,956,016 Kuenzner et al Operating device for Menu controlled functions of vehicle, Assigned to BMW;
U.S. patent application Ser. No. 09/963,565 Apr. 4, 2002 by Hirose, et al. Display device with screen having curved surface, assigned to Nissan;
PCT Patent application PCT/GB99/04006, Touch Sensitive Switch, Butler et al, assigned to Ford Motor Co.;
US pat app Kind Code 20020002432 Bockmann et al. filed Jan. 3, 2002 assigned to Volkswagen. Automobile multifunctional display and control device method;
In terms of the control of the vehicle, there are basically three major components (not including foot based controls).
Data Displays by instruments either analog or digital, and accessories. Vehicle data is generally speed, fuel level, engine rpm, battery charge, etc. Some of these are rapidly varying (e.g. RPM) others slow (eg. fuel). Some are more important than others.
Hand operated controls, generally today in the form of knobs, switches, sliders, levers and dials. Switches and knobs are most common today it seems. Most are located on the instrument panel, but some are on stalks protruding from the steering column, and window and seat controls and outside mirror controls can most often be found on the doors, or seats. Some controls (such as cruise control, auxiliary radio controls etc) can be found on the steering wheel in many vehicles.
Control labeling, today nearly universally achieved with printed data (language or pictograph) on or adjacent the control, to comply with FMVSS 101. In several cases, the data cannot rotate with the knob.
Modern technology has the ability to greatly expand the amount of data which can be provided, as long as the means exists to display it safely (legibility, position, etc). However, the means to interact with the data, if required or desirable has to be present in the controls, which at the same time need to comply with regulations. The steering wheel, which is a logical place for more control functions, is pretty much constrained today in this regard by the presence of the airbag, and the requirement for slip rings or other complex wiring
Central to the issue, is the question of just how the driver uses the controls?. I have observed that a driver of a vehicle today, interacts with the controls of the vehicle instrument panel, primarily in three ways:
By sight only;
By touch/feel only (possibly accompanied by a sound, such as a click-usually corresponding to a feeling sensation such as provided by a detent;
By a quick glance, and then touch—possibly followed by another quick glance to check a further or final setting of a knob, slider control, etc.
Feedback as to correctness of the action taken, if not obvious from sight or feel of the controls, is often times derived from the action of the device controlled itself, for example seeing and hearing the windshield wipers moving at high speed, when they were moving at low speed at a previous control setting.
Often while driving, only methods 2 and 3 above can be effected, as the control details may be too small to read or operate (radio function buttons are notorious) and/or require too much concentration (i.e. too many glances at the controls and their lettering, pictographs, and position) while driving to allow one to take ones eyes off the road for the time required to use sight only. Accordingly, for many users today, some functions are effectively inoperable while driving, since they cannot be worked by touch only due to the crowded nature of their placement, and they are too hard to see in a glance—especially for those who cannot easily correct their vision away from the far sighted vision needed to drive.
It should be noted that certain technical papers indicate that single glances of more than 2 seconds duration are considered unsafe, and some traffic safety researchers feel the limit to do any control activity should be just a few glances of no more than 1.2 sec. each. These studies indicate in considerable detail that excessive glance time can be related to ten's of thousands of deaths per year in the USA alone.
The new Auto Industry guide lines for "Glance time" suggest that control of the vehicle function should not require one to take ones eyes off the road for than 2 sec max, and no more than 10 glances (of 1-2 sec. ea) should be required to complete the operation in question. (while seemingly are a large number, some navigation tasks in certain vehicles have historically taken considerably more than this). This would seem the minimum stipulation one could possibly recommend in light of the suggestions in many technical papers. And it suggests that indeed there is considerable room for improvement to not only the situation today, but even what is being contemplated.
Not only are there problems seeing or touching small complex controls, some controls are not intuitive, and hard for the general public to understand in the manual, even if one has time to read and comprehend it. This manual comprehension problem is increased considerably, for those buying more expensive vehicles on short term leases. These vehicles are in addition, usually the ones with the most features, (and generally therefore the smallest buttons, due to instrument panel congestion), and many persons seldom take the time to fully digest the manual. (Some manuals today for feature oriented luxury cars are several hundred pages long !)
Generally a few functions, such as turn signal stalks, transmission levers, and some knobs are big enough and/or simple enough such that only touch is needed, combined with feedback from sensing the physical action enabled (e.g. wipers switched to high speed). Thus after some acquaintance period, most vehicles enable the driver to perform the basic functions by touch alone, or just a reasonably quick glance and then touch. However, this often applies only to basic operations, given the learning curve involved and the difficulty in operation of added features, such as complex HVAC (heating ventilation and air conditioning) systems, navigation systems, and "infotainment" devices.
The present situation thus greatly constrains the addition of still further vehicle related functions, made possible by computing, electronics and communication technology. Heretofore, the addition of such functions in some cases has been distracting to the driver and thus dangerous to the public. With fixed instrument panel space, much of which is taken up by airbags, glove compartments and the like, manufacturers have resorted to the above mentioned expedient of ever smaller and more complex controls in the remaining space, in order to gain functionality. Many are in addition located out of the drivers normal line of sight, and some even require one to stare at changing numbers in an awkward location. Others require reading very small print (often impossible for those requiring reading glasses while driving—a real dilemma for many drivers over middle age particularly).
Of late, many have shown interest in "Voice Recognition" as an answer to such problems, and increasing numbers of vehicles such as the Infiniti Q45 and Jaguar "S" model, have such incorporated. Using ones voice (and the listening to computer voiced data streams) in theory could reduce the need for glancing at all.
However, voice recognition has many problems. For example, to be useful, vocal prompts for the driver are often needed, which can be time consuming, frustrating, and difficult to hear. Undue concentration on same can also cause unsafe driving, and masks the presence of sirens. In addition, voice is both linear, and sequential. Only one message/action can be executed at once, and generally needs to follow a previous one. And the whole message has to be understood by the driver, or data can be lost and the process required to be repeated, which can cause driver frustration and endanger safety in extreme circumstances.
I have felt for some time that voice is not the answer. A recent study by Dr. Ben Shneiderman at the Human Computer Interaction Lab at the University of Maryland reported in The Washington Post, Thursday May 9, 2002, noted that voice commands also require much more precious brain activity than visual "eye-hand" tasks. Thus voice cannot be good for driving safely. The Instant invention however, maximizes the efficiency of such Eye-hand tasks, making them familiar and easy to see and act upon.
Voice aside, perhaps the only way more data can be presented to, or received from, the driver is through the use of specialized displays and entry devices which can be reconfigured to suit the need of the user at the instant of use. Such displays are commonplace today in the computer world (e.g. "Windows", "Web Browsers"), so why not in a car?
Some companies have proposed or developed conventional reconfigurable computer "windows" type systems using up/down/left/right buttons or even joysticks to select the various software presented screens and menus thereon in an attempt to solve this problem. Such devices are however, not intuitive and hard to use, for at least 95% of the populace I feel. Because of such problems, even where implemented, they have been relegated to non-critical functions, such as navigation, climate control, cell phone dialing or audio system entertainment. And even here, they are intrinsically unsafe in many manifestations. There is little or no tactile feel, and too much reliance on consecutive visual recognition of displayed items—which in addition are often small in size, as noted above.
Problems with computer displays of the multiple windows type used in vehicles, are discussed in U.S. Pat. No. 5,995,104 by Kataoka, aimed at a Navigation system. Some opportunities available with computer based data presentation in visual and multimedia form are discussed in Obradovich, et al U.S. Pat. No. 6,009,355.
It should also be noted that the lack of natural intuitive tactile feel further makes such menu driven "pure computer screen" type systems slower to operate and constantly requiring visual concentration. This is an issue when the control system is used for any time-critical tasks and has obvious safety connotations.
This is not just true in cars, but in other stressful situations as well, for example in military vehicles, construction equipment, and control of home appliances by a harried housewife in the kitchen.
Another approach to reconfigurability is a touch screen, which is widely regarded as one of the most intuitive of computer interfaces. To my knowledge, the application of touch screens for computer input in automobiles was first achieved in the 1988, in the General Motors Buick Riviera using a relatively small CRT display located in the center stack, in a relatively low position. Such a display is described in U.S. Pat. No. 4,787,040 by Ames, et al. entitled Display system for Automotive Vehicle issued to IBM Corporation Nov. 22, 1988.
However, widespread employment of such touch screens has historically has been limited because it cannot be operated by feel, and requires of a driver more than a quick glance to operate successfully. This is in part I believe because there is nothing on a conventional touch screen to reference ones self to, except the displayed data itself—which then has to be continually read.
To combat this problem (experienced in the early Buick display and others), some vehicles such as the Cadillac CTS have incorporated ordinary non-touch screen LCD displays, with buttons and other conventional touch type controls around the periphery thereof to effect reconfigurable operation in conjunction with icons displayed on the screen nearby (and thus to a degree meet FMVSS 101). Taking this a step further, the Denso Company has worked with Jaguar to introduce a touch screen of the LCD type in the their X model. It has a small 7 inch screen, also surrounded by conventional buttons and touch controls, and located in the center stack. But the display itself has no reference and no feel, and the surrounding buttons are, as in many other examples, small and hard to read. Thus the fact that certain touch icon functions on the screen are reconfigurable is only a small improvement on the previous and prevailing situation.
Another example of a touch type data entry device is that of U.S. Pat. No. 6,067,081 by Hahiganss, et al., assigned to VDO corporation of Germany, an Automotive parts manufacturer. This is a device providing programmable sensations, which can be used in conjunction with a display screen, though there is no teaching that the touch is of the display screen itself, desirable for intuitive interaction. Thus the Hahiganss et al invention would seem not to comply with FMVSS 101.
Palalau et al, U.S. Pat. No. 6,373,472 includes switches on the steering wheel with a heads up display on the windshield. This is a novel approach which offers many advantages, but requires added cost and complexity, and a departure from the customary vehicle operation that drivers are used to. In addition it could be dangerous in some cases as the more fumbling with the wheel that occurs, the more the possibility of changing vehicle direction as a result. And too, the wheel, with its airbag and rotary motion, severely limits the amount of sophistication one can put in the controls thereon.
A recently published PCT application PCT/GB99/04006 by Butler et al of Ford motor company illustrates a multifunctional switching device for the operator to use whose groove aspect which bears some similarity to certain tactile groove aspects of the invention, though it is neither a touch screen nor reconfigurable per se. Like some embodiments of the instant invention, it can provide data only when needed by the user ("secret until lit" feature), but it cannot be reconfigured as to what this data is.
An alternative control device for a car having sensations of feel is a force feedback joystick coupled with a conventional (and programmably reconfigurable) display, such as an LCD based display, on the instrument panel. One example, called "I-Drive", has been introduced by BMW in its 7 series car and appears to be disclosed at least in part in U.S. Pat. No. 5,956,016 of Kuenzner et al of BMW and in U.S. Pat. No. 6,154,201 assigned to Immersion Corporation, which describes various force feedback of a conventional type to a knob useful for automotive or other use. This has some similarity to certain "programmable feel" related aspects of the present invention and its predecessors, even though the knob disclosed is not located on the screen, nor inter-related with touch characteristics of the screen as is the instant invention.
As a general comment, I-Drive does not appear to be intuitive to use, and has received considerable criticism in the Automotive press (see for example, Road and Track, issue of May 2) The manufacturer must have realized this, as in the 7 series manifestation at least, many of the functions are backed up with conventional controls. as well, thus adding cost. This also may be because the FMVSS 101 regulations require the markings of a control to be on or adjacent the control, and the joystick device by itself cannot meet this criteria.
If one can provide a reconfigurable instrument panel that can be safely used, then U.S. Pat. No. 5,757,268 Toffolo, et al. (referenced above) gives a good description of some of the opportunities available in optimizing the presentation of displays and the information provided. Toffolo however, is focused on a conventional display screen approach and is generally limited relative to the display size, two areas over come by the instant invention. And Toffolo does not address several control areas of considerable importance, such as designation or confirmation by the driver of data, or the overriding of important controls (e.g. speedometer) by visual or other data in the case of emergency situations.
Finally there are many projects around the globe aimed at sensory equipped intelligent vehicles and highway systems. Representative patent applications in this area are Ser. Nos. 09/963,490 Road lane marker recognition by Furusho et al, and 09/951,499 Lane recognition apparatus for vehicle, Shirato et al, both of which are assigned to Nissan, and utilize TV camera and machine vision technology to help guide a car such that it stays within lanes. Some of this technology however is very difficult to perfect in a full automatic mode. I know of no reference which has addressed the issue of manual assist to such systems, provided in a large screen tactile control and display device of the type disclosed herein.
To conclude, no prior art reconfigurable instrument panels known to me provide any feel on a display screen itself, as to where on the screen the users finger is, nor do they provide a method for tactilely signalling information back to the user data which would make reliance on long and dangerous glances unnecessary
In addition, no prior art instrument panel uses common knobs and other selection and control details familiar to the driving public of today which can be reconfigured either physically or in terms of their displayed function, data or other variables in a manner that appears to intrinsically comply with FMVSS 101.
Furthermore, no prior art instrument panel I am aware of provides means for safely displaying real time or down loaded video data to the driver in a large enough to easily to see in a cost effective manner, vital for observation of critical events inside and outside the vehicle, as well as to make downloaded information from remote sources easy to see at a glance. And in the same vein, no known instrument panel is capable of providing large lettering for all necessary controls to aid the elderly or vision impaired driver.
And in the same vein, no prior art reconfigurable instrument panel to my knowledge, and even many controls of conventional IP's, do not utilize controls which can easily be "hit" or otherwise actuated, with just a helping glance or by feel alone. And, no prior art teaches incorporation of both knobs or other control details and tactile touch functions on an instrument panel to allow one to optimally execute functions in concert.
In addition to the prior art referenced above, there are a series of related US patents by Denny Jaeger, some of which are in conjunction with Kenneth Twain (eg U.S. Pat. Nos. 5,572,239, 5,841,428, 6,326,936) which relate to techniques for implementing control devices such as knobs and switches on flat panel displays (electroluminescent or LCD) to achieve the benefits of controls function reconfiguration. The approach taken however, results in complex (and expensive) systems which, while programmable as to the display, do not facilitate interchange of the physical components. In many embodiments too, they require significant optical compromises in the display (such as blank spots) and the flat panels used require specialized busbars removing these displays from the mainstream activity. In some cases, intolerable leakage problems can occur as the LCD liquid crystal material can leak around the knob shafts for example.
To solve the problems encountered, some embodiments (of the many shown) of Jaeger and Jaeger et al., have attempted to use optical techniques to shoot through the screen so to speak. In the earliest example, a detector and source for each device such as a knob or switch, is located and attached to the other side of the display. It is positioned to shoot through either a specialized transparent busbar or a bus bar routing hole specially created in the display. This can work presumably, but is complex and expensive, and would appear to use up valuable display space, as well as requiring a device dedicated and positioned to operate each physical control. In LCDs requiring separate specialized backlight sources for their operation, such sensing devices would appear impractical, as they would block the radiation from the backlight.
Where optical sensing is employed in later patents by Jaeger and Jaeger et al, these inventors have apparently focused on having the sensing device (eg a phototransistor) on the front of the display, located on a member attached to the screen in some way. Either the light source is also on the front, or light from the display is programmed to interrogate the position of the sensor on the knob which senses this activity. The inventors also have disclosed sensors of this type which are largely incremental, rather than absolute, which limits some control regimes and can cause errors. Additionally, Jaeger has disclosed a small LCD device electrically placed on the front of a knob or button and controlled to change information thereon, an approach which requires specialized wiring and LCDs for every physical control detail used.
Finally, Jaegers invention are specific to flat panel displays and cannot provide curved or irregular display capability of maximum utility and style for Automobile instrument panels, and teach little or no ability to use materials other than glass as the display surface, also a requirement in vehicles (for passive safety and other reasons), especially as the displays grow in size.
The instant invention solves all of these problems, by using an electro-optical detection means, typically an inexpensive TV camera, to sense, typically from the rear of a rear projection display of nearly any material and shape, more than one physical detail and its position, and generally its absolute position as well. And it can operate on any desired combination of physical control details (such as knobs sliders etc) with only a software change. This then enables the complete interchange of the display and control surface, including any control details such as knobs, which are simple passive devices with no wires needed. In addition, the invention herein, unlike the prior art, allows an integrated touch screen capability to be provided which can be completely integrated with the physical control capability, in some cases even at no added manufacturing cost. The Instant invention is thus arguably of higher performance, simpler to maintain, and lower in cost—especially critical for high volume applications such as automobiles.


A Flash Memory Unit comprises a plurality of memory banks capable of simultaneously programming a plurality of pages into a plurality of data blocks within the respective memory banks. On start up, the Flash Memory System sends a signal to a Host. If the Host fails to respond, the Flash Memory Unit determines that the Host is a standard Host and stores data one page at a time. If the Host responds with a proper signal, the Flash Memory Unit determines that the Host is a high performance Host and stores multiple pages of data simultaneously. The high performance Host is configured to select identical LBA offsets from a plurality of Virtual Logical Blocks of User Data, and send the data defined by these Logical Block Addresses to the Flash Memory Unit for storage. The plurality of Logical Blocks of data are respectively transmitted to a plurality of RAM Data Registers, and simultaneously programmed into their respective memory banks. In sequential steps of programming, data defined by consecutive Logical Block Addresses are stored in Physical Pages defined by consecutive Physical Block Addresses. Data stored by a high performance Host is therefore retrievable by a standard Host.

The present invention relates to the field of Flash Memory Systems. More particularly, the present invention relates to Flash Memory Systems interfacing with Host Systems.
Flash memory technology is an electrically rewritable nonvolatile digital memory medium. Being non-volatile, it does not require a sustained voltage to retain digital data within its memory. A flash memory cell typically stores charge on a floating gate to represent a first logic state in the binary state system, while the lack of stored charge represents a second logic state in the binary state system. Flash memory cells typically support a write operation, a read operation, and an erase operation.
As flash memory technology has advanced, a variety of applications has become possible. In particular, flash memory implementations that emulate the mass storage function of conventional rotating magnetic media, e.g., a hard disk drive or a floppy disk drive, coupled to a host computer system or other host digital system have gained wide acceptance. Hard disk drives and floppy disk drives suffer several deficiencies which are not shared by flash memory technology. First, hard disk drives and floppy disk drives have many moving parts, e.g. an electrical motor, a spindle shaft, a read/write head, and a magnetizable rotating disk. These components give rise to reliability problems and magnify the hard disk drive""s and floppy disk drive""s susceptibility to failure resulting from the vibration and shock of being dropped or bumped. Secondly, a motor driven disk drive consumes a significant amount of power, substantially shortening the operational time between battery chargings. Finally, accessing data stored in the hard disk drive or the floppy disk is a relatively slow process.
In contrast, a Flash Memory System possesses many advantages over rotating storage disks. The typical Flash Memory System has no moving parts, accounting for the higher reliability of the typical Flash Memory System. In addition, the rugged design of the typical Flash Memory System withstands environmental conditions and physical mishandling that would otherwise be catastrophic to the hard disk drive or the floppy disk drive. Generally, a user can access data stored in the typical Flash Memory System fairly quickly. Finally, the power consumption of the typical Flash Memory System is considerably lower than the hard disk drive""s and the floppy disk drive""s power consumption.
Because of the market saturation and universal application of rotating media such as hard disk drives, even a superior process or device seeking to capture a share of the market must be compatible with existing software and operating systems. To achieve compatibility with systems configured to store data within legacy rotating mass storage systems, flash memory is typically broken up into a series of data fields capable of storing five hundred twelve bytes of user data and sixteen bytes of overhead data, thereby emulating the size of a data field typically available in commercial hard disks. FIG. 1 depicts a non-volatile memory array within a flash memory device. A collection of Physical Sectors or Pages 108, . . . 112 are typically capable of storing of five hundred twelve bytes of user data plus sixteen bytes of overhead data per Page, thereby conforming to the storage capacity of a sector of a typical rotating storage device. A plurality of Physical Pages 108, . . . , 112, typically sixteen or thirty two Pages, comprise a Physical Data Block 102.
According to the prior art, a Flash Memory System has been comprised of a single memory structure 100 comprising a plurality of Physical Data Blocks 102, . . . 106. Each data Physical Data Block 102, . . . , 106 is uniquely assigned a Virtual Physical Block Address (VPBA), for identifying and distinguishing a plurality of Physical Data Blocks comprising a Flash Memory System. Usually, each data block 102, . . . , 106 is selectively programmable and erasable.
FIG. 2 illustrates one embodiment of flash memory architecture according to the prior art. A Host 215, such as a computer or digital camera, transmits and receives data to a removable flash memory card 201. During transmission from the Host to the Flash Memory System, the Host assigns logical block addresses to the data. When retrieving the data, the Host requests data according to the logical block addresses which it previously assigned. The data enters a host interface circuit 203 of the flash memory Controller 202, by means of a host interface bus 220, typically comprising parallel bus architecture. The host interface circuit controls the storage of incoming data by means of a RAM Data Buffer 204. When a predetermined amount of data has been stored within the RAM Data Buffer 204, the memory interface circuit 205 transmits data through a memory bus 230 to the non-volatile Flash Memory Unit 206, which was disclosed in greater detail according to FIG. 1. Typically the data bus 230 is a parallel bus structure. The size of the data buffer 204 is advantageously designed to store an amount of data equal to a multiple of some non volatile memory field, such as a page comprising approximately five hundred twenty eight total bytes of data, depicted in FIG. 1.
At the present state of technology, a Flash Memory System has a limited number of program cycles before xe2x80x9cwearing out.xe2x80x9d To ameliorate the problem of wearing-out, a controller discussed in greater detail in FIG. 2 attempts to cycle through the available memory locations before returning to the first location. By regulating the rate of wear among cells, the controller prevents uneven wear focusing on one area of the Flash Memory System. As a consequence of wear-leveling programs, all the cells within a Flash Memory System will therefore typically wear-out at the same rate. The wear-leveling program therefore reduces the likelihood that the Flash Memory System will experience premature degradation within a localized memory area due to overuse of one area. The entire Flash Memory System therefore remains uniformly reliable through its life. A hard disk drive does not require this wear leveling feature because its storage mechanisms can undergo a practically unlimited number of program/write operations without degrading performance. This contrast results in an operational disparity between the addressing system used within a flash memory, and that used within a hard drive or floppy disk.
In both hard drives and Flash Memory Systems, the physical addresses assigned within a memory typically follow a geometric structure within the memory system. That is, physical addresses will typically increment through successive memory locations. When User Data is received by a memory system, whether Flash Memory or rotating disk, a Host system normally assigns an address to incoming data. In a hard drive, data is typically stored in the sector whose physical address matches the logical address defined by the Host System. If a Host system updates User Data previously defined by a specific logical address, the new data will overwrite the original data at the prescribed address.
In a Flash Memory System, however, as a result of cycling through various areas of a flash memory according to a wear-leveling algorithm, physical areas defined by new physical addresses are continually filled. When a Host system updates User Data defined by a specific logical address and sends it to the Flash Memory System, the wear-leveling program will assign the incoming User Data to a physical location unrelated to the physical location in which User Data of the same logical address had previously been stored. Old data associated with a particular logical address is not immediately overwritten by incoming data of the same logical address. The old data is simply obsoleted, and the incoming data is written into the next available Physical Data Block, that is, the next addressable Physical Data Block that is free and non-defective. As a result, the Host assigns addresses to data that bear no relationship to the addresses where the flash memory ultimately stores the data. A distinctive characteristic of the wear-leveling data storage program implemented by the typical Flash Memory System therefore lies in the continuously changing relation between the logical addresses assigned by the Host, and the physical addresses actually used by the Flash Memory System. Through this dual memory process, a Flash Memory System is able to functionally emulate the relationship between a hard drive and a Host with respect to data storage and retrieval, thereby maintaining compatibility with existing software.
FIG. 3 illustrates various registers and fields used to take incoming data and store it within the Flash Memory Unit 206 (FIG. 2). In order to facilitate retrieval of User Data stored by a Host System, however, a correlation of logical and physical addresses must exist. This correlation is typically stored within the Flash Memory System, in the overhead portions of each page 108, . . . 112, and in the RAM Space Manager 370. When a Host transmits User Data 310, . . . , 316 identified by a set of logical addresses 302, . . . , 308 to a Flash Memory System, the Flash Memory System stores the data in certain physical locations 322, . . . 328 and then correlates the logical 302, . . . , 308 and physical 330, . . . , 336 addresses of that data in specifically designated correlation registers or fields such as the space manager 370. Subsequently, when the Host requests data identified by a specific logical address, the Flash Memory System examines the various registers, fields, or files correlating logical addresses to physical addresses. Upon locating the logical address requested by the Host, the Flash Memory System is able to secure the Physical Address correlating to that logical address. The Flash Memory System retrieves the User Data from that physical address.
The storage and retrieval process involves a series of operations of masking and concatenating various bits within various address registers. The bit register used to store a Logical Block Address can be divided into two sub-registers, a higher order bit field 342 and a lower order bit field 344 of LBA temporary register 340. A group of Logical Blocks 310, . . . , 316, typically sixteen or thirty two, defined by a common address within the higher-order bit field comprise a Virtual Logical Block 300. The number in the higher-order bit field is the Virtual Logical Block Address. The number in the lower order bit fields among the component Logical Blocks is an LBA offset which distinguish the individual Logical Blocks. The lower order addresses or offsets typically increment from zero through fifteen or zero through thirty-one, though any size Virtual Logical Block is possible. The higher order Virtual Logical Block address plus the lower order bits define a Logical Block address, as illustrated by LBA temporary register 340. Component Logical Blocks 310, . . . , 316 within a Virtual Logical Block are therefore defined by a Logical Block Address (LBA).
A Virtual Logical Block (VLB) 300 of data, defined by a Virtual Logical Block Address (VLBA) represents an amount of data equivalent to a physical area of memory known as a Physical Data Block 320 which is defined by a Virtual Physical Block Address (VPBA). A VPBA is comprised of complement Physical Pages. Consecutive pages within a VPBA are distinguished by PBA offset. The VPBA plus the PBA offset define a unique PBA or Physical Block Address 330, . . . , 336 for each page. Each Logical Block 310, . . . , 316 represents an amount of data equivalent to a physical Page 322, . . . , 328. Data fields and registers dedicated to correlating logical and physical addresses, such as a RAM Space Manager 370 consume valuable memory space within a Flash Memory System, memory that could otherwise be advantageously used to store User Data. If a Flash Memory System were comprised of sufficient correlation registers 380, . . . , 384 to correlate every LBA 345, 346, etc. to a respective PBA 330, . . . , 336 a great deal of Flash Memory would be consumed in the correlation function, leaving far less available memory for storing User Data. Such detailed correlation would be required, for example, if a Virtual Logical Block of User Data 300 were fragmented into sixteen or thirty-two component LBA""s 302, . . . , 308 and stored in sixteen or thirty-two diverse pages distributed among different Physical Data Blocks within the Flash Memory System 200.
One way of minimizing that consumption of memory space devoted to correlation data is to limit correlation to larger groups of data, such as correlating Virtual Logical Blocks Addresses to Virtual Physical Block Addresses defining large blocks of physical memory. One way of retaining a correlation between component Logical Blocks of a VLB and individual Physical Pages of a Physical Data Block without multiplying correlation registers to include every Logical Block is to store consecutively addressed Logical Blocks 310, . . . , 316 of VLB 300 in consecutively addressed pages 322, . . . , 328 within a Physical Data Block 320. A one-to-one correlation between consecutive Physical Block Addresses 330, . . . , 336 within a Physical Data Block 320 and component Logical Block Addresses 302, . . . , 308 within a Virtual Logical Block 300 are thus retained through a spacial or quasi-spacial arrangement. No register need be devoted to correlating individual LBA""s with individual Physical Page addresses. Only the VLBA in the high order bit field need be correlated to the VPBA representing the Physical Data Block.
FIG. 4 is a flow chart illustrating the storage of incoming User Data according to the data fields and registers of FIG. 3. In the first step 402, Virtual Logical Block seventeen 300 (FIG. 3) is received from a Host 215 for storage in a non-volatile Flash Memory Unit 206 (FIG. 2). In the following step 404, the Controller 202 moves the first LBA 302 to the temporary LBA Register 340. Next 406, the Controller masks the lower order bits 344 within the temporary LBA Register 340, and moves the VLBA 342 into a VLBA Register 360. In the next step 408, the Controller examines the Space Manager 370 and identifies VPBA correlation register 384 corresponding to the current VLB 349 as disclosed in the VLBA register 360. In the next step 412, the Controller 202 identifies a free and non-defective Physical Data Block 320 identified by a new VPBA. In the following step 414, the Controller 202 writes the new VPBA in the correlation register 384 of the Space Manager 370.
The Controller is now ready to identify specific pages 322, . . . , 328 within the select Physical Data Block 320 for storing incoming User Data within the incoming Virtual Logical Block 300. To achieve a one-to-one correlation between consecutive Logical Blocks 310, . . . , 316 within the Virtual Logical Block 300, and consecutive Physical Block Addresses 330, . . . , 336, the Controller combines the VPBA of the Physical Data Block 320 with the LBA offset of the current LBA 302, . . . , 308. In step 415 the Controller 202 stores the VPBA of the select Physical Data Block 320 in a temporary PBA register 351. In step 416, the Controller 202 masks the higher order bits 342 of the temporary LBA register 340 and concatenates the lower order bits 344 containing the LBA offset into the lower order register 354 of the temporary PBA register. The combined upper 352 and lower 354 registers from the temporary PBA register 351 form a Physical Block Address. In step 418, the processor then programs the Logical Block of data 310, . . . 316 identified by the temporary LBA Register 340 into the physical page 322, . . . , 326 identified in the temporary PBA Register 351.
In step 420, the controller examines the next Logical Block of incoming data, and moves the LBA of the incoming Logical Block into the temporary LBA register. According to the final step 422, if the value in the VLBA Register 360 remains unchanged, the Controller 202 returns to step 416. If the new User Data received from the Host 215 comprised a new VLBA, the process returns to step 402 and resumes.
Some of the steps in FIG. 4 could be performed in a different order without changing the outcome of the process. Because the specific mechanics of storage could be performed in a number of equivalent ways, the process disclosed in FIG. 4 is not intended to suggest that a correlated storage process according to the prior art necessarily follows these exact steps. The details are disclosed simply to illustrate one way of performing a data storage process in a manner that preserves a natural correlation between LBA""s and PBA""s. According to the process as described above, the LBA offset 344 is used as a PBA offset 354 when storing a VLB into a Physical Page. Because of the order preserved in the storage or programming process, individual LBA""s requested by the Host 202 may be retrieved by the Flash Memory System 201.
FIG. 5 discloses a process according to the prior art whereby data is retrieved from the Flash Memory Unit 206 upon request from the Host 202. Again, the retrieval steps listed below are exemplary of data retrieval according to the prior art, and is not intended to limit the retrieval of data to any single algorithm according to the prior art. According to step 502, the Host 202 (FIG. 2) requests retrieval of data defined according to a particular LBA or group of LBA""s 302, . . . , 308 (FIG. 3). In step 504, the Controller 202 moves the requested LBA 302, . . . , 308 to a temporary LBA register 340, conceptually depicted as comprising an upper 342 and lower 344 register of higher order bits and lower order bits respectively. In the next step 506, the Controller 202 masks out the lower order bits 344 and defines the requested VLBA in a temporary VLBA register 360 according to the value within the higher order register 342. In the following step 508, the Controller 202 increments the Space Manager 370 to the VLBA in the temporary VLBA register 360, thereby accessing the current correlation register 384 corresponding to the VLBA found in the temporary VLBA register 360. In step 510, the Controller 202 copies the VPBA found in the current correlation register 384 into the upper register 352 of the temporary PBA register 351. In the following step 512, the Controller 202 masks the higher order bits within the upper register 342 of the temporary LBA register 340 and concatenates the lower order bits within the lower register 344 containing the LBA offset into the lower order register 354 of the temporary PBA register 351. The combined upper 352 and lower 354 registers of the temporary PBA register 351 form a Physical Block Address. The Controller 202 is now able, according to step 514, to access the Physical Data Block defined by the Physical Block Address constructed within the temporary PBA register, and forward the User Data found therein to the Host. According to step 516, the controller also forwards the Logical Block Addresses in the temporary LBA Register to the Host, thereby defining the Logical Block of User Data according to the original address ascribed to it by the Host.
By concatenating the LBA offset onto a VPBA during the storage and retrieval process, the Controller is able to create an LBA to PBA correlation upon request, and need only store a correlation between the VLBA and the VPBA in the Flash Memory System 201, reducing the amount of memory necessary for correlation to only a fraction of what would be necessary without this process. Accordingly, when the Host requests the data defined by a series of Logical Block Addresses, the Flash memory retrieves the User Data from a physical location, and returns it to the Host. When the Host retrieves data therefore, the data sent to the Host is identified by the same address which the Host requested. The dual addressing scheme and cross referencing used within the Flash Memory System is invisible to the Host.
Although flash memory is typically much faster than rotating disk type memory, there is a wide disparity between the xe2x80x9creadxe2x80x9d and xe2x80x9cwritexe2x80x9d times within flash memory. The read time of flash memory is on the order of microseconds, and compares favorably with RAM type memory. The programming or write operation to Flash Memory, however, is on the order of milliseconds, typically slower by powers of ten than the programming time typically found in RAM type memories. Accordingly, the RAM Data Buffer 204 is able to receive and retransmit digital data far faster than the non-volatile memory unit 206 is able to receive it. The programming phase of a Flash Memory System therefore becomes a major factor limiting the potential speeds possible through integrated circuit and MOS system incorporating Flash Memory components.
The speed of programming Flash Memory was substantially improved by the development of a multi bank Flash Memory System as seen in FIG. 6. A Flash Memory System 600 is operatively connected to a Host system 601 such as a computer or digital camera. A controller 604 comprising a Host Interface Circuit 605, a Data Buffer 607 and a Memory Interface Circuit 609 is operatively coupled to a Flash Memory Unit 602. The Flash Memory Unit 602 is comprised of a plurality of Memory Banks 621, . . . , 627. The first Bank 621 is comprised of a plurality of Physical Data Blocks 631, . . . , 637 and a single RAM Data Register 613. The second Bank 623 is comprised of a plurality of Physical Data Blocks 641, . . . , 647 and a single RAM Data Register 615. The third Bank 625 is comprised of a plurality of Physical Data Blocks 651, . . . , 657 and a single RAM Data Register 617. The fourth Bank 627 is comprised of a plurality of Physical Data Blocks 661, . . . , 667 and a single RAM Data Register 619. Typically, each of the plurality of Memory Banks 621, . . . , 627 are comprised of an equal number of Physical Data Blocks. Typically, each RAM Data Register 613, . . . , 619 has a data capacity equal to one Page of physical memory, which is typically capable of holding five hundred twelve bytes of User Data plus sixteen bytes of overhead data. The Flash Memory Unit 602 of FIG. 6 is comprised of four Memory Banks 621, . . . , 627 for exemplary purposes only. Multi-bank flash memories could be comprised of any number of memory-banks. Similarly, the size of data fields and memory areas are for exemplary purposes, depicting the more common configurations found according to the prior art. Neither these depictions of the prior art, nor its application to the present invention is intended to restrict the application of the present invention to any specific number of Memory Banks. Neither are the illustrations contained herein intended to restrict the sizes of data fields and registers, whether physical or logical, nor restrict an amount of incoming data being stored or processes. Rather, specific parameters such as sizes of data fields, the number of sub-groupings of physical memory comprising a larger memory component, or the number of sub-groupings comprising a larger group of data, are offered for illustrative purposes only, and have been selected to represent quantities frequently found in the prior art.
In multi-bank Flash Memory Systems 600, the RAM Data Buffer 607 does not directly store data into Flash Memory Blocks 631, . . . , 667. Rather, the RAM Data Buffer 607 loads data in to the plurality of RAM Data Registers 613, . . . 619, which then simultaneously load User Data into their respective Memory Banks 621, . . . 627. Each RAM Data Register 613, 615, 617, 619 is typically capable of storing and programming one page of data.
As the Flash Controller 604 receives information from the Host 601, the Host Interface Circuit 605 queues the information in the RAM Data Buffer 607. When the RAM Data Buffer 607 is filled according to a predetermined amount of data, the memory interface circuit 609 begins writing data from within the RAM Data Buffer 607 to select RAM Data Registers from among the plurality of RAM Data Registers 613, 615, 617, 619 within the Flash Memory Unit. In the four-bank Flash Memory Unit 602 depicted in FIG. 6, the Buffer 607 would typically store four pages of data. According to the most advantageous designed, the number of select RAM Data Registers typically equals the number of Virtual Logical Blocks of incoming data. Data Bus 611 is a parallel bus structure for moving data from the Data Buffer 607 to the Data Registers 613, 615, 617, 619. Because the RAM Data Buffer 607 and the RAM Data Registers 613, 614, 617, 619 are random access memory structures, the read and write times between these structures is extremely fast. After the select RAM Data Registers 613, . . . , 619 have filled, the individual RAM Data Registers 613, . . . , 619 simultaneously begin writing data to flash memory areas within their respective Memory Banks 621, . . . , 627. In a four bank system, programming time is reduced to approximately xc2xc the time required in a traditional Flash Memory Unit. In a ten bank system, programming time with the reduced to approximately one tenth the programming time required by a traditional flash Memory Unit. A multibank system is therefore faster than a traditional Flash Memory Unit by a factor equal to the number of Ram Data Registers simultaneously engaged in programming User Data into a Flash Memory Unit.
Although the transmission and programming time from the RAM Data Buffer 607 to the RAM Data Registers 613, . . . , 619 is negligible when compared against the programming time for the Flash Memory cells, advanced designs can substantially reduce the time expended on writing User Data from the RAM Data Buffer 607 to RAM Data Registers 613, . . . , 619. FIG. 7 discloses a Memory Unit comprised of multiple Memory Banks 702, 704, 706, 708. A distinctive feature of this embodiment, however, is the presence of dual RAM Data Registers 710 and 720, 712 and 722, 714 and 724, 716 and 726, respectively assigned to each individual Memory Bank 702, . . . , 708. Each Memory Bank 702, . . . , 708 individually comprises a primary Register 710, 712, 714, 716 and an auxiliary Register 720, 722, 724, 726. According to this embodiment, the RAM Data Buffer 730 loads the four respective primary Registers 710, . . . , 716 with data to be stored in the Flash Memory cells of the respective Memory Banks 702, 704, 706, 708. Again, for continuity of the comparison, it is be assumed that there are a total of four Virtual Logical Blocks of incoming User Data, each VLB comprising thirty-two Logical Blocks of User Data, are to be distributed among the four Memory Banks 702, 704, 706, 708. Each Memory Bank 702, 704, 706, 708 will therefore receive one Virtual Logical Block, or thirty-two Logical Blocks data, programmed one page at a time, plus the overhead data associated with each page. This process will occur over thirty-two cycles.
By advantageously alternating between the primary Registers 710, . . . 716 and auxiliary Registers 720, 722, 724, 726, a time delay in writing data from the RAM Data Buffer 730 to the RAM Data Registers 710, . . . 726 would occur only on the first cycle of writing of the first four pages of data to the four respective registers. Programming of the Flash Memory of the respective Banks 702, . . . , 708 takes far longer than loading a page of memory into a RAM Data Registers. Therefore, as the primary Registers 710, . . . , 716 are programming their respective pages of data into the Flash Memory Cells of their respective Memory Banks 702, . . . , 708, the RAM Data Buffer 730 can load a next four pages of data into the four auxiliary Registers 720, . . . , 726. Because this takes place while the Flash Memory cells are being programmed by their respective primary Registers 710, . . . 716, there is no actual delay imposed in the writing of the auxiliary Registers 720, . . . , 726. When the primary Registers 710, . . . , 716 have finished loading their respective pages of data into the Memory cells of their respective Memory Banks 702, . . . , 708, the auxiliary Registers 720, . . . 726 are immediately ready to begin loading their respective pages of data into their respective Memory Banks 702, . . . 708. During the programming of the auxiliary registers 720, 722, 724, 726 into their respective Physical Data Blocks, the RAM Data Buffer 730 can simultaneously load the next cycle of data into the primary registers. This process of simultaneously loading data into one set of registers while a complimentary set of registers programs select Flash Memory cells continues until the select data has been loaded into the Flash Memory. As noted, the only delay imposed by the loading of data from the RAM Data Buffer 730 into the respective RAM Data Registers 710, . . . , 716 occurs during the first cycle.
Assuming that each RAM Data Register has a capacity of one page of data, which is roughly equal to one Logical Block of User Data; where N=the total number of Memory Banks being utilized in a programming operation according to the present invention, p=the total number of pages to be loaded, t=the amount of time to load a single page of data into a single RAM Data Register or RAM Data Buffer, and T=the amount of time required to program a single page of data into Flash Memory, the following table compares the programming speeds according to the prior art FIG. 2, multiple Memory Banks with a single RAM Data Register per Memory Bank according to the present invention (FIG. 6), and multiple Memory Banks with dual RAM Data Registers according to the present invention (FIG. 7):
The programming times for the above table assumes that the Data Bus 611, 740 of the multi bank systems carries data at the same rate as the Data Bus 230 of a traditional Flash Memory Unit. If Data Bus 611, 740 according to the current invention could program all RAM Data Registers 710, . . . , 716 simultaneously through a parallel configuration, the above equations would have to be altered slightly.
Returning to the discussion according to FIG. 6, according to the above illustration, N Memory Banks per Memory Unit effectively results in a total programming time that is N times as fast as an application with a traditional Flash Memory Unit. On first blush, this would appear to invite the construction of Memory Units comprising hundreds of Memory Banks. Although there is no theoretical limit to the number of Memory Banks that might be incorporated within a multi-bank Flash Memory Unit, operational parameters according to a particular application will typically dictate practical limits to the number of Memory Banks that can be effectively utilized.
According to the prior art, multi-bank Flash Memory units were programmed according to an interleaving process, illustrated in conjunction with FIG. 8. According to the following illustration, it is assumed for exemplary purposes only that each VLB comprises thirty-two individual Logical Blocks in four Physical Data Blocks. It is also assumed for exemplary purposes that each Register 840, . . . 846 programs one Page of User Data per cycle, one Page corresponding to one Logical Block of User Data. Four consecutive VLB""s of User Data contain one-hundred twenty eight Logical Blocks 810, . . . , 826 of data, which may be represented either by an address, or an offset number measured against the total number of Logical Blocks in the incoming set of User Data 802. For example, the third Logical Block 825 within the fourth Virtual Logical Block 806 can be represented either by the address 24:2, indicating VLBA 24, offset 2, or simply according to the total offset number 98, measured against all one hundred twenty-eight Logical Blocks in the incoming set of User Data 800. Four consecutive VLB""s 803, 804, 805, 806 comprising a single set of incoming User Data 800 are processed by the Controller 604 (FIG. 6), and essentially form one continuous stack of incoming data.
When data was stored in such a multibank structure according to the prior art, an interleaving process fragments a single Virtual Logical Blocks of data into multiple Physical Memory Blocks. This process can be illustrated in in conjunction with FIG. 8. Consecutive logical blocks 810, 811, 812, 813 within the same Virtual Logical Block 803 are consecutively loaded into the RAM Data Registers 840, . . . , 846 for storage. In the first cycle, Logical Block 21:0810 is loaded into RAM Data Register 1840, Logical Block 21:1811 is loaded into RAM Data Register 2842, Logical Block 21:2812 is loaded into RAM Data Register 3844, and Logical Block 21:3813 is loaded into RAM Data Register 4846. The contents of the four registers 840, . . . , 846 are then simultaneously programmed into the first Pages 858, 861, 864 and 870 within four separate and distinct Physical Data Blocks 850, 852, 854, 856 within the respective Memory Banks 832, 834, 836, 838. Data stored according to this interleaved process therefore fragments a single Virtual Logical Block of Data Across four separate Physical Memory Blocks 850, 852, 854, 856 disposed within four separate Memory Banks 832, 834, 836, 838. When the data were retrieved in a reverse process, it can be reconstructed accurately. However, if a reverse interleaving process is not utilized, reconstruction of the User Data becomes problematic. Although reconstruction can be accomplished through detailed Correlation Fields which correlate LBA""s to PBA""s, the resulting liabilities in memory consumption make this option largely unworkable.
Because the interleaving process is achieved in part to the activity of the Host, a Host designed to work in conjunction with a standard or single-bank Flash Memory Unit can only reconstruct a file of User Data when a single VLB is stored in a single VPB, establishing a one-to-one Correlation between the LBA""s and the PBAs. Older Hosts therefore cannot retrieve data from multiple memory banks that store data in a fragmented or interleaved fashion; the systems are simply not compatible. The problem could theoretically be resolved by designing a multibank flash memory stick with a RAM Data buffer 830, FIG. 8 of sufficient data capacity to store the four incoming Virtual Logical Blocks of data 803, . . . , 806, and perform the interleaving process transparently within the flash memory stick. A Host would simply load data continuously into a RAM Data Buffer of the Flash Memory System. How the Flash Memory System processed the data would be transparent, and therefore irrelevant and to the Host. The obvious drawback is the massive amount of memory which must be set aside for use by the RAM Data buffer. Similarly, the problem could be solved by devoting a massive amount of memory within the Flash Memory System to the RAM the Space Manager. If every single LBA were correlated to every single PBA, fragmentation would not prevent reconstruction of data. Again however, a massive amount of valuable memory would have to be devoted to the random access memory of the Flash Memory System, reducing the actual capacity of the flash memory itself. Although either of these solutions might resolve the problem of designing a Flash Memory System compatible with various Hosts, they do not lend themselves well to Flash Memory applications.
There exists therefore need for a multi-bank flash memory stick which exhibits the speed advantages a multibank Flash Memory Unit, while maintaining downward compatibility with older Hosts designed for traditional single bank Memory sticks. There further exists a need for a Host that can utilize the speed advantages of a multibank flash Memory Unit while storing the data in an arrangement that can later been retrieved by older Hosts. There further exists a need for a user friendly means for configuring a Flash Memory System to store data in a proper arrangement according to the capabilities and format of the Host transmitting the data for storage. There further exists a need for a user friendly means of configuring a Host to send and retrieve data in a format or protocol that is compatible with both traditional single-bank flash memory sticks, and multibank Flash Memory sticks. There further exists a need for achieving compatibility while minimizing the amount of memory expended on the RAM Data buffer. There further exists a need for achieving compatibility with diverse Hosts while minimizing the amount of flash memory expended on the RAM a Space Manager.
The present invention discloses a method and apparatus for storing incoming user data in a multibank Flash Memory System which exhibits the speed advantages a multibank Unit while storing a Virtual Logical Block of data in a non fragmented arrangement, thereby maintaining downward compatibility with older Hosts designed for traditional single Memory Banks sticks. The present invention further discloses a method and apparatus for utilizing the speed advantages of a multibank Flash Memory Unit while storing data in an arrangement accessible to older Hosts. The present invention further discloses a method and apparatus for configuring a multibank Flash Memory System to store data in a proper arrangement according to the capabilities and format of a Host transmitting the data for storage. The present invention further discloses a method and apparatus for configuring a high-performance Host to send and retrieve data in a format or protocol that is compatible with both traditional single-bank flash memory sticks, and multibank Flash Memory sticks. The present invention further discloses a method and apparatus for achieving compatibility with both traditional and high performance Hosts while minimizing the amount of memory expended on the RAM Data buffer. The present invention further discloses a method and apparatus for achieving compatibility with both traditional and high performance Hosts while minimizing the amount of memory expended on the RAM Space Manager.
According to one embodiment of the present invention, a Flash Memory System comprises a plurality of separate and independently addressable Memory Banks. Each Memory Bank comprises a plurality of independently addressable and independently programmable non-volatile Data Storage Areas and a primary RAM Data Register. A first primary RAM Data Register within a first Memory Bank is capable of programming data into Data Storage Areas within the first Memory Bank, and a second primary RAM Data Register within a second Memory Bank is capable of programming data into Data Storage Areas within the second Memory Bank. The Flash Memory System also comprises a Vendor Unique Value, including means for loading the Vendor Unique Value into a Handshake Data Envelope upon start up. When no responsive handshake is received from a Host, the Flash Memory System defaults to a first mode for storing data in a manner compatible with traditional Hosts. When the responsive handshake is received from the Host, the Flash Memory System is configured to a second data storage mode capable all of storing multiple pages of data simultaneously by means of the multiple Memory Banks.
According to one embodiment of the present invention, a Flash Memory System comprises a plurality of separate and independently addressable Memory Banks. Each Memory Bank comprises a plurality of independently addressable and independently programmable non-volatile Data Storage Areas, and a primary and an auxiliary RAM Data Register. A first primary and first auxiliary RAM Data Register within a first Memory Bank are independently capable of programming data into Data Storage Areas within the first Memory Bank. A second primary and the second auxiliary RAM Data Register within a second Memory Bank are independently capable of programming data into Data Storage Areas within the second Memory Bank. When operating in a high-performance storage mode utilizing simultaneous programming of multiple Memory Banks, sequential programming cycles will alternately utilize the primary and auxiliary RAM Data Registers for data storage. The Flash Memory System also comprises a Vendor Unique Value, including means for loading the Vendor Unique Value into a Handshake Data Envelope upon start up. If no responsive handshake is received from a Host, the Flash Memory System defaults to a first mode for storing data in a manner compatible with traditional Hosts. If a responsive handshake is received from the Host, the Flash Memory System is configured to a second mode, capable all of storing multiple pages of data simultaneously by means of the multiple Memory Banks.
According to one embodiment of the present invention, a method of programming incoming data into a multibank Flash Memory System comprising a Vendor Unique Value, a Controller operatively connected to a Memory Unit, the Controller comprising a RAM Data Buffer operatively connected to a Memory Interface Circuit, the Flash Memory Unit comprising a plurality of separate and individually addressable Memory Banks, each Memory Bank comprising a primary RAM Data Register and a plurality of individually addressable and individually programmable Physical Data Blocks, each Physical Data Block comprising a plurality of individually addressable and individually programmable Pages, the method comprising the steps of generating a Handshake Data Envelope, loading the Vendor Unique Value within a Flash Memory System into the Handshake Data Envelope; and sending the Handshake Data Envelope to a Host. If no responsive handshake is received from the Host, the Flash Memory System defaults to a first data storage configuration and programs incoming data into the Flash Memory System according to a first data storage method of programming one page of User Data per programming cycle. If a responsive handshake is received, the Flash Memory System is configured to a second data storage configuration which includes the simultaneous programming of a plurality of pages of data into multiple Memory Banks on each programming cycle. The programming is performed in a non-interleaved fashion so that consecutive Logical Block Addresses within a common Virtual Logical Block Address are stored in consecutive physical block addresses in a common Physical Data Block.
According to one embodiment of the present invention, a method of programming incoming data into a multibank Flash Memory System comprising a Vendor Unique Value, a Controller operatively connected to a Memory Unit, the Controller comprising a RAM Data Buffer operatively connected to a Memory Interface Circuit, the Flash Memory Unit comprising a plurality of separate and individually addressable Memory Banks, each Memory Bank comprising a primary RAM Data Register, an auxiliary RAM Data Register and a plurality of individually addressable and individually programmable Physical Data Blocks, each Physical Data Block comprising a plurality of individually addressable and individually programmable Pages, the method comprising the steps of generating a Handshake Data Envelope, loading the Vendor Unique Value within a Flash Memory System into the Handshake Data Envelope, and sending the Handshake Data Envelope to a Host. If no responsive handshake is received from the Host, the Flash Memory System defaults to a first data storage configuration and programs incoming data into the Flash Memory System according to a first data storage method of programming one page of User Data per programming cycle. If a responsive handshake is received, the Flash Memory System is configured to a second data storage configuration which includes the simultaneous programming of a plurality of pages of data into multiple Memory Banks on each programming cycle. The programming is performed in a non-interleaved fashion so that consecutive Logical Block Addresses within a common Virtual Logical Block Address are stored in consecutive physical block addresses in a common Physical Data Block. Sequential programming cycles will alternately utilize the primary and auxiliary RAM Data Registers for data storage.
These and other advantages will become apparent to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawings and figures.

Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible


In an eyeglass frame comprising a pair of lens fixing rims, a bridge connecting the paired rims, and a pair of temples, the bridge and/or the temples are made of Ti-Ni-V alloy having a super elasticity of a generally rectangular stress-strain hysteresis loop over a relevant temperature range of 0.degree.-20.degree. C. so as to improve eyeglass wearing comfortability. The Ti-Ni-V alloy comprises Ni and Ti with an atomic ratio Ni/Ti of 1.02-1.06 and V 0.25-2.0 at. %, and is worked into a desired shape and thereafter is heat-treated at 425.degree.-525.degree. C. for 10-60 minutes.

1. Field of the Invention
The present invention relates to eyeglass frame and, in particular, such frames using Ti-Ni alloy elements.
2. Description of the Prior Art
U.S. Pat. No. 4,772,112 issued to Zider et al. and assigned to CVI/Beta Ventures, Inc. discloses to use a shape memory alloy such as Ti-Ni alloy for elements in the eyeglass frame.
It is well known in the art that the Ti-Ni shape memory alloy has a super elasticity or a pseudo elasticity as well as the shape memory effect. The reference 1 proposes to use, as an optimized elasticity, a combination of a super elasticity as shown in FIG. 2f and a work-hardened pseudo elasticity of FIG. 2h in the Reference.
The stress-strain curve according to the optimized elasticity has a comparatively small hysteresis loop and the strain variation is almost in propotion to variation of the stress. Although the reference recommends utilization of the optimized elasticity for the eyeglass frame, it has been confirmed by the present inventor that the super or pseudo elasticity having a generally rectangular hysteresis is more relevant for the eyeglass frame elements such as bridges and temples.
Although the conventional Ti-Ni shape memory alloy has the stress-strain curve of the rectangular hysteresis loop as shown in FIG. 2c in the reference, the curve is realized only a limited temperature range which is smaller than a broad relevant temperature range such as 0.degree.-20.degree. C. Therefore, the Reference abandon utilization of the pseudo elasticity having the generally rectangular hysteresis for the eyeglass frame elements.

Eyeglass frame having Ti-Ni-V alloy element with improved wear comfortability