Wet abrasive blasting systems are described that have a slurry piping system and a gas piping system that have pipes and other piping components, such as valves and regulators, that have a more consistent internal cross-sectional area than conventional wet abrasive blasting systems. The more consistent flow area provides astonishing improvements in blasting efficiency and consistent and predictable slurry flow rates.

To remove the paint, dirt or other surface coating from a substrate such as a surface to be painted or cleaned, a blasting system is both desirable and necessary. There are a variety of blasting processes for these purposes, including but not limited to, water blasting, dry abrasive blasting, and wet abrasive blasting. In certain applications, abrasive blasting systems are able to efficiently clean or remove a coating without damaging the underlying metal or other substrate. Although in other applications, a certain degree of surface roughening may be desired.
The use of dry abrasive blasting with particles such as those used in conventional sand blasting may result in surface roughness and other damage to the substrate. Typical blast particles are hard and abrasive in order to increase the efficiency of the blasting operation but may therefore result in damage to the substrate. Soft recyclable blast particles are sometimes substituted to avoid surface damage. These recyclable blast particles include, but are not limited to, agricultural products such as crushed walnut shells, crushed pistachio shells, and rice hulls. Plastic particles are sometimes used to reduce substrate surface damage but may also result in a reduction in efficiency of the blasting operation.
Wet abrasive systems have been used to also control surface damage. Wet abrasive systems combine the benefits of these blasting systems and dry abrasive blasting systems. In wet abrasive blasting, the fluid may encapsulate the abrasive media to simultaneously add mass to the abrasive and buffer the impact of the abrasive against the substrate to reduce potential surface damage but still effectively strip or clean the surface while also reducing the dust produced compared to a dry abrasive blasting system. However, wet abrasive systems require efficient mixing of slurry and a gas stream to produce a consistent stream of a three-phase mixture of fluid, solid abrasive, and gas stream. If the mixing of slurry and pressurized gas is not well controlled, the blasting process is less efficient and the benefits of a wet abrasive system are not fully realized.
There is a need for a wet abrasive system that is easier to control in order that the benefits of a wet abrasive system are more fully realized.


An energy dissipating device which is capable of dissipating energy through its plastic axial deformation without undergoing buckling comprises at least three hysteretic elements, being interconnected in series in such a way, that at least one hysteretic element will be subjected to compression while at least another hysteretic element is subjected to tension when an external load is applied to the energy dissipating device.

Energy dissipating devices are used to connect adjacent structural elements or systems of structures like a bridge deck and its abutment or a building and its foundation with the aim of mitigating the adverse effects of dynamic actions like those deriving from earthquakes but also from windstorms, impacts, etc.
As it is known, the reason for adopting these devices stems from the fact that seismic actions produce sudden onset soil displacements with associated accelerations that, transmitted through the foundation, generate inertial forces due to the comparatively large mass of structures such as bridges, buildings and the like.
Alternatively we may say that during a seismic event large amounts of energy are generated and propagated through the soil. Said energy can be transmitted to a structure, and the same represents the main cause of possible damage secondary to a seismic event.
Furthermore, it is also known that by using suitably located isolating devices, referred to as "seismic isolators", it is possible to limit the amounts of energy transmitted to the structure and thus also the loads thereby generated. In other words, seismic energy is reflected by the aforesaid isolation devices, except for that portion associated with a frequency equal to or near the resonance frequency.
However, the structure (considered as an oscillating system) will nonetheless tend to accumulate the portion of energy within said spectrum range, making it thus necessary to use a device that dissipates the energy in the form of heat.
There are several physical mechanisms that can be used to dissipate energy. The subject case exploits the dissipating capacity of materials, when they are stressed beyond their yield point.
As it is well known, by subjecting for example a metal element like a strut made of steel to an increasing strain, a first phase of direct force-deformation proportionality is observed (elastic phase), followed by a phase of little dependence of the former on the latter (plastic or post-elastic phase). Devices using this principle are referred to as hysteretic elements (HE). Thus, the term "hysteretic" is referred to elements or devices, whose reaction largely depends on the impressed displacement (or deformation) in contrast to "viscous" elements or devices, whose reaction largely depends on the rate (velocity) of the displacement (or deformation).
The idea of utilizing steel struts as hysteretic elements within a structure to absorb large portions of seismic energy began with the conceptual and experimental work of Skinner—New Zealand (1975). Today this kind of device is known as steel hysteretic damper (SHD). Actually, plastic deformation of steel is one of the most effective mechanisms available for the dissipation of energy, from both economic and technical point of view. Steel dissipaters for steel hysteretic dampers have been conceived and manufactured in a very large geometric configuration variety. Nonetheless, their most serious drawback is the limited capacity of accommodating large displacements, as necessary in zones prone to moderate or high seismicity.
This is the main reason why hydraulic viscous dampers (HVDs) gained a progressively increasing popularity in bridge structures as elements capable of mitigating local vibrations, limiting structural drift as well as source of supplemental damping, virtually without any limitation displacement-wise.
In recent years, however, some concerns were raised in the United States by the conditions of devices in service on Caltrans bridges, suspected of leaking hydraulic fluid, after a time in service of approximately 10 years. Even though this event should not be interpreted as a proof of a systemic deficiency of this type of devices (in Europe such hitches are rarely been observed), nonetheless some tests and inspections, recently completed at University of California at San Diego, indicated an unexpected level of degradation in dampers not subjected to any large seismic event.
In response to this concern and as an alternative solution to the use of HVDs, a few research projects have been carried out at the University of Utah and the Department of Structural Engineering of University of California at San Diego to investigate the applicability and limitations of hysteretic elements (HEs) for long-span bridge applications.
Steel brace frames are widely used for building construction. For seismic applications, however, diagonal braces are expected to yield in tension, but buckle in compression. To avoid this undesirable phenomenon and thus provide a more reliable source of energy dissipation, the concept of buckling restrained braces (BRB) as hysteretic elements was first developed in Japan in the early 1970s.
Extensive research was since conducted in Japan and a variety of BRBs have been developed by Nippon Steel Corp. But it was not until after the Kobe Earthquake in 1995 that Japanese designers started to incorporate BRBs in the so-called "damage-tolerant" seismic design of multistory buildings. Actually, BRBs have also been used in two long-span bridges in Japan after the above mentioned disastrous event, one for a case of seismic retrofit and one for a new construction.
The main idea behind BRB is to avoid global buckling such that a full and stable hysteresis loop can be developed to dissipate energy. A variety of BRBs have been developed, but the concept is very simple. FIG. 11 illustrates this concept.
A long and relatively slender bar or strut functions as hysteretic element that acts as a yielding steel core, usually made of low strength steel with high ductility. It is encased in a steel tube with mortar infill functioning as a buckling preventer for the hysteretic element. However, as opposed to what occurs in reinforced concrete members, some unbonding materials or even an air gap is provided to isolate the yielding steel core and the surrounding buckling restraining mechanism to discourage composite action.
The foremost BRBs' drawback resides in their excessive length, which derives from the relatively limited permissible yield deformation under repeated cycling, as requested in seismic applications. This shortcoming severely limits the applicability of this type of devices to those cases where large spaces are available for their installation.
Therefore, it is an object of the invention to provide a simple and cheap energy dissipating device which has broad application possibilities even where space is limited.
The solution of this object is achieved by an energy dissipating device according to claim 1. Preferred further configurations of the energy dissipating device are described in the dependent claims.
It is characteristic for an energy dissipating device according to the invention, that the energy dissipating device comprises at least three hysteretic elements, being interconnected in series in such a way, that at least one hysteretic element will be subjected to compression while at least another hysteretic element is subjected to tension under an external load (e.g. seismic, wind and/or impact load) being applied to the energy dissipating device, as it will become clear in the following.
This has the beneficial effect that the axial overall dimension of the device is markedly reduced. Or, conversely, larger relative displacements can be accommodated in a device having equal length compared with those known from the past. By reducing the overall length of the device, it can be much more easily installed in existing or newly designed structures.
Moreover, the tensioned hysteretic element(s) may stabilize the compressed hysteretic element(s) against buckling, so that a buckling preventer may not be needed, at least under certain circumstances.
Furthermore, the energy dissipating device is preferably designed in such a way that it can undergo several hysteretic cycles before it needs to be replaced.
In another configuration of the energy dissipating device the hysteretic elements are arranged in parallel to each other. A parallel arrangement of the hysteretic elements has the advantage that said device has a compact overall length compared to existing Buckling Restrained Braces. Even though a parallel arrangement is preferred, here also such hysteretic elements are to be considered, which are arranged to form an angle between each other.
If a more compact device is desired, the hysteretic elements are preferably arranged alongside to each other. Since the at least three hysteretic elements are interconnected in series, the overall length of the energy dissipating device is about one third, compared to the overall length of an existing Buckling Restrained Brace with the same capacity to accommodate displacements. Another advantage is that a reduction of the overall length to one third leads to a buckling load that is at least increased by a factor of nine (9) according to Euler's theory. This is a further reason why a buckling preventer may not be needed in this type of device. Consequently, it is also possible to increase the capacity to accommodate displacements by a factor of about three (3) compared to existing Buckling Restrained Braces with an equal overall length.
Alternatively, at least one hysteretic element is arranged concentrically with another hysteretic element. The concentric arrangement of a hysteretic element does not necessarily require that the center axes of the hysteretic elements coincide in a line. Although this is preferred, also such energy dissipating devices shall be included in which the center axes of the hysteretic elements do not coincide. By this arrangement it is also possible to reduce the length of the energy dissipating device. This has the aforementioned advantages of a reduced overall length compared with a conventional Buckling Restrained Brace having the same capacity to accommodate displacements.
Preferably, the energy dissipating device may have at least one hysteretic element that is made of a metal like mild steel or an alloy. Since the amount of energy which can be dissipated by the device as well as the ability to accommodate displacements depends on the hysteretic element's material, here especially materials with a high ductility, which preferably also show similar deformation characteristics under compression and tension, are preferred. By a suitable choice of the hysteretic element's material, as well as by the choice of the hysteretic element's dimensions, design parameters such as the yield point, the capability of accommodating displacements and the capability of dissipating energy by the hysteretic elements can be influenced.
It is practical that concentrically arranged hysteretic elements are formed of tubes. The tubes may have a cross section area which has a circular, square, rectangular or any other closed or opened shape. However, tubes with a closed and symmetrical cross sectional shape are preferred.
Symmetrical tubes do increase the resistance against buckling since lateral or radial deformations under axially applied loads are minimized. One significant benefit accrued from the use of tubes is the elimination of the undesirable effects of the bending moment M=F*e that develops during the application of an axial force "F" when using for example flat steel bars as hysteretic elements with an eccentricity "e".
Obviously, to be concentrically arranged the inner tubes have a smaller diameter than the outer tube. The cross sectional area should be the same for all concentric tube-like hysteretic elements and is determined by the design reaction force of the device and the yield strength of the material used. This means, apart from some minor corrections due to the shape factor, the thickness of the tube's wall is inversely proportional to its diameter. As a result the concentrically arranged tubes have a similar deformation behavior.
Moreover the median part of one or more tubes may be cut longitudinally, in other words, along a generatrix. This helps to remedy the drawbacks of radial deformations of the tubes induced by axially applied loads. It is known that axially applied loads in tube-like elements produce tangential stresses in the same, which cause reduction or increase in their diameter in tension or compression respectively. Consequently, two adjacent tubes may get in touch and produce uncontrollable frictional forces, which negatively influence the reaction of the device. This effect is particularly important for configurations where the tube is arranged in the middle of adjacent concentrically arranged tubes. The local instability of the lips resulting from the cutting is minimized by the containment effect of the surrounding outer and inner tubes.
Further, the energy dissipating device may comprise a buckling preventer. A buckling preventer may be any contrivance that helps to avoid buckling of a hysteretic element. Although it is preferred to avoid the use of a buckling preventer, it might be necessary to provide an energy dissipating device with a buckling preventer to reduce the risk of buckling particularly in specific situations.
The innermost of at least one hysteretic element may be filled with a stabilizing material as buckling preventer.
As stabilizing material every high compression resistant material is suitable, for instance a mortar infill. The stabilizing material is an effective and economic method to avoid lateral deformations of said hysteretic element and in consequence to increase the resistance against buckling of the whole device.
In a further configuration of the invention's energy dissipating device the buckling preventer comprises a containment tube surrounding at least one hysteretic element wherein the space between the hysteretic element and the containment tube may be filled with a stabilizing material at least partially. By the use of a containment tube a lateral deformation of the at least one hysteretic element under an axially applied load is avoided. By filling a stabilizing material in the space between the hysteretic element and the containment tube the possibility of a lateral deformation of the at least one hysteretic element under an axially applied load is even more reduced since there is no space left for such a deformation.
Further the buckling preventer may also comprise a containment tube which surrounds several hysteretic elements at once. Then the space between the hysteretic elements and/or the containment tube and/or the space between the hysteretic elements themselves is preferably filled with a stabilizing material.
The containment tube may be manufactured from a single piece of tube. Alternatively, the buckling preventer may also be composed of an outer containment tube and an inner containment tube. In this case the space between the outer and inner containment tube is preferably filled with a stabilizing material as additional buckling restraining mechanism. The use of an inner and outer containment tube, especially if the space in-between is filled with a stabilizing material, is a simple but effective way of increasing the buckling resistance of the energy dissipating device.
Especially in the case where the hysteretic elements are symmetrically located with respect to the longitudinal axis of the device, the buckling preventer may comprise at least one transverse restraint interconnecting at least two hysteretic elements. Such restraints prevent the lateral deformation of the at least two hysteretic elements, thus the buckling resistance of the device is increased. Moreover, by using more transverse restraints connecting outer ends as well as the intermediate parts of both hysteretic elements, it is possible to further increase the buckling resistance of the whole device. In this way an external containment tube used as buckling preventer may be avoided. This leads to a simpler construction of the energy dissipating device.
In a further configuration, the at least one hysteretic element may comprise on at least one of its surfaces a lubricant and/or an un-bonding material and/or a sliding pad in order to reduce frictional forces developed during a relative movement between the at least one hysteretic element and the stabilizing material and/or the containment tube and/or another hysteretic element under an external load. This is based on findings that it is advantageous if the hysteretic elements themselves have no forced contact with the stabilizing material so that they are able to move in direction of the axially applied load without excessive frictional forces.
Especially in the case, when the hysteretic elements are tube-like elements, the energy dissipating device may comprise a rigid joint which connects at least two hysteretic elements in series, being formed by at least a steel crown and/or steel plate interconnecting the two hysteretic elements. The advantage of the rigid joint is that with its stiffness it is able to resist radially applied forces. Consequently the steel crown and/or steel plate interconnecting the two hysteretic elements reduce radial deformations (changes in diameter) of the hysteretic elements. Thus a contact as well as frictional forces between the tube-like elements are avoided.
Further, the energy dissipating device may comprise a shock-transmitter that accommodates slow velocity movements and transmits almost unaltered sudden onset movements. A shock-transmitter allows slow movements without appreciable resistance, but prevents those of sudden onset without appreciable deformations. Thus, this arrangement enables to accommodate the displacements between the interconnected structural elements due to thermal variations and to transmit to the hysteretic elements the displacements due to an earthquake (but also braking forces, wind etc.) so that a significant portion of the energy associated to them can be dissipated.
Within FIG. 1a to FIG. 10 equal reference signs are used for equal components.


A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.

Storage drives (e.g., SSDs which stores data in units of pages and blocks, and HDDs which stores data in units of sectors and tracks) are normally comprised of one or more memory controllers and non-volatile memory. A host sends read commands to the storage drive requesting the return of a number of data blocks which are stored on the storage drive. In response to the read command, the memory controller associated with the storage drive attempts to retrieve the requested data blocks from the storage drive. Conventionally, in response to a successful read, the memory controller returns the requested data and a status indicative of a successful read. In response to a failed read, which results from a failure to read any of the requested blocks, the memory controller returns no read data, and only returns a status indicative of a failed read. If the failed read happened after a request to return a large number of data blocks, the host is given no indication which of the requested data block(s) were in error.
In this case, in response to receiving a failed status indicator, the host must take further steps to determine the location of the failed data. In conventional methods, the host either requests all the read data from other redundant drives and mechanisms such as RAID or attempts to identify the failing blocks by issuing additional multiple read commands with smaller read ranges. Alternatively, the host uses additional commands designed for drive health management to retrieve locations of failing data. Conventional methods require additional commands, extra storage space, processing time, and power resources to retrieve the failed data locations and complete the read command.
As data becomes more complex, read commands are increasingly issued for larger and larger packets of data, consisting of blocks, which in turn yield a higher likelihood of failure of the read command. Accordingly, there is an unmet demand for storage drives to be capable of handling failed read commands more efficiently.

This patent is subject to a terminal disclaimer.

Media error reporting improvements for storage drives


A semiconductor structure includes a carrier having a surface, a supporting element, a semiconductor stack and a bridge layer. The supporting element is on the surface. The semiconductor stack is on the surface and has a side surface. The bridge layer includes a first portion connecting to the supporting element, a second portion, and a third portion connecting to the semiconductor stack. The second portion is extended from the third portion toward the first portion and is protruded from the side surface.

Light-emitting diodes (LEDs) have advantages such as low energy consumption, low heat production, long operating lifetime, strong collision resistance, small size and quick speed of response, and are widely used in various fields where a lighting device is needed, for example, vehicles, home appliances, displays and light fixtures.
Since a light-emitting diode may generate a monochromatic light, it can be used for forming a pixel in a display. For example, pixels in an out-door display or an in-door display. Recently, increasing the display resolution has become a trend in developing display technologies. In order to increase the resolution, transferring more LEDs (or pixels) onto a target substrate may be required, and some technical problems are remained to be solved.

Semiconductor structure having a bridge layer


A device and methods for catching, removing from within buildings, and releasing wild birds are provided. Sonic and/or dynamic characteristics of water are utilized as an attractant to lure birds towards a device for capturing birds. The attractant is located within a holding area of the device. The walls of the device are transparent and vented to allow the dynamic characteristics of the water to be seen from outside the device and to allow the sonic characteristics to be heard from outside the device. The device includes an opening that allows birds to enter the holding area of the device and that also prevents birds located within the holding area from exiting the device.

Birds enter structures such as retail stores, warehouses, manufacturing facilities, and other high ceiling environments via shopping cart doors, loading docks, human entrances, and other openings in the structures. Birds typically enter commercial structures in hot, cold, or rainy weather to optimize their comfort and often teach other birds methods of ingress in the buildings. Seasonal migration can compound the problem.
Birds carry many diseases and pose direct health risks to employees and customers when they enter build structures, and present a risk of contamination to food in such environments. Techniques such as flushing, mist netting and harvesting are used in many commercial environments to remove wild birds from the interior of the structures and release them outside of the structure. Flushing can be accomplished by employees at the structure, but is relatively ineffective—particularly when a bird has been within the structure for more than forty-eight (48) hours. Mist netting and harvesting are techniques which must be performed by professional pest-control technicians, and can cost between $450 to $8000 for each service and depending upon the number of birds removed. In addition to the out-of-pocket costs for pest-control technicians to remove birds from buildings, in the case of a retail store, the store has to be shut down while pest-control technicians are working. In the case of a 24-hour retail business, a loss of sales and productivity occurs. Such store closings in the aggregate may mean a loss of millions or tens of millions of dollars per year even if the store closings occur late at night or in early morning hours (e.g., midnight to 6 a.m.).
A number of devices have been developed for trapping, capturing and/or isolating birds utilizing various methods of attractants, such as food and/or water. Food is typically not an ideal attractant in retail stores and other similar environments due to the ample supplies of easily accessible open food sources within such environments. Water, on the other hand, is typically in greater demand in such environments. Thus, open sources of water can be a very strong attractant in such environments. Nevertheless, devices of the prior art are not very successful in utilizing a water supply to attract birds for capture, particularly in large building structures in which birds may typically not recognize the fact that a source of water is located within the device unless the birds come in extremely close proximity to or even are captured within the device. For example, US Patent Application Pubs. 2006/0156616 and 2006/0156995 of William P. Ried, incorporated herein by reference in their entireties, both disclose devices for capturing birds within a holding pen. The device includes a waterer assembly in the holding pen in which water is heated to prevent it from freezing and held in an enclosed storage area. The assembly includes a plurality of drip tubes that extend into the storage area to provide water to birds within the storage area. The diameters of the drip tubes are sized such that water is drawn into the drip tubes through capillary action. Thus, unless a bird is in extremely close proximity to the waterer of Ried, such that the bird can see the water forming on the end of the drip tubes, the bird has no way to recognize that it can find water within the device of Ried. Therefore, it would be beneficial to provide a device and/or methods of capturing birds in which birds can easily recognize and be attracted toward a source of water from a distance.
A number of prior art devices such as bird baths, feeders and livestock watering troughs utilize the sonic and/or dynamic characteristics of water to either attract birds to those devices and entice them to eat or drink from the devices. Examples of such devices are shown in U.S. Pat. No. 4,149,490 to English, and U.S. Patent Application Pubs. 2005/0217605 of Reusch et al. and 2008/021072 of Walkas, the entire disclosures of which are incorporated herein by reference. Nevertheless, none of these devices provide any mechanism for capturing birds, nor a mechanism to utilize the water attractant to lure the birds into a holding area. Therefore, it would be beneficial to provide a device and/or methods that captures birds and that utilizes the sonic and/or dynamic characteristics of water to lure birds into a holding area.

Wild bird catch and release device and method of catching and releasing wild birds


A compressed air system and method of operating the system wherein the slip between the compressor motor and its powering alternator is used as an indication of whether the compressor is running in a loaded or unloaded mode. A slip parameter such as % Slip is determined and compared to an allowable value in real time. If the compressor is determined to be erroneously in a loaded mode, a corrective action may be taken to reduce the probability that the motor is later started with the compressor still in the loaded mode.

Compressed air systems are used to provide energy for driving a variety of devices in a variety of applications. One such application is a railroad locomotive where compressed air is used to power locomotive air brakes and pneumatic control systems.
A typical compressed air system will include a motor-driven compressor to maintain the air pressure in a reservoir within a desired range of pressures. The compressor is cycled on and off in response to a measurement of pressure in the reservoir. A bypass valve is connected to the outlet of the compressor to selectively vent the compressor to atmosphere for running the compressor in an unloaded mode. The unloaded mode is used when the compressor motor is first energized in order to reduce the starting current drawn by the motor. After the compressor/motor have come up to speed, the bypass valve is closed to place the compressor in the loaded mode for supplying compressed air to the reservoir. After a desired pressure is achieved in the reservoir, the compressor is allowed to run in the unloaded mode for a short period, such as 30 seconds, in order to cool down the compressor and motor components. At the end of the cool down period, the motor is de-energized and the system stands ready to be re-started when the reservoir pressure drops below the low-pressure set point.
On occasion, the compressor/motor will fail to achieve a desired speed within a predetermined time period after the motor is energized. This may be due to a variety of problems, including mechanical failures in the motor or compressor, electrical failures in the motor, power supply or connections, or an improperly positioned bypass valve that leaves the compressor in the loaded mode during start-up. Regardless of the cause of the problem, the failure of the compressor to achieve a desired speed within a predetermined time period will result in the motor being tripped in order to prevent excessive heat buildup in the motor, and a system fault will be logged. With repeated failures to start, the compressed air system will be declared out of service in an effort to protect the induction motor from thermal breakdown, thereby adversely impacting the availability of the locomotive for use.

Compressed air system utilizing a motor slip parameter


A method for efficiently restoring data from a sequential-access backup archive includes receiving a candidate list identifying data sets that are potentially contained within a sequential-access backup archive. The method further receives a filter list identifying data sets that are desired to be restored from the backup archive. Using the candidate list and filter list, the method generates a search list identifying data sets that are to be ignored when searching the backup archive. The method then sequentially performs multiple searches of the backup archive such that the multiple searches collectively perform a single pass through the backup archive. When performing these searches, each search begins from the last accessed portion of the backup archive and stops upon encountering a data set not explicitly ignored by the search list. A corresponding system, apparatus, and computer program product are also disclosed herein.

1. Field of the Invention
This invention relates to restoring data, and more particularly to apparatus and methods for restoring data from a sequential-access backup archive.
2. Background of the Invention
A "backup" generally refers to a copy of original data that is created and maintained for recovery purposes. The copy may be used to restore the original data in the event the original data is lost or corrupted. Although most backups share a common purpose, the manner in which data is backed up (also referred to as the "data repository model") can vary significantly. In many cases, a data repository model is based at least partly on the type of storage media used (i.e., whether the backup is stored on magnetic tape, a hard disk, an optical disk, or the like). Once data is backed up, techniques used to recover the data also vary significantly. Such recovery techniques may be based at least partly on the way the backup data was originally stored and structured.
In some cases, backups stored on magnetic tape lack information (such as indexes or waypoints) indicating where data sets are stored in the backup or which data sets are actually included in the backup. In such cases, restoring specific data sets from the backup may be a time-consuming and resource-intensive process. Specifically, restoring data sets in such cases may require reading each data set in the backup to determine if the data set is one to be restored. This may not be a problem where the backup contains a small number of data sets. However, if the backup contains a large number of data sets, reading and inspecting each of the data sets may consume significant processing time and resources.
The above-stated problems may be compounded by the fact that data sets that were requested to be backed up may not reflect the data sets that were actually backed up. The problem may also be exacerbated by the fact that the amount of data in each data set may vary. Thus, a search technique cannot simply treat the backup as an array of fixed size entries to fast forward to a desired data set.
In view of the foregoing, what is needed is an apparatus and method to more efficiently restore data sets from a backup archive having the above-described characteristics. Further needed are apparatus and methods to efficiently search for desired data sets using search commands supported by existing storage controllers. Yet further needed are apparatus and methods to minimize the processing time and resources utilized when performing such searches.

Efficiently restoring data from a sequential-access backup archive

International Business Machines Corporation


As to at least two transistors different only in channel lengths from each other, Idsxe2x88x92Vgs characteristics in a linear region are measured under two drain-to-source voltages Vds. Consequently, a graph of Rtot=Vds/Ids vs. channel lengths is obtained for two Vds, whereby an effective channel length Leff for each Vds is extracted. A velocity saturation coefficient U1 is obtained by expressing the relation between two effective channel lengths Le1 and Le2 corresponding to the two Vds on the graph and dividing the value of Le2 at Le1=0 by the difference xcex94Vds between the two Vds. Thus, parameters related to mobility and a velocity saturation effect are extracted with consistency in a form matching with remaining E-T data.

1. Field of the Invention
The present invention relates to a characteristic extraction technique, a characteristic evaluation technique, a recording medium and a semiconductor device.
2. Description of the Background Art
In the process of developing a logic device, circuit simulation is widely employed for estimating the optimum margins on circuit characteristics. FIG. 31 is an explanatory diagram showing the outline of circuit simulation. A device referred to as a circuit simulator is employed for executing the circuit simulation. Data related to the characteristics of each element forming the circuit (device) to be simulated and data (referred to as xe2x80x9ccircuit connection informationxe2x80x9d) related to connection conditions for each element are input in the circuit simulator. The circuit simulator executes simulation on the basis of the input data, and outputs data related to the characteristics of the circuit. On the basis of the output data, an operator can determine whether or not the circuit operates with the optimum margins and feed back the results of the determination to development of the device.
In development of the state-of-the-art logic device, circuit simulation based on the well-known SPICE model forming the world standard is generally employed in particular. Further, modeling not only employing typical values as the characteristics of the element but also adopting dispersion of the characteristics of the element from the best to the worst values in consideration of errors (process errors) occurring in the process of manufacturing the device, i.e., worst/best modeling is performed. In the worst/best modeling employing SPICE, a method based on E-T (electrical test) data forms the main stream.
In this method, a group of parameters referred to as E-T data are input as the data related to the characteristics of the element. Circuit simulation is executed after the input E-T data are converted to a group of parameters referred to as SPICE parameters necessary for executing simulation based on the SPICE model. The E-T data, which are parameters associable with the SPICE parameters and having physical meanings, can advantageously be directly extracted from the electric characteristics of the element in a short time.
If the element is a MOSFET (MOS field-effect transistor), a threshold voltage Vth, channel shortening DL, external resistance Rds, channel narrowing DW, mobility xcexc and a saturation velocity Vsat (or a parameter expressing a velocity saturation effect in place of Vsat) are extracted as the E-T data. FIG. 32 is a sectional view of a MOSFET for illustrating the physical meanings of these parameters. The channel shortening DL is defined as the difference between a channel length (mask length) Lm as the dimension of a mask and an electrically effective channel length (effective channel length) Leff. That is,
DL=Lmxe2x88x92Leffxe2x80x83xe2x80x83(e1)
While not shown in FIG. 32, the channel narrowing DW is similarly defined as the difference between a channel width (mask width) Wm as the dimension of the mask and an electrically effective channel width (effective channel width) Weff. That is,
DW=Wmxe2x88x92Weffxe2x80x83xe2x80x83(e2)
Total resistance between a source electrode SS and a drain electrode DD is given by the sum of resistance (channel resistance) Rch of a channel region Ch and the external resistance Rds. Both of the source electrode SS and the drain electrode DD include electrode wires. The external resistance Rds is a resistance component outside the channel region Ch, and generally includes resistance (source/drain resistance) of a source region S and a drain region D and resistance of the electrodes (including the electrode wires). Assuming that Rtot represents the total resistance,
Rtot=Rch+Rdsxe2x80x83xe2x80x83(e3)
The external resistance Rds is not important in an element having a large channel length due to large channel resistance Rch. In a refined element, however, the external resistance Rds is important due to small channel resistance Rch. In particular, resistance components of electrodes are unignorable. A gate insulator film OX having a thickness Tox is interposed between a gate electrode and a semiconductor layer.
However, a method of extracting these parameters related to the MOSFET in a mutually matching form has not been known in general. A highly precise extraction method has been devised as to the channel shortening DL and the external resistance Rds as described in Japanese Patent Application No. 10-213019 (1998) (hereinafter referred to as literature 1), for example, and a method of precisely extracting the channel narrowing DW has been devised as described in Japanese Patent Application No. 10-239148 (1998) (hereinafter referred to as literature 2), for example. In relation to the mobility xcexc and the saturation velocity Vsat, however, there is known no method of performing extraction in a form matching with the remaining parameters.
In relation to the mobility xcexc, for example, the Moneda method is generally known as a typical extraction method. The Moneda method is disclosed in F. H. De La Moneda, H. N. Kothcha and M. Shatzkes, xe2x80x9cMeasurement of MOSFET Constantsxe2x80x9d, IEEE Elect. Dev. Lett., EDL-3(1), pp. 10, 1982 (hereinafter referred to as literature 3). In the Moneda method, the following equation (1) is assumed as the model of the mobility xcexc:                     μ        =                  μ0                      1            +                          θ                                            (                                  Vgs                  -                  Vth                                )                                                                        (        1        )
where Vgs represents a gate-to-source voltage, xcexc0 represents the mobility xcexc at the time when the gate-to-source voltage Vgs matches with the threshold voltage Vth, and xcex8 represents a parameter.
In this case, the total resistance Rtot is given by the following equation (2):                     Rtot        =                  Rds          +                      S                                      (                              θ                +                                  1                                      Vgs                    -                    Vth                    -                                          Vds                      /                      2                                                                                )                                                          (        2        )
where the parameter S is given by the following equation (3):                     S        =                              Lm            -            DL                                μ0            ·            Cox            ·            Weff                                              (        3        )
where the parameter Cox is the capacitance of the gate insulator film OX.
On the basis of the equation (2), the mobility xcexc is extracted along the following procedure:
Step 1: Drain-source current Ids vs. gate-to-source voltage Vgs characteristics (Idsxe2x88x92Vgs characteristics) in a linear region of a plurality of transistors (MOSFETs) different only in channel length from each other are measured.
Step 2: An Rtotxe2x88x921/(Vgsxe2x88x92Vthxe2x88x92Vds/2) characteristic is plotted for each transistor as shown in FIG. 33, for performing linear fitting. Vds represents a drain-to-source voltage. In this case, slope of the straight line corresponds to S in the equation (3), and the vertical axis intercept is xcex8xc2x7S+Rds (=R).
Step 3: From the result in the step 1, an Sxe2x88x92Lm characteristic is plotted as shown in FIG. 34, for performing linear fitting. In this case, slope of the straight line is 1/(xcexc0xc2x7Coxxc2x7Weff) (=C).
Step 4: Assuming that Wm≈Weff and Cox=xcex5ox/Tox, xcexc0 is given by Tox/(Cxc2x7xcex5oxxc2x7Wm) from the result in the step 3, where xcex5ox represents a factor of proportionality between the capacitance Cox and 1/Tox. An actual value may be given to Cox.
Step 5: An Rxe2x88x92S characteristic is plotted as shown in FIG. 35 from the result in the step 1, for performing linear fitting. In this case, slope of the straight line is xcex8.
In the Moneda method, as hereinabove described, primary deterioration is assumed in relation to the mobility xcexc, for extracting the channel shortening DL, the external resistance Rds and the parameters xcexc0 and xcex8 related to the mobility xcexc at the time when the gate-to-source voltage Vgs is around the threshold voltage Vth. Hence, a secondary mobility deterioration factor or external resistance Rds having Vgs dependency cannot be extracted.
This also applies to a well-known extraction method related to the velocity saturation effect. In a conventional typical method extracting a parameter related to the saturation effect, the following equation (4) is employed:                               1          β0                =                              Leff            +                          U1              ·              Vds                                            μ0            ·            Cox            ·            Weff                                              (        4        )
where U1 represents a velocity saturation coefficient.
On the basis of the equation (4), the velocity saturation effect is extracted along the following procedure:
Step 1: Idsxe2x88x92Vgs characteristics in a linear region of a plurality of transistors (MOSFETs) different only in channel length from each other are measured.
Step 2: For each transistor, xcex2 is regarded as (maximum value of slope of Idsxe2x88x92Vds characteristics)Vds.
Step 3: A 1/xcex20-Leff characteristic is plotted as shown in FIG. 36, for performing linear fitting. In this case, slope of the straight line is 1/(xcexcxc2x7Coxxc2x7Weff) (=A). The vertical axis intercept is U1xc2x7Vds/xcexc0xc2x7Coxxc2x7Weff (=B).
Step 4: The velocity saturation coefficient U1 is given by B/(Axc2x7Vds) from the result in the step 3.
However, it is said that this method is problematic in extraction precision since the velocity saturation coefficient U1 is not extracted in a form matching with the remaining E-T data but influenced by the external resistance Rds.
In the conventional extraction methods, as hereinabove described, the mobility xcexc and the velocity saturation effect are not extracted in a form matching with extraction of the parameters DL, Rds, DW etc., and hence deterioration of precision is disadvantageously unavoidable.
A characteristic extraction device according to a first aspect of the present invention, extracting a parameter expressing a velocity saturation effect of a MOS transistor, comprises (a) an effective channel length extraction part receiving a signal expressing measured data of a characteristic of the MOS transistor and extracting an effective channel length of the MOS transistor for at least two drain-to-source voltages on the basis of the signal, and (b) a parameter calculation part calculating the parameter on the basis of the extracted effective channel length and outputting a signal expressing its value.
In the device according to the first aspect, since the parameter expressing the velocity saturation effect is extracted on the basis of the effective channel length, the parameter is precisely extracted in a form matching with channel shortening and external resistance, which are other parameters forming E-T data.
According to a second aspect of the present invention, the parameter calculation part (b) includes (b-1) a U1 calculation part calculating a velocity saturation coefficient U1 as the parameter expressing the velocity saturation effect by regarding the effective channel length as a function Le(Vds) of the drain-to-source voltages Vds and assuming the following relation with another parameter Leff:
Le(Vds)=Leff+U1xc2x7Vds
According to the second aspect, the velocity saturation coefficient is precisely extracted as the parameter expressing the velocity saturation effect in a form matching with channel shortening and external resistance.
According to a third aspect of the present invention, at least two drain-to-source voltages are two drain-to-source voltages Vds1 and Vds2, and the U1 calculation part (b-1) includes (b-1-1) a device part expressing a set of values Le(Vds1) and Le(Vds2) of the function calculated by using the relation for the two drain-to-source voltages Vds1 and Vds2, as a data point on a graph for each of at least two MOS transistors, (b-1-2) a device part expressing a group of the data points in a straight line on the graph, and (b-1-3) a device part obtaining the velocity saturation coefficient U1 by dividing the value Le(Vds2) at the Le(Vds1) being about zero on the straight line by the difference Vds2xe2x88x92Vds1 between the value Vds1 and the value Vds2.
According to the third aspect, the velocity saturation coefficient, which is obtained on the basis of an intercept on a straight line expressing a set of values Leff(Vds1) and Leff (Vds2) of the function on a graph or an approximate value thereof, is readily and precisely provided.
According to a fourth aspect of the present invention, at least two drain-to-source voltages are two drain-to-source voltages Vds1 and Vds2, and the U1 calculation part (b-1) includes (b-1-1) a device part expressing a set of a ratio Le(Vds2)/Le(Vds1) and an inverse 1/Le(Vds1) obtained from values Le(Vds1) and Le(Vds2) of the function calculated by using the relation for the two drain-to-source voltages Vds1 and Vds2, as a data point on a graph for each of at least two MOS transistors, (b-1-2) a device part expressing a group of the data points in a straight line on the graph, and (b-1-3) a device part obtaining the velocity saturation coefficient U1 by dividing slope of the straight line by the difference Vds2xe2x88x92Vds1 between the value Vds1 and the value Vds2.
According to the fourth aspect, the velocity saturation coefficient, which is obtained on the basis of slope of the straight line expressing the set of Leff(Vds2)/Leff (Vds1) and I/Leff(Vds1) on the graph, is readily and precisely provided.
According to a fifth aspect of the present invention, the effective channel length extraction part (a) includes (a-1) a device part receiving signals expressing measured data of characteristics of at least two MOS transistors different only in channel length from each other as the signals expressing the measured data and obtaining data related to drain-to-source currents Ids vs. gate-to-source voltages Vgs under at least two drain-to-source voltages Vds as to at least two MOS transistors different only in the channel length from each other on the basis of the signals, (a-2) a device part expressing a set of total resistance defined as Vds/Ids and the channel length for each of at least two MOS transistors, each of at least two drain-to-source voltages Vds and each of at least two gate overdrives Vgt as data points on a graph, (a-3) a device part individually expressing each group of the data points having both of the drain-to-source voltage Vds and the gate overdrive Vgt in common in a straight line, and (a-4) a device part calculating the effective channel length for each of at least two drain-to-source voltages Vds from an intersection between the straight lines having different gate overdrives Vgt.
According to the fifth aspect, the effective channel length, which is calculated from the intersection between the straight lines expressing total resistance vs. channel length with different gate overdrives on the graph, is readily and precisely provided.
According to a sixth aspect of the present invention, the characteristic extraction device further comprises (c) an f extraction part receiving signals expressing measured data of characteristics of at least two MOS transistors different only in channel length from each other and extracting channel resistance f(Vgt) per unit effective channel length as a function of a gate overdrive Vgt on the basis of the signals, (d) a DW extraction part receiving signals of measured data of characteristics of at least two MOS transistors different only in channel width from each other and extracting channel narrowing DW(Vgt) as a function of the gate overdrive Vgt on the basis of the signals, (e) a xcexc calculation part deciding the parameter so as to fit mobility xcexc (Vgt) as a function of the gate overdrive Vgt expressed by the following relations employing a capacitance Cox of a gate insulator film, a drain-to-source voltage Vds and a channel width Wm:             1              μ                          (          Vgt          )                      =                  h                          (          Vgt          )                    ·      Cox      ·              (                  Vgt          -                      Vds            2                          )              and                    h                          (          Vgt          )                    =                        f                                (            Vgt            )                          ·                  (                      Wm            -                          DW                                            (                Vgt                )                                              )                      ,          xe2x80x83            and
(f) a Vsat calculation part calculating a saturation velocity given by a function of the velocity saturation coefficient U1 calculated in the U1 calculation part (b-1) and the parameter decided in the F calculation part (e) as a parameter expressing the velocity saturation effect and outputting a signal expressing the value thereof.
According to the sixth aspect, the saturation velocity is extracted as the parameter expressing the velocity saturation effect on the basis of the parameters expressing the velocity saturation coefficient and the mobility, whereby the parameter expressing the velocity saturation effect is precisely provided in a form matching with channel shortening, external resistance and channel narrowing.
The present invention is also directed to a characteristic extraction device. A characteristic extraction device according to a seventh aspect of the present invention, extracting a parameter expressing mobility of a MOS transistor, comprises (a) an f extraction part receiving signals expressing measured data of characteristics of at least two MOS transistors different only in channel length from each other and extracting channel resistance f(Vgt) per unit effective channel length as a function of a gate overdrive Vgt on the basis of the signals, (b) a DW extraction part receiving signals expressing measured data of characteristics of at least two MOS transistors different only in channel width from each other and extracting channel narrowing DW(Vgt) as a function of the gate overdrive Vgt on the basis of the signals, and (c) a xcexc calculation part deciding the parameter to fit mobility xcexc(Vgt) as a function of the gate overdrive Vgt expressed by the following relations with a capacitance Cox of a gate insulator film, a drain-to-source voltage Vds and a channel width Wm and outputting a signal expressing the value thereof:             1              μ                          (          Vgt          )                      =                  h                          (          Vgt          )                    ·      Cox      ·              (                  Vgt          -                      Vds            2                          )              and            h                    (        Vgt        )              =                  f                          (          Vgt          )                    ·              (                  Wm          -                      DW                                      (              Vgt              )                                      )
According to the seventh aspect, the parameter expressing the mobility, which is decided on the basis of the channel resistance (hereinafter referred to as xe2x80x9cparameter fxe2x80x9d) per unit effective channel length and channel narrowing, is precisely provided in a form matching with channel shortening, external resistance and channel narrowing.
According to an eighth aspect of the present invention, the f extraction part (a) includes (a-1) a device part obtaining data related to drain-to-source current Ids vs. gate-to-source voltage Vgs as to each of at least two MOS transistors different only in the channel length from each other, (a-2) a device part expressing a set of total resistance defined as Vds/Ids and the channel length for each of at least two MOS transistors different only in the channel length from each other and each of at least two gate overdrives Vgt as a data point on a graph, (a-3) a device part individually expressing each group of the data points having the gate overdrive Vgt in common in a straight line, and (a-4) a device part calculating channel resistance f(Vgt) per the, unit effective channel length as a function of the gate overdrives Vgt from slopes of the straight lines corresponding to at least two gate overdrives Vgt respectively.
According to the eighth aspect, the parameter f, which is calculated from slope of the straight lines expressing total resistance vs. channel length with different gate overdrives on the graph, is readily and precisely provided.
According to a ninth aspect of the present invention, the DW extraction part (b) includes (b-1) a device part obtaining data related to drain-to-source current Ids vs. gate-to-source voltage Vgs as to each of at least two MOS transistors different only in the channel width from each other, (b-2) a device part expressing a set of conductance defined as Ids/Vds or the drain-to-source current Ids itself and the channel width for each of at least two MOS transistors different only in the channel width from each other and each of at least two gate overdrives Vgt as a data point on a graph, (b-3) a device part individually expressing each group of the data points having the gate overdrives Vgt in common in a straight line, and (b-4) a device part calculating the channel narrowing DW(Vgt) as a function of the gate overdrives Vgt from intercepts of a coordinate axis, expressing the channel width, of the straight lines corresponding to at least two gate overdrives Vts respectively.
According to the ninth aspect, channel narrowing, which is calculated from the intercepts on the straight lines expressing the relation between the conductance (or drain-to-source current) and the channel width on the graph, is readily and precisely provided.
The present invention is also directed to a characteristic evaluation device, A characteristic evaluation device according to a tenth aspect of the present invention, evaluating characteristics of a circuit having a MOS transistor, includes (1) an E-T data extraction part, extracting E-T data of the MOS transistor, including (1-1) the characteristic extraction device according to any of the first to sixth aspects of the present invention and (1-2) the characteristic extraction device according to any of the seventh to ninth aspects of the present invention, (2) a principal component analysis part extracting independent variables by executing principal component analysis on the E-T data extracted in the E-T data extraction part (1), (3) a Monte Carlo calculation part supplying statistical dispersion to the E-T data by supplying statistical dispersion to at least part of the independent variables, and (4) a circuit simulator receiving a signal expressing the statistically dispersed E-T data obtained in the Monte Carlo calculation part (3) and a signal expressing circuit connection information which is information related to connection conditions between elements forming the circuit and executing circuit simulation related to the circuit.
According to the tenth aspect, circuit simulation is performed in consideration of statistical dispersion with mutually matching E-T data, whereby the characteristics of the circuit can be evaluated in high precision.
The present invention is also directed to a semiconductor device. A semiconductor device according to an eleventh aspect of the present invention is manufactured through the characteristic extraction device according to any of the first to ninth aspects of the present invention or the characteristic evaluation device according to the tenth aspect of the present invention.
The semiconductor device according to the eleventh aspect, which is manufactured through the device according to any of the first to ninth aspects, can be efficiently completed to a product having guaranteed characteristics.
A semiconductor device according to a twelfth aspect of the present invention comprises an integrated circuit, including a MOS transistor, formed on a semiconductor substrate, and at least three MOS transistors, formed on the semiconductor substrate, separated from the integrated circuit, while at least three MOS transistors include a set of MOS transistors different only in channel length as mask length from each other and a set of MOS transistors different only in channel width as mask width from each other while allowing overlapping, conditions provided by the following relations:             Lm      L0         greater than                   "LeftBracketingBar"                  Δ                                xe2x80x83                              L                "RightBracketingBar"            r                  Lm      L0         greater than                             1          r                ·                              "LeftBracketingBar"                          Δ                                            xe2x80x83                                          Rds                        "RightBracketingBar"                    Rdsi                          Lmi                  Wm      L0         greater than                   "LeftBracketingBar"                  Δ                                xe2x80x83                              W                "RightBracketingBar"            r
are satisfied for the set of MOS transistors different only in the channel length from each other in relation to deviation xcex94L between a first transistor having the maximum channel length and a second transistor having the minimum channel length in difference between finished length and mask length related to channel length, a mask length LmLO of the first transistor, deviation xcex94W between the first transistor and the second transistor in channel width as finished width, a channel width WmLO as a mask width of the first transistor, external resistance Rdsi of the second transistor, deviation xcex94Rds between the first transistor and the second transistor in external resistance, a channel length Lmi as a mask length of the second transistor, and an allowable value r for an extraction error of channel shortening relative to an effective gate length, and conditions provided by the following relations:             Lm      W1         greater than                   "LeftBracketingBar"                  Δ                                xe2x80x83                              L                "RightBracketingBar"            r                  Wm      W1         greater than                   "LeftBracketingBar"                  Δ                                xe2x80x83                              W                "RightBracketingBar"            r
are satisfied for the set of MOS transistors different only in the channel width from each other in relation to deviation xcex94W between a first transistor having the maximum channel width and a second transistor having the minimum channel width in difference between finished width and mask width related to channel width, a mask width WmWI of the first transistor, deviation xcex94L between the first transistor and the second transistor in channel width as finished width, a channel length LmWI as a mask length of the first transistor, and an allowable value r for an extraction error of channel narrowing relative to an effective gate width.
According to the twelfth aspect, at least three MOS transistors satisfying prescribed conditions related to channel dimensions are formed on the same semiconductor substrate independently of the integrated circuit, whereby E-T data related to MOS transistors forming the integrated circuit can be extracted with prescribed precision.
The present invention is also directed to a characteristic extraction method. A characteristic extraction method according to a thirteenth aspect of the present invention, extracting a parameter expressing a velocity saturation effect of a MOS transistor, comprises steps of (a) extracting an effective channel length for at least two drain-to-source voltages, and (b) calculating the parameter on the basis of the extracted effective channel length.
According to the thirteenth aspect, since the parameter expressing the velocity saturation effect is extracted on the basis of the effective channel length, the parameter is precisely extracted in a form matching with channel shortening and external resistance, which are other parameters forming the E-T data.
According to a fourteenth aspect of the present invention, the step (b) includes a step (b-1) of regarding the effective channel length as a function Le(Vds) of the drain-to-source voltages Vds and assuming the following relation with another parameter Leff:
Le(Vds)=Leff+U1xc2x7Vds
thereby calculating a velocity saturation coefficient U1 as the parameter expressing the velocity saturation effect.
According to the fourteenth aspect, the velocity saturation coefficient is precisely extracted as the parameter expressing the velocity saturation effect in a form matching with channel shortening and external resistance.
According to a fifteenth aspect of the present invention, the at least two drain-to-source voltages are two drain-to-source voltages Vds1 abd Vds2, and the step (b-1) includes steps of (b-1-1) expressing a set of values Le(Vds1) and Le(Vds2) of the function calculated by using the relation for the two drain-to-source voltages Vds1 and Vds2 as a data point on a graph for each of at least two MOS transistors, (b-1-2) expressing a group of the data points in a straight line on the graph, and (b-1-3) obtaining the velocity saturation coefficient U1 by dividing the value Le(Vds2) at the Le(Vds1) being about zero on the straight line by the difference Vds2xe2x88x92Vds1 between Vds1 and Vds2.
According to the fifteenth aspect, the velocity saturation coefficient, which is obtained on the basis of an intercept on a straight line expressing a set of values Leff (Vds1) and Leff(Vds2) of the function on a graph or an approximate value thereof, is readily and precisely provided.
According to a sixteenth aspect of the present invention, the at least two drain-to-source voltages are two drain-to-source voltages Vds1 and Vds2, and the step (b-1) includes steps of (b-1-1) expressing a set of a ratio Le(Vds2)/Le(Vds1) and an inverse 1/Le(Vds1) obtained from values Le(Vds1) and Le(Vds2) of the function calculated by using the relation for the two drain-to-source voltages Vds1 and Vds2 as data a point on a graph for each of at least two MOS transistors, (b-1-2) expressing a group of the data points in a straight line on the graph, and (b-1-3) obtaining the velocity saturation coefficient U1 by dividing slope of the straight line by the difference Vds2xe2x88x92Vds1 between the value Vds1 and the value Vds2.
According to the sixteenth aspect, the velocity saturation coefficient, which is obtained on the basis of slope of the straight line expressing the set of Leff(Vds1)/Leff(Vds2) and 1/Leff(Vds1) on the graph, is readily and precisely provided.
According to a seventeenth aspect of the present invention, the step (a) includes steps of (a-1) receiving data related to drain-to-source currents Ids vs. gate-to-source voltages Vgs under at least two drain-to-source voltages Vds as to at least two MOS transistors different only in channel length from each other, (a-2) expressing a set of total resistance defined as Vds/Ids and the channel length for each of at least two MOS transistors, each of at least two drain-to-source voltages Vds and each of at least two gate overdrives Vgt as data points on a graph, (a-3) individually expressing each group of the data points having both of the drain-to-source voltage Vds and the gate overdrive Vgt in common in a straight line, and (a-4) calculating the effective channel length for each of at least two drain-to-source voltages Vds from an intersection between the straight lines having the different gate overdrives Vts.
According to the seventeenth aspect, the effective channel length, which is calculated from the intersection of the straight lines expressing total resistance vs. channel length with different gate overdrives on the graph, is readily and precisely provided.
The present invention is also directed to a characteristic extraction method. A characteristic extraction method according to an eighteenth aspect of the present invention, extracting a parameter expressing mobility of a MOS transistor, comprises steps of (a) extracting channel resistance f(Vgt) per unit effective channel length as a function of a gate overdrive Vgt from at least two MOS transistors different only in channel length from each other, (b) extracting channel narrowing DW(Vgt) as a function of the gate overdrive Vgt from at least two MOS transistors different only in channel width from each other, and (c) deciding the parameter to fit mobility xcexc(Vgt) as a function of the gate overdrive Vgt expressed by the following relations with a capacitance Cox of a gate insulator film, a drain-to-source voltage Vgs and a channel width Wm:             1              μ                          (          Vgt          )                      =                  h                          (          Vgt          )                    ·      Cox      ·              (                  Vgt          -                      Vds            2                          )              and            h                    (        Vgt        )              =                  f                          (          Vgt          )                    ·                        (                      Wm            -                          DW                                            (                Vgt                )                                              )                .
According to the eighteenth aspect, the parameter expressing the mobility, which is decided on the basis of the channel resistance (hereinafter referred to as xe2x80x9cparameter fxe2x80x9d) per unit effective length and channel narrowing, is precisely provided in a form matching with channel shortening, external resistance and channel narrowing.
According to a nineteenth aspect of the present invention, the step (a) includes steps of (a-1) obtaining data related to drain-to-source current Ids vs. gate-to-source voltage Vgs as to each of at least two MOS transistors different only in channel length from each other, (a-2) expressing a set of total resistance defined as Vds/Ids and the channel length for each of at least two MOS transistors different only in the channel length from each other and each of at least two gate overdrives Vgt as a data point on a graph, (a-3) individually expressing each group of the data points having the gate overdrive Vgt in common in a straight line, and (a-4) calculating channel resistance f(Vgt) per the unit effective channel length as a function of the gate overdrives Vgt from slope of the straight lines corresponding to at least two gate overdrives Vgs respectively.
According to the nineteenth aspect, the parameter f, which is calculated from slope of the straight lines expressing the total resistance vs. channel lengths with different gate overdrives on the graph, is readily and precisely provided.
According to a twentieth aspect of the present invention, the step (b) includes steps of (b-1) obtaining data related to drain-to-source current Ids vs. gate-to-source voltage Vgs as to each of the at least two MOS transistors different only in channel width from each other, (b-2) expressing a set of conductance defined as Ids/Vds or drain-to-source current Ids itself and the channel width for each of at least two MOS transistors different only in the channel width from each other and each of at least two gate overdrives Vgt as a data point on a graph, (b-3) individually expressing each group of the data points having the gate overdrive Vgt in common in a straight line, and (b-4) calculating the channel narrowing DW(Vgt) as a function of the gate overdrive Vgt from intercepts of a coordinate axis, expressing the channel width, of the straight lines corresponding to at least two gate overdrives Vts respectively.
According to the twentieth aspect, channel narrowing, which is calculated from the intercepts on the straight lines expressing the relation between the conductance (or drain-to-source current) and the channel widths on the graph, is readily and precisely provided.
A characteristic extraction method according to a twenty-first aspect of the present invention, extracting a parameter expressing a velocity saturation effect of a MOS transistor, comprises steps of (A) extracting the velocity saturation coefficient U1 with the characteristic extraction method according to any of the fourteenth to sixteenth aspects of the present invention, (B) extracting the parameter expressing the mobility with the characteristic extraction method according to any of the eighteenth to twentieth aspects of the present invention, and (C) calculating a saturation velocity given by a function of the velocity saturation coefficient U1 extracted in the step (A) and the parameter extracted in the step (B) as the parameter expressing the velocity saturation effect.
According to the twenty-first aspect, the saturation velocity, extracted as the parameter expressing the velocity saturation effect on the basis of the parameters expressing the velocity saturation coefficient and the mobility, is precisely provided in a form matching with channel shortening, external resistance and channel narrowing.
According to a twenty-second aspect of the present invention, at least two MOS transistors different only in the channel length from each other are at least two MOS transistors different only in channel length as mask length from each other, and conditions provided by the following relations:             Lm      L0         greater than                   "LeftBracketingBar"                  Δ                                xe2x80x83                              L                "RightBracketingBar"            r                  Lm      L0         greater than                             1          r                ·                              "LeftBracketingBar"                          Δ                                            xe2x80x83                                          Rds                        "RightBracketingBar"                    Rdsi                          Lmi                  Wm      L0         greater than                   "LeftBracketingBar"                  Δ                                xe2x80x83                              W                "RightBracketingBar"            r
are satisfied in relation to deviation AL between a first transistor having the maximum channel length and a second transistor having the minimum channel length in difference between finished length and mask length related to channel length, a mask length LmLO of the first transistor, deviation xcex94W between the first transistor and the second transistor in channel width as finished width, a channel width WmLO as a mask width of the first transistor, external resistance Rdsi of the second transistor, deviation xcex94Rds between the first transistor and the second transistor in external resistance, a channel length Lmi as a mask length of the second transistor, and an allowable value r for an extraction error of channel shortening relative to an effective gate length.
According to the twenty-second aspect, conditions related to channel sizes are provided as to the MOS transistors subjected to extraction of E-T data, whereby extraction can be performed within a prescribed range of extraction errors.
According to a twenty-third aspect of the present invention, at least two MOS transistors different only in the channel width from each other are at least two MOS transistors different only in channel width as mask width from each other, and conditions provided by the following relations:             Lm      W1         greater than                   "LeftBracketingBar"                  Δ                                xe2x80x83                              L                "RightBracketingBar"            r                  Wm      W1         greater than                   "LeftBracketingBar"                  Δ                                xe2x80x83                              W                "RightBracketingBar"            r
are satisfied in relation to deviation xcex94W between a first transistor having the maximum channel width and a second transistor having the minimum channel width in difference between finished width and mask width related to channel width, a mask width WmWI of the first transistor, deviation xcex94L between the first transistor and the second transistor in channel length as finished length, a channel length LmWI as a mask length of the first transistor, and an allowable value r for an extraction error of channel narrowing relative to an effective gate width.
According to the twenty-third aspect, conditions related to channel sizes are provided as to the MOS transistors subjected to extraction of E-T data, whereby extraction can be performed within a prescribed range of extraction errors.
The present invention is also directed to a characteristic evaluation method. A characteristic evaluation method according to a twenty-fourth aspect of the present invention, evaluating characteristics of a circuit having a MOS transistor, comprises steps of (1) extracting E-T data of the MOS transistor, including steps of (1-1) extracting the parameter expressing the velocity saturation effect of the MOS transistor with the characteristic extraction method according to any of the thirteenth to seventeenth aspects of the present invention, and (1-2) extracting the parameter expressing the mobility of the MOS transistor with the characteristic extraction method according to any of the eighteenth to twentieth aspects of the present invention, (2) extracting independent variables by executing principal component analysis on the E-T data extracted in the step (1), (3) supplying statistical dispersion to the E-T data by supplying statistical dispersion to at least part of the independent variables, and (4) executing circuit simulation with the statistically dispersed E-T data obtained in the step (3) and circuit connection information which is information related to connection conditions between elements forming the circuit.
According to the twenty-fourth aspect, circuit simulation is performed in consideration of statistic dispersion with mutually matching E-T data, whereby the characteristics of the circuit can be evaluated in high precision.
The present invention is also directed to a recording medium. A recording medium according to a twenty-fifth aspect of the present invention records a program, 15 readable by a computer, defining an operation of the computer, and the recording medium records a program, as the program, defining the characteristic extraction method according to any of the thirteenth to twenty-third aspects of the present invention or the characteristic evaluation method according to the twenty-fourth aspect of the present invention.
According to the twenty-fifth aspect, the recording medium records the program defining the method according to any of the thirteenth to twenty-fourth aspects, whereby the method according to any of the thirteenth to twenty-fourth aspects can be carried out by connecting the recording medium to the computer.
The present invention has been proposed in order to solve the aforementioned problems of the prior art, and an object thereof is to obtain a characteristic extraction technique and a characteristic evaluation technique extracting E-T data of a MOSFET in a mutually matching form thereby enabling highly precise characteristic evaluation, and to provide a semiconductor device manufactured through these techniques, a recording medium suitable for these techniques, and a semiconductor device enabling precise extraction of E-T data through the characteristic extraction technique and the characteristic evaluation technique.

Characteristic extraction device, characteristic evaluation device, characteristic extraction method, characteristic evaluation method, recording medium and semiconductor device


Sulfhydryl odors in organothiophosphate formulations are suppressed by treatment of the thiophosphate compound (e.g., bensulide) during preparation of the formulation with a selected emulsifier agent, ethoxylated tallow amine. The amine and any reacting products resulting from the treatment are retained in the final formulation. The amine will continue to react with the mercaptan and other sulfhydryl compounds formed by the continuing degradation of the thiophosphate compound, thereby providing further odor control.

1. Field of the Invention
The present invention concerns thiophosphate-containing biocide preparations, and, more particularly, agricultural formulations of biocidal thiophosphate that have a reduced tendency to emit sulfurous vapors.
2. Description of the Related Art
Organothiophosphate compounds refer generally to those containing carbon-phosphorus bonds in which the phosphorus component is also bonded to one or more sulfur atoms. Many of these compounds function as pesticides. Hence, Organothiophosphate insecticides are well known and widely used for crop protection. Included among these compounds are, for example, the commercially available preparations of bensulide known under the trademarks Bensumec™, Betamec™, Betasan™, Disan™, Exporsan™, Prefar™, Pre-San™, and others.
Unfortunately, the organothiophosphate-type insecticides typically contain sulfhydryl compounds, such as thiols or mercaptans, that produce a well known and irritating sulfurous (i.e., "rotten egg") odor. The presence of compounds such as mercaptans in formulations of these insecticides is due to a number of factors. In some instances, thiophosphate analogs of the organothiophosphate compound are present as by-products of the synthesis, with these analog species tending to decompose to mercaptans. Moreover, organothiophosphate compounds tend to degrade or decompose over time to produce mercaptans, particularly when subjected to heating. Regardless of how the sulfhydryl odor is produced, it is detrimental from an environment point of view, as well as from handling and field application perspectives.
Bensulide technical (S—(O, O-diisopropyl phosphorodithiotate) ester of N-(2-mercaptoethyl) benzenesulfonamide) is the active ingredient in several organothiophosphate pesticide formulations. Bensulide technical is synthesized at a purity range from 92.0% to 95.0%. The remaining 6% percent are process impurities, with some of these impurities being mercaptans and sulfides produced from the reaction of the dithiophosphoric acid.
Bensulide is not considered to be a very stable compound. Indeed, bensulide undergoes an autocatalytic decomposition such that, after 10-20% of the material has decomposed, a large increase in decomposition rate occurs. Decomposition products are known to be mercaptans and sulfides.
Impurities in bensulide have been purged and trapped for analysis by gas chromatography/mass spectrometry (for example, see Bobbi Kahn, Analysis & Certification of Product Ingredients in Betasan, Stauffer Chemical Company, Richmond Research Center (RCC-9/2/86 86-88). The largest impurity was identified as hydrogen sulfide (H2S) and was the only impurity in the headspace analysis that was not found in the actual bensulide composite sample.
Although there are a number a ways known in the art to control various chemical odors, there are often unknown or unwanted chemical changes or other side effects that occur. Moreover, many methods are time consuming, involve hazardous materials, and are relatively expensive to carry out on commercially useful scales, especially when filtration/separation and disposal costs are considered. Thus, there remains a need in the art for new and improved ways for controlling odor in organothiophosphate formulations.

Control of sulfhydryl compound odor in organothiophosphate formulations


Provided is a novel compound which shows an antagonistic effect against T-type calcium channels, and is useful as a pharmaceutical product.

Intracellular calcium is an important factor causing a large variety of physiological responses such as neuronal excitement, muscle contraction, hormone secretion, fertilization, immune response, cell motility, and cell death; and the concentration is regulated by means of ion channels or pumps, such as voltage-dependent calcium channels and receptor-operated calcium channels. The voltage-dependent calcium channels are calcium channels which are opened and closed depending on the change of the potential difference between inside and outside of the cell, and exist on the cellular membrane of muscles or nerve cells. The voltage-dependent calcium channels are currently classified into L-type, T-type, N-type, P/Q-type, and R-type calcium channels, based on electrophysiological characteristics and pharmacological characteristics. Unlike L-type, N-type, P/Q-type and R-type calcium channels, which are classified as medium potential and high potential activated calcium channels in view of the voltage activation threshold, T-type calcium channels are activated at a potential that is close to the resting membrane potential. Therefore, the T-type calcium channels is believed to play a role as triggers for influx of calcium into the cell, and to participate in the pacemaker activity, production of low-threshold calcium spikes, and burst firing.
T-type calcium channels include three subtypes such as Cav3.1 (α1G), Cav3.2 (α1H) and Cav3.3 (α1I); and expression of the channel in, for example, the brain, nerve tissues, heart, kidneys, liver, pancreas, smooth muscles, testicles has been reported. It has been suggested that activation of the T-type calcium channels in these organs and tissue cells described above may cause intracellular calcium overload, and may participate in the onset and progress of various pathological conditions such as, for example, hypertension, tachyarrhythmia including atrial fibrillation, cardiac hypertrophy, cardiac failure, renal dysfunction, and cancers. Therefore, T-type calcium channel antagonistic drugs are believed to be effective in the treatment or prevention of these diseases (Non-Patent Documents 1 to 5).
One of known T-type calcium channel antagonistic drugs is mibefradil, however, this drug is not commercially available at present due to problems such as drug interaction. Furthermore, for example, Patent Document 1 discloses a 3,4-dihydroquinazoline derivative; Patent Document 2 discloses a quinazoline derivative; Patent Document 3 discloses a pyridylamide derivative; Patent Documents 4 and 5 disclose 3-fluoropiperidine derivatives; Patent Document 6 discloses an indole derivative; Patent Document 7 discloses an oxadiazole derivative; Patent Documents 8 and 9 disclose thiazole derivatives; Patent Document 10 discloses an isoxazole derivative; and Patent Document 11 discloses a 1,3-dioxoindole derivative, as the T-type calcium channel antagonistic drugs. However, these compounds have not been hitherto put to clinical use.

Abstract: A compound represented by general formula (I), and a pharmaceutical agent containing the same, are disclosed:

Abstract: wherein n represents the number of nitrogen atoms contained in the 6-membered fused aromatic ring, and is 0, 1 or 2; p represents the number of nitrogen atoms contained in the 6-membered aromatic ring, and is 0 or 1; X represents an oxygen atom, —SO2— or —N(R9)—; and R1 to R5 each represents a hydrogen atom or other substituents.


This invention is a pedicle screw (1), comprising a threaded rod (2) having a longitudinal axis (XX) and a head (4) in which there is a channel (5) adapted to receive a spinal support rod, and a means for blocking the rod; the channel is formed such that its longitudinal axial plane (P) is inclined relative to the longitudinal axis (XX) of the threaded rod. The head (4) of the screw being made up of two flanks (6, 7), a threaded hole (11) is formed in one of them; the inclination of the channel (5) relative to the axis of the treaded rod (2) makes it possible to place a tool for blocking the rod in the channel without this tool coming into contact with the muscle tissues delimiting the incision. Moreover, the threaded seat (11) permits the positioning of instruments without obstructing the channel for passage of the rod.

In order to maintain bones in specified orientation relationship, there are various known techniques for screwing a bone-fixing screw into bones in various parts of the body, such as the spine, and combining rods with said implanted screw so that the rods will be positioned alongside the bones. The screws of the prior art are provided with a rod-fixing means. The rod-fixing means have an opening that is located either parallel to the axial direction of thread or on the side thereof, but these solutions have problems; inserted rods slip out of place with the parallel arrangement, while with the latter, operators have to insert a rod at right angles to the axis of the thread, which can prove to be a difficult procedure.

Pedicle screws with inclined channels to hold support rods


A graphite-based negative electrode active material including a first graphite particle being spheroidized and a second graphite particle having a roundness lower than the roundness of the first graphite particle, wherein the content of the second graphite particle based on the sum of the first graphite particle and the second graphite particle is in the range of 1 to 30% by mass, the ratio of a median particle diameter (D50) to a particle diameter at 5 cumulative % (D5), D50/D5, in a cumulative distribution of the first graphite particle is smaller than the ratio of a median particle diameter (D50) to a particle diameter at 5 cumulative % (D5), D50/D5, in a cumulative distribution of the second graphite particle, and the tap density in saturation of the particle mixture of the first graphite particle and the second graphite particle is higher than both the tap density in saturation of the first graphite particle and the tap density in saturation of the second graphite particle.

Lithium ion secondary batteries have high energy density and excellent charge/discharge cycle characteristics, and are thus widely used for a power supply for compact mobile devices such as cellular phones and laptop computers. In addition, the recent increasing environmental considerations and growing consciousness of energy saving have been promoting a demand for large batteries having a large capacity and a long life in the fields of electric vehicles, hybrid electric vehicles, power storage, etc.
In general, a lithium ion secondary battery primarily consists of: a negative electrode including a negative electrode active material of a carbon material capable of intercalating and deintercalating a lithium ion; a positive electrode including a positive electrode active material of a lithium composite oxide capable of intercalating and deintercalating a lithium ion; a separator separating the negative electrode and the positive electrode; and a non-aqueous electrolytic solution prepared by dissolving a lithium salt in a non-aqueous solvent.
Amorphous carbon or graphite is used for the carbon material used as the negative electrode active material, and graphite is typically used particularly in an application which requires a high energy density.
For examples, Patent Literature 1 discloses that in order to obtain a non-aqueous electrolytic solution secondary battery which exhibits a high capacity and a high charge/discharge efficiency, a negative electrode active material is used which includes a carbon material containing at least two materials of a scale-shaped graphite particle and a graphite material the surface of which is covered with amorphous carbon and which is not scale-shaped, the packing density of the negative electrode being in the range of 1.3 to 1.8 g/cc, the specific surface area of the negative electrode being in the range of 2.1 to 4.1 cm2/g, and the fraction of the scale-shaped graphite particle being in the range of 10 to 70 wt % based on the whole of the carbon material.
Patent Literature 2 discloses that in order to obtain a non-aqueous electrolyte battery which has a high capacity and high cycle characteristics and exhibits a high volume energy density even in discharging at a large current, a negative electrode active material is used which includes a negative electrode active material mixture of scale-shaped graphite and at least one or more carbon materials selected from spheroidal graphite, bulk graphite, fibrous graphite, non-graphitizable carbon, and carbon black, the content of the one or more carbon materials in the negative electrode active material mixture being in the range of 1 wt % or more and 50 wt % or less.
Patent Literature 3 discloses that an active material including a mixture of an artificial graphite particle having a tap density of 1 g/cm3 or higher and a spheroidal graphite particle having a large roundness is used for the purpose of significantly improving the charge/discharge cycle characteristics of a high-energy density lithium secondary battery, and simultaneously enhancing or maintaining the discharge rate characteristics, the discharge characteristics at low temperatures, and the heat resistance. Patent Literature 3 also discloses that the fraction of the spheroidal graphite particle based on the whole of the active material is preferably 5 to 45% by mass.
Patent Literature 4 discloses a negative electrode active material for a lithium ion secondary battery, wherein the negative electrode active material is a powder mixture of a graphite powder A which is obtained by mixing a scale-shaped natural graphite and a binder pitch, and subjecting the resultant to molding, calcination for graphitization, and pulverization, and has a tap density of 0.4 to 0.9 g/cm3, D90/D10 of 3.5 to 7.0, and D50 of 10 to 20 μm, and a graphite powder B which is obtained by covering a spheroidized natural graphite with a pitch and calcining the resultant for graphitization, and has a tap density of 0.9 to 1.4 g/cm3, D90/D10 of 2.0 to 3.5, D50 of 10 to 20 μm, and a roundness of 0.91 or higher, and the mixing ratio by weight of the graphite powder A is 20 to 80% and the mixing ratio by weight of the graphite powder B is 20 to 80%. Patent Literature 4 also discloses that the object is to provide a negative electrode active material for a lithium ion secondary battery having a high electrode density, an excellent permeability of an electrolytic solution, a small capacity loss due to charging/discharging, and good cycle characteristics.

Graphite-based negative electrode active material, negative electrode, and lithium ion secondary battery