A liquid cooling system is disclosed for use in an electronic apparatus. The system is constructed to be of a reduced size and thickness, thus allowing it to be used for cooling heat-generating devices such as semiconductor elements, while maintaining corrosion resistance. The system includes a pump, a heat-receiving jacket, and flow passages through which the cooling liquid is circulated. An ion exchange bag having a water-permeable bag is disposed within the liquid cooling system. The water-permeable bag further contains an ion exchange resin therein.

The present invention relates to an electronic apparatus for cooling a semiconductor element therein, with using a liquid cooling system.
The semiconductor element generates heat during the operation thereof, which is used in an electronic apparatus, such as a computer, etc.
In particular, with the semiconductor in recent year, the heat-generation comes up much more, due to the demands on high processing speed and high capacity or performances thereof. In general, the semiconductor element looses the function of as the semiconductor element, remarkably, when exceeding over a predetermined level in temperature thereof, and therefore it is necessary to make compulsive cooling, in particular, on the semiconductor having a large amount of heat generation thereof.
As a method for cooling down the semiconductor of the electronic apparatus, for example, there are already known methods of applying the heat conduction, applying an air cooling, with using a heat pipe, and applying a liquid cooling, etc.
Among of those, cooling applying a liquid cooling is most effective for the semiconductor element having large heat-generation.
Such the cooling method applying the liquid cooling is described, in more details thereof, for example, Japanese Patent Laying-Open Nos. Hei 5-335454 (1993), Hei 6-97338 (1994), Hei 6-125188 (1994), Hei 10-213370 (1998), etc.
However, those conventional technologies are limited in the use thereof only in a filed of a large-scaled computer.
This is because the liquid cooling system comes to be large in the scale due to the fact that it needs a large number of parts for exclusive use of cooling, such as a pump, a piping system, a radiator, etc., and it is difficult to maintain the reliability in respect of applying the liquid into cooling thereof.
Also, another one reason thereof is the fact that such the semiconductor element is not used in the field other than the large-scaled computer, which has a large heat-generation so that the liquid cooling is needed therein.
Technology of applying the liquid cooling into a small-sized electronic apparatus is disclosed in Japanese Patent Laying-Open No. Hei 6-266474 (1994). In this prior art, a heat-receiving jacket attached on the semiconductor element and a radiator disposed apart from it are connected through flexible tubes, thereby cooling down it with an aid of the liquid flowing therein.
However, as was mentioned previously, an amount of heat-generation comes up every year, in particular, of the semiconductor elements, etc., which are used in the electronic apparatuses, such as, a personal computer, a home server, a projector, a media storage, etc., and for treating with it, but a compulsive cooling is not sufficient enough, with using the natural air cooling or a fan, or a cooling of using the heat pipe therein.
Then, attention was paid onto the technology described in Japanese Patent Laying-open No. Hei 6-6266474 (1994), and with this, it is possible to receive the liquid cooling system within an inside of a case of a personal computer, by using the case itself of the computer to be a heat radiation plate, which is made of a metal material having good heat conductivity.
However, installation of the liquid cooling system into such the computer causes a new problem.
That is, due to the fact that only a small amount of the liquid is held within the liquid cooling system, and further that the operating temperature thereof is relatively high, etc., corrosion is promoted on the parts or elements in contact with the liquid, which are made of a metal material, such as, the heat-receiving jacket and the radiator, since the liquid is degraded in quality thereof even if the corrosive ion flow out in a very small amount thereof, in particular, from the parts or element of an organic material (i.e., the parts or element made of synthetic resin).
If causing water leakage due to the corrosion, it results into an important problem of stopping the function of that electronic apparatus; therefore, it is indispensable to make a treatment of measure of anti-corrosion on the parts or element, to be in contact with the cooling water.
Further, a treatment of measure of anti-corrosion due to a liquid is already known, for example, in Japanese Patent Laying-Open No. 2003-185321 (2003).

Liquid cooling system and electronic apparatus using the same


An apparatus for testing electronic devices employs a programmable device to adjust the timing of the strobes such that the strobes sample the bit stream from a device under test at or near the center of the bit position. The strobe time adjustment is performed based on pairs of strobe readings made around a number of different bit positions. The programmable device examines the pairs of strobe reading made around each of the different bit positions to determine whether or not a bit transition has occurred there. The programmable device selects the bit positions around which a bit transition has not occurred as eye candidates, and defines the center of the largest contiguous region of eye candidates as the center of the bit position.

1. Field of the Invention
The present invention relates generally to electronic device testing, and more particularly, to bit synchronization techniques used in testing integrated circuit (IC) devices that output high-speed serial data streams.
2. Description of the Related Art
Next generation ICs will use a large number of high-speed serial links to communicate with external memory and I/O devices. In order to obtain accurate test results of such devices, it is important that a continuous stream of bits (0's and 1's) outputted by them is consistently strobed near the center of the bit and away from the transitions between the bits. If the strobes are positioned near the bit transitions, inaccurate strobe readings (e.g., 0 strobed as a 1, or 1 strobed as a 0) might result and cause inaccurate test results.
A conventional automated test equipment (ATE) uses a binary search method to locate the center of the bit. The binary search method is carried out during the initialization phase of testing when the device under test is outputting a bit stream of alternating 0's and 1's. With this method, two strobe points separated by one bit interval are initially selected. Then, a third strobe point that is halfway between the initial two strobe points is selected. The reading from the third strobe point is compared with the readings from the first two, and the pair that exhibits a transition (0 to 1 or 1 to 0) is selected as end points of a fourth strobe point that is halfway between the pair. The reading from the fourth strobe point is compared with the readings from the end points, and the pair that exhibits a transition (0 to 1 or 1 to 0) is selected as end points of a fifth strobe point that is halfway between the pair. This process is repeated until the bit transition is identified with a predetermined degree of accuracy. The bit strobe position is then computed as the position of the bit transition plus one-half of the bit interval.
The binary search method as described above is too slow and cannot be used while a test is ongoing. As a result, it is unable to correct for bit misalignments that may result during testing, e.g., during clock starts and stops, and from drifts caused by heating up or cooling down of the device.
U.S. patent application Ser. No. 10/948,709, filed Sep. 23, 2004, entitled "Bit Synchronization for High-Speed Serial Device Testing," discloses another method to locate the center of a bit. In this method, a number of different time sets that define different strobe positions along a bit interval are used. The strobe readings generated with the different time sets are evaluated and one of the time sets is selected as the one to be used during testing.
While the method described in U.S. patent application Ser. No. 10/948,709 is faster than the binary search method and permits strobe position adjustments during testing, it requires multiple time sets to be stored in memory during the entire test. This is not desirable, because memory space is not efficiently utilized, especially during the test when memory resources can be scarce.

Bit synchronization for high-speed serial device testing


The invention relates to the technical field of wireless communications, and in particular to a method, system, and device for measuring interference, so as to solve the problem in the prior art that the precision of interference measured by a terminal is low if a cell adopts a Resource Element Muting(RE MUTING) solution. The method includes: a network side device determining configuration information of a first Resource Element(RE) group performing interference measurement (501); and the network side device generating first interference notification information according to the determined configuration information of the first RE group and sending the first interference notification information to a terminal, so as to instruct the terminal to determine the first RE group according to the first interference notification information and perform the interference measurement on the determined first RE group (502). The terminal is notified to perform the interference measurement on the first RE group, so that when the RE MUTING solution is adopted, the precision of the measured interference is increased.

Each cell in a wireless cellular network system is typically provided with a base station communicating with a user equipment. Before a data transmission process is started, the base station will transmit reference signals (i.e., pilot signals) to the user equipment, and the user equipment can obtain a value of channel estimation from the reference signals. The reference signals are a known sequence of signals transmitted at a specific prescribed time at a specific prescribed frequency. The quality of channel estimation will be influenced by interference, noise and other factors.
Typically the user equipment is located at different geographical locations with different received signal strengths and different noise and interference strengths. Thus some user equipments, e.g., a user equipment located at the center of a cell, can communicate at a higher rate, and some other user equipments, e.g., a user equipment located at the edge of a cell, can communicate only at a lower rate. Data is transmitted to the user equipment preferably in a format matching a channel condition of the user equipment in order to make full use of a transmission bandwidth of the user equipment. A technology to match a format in which data is transmitted to the user equipment with a channel condition of the user equipment is referred to as link adaptation.
The user equipment shall report a Channel Quality Indicator (CQI) according to a channel condition of the user equipment in order to assist the base station in performing link adaptation. The CQI reported from the user equipment corresponds to specific time and frequency resources, that is, the CQI reported from the user equipment represents a capability of transmission over these time and frequency resources. The CQI shall be calculated by the user equipment measuring interference and noise of an adjacent cell to the user equipment, including interference I and noise power N0.
The International Telecommunication Union (ITU) poses a very stringent requirement on the performance of a next-generation mobile communication system, for example, a largest transmission bandwidth of the system up to 100 MHz and a required peak rate of uplink and downlink data transmission up to 1 Gbps and 500 Mbps, and a very high demand for an average spectrum efficiency, particularly an edge spectrum efficiency, of the system. In order to satisfy the requirements on the new system, the 3GPP proposes in Long Term Evolution-Advanced (LTE-A) of a next-generation mobile cellular communication system the use of the technology of coordinated multi-point transmission to improve the performance of the system. The technology of coordinated multi-point transmission relates to coordination between a plurality of transmission points separated in geographical location. In general, the plurality of transmission points are base stations of different cells. The technology of coordinated multi-point transmission is divided into downlink coordinated transmission and uplink joint reception. The technology of downlink coordinated multi-point transmission is generally divided into two categories of joint scheduling and joint transmission. Joint scheduling refers to coordination of time, frequency and space resources between the cells to allocate resources orthogonal to each other for different User Equipments (UEs) in order to avoid mutual interference. Inter-cell interference is a major factor restricting the performance of a UE at the edge of a cell, and thus joint scheduling can lower inter-cell interference to thereby improve the performance of the UE at the edge of the cell. As illustrated in FIG. 1A, joint scheduling of three cells schedules three UEs with possible mutual interference onto resources orthogonal to each other to thereby avoid interference between the cells effectively.
Unlike a joint scheduling scheme in which data is transmitted from only one cell to a UE, data is transmitted concurrently from a plurality of cells to a UE in a joint transmission scheme to thereby enhance reception of a signal at the UE. As illustrated in FIG. 1B, data is transmitted from three cells to a UE over the same resource, and the UE receives signals of the plurality of cells concurrently. Superposition of the useful signals from the plurality of cells can improve the quality of the signal received at the UE on one hand and lower interference to the UE on the other hand to thereby improve the performance of the system.
The user equipment shall further estimate channel state information of a base station in a coordinating cell to the user equipment in addition to a serving cell in order to support coordinated multi-point transmission effectively. Channel state information is estimated by measuring a pilot in the LTE-A. Fig.1C illustrates a mapping relationship of pilots and data in a Physical Resource Block (PRB). The first two Orthogonal Frequency Division Multiplexing (OFDM) symbols are used for transmission of control information, and a data region starts with the third OFDM symbol. The data region includes pilot Resource Elements (REs) and data RE. A pilot of an adjacent cell will typically be mapped onto different REs. This is because a pilot RE is typically at high power and transmitted throughout a bandwidth and there will be very strong interference between pilots mapped onto the same RE to influence the precision of channel estimation. As can be apparent from Fig.1C, a user equipment in a cell 1 shall perform channel estimation on REs corresponding to measurement pilots of a cell 2 and a cell 3 to obtain channel state information of the cell 2 and the cell 3. On these REs, downlink data transmission (e.g., a Physical Downlink Shared Channel (PDSCH)) may be scheduled in the cell 1, that is, the pilots of the cell 2 and the cell 3 will suffer interference of the data transmission in the cell 1. For the user equipment in the cell 1, the strength of a signal received at the user equipment from the cell 1 will typically be far above those of signals of the cell 2 and the cell 3 so that the Signal to Interference and Noise Ratios (SINRs) of the measurement pilots of the cell 2 and the cell 3 will be very low and no channel estimation at satisfactory precision can be obtained. In order to address this problem, the cell 1 can mute those REs on which the cell 2 and the cell 3 transmit the measurement pilots, that is, the cell 1 transmits a signal at zero power at those REs, and this solution is referred to as RE MUTING, and the muted REs are referred to as MUTING REs (see FIG. 1D for details thereof).
The user equipment shall feed back a CQI by estimating interference to the user equipment itself, and interference of an adjacent cell is absent at the location of the pilots in the RE MUTING solution. Interference of an adjacent cell is typically the strongest, and thus the interference estimated at the locations of the pilots will be far below the real interference to the user equipment.
In summary the user equipment may measure interference at lower precision at present if the RE MUTING solution is adopted in the cell.

Method, system and apparatus for measuring interference

China Academy of Telecommunications Technology


A communication system (100) includes a control unit (101) electronically coupled to a pushbutton switch (129). The control unit (101) includes a wake-up circuit (110) having a signal generator (201) and a signal detector (202). The signal generator (201) generates a digital pulse signal (139) having a predetermined amplitude (303) and a predetermined duration (304) for receipt by the pushbutton switch (129). The signal detector (202) monitors the digital pulse signal (139) to determine whether the pushbutton switch (129) is actuated or not actuated. The communications system (100) maintains a low power consumption mode responsive to determining when the pushbutton switch (129) is not actuated, and enables a normal power consumption mode responsive to determining when the pushbutton switch (129) is actuated.

The present invention relates generally to electronic systems having a standby mode to minimize current drain, and more particularly to a wake-up circuit for an electronic system and method therefor for use in telematics communication system.
Mobile or portable electronic systems, such as a telematics communication system, are typically powered by a portable power supply, such as a battery in an automotive vehicle, and have full functionality in a normal operating mode. Such electronic systems commonly have a standby mode to minimize current drain on the battery when the electronic system is turned on but not requiring the full functionality in the normal operating mode. Hence, the standby mode permits low power or current consumption to support reduced or minimum functionality of the electronic system while the normal operating mode permits normal operating power or current consumption to support full functionality of the electronic system. Typically, an electronic system has a normal mode power supply to provide power to the electronic system when operating in the normal operating mode and a separate standby mode power supply to provide power to the electronic system when operating in the standby mode.
An electronic system is known to xe2x80x9cwake-upxe2x80x9d when the electronic system changes from the standby mode to the normal operating mode responsive to a wake-up signal. A wake-up signal may be generated when a user activates a switch, such as a pushbutton or a key. In some electronic systems it is important that the electronic system wake-up almost instantaneously to give an impression to a user that the electronic system was always in the normal operating mode and to instantaneously provide the full functionality associated with the normal operating mode.
When the pushbutton is used as the switch to generate the wake-up signal, a relatively high level of current must pass through its conductive contacts to overcome or break through any electrical resistance caused by contamination or oxidation that may be present on the conductive contacts.
Further, when the pushbutton is located at a remote position relative to control circuitry of the electronic system and electrically coupled to the control circuitry of the electronic system using a wire, then the electronic system must be able to determine the electrical state of the switch or the wire indicating a failure thereof. The detection of the electrical state-of the switch or the wire is especially needed when the pushbutton serves a critical function, such as an emergency call button in the telematics communication system.
One known technique for the processor to determine the electrical state of the switch is using a resistor-based circuit. In this case, a resistor is connected in parallel with a switch. A first terminal of the resistor is connected to ground. A second terminal of the resistor is connected to a direct current (DC) voltage. An analog to digital (A/D) input port to the processor monitors the DC voltage at the second terminal of the resistor. The processor interprets a low voltage (e.g., 0 V) at the AID input port as an active state, wherein the switch is pressed or closed. The processor interprets a mid voltage (e.g., 2.5 V) at the A/D input port as an idle state, wherein the switch is not pressed or open. The processor interprets a high voltage (e.g., 5 V) at the A/D input port as a failure state, wherein a wire connecting the switch to the processor is broken or open. However, there are several disadvantages of the resistor-based circuit. The resistor-based circuit is relatively complex and therefore, relatively expensive to implement. The resistor-based circuit draws a steady amount of current that drains a battery power supply such that the switch practically can only be used when the electrical system is turned on, since the standby current drain is too high. Further, the resistor-based circuit cannot detect a short circuit state, wherein the switch is stuck in a closed position.
Accordingly, there is a need for a wake-up circuit for an electronic system and method therefor that uses a minimum amount of current while the electrical system is in the standby mode, that delivers a relatively high level of current to the switch during wake-up, and that determines the electrical state of the switch or the wire in the remotely positioned switch or in the wire leading to the remotely positioned switch.

Method and apparatus for determining whether to wake up a system by detecting a status of a push button switch that is remotely located from the system


The present invention provides a method and apparatus for de-interlacing video data by using a horizontal motion vector of a horizontal motion between fields. The horizontal motion regarding a target pixel of a frame is compensated if the horizontal motion vector is found to be substantially not null according to the pixels residing in the fields determined by the horizontal motion vector. This results in an upgraded quality of image after the de-interlacing process.

1. Field of the Invention
The present invention relates to an image de-interlacing method and apparatus, and more particularly, to an image de-interlacing method and apparatus that compensates video data with horizontal motion estimation.
2. Description of the Prior Art
In general, an interlaced scanning technique is to display two fields of a frame by interlacing. The two fields are respectively an odd field and an even field. A progressive scanning technique (i.e. non-interlaced scanning), on the other hand, merges the two fields into a frame, and doubles the scanning frequency of all the scan lines of the frame in order to display.
In order to display interlaced image data in sequence, a de-interlacing method suggests adding a new scan line between two sequential scan lines of a field. The motion-adaptive method is widely adopted to perform the operation of de-interlacing.
However, interpolation of high frequency motion is performed imprecisely in conventional motion adaptive methods. Furthermore, if the video data is encoded/decoded before the de-interlacing operation, a cross color phenomenon will distort the high frequency part of the data, affecting the interpolated result of the image. Therefore, the quality of the image after the de-interlaced process is unacceptable.

Method and apparatus for de-interlacing video data


Systems and methods for a compact wall model are provided. According to one aspect, embodiments herein provide a method that comprises receiving input data related to an enclosure, the input data including solar intensity data on an exterior of a wall of the enclosure, generating, by a processor, a thermal model of a wall of the enclosure based at least in part on the input data, the wall modeled as having a plurality of layers and the thermal model including a plurality of nodes such that each layer of the plurality of layers is associated with at least one node of the plurality of nodes and each node of the plurality of nodes is thermally coupled to an adjacent node by a thermal resistance, solving, by the processor, an energy balance equation for the at least one node to determine a predicted temperature for the at least one node, and output the predicted temperature to a display device.

Computational Fluid Dynamics (CFD) use mathematical methods to solve problems that include fluid flow, such as air flow distribution within a data center. Although CFD modeling is an effective way to optimize data center airflow configurations, CFD analysis methods have a number of disadvantages. For example, a CFD approach typically involves calculations that are time-consuming and may include many assumptions which are intrinsically built into the model, which can lead to inaccurate results.

Systems and methods for constructing a compact wall model


L1 cache synonyms in a two-level cache system are detected and resolved by logic in the L2 cache. Duplicate copies of the L1 cache tags and state (xe2x80x9cDtagsxe2x80x9d) are maintained in the L2 cache. After a miss occurs in the L1 cache, the Dtags in the second-level cache that correspond to all possible synonym locations in the L1 cache are searched for synonyms. If a synonym is found, the L2 cache notifies the L1 cache where the requested cache line can be found in the L1 cache. The L1 cache then copies the cache line from the location where the synonym was found to the location where the miss occurred, and it invalidates the cache line at the original location. The Dtags in the second-level cache are updated to reflect the changes made in the L1 cache.

This application is related to, and hereby incorporates by reference, the following U.S. patent applications:
Multiprocessor Cache Coherence System And Method in Which Processor Nodes And Input/output Nodes Are Equal Participants, Ser. No. 09/878,984, filed Jun. 11, 2001;
Scalable Multiprocessor System And Cache Coherence Method, Ser. No. 09/878,982, filed Jun. 11, 2001;
System and Method for Daisy Chaining Cache Invalidation Requests in a Shared-memory Multiprocessor System, Ser. No. 09/878,985, filed Jun. 11, 2001;
Cache Coherence Protocol Engine And Method For Processing Memory Transaction in Distinct Address Subsets During Interleaved Time Periods in a Multiprocessor System, Ser. No. 09/878,983, filed Jun. 11, 2001;
System And Method For Generating Cache Coherence Directory Entries And Error Correction Codes in a Multiprocessor System, Ser. No. 09/972,477, filed Oct. 5, 2001, which claims priority on U.S. provisional patent application 60/238,330, filed Oct. 5, 2000, which is also hereby incorporated by reference in its entirety.
The present invention relates generally to the design of cache memories in computer central processor units (CPU""s), and particularly to the organization of two-level CPU caching systems in which the first-level cache is virtually indexed.
The present invention is applicable to both single processor and multi-processor computer systems, but will be described primarily in the context of a distributed multi-processor system.
An xe2x80x9cindex positionxe2x80x9d within a cache identifies one or more cache lines within the cache. The number of cache lines stored at each index position is called the associativity of the cache. A direct mapped cache has an associativity of one. A two-way associative cache has an associativity of two, and thus has two cache lines at each index position of the cache.
A xe2x80x9cmemory line,xe2x80x9d also often called a cache line, is the basic unit of storage that is stored in a memory cache. A memory line or cache line is also the basic unit of storage that is tracked by the cache coherence logic in multi-processor computer systems. A memory line of data will often be called a xe2x80x9cmemory linexe2x80x9d while it is stored in main memory or is in transit between system nodes, and the same data may also be called a cache line while it is stored in a memory cache.
When a first-level (L1) cache is virtually indexed the xe2x80x9ccache index bitsxe2x80x9d within the virtual address supplied by a processor are used to retrieve a tag from a tag array within the cache. Virtual indexing of a first-level (L1) cache allows the lookup of the L1 cache tag to proceed concurrently with the translation of the requested virtual memory address into a physical memory address, sometimes herein called the targeted physical memory address. The virtual to physical address translation is performed by a translation look-aside buffer (xe2x80x9cTLBxe2x80x9d). The tag from the cache is then compared to the targeted physical memory address obtained from the TLB, and if there is a match and the cache state for the cache line is not xe2x80x9cinvalidxe2x80x9d (which together indicate a cache hit), the data from the cache that corresponds to the tag is sent to the processor. If there is a miss, meaning that the retrieved tag did not match the physical address obtained from the TLB, the requested cache line of data must be obtained from a second-level cache or main memory.
While virtual indexing speeds up the lookup of a cache, it also may give rise to the possibility of synonyms. Synonyms are cache lines at different cache indices that map to the same physical memory address, and therefore refer to the same data entry. Synonyms may arise when a physical memory address is shared between two or more different programs or different parts of the same program, which may access it with two or more different virtual addresses. If the size of the cache divided by its associativity is greater than the size of the memory pages used in the system, a memory line at any given physical memory address can be stored at more than one index position within the cache. More specifically, the number N of cache line index positions at which any memory line may be found within the cache is equal to:   N  =            cache                    xe2x80x83                  size              associativity      xc3x97      pagesize
Having more than one cache index position correspond to the same physical memory address can give rise to a memory coherence problem if the data entry for one virtual memory address is changed without changing the data for another virtual memory address that maps to the same physical memory address. It is therefore necessary to either prevent synonyms from occurring or else to detect and resolve synonyms before they give rise to a memory coherence problem.
In addition, in the context of a shared memory multi-processor computer system with multiple first-level caches, it is also necessary to ensure that the cache coherence logic handling a request for a particular physical memory address be able to find any and all copies of the corresponding memory line, including those in first-level caches, even though there may be multiple L1 cache index positions at which the identified memory line may be stored within any particular L1 cache.
Since synonyms are only possible if the size of the first-level cache divided by its associativity is larger than the size of the system""s memory pages, synonyms may be avoided by decreasing the size of the cache, increasing associativity, or increasing the size of the memory pages. Unfortunately, decreasing the size of the first-level cache reduces system performance, because it increases the number of cache misses. Increasing associativity greatly increase the complexity, and thus cost, of the L1 caches, and may also reduce system performance by increasing the time required retrieve a cache line from the L1 cache. Increasing the size of the system""s memory pages is often not practical, because memory pages are the basic unit of memory used for many tasks, including memory allocation to processes, disk transfers and virtual memory management.
Alternatively, synonyms may be avoided at the system or kernel software level by restricting the assignment of virtual addresses by increasing the number of least significant address bits of the virtual addresses that must match the corresponding physical address. As a result of this restricted allocation of virtual addresses, all virtual addresses that correspond to a particular physical address will always have the same L1 cache index. This last method of avoiding synonyms places a burden on system software policies and on the usage of virtual address spaces.
A possible method of resolving the problem of L1 cache synonyms that was considered by the inventors, but rejected for reasons described next, is to build logic into the L1 cache for detecting synonyms and resolving them. When an L1 cache miss occurs, the logic would search for a synonym within the L1 cache and abort the miss if a synonym is found. The cache line would then be copied from the location where the synonym was found to the location where the miss occurred, and the cache line at the original location would be invalidated. The main disadvantage of this method is that it would cause the first-level cache to be kept busy after every cache miss, while the first-level cache is searched for synonyms. Most of the time a synonym will not be found, however, because synonyms are rare in practice. Searching the first-level cache for synonyms after every miss reduces system performance by increasing the amount of time between cache requests by the processor coupled to the L1 cache, and potentially reduces system performance by delaying the resolution of other subsequent L1 cache accesses. In addition, in multiprocessor systems, this technique may reduce system performance by decreasing the amount of time that the cache is available for responding to cache coherence protocol requests. The impact on system performance may be especially severe for processor cores that aggressively exploit instruction level parallelism and which therefore could tolerate the latency of a first-level cache miss. An additional disadvantage of searching the first-level cache for synonyms after a miss occurs is that it delays the initiation of the search of the second-level cache for the tag, unless the search of the second-level cache is done concurrently with the search of the first-level cache for synonyms. Searching the first-level and second-level caches concurrently requires a complex handshake between the first-level and second-level caches, because it introduces the need to abort the second-level search if a synonym is found in the first-level cache. The handshake is particularly difficult when several first-level caches share a single second-level cache, as is the case in some single chip multiprocessor (xe2x80x9cCMPxe2x80x9d) systems.
L1 cache synonyms in a two-level cache memory system are detected and resolved using duplicate tags and detection logic in the second-level (L2) cache, rather than in the first-level (L1) cache. Duplicate copies of all the first-level cache tags and state (xe2x80x9cDtagsxe2x80x9d) are maintained in the second-level cache. When a miss occurs in the first-level cache, an L1 miss message is sent to the L2 cache. The Dtags in the L2 cache that correspond to all possible synonym locations in the first-level cache are searched for a synonym of the requested cache line. By definition, a synonym of a requested cache line has the same physical address as the requested cache line, but is stored in at a different cache index of the L1 cache than the index corresponding to the specified virtual address of the cache line.
The L1 cache index is typically determined by a predefined subset of the cache line""s virtual address bits. Furthermore one or more of the most significant bits of the L1 cache index are herein called the xe2x80x9cvpn bitsxe2x80x9d of the virtual address. The number of vpn bits, M, is equal to:   M  =      ceiling              (                        Log          2                                  (                                    cache                                            xe2x80x83                                          size                                      associativity              xc3x97              pagesize                                )                    )
where the xe2x80x9cceilingxe2x80x9d function rounds up the value to which the ceiling function is applied to the closest integer if that value is not already an integer. The vpn bits of a virtual address identify which one of the possible N synonym cache index positions in the L1 cache corresponds to the virtual address. The other N-1 synonym cache index positions have the identical cache index value, except for the M most significant bits thereof.
The L1 cache miss request to the L2 cache specifies both the physical address of the requested cache line and the vpn bits of the specified virtual address so that the second-level cache can search the appropriate N-1 Dtag entries for a synonym having a tag matching the requested physical memory address but a different L1 cache index.
If a synonym is found, the second-level cache aborts the miss and notifies the first-level cache where the requested cache block can be found in the first-level cache. The first-level cache then copies the cache line from the location where the synonym was found to the location where the miss occurred, and it invalidates the cache line at the original location. Finally, the Dtags in the second-level cache are updated to reflect the changes made in the first-level cache.

Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy

Hewlett-Packard Development Company, L.P.


In a toroidal type continuously variable transmission having an input disk, an output disk and power rollers sandwiched and frictionally engaged between the input and output disks so as to transmit rotational power therebetween at a transmission ratio variable according to the inclination of the power rollers relative to the input and output disks, a stationary shaft is provided as supported by a housing, and the input and output disks are rotatably supported by the stationary shaft via individual radial bearing means and individual axial bearing means. The stationary shaft has an axial bore and transverse orifices, and the bearings are lubricated by lubrication oil supplied through the axial bore and the transverse orifices.

1. Field of the Invention
The present invention relates to a toroidal type continuously variable transmission (referred to as T-CVT hereinbelow) which has an input disk, an output disk and power rollers sandwiched and frictionally engaged between the input and output disks and transmits rotational power between the input and output disks via the power rollers at a transmission ratio variable according to the inclination of the power rollers relative to the input and output disks.
2. Description of the Prior Art
In the T-CVT of the above-mentioned basic construction which itself is well known in the art, it is a general construction that the input disk is supported by an input shaft and the output shaft is journaled on the input shaft to be rotatable therearound. Such a general construction that the input and output disks are both commonly supported by the input shaft provides a T-CVT at a smaller size and a lower weight for the same power transmission capacity, by a smaller number of construction members, and therefore at a lower manufacturing cost, as compared with a T-CVT having input and output shafts supporting the input and output disks separately.
However, since the input disk and output disks of the T-CVT rotate in opposite directions relative to one another, when the output disk is journaled on the input shaft, the bearing means which supports the output disk on the input shaft is subjected to a very high rotation speed which is an addition of the rotation speed of the input disk and that of the output disk, and therefore the bearing means often suffers an early wearing. Further, on the other hand, since the input disk is generally rotatably supported on the input shaft via a bearing means so that the input disk is axially biased relative to the input shaft by a torque cam means which converts a part of the torque into an axial force based upon an angular shifting of the input disk relative to the input shaft, such a bearing is subjected to a very small rotation and generally suffers uneven wearing of the bearing surface.

Toroidal type continuously variable transmission supported by a common bearing and reaction stationary shaft


A system for designing an intercommunication network among a plurality of devices. The system includes a device for storing rules to meet design requirements and a mechanism connected to the device for storing rules in order to revise the rules dynamically. Also provided is a device for storing data and a mechanism connected to the device for storing data in order to revise the data. A requestor has the ability to access all rules and to revise a portion of the data. Moreover, a designer has the ability to access all rules and to revise another portion of the data, which portion has at least one subportion that cannot be revised by the requestor.

The present invention relates to a system for designing a network and more particularly to a system for designing an intercommunication network among a plurality of devices by the use of revisable rules and data.
Design of network systems such as wire cables used for power or signals, plumbing fixtures and pipes, heating, ventilation and air conditioning duct work, aircraft mechanical cabling, pneumatic tubes and the like heretofore generally has been manual. For the purpose of brevity the word cable is used hereinbelow to represent all such elements appropriate to varied environments, such as, but not limited to, wire for electrical systems, pipes for plumbing systems and tubes for pneumatic systems and the like. Wire, pipe or tube lengths, for example, are conventionally determined or estimated by various methods including measuring string on a mock-up scale or life-sized physical model of a product or building or by digitizing engineering drawings.
Resulting computer generated or manually generated engineering drawings are symbolic, which is a disadvantage when designing a network. Such symbolic manufacturing drawings are usually not geometrically accurate nor are the dimensions accurate. The final engineering drawing, while generally to standards, is symbolic, so the drawing does not resemble a cable.
Cable routing drawings suffer from another disadvantage: conventionally they are more descriptive than pictorial. When cables require sequential assembly, computer aided models are so complex as to be almost invariably incomplete even after several revisions. Their level of complexity and degree of completeness are inversely related to the ease by which assemblers or installers can decipher the drawings that describe the network. The only task not manually performed has been the process of drafting engineering drawings, which task is often accomplished by a computer aided design system. Even here, administrative data as well as geometric data needed for drafting is usually accumulated manually.
Network and especially cable design has traditionally involved less than accurate methods. Requests to have cables designed were often incomplete. This was due to the communications medium between the cable designer, who belongs to a first class of user, and people requesting cables, who belong to a second class of user, being inaccurate, hand written notes.
In a manual system of designing, when a number of designers provide information over the course of the project, the data that is actually entered can bear less than strict resemblance to that which was intended. That is, the information that is transferred from one designer to another or from one designer to an anthologizer may be distorted, missing or otherwise incomplete. One step toward solving this problem has been described in the article "Think Large Scale CAD/CAM With Telecommunications" by B. Forgue, Mesures, Vol. 52, No. 2, 23 February 1987, pp. 33-34. This article discloses a network that conveys data between a central office and 12 regional offices for the manufacturer of corrugated cardboard cartons. A graphics database is continuously updated by 60 designers. Three dimensional packages are designed around the product to be contained and corresponding flattened shapes and sizes are formed by folding and unfolding on a CRT display. All 60 designers in the system are considered to be in the same class and each of them is responsible for describing the corrugated box being designed. In the aforementioned system, the design requirements are relatively rudimentary so there is no need for another class of individuals to provide information to the system in order to guarantee completeness thereof.
U.S. Pat. No. 4,422,158 issued to Galie discloses a digital data processing system and a query composed of entries to locate items that are stored in a multiple layer data base. The entries have one or more event types and the database includes items that have either an exact or inexact match with entries of the query. The query and a first one of the database layers are processed to form packages having an assigned order. The packages contain representations of the event types in a second layer of the database and representations of the degree of match between the entry in the first layer and an entry of the query. As a result, the representations of the furthest degree of match represent the degree of match of the query to both the first and second layers of the database. Only one class of users can use the aforementioned system at a time. Accordingly, no provision is made for a second class of users to interact with the first class to complete technical descriptions of the items in the database.
U.S. Pat. No. 4,648,044 issued to Hardy et al describes a tool for building a knowledge system and running a consultation on a computer. The knowledge system includes a knowledge base having English-like language expressing facts, rules and meta-facts for specifying how rules are to be applied to solve a specific problem. The tool includes interactive knowledge base debugging, question generation, legal response checking, explanation, certainty factors and the use of variables. A knowledge engineer in the aforementioned system creates the entire expert system prior to its use. A consultation user represents a single class of user and does not interact with the knowledge engineer. Thus, the consultation user himself is responsible for providing enough information to obtain a complete answer to his own queries.
U.S. Pat. No. 4,658,370 issued to Erman et al discloses a tool for knowledge engineers for building and interpreting a knowledge base having separate portions. Portions include encoding control knowledge, factual knowledge and judgmental rules. The tool has an inference engine applying the judgmental rules according to a built-in control procedure defining discrete states or control steps during a consultation with the user. The tool can be used to build knowledge systems that can explain their conclusions and reasoning and are intelligible and modifiable. The knowledge engineer may provide control blocks to be executed at the start of the consultation, after the instantiation of specified classes, when a value for a specified attribute is to be determined, after a specified attribute is determined and upon explicit invocation by another control block. Once again, there is only one class of user. A knowledge engineer in the aforementioned system creates the entire expert system prior to its use. A consultation user represents another class of user and does not interact with the knowledge engineer. Thus, the consultation user is responsible for providing enough information to obtain a complete answer to the queries that he himself poses.
Network connections such as cabling are often designed last. This is symptomatic of last minute changes in the design of subassemblies that require cables. The time associated with completing a given product must often be lengthened because network connections cannot keep up with latest design changes.
As a result of the aforementioned factors, cable designing for development projects has usually been inefficient and frequently inaccurate.
It would be advantageous to provide a digital system to allow only a few requestors to create a cable description.
It would further be advantageous to provide a digital system to allow only a few cable designers to design a network of completed cable descriptions.
It would also be advantageous for the invention, once developed, to be practiced by any person using similar hardware.
Moreover, it would be advantageous to allow two classes of users to supply complete cable descriptions.

System for designing intercommunication networks


A method for parsing and executing a software program includes receiving a portion of a software program in an original linguistic form, wherein the portion of the software program includes a nonlinear program element having a body, and, while retaining the original linguistic form, directly executing the nonlinear program element by manipulating a parse state and an input stream of tokens representing the body of the nonlinear program element, wherein directly executing comprises executing tokens until the dynamic end of the nonlinear program element is reached. A system includes a tokenizer operable to tokenize the software program and a parser operable to directly execute a nonlinear program element in the software program by manipulating a parse state and an input stream of tokens representing the body of the nonlinear program element, while preserving the original linguistic form of the software program.

Compilers are programs that translate an input stream to a (usually different) output stream. Generally compilers translate a program in some programming language (such as C or C++) into the binary machine instructions required for the program's execution on a specific computer architecture. In some cases, compilers are used as program analyzers to perform "source-to-source" translations which modify a source program to support optimizations. Compilers are usually organized into several phases (or passes): lexical translation into a token stream, parsing the token stream, analysis and code generation.
Lexical translation converts the input text stream into a collection of tokens (essentially compressing the input stream). The parsing phase checks to see that the token stream constitutes a "valid" program of the programming language. Validity of a program must not be confused with the notion of a "correct program." In the English language, for example, sentences can be valid but not correct, such as the sentences "The sky is always orange", or "The earth is flat." The output of this parsing phase is (usually) a graph of the program which is an intermediate representation (IR) which is used for subsequent analysis and transformations.
The analysis phase repeatedly examines the program to find patterns which can be transformed to enhance the efficient execution of the program. This phase may remove program sequences which never execute, for example. Or it may move instances of a redundant computations to a single point in the program. Finally, the code generation phase converts the IR into the machine instructions for the particular target computer architecture (e.g., IBM's Power PC, Intel's Pentium or x86, MIPS, SPARC, Java ByteCodes, etc.)
Notably, all of the above transformations are performed statically. That is, these transformations are carried out before the dynamic execution of the program. Generally, once the program has begun to execute, no further transformations are applied.
The desired output of the code generation phase is a sequence of machine instructions that mirror the behavior of the original source program. It is necessary to execute those instructions to effect the behavior of the program. If the target machine is a physical computer (such as the PowerPC or the Pentium), the program is "native", and generally runs very quickly. The target architecture might also be a Virtual Machine (VM) such as the Java Virtual Machine (or JVM) or Zend's VM for the language PHP. Traditionally, a virtual machine is a program that simulates the behavior of an abstract computer architecture by repeating the cycle: an instruction is fetched, its operands are fetched, the operation is performed, and any results are saved.


A universal cartridge follower for a firearm magazine comprising a cartridge receiving surface and side walls extending from the cartridge receiving surface. The cartridge receiving surface is operationally configured to intercept a firearm bolt. The side walls extend from the cartridge receiving surface and have opposing first surfaces defining a first width of the cartridge receiving surface and at least opposing second surfaces defining a second width of the cartridge receiving surface.

Traditional magazines for Kalashnikov type firearms are designed to stop a cartridge follower at a designated point within the magazine allowing the firearm bolt to close after the last cartridge is fired from the magazine. Although magazines for Kalashnikov type rifles have been made with cartridge followers designed to hold a rifle bolt open after the last cartridge is fired from the magazine, a need still exists to retrofit various traditional magazines with a universal cartridge follower capable of stopping or catching the rifle bolt thereby holding the rifle bolt in an open position when the magazine is emptied of the last cartridge.

Universal AK-47 and variant bolt hold open follower


A display device includes a light guide plate 2 having at least one incoming surface and a plurality of light sources (3-1 to 3-4) arranged to face any of the incoming surfaces. The light guide plate 2 has a plurality of prisms 11 that is arrayed along each pattern in a plurality of patterns (21 to 24) displayed on one surface 2b of the light guide plate and reflects light emitted from a light source corresponding to the pattern and entering the light guide plate through the incoming surface toward a direction within a prescribed range of angles with reference to a direction normal to the other surface 2c of the light guide plate. Each prism 11 is formed as a triangular pyramid groove in one surface of the light guide plate 2, and one of inclined surfaces of the triangular pyramid groove is formed as a reflective surface 11a that reflects light emitted from a light source corresponding to a pattern along which the prism is arrayed and entering the light guide plate.

Conventionally, a technique has been proposed for displaying a pattern according to a direction of light incident on a light guide plate which is formed into a plate shape and which has light transparency (see, for example, Patent Document 1).
For example, a light guide plate display device disclosed in Patent Document 1 includes a light guide plate, a plurality of light source devices provided along respective end faces of the light guide plate, and a plurality of prisms formed inside the light guide plate. The prisms respectively have a plurality of side surfaces facing the light source devices, and the side surfaces are respectively inclined in a thickness direction of the light guide plate at least in two stages by a transmissive inclined surface which transmits light radiated from the light source device, and a reflective inclined surface which reflects light radiated from the light source device and outputs the reflected light to a display surface of the light guide plate. Furthermore, a plurality of patterns is provided on the light guide plate. The prisms are formed such that, in each prism included in each pattern in the plurality of patterns, the area of the reflective inclined surface on the side surface facing the corresponding light source device is large and the area of the reflective inclined surface on the other side surfaces is small.


A printing apparatus includes an open/close lid configured to close or open a paper conveyance path of a recording paper, and a locking member configured to hold a closing state of the open/close lid by engaging with an engaging portion of the open/close lid, and to be capable to move to a position engageable with the engaging portion of the open/close lid or a position of retracting from the position engageable with the engaging portion of the open/close lid. The locking member moves to the position engageable with the engaging portion of the open/close lid at non-print time, and further moves to the position of retracting from the position engageable with the engaging portion of the open/close lid at print time.

1. Field of the Invention
The present invention relates to a printing apparatus. In particular, the present invention is suitable for a printing apparatus including an open/close lid that closes or opens a conveyance path of a recording paper.
2. Description of the Related Art
Conventionally, printing apparatuses based on various systems are proposed as a means for printing an image to a recording paper. With the printing apparatus, a paper feed unit feeds and conveys a recording paper for printing an image, and a printing unit therein prints the paper. The printing apparatus includes an opening for externally discharging the printed recording paper after conveying the recording paper via a paper conveyance path downstream.
In particular, the number of compact printers with high portability is recently increased. The usage environment of the printer is not limited to the indoors, furthermore, the compact printer is available with an attachable battery without requiring the plug-in connection via a cable when supplying electrical power. Therefore, the printing apparatus needs to be structured in consideration of the outdoor use. Specifically, when the opening portion, from which the recording paper in the printing apparatus is discharged, is always open, dust or a foreign matter can invade the printing apparatus from the opening portion. In particular, when the printing apparatus is carried outside, there is high possibility that sand dust invades the printing apparatus during conveyance.
If the foreign matter invades the printing apparatus, a printing operation is performed in a state in which the foreign matter adheres to the surface of the recording paper. Thus, there is fear that the quality of a printed matter deteriorates, or the printing unit is damaged, so that the printing apparatus can deteriorate earlier. Therefore, there is recently provided a printing apparatus having an openable and closable lid capable of opening or closing an opening portion to prevent a foreign matter from invading. To prevent a recording paper from falling on the floor when the recording paper is externally discharged from the printing apparatus, there is provided a printing apparatus having a paper stacking unit such as a paper discharge tray. Moreover, there is a printing apparatus in which a part of an exterior casing forms a lid having both a function for preventing the foreign matter from invading and a function as the paper discharge tray.
However, if the lid is arranged on the paper conveyance path, when a user carelessly starts the printing operation in a closing state of the lid, and the leading edge of the conveyed recording paper thus collides with the inside of the lid since the paper conveyance path is closed. In this case, there is a problem that the recording paper is not subsequently conveyed, the recording papers are stuck in the printing apparatus, and paper jam occurs.
As a jam preventing mechanism for preventing the jam, there is a technique for detecting the closing state of a paper discharge port by open/close lid with a detection sensor. With the technique, the open/close lid is opened, a detected member is consequently moved from a standby position, and the sensor detects a flag portion of the detected member. The state corresponds to an on-mode for enabling the start and continuation of a printing operation. On the other hand, by closing the open/close lid, the detected member is moved to the standby position, i.e., the position where the detected member is not detected. The state corresponds to an off-mode for disabling the printing operation. Therefore, if carelessly closing the open/close lid during the printing operation, the on-mode for enabling the detection of the detected member is changed to the off-mode for disabling the detection of the detected member, thereby suspending the printing operation.
Further, there is a technique in which the apparatus is configure to includes a biasing solenoid in conjunction with a power supply of an apparatus at an opening portion and a lever operated by energizing the solenoid, and the open/close lid is closed or opened by latching the lever thereto. The lever is rotated by energizing the solenoid at power-on and is retracted from a hook portion of the open/close lid with which the lever is engaged. Then, the latching is released and the opening portion is simultaneously opened by a spring which is biasing the open/close lid in the direction of opening the lid.
However, with the configuration including the detection sensor that detects the opening/closing state of the open/close lid, a sensor for detecting the opening/closing state is required independently of a sensor which is necessary for a normal operation. Further, there is a problem that, a circuit for controlling the sensor needs to be additionally provided, thereby increasing in costs and becoming a complicated configuration. Furthermore, there is another problem that, although printing operation is started already, if the user closes the open/close lid since there is not the printed matter in the paper stacking unit, a signal of the sensor turns off state when the open/close lid is closed and the printing operation is suspended.
With the configuration of releasing the lock by energizing the solenoid, the lock is released only at the energization time. Thus, if the user carelessly closes the open/close lid after starting the printing operation, the open/close lid is held in the closing state. Further, if releasing the lock of the open/close lid after starting the printing operation is required, the solenoid needs to be continuously energized. In addition, there is a problem of great increase in costs because the solenoid is used to control the locking operation of the open/close lid.

Printing apparatus including an open/close lid


A nano-magnetic head for inputting and outputting magnetic signals with nano-region precision on a magnetic recording medium such as magnetic tapes, magnetic cards, magnetic disks, magnetic drums, etc. The nano-magnetic head uses a nanotube with its base end portion fastened to a holder that is at an end of an AFM cantilever. The tip end portion of the nanotube protrudes from the holder, and a nanocoil is wound around the outer circumference of the tip end portion of the nanotube so that signals are inputted and outputted at both ends of the nanocoil. By way of lining up ferromagnetic metal atoms in the hollow portion of the nanotube, it is possible to strengthen the magnetic signal. The nano-magnetic head is combinable with a signal controller, thus forming a nano-magnetic head device.

1. Field of the Invention
The present invention relates to a nano-magnetic head that uses a nanotube being capable of inputting and outputting magnetic signals with nano-region precision on a magnetic recording medium. The present invention further relates to a nano-magnetic head device equipped with a signal controller that inputs and outputs signals to and from a nano-magnetic head respectively.
2. Prior Art
Generally, a magnetic head is constructed from a core and a coil. The core has a gap between magnetic poles, and the coil is wound around the core. A magnetic recording device is constituted by disposing this gap between magnetic poles so that the gap contacts a magnetic recording medium such as a magnetic tape, magnetic card, magnetic disk, magnetic drum and other magnetic substance. When a signal current flows through the coil, magnetic flux is generated in the ring-form core. A part of this magnetic flux leaks into the magnetic recording medium from the gap between magnetic poles, and information is magnetically recorded in the molecules of the magnetic material of the magnetic recording medium by this leakage magnetic flux.
Conversely, when the magnetic recording medium on which magnetic recording has been performed is moved relative to the gap between magnetic poles, a signal current is generated in the coil by electromagnetic induction. Magnetic information is played back by way of amplifying this signal current.
As seen from the above, a magnetic head is a device that magnetically records information on a magnetic recording medium and plays back magnetic information from such a magnetic recording medium.
The size of the minimal units of magnetic information recorded on the magnetic recording medium varies directly depending upon the size of the gap between magnetic poles formed in the core. Accordingly, in order to increase the magnetic recording density, it is necessary to design the magnetic head so that the core and the gap between the magnetic poles of the core are as small as possible in size. However, as along as the formation of the core and the gap between the magnetic poles depends on mechanical working or other physical working, there are size limits that restrict the miniaturization of these members. Accordingly, not only the development of magnetic substances but also the development of core materials is an urgent task for increasing magnetic recording density.
Accordingly, it is an object of the present invention to provide a nano-magnetic head that reduces the size of the minimal units of magnetic information to the nano-scale in a single stroke, thus providing a great increase in magnetic recording density.
It is another object to provide a nano-magnetic head device that uses such a nano-magnetic head.
The above object is accomplished by a unique structure for a nano-magnetic head that is characterized in that the base end portion of a nanotube is fastened to a holder so that the tip end portion of this nanotube protrudes from the holder, a nanocoil is wound around the outer circumference of this tip end portion of the nanotube, and signals are inputted and outputted at both ends of this nanocoil.
The above object is accomplished by another unique structure for a nano-magnetic head that is characterized in that the base end portion of a nanotube is fastened to a holder so that the tip end portion of this nanotube protrudes from the holder, a microcoil is wound around the outer circumference of this holder, and signals are inputted and outputted at both ends of this microcoil.
In the above nano-magnetic head, the holder is a protruding portion of an AFM (Atomic Force Microscope) cantilever, where the protruding portion is also called xe2x80x9cpyramid portionxe2x80x9d which is sometimes used below in the present specification.
The above object is accomplished by still another unique structure for a nano-magnetic head that is characterized in that the base end portion of a nanotube is fastened to a holder so that the tip end portion of this nanotube protrudes from the holder, a microcoil is wound around the outer circumference of a main body portion that supports the holder, and signals are inputted and outputted at both ends of this microcoil.
In this nano-magnetic head, the holder is the protruding portion of an AFM cantilever, and the main body portion is the cantilever portion of the AFM cantilever.
Furthermore, in the present invention, ferromagnetic metal atoms can be installed in the hollow portion of the nanotube.
The above object is further accomplished by a unique structure for a nano-magnetic head device that comprises the nano-magnetic head as described above and a signal controller that inputs and outputs signals to and from this nano-magnetic head, respectively, so that the nano-magnetic head device performs magnetic writing in a nano-region of a magnetic recording medium and reads magnetic record from this nano-region.

Nano-magnetic head and nano-magnetic head device using the same

9-404, 14-2, Korigaoka 1-chome, Hirakata-city


Present novel and non-trivial methods for presenting traffic information are disclosed. In a first method, data representative of ownship position, first traffic, and second traffic are received by a traffic symbology generator (“TSG”). The traffic is divided into zones and a correlation between the targets of the traffic is determined. A traffic symbology data set is generated by the TSG based upon the results of the correlation(s). In a second method, data representative of ownship position and first traffic, runway references, and a selectable display range are received by the TSG. The traffic is divided into zones, and a traffic symbology data set is generated by the TSG thereafter. In a third method, data representative of ownship position and first traffic are received by the TSG. The traffic is divided into zones, and a traffic symbology data set is generated by the TSG thereafter.

1. Field of the Invention
This invention pertains generally to the field of display units provide flight traffic information to the pilot or flight crew of an aircraft.
2. Description of the Related Art
Conventionally, avionics engineers and aviation governing authorities are improving and providing pilots and flight crews with information necessary to identify in-flight traffic. One approach that has been taken is to provide the flight crew with information on the location of other aircraft in the area. One exemplary system, which is capable of providing this information, is known as traffic alert and collision avoidance system ("TCAS"). The system is required for many aircraft including those operated by airliners operating in the United States. The TCAS has been designed to interrogate transponders of other aircraft, sometimes referred to as intruder or target aircraft. The TCAS evaluates the threat of a collision with other targets and provides traffic advisories ("TAs") and resolution advisories ("RAs"). A TA is presented to a pilot in situations in which the TCAS identifies other traffic in the area which may become a threat to the aircraft in a short period of time, and an RA is presented to the pilot when there is imminent threat to the aircraft of a collision. The RA can provide commands to the pilot corresponding to a collision avoidance maneuver.
Recently, a traffic information system referred to as automatic dependent surveillance broadcast ("ADS-B") has evolved. The ADS-B system is capable of broadcasting position, velocity, and status information from an aircraft at regular intervals using position information obtained from onboard navigation systems. The ADS-B system may use a mode S transponder or other transmitter, and provide transmissions at regular intervals. As such, ADS-B transmitters need not be interrogated by another aircraft.
Another type of traffic information system is a traffic information services broadcast ("TIS-B") system. The TIS-B system is typically a ground station which provides position, velocity, and status information of air and ground vehicles using information obtained from ADS-B, primary surveillance radar, secondary surveillance radar, and other systems. The TIS-B ground station provides a squitter message on a periodic basis similar to the squitter message in the ADS-B system. As such, the ADS-B system is commonly seen as an air-to-air link, and the TIS-B is seen as a ground-to-air link. Each of the systems provides a data link to another aircraft. A further source of traffic information may be provided from air traffic control ("ATC") via looking out the window or through a ground based or other radar system. Such information can then be communicated by the ATC to any aircraft within the vicinity of the airport.
With a variety of systems available to provide traffic information to the pilot, there is the opportunity to receive traffic information from more than one source; if so, then a correlation algorithm may be applied to determine whether targets provided from one traffic system correlate with targets provided from a second traffic system. For uncorrelated traffic, a choice may be provided by using a traffic source selection method such as the one disclosed by Carrico in U.S. Pat. No. 7,148,816. In addition, a pilot operating an aircraft located on the ground tends to use a narrow display range which provides for better surface traffic information and improves his or her ground situational awareness. Although this surface traffic information is useful, the lack of additional useful information about off-screen traffic comprised of aircraft approaching to land or landing on a runway, taking-off from the runway, and/or operating a missed approach of the runway limits the pilot's situational awareness of nearby traffic approaching the airport. In addition, with an expected increase of airborne traffic in the foreseeable future, the chance of cluttering the information presented on the display unit may possibly increase, thereby possibly interfering with the pilot's efficient access to more applicable information.

Methods for presenting traffic information on an aircraft display unit


A method of forming a gate electrode in a semiconductor device is disclosed. A method of forming a gate electrode in a semiconductor device according to the present invention includes steps of: forming a gate oxide layer, a polysilicon layer, a diffusion barrier layer, a metal layer and a mask layer on a semiconductor substrate, in sequence; patterning the mask layer, the metal layer and the diffusion barrier layer to the first width; patterning the mask layer, the metal layer and the diffusion barrier layer having the first width to a second width by wet etching; forming a spacer on the side walls of the mask layer, the metal layer and the diffusion barrier layer having the second width; and patterning the polysilicon layer and the gate oxide layer using the mask layer and the spacer as an etch barrier.

1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a tungsten gate electrode.
2. Description of the Related Art
In general, a polysilicon layer is used for a gate electrode material of a MOSFET. However, as high integration of a semiconductor device, the line width of the gate electrode is significantly reduced. Therefore, in case of a polysilicon gate electrode, it is difficult to obtain low resistivity required for the high integration device. Accordingly, a tungsten layer has been researched as the gate electrode material, recently.
In case of a tungsten gate electrode, gate re-oxidation process is generally performed after forming a tungsten gate electrode, for improving the reliability of a gate insulating layer. However, when performing the gate re-oxidation process, the side wall of a tungsten layer 5 is excessively oxidized due to its fast oxidation rate, to occur abnormal oxidation of the tungsten layer 5, as shown in FIG. 1, thereby deteriorating properties and reliability of a device. In FIG. 1, reference numbers 1, 2, 3 and 4 indicate a semiconductor substrate, a gate oxide layer, a polysilicon layer and a diffusion barrier layer, respectively. Furthermore, reference numbers 6 and 7 indicate a mask pattern used for etch barrier and a thermal oxidation layer grown by abnormal oxidation, respectively.
To solve the above problem, a method of forming a tungsten gate electrode using a spacer, is suggested. Referring to FIG. 2 when performing etch process to form a gate electrode, the tungsten layer 5 and the diffusion barrier layer 4 are etched and a spacer 8 is then formed on the side wall of the etched tungsten layer 5 and diffusion barrier layer 4. Therefore, when performing subsequent gate re-oxidation process, abnormal oxidation is not occurred on side wall of the tungsten layer 5.
Thereafter, as not shown in FIG. 2, the polysilicon layer 3 and the gate oxide layer 2 are etched to form a gate electrode. Next, LDD ion implantation and gate re-oxidation processes are performed, respectively.
As described above, when performing gate re-oxidation process, abnormal oxidation is not occurred on side of the tungsten layer 5 by the spacer 8. However, since the width of the gate electrode increases due to the spacer 6, it is difficult to apply high integration semiconductor device required for a gate electrode with fine line width.

Method of forming gate electrode in semiconductor device

Hyundai Electronics Industries Co., Ltd.


A unique identifier which substantially prevents product counterfeiting, wherein the unique identifier can be produced in a very cost-effective manner. The unique identifier is suitable not only for use as a product identifier but also for authorization, for example for securing physical or electronic accesses, such as doors, computer programs or the like.

Product counterfeiting has become a significant factor in business. According to current reports, already ten percent of world trade is done through copies or counterfeits through product knock-offs, illegal surplus production, parallel or re-imports which cause damages internationally in a range of 300 billion Euros. In Germany, according to the German machine and equipment producers association, about two thirds of the manufactures of capital equipment are affected by product counterfeiting.
Product counterfeiting significantly affects the labor market, wherein 50,000 jobs are lost in Germany alone according to estimates by the ministry of justice due to product counterfeiting. In all of Europe as many as 300,000 jobs are affected.
Thus, capital equipment manufacturers are affected by product counterfeiting in particular, since they had to make substantial investments to develop, test, produce and advertize their quality products. A counterfeiter does not have to make these investments so that tagging on to the success of the original, he saves substantial cost and therefore has much higher profit margins, in particular when the counterfeit products are of inferior quality or the counterfeiter can sell at substantially lower prices.
Another downside is that manufacturers lose their reputation in the marketplace when counterfeits with inferior quality and safety enter the marketplace but are not immediately identifiable as counterfeits but are associated with the original manufacturers.
Another big problem besides the economic damages through products counterfeiting are the accidents and health risks that may be associated with counterfeit products. This is the case in particular when counterfeit products are not produced according to the same standards as the originals. This applies in particular to the drug industry, but also in other safety critical business areas like machinery and equipment, inferior counterfeit products can have significant consequences.
Thus it is an objective of capital equipment manufacturers to prevent product counterfeiting as far as possible. For this purpose, various protective technologies or technical safety devices like, for example, holograms, safety labels, micro color codes, digital watermarks and similar are developed, wherein the present emphasis is on developing product identifiers, whose features cannot be counterfeit.
For example, modern paper money uses a plurality of safety features intended to make counterfeiting impossible. Among these are, for example, Euro banknotes using special paper, optical safety features like watermarks, anti-copy grids, Melier fibers, safety threads, special dyes, iris printing, foil elements, holograms, micro-perforations, micro-lettering, fluorescent colors, optically variable ink, gloss effects, see-through windows, see-through registers, haptic safety features like paper feel and embossing and acoustic safety features regarding the sound of banknotes during crumpling or rubbing. Additionally, features are being used that are machine detectable like infrared dyes, magnetic elements, electric conductivity and similar.
A disadvantage of these product identifiers, however, is that their counterfeit safety is only provided as long as the product identifier has a technological edge over the counterfeiters which, however, typically is only temporary. Additionally, such multilayered product identifiers are rather expensive and can therefore only be effectively used for high-price products. Eventually, also a counterfeiting of particularly safe product identifiers cannot be completely prevented since it is very difficult for very complex product identifiers for a consumer and also for a seller to identify whether it is an original product identifier or a counterfeit.

Unique identifier, method for providing the unique identifier and use of the unique identifier


An electronic connector comprises: an insulating body, a plurality of terminals contained in the insulating body, a metal shield housing the insulating body, and a light pipe covering the metal shield. The insulating body and the metal shield define a mating space having an inserting opening. The light pipe is made of transparent, compressible LSR and comprises a base body and a ring sealing gasket in front of the base body covering the periphery of the insertion opening. When the electronic connector is assembled in a panel, the sealing gasket is held between a hold of the panel and the metal shield to form a sealing structure, so that the electronic connector and assembly comprising the same are excellently waterproofed.

As electronic and information technology for decoration or indication etc. develops, electronic products adapt more and more light effects.
Chinese patent application No. 200810124035.0 discloses an electronic connector assembly 8 having a light emitting device for decorating the design by light effect. The electronic connector assembly 8 comprises an electronic connector 80, light emitting components 81 indicating the on-off status of the electronic connector 80 and decorating the electronic connector 80, and a transmission component 82 cooperating with the light emitting component 81. The electronic connector 80 comprises an insulating body 800, a plurality of terminals (not shown) positioned in the insulating body 800, and a metal shield 802 covering the insulating body 800. The light emitting components 81 are two opposite LEDs (light-emitting diodes) or EL (electroluminescence) slices. The transmission component 82 is made of a material with high transmission rate and comprises a transmission base 820 and two transmission side bodies 821 on two sides of the transmission base 820. The front end of the transmission base 820 is provided with a transmission ring 822. One side of the transmission body 821 is connected to the transmission base 820, and the other side thereof is adjacent to the light emitting component 81. The physical dimension of the transmission body 821 corresponds to the light emitting component 81. An exposed surface of the transmission ring 822 is coated with dispersion materials to achieve an effect of well-distributed illumination.
In assembly, the light emitting components 80 is fixed to cover the electronic connector 80, and the light emitting components 80 are distributed on the two sides symmetrical to the axis of center line of transmission ring 822 so that light from the light emitting component 81 transmits out through the transmission ring 822. Accordingly, the electronic connector assembly 8 can produce a ring source which can generate well-distributed light with materials coated on the exposed surface of the transmission ring 822, thereby curing the defect of poor light effect.
However, for electronic products working in poor or special conditions, waterproofing is important. Obviously, the above electronic connector assembly 8 cannot comply with such requirement because the shapes of the transmission ring 822 and the metal shield 802 do not correspond. They cannot be closely combined or achieve sealing with the panel. Therefore, further work is required to make the electronic connector and the assembly thereof complying with more and stricter requirements.

Electronic connector and assembly comprising the same


The present invention is directed to a compound of formula I,

Unsaturated monomers are useful for synthesizing a variety of polymers. The polymers can have various properties based upon the mixture of monomers that make up the composition of the polymer. Functionalized unsaturated monomers allow for the production of polymers having the functional groups. Polymers comprising the residue of unsaturated monomers are useful in a variety of industries including, but not limited to, coatings. Novel unsaturated monomers and polymers that provide new and/or improved properties to compositions comprising the same are desired.

This patent is subject to a terminal disclaimer.

Carbamate functional monomers and polymers and use thereof

Abstract: wherein R1 comprises hydrogen, an alkyl group, or an aryl group; R2 comprises hydrogen or a methyl group; R3 comprises a divalent organic group; R4 comprises a divalent organic group; and X comprises oxygen, NH, or N(R5), wherein R5 comprises a monovalent organic group. The present invention is also directed towards polymers comprising a pendant carbamate-functional moiety comprising the structure:

Abstract: wherein R1 comprises hydrogen, an alkyl group, or an aryl group; R2 comprises hydrogen or a methyl group; R3 comprises a divalent organic group; R4 comprises a divalent organic group; and X comprises oxygen, NH, or N(R5) wherein R5 comprises a monovalent organic group. The present invention is also directed to methods of preparing such compounds and polymers, compositions comprising such polymers, and coatings produced from such compositions.


Disclosed herein are genetic markers for pig litter size, methods for identifying such markers, and methods of screening pigs to determine those more likely to produce larger litters. The markers are based upon the presence or absence of certain polymorphisms in the pig estrogen receptor gene. Preferably, the polymorphism is a restriction fragment length polymorphism (RFLP). A 3.7 kilobase fragment and a 4.3 kilobase fragment obtained by digesting pig genomic DNA with the restriction endonuclease Pvu II and detecting the fragments with a probe comprising a detectably labeled human estrogen receptor gene are associated with increased litter size.

Reproductive efficiency, which can be defined as the number of pigs produced per breeding female, is the major limiting factor in the efficient production of pork. The number of pigs born alive in the United States averages approximately 9.5 pigs per litter. Heritability for litter size is low (10% -15%), and standard genetic methods of selecting breeding females on the basis of past litter size have not been effective. Therefore, there is a need for an approach that deals with selection for reproduction at the cellular or DNA level.
Chinese breeds are known for reaching puberty at an early age and for their large litter size. American breeds are known for their greater growth rates and leanness. Thus, it would be desirable to combine the best characteristics of both types of breeds, thereby improving the efficiency of U.S. pork production. These efforts would be greatly assisted by the discovery of genes or genetic markers that are associated with increased litter size in pigs.
Reproduction in mammals takes place in response to a chain of events that occur between the brain and the reproductive organs. The steroid hormones, such as estrogen, play a crucial role. Steroid hormones interact with cells and tissues, initiating a series of events that result in the ability to reproduce successfully.
In pigs, estrogen, which is produced mainly by the ovaries, has profound effects on the uterus, brain, and pituitary gland. Estrogens modulate the onset of puberty, reproductive behaviors, cyclic release of gonadotropins, and feeding behavior. The effects of estrogens take place as a result of the binding of estrogen to specific receptor proteins found in the nucleus of the estrogen-responsive cells. McEwen, et al., Recent Prog. Horm. Res., 38:41-92 (1982), incorporated herein by reference.
The gene responsible for coding for the human estrogen receptor has been identified, and it is publicly available from the American Type Culture Collection. See ATCC Catalog Sept. 1990, page 112, entry 57681, incorporated herein by reference. The probe is named pOR3 and is 1.3 kb. Green et al., Nature (London) 320:134-139 (1986), incorporated herein by reference. The human gene is known to be polymorphic as a result of restriction fragment length polymorphism (RFLP) analysis. Castagnoli et al., Nucl. Acids Res., 15:886 (1987) and Coleman et al., Nucl. Acids Res., 16:7208 (1988), both of which are incorporated herein by reference. The functional differences relating to these different genotypes are not well understood, but they have been implicated in increased spontaneous abortions in humans with breast cancer. Lehrer et al., The Lancet, 335:622-624 (Mar. 17, 1990), incorporated herein by reference.
The estrogen receptor gene has been isolated and sequenced for other species, but not for pigs. Koike et al., Nucl. Acids Res., 15:2499-2513 (1987), incorporated herein by reference, reports the isolation and sequencing of a cDNA clone of the rat uterus estrogen receptor. The authors state that a comparison of rat, human, and chicken estrogen receptor sequences indicates the presence of three highly conserved regions, suggesting that these regions play important roles in estrogen receptor function.
In addition, Koike et al. Biochemistry 26:2563-2568 (1987), incorporated herein by reference, reports the partial characterization of the porcine estrogen receptor binding site. The paper reports a fragment of about 30 kDa that probably corresponds to the hydrophobic C-terminal-half region and has a greater than 90% homology with the corresponding rat, human, and chicken sequences.
RFLP analysis has been used by several groups to study pig DNA. Jung et al., Theor. Appl. Genet., 77:271-274 (1989), incorporated herein by reference, discloses the use of RFLP techniques to show genetic variability between two pig breeds. Polymorphism was demonstrated for swine leucocyte antigen (SLA) Class I genes in these breeds. Hoganson et al., Abstract for Annual Meeting of Midwestern Section of the American Society of Animal Science, Mar. 26-28, 1990, incorporated herein by reference, reports on the polymorphism of swine major histocompatibility complex (MHC) genes for Chinese pigs, also demonstrated by RFLP analysis. Jung et al. Animal Genetics, 20:79-91 (1989), incorporated herein by reference, reports on RFLP analysis of SLA Class I genes in certain boars. The authors state that the results suggest that there may be an association between swine SLA/MHC Class I genes and production and performance traits. They further state that the use of SLA Class I restriction fragments, as genetic markers, may have potential in the future for improving pig growth performance.
Prior to the present invention, RFLP analysis has not been applied to the pig estrogen receptor gene, which has not even been isolated or characterized. The present invention overcomes these deficiencies. It provides genetic markers, based upon the discovery of polymorphisms in the pig estrogen receptor gene, which relate to increased litter size in pigs. This will permit genetic typing of pigs for their estrogen receptor genes and determining the relationship of specific RFLPs to increased litter size. It will also permit the identification of individual males and females that would be expected to produce a litter size larger than the average for their breed. Thus, the markers will be selection tools in breeding programs to develop lines and breeds that produce litters containing a larger number of offspring.

Method for determining genetic marker for increased pig litter size

Iowa State University Research Foundation, Inc.


A biquad wideband signal processing circuit can operate over bandwidths of 50 MHz to 20 GHz or more. The biquad circuit employs a configuration of integrators (transconductors), buffers, and scalable summers that can be implemented using deep sub-micron CMOS technology. Combining this scaling with high gain/high bandwidth enables implementation of feedback and programmability for broadband analog signal processing. A biquad circuit implementing a number of parallel integrator lines having adjustable gain provides greater accuracy, stability, and bandwidth, and allows for control of process variations and temperature variation in real-time.

Increases in signal bandwidth and data rates have prompted the development of new signal processing techniques to solve challenges associated with wideband signals. Increased signal bandwidth has also made new applications possible, including ultrawideband (UWB) technology-based active radio-frequency (RF) identification (ID) in heterogeneous environments. In addition, increasing signal bandwidth improves ranging accuracy, making wideband technologies especially attractive for radar, imaging, and other applications.
Unfortunately, fundamental scaling limits on clock speed, switching, heat dissipation, and difficulty of fault recovery make digital logic unsuitable for wideband signal processing. For example, today's DSP technology cannot process the wideband signals required for emerging applications such as high-definition TV, software-defined radio, cognitive radio, 4-G handheld services, white spaces, UWB-based services, and real-time GHz/THz medical imaging. Beyond the need for greater speed and bandwidth processing capability, methods for reducing power consumption also have huge appeal and utility in many signal processing applications. For example, a huge premium is placed on power consumption in mobile devices; high-speed DSPs are a huge drain on the battery life of cell-phones and PDAs.
For wideband applications, the Nyquist rate is in the multiple giga-samples per second (GSPS) range and, hence, only relatively simple signal processing can be implemented and often requires highly pipelined and parallel processing architectures. Going forward, DSP technology is unlikely to reach the capabilities required by these applications because the limits of CMOS-based digital signal processing structures are not expanding according to Moore's Law any more. In fact, deep sub-micron CMOS gates have widths measured in molecules, suggesting that transistor sizes (and switching speeds) are nearing their fundamental limits. In other words, there is little room to increase the bandwidth processing ability of DSP technology because transistor switching speed, which is inversely related to transistor size, cannot get much faster.
Analog logic, in turn, has its own limitations. Because analog circuits are not formed of truly independent blocks, changing one block of analog logic can force changes in every other block in the circuit. In addition, advances in process technology occur so quickly that application-specific designs often become obsolete before they are fabricated. Finally, analog circuits are neither fully reconfigurable nor fully programmable.