A method of allowing a secure and transparent communication between a user device and servers of a data access network system via a firewall and a gateway is described. The method includes the step of designating a plurality of ports in the firewall for the gateway, each corresponding to one of a number of ports in the gateway. Each of the gateway ports can be dynamically assigned to correspond to the port of one of the servers. The method also includes a step of proxifying an object reference used in a user request for a target server from the user device in order to establish secure connection between the user device and the target server. This step is first performed by replacing the IP address and the port number of the target server of the user request with a dynamically assigned gateway port and the IP address of the gateway. Then the dynamically assigned gateway port and the gateway""s IP address are mapped to the port of and IP address of the target server such that the user request is not required to expose the IP address and port number of the target server at the gateway.

1. Field of the Invention
The present invention pertains to communication networks. More particularly, this invention relates to providing a secure and transparent network gateway that does not require complex configuration to the associated firewall.
2. Description of the Related Art
In an open-ended network system such as Internet, a firewall is typically employed between servers and remote accessing clients (e.g., user terminals). The main purpose of the firewall is to control external accesses to and from the servers. This means that the firewall allows the external accesses to the servers to cross the firewall in a controlled fashion. FIG. 1 shows one such prior art arrangement of the firewall.
In FIG. 1, communication between the user terminal 11 and the target object servers 12 is conducted using Object Request Broker (ORB) transparent protocol over a TCP/IP (Transmission Control Protocol-Internet Protocol) communications protocol. When tie user terminal 11 wants to access a particular object in one of the target object servers 12, the terminal 11 uses an Interoperable Object Reference (IOR) to issue an object invocation using an object reference of the requested object. The object invocation is referred to as the user access request below. The object reference typically includes the TCP/IP port number and IP (Internal Protocol) address of the object. The port number and IP address specify the target object server that contains the requested object.
The firewall 13 has a number of TCP/IP ports and IP addresses, each configured or opened to correspond to one of the servers 12. When the user access request enters the firewall 13, the firewall 13 checks if the port and IP address specified in the user access request are opened in the firewall 13. If the port and IP address are opened in the firewall 13, the request passes through the firewall 13 and reaches the designation target object server. Then a communication channel can be established for transferring the requested object to the user terminal 11. If the firewall 13 does not have the corresponding port opened, the firewall 13 does not let the user access request to pass through it and does not establish communication channel for the user access request.
One disadvantage of this prior art firewall is that the firewall has statically configured target object ports and IP addresses. Adding new target object servers requires reconfiguration of the firewall. This can only be done by opening new ports and IP addresses. For security reasons, these ports and IP addresses cannot be opened ahead of time because it creates security loopholes. This means that the firewall does not have any flexibility.
One prior solution to solving the problem of accessing the target objects is to employ a CORBA (Common Object Request Broker Architecture) gateway behind the firewall, as can be seen from FIG. 2. The CORBA gateway can also be implemented as part of the firewall. One such prior CORBA gateway is the Wonderwall manufactured and sold by Iona Technologies PLC from Ireland.
In FIG. 2, the firewall 22 is configured to have one port number and IP address designated to the CORBA gateway 23. All user access requests to the servers 24 are forwarded to the CORBA gateway 23 by the firewall 22. The CORBA gateway 23 maps all of the servers 24. Each of the target object servers 24 has an individual IP address and at least one port number. The CORBA gateway 23 includes a mapping lookup table that specifies the port numbers and IP addresses of all the servers 24 connected to the CORBA gateway 23. Each pair of port number and IP address stored in the mapping lookup table of the CORBA gateway 23 can be retrieved from the lookup table using an object key. The object key is part of the object reference from the user access request. Whenever a user access request passes through the gateway 23, the request has to be examined and routed by the gateway 23 according to the content of the object key in the user access request.
In order for a user access request to access a particular target object server, the object reference of the access request is first proxified at the user terminal (e.g., terminal 21) using the IOR such that the proxified request points to the CORBA gateway 23, instead of the intended target object server. The proxification is done by specifically replacing the port number and IP address of the object reference used by the user access request that point to the particular target object server with the port number and IP address of the CORBA gateway 23. To access the target object server, a TCP/IP connection between the user terminal (e.g., the terminal 21) and the gateway 23 must first be established. This is done through the ORB protocol in the user terminal 21 upon receiving the object reference from the client application. In this case, the firewall 22 must have the IP address and port configured in order for the TCP/IP connection to go through. Once the TCP/IP connection is established, the ORB protocol in the user terminal 21 sends the request that contains the object key in the request header.
At the CORBA gateway 23, the server port number and IP address are extracted from the request header by using the object key of the access request to search the mapping lookup table in the CORBA gateway 23. The CORBA gateway 23 establishes another connection (i.e., gateway-target object server) and forwards the request over this connection to the target object server. This dynamically maps the port number and IP address of a particular target object server to the CORBA gateway 23.
However, disadvantages are associated with the prior CORBA gateway. One disadvantage associated is that the gateway typically does not allow the firewall to provide end-to-end security for the communication (e.g., authentication, confidentiality, and integrity). This means that SSL (secure socket layer) protocol cannot be used, for example, between the firewall 22 and the servers 24 as a single session. This is due to the fact that the CORBA gateway requires access to request header in order to extract the object key. Connections have to be terminated at the firewall/gateway and encrypted data have to be decrypted to allow examination of the object reference headers and to make filtering decisions. If SSL is used, secure communication can only establishes two separate sessions. One of which is between the user terminal and the firewall and the other is between the firewall and the target object servers. This means that a single SSL session cannot be established between the user terminal and the target object servers. As a consequence, encryption of data cannot be preserved from end-to-end. There is no direct authentication between the user terminal and the target object servers. The gateway has to be trusted to pass client and target object server credentials (e.g., identity certificate). However, this credential must be passed as additional payload. This means that the target object server must be modified to manage user credentials.
Another disadvantage is that the configuration of access control list based on object keys of the prior CORBA gateway is static, complex, and manual. Moreover, the prior CORBA gateway does not provide a mechanism for authenticating clients and target object servers at the firewall. Depending on security policy, the client authentication may be necessary at the firewall before commencing traffic to the target object servers. This protection is necessary for malicious outside attacks and the firewall creates a first line of defense. Authenticating target object servers at the firewall may be necessary in situations where security policy requires that an authorized resource is available at the target address, not a Trojan horse. A client or user terminal may use a Trojan horse to penetrate Internet network.
One feature of the present invention is to provide a secure and transparent network connection for an open-ended network system.
Another feature of the present invention is to provide a secure and transparent network gateway that does not require complex configuration to the associated firewall.
A further feature of the present invention is to provide a secure and transparent network gateway that simplifies the proxification of Interoperable Object References (IORs) and does not expose dynamically assigned ports of the gateway to external client applications.
A still further feature of the present invention is to provide a secure and transparent network gateway that maps a dynamically assigned gateway port to specific destination IP and port at the servers.
A method of allowing a secure and transparent communication between a user device and servers of a data access network system via a firewall and a gateway is described. The method includes the step of designating a plurality of ports in the firewall for the gateway, each corresponding to one of a number of ports in the gateway. Each of the gateway ports can be dynamically assigned to correspond to the port and IP address of one of the servers. The method also includes a step of proxifying an object reference that refers to a target server of the servers to be accessed by a user request from the user device in order to allow a single end-to-end secure session between the user device and the target server to be established via the gateway. This step is performed by first replacing the IP address and the port number of the target server of the user request with a dynamically assigned gateway port and the IP address of the gateway. Then the dynamically assigned gateway port and the gateway""s IP address are mapped to the port of and IP address of the target server such that the user request is not required to expose the IP address and port number of the target server and the single end-to-end secure session between the user device and the target server is established.
In a data access network system having servers, a client access device, a firewall, and a first and a second gateway serially coupled between the servers and the firewall, a method of establishing secure connection between the client device and a target server of the servers is described. The method includes the step of designating a plurality of ports in the firewall for the first gateway, each corresponding to one of a number of ports in the first gateway. Each of the gateway ports of the first gateway can be dynamically assigned to correspond to a port of the second gateway. Each of the gateway ports of the second gateway can also be dynamically assigned to correspond to a port of the servers. The method also includes a step of proxifying an object reference that refers to the target server to be accessed by a user object invocation request from the user device in order to establish a single end-to-end secure session between the user device and the target server. This step is performed by (1) replacing the IP address and the port number of the target server within the object reference with a dynamically assigned gateway port and the IP address of the first gateway, (2) mapping the dynamically assigned gateway port and the first gateway""s address to a dynamically assigned gateway port and the IP address of the second gateway, and (3) mapping the dynamically assigned gateway port and the IP address of the second gateway to the port and IP address of the target server such that the user request is not required to carry the IP address and port number of the target server. Once the object reference is proxified and proper mapping at the gateway is established, the user then may issue an object invocation request using the proxified object reference. When the user transmits the object invocation request by the client application in the user terminal, a chain of TCP/IP connections (i.e., user terminal-gateway, gateway-gateway, gateway-object) is established from the user terminal. Once such chain of TCP/IP connections is established, the underlying client application in the user terminal establishes over these connections a single SSL session with the target object server. After the SSL connection is established, the user""s object invocation request is sent.

Method and apparatus for allowing a secure and transparent communication between a user device and servers of a data access network system via a firewall and a gateway

Hewlett-Packard Development Company, L.P.


A limited scan antenna wherein radiating element and phase requirements are reduced by positioning the radiating elements to radiate through a radial waveguide. The longer wavelength in the radial waveguide relative to the free space wavelength permits a wider actual separation, while maintaining grating lobe suppression. Wave refraction at the interface of the radial waveguide with free space is a function of the guide wavelength and determines the maximum scanning capability of the antenna.

1. Field of the Invention
The invention relates to antenna systems and more particularly to electronic scanning systems for scanning a given sector with a minimum number of radiating elements.
2. Description of the Prior Art
Beam scanning in electronically scanned antennas is achieved by controlling the excitation phase at the array elements to establish phase gradients across the array which determine the beam positions. In these systems the maximum scan angle that may be achieved without establishing grating lobes (additional principle lobes) in real space is determined by the interelement spacing in the array. A uniformly spaced array of isotropic elements may have a maximum scan angle of 90.degree. on either side of the perpendicular to the array surface when the spacing in the scanning plane is less than 1/2 wavelength. This scanning range is decreased, however, to a maximum of approximately 20.degree. on either side of the perpendicular when the spacing is increased to 3/4 of a wavelength. Because of this spacing limitation conventionally designed high gain electronically scanned antennas require a significant number of radiating elements with associated control and phase shift of components.
Early efforts for reducing the significant cost of electonic scanned arrays utilized small electronically steerable arrays located in the focal region of a microwave optical system. These systems, however, exhibited low aperature efficiency, because only a portion of the aperture was illuminated for each scan angle.
Significant improvements in aperature efficiency and antenna component reductions were realized with the development of the overlapping subarray technique. This technique uses appropriate combinations of orthogonal beamformers and switching networks to achieve the desired scanning capability and beam characteristics. In these designs the primary collimating device is a lens or reflector with subarraying networks, such as, Butler matrices or Rotman lenses having apertures located in the focal regions. These antennas exhibit the unfavorable characteristics of a physically deep configuration which is concomitant with optically fed array systems. This physical depth may be reduced by substituting a Butler matrix for the primary collimating lense. This is not an attractive approach for large aperature antennas because of the complexity of the Butler matrix.
Another approach uses partially overlapped or interlaced subarrays. These, however, exhibit poor side lobe performance with reduced scanning capabilities relative to the fully overlapped subarrays.
Many of the shortcomings of the above prior art system are overcome by the invention disclosed in U.S. Pat. No. 4,507,662 assigned to the assignee of the present invention. In this device radiating elements of an antenna array are correspondingly coupled to a second array having element spacing substantially smaller than that between the radiating elements. This second array is space coupled, through a space coupling region, to a third array, which is scannable in the space coupling region. The third array has fewer elements than the second array and is approximately of the same physical size and length. Each scan angle of operation of the third array establishes a phase distribution across the second array, which is coupled to radiating array, thereby providing radiation in free space, at a scan angle corresponding to the scan angle of the third array. Since the feed has fewer elements than the radiating array, an element and associated component savings are realized. The element saving, however, is somewhat offset by the additional elements utilized in the space coupling region.

Radial waveguide channel electronic scan antenna


An improved active pixel sensor soft reset circuit for reducing image lag while maintaining low reset kTC noise. The circuit pulls down the sensor potential to a sufficiently low level before the soft reset function is completed. The level to which the sensor potential is pulled is set between 0 and the critical potential at which the reset transistor will be on when the soft reset function begins. The timing of the pull down function is such that the sensor is stabilized at the low potential before the soft reset function completes. In one embodiment, the sensor potential is pulled down using a pull-down circuit, which may consist of a CMOS type inverter. In another embodiment, the sensor potential is pulled down by the bit line. Two ways in which the bit line may be pulled down are natural discharge, or by increasing the bias on the loading transistor. Two ways in which the bias on the loading transistor may be increased are a biasing circuit, or by using a pull-down transistor. The active pixel sensor may be implemented with any suitable sensor technology, such as photodiode, photogate, or pinned diode.

The present invention relates to metal oxide semiconductor (MOS) image sensors and, more particularly, to reset circuits for active pixel sensors (APS) in a CMOS array.
Integrated circuit technology has revolutionized various fields including computers, control systems, telecommunications, and imaging. There are a number of types of semiconductor imagers, including charge coupled devices, photodiode arrays, charge injection devices, and hybrid focal plane arrays. Some sensors are referred to as active pixel image sensors (APS). An active pixel image sensor is defined as an image sensor technology that has one or more active transistors within the pixel unit cell. Some types of active pixel sensor technologies include the amplified MOS imager (AMI), charge modulation device (CMD), volt charge modulated device (VCMD), base stored image sensor (BASIS), and the static induction transistor (SIT).
One prior art circuit using a CMOS photodiode-type active pixel sensor is shown in xe2x80x9c128xc3x97128 CMOS Photodiode-Type Active Pixel Sensor With On-Chip Timing, Control And Signal Chain Electronics,xe2x80x9d by R. H. Nixon et al., Proceedings of the SPIE-The International Society for Optical Engineering, Volume 2415, 1995, pages 117-123. FIG. 2 of that reference has been reproduced herein as FIG. 1.
FIG. 1 is a schematic diagram of a CMOS APS, along with readout circuits. The pixel unit cell 25 consists of a photodiode (PD), a source-follower input transistor SF1, a row-selection transistor ROW and a reset transistor RESET which controls lateral blooming through proper biasing of its gate. The drain diffusion 50 is coupled to the voltage source VDD. At the bottom of each column of pixels, there is a column circuit 60 consisting of a load transistor VLN1 and two output branches to store the reset and signal levels. Each branch consists of a sample and hold capacitor (CS or CR) with a sampling switch (SHS or SHR) and a second source-follower SF2 with a column-selection switch (COL). The reset and signal levels are read out differentially, allowing correlated double sampling to suppress 1/f noise and fixed pattern noise (not kTC noise) from the pixel. A double delta sampling (DDS) circuit shorts the sampled signals during the readout cycle reducing column fixed pattern noise. These readout circuits 60 are common to an entire column of pixels. A read-out circuit 70 that is common to the entire array includes load transistors (VLN2) of the second set of source followers (VLP) and the subsequent clamp circuits CLAMP and output source followers SF3 and SF4.
Timing for the readout sequence is as follows. After a row has been selected, the signal that is present on each column pixel in that row is sampled (SHS) onto the holding capacitor CS. Next, each pixel in the row is reset (RESET). This is followed by sampling the reset level (SHR) onto holding capacitor CR. A simplified expression for the output voltage of the reset branch of the column circuit is given by:
Vcolxe2x80x94R≅xcex2{xcex1[Vpdrxe2x88x92Vtpix]xe2x88x92Vtcolr}
where xcex1 is the gain of the pixel source-follower, xcex2 is the gain of the column source-follower, Vpdr is the voltage on the photodiode after reset, Vtpix is the threshold voltage of the pixel source-follower n-channel transistor, and Vtcolr is the threshold voltage of the column source-follower p-channel transistor. Similarly, the output voltage of the signal branch of the column circuit is given by:
Vcolxe2x80x94S≅xcex2{xcex1[Vpdsxe2x88x92Vtpix]xe2x88x92Vtcols}
where Vpds is the voltage on the photodiode with the signal charge present and Vtcols is the threshold voltage of the column source-follower p-channel transistor. Experimentally, the peak to peak variation in Vtcolrxe2x88x92Vtcols is typically 10-20 mV. It is desirable to remove this source of column-to-column fixed pattern noise FPN. JPL has previously developed a double delta sampling (DDS) technique to eliminate the column-to-column FPN. This approach represents an improved version of the DDS circuitry.
Sequential readout of each column is as follows. First a column is selected. After a settling time equivalent to one-half the column selection period, the DDS is performed to remove column fixed pattern noise. In this operation, a DDS switch and two column selection switches on either side are used to short the two sample and hold capacitors CS and CR. Prior to the DDS operation the reset and signal column outputs (Vcol_R and Vcol_S) contain their respective signal values plus a source follower voltage threshold component. The DDS switch is activated immediately after CLAMP is turned off. The result is a difference voltage coupled to the output drivers (VR_OUT and VS_OUT) that is free of the voltage threshold component.
One problem of this circuit is that the implementation of the active pixel cell 25 continues to have the problems related to the design choice between hard reset and soft reset implementations. The choice between these implementations determine how the reset signal RST and the voltage on the drain diffusion 50 (hereafter designated as VRST) will be controlled. In the implementation illustrated in FIG. 1, a soft reset implementation is shown, in that the voltage VRST on the drain diffusion 50 is shown to be VDD. This is a typical prior art implementation in which VRST=VDD=RST. One definition of a soft reset system is where the signal (shown as VDD on the drain diffusion 50 in FIG. 1) is greater than the reset voltage RST, minus a threshold voltage VT. This soft reset definition is illustrated in the equation:
soft reset: VRST greater than RSTxe2x88x92VTxe2x80x83xe2x80x83(1)
where the threshold voltage VT is a variable, depending on sensor potential. Also, the theoretical equation for the noise in a soft reset system is:                               soft                                xe2x80x83                              reset                                :                                          xe2x80x83                              Noise                =                              1            2                                                        KT              C                                                          (        2        )
In contrast, one definition of a hard reset system is where the VRST level is less than the reset signal RST minus the threshold voltage VT. This hard reset definition is illustrated in the equation:
xe2x80x83hard reset: VRST less than RSTxe2x88x92VTxe2x80x83xe2x80x83(3)
And the theoretical equation for the noise in the hard reset method is:                               hard                                xe2x80x83                              reset                                :                                          xe2x80x83                              Noise                =                              1            2                                                        KT              C                                                          (        4        )
The hard reset and soft reset equations (1) and (3) illustrate that there is a critical voltage VCR which marks the boundary between a soft reset and a hard reset. This critical voltage is defined by the equation:
critical voltage: VCR=RSTxe2x88x92VTxe2x80x83xe2x80x83(5)
The advantages of the hard reset method is that it is fast and uniform, but in theory it suffers from approximately twice the reset noise problems (kTC noise) of the soft reset method. In contrast, the soft reset method has less reset noise, but causes image lag, because the reset is incomplete due to the reset transistor operating in the subthreshold region.
The present invention is directed to a method and apparatus that overcome the foregoing and other disadvantages. More specifically, the present invention is directed to a method and apparatus for reducing image lag through an improved soft reset circuit for an active pixel sensor (APS).
An improved active pixel sensor soft reset circuit for reducing image lag is provided. The active pixel sensor circuit includes a sensor for outputting a sensor potential, and a reset transistor for resetting the sensor. A buffer transistor buffers the output of the sensor, and a row select transistor is used for the read-out function. The row select transistor is coupled between the buffer transistor and a bit line. The bit line is also coupled to a loading transistor.
In accordance with one aspect of the invention, the sensor potential is pulled down to a sufficiently low level during a pull down function that may be implemented before and/or during the soft reset function. If the sensor potential is pulled down during the soft reset function, the pull down time is made to be less than the soft reset time. The low level is set between 0 and the critical potential at which the reset transistor will be on when the soft reset function starts. The timing of the pull down function should stabilize the sensor at the low potential before the actual soft reset function begins.
In accordance with another aspect of the invention, the sensor potential is pulled down by a pull-down circuit. In one embodiment, the pull-down circuit may consist of an NMOS transistor and PMOS transistor, coupled together as a CMOS inverter.
In accordance with another aspect of the invention, the sensor potential may be pulled down by the bit line. The bit line in turn, may be pulled down in a number of different ways. One way for the bit line to be pulled down is through natural discharge. A way to increase the speed with which the bit line is pulled down is to increase the bias on the loading transistor. One way to increase the bias on the loading transistor is to use a special biasing circuit to increase the bias. Another way to increase the bias on the loading transistor is to use a pull-up transistor, which may be either an NMOS transistor or a PMOS transistor.
It will be appreciated that the disclosed method and apparatus for an improved active pixel sensor soft reset circuit is able to obtain the advantages of a hard reset, while maintaining the low reset (kTC) noise of a soft reset. The image lag problem of other soft reset implementation methods is reduced. Furthermore, the active pixel sensor may be implemented using any suitable technology, such as photodiode, photogate, or pinned diode.

APS soft reset circuit for reducing image lag


Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

1. Field of the Invention
The embodiments relate to semiconductor devices (e.g., field effect transistors, diodes, etc.) and, more specifically, to a semiconductor device with a p-n junction having reduced current leakage even in the presence of metal silicide defects that extend to (i.e., contact or traverse) the junction and an associated method of forming such a semiconductor device.
2. Description of the Related Art
In order to overcome problems associated with continued size scaling in semiconductor devices (e.g., field effect transistors, diodes, etc.), the designs for p-n junctions in such devices have become more complex. For example, in order to decrease the drain-induced barrier lowering (DIBL) associated with size scaling in field effect transistors, current designs for source/drain to channel junctions often include shallower source/drain regions, higher source/drain doping levels, halo regions, etc. Unfortunately, some of these current designs are more sensitive to defects which cause increased junction leakage and, thereby render the devices non-functional.

Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device

International Business Machines Corporation


A two-phase switched reluctance machine is provided using discontinuous core structures as the stator for low-cost, high-performance drives. This discontinuous stator core structure contains short flux paths and maximum overlap between the rotor poles and stator poles in the stator discontinuous core structures, regardless of the rotor position. Example configurations of such core structure include E-core, L-core and I-core configurations. Using less steel and magnet wire than in conventional SRM designs results in cost savings of stator material and winding material. Efficiency of this novel SRM is improved because of shorter flux paths resulting in reduction of core losses and decreased phase resistance resulting in reduction of copper losses. Two-phase simultaneous excitation of the novel SRM can reduce torque ripple during commutation as compared with existing two-phase SRMs.

Induction motors and universal motors are being used in most applications requiring constant-speed and low-horsepower, mainly because of their competitive cost. To replace such conventional motors, research has been conducted on single-phase switched reluctance motor ("SRM") drives over the last decade. However, single-phase SRM drives are not suitable for high performance applications since they have some inherent limitations, including low output power density and only a 50% duty cycle of torque generation. They also require an additional component in the form of permanent magnets or auxiliary windings for self-starting.
Because of the known deficiencies of single-phase SRMs, more attention has been paid to two-phase SRM drives, especially for high torque and/or high-efficiency applications. For instance, two-phase SRM drives are positioned as brushless motor drives in variable-speed applications, such as those found in home appliances and power tools. One drawback of conventional two-phase SRM drives is their cost. Two-phase SRM drives typically may require equal, more, or less steel and magnet wire than single-phase SRMs and multiphase (greater than 2 phases) SRMs. Thus, one of the ways that two-phase SRM drives can distinguish themselves in the marketplace is by reducing their cost in comparison to conventionally available SRMs and hence to all other machines that are in practice.
Accordingly, it is generally desirable to provide a low-cost, two-phase SRM drive that can be deployed in high torque and/or high-efficiency applications. The two-phase SRM drive should cost less than currently available two-phase SRM drives without having to sacrifice torque output or motor efficiency.

Switched reluctance machines with minimum stator core


An improved method for producing a thin layer having highly uniform thickness, which layer may be pre-coated on an undulating surface of a substrate element. A working layer of the material is formed having a thickness greater than the final thickness desired. An areal (XY) determination of working layer thickness is made by ellipsometry, laser interferometry, or x-ray diffraction, or other known means. A map of thicknesses to be removed from the free surface of the working layer is entered into the control system of a magnetorheological finishing apparatus. The working layer is mounted on a workpiece holder of the apparatus and correctly indexed to the machine. The machine then removes material by magnetorheological finishing as instructed by the control system to leave a residual layer having a very high degree of thickness uniformity at a nominal average thickness and a very high surface integrity.

1. Field of the Invention
The present invention relates to production of thin films; more particularly, to such films having a high degree of thickness uniformity; and most particularly, to a method wherein an magnetorheological fluid finishing system programmably removes material from a thin layer, which may have been previously coated to a non-uniform substrate to leave a layer having a very high level of thickness uniformity.
2. Discussion of the Related Art
Use of magnetically-stiffened magnetorheological fluids for abrasive finishing and polishing of substrates is well known. Such fluids, containing magnetically-soft abrasive particles dispersed in a liquid carrier, exhibit magnetically-induced plastic behavior in the presence of a magnetic field. The apparent viscosity of the fluid can be magnetically increased by many orders of magnitude, such that the consistency of the fluid changes from being nearly watery to being a very stiff paste. When such a paste is directed appropriately against a substrate surface to be shaped or polished, for example, an optical element, a very high level of finishing quality, accuracy, and control can be achieved. A typical MRF finishing system is the QED Technologies Q22 MRF System, available from QED Technologies, Rochester, N.Y., USA.
In a typical magnetorheological finishing system, a work surface comprises a vertically-oriented wheel having an axially-wide rim which is undercut symmetrically about a hub. Specially shaped magnetic pole pieces are extended toward opposite sides of the wheel under the undercut rim to provide a magnetic work zone on the surface of the wheel, preferably at about the top-dead-center position. The surface of the wheel is preferably an equatorial section of a sphere.
Mounted adjacent to the work zone is a substrate receiver and work holder for extending a substrate to be finished into the work zone. The finishing system may be programmed to move the work holder in a plurality of modes and speeds of motion to remove more or less material from the workpiece by varying the areal location of work and speed of travel of the workpiece through the work zone, and therefore the exposure time in the work zone. The finishing may be carried out at any desired angular orientation of the work zone on the carrier wheel, e.g., the workpiece may be positioned on a controllable bed, the carrier wheel positioned over the substrate, and a work zone provided at the bottom dead center position on the carrier wheel.
It is known in the art of thin layer fabrication to coat very thin layers of materials onto substrates. Such layers can be very useful in, for instance, the field of micro-electronics fabrication. For example, it is known to coat a thin layer of silicon on a glass surface of a silicon wafer, the glass being an insulator (xe2x80x9csilicon on insulatorxe2x80x9d, or SOI). It is highly desirable that the silicon layer be very uniform in thickness, typically about 100 nm, and not have cracks extending into or through the layer.
A serious problem can arise, however, in producing coatings requiring a very high level of thickness uniformity and surface integrity. Non-planarities in the substrate may not be followed conformably by the coatings but may tend to be filled in or rounded in the free surface of the coatings; thus, an actual coating may undesirably have thicker and thinner areas, depending upon the topography of the substrate to which it is coated. In the prior art, producing coatings of extreme thickness uniformity and surface integrity can require very complicated manufacturing process including chemical mechanical polishing.
Even in some of such applications, it can be necessary to mechanically or chemically-mechanically finish the upper surface of the coating, as by conventional optical polishing, to achieve a desired absolute thickness. However, such grinding, because of the mechanical stresses required, is known to leave residual microscopic stress fractures in the polished surface. For ultra-thin layers, such fractures may actually extend all the way through the layer, compromising the mechanical and electrical properties of the layer.
In use, the criterion for suitability of such a coating is not its absolute level of flatness but rather its absolute thickness, level of thickness uniformity, and level of surface integrity. Thus, what is needed is a means for providing an ultra-thin layer having very high thickness uniformity and high surface integrity, especially when coated on a substrate having surface non-planar excursions which may be as great as, or greater than, the thickness of the coated layer itself.
It is further needed to be able to provide such a layer with minimal residual stress damage to the layer.
It is a principal object of the invention to provide a method for producing thin layers, and especially on non-planar substrates, wherein the layer so produced has a high level of thickness uniformity and freedom from surface cracks.
It is a further object of the invention to provide a method for finishing of thin layers wherein the finishing leaves minimal stress fracturing of the free surface of the thin layer.
Briefly described, in an improved method for producing a thin layer having highly uniform thickness and freedom from surface or sub-surface cracking, a working layer of the material is formed at a thickness greater than the final thickness desired. The layer may be an independent element or may be formed as a coating on a carrier substrate. An areal (XY) determination of working layer thickness is made by a known technique, such as ellipsometry, laser interferometry, or x-ray diffraction. A currently preferred means is an AcuMap II device, available from ADE Technologies, Inc., Newton, Mass., USA. Data representing a map of thicknesses to be removed from the free surface of the working layer are entered into the control system of a magnetorheological finishing apparatus. The independent layer element or the coated substrate element is mounted on a workpiece holder of the apparatus and correctly indexed to the machine. The MRF machine then removes material as instructed by the control system to leave a residual layer having a very high degree of thickness uniformity at a nominal average thickness and having a very high level of surface integrity.
The invention is useful in providing thin films of materials including, but not limited to, ceramics, glass, metals, transition metal oxides, magnetoresistive alloys, aluminum oxide, nitrides, carbides, gallium arsenide, tungsten, silicon, and sapphire.

Uniform thin films produced by magnetorheological finishing


A method and a device for shutting down a drive during a power outage are disclosed. The method and device include a matrix converter, several commutation capacitors on the power line side, a switch unit on the power line side and a resistor unit. During a power outage, the matrix converter is immediately disconnected from the power supply, and the resistor unit is connected to the input terminals of the matrix converter in such a way that the amplitude of a voltage applied to the resistor unit equals the amplitude of an actual capacitor voltage space vector, and the speed setpoint is set to zero. This enables a drive with a matrix converter to be shut down during a power outage by way of a pulsed resistor.

The present invention relates to a method for shutting down a drive connected to a matrix converter during a power outage and a device for carrying out the method.
It is desirable in many drive applications, such as lifting devices, to shut down the drive(s) during a power outage in an orderly and reliable manner. With drives having a voltage intermediate circuit converter, it is sufficient to install in the voltage intermediate circuit a suitably sized pulsed resistor which is connected electrically in parallel with the intermediate circuit capacitor. This pulsed resistor includes a series connection of a turn-off semiconductor switch and a resistor. Depending on the braking power of the motor, the average voltage of the resistor is regulated by controllably pulsing the turn-off semiconductor switch so that the power dissipated in the resistor corresponds to the instantaneous braking power of the motor.
Other converter topologies exist beside the "voltage intermediate circuit" converter topology, for example, the "matrix converter" converter topology. A matrix converter of this type is connected to the power line via an optional power line or electromagnetic compatibility filter. This power line filter is implemented, for example, by employing line chokes and commutation capacitors connected to the input terminals of the matrix converter. The commutation capacitors which can be connected in a Delta or Star configuration, are essential for the operation of the matrix converter. However, the chokes in the power lines may optionally be omitted.
Since the matrix converter does not include a voltage intermediate circuit, a conventional pulsed resistor can no longer be used for shutting down a drive when employing a matrix converter. Since certain drive applications require a safe shutdown, matrix converters cannot be used with these drive applications for powering the motors. Accordingly, these particular drive applications cannot employ the converter topology "matrix converter."
It would therefore be desirable and advantageous to provide an improved device for shutting down a drive during a power outage, which obviates prior art shortcomings and is able to specifically operate with a conventional matrix converter.

Method and device for shutting down a drive with a matrix converter during a power outage


Improved grease compositions comprise a major amount of an oil based metal soap thickened base grease selected from the group consisting of complex and failed complex greases, at least one sulfur and phosphorus containing composition alone or together with an overbased metal salt of an organic acid and a hydrocarbyl phosphite, in amounts sufficient to increase the dropping point of the base grease, as measured by ASTM Procedure D-2265 by at least 15.degree. C., the phosphorus and sulfur compound being described in detail herein.

Man's need to reduce friction dates back to ancient times. As far back as 1400 B.C., both mutton fat and beef fat (tallow) were used in attempting to reduce axle friction in chariots.
Until the mid-1800's, lubricants continued to be primarily mutton and beef fats, with certain types of vegetable oils playing minor roles. In 1859, however, Colonel Drake drilled his first oil well. Since that time most lubricants, including greases, have been based on petroleum ("mineral") oil, although synthetic oil based lubricants are used for special applications.
In the NLGI Lubricating Grease Guide, C 1987, available from the National Lubricating Grease Institute, Kansas City, Mo., USA, is a detailed discussion of greases, including various types of thickeners. Such thickeners include simple metal soap, complex metal salt-metal soap and non-soap thickened greases.
Simple metal soap thickened greases have provided exemplary performance. However, under certain conditions an increased dropping point as measured by ASTM Procedure D-2265 is required.
One way to increase the dropping point of base greases is to convert a simple metal soap grease to a complex grease by incorporating therein certain acids, typically carboxylic acids such as acetic acid, alpha-omega-dicarboxylic acids and certain aromatic acids. This process necessarily consumes considerable time resulting in reduced production. Nevertheless, complex greases provide highly desirable properties and are widely used. Oftentimes complexing does not take place and the grease retains substantially the properties of the corresponding simple soap grease. Such greases are referred to herein as failed complex greases. Reasons for failure to achieve complex formation are not well understood.
Doner et al, in a series of U.S. Patents, specifically, U.S. Pat. Nos.
______________________________________ 5,084,194 5,068,045 4,961,868 4,828,734 4,828,732 4,781,850 4,780,227 4,743,386 4,655,948 4,600,517 4,582,617 ______________________________________
teaches increased thickening of metal salt thickened base greases is obtained employing a wide variety of boron-containing compounds. Other additives contemplated for use with boron-containing compounds are phosphorus- and sulfur-containing materials, particularly zinc dithiophosphates.
Reaction products of O,O-dihydrocarbyl-phosphorodithioic acids with epoxides are described by Asseff in U.S. Pat. No. 3,341,633. These products are described as gear lubricant additives and as intermediates for preparing lubricant additives.
U.S. Pat. No. 3,197,405 (LeSuer) describes phosphorus and nitrogen containing compositions prepared by forming an acidic intermediate by the reaction of a hydroxy substituted triester of a phosphorothioic acid with an inorganic phosphorus reagent and neutralizing a substantial portion of said acidic intermediate with an amine. These compositions are described as lubricant additives.
U.S. Pat. No. 4,410,435 (Naka et al) teaches a lithium complex grease containing a base oil, a fatty acid having 12-24 carbon atoms, a dicarboxylic acid having 4-12 carbon atoms and/or a dicarboxylic acid ester and lithium hydroxide thickened with a phosphate ester and/or a phosphite ester.
The aforementioned copending applications relate to improved grease compositions comprising a major amount of an oil-based simple metal soap thickened base grease and minor amounts of additives to increase the dropping point of the base grease. The additives comprise a phosphorus and sulfur containing composition, alone, or together with an overbased metal salt of an organic acid and a hydrocarbyl phosphite, said phosphorus and sulfur containing composition selected from the group described in greater detail hereinbelow.


An apparatus and system are provided for delivering communication services such as video, data and telephony services to individual residential units.

1. Field
The systems and methods described in this patent document relate generally to optical networks and more specifically to fiber to the home optical systems.
2. Description of the Related Art
Optical networks can be used to deliver communication services to businesses and homes. Optical networks have the capability of delivering a variety of services such as video, data, and telephony services. The optical network devices that are presently considered for providing residential services typically are devices such as optical network units that are designed to provide services to multiple residential units and are not appropriate for use with a single residential unit.

Abstract: According to one embodiment, an optical network terminal (ONT) for providing communication services to a single residential unit comprises a passive optical network interface (PI) circuit, a residential service interface (RSI) circuit, and a power unit. The PI circuit receives optical signals from an optical fiber and transmits optical signals onto the optical fiber. The PI circuit is adapted to convert received optical signals containing voice information to electrical voice ATM cells, received optical signals containing data information to electrical data ATM cells, and received optical signals containing video signals to electrical video signals. The PI circuit is also adapted to convert electrical voice ATM cells and electrical data ATM cells to optical signals for transmission over the optical fiber;

Abstract: The RSI circuit that is adapted to convert the electrical voice ATM cells to a telephony format suitable for use at the residential unit and the electrical data ATM cells to a network format suitable for use at the residential unit. The RSI circuit is also adapted to convert telephony format information received from the residential unit to voice ATM cells and network format information received from the residential unit to data ATM cells.

Abstract: The power unit provides power for use in the PI circuit and the RSI circuit. The power unit includes an AC/DC converter for converting ac power received from the residential unit to dc power for use in the ONT and backup batteries for providing power when there is an interruption of the ac power.


Embodiments of the invention are directed to systems, methods, and computer program products for an electronic system for management of image processing model database. The system is configured for versioning machine-learning neural-network based image processing models and identifying and tracking mutations in hyper parameters amongst versions of image processing models. The system is configured to determine that a second image processing model is a version of a first image processing model. The system is further configured to map the mutations in hyper parameters between the first plurality of hyper parameters of the first image processing model and the second plurality of hyper parameters associated with the second image processing model.

Increasingly prevalent computers, mobile phones, smart devices, appliances, and other devices, require a variety of complex functions involving image processing, identification, pattern recognition, 3D image reconstruction, visualization, modelling, etc. However, these complex functions require complex processing capabilities that are not met by conventional systems. Machine learning or deep learning models are required for these tasks. There is a need for improved machine-learning neural-network based models that have the ability to learn and model non-linear and complex relationships, generalize and infer unseen relationships, and have the ability to handle a variety of inputs, thereby overcoming the deficiencies of conventional systems. The present invention provides solutions to various problems prevalent in neural-network based machine-learning technology.
The previous discussion of the background to the invention is provided for illustrative purposes only and is not an acknowledgement or admission that any of the material referred to is or was part of the common general knowledge as at the priority date of the application.

Electronic system for management of image processing models


In a Micro Electro-Mechanical System (MEMS) switch, a common switch failure is a short between the upper and the lower electrostatic actuation plates. Such shorts may occur due to torque deformation. Stopper bumps having a slightly lower height profile than that of the contact bumps are provided to prevent such shorts. The stopper bumps may be made using the same mask as that used to create the contact bump with the height of the respective bumps controlled by determining the diameter of the bumps.

There are many applications which require fast switching speeds. For example, for multi-mode multi-band cell phone applications such as GSM (Global System for Mobile Communications), GPRS (General Packet Radio Service), and 3G (Third Generation Wireless), the antenna switch unit switches the antenna to different bands as well as between transmission (TX) and receiving (RX) modes. Currently, solid-state switches are used for this purpose. While RF (Radio Frequency) MEMS metal contact series switches generally have much better insertion loss and isolation characteristics, they are much slower than solid-state switches.
Referring to FIGS. 1 and 2, these figures illustrate a top view and a side view of a MEMS in-line cantilever beam metal contact series switch, respectively. This type of MEMs switch can be manufactured by well known MEMS fabrication processes.
As shown, the switch is formed on a substrate 100 having an isolation layer 101. A metalized signal line 102 may be formed on one side of the substrate 100 and a second signal line 104 may be formed on the second side of the substrate 100 over the isolation layer 101. A cantilevered beam 106 may be secured to the second signal line 104 with an anchor 103. A bump (electrode) 108 may be formed for example by a field oxide (FOX) technique under the first signal line 102. A lower electrostatic actuation plate 110 may be formed on the substrate 100 beneath an upper electrostatic actuation plate 111 formed in the cantilevered beam 106. When the actuation plate 110 is energized, by applying a voltage, the upper actuation plate 111, and thus the cantilevered beam 106, is pulled downward causing the bump 108 with the first signal line 102 to make contact with the cantilevered beam 106. This closes the switch and provides an electrical signal path between the first signal line 102 and the second signal line 104.
Referring to FIG. 3, the most common switch failure is a short between the upper 111 and the lower electrostatic plates 110. Such shorts can occur due to deformation of the upper beam 106. The most common deformation is typically due to torque that creates short between the corner of the upper electrode 111 and the lower electrode 110. As shown in FIG. 3, the corner of the upper electrode exhibits signs of torque related shorts 120.

MEMS switch stopper bumps with adjustable height


An apparatus provided for releasing the dogging function of a panic device for an exit door without the use of a key or other external device includes an end cap button; an adjustable connecting rod assembly; and a modified latch plate; Depressing the end cap button pushes the rod assembly to rotate the modified latch plate to release the dogging function of the panic device.

The present disclosure relates to the field of door security systems and more specifically to a mechanism operable with the existing panic device to release the dogging mechanism without the use of an external key or similar external device.
Door exit devices, also referred to as panic exits or fire exits, are typically operated from the inside of an outward swinging door and are designed to provide building occupants fast and easy egress in an emergency. A door exit device generally comprises a manually actuated latch release mechanism releasing a door latch responsive to a relatively minimal force applied in the direction of egress travel through the doorway. The manually actuated release mechanism includes a readily accessible push pad or crossbar rail extending at least halfway across the width of the door.
With safety of building occupants as its primary function, a door exit device must always release the door latch, allowing exit without special access authorization or significant door operation knowledge. Any minimally sufficient horizontal push force applied to the outer vertical surface of a push pad type exit device retracts the latch bolt and releases the door to be opened. Several exit device designs have been designed and utilized including rim type, vertical rod, and mortise lock type devices. Examples of such devices are disclosed in U.S. Pat. No. 4,466,643, to Godec at al.; U.S. Pat. No. 5,016,927 to Toledo; U.S. Pat. No. 5,184,852 to O'Brien; and U.S. Pat. No. 5,927,765 to Austin et al.
Many of these panic devices have a dogging function which allows the panic device to be intentionally placed into an unlocked and unsecure position. This is achieved by means of a cylinder or hex key latching of the panic device when in the depressed push pad state. One example of such a device is shown in U.S. Pat. No. 4,968,070 to Choi. Currently the functionality will only allow the panic device hardware to be locked/unlocked by means of this hex key or cylinder key.
There is a need for an apparatus that will allow the locking of the panic device hardware in a quick manner without the need of a hex key or cylinder key. One benefit of this added functionality is that any individual can lock the panic device door without the need for a hex key or cylinder key. This feature would provide an added security to the door if a need arises requiring the immediate securing of the door. Currently only building owners with the hex key or cylinder key can lock the panic device door if the panic device is in the dogged down (always unlocked) position.
There remains a need for an exit device apparatus, system and method that efficiently and quickly releases the dogging function of the panic device. The present invention addresses such a need and other needs not addressed by the prior art.