Family of methods for correcting errors in transfer of information over a lossy medium. The message to be sent is first broken into Data Blocks, which are further divided into N data segments. These data segments are sent verbatim and followed by XOR combinations of the data segments, called Error Correcting Segments. Incorrect Data or Error Correcting Segments are detected through the use of a CRC or any other error detection algorithm, and errored Data or Error Correcting Segments are discarded. Once all Data or Error Correcting Segments for a message segment are received, logic or a look up table is used to determine which of the Data Segments can be recovered. The lost Data Segment recovery is done using a binary XOR of multiple good Data or Error Correcting Segments. For additional error correction, Data and Error Correcting Segments can also be repeatedly transmitted multiple times to further improve the performance of this algorithm.

The present invention relates to an error correction method for a lossy communications environment. It may readily be applied to a high traffic or high loss multipoint system. The present invention may be used in any digital communications system, including such applications as satellite communications systems, terrestrial radio systems, and cellular phone systems. The present invention is useable for Internet and Intranet broadcasting.
Communications systems need to reliably transmit information to all users within that system. To accomplish this, data is often broken into smaller pieces called packets which can be easily managed by the communications system. Communications systems invariably suffer from corrupted bits and lost packets, resulting from a multitude of causes, including, but not limited to interference, noise, and buffer overflows.
To recover corrupted bits and lost packets, many error correcting techniques may be applied. The most common is called a Forward Error Correcting Code (FEC) which may correct single or multiple errors in a packet. An FEC works by adding error correcting bits to the transmitted packet. Unfortunately, if too many errors occur in a packet, the corrupted packet will remain corrupted or be lost, even with the use of an FEC code. Because of this, errors resulting from interference and buffer overflows are generally not correctable with an FEC code. Another disadvantage is that there is a necessary bandwidth overhead in sending the parity bits required by an FEC code.
To detect the occurrence of corrupted packets, existing systems can use an error detection algorithm. Commonly used error detection algorithms include the Cyclic Redundancy Checking (CRC) algorithm and checksum algorithm, which can detect the occurrence of multiple errors. A technique of adding parity bits can be used to detect single and odd numbers of errors.
The absence of a packet that is expected, usually resulting from strong interference or buffer overflows, can be detected by the addition of sequence information to the packet.
One method to greatly improve the probability of receiving an uncorrupted packet is to send the packet multiple times. In this case, any number of errors in a single packet, or even a lost packet, will not prohibit uncorrupted reception of the packet""s information, as long as at least one packet is correctly received. Unfortunately, sending each packet R times requires R times as much bandwidth.
Another method to greatly reduce the probability of losing information is to request and retransmit a packet in the event that a packet is lost or corrupted. This method is often referred to as ARQ (automatic repeat request). To accomplish this, acknowledgments (ACKs), negative acknowledgments (NACKs), and timeout windows may be employed to identify which packets are incorrectly received or may need to be resent. These identified packets may be retransmitted as many times as necessary until the information is indicated to be successfully received. Two serious drawbacks of this method are that latency and bandwidth are increased with each retransmission. Also, the ACK and NACK messages themselves require additional bandwidth. The increased and non-deterministic latency of this protocol is not well suited to many types of traffic such as satellite communications systems. Also, the additional bandwidth required for the ACK and NACK messages make this method very poorly suited to communications systems that support broadcast of information to many or all users, as the bandwidth of the ACK and NACK messages increases with each user in the system. Broadcast of information is the transmission of identical information to multiple or all users in a communications system.
Each of these methods of packet recovery have some advantages over the others. However, the method of present invention has the advantage that information can be sent with a higher reliability, using the same amount of bandwidth, than the prior art method of repeating each packet multiple times.
The prior art methods have not been optimally effective in correcting errors in the transfer of information over some lossy mediums such as radio links, copper wires, or fiber optic cables, where the channel is randomly blocked due to interference or jamming.
The present invention relates to a method for correcting errors in the transfer of information over a lossy medium such as radio frequencies, copper wires, or fiber optic cables, where the channel is randomly blocked due to interference or jamming. However, it is not limited to lossy mediums, but may also be used in non-lossy mediums. The message is first divided into data blocks. The data blocks are then divided into data segments. The data segments of each data block are used to generate distinct combinations of data segments through a Boolean operation (such as XOR) or an arithmetic operation to form Error Correcting Segments. The Data Segments and Error Correcting Segments are transmitted. In the event that a Data Segment of the information is incorrectly received, the message can be entirely reconstructed as long as one valid subset of Data Segments is correctly received. In the case where a data block is divided into two Data Segments, three Data and Error Correcting Segments are transmitted. The retrieval of any two Data and Error Correcting Segments provides enough information to retrieve the full amount of information transmitted in the corresponding data block. In the case where a data block is divided into three data segments, seven Data and Error Correcting Segments are transmitted. The retrieval of any four good Data or Error Correcting Segments results in full retrieval of transmitted information. Furthermore, in the case where only three good Data Segment or Error Correcting Segments are received, there are only four out of the thirty five possible sets of three Data and Error Correcting Segments which will not lead to the retrieval of the complete message.
In the simplest case, after a message is divided into Data Blocks, each Data Block is further subdivided into two Data Segments A and B in which there is only one distinct combination of these Data Segments (for example, A⊕B, i.e., A XOR B). There is no acknowledge signal which is sent from the receiver to the transmitter. This reduces overhead and latency since no ACK or NACK messages need to be sent or awaited. The entire Data Block (i.e., both [A] and [B]) can be recovered if any of the following three Data or Error Correcting Segments are received: (1) [A],[B]; (2) [A],[A⊕B]; or (3) [B],[A⊕B].
The method provides significantly better performance for a fixed amount of overhead relative to simple repetition or repeat schemes. This method is particularly suitable for broadcast mediums and high latency applications such as satellite communications for which an ARQ scheme is not acceptable or practical. Lastly, this method will outperform a standard FEC code in a jamming type environment where errors are in the form of large bursts, such as frequency hopping radio that has strong interference on a percentage of frequencies. Further applications include Internet or Intranet broadcasting and may be used in any network architecture.
The present invention relates to an error correcting method for a multipoint communications system, comprising partitioning a message into Data Blocks in which each of the Data Blocks are further divided into N data segments, representing one or more bits. At least one distinct combination of N data segments is computed using a Boolean or arithmetic operator such as XOR to form Error Correcting Segments where N is equal to 2, 3, or a larger natural number. In the present invention, steps, in addition to receiving the Data or Error Correcting Segments, such as correcting bit errors and performing operations on the Data or Error Correcting Segments which have been received correctly are employed to recover as much of the data block information as possible.
In a variation of the error correcting method of the present invention, each of the Data or Error Correcting Segments is transmitted two or more times. This reduces the error rate at the expense of additional overhead.
The present invention is directed for use in any lossy environment, but is particularly useful in broadcast data systems such as communications systems exposed to intentional or unintentional jamming and satellite systems.

Method for correcting errors in transfer of information


Exemplary embodiments provide a method for connection or application of a converter to a rotating asynchronous machine which is operated without an encoder, without a high current and without a torque surge. The method provides a control unit, using an inverter or converter, for feeding the asynchronous machine which rotates at a mechanical rotary speed. The asynchronous machine is regulated by the control unit. A stator current vector is ascertained from measured currents of the stator windings of the asynchronous machine and a rotating stator voltage vector. Calculation is effected in respect of a stator flux change vector from the stator current vector, the stator voltage vector and a stator resistance in accordance with a motor model. An angle difference between the stator current vector and the stator flux change vector is calculated. That angle difference is regulated to a reference value of 90° or −90°, wherein an output signal of the regulator corresponds to a rotary field frequency, to be impressed, of the voltage vector of the stator. Regulation is effected in respect of an amplitude of the stator voltage vector by way of a current regulator to which the difference of a current reference value and a parameter corresponding to the amplitude of the stator current is made available at the input as a regulating difference.

The control unit connects to and synchronises with the rotating or stationary asynchronous machine (ASM or DAM).
The procedure of identification of the mechanical rotary speed or the synchronous rotary field frequency in an asynchronous machine operated without an encoder is referred to in the literature as the 'capture mode'. An associated circuit which permits such connection while avoiding current and torque peaks bears the technical name 'capture circuit'.
The capture circuit is used in applications in which, for example, due to major mass moments of inertia of the drive, it is not possible to exclude the converter being connected to a drive which is still spinning. Further fields of use are found in the area of fan technology where at the time of connection the current rotary speed of the drive is not known and also cannot be measured for economic reasons.
Connecting a converter to a rotating asynchronous machine results in a high current and a torque surge which should be avoided, in dependence on residual remanence, slip and impressed voltage.
Methods of starting asynchronous machines in a situation with a stationary or rotating is rotor are known from various patent literature. For example, DE 38 20 125 C2 presents such a method. The method presented is for starting an inverter-fed encoder-less asynchronous motor which permits capture of a rotating drive without a residual flux being present in the machine. The method is based on an equivalent-circuit diagram, held in rotor field co-ordinates, of the ASM, in which the slip frequency is reconstructed from a measurement of the terminal current. The synchronous rotary frequency for the control voltage is ascertained from the calculated or estimated slip frequency and the impressed stator frequency. The change in time of the torque-forming current component is in that case added as a dynamic correction value to the motor frequency. The method converges in the synchronous rotary frequency of the drive and in that way permits identification of the synchronous speed.
DE 195 32 477 A1 describes a method for starting an encoder-less asynchronous machine which functions both with and also without a residual flux in the ASM uses zeroing of the torque formed. In that method the stator current vector is measured and a stator flux vector generated by the voltage is estimated or determined. From those values the moment caused at the motor is calculated and regulated to zero by means of a regulator. The system experiences excitation by a current pulse, from which it follows that upon possible rotation of the machine a torque is formed, which can be regulated as desired by the regulating system.
An essential feature of the last two methods mentioned is that a torque which is regulated to zero with a regulating system is calculated from the impressed voltage and the measured current. As a departure from that approach, DE 195 03 658 A1 presents a method which uses the residual remanence of the rotor flux and the voltage induced in the stator winding. When no residual rotor flux is present the method can also be used by excitation being effected with a voltage pulse.
An estimated value for the mechanical rotary field frequency of the rotor is derived from the rotary field frequency of the induced voltage vector which is ascertained by way of differentiation of the angle of the voltage vector measured at different times.
EP 469 177 A1 describes a method which also determines the rotary speed of an asynchronous motor, utilising the remanence effect. Evaluation of the terminal voltage induced by the remanence of the rotor has to be effected in that case by an additional circuit arrangement for voltage measurement as during the measurement operation no voltage is impressed by the converter and the final stage is blocked.
The method of DE 35 43 941 A1 uses the residual remanence of the system in a similar way. On the basis of the measured induced voltage, a rectangular signal of the same phase and frequency is generated, which is used for identification of the mechanical rotary speed or the synchronous rotary field frequency.
DE 35 43 983 A1 presents a method which is suitable for connecting a converter to a non-excited rotary machine which is still rotating. That method involves a search method which involves passing through the rotary frequency range with a constant reference current IS. On the basis of the change in the voltage to be impressed for that purpose (dU/dt) the search speed is adapted and reduced for major voltage changes. The mechanical rotary speed is detected on the basis of the increase in the flux in the region of the synchronous operating point. A disadvantage with that search method is the time required for identification of the mechanical rotary speed and the impressed torque which occurs because of the magnetisation effect.
DE 199 19 752 C1 describes a method which unlike the foregoing methods dispenses with calculation of the torque, the rotor flux or the moment or magnetisation current. In addition that method does not require any rotor residual remanence. In this method the reference value for the stator current vector is determined directly from the stator flux vector, wherein the direction of the current vector is selected substantially parallel to the direction of the flux vector. The method permits the use of the current regulator structures which exist in many cases (field-oriented regulation) and can be incorporated at minimum complication and expenditure. It only presupposes an expansion for calculation of the stator flux vector, which is determined by means of the impressed voltage and the measured current.

Applying a control unit to an asynchronous machine which is operated without a rotary encoder


An apparatus for manufacturing an absorbent article includes an arm member having a tip end portion feeding the elastic member. The tip end portion moves alternately in a first direction and a second direction, so that the elastic member is brought into contact with a web being conveyed in a predetermined direction with a continuum of components constituting one portion of the absorbent article and is placed in a predetermined waveform. Here, in a plan view of the web, a distance between the arm member and a nip point becomes largest when the nip point goes beyond a position on the predetermined waveform where an angle between the predetermined direction and a tangent line to the predetermined waveform becomes largest.

In the conventional process of manufacturing absorbent articles, such as disposable diapers, widely used is a method in which string-like elastic members (rubber) are arranged in portions to be processed into leg-surrounding regions and a crotch region which constitute an absorbent article so that the leg-surrounding regions and the crotch region should be more fitted to a person to wear the absorbent article (for example, a human body).
Specifically, in the manufacturing process, the string-like elastic members are placed in waveforms on a web with continua of components such as a back sheet and an absorption sheet to form absorbent articles. In other words, the string-like elastic members are placed in waveforms on the web conveyed by a crosswise conveyor system in which absorbent articles to be formed are arranged with a longitudinal direction of each of the absorbent articles going in a cross direction (a CD direction) which intersects a conveyance direction (an MD direction) of the web. In this way, the absorbent article having gathers to be fitted to the shapes of the leg-surrounding regions and the crotch region can be continuously formed.
As described above, as a method for placing string-like elastic members in waveforms on a web being conveyed, there is known a method in which a guide member guiding feeding positions of elastic members onto a web is driven by a cam (see Patent Literature 1, for example).
There is also known a method in which a guide member guiding feeding positions of elastic members onto a web is reciprocally moved in a cross direction intersecting a conveyance direction of the web (see Patent Literature 2, for example).
It is not realistic in terms of the layout of an apparatus to bring a guide member into contact with a nip point to align the nip point with the feeding position of a elastic member guided by the guide member. Here, the nip point is that at which an elastic member and a web are held between press rollers provided above and below the web and thereby come in contact with each other. For this reason, a certain distance is generally provided between the nip point and the feeding position. In other words, the distance has to be considered when the profile of a device moving the guide member is designed.
The inventors have discovered that, in the known technique, the aforementioned conventional apparatus for manufacturing an absorbent article has the following problem.
Specifically, to place an elastic member accurately in a desired position on a web being conveyed at high speed, the profile of a device such as a cam has to be elaborately designed in consideration of a distance between a nip point and a feeding position.
The present invention has been made in view of the foregoing circumstances. Accordingly, an object of the present invention is to provide an apparatus and a method of manufacturing an absorbent article that are capable of placing a elastic member in a desired position on a web being conveyed at high speed without elaborate profile designing.

Apparatus for manufacturing absorbent article


The present disclosure relates to a high temperature resistance temperature detector for measuring exhaust gas temperature for example. The structure includes a resistive element disposed on an insulated carrier. The structure further includes a housing disposed over the carrier and resistive element for inhibiting oxidation of the element which would result in failure of the detector.

Present embodiments relate generally to gas turbine engines. More particularly, but not by way of limitation, present embodiments relate to resistive temperature detectors for exhaust gas temperature measurement in a gas turbine engine.
In turbine engines, air is pressurized in a compressor and mixed with fuel in a combustor for generating hot combustion gas which flow downstream through turbine stages. These turbine stages extract energy from the combustion gas. A high pressure turbine includes a first stage nozzle and a rotor assembly including a disk and a plurality of turbine blades. The turbine engine may include a number of stages of static airfoils, commonly referred to as vanes, interspaced in the engine axial direction between rotating airfoils commonly referred to as blades. The high pressure turbine first receives the hot combustion gas from the combustor and includes a first stage stator nozzle that directs the combustion gas downstream through a row of high pressure turbine rotor blades extending radially outwardly from a first rotor disk. In a two stage turbine for example, a second stage stator nozzle is positioned downstream of the first stage blades followed in turn by a row of second stage turbine blades extending radially outwardly from a second rotor disk. The stator nozzles direct the hot combustion gas in a manner to maximize extraction at the adjacent downstream turbine blades.
The first and second rotor disks are joined to the high pressure compressor by a corresponding rotor shaft for powering the compressor during operation. A multi-stage low pressure turbine follows the two stage high pressure turbine and is typically joined by a second shaft to a fan or low pressure compressor disposed upstream from the high pressure compressor in a typical turbofan aircraft engine configuration for powering an aircraft in flight.
As the combustion gas flows downstream through the turbine stages, energy is extracted therefrom and the pressure of the combustion gas is reduced. The combustion gas is used to power the compressors as well as a turbine output shaft for power and marine use or provide thrust in aviation usage. In this way, fuel energy is converted to mechanical energy of the rotating shaft to power the compressor and supply compressed air needed to continue the process.
During the operation of the gas turbine engine, it is necessary to obtain temperature readings at different locations in the engine. This data is utilized by the engine control logic to properly operate the engine and provide maximum performance at the highest efficiency. One such temperature probe which is utilized at the exhaust area of the combustor, it is known as an Exhaust Gas Temperature probe or EGT probe or sensor. These probes utilize type-K thermocouples typically having dissimilar metals to create a differential which may be then input to the engine control logic to optimize performance.
Resistance temperature detectors (RTD) are also utilized in probe assemblies to measure operating temperatures. RTDs utilize variable resistant material at a position where a temperature is to be measured with leads connected to an instrument which measures an amount of varying voltage when power is supplied to a sensor. Since resistance changes with temperature, the temperature may be determined by applying a constant current to the resistor and measuring the voltage drop to determine the resistance and resultant temperature.
Various metals may be used which provide differing resistances upon exposure to heat. One problem with use at high operating temperatures is that materials suffer from oxidation, ionic migration wire alpha shifts and weakened strength. This can result in decreased life as well as temperature measurement drift. For operation in high temperature environments, typically at or above 1832 degrees Fahrenheit, operating conditions are limited to specialized RTD constructions using platinum, wire wound or thin film constructions. However, even these constructions are still limited generally for short durations of temperature exposure above 1832 degrees Fahrenheit which severely limits applicability in various industries.
Current designs cannot withstand temperatures at the combustor exit or high pressure turbine entrance for extended periods of time. Accordingly, temperatures must be taken near the low pressure turbine and extrapolated to a position at the combustor exit. This however can lead to error. Additional problems occur such as decreases in engine management efficiency due to the extrapolation, as opposed to obtaining an actual reading. Moreover, time delays in optimization of engine conditions may further result in less than maximum engine performance when engine operating conditions change, for example ambient air temperature changes. For these reasons, a compromise is struck between positioning too close to the combustor, which may result in early failure of the detector, and placing further from the combustor which may result in less accurate temperature readings at the combustor exit.
As may be seen from the foregoing, there is a need to optimize the engine management by providing a temperature reading closer to the combustor. There is a further need to optimize temperature detectors so that the temperature detector can withstand temperatures typically occurring at the combustor and high pressure turbine and inhibiting degradation, drift and failure at high temperatures for extended periods of time.

High temperature resistive temperature detector for exhaust gas temperature measurement


A technique is provided for measuring an object based on multiple views. The technique includes registering each of the plurality of images and a first model of the object with one another and reconstructing a second model of the object based on the plurality of images and the first model registered with one another.

The invention relates generally to the field of industrial metrology and, in particular, to model-based measurement techniques using multiple views.
Measurement of objects is of vital importance in manufacturing and repair industries. Various types of measurement systems, such as computed tomography (CT), coordinate measuring machines (CMM), laser-based profilometry, and infrared, are used for industrial inspection. For example, these measurement systems may be used for measuring dimensions or for identifying defects in manufactured parts, such as tubes. Unfortunately, many of these measurement systems are costly, slow to produce, bulky, application specific, and require high maintenance. For example, different gauges are often required for different tubes. Also, in many applications the tubes considered are smooth surfaces without texture or fiducial markings, and therefore current techniques that rely on point correspondences cannot be employed, as the accuracy level is lower than acceptable. As the manufacturing tolerances become tighter, there is a corresponding increase in the demands for metrology techniques for maintaining the tolerances. The need for quality and performance testing has become an integral part of the production or manufacturing process.
Accordingly, a need exists for a measurement technique that is relatively inexpensive, versatile and programmable for different applications and that requires low maintenance.

System and method for object measurement


The multimedia processing system includes a plurality of first units including a CPU and a top domain; a storage domain configured to store a plurality of multimedia data; a multimedia codec domain configured to decode segments of target multimedia data received from the storage domain and to output decoded segments according to control of the CPU or the top domain; a system bus configured to connect the plurality of first units, the storage domain, and the multimedia codec domain with one another; and an alive domain configured to control power supply to the plurality of first units, the storage domain, the multimedia codec domain, and the system bus and to receive a signal from a user.

1. Field
Embodiments of the inventive concepts relate to a multimedia processing system and a method of operating the same, and more particularly, to a multimedia processing system for processing a multimedia file in an electronic apparatus and a method of operating the same.
2. Related Art
Multimedia data is compressed by an encoding device and is then transmitted to a decoding device or stored in a storage device together with a spatial information signal. A system, which effectively recovers compressed audio data such as MP3, AAC, and WMA in multimedia data and compressed video data such as MPEG in the multimedia data into an analog format and a digital pulse code modulation format, consumes a lot of processing power to recover the compressed multimedia data. The processing power is an important issue since it affects battery consumption in portable devices.

Multimedia processing system and method of operating the same


Epoxy resin compositions having improved storage stability before curing and improved thermal and mechanical performance after curing comprise a mixture of a polyepoxide and a curing agent that is reactive with the polyepoxide. The epoxy resin composition is characterized by a glass transition temperature of less than 20.degree. C., measured under standard conditions, after subjecting the epoxy resin composition to a specified thermal cycle. The preferred curing agents are aromatic diamines, for example, 3,7-diaminodibenzothiophene-5,5-dioxide; 3,7-diaminophenothiazine sulfone, 3,7-diamino-N-methylphenothiazine sulfone; 2,7-diamino-9-fluorenone and 2,4,6,8-tetramethyl-3,7-diaminothioxanthene sulfone.

Epoxy resins currently used in the manufacture of high performance composites all tend to suffer from loss of tack, drape, and usability under conditions of ambient handling and storage due to chemical advancement, i.e., partial curing, of the resin. These epoxy compositions typically consist of a poly-O-glycidyl ether and/or poly-N-glycidyl amine, and an aromatic amine curing agent such as 3,3'-diaminodiphenyl sulfone, 4,4'-diaminodiphenyl sulfone or fluorenedianiline, and various other additives. These compositions are typically used in a hot melt process to form a prepreg. Hot melt processing may involve mixing, filming and prepregging at temperatures between 80.degree. C. and 130.degree. C. After hot melt processing these standard curing agents can react with the polyepoxide component even at low temperatures, especially in the presence of moisture. These reactions lead to limited out-time under conditions of ambient storage.
Out-time, which is a function of temperature and environment, is important in the construction of large and/or intricate parts where lay-up procedures can often exceed one month. For example, humidity is known to catalyze reactions in epoxy resin compositions at low temperatures. Systems that do not advance during the manufacture of parts provide better control of resin flow and therefore produce more homogeneous composites with better mechanical performance. Resistance to advancement also provides better product quality control.
Out-time is defined as the period over which tack, drape and usability are preserved by the resin composition (and products containing the resin composition such as prepreg) under defined environmental conditions. Tack is a subjective estimate of the ability of two resin-containing structures (such as prepreg) to stick together so that alignment is not easily disturbed. Should realignment be necessary, however, no damage is suffered to the objects upon removal and realignment. An example of such an alignment process is found in the lay-up procedure for carbon fiber-reinforced composite structures. Drape is the ability of a resin-containing structure (such as prepreg) to be bent and shaped without fracture or rebound of the uncured resin. Maintenance of tack and drape requires that resin advancement be kept to a minimum so that the glass transition of the resin does not exceed a critical level, which is typically about 20.degree. C. "Usability" indicates that cured resin and composite properties are not deleteriously affected by conditions encountered prior to cure.
Epoxy resin compositions in which an aromatic amine curing agent becomes dissolved during mixing, filming and prepreg manufacture are described, for example, in U.S. Pat. No. 4,940,740. The preferred curing agents are 2,4'-, 4,4'- and 3,3'-diaminodiphenylmethane, 2,4'-, 4,4',- and 3,3'-diaminodiphenyl sulfone, 2,2-bis(4-aminophenyl)propane and 2,2-bis(3-aminophenyl)propane. U.S. Pat. Nos. 4,330,659 and 4,500,582 disclose the use of the reaction product of diaminodiphenyl sulfone compounds and glycidyl ethers of polyhydric phenols as a hardener for epoxy resins. Storage stability of these resin compositions is poor under ambient, humid conditions. Resin compositions described as having improved storage stability are disclosed in U.S. Pat. No. 4,933,392, where compositions containing dicyandiamide (DICY) or polycarboxylic acid hydrazide are reported to be stable at 40.degree. C. for up to 45 weeks. However, these curatives do not provide the thermal and mechanical properties attainable with aromatic amine curing agents, and at levels .ltoreq.10 parts DICY per hundred parts polyepoxide tend to cause resin advancement problems during hot melt processing.
Aromatic diamines such as those disclosed in the present invention have been disclosed previously, although not their use as curing agents for epoxy resins. For example, U.S. Pat. No. 2,684,372 discloses the preparation of 2,7-diaminothioxanthone dioxide. JP 62-028792 discloses the preparation of 3,7-diaminodibenzothiophene-5,5-dioxide, which is said to be useful in preparing aromatic polyamides.

Epoxy resin compositions with improved storage stability


A method for forming a polarization inversion portion, in which electrodes with a predetermined pattern are formed on one surface of a ferroelectric crystal that has been subjected to a single polarization, and a local polarization inversion portion corresponding to the pattern of the electrodes is formed in the ferroelectric crystal by applying electric field to both front and back surfaces of the ferroelectric crystal via the electrodes, makes it possible to accurately form a polarization inversion pattern. In this method, portions of the ferroelectric crystal corresponding to the respective electrodes and portions between these portions are subjected to a polarization inversion, and one polarization inversion portion is formed.

1. Field of the Invention
The present invention relates to a method of forming a polarization inversion portion by applying electric field to a ferroelectric crystal, more particularly to a polarization inversion method of ferroelectrics which is capable of forming a uniform polarization inversion pattern by shortening an electric field application time. Furthermore, the present invention relates to a method of fabricating an optical wavelength conversion device, which applies the polarization inversion method of the ferroelectric.
2. Description of the Related Art
A method has been already proposed by Bleombergen et al., which changes a wavelength of a fundamental wave to that of a second harmonic by use of an optical wavelength conversion device providing an area in which a self-polarization (domain) of ferroelectric showing a nonlinear optical effect is periodically inverted (see Physical Review, Vol. 127, No. 6, pp. 1918 (1962)). In this method, a cycle xcex9 of a polarization inversion portion is set to an integer multiple of a coherence lengthxcex9c which is given by the following equation (1)
xcex9c=2xcfx80/{xcex2(2xcfx89)xe2x88x922xcex2(xcfx89)}xe2x80x83xe2x80x83(1)
where xcex2 (2xcfx89) is a propagation constant of a second harmonic and xcex2 (xcfx89) is a propagation constant of a fundamental wave. Thus, a phase matching of the second harmonic can be achieved. When the wavelength conversion is performed by use of a bulk crystal of a nonlinear optical material, a wavelength that is subjected to the phase matching is limited to a specific wavelength which is inherent to the crystal. However, according to the above described method, the phase matching that is a so-called pseudo phase matching can be effectively achieved by using the cycle xcex9 satisfying the equation (1) for an desired wavelength.
As a method forming the above described periodic polarization inversion structure, one has been known as described in Japanese Unexamined Patent Publication No.7(1995)-72521. In this method, after periodic electrodes having a predetermined pattern are formed on one surface of a ferroelectric crystal showing a nonlinear optical effect, which has been subjected to a single polarization, a ferroelectric crystal is corona-charged by the periodic electrodes and a corona wire disposed on a surface opposite to that one surface, and electric field is applied to the ferroelectric crystal, thus converting a portion opposite to one of the periodic electrodes of the ferroelectric crystal to a local polarization inversion portion.
In addition to the method which applies the corona charging, a method has been known as is described in Japanese Patent No. 3005225, in which an entire surface electrode is formed on the entire surface of ferroelectric opposite to a surface where periodic electrodes having a predetermined pattern are formed, and electric field is directly applied to the ferroelectric by use of the entire surface electrode and the periodic electrodes, thus forming a local polarization inversion portion.
When the polarization of the ferroelectric crystal is inverted by any of the above described conventional methods, one polarization inversion portion is formed in the portion opposite to a corresponding one of the periodic electrodes of the ferroelectric crystal.
Incidentally, in the case where a periodic polarization inversion structure having a particularly long cycle or a large area is formed in forming the periodic polarization inversion portions in the ferroelectric crystal by use of the above described electrodes, a long electric field application time is required. If the electric field application time is long, a problem is recognized, in which an inversion width is large in an earlier polarization inversion portion where a polarization inversion first starts, and the inversion width is small in a latter polarization inversion portion where the polarization inversion is started later, thus creating unevenness of the width of the polarization inversion portion.
When the foregoing problem occurs in the optical wavelength conversion device in which the periodic polarization inversion structure is formed in a ferroelectric crystal showing then on linear optical effect, a cycle or width ratio of the polarization inversion portions is uneven and a decrease in wavelength conversion efficiency is brought about.
In consideration of the foregoing circumstances, an object of the present invention is to provide a polarization inversion method of ferroelectrics, which is capable of accurately forming polarization inversion portions having a desired pattern in a short electric field application time.
Another object of the present invention is to provide a method of fabricating an optical wavelength conversion device, which is capable of forming a periodic polarization inversion structure having an excellent periodicity in a nonlinear optical crystal that is ferroelectric.
A first polarization inversion method of ferroelectric of the present invention is one in which one electrode having a shape corresponding to the area is not disposed in an area of a ferroelectric crystal where a polarization is desired to be inverted, but one in which a plurality of electrodes smaller than the area are disposed in this area, and electric field is applied to the ferroelectric crystal through the plurality of electrodes, the method comprising the steps of: forming electrodes having a predetermined pattern on one surface of the ferroelectric crystal that has been subjected to a single polarization; and forming a local polarization inversion portion in the ferroelectric crystal by applying electric fields to front and back surfaces of the ferroelectric crystal via the electrodes, wherein one polarization inversion portion having a desired pattern is formed by allowing portions of the ferroelectric crystal respectively corresponding to the plurality of electrodes and portions between these portions to be polarization-inverted.
A second polarization inversion method of ferroelectrics of the present invention is a method in which the first method is applied especially to a case where a periodic polarization inversion structure is formed. In this second method, periodic electrodes are used as the foregoing electrodes, which include a plurality of electrode groups formed periodically, each being composed of a plurality of electrodes; and each polarization inversion portion is formed for a corresponding one of the electrode groups, thus forming a periodic polarization inversion structure in which the polarization inversion portion is periodically and repetitively formed.
In the polarization inversion method of ferroelectric according to the present invention, a corona wire is disposed on one surface of a ferroelectric crystal opposite to one surface thereof, and electric field should be applied by corona charging by use of the corona wire and the electrodes.
The first and second polarization inversion methods of ferroelectric of the present invention are particularly effective when the ferroelectric crystal is a LiNbxTa1-xO3 (0 less than x less than 1) crystal or a crystal doped with one of MgO, ZnO and Sc.
On the other hand, a method of fabricating an optical wavelength conversion device of the present invention is a method to which the foregoing second polarization inversion method of ferroelectrics of the present invention is applied. In this method of fabricating an optical wavelength conversion device of the present invention, a nonlinear optical crystal is used as a ferroelectric crystal that has been subjected to a single polarization, and a periodic polarization inversion structure corresponding to a periodic pattern of the foregoing one group of the electrodes is formed in the nonlinear optical crystal.
In general, when a polarization of the ferroelectric crystal is inverted, it is proved by experiments that an inversion nucleus first occurs, and then a polarization inversion grows around the inversion nucleus. When electric field is applied to the ferroelectric crystal via the electrode, inversion nuclei that are the portions illustrated by the oblique lines occur in the ends of the electrode 51 of the ferroelectric crystal 52 as shown in FIG. 6A, and the inversion nuclei grow as shown in FIG. 6B. Then, the inversion nuclei connect with each other, and finally the polarization inversion portion 53 having a shape corresponding to the electrode 51 is formed as shown in FIG. 6C.
When the periodic polarization inversion structure was formed by the conventional method, the periodic electrodes 51 were previously formed in the ferroelectric crystal 52 as shown in FIG. 7A, and electric field was applied to the ferroelectric crystal 52 via the electrodes 51. With such an electric field application, the polarization inversion portions 53 were allowed to be grown from the electrodes 51 to regions outside the electrodes 51, respectively, as shown in FIG. 7B, and the polarization inversion portions having a desired pattern were formed. Particularly, when a cycle of the polarization inversion portions is long, it has been required to make an electric field application time longer in forming a desired pattern with, for example, an aspect ratio of 1:1.
When the electric field application time, that is, an inversion time was long as in the conventional method, it was proved that charges are apt to concentrate at an earlier polarization inversion portion, that is, at a portion where the inversion nucleus first occurs and this causes unevenness of a width of the polarization inversion. This phenomenon was remarkably recognized in a LiNbxTa1-xO3 (0 less than X less than 1) doped with one of MgO, ZnO and Sc, in which an electrical conductivity of the ferroelectric crystal changes greatly at the boundary of the polarization inversion and charges are prone to concentrate in the earlier polarization inversion portion.
In the first polarization inversion method of ferroelectrics of the present invention, the plurality of electrodes smaller than areas of the ferroelectric crystal where the polarization is desired to be inverted are previously arranged therein, and the electric field is applied to the ferroelectric crystal via the plurality of electrodes. Accordingly, compared to the conventional method in which one electrode having the shape corresponding to the area where the polarization is desired to be inverted is formed therein, more electrode terminals exist in one area where the polarization is desired to be inverted.
In FIGS. 8A and 8B, shown is a state where the polarization inversion portions 53 with a desired pattern are formed in the ferroelectric crystal 53. In FIGS. 8A and 8B, reference numeral 51 denotes electrodes, and, in FIGS. 8A and 8B, a case in which one polarization inversion portion 53 is formed by the two electrodes 51 is exemplified.
As described above, if more electrode terminals exist where the inversion nuclei occur, the inversion nuclei occur with a high density, so that the polarization inversion portions can be formed in desired areas within a short electric field application time. Accordingly, a drawback caused by a low density of the occurrence of the inversion nuclei and unevenness of the inversion nuclei, that is, a drawback in which the polarization inversion area is broad in the earlier polarization inversion portion and the polarization inversion area is narrow in the latter polarization inversion portion where the polarization inversion starts later is avoided, and the polarization inversion portion having a desired pattern can be formed accurately.
In the first polarization inversion method of ferroelectric of the present invention, periodic electrodes in which the electrode groups composed of the plurality of electrodes are arranged periodically are used as the electrode for use in the electric field application, and one polarization inversion portion is formed for a corresponding one of the electrode groups, thus forming the periodic polarization inversion structure in which the polarization inversion portion is periodically arranged. Accordingly, the second polarization inversion method of ferroelectric of the present invention can avoid a drawback in which the width of the polarization inversion is broad in the earlier polarization inversion portion and the width of the polarization inversion is narrow in the latter polarization inversion portion, and a periodic polarization inversion structure having a uniform cycle and width ratio can be formed.
On the other hand, the method of fabricating an optical wavelength conversion device of the present invention is a method to which the foregoing second polarization inversion method of ferroelectrics is applied. Since the periodic polarization inversion structure corresponding to the periodic pattern of the electrode group is formed in the ferroelectric crystal that is a nonlinear optical crystal, the method of fabricating an optical wavelength conversion device of the present invention can fabricate an optical wavelength conversion device showing high wavelength conversion efficiency, which comprises the periodic polarization inversion structure having a uniform periodicity.
The method of fabricating an optical wavelength conversion device of the present invention is effective when this method is applied to a fabrication of an optical wavelength conversion device which performs a wavelength conversion for infrared-zone light. Specifically, since such a kind of optical wavelength conversion device shows a comparatively long cycle of a polarization inversion portion, that is, a comparatively broad width of the polarization inversion portion, a necessary electric field application time is long, so that a width of the polarization inversion is apt to be uneven. However, occurrence of such a drawback can be reliably prevented with an application of the present invention.
If the cycle of the polarization inversion portions is comparatively long as described above, distance between the electrodes is comparatively broad, and it is easy to form a divided electrode group. On the contrary, when the polarization inversion portions of a short cycle are formed, the width of each electrode in one divided electrode group need be made very small, and working of the electrode is very difficult.
As the number of the electrodes constituting one electrode group is larger, more electrode terminals exist where the inversion nuclei occur, and the foregoing effects of the present invention become conspicuous. However, the width of each electrode becomes narrower as the number of the electrodes is made larger, resulting in difficulty of the working of the electrode. Accordingly, the number of the electrodes constituting one electrode group should be set properly in consideration for both of the effects and the workability.

Polarization inversion method of ferroelectrics and fabrication method of optical wavelength conversion device


The present invention relates to certain compounds of Formula Ia and pharmaceutical compositions thereof that modulate the activity of the cannabinoid CB2 receptor. The present invention further relates to certain compounds of Formula Ia and pharmaceutical compositions thereof that modulate the activities of both the CB1 receptor and the CB2 receptor. Compounds of the present invention and pharmaceutical compositions thereof are directed to methods useful in the treatment of: pain, for example bone and joint pain, muscle pain, dental pain, migraine and other headache pain, inflammatory pain, neuropathic pain, pain that occurs as an adverse effect of therapeutics and pain associated with osteoarthritis; hyperalgesia; allodynia; inflammatory hyperalgesia; neuropathic hyperalgesia; acute nociception; osteoporosis; multiple sclerosis-associated spasticity; autoimmune disorders; allergic reactions; CNS inflammation; atherosclerosis; undesired immune cell activity and inflammation; age-related macular degeneration; cough; leukemia; lymphoma; CNS tumors; prostate cancer; Alzheimer's disease; stroke-induced damage; dementia; amyotrophic lateral sclerosis, and Parkinson's disease.

Cannabinoids are a group of extracellular signaling molecules that are found in both plants and animals. Signals from these molecules are mediated in animals by two G-protein coupled receptors, Cannnabinoid Receptor 1 (CB1) and Cannabinoid Receptor 2 (CB2). CB1 is expressed most abundantly in the neurons of the CNS but is also present at lower concentrations in a variety of peripheral tissues and cells (Matsuda, L. A. et al. (1990) Nature 346:561-564). In contrast, CB2 is expressed predominantly, although not exclusively, in non-neural tissues, e.g. in hematopoietic cells, endothelial cells, osteoblasts, osteoclasts, the endocrine pancreas, and cancerous cell lines (Munro, S. et al. (1993) Nature 365:61-65; and as reviewed in Pacher, P. et al. (2006) Pharmacol. Rev. 58(3): 389-462). As such, CB1 is believed to be primarily responsible for mediating the psychotropic effects of cannabinoids on the body, whereas CB2 is believed to be primarily responsible for most of their non-neural effects.
The texts of the references cited in this disclosure are herein incorporated by reference in their entireties. In the event that a definition of a term as incorporated by reference differs from the meaning defined herein, then the meaning provided herein is intended.


The density for any generation of Standard In-Line Memory Module (SIMM), or Dual In-Line-Memory Module (DIMM), chipset used to provide computer Random Access Memory (RAM), can be multiplied by surface-mounting multiple banks of SIMMs or DIMMs, where each bank occupies one side of a printed-circuit board (PCB) and at least a second PCB is connected to a first PCB, which is in turn connected through the standard edge connectors to the bus, with the banks connected through shared and controlled input-and-output lines, and wherein a single standard controller directs address-oriented storage to the corresponding portion of the stacked and connected banks.

Not Applicable
Not Applicable
1. Field of the Invention
A computer system needs memory to store instructions and data that are processed by the central processing unit (CPU). In a typical computer, the CPU communicates with the memory via a bus, that sets a limit on the amount of parallel information (width) that can move in a single time unit. Memory comes in special chips known as DRAM (dynamic random access memory), which are packaged together in industry-standard modules. The chips are arranged in a line on a printed circuit board (PCB), with the memory chips either on a single side (SIMM, or Single In-Line Memory Module) or on both sides (DIMM, or Dual In-Line Memory Module). There are industry-standard machines for connecting memory chips to a board and then soldering the connections between the chips"" input/output (I/O) pins and the metal circuits printed on the board, because the cost and yield respectively increase and decrease when the same work is done by hand, even by skilled (yet thus more expensive) labor. The size of the memory chip on a SIMM or DIMM has become standardized to increase the manufacturability and lower the cost of the completed memory module. A memory module PCB, also known as a xe2x80x98memory bankxe2x80x99, will have a set of connectors between its on-board circuitry and the computer system bus additionally, it often has subordinate governing and special logic circuits to help manage the U/O flow between the memory module and the rest of the computer system.
There are two goals that designers, manufacturers, and users of memory modules strive for While the amount of memory that can be stored on a single memory chip has been increasing steadily the amount of memory necessary for smooth and fast operation of a computer system has also been increasing. Individual memory banks have gone through several generations in the past decade alone, moving from 8 megabytes to 16 megabytes to 32 megabytes to 64 megabytes per module, with 128 megabyte modules on the commercial horizon. Over roughly the same time, however, the minimum system RAM for a normal personal computer (PC) has shifted from 640K to 65MB. So one goal is to maximize, for the capacity of a given generation of memory chip, the total amount of memory that can be contained on a memory bank, when the memory bank is a SIMM (or DIMM) incorporating a number of such memory chips, within the same geometric limits for the memory banks.
At the same time that the amount of memory desired has increased, the price for memory has decreased (almost exponentially), just as the price paid for a given power computer has also decreased. This has created some unpleasant trade-offs for computer manufacturers, and for memory bank manufacturers. For the same amount of memory each year they will get less money, meaning that they constantly need ways to provide more memory for less cost. For this reason, anything that increases the manufacturing yield of a memory bank with a particular memory capacity, find anything that decreases the cost of manufacturing a memory bank, is a useful and valuable advance. Thus, decreasing the density of on-board circuitry for a memory bank necessary to provide memory capacity is a desirable result, since it decreases the cost and increases the yield of production of such. Two design elements that increase the cost, and decrease the yield, of producing a memory bank are, first, increasing the number of pin connectors needed to attain a given number of I/O connections between the memory bank and the bus; and second, requiring manual assembly and soldering of a given number of pin connections between the memory chips and the PCB the memory bank. The more pins that must be connected, the fewer banks can be manufactured in a given amount of time, and the lower the manufacturing yield will be (since there are that many more chances for a pin connection to be inaccurately made). If the number of connections required can be cut by a significant percentage, then the overall productivity for a given memory bank capacity will be increased.
Technological advances are costly to implement, and for certain implementations it is desirable to use less costly technology interchangeably with system configurations which can use higher technology. For example, sometimes it is desirable to use 16-meg chips with systems that support 64-meg technology. In such a configuration, a 64 or 72 bit wide data bus using 64-megabit (8M times 8) chips can be used. If the system is designed for 8M times 8 chips, the JEDEC standard is for a 12 times 11 address scheme (i.e., 12 row address bits and 11 column address bits). In such a scheme, only one bank is required to read all 64 or 72 bits, and thus only a single RAS signal is needed. However, 64 megabit chips all utilize 3.3 volt technology which for several reasons is quite expensive and thus, while fewer chips can be used to store the same information, these fewer chips in the aggregate are more expensive than using 16 megabit chips manufactured in 5-volt technology. For example. 8, 8 times 8 chips can be used to store the same amount of information as is stored in 32, 4 times 4 chips. However, the 32 4 times 4 chips are much cheaper in the aggregate than the 8.8 times 8 chips, and thus for many applications, even though more chips are involved, it is desirable to use the 5-volt technology and 32, 4 times 4 chips. As a result, computer designers have struggled to increase the amount of memory accessible within a given physical format or module even though there has been a more costly alternative of increasing the memory bank""s capacity by buying higher-priced but higher-capacity individual memory chips for that bank.
Moreover, bus limitations are now one of the bottleneck points to computer designs. The more that off-bus smarts can be designed into the memory bank, the less the load on the system for overhead, in managing memory addressing, becomes. A number of methods have already been designed to deal with part of this problem.
For example, a computer""s memory typically includes one or more memory banks (or memory components) connected in parallel such that each memory component stores one set of data, such as a word or double word, per memory address. The memory controller communicates with, and interprets commands from, the CPU to the memory modules. For example, the CPU issues a command and an address which are received and translated by the memory controller. The memory controller, in turn, applies appropriate command signals and row and column addresses to the memory modules. Examples of such commands include a row address strobe (RAS), column address strobe (CTS), write enable (WEE), and possibly a clock signal (CLK). (The line or bar over the acronym for a symbol generally indicates, that the active state for the particular signal is a logical low value.) In response to the commands and addresses, data is transferred between the CPU and the memory modules. Each time a memory changing update instruction must be issued, however, the computer""s cycle overhead is increased. Techniques that do not require the CPU to manage all details of memory storage decrease this overhead and thus indirectly increase performance; therefore, design elements of a memory bank that decrease the demand on the CPU to issue memory change updates indirectly increase performance.
Secondly, because the majority of program execution through the CPU is sequential in nature (operation 1, operation 2, operation 3 . . . , operation 50), program execution very often proceeds along a row of memory. When in page mode, the memory controller compares the row address of the memory location currently being accessed with the row address for the next memory access. If the row addresses are the same (known as a xe2x80x9cpage hitxe2x80x9d), then the memory controller continues asserting the RAS control signal at the end of a current bus cycle. Because the memory already has the correct row address, the new column address can be immediately transferred to the memory without requiring a RAS/CAS delay. Design elements on memory banks that support an approach of automatically flowing along the memory addresses without requiring CPU activity or RAS/CAS delays, again decrease system overhead costs and thereby indirectly increase performance. Thirdly, methods that can use extended data out (EDO) DRAMs (which are faster) improve upon the FPM DRAMs. In FPM DRAMs, the CAS high-to-low transition latches the column address, while the CAS low-to-high transition turns off an output buffer of the RAM. EDO DRAMs instead separate the two functions of the CAS signal. The low-to-high transition of CAS no longer turns off the output buffer. This change provides an extended time during which the output data is valid, hence the xe2x80x9cextended data outxe2x80x9d name. EDO memory allows the CPU to sample the output data even while an address for a subsequent data transfer operation is being set up for the next read cycle. Any design method that supports a memory bank approach that allows further extension of this approach will be valuable.
Fourthly, Burst EDO (BEDO) DRAMs improve upon the good idea used in EDO DRAMs (leaving data valid even after CAS goes high). Most current CPUs typically access BEDO DRAMs in four-cycle bursts at four adjacent memory locations to fill a cache memory. Recognizing this typical access operation. BEDO DRAMs quickly provide the following three addresses itself after receiving the first address. BEDO DRAMs; typically include a two-bit counter which provides three column addresses after the first received column address. The memory controller, and CPU, thus avoid the tight timing requirements of providing multiple addresses at appropriate times to the DRAM device. As a result, a xe2x80x9cdeadxe2x80x9d time occurring between the appearance of each bit, byte, word, set or xe2x80x9cgroupxe2x80x9d of valid data at the output pins of the BEDO DRAM device is reduced, as compared with respect to EDO and FPM DRAMs. For example, where an FPM DRAM requires an initial five clock cycles to provide a first data group, and three clock cycles for each of three subsequent data groups (i.e., xe2x80x9c5-3-3-3 burstingxe2x80x9d). BEDO DRAMs can provide bursting at rates of up to 5-1-1-1 or less. The longer that a xe2x80x98burstxe2x80x99 can be extended, the longer, of course, before the memory update instruction overhead is incurred. Memory bank design that supports such approaches will be valued.
Finally, an even faster form of DRAM is synchronous DRAM (SDRAM). FPM, EDO, and BEDO DRAM are asynchronous DRAM devices because they do not require a clock input signal. The memory controller for asynchronous devices receives the system clock signal and operates as a synchronous interface with the CPU so that data is exchanged with the CPU at appropriate edges of the clock signal. Memory controllers for SDRAM devices are necessarily simpler because the SDRAM devices and the CPU both operate based on a clock signal. To achieve optimum performance with a CPU, the SDRAM, device must be synchronized with the CPU. But the more memory that can be connected with the same clock device, the higher the SDRAM performance overall can be, again due to the decreased overhead.
As the speed of DRAM devices increase, other bottlenecks within computer systems arise. For example, as DRAM devices are operated at faster clock rates, the memory controllers to which they are coupled often cannot exchange data between the CPU and the memory device quickly, enough. Additionally, both BEDO DRAM and SDRAM devices required comparatively strict timing requirements compared to FPM and EDO DRAM devices. The strict timing requirements of BEDO DRAM requires a strict relation between generating an edge of CAS and when data is valid for reading or writing to the memory device. During each read cycle, CAS must fall during the middle of the period when data is to be read from the BEDO DRAM. For example, there is very little room for time delay or skew between the system clock and the CAS control signal supplied to the BEDO DRAM when the BEDO DRAM is operated in the 5-1-1-1 burst mode. As a result, designers must design their computer systems, or other applications, with minimum trace lengths on circuit boards to reduce propagation delays, and employ other methods to minimize skew between the system clock and command signals based on the clock. One memory controller chip set by Intel is believed to accommodate BEDO DRAM; however, such a chip set likely still requires the designer to be subject to the strict timing requirements of BEDO memory. Similarly, SDRAM devices require strict timing of data transfers with the SDRAM device in relation to the system clock signal. As a result of such strict requirements of BEDO DRAM and SDRAM devices, computer system designers and other users of DRAM devices have difficulty implementing such higher speed DRAM devices into their applications, despite the increased performance of such devices. As a result, system designers have accepted and employed lower speed DRAM devices in exchange for looser timing requirements in their designs, despite the speed and other benefits of BEDO and SDRAM devices. Another problem has been fitting the increasing density of memory within given physical constraints. A related problem has been providing memory within close enough physical location that timing difficulties, as detailed above, do not arise from greatly differing circuit lengths between differing memory banks. As the speed of memory access increases, this latter problem has worsened. As a result, designers must designs their computer systems, or other applications, with minimum trace lengths on circuit boards to reduce propagation delays, and employ other methods to minimize skew between the system clock and command signals based on the clock. With the new Burst Extended Data Out chips (BEDO), where memory access can automatically shift along more than one memory chip or module, comparatively strict timing (and thus circuit length) requirements exist.
Moreover, the denser the connecting lines between a memory bank and the bus, and between the PCB and the individual memory chips have to be, the greater the heat density, and the more difficult the manufacturability, of a particular memory bank becomes. The more that a design allows the memory banks to share I/O ports, the fewer pin connectors are required, decreasing manufacturing difficulty and cost, and increasing yield, for a given memory density.
The invention described below meets both of the goals mentioned above, and thus provides a significant advantage of the current state of the art for memory modules. First, for a given generation of memory chip, it doubles or quadruples the amount of memory that can be addressed in a single memory module using a single edge connector to the computer system bus, by allowing simultaneous access to a stepped fractional portion of the shared memory capacity aboard the module for each I/O operation or cycle, while requiring substantially less pin connectors for a given PCB. Instead of using 168 pins for a standard bank, it need only use 90 pins: and only half (32) the number of control connectors as on the standard approach (64), because the control connectors are shared between memory banks.
Secondly, because the control lines are, shared between banks, and thus only half the number are needed, the length of the lines is shortened between the I/O pins connecting to the system bus and the I/O pins connecting to the individual memory chips.
Thirdly, and again for a given generation of memory chip, the memory bank can be manufactured using industry-standard PCB assembly machinery rather than manual assembly to connect the memory chips"" pins to the PCB. Because the banks are flexibly connected with supporting elements, the completed memory unit is sturdier and thus easier to use in further assembly onto the computer motherboard.
Fourthly, because the memory chips are mounted onto standard PCBs rather than directly on top of each other, the yield is increased. Instead of using 100 memory chips to produce 40 directly-double-stacked memory banks, 100 memory chips are used to produce 50 double-bank memory banks. Furthermore, the number of steps required is a quarter that for other memory-bank production methods using stacking technology.
Finally, because the method allows the usage of industry-standard, surface mount machinery for automated assembly onto standard PCBs, rather than requiring dual-pass or manual mount approaches, the manufacturing costs and yields are comparable to those of memory banks with half the given capacity, for a particular generation of memory chip.
2. Description of the Related Art
Various means to deal with the memory constraints have been provided. Some memory modules have built in memory delays which copy the CAS signal (as seen by the BEDO) to control memory. Others have built separate memory controllers to control the signals from the motherboard to the memory board. None of these have addressed the need for increased memory density in a given physical locality, i.e. in a particular, single memory card attached to the motherboard and bus of the personal computer.
The concept of a stackable memory card, as seen in U.S. Pat. No. 5,963,464 ignores two significant, and one less, problems which are solved by the subject of this application. First, in that patent the orientation of the initial memory bank must be horizontal, and there must be space above the motherboard sufficient to contain the entire stack of xe2x80x98secondaryxe2x80x99 boards. Secondly, the additional wiring length (and distance) increases linearly with the addition of each memory card, which will create timing and control problems dependent upon the memory addressing used by the CPU. Finally, as the heat of the memory chips rises, there risk of chip failure from overheating increases with the addition of each stacked memory card.
The use of a Field Effect Transistor (FET) or other switching device to isolate- individual memory modules, and even memory chips, from each other on multiple-banks of memory in U.S. Pat. No. 5.953,215 addresses solely the desire to reduce the perceived capacitance and resistance from the presence of multiple memory chips. The switching devices in this invention require additional control signals out of the addressing methods to turn the switches on or off, and limit the memory throughput of the entire memory module to the lower limit set by the capacitance limit chosen by the module designer.
In the preferred embodiment of this invention at least two chipsets of industry-standard SIMM or DIMM RAM memory chips are first each mounted, using industry-standard surface mount technology, on a PCB with a chip and bank selecting controller chip, wherein the first bank contains an edge connector for linking the combined memory banks to the computer system, and the two banks share the data, address, and control lines from the edge connector to the memory chipsets. Address commands directed from the CPU are decoded to direct the memory I/O flow to the proper bank and row(s) to be addressed, with automatic updating through the capacity of, both banks to accommodate the programmed sequence. Burst lengths may be for 1, 2, 4 or 8, locations, or a full page, with a burst terminate option. Bank (i.e. column) addresses may be changed on each clock cycle to achieve a high-speed, fully random access. Moreover, while one bank is being addressed another, connected bank can be precharged to hide or eliminate the need for address update control information from the CPU. The PCBs are physically linked together by snap connectors which support the combination at four points, providing physical stability and adequate separation for heat dispersion from the memory chips. Because the banks are filled simultaneously (rather than serially), for a given address flow the number of row- or chip-change instructions will be reduced to the extent that multiple operations do not overflow the capacity, which is effectively doubled over that of a single bank. Because the distance between one bank and the next will be less than the distance along the bus between one module and the next, the time delay for addressing memory and the overall capacity within a given motherboard""s layout will be decreased and increased respectively. Finally, because the two banks share addressing, control, and data lines (with the controller circuit coordinating the flow between the banks), the density of leads on each bank is reduced for a given memory capacity, thereby increasing the manufacturabilty, yield, and longevity of a module with a given memory capacity.

High-speed, multiple-bank, stacked, and PCB-mounted memory module


An electrical connector assembly includes a first insulating body and a second insulating body connected with the first insulating body. A plurality of first contacts are disposed in the first insulating body, and a plurality of second contacts are disposed in the second insulating body. The rear-touching portion of the first contacts and the rear-touching portion of the second contacts touch each other. The front-touching portion of the first contacts and the front-touching portion of the second contacts mate with other connectors. There are a plurality of fixing blocks provided on the rear portion of the first insulating body and corresponding fixing holes defined in the rear portion of the second insulating body, so the electrical connector assembly according to the present invention has a simplified structure and is convenient for assembling.

1. Field of the Invention
The present invention relates to an electrical connector assembly, and more particularly, to an electrical connector assembly having simplified structure and being convenient for assembling.
2. The Related Art
It is known that electrical connector assemblies are indispensable units installed in electrical products for transmitting signals and power. For present, more and more electrical connector assemblies are designed to adapt to the variety, the multiple functions and the high transmission properties of the electrical products.
There is an electrical connector assembly, which has two mating faces for respectively mating with matching connectors. This electrical connector assembly commonly includes a first insulating body, a second insulating body and an assembling cover. The first insulating body receives a plurality of first contacts therein. The second insulating body receives a plurality of second contacts therein. The rear-touching portions of the first contacts and the rear-touching portions of the second contacts are respectively connected with a PCB. The assembling cover assembles with the first insulating body and the second insulating body together. As using, the front-touching portions of the first contacts and the front-touching portions of the second contacts respectively mate with the matching connectors.
However, the electrical connector assembly provides a separate assembling cover for assembling the first insulating body and the second insulating body, which results in complicated structure and inconvenience for assembling.


A two-step masking process is disclosed for forming a ball limiting metallurgy (BLM) pad structure for a solder joint interconnection used between a support substrate and a semiconductor chip. A solder non-wettable layer and a solder wettable layer are deposited on the surface of a support substrate or semiconductor chip which are to be connected. A phased transition layer is deposited between the wettable and non-wettable layers. A thin photo-resist mask defines an area of the solder wettable and phased layers which are etched to form a raised, wettable frustum cone portion. A second mask is deposited on the surface of the support substrate or semiconductor chip, and has an opening concentrically positioned about the frustum cone. Solder is deposited in the opening and covers the frustum cone and the area about its periphery. When solidified, the solder, acting as a mask, is used to sub-etch the underlying solder non-wettable layer thereby defining the BLM pad. When reflowed, the solder beads away from the surface of the solder non-wettable layer to form a ball which securely adheres about the frustum cone.

1. Field of the Invention
The present invention generally relates to a method for adhering a semiconductor chip to a supporting substrate and, more particularly, to a solder ball limiting metallurgy (BLM) process for improving the integrity of solder joint interconnections between a substrate and a chip.
2. Description of the Prior Art
Solder ball connections have been proven very successful for electrically connecting a semiconductor chip to a supporting substrate. Since the substrate surface is solder non-wettable, Pb/Sn (lead/tin) solder does not bond to the substrate surface directly. Hence, an intermediate pad structure must normally be used between the two surfaces to facilitate adhesion. U.S. Pat. No. 5,127,188 to Owada et al. shows an example of this type of solder joint wherein an adhesion pad, commonly known as ball limiting metallurgy (BLM), is interposed between a chip and, for example, an Sn/Pb alloy solder ball.
The solder ball fabrication could be done by use of either a dry or a wet process. In the conventional dry process, as described in U.S. Pat. No. 4,434,434 issued to Bhattacharya et al., the BLM and the solder are sequentially evaporated on the wafer surface through a thick metal or a photoresist mask. The BLM metalization typically consists of three layers of metalizations deposited in a single pump down cycle. These composite layers consist of an adhesion layer at the bottom and a solder wettable layer at the top, with an intermediate phase layer (a mixture of adhesion and wettable metalizations) between the two layers. The Cr/Phased Cr-Cu/Cu/Au metalization is often used as the BLM material and Pb-low Sn solder is a commonly used solder (sometimes called C-4 solder). Since the solder interconnection lies on top of the thin insulator layer on the chip surface and the joint is often subjected to mechanical and thermal stressing, the damage to the insulator could occur due to a localization of film stress within the joint. Specifically, the insulator damage could occur quite readily if the edges of the Cr and the Cu layers coincide. For this reason, an edge separation is needed to be maintained by extending the Cr edges beyond the Cu edges. This is done by a proper placement of the charges within the evaporator. This edge separation is needed for both the dry and the wet (plating) processes to maintain the mechanical integrity of the joint.
U.S. Pat. No. 4,360,142 to Carpenter et al. discloses a modified dry process, which uses a six layer BLM: CR/Cr-Cu phased/Cu/Cr-Cu phased/Cu/Au. During solder melting Au dissolves readily in the solder and the top Cu layer is wetted by the solder. However, due to the presence of an intervening top Cr-Cu phased layer, the bottom Cu remains unreacted. Carpenter et al. teaches that the thermal gradient in the joint can be reduced by the presence of the unreacted Cu, an excellent heat conduction material. The resulting reduction of the thermal gradient will greatly reduce the susceptibility to thermomigration, a process of atom depletion induced by the presence of a thermal gradient.
U.S. Pat. No. 4,360,142 discloses an alternative method of BLM fabrication. In this process, a blanket deposition of six layers of film is done on the wafer. Following deposition of the last layer, a layer of photoresist is formed on the surface, exposed to the desired pattern and developed. Suitable etching solutions are used to remove the exposed areas of all six layers of film to define the BLM. Subsequently, the solder is deposited via a metal mask over the BLM followed by the reflowing of the solder ball over the BLM pad. This process does not provide Cr-Cu edge separation and thus the insulator damage could readily occur in the disclosed structure.
In the wet process the solder deposition is made by electroplating the Pb-Sn solder on top of the blanket BLM metalization through the holes in a thick resist. At first, a blanket layer of Cr/phased Cr-Cu film is deposited on top of the water surface. This blanket film layer serves as the electrical contact for the electroplating. A thick layer of resist is laminated over the blanket BLM film and then hole patterns are generated by conventional lithography processes. By using the blanket film layer as a common electrical contact, the solder is then electroplated at the holes on top of the metalization layers. Next, the photoresist is stripped and the excess metalization layers are then chemically etched using the solder deposit as a mask. The etching is done sequentially by first removing the Cu layer, followed by the phased layer and then the Cr layer. Finally, in order to provide the edge separation, the Cu is etched off selectively. FIG. 1 shows this process results in an overhang of the phased layer. Specifically, FIG. 1 shows a solder wettable layer 16, intermediate phased layer 14 and a solder non-wettable layer 12 deposited on a supporting substrate 10. The wettable layer 16 and the non-wettable adhesion layer 12 are composed of different metals with the intermediate layer 14 being a phased combination of the two. A solder mass 18 is deposited over the structure. The actual BLM pad structure is defined after a series of electrochemical and chemical sub-etched processes using the solder mass 18 as a mask. The resulting structure consists of the phased layer 14 extending beyond both the non-wettable layer 12 and the wettable layer 16. As explained above, when heated, the solder mass 18 reacts with and adheres to the wettable layer 16. The layer arrangement of FIG. 1 is particularly undesirable since molten solder will come into contact with the extending edges of the phased layer 14. The phased layer 14 is a composition of wettable and non-wettable metals and could be wetted by the solder. Thus, the structure does not provide adequate edge separation between the wetted phased layer and the Cr layer. As a result, high stress concentration would develop at the BLM edges, causing insulator damage.

Process of making pad structure for solder ball limiting metallurgy having reduced edge stress

International Business Machines Corporation


Provided herein are compositions and methods for enhancing enzyme activity, half-life and/or thermostability. Also provided herein are compositions and methods including the enhanced enzymes. Also provided herein are methods and compositions related to improved pectinolytic enzymes, such as pectate lyase, which exhibit enhanced activity, thermostability and/or longer half-life.

Commercial enzyme preparations used in food processing generally contain a pectate lyase enzyme component, which catalyzes chemical reactions that lead to quality improvement in food products. Because the enzyme preparations may include constituents derived from microorganisms that are used to produce this enzyme, sterility, especially in the food processing context, can be an important consideration.
Normally, high temperatures can provide sterilization. However, the high temperatures that provide sterilization can result in enzyme denaturation. Consequently, the activity of enzyme can be decreased or lost.

Thermostable enzymes and methods of making and using the same


A system and method for the efficient transmission of information in a code division multiple access (CDMA) wireless telecommunication system. To increase the rate of reliable transmission, an orthogonal frequency-division multiplexing (OFDM) scheme is implemented in a direct-spread CDMA network, this combination sometimes being referred to as multi-carrier CDMA (MC-CDMA). Information (such as voice and data), interspersed with a known pilot signal, is encoded and spread across the frequency domain, rather than the time domain as in traditional CDMA; the allowable transmission bandwidth is divided into a number of carriers. To achieve even larger transmission rates, the guardband between carriers is eliminated. To prevent interference, the number of pilot transmissions is reduced and a corresponding number of frequency bins at the border of an OFDM block are loaded with zeros. The receiver simply ignores these subcarriers when reconstructing the transmitted signal.

The now ubiquitous telecommunication instruments commonly called cellular telephones (or simply "cell phones") are actually mobile radios having a transmitter and a receiver, a power source, and some sort of user interface. They are referred to as cell phones because they are designed to operate within a cellular network. Despite being radios, they typically do not communicate directly with each other. Instead, these mobile telephones communicated over an air interface (radio link) with numerous base stations located throughout the network's coverage area. The network base stations are interconnected in order to route the calls to and from telephones operating within the network coverage area.
FIG. 1 is a simplified block diagram illustrating the configuration of a typical cellular network 100. As may be apparent from its name, the network coverage area (only a portion of which is shown in FIG. 1) is divided into a number of cells, such as cells 10 through 15 delineated by broken lines in FIG. 1. Although only six cells are shown, there are typically a great many. In the illustrated network, each cell has associated with it a base transceiver station (BTS). Generally speaking, BTS 20 is for transmitting and receiving messages to and from any mobile stations (MSs) in cell 10; illustrated here as MS 31, MS 32, and MS 33, via radio frequency (RF) links 35, 36, and 37, respectively. Mobile stations MS 31 through MS 33 are usually (though not necessarily) mobile, and free to move in and out of cell 10. Radio links 35-37 are therefore established only where necessary for communication. When the need for a particular radio link no longer exists, the associated radio channels are freed for use in other communications. (Certain channels, however, are dedicated for beacon transmissions and are therefore in continuous use.) BTS 21 through BTS 25, located in cell 11 through cell 15, respectively, are similarly equipped to establish radio contact with mobile stations in the cells they cover.
BTS 20, BTS 21, and BTS 22 operate under the direction of a base station controller (BSC) 26, which also manages communication with the remainder of network 100. Similarly, BTS 23, BTS 24, and BTS 25 are controlled by BSC 27. In the network 100 of FIG. 1, BSC 26 and 27 are directly connected and may therefore route calls directly to each other. Not all BSCs in network 100 are so connected, however, and must therefore communicate through a central switch. To this end, BSC 20 is in communication with mobile switching center MSC 29. MSC 29 is operable to route communication traffic throughout network 100 by sending it to other BSCs with which it is in communication, or to another MSC (not shown) of network 100. Where appropriate, MSC 29 may also have the capability to route traffic to other networks, such as a packet data network 50. Packet data network 50 may be the Internet, an intranet, a local area network (LAN), or any of numerous other communication networks that transfer data via a packet-switching protocol. Data passing from one network to another will typically though not necessarily pass through some type of gateway 49, which not only provides a connection, but converts the data from one format to another, as appropriate.
Note that packet data network 50 is typically connected to the MSC 29, as shown here, for low data rate applications. Where higher data rates are needed, such as in 1xEV-DO or 1 xEV-DV networks, the packet data network 50 is connected directly to the BSCs (26, 27), which in such networks are capable of processing the packet data.
The cellular network 100 of FIG. 1 has several advantages. As the cells are relatively small, the telephone transmitters do not need a great deal of power. This is particularly important where the power source, usually a battery, is housed and carried in the cell phone itself. In addition, the use of low-power transmitters means that the mobile stations are less apt to interfere with others operating nearby. In some networks, this even enables frequency reuse, that is, the same communication frequencies can be used in non-adjacent cells at the same time without interference. This permits the addition of a larger number of network subscribers. In other systems, codes used for privacy or signal processing may be reused in a similar manner.
At this point, it should also be noted that as the terms for radio telephones, such as "cellular (or cell) phone" and "mobile phone" are often used interchangeably, they will be treated as equivalent herein. Both, however, are a sub-group of a larger family of devices that also includes, for example, certain computers and personal digital assistants (PDAs) that are also capable of wireless radio communication in a radio network. This family of devices will for convenience be referred to as "mobile stations" (regardless of whether a particular device is actually moved about in normal operation).
In addition to the cellular architecture itself, certain multiple access schemes may also be employed to increase the number of mobile stations that may operate at the same time in a given area. In frequency-division multiple access (FDMA), the available transmission bandwidth is divided into a number of channels, each for use by a different caller (or for a different non-traffic use). A disadvantage of FDMA, however, is that each frequency channel used for traffic is captured for the duration of each call and cannot be used for others. Time-division multiple access (TDMA) improves upon the FDMA scheme by dividing each frequency channel into time slots. Any given call is assigned one or more of these time slots on which to send information. More than one voice caller may therefore use each frequency channel. Although the channel is not continuously dedicated to them, the resulting discontinuity is usually imperceptible to the user. For data transmissions, of course, the discontinuity is not normally a factor.
Code-division multiple access (CDMA) operates somewhat differently. Rather than divide the available transmission bandwidth into individual channels, individual transmissions are spread over a frequency band and encoded. By encoding each transmission in a different way, each receiver (i.e. mobile station) decodes only information intended for it and ignores other transmissions. The number of mobile stations that can operate in a given area is therefore limited by the number of encoding sequences available, rather than the number of frequency bands. The operation of a CDMA network is normally performed in accordance with a protocol referred to as IS-95 (interim standard-95) or, increasingly, according to its third generation (3G) successors, such as those sometimes referred to as 1xEV-DO and 1xEV-DV, the latter of which provides for the transport of both data and voice information.
FIG. 2 is a flow diagram illustrating the basic steps involved in sending a CDMA transmission according to the prior art. At START it is assumed that information from an information source (such as a caller's voice) is available and that a connection has been established with a receiving node. At step 205, the audible voice information is sampled and digitally encoded. The encoded information is then organized into frames (step 210). Error detection bits are then added (step 215) so that the receiver can evaluate the integrity of the received data. The resulting signal is then convolutionally encoded (step 220). Block interleaving is then performed (step 225) on the resulting signal to further enhance the receiver's ability to reconstruct the bit stream with a minimum of error. The interleaved signal is then spread by a pseudonoise (PN) code (step 230), a long code is applied (step 235) and a Walsh code is used to spread the wave form and provide channelization (step 240). I and Q short codes are added (step 245) and the results filtered (step 250) before being combined and spread (step 255), then amplified (step 260) for transmission.
As alluded to above, mobile stations and the network they are a part of are presently being used to carry an increasingly large amount of traffic. Not only is the number of ordinary voice calls increasing, but so is the number of other uses to which mobile stations can be put. Short message service (SMS) messaging and instant messaging are becoming more popular, faxes and emails can be sent through mobile stations, and World Wide Web pages can be downloaded. Portable personal computers can be equipped to send through the network data files such as spreadsheets, word processing documents, and slide presentations. All of this information may enter and leave the network infrastructure through the air interface, meaning that more efficient methods of radio transmission are constantly in demand. The present invention presents a solution that addresses this growing need.

Method and apparatus for increasing data rates in a wideband MC-CDMA telecommunication system


Stable unit dose compositions with high water content are provided. Such unit dose compositions include an aqueous composition having a water activity of from about 0.65 to about 0.95 and a water-soluble container formed from a water-soluble or water-dispersible film material. In one embodiment, the aqueous composition includes water in an amount of 25% to 70% by weight, a surfactant system, and a water binding agent. The surfactant system may include: (1) a linear alkylbenzene sulfonate (LAS) and/or an alcohol ethoxylsulfate (AES), (2) a non-ionic surfactant, and (3) a fatty acid. The unit dose compositions can prevent the enclosed liquid detergent composition with a high level of water content from dissolving or pre-maturely dispersing the water-soluble container.

Unit dose compositions can include a beneficial composition such as a detergent product, a color care agent, a softening agent, or a fragrance. Unit dose detergent products are often found by consumers to be preferable for use as they have several advantages, including convenience of use and dispensing, lower cost per use, and avoiding or minimizing direct skin contact with potentially irritating cleaning compositions.
Unit dose liquid detergent compositions are often contained within water-soluble or water-dispersible films, and thus are limited to low water levels to prevent the films from being dissolved or dispersed pre-maturely by the enclosed liquid detergent compositions. The typical water content of a unit dose liquid detergent composition is less than 25 wt % based on the total weight of the composition.
For example, U.S. Pat. No. 4,793,416 discloses unit dose liquid detergent compositions enclosed within a water-soluble polymeric film pouch, which exemplifies a liquid detergent composition with a water content of 16.29 wt %.
U.S. Pat. No. 6,037,319 discloses water-soluble packets containing concentrated liquid cleaning compositions, which contain less than about 10 wt % of water.
U.S. Pat. No. 7,563,757 discloses water soluble pouches containing liquid detergent compositions which contain less than 25 wt % water, and preferably between 5-15 wt % water.
US 2016/0040099 A1 discloses a unit dose liquid laundry detergent composition containing about 5.5-20 wt % (e.g., 11.66 wt %) of water.
Water is an inexpensive ingredient of unit dose compositions and a ubiquitous solvent. There is a need for an aqueous composition that contains high water content, which would reduce the cost of goods while retaining the benefit of the beneficial composition. The present disclosure provides such an aqueous composition, as well as a method of producing and using such a composition in unit dose compositions.

This patent is subject to a terminal disclaimer.