A feed table apparatus (30) for moving a workpiece (31) toward a machine tool. The apparatus (30) comprises a roller assembly (32) which provides rolling support of the workpiece (31) toward machine tool and a shuttle vise assembly (36) for moving the workpiece (31) longitudinally along the roller assembly (32). The shuttle vise (36) includes a reaction frame (37) having a first upright post (40) and a second upright post (40') A coupling mechanism (43) movably mounts the reaction frame (37) directly to the elongated roller framework (33) for longitudinal relative movement therealong. The coupling mechanism (43) further couples the reaction frame (37) to the roller framework (33) in a manner transferring reaction forces, caused by clamping the workpiece (31) with opposing vise jaws (41, 41') to the roller framework (33).

An automated feed table is often employed to feed bar stock and other types of workpieces to a machine tool, such as a band saw, table saw, drill or milling machine, etc. FIGS. 1 and 2 illustrate a prior art feed table apparatus 10a of the type used to feed small to moderate size workpieces to a band saw. Feed table 10a includes a roller assembly 11a which provides rolling support of a workpiece 12a (shown in phantom lines). The feed table also includes a fixed vise assembly 13a mounted to a feed table frame 15a and a movable shuttle vise assembly 14a movably mounted to feed table frame 15a. Fixed vise assembly 13a and shuttle vise assembly 14a cooperate to grip and stabilize workpiece 12a during cutting by machine tool 16a. Shuttle vise 14a also cooperate with the fixed vise to move the workpieces toward band saw 16a.
When production cutting of bar stock is performed, the feeding and cutting sequence typically includes the following automated steps: gripping of the bar or bars (workpiece 12a) with movable shuttle vise assembly 14a; releasing the fixed vise assembly 13a; advancing workpiece 12a toward the band saw and beyond blade 17a (which is moved to a retracted position) by moving shuttle vise assembly 14a; stabilizing workpiece 12a relative blade 17a by clamping the same by fixed vise assembly 13a; cutting workpiece 12a to length by blade 17a; releasing movable shuttle vise assembly 14a and moving it back away from cutting blade 17a while continuing to clamp workpiece 12a by fixed vise assembly 13a (and while retracting blade 17a); gripping workpiece 12a with movable shuttle vise assembly 14a; releasing fixed vise assembly 13a; and advancing workpiece 12a back toward cutting blade 17a for another cut.
Additionally, a fixed vise (not shown) will usually be provided on the saw table or base 19a to grip the workpiece immediately proximate blade 17a. Such a saw table vise also is automatically operated to open and close with operation oil the feed table vises (usually substantially in the same operation mode as fixed vise 13a).
Feed table designs, such as that illustrated in FIGS. 1 and 2, generally include opposing vise jaws 18a and 18a' cantilevered upwardly from vise bases 20a and 20a' which are mounted (or movably mounted, with respect to shuttle vise 14a) to feed table guide ways 15a. Upward cantilevered jaws 18a and 18a' have been found to have a common problem; namely, when clamping workpieces 12a, and particularly large workpieces, opposing jaws 18a and 18a' tend to spread apart or open up at the upper portions of the jaws. As jaws 18a and 18a' push against workpiece 12a, the resistance to compression exerted by workpiece 12a causes upper portions or ends of opposing jaws 18a and 18a' to separate outwardly.
Such separation can be problematic because workpiece 12a will not be properly gripped by either fixed vise assembly 13a and/or shuttle vise assembly 14a, which may permit workpiece 12a to move or slip upwardly and/or axially during the cutting sequence. Accordingly, workpiece 12a may be improperly cut, adversely affecting cutting precision and accuracy, and in extreme situations, necessitating scrapping of workpiece 12a or portions cut from the workpiece. Typical of such prior art feed table designs are the feed tables disclosed in U.S. Pat. No. 4,179,961 and U.S. Pat. No. 3,504,585 to Harris; and U.S. Pat. No. 3,474,693 to Wilkie et al.
As the length, diameter, and accordingly the weight, of workpieces increases, machine tool feed tables have employed roller assemblies which include a plurality of side-by-side rollers capable of supporting and advancing larger and heavier workpieces. Such prior art feed tables, as illustrated in FIG. 3, also typically include reaction frame assemblies 21b which add substantial lateral stability and rigidity to the opposing jaws of the fixed vise and/or shuttle vise assemblies.
In FIG. 3, such a prior art feed table is illustrated and can be seen to include a vise reaction frame assembly 21b which extend over (upper cross-beam 23b) and under (lower cross-beam 24b) a guide roller assembly 11b. The vise reaction frame is positioned to resist the tendency of the opposing vise jaws 18b and 18b' of shuttle vise assembly 14b to open up in reaction to the clamping of workpieces (not shown). Shuttle vise assembly 14b includes at least one movable jaw 18b mounted to a first upright post 22b and an opposite jaw 18b' which may be rigidly fixed to a second upright post 22b'. Reaction frame assembly 21b, therefore, includes cross-beams 23b and 24b which are rigidly secured between the top and bottom of first post 22b and second poser 22b' to encircle roller frame assembly 116. Accordingly, gripping of a workpiece is very positive since the reaction forces are resisted by reaction frame assembly 21b. This reduces the tendency of opposing jaws 18b and 18b' to spread apart during clamping of workpieces.
In order to provide for displacement or shuttling of vise 14b, vise reaction frame assembly 21b must be capable of shuttling longitudinally along roller assembly 11b. Thus, lower cross-beam 24b is typically mounted on a pair of drive screws 25b and 25b' which reciprocate shuttle vise assembly 14b relative to roller assembly 11b. In operation, therefore, drive screws 25b and 25b' cause reaction frame assembly 21b and vise jaws 18b and 18b' to shuttle along feed table apparatus 10b outside longitudinal roller assembly frame members 26b and 26b'. As will be seen from FIG. 3, however, this construction requires that roller assembly 11b be mounted by legs 28b at the ends of frame members 26b and 26b' to table base 15b so that the cross-beam members can pass above and below roller frame members 26b and 26b'.
Accordingly, although reaction frame assemblies of this type effectively counteract the reaction forces caused by clamping the workpiece with jaws 18b and 18b', they, require a long span of roller frame members 26b and 26b' between its support legs, and they include an upper cross-beam 23b, which prevents laying the bar stock directly on the feed table from above. Additionally, such prior art vise reaction frames are rather complex, bulky and costly to construct.

Shuttle vise assembly for a feed table apparatus


An air handler unit (AHU) in communication with a building automation system (BAS) or through direct programming of one or more smart valves within the AHU operates to meter an amount of water that flows through a coil in the AHU. In one embodiment, the BAS transmits a temperature setpoint signal to the smart valve and allows the smart valve to control its valve position without additional input from the BAS. In another embodiment, the AHU includes a master smart valve and a second valve. The BAS provides the temperature setpoint signal to the master smart valve, which in turn provides another temperature setpoint signal to the second valve. The second valve may take the form of a slave smart valve or a slave non-smart valve.

Air handler units (AHUs) are commonly employed to condition and circulate air as part of a heating, ventilating, and air-conditioning (HVAC) system for buildings, and large buildings in particular. AHUs may provide heating, cooling, or both to change the supply air temperature, humidity level, or both depending on geographic location and current environmental factors. Such conditioning is provided by coil(s) (e.g., heat exchanger coils or cooling coils) located to interact with the AHU's air flow. AHUs may take the form of terminal units (also called fan coil units), packaged units or rooftop units, but will be referred to herein as AHUs for purpose of brevity.
Conditioning of the air flow typically employs the use of hot water or steam for heating and cool or chilled water for cooling. Coils for transferring heat may take the form of metallic tubes combined with metallic fins to encourage heat transfer; whereas cooling coils may employ eliminator plates and condensate pans to remove and drain condensation. In large buildings or building complexes, for example, central boiler and chiller plants are generally employed to generate hot water/steam and cool water, respectively. The water is circulated to and through the building in dedicated conduit.
In more modern HVAC systems, the AHUs may include self-regulating (also referred to as self-ranging, self-balancing or smart) valves that modulate the flow of the water through the coils inside the AHUs. These conventional smart valves typically communicate with water temperature sensors that monitor the temperature of the cold/hot water return and/or supply flows. When the water temperature sensors monitor both the return and supply flows, the smart valve may be configured to maintain a minimum temperature difference between the supply and return flows in addition to controlling the temperature of the air being discharged from the coil. In addition, the AHUs include fans or blowers that move the air flow over and/or through the coils to obtain a desired downstream or "off coil" air temperature and a desired airflow volume. The downstream air flow may be directed toward a desired space (e.g., a room or hallway) through air ducts and/or vents.
The control of the AHU, generally, and the control of at least some of the equipment comprising the AHU may be accomplished with an automation system such as, but not limited to a unit or building automation system (hereinafter generally referred to as a building automation system or BAS). Controlling the downstream air temperature, in particular, may be based on comfort requirements or desires, equipment capabilities, process requirements, efficiency goals, or some combination thereof.

Systems and methods for using a smart valve to control conditioned air


Alloys such as U-6Nb are prepared by forming a stacked sandwich array of uraniun sheets and niobium powder disposed in layers between the sheets, heating the array in a vacuum induction melting furnace to a temperature such as to melt the uranium, holding the resulting mixture at a temperature above the melting point of uranium until the niobium dissolves in the uranium, and casting the uranium-niobium solution. Compositional uniformity in the alloy product is enabled by use of the sandwich structure of uranium sheets and niobium powder.

Certain applications exist for uranium-base alloys containing small amounts of niobium, for example, U-6Nb. Alloys of this composition have proven difficult to prepare. Direct alloying as by combining plates or pieces of the metals and melting in a vacuum induction furnace has not been effective owing to a lack of compositional control in the resulting cast product. An expensive and inefficient double arc melting process has been used to obtain alloys of controlled composition. Another approach employed, where U-Nb alloy scrap is being recycled and combined with additional amounts of uranium and niobium, includes multiple steps of combining the U-6Nb alloy scrap with the stoichiometric amount of uranium required for producing a half-round bar slab of uranium-2 wt. % niobium alloy and melting the mixture by vacuum induction melting, stacking the resulting U-2Nb alloy bars with slabs of niobium metal into a sandwich-type electrode, arc melting the electrode, and arc melting a second time to form a billet of U-6Nb. This combination of double arc melting and vacuum induction heating produces a satisfactory product that makes use of recycled scrap but is unduly complicated and expensive. A simpler process that avoids such multiple steps and that avoids any need for arc melting would be highly advantageous over the previously used processes.

Process for alloying uranium and niobium

The United States of America as represented by the United States Department of Energy


This invention relates to compositions and methods utilizing a chemotherapeutic drug and 6-bromoindirubin3′-oxime (BIO) for the treatment of cancer, including glioblastoma multiforme. The present invention demonstrates that BIO works synergistically with chemotherapeutic drugs to increase the cytotoxic effects of these drugs in glioma cells.

All publications herein are incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference. The following description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
Cancer remains among the leading causes of death in the United States and around the world. Various forms of cancer are differentially treated, depending in part on the location of a tumor. One particularly difficult group of tumors to treat includes those that reside in and near the brain. Treatment of brain tumors presents a number of problems, not the least of which being the dangers inherent in any surgical procedure involving regions of the brain and the tissue located nearby. There is little room for error and the consequences of even a minor surgical mishap can be devastating to a patient; brain damage, or even death may result. Still, where possible, surgery remains the preferred method of treatment for most brain tumors and is often performed in conjunction with radiation therapy and chemotherapy. However, even commonly referenced medical authority suggests that patients with brain tumors be referred to centers specializing in investigative therapies; an indication that conventional modes of treatment are not overwhelmingly successful.
Glioblastoma multiforme and anaplastic astrocytomas are classified in the category of brain tumors commonly known as malignant gliomas. Although not particularly common tumors themselves, they represent a class of tumors associated with significant rates of mortality and morbidity. Indeed, brain tumors are the third-most frequent cause of cancer-related death in middle-aged males and the leading cause of cancer death in children. According to the National Brain Tumor Foundation, approximately 190,000 people are diagnosed with primary or metastatic brain tumors in the United States each year. According to the Society for Neuroscience, approximately 20,000 cases of glioma are diagnosed each year, and more than half die within 18 months. For patients with the most severe, aggressive form of glioblastoma multiforme ("glioma" or "GBM"), median survival is less than a year. Current treatment for malignant glioma consists of surgical resection followed by radiation therapy and chemotherapy. However, this treatment generally fails in substantially changing the outcome for a patient. Thus, there remains a significant need in the art for improved methods for the treatment of cancer, and, in particular, for brain tumors.
Cancers are primarily comprised of a heterogeneous population of cells with marked differences in their proliferative potential. Cancer stem cells are a minor population of tumor cells that possess the stem cell property of self-renewal, and it is believed that dysregulation of stem cell self-renewal is a likely requirement for the development of cancer. (Al-Hajj, M. et al., Therapeutic Implications of Cancer Stem Cells, CURR. OPIN GENETIC DEV. 2004 14:43-47.)
Stem cells have the capacity to replicate themselves into cells with similar properties in order to maintain a pool of precursor cells. Adult stem cells, also called tissue stem cells, are found in differentiated tissues in which, in a controlled manner, they differentiate and/or divide to produce all the specialized cell types of the tissue from which they originate. Adult stem cells are often multipotent, capable to produce several but limited numbers of cell types. Normal tissue stem cells are typically defined by three common properties: (i) the presence of an extensive capacity for self-renewal that allows maintenance of the undifferentiated stem cell pool over the lifetime of the host; (ii) strict regulation of stem-cell number; and (iii) the ability to undergo a broad range of differentiation events to clonally reconstitute all of the functional elements within the tissue. Importantly, the stem cells in each tissue differ with respect to their intrinsic ability to both self-renew and to differentiate into particular mature cell types (Bixby, S. et al., Cell-Intrinsic Differences Between Stem Cells From Different Regions Of The Peripheral Nervous System Regulate The Generation Of Neural Diversity, NEURON 2002, 35:643-656).
The use of 6-bromoindirubin-3′-oxime ("BIO") to maintain embryonic stem cells in an undifferentiated state is known in the art. (Sato et al., Maintenance of Pluripotency in Human and Mouse Embryonic Stem Cells through Activation of Wnt Signaling by a Pharmacological GSK-3-specific Inhibitor, NAT. MED. (2004), 10(1), pp. 55-63, and Meijer et al., GSK-3-selective Inhibitors Derived from Tyrian Purple Indirubins, CHEM. BIOL. (2003), 10(12), pp. 1255-1266.) Indirubin-type compounds are also used to inhibit GSK-3 and other protein kinases. (International PCT Pat. App. Pub. No. WO 2005/041954, filed Oct. 28, 2004.) BIO has been isolated, included pharmaceutically acceptable compositions, salts, or vehicles thereof, and methods of inhibiting GSK-3 activity with BIO in vitro or in a cell have been described.
Several genes initially linked to carcinogenesis have been implicated in the regulation of the normal stem-cell self-renewal process, including the Bmi-1, Notch, Wnt and Sonic hedgehog pathways. (Spink, K. E. et al., Structural Basis of the Axinadenomatous Polyposis Coli Interaction, EMBO J. 2000, 19:2270-2279; Taipale, J. et al., The Hedgehog and Wnt Signaling Pathways In Cancer, NATURE 2001, 411:349-354; Bhardwaj, G. et al., Sonic Hedgehog Induces the Proliferation of Primitive Human Hematopoietic Cells Via Bmp Regulation, NAT IMMUNOL 2001, 2:172-180; Austin, T. W. et al., A Role for the Wnt Gene Family In Hematopoiesis: Expansion of Multilineage Progenitor Cells, BLOOD 1997, 89:3624-3635.) For example, Reya et al. (A Role for Wnt Signaling in Self-Renewal of Hematopoietic Stem Cells, NATURE 2003, 423:409-414) demonstrated the dependence of normal HSC self-renewal decisions on Wnt-signaling through the canonical pathway. Willert et al. demonstrated the ability of purified Wnt3a to permit the in vitro expansion of transplantable HSCs. (Willert, K. et al., Wnt Proteins Are Lipid-Modified and Can Act as Stem Cell Growth Factors, NATURE 2003, 423:448-452.) Additional studies implicate the Wnt/b-catenin pathway in the maintenance of stem-cell self-renewal in other tissues as well. (Andl, T. et al., Wnt Signals Are Required for the Initiation of Hair Follicle Development, DEV CELL 2002, 2:643-653; Jamora, C. et al., Links Between Signal Transduction, Transcription and Adhesion in Epithelial Bud Development, NATURE 2003, 422:317-322.)
Cyclins and cyclin-dependent kinases (CDK) are key regulators in mammalian cell cycle. Regulation of these complexes occurs through cyclin production and destruction, relocation, inhibitory and activating phosphorylation events, relocation and also via the effects of other proteins. Each cyclin associates with one or two CDKs and most CDKs associate with one or two cyclins. CDK1 forms a complex with cyclin A/B and regulates phosphorylation of cytoskeleton proteins involved in mitosis. CDK2 and CDK3 form complexes with cyclin E which regulate the G1-S phase transition while the CDK2/CycA complex regulates S phase progression. CDK4/CycD and CDK6/CycD are activated by mitogenic signaling during early G1 and progressively accumulate as cells transition through this phase of the cell cycle. CDK5 is activated in postmitotic neurons and regulates neuron migration during brain development. CDK7/CycH is believed to be a link between transcription and cell cycle. CDK8/CycC and CDK9/CycT are involved in transcription. The kinase activity of CDKs is tightly regulated by phosphorylation and protein-protein interactions. Activation of CDKs requires binding to a specific cyclin and phosphorylation of a conserved threonine residue in a region called the T loop. Examining the phosphorylation of peptides by CDK/cyclin complexes suggests that both CDKs and cyclins play a role in recognizing substrates. A consensus sequence, (S/T)PX(R/K), is identified in the peptides that are phosphorylated by CDK/cyclins.
Cyclin-dependent kinase activity is regulated by T-loop phosphorylation, by the abundance of their cyclin partners and by association with CDK inhibitors of the Cip/Kip or INK family of proteins. The inactive ternary complex of CDK4/cyclin D and p27 Kip1/Cip1 requires extracellular mitogenic stimuli for the release and degradation of p27, which affects progression through the restriction point and pRb-dependent entry into S-phase. The active complex of CDK4/cyclin D targets the retinoblastoma protein for phosphorylation, allowing the release of E2F transcription factors that activate G1/S-phase gene expression. In HeLa cells, upon UV irradiation, upregulation of p16 INK4a association with CDK4/cyclin D3 leads to a G2 delay, implicating CDK4/cyclinD3 activity in progression through G2-phase of the cell cycle.

Treatment of cancer with bio and chemotherapy


A maximum likelihood decoding circuit is arranged to reduce the power consumption through the effect of the Viterbi algorithm. A plurality of storing elements 61a to 61h located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks 60(1) to 60(D) in a manner to correspond to the combination (state) of intra-code interferences. The outputs from the storing elements 61a to 61h are again applied into the inputs of the corresponding storing elements contained in the same storing element block through the path history selecting circuits 62a to 62h. Each of the storing element block 60(1) to 60(D) is periodically started on the input timing of a receiving signal at each processing time point by starting points (pointers) 63(1) to 63(D) outputted from a starting signal (pointer) generating circuit 68. A storing element block output circuit 64 and storing element block output terminals 65(1) to 65(D) are provided in each of the storing element blocks 60(1) to 60(D) so that a path memory circuit output 67 may be outputted through an OR circuit 66.

The present invention relates to a receiving device or a reproducing device provided in an information transmitting and communicating apparatus or an information storing and reproducing apparatus and more particularly to a maximum likelihood decoding device or a method of implementing a general composition of a maximum likelihood decoding circuit widely used in various information processing and signal processing devices.
In order to improve low-quality transmission or reliability of data reproduction from a recording and reproducing signal in a fast information communications system or a high-density information recording and reproducing system, there has been widely used an error correction demodulation technique based on a data decoding technique and a convolutional encoding technique that utilizes the MLSD (Maximum Likelihood Sequence Detection).
This maximum likelihood sequence detection is a technique of suppressing a probability of causing an error in a decoded code sequence to a minimum by estimating the decoded code sequence in time series based on the storage characteristic or the correlation of the decoded data. In this technique, when a received signal sequence {Y(n)} (n denotes an integer for indicating a discrete signal occurrence sequence and time) is given into the decoding input, the maximum likelihood sequence of receiving {Y(n)} (the maximum likelihood sequence) is selected from all possible transmission information (code) sequences {X(n)} and then the maximum likelihood sequence is outputted as the decoded information (code) sequence {Z(n)}. In other words, given all possible sequences of a certain receiving signal sequence {Y(n)}, on the assumption of a certain transmitting sequence {X(n)}, the transmitting sequence {X(n)} is selected so that the a-posteriori probability P ({Y(n)}/{X(n)}) before and after the receiving signal sequence {Y(n)} is received is made maximum, for estimating the maximum likelihood sequence of the decoded sequence {Z(n)}. At this time, the transmitting sequence {X(n)} is estimated not independently but on the context. This kind of maximum likelihood sequence detection provides the most excellent decoding error probability in the decoding operation as keeping a correct decision probability P ({X(n)} and {Z(n)}) (the probability of coinciding the transmitting sequence {X(n)} with the decoded sequence {Z(n)}) in the condition of transmitting all possible transmission sequences {X(n)} at equal probabilities, in other words, in the condition of giving no information about the transmitting probability of each transmitting sequence {X(n)}.
This maximum likelihood sequence detection is efficiently realized by using a dynamically programing Viterbi algorithm. The papers about the maximum likelihood sequence detection and the Viterbi algorithm are, for example, G. D. Forney, xe2x80x9cThe Viterbi Algorithmxe2x80x9d, Proceedings of the IEEE, vol. 61, No.3, March 1973, pp.268 to 278 and G. Ungerbock, xe2x80x9cAdaptive Maximum Likelihood Receiver for Carrier-Modulated Data Transmission Systemsxe2x80x9d, IEEE Transactions on Communications, vol. COM-22, No.5, May 1974, pp.624 to 638. These papers discuss the receiver apparatus arranged to use the maximum likelihood sequence detection or its partial basic arrangement. Further, the actual implementation of the Viterbi Algorithm is discussed in detail in Hui-Ling Lou, xe2x80x9cImplementing the Viterbi Algorithmxe2x80x9d, IEEE Signal Processing Magazine, Sept. 1995, pp.42-52 and G. Fettweis and H. Meyr, xe2x80x9cHigh-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecturexe2x80x9d, IEEE Communications Magazine, May 1991, pp. 46 to 55.
The maximum likelihood sequence detection arranged to use this kind of Viterbi algorithm is executed to select the sequence having the maximum receiving likelihood (the maximum likelihood sequence) based on the context of the receiving signal sequences and output it as the most probable decoded information (code) sequence. This sequence corresponds to the decoded result. Hence, this detection needs to prepare a survivor path sequence history storing circuit (path memory) for storing the candidate sequences (survivor path sequences) of the maximum likelihood sequences to be progressively narrowed, sequentially updating the content based on the comparative operational result of the likelihood, and deciding the maximum likelihood decoded result. From a viewpoint of the principle of the Viterbi algorithm, this path sequence history storing circuit is required to store information about a long survivor path sequence history, which should be long enough to secure the decoding reliability against the noises in the receiving signal sequence. For implementing the Viterbi algorithm, it is necessary to prepare the survivor path sequence storing circuit (path memory) having a massive volume for corresponding to the required decoding reliability.
For example, a small-sized information processing instrument representatively such as a portable information terminal is earnestly required to reduce the power consumption for the purpose of suppressing the consumption of a cell and extending the operating time. In the case of applying the maximum likelihood decoding technique to a signal processing system included in this type of information processing instrument, the reduction of the electric power consumed in the path memory is one of the significant technical issues.
It is an object of the present invention to reduce the electric power consumed in a relatively large-scale survivor path sequence storing circuit (path memory) included in the maximum likelihood decoding circuit or the maximum likelihood decoding device.
It is an object of the present invention to provide a decoding circuit to be mounted into a relatively small-sized information processing instrument requested to lower the power consumption.
It is still another object of the present invention to provide a decoding circuit which enables to control and operate the instrument to be built into the system from various points of view.
It is a further object of the present invention to provide a decoding circuit which may improve flexibility in design, integrity in mounting, and yields in packing the decoding circuit to the semiconductor integrated circuit.
It is a still further object of the present invention to provide an information processing apparatus which is arranged to reduce the power consumption of the relatively large-scale survivor path sequence storing circuit (path memory) included in the mounted maximum likelihood decoding circuit or maximum likelihood decoding device, for realizing the reduction of the power consumption of the overall apparatus.
It is another object of the present invention to provide an information processing apparatus which is arranged to consume a low electric power and easily implement the high reliability based on the maximum likelihood decoding.
It is another object of the present invention to provide an information processing apparatus which may be controlled and prompted from various points of view and based on the information obtained from the mounted decoding circuit.
It is another object of the present invention to provide an information processing apparatus which is arranged to improve flexibility in design and integrity in packaging when packaging the mounted decoding circuit for doing the maximum likelihood decoding operation to a semiconductor integrated circuit.
The present invention utilizes convergence of the survivor path sequence information in the Viterbi algorithm. Of plural pieces of survivor path sequence information stored in the survivor path sequence storing circuit, the survivor path sequence information pieces corresponding to the convergence-completed portion are all identical with each other. The stored content is not varied from when the convergence is completed to when the information is outputted as the decoded result. In the actual decoding process, the phenomenon that the survivor path information pieces are not still convergent in the almost length of the prepared survivor path sequence storing circuit depends on the expected decoding reliability and hence is brought about so rarely. Normally, the survivor path sequence information is quickly and concentratively converted at a quite early stage of the length of the prepared survivor path sequence storing circuit. The present invention uses the property of the convergence of the survivor path sequence information for lowering a frequency of updating the stored content of the storing element of the survivor path sequence storing circuit and a utilization rate of the circuit, thereby reducing the power consumption. For this purpose, the present invention provides means for composing the survivor path sequence storing circuit for constantly holding plural candidates of the survivor path sequence information for each receiving signal sequence time in the same storage element block composed of plural storage elements and recursively updating the survivor path sequence information among the storage elements, for the purpose of concretely implementing the reduction of the circuit utilization rate. Further, for enhancing the reducing effect of the power consumption, the present invention provides means for predicting the storage element block in which the convergence of the survivor path sequence information is completed or the storage elements for holding the survivor path sequence information that is not necessary later than the present time and stopping a synchronous clock signal for starting the update operation of the predicted storage elements.

Decoding circuit using path sequence including feed-back type path sequence storing blocks


An image heating apparatus has a heater for generating heat when an electric power is supplied from a commercial power source to the heater, a temperature detecting element for detecting a temperature of the heater, a control wave number setting circuit for setting a control wave number of the electric power to be supplied to the heater, and an electric power controlling circuit for controlling the electric power supplied to the heater in accordance with a detected temperature from the temperature detecting element and the control wave number set by the control wave number setting circuit.

1. Field of the Invention
The present invention relates to an image heating apparatus used in an image forming apparatus such as a copying machine, a printer and the like.
2. Related Background Art
In the past, as image heating apparatuses used as fixing apparatuses, for example, there has been proposed a fixing apparatus comprising a heat generating resistor for generating heat when it is energized by a commercial power source, a temperature detector for detecting a temperature of the heat generating resistor, and a control means for controlling a transmission and interruption of an electric power from the commercial power source to the heat generating resistor on the basis of the temperature detected by the temperature detector, and such a fixing apparatus has been put to practical use.
In such a fixing apparatus, the temperature of the heat generating resistor is controlled by switching a condition of the apparatus to an energized condition or a de-energized condition for each half wave of an electric power outputted from the commercial power source, in accordance with the detected temperature from the temperature detector.
In this case, the control means controls the number of energizating waves within a predetermined period (control wave number) including a predetermined number of half waves of alternating current supplied from the commercial power source to the heat generating resistor, on the basis of the detected temperature.
However, since the predetermined period is constant, for example, if the predetermined period is long, although fine control of electric power can be made because the number of half waves (for each predetermined period) controllable for the transmission and interruption of the electric power from the commercial power source to the heat generating resistor is great, response to the detected temperature of the temperature detector is worsened because a time period between a previous control and a next control becomes long. On the other hand, if the predetermined period is short, although the response to the detected temperature of the temperature detector can be improved because the time period between the previous control and the next control is short, the fine control of electric power cannot be made because the number of half waves (for each predetermined period) controllable for the transmission and interruption of the electric power from the commercial power source to the heat generating resistor is small.
Therefore, when the predetermined period is constant, since the fine control of electric power and the response are not compatible, it is difficult to achieve further improvement in temperature control accuracy.

Image forming apparatus with control wave number setting means


Methods for managing a single memory pool comprising frame buffer memory and display list memory are presented. The single memory pool can comprise sub-pools including: a super-block pool comprising a plurality of super-block objects; a node pool comprising a plurality of node objects; and a block-pool comprising a plurality of blocks. The method may comprise: receiving a memory allocation request directed to at least one of the sub-pools; allocating an object local to the sub-pool identified in the memory request, if local sub-pool objects are available to satisfy the memory request; allocating an object from super-block pool, if the memory request is directed to the node-pool or block-pool and there are no available local objects in the respective sub-pools to satisfy the memory request; and applying at least one of a plurality of memory freeing strategies, if the sub-pools lack available free objects.

1. Field of the Invention
The present invention relates to the field of printing and in particular, to systems and methods for memory management for rasterization.
2. Description of Related Art
Document processing software allows users to view, edit, process, and store documents conveniently. Pages in a document may be displayed on screen exactly as they would appear in print. However, before the document can be printed, pages in the document are often described in a page description language ("PDL"). As used in this document PDL's may include PostScript, Adobe PDF, HP PCL, Microsoft XPS, and variants thereof as well as any other languages used to describe pages in a document. A PDL description of a document provides a high-level description of each page in a document. This PDL description is often translated to a series of lower-level printer-specific commands when the document is being printed. The process of translation from a PDL description of a document to a lower-level description that may be used to place marks on a print medium is termed rasterization.
The translation process from PDL to lower-level printer-specific commands may be complex and depend on the features and capabilities offered by a particular printer. Flexible and portable general-purpose schemes to translate PDL descriptions of documents to printer-specific commands may allow for the optimization of printer performance based on available memory, desired print speed, and other cost and performance criteria.
Traditionally, memory in printing systems has been organized in two distinct pools comprising the display list memory and the frame buffer memory. Display list memory typically holds display list objects for rasterization, while the frame buffer memory typically holds bitmapped data specifying marks to be made on a printed page. The use of separate memory pools prevents the use of display list memory for frame buffer purposes, and vice versa. Print failures can occur due to insufficient memory in either pool. In such situations, there may be sufficient extra memory in the one pool, but the memory is unavailable for use in the other memory pool because of the separate nature of the two pools. Moreover, the use of separate memory management routines to manage display list and frame buffer memory pools may make it difficult to modify and maintain the code used to manage memory across a product family because different strategies and optimizations may be used in individual products. For example, when display list memory is exhausted, one product may trigger pre-rasterization, whereas another product may swap display list memory to disk. The lack of uniformity and the often disparate assortment of memory management routines implemented greatly increases the difficulty of rolling out updates, and improving functionality and performance.
Thus, there is a need for systems and methods to manage memory on printers for rasterization that would allow a seamless upgrade path, while providing additional optimizations.

Systems and methods for memory management for rasterization


The invention relates to speech signal processing that detects a speech signal from more than one microphone and obtains microphone signals that are processed by a beamformer to obtain a beamformed signal that is post-filtered signal with a filter that employs adaptable filter weights to obtain an enhanced beamformed signal with the post-filter adapting the filter weights with previously learned filter weights.

1. Field of the Invention
This invention relates to processing of beamformed signals, and in particular to post-filtering of beamformed signals.
2. Related Art
Background noise is often a problem in audio communication between two or more parties, such as radio or cellular communication. Background noise in noisy environments directly affects the quality and intelligibility of voice conversations, and in the worst cases, the background noise may even lead to a complete breakdown of communication. With the use of hands-free voice communion devices in vehicles increasing, the quality and intelligibility of a voice communication signal is becoming more of an issue.
Hands-free telephones provide a comfortable and safe communication system of particular use in motor vehicles. The use of hands-free telephones in vehicles have also been promoted by laws enacted in many cities, such as Chicago, Ill., that requires the operator of a vehicle to use a hand-free device when making or receiving cellular telephones calls while operating the vehicle.
In addition to the quality of the voice communication signal between the parties on a telephone call, vehicles and communication devices are making use of voice commands. Voice commands often rely on voice recognition of words. If the voice command is issued in an environment with background noise, it may be misinterpreted or be unintelligible to the receiving device. Once again, the use of single channel noise reduction is desirable in such devices.
Approaches to single channel noise reduction methods employing spectral subtraction are known in the art. Such as, speech signals being divided into sub-bands by sub-band filtering where a noise reduction algorithm is applied to each of the sub-bands. These types of approaches, however, are limited to almost stationary noise perturbations and positive signal-to-noise distances. The processed speech signals are also distorted by these approaches, since the noise perturbations are not eliminated but rather spectral components that are affected by noise are damped. The intelligibility of speech signals is, thus, normally not improved sufficiently by these approaches.
Current multi-channel systems primarily make use of adaptive or non-adaptive beamformers, see, e.g., "Optimum Array Processing, Part IV of Detection, Estimation, and Modulation Theory" by H. L. van Trees, Wiley & Sons, New York 2002. The beamformer may combine multiple microphone input signals to one beamformed signal with an enhanced signal-to-noise ratio (SNR). Beamforming typically requires amplification of microphone signals corresponding to audio signals detected from a wanted signal direction by equal phase addition and attenuation of microphone signals corresponding to audio signals generated at positions in other direction.
The beamforming may be performed, in some approaches, by a fixed beamformer or an adaptive beamformer characterized by a permanent adaptation of processing parameters such as filter coefficients during operation (see e.g., "Adaptive beamforming for audio signal acquisition", by Herbordt, W. and Kellermann, W., in "Adaptive signal processing: applications to real-world problems", p. 155, Springer, Berlin 2003). By beamforming, the signal can be spatially filtered depending on the direction of the inclination of the sound detected by multiple microphones.
However, suppression of background noise in the context of beamforming is highly frequency-dependent and thus rather limited. Therefore, approaches that employ post-filters for processing the beamformed signals may be necessary in order to further reduce noise. But, such post-filters result in a time-dependent spectral weighting that is to be re-calculated in each signal frame. The determination of optimal weights, i.e., the filter characteristics, of the post-filters is still a major problem in the art. For instance, the weights are determined by means of coherence models or models based on the spatial energy. However, such relatively inflexible models do not allow for sufficiently suitable weights in the case of highly time-dependent strong noise perturbations.
Thus, there is a need for providing an approach for filtering background noise in the context of beamforming that overcomes the limitations of traditional post-filtering of the beamformed signal to reduce background noise.


A DD converter circuit 109 for interpolating a digital video signal which is locked to a 14.3-MHz burst clock to convert the sampling data so as to be locked to a 13.5-NHz free-run clock, and a frame memory circuit 110 for writing a digital video signal which is output by the DD converter circuit 109 on the 14.3-MHz burst clock as well as reading the written digital video signal on a 13.5-MHz clock S112 are included. Therefore, a video signal processor which can realize the rate conversion of the digital video signal without using an analog PLL circuit can be provided.

The present invention relate to a video signal processor for separating a television signal into Y (Luminance) and C (Color) signals and outputting the Y and C signals as digital video signals and, more particularly, to rate conversion of the digital video signals and generation of a clock which is used for the rate conversion.
Hereinafter, a prior art video signal processor for separating an analog television signal into Y (Luminance) and C (Color) signals, and converting the signals into digital video signals to be output is described with reference to drawings.
FIG. 9 is a block diagram illustrating the prior art video signal processor.
FIG. 10 are waveform charts of a video signal, FIG. 10(a) showing a video signal, FIG. 10(b) showing a synchronous signal, and FIG. 10(c) showing a burst signal.
FIG. 11 are diagrams for explaining the Y/C separation, FIG. 11(a) showing a video signal, FIG. 11(b) showing a Y (luminance) signal, and FIG. 11(c) showing a C (color) signal.
As shown in FIG. 9, the prior art video signal processor comprises an analog television signal input terminal 101, a first digital video signal output terminal 102, a first A/D converter circuit 103, a synchronization separator/burst detector circuit 104, a burst locked clock generator circuit 105, a Y/C separator circuit 106, a color decoder circuit 107, a TBC circuit 108, a divider circuit 112, a vertical/horizontal signal generator circuit 113, a multiplexer circuit 114, a D/A converter circuit 115, a second A/D converter circuit 116, a synchronization separator circuit 117, a horizontal synchronous clock generator circuit 118, a second digital video signal output terminal 201, a DVC preprocessing circuit 202, and a frame synchronization clock generator circuit 205.
Hereinafter, the operation of the so-constructed video signal processor is described.
The analog television signal input terminal 101 is an input terminal to which an analog television signal S101 is input. As the analog television signals, there are standard television signals which are determined by the standards like broadcasting, television signals whose synchronous signals have deviated frequencies or which include jitter, such as television signals which are reproduced for example by a video tape recorder, and non-standard television signals which are not standard television signals.
The first digital video signal output terminal 102 outputs a first digital video signal S102 which is obtained by multiplexing a Y (luminance) signal, a Cr (color difference-red) signal, Cb (color difference-blue) signal and a synchronous signal, to an apparatus or an equipment which is connected to this video signal processor, at a 27-MHz bit rate which is a transmission format of ITU-R recommendation BT.656 according to the digital interface standards.
The first A/D converter circuit 103 samples the analog television signal S101 on a 14.3-MHz burst locked clock S105 (which is described later), to be converted into a digital television signal S103. The first A/D converter circuit 103 also can sample the analog television signal S101 for example on a 28.6-MHz burst locked clock.
The synchronization separator/burst detector circuit 104 separates a synchronous signal S104a as shown in FIG. 10(b) from the digital television signal S103 as shown in FIG. 10(a) by a threshold. Further, the circuit 104 extracts a 3.58-MHz burst signal S104b as shown in FIG. 10(c), which is multiplexed as a reference signal for color reproduction, from the separated synchronous signal.
The burst locked clock generator circuit 105 multiplies the 3.58-MHz burst signal S104b by four to generate a 14.3-MHz burst locked clock S105.
The Y/C separator circuit 106 converts the digital television signal S103 in which a Y (luminance) signal and a C (color) signal are frequency-multiplexed as shown in FIG. 11(a), into a Y signal S106a as shown in FIG. 11(b) and a C signal S106b as shown in FIG. 11(c). When the input analog television signal is a standard television signal, still-picture parts are subjected to a three-dimensional processing using a frame memory, and moving-picture parts are subjected to a two-dimensional processing using a line filter, with utilizing the fact that the color phase is inverted frame/line by frame/line.
The color decoder circuit 107 demodulates the digital C signal S106 into a digital Cr signal S107a and a digital Cb signal S107b, because the phases of the Cr signal and the Cb signal are shifted by 90 degrees from each other.
The TBC (Time Base Corrector) circuit 108 detects the time of the horizontal synchronous signal of the synchronous signal S104a, and converts the Y signal S106a, the Cr signal S107a and the Cb signal S107b according to the length of the horizontal synchronous signal of the synchronous signal S104a, to be output as a Y signal S108a, a Cr signal S108b, and a Cb signal S108c.
The D/A converter circuit 115 converts the Y signal S108a, the Cr signal S108b and the Cb signal S108c which are the digital signals output from the TBC circuit 108, into analog signals, i.e., a Y signal S115a, a Cr signal S115b, and a Cb signal S115c.
The second A/D converter circuit 116 samples the Y signal S115a, the Cr signal S115b and the Cb signal S115c on a 13.5-MHz clock S112 (which is described later), to be converted into digital signals, i.e., a Y signal S116a, a Cr signal S116b and a Cb signal S116c. Here, it is also possible that the Cr signal and the Cb signal are multiplexed before being input to the second D/A converter circuit 115, and the D/A converter circuit 115 and the second D/A converter circuit 116 perform the conversion of the Y signal and the C signal. Further, the second A/D converter circuit also can perform the sampling for example on a 27-MHz clock.
The synchronization separator circuit 117 separates a horizontal synchronous signal S117a and a vertical synchronous signal S117b from the Y signal S116a, and outputs the signals.
The horizontal synchronous clock generator circuit 118 outputs a 27-MHz horizontal synchronous clock S118 which is synchronized with the horizontal synchronous signal S117a, to the divider circuit 112 and the multiplexer circuit 114. The horizontal synchronous clock generator circuit 118 is commonly constituted by an analog PLL circuit.
The divider circuit 112 divides the frequency of the 27-MHz horizontal synchronous clock S118 into 13.5 MHz. This 13.5-MHz clock S112 is the above-mentioned sampling clock which is input into the second A/D converter circuit 116.
The vertical/horizontal signal generator circuit 113 generates a synchronous signal S113 corresponding to a BT.656 transmission format, from the horizontal synchronous signal S117a and the vertical synchronous signal S117b, and output the signal S113.
The multiplexer circuit 114 multiplexes the Y signal S116a, the Cr signal S116b, the Cb signal S116c and the synchronous signal S113 on the 27-MHz horizontal synchronous clock S118, and outputs a multiplexed signal as the first digital video signal S102. The first digital video signal S102 is output from the first digital video signal output terminal 102 to an apparatus or an equipment which is connected to this video signal processor.
The second digital video signal output terminal 201 is an output terminal for outputting a second digital video signal S201 in which the Y signal, the Cr signal and the Cb signal are multiplexed, at 18 MHz. The second digital video signal S201 is input to a DCT (Discrete Cosine Transform) block for performing intra-frame compression/decompression, processed at 18 MHz, and thereafter recorded/reproduced by a block for performing recording/reproduction into/from a tape.
The DVC preprocessing circuit 202 multiplexes the 13.5-MHz Y signal S116a, Cr signal S116a and Cb signal S116c which are output from the second A/D converter circuit 116, on the basis of a 18-MHz clock S205 which is synchronized with one frame (described later), to be output as the second digital video signal S201. At this time, the DVC preprocessing circuit 202 decompresses the Y signal S116a into a 18-MHz Y signal, thins down the Cr signal S116b and the Cb signal S116c into 9 MHz, and thereafter multiplexes these signals.
The frame synchronization clock generator circuit 205 generates and outputs the 18-MHz clock S205 which is synchronized with one frame, corresponding to twice of the vertical synchronous signal S117b which is output from the synchronization separator circuit 117. Here, the frame synchronous clock generator circuit 205 is commonly constituted by an analog PLL circuit.
However, in the prior art video signal processor, in order to convert the rates of the 14.3-MHz digital Y signal, digital Cr signal and digital Cb signal to obtain the 13.5-MHz digital Y signal, digital Cr signal and digital Cb signal, it is required to provide an external analog PLL circuit, like the horizontal synchronous clock generator circuit 118 for generating the 27-MHz horizontal synchronous clock S118. Further, also when the 13.5-MHz digital Y signal, digital Cr signal and digital Cb signal are subjected to the rate conversion to obtain the 18-MHz digital Y signal, digital Cr signal and digital Cb signal, and then these signals are multiplexed, an analog PLL circuit like the frame synchronization clock generator circuit 205 for generating the 18-MHz clock S205 is required.
As described above, in the prior art video signal processor, it is required to provide an external analog PLL circuit to perform the rate conversion of the digital video signals, whereby the circuit (component) scale is increased and the integration of the LSI becomes difficult.
Therefore, the present invention has an object to provide a video signal processor and a video signal processing method, which reduces the circuit scale as well as facilitates the integration of the LSI.
A sampling frequency converter according to one aspect of the present invention comprises: a digital-digital conversion means for receiving a first digital video signal which has been sampled on a first clock signal having a first frequency, interpolating the first digital video signal to calculate a second digital video signal, a length of one horizontal period and a sampling frequency of which signal are the same as those of the first digital video signal and an effective pixel period in one horizontal period of which signal is N times (N greater than 0) as long as that of the first digital video signal, and converting the first digital video signal into the second digital video signal to be output on the basis of the first clock signal; a clock generation means for generating a second clock signal having a second frequency which is one-Nth as high as that of the first clock signal; and a storage means for retaining the second digital video signal as well as reading the retained second digital video signal on the second clock signal to be output as a third digital video signal.
According to the sampling frequency converter of the above-discussed aspect of the present invention, the rate conversion of the digital video signal is enabled without providing an analog PLL circuit for generating a clock which is synchronized with a horizontal synchronous signal.
A video signal processor according to another aspect of the present invention comprises: an A/D converter circuit for sampling an analog video signal on a first clock signal having a first frequency, to be converted into a first digital video signal; a synchronous signal separation means for separating a first synchronous signal from the analog video signal; a first clock generation means for generating the first clock signal from the first synchronous signal; and a sampling frequency converter for interpolating the first digital video signal to be converted into a second digital video signal, and outputting the second digital video signal on the basis of a second clock signal having a second frequency. The sampling frequency converter comprises: a first digital-digital conversionmeans for interpolating the first digital video signal to calculate a second digital video signal, a length of one horizontal period and a sampling frequency of which signal are the same as those of the first digital video signal and an effective pixel period in one horizontal period of which signal is N times (N greater than 0) as long as that of the first digital video signal, and converting the first digital video signal into the second digital video signal to be output on the basis of the first clock signal; a second clock generation means for generating a second clock signal having a second frequency which is one-Nth as high as that of the first clock signal; and a storage means for retaining the second digital video signal as well as reading the retained second digital video signal on the second clock signal to be output as a third digital video signal.
According to the video signal processor of the above-discussed aspect of the present invention, the rate conversion of the digital video signal is enabled without providing outside an analog PLL circuit for generating a clock which is synchronized with a horizontal synchronous signal, whereby the circuit scale is reduced and the integration of the LSI is easily performed.
According to a video signal processor of another aspect of the present invention, a video signal processor discussed above further comprises: a multiplication means for multiplying the second clock signal to generate a third clock signal having a third frequency; a division means for dividing the third clock signal to generate a fourth clock signal having a fourth frequency; and a second digital-digital conversion means for converting the third digital video signal into a fourth digital video signal on the basis of the fourth clock signal.
According to the video signal processor of the above-discussed aspect of the present invention, the rate conversion of the digital video signal is enabled without providing outside an analog PLL circuit for generating a clock which is synchronized with one frame, whereby the circuit scale is reduced and the integration of the LSI is easily performed.
According to the video signal processor of another aspect of the present invention, the video signal processor of an above-discussed aspect further comprises a synchronization comparison means for comparing a phase of the first synchronous signal with a phase of a second synchronous signal which is generated from the second clock signal. The storage means comprises: a first frame storage means for retaining the second digital video signal in frame units as well as reading the retained second digital video signal in frame units on the basis of the second clock signal to be output as a fourth digital video signal; a second frame storage means for retaining the second digital video signal in frame units as well as reading the retained second digital video signal in frame units on the basis of the second clock signal to be output as a fifth digital video signal; and a switching means for receiving the fourth digital video signal and the fifth digital video signal, and alternately switching between the fourth digital video signal and the fifth digital video signal to be output as the third digital video signal. The synchronous comparison means outputs a switch signal which instructs the switching means to output either the fourth digital video signal or fifth digital video signal as the third digital video signal repeatedly twice when it detects that the phase of the first synchronous signal has gotten ahead of the phase of the second synchronous signal, and outputs a switch signal which instructs the switching means to eliminate one frame of either the fourth digital video signal or fifth digital video signal when it detects that the phase of the second synchronous signal has gotten ahead of the phase of the first synchronous signal, to the switching means, and the switching means outputs one of the fourth digital video signal and the fifth digital video signal as the third digital video signal, in accordance with the switch signal.
According to the video signal processor of the above-discussed aspect of the present invention, the occurrence of noises on a screen can be avoided even when non-standard television signals are input.
A sampling frequency conversion method according to another aspect of the present invention comprises: a digital-digital conversion step of receiving a first digital video signal which has been sampled on a first clock signal having a first frequency, interpolating the first digital video signal to calculate a second digital video signal, a length of one horizontal period and a sampling frequency of which signal are the same as those of the first digital video signal and an effective pixel period in one horizontal period of which signal is N times (N greater than 0) as long as that of the first digital video signal, and converting the first digital video signal into the second digital video signal to be output on the basis of the first clock signal; a clock generation step of generating a second clock signal having a second frequency which is one-Nth as high as that of the first clock signal; and a storage step of retaining the second digital video signal as well as reading the retained second digital video signal on the second clock signal to be output as a third digital video signal.
According to the sampling frequency conversion method of the above-discussed aspect of the present invention, the sampling frequency converter which enables the rate conversion of the digital video signal can be constituted, without providing an analog PLL circuit for generating a clock which is synchronized with a horizontal synchronous signal.
A video signal processing method according to another aspect of the present invention comprises: an A/D conversion step of sampling an analog video signal on a first clock signal having a first frequency to be converted into a first digital video signal; a synchronous signal separation step of separating a first synchronous signal from the analog video signal; a first clock generation step of generating the first clock signal from the first synchronous signal; a first digital-digital conversion step of interpolating the first digital video signal to calculate a second digital video signal, a length of one horizontal period and a sampling frequency of which signal are the same as those of the first digital video signal and an effective pixel period in one horizontal period of which signal is N times (N greater than 0) as long as that of the first digital video signal, and converting the first digital video signal into the second digital video signal to be output on the basis of the first clock signal; a second clock generation step of generating a second clock signal having a second frequency which is one-Nth as high as that of the first clock signal; and a storage step of retaining the second digital video signal as well as reading the retained second digital video signal on the second clock signal to be output as a third digital video signal.
According to the video signal processing method of the above-discussed aspect of the present invention, the video signal processor which can perform the rate conversion of the digital video signal without providing outside an analog PLL circuit for generating a clock which is synchronized with a horizontal synchronous signal, has a reduced circuit scale, and easily performs the integration of the LSI can be constituted.
According to the video signal processing method of another aspect of the present invention, the video signal processing method of the above-discussed aspect further comprises: a multiplication step of multiplying the second clock signal to generate a third clock signal having a third frequency; a division step of dividing the third clock signal to generate a fourth clock signal having a fourth frequency; and a second digital-digital conversion step of converting the third digital video signal into a fourth digital video signal on the basis of the fourth clock signal.
According to the video signal processing method of the above-discussed aspect of the present invention, the rate conversion of the digital video signal is enabled without providing outside an analog PLL circuit for generating a clock which is synchronized with one frame, whereby the circuit scale is reduced and the integration of the LSI is easily performed.
According to the video signal processing method of another aspect of the present invention, the video signal processing method of an above-discussed aspect further comprises a synchronization comparison step of comparing a phase of the first synchronous signal with a phase of a second synchronous signal which is generated from the second clock signal. The storage step comprises: a first frame storage step of retaining the second digital video signal in frame units as well as reading the retained second digital video signal on the basis of the second clock signal in frame units to be output as a fourth digital video signal; a second frame storage step of retaining the second digital video signal in frame units as well as reading the retained second digital video signal on the basis of the second clock signal in frame units to be output as a fifth digital video signal; and a switching step of receiving the fourth digital video signal and the fifth digital video signal, and alternately switching between the fourth digital video signal and the fifth digital video signal to be output as the third digital video signal. The synchronization comparison step outputs a switch signal which instructs to output either the fourth digital video signal or the fifth digital video signal as the third digital video signal repeatedly twice when it is detected that the phase of the first synchronous signal has gotten ahead of the phase of the second synchronous signal, and outputs a switch signal which instructs to eliminate one frame of either the fourth digital video signal or fifth digital video signal when it is detected that the phase of the second synchronous signal has gotten ahead of the phase of the first synchronous signal. The switching step outputs one of the fourth digital video signal and the fifth digital video signal as the third digital video signal, in accordance with the switch signal.
According to the video signal processing method of the above-discussed aspect of the present invention, the occurrence of noises on a screen can be prevented even when non-standard television signal are input.

Sampling frequency converter, sampling frequency conversion method, video signal processor, and video signal processing method

Matsushita Electric Industrial Co., Ltd.


A pulse rate counting device includes: a short-term average value calculation unit for calculating an average interval of predetermined previous pulses; a fluctuation amount calculation device for calculating the amount of fluctuation on the basis of the difference between the average interval and an actual pulse wave interval; a search range determination unit for calculating the width of the search range, calculating an amount of displacement on the basis of a time change of the average interval, and determining as a search range a range including an appearance prediction value of the next detection point calculated from the average interval and indicated by the width of the search range from a starting point determined on the basis of the amount of displacement; and a pulse wave interval detection unit for detecting the detection point in the determined search range, and outputting a pulse wave interval.

1. Field of the Invention
The present invention relates to a heart rate counting device, and more specifically to a pulse rate counting device which obtains a pulse rate with high accuracy from unstable pulse wave data acquired during physical activity etc.
2. Description of the Related Art
Conventionally, a device for obtaining a pulse rate using a pulse wave sensor attached to the ear or finger of a user has become commercially practical as heart rate counting technology requiring smaller load for the user than electrocardiograph.
Pulse wave data is stable when the quantity of motion is small during walking etc. (refer to FIG. 1A), and can be used for detecting a pulse wave interval with high accuracy. However, the pulse wave data becomes unstable when the quantity of motion is large during running etc. (refer to FIG. 1B), and it is difficult to detect a pulse wave interval with high accuracy.
Therefore, in the conventional technology, a pulse rate is obtained using two sensors, that is, a pulse wave sensor and a physical activity sensor for detecting the physical activities as a physical activity signal using an acceleration sensor (for example, refer to the patent document 1) to solve the problem of unstable pulse waves caused by a large change in the pulse rate during physical activity.
However, in the conventional system, the physical activity sensor is required in addition to the pulse wave sensor, thereby causing the problem of increasing the load for a user in price and attaching operation.
Since there is less unstable pulse waves during resting or during moderate physical activity, the change in heart rate can be roughly classified into three levels, that is, a stable status, an increasing tendency, and a decreasing tendency, and the subsequent heart rate can be predicted depending on the current tendency.
During fast walking or running effective as aerobic exercise, there occurs more unstable pulse wave due to the physical activities, the displacement of a sensor, etc. Therefore, there occur various fluctuations such as repetitions of small changes in the waveform intervals in pulse waves, repetitions of increase and decrease in amplitude, etc., thereby causing the problem that it is difficult to detect a correct pulse only by determining an increasing tendency or decreasing tendency acquired from a simple average value of a previous measurement result.    [Patent Document 1] Japanese Published Patent Application No. H9-154825

Pulse rate counting device, pulse rate counting method, and record medium therefor


Techniques are provided for vectorizing Heapsort. A K-heap is used as the underlying data structure for indexing values being sorted. The K-heap is vectorized by storing values in a contiguous memory array containing a beginning-most side and end-most side. The vectorized Heapsort utilizes horizontal aggregation SIMD instructions for comparisons, shuffling, and moving data. Thus, the number of comparisons required in order to find the maximum or minimum key value within a single node of the K-heap is reduced resulting in faster retrieval operations.

There exists a wide variety of sequential sorting algorithms, which can be divided into comparison-based and non-comparison-based algorithms. Comparison-based algorithms compare elements being sorted directly to obtain their order. The most efficient algorithms of this class, e.g., Quicksort, Merge Sort, and Heapsort, achieve an average time complexity of O(n log n) and are considered among the fastest sorting algorithms. Non-comparison based sort algorithms use the full or parts of the elements' respective bitstrings and lookup tables to order the elements. Algorithms in this class, e.g., Radix sort, Pigeonhole sort, Bucket sort, can achieve time complexities of O(n); however, they are not practical for many datasets.
In many applications, such as databases and search engines, sorting accounts for a large fraction of an application's overall runtime. Hence, there is a strong incentive to optimize sorting algorithms.
Discussed herein are approaches for speeding up sorting algorithms by vectorizing them and utilizing horizontal aggregation SIMD instructions for comparisons and shuffling or moving data.
The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section

This patent is subject to a terminal disclaimer.

Method for vectorizing heapsort using horizontal aggregation SIMD instructions


The invention relates to a knee-joint prosthesis with a hydraulic damping cylinder (1) for regulating the swing phase control and stance phase stabilization, and with an electronic control for a force field acting on the hydraulic fluid of the damping cylinder (1), the viscosity of the hydraulic fluid being able to be changed by the force field. The object of the present invention is to make available a knee-joint prosthesis whose electronic control has a high degree of safety and a minimal power consumption. According to the invention, the object is achieved by the fact that an actuating member (6, 7, 9, 12) is provided which generates a permanent force field and acts on the hydraulic fluid with an existing force field which is weakened or strengthened by the electronically controlled force field.

The invention relates to a knee-joint prosthesis with a hydraulic damping cylinder as set forth in the preamble of claim 1. The damping properties of a hydraulic cylinder for use in a prosthetic knee can be designed to be controllable in order to take account of the different resistance demands in the swing phase and the stance phase. One possibility of adaptation lies in electronic control via electrical actuating members which either change the current conditions or affect the viscosity properties of the fluid. A change in current conditions can be effected via a regulator valve, and a change in viscosity properties can be effected by acting, for example, on magnetorheological fluids.
As regards changing the viscosity properties of a fluid, it is known from the prior art for an actuating member, as a function of the phase of movement, to change the viscosity of the fluid by application of a magnetic field, with a high resistance and consequently a high viscosity being necessary in particular in the stance phase. Since the stance phase generally lasts longer than the swing phase, a relatively high current is always needed to safely permit standing.
Starting from this prior art, the object of the invention is to make available a knee-joint prosthesis which can be controlled with lower power consumption and which additionally guarantees increased safety in the event of the control system failing.
According to the invention, this object is achieved by a knee-joint prosthesis with the features of claim 1.
Advantageous embodiments and developments of the invention are set out in the dependent claims.
By means of an actuating member which generates a permanent force field and acts on the hydraulic fluid with an existing force field which is weakened or strengthened by the electronically controlled force field, only a low current need be applied for the swing phase in order to weaken the existing force field via the electronically controlled force field or to increase stance safety by means of an electronically controlled force field correspondingly differently oriented. In the event of a failure of the electronic control system, the stance stability of the prosthesis wearer is thus further guaranteed and a movement possibility, albeit a limited one, remains. In addition, the maintenance intervals for the knee-joint prosthesis can be extended, since overall there is a lower power consumption.
One embodiment of the invention involves a premagnetized actuating member which acts on a magnetorheological hydraulic fluid with a magnetic field.
In order to provide a constant magnetic field, the actuating member advantageously has a permanent magnet whose magnetic field is strengthened or weakened via a suitably arranged magnet coil to which voltage is applied.
As an alternative to this, provision is made for the force field to be an electrical field and for the hydraulic fluid to be an electrorheological fluid, the actuating member having electrodes made of an electret.
A particularly compact construction of the knee-joint prosthesis and of the damping device is obtained if the actuating member is located inside a piston or is integrated in the latter, which piston moves in the damping cylinder so that no additional structural space is needed to accommodate the actuating member. In a development of the magnetorheological variant, provision is made for the damping cylinder to be made of a ferromagnetic material in order to achieve a higher degree of integration.
In a further development, provision is made for a passage for the movement of the hydraulic fluid to be present between the inside wall of the cylinder and the hydraulic piston, so that the cylinder wall forms part of the magnetic circuit or the field excitation closed by the piston, the embedded permanent magnet or electrets via the passage and the cylinder. The passage is advantageously designed as an annular gap so that leakage takes place around the piston.
As an alternative to this, a passage for the movement of the magnetorheological or electrorheological fluid is formed inside the piston, so that the magnetic circuit or the field closes inside the piston and there changes the viscosity of the fluid flowing through. In this embodiment, it is not necessary for the cylinder to be made of a ferromagnetic material. The passage can be designed as a bore, channel or annular gap with diamagnetic bridges for magnetorheological fluids, in which case a plurality of bores or channels can also be formed inside the piston or at the piston edge.
An advantageous form of energy supply to the actuating member consists of a feed line through the piston rod, by which means the energy can be fed in a very stable manner and immediately to the magnet coil or the electrodes inside the piston.
In another embodiment of the invention, it is provided that the cylinder volumes which can be changed by the hydraulic piston are connected via a connecting line or leakage line and the actuating member acts on the magnetorheological or electrorheological fluid in the leakage line or connecting line with a field or changes the existing field in the line. Such an arrangement involves a relatively low outlay in construction terms and can be realized with conventional hydraulic means and field-generating elements.
The invention is explained in more detail below on the basis of illustrative embodiments. Identical reference numbers in different figures designate identical structural elements.

Knee-joint prosthesis with a hydraulic damping cylinder


An attachment system for tissue apposition or manipulation and a method of attaching a suture to a tissue for apposition or manipulation of the tissue are provided. The system includes an attachment device including a body having a proximal portion and a distal portion. The attachment device further includes a tissue attachment portion operably connected to the distal portion wherein the tissue attachment portion has a shape that is maintained throughout a tissue apposition procedure. The attachment device also includes a suture operably connected to the body and having an unconnected proximal end and a retaining structure at the proximal portion of the body. The retaining structure configured to releasably mate with a complementary retaining structure on a stylet.

Tissue perforations in the walls of internal organs and vessels may occur naturally may be formed intentionally or unintentionally. Numerous medical devices and methods have been developed to close the perforations and to allow the tissue to heal. In some procedures, it is desirable to retract tissue for further manipulation. For example, a fold may be created in the stomach that results in a gastric reduction by first placing an anchor through the stomach wall and tensioning the anchor so that the stomach wall invaginates. The gastric fold created may than be held in place with another anchor.
Devices currently used to close perforations and to hold tissues in position include clips, staples, anchors, sutures, adhesives and the like. The devices may be deployed using minimally invasive techniques, for example using endoscopic or laproscopic systems. For many tissue perforations, accessing the site and approximating the tissue to close the perforation requires complex and time consuming procedures. In some situations, the perforation may be larger than can be treated with a clip to hold the tissue together. For some perforations, the placement of the medical device at the proper site may be difficult. The delivery may be difficult due to engagement of the device within the delivery system, for example the device may be prematurely deployed or the placement may not allow proper apposition of the perforated tissue for healing. Some devices may be long enough to extend through the tissue, but uncontrolled insertion may lead to inadvertent puncturing of tissues due to the device extending too far. Some medical devices may not allow for repositioning of the device at the perforation site when the initial placement is not correct.
What is needed in the art is a medical device for repairing tissue perforations and for tensioning or holding tissues that is readily deployable at the tissue site, with controlled insertion and being repositionable to provide for proper tissue apposition. The medical device should also provide for apposition of large tissue perforations.

Attachment device for tissue approximation and retraction


Aspects of the present invention concern compositions that induce and/or improve an immune response to hepatitis C virus (HCV). Methods of making and using compositions that include epitopes of the HCV E2 structural protein involved in promoting or inhibiting neutralization of HCV are provided.

More than 70% of the estimated 170 million people worldwide who are infected with hepatitis C virus (HCV) develop chronic infection. Chronic HCV infections can lead to chronic liver disease, cirrhosis, and hepatocellular carcinoma. Chronic HCV infection is the leading indication for liver transplantation in the United States (Alter, H. J. et al. 2000 Semin Liver Dis 20:17-35). Antiviral treatment of HCV is now successful in about half of the cases, but it is expensive, requires long-term treatment, and is associated with serious side effects. There is no vaccine currently available for the prevention of HCV infection.
HCV is a positive-sense RNA virus belonging to the Flaviviridae family. It encodes a single polyprotein of ≈3,000 aa. Through the action of a combination of host and viral proteases, the polyprotein is cleaved into structural proteins (core, E1, E2, and p7) and nonstructural proteins (NS2-NS5B). The two envelope glycoproteins, E1 and E2, are believed to form heterodimers/oligomers on the surface of HCV particles that participate in the process of cell entry (Bartosch, B. et al, 2003 J Exp Med 197:633-642).
The mechanisms that govern the clinical outcomes of HCV infection are not well understood. Whereas cellular immune responses have been considered essential for controlling viral infection (Thimme, R. et al. 2003 Hepatology 37:1472-1474), the role of the humoral immune response remains to be defined. Increasing evidence demonstrates that neutralizing antibodies are present in patients with chronic hepatitis C (Bartosch, B. et al. 2003 Proc Natl Acad Sci USA 100:14199-14204; Meunier, J. C. et al. 2005 Proc Natl Acad Sci USA 102:4560-4565), and that epitopes located within the E2 protein are important for HCV neutralization (Farci, P. et al. 1996 Proc Natl Acad Sci USA 93:15394-15399; Triyatni, M. et al. 2002 Virology 298:124-132; Hsu, M. et al. 2003 Proc Natl Acad Sci USA 100:7271-7276; Logvinoff, C. et al. 2004 Proc Natl Acad Sci USA 101:10149-10154; Owsianka, A. et al. 2005 J Virol 79:11095-11104; Tarr, A. W. et al. 2006 Hepatology 43:592-601; Brown, R. J. et al. 2007 J Gen Virol 88:458-469; Schofield, D. J. et al. 2005 Hepatology 42:1055-1062; Eren, R. et al. 2006 J Viral 80:2654-2664).
Recent data in chimpanzees has shown that an experimental Ig preparation made from anti-HCV-positive plasma (HCIGIV) prevents HCV infection when the preparation is mixed with a virus inoculum ex vivo before infusion (Yu, M. W. et al. 2004 Proc Natl Acad Sci USA 101:7705-7710). Unfortunately, the in vivo efficacy of HCIGIV in both chimpanzees and humans has been disappointing. For example, two clinical studies failed to show that anti-HCV Ig preparations could decrease HCV RNA levels or prevent recurrent infections after liver transplantation (Davis, G. L. et al. 2005 Liver Transpl 11:941-949, Schiano, T. D. et al. 2006 Liver Transpl 12:1381-1389). The need for more treatments for HCV infection is manifest.

The United States of America, as Represented by the Secretary of the Department of Health and Human Services


A Braille writing device capable of processing information, comprises a motherboard (10) including a plurality of Braille cells (11) arranged in rows and columns, each cell consists of six dot-shaped recesses or pinholes, a sub-board (20) is configured to be inserted into a flute (12) being provided at each of left and right margins of the motherboard and moveable along the flute, a plurality of marks (13) are provided on an outer surface of the flutes (12), and a detent member (30) is formed between each two of the marks (13) in the inner side of the flute (12) and configured to prevent the moveable sub-board from being moved during writing. A Braille information processor (40) is fixed on a concave formed on the backside of the motherboard (10), comprising a circuit board (41), a central processing unit (42), a plurality of Braille trigger switch groups (44) each of which consists of six trigger switches (43), and an infrared transmitter (45). The Braille information processor can be coupled to a PDA or computer.

The blind including sightless and asthenopic persons are the weakest handicapped persons and need education to improve their life abilities. Conventional educations designed for the blind do not provide any effective methods to aim at the asthenopic persons having limited sight. Thus, those asthenopic persons have to learn Braille like those blinds who are totally sightless. Recently, some special education methods in view of asthenopic persons are desirable and those asthenopic persons are encouraged to use their limited sight to learn normal characters, instead of Braille, using magnifying glasses, cable television system with magnifying function, telescopes and special reading glasses or the like. However, since it is quite easy to feel tired to use eyes for reading, appropriate reading methods and devices are needed.
Braille is a type of symbols each of which consists of six projected dots. The basic structure of the international standard Braille consists of six projected dots (). When writing, a sheet of Braille paper is attached to a Braille plate on which circular doted-recesses are formed and using a Braille stylus to press the corresponding points of the recesses to form projections on the paper. When reading, the paper should be reversed. If any error is found, the correction of the error is time-cost and the process of the correction is complicated. A conventional Braille plate consists of a top board and a bottom board which are hinged with each other on one side. A sheet of Braille paper between the two boards is "written" with a Braille stylus through rectangular openings formed on the top board and circular recesses formed on the bottom board to form projections on the sheet of paper. Those projections arranged in light of the Braille rules can be touched by hands for reading. Such Braille writing device is costly. And, it is very hard to fix the paper on the device.
On the other hand, listening is the best choice for the blind to "read". However, none of the Braille writing devices is able to provide such functions like processing the input Braille and outputting the input Braille by speaking. Recently, computers and palmtops called PDA are widely used in our life so that it is possible to incorporating the electronic technology and computer technology into a Braille writing device.

Shenzhen Wang Ling Science and Technology Development Co., Ltd.


A stencil printer operable in a duplex print mode of the present invention prints an image on one side of a sheet and then prints another image on the other side of the same sheet. The printer includes at least one print drum and at least one press roller facing the print drum for pressing the sheet against the print drum. When the press roller is used to press the other side of the sheet against the print drum, the press roller is implemented as an elastic body provided with a fluorine compound layer on the surface thereof.

1. Field of the Invention
The present invention relates to a printer, e.g., a stencil printer constructed to transfer ink to a sheet-like recording medium via a master or perforated stencil wrapped around a print drum. More particularly, the present invention relates to the structure of a press roller, which is included in a printer operable in a duplex print mode, for pressing a sheet against a print drum in contact with an image printed on the sheet.
2. Description of the Background Art
A digital stencil printer, extensively used today as a simple printer, includes a thermal head on which fine heating elements are arranged in an array. While a thermosensitive stencil is conveyed, the heating elements are selectively energized in accordance with image data in contact with the stencil for thereby perforating, or cutting, the stencil with heat. After the perforated stencil, i.e., a master has been wrapped around a porous print drum, a press roller or similar pressing means presses a sheet or sheet-like recording medium against the print drum with the result that ink is transferred from the print drum to the sheet via the master, printing an image on the sheet. Various conveying members joining in sheet conveyance, including rollers, belts and pressing members, are arranged on a path extending from a sheet feeding section to a sheet discharging section via a printing section, so that a sheet is conveyed while sequentially contacting such conveying members. It is to be noted that the members, joining in sheet conveyance, include both of conveying members and members that simply steer a sheet in contact therewith.
A current trend in the stencil printers art is toward duplex print mode operation that prints images on both sides of a sheet for reducing the consumption of sheets as well as a space for storage. It has been customary to produce a duplex print by feeding a sheet from a sheet feeding section via a print position to print an image on one side of the sheet, turning the resulting one-sided sheet by hand, and again feeding the one-sided sheet via the print position to print an image on the other side of the sheet. This procedure, however, forces the operator of the printer to turn the one-sided sheet and again set it in the sheet feeding section or neatly position a stack of one-sided sheets, resulting in time- and labor consuming work.
Further, because ink on the one-sided sheet, carrying an image on one or front side thereof, is still wet just after printing, the rollers and press roller disfigure the image if immediately pressed against the sheet for printing an image on the other or reverse side of the same sheet. In light of this, printing on the other side of the sheet has heretofore been effected on the elapse of several hours or more. Particularly, when the image on the front side includes a solid portion, printing on the reverse side has customarily been effected next day because it takes a longer period of time for the solid portion to be dried.
As stated above, the duplex print mode has a problem that a long drying time must be provided between printing on the front side of a sheet and printing on the reverse side of the same sheet, and a problem that the same sheet must be repeatedly passed through the print position two times. Consequently, the duplex print mode needs a net printing time two times longer than a net printing time necessary for a simplex print mode.
To solve the above problem, Japanese Patent Laid-Open Publication No. 2002-103768, for example, proposes a stencil printer operable in the duplex print mode and including a first print drum and a second print drum positioned downstream of the first print drum in the direction of sheet conveyance. First and second pressing means respectively face the first and second print drums via a sheet conveyance path. After the first pressing means has been pressed against the first print drum, the second pressing means is pressed against the second print drum, thereby producing a duplex print.
Japanese Patent Laid-Open Publication No. 9-95033, for example, discloses a stencil printer operable in a duplex print mode and using a single divided master formed with a first and a second image to be respectively transferred to one side and the other side of a sheet. In the duplex print mode, a first press roller presses a sheet against a print drum via the master wrapped around the print drum to thereby print a first image one side of a sheet. Subsequently, the resulting one-sided sheet is again fed by biasing means, so that a second press roller prints a second image on the other side of the sheet.
With either one of the prior art schemes described above, it is possible to produce a duplex print by passing a sheet only one time for thereby substantially halving the printing time necessary for duplex print mode operation to complete.
However, the problem with the schemes taught in Laid-Open Publication Nos. 2002-103768 and 9-95033 is that when an image is to be formed on the other side of a sheet carrying an image on one side thereof, ink deposited on the one side is transferred to the press roller and then transferred to the other side of the next sheet when an image is to be printed on one side of the next sheet, resulting in so-called offset. More specifically, in a stencil printer using emulsion ink, a certain drying time is necessary for ink to be fixed on a sheet. To obviate the retransfer of ink from the press roller to the reverse side of the next sheet, Japanese Patent Laid-Open Publication No. 2002-219849, for example, proposes to form fine projections on the circumference of a press roller included in a downstream printing section.
The press roller disclosed in Laid-Open Publication No. 2002-219849 may be applied to either one of the schemes taught in Laid-Open Publication Nos. 2002-103768 and 9-95033. We, however, experimentally found that when spherical grains substantially identical in shape were so arranged as to form a smooth surface, as shown in FIG. 11(B) of Laid-Open Publication No. 2002-219849, the total area of the grains to contact the image surface of a sheet was not so different from a plane, failing to contribute to the obviation of smearing ascribable to ink retransfer. Even a configuration shown in FIG. 11(C) of the above document increased the area to contact the image surface of a sheet.
While reducing the area over which the press roller contacts the image surface of a sheet may effectively obviate smearing mentioned above, this scheme makes the tips of the portions of the press roller contacting the image area sharp and causes them to penetrate the sheet or even the master via the sheet. The contact area cannot therefore be reduced beyond a certain limit.
We conducted a series of experiments to determine, when a press roller presses one surface of a sheet, carrying an image on the one surface, to print an image on the other surface in the duplex print mode, a time interval after the printing on the one surface that reduces smearing ascribable to retransferred ink. The experiments showed that smearing ascribable to retransferred ink could be almost obviated when the time interval between the printing on the one surface and the printing on the other surface was 5 seconds or more. In practice, however, the time interval should be 3 seconds or less in order to make the most of the merits of a stencil printer.
On the other hand, sheet conveying processes include one that discharges a sheet carrying an image transferred from a print drum, one that again feeds a sheet, carrying an image thereon, in order to print a multicolor image on one side of the sheet, and one that turns a sheet, carrying an image on one side thereof, and again feeds it for producing a duplex print. A sheet is therefore conveyed while sequentially contacting most of members arranged on various paths and joining in sheet conveyance. It follows that reducing the deposition of ink on the press roller or similar rotatable pressing member cannot accurately protect images from smearing.
Technologies relating to the present invention are also disclosed in, e.g., Japanese Patent Laid-Open Publication No. 5-70010.