A book-like fixture and method for assembly of a plurality of multi-layered ceramic packages including a substrate and a cap. The fixture has a baseplate, a removable tray, an alignment plate for precisely aligning the caps with the substrates, a compression plate, and a plurality of compression devices designed to uniformly distribute compressive force on the plurality of packages. The fixture is preferably adapted for use of removable trays conforming to the Joint Electronics Design Engineering Council Tray Standard. The compression devices preferably have a spring, preferably a detachable leaf spring, and a compression plate placed over each cap. The structure of the fixture allows replacement of the springs and other modifications to allow assembly of multi-layered ceramic packages of differing dimensions. The structure of the fixture also allows stacking one on top of another.

Multi-layered ceramic (MLC) packages, specifically single chip modules (SCM) and multi-chip modules (MCM), are used in a number of applications. Such modules generally consist of a substrate and a cap that must be bonded together to a specified dimensional tolerance, usually using adhesives that are heat-cured. Industry competitiveness demands low-cost, high-volume, high-yield assembly of such modules.
Stamped fixtures, typically of stainless steel, such as "Auer Boats" manufactured by AUER Precision Company, Inc. of Mesa, Ariz., are prevalent in the industry as fixtures used for such assembly. Such fixtures incur high initial tooling costs, however, for even minor variations in MLC package design, and are not compatible with conveyor equipment designed to work with a tool set complying with the Joint Electronic Device Engineering Council (JEDEC) Standards. Use of typical stamped fixtures requires additional handling which is labor intensive and also results in yield loss due to handling defects. In addition, loose cap-to-substrate alignment tolerances decrease the usable substrate area.
The configuration of a typical stamped stainless steel fixture of the prior art for assembly of an MLC package is shown in FIG. 1. A typical MLC package consists of a substrate 100 and cap 102, the substrate having mounted upon it an integrated circuit chip 104 and having pins 106 extending from the bottom of the substrate.
To assemble the MLC package, the substrate containing the chip is set in a base 110 aligned by guides 111. An alignment plate 112 is aligned on the substrate using alignment pins 114 attached to the alignment plate, each pin comprising a spacer portion 116 and a pin portion 118 adapted to fit in hole 119 in base 110. Substrate 100 and chip 104 are typically prepared with chip underfill applied around and wicking under chip 104, thermally conductive paste applied on top of chip 104, and seal adhesive placed on the surface of substrate 100 where cap 102 will contact the substrate. The underfill protects the chip-substrate interface and prevents oxidation of the solder used to attach the chip pins to the substrate. The thermally conductive paste creates a conductive pathway from the top of the chip to the cap, so that heat may be dissipated away from the chip through the cap. Finally, the seal adhesive bonds around the perimeter of the cap to seal the area inside the cap to protect it from oxidation. Cap 102 is then placed on top of the substrate so prepared.
Pressure is then applied to press the substrate against the cap, using clip 120. Clip 120 consists of a bridge 122 having tabs 124 punched therethrough, and prongs 126 attached at either end of bridge 122. Each prong 126 has an upper stop tab 128, a lower stop tab 130, and an angled end 132. Tabs 124 are spaced to hold the ends of leaf spring 134 therebetween. The compression force, usually 2 to 10 pounds, imparted by the spring serves to "squish" the paste layer on top of the chip to conform it to the space between the chip and the cap, thus assuring a good conductive connection and cap seal.
The clip 120 is inserted manually by squeezing the prongs 126 slightly toward one another and inserting them through alignment plate holes 136 and baseplate holes 138 thus compressing spring 134. Once the prongs 126 have completely penetrated holes 138, the prongs are allowed to spring back away from one another, and the lower tabs 130 hold the prongs into place to prevent the force of compressed spring 134 from retracting the clip. Upper tabs 128 prevent the prongs from being inserted too far into holes 138 such that too much compressive force would be imparted on cap 102. The MLC package so assembled is then put into an oven to heat cure the seal adhesive. Cured modules then must be removed manually from the fixture.
A typical stamped stainless steel fixture of the prior art might accommodate anywhere from one to ten such MLC packages, but typically no more than five on a single base with a single corresponding alignment plate. One clip for each MLC package on the base must be inserted and removed manually, however, for each MLC package. Manual removal of the clip requires compressing prongs 126 toward each other a sufficient amount to clear tabs 128 and 130 through holes 138 and 136. This operation usually requires handling the clip at ends 132, sometimes causing finger damage to pins 106 if mishandled.
Another difficulty associated with the stamped fixtures of the prior art is that they cannot be stacked on top of one another. Because the oven curing step may often take three to four hours, the ability to maximize the number of fixtures in a single oven can dramatically increase throughput without requiring investment in additional ovens.
In addition, because the fixtures of the prior art are manufactured by a stamped metal process having inherently loose tolerances, the alignment between the base and the substrate may not meet the tight tolerances of customer specifications. As the industry strives to ever increase the amount of performance per size of unit, more of the substrate closer to the edges is typically used for functional design, and thus close tolerances of cap-to-substrate alignment have become more critical.
Finally, such fixtures must be re-tooled to accommodate even minor variations in MLC package width, length, or height, a serious drawback considering the common height variation in MLC packaging. In addition, a fixture is needed that uses industry standard JEDEC trays.
It is an object of the present invention, therefore, to provide a fixture flexible enough to handle the variations in package dimensions from product line to product line, capable of high-volume production with high yield conforming to precise dimensional tolerances, and strong enough to withstand constant manufacturing use.

Method for assembling a multi-layered ceramic package

International Business Machines Corporation


Systems and methods providing user privacy in association with decentralized ledger technology are disclosed. Improved methods and systems for access control are disclosed wherein an access request can be received at the distributed ledger to fetch a data file without disclosing requester identity, that can verify the access request at the decentralized ledger as a legitimate request or as a malicious/faulty request, and can assist a user of a legitimate request to access the data and deny access to malicious/faulty requests that are compatible with a decentralized ledger environment.

Identity management is the foundation of many other applications. As more applications are built on top of decentralized ledger, it is necessary to develop a compatible identity management system. Because of the nature of decentralization, privacy becomes a big concern, i.e., the user cannot safely disclose his/her identity information on the decentralized ledger. The proposed invention proposed a framework together with concrete building components to solve this problem.
A decentralized ledger is an electronic data structure that is maintained by multiple participants, without relying on any centralized party, and various applications can be developed on top of it. This relates to what is commonly referred to as "Blockchain" technology. Decentralized ledgers have various applications related to and requiring data processing and storage. The decentralization feature, however, raises several security concerns since many established security and user privacy protection mechanisms are not compatible with a decentralized environment. As many users and applications need to interact with data, it is important to provide privacy management and control mechanisms that are fully compatible with this decentralized ledger environment while preserving identification privacy for its users.
Identity management is the foundation of many applications. In the decentralized environment, there is a lack of centralized, trusted party to manage all the identity management activities, and the most common operation of identity claim verification has to be done in a decentralized manner. This brings a big concern on privacy, because if all identity related information is stored in plain text, every participant of the decentralized application can learn the information. On the other hand, if identity information is protected using ordinary encryption, it will prevent the participants from processing it. Therefore, there is an urgent need to develop a privacy friendly decentralized ledger based identity management system.
What is needed are improved methods and systems for party identification and access control wherein an access request can be received at the distributed ledger to fetch a data file without disclosing requester identity.

Privacy friendly decentralized ledger based identity management system and methods


A sliding element, in particular a piston ring, preferably made of cast iron or steel, has a coating which has a plurality of layers of CrN (14) and a-C:H:Me coatings (16) alternately. In a method for coating the sliding element, in particular a piston ring, preferably made of cast iron or steel, a plurality of layers of CrN and a-C:H:Me coatings are applied alternately.

1. Technical Field
The invention relates to a sliding element, in particular a piston ring, having a coating, and to a method for coating a sliding element.
2. Related Art
In many technical applications, sliding elements are in sliding contact with sliding contact surfaces. The combination of a piston ring with a cylinder liner can be seen as a typical application. Provided that the cylinders or cylinder liners are made, for example, of aluminium-silicon alloys, which is the case in particular with Otto engines, DLC (diamond-like carbon) coating systems have proved to be successful as regards wear and friction power. However, the known DLC coating systems are in need of improvement as regards lifetime and their usability in diesel or turbocharged Otto engines with conventionally iron-based cylinder liners. Because of the significantly higher cylinder pressures and in particular in combination with direct injection, an increased proportion of mixed friction occurs. The definitive reason for the lack of suitability of DLC coating systems for such situations is seen as being the conventionally small layer thickness of less than 5 μm.
DE 10 2005 063 123 B3 discloses a DLC coating with a running-in layer. With regard to greater layer thicknesses, there are also known PVD coatings, in particular based on CrN, which have layer thicknesses in the range of from 10 to 30 μm. Although these result in an improved lifetime, the friction power and wear resistance, in particular in conditions of insufficient lubrication, and the scuff resistance are impaired. By contrast, DLC coating systems offer the advantage, owing to their amorphous structure, that they exhibit a large degree of chemical inactivity with metal surfaces and accordingly an extremely low adhesive tendency towards the sliding contact surface.
This is true, for example, of the coating according to DE 10 2008 016 864 B3, which has on the inside a metal-containing amorphous carbon layer and on the outside a metal-free amorphous carbon layer.

Sliding element and method for coating a sliding element


In an approach to determining one or more logical breaks in a digital text, a computer determines a reading speed of a user for a current reading session of a digital text and an available time for the current reading session for the user. The computer then determines, based, at least in part, on the reading speed and the available time, a user range in the digital text for the current reading session, and then one or more possible logical breaks within the user range. The computer further determines a first logical break, based on the determined user range, of the one or more possible logical breaks for the current reading session.

The present invention relates generally to the field of data processing, and more particularly to specific processing of a digital text document in order to improve a user experience.
A chapter in a book is a main division, indicating where an author has chosen to separate one section of a story from another. Those reading the book may use chapters as a logical break in order to pace his or her reading. However, the author's choice in where to place a chapter break may not always align with the time available that one has for a particular session of reading. With the culture shift from printed to digital material, and the increase in the use of e-readers and the availability of electronic books ("e-books"), people are reading more frequently, and in more locations.

Determining logical breaks in a digital text

International Business Machines Corporation


An interferometric measuring device for measuring surface characteristics, shapes, distances, and distance variations, e.g., vibrations, in particular in narrow, hollow spaces, of measuring objects, having a probe part and an optical fiber. Surface dimensions are able to be measured, even in very fine bore holes, in that, in a measuring head, at the free end of the probe part approaching the measuring object, the optical fiber projects out and is itself designed as a measuring fiber for illuminating a point of measurement and for picking up measuring light coming from this measuring point.

The present invention is directed to an interferometric measuring device having a probe part and an optical fiber. The measuring device is for measuring surface characteristics, shapes, distances, and distance variations, e.g., vibrations, in particular in narrow, hollow spaces of measuring objects.
An interferometric measuring device of this kind is known from the German Published Patent Application No. 198 08 273. In the case of this known measuring device, the interferometric measuring system utilizes coherence multiplexing to split the measuring device""s optical system into two subsystems, one designated as modulation interferometer and one as a probe part. The result is a probe part which is easy to manipulate and which has a measuring head that facilitates measurements in relatively long, narrow bore holes. The measuring device is designed for a multiple-wavelength interferometry, so that an expansion of the measuring range is achieved. However, there are bore holes whose dimensions are so narrow that even a measuring head of this kind can no longer be used.
German Published Patent Application No. 198 19 762 proposes another interferometric measuring device of this type which includes various space-saving measuring probes for the measuring system.
European Published Patent Application No. 0 126 475 describes a method and a device for the contact-free measurement of actual positions and/or of rough surface profiles, which is based on the concept of a multiple-wavelength heterodyne interferometer and, as a light source, includes one or more lasers. By employing phase analysis, the heterodyne technique makes it possible to substantially suppress measuring errors.
The underlying object of the present invention is to provide an interferometric measuring device of the type indicated at the outset which will enable measurements to be performed as accurately as possible, even in still narrower hollow spaces, such as those smaller than one millimeter, as occur when working with injection nozzles.
According to the present invention, in a measuring head, at the free end of the probe part approaching the measuring object, the optical fiber projects out and is itself designed as a measuring fiber for illuminating a point of measurement and for picking up measuring light coming from this measuring point. The measuring fiber, whose diameter is within the range of less than 100 xcexcm, for example, may be driven with its free end into very thin bore holes and illuminate the surface area to be measured and, from there, receive light, in order to retransmit it to an evaluation device that is known per se and that works, in particular, in accordance with the principle of phase analysis.
In this context, to achieve an exact illumination, as well as precise pick-up of the measuring light, the measures are advantageous which provide for designing the free end region of the measuring fiber to illuminate a point of measurement and to pick up the measuring light in dependence upon the measuring task.
Other advantageous embodiments for attaining a precise measuring result provide for polishing the free end region, providing it with a diaphragm, configuring it as a lens or prism, treating it against disturbing reflected light, beveling, reflection-coating, or antireflection-coating it, or providing it with a combination of these measures.
For purposes of beam shaping or beam guidance, the unattached end region of the measuring fiber is finely worked in that it is provided with a drop of adhesive and/or is roughened.
A further advantageous measure for the transmission and analysis of light provides for the measuring fiber to be a monomode fiber.
Various possible embodiments are derived from an interferometer design which corresponds to a classic interferometer, a white light interferometer, or to a heterodyne interferometer. In white light interferometry, a broadband, short-coherent light source, such as a superluminescent diode or similar light source, is utilized, and the maximum of the interference contrast is analyzed, as is known per se.
Interferometers of the mentioned type are also described in greater detail in the publications mentioned at the outset. In general, classic interferometers are likewise widely used.
To advantageously expand the measuring range, i.e., increase the range of unambiguity, for example, the interferometer is designed as a multiple-wavelength interferometer. With respect to procedural details, reference is likewise made to the related art mentioned at the outset.
If provision is made in the probe part for a fiber section to be preconnected to the measuring fiber and for the interface between the fiber section and the measuring fiber to be utilized as a beam-splitter surface for forming a reflected reference wave and a transmitted measuring wave, then the measuring fibers are easily interchangeable, and the measuring head may be equipped for different measuring tasks. At the same time, the interface is expediently utilized for the interferometric design, so that, for example, no additional reflecting surface is required for the reference beam. In this context, a beneficial measure for a simple design is for the connection between the measuring fiber and the fiber section to be designed as a fiber coupler.
Simple manipulation of the measuring device is also advantageously provided in an embodiment where, for purposes of illumination, a short-coherent light source is positioned in a modulation interferometer that is remote from the probe part and linked thereto via an optical fiber, or is positioned in the probe part, which is then linked via an optical fiber to a remote demodulation interferometer, and where the coherence length of the light source is shorter than one half of the difference between a path length of a reference wave and a path length of a measuring wave.
In partitioning the design into the probe part and the demodulation interferometer, it is expedient, in this context, for the light from the light source to be channeled via an additional optical fiber and a fiber beam splitter into the fiber section and, once the point of measurement is illuminated, out of this, into the optical fiber.
If provision is also made for the probe part to have a fixed probe part and, rotationally mounted therein, a probe part which is rotatable with the measuring head, then an all-around measurement may be performed in simple fashion.

Short coherence fiber probe interferometric measuring device


A camera module having a flash that is provided therein. The flash may be an LED light source. The LED may come in a package that is generally rectangular, with the exception that one corner is flattened. The camera module includes a housing that receives the light source, an image sensor, and a lens. The housing includes mating features that receive the LED package, those features including a flattened corner so that the LED package can only be received within the housing when it is properly oriented. The housing also includes electrical terminals for connection to the LED that include springs. When the LED package is properly oriented and received within the housing, contact pads on the LED package and the electrical terminals on the housing are pressed together against the resilient force of the spring.

Digital camera modules are currently being incorporated into a variety of electronic devices. Such camera hosting devices include, but are not omitted to, cellular telephones, personal data assistants (PDAs), and computers. The demand for digital camera modules continues to grow as the ability to incorporate the camera modules into host devices expands. Typically, host device manufacturers prefer small camera modules that minimally affect the host device design. Therefore, one design goal of digital camera modules is to reduce the number of design constraints that camera modules impart on the host device design.
Typically, conventional camera module designs present several design and manufacturing challenges to the hosting devices in which they are incorporated. For example, when a conventional camera module is incorporated into a host device, a separate flash system (e.g., light element, actuator, control circuitry, etc.) also has to be incorporated into the host device. Consequently, the host device design (e.g., physical layout, circuitry, etc.) is affected by both the camera module and the flash system. Furthermore, camera module manufacturers typically do not provide flash systems and, therefore, it is up to the host device manufacturer to do so. This is frustrating for host device manufacturers because host device manufacturers are typically not specialized in camera module technology. Of course, image quality can suffer when a camera module is not matched with the proper flash system.
Accordingly, an improved digital camera module with an incorporated flash system is needed.


Compact electro-optic modulator with integrated voltage-switched transparent conductive oxide capacitor with one-dimensional silicon photonic crystal nano-cavity.

The ever-increasing demand to process, store, and exchange information creates an unceasing driving force for high bandwidth, energy-efficient photonic technologies. In recent years, the need to develop photonic devices with extremely high energy efficiency to atto-joule/bit has been recognized. Silicon photonics has the potential to transform future optical interconnect systems by reducing the energy consumption and enhancing the bandwidth of existing electronic systems by orders of magnitude using Complementary Metal-Oxide-Semiconductor (CMOS) compatible fabrication processes. In addition to the application to optical interconnects, silicon photonic devices can also operate logic gates to conduct certain types of optical computation. However, the performance of silicon photonic devices is still limited by the diffraction limit and the relatively weak plasma dispersion effect. Although silicon has a relatively high refractive index, it can only shrink the wavelength inside the silicon waveguide proportionally to the scale of λ/n, roughly to 400˜600 nm. Further reduction of the device footprint requires exploiting surface plasmon polaritons, which are bound waves at the interface between a metal and a dielectric. The extremely strong light confinement of metal-insulator-metal waveguides has led to the demonstration of ultra-compact and high bandwidth plasmonic electro-optic (E-O) modulators. However, plasmonic structures and devices are very lossy and can only carry information over a very short distance, and hybrid plasmonic-dielectric waveguide integration must be used for real optical interconnects, which increases the complexity of design and fabrication.
A further constraint of silicon photonic devices is that the plasma dispersion effect induced by free carrier injection or depletion can only induce moderate refractive index perturbation. For example, for a typical depletion-based silicon photonic modulator with a moderate doping level of 2.5×1018 cm−3 in its active region, when completely depleted, the refractive index only changes by 0.06%. As a result, current Mach-Zehnder interferometer (MZI) silicon modulators require a long device length up to hundreds of micrometers to several millimeters to accumulate sufficient phase modulation. The large device footprint also leads to a large energy consumption of pico-joule/bit, which cannot meet the requirement of future photonic interconnects application. Compared with MZI modulators, resonator-based E-O modulators occupy a much smaller footprint and achieve significantly higher energy efficiency. To date, various ultra-compact silicon micro-ring resonators, micro-disk resonators and photonic crystal nano-cavities have been used in optical interconnect systems, achieving high performance in modulation speed, compactness, and energy efficiency. However, resonator-based modulators have an intrinsic trade-off between energy efficiency and optical bandwidth. For practical devices, thermal control with integrated heaters and temperature sensors are often used to obtain stable performance, but with the sacrifice of additional energy consumption and footprint.
In addition, existing transparent conductive oxide-based E-O modulators based on straight silicon waveguide or plasmonic slot waveguide use electrically-induced optical absorption from the integrated MOS capacitor. The phase change induced by the real part of the permittivity of transparent conductive oxide materials, although accompanied by the imaginary part of the index change, does not contribute to any E-O modulation. Therefore, a relatively long modulation length (a few microns) is required to induce sufficient optical absorption. Moreover, these modulators require the presence of metal gates for strong plasmonic light confinement and electronic signal conductance, which introduces relatively high optical loss even at the transparent state.
Accordingly, there is a need in the art for E-O modulators which are energy efficient and have increased bandwidth while occupying a smaller footprint.

Nano-cavity modulator device and method of manufacture and use


A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.

1. Technical Field
This invention generally relates to systems modeling and development, and more specifically relates to hardware simulators with a hardware accelerator.
2. Background Art
Today's integrated circuit (IC) systems are often a highly complex combination of hardware and software that must function within very specific constraints in order for the computer system to operate as designed. Computer aided design tools allow IC designers to model a new design and to model how the new design will interact with and respond to existing systems or components prior to production. Modeling with computer aided design tools can significantly accelerate the design process and reduce the time to market for IC systems, which can be a competitive advantage. This modeling is typically accomplished by using simulation systems that model hardware function and performance in software, hardware-accelerated software simulation systems, or hardware emulation systems that use a combination of software and hardware to model a circuit or system design.
Simulation has long been a preferred method for verification of logical correctness of complex electronic circuit designs. Simulation is broadly defined as the creation of a model which, if subjected to arbitrary stimuli, responds in a similar way to the manufactured and tested design. More specifically, the term "simulation" is typically used when such a model is implemented as a computer program. In contrast, the term "emulation" is the creation of a model using programmable (also known as reconfigurable) logic or field-programmable gate array (FPGA) devices. Simulation/Emulation saves a significant amount of time and financial resources because it enables designers to detect design errors before the expensive manufacturing process is undertaken. Moreover, the design process itself can be viewed as a sequence of steps where the initial general concept of a new product is being turned into a detailed blueprint. Detecting errors at the early stages of this process also saves time and engineering resources. The primary advantage of emulation over simulation is speed. However emulation typically lacks access to internal nodes needed for detailed analysis. Simulation acceleration uses special a purpose hardware accelerator to speed up the model evaluation. Simulation acceleration has the advantages of software simulation and increased speed.
The typical IC design process describes the IC logic in Very high speed IC Hardware Description Language (VHDL) or some other type of hardware description language, feeds VHDL into a simulation environment, and loads a netlist which describes the interconnection topology of the design into a hardware accelerator. The hardware accelerator typically is a chassis full of software programmable logic such as an array of multiplexers. Software evaluates the netlist and partitions it so that the programmable logic can be programmed to simulate the topology of the proposed design. The designer then interacts with the hardware accelerator to simulate and evaluate the operation of the proposed IC design.
Referring now to FIG. 1, a typical simulation environment 100 includes a workstation 110, and a hardware accelerator 120. A communication link 130 provides an intercommunication link between the work station and the hardware accelerator 120. In this prior art simulation system 100, the simulation model 140 in the hardware accelerator 120 has separate partitions for latches 150 and combinational logic 160. Workstation 110 may be any type of microprocessor-based computer or computer system known to those skilled in the art. Hardware accelerator 120 is a large-scale hardware configuration implemented with programmable logic such as multiplexer arrays or some other type of custom hardware. Some hardware accelerators 120 include a function unit array 170. This system is capable of using the function unit array 170 to emulate many different types of computer system hardware components including, for example, combinational logic, latches and memory devices.
FIG. 2 shows another simulation system believed to be in the prior art. This simulation environment 200 includes a workstation 110, and a hardware accelerator 120. A communication link 130 provides an intercommunication link between the work station and the hardware accelerator 120. In this prior art simulation system 200 the hardware accelerator 120 has a simulation model 140 that has a single partition 210 for latches and combinational logic. The hardware accelerator 110 includes a function unit array 170 as described above with reference to FIG. 1. This system relies on virtual logic to provide the benefits of a latch only cycle and a combinational only cycle, which decreases system performance.
In an IC design, there are memory elements such as latches and arrays, and combinatorial logic elements such as "AND" and "OR" gates. In a simple design, the output values from the latches propagate through the combinational logic. The output of the combinational logic becomes the input of the latches that are updated on the next "clock". A simulation cycle would consist of the following sequence:latches→combinational logic - - - (clock)→latches
During simulation, developers want to look at the values of both latches and combinational logic, and the general expectation is that the values of the combinational logic correspond to the output of the latches, i.e. the state of the design before the "clock". If developers were to only read signals, the simulator would only have to stop the simulator after the combinational logic. A simulation cycle would consist of the following sequence:
"user control (read, clock)" --> "update latches" --> "updatecombinational" --> "user control".However, developers also have the option of changing or sticking the values of latches and signals when the simulation is continued after a user control stop. If the developer changes a latch or signal and then issues a "clock" command, the expectation is that the latches will be updated based on the changes that the user made. Therefore, in this case, a simulation cycle would consist of the following sequence:
"user control (read/alter/stick, clock)" --> "update combinational" -->"update latches" --> "update combinational" --> "user control".In the last example, the combinational logic is evaluated twice (before and after the user control). The combinational logic is updated before the user control so that the developer would have access to the updated signal values. The update combinational after user control can be deferred and only done on user control cycles when the user actually alters signals.
In more complex designs, there can be memory elements within the combinational logic such as transparent latches. Transparent latches act like latches in that they can retain their previous cycle's value, but they act like combinational logic in that their output is updated right away, without waiting for a clock. Because of these memory elements, there may be a feedback loop within the combinational logic such that the output will be different after updating the combinational logic several times. Depending on the runtime environment, the simulator may be able to avoid ever having to update the combinational logic more than once, or this feedback behavior may be accepted/expected by the users.
In some prior art simulators like the Awan simulator developed by IBM, the model contains two separate partitions (a combinational partition followed by a latch partition). The functions of update latches and update combinational are achieved by setting the simulator's start and end address to the partition's start and end address. So to clock a large number of cycles at a time, the start and end address would be set so that both partitions are run, and the simulation would stop after evaluating the latch partition. This made it simple to avoid multiple combinational logic evaluations as described above.
In some simulators, including those that employ more parallelism to increase speed, there are no separate partitions for latches and combinational logic. Within the model, the latches are placed before the combinational logic that they feed, so that one or more full cycles would end after evaluating the combinational logic. Whenever the simulator needs to update either the latches or the combinational logic, both are actually evaluated. So the simulator cannot perform an update latches and an update combinational by running the separate models in the separate partitions for latches and combinational logic.

Hardware accelerator with a single partition for latches and combinational logic


An aqueous solution containing a polymer dispersant and a metal compound, and an aqueous solution of a reducing agent, are joined together and uniformly mixed while being subjected to reduction reaction to give metal microparticles, in a thin film fluid formed between processing surfaces arranged to be opposite to each other so as to be able to approach to and separate from each other, at least one of which rotates relative to the other, by using a reaction apparatus of uniform stirring and mixing the above aqueous solutions.

Patent Document 1: JP-A H11-080647    Patent Document 2: JP-A 2000-239853    Patent Document 3: JP-A 2006-321948    Patent Document 4: JP-A 2004-33901
Generally, metal nanoparticles have a very high ratio of the particle surface thereof to the total number of atoms and have physical properties different from those of bulk metal. Particularly, metal nanoparticles having a diameter of 10 nm or less exhibit a high catalyst function and undergo a reduction in melting point, and in the case of gold, silver, copper, or the like show a physical property of having absorption at a specific wavelength, called plasmon absorption in the visible light range.
A solution having such metal microparticles dispersed uniformly therein, that is, a metal colloidal solution, has been utilized in various fields by making use of its characteristics. For example, the metal colloidal solution can be utilized as a colorant in paints etc. (JP-A H11-080647/Patent Document 1) and in production of a thin film having metallic luster (JP-A 2000-239853/Patent Document 2) or can be utilized in an electroconductive paste with which electrodes and circuits in chip parts, plasma display panels etc. are made significantly fine and formed or printed with high density, high accuracy, and high reliability.
Among previous methods for producing metal colloidal solutions, there are those methods carried out with a batch reaction apparatus as shown in JP-A 2006-321948 (Patent Document 3) or with a general micro-reactor as shown in JP-A 2004-33901 (Patent Document 4). In the batch type method, however, it is generally difficult to control the temperature in the batch reaction apparatus and it is thus inevitably difficult to conduct a uniform reaction. In addition, the concentration control is also difficult because complete uniform stirring is necessary. Further, a long reaction time is also necessary, and thus it is extremely difficult to control all the reaction conditions. Although there are many advantages in micro-devices and system when the general micro-reactor is used, there are actually many problems as follows: when the diameter of a micro-flow path is decreased, the pressure loss is inversely proportional to the fourth root of the flow path, that is, a fluid-sending pressure that is so high as to make it hard to obtain a pump for sending a fluid is necessary; in the case of a reaction involving separation, the phenomenon of clogging a flow path with products and the closure of a micro-flow path by foam generated by the reaction; the reaction is expected fundamentally by the diffusion speed of molecules, and thus the micro-spaces are not effective or applicable to every reaction, and in practice, successful ones should be selected by testing the reaction in a trial-and-error system.
Scaling up has been coped with a method of increasing the number of microreactors, that is numbering up, but the number of microreactors which can be stuck is limited to several dozen, thus inherently aiming exclusively at products of high value, and the increase in the number of devices leads to an increase the absolute number of failure causes, and when the problem of clogging actually occurs, it can be very difficult to detect a problem site such as failure site.

Method for producing metal microparticles, and metal colloidal solution containing the metal microparticles


A rechargeable battery is provided having positive and negative plates formed of flexible substantially solid sheets. The plates are each pasted with an active material and separated by a light weight absorbent separator. A light weight casing provides structural support for the plates and encases the battery's components. The battery is preferably a recombinant lead acid battery with its plates being formed of lead foil sheets. The casing is preferably reinforced to maintain a constant spacing between the plates by a plurality of support pins extending between upper and lower casing members through the plate sheets. Plates may be stacked one above another to provide a plurality of cells. In separate aspects of the invention, a battery may be formed having a polar plate that has positive and negative surfaces on its opposite sides. In another separate aspect of the invention a novel terminal arrangement is provided.

With the increasing popularity of portable electronic appliances, there have been extensive efforts to reduce the size and weight of their various components. In many circumstances, one of the principle limitations to such size reductions is the energy storage device. Accordingly, there have been ongoing efforts to develop energy storage devices that are lighter in weight, smaller in size and capable of storing the maximum electrical charge per unit weight and/or size. In order to remain economical during extended uses, it is important that the batteries be rechargeable.
In recent years there have been substantial improvements in rechargeable battery technology; however, existing battery designs remain quite heavy in comparison with other electrical components. There are numerous batteries on the market, with the different designs using a wide variety of chemistries. The two most popular types of batteries that are used to power portable electronic devices are nickel cadmium (NICAD) batteries and sealed lead acid batteries.
The most common and probably the best known battery construction is lead acid. Substantially all the existing automotive battery designs are lead acid based. One advantage of lead acid batteries is that they have very repeatable power delivery characteristics and may be recharged and overcharged repeatedly with minimal damage to the cells. Additionally, the power curve is consistent enough that the charge remaining in a cell at any given time can be relatively accurately predicted by merely measuring the cell's potential. Thus, a user can be easily warned well in advance of a loss of power. The major drawback of lead acid batteries is that they tend to be heavy; traditionally, large lead grids are used to form the battery's plates and the cells are flooded with an acid based electrolyte. Typically, the grids are structurally self supporting which increases their weight. Additionally, in order to ensure a reliable electrolytic seal between adjacent cells, in practice it is generally necessary to fomm a gas tight seal about each cell.
A significant improvement to the traditional lead acid battery design is the recombinant battery. The recombinant lead acid battery differs from its predecessors in that substantially all of the electrolyte is absorbed within the separator between adjacent plates and/or an active paste applied directly to the plates. Gases evolved during operation or charging are not normally vented into the atmosphere, but rather are induced to recombine within the battery. With such an arrangement, no free acid is available, which allows the battery to be sealed and maintenance free. The elimination of free acid also provides a safer battery design.
Several refinements have been made to recombinant lead acid batteries. For example, U.S. Pat. No. 3,862,861 describes a significantly improved lead acid battery design, which uses flexible, non-self-supporting grids within a recombinant lead acid battery design. Specifically, the flexible grids are fabricated from a very high purity lead and are separated only by a microporous fiberglass material that retains the electrolyte within the separator itself. Such an arrangement improves the energy storage per unit weight characteristics of lead acid batteries since the separator structure is significantly lightened.
U.S. Pat. Nos. 4,383,011, 4,525,438 and 4,659,636 all describe alternative recombinant lead acid battery designs. The '636 design stacks a plurality of flattened cells in order to produce a somewhat flattened battery unit. Unfortunately, even these relatively improved lead acid battery designs only match the energy density (watt-hours of energy stored per unit weight of battery) and the packaging density (watt-hours of energy stored per unit volume of battery) of NICAD cells.
An important technical requirement of lead acid batteries is that the spacing between plates must be maintained at a constant distance. As is well known in the art, if the plates of a lead acid battery are not sufficiently constrained, the plates will expand and the battery degrades relatively quickly. Accordingly, the casing must be sufficiently strong to prevent separation of the plates under the influence of the considerable forces that can act on the plates during a charge/discharge cycle.
Two areas of prior art recombinant batteries are particularly bulky and/or heavy. The first is the electrodes which are typically fabricated from lead grids and the second is the casing structure which is typically heavily reinforced. Prior art batteries, such as those described above, merely increase the thickness of the casing in order to prevent deformation of their casings and/or electrodes. However, such external support is disadvantageous since it is quite bulky. Therefore, there is a need for an improved light weight battery plate support structure.
Although nickel-cadmium batteries tend to have slightly better energy and packaging density characteristics than conventional lead acid batteries, they also have numerous drawbacks for powering portable electronic units. Among the most noticeable is that their power delivery curves vary a great deal depending upon their charging and recharging history. Thus, they are unsuitable for use in devices that must be recharged at varying intervals. Accordingly, there is a need for an improved battery design that has improved energy density and packaging density characteristics.


High foot mobility footwear, including a sole and an upper that define separated front seats to hold respectively toes or groups of toes, where the sole includes a plurality of portions resting on the ground, substantially contiguous to each other along the plantar surface.

Certain types of footwear are known and commercially available that reproduce the natural shape of the foot, in order to ensure better articular mobility especially of the toes and to give more comfort during the action of walking, giving the user the sensation of walking on bare feet while ensuring the necessary protection.
Such a type of footwear is described in the international patent application WO2007/038487 of the same applicant. This patent application describes a shoe in which the front part defines multiple portions independent of each other made of flexible material to accommodate the toes; such portions involve both the upper and the sole of the shoe.
These shoes have a non-slip sole which, although being made with a thin enough thickness and elastic material like rubber and similar, may not allow for a desired yielding during the execution of foot movements. The shoe, therefore, is extremely soft and yielding in the upper part, namely in the portion that covers the dorsum of the foot, while being stiffer at the sole, as the sole itself must ensure, however, a cushioning and protective effect of the plantar surface of the foot, that is, the surface of the foot that supports the weight of the user.
Furthermore, the sole of the above-mentioned known footwear does not guarantee, in particularly hard use conditions, as in the execution of extreme sports or similar, a sufficient non-slip grip on more difficult surfaces, such as those that are very slippery or inclined.


An integrated circuit, a mobile phone and a display are provided with the integrated circuit. The integrated circuit includes a substrate, a data distributor and a data driver distributed on the substrate. A power line trace gap is provided within the data distributor; a first data line connected to the data driver and to the data distributor; and a first power line connected to the data driver and passing through the power line trace gap.

An integrated circuit, also known as a microcircuit, microchip or chip, is a microelectronic device or component. An integrated circuit is a micro-structure having required circuit functions, formed by using a certain process to interconnect the elements and circuits required in a circuit on one or several substrates.
The integrated circuit can be applied to devices in the field of military, communication, remote control, and the like. Taking an integrated circuit applied to a mobile phone as an example, as shown in FIG. 1, a data distributor 2 (DEMUX, also referred to as a demultiplexer), a data driver 3, and a power line 4 and a data line 5 connected to the data driver 3 are integrated on the substrate 1. Here, the data line 5 is used to transmit data signals. The data distributor 2 is used to distribute the signals transmitted by the data line 5 into multipath signals, so that it is possible to ensure fewer data lines connected to the data driver 3. The power line 4 is used to transfer power to supply power to the data driver 3.
Generally, after the power line 4 is drawn out of the data driver 3, it is necessary to make the power line bypass the data distributor 2, so as to extend to other areas of the substrate 1 to supply power to devices in other areas. However, this causes the parasitic capacitance across the data line 5 to be large, so that the transmission of the data signal can be blocked, which results in delay of the data signal.

Integrated circuit, mobile phone and display

Kunshan New Flat Panel Display Technology Center Co., Ltd.

Kunshan Go-Visionox Opto-Electronics Co., Ltd.


An aspect of the present invention is directed to a method for forming a mirror-reflecting film on a waveguide in an optical wiring board, characterized in that a multilayer film, in which a base, a metal layer and an adhesive layer are layered in this order, is used, and the metal layer is transferred and bonded to an inclined face for mirror-reflecting film formation provided on the waveguide, with the adhesive layer of the multilayer film intervening. The present invention provides a method which, when forming a mirror-reflecting film on a waveguide in an optical wiring board, enables inexpensive and easy formation of the mirror-reflecting film, using the smallest quantity of metal possible and employing comparatively simple facilities and techniques.

Optical wiring boards, which are printed boards incorporating optical waveguides, are attracting attention as a means of resolving such persistent problems in various information processing equipment as high-frequency noise accompanying faster signals and inadequate transmission bandwidth.
In such optical wiring boards, mirror-reflecting films are formed on optical waveguides in order to bend light at desired angles, as for example when light is output from or, conversely, input to the board surface. As the method of forming such films, for example a method such as that of Non-patent Document 1 is known. This method comprises a process of forming a mirror-shape inclined face, and a process of forming a reflecting film on this surface. A summary of the method is explained as follows, referring to the figures.
In FIG. 1, (a) through (i) are schematic diagrams for explaining an example of a method of fabricating an optical wiring board, in which a mirror-reflecting film is formed on an optical waveguide, and show a representative method of fabricating a flexible-type optical wiring board.
First, a flexible electric board comprising a metal layer 1 of copper foil or similar and an insulating layer 2 formed from polyimide resin or similar is prepared ((a) of FIG. 1). On the face of the insulating layer 2 is formed a first cladding layer 3 ((b) of FIG. 1).
As the material of the cladding layer 3, resin having the desired transparency at the wavelength of the propagating light, for example 850 nm, is used. Various forms may be used, including liquid, semi-solidified film, or a UV-hardening material or thermosetting material. When a liquid is used, for example a spin coating method is applied, or in the case of a film, for example a vacuum lamination method is applied, and the liquid or the film is deposited on the insulating layer 2 and is hardened as necessary.
Next, a core layer 4 is formed ((c) and (d) of FIG. 1). The core layer 4 is a portion which confines light and enables propagation of light through total reflection at the interface with the cladding layer 3, and is normally patterned to a width of order several μm to several hundred μm.
As the constituent material of the core layer 4, a resin having a higher refractive index than the cladding layer 3, and having the desired transparency at the wavelength of the propagating light, for example 850 nm, is used. The form may be liquid or a semi-solidified film, and in general, a material which has UV hardening properties and can be patterned by UV lithography is employed.
The core layer 4 is generally formed by steps in which, after the entire surface is covered with film similarly to the cladding layer 3, masking is performed to mask unnecessary portions, and UV irradiation is then performed to harden only the necessary portions ((c) of FIG. 1), followed by a step in which the unnecessary portions are washed away (development) ((d) of FIG. 1).
Next, an inclined face 5 for mirror film formation is formed ((e) of FIG. 1). As the technique, for example a method employing a dicing blade, a method employing a router blade, or a method employing a laser may be used, in which normally the inclined face 5 is formed at an angle of approximately 45°. In the step immediately after formation of the inclined face 5, it may occur that the surface smoothness is insufficient for use as a mirror; in such cases, a varnish obtained by diluting the waveguide material may be applied to the machined face to improve the smoothness.
Next, the mirror-reflecting film 6 is formed on the inclined face 5 ((f) of FIG. 1). In forming the mirror-reflecting film 6, normally a vacuum process such as vacuum evaporation or sputtering is adopted. As the material of the mirror-reflecting film 6, of course a material with superior reflectivity in the wavelength region of the light to be transmitted is selected, but in consideration of reliability and cost, a material with a balance of properties is selected. For example, in Non-patent Document 1, Au (gold) is used.
Next, the core layer 4 in which the mirror-reflecting film 6 has been formed on the inclined face 5 is covered with a second cladding layer 7 ((g) of FIG. 1). In forming the second cladding layer 7, in general, the same material as in the first cladding layer 3 is adopted. The technique is also similar; in the case of a liquid, for example a spin-coating method is used, and in the case of a film form, for example a vacuum lamination method can be used for the formation (film deposition), followed by hardening performed as necessary.
After forming the second cladding layer 7, a coverlay layer 8 is formed thereupon to protect the light transmission layer ((h) of FIG. 1). As the material of the coverlay layer 8, a polyimide resin, polyester resin, or similar is used, and is applied by a vacuum press method or lamination method, followed by heating at approximately 140 to 170° C. to harden an adhesive layer.
Finally, processes such as formation of through-holes, circuit patterning, and solder resist, as well as metal plating are performed to complete the surface layer circuit 9 ((i) of FIG. 1). At this time, micrometer-order positioning precision may be required for the pads for mounting optical elements, and in such cases, a method of high-precision pad formation using laser machining is adopted, as for example described in Patent Document 1.    Patent Document 1: Japanese Patent Application Laid-open No. 2007-086210    Non-patent Document 1: Matsushita Electric Works Technical Report, Vol. 54, No. 3, "Optical/Electric Composite Flexible Print Board" (issued September 2006)

Method for forming mirror-reflecting film in optical wiring board, and optical wiring board


A central processing unit, a read only memory, a random access memory, an oscillator for supplying a clock signal to the central processing unit, a peripheral circuit and a control circuit are provided. The control circuit supplies a first voltage to the central processing unit, the read only memory, the random access memory and the peripheral circuit in synchronization with rising/falling of the clock signal, and supplies a second voltage to the central processing unit with passage of predetermined time after the rising/falling of the clock signal. The first voltage enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to change their operations. The second voltage is lower than the first voltage, and enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to maintain their operations.

1. Field of the Invention
The present invention relates to a single chip microcomputer suitably used for an electronic device such as a video camera or the like operated at a plurality of speeds. More particularly, the invention relates to a single chip microcomputer capable of reducing power consumption.
2. Description of the Related Art
A conventional single chip microcomputer comprises two kinds of oscillators provided to generate high-speed and low-speed clock signals, respectively. During a high-speed operation, a central processing unit (referred to as a CPU, hereinafter) is operated by a high-speed clock signal. During a low-speed operation, the CPU is operated by a low-speed clock signal. FIG. 1 is a block diagram showing the constitution of such a conventional single chip microcomputer.
The conventional single chip microcomputer shown comprises first and second oscillators 103 and 104, to which power supply voltage Vdd is supplied from a power supply terminal. An oscillation frequency of the first oscillator 103 is set equal to, e.g., 20 MHz, while an oscillation frequency of the second oscillator 104 is set equal to, e.g., 32 kHz. In other words, the first oscillator 103 is designed for a high-speed clock signal, whereas the second oscillator 104 is designed for a low-speed clock signal.
The single chip microcomputer also comprises a selector 105 which is provided to select each of the clock signals G5 and G6 of the first and second oscillators 103 and 104, and output it as a clock signal G4 to a CPU 110. The microcomputer further comprises a random access memory (referred to as a RAM, hereinafter) 106, a read only memory (referred to as a ROM, hereinafter) 107, and a peripheral circuit 108. An I/O port 111 is also provided to transfer a signal with an external unit, and with the CPU 110 for transferring a signal with the CPU 110.
In addition, a control circuit 112 is provided to control an oscillation frequency of a clock signal inputted to the CPU 110 based on a switching signal A1 outputted therefrom The control circuit 112 outputs an oscillator control signal G1 to the first oscillator 103, where the control signal G1 is used to switch the operation of the first oscillator 103 between ON and OFF. The control circuit 112 outputs an oscillator control signal G2 to the Second oscillator 104, where the control signal G2 is used to switch the operation of the second oscillator 104 between ON and OFF. On the other hand, the clock signals G5 and G6 are inputted not only to the selector 105 but also to the control circuit 112. To the selector 105, the control circuit 112 outputs a clock selection signal G3 used to control the selection of the clock signals G5 and G6.
The power supply terminal directly supplies power supply voltage Vdd to the RAM 106, the ROM 107, the peripheral circuit 108, the CPU 110, the I/O port 111 and the control circuit 112.
In addition, a reset signal RST is inputted to each of the CPU 110 and the control circuit 112 to realize its initial state.
FIG. 2 is a timing chart showing an operation before/after the conventional single chip microcomputer is changed from a high-speed operation to a low-speed operation. In the conventional single chip microcomputer constructed in the foregoing manner, when an operating speed is changed from high-speed operation to low-speed operation, the CPU 110 transmits a high-level switching signal A1 to the control circuit 112 based on a program stored in the ROM 107. Then, upon having received the high-level switching signal A1, the control circuit 112 sets the level of an oscillator control signal G1 to be low by a specified timing. Accordingly, the operation of the first oscillator 103 is stopped. On the other hand, the level of an oscillator control signal C2 is always high, and the second oscillator 104 is in a constantly operated state. Thus, it is only the second oscillator 104 that is operated during a low-speed operation.
Therefore, in the conventional single chip microcomputer, since power consumed by the first oscillator 103 during the low-speed operation is 0, a charging/discharging current is reduced, bringing about a reduction in power consumption like that shown in FIG. 2.
However, there is a drawback inherent in such a conventional single chip microcomputer. Specifically, even if the charging/discharging current is reduced, no reduction occurs in an OFF leakage current caused to flow when a transistor in the chip is microstructured in dimension. Consequently, in a microstructuring process applied to the microcomputer requiring a high-speed operation, a leakage current component is increased, which makes it impossible to achieve low power consumption. If a requested operating speed is not so high, the OFF leakage current can be suppressed by setting high a threshold voltage Vt of the transistor, even when the transistor is microstructured. If a high-speed operation is requested, however, since a low threshold voltage Vt is necessary, power consumption during the low-speed operation is increased by the OFF leakage current when the transistor is microstructured.
Under these circumstances, regarding the microcomputer requiring the high-speed operation, one capable of reducing power consumption has been proposed (Japanese Patent Laid-open Application No. Sho. 60-10318). In the microcomputer described therein, two kinds of power supply voltages and clock signals are switched according to an operating speed, and power consumption is thereby reduced during the low-speed operation. The power supply voltages and the clock signals are simultaneously switched by a control circuit.
However, even in the conventional microcomputer described in Japanese Patent Laid-Open Application No. Sho. 60-10318, power consumption during the low-speed operation is still large, and there is a demand for a further reduction in power consumption.
It is an object of the present invention to provide a single chip microcomputer capable of reducing power consumption.
According to one aspect of the present invention, a single chip microcomputer comprises a central processing unit which stores a program executed by the central processing unit, a read only memory, a random access memory which holds data processed by the central processing unit, an oscillator which supplies a clock signal to the central processing unit, a peripheral circuit which transfers a signal to the central processing unit and receives a signal from the central processing unit, and a control circuit. The control circuit supplies a first voltage to the central processing unit, the read only memory, the random access memory and the peripheral circuit in synchronization with rising/falling of the clock signal. The control circuit supplies a second voltage to the central processing unit with passage of predetermined time after the rising/falling of the clock signal. The first voltage enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to change their operations. The second voltage is lower than the first voltage, and enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to maintain their operations.
According to the aspect of the present invention, a voltage supplied to each of the central processing unit, the read only memory, the random access memory and the peripheral circuit is set equal to one for enabling the respective units and circuits to be operated in synchronization with rising/falling of the clock signal. In other words, a voltage is set for enabling the respective units and circuits to change their operations. In addition, with passage of predetermined time after the rising/falling of the Clock signal, a voltage is reduced to one for enabling the respective units and circuits to maintain their operations. Accordingly, leakage current is reduced while the stable operation of each circuit is maintained. As a result, power consumption is reduced. Especially, when two kinds of high-speed and low-speed clock signals are used, a reduction in power consumption is considerable if the foregoing control is applied during a low-speed clock operation. Further, by limiting a circuit to receive the supply of a voltage for a fixed period to the RAM or its partial area, power consumption can be further reduced.
According to another aspect of the present invention, a single chip microcomputer comprises a central processing unit, a read only memory which stores a program executed by the central processing unit, a random access memory which holds data processed by the central processing unit, a first oscillator which supplies a first clock signal to the central processing unit, a second oscillator which supplies a second clock signal having a frequency lower than that of the first clock signal to the central processing units a clock selector which selects and supplies any one of the first and second clock signals to the central processing unit, and a peripheral circuit which transfers a signal to the central processing unit and receives a signal from the central processing unit. The single chip microcomputer further comprises a first step-down circuit which steps down a power supply voltage supplied to a power supply terminal to a first voltage, a second step-down circuit which steps down the power supply voltage to a second voltage, and a control circuit. The first voltage enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to be operated with the second clock signal. The second voltage is lower than the first voltage and enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to maintain their operations. The control circuit controls voltage supplied to the central processing unit, the read only memory, the random access memory and the peripheral circuit, and controls a clock signal supplied to the central processing unit in relation to the first and second clock signals.
The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters.

Single chip microcomputer with reduced channel leakage current during a stable low speed operation state


A wireless electronic device having first and second baseband processors is provided. In one suitable arrangement, radio-frequency power splitters and adjustable low noise amplifiers may be form in the receive paths. The use of power splitters allow signals associated with the first and second baseband processors to be received in parallel. In another suitable arrangement, radio-frequency switches are used in place of the power splitters. The states of the switches may be controlled using at least one of the first and second baseband processors. The use of switches instead of power splitters requires that wake periods associated with the first baseband processor and wake periods associated with the second baseband processor are non-overlapping. To ensure minimal wake period collision, a wake period associated with the second baseband processor may be positioned at a midpoint between two successive wake periods associated with the first baseband processor.

This relates to electronic devices such as cellular telephones and, more particularly, to methods for coordinating signal reception across wireless integrated circuit boundaries.
Electronic devices such as cellular telephones contain wireless circuitry such as radio-frequency transceiver integrated circuits and associated wireless baseband integrated circuits. These wireless integrated circuits may be used in handling wireless voice and data communications during operation of an electronic device.
To minimize power consumption and extend battery life, it is generally desirable to place wireless integrated circuits in a low power sleep state when they are not being actively used. When a wireless integrated circuit is needed to handle a wireless communications task, the wireless integrated circuit can be awoken from its sleep state.
Challenges can arise in managing the sleep states and wake states of wireless integrated circuits in devices that contain multiple integrated circuits for handling different communications protocols. If care is not taken, resource conflicts can arise between the wireless integrated circuits that degrade performance.
It would therefore be desirable to be able to provide improved ways in which to coordinate the operation of wireless integrated circuits in an electronic device.

Methods for coordinated signal reception across integrated circuit boundaries


A method for wireless communication of a user equipment (UE) in a radio resource control (RRC) Inactive state, the method includes sending, by the UE, an RRC Connection Resume Request message to a base station, and transmitting, by the UE, a packet to the base station using one or more radio resources allocated by the base station, where the base station identifies the UE based on the RRC Connection Resume Request message, which includes a UE ID or a UE-specific preamble. Before the UE enters the RRC Inactive state, the base station sends a pre-configured random access configuration to the UE for transmitting the packet in a subsequent a random access procedure. The pre-configured random access configuration includes at least one of a pre-configured bandwidth part configuration, a plurality of access control parameters, the UE ID, and a time pattern for the random access procedure.

The 3rd Generation Partnership Project (3GPP) has introduced a new radio resource control (RRC) state: RRC Inactive state, for the next generation (e.g., 5G or new radio (NR)) wireless communication networks. RRC Inactive state aims to achieve power saving with acceptable access latency. When a user equipment (UE) is in RRC Inactive state, the next generation radio access network (e.g., 5G RAN) and the UE store the Access Stratum (AS) context (e.g., UE context) separately. In addition, while in RRC Inactive state, the UE does not have an RRC connection with the next generation radio access network (e.g., 5G RAN), although the next generation radio access network (e.g., 5G RAN) keeps a connection with the next generation core network (e.g., 5G CN) for the UE. Other characteristics of RRC Inactive state have been in development.
Thus, there is a need in the art for efficient packet delivery in RRC Inactive state to reduce signaling overhead, power consumption, and resource cost on both the UE side and the radio access network side.

Data packet delivery in RRC inactive state


A low-noise main bearing cap for an internal combustion engine is designed that includes a main bearing cap body, wherein the main bearing cap body is connected to an engine body main bearing seat. The main bearing cap body is provided with a vibration isolator A vibration isolation structure is provided between the main bearing cap body and the vibration isolator The main bearing cap body is connected with the vibration isolator through a connector The vibration isolation structure comprises an S-shaped structure and an oil film gap, and the vibration isolator is provided with an oil inlet passage which is communicated with the oil film gap. The present design solves the control problem of the main bearing vibration source caused by the main bearing load.

At present, the requirements for vibration and noise control of internal combustion engines are getting higher and higher, and the noise level of internal combustion engines has become an important index of internal combustion engine design. Noise sources of internal combustion engines comprise combustion noise, mechanical noise and aerodynamic noise. Combustion noise and mechanical noise are referred to as structural radiation noise, which is radiated through the structural surface of an internal combustion engine. The existing experimental results show that the noise generated by the engine body and its accessories accounts for 50˜70% of the total noise of the internal combustion engine. The main bearing load is one of the main excitation sources causing the vibration of the engine body structure and the radiation noise, and is the main contributor to the vibration of the engine support. Therefore, controlling the vibration caused by the main bearing load is one of the main ways to design the internal combustion engine with low vibration and low noise.
At present, the existing control methods for the transmission paths of the main bearing load or vibration of an internal combustion engine are mainly to improve structural rigidity by adding the rib structure or increasing the diaphragm thickness in the vicinity of the main bearing. The disadvantage of this approach is that it significantly increases the overall weight. At present, the control effect on vibration and noise of an internal combustion engine has reached the limit, and the main bearing load is still one of the main contributors to the radiation noise of the internal combustion engine structure.
At the same time, the related literature reports on the vibration and radiation noise control of the internal combustion engine structure have solved the main problems such as the improvement of a dynamic model of a crank-connecting rod mechanism, the optimization of a piston skirt profile, the optimization of bearing lubrication performance, the analysis of crankshaft bending-torsion coupling vibration, the optimization of a crankshaft three-dimensional vibration model, etc., but the main bearing load or its vibration control is not considered as the key point.
For crankshaft vibration control, the torsional vibration of a crankshaft is mainly controlled by installing a torsional vibration damper, or the axial vibration of a crankshaft is controlled by installing a longitudinal vibration damper, and the bending vibration of a crankshaft is indirectly controlled. However, the vibration of the main bearing is not effectively controlled by installing a torsional vibration damper or a longitudinal vibration damper, and sometimes it will be strengthened. Therefore, the current progress seldom involves the research of a vibration control method and mechanism of the main bearing of the internal combustion engine. Controlling the vibration of the main bearing of the internal combustion engine, and then the vibration transmitted to the engine body is a key problem that needs to be solved urgently at present.

Low-noise main bearing cap for internal combustion engine


A non-volatile memory comprises memory cells M arranged in a matrix (MB), word lines (W1 to Wn) for row selection, sub-bit lines (B: B12, B21, B22, B31), sub-column lines (C: C11, C12, C22), a column selection circuit 1, a bit line selection circuit 2, and a column line selection circuit 3. The word lines (W1 to Wn) are used as gates common to the rows of the memory cells M, a group of sub-bit lines B and sub-column lines C is selected by the column selection circuit 1, an even-numbered or odd-numbered sub-bit line B is selected from each group and connected to any one of main bit lines (B1, B2 and B3) by the bit line selection circuit 2, and an even-numbered or odd-numbered sub-column line (C) is selected from each group and connected to any one of main column lines (C1 and C2) by the column line selection circuit 3.

This invention relates to non-volatile memories, and more particularly to non-volatile memories having memory cells of floating gate type.
One previously proposed non-volatile memory is the erasable and programmable read only memory (EPROM) described in, for example, Japanese laid-open patent specification 3/34470.
FIG. 9 is a diagram of the above-mentioned non-volatile memory, which has connected therein a memory cell array 51, a row decoder 52, a column decoder 53, a column selection logic circuit 54, and a load circuit 55. FIG. 10 is a circuit diagram of the main parts of the memory cells, the load circuit 55 and the column selection logic circuit 54. FIG. 11 is a plan view of the memory cell array, and FIG. 12 is a perspective view of the memory cell corresponding to part of FIG. 11.
In this non-volatile memory, as shown in FIG. 12, aligned N type impurity-diffused layers 64 and 65 are formed on a silicon substrate 61 of, for example, P type, by ion implantation through the mask of a first polycrystalline silicon layer 63 which is formed on a first gate insulating film 62 on the substrate 61, and then a second gate insulating film 66 is formed over the substrate 61.
Thereafter, control gates 67 (which constitute the word lines) formed by strip-shaped second polycrystalline silicon layers are formed perpendicular to the impurity-diffused layers 64 and 65, and then the underlying second gate insulating film 66 and the first polycrystalline layer 63 are selectively etched away in a self-alignment manner through the mask of the control gates 67, so that floating gates formed by the first polycrystalline silicon layers 63 are built up on the substrate 61.
As shown in FIG. 11, the impurity-diffused layers 64 and 65 are alternately used as the bit lines and column lines, and channels are formed in the regions under the control gates 67 between the bit lines and the column lines, thus creating a large number of cells (M11, M12 . . . M33 . . .) for the achievement of a high-density integrated non-volatile memory.
The operation of the above non-volatile memory will now be described with reference to FIGS. 9 and 10.
When a word line Wn of, for example, the nth row is selected by an input row address to the row decoder 52, and when a column selection line Cn of, for example, the nth column is selected by an input column address to the column decoder 53, the word line Wn and the column selection line Cn are raised to a high level, and the other word lines and column selection lines of the other rows and columns stay at a low level.
At this time, transistors Q11, Q12 and Q13 connected to the column selection line Cn of the nth column are turned on, thus allowing a column line CLn to undergo discharge, and hence to be fixed to earth potential Vss. In addition, data paths are formed running from the odd and even bit lines, B1 and B2, to the odd and even data buses, DBL1 and DBL2, respectively. When the word line Wn of the nth row is selected, the memory cells (Q8 and Q9 as illustrated) connected to the word line Wn are selected.
At this time, if the memory cell Q8 is programmed to be logic "0", the memory cell Q8 remains in the off-state, and no signal is transmitted to the odd data bus DBL1. If the memory cell Q9 has no logic "0" written therein, or is programmed to be logic "1", the memory cell Q9 becomes in the on-state, and thus a current path is formed running from the even data bus DBL2 through the transistor Q13 to earth.
All the column lines and bit lines in the non-selected state are biased through transistors QS, Q6 and Q7 by a slightly higher voltage, Vcc, than the transition point of a sensing amplifier, not shown, connected to the odd and even data buses DBL1 and DBL2. This bias voltage prevents an unnecessarily large voltage change occurring when the bit lines which previously underwent discharge to drop to earth potential Vss are accessed.
Upon writing (programming), the word line Wn of the nth row and the column selection line Cn of the nth column are charged substantially to a program potential Vpp (>Vcc). When the memory cell Q8 is not programmed, the odd data bus DBL1 is at the low level. When the logic "0" is programmed in the memory cell Q9, the even data bus DBL is raised to the program potential Vpp as described above.
This non-volatile memory has the following problems when the number of word lines is increased for high-density integration.
Firstly, the wiring resistance of the N type impurity-diffused layer for the bit lines or column lines is increased in proportion to the number of word lines. In other words, the memory cell current flowing in the memory cell is limited by the parasitic resistance inserted in series with the source and drain of the memory cell. Therefore, upon reading of data, the current flowing from the data bus to the memory cell decreases, so that the time during which the data bus is subjected to discharge becomes long. As a result, the access time is increased, so that it is difficult to read data at a high speed.
Secondly, since the bit lines and column lines constituting the memory cell array are made of the N type impurity-diffused layer, the junction capacitance between the impurity-diffused layer and the silicon substrate is added as a parasitic capacitance, thus increasing the time of discharge through the bit lines and column lines which precedes the discharge through the data bus.
Thirdly, since the memory cell current is limited by the series resistance of the source and drain of the memory cell, it is difficult to assure the current for writing data in the memory cell. The writing current usually needs to be about 1 mA. Since the writing voltage is specified generally as 12.5.+-.0.5V, it is absolutely necessary that the total resistance of the resistance of the bit line and column line and the working resistance of the memory cell be 12.5 k.OMEGA. or below.
The sheet resistance of an N type impurity-diffused layer is usually 10 to 50 .OMEGA./.quadrature.. In addition, referring to FIG. 12, if the first polycrystalline silicon layer (floating gate) 63 and the second polycrystalline silicon layer (control gate) 67 are designed on the same rule, the resistance value of the N type impurity-diffused layers 64 and 65 per row is at least 20 .OMEGA., and thus the number of rows (=the number of word lines) cannot be increased to 625 or above because the total resistance of the impurity-diffused layers becomes about 12.5 k.OMEGA..
This means that when the number of rows is selected to be equal to that of columns in accordance with the structure of the typical memory cell array 51, it is difficult to realize a larger-capacity non-volatile memory using the above high-density memory cells than 256 kbits.
Moreover, when the memory cells are integrated at a high density, the numbers of bit lines and column lines are increased with the increase of the number of memory cells, and thus it is also necessary to increase the number of the output terminals of the peripheral circuits such as the column decoder 53 and the load circuit 55. Since in this non-volatile memory the arrangement pitch of the output terminals of the peripheral circuits is the same as that of the bit lines and column lines in the memory cell array 51, the output terminals of the peripheral circuits must also be considered to be integrated at a high density in accordance with the increase of the integration density of the memory cells. Therefore, it is very difficult to design the non-volatile memory.

High density nonvolatile memory and decoder of the same


An image forming apparatus includes image forming and sheet feeding mechanisms. The sheet feeding mechanism includes a bottom plate, a first roller, a separator including second and third rollers, and a sensor. The bottom plate loads sheets. The first roller feeds an uppermost sheet of the sheets loaded on the bottom plate. The separator separates the uppermost sheet from the other sheets when a plurality of sheets are fed by the first roller. The sensor is disposed between heads of the sheets loaded on the bottom plate and the separator and detects the uppermost sheet fed by the first roller. The image forming apparatus further includes a controller for driving the first roller to feed a next uppermost sheet loaded on the bottom plate when the sensor does not detect the next uppermost sheet when a tail portion of the previous sheet passes the separator.

1. Field of the Invention
The present invention relates to an image forming apparatus, an image forming method, and a sheet feeding apparatus, and more particularly to an image forming apparatus, an image forming method, and a sheet feeding apparatus capable of effectively feeding sheets.
2. Description of the Background Art
A background image forming apparatus, such as a copying machine, a printer, or a facsimile machine, generally includes a sheet feeding apparatus for feeding sheets one by one from a paper tray. The sheet feeding apparatus generally includes a mechanism for separating an uppermost sheet from the other sheets fed from the paper tray and feeding only the uppermost sheet when a plurality of sheets are fed from the paper tray. As one of the mechanism, a friction reverse roller method is known. The sheet feeding apparatus using the friction reverse roller method includes a feeding roller and a separating roller as the mechanism for separating the uppermost sheet from the other sheets fed from the paper tray and feeding only the uppermost sheet.
FIG. 1 illustrates a sheet feeding apparatus 20b which is one example of the sheet feeding apparatus using the friction reverse roller method. The sheet feeding apparatus 20b includes a bottom plate 9b, a pick-up roller 4b, a feeding roller 2b, a separating roller 3b, a grip roller 5b, and a sensor 6b.
The bottom plate 9b is disposed in a paper tray 1b of the image forming apparatus and loads sheets S. The pick-up roller 4b feeds the sheets S loaded on the bottom plate 9b from the paper tray 1b. The feeding roller 2b rotates in a sheet conveyance direction. The separating roller 3b faces and pressingly contacts the feeding roller 2b and is driven to rotate in a direction opposite the sheet conveyance direction. The bottom plate 9b moves upward in a direction U to cause an uppermost sheet S of the sheets S loaded on the bottom plate 9b to contact the pick-up roller 4b.
The pick-up roller 4b is connected to the feeding roller 2b via gears and rotates to feed the uppermost sheet S toward a nip formed between the feeding roller 2b and the separating roller 3b. The feeding roller 2b further feeds the sheet S toward the grip roller 5b. When the sheet S reaches the grip roller 5b, the pick-up roller 4b moves away from the sheet S. The feeding roller 2b stops rotating before a tail portion of the sheet S passes the nip formed between the feeding roller 2b and the separating roller 3b to prevent the rotating feeding roller 2b from successively feeding a next uppermost sheet S of the sheets S loaded on the bottom plate 9b and thereby interfering with proper image forming operations.
The feeding roller 2b includes a roller, a shaft, and a one-way clutch. The clutch switches on and off connection between the roller and the shaft. When the clutch switches off the connection, the shaft does not rotate the roller because a driving force of the shaft is not transmitted to the roller. Therefore, the feeding roller 2b is driven to rotate in the sheet conveyance direction by the sheet S fed by the grip roller 5b without disturbing proper conveyance of the sheet S.
The sensor 6b is disposed downstream of the grip roller 5b in the sheet conveyance direction. When the sensor 6b detects a head of the previous sheet S, feeding of the next uppermost sheet S starts so that the next sheet S is stably conveyed. The pick-up roller 4b and the feeding roller 2b are driven at a predetermined timing when the next sheet P is fed to enable image forming operations at a predetermined print speed without contacting the tail of the previous sheet S.
The background image forming apparatus tends to suppress the speed at which the sheet S is fed during image forming so as to form a high-resolution image. However, the background image forming apparatus is still required to provide a higher print speed. To respond to such requirement, the distance between the sheet S and the next sheet S is reduced in the background image forming apparatus.

Image forming apparatus, image forming method, and sheet feeding apparatus capable of effectively feeding sheets


A method of regulating data flow in a wireless communication network includes: collecting data regarding dynamic loading of sector-carrier pairs (pilots) in communication sectors of the wireless communication network; obtaining data rates for data flows of the pilots to access terminals within the wireless communication network; determining one or more pilots to use for conveying data in the wireless communication network based on the data rates and the dynamic loading; and altering data flow over the pilots by at least one of changing a data rate over at least one of the pilots or changing a combination of pilots used by the wireless communication network for conveying data to increase total data flow.

Wireless communication systems are widely deployed to provide various communication services such as voice, video, packet data, messaging, broadcast, etc. These wireless systems may be multiple-access systems capable of supporting multiple users by sharing the available system resources, e.g., time, frequency, power. Examples of such multiple-access systems include Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, Orthogonal FDMA (OFDMA) systems, and Single-Carrier FDMA (SC-FDMA) systems.
A wireless communication system may include a number of base stations that can support communication for a number of mobile terminals. The system may support operation on multiple carriers. Each carrier may be associated with a particular center frequency and a particular bandwidth. Each carrier may carry pilot and overhead information to support operation on the carrier. Each carrier may also carry data for terminals operating on the carrier. Some transmissions between a terminal and a base station may cause interference to, and may also observe interference from, other transmissions in the communication system. The interference may adversely impact the performance of all affected base stations.
Further, traffic load in the wireless communication system can impede performance of the system. Loads vary dynamically, with users coming to and leaving from the system or moving within the system over short periods of time. Further, traffic demands of users vary in time, e.g., with a user inducing a large load for a data download, but then no or little loading after that. Also, loads within the system are non-uniform. Different users may have different demands and thus induce different loading on the system. For example, one user may have a large data download requiring significant system resources while another user may have a small data demand requiring few system resources.


An apparatus and method of fabricating a through-wafer via. A first mask is formed over a first side of a first semiconductor die to define a first via area. A deep recess is etched through the first semiconductor die in the first via area and a blanket metal layer is formed over the first side including the deep recess. The blanket metal layer is removed from an outer surface of the first side of the first semiconductor die while retaining a portion of the blanket metal layer within the deep recess.

Modern semiconductor devices may comprise thousands or even millions of components (e.g., transistors, interconnects, pads, etc.) integrated into a single die. As such, semiconductor real estate is a premium asset not to be squandered by an integrated circuit ("IC") designer. To maximize the useable real estate of a single die, components may be integrated onto the front side as well as the backside of the die. To interconnect a dual sided die, through-wafer vias are formed throughout the die coupling the topside of the die to the bottom side of the die.
Another technique used to maximize the number of components within a single device is to stack two or more semiconductor dice together in what is called a bonded wafer stack. Components within these bonded wafer stacks are then interconnected using through-wafer vias. Known techniques form these through-wafer vias with a deep reactive ion etching process, requiring expensive tools. Not only is deep reactive ion etching expensive, but it is a slow fabrication technique.
Redistribution features (e.g., transmission lines) are often formed on the surface of a die to couple a via to other component locations. Current processes struggle with the challenge of coating straight sidewalls with metal to form the redistribution features. Typically, thicker metal layers are deposited to overcome these coating issues, with the detrimental side effect of increased incidence of stress induced wafer breakage. Known processes use additional lithography and metal plating processing, separate from via formation, to form these redistribution features. Similarly, known techniques require that the metallization of the vias be patterned after via formation using an additional high-aspect-ratio lithography process.

Through-wafer vias and surface metallization for coupling thereto


The invention relates to a service trolley. The service trolley includes a tabletop having at least one stowable wing, wheels attached to the trolley for moving the trolley, and a hot plate integrated into the tabletop.

The inventor is aware of service trolleys used in the hospitality industry. Although, known trolleys, such as room service trolleys may include stowable wings and include a hotbox, this is usually ineffective and unpractical as the hotbox is located underneath the table to be dined at. The inventor is not aware of any trolleys that include a cold storage compartment, which could be used to keep foods and beverages cold. Known trolleys are only efficient in serving a one-course meal, thus the inventor identified a need to serve a three-course meal and beverages e.g. wine, by using a single service trolley that allows for cold and warm storage simultaneously. Food and beverages can thus be served at the required temperatures at the serving location.


Methods and systems for preparing a hole having an accurately controlled area in an orifice plate for a mass flow controller are provided. Methods involve forming an initial hole in the orifice plate. The initial hole has an opening having an initial area. The orifice plate comprises a material that can react to form a coating on the orifice plate. The coating occupies a greater volume than the material consumed to form the coating. The material of the orifice plate is reacted with a reactant to produce the coating and thereby produce a reduced area hole having an opening with a reduced area that is smaller than the initial area. The reduced area hole is measured. A determined amount of the coating is removed from at least the reduced area hole to produce a final hole in the orifice plate, wherein the reduced area is smaller than an opening area of the final hole.

Mass flow controllers (MFCs) automatically control the flow rate of a gas in accordance with a desired flow rate input into the MFCs, typically as an electric signal. Various types, or configurations, of MFCs are available, some of which rely on heat transfer to determine a flow rate of incoming gas. Others rely on a small hole, also referred to as an orifice, formed in a plate through which gas passes to produce a measurable pressure difference.
While these and other types of mass flow controllers are adequate for many applications, including traditional semiconductor device fabrication applications, they are increasingly unsuitable for semiconductor device deposition processes and etch processes that deliver gases to process chambers for advanced semiconductor fabrication processes. These advanced processes often produce features having line widths on the order of 20 nm or less. To improve processing of such features, particularly when multiple semiconductor wafers are processed simultaneously in different chambers or stations, flow control provided by conventional MFCs may need to be improved. Each MFC in a system should control gas flows identically and with a high degree of accuracy.

Manufacture of an orifice plate for use in gas calibration