In a display unit, light emitting pixels are arrayed in a matrix form, an image signal having a half tone can be displayed, and the number of gray scale in a gray image can be increased without an increase in the number of times data is read out from a memory while maintaining a proportional relationship between display data and brightness of a screen. A changing portion generates an ON/OFF signal, in lower order bits in the respective display data read from the memory, according to a value of each of the bits, and compares, in higher order bits in the display data, a value indicated by the bits with a predetermined value so as to output an ON signal when the value indicated by the bits is greater than the predetermined value. The ON/OFF signal is supplied to column electrodes.

1. Field of the Invention
The present invention relates to a display unit in which light emitting pixels are arrayed in a matrix form, and an image signal having a half tone can be displayed.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional display unit disclosed in Japanese Patent Publication (Kokoku) No. 2-709. In FIG. 1, reference numeral 1 denotes a matrix display panel such as a fluorescent character display tube, 2 is a driver to drive row electrodes of the matrix display panel 1, and 3 is another driver to drive column electrodes of the matrix display panel 1. Display elements (light emitting elements) are disposed at intersections of the row electrodes and the column electrodes, and are turned ON by driving the corresponding row electrode and the corresponding column electrode. Reference numeral 4 denotes a shift register to place an ON/OFF signal from a changing portion 15 on the corresponding column electrode, 5 is a row electrode control circuit to create a drive signal for the row electrode, and 6 is a column electrode control circuit to create a drive signal for the column electrode. The column electrode control circuit 6 latches output of the shift register 4 for a predetermined time interval depending upon a latch signal from a timing generating circuit 8.
Reference numeral 9 denotes a display control unit to write display data onto a memory 7, 10 is a selector to feed the memory 7 with any one of a read address and a write address, 11 is a read/write control circuit to feed the selector 10 with a switching signal, 12 is a clock generating circuit to feed a clock signal to the timing generating circuit 8 and the read/write control circuit 11, 13 is a read address counter to generate the read address, and 15 is the changing portion to transform data read from the memory 7 into the ON/OFF signal for pixel.
The matrix display panel 1 is provided with a structure as shown in FIG. 2. That is, the display elements are disposed at intersections of a group of signal lines for feeding signals to the column electrodes X.sub.1 to X.sub.m and a group of signal lines for feeding signals to the row electrodes Y.sub.1 to Y.sub.m. Thus, the display elements are controlled according to a combination of the signals fed to the two groups of signal lines.
A description will now be given of the operation. The display control unit 9 outputs the display data, an address corresponding to a position at which the display data is displayed, and a timing signal in synchronization with the display data. The timing signal is inputted into the read/write control circuit 11. The read/write control circuit 11 receives the timing signal as input, and thereafter outputs a signal by which the selector 10 is switched over to the write address. Therefore, the address from the display control unit 9 is fed to the memory 7 as the write address. As a result, the display data can be stored in the memory 7 at an area specified by the write address.
Further, the display data stored in the memory 7 is read out according to the read address which is produced in the read address counter 13. The read address counter 13 generates an X address (a column address) fed to the column electrode control circuit 6, a Y address (a row address) fed to the row electrode control circuit 5, and a comparison signal B. The X address and the Y address are fed into the memory 7 through the selector 10. In this case, the selector 10 selects the read address according to control by the read/write control circuit 11. Consequently, it is possible to output data from the memory 7 according to the read address including the X address and the Y address.
Further, the Y address is sent to the row electrode control circuit 5. The row electrode control circuit 5 decodes the Y address so as to drive the row electrodes Y.sub.1 to Y.sub.m of the matrix display panel 1 through the driver 2. The data read from the memory 7 is sent to the changing portion 15. The changing portion 15 compares the data with the comparison signal B produced in the read address counter 13 so as to generate an ON/OFF signal according to the result of comparison. When the data is greater than the signal B, the ON signal is generated. When the data is equal to or less than the signal B, the OFF signal is generated. Here, `1` shows the ON signal and `0` shows the OFF signal. The ON/OFF signal is disposed in the shift register 4 according to a shift clock from the timing generating circuit 8. Further, the signal is latched by the column electrode control circuit 6 in response to a latch signal from the timing generating circuit 8. In response to the latched signal, the column electrode control circuit 6 drives the column electrodes X.sub.1 to X.sub.m through the driver 3.
In such a display unit, an image is displayed by sequentially and periodically driving the row electrodes Y.sub.1 to Y.sub.m, and by switching operation of a signal which is fed to the column electrodes X.sub.1 to X.sub.m in synchronization with the driving of the row electrodes Y.sub.1 to Y.sub.m. The display elements can exclusively provide binary representation, that is, any one of ON and OFF. However, when an image signal having a half tone should be displayed, the data in the memory is read out a predetermined number of times, and a cumulative elapsed ON time in each display element is controlled, thereby realizing gray image display.
A more detailed description will now be given of a display operation by way of, as an example, the matrix display panel 1 including a device having a 4-by-4 pixel array. Pixel positions in the matrix display panel 1 correspond to memory addresses in a one-to-one manner, resulting in a relationship as shown in FIGS. 3 and 4. FIG. 3 shows the pixel positions, and FIG. 4 shows the memory addresses corresponding to the respective pixel positions. FIG. 5 shows illustrative display data stored in the memory 7 at the respective addresses. As shown in FIG. 6, the addresses of the memory 7 can be classified into the X address and the Y address. FIG. 9 is a timing diagram showing row electrode driving timing and column electrode driving timing. FIG. 10 is an explanatory view showing the result of the driving.
When the display data corresponding to each pixel includes a 4-bit structure, it is possible to display a 16-scale gray image (because of 2.sup.4 =16). In this case, as shown in FIG. 7, the read address counter 13 includes a 2-bit counter 13a for generating the X address, a 4-bit counter 13b for generating the comparison signal B, and a 2-bit counter 13c for generating the Y address. The 2-bit counter 13b counts the clock signal from the read/write control circuit 11 to sequentially output values of 0 to 3 corresponding to the column electrodes X.sub.1 to X.sub.4. The 4-bit counter 13b counts a carry signal of the 2-bit counter 13a. In the 4-bit counter 13b, an initial value is set to zero. The 2-bit counter 13c counts a carry signal of the 4-bit counter 13b. The initial value of zero in the 2-bit counter 13c corresponds to the row electrode Y.sub.1.
Accordingly, with the comparison signal B of zero and the Y address of zero, four data stored in the first row shown in FIG. 5 are sequentially read out. As shown in FIG. 8, the changing portion 15 comprises, for example, a comparator 15a. The comparator 15a compares display data A with the comparison signal B so as to output an ON signal when A is greater than B, or output an OFF signal when A is equal to or less than B. As shown in FIGS. 5 and 6, the first row sequentially contains data of "15 (in decimal notation)," "10 (in decimal notation)," "12 (in decimal notation)," and "0". Since the comparison signal B is zero, the changing portion 15 sequentially outputs "1," "1," "1," and "0". Signals from the changing portion 15 are sequentially inputted into the shift register 4.
When the respective signals in the first row are inputted into the shift register 4, the timing generating circuit 8 outputs the latch signal such that the contents of the shift register 4 can be latched by the column electrode control circuit 6. The column electrode control circuit 6 drives the column electrodes X.sub.1 to X.sub.4 through the driver 3 according to the contents of the shift register 4. At the time, a value of zero is fed into the row electrode control circuit 5 as the Y address so that the row electrode control circuit 5 can drive the row electrode Y.sub.1 in the first row through the driver 2. Thus, as shown by a period t1 in FIGS. 9 and 10, display elements at intersections of the first row and the first to third columns are turned ON, and a display element at an intersection of the first row and the fourth column is not turned ON. In FIG. 10, a hollow ring denotes a display element which is turned ON, and a numeral in the hollow ring denotes an ON time interval. Further, reference numerals t1 to t64 correspond to reference numerals t1 to t64 in FIG. 9.
Next, by the read/write control circuit 11, a count value of the 2-bit counter 13a is reset to zero, and a count value of the 4-bit counter 13b is set to one. A count value of the 2-bit counter 13c is zero. Consequently, the four display data in the first row are read from the memory 7 again, and the display data are compared with the comparison signal B (=1) in the changing portion 15. According to the result of comparison, the changing portion 15, the shift register 4, the column electrode control circuit 6, and row electrode control circuit 5 are operated as set forth above. Therefore, as shown by a period t2 in FIGS. 9 and 10, the display elements are turned ON at the intersections of the first row and the first to third columns, and the display element at the intersection of the first row and the fourth column is not turned ON.
When the count value of the 4-bit counter 13b reaches 15 (in decimal notation) after count from 0 to 3 is repeated in the 2-bit counter 13a, the changing portion 15 compares the data in the first row from the memory 7 with the comparison signal B (=15). The first row sequentially contains the data of "15 (in decimal notation)," "10 (in decimal notation)," "12 (in decimal notation)," and "0." Because of the comparison signal of 15, the changing portion 15 sequentially outputs "0," "0," "0," and "0." As a result, as shown by a period t16 in FIGS. 9 and 10, all the display elements at the intersections of the first row and the first to fourth columns are not turned ON. As set forth above, comparison is made the number of times identical with the number of gray scale for each row data. As shown at the leftmost end of the first row in FIGS. 9 and 10, according to the result of comparison, the display element corresponding to the address "0" is held ON for a period of 15 unit times, the display element corresponding to the address "1" is held ON for a period of 10 unit times, and the display element corresponding to the address "2" is held ON for a period of 12 unit times. In such a manner, a gray image can visually be displayed according to the ON time periods.
Next, the count values of the 2-bit counter 13a and the 4-bit counter 13b are reset to zero, thereby setting the count value of the 2-bit counter 13c to one. Thus, the above processing is performed for data in the second row corresponding to the Y address "1". As a result, as shown at the leftmost end of the second row in FIGS. 9 and 10, the display element corresponding to the address "4" is held ON for a period of 8 unit times, the display element corresponding to the address "5" is held ON for a period of 4 unit times, the display element corresponding to the address "6" is held ON for a period of 2 unit times, and the display element corresponding to the address "7" is held ON for a period of 14 unit times.
The above processing is similarly carried out for data in the third row (the Y address of 2) and the fourth row (the Y address of 3), resulting in completion of the display operation in one frame. In the conventional display unit shown in FIG. 1, all the ON signals have a constant time interval as shown in FIG. 11, and a pulse number control method is employed in which the gray image display is realized according to the number of the ON signals.
On the other hand, another display unit is known in which pulse width control is made. In such a display unit, as shown in FIG. 12, a changing portion 15 has a selector 15b which can select one bit among 4-bit display data from a memory 7 according to a select signal S. The selection of the selector 15b results in an ON/OFF signal. Further, a timing generating circuit 8 is controlled to vary a time interval of the ON signal according to a bit weight (selected from weights 1, 2, 4, and 8). FIG. 13 is a timing diagram showing row electrode driving timing and column electrode driving timing. FIG. 14 is an explanatory view showing the result of driving.
In this case, a counter for generating an X address in a read address counter 13 sequentially feeds the memory 7 with values of 0 to 3. Output timing of the values of 0, 1, 2, and 3 do not have a constant interval, but have an interval according to the bit weight. A counter for generating the select signal S is positioned at a subsequent stage of the counter for generating the X address, and is incremented by one after the counter for generating the X address outputs all the values of 0 to 3. Further, another counter for generating a Y address is positioned at a subsequent stage of the counter for generating the select signal S, and is incremented by one after the counter for generating the select signal S outputs all values of 0 to 3.
Therefore, four data in the first row in the memory 7 are respectively read out four times (according to timing of the periods t1 to t4), and are compared with the select signal S for each time. The first select signal S is set to zero, the second select signal S is set to one, the third select signal S is set to two, and the fourth select signal S is set to three. In the first comparison, the changing portion 15 selects and outputs the least significant bit among the 4-bit data from the memory 7. In the second comparison, the changing portion 15 selects and outputs the first bit among the 4-bit data from the memory 7. In the third comparison, the changing portion 15 selects and outputs the second bit among the 4-bit data from the memory 7. Finally, in the fourth comparison, the changing portion 15 selects and outputs the most significant bit among the 4-bit data from the memory 7.
In such a manner, when, for example, data at the address "0" shown in FIG. 6 is outputted from the memory 7 four times, the changing portion 15 outputs "1," "1," "1," and "1" according to the timing of the periods t1 to t4. Since the output respectively have weights 1, 2, 4, and 8, in display modes t1 to t4 in the first row shown in FIG. 14, display is made for time intervals obtained by the leftmost values corresponding to the address "0". When data at the address "1" is outputted from the memory 7 four times, the changing portion 15 outputs "0," "1," "0," and "1" according to the timing of the periods t1 to t4. Thus, in the display modes t1 to t4 in the first row shown in FIG. 14, display is made for time intervals obtained by the second values from the left corresponding to the address "1."
For data at the address "2" and at the address "3," processing identical with the above processing is carried out by the changing portion 15, the timing generating circuit 8, and so forth. In such a manner, signals corresponding to signals in the periods t1 to t4 in FIG. 13 are fed to a row electrode Y.sub.1 and column electrodes X.sub.1 to X.sub.4. As shown by the leftmost display mode in the first row in FIG. 14, a display element corresponding to the address "0" is held ON for a period of 15 unit times, a display element corresponding to the address "1" is held ON for a period of 10 unit times, and a display element corresponding to the address "2" is held ON for a period of 12 unit times.
Subsequently, the Y address fed to both the memory 7 and the row electrode control circuit 5 is set to one, and the same processing as the above processing is carried out for data at the addresses "4" to "7." Thus, in case of data as shown in FIG. 6, signals corresponding to signals in periods t5 to t8 in FIG. 13 are fed to a row electrode Y.sub.2 and column electrodes X.sub.1 to X.sub.4. The same operation is carried out with respect to Y addresses "2" and "3."
In the display unit, the ON signals are set to have four types of time intervals, and a gray image can be realized by a combination of the ON signals as shown in FIG. 15. For example, in case of display data of weight 8, an ON signal having a time interval of 8 is fed to the column electrodes X.sub.1 to X.sub.4. Alternatively, in case of display data of 7, an ON signal having a time interval of 1, an ON signal having a time interval of 2, and an ON signal having a time interval of 4 are respectively fed to the column electrodes X.sub.1 to X.sub.4.
In the display unit employing the pulse number control method, the display data must be read out from the memory 7 the number of times identical with the number of gray scale before one frame can be displayed. Hence, when an increase in the number of bits in the display data increases the number of gray scale, it is necessary to operate the memory 7 and the control circuit at a higher velocity. As a result, the increase in the number of gray scale is limited.
In the display unit employing the pulse width control method, the number of times the display data is read from the memory 7, required to display the one frame, becomes equal to the number of bits in the display data. Thus, the pulse width control method requires considerably less number of times of read than the pulse number control method. However, for a short time interval such as the period t1 or t5, it is necessary to read out the display data expressed as the number of bits per data by the number of pixels per row (for example, four bits by four pixels in case of a 16-scale image including a 4-by-4 pixel array). Consequently, it is also necessary to operate the memory 7 and the control circuit at a higher velocity, and the increase in the number of gray scale is limited.
Further, due to influences such as response velocities of drivers 2 and 3 and light emitting elements, or ripple noise in power supply voltage, it becomes difficult to, for example, realize a pulse width corresponding to a time interval of 7 by summing up the ON signals respectively having the time interval of 1, the time interval of 2, and the time interval of 4. As the number of scale is further increased, such a tendency becomes more pronunced. When the scale number is increased, a value of the display data can not easily be made proportional to brightness of the display panel because of the following reason. That is, when the number of gray scale is increased to reduce an interval of the ON signal, sometimes supply of the ON signal fails to turn ON the display element by a response rise delay time and so forth due to the influences such as response velocity of the display element. That is, at times, the value of the display data can not easily be made proportional to brightness of display.
In addition, both the control circuit in the pulse number control method and the control circuit in the pulse width control method feed the ON signals to the column electrodes and the row electrodes according to the same timing. As a result, an expensive circuit having a higher response velocity is required for both a column electrode drive circuit and a row electrode drive circuit.


A clock generator which is provided with a circuit generating non-overlap clock from input clock, a frequency dividing circuit driven by the non-overlap clock and a latch disposed between the frequency dividing circuit and a clock driver, and whose critical pass being a cause of delay is shortened by sampling the frequency-divided output into the latch by the input clock and thereafter driving it by the clock driver, and a clock generator in which an internal clock at high speed in the internal clock logical value generating circuit is added with internal clock edge generating circuit required to operate at high speed and an output of initial stage of a buffer for inputting external clock is divided to supply to the internal clock edge generating circuit and to the other circuits, thereby capacity of the buffer required to operate at high speed in the circuit is decreased to reduce the delay of external clock.

1. Field of the Invention
The present invention relates to a clock generator in a semiconductor system using semiconductor integrated circuit and semiconductor integrated circuit element, and to a clock generator which enables the high speed operation thereof by decreasing delay between the input clock and output clock.
2. Description of Related Art
FIG. 1 is a block diagram of an example of construction of a conventional clock generator.
In FIG. 1, reference numeral 61 designates a crystal oscillating circuit (CO), 62 a multiplexer, 63 a frequency dividing circuit, 64 a clock driver, 65 an RES# signal synchronizing circuit, and 66 an ADS# signal synchronizing circuit. Moreover, reference numeral 67 designates a quartz resonator connecting terminal, 68 an external clock signal input terminal, 69 a clock (CLK2) signal output terminal, 70 a clock (CLK) signal output terminal, 71 a clock signal source selecting terminal, 72 an RES# signal input terminal, 73 a RESET signal output terminal, 74 an ADS# signal input terminal, and 75 an AD50 signal output terminal.
Next, explanation will be given on an operation of a conventional clock generator of a construction mentioned above.
A quartz resonator having oscillating frequency being equal to clock frequency expected to be outputted from the clock (CLK2) signal output terminal 69 is connected with the quartz resonator connecting terminal 67, and an external clock signal is connected with the external clock signal input terminal 68 respectively as clock signal sources. And in the case where the clock signal source selecting terminal 71 is set at low level, the terminal 68 is selected as clock signal source, and in the case where it is set at high level, the terminal 67 is selected respectively by the multiplexer 62. The clock signal source selected by the multiplexer 62 is outputted therefrom to be inputted to the clock driver 64 and driven from the clock (CLK2) signal output terminal 69.
On the other hand, the clock signal source outputted from the multiplexer 62 is inputted to the frequency dividing circuit 63, and driven from the clock (CLK) signal output terminal 70 after the frequency thereof being divided into two.
In addition, explanation on operations of the RES# signal synchronizing circuit 65 and the ADS# signal synchronizing circuit 66 will be omitted as there is no direct relation with the present invention.
Moreover, as shown in the block diagram in FIG. 1, although a non-overlap clock is widely used in order to prevent malfunctioning due to lacing of data, as a clock for driving the 1/2 frequency dividing circuit usually comprising flip-flop of two stages, the clock and the generating circuit thereof are omitted.
FIG. 2 shows a block diagram showing a construction of a conventional clock generator being provided with the non-overlap clock generating circuit 76.
In the case where the construction of the clock generator is that of the block diagram in FIG. 2, the clock signal source outputted from the multiplexer 62 is inputted to the non-overlap clock generating circuit 76. The non-overlap clock generating circuit 76 generates clock signal 77 of two-phase having non-overlap period from the inputted clock signal source. And the frequency dividing circuit 63 is not directly driven by the output of the multiplexer 62, but is driven by the non-overlap clock 77 generated by the non-overlap clock generating circuit 76.
In addition, other operations are quite the same as those of the clock generator shown in a block diagram in FIG. 1 above-mentioned.
Moreover, as an example of a conventional clock generator, a construction as shown in a block diagram in FIG. 3, for example.
In FIG. 3, reference numeral 1 designates an external clock. The external clock 1 is inputted from a pad 2 to be a first clock C1 through inverters 31 and 32 of two stages of a buffer 3, and to be a second clock C2 directly from the inverter 31, these clocks C1 and C2 respectively being inputted to a non-overlap clock generating circuit 51 of an internal clock logical value generating circuit 5
FIG. 4 is a circuit diagram showing an concrete construction of the non-overlap clock generating circuit 51. Both of the first clock C1 and the second clock C2 having inputted to the non-overlap clock generating circuit 51 are inputted to the frequency dividing circuit 52 as a fourth clock C4 and a third clock C3 through NOR gates and inverters of two stages, respectively.
FIG. 5 is a circuit diagram showing a concrete construction of the frequency dividing circuit 52. The frequency dividing circuit 52 comprises D latches D1 and D2 of two stages. The third clock C3 inputted into the frequency dividing circuit 52 is outputted as sixth clock C6 through one D latch D1 and the fourth clock C4 inputted into the frequency dividing circuit 52 is outputted as a fifth clock C5 through the other D latch D2, respectively.
The fifth clock C5 is outputted as a second internal clock IC2 through an inverter 18 and an internal clock outputting buffer 15'. On the other hand, the sixth clock C6 is outputted as a first internal clock IC1 only through an internal clock outputting buffer 15.
FIG. 6 is a timing chart showing a waveform of above-mentioned each clock.
Compared with the external clock 1 shown in FIG. 6(a), the second clock C2 through the inverter 31 of the buffer 3 is inverted and delayed a little, as shown in FIG. 6(c), and the first clock C1 through inverters 31 and 32 of two stages of the buffer 3 is inverted two times and delayed about two times of the second clock C2, as shown in FIG. 6(b).
The fourth clock C4 shown in FIG. 6(e) is delayed by the time required for the first clock C1 passing through one NOR gate and two inverters from C1, and the third clock C3 shown in FIG. 6(d) is generated in the non-overlap state with the fourth clock C4.
And the sixth clock C6 shown in FIG. 6(g) is generated from the third clock C3 due to delay corresponding to one D latch, and the first internal clock IC1 is generated shown in FIG. 6(h) from the sixth clock C6 due further to delay of time to pass one internal clock output buffer 15.
Accordingly, time delay shown by Td in FIG. 6 is generated between the external clock 1 shown in FIG. 6(a) and the first internal clock IC1 shown in FIG. 6(h) .
In the above-mentioned first conventional clock generator, until the frequency-divided clock is generated from the clock signal source outputted from the multiplexer 62 and is outputted, it is to be through the frequency dividing circuit 63 in the case of the construction example, shown in FIG. 1, or is to be through the frequency dividing circuit 63 and non-overlap clock generating circuit 73 in the case of the construction example shown in FIG. 2, in which the frequency dividing circuit 52 is driven by the non-overlap clock 17. That is to say, the critical pass between the inputted external clock being the source clock signal and the output clock is;
external clock.fwdarw. PA1 non-overlap signal generating circuit 51.fwdarw. PA1 frequency dividing circuit 52.fwdarw. PA1 clock driver 15. PA1 (1) in the case where input to the CK input terminal PA1 (2) in the case where input to the CK input terminal PA1 (3) in the case where input to the CK input terminal PA1 (4) in the case where input to the CK input terminal PA1 (1) in the case where input to the C input terminal 802 is "1". PA1 (2) in the case where input to the C input terminal. 802 PA1 input clock.fwdarw. PA1 latch means.fwdarw. PA1 clock driver, PA1 which is shorter than that of a conventional clock generator, and moreover the time delay thereof is largely reduced as a non-overlap clock generating circuit whose delay is especially large is not integrated in the critical pass.
Especially, as the non-overlap clock generating circuit 51 is composed generally of a chain of gates, the delay thereof is made large as a necessary consequence. Accordingly, there is a problem that the time delay between input clock (external clock) and output clock is made large.
In addition, also when the second conventional clock generator is used, a large time delay shown by Td in FIG. 6 is generated.
Next, explanation will be given on Japanese Patent Application Laid-Open No. 1-276327 (1989) as a third conventional example of a clock generator referring to drawings thereof.
FIG. 7 is a block diagram showing a construction of a clock generator disclosed in aforementioned Japanese Patent Application Laid-Open No. 1-276327 (1989).
In FIG. 7, reference numeral 101 designates an input terminal of a reference clock, 102 a D flip-flop functioning as a 1/2 frequency divider, 103 a D flip-flop, 104 a set/reset flip-flop, and 105 designates a D latch.
Numerals 109 and 110 designate clock output terminals and respectively output 1/2 frequency-divided clock and 1 frequency-divided clock of reference clocks inputted to the clock input terminal 101. A reference numeral 106 designates an input buffer, and 107, 108 designate output buffers.
The reference clock inputted from the clock input terminal 101 is given to clock input CK of the D flip-flop 102 and to D input of the D latch 105 through the input buffer 106.
Q output of the D flip-flop 102 is connected to D input of the D flip-flop 102 itself and Q output to D input of the D flip-flop 103, and Q output of the D flip-flop 103 is outputted to the output terminal 109 through the output buffer 107.
Q output and Q output of the D latch 105 are respectively outputted to S input and R input of the set/reset flip-flop 104. And Q output of the set/reset flip-flop 104 is outputted to the output terminal 110 through the output buffer 108.
By the way, explanation will be given in the following on the D flip-flops 102 and 103 used in a clock generator of such a construction as above-mentioned, referring to a circuit diagram of FIG. 8 showing circuit construction of the D flip-flops 102 and 103.
In FIG. 8, reference numeral 901 designates a D input terminal inputting data, 902 a CK terminal inputting clock, 903 and 904 a Q output terminal and Q output terminal respectively, and 905 and 906 inverters, 907 an NAND gate, 908 through 910 OR-NAND gates respectively in each of which an OR gate and an NAND gate are integrated.
Here, logical relation among the D input terminal 901, CK input terminal 902, Q output terminal 903, and Q output terminal 904 is a so called rising edge trigger D flip-flop, and expressed in relation shown in Table 1.
TABLE 1 ______________________________________ D CK Q .sup.-- Q ______________________________________ 1 0 .fwdarw. 1 1 0 0 0 .fwdarw. 1 0 1 X OTHER THAN ABOVE Q .sup.-- Q ______________________________________
In addition, the D flip-flops 102 and 103 shown in FIG. 7 is respectively so constructed that the OR-NAND gate 908 and the inverter 906 shown in FIG. 8 may function as a set/reset flip-flop of input stage, and the OR-NAnd gates 909 and 910 may function as a set/reset flip-flop of output stage. The operation of the D flip-flops 102 and 103 of a construction shown in FIG. 8 is as follows.
902 is "0".
As output of the inverter 905 is "1", OR input of the OR-NAND gates 909 and 910 in the set/reset flip-flop of output stage is "1", and there is no new input, the output state in the past will be maintained. Accordingly, values of Q output terminal 903 and Q output terminal 904 do not change. In the set/reset flip-flop of input stage, as the NAND gate 907 turns into ON state, the state of the D input terminal 901 is taken in the OR-NAND gate 908 and the reversed value thereof becomes output of the inverter 906. But one OR input of the OR-NAND gate 908 is in "1" state of the inverter 905, the set/reset flip-flop of input stage is not in a holding state.
902 changes from "0" to "1".
The output of the inverter 905 changes from "1" to "0". Therefore, the NAND gate 907 changes from ON state to OFF state and the set/reset flip-flop of input stage takes in the state of the D input terminal 901 being immediately before the change to the OR-NAND gate 908, and the NAND gate 907 shifts to a holding state. On the other hand, in the set/reset flip-flop of output stage, as OR inputs of the OR-NAND gates 909 and 910 change from "1" to "0", the state of the set/reset flip-flop of input stage are taken in to be outputted to the Q output terminal 903 and Q output terminal 904.
902 is "1".
As the NAND gate 907 becomes OFF state, new data is not taken in.
902 changes from "1" to "0".
The NAND gate 907 changes from OFF state to ON state, thereby OR inputs of the NAND gates 909 and 910 become "1"according to the inverter 905 much faster than the information of the D input terminal 901 is transmitted to these gates. Accordingly, the set/reset flip-flop of output stage becomes a holding state, and outputs from the Q output terminal 903 and Q output terminal 904 do not change.
Next, explanation will be given on the D latch 105 referring to a circuit diagram in FIG. 9 showing it circuit construction. In FIG. 9, reference numeral 801 designates a D input terminal inputting data, 802 a C input terminal inputting enable signal, 803 and 804 a Q output terminal and Q output terminal respectively outputting data, 805 and 806 OR-NAND gates, and 807 designates an inverter.
Here, logical relation among the D input terminal 801, C input terminal 802, Q output terminal 803, and Q output terminal 804 is the one as expressed in Table 2.
TABLE 2 ______________________________________ D C Q .sup.-- Q ______________________________________ 1 1 1 0 0 1 0 1 X 0 Q .sup.-- Q ______________________________________
The operation of the D latch 105 of such a construction as shown in FIG. 9 is as follows.
As OR outputs of the OR-NAND gates 805 and 806 are both "1", the information of the D input terminal 801 is transmitted to the Q output terminal 803 through the OR-NAND gates 800 and 806. To the Q output terminal 804, the reversed value of the Q output terminal 803 is transmitted through the inverter 807.
is "0".
A set/reset flip-flop is constructed by the OR-NAND gate 806 and the inverter 807. In the case where the Q output terminal 803 holds "0", as OR input of the OR-NAND gate 805 is "0", the gate 805 becomes OFF state and the information of the D input terminal 801 is not taken in. And in the case where the Q output terminal 803 holds "1", as 0R input of the OR-NAND gate 806 is "0", the information from the OR-NAND gate 805 is not taken in. In either case, regardless of the information of the D input terminal 801, the information before the C input terminal 802 changes its value from "1" to "0" is held at the Q output terminal 803 and the Q output terminal 804.
Next, explanation will be given on the set/reset flip-flop 104, referring to a circuit diagram of FIG. 10 showing is circuit construction.
In FIG. 10, reference numeral 701 designates an S input terminal, 702 an R input terminal, 703 a Q output terminal, 704 a Q output terminal, and 705 and 706 designates NOR gates.
Here, as the S input terminal 701 and the R input terminal 702 are connected directly with the Q output terminal 704 and Q output terminal 703 of the D latch respectively, when one input is "1", the other is "0".
Logical relation among the S input terminal 701, R input terminal 702, Q output terminal 704, and Q output terminal 703 is such as expressed in Table 3 according to the NOR gates 705 and 706.
TABLE 3 ______________________________________ S R Q .sup.-- Q ______________________________________ 1 0 1 0 0 1 0 1 ______________________________________
In the following, explanation will be given on the operation of the third conventional clock generator shown in the block diagram of FIG. 7, referring to a timing chart of FIG. 11.
A waveform shown in FIG. 11(a) is the one of reference clock inputted to the clock input terminal 101, and such a clock is taken in a clock generator constructed on an LSI through the input buffer 106 to be inputted to the CK input terminal of the D flip-flop 102.
In the D flip-flop 102, as Q output is connected to D input thereof, every time the waveform shown in FIG. 11(a) changes from "0" to "1", data of reverse polarity to the past is outputted as Q output. This waveform is shown in FIG. 11(b). That is, the D flip-flop 102 functions as a 1/2 frequency divider.
The Q output terminal of the D flip-flop 102 is given to the CK input of the D flip-flop 103. The output waveform after the output of the D flip-flop 103 passed-through the output buffer 107, that is, 1/2 frequency-divided clock 109 is shown in FIG. 11(c).
On the other hand, the buffered reference clock by the input buffer 106 is also inputted to D input of the D latch 105. However, as C input of the D latch 105 is fixed to be "1", the Q output thereof becomes to be same waveform (although delayed) as the reference clock as shown in FIG. 11(d).
The waveform shown in FIG. 11(e) is the output waveform of the set/reset flip-flop 104 after passing the output buffer 108. As the set/reset flip-flop 104 is directly connected with the output of the D latch 105, the D input terminal of the D latch 105 is connected with the clock input terminal 101 through the input buffer 106, and the C input terminal of the D latch 105 is fixed to be "1", a waveform shown in FIG. 11(e) is the one of the reference clock shown in FIG. 11(a) being delayed.
By the way, in the aforementioned third conventional clock generator disclosed in Japanese Patent Application Laid-Open No. 1-276327 (1989), although phases of the generated clocks match with each other, the number of gates from the input terminal of the reference clock to the output terminal of the generated clock is large. Therefore, the delay generated clock is large as compared with the reference clock. For example, in the case where internal clock is generated, if a phase difference between external clock (reference clock) and itself is large, a sampling of external signal cannot be performed as desired, leading to much possibility of malfunction.
In addition, the D flip-flop itself has many gates, leading to a problem that a layout area on an LSI becomes large.


Methods and apparatus for dynamic bandwidth allocation are disclosed. An example method includes determining, by a network device, at least one of a congestion state of a packet memory buffer of the network device and a congestion state of an external packet memory that is operationally coupled with the network device. The example method further includes dynamically adjusting, by the network device, respective bandwidth allocations for read and write operations between the network device and the external packet memory, the dynamic adjusting being based on the determined congestion state of the packet memory buffer and/or the determined congestion state of the external packet memory.

Network devices, such as network switches, may receive packet data on a number of ingress ports, process that packet data and then forward the processed packet data on to corresponding network destinations using a number of egress ports. During packet processing, a network device stores packet data using one or more packet memories, which may be shared by all of the ingress and egress ports of the network device. For example, in one arrangement, a network device may include an internal packet memory as well as being operationally coupled with an external packet memory.
In such implementations, received packet data may be stored in the internal packet memory during processing, buffered in the internal packet memory (such as in a packet buffer) and then written to external packet memory, or may use a combination of internal and external storage. For instance, packet data may be stored internally during normal traffic conditions while using the external packet memory to absorb transient bursts in data traffic. In other situations, the internal packet memory may be simply used to buffer all received packet before writing it out to external packet memory. Of course, a number of other approaches and techniques for storing packet data during processing using an internal packet memory and an external packet memory may be used.
In configurations where at least a portion of packet data being processed by a network device is stored in an external packet memory, implementation of an interface between the network device and the external memory with adequate bandwidth for read and write memory operations between a network device and an external packet memory may be cost prohibitive. For instance, high-speed serializer-deserializer (SERDES) circuits are commonly used to implement such interfaces. These high-speed SERDES circuits affect product cost as they typically use a significant amount of power and, when implemented in an integrated circuit, consume a substantial amount of circuit area. Because such interfaces are often used for handling temporary traffic bursts, which may occur infrequently, the cost of implementing an interface with sufficient bandwidth to handle such traffic bursts may not be cost-effective.


To provide a tire vulcanizer capable of solving problems of an electrical heating platen, which relate to the deformation at the time of tire vulcanization and to the replacement of the platen. The tire vulcanizer vulcanizes and molds a green tire placed in an outer mold by heating the green tire from the outer side and the inner side of the green tire, and is featured by including an electric platen (10) which is arranged to be in contact with each of the upper and lower sides of a container with the green tire placed therein, or to be embedded in each of the upper and lower portions of the container, so as to heat the green tire from the outside of the outer mold at the time of vulcanization, and which is formed into a doughnut-like disc shape and divided into a plurality of sections in the circumferential direction of the platen (10).

Conventionally, in a tire vulcanizer which vulcanizes and molds a green tire, an outer mold (mold), in which the green tire is placed, is heated, and the inner wall surface of the green tire is pressed toward the outer mold while being heated by a high-temperature and high-pressure heating medium being supplied to the inner space of the green tire (to the inside of the bladder). Then, the outer side and the inner side of the green tire are heated by the heated outer mold and the heating medium supplied to the inner space of the green tire, and thereby the green tire is vulcanized.
Note that the conventional tire vulcanizer is configured such that steam as a heating medium is supplied into and circulated through the inner space of the green tire, and such that a heated and pressurized medium, such as nitrogen gas and warm water, is sealed in the inner space.
As a prior art of the tire vulcanizer described above, in which a green tire is heated from the outside thereof, there is an apparatus using a heat medium, as disclosed, for example, in Patent Literatures 1, and 2. In the prior art, a platen (heat plate) is arranged on each of the upper and lower sides of an outer mold in which a green tire is placed, and steam as a heat medium is supplied to the inside of both the platens, so that heat is transferred to the green tire from the outside of the outer mold.
On the other hand, as for a tire vulcanizer in recent years, instead of the above-described heating technique using the heat medium, a heating technique using an electric platen has been proposed from the viewpoint of energy saving, and the like.
As electric heating methods applied to the electric platen, there are known a heating method using a rod-shaped or planar electric heater embedded in the platen (see, for example, Patent Literature 3, described below), and an induction heating method using an electromagnetic coil (see, for example, Patent Literature 4, described below).
Further, the conventional platen described above is formed into a one-piece structure having a doughnut-like disc shape, for facilitating the formation of a heat medium flow path, the attachment to the mold, and the like. However, Patent Literature 5, described below discloses a tire vulcanizing mold in which, in order to obtain a uniform degree of vulcanization over the whole of a tire, the platen is divided in the radial direction thereof, and the rates of temperature increase of heating sections are correspondingly changed.


The present invention relates to a packet data communication system and is primarily intended for packet data radio communication systems, such as a GSM-system (PLMN) supporting a GPRS-service. A data frame received from a connected second packet data network (Internet) is divided into a sequence of data segments (DS). Speech packets (SPP) with an origin from a connected telecommunication network and the segments (DS) and are transmitted over a packet data link (PL1) to a radio base station (BTS) with priority given to the speech packets (SPP). The data segments (DS) shall be transmitted on a corresponding radio link (RL2) to a designated mobile station (MS). The problem is that during high traffic loads the segments are subjected to long delays and as a result no segments can be transmitted on the corresponding radio link. Giving priority to a first few data segments of the sequence when transmitted over the packet data link (PL1) solves the problem.

This application claims priority under 35 U.S.C. xc2xa7xc2xa7119 and/or 365 to 9900897-1 filed in Sweden on Mar. 12, 1999; the entire content of which is hereby incorporated by reference.
The present invention relates to a packet data communication system which is connected to a telecommunication system and to another packet data communication system, and which gives transmission priority with respect to short delays for information packets received from the telecommunication network.
In packet data transmission systems, the channels through the network share the capacity of the links within the system. This is in contrast to circuit switched communication systems where a corresponding link is dedicated to each transaction. The traffic generated in packet data systems is in the nature of bursts, i.e. traffic load varies, often rapidly, in time. The transmission delay of the packets will depend on the traffic load in the system and will thus also vary, often rapidly, in time. For a specific link, the transmission delay will depend on the number y of packets in line for transmission over the link. Packet losses may occur if transmission delays are too prolonged.
Telecom applications using packet transmission can be divided roughly into speech and data. In this case by xe2x80x9cspeechxe2x80x9d is meant spoken information between two end users in a dialog. Speech applications usually use circuit switched telecommunication systems for transmission, since these systems are developed to fulfil the stringent requirements on short delays. Nevertheless, packet data systems are expected to transfer more of the speech in the future. However, data is the major application for packet data networks at the present time. To compete with the telecommunication system on the transmission of speech, packet transmission systems must keep delays short.
Generally the demand for short delay is not as critical for data as for speech. Data, however, is more vulnerable to loss of data packets.
It has been suggested that Internet should support differentiated Quality of Service for separate services. This would result in speech transmission being given priority with respect to delay over the transmission of data when speech and data compete for common transmission resources. These discussions have been held within a group IETF (Internet Engenering Task Force).
A granted patent U.S. Pat. No. 4,538,259 is related to a communication system transmitting voice packets. The voice packets are transmitted through the network to a receiving node where they are reproduced into sound. To reproduce the sound the digitised voice packets have to be D/A converted at a certain rate. One problem is that variations in transmission delays cause the voice packets to arrive at the receiving node at different intervals. To adjust for the variations in delay packets are intentionally delayed slightly in the receiving node before being reproduced into sound. The object of U.S. Pat. No. 4,538,259 is to define an adequate intentionally delay in the receiving node. If it is to too long, the quality of the connection is negatively effected as the total delay increases. Speech packets may also be lost due to overflow in the receiver buffer. If, on the other hand, the delay in the receiver is made too short it will not suffice to compensate for the variations in the transmission delay. To achieve the object according to U.S. Pat. No. 4,538,259 the first voice packet is sent with priority, thereby having a more defined transmission time through the communication system.
The present invention is more closely related to a packet data service designated General Packet Data Service, which is hereafter referred simply as GPRS. GPRS is to be a standardised service for mobile communication system GSM and work has been going on for some years to this end within the European standardisation organisation ETSI. A GSM network will have a connection to other packet data networks, for instance networks using TCP/IP protocols and will receive data packets in the form of data frames for further transmission to a receiving mobile station. The received data frames are however to large to fit into the protocol of the radio link and are therefore split into data segments before being transmitted to the mobile station.
According to one proposal there is included a packet control unit for receiving data frames and splitting each frame into a sequence of data segments. A packet data link is connected from the packet control unit to at least one radio base station. The radio base station is provided with a number of radio links for packet transmission to a number of mobile stations. A data frame addressed to a certain mobile station is thus split into a sequence of data segments in the packet control unit. The sequence is then transmitted over the packet data link to the radio base station. The sequence is interleaved over the packet data link with other sequences of data segments to be sent from the packet control unit to the radio base station, i.e. segments of different sequences are mixed in the transmission flow. Segments received in the radio base station are then sent over the radio links. The radio channels are a scarce resource and there is a need to utilise them efficiently. The lower limit of the transmission delay within the GSM system is determined by the capacity of the radio link.
The architecture of a GSM-system supporting the GPRS service has not yet been settled.
It has recently been disclosed that also American operators intend to introduce the GPRS-service in the AMPS and IS-136 mobile radio systems.
The present invention addresses a problem of efficiently transmitting data segments over a first packet data link to be received in a first node in time for the first node to transmit the segments at predefined times over a second packet data link, when the first packet data link is also used for transmission of information packets having priority over the data segments and when the transmitted capacity of the first packet data link is limited.
The problem relates for example to a GSM-system that uses packet transmission between internal nodes, to provide for both a traditional circuit connected speech service and for packet data service handling applications such as Internet data services. The packet data service shall enable data frames to be received from a data network such as Internet and be transmitted to a designated mobile station. The traditional connected speech service shall provide for communications between a PCM coded link, i.e. a link traditionally used for a circuit switched connection, and a mobile station.
A data frame is received by a GSM network and divided into a sequence of data segments in the packet control unit such as to fit into the protocol of the radio link. PCM coded information, i.e. mainly speech, is continuously received by the GSM network and continuously coded into information packets, in the case of speech this is effected by speech transcoders. According to the example, the architecture of the GSM-system enables the data segments and the information packets to be transmitted to a radio base station on the same first packet data link, i.e. to the first node. On the first packet data link the flow of data segments and information packets compete for transmission capacity.
Information packets are given priority over data segments when transmitted over the first packet data link.
However, data segments also have to be delivered to the base station on time for transmission to the mobile station. When priority is given to the information packets there is a risk that no data segments will arrive at the base station at the times for transmission over the radio link.
The data segments corresponding to a sequence are consecutively transmitted over the radio link, i.e. a second packet data link, to the mobile station. The time for transmission of the segments is determined by the mapping of logical channels on the radio link, the synchronisation of the mobile stations and also on the need to utilise effectively the scarce resource of the radio link.
The present invention solves the problem, by a method in which the first data segments of a sequence derived from one data frame are transmitted over the first packet data link with the same priority as the information packets, thereby reducing the risk of the first data segments arriving too late at the first node. Instead, some of the first data segments probably arrive too early and are buffered until time for transmission over the second link. A subsequent transmitted data segment may thereafter be subjected to a longer delay than would otherwise be possible without causing a problem, due to the presence of a data segment that has already arrived in the first node and that is ready for transmission over the second data packet link at the predefined time.
The problem is also solved by a packet communication system comprising an interface with means to transform a received stream of information into a corresponding stream of information packets. The system also comprises a packet control unit for receiving a data frame, a first nod, a first packet data link connecting the interface and the packet control unit to the first nod. The packet control unit includes means for splitting a received data frame into a sequence of data segments. The packet communication system also comprises means for transmitting said stream of information packets and said sequence of data segments over the first packet data link with priority given to information packets and to some first data segments in the sequence of data segments.
The problem is also solved by a method in which data segments and information packets are transmitted over a first packet data link to a first node. Information packets are given priority on the first packet data link. Data segments received by the first node are each to be transmitted at a predefined time over a second packet data link. Data segments are buffered in the first node until the predefined times for transmission over the second packet data link. In the event of the number of data segments decreasing a threshold number, the first node sends a signal. In response to the signal some few data segments are sent with priority over the first packet data link. Thereby, filling of the buffer is speeded up.
According to one embodiment of the invention, the packet data system is a radio communication network with a PCM coded connection to the telecommunication network and a connection to a packet data network. Data frames received from the data network are divided into sequences of data segments. A stream of information received by the PCM coded connection is transformed into a corresponding stream of information packets. The data segments and the stream of information packets are transmitted over the first link to the radio base station, with priority given to the information packets and the first data segments of a sequence. Sequences of data segments and information packets are transmitted from the radio base station to a mobile station on separate packet data radio links.
An advantage with the present invention is that the risk of no data segment being available in the first node at the predefined time for transmission over the second packet data link is markedly reduced, just by giving the first few data segments of the sequence a higher priority.
Further advantages afforded by the invention will be apparent from the following analysis of a packet data radio communication system. There is a fundamental difference in transmission of a data frame received by a packet data network and a stream of information received by a telecommunication network. The data frame is divided into segments, that are transmitted to the first node and then to the mobile station. The data frame is not restored until all segments of the frame have been received in the mobile station, wherewith the information carried thereby can be retrieved. This implies that an inevitable delay is introduced to the data frame when received at the mobile station. The lenght of the delay is dependent on the capacity of the radio link for all the segments to be transmitted.
Speech packets and data segments are transmitted over separate radio links. Data segments are transmitted over the radio link in a consecutive order at defined times.
The fact that all data segments of the sequence are available in the packet control unit means that data segments can be sent in advance over the first packet data link and buffered in the radio base station until time for transmission on the radio link. As distinct from data segments, information packets may not be delayed in the radio base station. Any delay of information packets in the radio base station will have an affect on the total transmission delay.
The advantages afforded by the present invention will be fully apparent in the light of the above analysis. The main advantage resides in less danger of the first node, e.g. the radio base station, being devoid of data segments at the time for transmission over the second link, e.g. the radio link. If it were not for the invention, the risk of running out of segments would be greatest at the beginning of transmission of the sequence of segments, since no or only some segments are then are buffered in the first node. The risk of the radio base station running out of segments for transmission could, in theory, be reduced by increasing the traffic capacity of the first packet data link. However, to achieve the same risk reduction, the capacity of the first link would have to be greatly increased, at a corresponding cost. The solution according to the present invention is much cheaper to implement. The invention is easy to implement. In a system supporting differentiated Quality of Service the nodes already handles priorities and the invention can be implemented merely by adding priority information to some data segments.

Packet communication system and a method related to such a system


A residential gateway (RG) for distributing video, data and telephony services to multiple devices within a residence is disclosed. The RG receives signals from a telecommunications network, converts the signals to formats compatible with the multiple devices, and transmits the appropriate signals to the appropriate devices. Optical Remote Control devices (RCs) associated with remotely located televisions (TVs) transmit channel select commands to the RG as optical signals. The optical signals are received by an optical receiver located in close proximity to the remotely located TVs. The optical signal is then converted to an RF signal by an RF transmitter which transmits the RF signal over coaxial cable. A Remote Antennae Module (RAM) extracts the channel select command from the RF signal and provides it to the RG.

Advances in the field of telecommunications allow large amounts of digital information to be delivered to a residence. Digital telecommunications networks (access systems), such as Hybrid-Fiber-Coax (HFC), Fiber-to-the-Curb (FTTC), and Digital Subscriber Line (DSL), can provide both traditional telecommunications services such as Plain Old Telephone Service (POTS) as well as advanced services such as Switched Digital Video (SDV) and high-speed data access. Devices inside the residence, will be connected to the network by twisted wire pairs which provide telephone services today, or by coaxial cable similar to that used by cable operators to provide cable television (TV) services. Because of this range of services, it is likely that digital networks will be widely deployed. In a widespread deployment of digital networks, millions of homes will connect to the digital networks.
Because the majority of new video services will be digital, and because existing TVs are analog, there is a need for a device, hereinafter referred to as a Residential Gateway (RG), to convert the digital signals supplied by the network to analog signals compatible with existing TVs. Furthermore, there is a need for the RG to act as an interface subsystem for each device connected to the digital network. For example, the RG needs to act as a Premises Interface Device (PID) to extract time division multiplexed information and generate a telephone signal, and a Ethernet Bridge or Router (EBR) to generate a signal compatible with a computer.
Transmission of channel select commands associated with remotely located TVs may encounter problems related to the distance to the RG and possible obstacles therebetween. Thus, there is a need for a method and apparatus for ensuring the RG receives the channel select commands from remotely located TVs.


Disclosed are systems for converting rotational momentum into linear propulsion. A propulsion system includes one or more thrust units with masses controllably driven by actuators to generate inertia that thrusts a vehicle with the propulsion system in a desired direction. The propulsion system can be configured to have multiple units, each configured to generate thrust in a desired direction and counteract or neutralize thrust in other directions. The propulsion system can generate thrust via two operational cycles and/or through continuous operation. The propulsion system may comprise two mirroring units, each configured to operate in mirrored synchrony to generate a net thrust in a desired direction and counteract or neutralize thrust in other or undesired directions.

Propulsion thrusters, which may be alternatively referred to as propulsion systems, may be used individually or in groups to propel a vehicle, object, or entity through space. Travel through "space" may include outer space travel, aerial travel, ground travel, water travel, etc. Use of a closed propulsion system or thrusters allows for propulsion of an object or objects without the use of combustion mechanisms involving accelerated gas or working fluid.

System for converting rotational momentum into versatile linear propulsion


In an embodiment, a method for generating and distributing keys retains the scalability of a group VPN, but also provides true pair-wise keying such that an attacker who compromises one of the devices in a VPN cannot use the keys gained to decrypt the packets from the other gateways in the VPN, or spoof one of the communicating gateways. The method is collusion resistant when co-operating attackers overtake several VPN gateways and observe the keys stored in those gateways. In an embodiment, a VPN gateway comprises a cryptographic data processor configured to encrypt and to decrypt data packets; group key management logic; and Key Generation System logic. In one approach a gateway performs, in relation to adding a group member, receiving in a security association message secret data for use in the KGS; and derives keys for secure communication with one or more peer VPN gateways using the secret data.

The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.
The Group Domain of Interpretation (GDOI) as defined in M. Baugher et al., "The Group Domain of Interpretation," Request for Comments (RFC) 3547 of the Internet Engineering Task Force (IETF) (December 2002) is currently used in certain virtual private network (VPN) systems to distribute group keys to a group of VPN gateways attached to a private wide area network (WAN), such as a multi-protocol label switching (MPLS) network. In one approach, large groups of VPN gateways are configured to communicate with each other such that eavesdroppers cannot view, modify, or replay encrypted packets between sent between the gateways. Group keying can be used, and GDOI can be used to provide group keys to tunneling technologies (such as dynamic multipoint VPN [DMVPN] and Layer 2 Tunneling Protocol [L2TPv3] tunnels).
In one approach, all VPN gateways install and use the same keys. This is often an adequate level of security because each VPN gateway is trusted to pass the same data to any other gateway, and all VPN gateways are trusted identically. However, if group keys available on any VPN gateway are revealed to an attacker, then the attacker can eavesdrop on all traffic in the entire VPN. Furthermore, the attacker can inject packets claiming to be from any of the legitimate VPN gateways.
Some users may prefer that the threat of eavesdropping and spoofing be reduced or otherwise mitigated while still maintaining the scalability of the group VPN. In particular, some VPN gateways are installed on premises that are not physically secured or managed by the VPN gateway security administrators. The administrators of such VPN gateways are legitimately concerned that an attacker will obtain access to the VPN gateway and attempt to extract its keys.

Pair-wise keying for tunneled virtual private networks


A molecular interferometric imaging system for detecting an analyte in a sample, that includes an illumination source providing a beam of radiation; a pixel array for detecting radiation in an image plane; a biolayer designed to react to the analyte when it comes in contact with the sample; a substrate designed to convert phase modulation into intensity modulation which can be detected and imaged directly by the pixel array, the biolayer being on the substrate; a reference surface; an image switching means for switching between a first position for collecting a sample image of the biolayer, and a second position for collecting a reference image of the reference surface; and a processing means for producing a composite image using the sample image and the reference image for illumination normalization.

The present invention generally relates to obtaining direct images of biological molecules distributed on surfaces designed to convert molecular phase to reflected intensity. The reflected intensity is linearly proportional to protein density. Normally invisible biological molecules are made visible by the condition of in-line interferometric quadrature established by the substrate that transduces phase to intensity. The basic principle of operation is shearing in-line common-path interferometry in which a digital interferometric image of patterns of biological molecules is acquired and referenced to a reference surface by two image acquisitions. The technique has the advantage of high speed, high sensitivity and high-resolution optical detection of biological molecules.
The Quadraspec biological compact disc system described in U.S. Pat. No. 6,685,885 requires all serial data to be acquired on a single channel. However, it may also be advantageous in signal-to-noise (and hence sensitivity) applications to acquire many channels at the same time. With the present technique, a pixel array captures a plurality of pixel readings for each image. Moreover, while conventional laser scanning techniques are time-consuming when obtaining high-resolution scans of protein spots, as well as incompatible with disc wobble when scanning spots under high magnification, the present system minimizes these problems by acquiring numerous pixels in a single exposure. In addition, the focus of the microscope can be adjusted for each well, and even at a lower magnification, an entire "well" of spots can be seen in the field of view. As such, all the protein spots are acquired at the same time and under the same conditions.
Conventional laser scanning interferometric approaches are also incompatible with real-time kinetic captures from wet samples, particularly as flow-cell plumbing is impossible, except for the use of centrifugal force to move fluids. The present system can image through a flow-cell and system, thereby making it much more like surface plasmon resonance ("SPR") systems.
However, there are several advantages of the present system over SPR techniques, particularly as the present technology is easier to implement and has a higher sensitivity than SPR technology. The present system uses a non-resonant quadrature condition, thus the operating condition is relatively insensitive to spacer thickness or wavelength. SPR systems, on the other hand, are sensitive to thicknesses and require tightly constrained wavelengths and angles. The goal of quadrature detection is to suppress noise rather than to boost signal which frees it from operating-point drift and allows it to be multiplexed over large areas. The present system also has minimal restrictions on operating wavelength or angle. The quadrature conditions can be achieved at either surface-normal or higher angles. Operation at 30° is achievable without loss in sensitivity. The optimal wavelength is also defined within a relatively broad range of tens of nanometers.
Because the operation of the present system is so robust, the noise is very low, thereby giving higher signal-to-noise ratios than SPR approaches. It is anticipated that molecular interferometric imaging will have a surface mass sensitivity of one to two orders of magnitude better than SPR. In addition, the thickness of the spacer that establishes the quadrature condition does not have to be tightly constrained. A 20% drift in thickness across a platform causes almost no change in operating sensitivity. Moreover, the loose requirements on spacer thickness and operating wavelength allows a large area to be manufactured that does not have significant sensitivity drift across the platform. This allows large-area multiplexing.
Additional features and advantages of the invention will become apparent to those skilled in the art upon consideration of the following detailed description of illustrated embodiments.

Molecular interferometric imaging process and apparatus


A connector panel for plug-in units in a telecommunication system, the telecommunication system including a sub-rack or shelf having a backplane for power supply of a number of N plug-in units within the shelf and for enabling the N plug-in units within the shelf to communicate with each other; wherein the connector panel is an entity separate from the backplane and includes a number of m connectors providing an interface between n dedicated plug-in units among the N plug-in units within the shelf, with 2≤n<N and m≥n; and wherein the connector panel is configured to be removably attached at an interior wall of the shelf.

The invention is applicable, for example, to a telecommunication system using optical data transmission technology. One specific example of using this invention is in a long-haul dense wavelength division multiplexing (DWDM) transmission system, such as the hiT 7300 Optical Packet Transport platform of Coriant GmbH & Co. KG, DE. This platform is optimized for high-capacity transport of data in optical long-haul networks, at bit rates from 2.5 Gbit/s to 100 Gbit/s per wavelength and further is designed to be upgraded for 400 Gbit/s and more in the future. The key building blocks of this system include optical amplifiers, routers, optical add-drop multiplexers (OADMs), reconfigurable optical add-drop multiplexers (ROADMs), photonic cross-connects (PXCs) and additional function units, such as "hot-pluggable" transponders and multiplex transponders, with tunable XFPs (small form-factor pluggable transceivers), SFPs (10 Gbit/s small form-factor pluggable transceivers) and CFPs (100 Gbit/s form-factor pluggable transceivers) that enable easy configuration.
These and other functional units usually are provided as plug-in units to be assembled in sub-racks or shelves in a rack of a telecommunication system, such as an optical DWDM system, and may be configured according to customer demand.
Within each shelf, power supply of and communication between the plug-in units is usually performed via a so-called backplane, said backplane also connecting the plug-in units with a control board/unit usually also provided within each shelf.
U.S. Pat. No. 6,822,874 B1 and WO 2005/051006 A1 describe examples of modular telecommunication platforms using plug-in units. U.S. 2008/0304428 A1 and EP 2051453 A1 describe optical transmission networks which also are examples of systems to which the invention can be applied. Any of the network elements described therein provide examples of the plug-in units addressed above. The hiT 7300 platform of Coriant is further described in publications of Coriant and its predecessor, Nokia Siemens Networks, such as at www.coriant.com/products/hiT7300.asp. Of course, the invention is not limited to any particular platform, but can be used for any type of telecommunication system and, more specifically, optical DWDM systems.
In these kinds of systems, for particular applications or for purposes of upgrading, it may be desirable to combine two or more plug-in units into a specific package or cluster. A cluster is formed, for example, if more than one printed wiring board (PWB) is needed for one functional unit with more than one interface to the backplane. When combining several PWBs into one functional unit, dedicated connections between the PWBs are needed. In particular when clusters are formed for upgrading a telecommunication system, the preinstalled backplane often will not support the necessary dedicated connections. In the past, this issue has been addressed either by redesigning the backplane to provide the necessary connections, by configuring the printed wiring boards in such a way that a number of different printed wiring boards are combined and connected directly using board-to-board connectors to form multi-PWB plug-in module, or by combining several printed wiring boards to form a cluster using more than one backplane connection. Those clusters might form one mechanical unit, but they might also be composed of separate mechanical entities.
If different combinations of different printed wiring boards (forming different clusters) are to be connected via dedicated connections within the backplane, the amount of possible combinations is limited and the backplane costs will be increased. There is little flexibility. If additional, not predesigned combinations of PWBs shall be added later, e.g. for upgrading the telecommunication systems, a redesign of the backplane will be necessary. This leads to additional costs and interferes with backwards compatibility concerning already installed bases at a customer's site.
Combining several PWBs into clusters, forming specialized plug-in units will make the number of different individual clusters will be very high because different numbers and combinations of different PWBs will be configured as clusters. The large amount of different predesigned clusters results in higher logistic costs at manufacturing. Moreover, the weight of one cluster, which is the sum of the individual PWBs combined, will increase, making the cluster more difficult to handle. Additionally, by combining several PWBs into one cluster, it may be expected that the mean time between failures (MDPF) will decrease.
The invention provides an optical DWDM system which allows easier and more flexible modification and upgrade of the system configuration.

Connector panel for plug-in units of a telecommunication system and associated shelf


An I/Q imbalance compensation block of a RF receiver for compensating an imbalance between an in-phase component and a quadrature component of an RF signal is disclosed. The compensation block includes a conjugation block; an adaptive finite impulse response (FIR) filter; and an adder. The filter use filter coefficients iteratively updated at least partly in response to a compensated digital signal. The filter can have a complex number for at least one, but not all of filter taps, and real numbers for other filter taps. The filter can be provided with adaptation step sizes different from filter tap to filter tap. The filter can also be provided with an adaptation step size(s) varying over time. The filter can also be provided with an adaptation step size(s) divided by the square norm of the compensated signal.

1. Field
Embodiments of the invention relate to electronic devices, and more particularly, in one or more embodiments, to radio frequency receivers.
2. Description of the Related Technology
Many electronic systems operate with radio-frequency (RF) signals. Such electronic systems can include an RF receiver that processes a wireless or wired signal (for example, a radio frequency signal) received via a wireless medium, such as air, or over a wire, such as a copper cable. An RF receiver can include various components to amplify and/or filter an RF signal to recover original data carried by the RF signal.
Referring to FIG. 1, a conventional direct-conversion radio frequency (RF) receiver system will be described below. The illustrated system 100 includes an antenna 101, an input stage structure 110, an input matching network 120, a low noise amplifier (LNA) 130, a first mixer 140a, a second mixer 140b, a local oscillator 142, a phase shifter 144, a first low pass filter (LPF) 150a, a second low pass filter 150b, a first analog-to-digital converter (ADC) 160a, a second analog-to-digital converter (ADC) 160b, an adaptive I/Q compensation filter 170, an adder 180, and a baseband module 190. The adaptive I/Q compensation filter 170 and the adder 180 can be collectively referred to as an "I/Q compensation module" or "I/Q compensation block" in the context of this document. In an instance in which the receiver system is used for processing a wired signal, the antenna 101 can be omitted.
Since there are two mixers operating with 90° phase offset, the RF receiver system 100 can be referred to as using "quadrature" reception. The PQ compensation module can be used with super-heterodyne receivers, or any other RF receiver that employs quadrature reception, even if this quadrature operation occurs in only one stage of the RF receiver.
The antenna 101 is configured to receive an RF signal. The antenna 101 can be any suitable antenna for wireless signal reception. The antenna 101 provides the received wireless signal to the input stage structure 110.
The input stage structure 110 serves to receive and process the RF signal. The input stage structure 110 can include, for example, an antenna interface circuit to interface with the antenna 101, and a filter (for example, a band pass filter) to filter out signals outside of a signal band of interest. The input stage structure 110 generates a first processed signal, which is provided as an input to the input matching network 120.
The input matching network 120 serves to improve power transfer from the input stage structure 110 to the low noise amplifier 130, and to reduce signal reflection from the low noise amplifier 130. Further, the input matching network 120 can serve to improve the noise performance of the low noise amplifier 130. The input matching network 120 is configured to match the impedance of the low noise amplifier 130 with the impedance of the structure (for example, the input stage structure 110 and the antenna 101) on the opposite side of the input matching network 120 from the low noise amplifier 130. The input matching network 120 receives the first processed signal from the input stage structure 110, and generates a second processed signal z(t), which is provided as an input to the low noise amplifier 130.
The low noise amplifier 130 serves to amplify the second processed signal z(t) from the input matching network 120 to generate an amplified signal, and provides the amplified signal to the first and second mixers 140a, 140b. The low noise amplifier 130 is configured to amplify a relatively weak signal with a gain such that the effect of noise on subsequent stages of the receiver system 100 is reduced.
The first mixer 140a serves to mix the amplified signal from the low noise amplifier 130 and a first local frequency signal LOI from the phase shifter 144 to generate a first mixed signal. The first mixed signal can include the fundamental frequencies of the current signal, the first local frequency signal, harmonics thereof, and intermodulation products. The second mixer 140b serves to mix the amplified signal from the low noise amplifier 130 and a second local frequency signal LOQ from the phase shifter 144 to generate a second mixed signal. The second mixed signal can include the fundamental frequencies of the current signal, the second local frequency signal, harmonics thereof, and intermodulation products.
In the illustrated example, the first local frequency signal LOI can be used to process in-phase (I) components of the received signal while the second local frequency signal LOQ can be used to process quadrature (Q) components of the received signal. Ideally, the first and second local frequency signals LOI, LOQ should have a phase difference of 90 degrees from each other. The phase shifter 144 is configured to generate such a phase difference, using a local oscillation signal from the local oscillator 142. These components can also exist in other types of RF receivers, such as super-heterodyne or low-IF receivers.
The first and second low pass filters 150a, 150b serve to filter the first and second mixed signals, respectively, and provide the filtered mixed signals to the first and second analog-to-digital converters 160a, 160b, respectively. The first and second low pass filters 150a, 150b are for anti-aliasing, and pass frequencies up to some cut-off frequency. These filters block higher frequencies beyond this cut-off frequency.
The first and second analog-to-digital converters 160a, 160b serve to convert the filtered mixed signals from analog form into a digital signal x[n]. The first mixer 140a, the first LPF 150a, and the first ADC 160a form an in-phase or I path. The second mixer 140b, the second LPF 150b, and the second ADC 160b form a quadrature-phase or Q path. The first and second analog-to-digital converters 160a, 160b can provide the digital signal x[n] as an input to the adaptive filter 170 and the adder 180. The output of the first ADC 160a forms the real number portion of the digital signal x[n], and the output of the second ADC 160b forms the imaginary number portion of the digital signal x[n].
The adaptive filter 170 is configured to generate a compensation signal to compensate for an imbalance between the I path and the Q path. Such an imbalance can be referred to as "I/Q imbalance" or "I/Q mismatch" in the context of this document, and will be described later in detail. The adaptive filter 170 can use a feedback signal from the adder 180, and the digital signal x[n] to generate the compensation signal that is to be provided to the adder 180.
The adder 180 is configured to add the digital signal x[n] and the compensation signal, and provides the compensated signal to the baseband module 190. The baseband module 190 receives the compensated signal from the adder 180, and performs digital signal processing on the signal. The digital signal processing can include, for example, demultiplexing and decoding.
In an RF receiver such as a direct-conversion receiver, I/Q imbalance occurs, for example, when the transfer function of the I path of the receiver is different from that of the Q path of the receiver, and/or when the phase relationship between the two paths is not quite 90 degrees. Such imbalance occurs due to imperfections and variability of the analog components of an RF receiver, such as the filters, mixers, amplifiers, and ADCs. Sources of such imbalances include, but are not limited to, gain and phase mismatch of the mixers, frequency responses of low pass filters, gain and offset of ADCs, ADC-clock timing mismatch, and a non-linear I/Q imbalance. I/Q imbalance is typically unavoidable using state-of-art analog circuit implementations.
I/Q imbalance can adversely affect the performance of an RF receiver. For example, I/Q imbalance can decrease the image rejection ratio (IRR) of an RF receiver down to, for example, 20-40 dB, resulting in crosstalk or interference between mirror frequencies. Thus, I/Q imbalance reduces the signal-to-noise ratio of the receiver 100, and increase the number of bit errors for a given data rate. Thus, I/Q imbalance needs to be reduced or cancelled.
I/Q imbalance can produce an undesired image signal, which falls within the band of interest. The term "image signal" refers to an undesired signal at frequencies occupied by the desired input signal. I/Q imbalance is a potential source of interference to proper reception. The term "image rejection ratio" is a measure of image strength relative to desired signal, and can refer to a ratio of (a) power of the desired signal to (b) power of the image signal. The image rejection ratio is usually expressed in decibels (dB). A desired IRR performance can be at least 45 dB, for example, in cable-modem applications where the desired baseband signal occupies 50-70 MHz of bandwidth.
There have been various attempts to reduce or eliminate I/Q balance from RF receivers. Among others, digital signal processing techniques have been used to reduce I/Q imbalance. Some of these techniques focus on frequency-independent I/Q imbalance compensation in specific architectures and assume certain modulation schemes possibly combined with some known pilot or training data. Other techniques attempt to compensate for frequency-dependant imbalances, assuming known pilot data or using interference cancellation (IC) or blind signal separation (BSS) principles.
Among the techniques for frequency-dependent I/Q imbalance compensation, Anttila et al., "Circularity-Based I/Q Imbalance Compensation in Wideband Direct-Conversion Receivers," IEEE Transactions on Vehicular Technology, Vol. 57, No. 4, pp. 2099-2113 (July 2008), presents a blind (non-data-aided) circularity-based compensation of frequency-dependent I/Q imbalances in RF receivers.
Referring to FIG. 2A, an I/Q compensation module disclosed by Anttila et al. will be described below. The illustrated I/Q compensation module 200 includes a first node 201, a second node 202, a complex conjugation block 210, an adaptive filter 220, a delay element 225, a filter adaptation block 227, and an adder 230. A digital signal x[n] is provided to the first node 201 from the I and Q paths of a receiver, such as the I and Q paths of FIG. 1. The digital signal x[n] is provided to the adder 230 and the conjugation block 210.
In the context of this document, "n" denotes a discrete-time index, where the time-interval between indices can be found from the sampling rate. In the context of this document, a discrete-time sequence of samples "x" is referred to as "x[n]." For simplicity of notation, "x[n]" can also be used to indicate the value of the sequence "x" at time-index "n." Vectors in boldface, such as xn, will be used to refer to the vector at time-index "n."
The conjugation block 210 is configured to change the polarity of the imaginary number part of the digital signal x[n], thereby generating a complex conjugate signal x*[n] of the digital signal x[n]. For example, the digital signal x[n] can be a sequence of complex numbers. For example, let one sample in the sequence be expressed as a+jb, in which a is the real number part, jb is the imaginary number part, and j corresponds to the square root of −1. The complex conjugate x*[n] has the same real part and has an imaginary part having the same magnitude and the opposite sign. In the example above, the complex conjugate can be expressed as a−jb.
The adaptive filter 220 can be a finite impulse response (FIR) filter, whose coefficients at time-index "n" can be expressed as the vector wn. The FIR filter is a type of a discrete-time filter. The FIR filter can generate an output digital sequence v[n] as expressed in Equation 1 below.v[n]=wn[0]x[n−N+1]+wn[1]x[n−N]+ . . . +wn[i]x[n−N+i]+ . . . +wn[N−1]x[n]  Equation 1
In Equation 1, variable x[n] is the input signal, and variable v[n] is the output signal. Weights wn[i], (i=0, 1, 2, . . . , N−1) are filter coefficients at time "n," also known as tap weights. N is the filter order or length, and an (N+1)th order filter has N terms, each of which can be referred to as a tap. For example, weight wn[0] can be referred to as a first tap at time "n," which can correspond to a tap that is not delayed. Weight wn[1] can be referred to as a second tap. wn[N−1] can be referred to as an N-th tap.
The adaptation filter 220 receives a feedback signal λ yn y[n] from the adder 230 via the delay element 225 and the filter adaptation block 227. In the illustrated example, an output signal y[n] from the adder 230 is delayed by the delay element 225. The amount of a delay provided by the delay element 225 can be at least one sample. The delayed output signal is provided to the filter adaptation block 227, which generates the feedback signal λ yn y[n]. The feedback signal λ yn y[n] is used by the adaptive filter 220 to generate a compensation signal to be added to the input signal x[n] at the adder 230 to cancel or reduce I/Q imbalance.
The adaptive filter 220 is configured to perform a complex-convolution operation (*) on the conjugate signal x*[n] with the adaptive filter signal wn to generate a compensation signal expressed as x*[n]*wn. The convolution operation can be computed as the sum of the product of the two sequences after one is reversed and shifted on the time axis. The adaptive filter wn can be iteratively updated as in Equation 2 below.wn+1=wn−λyny[n]  Equation 2
In Equation 2, y[n] is the compensated signal value at time "n." This value can be expressed as y[n]=x[n]+v[n]=wnTxn, wherein wn Δ [wn[0], wn[1], wn[2], . . . , wn[N−1]]T denotes the vector of coefficients (alternatively "filter coefficients") of the compensator at time index n, and the vector xnΔ[x[n−N+1], x[n−N], . . . , x[n]]T. λ denotes the adaptation step size or adaptation rate, and ynΔ [y[n], y[n−1], . . . , y[n−N+1]]T.
The adder 230 adds the compensation signal to the digital signal x[n], and provides the compensated signal y[n] to the baseband module 190 (FIG. 1) of the receiver. The compensated signal sequence y[n] is provided as a feedback signal to the adaptive filter 220 through the delay element 225 and the filter adaptation block 227.
The technique described in the above example is blind to the received baseband signal, which is useful since a training signal need not be applied at the receiver input. The technique is adaptive in that it accounts for time-varying mismatches. The technique is also frequency-selective, and thus can be suitable for correction of wideband channels.
Equation 2, above, indicates that the technique determining filter coefficients wn blindly (i.e., without knowledge of the baseband signal) and adaptively by employing the signal "properness" property, that is, determining if y[n] is a proper signal sequence, which indicates that y[n] and y*[n] are uncorrelated. In the technique of Anttila et al., λ is a fixed training coefficient selected by the user. After convergence, the signal y[n] should exhibit the condition expressed in Equation 3 below, in which E denotes expected value operator (or expectation operator) that provides the long-run average.E[y[n−i],y[n]]=0,where i=0,1, . . . N−1.  Equation 3

Apparatus and method for adaptive I/Q imbalance compensation


A fixing device for vehicle doors includes a door lock striker, a fixed member, and a movable member. The fixed member has two inclined surfaces that are movable relative to the door lock striker and located on opposite sides of the door lock striker. The movable member has two inclined surfaces arranged on opposite sides of the door lock striker and is urged such that each inclined surface is pushed against the corresponding inclined surface of the fixed member. The door lock striker includes a leg portion. The movable member includes two bodies forming the two inclined surfaces of the movable member, and a connecting portion that connects the bodies at the rear end portions of the bodies, which are pressed towards the fixed member and moved rearward. The connecting portion has an arched shape that protrudes in the protruding direction of the leg portion.

A conventional fixing device for vehicle doors includes two members, which are arranged on a vehicle body panel and a door panel such that an inclined surface of one of the members comes into contact with a corresponding inclined surface of the other one of the members when the vehicle door is closed. The fixing device is adapted to urge and press one of the members (a movable member) against the other one of the members (a fixed member). See, for example, Patent Document 1.
That is, using the force by which the members are pressed against each other, the vehicle door in the closed state is pressed in a direction crossing the opening and closing direction of the vehicle door, or, for example, against the hinge portion, which is the motion pivot of the door. In this manner, backlash of the vehicle door is restrained through a simple configuration.


An image forming apparatus includes: a setting unit to set a printing condition of a job, the printing condition containing a condition indicating whether check print is to be executed or not; an image forming unit to execute image forming processing in accordance with the printing condition set by the setting unit; and a control unit to determine one or more pages to be subjected to the check print based on the printing condition and a predetermined determination condition if the printing condition set by the setting unit indicates that the check print is to be executed, and to cause the image forming unit to execute the image forming processing for the check print with respect to the determined one or more pages.

1. Field of the Invention
The present invention relates to an image forming apparatus having a check printing function.
2. Description of Related Art
In an image forming apparatus having a check printing function, whether an image is formed in a desired finishing style can be checked before actually printing the image. In the conventional image forming apparatus, the image forming processing for check print is executed with respect to one copy of a document. Therefore, if one copy of a document has a large number of pages, the image forming processing is executed with respect to a large number of sheets regardless of user's wishes, which causes unnecessary operations if a user does not want to check all the pages.
Therefore, there is known an image forming apparatus in which a user indicates the number of sheets to be printed in advance before check print is executed and then the check print is executed on only the indicated number of sheets (see JP-A-2003-266899, for example).
Furthermore, there is also known an image forming apparatus provided with a double-side mode, a staple mode, a reduced-layout mode in addition to a manual setting mode of indicating the number of sheets for check print by a user. In this image forming apparatus, the number of sheets for check print is automatically calculated in accordance with each of the double-side printing mode, the staple mode and the reduced-layout mode, and the check print is executed on only the calculated number of sheets (see JP-A-2004-32704, for example).
However, with respect to JP-A-2003-266899, a user must set the number of sheets to be printed for check print. With respect to JP-A-2004-32704, a user is required to set the number of sheets to be printed in each of the double-side mode, the staple mode and the reduced-layout mode by himself or herself, which is cumbersome for the user.
In conventional image forming apparatuses containing the apparatuses disclosed in JP-A-2003-266899 and JP-A-2004-32704, it is merely possible to specify the number of sheets for check print, and it is impossible to specify the pages to be targeted for check print in accordance with the purpose of the check print.
As described above, with respect to the conventional image forming apparatuses, the operation load imposed on users is great, and also it is impossible to specify the pages for check print in accordance with the purpose, so that these image forming apparatuses are inconvenient to use for users.

Konica Minolta Business Technologies, Inc.