Perfected cryptographic protocol making it possible to counter attacks based on the analysis of the current consumption during the execution of a DES or similar.

It is known that certain encrypted electronic entities, in particular microcircuit cards, are vulnerable to attacks based on the analysis of certain parameters during an operational phase. It is said that information can "leak" from a calculation made in the card, typically the execution of a cryptographic protocol initiated by the defrauder in possession of the card. The parameters analysed during the execution of such a protocol can be, typically, differences in computing time or electromagnetic radiations during the execution of the computation but, above all, the current consumption by the electronic entity for which an attempt is being made to break the code.
Thus, the conventional attack consists in causing the electronic entity which has fallen into the hands of the defrauder to execute a certain number of cryptographic protocols based on random messages, and therefore destined for failure, but having the consequence of having executed each time by the entity (the microcircuit card) a chain of operations known by the abbreviation DES (Data Encryption Standard) whilst analysing the current consumption during each execution of the said DES. The purpose of this attack is to discover the secret code of the said entity. As regards the DES, this is a well known algorithm, very widely used at present in the field of bank cards or that of access control cards.
By way of example, in the framework of a normal authentication between an entity A, for example a server, and an entity B, for example a microcircuit card in which the DES is programmed, the exchanges of information between the two entities are as follows:
the server A requests the card B to send a message, A and B being assumed to be in possession of the same key.
B sends any message and retains it in memory.
A applies the DES to the message using its key and returns the result to the card B.
At the same time, the card B applies the DES to the message which it has sent to the server A by making use of its own key. It obtains a result which is compared with that generated by the server A. If the two results are identical, the authentication is validated.
Furthermore, in the case of a fraud, that is to say in the case where the defrauder has the card and is seeking to determine the key, the defrauder can connect the card to a reader with which he will be able to transmit messages to it and connect it to means of recording the current consumption during the execution of the operations which it carries out.
On the basis of these simple means, the defrauder forms a system F which he connects to the card in place of the server A.
The process is then as follows. F requests a message from the card exactly as in the case of initialising an authentication. B sends this message. F sends another message to B presumed to be the result of treatment by the DES of the message sent by B. This message is of course incorrect. However, B makes use of its own key to execute a DES in order to obtain a result for the purpose of comparing it with the (incorrect) message sent by F. The result of this comparison is inevitably negative but the defrauder has succeeded in initiating the execution of a DES by B. During the execution of the said DES, the current consumption is detected and stored.
If F is capable of having a certain number of DES carried out by the card B, under the same conditions, and of storing the current consumption each time, it is possible to implement an attack whose principle is known. This attack, called "DPA" (Differential Power Analysis) makes it possible to reconstitute the secret key of the entity B.
The document WO 99/63696 aims at countering attacks of this type by reducing the exploitable information capable of "leaking" during the execution of algorithms. In order to do this it suggests, in particular, introducing hazards in the cryptographic protocols in order to increase the number of cycles necessary in order to discover the secret key.

Method of executing a cryptographic protocol between two electronic entities

Abstract: According to the invention, a message (M) is processed by two entities (A and B) and the entity (B) subject to attack executes a chain of operations known as DES in which it is chosen to carry out a given operation (O1, O2, O3 . . . On) or the same operation complemented (Ō1, Ō2, Ō3 . . . Ōn), the choice being random.


A method of forming anodes for electrochemical devices by laminating a metal foil to a current collector and creating anode-active-material patches, composed of the metal foil, that are spaced from one another by inter-patch regions, wherein each inter-patch region provides a location for forming one or more electrical tabs of the finished anodes. The method can further include applying conductive-coating patches to the current collector prior to laminating the metal foil to the current collector, wherein each conductive-coating patch corresponds to one of the anode-active-material patches. In some embodiments, the conductive-coating patches can assist with forming the anode-active-material patches and/or can improve the cycling performance of an electrochemical device made using anodes made therewith. Anodes containing anode-active material and conductive coatings applied to current collectors are also disclosed.

Rechargeable, or secondary, lithium-metal batteries offer volumetric and gravimetric energy densities higher than current lithium-ion batteries. Unlike lithium-ion batteries, which contain anodes (negative electrode) formed from an intercalant material such as graphite, in typical secondary lithium-metal batteries, lithium foil (anode-active material) is laminated to both sides of a copper foil (current collector) to form the conventional lithium-copper-lithium (Li/Cu/Li) anode structure. However, lithium is soft and sticky, and it is difficult by conventional roll-milling processes to produce ultra-thin (<50 um thick) lithium foil having width more than 120 mm. That width constraint consequently limits the size of the anode and cells that can be built using lamination techniques.
FIGS. 1A and 1B illustrate a conventional approach to producing conventional Li/Cu/Li anodes (represented by dashed line regions 10) using a roll-to-roll process 12 involving continuous lamination of ultra-thin lithium-foil ribbons 14A and 14B on both sides of a copper-foil web 16 to form a webbed anode precursor 18. The width, Ww, of the copper-foil web 16 is usually wider than the width, Wf, of the lithium foil, and the laminated structure typically has a bare copper region 16A along at least one edge of the copper-foil web. The bare copper region 16A is provided for forming electrical tabs 10A for enabling electrical contact to the Li/Cu/Li anodes 10 that are stamped out from the webbed anode precursor 18 when the Li/Cu/Li anodes are assembled into a stacked "jellyroll" of an electrochemical cell. Without the electrical tabs 10A, it would be difficult to connect multiple layers of the Li/Cu/Li anodes 10 in the stacked jellyroll to an external electrical lead (not shown) in the finished electrochemical cell. As mentioned above, due to the physical properties of lithium the width Wf of the lithium-foil web 16 is limited to about 120 mm when using the desired ultra-thin lithium foil, and this limits the size of the Li/Cu/Li anodes, such as the Li/Cu/Li anodes 10 of FIGS. 1A and 1B, that can be made using conventional roll-to-roll lamination techniques, which correspondingly severely limits the size of lithium-metal electrochemical cells (not shown), for example, secondary lithium-metal-battery cells, that can be made with ultra-thin-lithium-metal anodes. In turn, this limitation hampers development of lithium-metal secondary cells for applications that require high-capacity batteries for practicable operation, such as electric vehicles, among others.

Anode fabrication by pattern lamination, anodes made thereby, and electrochemical devices incorporating such anodes


A connection interface allows individuals (such as guests at a lodging facility) to use portable personal electronic devices (such as laptop computers, digital audio players, and digital audio/video players) in conjunction with a television. The connection interface device includes inputs to receive signals from various portable devices, and includes selection keys by which a guest can select a particular type of input to the television. The connection interface senses presence of video and audio signals on its inputs, and the state of the selection keys, and provides data over an in-room network with a television interface terminal. The connection interface device also routes the signals received at its inputs to corresponding inputs of the television. The television interface terminal responds to inputs from a remote control, keyboard or game controller and provides commands to the television to tune to selected channels for free-to-guest programming pay-per-view movies, video games, Internet, and other interactive services. Based on data from the connection interface, the television interface terminal can command the television to receive and play selected inputs from the connection interface.

The present invention relates to entertainment systems. In particular, the present invention is an in-room system that permits an individual to connect portable devices, such as laptop computers, digital audio players or digital audio/video players with a television.
The past two decades have seen the wide scale introduction of entertainment systems in hotels and other facilities (such as hospitals, schools, travel centers, cruise ships, etc.) to provide a variety of services to the guest through the guest room television. The services can include regular off-air television programs, pay-per-view video on demand movies, video games, Internet access, and guest services such as video shopping and video checkout.
Lodging entertainment systems include a headend which is located within the lodging facility and which is linked to guest terminals in the individual guest rooms by an MATV cable distribution system. The distribution system provides transmission of both audio/video RF signals (analog, digital or both), as well as two-way data and digital communication (typically RF) signals between the headend and guest terminals.
Typically, lodging entertainment systems are not owned by the hotel. Rather, the systems are provided by a vendor who supplies the headend equipment, and the guest room equipment (including the television, remote control, game controller, keyboard, and associated control circuitry or interface terminal which interfaces the television to the distribution system). The interface terminal may be contained in a separate set-top box, or may be on a circuit board installed within the guest room television.
Guests at lodging facilities frequently travel with electronic devices such as laptop computers, video game players, digital audio players, digital media players (like iPod, portable DVD, and MP3 players), and video recorders. In general, these guests have been unable to connect their personal electronic devices to the guest room television so they can make use of the larger screen and enhanced audio available from the guest room television. The entertainment system is usually configured to prevent guests from disconnecting or otherwise tampering with the guest room television.
Some television vendors have designed special "jack packs" to allow guests to connect personal electronic devices through the jack pack to a guest room television. An example of such a jack pack is shown in the Bambic et al. U.S. Patent Application Publication No. 2006/0075437. In general, a jack pack is designed to work only with a specific vendor's television. Control signals are provided by the jack pack to the television, and special connections and special control inputs to the television are required to interface with the jack pack. Operation of the jack pack is entirely separate from the lodging entertainment system. Thus, neither the guest nor the lodging facility obtains any benefit from the lodging entertainment system when a jack pack device is being used.

Connection interface for personal electronic devices with a television


A motorized saw has a guide rail which is arranged on at least one clamping stud and can be clamped in place between two bearing surfaces by clamping means. A clamping element is provided which is arranged on the clamping stud and in a locating opening of the guide rail and which fixes the guide rail in at least one radial direction of the clamping stud in the clamped state. A clamping element has at least one clamping surface which is formed at an end face of the clamping element and which encloses an angle of less than 90° with the longitudinal center axis of an opening of the clamping element.

The invention relates to a motorized saw of the generic type specified in the preamble of claim 1 and to a clamping element, in particular for fixing the guide rail of a motorized saw on a clamping stud.
DE 41 42 751 C1 discloses a motorized saw whose guide rail is arranged on clamping studs and is clamped in place between a bearing plate of the housing and the sprocket cover. In addition, means for the axial locking of the guide rail on the clamping studs before the fixing of the sprocket cover are provided.
In known motorized saws, there is a distance between the clamping studs and the locating opening of the guide rail, such that the guide rail can be readily put onto the clamping studs. The guide rail is fixed solely by clamping forces.


In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. An output pulse having the same width as the pulse of the clock signal is generated.

The present invention relates to a shift register which is preferably applied to, for example, a driving circuit of an image display device, and which makes it possible to miniaturize the driving circuit and also to desirably change the pulse width of an output signal, and also concerns an image display device using such a shift register.
Conventionally, in a data signal line driving circuit and a scanning signal line driving circuit of an image display device, shift registers have been widely used so as to provide synchronized timing that is applied upon sampling inputted video image data, or so as to form a scanning signal to be applied to the scanning signal lines.
In the data signal line driving circuit, a sampling signal is generated so as to write video image data derived from a video image signal in pixels through a data signal line. In this case, when a sampling signal has an overlapped portion with a sampling signal from the preceding stage or the succeeding stage, the resulting video image data fluctuates greatly, causing erroneous image data to be outputted to the data signal line. In order to solve the above-mentioned problems, a conventional shift register 101 has a circuit construction, for example, as shown in FIG. 32.
The shift register 101, shown in FIG. 32, consists of n stages, and each stage is provided with a D-type flip-flop 102, a NAND circuit 103, inverters 104a and 104b and a NOR circuit 105. To the shift register 101, two clock signals SCKxc2x7SCKB, which have phases different from each other, and a start pulse SSP are inputted.
Each of the clock signals SCKxc2x7SCKB is prepared so as to have half the sampling cycle of the inputted video image signal, and in synchronism with the clock signals SCKxc2x7SCKB, pulses are successively outputted from the shift registers 101 on the respective stages. With respect to the i-numbered stage (1xe2x89xa6ixe2x89xa6n), an output Qixe2x88x921 of the D-type flip-flop 102 on the (ixe2x88x921)-numbered stage and an output Qi of the D-type flip-flop 102 on the i-numbered stage are inputted to the NAND circuit 103 on the i-numbered stage so that an output signal NSouti is obtained.
Moreover, in order to prevent a sampling signal Si on the i-numbered stage and a sampling signal Si+1 on the (i+1)-numbered stage from overlapping each other, the output signal NSOUTi is not only directly inputted to one of the input terminals of the NOR circuit on the i-numbered NOR circuit 105, but also inputted to a delay circuit constituted by inverters 104a and 104b on two steps. Since the output of the delay circuit is inputted to the other input terminal of the NOR circuit 105, it is possible to shorten the width of the sampling signal S1 outputted from the NOR circuit 105 on the i-numbered stage.
The same process as described above is carried out on each of the shift registers 101 on the respective stages so that as illustrated in FIG. 33, sampling signals S1 to Sn having no overlapped portions with each other are obtained.
Next, referring to FIGS. 34 and 35, an explanation will be given of a conventional shift register 111 installed in a scanning signal line driving circuit.
The scanning signal line driving circuit outputs a scanning signal to each of the scanning signal lines so that video image data is successively written in pixels arranged on a display section. At this time, the pulse output has to be stopped so that the (i+1)-numbered scanning signal is not overlapped with the i-numbered scanning signal or so that a process for refreshing the video image data that has been written on the i-numbered data signal line is carried out.
Therefore, as illustrated in FIG. 34, the conventional shift register 111, installed in the scanning signal line driving circuit, consists of n stages, and each stage is provided with a D-type flip-flop 112, a NAND circuit 113 and a NOR circuit 114. Moreover, to the shift register 111, two clock signals GCKxc2x7GCKB, which have phases different from each other, a start pulse GSP and a pulse width control signal PWC are inputted.
In the shift register 111, pulses are successively outputted from the respective stages in synchronism with the clock signals GCKxc2x7GCKB. With respect to the i-numbered stage (1xe2x89xa6ixe2x89xa6n), an output Qi-1 of the D-type flip-flop 112 on the (ixe2x88x921)-numbered stage and an output Qi of the D-type flip-flop 112 on the i-numbered stage are inputted to the NAND circuit 113 on the i-numbered stage so that an output signal NOUTi is obtained. The output signals NOUT1 to NOUTn, thus obtained, are outputted in the same cycles as the respective scanning signals GL1 to GLn.
In the shift register 111, the pulse width control signal PWC is further inputted to one of the input terminals of the NOR circuit 114 on each stage. Moreover, to the other input terminal of the NOR circuit 114 on the i-numbered stage is inputted the output signal NOUTi of the-NAND circuit 113 on the i-numbered stage. Consequently, a scanning signal GLi is outputted from the NOR circuit 114 from the i-numbered stage.
The same process as described above is carried out on each of the shift registers 111 on the respective stages so that as illustrated in FIG. 35, sampling signals GL1 to GLn having no overlapped portions with each other are obtained. Therefore, the (i+1)-numbered scanning signal GLi+1 is not overlapped with the i-numbered scanning signal GLi so that a process for carrying out a refreshing process, etc. on video image data that has been written on the i-numbered data signal is provided.
Here, as illustrated in FIG. 36, in the above-mentioned D-type flip-flops 102xc2x7112, when a signal A is inputted through the D terminal and two clock signals CKxc2x7CKB are inputted through the other terminal, a signal B is outputted from the Q terminal.
However, the conventional shift registers 101xc2x7111 require circuits as shown in FIGS. 32 and 34, resulting in a problem of a bulky driving circuit.
In recent years, there have been ever-increasing demands for image display devices having a wider display screen and a narrower frame width with high precision; therefore, it is necessary to make the area of the driving circuit smaller. Moreover, in applications other than image display devices, there are high demands for simplified circuit construction of shift registers.
Moreover, with respect to a conventional shift register used for a data signal line driving circuit, an arrangement as shown in FIG. 37 is proposed. In the shift register shown in FIG. 37, an S clock signal SCK is applied with a cycle half the sampling cycle of the inputted video image signal, and an output of the shift register section P1S is successively outputted in synchronism with the clock signal.
With respect to an n-numbered stage of the shift register P1S, an output Qn on the n-numbered stage (SSRn) and an output Qnxe2x88x921 on the (nxe2x88x921)-numbered stage (SSRnxe2x88x921) are used in a NAND_Sn so as to obtain NSOUTn.
A sampling signal on the n-numbered stage is allowed to have a narrower sampling signal by using a NOR_San which takes NOR between the NSOUTnand the sampling pulse width control signal SPWC for controlling the sampling pulse width, so as not to overlap the sampling signal on the (nxe2x88x921) stage. The same process is carried out on each of the outputs of the shift registers P1S so that, as illustrated in a timing chart in FIG. 38, a sampling signal having no overlapped portion is obtained. In this case, the pulse width control signal SPWC has a frequency twice the frequency of the S clock signal SCK.
Moreover, with respect to a conventional shift register used for a scanning signal line driving circuit, an arrangement as shown in FIG. 39 is proposed. In the shift register shown in FIG. 39, a scanning signal, writes a video image signal applied to a data signal line on pixels arranged on a display section, is successively outputted. In this case, with respect to the n-numbered scanning signal, its output has to be stopped so that it is not overlapped with the (nxe2x88x921)-numbered scanning signal or so that a process for refreshing the video image data that has been written on the (nxe2x88x921)-numbered data signal line is carried out.
More specifically, referring to a circuit diagram of FIG. 39 and its timing chart of FIG. 40, an explanation will be given of the operation. In FIG. 39, the output of the shift register P1G is successively released in synchronism with a G clock signal GCK. With respect to an n-numbered stage of the shift register P1G, an output (Qn) on the n-numbered stage (GSRn) and an output (Qnxe2x88x921) on the (nxe2x88x921)-numbered stage (GSRnxe2x88x921) are used in a NAND_Gn so as to obtain NOUTn. The NOUTn are respectively outputted with the same cycle as the scanning signal.
As described earlier, with respect to the n-numbered scanning signal, its output has to be stopped so that it is not overlapped with the (nxe2x88x921)-numbered scanning signal or so that a process for refreshing the video image data that has been written on the (nxe2x88x921)-numbered data signal line is carried out or so that a precharging process, etc. is carried out. For this reason, a scanning pulse width control signal GPWC is inputted, and this and NOUTn are used in a NOR_Gn so as to obtain GLn. The GLn forms a scanning signal for driving the n-numbered scanning signal line. At this time, the pulse width control signal GPWC has a frequency twice the frequency of the G clock signal GCK.
Here, in the flip-flop circuit (D-flip-flop) constituting the shift register of FIG. 37 and FIG. 39, as illustrated in FIG. 36, the circuit construction is designed so that, when a signal A is inputted to the D-terminal with two clock signals CK and CKB being inputted through the other terminals, a signal B is outputted.
In general, the power consumption increases in proportion to the frequency, the load capacitance and the square of the voltage. Therefore, for example, in circuits that are connected to an image display device, such as those for generating video image signals for the image display device, or in image display devices, there is a tendency to reduce the driving voltage as small as possible.
For example, in a circuit using monocrystal silicon transistors such as the above-mentioned generation circuit for video image signals, the driving voltage is set to, for example, 5 V or 3.3 V, or a value not more than this value, in most cases.
In contrast, in a circuit using polycrystal silicon thin-film transistors so as to ensure a wider display area, such as pixels, a data signal line driving circuit or a scanning signal line driving circuit, since a difference of threshold voltages between substrates tends to reach as high as several volts (for example, 15 V), the reduction of the driving voltage has not been sufficiently achieved. Therefore, in the case when an input signal lower than the driving voltage of a shift register is inputted to a shift register, a level shifter for voltage-raising the input signal is installed in the shift register. In general, with respect to the input signal for the level shifter, two kinds of signals having two phases are used, and the two kinds of signals have respectively reversed phases.
More specifically, as shown in FIGS. 37 and 39, for example, when an input signal having an amplitude of approximately 5 V is inputted to each of shift registers P1S and P1G, two level shifters Ls of the three in the Figure voltage-raises clock signals SCK and GCK to reach the driving voltage (15 V) of the shift registers P1S and P1G. The outputs of these level shifters Ls are inputted to flip-flops SSR1 to SSRx and GSR1 to GSRx that constitute the shift registers P1S and P1G. In synchronism with the outputs of the level shifters Ls thus applied, the shift registers P1S and P1G are allowed to have respective outputs.
However, in various circuits using conventional shift registers as shown in FIGS. 37 and 39, that is, for example, in a data signal line driving circuit, logical circuits (NOR, etc.) are required so as to prevent the sampling signals from overlapped each other, resulting in a large driving circuit; and for example, in a scanning signal line driving circuit, logical circuits (NOR, etc.) are also required so as to prevent the scanning signals from overlapping each other, resulting in a large driving circuit.
Moreover, each of the above-mentioned pulse width control signals SPWC and GPWC has a frequency that is twice the frequency of each of an S clock signal SCK and a G clock signal GCK, resulting in a greater driving frequency.
Moreover, in the shift registers P1S and P1G, after the clock signals SCK, SCKB (with a phase reversed to SCK) and GCK, GCKB (with a phase reversed to GCK) have been shifted in their levels, they are supplied to respective flip-flops constituting the shift register; therefore, the resulting problem is that the greater the distance between the flip-flops SSR1 to SSRx and the distance between the GSR1 to GSR2, the greater the transmission distance, causing an increase in the power consumption. In other words, as the transmission distance becomes longer, the capacitance of the transmission-use signal lines becomes greater, with the result that the level shifters LS require a greater driving capability, thereby resulting in an increase in the power consumption.
Moreover, as in the case when the driving circuit containing level shifters LS is constructed by using polycrystal silicon thin-film transistors, when the level shifter LS has only an insufficient capability, a buffer BUF having a great driving capability needs to be installed immediately after the level shifter LS so as to transmit signal waveaforms that are free from rounding; this further causes an increase in the power consumption.
In recent years, there have been ever-increasing demands for image display devices with high precision having a wider display screen and narrower portions other than the display area; therefore, the frequency of clock signals has to be increased, and in response to this, it is required that the number of the stages of the shift registers P1S and P1G be increased and that the area of the driving circuit be minimized.
The first objective of the present invention is to provide a shift register which has output pulses on respective stages that are free from overlapped portions and which makes it possible to miniaturize the driving circuit and also to desirably change the pulse width of an output signal, and an image processing apparatus which can achieve a narrower frame width with the driving circuit simplified by applying such a shift register.
Moreover, the second objective of the present invention is to provide a shift register which can achieve a narrower frame width by simplifying the driving circuit, and is operated normally even in the case of a low amplitude of a clock signal with reduced power consumption, and an image display device using such a shift register.
In order to achieve the first objective, the shift register of the present invention is provided with: flip-flops of a plurality of stages to which a clock signal is inputted and switching means that is installed in each of the flip-flops of a plurality of stages and that controls the input of the clock signal. In this arrangement, in response to the output signal of the flip-flop on the i-numbered stage (where i is an arbitrary integer) among the flip-flops of the stages, the switching means on the (i+1)-numbered stage is controlled so that the input of the clock signal to the flip-flop on the (i+1)-numbered stage is controlled and an output pulse having the same width as the pulse width of the clock signal is generated.
In the above-mentioned shift register, the output of the flip-flop that is operated in synchronism with the clock signal controls the clock signal to be supplied to the flip-flop on the next stage through the switching means. Here, this controlled clock signal forms an output on the corresponding stage, and the output is allowed to have the same pulse width as the clock signal.
Conventionally, the output of the flip-flop on the preceding stage and the output of that of the present stage have been subjected to a logical operation so as to generate a signal having the same pulse width as the clock signal; however, in the shift register of the present invention, it is not necessary to install the circuit for carrying out the above-mentioned logical operation. Moreover, in the logical operation section, the output from the logical operation section tends to have a partially overlapped portion due to delay (delay in the rising-edge or trailing-edge of the signal) of signals occurring in the logical operation section; however, the shift register of the present invention makes it possible to eliminate the partially overlapped portion of the output of the logical operation section. Furthermore, it is possible to eliminate a special circuit and a transmission line for a special signal for preventing the overlapped portion of the output pulse; therefor, it becomes possible to greatly reduce the size of the shift register.
Therefore, it is possible to provide a shift register which has no overlapped portion in the output pulses from the respective stages and which achieves a simplified circuit construction.
Moreover, in order to achieve the first objective, the image display device of the present invention, which is provided with a display section constituted by a plurality of pixels arranged in a matrix format, a data signal line driving circuit, connected to a plurality of data signal lines, for supplying to the respective data signal lines image data to be written in the pixels, and a scanning signal line driving circuit, connected to a plurality of scanning signal lines, for supplying to the scanning signal lines a scanning signal for controlling a writing operation of the image data to the pixels, is characterized in that the shift register of the present invention is installed at least in either the data signal line driving circuit or the scanning signal line driving circuit.
In the above-mentioned image display device, the application of the shift register of the present invention makes it possible to minimize the circuit scale of the driving circuit and consequently to provide an image processing apparatus which can achieve a narrower frame width.
Moreover, in order to achieve the second objective, the shift register of the present invention, which is provided with flip-flops of a plurality of stages that operate in synchronism with clock signals and level shifters for voltage-raising the clock signals to be inputted to the flip-flops on a plurality of stages, is characterized in that the level shifter is installed in each of the flip-flops on a plurality of stages, and in that supposing that n is an integer not less than 1, in accordance with the output signal of the flip-flop on the n-numbered stage, a pulse that is voltage-raised with the same width of the pulse width of the clock signal by the level shifter on the (n+1)-numbered stage is inputted to the flip-flop on the (n+1)-numbered stage, and is also outputted as an output signal of the shift register.
For example, the present shift register is provided with flip-flops of a plurality of stages that operate in synchronism with clock signals, level shifters, each of which, in the case when the clock signal has a voltage value lower than the power supply voltage, voltage-raises the clock signal for each of the flip-flops on a plurality of stages, and control means for controlling the operation of the level shifter, each of the level shifters and the control means being placed for each of the flip-flops on a plurality of stages. In this arrangement, in accordance with the output signal of the flip-flop on the n-numbered stage of a plurality of stages, the level shifter is controlled by the control means on the (n+1)-numbered stage and the clock signal is voltage-raised and inputted thereto so that the flip-flop on the (n+1) numbered stage is operated, and a pulse which has been voltage-raised so as to have the same width as the pulse width of the clock signal, is outputted.
In the above-mentioned shift register, the output of each of the flip-flops, which is operated in synchronism with the clock signal, is allowed to activate a level shifter that voltage-raises the clock signal to be supplied to the flip-flop on the next stage; thus, it is possible to activate only one portion of the level shifters installed inside the shift register. This voltage-raised clock signal is allowed to form an output (SL1, etc.) of the shift register, which has the same pulse width as the clock signal.
Conventionally, level shifters are installed outside a shift register, and the clock signal is once voltage-raised to a driving voltage, and this is supplied to a plurality of flip-flops constituting the shift register. Moreover, a large buffer is provided so as to prevent the voltage-raised clock signal from being subjected to rounding and delay due to the capacitance of transmission lines, the gate capacitance of transistors connected thereto, etc.; therefore, due to these capacitances and high electric potential after having been raised, as also described in the Prior Art section, the power consumption increases in accordance with the expression, Power P=Capacitance Cxc3x97Frequency fxc3x97a square of Voltage V, resulting in a great increase in the power consumption of the circuit.
In contrast, in accordance with the construction of the present invention, a low-voltage clock signal is transferred and each flip-flop is installed immediately after a level shifter so that one portion of the level shifter splaced in side the shift register are operated; thus, it becomes possible to greatly reduce the power consumption.
In addition, since it is not necessary to install a circuit (NOR, etc.) for carrying out logical operations, the size of the driving circuit can be reduced. Moreover, in the logical operation section, the output from the logical operation section tends to have a partially overlapped portion due to delay (delay in the rising-edge or trailing-edge of the signal) of signals occurring in the logical operation section; however, the present invention makes it possible to eliminate the partially overlapped portion of the output of the logical operation section. Furthermore, it is possible to eliminate a special circuit and a transmission line for a special signal (SPWC, etc.) for eliminating the overlapped portion of the output pulse; therefore, it becomes possible to greatly reduce the size of the driving circuit.
In order to achieve the second objective, the image display device of the present invention is provided with a display section which is provided with: a plurality of pixels arranged in a matrix format; a plurality of data signal lines placed on the respective columns of the pixels and a plurality of scanning signal lines placed on the respective rows of the pixels and which displays an image on the pixel by a data signal that is sent from the data signal line to each pixel in synchronism with a scanning signal supplied from each scanning signal line so as to form an image; a scanning signal driving circuit for successively supplying scanning signals having different timing from each other to the scanning signal lines in synchronism with a first clock having a predetermined cycle; and a data signal line driving circuit for extracting data signals applied onto the respective pixels on the scanning signal line to which the scanning signal has been applied, from a video image signal that has been successively applied in synchronism with a second clock having a predetermined cycle and is representative of a display state of each pixel, and for outputting the resulting data to each of the data signal lines. In the image display device having the above-mentioned arrangement, at least either the data signal line driving circuit and the scanning signal line driving circuit is provided with either of the above-mentioned shift registers having the first or second clock signal as a clock signal.
For example, the above-mentioned scanning signal driving circuit successively outputs the scanning signal to the scanning signal lines in synchronism with a predetermined timing signal. Further, the data signal line driving circuit successively outputs the video image signal to the data signal lines in synchronism with a predetermined timing signal.
In general, in the image display device, as the number of data signal lines or the number of scanning signal lines increases, the number of the flip-flops for generating timing for each signal line increases, thereby making the distance between the two ends of the flip-flop longer. Here, in the shift register of each of the above-mentioned arrangements, the driving capability of the level shifter is small, and even when the distance between the two ends of the flip-flop is long, it is possible to eliminate a buffer, and consequently to reduce the power consumption. Therefore, by installing the shift register having any one of the above-mentioned arrangements in at least either the data signal line driving circuit or the scanning signal line driving circuit, it is possible to reduce the power consumption, to miniaturize the circuit scale of the shift register and also to provide a narrower frame width in the image display device.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.


A lighting apparatus is provided with a housing having an upper assembly, a lower assembly, and a middle assembly. A lighting module is positioned within the housing in which the lighting module includes at least one light emitting diode (LED). A reflector is positioned within an outer lens of the middle portion of the housing above the lighting module. A reflector plate is positioned within the housing at approximately the same level or below the lighting module. The reflector plate is configured to reflect light emitted by the at least one LED after the light is reflected by the reflector. The outer lens is configured to refract light emitted by the at least one LED after the light has been reflected by the reflector.

1. Field of Invention
The present invention generally relates to a lighting apparatus. More particularly, the present invention relates to a lighting apparatus that uses light emitting diodes (LEDs) to perform indirect lighting.
2. Description of the Background of the Invention
Traditionally, many lamps have used incandescent or high intensity discharge (HID) light sources. When mounted to a structure, such as a ceiling or a wall, such lamps may emit light directly through a lens below the light source. Recently, however, LEDs have been found to be very efficient light sources as compared to incandescent and HID light sources. As such, converting lighting systems from using HID and incandescent lights to LED lights in order to make use of LED efficiencies is desirable.
The use of point sources such as LEDs in some instances, however, can cause undesirable glare. A phenomenon known as cave effect may also occur if all or nearly all light is directed downwards while little to no light is directed upwards. The use of LEDs may also pose challenges with heat dissipation as LEDs can generate nontrivial amounts of thermal energy.
Various sensors can be used to conserve energy by allowing a lighting apparatus to only turn on when needed. Some light fixtures have sensors positioned outside the light fixture or near the exterior of the light fixture. However, by being exposed outside the housing of the lighting fixture, the sensors may become damaged, especially in areas of vehicle activity such as in a parking structure.
Accordingly, there is a need for an LED lighting apparatus that reduces undesirable glare and provides efficient thermal management within the lighting apparatus. Additionally, there is a need for a lighting apparatus that reduces the potential for sensor damage without inhibiting the operation of the sensor used with the lighting apparatus.

Lighting apparatus with reflector and outer lens


The present invention is directed to bi-specific monovalent diabodies that comprise two polypeptide chains and which possess at least one binding site specific for an epitope of CD3 and one binding site specific for an epitope of gpA33 (i.e., a “gpA33×CD3 bi-specific monovalent diabody”). The present invention also is directed to bi-specific monovalent diabodies that comprise an immunoglobulin Fc Domain (“bi-specific monovalent Fc diabodies”) and are composed of three polypeptide chains and which possess at least one binding site specific for an epitope of gpA33 and one binding site specific for an epitope of CD3 (i.e., a “gpA33×CD3 bi-specific monovalent Fc diabody”). The bi-specific monovalent diabodies and bi-specific monovalent Fc diabodies of the present invention are capable of simultaneous binding to gpA33 and CD3. The invention is directed to pharmaceutical compositions that contain such bi-specific monovalent diabodies or such bi-specific monovalent Fc diabodies. The invention is additionally directed to methods for the use of such diabodies in the treatment of cancer and other diseases and conditions.

Field of the Invention
The present invention is directed to bi-specific monovalent diabodies that comprise two polypeptide chains and which possess one binding site specific for an epitope of gpA33 and one binding site specific for an epitope of CD3 (i.e., a "gpA33×CD3 bi-specific monovalent diabody"). The present invention also is directed to bi-specific monovalent diabodies that comprise an immunoglobulin Fc Domain ("bi-specific monovalent Fc diabodies") and are composed of three polypeptide chains and which possess one binding site specific for an epitope of gpA33 and one binding site specific for an epitope of CD3 (i.e., a "gpA33×CD3 bi-specific monovalent Fc diabody"). The bi-specific monovalent diabodies and bi-specific monovalent Fc diabodies of the present invention are capable of simultaneous binding to gpA33 and CD3. The invention is directed to pharmaceutical compositions that contain such bi-specific monovalent diabodies or such bi-specific monovalent Fc diabodies. The invention is additionally directed to methods for the use of such diabodies in the treatment of cancer and other diseases and conditions.
Description of Related Art
I. gpA33
Colorectal cancer is among the most common malignancies of the Western world and is a leading cause of cancer deaths (Silverberg, E. et al. (1989) "Cancer Statistics, 1989," CA Cancer J Clin. 39(1):3-20). One potentially useful target for colon cancer is the 43 kD transmembrane glycoprotein A33 (gpA33) ((Heath, J. K. et al. (1997) "The Human A33 Antigen Is A Transmembrane Glycoprotein And A Novel Member Of The Immunoglobulin Superfamily," Proc. Natl. Acad. Sci. (U.S.A.) 94(2):469-474; Ritter, G. et al. (1997) "Characterization Of Posttranslational Modifications Of Human A33 Antigen, A Novel Palmitoylated Surface Glycoprotein Of Human Gastrointestinal Epithelium," Biochem. Biophys. Res. Commun. 236(3):682-686). gpA33 was first discovered through raising monoclonal murine antibodies against the human pancreatic carcinoma derived cell line ASPC1. One antibody (MAb A33) was found to react with a surface cell protein of 43 kDa, which was therefore designated "gpA33" (Wong, N. A. et al. (2006) "EpCAM and gpA33 Are Markers Of Barrett's Metaplasia," J. Clin. Pathol. 59(3):260-263).
gpA33 is a transmembrane protein of the junctional adhesion molecule family; Abud, H. E. et al. (2000) "The Murine A33 Antigen Is Expressed At Two Distinct Sites During Development, The ICM Of The Blastocyst And The Intestinal Epithelium," Mech. Dev. 98(1-2):111-114; Barendswaard, E. C. et al. (1998) "Rapid And Specific Targeting Of Monoclonal Antibody A33 To A Colon Cancer Xenograft In Nude Mice," Int. J. Oncol. 12(1):45-53; Panjideh, H. et al. (2008) "Biodistribution And Efficacy Of [131I] A33scFv::CDy, A Recombinant Antibody-Enzyme Protein For Colon Cancer," Int. J. Oncol. 32(4):925-930). Although the functional significance of the A33 antigen is not yet understood, it has been shown to mediate colonic mucosal repair in an animal model of colitis and is homogeneously expressed in >95% of all colorectal carcinomas. A33 expression is uniform across both disease stage and degree of histological differentiation, and the antigen is not detectably secreted or shed into the blood stream (Infante, J. R. et al. (2013) "Safety, Pharmacokinetics And Pharmacodynamics Of The Anti-A33 Fully-Human Monoclonal Antibody, KRN330, In Patients With Advanced Colorectal Cancer," Eur. J. Cancer. 49(6):1169-1175; Panjideh, H. et al. (2008) "Biodistribution And Efficacy Of [131I] A33scFv::CDy, A Recombinant Antibody-Enzyme Protein For Colon Cancer," Int. J. Oncol. 32(4):925-930). Conversely, only a few instances of non-gastrointestinal A33 antigen expression have been identified (Johnstone, C. N. et al. (2000) "Characterization Of Mouse A33 Antigen, A Definitive Marker For Basolateral Surfaces Of Intestinal Epithelial Cells," Am. J. Physiol. Gastrointest. Liver Physiol. 279(3):G500-G510).
In light of the highly restricted expression of the A33 antigen, researchers have explored the possibility of treating A33-associated cancers with antibodies (Infante, J. R. et al. (2013) "Safety, Pharmacokinetics And Pharmacodynamics Of The Anti-A33 Fully-Human Monoclonal Antibody, KRN330, In Patients With Advanced Colorectal Cancer," Eur. J. Cancer. 49(6):1169-1175; Ackerman, M. E. et al. (2008) "A33 Antigen Displays Persistent Surface Expression," Cancer Immunol. Immunother. 57(7):1017-1027; Barendswaard, E. C. et al. (2001) "Relative Therapeutic Efficacy Of (125)I-And (131)I-Labeled Monoclonal Antibody A33 In A Human Colon Cancer Xenograft," J. Nucl. Med. 42(8):1251-1256; Carrasquillo, J. A. et al. (2011) "(124)I-huA33 Antibody PET Of Colorectal Cancer," J. Nucl. Med. 52(8):1173-1180; Chong, G. et al. (2005) "Phase I Trial Of 131I-HuA33 In Patients With Advanced Colorectal Carcinoma," Clin. Cancer Res. 11(13):4818-4826; Deckert, P. M. et al. (2000) "Pharmacokinetics And Microdistribution Of Polyethylene Glycol-Modified Humanized A33 Antibody Targeting Colon Cancer Xenografts," Int. J. Cancer. 87(3):382-390; Johnston, A. P. et al. (2012) "Targeting Cancer Cells: Controlling The Binding And Internalization Of Antibody-Functionalized Capsules" ACS Nano. 6(8):6667-6674; Koppe, M. J. et al. (2005) "Radioimmunotherapy And Colorectal Cancer," Br. J. Surg. March; 92(3):264-276; Sakamoto, J. et al. (2006) "A Phase I Radioimmunolocalization Trial Of Humanized Monoclonal Antibody HuA33 In Patients With Gastric Carcinoma," Cancer Sci. 97(11):1248-1254; Scott, A. M. et al. (2005) "A Phase I Trial Of Humanized Monoclonal Antibody A33 In Patients With Colorectal Carcinoma: Biodistribution, Pharmacokinetics, And Quantitative Tumor Uptake," Clin. Cancer Res. 11(13):4810-4817; Tschmelitsch, J. et al. (1997) "Enhanced Antitumor Activity Of Combination Radioimmunotherapy (131I-Labeled Monoclonal Antibody A33) With Chemotherapy (Fluorouracil)," Cancer Res. 57(11):2181-2186). Likewise fragments of such antibodies have also been evaluated for their potential therapeutic role (Coelho, V. et al. (2007) "Design, Construction, And In Vitro Analysis Of A33scFv::CDy, A Recombinant Fusion Protein For Antibody-Directed Enzyme Prodrug Therapy In Colon Cancer," Int. J. Oncol. 31(4):951-957).
II. CD3
CD3 is a T cell co-receptor composed of four distinct chains (Wucherpfennig, K. W. et al. (2010) "Structural Biology Of The T-Cell Receptor: Insights Into Receptor Assembly, Ligand Recognition, And Initiation Of Signaling," Cold Spring Harb. Perspect. Biol. 2(4):a005140; pages 1-14; Chetty, R. et al. (1994) "CD3: Structure, Function And The Role Of Immunostaining In Clinical Practice," J. Pathol. 173:303-307).
In mammals, the CD3 complex contains a CD3γ chain, a CD3δ chain, and two CD3ϵ chains. These chains associate with a molecule known as the T cell receptor (TCR) in order to generate an activation signal in T lymphocytes. In the absence of CD3, TCRs do not assemble properly and are degraded (Thomas, S. et al. (2010) "Molecular Immunology Lessons From Therapeutic T-Cell Receptor Gene Transfer," Immunology 129(2):170-177). CD3 is found bound to the membranes of all mature T cells, and in virtually no other cell type (see, Janeway, C. A. et al. (2005) In: IMMUNOBIOLOGY: THE IMMUNE SYSTEM IN HEALTH AND DISEASE," 6th ed. Garland Science Publishing, NY, pp. 214-216; Sun, Z. J. et al. (2001) "Mechanisms Contributing To T Cell Receptor Signaling And Assembly Revealed By The Solution Structure Of An Ectodomain Fragment Of The CD3ϵ:γ Heterodimer," Cell 105(7):913-923; Kuhns, M. S. et al. (2006) "Deconstructing The Form And Function Of The TCR/CD3 Complex," Immunity. 2006 February; 24(2):133-139).
III. Bi-Specific Diabodies
The ability of an intact, unmodified antibody (e.g., an IgG) to bind an epitope of an antigen depends upon the presence of variable domains on the immunoglobulin light and heavy chains (i.e., the VL and VH domains, respectively). The design of a diabody is based on the single chain Fv construct (scFv) (see, e.g., Holliger et al. (1993) "'Diabodies': Small Bivalent And Bispecific Antibody Fragments," Proc. Natl. Acad. Sci. (U.S.A.) 90:6444-6448; US Patent Publication No. 2004/0058400 (Holliger et al.); US 2004/0220388 (Mertens et al.); Alt et al. (1999) FEBS Lett. 454(1-2):90-94; Lu, D. et al. (2005) "A Fully Human Recombinant IgG-Like Bispecific Antibody To Both The Epidermal Growth Factor Receptor And The Insulin-Like Growth Factor Receptor For Enhanced Antitumor Activity," J. Biol. Chem. 280(20):19665-19672; WO 02/02781 (Mertens et al.); Olafsen, T. et al. (2004) "Covalent Disulfide-Linked Anti-CEA Diabody Allows Site-Specific Conjugation And Radiolabeling For Tumor Targeting Applications," Protein Eng. Des Sel. 17(1):21-27; Wu, A. et al. (2001) "Multimerization Of A Chimeric Anti-CD20 Single Chain Fv-Fc Fusion Protein Is Mediated Through Variable Domain Exchange," Protein Engineering 14(2):1025-1033; Asano et al. (2004) "A Diabody For Cancer Immunotherapy And Its Functional Enhancement By Fusion Of Human Fc Region," Abstract 3P-683, J. Biochem. 76(8):992; Takemura, S. et al. (2000) "Construction Of A Diabody (Small Recombinant Bispecific Antibody) Using A Refolding System," Protein Eng. 13(8):583-588; Baeuerle, P. A. et al. (2009) "Bispecific T-Cell Engaging Antibodies For Cancer Therapy," Cancer Res. 69(12):4941-4944).
Interaction of an antibody light chain and an antibody heavy chain and, in particular, interaction of its VL and VH domains forms one of the epitope binding sites of the antibody. In contrast, the scFv construct comprises a VL and VH Domain of an antibody contained in a single polypeptide chain wherein the domains are separated by a flexible linker of sufficient length to allow self-assembly of the two domains into a functional epitope binding site. Where self-assembly of the VL and VH domains is rendered impossible due to a linker of insufficient length (less than about 12 amino acid residues), two of the scFv constructs interact with one another other to form a bivalent molecule in which the VL of one chain associates with the VH of the other (reviewed in Marvin et al. (2005) "Recombinant Approaches To IgG-Like Bispecific Antibodies," Acta Pharmacol. Sin. 26:649-658).
Natural antibodies are capable of binding to only one epitope species (i.e., mono-specific), although they can bind multiple copies of that species (i.e., exhibiting bi-valency or multi-valency). The art has noted the capability to produce diabodies that differ from such natural antibodies in being capable of binding two or more different epitope species (i.e., exhibiting bi-specificity or multispecificity in addition to bi-valency or multi-valency) (see, e.g., Holliger et al. (1993) "'Diabodies': Small Bivalent And Bispecific Antibody Fragments," Proc. Natl. Acad. Sci. (U.S.A.) 90:6444-6448; US 2004/0058400 (Holliger et al.); US 2004/0220388 (Mertens et al.); Alt et al. (1999) FEBS Lett. 454(1-2):90-94; Lu, D. et al. (2005) "A Fully Human Recombinant IgG-Like Bispecific Antibody To Both The Epidermal Growth Factor Receptor And The Insulin-Like Growth Factor Receptor For Enhanced Antitumor Activity," J. Biol. Chem. 280(20):19665-19672; WO 02/02781 (Mertens et al.); Mertens, N. et al., "New Recombinant Bi- and Trispecific Antibody Derivatives," In: NOVEL FRONTIERS IN THE PRODUCTION OF COMPOUNDS FOR BIOMEDICAL USE, A. VanBroekhoven et al. (Eds.), Kluwer Academic Publishers, Dordrecht, The Netherlands (2001), pages 195-208; Wu, A. et al. (2001) "Multimerization Of A Chimeric Anti-CD20 Single Chain Fv-Fc Fusion Protein Is Mediated Through Variable Domain Exchange," Protein Engineering 14(2):1025-1033; Asano et al. (2004) "A Diabody For Cancer Immunotherapy And Its Functional Enhancement By Fusion Of Human Fc Region," Abstract 3P-683, J. Biochem. 76(8):992; Takemura, S. et al. (2000) "Construction Of A Diabody (Small Recombinant Bispecific Antibody) Using A Refolding System," Protein Eng. 13(8):583-588; Baeuerle, P. A. et al. (2009) "Bispecific T-Cell Engaging Antibodies For Cancer Therapy," Cancer Res. 69(12):4941-4944).
The provision of non-monospecific diabodies provides a significant advantage: the capacity to co-ligate and co-localize cells that express different epitopes. Bivalent diabodies thus have wide-ranging applications including therapy and immunodiagnosis. Bi-valency allows for great flexibility in the design and engineering of the diabody in various applications, providing enhanced avidity to multimeric antigens, the cross-linking of differing antigens, and directed targeting to specific cell types relying on the presence of both target antigens. Due to their increased valency, low dissociation rates and rapid clearance from the circulation (for diabodies of small size, at or below ˜50 kDa), diabody molecules known in the art have also shown particular use in the field of tumor imaging (Fitzgerald et al. (1997) "Improved Tumour Targeting By Disulphide Stabilized Diabodies Expressed In Pichia pastoris," Protein Eng. 10:1221). Of particular importance is the co-ligating of differing cells, for example, the cross-linking of cytotoxic T cells to tumor cells (Staerz et al. (1985) "Hybrid Antibodies Can Target Sites For Attack By T Cells," Nature 314:628-631, and Holliger et al. (1996) "Specific Killing Of Lymphoma Cells By Cytotoxic T-Cells Mediated By A Bispecific Diabody," Protein Eng. 9:299-305).
Diabody epitope binding domains may also be directed to a surface determinant of any immune effector cell such as CD3, CD16, CD32, or CD64, which are expressed on T lymphocytes, natural killer (NK) cells or other mononuclear cells. In many studies, diabody binding to effector cell determinants, e.g., Fcγ receptors (FcγR), was also found to activate the effector cell (Holliger et al. (1996) "Specific Killing Of Lymphoma Cells By Cytotoxic T-Cells Mediated By A Bispecific Diabody," Protein Eng. 9:299-305; Holliger et al. (1999) "Carcinoembryonic Antigen (CEA)-Specific T-cell Activation In Colon Carcinoma Induced By Anti-CD3×Anti-CEA Bispecific Diabodies And B7×Anti-CEA Bispecific Fusion Proteins," Cancer Res. 59:2909-2916; WO 2006/113665; WO 2008/157379; WO 2010/080538; WO 2012/018687; WO 2012/162068). Normally, effector cell activation is triggered by the binding of an antigen bound antibody to an effector cell via Fc-FcγR interaction; thus, in this regard, diabody molecules of the invention may exhibit Ig-like functionality independent of whether they comprise an Fc Domain (e.g., as assayed in any effector function assay known in the art or exemplified herein (e.g., ADCC assay)). By cross-linking tumor and effector cells, the diabody not only brings the effector cell within the proximity of the tumor cells but leads to effective tumor killing (see e.g., Cao et al. (2003) "Bispecific Antibody Conjugates In Therapeutics," Adv. Drug. Deliv. Rev. 55:171-197).
However, the above advantages come at salient cost. The formation of such non-monospecific diabodies requires the successful assembly of two or more distinct and different polypeptides (i.e., such formation requires that the diabodies be formed through the heterodimerization of different polypeptide chain species). This fact is in contrast to mono-specific diabodies, which are formed through the homodimerization of identical polypeptide chains. Because at least two dissimilar polypeptides (i.e., two polypeptide species) must be provided in order to form a non-monospecific diabody, and because homodimerization of such polypeptides leads to inactive molecules (Takemura, S. et al. (2000) "Construction Of A Diabody (Small Recombinant Bispecific Antibody) Using A Refolding System," Protein Eng. 13(8):583-588), the production of such polypeptides must be accomplished in such a way as to prevent covalent bonding between polypeptides of the same species (Takemura, S. et al. (2000) "Construction Of A Diabody (Small Recombinant Bispecific Antibody) Using A Refolding System," Protein Eng. 13(8):583-588). The art has therefore taught the non-covalent association of such polypeptides (see, e.g., Olafsen et al. (2004) "Covalent Disulfide-Linked Anti-CEA Diabody Allows Site-Specific Conjugation And Radiolabeling For Tumor Targeting Applications," Prot. Engr. Des. Sel. 17:21-27; Asano et al. (2004) "A Diabody For Cancer Immunotherapy And Its Functional Enhancement By Fusion Of Human Fc Region," Abstract 3P-683, J. Biochem. 76(8):992; Takemura, S. et al. (2000) "Construction Of A Diabody (Small Recombinant Bispecific Antibody) Using A Refolding System," Protein Eng. 13(8):583-588; Lu, D. et al. (2005) "A Fully Human Recombinant IgG-Like Bispecific Antibody To Both The Epidermal Growth Factor Receptor And The Insulin-Like Growth Factor Receptor For Enhanced Antitumor Activity," J. Biol. Chem. 280(20):19665-19672).
However, the art has recognized that bi-specific monovalent diabodies composed of non-covalently-associated polypeptides are unstable and readily dissociate into non-functional monomers (see, e.g., Lu, D. et al. (2005) "A Fully Human Recombinant IgG-Like Bispecific Antibody To Both The Epidermal Growth Factor Receptor And The Insulin-Like Growth Factor Receptor For Enhanced Antitumor Activity," J. Biol. Chem. 280(20):19665-19672).
In the face of this challenge, the art has succeeded in developing stable, covalently bonded heterodimeric non-monospecific diabodies (see, e.g., WO 2006/113665; WO/2008/157379; WO 2010/080538; WO 2012/018687; WO/2012/162068; Johnson, S. et al. (2010) "Effector Cell Recruitment With Novel Fv-Based Dual-Affinity Re-Targeting Protein Leads To Potent Tumor Cytolysis And In Vivo B-Cell Depletion," J. Molec. Biol. 399(3):436-449; Veri, M. C. et al. (2010) "Therapeutic Control Of B Cell Activation Via Recruitment Of Fcgamma Receptor IIb (CD32B) Inhibitory Function With A Novel Bispecific Antibody Scaffold," Arthritis Rheum. 62(7):1933-1943; Moore, P. A. et al. (2011) "Application Of Dual Affinity Retargeting Molecules To Achieve Optimal Redirected T-Cell Killing Of B-Cell Lymphoma," Blood 117(17):4542-4551; US Patent Publications No. 2012/0294796 and 2013/0149236). Such approaches involve engineering one or more cysteine residues into each of the employed polypeptide species. For example, the addition of a cysteine residue to the C-terminus of such constructs has been shown to allow disulfide bonding between the polypeptide chains, stabilizing the resulting heterodimer without interfering with the binding characteristics of the bivalent molecule.
Diabodies and other immunoglobulins have been described purporting to have specificity for either or both of gpA33 and CD3 (see, e.g., US Patent Publications No. 2012/0014957; 2012/0034160; 2012/0087858; 2012/0189541; 2012/0195900; 2012/0201746; 2012/0237442; 2012/0263722; 2012/0258108; and 2012/0276608).
Notwithstanding such success, the production of stable, functional heterodimeric, non-monospecific diabodies can be further improved by the careful consideration and placement of the domains employed in the polypeptide chains. The present invention is thus directed to the provision of specific polypeptides that are particularly designed to form, via covalent bonding, heterodimeric diabodies and heterodimeric Fc diabodies that are capable of simultaneously binding gpA33 and CD3.

Bi-specific monovalent diabodies that are capable of binding to gpA33 and CD3, and uses thereof


An optical fiber having a multi-step core structure, and a method of fabricating the same, are provided. The optical fiber includes a central core having a predetermined radius a1 from an central axis and a refractive index n1, a first outer core having a radius a2 and a refractive index n2 smaller than the refractive index n1 and surrounding the central core, a second outer core having a radius a3 and a refractive index n3 smaller than the refractive index n2 and surrounding the first outer core, and a cladding having a radius a4 and a refractive index n0 smaller than the refractive index n3 and surrounding the second outer core, i.e., a1<a2<a3<a4 and n1>n2>n3>n0. The diameter of the core is increased by making the refractive index distribution of the core multi-stepped, thus providing easy fabrication. The optical fiber has a low dispersion value in a 1550 nm wavelength, thus making superspeed long distance transmission possible.

1. Field of the Invention
The present invention relates to a single mode optical fiber having low dispersion and low loss in a 1550 nm wavelength baseband, and more particularly, to an optical fiber having a multi-step core structure and a method of fabricating the same.
2. Description of the Related Art
As techniques for super high speed optical transmission and large capacity communications are rapidly being developed of late, loss and dispersion of an optical fiber restrict transmission at super high speeds and with large capacity. In order to overcome the restriction due to optical fiber loss, a single mode fiber of silica uses a 1550 nm wavelength region in which the loss value is the lowest, and uses an optical amplifier which can amplify an optical signal in the 1550 nm wavelength region. Accordingly, the loss no longer restricts the large capacity transmission at super high speeds, and control of the dispersion is being mentioned as a relatively important technical problem.
However, a typical single mode optical fiber, the most widely used at the present time, is designed to have a dispersion value of zero in a 1310 nm wavelength region. Thus, even though loss is low in a 1550 nm wavelength region, the dispersion value is high in that region, thus limiting use of the 1550 nm wavelength.
In general, total dispersion of the single mode fiber is determined by the sum of material dispersion and waveguide dispersion. Here, the material dispersion is determined by the peculiar properties of a material forming an optical fiber, and waveguide dispersion is determined by the structure of the optical fiber.
FIG. 1 is a graph illustrating the relationship between the material dispersion, the waveguide dispersion, and the total dispersion of a conventional 1550 nm single mode fiber. FIG. 1 describes the relationship between the material and waveguide dispersions depending on the wavelength of an optical signal in a single mode fiber having zero dispersion in a wavelength region of about 1550 nm. As shown in FIG. 1, the material dispersion D.sub.M appears because a long wavelength optical signal is quickly propagated and a short wavelength optical signal is slowly propagated as the refractive index varies according to the wavelength of an optical signal, and has a positive dispersion value in a wavelength region of about 1300 nm or higher. The waveguide dispersion D.sub.W has a negative dispersion value as opposed to the material dispersion. As a result, total dispersion D.sub.TOTAL is determined as shown in FIG. 1, and a wavelength where the total dispersion D.sub.TOTAL is "0" is called a zero dispersion wavelength.
Thus, the total dispersion D.sub.TOTAL can be lowered in a wavelength region to be used, by appropriately adjusting the material dispersion D.sub.M and the waveguide dispersion D.sub.W. However, a material of the optical fiber must be changed to control dispersion due to the material. Thus, a method of varying the waveguide dispersion D.sub.W is used to control the total dispersion value of the single mode fiber. Here, the waveguide dispersion D.sub.W can be controlled by adjusting the core diameter of an optical fiber, the distribution of refractive indices of a core and a cladding, and the difference between the refractive indices thereof. In other words, in order to fabricate a single mode fiber having a low dispersion value in the 1550 nm wavelength region having low loss, the refractive index of the core of an optical fiber must be increased, and the diameter of the core must be reduced, as compared to a typical single mode optical fiber for a 1310 nm wavelength.
A profile having a refractive index as shown in FIG. 2A is disclosed in, and incorporated by referrence to, U.S. Pat. No. 4,715,679 to Venkata A. Bhagavatula entitled Low Dispersion, Low-Loss Single Mode Optical Waveguide, and a profile having a refractive index as shown in FIG. 2B is disclosed in, and incorporated by reference to, U.S. Pat. No. 4,516,826 to Un-Chul Paek entitled Single Mode Lightguide Fiber Having A Trapezoidal refractive Index Profile.
In U.S. Pat. No. 4,516,826, in which the distribution of the refractive index of the core is triangular or trapezoidal, as shown in FIG. 2B, a core diameter 2a and a mode field diameter 2Wo are smaller than those of the typical single mode fiber for a 1310 nm wavelength, and a dispersion value is low in the 1550 nm wavelength region by controlling the waveguide dispersion. However, such a structure must accurately control a geometrical structure, since a connection loss (.alpha.=4.3(a/Wo).sup.2), upon connection of optical fibers to each other increases when the diameters of the core and mode field, are small, and since a micro-bending loss of an optical fiber rapidly increases when the core diameter is remarkably diminished to control the waveguide dispersion. Therefore, in U.S. Pat. No. 4,516,826, the distribution of the refractive index of the core is to be trapezoidal in order to reduce the micro-bending loss of an optical fiber.
An accurate process control is required, however, to fabricate an optical fiber having a small core diameter and a triangle refractive index profile of a core. Particularly, when an optical fiber having a triangular profile is manufactured by modified chemical vapor deposition (MCVD), a center dip phenomenon where a refractive index dips at a core center occurs. Thus, a more accurate process control is required to fabricate an optical fiber having a desired core diameter and a desired core refractive index, making it difficult to reproduce the process.
Other known single-mode optical fibers and their fabrication process are contemplated by U.S. Pat. No. 4,106,850 to E. Marcatili entitled Optical Fiber With Graded Index Core And Pure Silica Cladding; U.S. Pat. No. 4,306,767 to M. Kawachi et al. entitled Singel-Mode Optical Fiber; U.S. Pat. No. 4,435,040 to L. Cohen et al. entitled Double-clad Optical Fiberguide; U.S. Pat. No. 4,822,399 to H. Kanamori et al. entitled Glass Preform For Dispersion Shied Single Mode Optical Fiber And Method For The Production Of The Same; U.S. Pat. No. 5,361,319 to A. Antos et al. entitled Dispersion Compensating Devices And Systems; U.S. Pat. No. 5,559,921 to Y. Terasawa entitled Single Mode Optical Fiber; U.S. Pat. No. 5,613,027 to V. Bhagavatula entitled Dispersion Shifted Optical Waveguide Fiber; U.S. Pat. No. 5,673,354 to Y. Akasaka et al. entitled Dispersion Compensating Optical Fiber; U.S. Pat. No. 5,732,178 to Y. Terasawa et al. entitled Single Mode Optical Fiber; U.S. Pat. No. 5,742,723 to M Onishi et al. entitled Optical Transmission System With Dispersion Compensating Optical Fiber; U.S. Pat. No. 5,748,824 to D. Smith entitled Positive Dispersion Optical Waveguide; U.S. Pat. No. 5,761,366 to S. Oh et al. entitled Optical Fiber With Smooth Core Refractive Index Profile And Method of Fabrication; and U.S. Pat. No. 5,822,488 to Y. Terasawa et al. entitled Single-mode Optical Fiber With Plural Core Portions, incorporated herein by reference.

Single mode optical fiber having multi-step core structure and method of fabricating the same


A radial ventilation cooling structure for a motor includes at least three core sections, a ventilation channel steel is provided between every two adjacent core sections, and a ventilation channel is formed between the ventilation channel steel and the every two adjacent core sections, and impedances of the multiple ventilation channels are gradually increased in a direction from two ends of the motor to a center of the motor.

When a motor is operating, coils, cores and other components may have energy loss, this part of loss is eventually dissipated in the form of heat energy. Radial ventilation cooling is one of commonly used cooling manners for the motor. This cooling manner can increase the heat dissipation area and improve the power density of the generator, thus it has been widely used.
As shown in FIG. 1, the core of the motor is divided into multiple core sections 11, a ventilation channel steel 12 is provided between adjacent core sections 11 in a radial direction of the motor. The ventilation channel steel 12 has a supporting effect to the core sections 11, and also divides the space between adjacent core sections 11 into a ventilation channel 13. The motor has a recirculation ventilation path in which a cold air enters an air gap 14 from an end of a winding (not shown) and passes through the ventilation channel 13 (for example, branch ventilation channels 1 to 8 in the Figure), and reaches a cavity between two core brackets 15, and finally the hot air in the cavity is drawn through a pipeline to a heat exchanger outside the motor and converted into a cold air by the heat exchanger, and then the cold air enters the inside of the motor. As shown in FIG. 2, the ventilation channel steel 12 in the conventional radial ventilation cooling structure for the motor is a bar-shaped ventilation channel steel having a rectangular cross section, and the height of the ventilation channel 13 in an axial direction of the motor, that is the height h of the ventilation channel steel 12 in the axial direction of the motor (as shown in FIGS. 1 and 2), is equal to the distance between adjacent core sections 11 in the axial direction of the motor.
In the process of implementing the above ventilation cooling, the inventors have found that there are at least the following issues in the conventional technology. After the airflow enters the air gap, the velocity of the airflow is continuously reduced due to the bypassing effect, a local drag and a frictional drag of the ventilation channels and the like, thus the static pressure is increasingly greater and the dynamic pressure is increasingly smaller from an inlet of the air gap to a middle position of the air gap. However, since the multiple ventilation channel steels has the same structure and the multiple core sections has the same structure, the multiple ventilation channels have the same impedance, thus the quantity of airflow flowing through the multiple ventilation channels are increasingly larger. The heat generated by the internal heat source (coils, cores, and etc.) of the motor is distributed uniformly in the axial direction of the motor, while the airflow flowing through the multiple ventilation channels is distribute non-uniformly, thus the distribution of the temperature of the coils and the multiple core sections in the axial direction of the motor is not uniform, and the temperature from the inlet of the air gap to the middle position of the air gap is increasingly lower. The distribution of the temperature of the coils and the multiple core sections in the axial direction of the motor is not uniform, and the maximum temperature value is great, which is apt to cause a too high local temperature rising phenomenon, resulting in a shutdown of the motor, and is also apt to cause the core bracket to be thermally deformed, and therefore affecting the normal operation of the motor.

Radial ventilation cooling structure for motor

BEIJING GOLDWIND SCIENCE & CREATION WINDPOWER EQUIPMENT CO., LTD.


The present invention relates to a process for the manufacture of an animal feed block according to a target constituent formulation. The process eliminates spoiling of product by inconsistent and fluctuating levels of active ingredient and wet ingredients so as to ensure repeatability from one batch to another.

Solid animal feed blocks are becoming increasingly popular in the farming community. Feed blocks provide a combination of wet and dry feed grade raw materials formulated to provide nutritional value to ruminant animals and are a convenient way to administer regulated quantities of nutraceuticals, vitamins, minerals or proteins over a period of time.
Production methods for feed blocks involve chemical reactions and may require varying degrees of heat and a catalyst such as calcium oxide (CaO) or magnesium oxide (MgO). The oxides hydrate when they come into contact with moisture contained in the wet materials. Many chemical reactions which occur during production of a feed block are not fully understood and bear a resemblance to cement chemistry. Control of these reactions is difficult and significant waste material is a feature of the industry. Inconsistent product quality can occur with only minor adjustments in quantity, weight or particle size of the ingredients being used. These adjustments have a direct impact upon the severity of the reaction during formulation.

Process for the manufacture of an animal feed block


An acoustic object detector for detecting presence of an acoustic signal is provided. The acoustic object detector includes a number of bandpass filters. Each bandpass filter is configured to convert an input signal into an analog signal within a frequency band. The acoustic object detector also includes a number of spike generating circuits each coupled to the respective bandpass filter. Each spike generating circuit is configured to generate a series of spike signals based upon an adaptive threshold for the analog signal. The acoustic object detection further includes a decision circuit configured to generate a digital signal at a time-frequency point from the series of spike signals.

Digital signal processing is used to process data from a sensor, such as an acoustic transducer. Digital signal processing typically requires a large number of mathematical operations to be performed quickly and repetitively on a set of data. As illustrated in FIG. 1A, sound source 112 generates sound waves or acoustic object 113, which are received by transducer 104 that converts sound waves 113 to analog voltage signals 105. Analog-to-digital converter (ADC) or front-end circuit 102 then converts analog voltage signals 105 to digital signals 103, which are manipulated digitally in digital signal processor (DSP) 114 to output digital signals 107. Then, digital-to-analog converter (DAC) 116 converts digital signals 107 to analog signals 109.
Conventional acoustic sensor 100 includes transducer 104, front-end circuit 102, as illustrated in FIG. 1B. Front-end circuit 102 converts analog signals 105 into digital signals 103. Front-end circuit 102 typically includes an analog-to-digital converter (ADC) 110. Front-end circuit 102 may also include preamplifier 106 and lowpass filter 108. DSP 114 receives and processes digital signals 103, and then converts digital signals 103 into analog signals 107, as illustrated in FIG. 1A.
To reduce the power consumption of front-end circuit 102, a duty cycling method may be used to periodically shut off front-end circuit 102. The disadvantage of this duty cycling method is that the acoustic sensor 100 may miss important signals.
Another approach to reducing power consumption uses a wake-up circuit to detect the energy distribution of analog signal 105 in time domain, either shutting off front-end circuit 102 or waking it up based upon comparison of the detectable energy against a threshold. However, this approach may wake up front-end circuit 102 even when a desired sound signal is not present. Furthermore, when processing sound signals, front-end circuit 102 uses constant performance parameters and thereby uses power unnecessarily.
A third approach uses DSP 114 to identify frequency characteristics of sound signal or acoustic object 113 and to scale the power consumption of the front-end circuit 102 as needed based upon the frequency characteristics. Referring to FIG. 1A again, conventional acoustic sensor 100 may digitize analog signals 105 to generate digital signal 103, and then may use DSP 114 to compute occurrences of acoustic object 113. Digital signal 107 from DSP 114 converts into analog control signal 111 by digital-to-analog convert (DAC) 116 to adjust front-end circuit 102. This approach requires constant use of front-end circuit 102, DSP 114 and DAC 116, having significant power consumption, hardware complexity and latency.

Acoustic sensor with an acoustic object detector for reducing power consumption in front-end circuit


The invention is directed to an automatic system for activating vehicle headlights upon the actuation of a windshield wiper. The windshield wipers automatically begin a wiping cycle when moisture is sensed on a windshield. In the preferred embodiment, a moisture sensing device is strategically placed in the left-hand side of the windshield, at the end of a wiper blade track. When the windshield is no longer wet, the wiping cycle will stop and the headlights will remain on for a short period of time thereafter before turning off.

In recent years, in order to instill highway safety, many states have passed laws requiring the use of windshield wipers and headlights during light or heavy bad weather conditions such as rain, sleet or snow. Accidents occur each year due to bad weather conditions, control failure or operator carelessness, and because of this growing rate, a great emphasis has been put on improving safety features in vehicles made today.
Various complex designs and expensive configurations for automatic windshield wipers or automatic headlights are well known in the prior art. None though, have attempted, in a simple and inexpensive way, to devise an automatic control system whereby the headlights are automatically turned on after the windshield wipers are automatically activated due to moisture detected by a moisture sensing device on the windshield.
It is estimated that approximately 95% of all adjustments to the windshield wipers are performed manually during periods of light rain or intermittent bad weather conditions. The current delayed or pulsed wiper control systems used in the prior art fail to adjust to changes in the level of moisture striking the windshield, resulting in constant adjustments being required by the operator of the vehicle. Although the prior art has attempted to correct this deficiency at great expense or through very complex circuitry, none address efficiently the need and importance of ensuring that the headlights of the vehicle are turned on for the safety of the vehicles occupants.

Moisture sensitive automatic windshield wiper and headlight control device


To avoid unnecessary power dissipation, a decoder for selecting redundant memory cells in a memory device provides, for each section of the memory device, a first node and a second node that are coupled through a fuse-programmable ROM. If a defective memory cell is found in a section of the memory device, the fuse-programmable ROM of that section is programmed so as to decouple the first node from the second node when the defective memory cell is addressed. Prior to every access cycle, the first and second nodes of all sections are precharged. When address signals are received, the second node of the addressed section is discharged, other second nodes remaining charged. Normal or redundant memory cells are selected by performing a logic operation on the potentials of the first nodes.

This invention relates to a fuse-programmable decoder for selecting redundant memory cells in a semiconductor memory device such as a dynamic random-access memory, static random-access memory, electrically erasable and programmable read-only memory, or other type of memory.
As the integration density of memory devices has increased, it has become necessary to reduce power dissipation by dividing the memory cell array into multiple sections, only one of which operates in any given access cycle. To improve production yields, each section is provided with redundant memory cells. If a defective memory cell is found during testing by the manufacturer, the device is programmed so that when the defective cell is addressed, a redundant memory cell will be accessed instead.
For this purpose, the device is provided with a fuse-programmable decoder to decode address signals and select redundant memory cells when pre-programmed addresses appear. The decoder operates by precharging a node to the power-supply potential, then allowing the node to discharge through a network of transistors and fusible links, referred to herein as a fuse-programmable ROM, if the address does not match a pre-programmed address. A separate node and fuse-programmable ROM are provided for each section of the memory device. (ROM stands for road-only memory.)
A problem with existing fuse-programmable decoders is that even though only one section of the memory cell array will be selected, in every memory access cycle al decoder nodes are precharged, and all the nodes corresponding to non-selected sections must be discharged. This leads to unnecessary current drain and power dissipation.
A further problem is that when a node is discharged, the source and drain electrodes of transistors coupled to that node are both placed at the ground potential. These transistors become equivalent to single capacitors coupled between the address signal lines and ground, placing a large capacitive load on the address signal lines, which slows memory operation and leads to more unnecessary power dissipation.

Low-power decoder for selecting redundant memory cells


In accordance with a representative embodiment, a BAW resonator structure, comprises a first BAW resonator, comprising: a first lower electrode having a first electrical resistance; a first upper electrode having a second electrical resistance; and a first piezoelectric layer disposed between the first lower electrode and the first upper electrode. The BAW resonator structure also comprises a second BAW resonator, comprising: a second lower electrode having the second electrical resistance; a second upper electrode having the first electrical resistance; and a second piezoelectric layer disposed between the second lower electrode and the second upper electrode. The BAW resonator structure also comprises an acoustic coupling layer disposed between the first BAW resonator and the second BAW resonator. The first electrical resistance is less than the second electrical resistance. An communication device comprising a coupled resonator filter (CRF) is also disclosed.

In many electronic applications, electrical resonators are used. For example, in many wireless communications devices, radio frequency (RF) and microwave frequency resonators are used as filters to improve reception and transmission of signals. Filters have traditionally included inductors and capacitors, and more recently include acoustic resonators.
As will be appreciated, it is desirable to reduce the size of many components of electronic devices. Certain known acoustic filter technologies present a barrier to overall system miniaturization. With the need to reduce component size, a class of resonators based on the piezoelectric effect has emerged. In piezoelectric-based resonators, acoustic resonant modes are generated in the piezoelectric material. These acoustic waves can be converted into electrical waves for use in electrical applications.
One type of piezoelectric resonator is a Bulk Acoustic Wave (BAW) resonator. The BAW resonator includes an acoustic stack comprising, inter alia, a layer of piezoelectric material disposed between two electrodes. Acoustic waves achieve resonance across the acoustic stack, with the resonant frequency of the waves being determined by the materials of the layers of the acoustic stack, and the thicknesses of the layers of the acoustic stack. One particular type of BAW resonator comprises a thin film piezoelectric layer for the piezoelectric material. These resonators are often referred to as Film Bulk Acoustic Resonators (FBAR).
FBARs are similar in principle to bulk acoustic resonators such as quartz, but are scaled down in size to resonate at GHz frequencies. Because the FBARs have thicknesses on the order of micrometers (microns) and length and width dimensions of hundreds of microns, FBARs beneficially provide a comparatively compact alternative to certain known resonators.
FBARs may comprise an acoustic stack disposed over air. In such a structure, the acoustic stack is sometimes referred to as a membrane. Typically, the membrane is suspended over a cavity provided in a substrate. In other BAW resonator structures the acoustic stack is disposed over an acoustic mirror formed in the substrate. Regardless of whether the acoustic stack is suspended over air or provided over an acoustic mirror, the acoustic stack comprises a piezoelectric layer disposed over a first electrode, and a second electrode disposed over the piezoelectric layer.
Filters based on FBAR technology provide a comparatively low in-band insertion loss due to the comparatively high quality (Q) factor of FEAR resonators. FBAR-based filters are often employed in cellular or mobile telephones that can operate in multiple frequency bands. In such devices, it is important that a filter intended to pass one particular frequency band ("the passband") should have a high level of attenuation at other nearby frequency bands, which contain signals that are desirably rejected. Specifically, there may be one or more frequencies or frequency bands near the passband which contain signals at relatively high amplitudes that should be rejected by the filter. In such cases, it would be beneficial to be able to increase the filter's rejection characteristics at those particular frequencies or frequency bands, even if the rejection at other frequencies or frequency bands does not receive the same level of rejection.
One type of filter based on FBAR technology is known as a coupled resonator filter (CRF). A CRF comprises a coupling structure disposed between two vertically stacked FBARs. The CRF combines the acoustic action of the two FBARs, which leads to a bandpass filter transfer function. For a given acoustic stack, the CRF has two fundamental resonance modes, a symmetric mode and an asymmetric mode, of different frequencies. At any other frequency the CRF filter acoustic response is governed by a linear combination of the symmetric and asymmetric modes. The degree of difference in the frequencies of the modes depends, inter alia, on the degree or strength of the coupling between the two FBARs of the CRF. If the degree of coupling between the two FBARs is too great, the passband is unacceptably wide, and an unacceptable 'swag' or 'dip' in the center of the passband results. Moreover, if the degree of coupling between the two FBARs is too great, the insertion loss at the center of the passband is unacceptably high. Alternatively, if the degree of coupling is too weak for certain RF applications, the passband is unacceptably narrow.
The dependence of the passband on the degree of coupling has lead efforts to attempt to control the degree of coupling between the FBARs of the CRF. For many materials commonly used for acoustic applications at RF frequencies, the degree of coupling resulting from the interaction between the coupling material and the FBARs is too great, and results in an unacceptably high difference in the resonance frequencies of the modes of the CRF. Among other drawbacks, this results in an unacceptable 'dip' or 'swag' in the center of the passband, and unacceptable spreading of the passband.
One known technique used to control the degree of coupling between the FBARs of the CRF involves the use a coupling structure comprising a plurality of coupling layers with alternating high and low acoustic impedances. At each interface between each coupling layer a partial reflection of the acoustic mode occurs. The multiple interfaces provide a multiplicative reflective effect, and the degree of coupling between the FBARs can be beneficially controlled even when materials with relatively high acoustic impedances are employed in the coupling structure. While coupling structures comprising a plurality of coupling layers facilitate decoupling of the FBARs in the CRF, their presence adds complexity to the fabrication process, and ultimately to the cost of the resultant product.
What is needed, therefore, is a BAW resonator structure that overcomes at least the known shortcomings described above.

Bulk acoustic resonator structure comprising hybrid electrodes

Avago Technologies Wireless IP (Singapore) Pte. Ltd.


An operation device includes a movable member that is movable within a predetermined range, and a restriction member that is disposed in a state of being movable in a movable direction of the movable member, that restricts the movable range of the movable member by coming into contact with a contact surface of the movable member in the movable direction, and that can be switched between a state of being in contact with a first range of the contact surface and restricting the movable range of the movable member and a state of being in contact with a second range, the second range being different from the first range, of the contact surface and restricting the movable range of the movable member.

An operation device of a home game machine or the like detects a user's action of pressing a button, shaking the operation device, or the like, and transmits information indicating the detected user's action to the main body of the game machine or the like. Also, some of such operation devices present haptic senses to users by using actuators, etc.
Specifically, there has been an example in which the movable range of a locking switch which can be operated by a user is controlled to allow the user to feel the size of an object that is virtually grasped by the user.


A system comprising: an event server including a plurality of event agents for handling events occurring in a geographic space; a selector operable to select an event agent among the plurality of event agents for handling an event candidate based on a type of a source information; and a mobile object server including a mobile object agent assigned to a moving object in the geographic space, wherein the mobile object server is operable to execute the mobile object agent to collect information of an event from the selected event agent and provide the moving object with information that assists the moving object with traveling in the geographic space.

The present invention relates to a system for managing moving objects and events in a geographic space.
As a large number of automobiles and events on the geographic space are expected to be managed by the system, the system has to process a great deal of information. Since cars generally move at high speed and require the latest information, it is desirable to complete all processes of a driving system within one server in order to minimize processing time for individual automobiles.
However, as the geographic space being handled by such a system expands, the amount of information being transmitted and received increases due to an increase in the number of automobiles and the number of roads, and the corresponding requirements might exceed the processing power of a single server. Even if the geographic space is divided and a plurality of servers are used to process the spaces resulting from the division, automobiles move at high speeds among the plurality of divided geographic spaces, and therefore further communication between the servers is necessary, such that the communication load between servers increases. The increase of the communication load between the servers prevents the system from processing each automobile in a short time. Therefore, a system to enable less communication load between servers and higher scalability is further needed for efficiently managing large scale geographic spaces.
Furthermore, rules for detecting traffic events on the geographic space may differ depending on locations of the events. A system to efficiently handle these different rules is needed.

This patent is subject to a terminal disclaimer.

International Business Machines Corporation


A fixed-focus lens including a first lens group, a second lens group and a third lens group, which are arranged in sequence from an object side to an image side, is provided. The first lens group has a negative refractive power and includes three lenses arranged from the object side to the image side. The lens, closest to the object side, of the first lens group is an aspheric lens. The second lens group has a positive refractive power and includes two lens arranged from the object side to the image side. The third lens group has a positive refractive power and includes six lenses arranged from the object side to the image side. Refractive powers of the lenses of the third lens group in sequence from the object side to the image side are negative, positive, negative, positive, positive and positive.

1. Field of the Invention
The present invention generally relates to a lens, and, more particularly, to a fixed-focus lens.
2. Description of Related Art
Referring to FIG. 1, a conventional fixed-focus lens 100 for a rear projection television (RPTV) is disclosed in U.S. Pat. No. 6,452,728. The fixed-focus lens 100 includes a first lens group 110, a second lens group 120 and a third lens group 130 arranged in sequence from an object side to an image side. A light valve 50 is disposed on the image side. The first lens group 110 includes four lenses 112, 114, 116 and 118 all having negative refractive powers. The lens 112 is an aspheric lens. The second lens group 120 includes two lenses 122 and 124. The lenses 122 and 124 have positive and negative refractive powers, respectively, and the lenses 122 and 124 constitute a cemented lens 121. The third lens group 130 includes six lenses 131, 132, 133, 135, 136 and 137. Refractive powers of these six lenses 131, 132, 133, 135, 136 and 137 in sequence from the object side to the image side are positive, negative, positive, positive, positive and positive. In addition, the lenses 132 and 133 constitute a cemented lens 134, and the lens 137 is an aspheric lens.
In the fixed-focus lens 100, because the third lens group 130 is close to the light valve 50 and the light valve 50 is close to a light source (not shown) generating heat, the third lens group 130 normally has a higher temperature relative to other lens groups. In general, the lenses of the third lens group 130 are made of glass to resist the high temperature. However, the last lens 137 of the third lens group 130 is an aspheric lens, and the cost of the fixed-focus lens 100 is increased when a glass aspheric lens, which is more expansive, is adopted as the lens 137. If a plastic aspheric lens, which is less expensive, is adopted as the lens 137 for reducing the cost, the lens 137 is easy to deform under the high temperature so that the reliability of the fixed-focus lens 100 is worse.