A two-stage converter, a method for starting the two-stage converter, an LLC converter, and an application system are provided. A controller of the LLC converter of the two-stage converter first controls a main circuit of the LLC converter to perform hiccup charging on a direct current bus of a later-stage converter at a preset interval, so that the direct current bus voltage of the later-stage converter gradually increases, until an auxiliary power supply of the later-stage converter starts to operate, to supply power to the controller of the later-stage converter. After the controller of the later-stage converter reports the detected direct current bus voltage, the controller of the LLC converter determines whether the output voltage of the LLC converter increases to a hiccup starting voltage. If so, the controller of the LLC converter controls the main circuit to operate in a hiccup voltage stabilization phase.

A two-stage converter having an LLC topology can be used to achieve isolation conversion of electric energy. For example, each module in each phase of a three-phase cascaded modular photovoltaic solid-state transformer shown in FIG. 1 includes an isolation direct current to direct current (DC/DC) converter and an H-bridge converter. In a case that the isolation DC/DC converter is implemented by an LLC converter, each module is a two-stage converter having an LLC topology. The two-stage converter having an LLC topology may have a two-level topology structure as shown in FIG. 2 or a three-level topology structure as shown in FIG. 3.
In a system shown in FIG. 1, the isolation function is performed by a high-frequency transformer of a former-stage LLC converter in each module. Further, the system can be directly connected to a medium-voltage grid of 35 kV by arranging a certain number of the modules, so that an unwieldy industrial frequency isolation transformer can be omitted, thereby decreasing a weight and a volume of the system. However, a controller of the H-bridge converter can only acquire power from a bus voltage of the H-bridge converter via a corresponding auxiliary power supply, instead of a bus voltage of the LLC converter (as shown in FIG. 4). Therefore, when starting the entire system as shown in FIG. 1, in order to enable the controller of the H-bridge converter in each module of the system, it is required to charge the direct current bus of each H-bridge converter first.
In some cases, when starting the system, the direct current bus of each H-bridge converter is usually powered via a grid by using a circuit structure as shown in FIG. 5a. A specific process is described as follows. First, a switch S1 is turned on. The grid charges the direct current bus of the H-bridge converter via a soft-start resistor R and an inductor L. When a direct current bus voltage of the H-bridge converter reaches a preset value, a switch S2 is turned on, so that the soft-start resistor R is bypassed, to decrease power loss of the system. Although this charging method is simple and reliable, the switch S2 and the soft-start resistor R are required, which increases a volume and cost of the system.

Two-stage converter and method for starting the same, LLC converter, and application system


An anti-drainback valve contains a locking mechanism for securing the valve into to a filter assembly. The locking mechanism is made up of at least two keys that extend from the valve into beyond a cap of the filter assembly in order to secure the valve within the filter assembly. When multiple keys are employed, such keys may be equally spaced around the circumference of the cap. Manufacturing costs are kept minimal as minimal material is required and a two part mold may be employed during manufacturing.

An anti-drainback valve (ADB) is a type of valve that is typically a component in spin-on oil and fuel filters. An ADB, when used in conjunction with oil filters, is designed to retain oil in a filter and to prevent the filter from being drained when the engine is not running. This ensures that the oil can achieve its full lubricating effect as soon as the engine is started.
ADBs are typically made from rubber. Rubber ADBs are often molded in silicon, nitrile, or other suitable rubber compounds in a two-part opening mold. A two-part mold is typically used for manufacturing ADBs because it is a cost-efficient process for producing a large quantity of ADBs based on their symmetrical shape.
Larger conventional spin-on filter assemblies typically employ ADBs that fit on a cap with a collared-type design. Such larger conventional filter assemblies are often used in locations where space restrictions are not an issue. An example of a large conventional filter assembly that utilizes a collar design can be found in U.S. Pat. No. 3,339,738.
There are certain situations and designs, however, that allow only for a very limited space for installing ADBs on oil and fuel filters in an engine. For example, engines on newer cars produced by companies such as Honda, Nissan, and Toyota have very limited space (about 75 to 90 mm) for mounting 65 mm diameter oil filters. Such space limitations have resulted in a difficulty in the installation of the conventional ADBs that utilize a collared cap design.
Plain caps (i.e., caps with relatively flat tops) have been designed for use on filter assemblies with tighter space limitations. Conventional ADBs used on filter assemblies utilizing such plain caps, however, do not lock into the caps securely. As a result, conventional ADBs may slip from the caps of the filter assemblies in rapid production assembly lines. This can cause a slowdown in production, and may even require a 100% inspection rate to ensure that slipped ADB filters do not reach customers.

Anti-drainback valve with position positive locking for spin-on oil and fuel filters


Low silica forms of faujasite-type zeolites are prepared from more siliceous forms of the same zeolite species by contacting the starting zeolite with a highly caustic concentrated sodium aluminate solution at elevated temperatures. In view of the fact that the process does not favor the formation of undesirable impurity phases such as zeolite A and thus does not require the presence of zeolite A nucleation inhibitors, the process is particularly advantageous in the production of forms of zeolite X having Si/Al.sub.2 molar ratios below 2.5.

A considerable number of crystalline zeolitic alumino-silicates, both naturally-occurring and synthetic, are known in the art. Having crystal structures formed by the corner-sharing of SiO.sub.2 and AlO.sub.2 tetrahedral units, some zeolite species are known in which the Si/Al.sub.2 ratio of the as-crystallized lattice is as low as 2.0 and others in which the Si/Al.sub.2 ratio is as high as several hundred. In accordance with the now generally-accepted theory expressed by Loewenstein's rule [Amer. Mineralog. (1954) 39, 92] AlO.sub.2 tetrahedra are joined only to SiO.sub.2 tetrahedra, and hence the Si/Al.sub.2 ratios of zeolite frameworks cannot be less than 2.0. There is no theoretical restriction upon the upper limit of the Si/Al.sub.2 ratio.
While certain zeolite species, for example ZSM-5, can be directly crystallized hydrothermally to have a very wide range of Si/Al.sub.2 ratios, i.e., 5 to >200, others such as the synthetic faujasites represented by the zeolite X-zeolite Y continuum have been limited to the relatively small range of 2.0 to about 6 for the as-crystallized compositions. A particular cesium-containing zeolite, CSZ-3, said to have the faujasite type of crystal structure, has been reported in which the as-synthesized form has a Si/Al.sub.2 ratio of as high as 7.0. Heretofore, attempts to change the as-crystallized Si/Al.sub.2 ratios, particularly in the case of the low-silica species, have been toward increasing the Si/Al.sub.2 ratios. The earlier efforts involved hydrolysis and extraction of framework aluminum to yield a more siliceous but defect-containing crystal lattice. More recently, procedures generally referred to as secondary synthesis have employed silicon tetrahalides or fluorosilicate salts to extract framework aluminum atoms and substitute in their stead silicon atoms. The primary goals of these investigations were to improve the hydrothermal stability of the crystal lattice and decrease the number of acidic sites associated with the AlO.sub.2 tetrahedra in order to render the catalytic activity more selective, particularly for hydrocarbon conversion reactions.
It is not always the case, however, that the more siliceous forms of the faujasite crystal structure provide superior performance. In certain common adsorption-separation processes, such as air separation, the basis for selective adsorption of one or more of the components of the mixture to be separated is the interaction of the local electrostatic fields in the zeolite with molecules of the mixture possessing permanent dipole or quadrupole moments. These interactions are extraordinarily complex and require, inter alia, that the particular combination of cation species making up the cation population of the zeolite be optimized in view of the various components of the mixture to be separated and the process conditions imposed. It is found that maximizing the number of cation sites in the zeolite adsorbent is often advantageous and accordingly it is necessary in such cases to maximize the number of AlO.sub.2 .sup.- tetrahedral units in the zeolite.
Zeolite X, having large pores interconnecting large internal cavities, and thus having the potential for adsorbing large amounts of selectively adsorbed molecules, is widely used in adsorption processes in which crystal degradation due to acid attack or hydrothermal abuse is not a significant problem. In addition the crystal structure of zeolite X permits its formation by hydrothermal crystallization in a form in which the number of AlO.sub.2 tetrahedra are essentially the same as the number of Si.sub.2 tetrahedra, i.e., the framework Si/Al.sub.2 ratio is about 2.0. In the synthesis of zeolite X, and also of the more siliceous zeolite Y, a variety of reagents can supply the silicon and aluminum incorporated into the crystal lattice as the tetrahedral oxide units. Suitable silicon-containing reagents include silica gel, silica acid, aqueous silica sols, amorphous solid silica and sodium silicate. Suitable aluminum-containing reagents include activated alumina, gamma alumina, aluminum trihydrate and sodium aluminate. The reagents within each group are not, however, exact equivalents, i.e., a zeolite product having a given Si/Al .sub.2 ratio and degree of purity cannot necessarily be prepared under identical reaction conditions and reagent proportions with each of the aforementioned sources of silica and alumina. There are, moreover, significant differences in the costs of raw materials so that some reagents are much preferred over others for the commercial manufacture of zeolites. In the case of zeolite X it has also been found that the reaction mixtures which can result in products having Si/Al.sub.2 ratios below about 2.5 are also capable of forming zeolite A as an impurity phase. To inhibit nucleation of the zeolite A structure, it is commonly the practice to include substantial amounts of potassium ions in addition to the usual sodium ions. The use of potassium ions has the disadvantage of adding to the cost of the synthesis mixture. It also results in a significant portion of the cation sites of the zeolite X product being occupied by potassium cations. In some instances the presence of these potassium cations is undesirable for the intended adsorption process, necessitating their removal by a post-synthesis ionexchange.

Process for preparing low silica forms of zeolites having the faujasite type structure


The alloy is preferably an alloy having a niobium and titanium base according to the expression: EQU Nb-Ti.sub.27-40.5 -Al.sub.4.5-10.5 -Hf.sub.1.5-5.5 Cr.sub.4.5-7.9 V.sub.0-6,. wherein the ratio of concentrations of Ti to Nb (Ti/Nb) is greater than or equal (.gtoreq.) to 0.5, and PA0 wherein the maximum concentration of the Hf+V+Al+Cr additives is less than or equal (.ltoreq.) to the expression: EQU 16.5+(5.times.Ti/Nb), PA0 and the minimum concentration of these additives is 10.5.. The crystal form of the alloy is specifically body centered cubic crystal form.

The present invention relates to a family of novel metal alloys having a lighter weight and better oxidation resistance than alloys with comparable melting range, and having a tensile strength greater than wrought Ni-base alloys at high temperature. It also relates to structures in which such novel alloys are a part.
The invention additionally relates to body centered cubic metal structures in which the metal is ductile at room temperature, but which retain significant tensile strength at high temperatures.
It is known that niobium base alloys have useful strength in temperature ranges at which nickel and cobalt base superalloys begin to show incipient melting. This incipient melting temperature is in the approximately 2300.degree. to 2400.degree. F. range. The use of the higher melting niobium base metals in advanced jet engine turbine hot sections would allow higher metal temperatures than are currently allowed. Such use of the niobium base alloy materials could permit higher flame temperatures within the engines and would also permit production of greater power at greater efficiency. Such greater power production at greater efficiency would be at least in part due to a reduction in cooling air requirements. Most niobium base alloys, particularly those which are commercially available, are subject to oxidation to a degree which makes their use in high temperature air atmospheric environments unacceptable because of the lack of reliable coatings.
Certain alloys having a niobium-titanium base have much lower densities of the range 6-7.3 grams per cubic centimeter. A group of such alloys are the subject matter of commonly owned U.S. Pat. Nos. 4,956,144; 4,990,308; 5,006,307; 5,019,334; and 5,026,522. Such alloys can be formed into parts which have significantly lower weight than parts formed of niobium based alloys or than presently employed nickel and cobalt superalloys as these superalloys have higher densities ranging from about 8 to about 9.3 grams per cubic centimeter.
One additional patent, U.S. Pat. No. 4,931,254, concerns an alloy having the following composition in atom percent:
______________________________________ Concentration Ingredient Range ______________________________________ niobium balance titanium 40-48% aluminum 12-22% hafnium 0.5-6% chromium 3-8% ______________________________________
Commonly owned U.S. Pat. No. 4,904,546 concerns an alloy system in which a niobium base alloy is protected from environmental attack by a surface coating of an alloy highly resistant to oxidation and other atmospheric attack.
In devising alloy systems for use in aircraft engines the density of the alloys is, of course, a significant factor which often determines whether the alloy is the best available for use in the engine application. The nickel and cobalt based superalloys also have much greater tolerance to oxygen exposure than the commercially available niobium based alloys. The failure of a protective coating on a nickel or cobalt superalloy is a much less catastrophic event than the failure of a protective coating on many of the niobium based alloys and particularly the commercially available niobium based alloys. The oxidation resistance of the niobium based alloys of the above commonly owned patents is intermediate between the resistance of commercial Nb base alloys and that of the Ni- or Co-based superalloys.
While the niobium titanium based alloys of the above commonly owned patents are stronger than wrought nickel or cobalt based superalloys at high temperatures, they are much weaker than cast or directionally solidified nickel based superalloys at these higher temperatures. However, for many engine applications, structures formed by wrought sheet fabrication are used, since castings of sheet structures cannot be produced economically in sound form for these applications.
What is highly desirable in general for aircraft engine use is an alloy which can be formed into a structure which has a combination of lower density, higher strength at higher temperatures, good ductility at room temperature, and higher oxidation resistance.
A number of articles have been written about use of refractory metals in high temperature applications. These articles include the following:
(1) S. T. Wlodek, "The Properties of Cb-Ti-W Alloys, Part I", Oxidation Columbium Metallurgy, D. Douglass and F. W. Kunz, eds., AIME Metallurgical Society Conferences, vol. 10, Interscience Publishers, New York (1961) pp. 175-204.
(2) S. T. Wlodek, "The Properties of Cb-Al-V Alloys, Part I", Oxidation ibid., pp. 553-584 .
(3) S. Priceman and L. Sama, "Fused Slurry Silicide Coatings for the Elevated Temperature Oxidation of Columbium Alloys", Refractory Metals and Alloys IV - TMS Conference Proceedings, French Lick, IN, Oct. 3-5, 1965, vol . II, R. I . Jaffee, G. M. Ault, J. Maltz, and M. Semchyshen, eds., Gordon and Breach Science Publisher, New York (1966) pp. 959-982.
(4) M. R. Jackson and K. D. Jones, "Mechanical Behavior of Nb-Ti Base Alloys", Refractory Metals: Extraction, Processing and Applications, K. C. Liddell, D. R. Sadoway, and R. G. Bautista, eds., TMS, Warrendale, PA (1990) pp. 311-320.
(5) M. R. Jackson, K. D. Jones, S. C. Huang, and L. A. Peluso, "Response of Nb-Ti Alloys to High Temperature Air Exposure", ibid., pp. 335-346.
(6) M. G. Hebsur and R. H. Titran, "Tensile and Creep Rupture Behavior of P/M Processed Nb-Base Alloy, WC-3009", Refractory Metals: State-of-the-Art 1988, P. Kumar and R. L. Ammon, eds., TMS, Warrendale, PA (1989) pp. 39-48.
(7) M. R. Jackson, P. A. Siemers, S. F. Rutkowski, and G. Frind, "Refractory Metal Structures Produced by Low Pressure Plasma Deposition", ibid., pp. 107-118.


A III-Nitride device has a back-gate disposed in a trench and under and in close proximity to the 2 DEG layer and in lateral alignment with the main gate of the device. A laterally disposed trench is also disposed in a trench and under and in close proximity to the drift region between the gate and drain electrodes of the device. The back-gate is connected to the main gate and the field plate is connected to the source electrode. The back-gate can consist of a highly conductive silicon substrate.

III-Nitride devices are normally-on depletion mode (D-mode) devices. A negative voltage is applied to the gate of the device to turn it off. In a typical III-Nitride device, an AlGaN layer atop a GaN layer forms a 2 DEG, normally conductive layer which conducts under a control gate and between a source and a drain electrode atop and in contact with the AlGaN layer.
However, leakage paths exist in the GaN layer which is normally relatively highly doped. The device also suffers from sub-threshold characteristics and relatively poor transconductance characteristics.
It would be desirable to provide a III-Nitride device which improves the leakage, the subthreshold characteristics and transconductance of such devices while employing well known processing techniques for its manufacture.

III-nitride device with back-gate and field plate for improving transconductance


This disclosure relates to treatments for reducing the side effects associated with treatment of a medication or drug, such as a chemotherapy medication, being experienced by a patient. This may be accomplished by administering to a patient taking the medication, a buffered aqueous liquid having a pH of about 10 to about 11.5, wherein the buffered aqueous liquid comprises sodium bicarbonate, sodium carbonate, and trisodium phosphate.

Chemotherapy is a well-known and potent treatment for many types of cancer. Chemotherapy can prolong a person's life and perhaps even rid them of cancer. However, there is a downside to chemotherapy. Some of the chemistry found in chemotherapy drugs cannot distinguish between normal cells and cancer cells, killing both, and causing the negative side effects. Most people will experience side effects, which are common with the administration of the potent compounds used in chemotherapy. The reactions are often unpredictable. Some of the more common reactions are general ill feeling, easy bruising or bleeding, hair loss, nausea and vomiting, difficulty in breathing, neuropathy, constipation and diarrhea.
Treating these side effects requires the administration of even more drugs in addition to the chemotherapy drugs. They may include antihistamines, corticosteroids, beclomethasone, bronchodilators and many other classes of drugs. All of these drugs may have their own negative side effects. The net result is that the patient is subjected to many different types of reactions that complicate the effectiveness of the chemotherapy medications.
The accompanying description will aid in the understanding of the described features and functionality of the disclosed treatment.

This patent is subject to a terminal disclaimer.

Treatment for reducing adverse events including chemotherapy discomfort and other conditions


The present invention provides compositions comprising amorphous calcium carbonate (ACC), suitable to being administered by inhalation, and methods for their use in treating ACC-responsive diseases and conditions. Further provided are ACC compositions suitable for buccal or sublingual administration.

Calcium is considered to be one of the most important minerals in the human body. It is required for maintaining bone mineral density, is essential for exocytosis of neurotransmitters, takes part in the contraction of muscle cells, replaces sodium as the depolarizing mineral in the heart, and participates in many other physiological functions.
Calcium used in supplements today, whether obtained from natural sources or synthetic precipitates, may comprise both organic and inorganic calcium salts. Calcium carbonate—an inorganic salt of calcium—is the main compound commercially used in the nutrient supplement market. Calcium carbonate has six known polymorphs, three of which are anhydrous crystalline (i.e., calcite, aragonite, and vaterite), two of which are hydrated (i.e., crystalline monohydrocalcite and ikaite), and one of which is hydrated amorphous, namely, amorphous calcium carbonate (ACC). The most thermodynamically stable of these phases is calcite, whereas the least stable is ACC. ACC is a form that precipitates out of a supersaturated solution, if not stabilized by any element or compound. ACC will crystallize rapidly and completely into one of the five more stable polymorphs within seconds. Solubility studies suggest dramatic differences between the calcium carbonate polymorphs. While crystalline phases are considered poorly soluble, the amorphous form is much more soluble.
In nature, ACC is utilized by a number of organisms, mainly crustaceans and other invertebrates that developed capabilities for stabilizing ACC in transient mineral deposition sites. These organisms require an exceptional efficient mineral source for the periodical mobilization, absorption and precipitation of calcium. In some crustaceans, such as the freshwater crayfish, ACC is stored in large quantities in specialized transient storage organs, named the gastrolith.
Various orally-administrable formulations comprising amorphous calcium carbonate have been disclosed. For example, International Patent Application published as WO 2005/115414 is directed to the use of the gastrolith organs, ground to a fine powder in pharmaceutical and nutraceutical calcium compositions. It was further disclosed that daily oral consumption of compositions comprising gastrolith components dramatically improves a range of conditions such as bone disorders, bone fractures, and cancer (WO 2008/041236). Pharmaceutical and nutraceutical compositions comprising ACC and phosphorylated peptides or amino acids for treating various disorders and conditions are disclosed in WO 2009/053967. The oral administration is, however, not always feasible or sufficient. There is a need for additional methods for administration of ACC.

Compositions of amorphous calcium carbonate for inhalation, sublingual or buccal administration


A method, apparatus, and system for providing distributed source coding techniques that improve data coding performance, such as video data coding, when channel errors or losses occur. Errors in the reconstruction of the data is eliminated or reduced by sending extra information. Correlation between a predicted sequence and an original sequence can be used to design codebooks and find the cosets required to represent the original image. This information may be sent over another channel, or a secondary channel.

I. Field
The present invention relates generally to multimedia over error-prone networks, and more specifically to video coding and decoding techniques used in conjunction with multimedia over wireless networks.
II. Background
Current video compression techniques, such as, ITU-T H.263, H.263+, H.263++, ISO MPEG-4 and JVT H.264 have become increasingly efficient in compressing video. The ability to achieve good visual quality at relatively low bitrates has led to increased popularity of video applications in emerging multimedia applications over bandwidth limited channels, such as, wireless channels. However, the predictive nature of compression techniques employed by current video codecs makes the compressed video bit-streams very fragile and susceptible to degradation due to packet losses in the channel.
Channel errors or packet loss can lead to loss of synchronization between a video encoder and a decoder. More specifically, a locally decoded copy of a reconstructed video frame at the encoder may not match the corresponding reconstructed video frame at the decoder. This loss of synchronization between a video encoder and a decoder is also sometimes termed "drift" since there will be a drift between the receiver's decoder and the sender's decoder. Drift can lead to significant losses in decoded video quality.
The reduction in decoded quality due to a drift is a direct consequence of the prediction-based coding that underlies current video codecs. That is, to currently decode the current video frame, all previous video frames need to have been reconstructed correctly. This problem is exacerbated in a wireless channel where packet losses are far more frequent than in a wire-line network and tend to occur in bursts.
Re-transmission schemes, such as Automatic Repeat Request (ARQ), or Forward Error Correction (FEC) schemes have been used to combat drift problems between the encoder and decoder and thereby alleviate the loss in quality due to packet losses. However, using ARQ or FEC schemes (or a combination of both) may not prove effective since the latency constraints of the video application may preclude the use of such schemes. Moreover, FEC-based schemes cannot guarantee that the data will be received and if it is not, the drift continues until the next intra-frame1 is received. 1 An intra-frame is used by video encoders to break the prediction loop and hence stop drift.
The Wyner-Ziv Theorem is discussed in A. D. Wyner and J. Ziv, "The rate distortion function for source coding with side information at the decoder," IEEE Trans. Inf. Theory, vol. 22, pp. 1-10, January 1976. This Theorem addresses the problem of source coding with side-information. Consider two correlated sources X and Y. The encoder needs to compress the source X when only the decoder has access to the source Y. When the mean squared error is the distortion measure and X=Y+N where N has a Gaussian distribution, the rate—distortion performance for coding X is the same whether or not the encoder has access to Y.
Recently, based on the principles of source coding with side-information within a Wyner-Ziv framework joint source-channel coding techniques have been proposed to address the problem of drift. See, for example, R. Puri and K. Ramchandran, "PRISM: A New Robust Video Coding Architecture based on Distributed Compression Principles," in Allerton Conference on Communication, Control and Computing, 2002; A. Sehgal, A. Jagmohan, and N. Ahuja, "Wyner-ziv Coding of Video: An Error-Resilient Compression Framework," IEEE Trans. on Multimedia, vol. 6, pp. 249-258, 2004; A. Aaron, S. Rane, R. Zhang, and B. Girod, "Wyner-Ziv Coding of Video: Applications to compression and error resilience," in Proc. IEEE Data Compression Conf., 2003; and A. Aaron, S. Rane, D. Rebollo-Monedero, and B. Girod, "Systematic Lossy Forward Error Protection for Video Waveforms," in Proc. IEEE Int. Conf. Image Proc., 2003.
The codecs discussed in R. Puri and K. Ramchandran, "PRISM: A New Robust Video Coding Architecture based on Distributed Compression Principles," in Allerton Conference on Communication, Control and Computing, 2002; and A. Aaron, S. Rane, R. Zhang, and B. Girod, "Wyner-Ziv Coding of Video: Applications to compression and error resilience," in Proc. IEEE Data Compression Conf., 2003, are full-fledged video codecs that eschew the predictive coding framework.
On the other hand, the codecs discussed in A. Sehgal, A. Jagmohan, and N. Ahuja, "Wyner-ziv Coding of Video: An Error-Resilient Compression Framework," IEEE Trans. on Multimedia, vol. 6, pp. 249-258, 2004; and A. Aaron, S. Rane, D. Rebollo-Monedero, and B. Girod, "Systematic Lossy Forward Error Protection for Video Waveforms," in Proc. IEEE Int. Conf. Image Proc., 2003, retain the predictive coding framework but send some extra information to mitigate the effect of drift.
Notwithstanding these advances, there is a need in the art for techniques that not only enables robust video delivery over wireless channels by helping alleviate the effects of packet losses on compressed video bit-streams transmitted over such wireless channels, but also satisfies the requirements of                Be able to work with existing compression techniques        Have low processing latency        Quickly eliminate/reduce the drift between the video encoder and decoder        Require low bitrate when compared to that used by the video codec

Method, apparatus, and system for enhancing robustness of predictive video codecs using a side-channel based on distributed source coding techniques


An inkjet textile printing apparatus includes a penetrant liquid storage tank, a textile printing colored liquid storage tank, and first to third flow passages. The penetrant liquid storage tank is configured and arranged to store a penetrant liquid that facilitates penetration of a textile printing colored liquid into a fabric. The textile printing colored liquid storage tank is configured and arranged to store the textile printing colored liquid. The first flow passage connects the penetrant liquid storage tank and a first nozzle together. The second flow passage connects the textile printing colored liquid storage tank and a second nozzle together. The third flow passage connects the first flow passage and the second flow passage together and forms a flow passage for supplying the penetrant liquid to the second nozzle.

1. Technical Field
The present invention relates to an inkjet textile printing method and an inkjet textile printing apparatus.
2. Related Art
A known inkjet printer forms an image on a recording medium by ejecting ink from a nozzle toward the recording medium. There is also a known technology (hereinafter called "inkjet textile printing") for using a fabric as the recording medium and using an inkjet printer to print on the fabric by ejecting ink onto the fabric. Inkjet textile printing is advantageous over such other textile printing methods as screen printing, roller printing, roller screen printing, and transfer printing because inkjet printing does not require fabrication of a printing plate like those other methods do and, thus, more easily accommodates high-mix low-volume production. Inkjet textile printing is also advantageous in that it incurs a smaller amount of waste liquid.
In inkjet textile printing, there are known technologies for improving image quality by using transparent inks in addition to inks containing coloring materials. Japanese Laid-Open Patent Publication No. 06-10278 discloses a technology related to an inkjet printing method for printing on a sheet-like item, wherein at least one of a plurality of inkjet nozzles is a dedicated nozzle for a colorless ink that contains a medium that can disperse or dissolve a coloring matter and does not contain a coloring matter and the method serves to apply an ink containing a coloring matter and a version of the colorless ink having compatibility with the coloring matter-containing ink to a portion of a printing area of the item where a light color or color leveling is necessary. Japanese Laid-Open Patent Publication No. 2010-65209 discloses technology for a textile printing inkjet ink set and an inkjet textile printing method, wherein the textile printing inkjet ink set comprises a recording ink containing a reactive dye, a water-soluble organic solvent, and water and a transparent ink containing a water-soluble macromolecular material and an inorganic base. The textile printing inkjet ink set and the inkjet textile printing method enable inkjet printing onto fabric that has not been pre-treated so as to produce high color densities while suppressing bleeding and mixing of ink. Japanese Laid-Open Patent Publication No. 2006-181804 discloses a technology for removing foreign matter and froth from inside an inkjet head. In order to reliably discharge foreign matter inside the inkjet head and reduce work performed by hand, a rotating part of a stationary table supporting the inkjet head is rotated and cleaning is executed in a manner suitable to the direction of the head. Japanese Laid-Open Patent Publication No. 06-320743 discloses a technology related to an inkjet textile printing apparatus configured to wipe an ink ejecting surface of a head using a so-called wiper ring treatment in order to prevent ink that has adhered to the ink discharge surface from adhering to a print medium and to prevent discharge variation of the ink discharged a plurality of nozzles. The technology serves to shorten the execution time of the wiper rink treatment.

Inkjet textile printing method and inkjet textile printing apparatus


A credential store provides for secure storage of credentials. A credential stored in the credential store is encrypted with the public key of a user owning the credential. A first user may provide a credential owned by the first user to a second user. The first user may add credentials owned by the first user to the credential store. An administrator may manage users of the credential store without having the ability to provide credentials to those users.

This disclosure relates generally to the field of computing systems. More particularly, but not by way of limitation, it relates to techniques for allowing access to computer systems.
Automation products perform tasks on a variety of different computer systems. Various systems have been developed to provide what is known as "Single Sign-On" (SSO) capability, allowing a user to provide authentication information once, typically a user id and a password, then gain access to other systems without being prompted to login again at each of the other systems. These various SSO systems have been in practice incapable of providing complete coverage for all computer systems of an enterprise, particularly where those systems are provided by different vendors, with varying authentication systems, so that the different systems cannot be integrated into an enterprise-wide SSO security architecture.
Some products available today attempt to deal with the problem by encoding passwords using simple encodings, such as Base64, then passing these encoded passwords to the different systems as needed. Other products encrypt all passwords in a single place, using a single key, making an attack on the single place particularly attractive.


An on-chip differential multi-layer inductor includes a 1st partial winding on a 1st layer, a 2nd partial winding on the 1st layer, a 3rd partial winding on a 2nd layer, a 4th partial winding on the 2nd layer, and an interconnecting structure. The 1st and 2nd partial windings on the 1st layer are operably coupled to receive a differential input signal. The 3rd and 4th partial windings on the 2nd layer are each operably coupled to a center tap. The interconnecting structure couples the 1st, 2nd, 3rd and 4th partial windings such that the 1st and 3rd partial windings form a winding that is symmetrical about the center tap with a winding formed by the 2nd and 4th partial windings. By designing the on-chip differential multi-layer inductor to have a desired inductance value, a desired Q factor, and a desired operating rate, a desired resonant frequency and corresponding desired capacitance value can be determined. Having determined the electrical parameters of the multi layer established, the geometric shapes of the windings, number of windings, number of layers to support the inductor, and the interconnecting structure may be determined.

This invention relates generally to integrated circuits and more particularly to on-chip inductors.
As is known, wireless communication standards place stringent requirements on wireless communication devices"" dynamic range of operation to accommodate for the dramatic variations in signal strength of receive signals, which may vary by orders of magnitude. To meet these requirements, wireless communication devices are designed using radio frequency (RF) integrated circuits (IC) that consume low power and produce little noise. As is also known, on-chip inductors are significant components of RFIC""s and are used in oscillators, impedance matching networks, emitter degeneration circuits, filters, and/or baluns. Thus, it is desirable to use on-chip inductors that consume as little power as possible and produce as little noise as possible. In addition, it is desirable to use on-chip inductors that provide a desired inductance value at a desired operating rate consuming as little IC real estate as possible.
To minimize power consumption and to reduce noise, an inductor should have a high quality factor (Q factor). As is known, the Q factor is a measure of an inductor""s performance characteristics expressed in power capabilities at a resonant frequency and its selectivity (i.e., power ratio in decibels versus frequency). As is known, CMOS on-chip inductors have a relatively low Q factor in the range of 5-10.
As with any circuit or component implemented on an integrated circuit, the circuit and/or component should be as small as possible (i.e., have as small of an IC footprint as possible) and still be able to achieve the desired performance criteria. In general, on-chip inductors"" performance criteria is becoming more and more demanding as the demands for larger inductance values, high Q factors, lower noise levels, higher operating rates, et cetera increase.
FIG. 1 illustrates a single ended multi-layer on-chip inductor, which includes multiple windings (Windings #1-#3) on multiple layers (Layers #1-#3). As shown, the windings are connected by vias (Vias #1 and #2). While such an inductor provides a relatively small footprint and can have higher inductance values than single layer inductors of a similar footprint, it typically has a relatively significant capacitance value that limits the resonant frequency, which in turn limits the operating frequency of the inductor. In addition and as is generally known, single ended circuits are inherently noisier than differential circuits. Thus, for noise sensitive circuits, a differential inductor is often chosen over a single ended inductor.
FIG. 2 illustrates a single layered differential inductor having 1st and 2nd windings (Windings #1 and #2) on one layer (Layer #1). Winding #1 is coupled to Winding #2 via a bridge on Layer #2 and interconnecting vias #1 and #2. The differential single layered inductor receives a differential signal via nodes 1 and 2. Such a differential inductor has a low capacitance value, but to achieve a large inductance value, it consumes a significant amount of IC real estate. In addition, the differential inductor is not symmetrical because node #1 to ground is all on the first layer and node #2 to ground includes the bridge and the vias, thus it is longer.
Therefore a need exists for a differential inductor that minimizes the use of integrated circuit real estate, can operate at relatively high frequencies, has a relatively high Q factor and a need also exists for a method of design and a method of manufacture for a multi layer differential inductor.
The on-chip differential multi-layer inductor disclosed herein substantially meets these needs and others. Such an on-chip differential multi-layer inductor includes a 1st partial winding on a 1st layer, a 2nd partial winding on the 1st layer, a 3rd partial winding on a 2nd layer, a 4th partial winding on the 2nd layer, and an interconnecting structure. The 1st and 2nd partial windings on the 1st layer are operably coupled to receive a differential input signal. The 3rd and 4th partial windings on the 2nd layer are each operably coupled to a center tap. The interconnecting structure couples the 1st, 2nd, 3rd and 4th partial windings such that the 1st and 3rd partial windings form a winding that is symmetrical about the center tap with a winding formed by the 2nd and 4th partial windings. By designing the on-chip differential multi-layer inductor to have a desired inductance value, a desired Q factor, and a desired operating rate, a desired resonant frequency and corresponding desired capacitance value can be determined. Having determined the electrical parameters of the multi layer established, the geometric shapes of the windings, number of windings, number of layers to support the inductor, and the interconnecting structure may be determined.
Other embodiments of an on-chip differential multi-layer inductor include parallel partial windings on 3rd and 4th layers that are operably coupled in parallel (i.e., shunted) with the 1st, 2nd, 3rd and 4th partial windings. In addition, the positioning of the partial windings with respect to the parallel windings and with respect to each other may be positioned to tune the capacitance value of the inductor to set the resonant frequency at a desired value.
In another aspect of an on-chip differential multi-layer inductor, the windings on multiple layers may have similar metalization (i.e., have about the same amount of metal layers). The amount of metalization, the geometric shape of the windings, and the number of layers to use may be determined based on the desired inductance value, desired metalization coverage, and operating rates. By evenly distributing or near evenly distributing metalization amongst the layers, the manufacturing yield of integrated circuits including on-chip inductors is increased.
As such, multiple embodiments of a differential inductor may be designed and manufactured to minimize the use of integrated circuit real estate, to operate at relatively high frequencies, and to have a relatively high Q factor.

On-chip differential multi-layer inductor


A system and method are disclosed for image processing of one or more items in an inventory of one or more supply chain entities. Embodiments include receiving an initial set of images of at least two items in the inventory, identifying color distributions from the initial set of images using two encoders, and grouping colors of the at least two items based on similarities of the identified color distributions using a color coding model.

Managing and planning operations for products in a fashion retail supply chain often requires analyzing color attributes of products prior to making actionable decisions. Color attributes may be expressed in terms of color codes, but color codes differ between manufacturers, product lines, and even the same products from season to season, which is problematic for attribute-driven operations such as planning, demand forecasting, and customer segmentation. This lack of uniform color-coding among products in a fashion retail supply chain is undesirable.

Image processing system for deep fashion color recognition


A rotary device for front seats of a motor vehicle enables both a driver seat and a front passenger seat to be rotatably capable of taking an ordinary forwardly facing position and a rearwardly facing position. The device includes a first detection switch provided in the driver seat for electrically detecting the position of the driver seat, a second detection switch provided in the passenger seat for electrically detecting the position of the passenger seat, a first rotation control provided in the driver seat for preventing or permitting the operation of a rotation release lever of the driver seat, and a second rotation control provided in the passenger seat for preventing or permitting the operation of the another rotation release lever of the passenger seat. A control system electrically controls the first and the second rotation controls by receiving signals from the first and the second detection switches so as to prevent a condition such that the driver seat is in the forwardly facing position but the passenger seat is in the rearwardly facing position.

1. Field of the Invention
The present invention relates to a rotary device for front seats of a motor vehicle, wherein both a driver seat and a front passenger seat are rotatable in such a manner that each seat is capable of taking an ordinary forwardly facing position and a rearwardly facing position.
2. Description of the Prior Art
A multi-purpose motor vehicle wherein both a driver seat and an assistant driver or front passenger seat are rotatable and capable of taking an ordinary forwardly facing position and a rearwardly facing position is known.
One example of a rotary device for front seats of the above-mentioned type of motor vehicle is disclosed in Japanese Patent Application Laid Open Gazette No. 59-227528. As a safety measure, this device provides that a driver seat should always be in the rearwardly facing position when a passenger seat is turned to a rearwardly facing position, and likewise that the passenger seat should always be in the forwardly facing position when the driver seat is turned to the forwardly facing position. This device also provides that an operation lever for detecting the position of the above-mentioned seats and an engaging pin for engaging with a rotation release lever are connected by means of a remote control or a remotely operated cable or wire. However, such a rotary device involves some disadvantages due to mechanical operation thereof by such remote control wire. For example, special consideration must be given to install a remote control wire, especially when there is a projecting portion (a tunnel portion) between a driver seat and a front passenger seat, as in ordinary passenger cars. As a result, mounting a remote control wire leads to a complex construction and a troublesome assembly operation of the body of the vehicle.
As discussed in Japanese Patent Application Laid Open Gazette No. 61-202934, a rotary seat device controlled by a control cable to prevent a situation such that a driver seat is in a forwardly facing position but an assistant driver or front passenger seat is in a rearwardly facing position also is known. However, this device also entails complexity of mounting the control cable in the same way as the device utilizing the remote control wire described above.

Rotary device for front seats of a motor vehicle


A semiconductor memory device includes a memory cell connected to a read bit line and a pair of write bit lines, and a data amplifier connected to the read bit line. A precharge potential resetting circuit uses a function of generating precharge potentials to the pair of write bit lines based on data of the memory cell amplified by the data amplifier to set the precharge potentials of the non-selected pair of write bit lines to have a potential relationship corresponding to the data stored by the memory cell. As a result, data destruction of the non-selected memory cell during write operation is reduced or prevented, and the speed of operation is increased and the area is reduced.

The present disclosure relates to semiconductor memory devices, and more particularly, to a semiconductor memory device which achieves high-speed operation while reducing or preventing data destruction in a non-selected memory cell during data write operation.
In conventional static random access memory (SRAM) devices, the further miniaturization of transistors included in a memory cell would increase significant variations in transistor characteristics, disadvantageously leading to destruction of data stored by the memory cell during memory operation.
There is a technique of reducing or preventing data destruction during read operation in which bit lines are provided for write operation and read operation separately. There is also a technique of reducing or preventing data destruction in a non-selected memory cell during write operation in which data read from the non-selected memory cell is written back to the non-selected memory cell (see Japanese Patent Publication No. 2007-4888 and International Publication No. 2008/032549).
There are the following problems with the above conventional technique of reducing or preventing data destruction during write operation in a semiconductor memory device.
Firstly, data which has once been read is written back to a non-selected memory cell during write operation. Therefore, the operation time is longer than that of simple write or read operation, and therefore, the speed of the operation of the SRAM device disadvantageously cannot be increased.
Next, in order to achieve the data write-back operation, a write circuit having a capability similar to that of a write buffer used in conventional write operation is required. Also, the timing of writing back needs to be accurately controlled, and therefore, the number of parts increases, disadvantageously resulting in an increase in the circuit area of the SRAM device.


A sensor arrangement is provided, including a first capacitive sensor and a second capacitive sensor. A charge pump is coupled to the first capacitive sensor and to the second capacitive sensor, the charge pump being operable to deliver a positive bias voltage. A differential output has a first terminal coupled to the first capacitive sensor and a second terminal coupled to the second capacitive sensor.

Sensing arrangements may include a variety of sensors. In some embodiments, sensing arrangements may include capacitive sensors used for sensing acoustical energy. Additionally, capacitive sensors are used in other applications as well, for example, humidity sensors, acceleration sensors and electret microphones. In some embodiments, a capacitive sensor may include a micro-electromechanical (MEMs) device.


A bidirectional capacitive isolator includes a capacitive isolation network, a first transceiver circuit, and a second transceiver circuit. The capacitive isolation network includes a first port and a second port. The first transceiver circuit is coupled to the first port of the capacitive isolation network, and includes circuitry configured to cancel signal transmitted by the first transceiver circuit from signal received by the first transceiver circuit. The second transceiver circuit is coupled to the second port of the capacitive isolation network, and includes circuitry configured to cancel signal transmitted by the second transceiver circuit from signal received by the second transceiver circuit.

Isolation is useful in electrical circuits to prevent the flow of direct currents and undesirable alternating currents between two parts of a system. While preventing flow of undesirable currents between parts of a system, isolation may allow signal transfer between the isolated parts of the system. Isolation may be provided by integrated circuits referred to as isolators. Electronic systems may include isolators for safety reasons and/or to protect electronic components of the systems (such as systems where one set of circuitry operates at a much higher voltage than another set of circuitry). For example, where two systems need to communicate, but the systems have grounds that may be at different potentials, communication may be through an isolator that is tied to the grounds of both systems, but which allows no current flow between the grounds. Various types of isolators may include optical coupling, capacitive coupling, inductive coupling (e.g., a transformer), or other types of coupling to isolate systems while allowing communication between the systems.

Isolated bidirectional communication circuit


Disclosed herein is a method of manufacturing a thin film transistor having a structure that a gate electrode and an oxide semiconductor layer are disposed with a gate insulating film interposed between the gate electrode and the oxide semiconductor layer, and a source/drain electrode is electrically connected to the oxide semiconductor layer, the method including: continuously depositing an aluminum oxide (Al2O3) layer as a protective film and an aluminum (Al) layer in this order on any of the source/drain electrode, the gate insulating film, and the oxide semiconductor layer by using sputtering.

The present application relates to a Thin Film Transistor (TFT) used in a display device or the like, and a method of manufacturing the same.
In recent years, with a view to application of a Thin Film Transistor (TFT), a light emitting device, a transparent conductive film, and the like to electronic apparatuses, the research and development of oxide semiconductors such as a zinc oxide and an indium gallium zinc oxide are very active. It is found out that when the oxide semiconductor is used in an active layer (channel) of the TFT, the oxide semiconductor shows a high electron mobility, and thus shows excellent electrical characteristics as compared with the TFT using amorphous silicon. In addition, the oxide semiconductor has an advantage such that even at a low temperature close to a room temperature, the high mobility can be expected, and so forth, and thus the positive development of the oxide semiconductor is progressed. With regard to the TFT using such an oxide semiconductor layer, a bottom gate type structure, and a top gate type structure have been reported. The bottom gate type structure, and the top gate type structure, for example, are described in PCT Patent Publication No. WO 2005-088726 and Japanese Patent Laid-Open No. 2007-194594.
However, in the oxide semiconductor, a film quality is easy to deteriorate due to breakaway of oxygen, mixing of hydrogen, and the like. This results in that in the TFT, a threshold voltage is shifted to a minus side, the current-voltage characteristics and the like are deteriorated, and so forth.
In order to cope with such a situation, a technique for forming a protective film made of an aluminum oxide (Al2O3) or the like as a protective film for an oxide semiconductor layer becoming a channel has been proposed. This technique, for example, is described in Japanese Patent Laid-Open No. 2010-135462. Such a protective film, for example, can be deposited in an atmospheric ambient of a mixed gas of oxygen (O2) and argon (Ar) with aluminum as a target by, for example, utilizing a reactive sputtering method.

Oxide semiconductor thin film transistor with an aluminum oxide protective film made using a continuous deposition process of aluminum oxide laminated with an aluminum film


The present disclosure discloses a method and an apparatus of power over Ethernet, and belongs to the field of communications. An Ethernet power sourcing equipment sets a power supply port to a sleep state, and sets a timer for the power supply port; enables the power supply port when the timer reaches a set time; and detects whether a powered device PD is connected to the power supply port, and if a PD is connected to the power supply port, triggers the power supply port to supply power to the PD; if no PD is connected to the power supply port, resets the power supply port to the sleep state, and sets the timer for the power supply port. Implementation of the present disclosure effectively reduces power consumption of the system and saves energy.

Power over Ethernet (Power Over Ethernet in English, POE for short) is a technology of supplying direct current to IP-based terminals (such as an IP telephone, a wireless local area network access point AP, and a network camera) while transmitting data signals for such terminals without modifying an existing basic cabling structure of the Ethernet. A PoE system includes a power sourcing equipment (Power sourcing equipment in English: PSE for short) and a powered device (Powered device in English, PD for short).
Currently, the PoE technology is applied to people's life more and more widely, an increasingly high proportion of PoE ports are applied in electrical interface switches of the Ethernet, and more and more types of devices are supported by the PoE.
In the working state, the PSE detects whether a PD is connected to a port of the PSE. If it is detected that a PD is connected to a port, the PSE identifies the type of the PD, evaluates the power loss required by the PD, and starts supplying power to the PD. If no PD is connected to the ports of the PSE, all ports of the PSE keep detecting. The continuous detection leads to continuous consumption and waste of power.

Method and apparatus of Power over Ethernet


A cutting insert includes an upper surface having a circular cutting edge, a lower surface opposite the upper surface, an exterior sidewall between the upper surface and the lower surface, and an interior sidewall defining a hole extending from the upper surface to the lower surface. The interior sidewall includes an upper interior sidewall portion and a lower interior sidewall portion. The lower interior sidewall portion increases in radius with respect to a downward direction of the cutting insert. The lower interior sidewall portion includes a plurality of recessed portions positioned about a circumferential direction of the lower interior sidewall portion.

Cutting inserts used in cutting tools such as milling cutters are typically mounted in complementary-shaped pockets spaced around a periphery of a tool body. The cutting inserts are typically secured within their respective pockets by screws inserted through a hole provided in the center of the cutting insert. During a cutting operation, such cutting inserts often experience not only compressive and vibratory forces, but some amount of torque due to the angle between the cutting edges of the cutting inserts and the workpiece. For cutting inserts of non-round shapes, such torque does not result in rotation of the cutting insert due to the interference-type fit between the angled sidewalls of such cutting inserts and the complementary-shaped walls of the pocket that receive them. By contrast, round cutting inserts can rotate within their respective pockets since no such mechanical interference naturally arises between the sidewalls of round cutting inserts and the circular walls of the pockets which receive them. The resulting rotation can reduce the life of the cutting insert and jeopardize the quality of the cut on the workpiece.
To prevent such unwanted rotation of round cutting inserts, several anti-rotation mechanisms have been developed previously. In one such mechanism, one or more lugs are provided on the pocket to retain the round cutting insert against rotation. However, during machining, a heavy feed tends to cause damage to or even remove the lug from the pocket, thus reducing the life of the cutting insert and ruining the tool holder.
Thus, there is a need for an anti-rotation mechanism for round cutting inserts which effectively prevents such cutting inserts from rotating without damaging the pocket that receives the cutting insert.

Cutting insert and cutting system comprising cutting insert


A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array including: a plurality of first lines; a plurality of second lines intersecting the first lines; and a plurality of memory cells each including a variable resistance element disposed at the intersection of the first and second lines and configured to store an electrically rewritable resistance value as data in a nonvolatile manner, and a control unit configured to detect an amount of a current flowing through the first line when a memory cell is accessed, and adjust the voltage of the first or second line based on the amount of the current.

1. Field
Embodiments described herein relate generally to a nonvolatile semiconductor memory device.
2. Description of the Related Art
Conventionally, as an electrically rewritable nonvolatile memory, a flash memory is known which includes a cell array configured by NAND connection or NOR connection of memory cells each having a floating gate structure. Further, a ferroelectric memory is also known as a memory that is nonvolatile and compatible with fast random access.
Meanwhile, as a technique for enabling greater miniaturization of memory cells, a resistance varying memory using a variable resistance element in each memory cell is proposed. Known variable resistance elements include: a phase change memory element varying a resistance by phase changes of a chalcogenide compound between a crystallized state and an amorphous state; an MRAM element using resistance changes due to tunnel magnetoresistance effect; a memory element of a polymer ferroelectric RAM (PFRAM) including a resistance element made of a conductive polymer; a ReRAM element inducing resistance changes upon electric pulse application, etc (Patent Document 1: JP 2006-344349A, paragraph 0021).
In the resistance varying memory, memory cells can be configured by a series circuit of not a transistor but a Schottky diode and a variable resistance element. Therefore, memory cells can be easily stacked to a three-dimensional structure and hence are advantageous for grater miniaturization (Patent Document 2: JP 2005-522045A).
However, a relatively large current flows through this resistance varying memory and its interconnection lines in a reset operation of changing the resistance state of the variable resistance element from a low resistance state to a high resistance state and in a read operation of sensing the resistance state of the variable resistance element. Therefore, influence of a voltage drop due to an interconnection resistance is unignorable. That is, since the influence of a voltage drop varies depending on the location to be accessed, a read margin and a reset margin are reduced. Furthermore, there is also a problem that the number of bits that can be accessed simultaneously is limited.

Nonvolatile semiconductor memory device adjusting voltage of lines in a memory cell array


An engagement unit for insertion on and engagement with a threaded bolt (33) is provided with an inner part (1) and with an outer part (2) that can be slid onto the inner part (1). The inner part (1) and the outer part (2) are configured with torque receiving means (8, 9, 23, 24) for transmitting a torque applied to the outer part (2) to the inner part (1). After the inner part (1) has been slid onto a threaded bolt (33) in a pre-assembly arrangement in which latching means configured on spring arms of the inner part (1) and cooperating with the threaded bolt (33) are able to slide along the threaded bolt (33), the engagement unit according to the invention can thus be inserted onto the threaded bolt (33) and, once the outer part (2) has been slid onto the inner part (1), can be tightened in the manner of a screw.

1. Field of the Invention
The invention is directed to an engagement unit for insertion onto and engagement with a threaded bolt.
2. Description of the Related Art
One known engagement unit is disclosed in DE 35 25 865 C1. The prior engagement unit is equipped with a number of spring arms that are configured with latching means for engagement with a threaded bolt. The engagement unit can thus be slid onto a threaded bolt in a simple manner.

Engagement unit for attaching and for engaging a threaded bolt


A display control device having a pointing device adapted to perform an operation associated with image capture or playback includes, mode setting switches and/or components for setting at least one of operation modes of recording, playback and communication, components for obtaining identification information to identify the user of the display control device, an operating member display for displaying operating members in positions corresponding to the pointing device, storage for storing data concerning a plurality of operating members having different functions and placement positions, an operating member setting component for extracting data concerning operating members on the basis of the identification information obtained and setting the data to display the operating members, and an operation input controller for associating the functions of the operating members displayed on the operating member display with the input position and input operation of the pointing device.

1. Field of the Invention
The present invention relates to a display control device and method which permits different users to have an operating system suitable for each individual user and perform operations associated with image capture or playback with ease.
2. Description of the Related Art
Digital cameras have various functions built in through the use of digital technology. While it has become possible to implement various functions, an operating panel used in utilizing built-in functions has to be equipped with many operating buttons to suit the functions.
A technique has been proposed which uses a touch-sensitive operating panel with a remote control device for operating two or more pieces of electrical equipment and changes its display screen according to electrical equipment to be operated (Japanese Unexamined Patent Publication No. 2000-134681).
Also, a technique has been proposed which permits the sizes, positions, colors and number of directive images to be displayed on the touch panel to be changed and changes the size of the key entry section on the touch panel according to the sizes of the directive images (Japanese Unexamined Patent Publication No. 9-81094).


The invention relates to the processing of a digital signal originating from a decoder and a noise reduction post-processing step, including, in particular, limitation of distortion introduced by the post-processing step in order to deliver a corrected output signal (SOUT), assigning said corrected output signal (SOUT) with: a current amplitude having an intermediary value between a current amplitude value of the post-processed signal (SPOST) and a corresponding current amplitude value of the decoded signal (S′MIC), or the current amplitude of the post-processed signal (SPOST), according to the respective values of the current amplitude of the post-processed signal (SPOST) and by the corresponding current amplitude of the decoded signal (S′MIC).

Generally, the bit rate required to pass an audio and/or video signal with sufficient quality is an important parameter in telecommunications. In order to reduce this parameter and thus increase the number of possible communications via one and the same network, audio coders have been developed in particular for compressing the quantity of information required to transmit a signal.
Certain coders make it possible to achieve particularly high information compression factors. Such coders generally use advanced information modeling and quantization techniques. Thus, these coders only transmit models or partial data of the signal.
The decoded signal, although it is not identical to the original signal (since part of the information has not been transmitted on account of the quantization operation), nevertheless remains very close to the original signal (at least from the perception point of view). The difference, in the mathematical sense, between the decoded signal and the original signal is then called "quantization noise".
Signal compression processings are often designed so as to minimize quantization noise and, in particular, to render this quantization noise as inaudible as possible when the processing of an audio signal is involved. Thus, techniques exist which take into account the psycho-acoustic characteristics of hearing, with the aim of "masking" this noise. However, to obtain the lowest possible bit rates, the quantization noise may sometimes be difficult (or indeed impossible) to mask totally, thereby, in certain circumstances, degrading the intelligibility and/or the quality of the signal.
In order to reduce this quantization noise and hence improve quality, two families of techniques can be used on decoding.
It is possible, firstly, to use an adaptive post-filter, of the type described in the article by Chen and Gersho:
"Adaptive post filtering for quality enhancement of coded speech", IEEE Transactions on Speech and Audio Processing, Vol. 3, No. 1, Jan. 1995, pages 59-71, and employed in particular in the speech decoders of CELP ("Code Excited Linear Prediction") type.
This involves performing a filtering which improves subjective quality by attenuating the signal in the zones where the quantization noise is most audible (in particular between the formants and the harmonics of fundamental period or "pitch"). Current adaptive post-filters afford good results for speech signals, but less good results for other types of signals (music signals, for example).
Another processing family is aimed at the conventional noise reduction processings which distinguish the useful signal from spurious noise and which can be applied as post-processing to reduce the quantization noise after decoding. This type of processing makes it possible at the origin to reduce the noise related to the signal capture environment and it is often used for speech signals. However, it is impossible to make the processing transparent in relation to the noise related to the sound pick-up environment, thereby posing a problem for music signal coding, in particular. Thus, in coding/decoding, one might want to transmit the "atmospheric" noise and it is then desirable for the noise reduction not to apply to this type of "atmospheric" noise but solely to the quantization noise, in particular in the context of post-processing on decoding aimed at reducing quantization noise.
Nevertheless, these various types of quantization noise reduction methods deform the signal to a greater or lesser extent. For example, the use of a post-filter (denoising) which would be too aggressive for the speech signal would make it possible to completely eliminate the quantization noise but the voice sound obtained would seem less natural and/or muffled. Optimization of these various types of methods is therefore difficult and it is appropriate systematically to find a compromise between:                the effectiveness of suppression of the quantization noise, and        the conservation of the properties of the initial signal, in particular in terms of natural or unnatural aspect.

Limitation of distortion introduced by a post-processing step during digital signal decoding


A cross stack rapid transition protocol is provided for permitting multiple network devices organized as a stack to rapidly transition their ports in response to network changes so as to minimize traffic flow disruptions while avoiding loops. Each switch in the stack has a stack port that connects the switch to another switch in the stack, and a plurality of ports for connecting the switch to other entities of the computer network. Each switch includes a Spanning Tree Protocol (STP) entity that transitions the ports of the switch among a plurality of states including a forwarding state and a blocking state. Each switch also tracks which other switches are members of the switch stack. The stack port of each switch is transitioned to the forwarding state, and a single switch having connectivity to a root is elected to be a Stack Root. One or more other switches may have Alternate Stack Root Ports, that provide alternate paths to the root. If the current Stack Root loses connectivity to the root, the switch whose Alternate Stack Root Port represents the next best path to the root issues one or more proposal messages to the other members of the switch stack. These other members respond with an Acknowledgement, and the former Stack Root transitions its port to the blocking state. Once the proposing switch receives an Acknowledgment from all other active members of the switch stack, it transitions its Alternate Stack Root Port to the forwarding state so that network messages can be forwarded to and from switch stack.

1. Field of the Invention
This invention relates to computer networks and, more specifically, to reconfiguring a computer network.
2. Background Information
Many organizations, including businesses, governments and educational institutions, utilize computer networks so that employees and others may share and exchange information and/or resources. A computer network typically comprises a plurality of entities interconnected by means of one or more communications media. An entity may consist of any device, such as a computer, that "sources" (i.e., transmits) or "sinks" (i.e., receives) data frames over the communications media. A common type of computer network is a local area network ("LAN") which typically refers to a privately owned network within a single building or campus. LANs typically employ a data communication is protocol (LAN standard), such as Ethernet, FDDI, Wireless Fidelity (Wi-Fi) or token ring that defines the functions performed by data link and physical layers of a communications architecture (i.e., a protocol stack).
Spanning Tree Algorithm
Most computer networks include redundant communications paths so that a failure of any given link does not isolate any portion of the network. Such networks are typically referred to as meshed or partially meshed networks. The existence of redundant links, however, may cause the formation of circuitous paths or "loops" within the network. Loops are highly undesirable because data frames may traverse the loops indefinitely.
Furthermore, some devices, such as bridges or switches, replicate frames whose destination is not known resulting in a proliferation of data frames along loops. The resulting traffic can overwhelm the network. Other intermediate devices, such as routers, that operate at higher layers within the protocol stack, such as the Internetwork Layer of the Transmission Control Protocol/Internet Protocol ("TCP/IP") reference model, deliver data frames and learn the addresses of entities on the network differently than most bridges or switches, such that routers are generally not susceptible to sustained looping problems.
To avoid the formation of loops, most bridges and switches execute a spanning tree protocol which allows them to calculate an active network topology that is loop-free (i.e., a tree) and yet connects every pair of LANs within the network (i.e., the tree is spanning). The IEEE has promulgated a standard (IEEE Std. 802.1D-1998™) that defines a spanning tree protocol to be executed by 802.1D compatible devices. In general, by executing the 802.1D spanning tree protocol, bridges elect a single bridge within the bridged network to be the "Root Bridge". The 802.1D standard takes advantage of the fact that each bridge has a unique numerical identifier (bridge ID) by specifying that the Root Bridge is the bridge with the lowest bridge ID. In addition, for each LAN coupled to any bridge, exactly one port (the "Designated Port") on one bridge (the "Designated Bridge") is elected. The Designated Bridge is typically the one closest to the Root Bridge. All ports on the Root Bridge are Designated Ports, and the Root Bridge is the Designated Bridge on all the LANs to which it has ports.
Each non-Root Bridge also selects one port from among its non-Designated Ports (its "Root Port") which gives the lowest cost path to the Root Bridge. The Root Ports and Designate Ports are selected for inclusion in the active topology and are placed in a forwarding state so that data frames may be forwarded to and from these ports and thus onto the LANs interconnecting the bridges and end stations of the network. Ports not included within the active topology are placed in a blocking state. When a port is in the blocking state, data frames will not be forwarded to or received from the port. A network administrator may also exclude a port from the spanning tree by placing it in a disabled state.
To obtain the information necessary to run the spanning tree protocol, bridges exchange special messages called configuration bridge protocol data unit (BPDU) messages or simply BPDUs. BPDUs carry information, such as assumed root and lowest root path cost, used in computing the active topology. More specifically, upon start-up, each bridge initially assumes itself to be the Root Bridge and transmits BPDUs accordingly. Upon receipt of a BPDU from a neighboring device, its contents are examined and compared with similar information (e.g., assumed root and lowest root path cost) stored by the receiving bridge in memory. If the information from the received BPDU is "better" than the stored information, the bridge adopts the better information and uses it in the BPDUs that it sends (adding the cost associated with the receiving port to the root path cost) from its ports, other than the port on which the "better" information was received. Although BPDUs are not forwarded by bridges, the identifier of the Root Bridge is eventually propagated to and adopted by all bridges as described above, allowing them to select their Root Port and any Designated Port(s).
In order to adapt the active topology to changes and failures, the Root Bridge periodically (e.g., every hello time) transmits BPDUs. In response to receiving BPDUs on their Root Ports, bridges transmit their own BPDUs from their Designated Ports, if any. Thus, BPDUs are periodically propagated throughout the bridged network, confirming the active topology. As BPDU information is updated and/or timed-out and the active topology is calculated, ports may transition from the blocking state to the forwarding state and vice versa. That is, as a result of new BPDU information, a previously blocked port may learn that it should be in the forwarding state (e.g., it is now the Root Port or a Designated Port).
Rapid Spanning Tree Protocol
Recently, the IEEE promulgated a new standard (the 802.1w standard) that defines a rapid spanning tree protocol (RSTP) to be executed by otherwise 802.1D compatible devices. The RSTP similarly selects one bridge of a bridged network to be the root bridge and defines an active topology that provides complete connectivity among the LANs while severing any loops. Each individual port of each bridge is assigned a port role according to whether the port is to be part of the active topology. The port roles defined by the 802.1w standard include Root, Designated, Alternate and Backup. The bridge port offering the best, e.g., lowest cost, path to the root is assigned the Root Port Role. Each bridge port offering an alternative, e.g., higher cost, path to the root is assigned the Alternate Port Role. Each bridge port providing the lowest cost path from a given LAN is assigned the Designated Port Role, while all other ports coupled to the given LAN in loop-back fashion are assigned the Backup Port Role.
Those ports that have been assigned the Root Port and Designated Port Roles are placed in the forwarding state, while ports assigned the Alternate and Backup Roles are placed in a discarding or blocking state. A port assigned the Root Port Role can be rapidly transitioned to the forwarding state provided that all of the ports assigned the Alternate Port Role are placed in the discarding or blocking state. Similarly, if a failure occurs on the port currently assigned the Root Port Role, a port assigned the Alternate Port Role can be reassigned to the Root Port Role and rapidly transitioned to the forwarding state, providing that the previous root port has been transitioned to the discarding or blocking state. A port assigned the Designated Port Role or a Backup Port that is to be reassigned to the Designated Port Role can be rapidly transitioned to the forwarding state, provided that the roles of the ports of the downstream bridge are consistent with this port being assigned the Designated Port Role. The RSTP provides an explicit handshake to be used by neighboring bridges to confirm that a new designated port can rapidly transition to the forwarding state.
Like the STP described in the 802.1D specification standard, bridges running RSTP also exchange BPDU messages in order to determine which roles to assign to the bridge's ports. The BPDU messages are also utilized in the handshake employed to rapidly transition designated ports to the forwarding state.
FIG. 1 is a block diagram of a RSTP BPDU message 100. The BPDU message 100 includes a BPDU message header 102 compatible with the Media Access Control (MAC) layer of the respective LAN standard. The message header 102 comprises a plurality of fields (not shown), such as a destination address (DA) field and a source address (SA) field. The DA field carries a unique bridge multicast destination address assigned to the spanning tree protocol. Appended to header 102 is a BPDU message area 104 that also contains a number of fields, including a protocol identifier (ID) field 106, a protocol version number field 108, a BPDU type field 110, a flags field 112, a root ID field 114, a root path cost field 116, a bridge ID field 118, a port ID field 120, a message age field 122, a maximum age field 124, a hello time field 126, and a forward delay field 128, among others. The root identifier field 114 typically contains the identifier of the bridge assumed to be the root and the bridge identifier field 118 contains the identifier of the bridge sourcing (i.e., sending) the BPDU 100. The root path cost field 116 contains a value representing the cost to reach the assumed root from the port on which the BPDU is sent, and the port identifier field 120 contains the identifying number of the port from which the BPDU is sent.
As shown, the flags field 112 carries a plurality of single or multiple bit flags that may be set, e.g., asserted, or cleared, e.g., de-asserted. Specifically, the flags field 112 includes a topology change flag 130, a proposal flag 132, a port role flag 134, a learning flag 136, a forwarding flag 138, an agreement flag 140 and a topology change acknowledgment (ACK) flag 142. The learning and forwarding flags 136 and 138 are set to reflect the current port state of the port from which the corresponding BPDU is being sent.
The handshake utilized by adjacent bridges for rapidly transitioning designated ports typically proceeds as follows. When an upstream bridge wishes to rapidly transition a designated port to the forwarding state, it issues a BPDU 100 from that port whose proposal flag 132 is asserted. The port role flag 134 is set to the value associated with the Designated Port Role. In the root ID and root path cost fields 114 and 116, the upstream bridge loads the corresponding information relative to the port from which the BPDU message 100 is to be sent. The upstream bridge then sends the BPDU message which is received at the neighboring downstream bridge.
Assuming the information contained in the BPDU message 100 is equal to or better than that currently stored by the port of the downstream bridge at which the BPDU is received, the downstream bridge asserts "sync" for all of its other bridge ports. Sync is a state machine variable defined by the 802.1w specification standard. Basically, this has the effect of causing the downstream bridge to transition all of its designated ports, other than "edge" ports, to the discarding state. An edge port is defined as a port which provides the only connection to a respective LAN, thereby representing an edge of the bridged network. Once the designated ports have been transitioned to the discarding state, the downstream bridge responds, typically through its root port, to the upstream bridge with a BPDU message 100 whose agreement flag 140 is asserted. This notifies the upstream bridge that the downstream bridge is in agreement with the upstream bridge's request to transition the respective port to the forwarding state.
In addition, the designated port(s) of the downstream bridge request permission from their downstream bridges to rapidly transition back to the forwarding state following the same process. That is, BPDU messages 100 with their proposal flags 132 asserted are sent from these ports. In effect, a "cut" is made in the active topology at the first affected designated port and the cut propagates down from this first designated port through all bridges on the subtree below it, i.e., in a direction away from the root, until the cut reaches the edge of the bridged network.
Virtual Local Area Networks
Is A computer network may also be segmented into a series of logical networks. For example, U.S. Pat. No. 5,394,402, issued Feb. 28, 1995 to Ross (the "'402 Patent"), discloses an arrangement for associating any port of a switch with any particular network segment. Specifically, according to the '402 patent, any number of physical ports of a particular switch may be associated with any number of groups within the switch by using a virtual local area network (VLAN) arrangement that virtually associates the port with a particular VLAN designation. More specifically, the switch or hub associates VLAN designations with its ports and further associates those VLAN designations with messages transmitted from any of the ports to which the VLAN designation has been assigned.
The VLAN designation for each port is stored in a memory portion of the switch such that every time a message is received on a given access port the VLAN designation for that port is associated with the message. Association is accomplished by a flow processing element which looks up the VLAN designation in the memory portion based on the particular access port at which the message was received. In many cases, it may be desirable to interconnect a plurality of these switches in order to extend the VLAN associations of ports in the network. Those entities having the same VLAN designation function as if they are all part of the same LAN. In order to preserve the boundaries of each VLAN, VLAN-aware bridges are specifically configured to prevent messages from being passed between parts of the network having different VLAN designations. Nonetheless, intermediate network devices operating above layer 2 (L2), such as routers, can relay messages between different VLAN segments.
In addition to the '402 patent, the IEEE promulgated a specification standard (IEEE Std. 802.1Q-1998) for Virtual Bridged Local Area Networks. To preserve VLAN associations of messages transported across trunks or links in VLAN-aware networks, both Ross and IEEE Std. 802.1Q-1998 disclose appending a VLAN identifier (VID) field to the corresponding frames. In addition, U.S. Pat. No. 5,742,604 to Edsall et al. (the "'604 patent"), which is commonly owned with the present application, discloses an Interswitch Link (ISL) encapsulation mechanism for efficiently transporting packets or frames, including VLAN-modified frames, between switches while maintaining the is VLAN association of the frames. In particular, an ISL link, which may utilize the Fast Ethernet standard, connects ISL interface circuitry disposed at each switch. The transmitting ISL circuitry encapsulates the frame being transported within an ISL header and ISL error detection information, while the ISL receiving circuitry strips off this information and recovers the original frame.
Multiple Spanning Tree Protocol
Recently, the IEEE published a supplement to IEEE Std. 802.1Q-1998 describing a Spanning Tree Protocol that is specifically designed for use with networks that support VLANs. The Multiple Spanning Tree Protocol (MSTP), which is identified as IEEE Std. 802.1s-2002, organizes a bridged network into regions. Within each region, MSTP establishes an Internal Spanning Tree (IST) which provides connectivity to all bridges within the respective region and to the ISTs established within other regions. The IST established within each MSTP Region also provides connectivity to the one Common Spanning Tree (CST) established outside of the MSTP regions by IEEE Std. 802.1Q-1998 compatible bridges running STP or RSTP. The IST of a given MST Region receives and sends BPDUs to the CST. Accordingly, all bridges of the bridged network are connected by a single Common and Internal Spanning Tree (CIST). From the point of view of the legacy or IEEE 802.1Q bridges, moreover, each MST Region appears as a single "virtual" bridge on the CST.
Within each MST Region, the MSTP compatible bridges establish a plurality of active topologies, each of which is called a Multiple Spanning Tree Instance (MSTI). The MSTP bridges also assign or map each VLAN to one and only one of the MSTIs. Because VLANs may be assigned to different MSTIs, frames associated with different VLANs can take different paths through an MSTP Region. The bridges may, but typically do not, compute a separate topology for every single VLAN, thereby conserving processor and memory resources. Each MSTI is basically a simple RSTP instance that exists only inside the respective Region, and the MSTIs do not interact outside of the Region.
MSTP also uses BPDUs to establish the ISTs and MSTIs as well as to define the boundaries of the different MSTP Regions. The bridges do not send separate BPDUs for each MSTI. Instead, every MSTP BPDU carries the information needed to compute the active topology for all of the MSTIs defined with the respective Region. Each MSTI, moreover, has a corresponding Identifier (ID) and the MSTI IDs are encoded into the bridge IDs. That is, each bridge has a unique ID, as described above, and this ID is made up of a fixed portion and a settable portion. With MSTP, the settable portion of a bridge's ID is further organized to include a system ID extension. The system ID extension corresponds to the MSTI ID. The MSTP compatible bridges within a given Region will thus have a different bridge ID for each MSTI. For a given MSTI, the bridge having the lowest bridge ID for that instance is elected the root. Thus, an MSTP compatible bridge may be the root for one MSTI but not another within a given MSTP Region.
Each bridge running MSTP also has a single MST Configuration Identifier (ID) that consists of three attributes: an alphanumeric configuration name, a revision level and a VLAN mapping table that associates each of the potential 4096 VLANs to a corresponding MSTI. Each bridge, moreover loads its MST Configuration ID into the BPDUs sourced by the bridge. Because bridges only need to know whether or not they are in the same MST Region, they do not propagate the actual table(s) mapping VLANs to MSTIs in their BPDUs. Instead, the MST BPDUs carry only a digest of the VLAN-to-MSTI mapping table(s). The digest is generated by applying the well-known MD-5 algorithm to the VLAN-to-MSTI mapping table(s). When a bridge receives an MST BPDU, it extracts the MST Configuration ID contained therein, including the digest, and compares it to its own MST Configuration ID to determine whether it is in the same MST Region as the bridge that sent the MST BPDU. If the two MST Configuration IDs are the same, then the two bridges are in the same MST Region. If, however, the two MST Configuration IDs have at least one non-matching attribute, i.e., either different configuration names, different revision levels and/or different computed digests, then the bridge that received the BPDU concludes that it is in a different MST Region than the bridge that sourced the BPDU. A port of an MST bridge, moreover, is considered to be at the boundary of an MST Region if the Designated Bridge is in a different MST Region or if the port receives legacy BPDUs.
FIG. 2 is a highly schematic block diagram of an MST BPDU 200. The MST BPDU 200 includes a header 202 compatible with the Media Access Control (MAC) layer of the respective LAN standard, e.g., Ethernet. The header 202 comprises a destination address (DA) field, a source address (SA) field, a Destination Service Access Point (DSAP) field, and a Source Service Access Point (SSAP), among others. The DA field 204 carries a unique bridge multicast destination address assigned to the spanning tree protocol, and the DSAP and SSAP fields carry standardized identifiers assigned to the spanning tree protocol. Appended to header 202 is a BPDU message area that includes an "outer" part 204 and an "inner" part 206. The outer part 204 has the same format as an RSTP BPDU message and is recognized as a valid RSTP BPDU message by bridges that do not implement MSTP. The "inner" part 206 is utilized by bridges executing MSTP to establish the IST and the MSTIs. The inner part 206 has a set of spanning tree parameters for the IST and a set of parameters for each MSTI supported by the bridge sourcing the MSTP BPDU 200.
Outer part 204, also referred to as the CIST priority vector, has a plurality of fields, including a protocol identifier (ID) field 208, a protocol version ID field 210, a BPDU type field 212, a flags field 214, a CIST root ID field 216, an external path cost field 218, a CIST regional root ID field 220, a CIST port ID field 222, a message age field 224, a maximum (MAX) age field 226, a hello time field 228, and a forward delay field 230. The flags field 214 of other part 204 includes the flags 130-142 (FIG. 1) described above in connection with the RSTP BPDU message format. The CIST root identifier field 216 contains the identifier of the bridge assumed to be the root of the Common and Internal Spanning Tree, which may be in the same MSTP Region as the bridge sourcing the BPDU message 200, in another MSTP Region or in part of the bridged network that is not running MSTP. The external path cost field 218 contains a value representing the lowest cost from the bridge sourcing the BPDU 200 to the CIST root identified in field 216 without passing through any other bridge in the same region as the bridge that is sourcing the BPDU message 200.
Inner part 206, also referred to as an MSTI priority vector, similarly has a plurality of fields, including a version 1 length field 232, a null field 234, a version 3 length field 236, an MST configuration ID field 238, a CIST regional root ID field 240, a CIST regional path cost field 242, a CIST bridge ID field 244, a CIST port ID field 246, a CIST flags field 248, and a CIST hops field 250. Inner part 206 may further include one or more optional MSTI configuration messages 252, each of which constitutes another MSTI priority vector or M-record.
Because version 2 of the RSTP does not specify any additional fields beyond those already specified by version 1, the MST BPDU does not have a version 2 length field.
Each MSTI Configuration Message 252 consists of a plurality of fields including a CIST regional root ID field 260, a CIST regional path cost field 262, a CIST bridge ID field 264, a CIST port ID field 266, a CIST flags field 268 and a CIST hops field 270. MST bridges utilize the STP parameters contained in fields 240-150 of inner part 206 and in each MSTI configuration message 252 to compute an active topology for each MSTI configured in the respective region.
Stack Arrangements
Multiple network devices, such as switches, may also be physically connected and logically organized to form a stack or cluster that can be made to appear to other entities or devices within the computer network at least logically as a single, virtual switch. One such technique involves forming a cascaded switch network by coupling multiple physical switches together via suitable bus connection links, such as Ethernet, Fast Ethernet, Fast EtherChannel®, Cisco GigaStack Gigabit Interface Converter (GBIC), Gigabit Ethernet, and Gigabit EtherChannel connections, among others (which may comprise additional circuitry), and programming the switches' internal control and forwarding circuitry, e.g., switch network management, bridge forwarding, etc., so as to permit the switches to operate as a single virtual switch. Examples of such clusters include the Catalyst Matrix™ from Cisco Systems, Inc.
The deployment of such stack or cluster designs within computer networks can affect the operation of the spanning tree protocol. Accordingly, a need exists for a technique that prevents loops while working efficiently with network devices organized into a stack or cluster.