A system and method for reordering data fragments to facilitate reads from a DDR SDRAM where the fragments are placed into a first and second data fragment buffer such that the data fragments are in sequential addresses whereby the second data read on the trailing edge of the clock cycle will read the proper data fragment.

1. Field of the Invention
The present invention generally relates to computer systems. More particularly, the present invention relates to a system and method of processing graphics-related data through re-ordering fragment data based on rasterization direction to line up with a DDR-SDRAM addressing order.
2. Description of the Related Art
In traditional graphics rendering, the last stage of rendering is referred to as rasterization. The rasterization stage of rendering converts transformed primitives into pixel values, and generally stores them in a frame buffer. Rasterization requires the calculation of each primitive""s contribution to each pixel. In a software rendering system, rasterization can be performed in two orders: primitive by primitive (object order), or pixel by pixel (image order). Most systems rasterize in object order, using a z-buffer algorithm to computer visibility.
In high data rate applications such as graphics rendering, processing data is preferably handled through fast data transfer components, such as a Double-Data-Rate (DDR) Synchronous Dynamic Random Access Memory (DDR-SDRAM or DDR). A DDR SDRAM differs from a standard DRAM (or SDRAM) in that it uses a separate strobe signal by which some or all of its data timing is referenced, and both the rising and the falling edges of the strobe signal are used to clock data into its destination. Using both edges of the strobe signal to transfer data thus doubles the amount of data transferred in a given time interval.
In rasterization with a DDR SDRAM, a problem arises in that the DDR SDRAM is only provided one address per clock cycle. Accordingly, the data received from the DDR SDRAM will typically come from the first address (n) and then from the next logical address (n+1). However, in some applications, the data does not logically flow from the addresses n to n+1, and the second data fragment read on the trailing edge clock signal will be discarded. This problem is particularly acute in graphics rendering because different kinds of objects are being drawn which are not likely to have pure linear or otherwise intuitive data flow, or in other words, the objects may not be drawn in the same direction during rendering. The speed advantage of a DDR SDRAM can thus be lost in a graphics rendering application because the data read at n+1 is not the correct data required following the read of n and the data fragment read from n+1 must be flushed from the pipeline.
Accordingly, it would be advantageous to provide a system and method that increases efficiency though providing accurate data from the DDR SDRAM when a processor is drawing in a direction not well oriented to the DDR SDRAM addressing. Such system and method should be compatible with the rasterization data in graphics rendering whereby the data fragments can be reordered such that the correct data fragment is present at the read occurring on the trailing edge of the clock signal. It is to the provision of such a system and method of reordering data fragments that the present invention is primarily directed.
The present invention is a system and method for reordering data fragments to facilitate reads from a DDR SDRAM where the data fragments are placed into a first and second data fragment buffer such that the data fragments are in sequential addresses whereby the second data read on the trailing edge of the DDR SDRAM clock cycle will read the proper data fragment. In particular, the system includes a first data fragment buffer (n) and a second data fragment buffer (n+1), and upon presentation of a first data fragment having an address and second data fragment having an address, the system compares the first data fragment address with the second data fragment address and if the second data fragment address is the next sequentially readable data address after the first data fragment address, the system stores the first data fragment in the first data fragment buffer and the second data fragment in the second data fragment buffer. Or, if the second data fragment address is sequentially readable before the first data fragment address, the system stores the second data fragment in the first data fragment buffer and the first data fragment in the second data fragment buffer. Otherwise, if the first data fragment address and second data fragment address are non-sequentially readable, the system flushes the first (oldest) data fragment.
The system preferably flushes the first and second data fragments once they are stored in sequential order and obtains a new first and second fragment for comparison. Alternately, the system can also flush solely the first data fragment once stored, make the second data fragment the first data fragment, and obtain a new data fragment. In other words, when the second data fragment is stored in the second data fragment buffer (n+1), the system can make the second data fragment the first data fragment prior to obtaining a new data fragment to become the second data fragment. Otherwise, if the system stores the second data fragment in the first data fragment buffer (n) and stores the first data fragment in the second data fragment buffer (n+1), it can likewise make the second data fragment the first data fragment and iterate the reordering process and obtain a new second data fragment. However, the system preferably flushes both fragments upon proper sequential ordering of the fragments in the data buffers and obtains two new fragments to become the first and second data fragments and iterates the ordering process.
The first and second data fragment buffers are preferably first-in-first-out buffers. Moreover, the DDR SDRAM can read data directly from the first data fragment buffer and second data fragment buffer, or the first data fragment buffer and second data fragment buffer can each store data fragments in another storage location, prior to the data fragments being read from a DDR SDRAM.
The present invention further provides a method for reordering data fragments to facilitate reads from a DDR SDRAM using a first data fragment buffer and a second data fragment buffer including the steps of presenting a first data fragment having and address where the first data fragment is intended to be read by a DDR SDRAM, presenting a second data fragment having an address where the second data fragment is intended to be read by a DDR SDRAM, and comparing the first data fragment address with the second data fragment address. If the second data fragment address is the next sequentially readable data address after the first data fragment address, the method includes the step of storing the first data fragment in the first data fragment buffer and the second data fragment in the second data fragment buffer. And if the second data fragment address is sequentially readable before the first data fragment address, the method includes the step of storing the second data fragment in the first data fragment buffer and the first data fragment in the second data fragment buffer. Otherwise, if the first data fragment address and second data fragment address are non-sequentially readable, the method includes the step of flushing the second data fragment. The method further preferably includes the step of obtaining new data fragments to become the first and second data fragments after the data fragments have been stored in the first and second buffers.
Preferably, upon the step storing the second data fragment in the first data fragment buffer and the first data fragment in the second data fragment buffer, the method further includes the step of either flushing the first and second data fragment and obtaining two new fragments for comparison and sequencing, or making the second data fragment the first data fragment prior to obtaining a new data fragment to become the second data fragment. If so embodied, the steps of storing the first data fragment and second data fragment are storing the first data fragment and second data fragment in first first-in-first-out buffers and second first-in-first-out buffers respectively. Further, the method can either includes the step of the DDR SDRAM reading data directly from the first data fragment buffer and second data fragment buffer, or alternately, the method can further include the steps of storing data fragments from the first data fragment buffer in another storage location, and storing data fragments from the second data fragment buffer in another storage location, prior to the data fragments being read from a DDR SDRAM.
The present invention accordingly provides several advantages in a computer system utilizing DDR SDRAMs. The use of the system improves DDR SDRAM memory efficiency as erroneous reads on the trailing edge clock cycle are minimized. Further, the system reduces buffer (FIFO) storage requirements as erroneous data is not required to be buffered when errantly read, which accordingly reduces the need for cached data fragments. Finally, the system simplifies downstream logic on the system as flushes of errant data are minimized so significant downstream error checking hardware is unnecessary.
Other objects, features, and advantages of the present invention will become apparent after review of the hereinafter set forth Brief Description of the Drawings, Detailed Description of the Invention, and the Claims.

System and method for reordering fragment data based upon rasterization direction


Disclosed is a disk for adjusting the angle of a snowboard binding. A base plate of the snowboard binding has a toothed gear formed at an inner periphery of a center opening thereof. As toothed gear formed at outer ends of disk gears included in the disk are engaged with the toothed gear of the base plate of the snowboard binding when a disk lever provided at the center of the disk is rotated clockwise or counterclockwise, the disk can be mounted to the base plate of the snowboard binding, so as to control the angle of the snowboard binding.

Snowboarding has a need for special motions and physical requirements not discovered in other sports including skiing. A person who rides a snowboard, i.e. snowboarder should stand on the snowboard only with his/her feet by use of devices used to safely attach the feet onto the snowboard. However, the attachment devices have a significant limit in strength and installation position thereof. It is noted that, when descending a snow-covered slope by snowboarding, a motive force to drive the snowboard is gravity. Therefore, the snowboarder needs to carefully guess the position of his/her body differently from other sports. In particular, it is noted that an angle between the center axis of each foot and the center axis of a snowboard greatly varies according to different snowboarders and various snowboarding tricks and descent techniques. Also, a boot set into a binding mounted on the snowboard is often used as a device to support the lower part of the leg right above the ankle. However, if the ankle at the center of the leg is changed in position relative to the snowboard, it may cause a change in an angle between the leg and the foot. Currently, there has been generally used a pair of rigid supporting devices vertically erected from a snowboard and aligned, respectively, with the center axes of both feet. The supporting devices are designed to be folded down onto a surface of the snowboard. Meanwhile, to assure a freedom in the implementation of various snowboarding motions, it is necessary to appropriately control the dismantling and remounting of bindings to and from a snowboard. Also, a distance between two bindings attached onto the snowboard and relative positions of the bindings on the basis of a longitudinal length of the snowboard should be changed according to snowboarders having different body sizes.

Disk for controlling an angle of binding in snowboard


A filterwell cartridge holder mountable within a hot tub filterwell with the filterwell cartridge holder having a handhold on one end and a feed pipe connector on an opposite end that is attachable to or removable from a filterwell feed pipe with the filterwell cartridge holder engaging and supporting dispensing cartridges thereon to maintain the dispensing cartridges in a dispensing mode within the filterwell.

While the prior art reveals multiple types of dispensing cartridges and cartridge holders useable in various bodies of water one of the more challenging locations for a dispensing cartridge and a dispensing cartridge holder is in the open top filterwell of a hot tub or spa where water flows from a main tub area, where persons sit, into a separate smaller water compartment containing a water filter, with the smaller water compartment referred herein as a filterwell. During hot tub or spa operation the water flows through a water cartridge filter in the filterwell, which removes debris from the water, before returning the water to the main tub area. The location of a dispensing cartridge in the filterwell has the advantage of keeping the dispensing cartridge out of the main tub area of the hot tub or spa and in a region where water flows therethrough; however, the dispensing cartridge needs to be able to reliably deliver disperant into the water as the water flows through the filterwell. To do so the dispensing cartridge preferably should be mounted on a filterwell cartridge holder that is locatable in the filterwell with both the filterwell cartridge holder and the dispensing cartridge thereon having minimal or no interference with the water filtering action within the filterwell.
In addition the flow of water through the filterwell, which is a small compartment where water flow patterns change as a result of change of activity level in the hot tub, can cause a free floating dispensing cartridge or to be tossed about within the filterwell. Such tossing action can affect the delivery rate of the dispensing cartridge as well as cause damage to the water cartridge filter in the filterwell and the dispensing cartridge. To avoid such difficulties both the filterwell cartridge holder and the dispensing cartridge thereon should be stably supported within the filterwell.
In addition, since the consumer needs to periodically replace the dispensing cartridge it is desirable to have convenient access to the filterwell cartridge holder and the dispensing cartridges thereon. That is, the filterwell cartridge holder should support the dispensing cartridges thereon so as to prevent a dispensing cartridge from hitting the walls of the filterwell due to the changing or swirling water flow patterns within the filterwell since either or both the dispensing cartridge or the walls of the filterwell could be damaged. In addition the violent action of the dispensing cartridge being tossed about in the filterwell can generate unwanted noises and improper dispensing rates.
U.S. Pat. No. 5,779,913 describes the mounting of a dispensing cartridge on the end of a stick, which is then placed within the core of a water filter cartridge. Unfortunately, the stick dispenser, which comprises an elongated dispenser with a severable stick on one end, does not prevent the stick dispenser from being buffeted about by water currents within the water cartridge filter. In addition, access to the stick dispensing cartridge, which is located within the water filter core, is inconvenient since the water filter needs be detached to replace the dispensing cartridge. Still other dispensing systems show the attachment of a dispenser cartridge directly to a weir gate or a skimmer basket, which are located outside the filterwell.
While access and stable positioning of the dispensing cartridge and the filterwell cartridge holder within the filterwell is important it is also important that the filterwell cartridge holder can be easily mounted in the filterwell without disruption of the filterwell structure and with minimal interference with the water flow patterns through the filterwell. In addition, the dispensing cartridges supported on the filterwell cartridge holder need to be periodically removed from the filterwell cartridge holder and then replaced with fresh dispensing cartridges.
The filterwell cartridge holder should allow a dispensing cartridge thereon to be easily removed and replaced since the dispensing cartridge may have to be removed from the filterwell cartridge holder to change the dispensing cartridge delivery rate or in some case to replace the dispensing cartridge. Preferably the filterwell cartridge holder should be conveniently positionable and securable within the filterwell and preferably removable or securable therein without the aid of any tools.


The present invention is to provide a monitor display control apparatus and a monitor display control method, in which ease of operation of scrolling a map image can be improved with an intention of an operator being reflected at the time of scrolling the map image. A value RV corresponding to the square of a distance up to a current position centering on a reference position is operated on the basis of output voltages of potentiometers detecting a tilted position of an operating rod. In a control unit, a scrolling speed and a scale factor of the map image displayed on a display screen of a monitor television are varied in accordance with a signal UP including information on an amount of displacement of the operating rod from the reference position.

1. Field of the Invention
The present invention relates to a monitor display control apparatus and a monitor display control method in which a map image is displayed on a display screen of a monitor component such as a car navigation device loaded on a vehicle, or the like.
2. Description of the Related Art
There are automobiles in which a car navigation system is installed. The car navigation system has a monitor component, and a map image or the like can be displayed on a display screen of the monitor component. Further, when a map image is being displayed on the display screen of the monitor component, a cursor is displayed on the center of the display screen. In this case, the map image is made to move (scroll) relatively with respect to the cursor in accordance with input from an operation component.
As such a car navigation system, there is a car navigation system in which a relative moving speed (scrolling speed) of a map image with respect to a cursor can be varied in plural stages in order to rapidly find out a destination or the like.
For example, there is a car navigation system in which a scroll key for scrolling a map image on a display screen is provided, and there is disclosed one example thereof in Japanese Patent Application Laid-Open (JP-A) No. 8-69515. This system is structured such that a scale factor of the map image displayed on the display screen is varied in stages and automatically in predetermined time units while maintaining a scrolling speed to be constant when a time of continuous thrusting the scroll key is increasing.
Moreover, in this system, when a destination has been registered in advance, the scale factor of the map image is varied so as to be approximate to an original scale (maximum enlarged display) as the destination approaches the cursor on the display screen. Namely, when the destination approaches the cursor on the display screen, the map image is displayed to be enlarged in spite of a time of continuous thrusting the scroll key, and the contents of the map image are reported in detail.
However, even when the destination has approached the cursor on the display screen, when the destination has not been registered in advance, the scale factor of the map image is not varied to an original scale (maximum enlarged display), and there are cases in which the map image is displayed in a wide range (displayed to be reduced). In such a case, it is necessary to interrupt thrusting the scroll key once, and to display the destination and the vicinity of the destination to be enlarged due to the scale factor of the map image being returned to the current scale. Namely, scrolling of the map image must be once interrupted in order to obtain the detailed information on the destination and the vicinity of the destination. As a result, an operation in which thrusting of the scroll key is interrupted and the scroll key is thrust again is required, and there is the disadvantage that the operation of the scroll key is made to be troublesome, and the ease of operation of scrolling a background image has been poor.
Further, there is a car navigation system in which, when a joy stick key provided to a remote controller for inputting various indications is tilted relatively from the reference position thereof for a long time, the scrolling speed is accelerated and only the road information highly necessary for a driver is displayed on a display screen of a monitor component, and there is disclosed one example thereof in JP-A No. 8-219803.
However, from the time when the joy stick key is tilted to the time when a predetermined time passes, the scrolling speed of the map image is not accelerated, it is difficult to instantly vary the scrolling speed of the map image (for example, to accelerate the scrolling speed) with an intention of the operator being reflected. Further, because this system is not structured such that a scrolling speed of the map image is limited to an extent in which the contents of the map image can be grasped when the scrolling speed is accelerated, there are cases in which the driver cannot visually recognize the map image when the scrolling speed is made fast. Moreover, because this system has a structure in which the map image cannot be displayed in a wide range (a structure in which the scale factor of the map image is made to be constant), a region which does not include a destination and the vicinity of the destination is made to be on an original scale (is displayed to be enlarged). As a result, there is the disadvantage that, even when the driver wishes to display the map image in a wide range, the system cannot correspond thereto, and the ease of operation of scrolling a background image has been poor.
Moreover, there is a car navigation system in which, when an operation of a shift key of the remote controller is carried out in a state in which an operation of the joy stick provided to the remote controller is continued, a scale factor of the map image displayed on the monitor component is varied only during the time when the operation of the shift key is being carried out, and there is disclosed one example thereof in JP-A No. 2002-81942. In this system, when the operation of the shift key is interrupted, the scale factor of the map image is automatically returned to the scale factor before the operation of the joystick was started. In this way, this system can momentarily vary the scale factor of the map image displayed on the display screen of the monitor component.
However, when an attempt is made to return the display from being in a wide-range display to being on an original scale (enlarged display), the operation of the joystick must be interrupted, i.e., the scrolling of the map image must be once stopped. In this way, in this system, because scrolling of the map image cannot be smoothly carried out, it cannot be necessarily said that the ease of operation of scrolling the map image is excellent.

Monitor display control apparatus and monitor display control method


Disclosed is a process for treating oily wastes, which have a predominantly liquid phase, by mixing the oily waste with a granulating medium under turbulent flow conditions. The process comprises mixing the oily waste with a granulating medium under such conditions, wherein granules are formed having an attrition index of less than about 10 percent and a filtration index of greater than 0.20 gallons per minute per square foot. The contaminating hydrocarbons may then be removed by contacting the granules with a solvent capable of removing at least a portion of the contaminating hydrocarbons. The granules are then recovered by means known in the art.

1. Field of the Invention
The present invention relates to a method for treating oily wastes by forming the waste into granules. More particularly, the method uses a high speed mixer to form granules of a discrete size, from which a portion of the contaminating hydrocarbons may be removed.
2. Description of Related Art
Treatment of oily waste material and, especially soils and particle fines which have been burdened with oily materials, has been and continues to be a problem. In the past, various methods have been used in an attempt to consolidate or to encapsulate the material prior to further treatment or to disposal of the material.
One method to treat oily wastes is to extract the hydrocarbons from the oily waste with a solvent. An example of a method is disclosed in U.S. Pat. No. 4,931,161, the disclosure of which is incorporated herein by reference, involves adding solids to the oily waste, then granulating the mixture. The granules are then contacted with a solvent to recover the hydrocarbons. The process however, produces granules of varied size and must be crushed and screened for uniformity.
Another method of treating the oily waste is to mix the waste with water containing modifiers under conditions that result in the material forming a slurry. The modifiers enhance the scrubbing effect of the water. However, a major consideration of all washing techniques is the fact that as the particle reject size decreases, handling and cleaning efficiency likewise decreases. This requires the fines to be separated by centrifuges, belt filters, and other costly methods known in the art. Because these fine particles are carried out of the cleaning system relatively early they contain higher amounts of harmful substances and may also constitute more than 30% of the soil being treated.
Another method is to convert the oily waste material to a substantially impermeable, load-bearing construction material. U.S. Pat. No. 4,514,307 provides an example of such a method. According to the '307 patent, waste material is combined with cementitious reactants consisting essentially of lime and fly ash, in the presence of water, to form a mixture in which the relative proportions of the waste material, linde, fly ash, and water are adapted to permit the lime and fly ash to react at atmospheric conditions and thus to form a cementitious matrix in which the waste material is encapsulated.
Still another method of treating oily wastes involves combining the waste with solids and then incinerating the mixture. U.S. Pat. No. 4,775,457 provides an example of such a method. According to the '457 patent crude oil and other heavy hydrocarbon sludges are mixed with adsorbent material, preferably an earth material, such as diatomaceous earth or perlite, and oxidized in an incinerator or calciner to produce gaseous combustion products and a friable solids material which is substantially hydrocarbon free and may be recycled for mixture with the incoming sludge stream or otherwise disposed of in an environmentally acceptable manner.
A disadvantage in using any of the aforementioned processes is that the particle size, to a large degree, is random. Particles may range in size from less than 0.003 to greater than 3 inches. This non-uniformity significantly hinders hydrocarbon removal from the granules in subsequent process steps.
It is, therefore, a principal object of the present invention to provide a method for producing free flowing granules having a discrete size. Preferably, the granules have a particle size of less than about 0.5 millimeters. As used herein, the term "free flowing" is defined as a powder that flows freely with no bridging in the bulk when withdrawn from the bottom of a conical hopper having a 30.degree. included angle.
It is another object of the invention to improve the efficacy of solvent extracting the hydrocarbons from the granules. These and other objects are accomplished by the invention set forth in the description and examples below.


A method includes receiving market data associated with an investment product that specifies a first guaranteed annual withdrawal amount and a second guaranteed annual withdrawal amount, where the first guaranteed annual withdrawal amount is greater than the second guaranteed annual withdrawal amount. The method includes automatically selecting a guaranteed annual withdrawal amount from the first guaranteed annual withdrawal amount and the second guaranteed annual withdrawal amount based on at least an evaluation of the market data.

Investment products are often tailored to address the investment goals of investors. Investors may have concerns related to a loss of principal investment due to market returns and volatility, having the ability to increase income, and ensuring an adequate amount of retirement savings and not outliving their income. In the past, a retiree typically relied on employer pension plans and Social Security to meet these concerns. However, these traditional sources of retirement income may no longer be sufficient to satisfy these concerns.
Investment product issuers derive revenue by selling the products to investors and charging fees associated with the products. However, investment products that provide guarantees to an investor regarding the value, benefits or payments of the investment product are also a source of financial risk to the investment product issuers. To manage and mitigate this financial risk, an issuer typically offers the financial product subject to special rules and fees that are incorporated into the financial product through an agreement with the investor. Such agreements can be a legal contract, product terms and conditions, a rider to a contract, a certificate, etc.
For example, an annuity is a contract in which an investor makes a lump-sum payment or series of payments in exchange for periodic payments that begin either immediately or at some future date. In general, two types of annuities exist, a fixed annuity and a variable annuity. A fixed annuity is designed such that the investor earns on a tax deferred basis a minimum guaranteed rate of interest, plus any discretionary higher rate, during the time that the investor's account is growing. Periodic payments may last for a definite period, such as 20 years, or an indefinite period, such as the lifetime of the investor, or the lifetimes of the investor and the spouse of the investor. In contrast, in a variable annuity, an investor may elect to invest in a range of different investment options, typically either in a fixed option (similar to a fixed annuity), or in underlying funds (similar to mutual funds). The rate of return on the variable annuity and the amount of the periodic payments to be paid often varies depending on the performance of the investment options selected.


An image generating apparatus and a display device for a layered display scheme based on a location of an eye of a user are provided, wherein the image generating apparatus may generate layer images for a three-dimensional (3D) image based on information related to pixels matched based on the location of the eye of the user.

1. Field
Example embodiments of the following description relate to a scheme of generating an image to display a three-dimensional (3D) image and a 3D image display device.
2. Description of the Related Art
Among factors related to three-dimensional (3D) image recognition, the foremost factor is a disparity between images viewed by both eyes of a user. Methods of providing different images to both eyes of a user may be classified into a stereoscopic type and an autostereoscopic type. The stereoscopic type method may filter a desired image through division using a polarized light, time division, and a wavelength division for differentiating a wavelength of a primary color. The autostereoscopic type method may enable images to be viewed in a predetermined space only using a parallax barrier or a lenticular lens.
The autostereoscopic type method may alleviate an inconvenience of wearing glasses. However, in the autostereoscopic type method, a great number of views may be used to broaden a viewing area, an image quality may deteriorate due to a crosstalk between views, and the image quality may also deteriorate remarkably at a location outside of a determined optimal viewing distance.

Image generating apparatus and display device for layered display scheme based on location of eye of user


A clock distribution system for an integrated circuit comprising a plurality of regions (1, 2, 3) connected by a communications bus (12). Each region comprises a functional block (10a, 10b, 10c) and at least one bus node (14a, 14b, 14c) for connecting a respective functional block to the communications bus (12). A distributed clock signal (16) is allowed to skew between regions, but synchronised within respective regions. A predetermined clock insertion delay (20a, 20b, 20c, 22a, 22b, 22c) is inserted in each functional block and bus node.

Integrated circuits require a clocking scheme in order to execute instructions and transfer data between functional blocks on the integrated circuit in a synchronised manner. The aim of conventional integrated circuits is for the clock signals to arrive at every circuit element or module simultaneously, so that the circuit elements operate in synchronism. Integrated circuits are therefore typically designed so that the clock signal is distributed in a symmetrical manner across the chip from a centrally located clock reference.
Despite the symmetry associated with prior art clock distribution schemes, imperfections in circuit conductors and variations introduced in the manufacturing process introduce clock skew between circuit elements or modules.
Existing development tools for designing integrated circuits have an automated process for distributing a balanced clock across a chip, so that each of the functional units on the chip operate in synchronism. The automated process for balancing the clock involves a two-stage process. Firstly, a clock tree is inserted into each functional block. Each block has a different insertion delay. Once the functional blocks are placed on the layout floorplan, the second stage of the process involves balancing the clock tree in order to reduce clock skew to within acceptable limits. This involves inserting additional buffers in each path to balance the skew at all clock inputs to every register on the chip. Using this technique the clock tree can be balanced to within 200-300 ps.
The conventional process described above has a number of drawbacks. For example, although the task of inserting the clock buffers into each path to the functional units is relatively automated, the second stage of the process requires more manual intervention, i.e. the tools must be directed as to where the additional clock buffers are to be inserted. This process is time consuming and it is difficult to determine whether the clock skew is within the acceptable tolerance levels. The constant desire to increase clock frequencies means that the problems mentioned above become even more relevant. As a consequence, it becomes difficult to simulate a large integrated circuit within a reasonable time-frame.
The balanced clock tree described above is a standard part of synchronous design methodology. However, a further disadvantage of this technique is that all registers across the whole chip are updated by the arrival of the clock edge, which results in a massive spike in the current drawn by the chip. This current surge is undesirable from a number of viewpoints. For example, the current surges cause unwanted electromagnetic emissions and can also lead to reliability problems due to electromigration failures.
A further disadvantage is that the track sizes have to be larger than necessary to deal with the large current surges. In addition, areas of silicon must be left unused so that the top-level clock drivers can be inserted.
The aim of the present invention is to provide a clock distribution system for an integrated circuit which is tolerable to clock skew, and which simplifies the process of designing large integrated circuits.


An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms whereas the hardware layer communicates in the terms of the testing apparatus. Various communication interface points are provided to the software and hardware layers, as well as the interface for tester abstraction.

FIG. 1 (Background) is a block diagram illustrating an automatic test equipment ("ATE") 10 coupled with an integrated circuit 12. The fundamental task of an ATE is to test and characterize the functionality of integrated circuits. An ATE is typically a powerful computing platform. Generally speaking, testing an integrated circuit or "chip", which during a test is referred to as a device under test or "DUT," involves applying a stimulus, often digital and in the form of a series of logic 1's and 0's, to one or more input pins of the DUT. When the DUT is an analog device, the stimulus applied to the inputs and the expected response are analog and are typically represented by waveforms of varying amplitude or frequency. The DUT generates an output, also typically in the form of a series of logic 1's and 0's, from one or more output pins. The output is captured by the ATE and compared with the expected output to produce test results 14. Characterizing a DUT, in contrast, involves identifying how the DUT reacts to variations in parameters, such as clock speed, voltage levels, and temperature.
Typically, an ATE 10 is physically located at an integrated circuit fabrication facility or "fab." Purchase of an ATE is a relatively expensive capital equipment expenditure. As such, many fabricators do not dedicate an ATE to testing one particular type of chip, but instead deploy it to test and characterize many different types of chips that each require unique test and characterization routines. Test engineers or other personnel may run tests and characterize some or all of the chips being produced at the fabrication facility.
As new integrated circuits are developed with new features, a fabricator typically attempts to use an existing ATE to test and characterize the new chip. In many instances, the ATE vendor develops new hardware, sometimes referred to as instruments or pin electronics, to interface with the new integrated circuit and allow the ATE to conduct the desired tests. Conventionally, the ATE vendor also has to develop and deploy new software to communicate with the new hardware. It is often time consuming and difficult to adapt existing ATE to the new functionality. One additional problem that often occurs with conventional ATE's involves the difficulty in ensuring that existing test routines for chips being fabricated, perhaps for years, are able to run properly. Oftentimes, the existing routines must be modified and debugged at considerable time and expense to conform with the new software or hardware releases.
Aspects of the present invention provide a software framework or operating system deployable in an ATE that facilitate use of the ATE in testing many different chips, quick and easy reconfiguration of a test or characterization routine to focus on testing of a particular trouble spot for a chip, modularity, test release independence to ease of updating or reconfiguring the ATE to add new features, which might involve adding or upgrading software subroutines and adding or upgrading hardware of the ATE.

Automatic test equipment operating architecture


A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

Integrated circuits ("ICs") vary in complexity from, for example, an analog circuit comprising only a few basic electronic components, such as transistors and diodes, to a complex digital system including hundreds of millions of transistors. Although different design methods and Electronic Design Automation ("EDA") tools are arranged to design ICs of various levels of complexity, the fundamental process of IC design remains unchanged. That is, IC design engineers design an integrated circuit by transforming a circuit specification into geometric descriptions of physical components that creates the basic electronic components. In general, the geometric descriptions are polygons of various dimensions, representing conductive features located in different processing layers. The detailed geometric descriptions of physical components are generally referred to as integrated circuit layouts. After the creation of an initial integrated circuit layout, the integrated circuit layout is usually tested and optimized through a set of steps in order to verify that the integrated circuit meets the design specification and will perform as desired.
Shown in FIG. 1 is a flowchart that illustrates the common post-design testing and optimization steps. After an integrated circuit design process is completed (shown at 2), an initial integrated circuit layout is created (shown at 4). The layout is first design-rule checked and then verified to be equivalent with the desired design schematic. This step (shown at 6) is generally referred to as design-rule check (DRC) and layout versus schematic (LVS).
The step of RC extraction (shown at 8) is subsequently performed in order to "extract" electrical characteristics of the layout. The common electrical characteristics that are extracted from an integrated circuit layout include capacitance and resistance in the electronic devices and on the various interconnects (also generally referred to as "nets") that electrically connect the aforementioned devices. The current step is also referred to as "parasitic extraction" because these capacitance and resistance values are not intended by the designer but rather result from the underlying device physics of the device configurations and materials used to fabricate the IC.
The designed IC is then simulated (shown at 10) to insure the design meets the specification with the parasitic capacitance and resistance in the IC. If the parasitic capacitance and resistance causes undesirable performance, the integrated circuit layout is typically changed through one or more design optimization cycles. If the simulation results satisfy the design specification, the design process is completed (shown at 12).
It is known that the parasitic capacitance and resistance can cause various detrimental effects in a designed IC, such as undesired long signal delays on the nets. Thus, the impact of the parasitic capacitance and resistance on the performance of the designed IC must be accurately predicted so that design engineers can compensate for these detrimental effects through proper design optimization steps.
It is also recognized that, when device feature sizes shrink down to the ultra-deep submicron range (less than 0.25 micron), interconnect delays begin to dominate the total delay in an IC. Moreover, because of the reduced contact-to-gate electrode distance and increased device density in ICs made with advanced technology, contact/via capacitance accounts for an increasing proportion of the total interconnect delay, when compared with coupling capacitance between adjacent nets.
The existing extraction methodology is problematic in contact/via parasitic capacitance extraction. Currently, extraction efforts are mainly focused on the coupling capacitance between adjacent nets. The parasitic effects on the contacts and vias are addressed with much less accuracy. The lack of extraction accuracy on contact and via capacitance may cause large discrepancies between simulated results and actual circuit performance.
As an example, an existing full-chip extracting system is typically "polygon-based." In extracting a design layout, a circuit layout is first divided into small pieces wherein each small piece contains a recognized primitive polygon pattern (also generally referred to as primitive). The extraction system, then, extracts parasitic values (e.g., resistance, capacitance) by reading a pre-made, parasitic capacitance/resistance look-up table typically stored in a technology file (shown at 9) for the per-unit parasitic value of such a primitive polygon pattern. The full-chip parasitic value is usually obtained by arithmetic operations on the primitive geometric patterns. The actual contact/via shapes and size variations are generally ignored by the extracting system.
FIG. 2A shows a perspective view of a MOSFET transistor occurring in an IC, where contacts "C" having a cylindrical shape and variation in size are made from the first interconnect layer "M1" to the source/drain regions "S" and "D." In an existing parasitic extracting system as described above, the actual contact shape and variation in size are not taken into account. Instead, a per-unit capacitance value, usually derived from an ideal, square-shaped contact primitive, is usually used to calculate the contact-to-gate-electrode parasitic capacitance in the transistor. As a result, the simulated results can be overly pessimistic with a margin of over 10%.
FIG. 2B shows a perspective view of a portion in an IC, where vias having a cylindrical shape and variation in size are formed between the first interconnect layer "M1" and the second interconnect layer "M2." Similarly, during RC extraction step 8 in an existing full-chip extracting system, parasitic capacitance between vias and via-to-metal-layer is roughly estimated without taking account of the actual via shape, via density and variation in size.

Accurate parasitic capacitance extraction for ultra large scale integrated circuits

Taiwan Semiconductor Manufacturing Company, Ltd.


A finned projectile intended to be launched toward a target has a project body and a plurality of main fins attached to the projectile body to provide stability thereto in flight. In the preferred embodiment, each main fin includes a supplementary fin movably secured thereto for increasing the overall surface area to further enhance the stability of the projectile after launch. A pin and channel arrangement is used for slidably retaining the supplemental fin and the main fins together for deployment under forces on the projectile during launch and flight thereof. The channel arrangement further includes a portion which angles suddenly to lock the supplementary fin in the deployed position. The preferred embodiment also includes putty disposed within the channel for preventing deployment of the supplementary fin during normal handling of the projectile. The putty is shattered upon initial impact with the pin during launching of the projectile.

The present invention relates particularly to a fin assembly designed to increase fin surface area for projectiles.
Firing range tests of 60 mm (millimeter) solid fuel ramjet projectiles from a 120 mm gun revealed certain significant deviations from expected trajectory. Among the explanations for such behavior are: damaged fins (e.g., attributable to in-flight metal burning, or to in-bore contact with the propellant granules during the projectile release from its primer case), and insufficient fin normal force required for static stability. In an attempt to solve the problem, the area of each fin 10 (FIG. 1) ahead of the leading edge 12 of the fin was increased, as illustrated by the dashed area 15, to provide an additional normal force, viz. .DELTA..sub.1 F.sub.f, but the resulting increase in stabilization was found to be insufficient. This undesirable result is attributable to the smaller fin moment arm x.sub.1cp (of that additional force for the increased area) relative to the center of gravity (CG) of the finned projectile 17.
It was recognized that the addition of surface area 20 at the trailing edge 22 of fin 10-1 (and of the other fins 10-2, 10-3 and 10-4, the latter being hidden by the body of projectile 17 in FIG. 1), rather than at the leading edge, would be more effective because that solution would serve to produce a larger fin moment arm x.sub.2cp, and additional normal force .DELTA..sub.2 F.sub.1. However, such a solution could not be implemented because of the limitation on the distance .DELTA.x.sub.f, owing to projectile packaging constraints.
In part, the packaging constraints are better understood by reference to FIG. 2 as well as to FIG. 1. The projectile 17 is packaged for use in a conventional propellant case assembly. The case assembly includes a pusher disk 30 having a rotating band/obturator 32, and is partly inserted into the propellant charge casing 35. The set of geometrical constraints on the fin design includes the following. The fin height h (FIG. 1) is fixed because the maximum diameter d.sub.f is limited by the bore size of the gun. The fin root chord length cannot be extended beyond the base of the projectile in excess of the length .DELTA.x.sub.f (FIG. 1), because of projectile packaging considerations for the attachment to the primer case containing the propellant charge. Also, the number of fins of the projectile cannot be increased to exceed four, such as to six as a means to increase the fin surface area, because of a limitation on the number of sabot pieces permitted for positioning the projectile in the gun barrel.
It is a principal object of the present invention to increase the stabilization of finned projectiles during flight, to be able to maintain the trajectory of the projectile.
Another object of the invention is to provide a finned projectile with improved stability, and thereby with the capacity to more accurately follow a desired trajectory, without violating the many practical constraints on size, shape and number of the fins imposed on the projectile.

Finned projectile with supplementary fins

The United States of America as represented by the Secretary of the Army


In a materials treating furnace, a belt is provided for transporting articles to be treated through a high temperature treatment zone. The belt comprises a succession of interwoven links, each of which is made up of a length of tungsten wire which has been heated and wound around an elliptical mandrel to provide a link which is in the form of a slightly flattened helix having no sharp bends. The interweaving of the helical links provides a large number of interlocking contact points between successive links.

The present invention relates to the heat treatment of materials in a furnace and more particularly to an improved tungsten wire belt for transporting articles to be treated through a heat treating zone.
As is understood, various articles can be advantageously treated by being subjected to high temperature for a preselected period of time. Such treatment may for example, effect sintering of articles made by compacting powdered refractory metals or ceramics. Further, in some processes it is desirable that the articles be transported through a heat treating zone in a furnace rather than being loaded and unloaded in batches.
Conventionally, articles have been transported through a heating zones on link belts made up of wire formed as conventional belt links such as illustrated in FIGS. 2 and 3. However, even when fabricated of a refractory metal such as tungsten, such conventional belts have been shown to be relatively frail and have been limited to a maximum use temperature of 2000.degree. C. and light loads, e.g., one ounce per square inch.
Among the several objects of the present invention may be noted the provision of novel heat treating apparatus; the provision of such apparatus which provides heat treatment at temperatures in the order of 1200.degree.-2200.degree. C.; the provision of such apparatus in which articles may be transported through a heating zone on a flexible belt; the provision of such apparatus employing a belt which is not subject to failure; the provision of such a belt which will withstand substantial loading; the provision of such a belt which is highly reliable and which is of relatively simple and inexpensive construction. Other objects and features will be in part apparent and in part pointed out hereinafter.

High temperature transport belt for materials treating furnace


A fluid infusion system is described. Certain embodiments include an infusion syringe assessment device that assesses one or more characteristics of an infusion syringe coupled to a fluid infusion pump during use. The system may include a fluid infusion pump configured to accept the infusion syringe. The fluid infusion pump may advance an infusion fluid to a test subject in accordance with an infusion routine based on one or more of the assessed characteristics of the infusion syringe. The infusion routine may include at least one rate, at least one volume, at least one start time, at least one end time, and/or at least one duration.

1. Field of the Invention
The present invention generally relates to a system and method for controlled delivery of substances and more particularly to controlled infusion of test substances to a test subject.
2. Description of Related Art
The pharmaceutical industry, contract research organizations, academia, and government entities routinely test the efficacy and safety of new chemical entities using intravenous infusion in laboratory animals such as, rats, dogs, and certain nonhuman primates. In some cases, large-scale toxicology infusion studies that can be used to assess the safety of new chemical entities are performed on a number of subjects. For instance, studies may assess several hundred animals for extended periods of time (e.g., many months or more). In other cases, drug metabolism, pharmacology, or safety pharmacology studies are performed using fewer animals over shorter periods.
These studies and other veterinary and/or human medical and research applications may include the use of medical and laboratory infusion pumps (e.g., electromechanical infusion pumps and other pumps). Infusion pumps may include, for instance, numerous types of electromechanical infusion pumps such as syringe, piston, peristaltic, diaphragm, large volume, stationary ("pole mount"), and portable ("ambulatory") type pumps. Other infusion pumps utilize gravity, springs, pneumatics, hydraulics, gases and other means. These pumps may be used to deliver a fluid (e.g., a new chemical entity) at a controlled delivery rate to a laboratory test animal, for instance. Similar pump technologies may be used for laboratory animal infusion and human-use infusion. Often, methods for human-use infusion (e.g., in a healthcare application) may be tailored to a single patient's needs while laboratory animal infusion (e.g., in an industrial or research application) may include common parameters tailored for use with multiple animals.
During studies, test substances may be delivered to a test subject, such as a laboratory animal, via a fluid delivery system conduit. For example, the test subject may be connected to an infusion pump (e.g., a syringe pump) using a network of components to carry the fluid from a pump fluid reservoir (e.g., a syringe) to the test subject. The network of fluid-carrying components, which may be referred to as "tubing set", may include various combinations of catheter, needle, cannula, polymeric tubing, fluid swivel, luer connectors, stopcocks, metal tubing for connecting polymer tubing, air filters, particle filters, etc. During use, the steps of loading, unloading, programming, starting and stopping one or more pumps, and adding or removing fluid delivery conduit systems are typically performed manually. For example, operators may manually enter one or more delivery rates into a pump, load a fluid-filled syringe into the pump, start fluid delivery from the pump by pressing a start button on the pump, and stop the pump by pressing a stop button. Further, users may manually document, using pen and paper or using a computer according to Good Laboratory Practices (GLP's), all these steps, as typically required by regulatory bodies, such as the Unites States Food and Drug Administration (FDA). The recorded data may include the type of fluid solution delivered by a pump, a user name, a time and date of each step, and description of the cause and/or resolution of pump alarms (e.g., occlusion alarms, syringe empty alarms, and other alarms indicating adverse pumping conditions). These steps may be complex, time consuming, labor intensive (e.g., requiring many operator man-hours), and increase the likelihood of human error. Additionally, these steps may provide undesirable contact between an operator and a test subject. For example, undesirable contact may occur in the case of containment (e.g., of allergens, disease, and other contamination), need for reduction of stimulation of test subject (e.g., the study of physiological parameters including heart rate and blood pressure), and other cases.
Accordingly, it may be desirable to provide a technique (e.g., system and/or method) that reduces the complexity of delivering test substances to a test subject. It may be desirable to provide techniques suitable for automating certain aspects of the toxicologic infusion study processes. Automating certain aspects of the processes may reduce the man-hours required for infusion studies, improve the quality of infusion studies by reducing the likelihood of human error, and/or reduce operator contact with test subjects.

Controlled delivery of substances system and method


Techniques for providing access rights to different portions of a software application to one or more authorized users are described herein. An issuance license may be inserted into the software application that divides the software application into one or more portions and identifies, for each portion, one or more users that are authorized access to the portion. Each portion of the software application may then be encrypted using, for example, a different cryptographic key. When the software is executed, an end user license may then be requested that corresponds to a particular user and that entitles the particular user access to each portion of the software application that the issuance license identifies the particular user as being authorized to access. The end user license may then be used to decrypt each portion of the software application that the issuance license identifies the particular end user as being authorized to access.

It is common to use cryptography to protect or hide sensitive data found in software from being seen or used by third parties. For example, Information Rights Management (IRM) is a feature found in the Office® software package from Microsoft Corp. of Redmond, Wash. IRM can help prevent sensitive information from being distributed to or read by persons who do not have permission rights to access the content of the sensitive information. As another example, the Outlook® application, included in aforementioned Office® software package, enables users to create and send e-mail messages with restricted permission to help prevent messages from being forwarded, printed, or copied and pasted. Documents, workbooks, and presentations that are attached to messages with restricted permission are automatically restricted as well.
Sometimes, in addition to data that is found in software, the actual software product itself can be highly sensitive, such as, for example, in the case of software tools for Digital Rights Management (DRM) software systems. With the increased complexity of software products, it is becoming more difficult to control access to software products which may have many portions/sections, some of which are very sensitive to some users and some which may not be sensitive at all to other users.

Providing access rights to portions of a software application


A semiconductor device includes a first semiconductor chip that is mounted face-down on a substrate, a second semiconductor chip that is mounted face-up on the first semiconductor chip, and a dummy chip that is interposed between the first semiconductor chip and the second semiconductor chip. The dummy chip is made from a homogenous material comprising silicon or an alloy containing an atomic percentage majority of silicon.

1. Technical Field
The present invention relates to a semiconductor device which is particularly preferably applied to a three-dimensional integrated configuration.
2. Related Art
There has been a method in which a face-up mounted semiconductor chip is stacked on a face-down mounted semiconductor chip in a semiconductor device of related art in order to achieve high density packaging of the semiconductor chip.
For example, disclosed in an example of related art is a method for forming a conductor film on a rear surface of a second semiconductor chip mounted on a first semiconductor chip in order to restrain interference between the stacked semiconductor chips caused by noise.
Japanese Patent No. 3,681,690 is the example of related art.
However, in a stacked structure of the semiconductor chips of related art, the interference occurs between the stacked semiconductor chips caused by noise, disadvantageously leading to reduced reliability of the semiconductor device. Further, in the method disclosed in the example of related art, the conductor film needs to be formed on the rear surface of the second semiconductor chip mounted on the first semiconductor chip, disadvantageously leading to a complicated manufacturing process of the second semiconductor chip.

This patent is subject to a terminal disclaimer.

Thee-dimensional integrated semiconductor device and method for manufacturing same


An arithmetic processing device includes, a memory that stores a first data and a second data, a plurality of arithmetic circuits, a first memory arranged for each of the arithmetic circuits and that stores a first predetermined row having the predetermined number of the first data stored in the memory, a second memory arranged for each of the arithmetic circuits and that stores a second predetermined row having a predetermined number of the second data stored in the memory, and a plurality of multiply-add arithmetic circuits arranged for each of the arithmetic circuits, a number of the multiply-add arithmetic circuits corresponding to the predetermined number, each of the multiply-add arithmetic circuits that obtains a third data by executing the operation using the first data and the second data based on a result of performing a row operation which is an operation of one row of the first data.

A GPU (Graphic Processing Unit) used as an arithmetic processing device is originally a processor for image processing. However, the GPU is often used as a processor for machine learning since the GPU has a number of floating point multiply-add arithmetic circuits to be described later and is optimized for a matrix calculation. In addition, the GPU is generally used for a large amount of matrix calculation in deep learning.
In many cases, the deep learning uses a neural network to perform a processing. For example, the deep learning for image recognition includes two processes, that is, a forward process for determining what is a given image and a backward process for updating parameters of a neural network for determination. An arithmetic processing device for the deep learning uses a difference between a calculation result in the forward process and an expected value to perform the backward process so as to update the parameters of the neural network. Then, the arithmetic processing device uses the updated parameters to improve the accuracy of the forward process.
The neural network is composed of plural layers and an arithmetic processing such as a feature amount extraction is performed and learning is repeated in each layer. In this way, the neural network has a multilayer structure in which a different arithmetic processing is performed in each layer. With such a multilayer structure, in order to update the parameters for each layer, a difference between a calculation result of the subsequent layer and an expected value is obtained, and the learning is performed while propagating the difference to a preceding layer and propagating a result of difference calculation in the preceding layer to a layer previous to the preceding layer. The terms "preceding" and "previous" used herein are based on a direction in which the forward process proceeds.
An arithmetic processing mainly used for image recognition in the deep learning may include a process called a convolution neural network in which an operation called convolution (hereinafter, referred to as "convolution operation") is frequently used. For example, for image recognition, a weighting frame having predetermined parameters as elements in a region on an input image is disposed in the original image. Then, the results of multiplication of each element of the input image on which the weighting frame is disposed and each element of the weighting frame are added up to calculate the feature amount of the region on the input image in which the weighting frame is disposed. The integration of feature amounts calculated by performing the disposition of the weighting frame on the original image for the entire input image using the movement width of the predetermined weighting frame becomes an output image output as the result of the convolution operation. The weighting frame is e sometimes called a "filter".
For example, an image having 8×8 elements, that is, an 8×8 bit grayscale image (hereinafter, referred to as an 8×8 input image), is considered as an input image. Further, descriptions will be made of a case where a filter having 4×4 elements (hereinafter, referred to as a 4×4 filer) is used and is shifted column by column or row by row in the input image. In the following description, the direction in which a row extends is referred to as a "row direction" and a direction in which a column extends is referred to as a "column direction". In this case, when a 4×4 filter arranged at one end in the row direction of the 8×8 input image is moved 5 (=8-3) times in the row direction, the 4×4 filter reaches the other end. That is, the output image has five elements in the row direction. Similarly, when a 4×4 filter arranged at one end in the column direction of the 8×8 input image is moved 5 (=8-3) times in the column direction, the 4×4 filter reaches the other end. That is, the output image has five elements in the column direction as well. Therefore, the output image becomes a 5×5 image. Each element of the output image has a total value obtained by multiplying each element of the filter arranged on the input image and each element of the input image at a position corresponding to each element.
In a case of performing an operation for summing such multiplied values, an arithmetic processing device often uses an instruction (command) called fma (Fused Multiply Add). The fma is an instruction that performs a floating point multiply-add operation represented by (A×B)+C.
Further, when performing such a convolution operation, a method called SIMD (Single Instruction Multiple Data) is used in which one instruction is executed to simultaneously perform an arithmetic processing on plural pieces of data and obtain plural operation result outputs at the same time. For example, an operation using SIMD for processing four pieces of data in parallel will be described. In the following description, the SIMD that processes n pieces of data in parallel is called nSIMD. That is, the arithmetic processing in this case may be said to be 4SIMD arithmetic processing. In the following description, the operation using SIMD is referred to as a SIMD operation.
In the case of convolution operation using the 8×8 input image and the 4×4 filter described above, the arithmetic processing device may calculate four values at a time, which are obtained by multiplying one element of the filter in each disposition state in which the filter is shifted four times in one row, by a corresponding element of the input image. That is, when performing the 4SIMD operation, the arithmetic processing device may calculate elements of the output image corresponding to the state of the filters of four different arrangements in parallel.
In the case of performing such an arithmetic processing using SIMD, the arithmetic processing device stores data to be used for arithmetic operation out of data of the input image stored in a memory as a storage device, in a register used for the SIMD operation, and then performs one arithmetic operation. By repeating this processing, the arithmetic processing device may perform a convolution operation. For example, in the case of a 4SIMD arithmetic processing, four registers are used for one SIMD arithmetic operation. When storing data in registers in the SIMD operation, the arithmetic processing device uses a SIMD load instruction to store data in all the registers of the SIMD register at a time.
Here, in the convolution operation, each element of the filter and a corresponding element of the input image are used to obtain one element of the output image. Further, in the convolution operation using SIMD, since the iterative operation is performed while shifting the range of the filter, the same data is used many times in the concurrent convolution operation.
In a convolution operation in the related art, the multiplication of elements and the sum of multiplication results are collectively performed for each disposition state of one filter. Therefore, when a parallel calculation is performed in plural arithmetic circuits as in the case of using SIMD, in order to improve the processing speed, it is necessary to adjust the calculation order to avoid using the same data or to prepare and use the copying of the same data at the same time.
As a technique of the convolution operation, there is a conventional technique of a semiconductor integrated circuit in which the ranges of data lines accessible by adjacent arithmetic circuits overlap with each other. Further, as a technique for parallel processing of operations, there is a conventional technique of performing an arithmetic operation by using data expressions in which intermediate outputs of operation elements are multiplexed.
However, when adjusting the calculation order in order to avoid reading of the same data, a multiplication or a division is used to determine data to be used. Since the multiplication or the division is high in costs since they consume a large number of cycles by the arithmetic operation, as compared with an addition or a subtraction. In addition, during the arithmetic operation of the multiplication or division, there is a possibility that an arithmetic circuit may not operate every cycle. For this reason, adjusting the calculation order may lower the processing speed of the arithmetic operation. In addition, when preparing the copy of data in order to avoid reading of the same data, there is a possibility that rearrangement of data which is not used at the same time becomes complicated and the number of data to be copied increases. For example, when a single movement distance of the filter is two rows and two columns or more, the above-described problem arises because the data to be read is broken into each arithmetic circuit. That is, in the case of using a processing method which performs arithmetic operations collectively for each filter arrangement state, there is a possibility that high calculation cost may be incurred to improve the processing speed.
In addition, even when different data is used, depending on a method of moving data to a register, the data may not be read from the register. For example, when two arithmetic circuits attempt to read data from the same register at the same timing, it may be difficult to read the data. Therefore, there is a possibility that the processing speed of the arithmetic operation may be lowered.
In particular, in the forward operation, when plural arithmetic circuits are used, it is difficult to input appropriate data in order to avoid conflicts between the arithmetic circuits, which makes it difficult to improve the arithmetic processing speed.
Further, even when a semiconductor integrated circuit in which the ranges of data lines accessible by adjacent arithmetic circuits overlap with each other is used, it is difficult to suppress occurrence of conflicts between two or more arithmetic circuits. Furthermore, even with the conventional technique using data expressions in which intermediate outputs are multiplexed, there is a high possibility that conflicts in data input autobiography may be caused, which makes it difficult to improve the arithmetic processing speed.
Related techniques are disclosed in, for example, Japanese Laid-Open Patent Publication Nos. 07-282237 and 2005-346470.

Arithmetic processing device and control method for arithmetic processing device


Techniques of wireless charging involve a charging base configured to predict when the user is about to charge a device based on a state of the device. For example, the state of the device may be defined by inertial measurement units (IMUs). The charging base then activates in response to predicting that the user intends to charge the device. In some implementations, the prediction is based on a machine learning (ML) engine trained to classify a movement of a device by a user as being about to charge or not being about to charge. If a movement of a device is classified as being about to charge, the charging base activates before the device is detected by the charging base.

Some electronic devices may be charged wirelessly via a charging base. In order to trigger the charging in such electronic devices using the charging base, an electronic device is brought either into contact with the charging base or within some proximity to the charging base. Wireless charging is made possible through the use of resonant inductive couplings within such electronic devices and the charging base.

Predictive wireless charging of electronic devices


A non-volatile latch having a power supply terminal and a ground terminal is disclosed. The non-volatile latch includes a pair of cross-coupled inverter elements each having a power supply terminal and a ground terminal. Magneto-resistive elements are interposed between the power supply terminals of both cross-coupled inverter elements and the power supply terminal of the non-volatile latch. In addition, magneto-resistive elements are interposed between the ground terminals of both cross-coupled inverter elements and the ground terminal of the non-volatile latch. By including magneto-resistive elements in each supply line, the effects of transistor parameter variation can be minimized.

This invention relates to the field of electronic memory devices, and more particularly, to non-volatile memory devices that can assume a desired state when power is applied.
Most digital electronic devices use both logic gates and memory elements to implement a desired function. The memory elements are used to store initial, intermediate and/or final data. The logic gates are used to provide and/or receive the data to/from the memory elements, and perform the necessary data manipulation. In a typical digital system, the basic memory elements are bi-stable logic circuits known as latching elements. There are numerous types of latching elements including, for example, D-latches, RS-latches, JK-latches, etc. These latching elements are often combined to form various forms of flip-flops or other storage devices.
Latching elements typically use one or more feedback paths that have an even number of inversions. By providing an even number of inversions, the feedback path reinforces the data state of the latching element. To write a desired state to the latching element, the feedback path is typically overdriven or a switch is provided to temporarily interrupt the feedback path while a new data state is provided to the latching element. The most basic latching element includes a pair of cross-coupled inverters. There are, however, numerous other known implementations.
A limitation of many conventional latching elements is that the data stored therein is lost when power is lost or otherwise interrupted. For example, when a personal computer or other data processing system loses power, the data stored in the latching elements are lost. When power is restored, the data processing system assumes a state that is unrelated to the state of the data processing system before the power loss. Often, much of the processing that was completed coincident with or prior to the power loss is lost, or must be re-constructed and/or re-executed which can be a time consuming and tedious task.
In high reliability applications, a primary power source and an auxiliary power source may be provided to reduce the likelihood that the latching elements will experience a power loss. In such systems, an auxiliary power source is used when the primary power fails. A limitation of this approach is that significant overhead is required including an auxiliary power source, a power degradation detection mechanism and a power switching mechanism. In addition, the auxiliary power source is often a battery or the like that has a limited lifetime. Therefore, if the primary power source fails for an extended period of time, the auxiliary power source may also fail causing the latching elements to lose the data stored therein.
Another approach for minimizing the loss of data after a power failure is to maintain an audit trail for each transaction submitted to the system. In such a system, an audit trail is periodically written to a non-volatile storage medium such as a magnetic tape or hard drive. The audit trail typically includes a listing of the status of each transaction that is submitted to the processor. If the power fails, the latching elements within the system lose the data stored therein, as described above. However, after power is restored, the audit trail can be used to reconstruct the status of each transaction. Only those transactions that were not completed and stored must be re-submitted for processing. This can significantly reduce the amount of data re-processing required after a power failure. However, significant time and resources are typically required to read the audit trail data and determine the status of each transaction.
It would be desirable, therefore, to provide a latching element that does not lose data when power is lost or otherwise interrupted. This may reduce the need to provide an auxiliary power source and/or audit trail system or the like.


In an apparatus for cleaning a soiled film in which the soiled film is passed upwardly through a wet cleaning station wherein a liquid cleaning agent is applied to the soiled film by means of wick plates which are pressed against the film from opposite sides and which extend downwardly into a liquid cleaning agent storage chamber from which they draw cleaning agent for wetting the film, the capillary flow of liquid cleaning agent to the film is finely adjustable by pressure panels engaging the wick plates with the upper edges of the storage chamber so as to provide for a wick plate low cross-section restriction adjacent the upper edges of the storage chamber which is finely adjustable or accurately controlling the cleaning agent supply to the soiled film.

The invention relates to an apparatus for cleaning soiled films which includes a transport mechanism for the film and a wet cleaning station with a storage chamber for containing liquid cleaning agent for wetting spaced wick plates between which the film passes while being wetted at both sides by the cleaning agent which is drawn into the wick plates from the storage chamber, the wick plates engaging the sides of the film with an adjustable force by means or pressure plates via an intermediate U-shaped band of cloth material.
Such a film cleaning apparatus is disclosed in DE-PS3623452. It facilitates film cleaning while consuming relatively small amounts or cleaning agents because the wick plates extend into the cleaning agent in the storage chamber and transfer the cleaning agent onto the film surface only on the basis or the capillary action of the fleece or felt of which the wick plates consist.
However, during use of this film cleaning apparatus, it became apparent that it is difficult to control the amount of cleaning liquid supplied to the film in such a manner that the film surface is wetted evenly to a minimal degree over an extended period of operation. For supplying the cleaning agent to the film, on one hand, wick plates are required which have good capillary action for transporting the cleaning agent but which, on the other hand, do not carry too much cleaning agent so that the cleaning agent dries off rapidly and evenly from the film surface upon leaving the cleaning station and before coming into contact with the redirecting guide roller. It has been tried so far to control the amount of cleaning fluid admitted to the cleaning area by testing the capillary action of the wick plates and selecting materials which supply the appropriate amount of cleaning agents to the film surface.
It is therefore the object of the present invention to provide a film cleaning apparatus which permits the use of wick plates with very high capillary action, that is, with the capability to transport a large amount of cleaning agent but which, at the same time, offers the possibility to adjust the amount of cleaning agent admitted to the surface of the film in such a way that the cleaning agent supplied by the wick plates to the film per time unit is reduced to the absolutely necessary amount and this amount can be maintained at a constant level.


An apparatus, method, and system to harvest and store electromagnetic energy is disclosed. The present invention uses, for example, conductive surfaces within the energy storage component itself as a means of electromagnetic energy collection. The surface may be an integral portion of the energy device, such as a charge collection surface within a battery or a capacitor that mainly provides the battery or a capacitor with a necessary function. In another embodiment of the invention a metallic or conductive surface is added to and specifically built into the energy device during manufacturing for the main purpose of collecting electromagnetic energy for the energy device but is otherwise not necessary for the energy storage component. Once the energy is collected, it can be rectified either via rectification components that were built directly into the energy storage component during its manufacture or connected external to the energy storage component but within the energy device. The so-designed energy device may represent a self-sustaining, autonomous electromagnetic energy harvesting—energy storage device.

This invention relates to an apparatus and/or a system or method of harvesting energy. In particular, the present invention collects electromagnetic energy that exists in the ambient environment or that is intentionally directed to an energy harvesting device and stores said energy for later use.
Electromagnetic energy exists in all sorts of forms. It is generally used to transmit information, but also exists, albeit typically small, as a source of energy which may be collected and stored.
Generally, systems that collect electromagnetic energy, such as antennas for example, are only designed to capture the information that is being transmitted through the electromagnetic medium and generally do not capture a substantial portion of the energy itself. Information-carrying signals, once received by the antenna, can then be amplified by the receiver and filtered to obtain the information. As such, the focus of such systems is on the information and the particular wavelength on which the information is transmitted, rather than the actual energy itself.
Presently, at the same time that the amount of energy electronic apparatus use is decreasing, the amount of electromagnetic energy being transmitted is increasing. Further, more and more electronics operate autonomously—either passively, by sensing or collecting information, or actively, by performing a function.

Energy device with integral collector surface for electromagnetic energy harvesting and method thereof


The electric device for producing successive positive and negative electric charges includes a thyristor-based electrical pulse generator for providing alternating positive and negative pulses with relatively small currents. The potential alternates between positive and negative charge current, and the small current is applied, in the form of sparks, to a body under treatment. A cup-shaped electrode is mounted in the distal end of a handle for application to the body. The treatment device is carried in a case for portability.

1. Field of the Invention
The present invention relates to treating bodily disorders and ailments, and particularly to an electric device for producing successive positive and negative electric charges for treating and fostering the healing of bodily disorders.
2. Description of the Related Art
Bio-electric stimulation therapy or electrotherapy is the use of electrical energy as a medical treatment. In medicine, the term electrotherapy can apply to a variety of treatments, including the use of such electrical devices as deep brain stimulators for neurological disease. The term has also been applied specifically to the use of electric current to speed wound healing. Additionally, the term "electrotherapy" or "electromagnetic therapy" has also been applied to a range of alternative medical devices and treatments. Most electrotherapy devices use at least a pair of electrodes attached to the body in order to pass a charge or current through the body. These devices require electrodes to be attached to the body, generally with some sort of conductive adhesive in the form of pads, etc., to be adhered to the body, which become unduly sticky, and can cause harm if not applied properly.
Thus, an electric device for producing successive, positive and negative electric charge pulses solving the aforementioned problems of stickiness, and harmful currents is desired.

Electric device for producing successive positive and negative electric charges


A pressure roller for a media processing device has enhanced temperature uniformity and resists temperature increases when subjected to elevated temperatures, enabling greater dimensional stability of the pressure roller in fluctuating temperatures. The pressure roller includes a hollow cylindrical member, an elastomeric layer, and an endbell on each end of the hollow cylindrical member. A chamber is defined by an inner wall of the hollow cylindrical member and the endbells in which a volume of fluid is contained to absorb heat from the hollow cylindrical member.

In general, inkjet printing machines or printers include at least one printhead that ejects drops or jets of liquid ink onto a recording or image forming surface. A phase-change inkjet printer employs phase change inks that are solid at ambient temperature, but transition to a liquid phase at an elevated temperature. The melted ink can then be ejected onto print media or an image receiving member by a printhead in response to firing signals received from a controller.
In a direct-to-media printer, the printheads eject ink drops directly onto print media, for example, paper sheets or a continuous media web. After ink drops are printed on the print media, the printer moves the print media through a nip formed between two rollers that apply pressure and, optionally, heat to the ink drops and print medium. One roller, typically referred to as a "spreader roller," contacts the printed side of the print media. The second roller, typically referred to as a "pressure roller," presses the media against the spreader roller to spread the ink drops and fix the ink to the print media.
Pressure rollers typically include a steel cylindrical core coated by an elastomeric layer. During long substantially continuous printing, the temperature of the pressure roller can become elevated due to contact with the heated spreader roller and the print media, which is also heated prior to spreading. Temperature differences along the axial length of the steel core can cause the pressure roller to expand in some locations along the axis of the core, particularly near the center. Non-uniform expansion of the roller alters the shape of the contact the pressure roller makes with the spreader roller, also known as the "nip profile." Changes in the nip profile can result in the print media wrinkling while traveling through the nip, particularly in continuous media printers. Wrinkling of the print media through the spreader can result in image defects in the printed product.
Temperature increases in the pressure roller caused by its use to help spread ink on the media also alters the properties of the elastomeric layer on the roller. For example, in some pressure rollers, increased heating can cause a reduction in the modulus of elasticity of the elastomeric layer. A decreased modulus of elasticity can further impact the nip profile, compounding the media wrinkle issues noted above. Therefore, improvements in the temperature resistance and uniformity of pressure rollers are desirable.

Pressure roller containing a volume of fluid


A method and apparatus for driving a plasma display panel in which discharge cells are formed by first, second, and third electrodes, has a frame divided into a plurality of subfields, each of which includes a reset period, an address period, and a sustain period. In the reset period, a voltage at the first electrode is modified from a first voltage to a second voltage, the first electrode is floated; and the voltage at the first electrode is gradually reduced to a third voltage.

1. Field of the Invention
The present invention relates to a plasma display, and more particularly, to a plasma display panel driver and a driving method thereof.
2. Description of the Related Art
Plasma display panels (PDPs) have recently been popularized from among flat panel displays because of their high brightness and light emission efficiency, and wider view angles.
A PDP is a flat display for showing characters or images using plasma generated by gas discharge. PDPs can include pixels numbering more than several million in a matrix format, in which the number of pixels are determined by the size of the PDP. A PDP structure will now be described.
Along with the general structure of the PDP, an electrode arrangement of the PDP will also be described.
The PDP includes glass substrates 1 and 6 facing each other with a predetermined gap therebetween. Scan electrodes and sustain electrodes in pairs are formed in parallel on the glass substrate, and the scan electrodes and the sustain electrodes are covered with a dielectric layer and a protection film. A plurality of address electrodes is formed on the glass substrate, and the address electrodes are covered with an insulator layer. Barrier ribs are formed on the insulator layer between the address electrodes, and phosphors are formed on the surface of the insulator layer and between the barrier ribs. The glass substrates are provided facing each other with discharge spaces between the glass substrates so that the scan electrodes and the sustain electrodes can cross the address electrodes. A discharge space between an address electrode and a crossing part of a pair of a scan electrode and a sustain electrode forms a discharge cell, which is schematically indicated.
The electrodes of the PDP have an (n×m) matrix structure in which a plurality of address electrodes are arranged in the vertical direction and a plurality of scan electrodes and sustain electrodes are arranged in pairs in the horizontal direction.
In general, a frame is divided into a plurality of subfields in the PDP, and gray scales are represented by combinations of the subfields. Each subfield has a reset period, an address period, and a sustain period. In the reset period, wall charges formed by a previous sustain discharge are erased, and wall charges are set up in order to perform a stable next address discharge. In the address period, cells which are turned on and cells which are not turned on are selected, and the wall charges are accumulated on the turned-on cells (addressed cells). In the sustain period, a sustain discharge for actually displaying images on the addressed cells is performed.
A conventional PDP driving waveform diagram, and a state of a wall voltage and an applied voltage caused by a PDP driving waveform is described as follows. The reset period will only be described in the PDP driving waveform.
The reset period includes an erase period, a rising ramp period, and a falling ramp period.
In the erase period, a voltage waveform which rises to a voltage of Ve from a reference voltage is applied to the sustain electrode while the scan electrode is maintained at the reference voltage after a sustain period of a previous subfield is finished, and accordingly, positive wall charges and negative wall charges respectively formed on the sustain electrode and the scan electrode are erased after the last sustain discharge of the previous subfield is finished.
In the rising ramp period, a ramp voltage which gradually rises to a voltage of Vset which is greater than a firing voltage from a voltage of Vs which is less than the firing voltage is applied to the scan electrode. While the ramp voltage rises, weak discharges are respectively generated to the address electrode and the sustain electrode X from the scan electrode Y. Negative wall charges are stored in the scan electrode and positive wall charges are stored in the sustain electrode by the weak discharges.
In the falling ramp period, a ramp voltage which gradually falls to a negative voltage of from the voltage of is applied to the scan electrode. While the ramp voltage falls, weak discharges are generated to the scan electrode from the sustain electrode and the address electrode by the wall voltage formed at the discharge cells. Part of the wall charges formed on the sustain electrode, the scan electrode, and the address electrodes are erased by the weak discharges thereby reaching a state suitable for addressing.
In general, when the wall voltage of Vw between the scan electrode and the sustain electrode at the last point of the rising ramp period is defined to be Vw0, the discharge is started when the difference between the voltage of Vw0 and an applied voltage Vin (the voltage difference between the scan electrode and the sustain electrode) exceeds the firing voltage of Vf.
No discharge is generated in the earlier stage 'a' of the falling ramp period since the voltage difference between the voltage of Vw0 and the applied voltage is less than the firing voltage Vf. Therefore, the conventional driving waveform problematically increases the reset time because of an unnecessary reset operation such as the initial period of 'a' in the falling ramp period.

Plasma display panel driving method and plasma display


The present invention makes it possible to improve the performance of a semiconductor device.

The present invention relates to a manufacturing method of a semiconductor device and can be used favorably for a manufacturing method of a semiconductor device including a solid-state image sensing device for example.
As a solid-state image sensing device, a solid-state image sensing device (CMOS image sensor) using a CMOS (Complementary Metal Oxide Semiconductor) has been developed. The CMOS image sensor is configured so as to include a plurality of pixels having photodiodes and transfer transistors.
In Japanese Unexamined Patent Application Publication No. 2005-142319 (Patent Literature 1), a technology of removing a metallic pollutant attaching to the bottom face of a trench is disclosed. According to the abstract, the temperature of a substrate is controlled to 200° C. to 600° C., excitation energy is given by plasma, and thus oxidation reaction is caused on the surface of a silicon film. As a result, a silicon oxide film is formed over the surface of the silicon film exposed in a trench. A metallic pollutant coheres at the interface between the silicon oxide film and the silicon film and comes to be metallic silicide. The silicon oxide film is removed by an HF system solution. In accordance with this, the metallic silicide is also removed.
In Japanese Unexamined Patent Application Publication No. 2008-60383 (Patent Literature 2), a technology that makes it possible to form a gate insulating film having a high reliability is disclosed. According to the abstract, after a groove is formed over the surface of a silicon substrate, the inner surface of the groove is cleaned to remove pollutants and successively a defective layer over the inner surface of the groove is removed by isotropic etching using a radical generated by ionizing a fluorine-contained gas and an oxygen gas at a substrate temperature of 200° C. or lower.
In Japanese Unexamined Patent Application Publication No. 2006-59842 (Patent Literature 3), a technology of inhibiting stress caused in a substrate by an element isolation (STI) section and mitigating the problem of joint leak current is disclosed. According to Example 3, a damaged layer formed inside a groove when the groove is formed in a silicon substrate by anisotropic dry etching is removed by isotropic etching.

Manufacturing method of semiconductor device

Abstract: After anisotropic etching is applied to an insulating film covering a gate electrode of a transfer transistor and a sidewall spacer is formed over the sidewall of the gate electrode, a damaged layer formed in the interior of a semiconductor substrate by the anisotropic etching is removed by oxidizing the surface of the semiconductor substrate, forming a sacrificial oxide film, and removing the sacrificial oxide film.