A compressor and heat pump combination has an active chamber and a passive chamber, each with its own hot plate and cold plate. The two chambers are joined along an edge by a membrane that largely transmits pressure, largely insulates against temperature transfer, and prevents passage of gases from one chamber to the other. The gas in the active chamber is alternately cooled and heated by exposure to the active cold and active hot plates, causing pressure changes in the active chamber that are transmitted to the passive chamber by the membrane. The pressure changes alternately cool the gas in the passive chamber below the temperature of the passive cold plate, and heat the gas in the passive chamber above the temperature of the passive hot plate. In alternately exposing the cooled gas in the passive chamber to the passive cold plate, and the heated gas in the passive chamber to the passive hot plate, heat is forced to flow from the passive cold plate to the passive hot plate. Other thermodynamic apparatus including stand alone compressors and heat pumps are described.

1. Field of the Invention
The present invention relates to thermodynamic cycle apparatus and methods, and more particularly to thermodynamic cycle apparatus including compressors and heat pumps and related methods.
2. Description of the Related Art
One type of engine is commonly known as a Stirling engine. The Stirling engine has a fixed mass of a gas inside its chamber, which remains in the chamber during operation of the engine.
At various points in the cycle of the Stirling engine, the fixed mass of gas is alternately heated and cooled, thereby changing its pressure. The pressure increases when the gas is heated, and the pressure decreases when the gas is cooled. The chamber of the engine is contiguous with a piston chamber, so that an increase in pressure drives the piston outward, and a decrease in pressure drives the piston inward. The moving portion of the piston is mechanically linked to a rotating shaft, which in turn drives a generator and produces electrical power; other uses and applications are also possible.
The heating and cooling functions are typically performed by a pair of hot and cold plates, located on opposite sides of the chamber. A displacer that can easily move back and forth inside the chamber forces the gas into contact with one plate while insulating it from the other. Air flows around the perimeter of the displacer, and movement of the displacer from one side to the other requires very little energy.
The hot plate is heated by a generally continuous source of heat, such as a flame, or a solar panel. The cold plate can be at room temperature, or cooled in a continuous manner, such as evaporatively or being located in or near a bath of ice.
An example of a Stirling engine is shown in FIGS. 13 and 14. The hot plate 136 and cold plate 137 are on opposite sides of a chamber 135. The sides adjacent to the hot and cold plates are thermally insulated, so that the heat flowing in and out of the chamber through the sides is minimized. The chamber 135 is filled with a fixed mass of fluid, which may be a gas such as air. A displacer 134 moves within the chamber 135, and forces the gas inside the chamber 135 into thermal contact with one of the plates, while insulating it from the other plate. Air flows around the displacer 134, which requires very little energy to move from one side to the other of the chamber 135.
FIG. 13 shows the Stirling engine in a "hot" position 130, with the displacer 134 held against the cold plate 137 by the displacer actuator 133, so that the gas in the chamber 135 is in thermal contact with the hot plate 136 and is insulated from the cold plate 137. Because there is a fixed amount of gas in the chamber, when the gas absorbs heat from the hot plate 136, it expands through the chamber outlet 138 and drives the piston 139 outward. As a result, the piston actuator 141 drives a crankshaft 132. The crankshaft 132, pivotably attached to the frame 142 by one or more bearings 143, rotates under the influence of the piston actuator 141, and turns generator 131. The generator 131 produces electricity, for use external to the engine 130. The engine 130 may have an optional flywheel 144 for stability.
Note that it takes very little energy to move the displacer 134 inside the chamber 135, so that the displacer actuator 133 can easily be driven by the rotating crankshaft 132 with very little loss. The displacer 134 itself is a lightweight thermal insulator, and it moves relatively freely inside the chamber of the Stirling engine 130. Its primary purpose is not to compress the gas in the chamber 135, but to force the gas into contact with one of the plates while insulating the gas from the other plate. There is room around the perimeter of the displacer 134 for gas to flow, so it requires very little energy to move the displacer 134 from one orientation to the other.
FIG. 14 shows the Stirling engine in the "cold" position 140, where the crankshaft has rotated 180 degrees from the view shown in FIG. 13. The displacer actuator 133 has moved the displacer 134 into contact with the hot plate 136, so that the gas is in thermal contact with the cold plate 137. The cold plate 137 absorbs some heat from the gas, so that the gas cools and, therefore, contracts. The reduction of pressure inside the chamber drives the piston 139 inward, causing the piston actuator 141 to further rotate the crankshaft 132.
For each rotation of the crankshaft 132, the engine passes continuously from the "hot" state to the "cold" state and back again.
Note that the piston actuator 141 and the displacer actuator 133 typically are out-of-phase, with a value between 0 degrees and 180 degrees.
Conversion of the Stirling engine of FIGS. 13 and 14 to a heat pump is straightforward, requiring replacement of the generator 131 with a motor, and optionally requiring adjustment of the phase between the piston actuator 141 and the displacer actuator 133, so that they are essentially opposite that as drawn in FIGS. 13 and 14. When used as a heat pump, the motor turns the crankshaft 132, driving the piston actuator 141 and, in turn, the piston 139. For heat pump operation, the chamber is forcibly expanded when the gas is in contact with the cold plate, and the chamber is forcibly compressed when the gas is in contact with the hot plate.
For one part of the heat pump cycle, the piston 139 is driven outward by the piston actuator, decreasing the pressure of the fixed amount of gas inside the chamber 135. The gas is therefore cooled, and is cooled below the temperature of the cold plate 137. The gas is then brought into thermal contact with the cold plate 137, and heat flows from the cold plate 137 into the gas, making the cold plate 137 even colder.
In the next part of the heat pump cycle, the piston is driven inward by the piston actuator 141, increasing the pressure and, therefore, the temperature of the gas. The temperature of the heated gas is greater than that of the hot plate 136. The gas is then brought into thermal contact with the hot plate 136, and heat flows from the gas into the hot plate 136, making the hot plate 136 even hotter.
These two parts of the cycle then repeat, thereby converting a mechanical energy supplied by the motor to a transfer of heat from a cold body to a hot body.
The Stirling engine has many advantages over other types of engines. For instance, there is a fixed amount of gas sealed inside the Stirling engine, which never leaves the engine. The heat source may be continuous, so that the amount of exhaust fumes is much less than for comparable internal or external combustion engines. Because the gas is sealed inside the chamber, environmentally risky materials may be used without risk of contaminating the surroundings. Also, a Stirling engine uses an external heat source, which could be a continuously-burning flame, solar energy, or a variety of others. Unlike an internal combustion engine, no explosions take place, so operation of a Stirling engine is typically very quiet.
There are drawbacks, though, to existing engines and heat pumps based on the Stirling engine of FIGS. 13 and 14. For instance, the gas-filled chamber is coupled to a mechanical piston. Mechanical pistons are inherently inefficient, in that they have some amount of frictional losses. In a piston, one solid object moves against another solid object while maintaining a seal between them, and motion of one solid against another invariably has a frictional loss associated with it.
Accordingly, there exists a need for engines and heat pumps, and generally for thermodynamic cycle apparatus, that overcome the inherent losses caused by friction.

Thermodynamic cycle apparatus and method


A thermal spraying powder includes granulated and sintered particles of an yttrium-aluminum double oxide obtained by granulating and sintering a raw powder containing yttrium and aluminum. The total volume of fine pores having a diameter of 6 μm or less in one gram of the granulated and sintered particles is 0.06 to 0.25 cm3. The thermal spraying powder reliably forms a thermal spray coating that is suitable for use where the thermal spray coating is subjected to a thermal shock in a corrosive atmosphere or an oxidative atmosphere and for use where the thermal spray coating is subjected to a thermal shock in a state where the thermal spray coating contacts a member that has reactivity to a base material.

The present invention relates to a thermal spraying powder containing granulated and sintered particles of an yttrium-aluminum double oxide.
When using a member formed of a material that has low corrosion resistance and oxidation resistance in a corrosive atmosphere or an oxidative atmosphere, a coating formed of a material that has a superior corrosion resistance and oxidation resistance such as an yttrium-aluminum double oxide is generally provided on the surface of the member. For example, Japanese Laid-Open Patent Publication No. 2002-80954 discloses a technique for forming a thermal spray coating of an yttrium-aluminum double oxide on the surface of a base material by plasma spraying granulated and sintered particles of an yttrium-aluminum double oxide.
To suppress corrosion and oxidation of the base material by ambient gas, the thermal spray coating desirably has a high density, or a low porosity. However, if the density is too high, when the thermal spray coating is subjected to a thermal shock, for example, when a heating process with plasma or a heater and subsequent cooling process are repeated, the thermal spray coating is likely to delaminate or detach from the base material. The delamination or detachment of the thermal spray coating occurs often due to the difference between the thermal expansion coefficient of the thermal spray coating and that of the base material made of a material different from the thermal spray coating. Meanwhile, if the density of the thermal spray coating is too low, the base material in the vicinity of the boundary surface between the base material and the thermal spray coating is corroded or oxidized, because the ambient gas reaches the base material through pores in the thermal spray coating. As a result, the thermal spray coating may delaminate or detach from the base material. Furthermore, when a member that has reactivity to the base material (for example, a member made of metal or an alloy) contacts the thermal spray coating, if the density of the thermal spray coating is too low, the member that contacts the thermal spray coating reacts with the base material through pores in the thermal spray coating. As a result, the thermal spray coating may delaminate or detach from the base material.
In this respect, in the technique disclosed in the above publication No. 2002-80954, consideration for the porosity of the thermal spray coating is inadequate. Therefore, it is difficult to obtain a thermal spray coating that is suitable for use where the thermal spray coating is subjected to a thermal shock in a corrosive atmosphere or an oxidative atmosphere and for use where the thermal spray coating is subjected to a thermal shock in a state where the thermal spray coating contacts a member that has reactivity to the base material.


An apparatus and method provides efficient parallel processing for use with a single-bit sampler that provides single-bit samples at a high sample rate. A serial-to-parallel converter converts the single-bit samples into parallel single-bit samples at a reduced sample rate. A digital quadrature mix performs a frequency shift to the parallel single-bit samples and simultaneously performs a real-to-complex conversion of the parallel single-bit samples from the serial-to-parallel converter to provide parallel I and Q output values at an intermediate frequency. The serial-to-parallel converter has shift register stages that provide a memory for use in functional realization of a boxcar filter and decimation-by-two in the digital quadrature mix. The digital quadrature mix utilizes logic to route and invert the parallel single-bit samples resulting in the parallel I and Q single-bit output values. Additional filter and decimate stages may be used to process the parallel I and Q single-bit output values.

This invention relates to communications systems, digital signal processing, and specifically to a method and apparatus for efficient parallel processing for use with high-speed single-bit sampling in a communications system.
Communications systems are utilizing digital signal processing to perform applications previously done with analog circuitry. Digital signal processing offers increased performance with reduced size, power consumption, and cost. Digital signal processing is used to perform digital modulation, demodulation, filtering, and other functions in communications system receivers and transmitters.
High-speed sampling and frequency shifting from an IF (intermediate frequency) are some of the more challenging aspects of a digital demodulator used in communications system equipment. The problem is made simpler if single-bit sampling can be used. Even when this is possible, filtering and moving the samples into the demodulator in real time is a formidable problem because of the very high speed sampling rates.
What is needed are more hardware efficient methods for performing quadrature mixing, filtering, decimating, and moving high-speed single-bit samples from an A-to-D converter or some similar digitizing device into the digital demodulator in real time.

Efficient method and apparatus for parallel processing for use with high-speed single-bit sampling


Systems and techniques for managing interaction between a network operator and entities managing resources and instances in a virtual radio access network. A radio access network resource manager comprises a database mapping cells to resources and instances associated with the cells, and one or more interfaces between the network operator and the entities managing resources and instances. The radio access network manager mediates commands and information received from the network manager and from the entities managing resources and instances, translating cell-level commands and information from the network manager to commands and information relating to associated resources and entities, and translating resource and instance-level information and requests from the entities managing resources and instances to cell-level information and requests to the network operator.

Traditional wireless communication systems, such as those operating under third generation partnership project (3GPP) standards and specifications, as well as 3GPP long term evolution (LTE), LTE-advanced (LTE-A), have frequently been focused on the use of dedicated physical and computational resources to serve users in a particular location, with a base station serving users in a more or less well defined area. Different base stations may cooperate with one another, particularly if they overlap one another's coverage area, but the focus has generally been on the placement of physical resources and the control of those resources.
In recent years, communication and computing technology has allowed for more and more applications directed to virtualization of resources—for example, virtual computing machines—"cloud" computing, or virtual—"cloud" storage, in which various hardware and software installations are. It is also possible to design or configure wireless communication resources so as to present "virtual" cells or other radio access network elements, in which one or more controlling elements allocates functions to available physical resources to perform desired functions and achieve a desired configuration.

Methods and apparatus for radio access network resource management


The portable collapsible awning provides a main collapsible frame structure for supporting a canopy, which is easily collapsible and portable, providing transportable protection from the elements. The main collapsible frame structure includes a plurality of vertical supports, which are each pivotally joined to one another by collapsible scissors-like crossbars. The vertical supports define a passageway for pedestrians, and are expandable and collapsible simultaneously in both the lateral and longitudinal directions. An auxiliary frame is further releasably attached at a proximal end to the main collapsible frame structure for supporting a walkway awning. The distal end of the auxiliary frame is adapted for overlying a portion of a roof of a vehicle, creating a covered walkway from the vehicle door to the user's destination without vertical supports or frame members intermediate the main canopy and the vehicle.

1. Field of the Invention
The present invention relates to portable sheltering structures similar to canopies, umbrellas, tents, etc., and particularly to a portable collapsible awning that includes a canopy and a walkway awning extending from the canopy, and further having an end adapted for resting on a vehicle roof to provide door-to-door protection when entering and exiting the vehicle.
2. Description of the Related Art
Covered walkways for protecting users from rain, snow and other inclement weather have been available in a wide variety of configurations for many years. Such walkways are typically in the form of a large umbrella or an awning that is fixed to a building or to the ground in a stationary manner. Although fixed awnings and umbrellas may be collapsed, they are not readily transportable.
Portable and collapsible covering systems have been utilized for a variety of purposes, and such systems typically include a plurality of support frame members joined together by cross bars, allowing the frame members to be collapsed and expanded in the longitudinal direction, similar in manner to an accordion. Such systems, however, are only collapsible in one direction and, thus, must be transported in a conveyance or vehicle that is at least as wide as the individual frame members. In order to make such a system easily transportable, the width of each frame member must be reduced, which does not allow the covering to serve a large group of people.
Further, such portable coverings are not adapted for use with a vehicle. If it is desired to provide protection from the vehicle's door to the user's destination, the frame must be positioned close to the door of the vehicle. The frame, however, would prevent the vehicle door from being fully opened. It would be desirable to provide a system allowing for the free opening of the vehicle door and providing a covered walkway from the door to the user's destination. Thus, a portable collapsible awning solving the aforementioned problems is desired.


An SAR ADC is operated by sampling an input voltage and redistributing a corresponding charge among the coupling capacitor and a plurality of binarily weighted capacitors of a CDAC array to produce a first voltage on a charge summing conductor. A successive approximation bit testing/conversion operation is performed at a first speed on a first group of bits, beginning with the MSB, to determine the bits of the first group with at least a first level of accuracy. A first error correction operation includes performing a bit testing/conversion operation on a last bit of the first group at a second speed which is lower than the first speed to determine the bits of the first group at least a second level of accuracy which is more accurate than the first level of accuracy. Both the voltage on the charge summing conductor and the bits of the group are incremented or decremented as necessary to elevate the level of accuracy of bits of the first group to at least the second level of accuracy.

The present invention relates generally to high speed, low-power SAR (successive approximation register) ADCs (analog-to-digital converters), and more particularly to an improved technique for operating an SAR ADC of generally conventional architecture to increase its conversion speed with little modification to its architecture or circuitry.
The basic conventional SAR ADC architecture is shown in FIG. 1, wherein a conventional CDAC (capacitive digital-to-analog converter) capacitor array 2 typically is connected to a charge summing conductor 7A which is connected to the one of the inputs of a comparator 3. The other input of comparator 3 is connected to a charge summing conductor 7B of a conventional xe2x80x9cdummyxe2x80x9d CDAC capacitor array 4. The output 4 of comparator 3 is connected to an input of a conventional SAR control logic circuit 5, which produces a plurality of digital output signals Dout on a digital bus 6 that is coupled to transistor switches in CDAC capacitor array 2. The transistor switches selectively couple the various capacitors in CDAC capacitor array 2 to a reference voltage conductor 9 conducting a reference voltage VREF+ or to a reference voltage conductor 16 conducting a reference voltage VREFxe2x88x92, which typically is ground.
FIG. 2 shows a typical external reference voltage amplifier 8 which produces VREF+ on conductor 9 within SAR ADC 1 of FIG. 1. There is a substantial bonding wire inductance 10A inside of an integrated circuit chip (indicated by the dashed line) on which the conventional SAR ADC 1 of FIG. 1 is formed. Inductance 10A is coupled between external conductor 9A and an internal conductor 9B conducting the internal value of VREF+which is applied by the transistor switches to the various capacitors of CDAC capacitor array 2 in accordance with digital signals Dout produced by SAR control logic 5 during the successive approximation testing/conversion operation. Reference numeral 13A in FIG. 2 represents series resistance of the transistor switch driving the CDAC, and conductor 9 and is shown as being lumped between node 9 and the output of an internal buffer 11.
Reference numeral 12 in FIG. 2 designates the widely variable capacitance CCDAC of the portion of CDAC capacitor array 2 which effectively xe2x80x9cloadsxe2x80x9d reference voltage amplifier 8 during the successive approximation process. If internal buffer 11 is omitted, then waveform V9A in FIG. 2 indicates xe2x80x9cringingxe2x80x9d of voltage that would be caused by bonding wire inductance 10A on conductor 9B when the CDAC array capacitance 12 varies suddenly due to switching that occurs in response to the digital signals 6 to establish the successive mid-range voltages needed for testing/conversion of each bit of the output word Dout.
Therefore, in the prior art it is usually necessary to provide above mentioned internal buffer circuit 11 to isolate the inductance 10A from the variable CDAC array capacitance 12 to avoid the kind of ringing indicated by waveform V9A. For high resolution ADCs, the CDAC capacitance has to be large, to achieve good noise and matching performance. Therefore, the switching load on the reference buffer is high for high resolution devices. Also, the speed at which the conversion is done puts a constraint on the settling time of the buffer. All these factors together increase the power consumption of the buffer 11. Undesirably, such an internal buffer 11 occupies a substantial amount of chip area and consumes a substantial amount of power.
One of the main drawbacks of high speed SAR ADCs that utilize internal CDACs (capacitive digital-to-analog converters) is that the external reference voltage amplifier driving the CDAC is subjected to the above mentioned widely changing capacitive load, depending on the value of the digital output word being generated to represent the analog input signal Vin. Consequently, if N is large, e.g., 16 bits or more, a large amount of time has to be allowed for the reference voltage amplifier 8 to settle to an accuracy corresponding to the N bit output word being produced.
FIG. 3 shows more details of CDAC capacitor array 2, wherein reference numeral 14 designates a plurality of binarily weighted CDAC array capacitors each having an upper terminal connected to charge summing conductor 7A and a lower terminal selectively coupled by a transistor switch circuit 15 to either VREF+ or VREFxe2x88x92 in response to the digital control signals 6 during the successive approximation bit testing/conversion procedure.
In the conventional SAR ADC 1 of FIG. 1, an analog input Vin=Vinxc2x1Vinxe2x88x92 is applied between an input conductor 17A of CDAC capacitor array 2 and an input conductor 17B of dummy CDAC capacitor array 4. Vin+ and Vinxe2x88x92 are sampled by means of input coupling capacitors in main CDAC array 2 and dummy CDAC array 4 during a sampling phase. At the end of the sampling phase, a conventional binary search algorithm is performed in response to the output of comparator 3 to establish a binary mid-range value for the output bit currently being tested/converted. Comparator 3 in effect compares the sampled analog input voltage to the present value of the binary mid-range value established in main CDAC array 2, and assigns a binary value of xe2x80x9c1xe2x80x9d to the bit presently being tested if the sampled analog input voltage exceeds the binary mid-range value, and otherwise assigns a binary xe2x80x9c0xe2x80x9d to the bit being tested/converted. As the conventional conversion process proceeds, it includes progressively testing and assigning xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d values to the output bits, one at a time, beginning with the MSB (most significant bit), to produce the output word Dout.
Each bit of the digital output word Dout, beginning with the MSB (most significant bit), is tested sequentially by comparator 3 to determine if that bit should be a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d. For an N bit accuracy of the ADC, the comparator should be able to resolve the difference of (Vref/2N) at its inputs. If N is increased, the comparator either (1) requires more time to settle, or (2) requires more bandwidth and consequently consumes more power if no more time is allowed for settling in order to resolve the more accurate bit testing decisions necessitated by the increasing of N.
In a typical SAR ADC, the analog to digital conversion proceeds one bit at a time until all of the bits of the digital output word are resolved, i.e., converted. All of the bits are processed at the full accuracy level required for an N-bit digital output word, so an equal amount of time is required to resolve each of the N bits of the output word Dout. Therefore, the amount of time required for a typical analog-to-digital conversion by an SAR ADC is:
Tcycle=Tsample+N*Tclock,
where Tclock is the time required for resolving any one of the N bits of the output word.
The design of high-speed, high-resolution SAR ADCs is substantially limited by the speed of the comparator 3, by the bandwidth/power/settling time of the external reference voltage amplifier 8, and the internal settling time of the charge summing conductor 7A of the CDAC array 2. The higher the resolution of the SAR ADC, the more stringent the limitations on the amount of noise that can be present in the comparator, and the higher the amount of CDAC switching capacitance that the reference voltage amplifier must drive as it settles. The higher the desired speed of analog-to-digital conversion, the higher the speed, bandwidth and power consumption of comparator 3 must be, and the less time is available during which the voltage reference amplifier 8 must settle to the required accuracy level during the successive approximation testing/conversion of each bit. The amount of time required for the internal CDAC charge summing conductor 7A to settle to the required accuracy level includes two components, including (1) an RC time constant which determines the amount of time required for charge redistribution along the charge summing conductor 7A, and (2) the amount of time required for settling of the internal reference voltage node 9B connected to the transistor switches 15 (FIG. 3) associated with the various binarily weighted capacitors of the CDAC.
To summarize, the main bottlenecks for achieving high-speed, low-power operation of an SAR ADC are the settling time of the reference voltage amplifier 8, the CDAC charge redistribution time for the charge summing conductor 7A, and the delay of the comparator 3. The output of external reference voltage amplifier 8 is coupled through bonding wire inductance to a switched CDAC load, so every time the CDAC capacitor array is switched for the next bit decision, there is a current surge that must be supplied by a reference voltage amplifier output. This causes RLC xe2x80x9cringingxe2x80x9d of the reference voltage, which must be allowed to settle to an N-bit accuracy level, which for N equal to 16, is approximately 30 microvolts, and is approximately 0.5 millivolts at the 12 bit accuracy level. To avoid this ringing, the internal reference buffer 11 ordinarily is provided on the SAR ADC integrated circuit chip 1 to isolate the bonding wire inductance 10A and the CDAC capacitor array 12. Unfortunately, the internal reference buffer 11 requires a large amount of supply current in order to drive the large switched capacitive CDAC array loads 12 as the successive bits are tested/converted.
Apart from the settling of the reference voltage amplifier, the CDAC also requires additional time for charge redistribution before each successive bit of the output word can be tested. The charge redistribution time is an exponential settling time, and requires, for example, approximately 12 time constants to settle to the 16-bit accuracy level, 9 time constants to settle to the 12 bit accuracy level, and approximately 6.3 time constants to settle to the 8 bit accuracy level.
The comparator delay is the time required for the comparator to resolve the difference between the voltage applied between its inputs. This delay is inversely proportional to the minimum voltage difference that needs to be resolved, which in turn is proportional to the resolution of the ADC.
Referring to FIG. 4A, an example is shown of the voltage difference V7Axe2x88x92V7B applied between the inputs of comparator 3 wherein a large value designated xe2x80x9cOVERDRIVE Axe2x80x9d is applied and then a very small value designated xe2x80x9cOVERDRIVE Bxe2x80x9d is applied. FIG. 4B shows the internal structure of comparator 3, which includes a differential input stage 3A which drives the differential output stage 3B. Those skilled in the art will recognize that for the very low value of OVERDRIVE B, which in some cases might be only approximately Vref/65536 at the 16-bit accuracy level, the input stage 3A will drive output stage 3B much more slowly than if the much larger OVERDRIVE B is applied between the inputs of input stage 3A. Therefore, much more time must be allowed for comparator decisions at a high level of accuracy, e.g., at the 16-bit accuracy level, than is the case for comparator decisions at a lower accuracy level, e.g. at the 12 bit accuracy level. For example, for accuracy at the 16-bit level, the overdrive of the comparator input stage 3A for the xe2x80x9ccritical decisionxe2x80x9d is approximately 30 microvolts. At the 12 bit accuracy level, the comparator input stage overdrive for the critical decision is approximately 0.5 millivolts.
U.S. Pat. No. 4,620,179 (the ""179 patent) by Cooper et al., assigned to Harris Corp., discloses a successive approximation analog-to-digital conversion technique that attempts to solve the above shortcomings of the prior art by providing an N bit SAR ADC wherein the first X bits are approximated to within less than the desired accuracy for N bits successive approximation and the remaining N-X bits are approximated to within at least the desired accuracy for N bit successive approximation. The ""179 patent teaches that the error thereby introduced can be removed by performing an error correction operation. The ""179 patent also teaches that there should be only one error correction cycle because each additional error correction operation cycle would require a significant increase in conversion time and yet afford only nominal improvement in conversion accuracy. Column 6, line 13 et seq. describe the technique for determining how many of bits of the N bit converter should be converted at full scale accuracy after which the single error correction cycle should be performed.
However, since there are three possible results of the error correction operation of the ""179 patent, namely, incrementing the least significant bit, decrementing it, or performing no operation, it is not practical to perform the error correction operation in a single cycle. The ""179 patent fails to recognize that in most cases, multiple error correction operation should be performed, and also fails to recognize that every error correction operation need not be performed at the final accuracy of the analog-to-digital converter, and instead teaches that multiple error correction operations are not advisable. Finally, the single error correction cycle described in the ""179 patent requires too much time to perform and substantially reduces the advantage of the error correction process.
Thus, there is an unmet need for an improved way of operating an SAR ADC to provide substantially decreased analog-to-digital conversion time and reduced power consumption without substantially increasing complexity of the circuitry/architecture of the SAR ADC.
Accordingly, it is an object of the invention to provide an improved way of operating an SAR ADC so as to substantially decrease its analog-to-digital conversion time and/or substantially reduce its power consumption, without substantially increasing the complexity of the circuitry and without compromising on the accuracy of the SAR ADC.
It is another object of the invention to provide a technique for operating an SAR ADC which reduces the amount of time that must be allowed for a reference voltage amplifier to settle, which reduces the amount of time that must be allowed for internal CDAC charge redistribution, and which reduces the amount of time that must be allowed for comparator delay.
It is another object of the invention to provide a reduction of the analog-to-digital conversion time of an SAR ADC by at least a factor of 2 by changing its bit testing scheme, and without substantially changing the circuitry or architecture of the SAR.
It is another object of the invention to reduce the power dissipation of an SAR ADC primarily by changing its bit testing scheme, without reducing the analog-to-digital conversion time and without substantially changing the circuitry/architecture of the SAR ADC.
Briefly described, and in accordance with one embodiment, the present invention provides an SAR ADC which is operated by sampling an input voltage and redistributing a corresponding charge among a plurality of binarily weighted capacitors of a CDAC array to produce a representative voltage on a charge summing conductor. A successive approximation bit testing/conversion operation is performed at a first speed on a first group of bits, beginning with the MSB, to determine the bits of the first group with at least a first level of accuracy. A first error correction operation includes two cycles: performing a bit testing/conversion operation on a last bit of the first group and an incrementing or decrementing operation. Both are performed at a second speed which is lower than the first speed to determine the bits of the first group to at least a second level of accuracy which is more accurate than the first level of accuracy. Both the voltage on the charge summing conductor and the bits of the group are incremented or decremented as necessary to elevate the level of accuracy of the bits of the first group to at least the second level of accuracy. A similar successive approximation bit testing/conversion operation is performed at a lower second speed on a second group of bits to determine the bits of the second group with at least the second level of accuracy.

Error correction architecture to increase speed and relax current drive requirements of SAR ADC


The grid member is formed of sheet metal and has an inverted T-shape with a bulb at the top, a double thickness central web and oppositely disposed flanges at the bottom. To achieve controlled expansion, an extended angular lance is cut at the top of the bulb. Further, staggered cutouts are placed in the two thicknesses which make up the web. By staggering the cutout areas of adjacent web layers, the overall web strength is maintained. These web cutouts and the lance at the top of the bulb cooperate upon thermal expansion, causing the bottom flanges to buckle down, and the web and bulb to separate laterally and fold. The folded web configuration directed by the staggered cutout pattern will maintain longitudinal rigidity.

Field of the Invention
This invention relates generally to a fire-resistant, ceiling board supporting grid system, and more particularly, to runner members capable of absorbing compressive elongation without substantial buckling as might occur during abnormal elevated temperatures, thereby preserving the integrity of the ceiling as a fire barrier under such conditions.
One of the critical problems encountered in these supporting grid structures is to maintain integrity under abnormally elevated temperatures, such as during a fire. Under these high temperature conditions, metallic grid members, which generally are fixed at their end points, expand and buckle whereby the supported ceiling panels are displaced and drop through the openings formed by the buckled grid members. As a result, the effectiveness of the suspended ceiling as a fire barrier is destroyed and the support structure is exposed to fire.
Prior art has considered structures for absorbing thermally induced compression in a supporting grid member. Most of the early designs used multiple expansion joints in a main runner. A relatively close placement of expansion joints will perform best in fire. This is because, when subjected to fire, the intersecting cross tees will remain close to their original spacings and thereby continue to support the panels. The early systems, however, were severely weakened at their expansion relief locations and could not be installed efficiently without excessive handling damage. Further, they were weak in cross bending and could not maintain beam alignment when exposed to fire.
To resolve this problem, some of the commercial systems reverted to main beams with only one relief point located near the end of the runner (reference U.S. Pat. No. 3,388,519). This however, reduced the handling problem at the expense of optimum fire performance.
Over the years there have been step-by-step improvements in systems that use multiple relief points in each main runner. However, the above problems, to a lesser degree, remain valid even in the improved systems. U.S. Pat. Nos. 3,778,947, 3,965,631 and 4,606,166 show products that handle marginally well when the web is kept vertical. The crushed bulb of these designs, however, limits handleability. This is especially true when a beam is handled on its side. U.S. Pat. Nos. 4,016,701 and 4,128,978 show products with metal removed from the top of the bead. This is the area of maximum bending stress, and the removal of metal here will significantly reduce load carrying capacity.


A method and apparatus for imparting a decorative strip onto the sidewall of a cured tire. The tire is sealed between a pair of chucks and inflated. The sidewall portion of the tire to be decorated is maintained in a flat horizontal posture by the chucks and the inflation pressure. The tire is then rotated while a gun, having a nib is contact with the tire sidewall, dispenses a paint directly onto the tire. A heating element for curing or partially curing the paint is maintained in juxtaposition to the sidewall for heating the paint strip as it passes thereunder.

The provision of white or colored bands circumferentially about the sides of a pneumatic tire is well known. Such "white sidewall" tires are generally accepted as the mark of a premium tire and are often required to compliment the body features and styling of the car on which the tires are used.
There are various known methods for generating a "white wall" band on a tire. The basic prior art teaches the implementation of extruded inlays placed in the tire carcass during construction and later buffed to obtain a uniform exposure of the decorative sidewall band after the curing operation. Further, attempts at spraying, painting, or otherwise depositing such decorative strips have been known, but the prior art typically involves either (a) wrapping of a specially compounded white rubber onto an unvulcanized tire carcass during assembly of the carcass, or (b) masking and air spraying of paint onto a cured tire, or (c) pouring of paint into a groove purposefully imparted into the tire sidewall for purposes of containing such paint, or (d) rotating a paint dispensing head around a stationary tire.
Prior to the invention herein, it has been most desirable to provide for the decoration of a tire sidewall without (a) the cost and complexity inherent in the extrusion of specially compounded rubber inlays, (b) the time and cost associated with the masking and mask cleaning in spraying operations, (c) the need for provision of sidewall groves to retain paint therein, (d) rotation of the dispensing device itself about a stationary tire, and (e) waste resulting from over spraying.

Method and apparatus for striping a tire sidewall


In general, techniques are described for providing user nomadicity in wireline broadband networks. A network device positioned in a wireline broadband network comprising a processor and an interface may be configured to perform the techniques. The processor may be configured to execute a first virtual customer premises equipment to provide, to a first subscriber, access to the wireline broadband network from a first subscription point in accordance with a first subscription. The processor may also be configured to provide, to a second subscriber, access to the wireline broadband network from the first subscription point in accordance with a second subscription. The interface may be configured to forward, in accordance with the first subscription, traffic received from the first subscription point and associated with the first subscriber, and forward, in accordance with the second subscription, traffic received from the first subscription point and associated with the second subscriber.

A wireline broadband network is a network by which network connectivity is provided to the premises of a subscriber by a physical communication medium, such as a coaxial cable, an optical fiber, or a copper wire. A network service provider that operates the wireline broadband network may deploy customer premises equipment (CPE) that terminates the physical access medium and controls access to the wireline broadband network. In the context of wireline broadband networks, CPEs are often referred to as residential routers and may include cable modems, optical network terminals, digital subscriber line (DSL) modems, asynchronous (ADSL) modems, set-top-boxes (STBs), or combination router and modems. The CPE may generally act as a router capable of providing additional functionality, such as dynamic host configuration protocol (DHCP) server functionality, by which to control access to the wireline broadband network for the particular subscriber to which the CPE is deployed.

Providing user subscription nomadicity in wireline broadband networks


The present memory includes a plurality of transistors laid out in a number of rows and columns. First and second series-connected transistors are included in a first column, and are connected between first and second bit lines and are respectively associated with first and second word lines. A region between the series-connected first and second transistors is connected to a first bit line. Third and fourth series-connected transistors are included in a second column, and are connected between the second bit line and a third bit line and are respectively associated with third and fourth word lines. A region between the series-connected third and fourth transistors is connected to a second bit line. The first, second, third and fourth transistors are respective parts of first, second, third and fourth rows of transistors.

1. Technical Field
This invention relates generally to semiconductor memory arrays, and more particularly, to such an array incorporating flash memory cells.
2. Background Art
One type of programmable memory cell is commonly referred to as the flash memory cell. The structure of one type of flash memory cell includes a source and a drain formed in a silicon substrate. The structure of another type of flash memory cell includes a source and a drain formed in a well that is formed in a silicon substrate. The flash memory cell includes a stacked gate structure formed on the silicon substrate. The region of the silicon substrate beneath the stacked gate structure is known as the channel region of the flash memory cell.
The stacked gate structure of a flash memory cell includes a pair of polysilicon structures separated by oxide layers. One of the polysilicon structures functions as a floating gate and the other polysilicon structure functions as a control gate for the flash memory cell. The oxide layer that separates the floating gate from the silicon substrate is commonly referred to as a tunnel oxide layer.
Programming operations on the flash memory cell involve application of a relatively large constant voltage to the drain of the flash memory cell while an even larger voltage is applied to the control gate. During such programming operation, the source of the flash memory cell is maintained at a ground level or a zero voltage level in relation to the voltages applied to the control gate and drain.
Such a relatively high voltage potential applied between the drain and source causes electrons to flow through the channel region from the source to the drain. The electrons flowing between the source and drain can obtain relatively high kinetic energy levels near the drain. In addition, the high constant voltage applied to the control gate raises the voltage potential of the floating gate to a high level at the start of the programming operation. Such a high voltage potential on the floating gate usually attracts the electrons flowing through the channel region. Under these conditions, electrons in the channel region having sufficiently high kinetic energy migrate through the tunnel oxide layer and onto the floating gate. This phenomenon is commonly referred to as hot carrier programming or hot carrier injection. A successful programming operation involves the injection of sufficient numbers of electrons onto the floating gate to achieve the desired threshold voltage for the flash memory cell. The threshold voltage is the voltage that must be applied to the control gate of the flash memory cell to cause conduction through the channel region during a read operation on the flash memory cell. The time involved in a programming operation depends upon the rate at which electrons are injected onto the floating gate.
The microelectronic flash or block-erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells that can be programmed and read. The size of each cell and thereby the memory are made small by omitting transistors known as select transistors that would enable the cells to be erased independently. As a result, all of the cells must be erased together as a block.
A flash memory device of this type includes individual metal-oxide-semiconductor (MOS) field effect transistor (FET) memory cells. Each of the FETs includes a source, a drain, a floating gate, and a control gate to which various voltages are applied to program the cell with a binary 1 or 0, to read the cells, or to erase all of the cells as a block.
The cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective word line and the drains of the cells in column being connected to a respective bit line. The sources of the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying programming voltage as follows: a voltage, typically in the range of 9-10 volts to the control gate, a voltage of approximately 5 volts to the drain and grounding the source. As disscussed above, these voltages cause electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein that increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
A cell is read by applying a voltage of about 5 volts to the control gate, applying about 1 volt to the bit line to which the drain is connected, grounding the source, and sensing the bit line current. If the cell is programmed and the threshold voltages is relatively high (4 volts), the bit line current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 volts), control gate voltage will enhance the channel, and the bit line current will be relatively high.
A cell can be erased several ways. In one arrangement, applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float erases the cell. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin oxide layer to the source. Applying a negative voltage on the order of xe2x88x9210 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase a cell. Another method of erasing a cell is by applying 5 volts to the P-well and xe2x88x9210 volts to the control gate while allowing the source and drain to float.
A problem with conventional flash EEPROM cells is that because of manufacturing tolerances, some cells become over-erased before other cells become sufficiently erased. The floating gates of the over-erased cells are either completely or partially depleted of electrons and having a very low negative charge or become positively charged. The over-erased cells can function as depletion mode transistors that cannot be turned off by normal operating voltages applied to their control gates and introduce leakage current to the bit line during subsequent programming and read operations. The slightly overerased cells can introduce varying amounts of leakage current to the bit line depending on the extent of overerasure.
More specifically, during program and read operations only one word line is held high at a time, while the other word lines are grounded. However, because a positive voltage is applied to the drains of all the cells on the bit line and if the threshold voltage of an unselected cell is very low, zero or negative, a leakage current will flow through the source, channel and drain of the cell.
The undesirable effect of leakage current is illustrated in FIG. 1, which is a simplified electrical schematic diagram of a column 100 of flash EEPROM cells 102, 104, 106, 108. The sources of the column 100 of transistors are all connected to a source supply voltage Vs. A programming or read voltage Vcg, is applied to be control gate of the transistor 104, which turns it on. A current I2 flows through the transistor 104 from ground through the source, channel (not shown) and drain. Ideally, the bit line current Ibl is equal to I2. However, if one or more of the unselected transistors, for example, transistors 102, 106, 108 as illustrated in FIG. 1, are overerased or slightly overerased, their threshold voltages will be very low, zero or even negative, and background leakage currents I1, I3, I4 could flow through the transistors 102, 106 and 108 respectively. The bit line current Ibl would then be equal to the sum of I2 and the background leakage currents I1, I3, I4. In a typical flash EEPROM, the drains of a large number of memory transistor cells, for example 512 transistors cells are connected to each bit line. If a substantial number of cells on the bit line are drawing background leakage current, the total leakage current on the bit line can exceed the cell read current. This makes it impossible to read the state of any cell on the bit line and therefore renders the memory inoperative.
Therefore, what is needed is a memory array wherein leakage cure is reduced.
The present invention is a memory array including a plurality of word lines and a plurality of bit lines. A first transistor is associated with a first word line and is connected in series with a second transistor associated with a second word line. The series-connected first and second transistors are connected between first and second bit lines. A region between the series-connected first and second transistors is connected to the first bit line. A third transistor is associated with third word line and is connected in series with a fourth transistor associated with a fourth word line. The series-connected third and fourth transistors are connected between the second bit line and a third bit line, a region between the series-connected third and fourth transistors being connected to the second bit line. The first, second, third and fourth transistors are respective parts of first, second, third and fourth rows of transistors, while the first and second transistors are part of a first column of transistors, while the third and fourth transistors are part of a second column of transistors.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there are shown and described embodiments of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.


An improved stud and alignment tool which may be pivotally engaged to forcibly slide the draw bar of a hitch assembly onto the stud of an implement frame includes a stud having an elongate body and a spherical tip member attached at a first end thereof. The alignment tool has a similar elongate body and has, at a first end thereof, a cavity extending longitudinally through a portion of the tool body. The cavity is shaped so as to receive the spherical tip member of the stud, thereby releasably and pivotally coupling the alignment tool with the stud. A method for aligning a stud with a hitch assembly draw bar includes the steps of pivotally and slidably engaging the alignment tool with the draw bar, pivotally engaging the alignment tool with the stud, and pivoting the alignment tool into axial alignment with the stud while slidably forcing the draw bar off the alignment tool and about the stud.

Most agricultural equipment, particularly, tractors, are fitted with a standard "three point" hitch which attaches to the tractor near the rear axel. A three point hitch comprises two bars, referred to as draw bars, and a third adjustable bar which project outward from the rear of the tractor, are movably mounted, and are spaced apart so as to define a triangular shape. Each draw bar has, at one end, an aperture in which a self aligning ball sleeve is pivotally mounted. A conventional ball sleeve has a generally ring like shape with a curved outer surface. The ball sleeve is mounted within the aperture at the end of the draw bar. This configuration allows the axis of the ball sleeve aperture to, within limitations, pivot with two degrees of freedom or any combination thereof.
The vehicle or implement to be towed, typically a grader or other piece of agricultural equipment, usually contains a standard triangular frame having two pins or studs attached at right angles to the base corners of the frame. The apex of the frame contains a set of holes into which a pin is inserted. FIG. 1 illustrates such a prior art stud 6 secured to an implement frame 8. Stud 6, which is cylindrically shaped, has a bevelled tip 6A at one end and a threaded section 6B over approximately half its length. A circular aperture 6C extends through stud 6 near end 6A for receiving a standard locking pin. Stud 6 is preferably formed of metal and is mechanically coupled to frame 8 in a conventional matter by nuts 12 and 14 and washer 16.
A tractor is typically hitched to a piece of equipment as follows. A draw bar (not shown) and stud 6 are positioned adjacent one another so as to align bevel tip 6A with the ball sleeve of the draw bar. Stud 6 is inserted into the ball sleeve and a locking pin (not shown) is inserted into pin hole 6C to securely fasten frame 8 to the draw bar. These steps are repeated until each stud of frame 8 is aligned and secured to its respective drawbar.
The task of manually aligning the studs with the ball sleeves of the draw bars is time consuming and often difficult. This difficulty is caused by the inability to accurately position the studs within even close proximity of the draw bars. Further, once the stud and draw bar are positioned adjacent one another the rigidity of the draw bar and the frame make it difficult to accurately align the ball sleeve with the axis of the stud, despite the broad angles at which the ball sleeve may be pivoted. Further, alignment of one of the two studs with its respective draw bar may misalign the other stud, particularly if it is not secured to its respective draw bars.
From the above discussion it may be appreciated that there exists a need for an apparatus and method of quickly and efficiently aligning the studs of an implement frame with the draw bars of a hitch assembly.
Accordingly, it is an object of the present invention to provide an improved stud which is more easily aligned with the draw bars of a hitch assembly than prior art studs.
A further object of the present invention is to provide a tool for aligning a stud with the draw bars of a hitch assembly.
Another object of the present invention is to provide an improved stud having a ball shaped tip which may be engaged by an alignment tool from a variety of off axis angles to align the stud with a draw bar of a hitch assembly.
A further object of the present invention is to provide an alignment tool having an internal socket at either or both ends thereof for receiving a stud having a ball shaped tip to facilitate aligning of the stud with the ball sleeve of a hitch assembly draw bar.
Another object of the present invention to provide an alignment assembly for fast and accurately aligning the studs of an implement frame with the drawbars of a hitch assembly.
Still a further object of the present invention is to provide method of aligning a stud with the draw bar of a hitch assembly which is faster and more efficient than prior art methods.
An even further object of the present invention is to provide an improved method of aligning a stud with a hitch assembly draw bar by pivotally engaging the stud with an alignment tool and slidably forcing the drawbar over the alignment tool and onto the stud.

Ball-tip stud and alignment tool and method of use


An expandable drawing surface is described. In various embodiments, a drawing surface manager is configured to cause a size of a drawing surface to expand dynamically to provide a user with a truly infinite drawing surface such that the user is not limited for space in any direction. To do so, the drawing surface manager creates and displays new pages for the drawing surface as the user scrolls in any direction. The new pages are displayed proximate existing pages such that the user is presented with a continuous drawing surface on which the user can work seamlessly. In one or more embodiments, a memory manager is configured to provide efficient memory techniques such that, at any point of time, only data associated with visible pages of the drawing surface is loaded onto a memory.

Conventional drawing applications allow the user to draw on a drawing surface of a finite size. Thus, users are often restricted by a limited amount of screen area to work with, especially when using mobile devices and tablet devices which have small display screens. Some conventional drawing applications for mobile devices may provide a drawing surface larger than the screen area defined by the display screen, but these drawing surfaces are still finite and limited on all sides.


An apparatus and method for burning in a computer having a parallel port, includes a diagnostic program, stored in an internal memory of the computer, for running diagnostic tests on at least one component of the computer. The apparatus also includes a power cycling circuit, coupled to the parallel port of the computer, for receiving a power-off signal from the computer, for turning power off to the computer in response to the power-off signal and for automatically turning power back on to the computer after a specified period of time has elapsed.

1. Field of the Invention
The present invention relates in general to burn-in processes for computers. More particularly, the present invention relates to a bum-in process for computers whereby power is cycled to the computer.
2. Description of Related Technology
The term "burn-in" is a common and well-known term in the electronics industry which refers to a testing method performed on electrical and electronic components, subassemblies and complete systems thereof. The burn-in process detects early failures, and allows manufacturers to replace or repair units which have failed under constant exposure to predetermined environmental or operational stresses, thereby ensuring the reliability of the circuits and systems once they have been placed in use with the customers.
The process of power cycling electronic components and circuits during the burn-in phase is well-known in the industry. However, in the computer manufacturing industry, there has been no method or apparatus which power cycles the entire computer during the burn-in phase while diagnostically testing various components, systems and/or interfaces within the computer between successive power-off cycles. Such power cycling can detect many types of early failures associated with the power-up and power-down of the computers. Such failures include, but are not limited to, for example, the failure of the basic input/output system (BIOS) to reset during the power-up phase of the computer, which can result in, for example, no video signal being sent to the video monitor by the computer. Other failures include the hard drive not booting upon power-up of the computer, the floppy drive not booting upon power-up of the computer, and an incorrect memory quantity reporting after a power-on self-test (POST) of the computer. All of these failures relate to the BIOS resetting to default values or the BIOS code being corrupted.
The BIOS code is a program stored in either a flash ROM or EEPROM of a computer motherboard or its peripherals, such as video adapters, hard drives, zip drives, cd-roms, etc. BIOS is a program which configures the computer system or peripherals to accept specified inputs and outputs from and to other integrated devices (peripheral devices). Upon initial power-up of the computer, it is the BIOS which provides system parameters, e.g., configuration parameters of the hard disk, etc., and allows the computer to "boot-up" a particular operating system, such as Windows 95.RTM.. Occasionally, the BIOS code is corrupted upon power-up of the computer such that the system parameter settings reset to default values which are incorrect for a particular computer configuration. When this occurs, the computer will not operate properly because the subsystems of the computer are unable to communicate properly with each other and to peripheral devices connected to the computer. This defect may be discovered during power cycling of the computer. Other defects which may be detected by power cycling the computer are a defective power supply and defective connections between the various circuits and components of the computer. By rapidly heating and cooling the components within a computer, power cycling can detect faulty circuit and/or components which do not perform within specified tolerances as a result of this rapid heating and cooling. Typically, such faulty circuits or components cause current fluctuations which can damage the computer or detrimentally effects its performance.
In the prior art, there are apparatuses and methods for automatically testing and power cycling computers. However, these prior art systems and methods do not operate in conjunction with a diagnostic program embedded within the computer to fully test various components, systems and/or interfaces within the computer while power cycling the computer in a simple, less expensive and elegant manner. For example, Mallory et al., U.S. Pat. No. 5,353,240, which is incorporated herein by reference, discloses a test apparatus and method for automatically testing computing equipment.
The test apparatus disclosed by Mallory et al., comprises a switch for switching power to a computer and also includes a complicated testing circuit coupled to the switch for testing whether the computer has turned on successfully. However this test apparatus does not operate in conjunction with a diagnostics software program as would be required to test various components, subsystems and/or interfaces within the computer. Instead, the test apparatus of Mallory et al., has a microprocessor based testing circuit which receives signals from the computer via the keyboard port of the computer.
The microprocessor of the test circuit disclosed by Mallory et al. has a memory for storing a time signal received from the computer. In addition, the testing circuit has the ability to receive a condition signal from the computer which indicates whether the computer has successfully restarted following the passage of a period of time. This condition signal also indicates whether testing on the computer is currently in progress, whether the computer needs attention, or whether the computer has successfully rebooted, failed or timed out.
Prior art test apparatus, such as that described above, do not provide thorough diagnostic testing of the various systems and components of a computer during rigorous power cycling of the computer. For example, Mallory et al., does not disclose any type of software diagnostics program, embedded within the computer, which cooperates with the power-cycling apparatus in order to test and power cycle the computer. Rather, Mallory et. al., discloses a complex microprocessor based testing apparatus and power cycling circuit which can only test whether the computer has successfully restarted.
Systems such as that disclosed by Mallory et al. have not met the needs of the rapidly growing computer manufacturing industry which include the need to test for conditions such as improper resetting of the computer's BIOS code, or corruption of the BIOS code, or faulty circuits on the motherboard which can only be detected by a diagnostics program operating in conjunction with the power cycling of the computer.
Because it would be extremely tedious, and would consume human resources, to manually turn a computer on and off while running various diagnostic tests via a software program embedded in the computer during power cycling, a method and apparatus are needed which can automatically power cycle the computer and successively run diagnostics tests on the computer in order to detect various defects within the computer at an early stage after the manufacturing process.

Method for burning in and diagnostically testing a computer


The invention concerns a control system for operating a ship's motive installation (1, 2). Via a gearing (4) having adjustable clutches (67, 69) for forward and astern movement, an engine (3) drives a propeller shaft (7). Control and sensor devices (53, 54) are provided. With them the engine speed and the degree of slip of the clutches can be altered. With a control lever (13, 14) of a control post (9) a propeller shaft speed can be adjusted. A control electronics (21) defines the momentary operational condition by freely selecting from three possible operation conditions. The respective operation condition is defined depending on operational parameters to be observed of the engine (3) and/or the gearing (4). The control system is particularly adequate for use within a ship's multi-engine motive installations.

From the prior art, a control system for operating a motive installation (publication of the firm Sturdy Marine Division "Marine Digital Control System" masthead Sep. 21, 1988) is known. This concerns a motive installation having a port-side and a starboard-side engine which are operatively connected via a respective gearing with a port-side and a starboard-side propeller shaft. With each motive group are coordinated three adjusting devices (control means) for the throttle valve adjustment (throttle servo), for gear selection (gear shift servo) and for actuating an adjusting valve of a clutch (trolling valve servo). The control means enumerated are attached via an electric line connection to an electronic control mechanism (CPU). Another electric connection exists between the control posts and the control mechanism.
The ship's motive installation can be operated with the control system known already by the fact that from two possible operating mode bits, one mode bit is selected. In a first operating mode, one of the clutches (forward and astern movement) is completely engaged. The velocity of travel is produced by varying the engine speeds. In another mode of operation, one engine speed is maintained while the travel velocity of the ship is determined by the degree of slip of the clutches (trolling). Adjustable slip clutches for driving a ship forward and astern have been disclosed in DE-OS 21 20 639.
In another control system already known for operating a motive installation, a mode bit selector device is provided in which a specific manner of operation can be preselected. According to the manner of operation preselected, a certain function is associated with the control lever of the control post. When preselecting the travel mode bit (cruise control), the clutch for forward movement is engaged. The engine speed is varied with the control lever in order to adjust a specific travel speed. When the slow travel mode bit (troll mode) is preselected with the mode bit selector device, the function associated with the control lever is altered. As long as said mode bit is selected, the engine is operated at a specific, uniform speed. The travel speed is varied via the control lever in such a manner that the degree of slip of the respective clutch of the gearing is selected of a greater or lesser magnitude. The rate of revolution of the propeller shaft is thus varied via the degree of slip of the clutch. The known control system has at its disposal control electronics to which are attached an input and output unit, a display unit and control and sensor devices (see publication of the firm Twin Disc "Twin Disc Power Commander" masthead: 319 MEC 5M-1-88).
DE 39 07 841 A1 discloses exclusively a control apparatus for a ship's propulsion system which fundamentally coincides with the one above described. The control electronics consists of a main communication control mechanism and an auxiliary communication control mechanism. The port-side motive installation is controlled via the main control mechanism while the starboard-side motive installation is monitored by the auxiliary control mechanism. For this purpose, the port-side control levers of the control posts (main and secondary control posts) are attached to the main control mechanism while the control starboard-side control levers of the control posts (main and secondary control posts), respectively, have one electric connection to the auxiliary control mechanism. The main communication control mechanism is additionally connected with the auxiliary communication control mechanism via line connections. The control and sensor devices are each separately attached to the main control mechanism (on the port-side) and the auxiliary control mechanism (on the starboard-side). A mode selector device and a display unit are coordinated with each control lever.
The known control systems, which make it possible to operate a motive installation using control electronics, have the advantage that a precise regulation of specific nominal values (such as the engine speed and the propeller shaft speed) is possible. Despite the use of electronic parts, on the other hand, it has only been limitedly attained to facilitate to the user the operation of said systems. For the attachment of a control post two connecting lines are required which, when for instance using a total of six control posts, means that twelve line connections are always needed. To this must be added other line connections for interconnecting the control mechanism and attaching other functions (alarm, command keys for the post delivery and acceptance). It must further be borne in mind that the failure of the electronics does not always lead to the failure of both motive installations. The already known control systems in which a specific operating mode must be preselected require a certain measure of technical understanding for a faultless handling. On one hand, the operator not always has such a technical understanding to the desired extent and, on the other, it finally is another condition to have the ability to take into consideration other requirements and peculiarities when wiring such a ship's motive installation. For the above stated reasons, faulty conditions are not ruled out in the known control systems. This includes that the motive installation is not always operated as would be required and also possible in view of the given technical prerequisites.

Control system for operating a ship's motive installation


An improved system connects subsea coupling components mounted to a movable junction plate assembly and a fixed junction plate assembly of a subsea petroleum recovery tree. The connecting handle on a movable junction plate assembly is biased for locking engagement with a movable plate to manipulate the movable junction plate assembly, but may be unlocked upon engagement with the fixed junction plate assembly to permit rotation of the connecting handle and thereby threadedly connect the junction plate assemblies. An extension arm assembly for supporting the movable junction plate assembly may be pivotably mounted to a control pod assembly, with the extension arm being extendible and contractible to allow an ROV or diver to move the junction plate assembly within a preselected zone of control.

Those familiar with subsea operations involving hydrocarbon recovery have recognized for decades that various subsea devices, such as control pods, must be powered by hydraulic or electrical lines extending to the devices from another location, such as the water surface. Since it may be necessary to repair or replace one such control pod, the hydraulic and/or electrical lines are coupled by suitable subsea connections. These connections accordingly are both made up and broken apart in the subsea environment, and those skilled in the art recognize the difficulty often encountered performing operations in a subsea environment which are relatively simple when performed in a normal atmospheric environment. Accordingly, the time and expense of utilizing a remotely operated vehicle (ROV) or a diver to perform the necessary coupling or decoupling operations can be significantly reduced if the coupling construction and method of coupling are simplified. Also, by increasing the reliability of the coupling operation, the risks associated with a more difficult and time consuming subsea operation is minimized. Accordingly, the overall costs associated with performing the subsea coupling and decoupling operations may be minimized by improved coupling technology.
ROV's traditionally have used to manipulate in position a junction plate assembly having either male or a female coupler halves, so that the moveable junction plate assembly may be secured to another plate assembly (e.g., a fixed junction plate assembly) having opposing male or female coupler halves to make up the coupled hydraulic or electrical lines. Traditionally, the movable junction plate assembly has a handle affixed thereto, which can be grasped by the arm of the ROV or diver for the purpose of manipulating the junction plate assembly to its desired position with respect to the fixed plate assembly. Once properly positioned, the ROV arm would then release the handle, and grasp a protruding drive screw of the junction plate assembly. The drive screw was subsequently rotated by the ROV to threadably connect the movable junction plate assembly to the fixed junction plate assembly. Those skilled in the art recognize that this sequence of operations, whether performed by a diver or an ROV, is somewhat cumbersome in the subsea environment. Problems have repeatedly occurred when trying to grasp either the junction plate handle or the protruding drive screw. Problems have also occurred when the movable junction plate assembly is not maintained in a secured position when the manipulating handle is released by the ROV, in which case the ROV arm may have difficulty grasping the protruding drive screw.
Additional problems are sometimes encountered when an ROV is moving a junction plate assembly from one location to another location. At times, the ROV may unintentionally release its grasp on the movable junction plate assembly, e.g., if the ROV is temporarily deactivated. When this occurs, the junction plate with the electrical and hydraulic lines connected thereto drops until it either rested on an object it strikes, or is suspended subsea from the electrical or hydraulic lines. In many cases, a falling junction plate assembly may drop to a position such that it is extremely difficult and thus costly to retrieve the junction plate assembly. Also, the dropping junction plate assembly may cause significant damage to either the junction plate assembly or to subsea components the assembly strikes, and/or may damage the hydraulic or electrical lines or their connections.
U.S. Pat. No. 4,194,857 discloses a subsea station with fluid conducting lines arranged to compensate for expansion and contraction, and to provide yieldability in the makeup connections. U.S. Pat. No. 4,611,831 discloses a connection device for connecting a series of circuits. A cylindrical lock is provided with a projecting head and a lateral pin. By compressing a biasing spring, the pin may be rotated 90 degrees to lock a first support piece to a centerpiece. The device of the '831 patent is not intended for subsea applications, and the cylindrical lock would not be easily adapted for securing a movable junction plate assembly to a fixed junction plate assembly in the reliable manner required by a subsea operators. U.S. Pat. No. 4,643,616 discloses a device for activating and connecting modules of a subsea oil production station. The device includes a telescopic articulated gib for manipulating a mechanical action connector. U.S. Pat. No. 4,915,419 discloses a locking mechanism for mating and unmating male and female coupling members in a subsea application. The apparatus includes a lock plate supported by a junction plate which is slidable between an unlocked position and a locked position. U.S. Pat. No. 5,024,467 discloses an assembly for coupling and uncoupling connection elements, such as pipes or conduits.
The disadvantages of the prior art are overcome by the present invention, and an improved movable junction plate assembly and fixed plate assembly for making up and breaking apart hydraulic or electrical couplings, and a method of connecting and disconnecting such couplings in a subsea environment, is hereinafter disclosed. The junction plate assemblies and techniques of the present invention have thus long been desired by subsea operators to meet the demands of systems which can reliably couple and uncouple hydraulic and electrical lines in subsea operations with minimal difficulty.

ROV installable junction plate and method


A method for matching templates and a system thereof. Each template includes a plurality of data chunks, each data chunk representing a minutia and comprising a location, a minutia angle and a neighborhood. The location is represented by two coordinates. In one embodiment, each coordinate and the minutia angle are quantized. The neighborhood includes positional parameters with respect to a selected minutia for a predetermined number of neighbor minutiae. In one embodiment, a neighborhood boundary is drawn around the selected minutia and neighbor minutiae are selected from the enclosed area. A reference template is compared to a measured template on a chunk-by-chunk basis. A chunk from each of the template is loaded into a random access memory (RAM). The location, minutia angle and neighborhood of the reference data chunk are compared with the location, minutia angle and neighborhood of the measured data chunk, respectively.

Biometric identification is used to verify the identity of a person by digitally measuring selected features of some physical characteristic and comparing those measurements with those filed for the person in a reference database, or sometimes on a smart card carried by the person. Physical characteristics that are being used include fingerprints, voiceprints, the geometry of the hand, the pattern of blood vessels on the wrist and on the retina of the eye, the topography of the iris of the eye, facial patterns and the dynamics of writing a signature and typing on a keyboard.
The fingerprint is one of the most widely used physical characteristics in biometric identification. Fingerprints are utilized as the most reliable means to identify individuals because of two outstanding characteristics; namely that they remain unchanged all through life and differ from individual to individual. Fingerprints consist of raised friction ridges of skin separated by recessed valleys of skin. Fingerprint "minutiae" are conventionally defined as ridge endings or ridge bifurcations where a ridge splits into two ridges.
Since the matching of a fingerprint as an image can require large file capacity to store the measured and referenced features and complex computation to match measured features with reference features, fingerprint identification is carried out using the positional relationship of features or minutiae that are extracted from the fingerprint image. The minutiae representing a fingerprint image are digitized and stored in a digital memory, which may be a readonly memory, magnetic tape, or the like. A fingerprint digitized in this manner may be compared with reference fingerprints stored in the memory. For the comparison to work, the reference fingerprint and the measured fingerprint must be extracted, characterized, and digitized so that the fingerprint templates contain the same information and have the same format.
One application of fingerprint identification is to use the fingerprint to unlock a smart card which often contains encrypted information. Presently, a PIN (personal identification number) is required to be entered by the user before the encrypted information can be extracted from the smart card and used. The use of a PIN has many drawbacks. For example, the accounting or card issuing organization faces significant administrative cost in handling the secret codes and the card holders have to memorize the secret codes.
Some privacy laws, for example, the privacy laws in Europe, require sensitive information such as a reference fingerprint template to be stored on the smart card in a way that it cannot leave the card without first unlocking the card with a PIN. Therefore, for a fingerprint matching scheme to be practical in Europe, the fingerprint template matching algorithm must be executed by a microprocessor in the smart card. Otherwise, the smart card must be unlocked by some other mechanism, such as a PIN, before the reference fingerprint template can be read. The difficulty of executing conventional fingerprint template matching algorithm on a smart card is mainly due to the limited computational capabilities and memory of a conventional smart card. For example, a conventional smart card typically has less than 512 bytes of RAM (with 256 bytes being typical) and between 1 Kilobyte and 16 Kilobytes of memory. An 8-bit RISC (reduced instruction set computer) microprocessor has a speed between 1 MegaHertz to 10 MegaHertz which is quite slow given the magnitude of the computations required to complete a comparison between a measured fingerprint and a reference fingerprint. In effect, the hardware constraints prevent the use of fingerprint to unlock data from smart cards.
In addition to hardware constraints, another important design criterion is cost. U.S. Pat. No. 4,582,985 (hereinafter, the '985 patent) entitled "Data Carrier", issued Apr. 15, 1986, to Bo Löfberg and hereby incorporated by reference in its entirety, describes a data carrier of a card type. According to the '985 patent, the data carrier includes a fingerprint verification device for carrying out the verification process. The verification device includes a sensor device for sensing a finger tip of the owner and obtaining the corresponding finger print line information. A specialized smart card must be used to accommodate the sensor device since a conventional smart card does not provide such accommodations. In addition, since the fingerprint template generation, storage, and comparison are done at the data carrier, the microprocessor of a conventional smart card is not adequate. Hence, a specialized smart card having a more capable processor must be used, thereby increasing cost.
Therefore, what is needed are systems and fingerprint template matching algorithms that can be executed by a microprocessor with low memory and low computational capacities, thereby keeping the cost of the smart card at an acceptable level.

This patent is subject to a terminal disclaimer.

Method and system for fingerprint template matching


A mobile communication device has a housing, a communication part, a display part, a detection part, and a control part. The communication part transmits and receives messages. The display part displays a first message, or a second message that is related to the first message. The detection part detects a change in the state of the housing. The control part that displays the second message on the display part in the display direction that is different from the display direction of the first message in case in which the detection part detects a change in the state of the housing when the display part displays the first message.

Mobile communication devices such as mobile phones, comprising a message communication function that transmits and receives messages, are known. For example, mobiles phones, in which multiple messages subjected to previously defined specific key operations or message processing operations are deployed and displayed respectively on a display part, are known. As another example, mobile phones in which incoming messages can be viewed while composing messages for transmission by displaying multiple messages simultaneously on the display part, are also known.

Mobile communication device, display method, and display program of mobile communication device


A coated article is disclosed including a substrate, a bond coating, and a thermally insulating top coating. The substrate includes a substrate surface and a substrate material at the substrate surface. The bond coating is disposed on and contacts the substrate surface, and includes the substrate material and a bond coating surface distal from the substrate surface. The bond coating surface includes a greater surface roughness than the substrate surface. The thermally insulating top coating is disposed on and contacts the bond coating surface. A method for forming the coated article includes applying the bond coating to the substrate surface, and applying the thermally insulating top coating to the bond coating surface.

Gas turbines for power generation systems must satisfy the highest demands with respect to reliability, power, efficiency, economy, and operating service life. Modern high-efficiency combustion turbines have firing temperatures that exceed about 2,300° F. (1,260° C.), and firing temperatures continue to increase as demand for more efficient engines continues. Many components that form the combustor and "hot gas path" turbine sections are directly exposed to aggressive hot combustion gases. The use of coatings on turbine components such as combustors, combustion liners, combustion transition pieces, combustion hardware, blades (buckets), vanes (nozzles) and shrouds is important in commercial gas turbine engines.
Coatings, such thermal barrier coating systems, contribute to desirable performance characteristics and operating capabilities at elevated temperatures. Typical thermal barrier coating systems include a bond coating disposed on the substrate of the turbine component, and a thermally insulating top coating disposed on the bond coating. The bond coating can be a diffusion type of coating or an MCrAlY type of coating, where M is nickel, cobalt, iron, or a combination thereof. The bond coating provides oxidation and hot corrosion protection to the underlying substrate of the turbine component, which are typically made of nickel-based, cobalt-based, or iron-based superalloys. Bond coatings also provide an interface for the ceramic top coat to adhere. However, while bond coatings improve adherence of the thermally insulating top coating, bond coatings are themselves often weaker than the underlying substrate due to their chemical compositions and phase constituents, which are different than the composition of the substrate, and may also be different than the phase constituents of the substrate. The chemical mismatch between the substrate and the bond coating creates a diffusion couple, and results in the formation of an interdiffusion zone with properties that are different than the bond coating and the substrate, and also creates a differential in the coefficient of thermal expansion across the substrate-interdiffusion zone-bond coating. It furthermore results in the formation of new, sometimes detrimental phases, which may cause embrittlement at the substrate/bond coating interface. Among other factors, the quality of the bond coating/substrate interface and the coefficient of thermal expansion transition in the thermal barrier coating system has an impact on the overall life capability of the thermal barrier coating system, and may lead to early spallation of the thermally insulating top coating.


A method of storing data in a storage medium includes determining a compensation unit for a portion of the storage medium, reading a first set of bit values from the portion of the storage medium, determining a compensation value based at least in part on an erroneous bit value of the first set of bit values and the compensation unit, and storing the compensation value in association with the portion of the storage medium.

Magnetic media is used to store data. Continuous perpendicular media is one type of magnetic media that is prevalent. Other types of magnetic media are candidates for extending magnetic recording to 1 Tb/in2 and above. These include Bit patterned media (BPM), thermal assisted recording media (TAR) or its alternative name of Heat assisted magnetic recording (HAMR) and discrete track media (DTM). Magnetic recording can employ synchronization between a write clock and specific disk locations during writing. For BPM, write errors can occur even for perfect synchronization due to statistical variations in the lithography placement and magnetic properties of an island, as well as the presence of gross defects. In the case of BPM media such defects can also be missing islands. One way to mitigate the effect of write errors is to increase the error correction code (ECC) strength, at the expense of loss of areal efficiency due to the associated overhead of disk real estate. For a given fabrication process, the statistical variations tend to scale unfavorably with increasing bit density. As ECC is to handle rare statistical variations in storage media properties, increasing ECC is not always an efficient way to compensate for write errors that occur in the write process. A more efficient storage scheme is achieved when write errors are minimized by optimizing the write process to compensate for the specific local variations in storage media properties.

Method to reduce written-in errors in storage media


An apparatus, system, and method are disclosed for modifying data set names. A communication module receives a data set name as an index of a catalog entry for a catalog. The data set name comprises at least two qualifiers. A modification module modifies at least one data set name qualifier using a naming algorithm, wherein an alias qualifier is not modified. A store module stores the catalog entry indexed with the modified data set name in order to optimize the location of that entry within the catalog.

1. Field
This invention relates to data set names and more particularly relates to modifying data set names.
2. Description of the Related Art
Data sets are typically stored in storage devices such as hard disk drives, optical storage devices, and the like. A data set may include a file, a data structure, a database, and/or the like. A catalog may store information regarding each data set. For example, the catalog may store a location, a creation date, a modified date, and a size for the data set.
The data set information may be stored in a catalog entry. Catalog entries are often indexed with one or more names of the data sets that the catalog entries reference. Thus, the data set's name is used to access the data set's catalog entry. The catalog entry may then be used to access the data set.
The catalog may be stored in a memory of a computer. Alternatively, the catalog may be stored on an external storage device. For example, the catalog for a storage subsystem may be stored on one or more logical volumes comprising one or more physical storage devices.
A plurality of extents may be allocated to store the catalog. In addition, the catalog may be organized so that catalog entries occupy the extents in a sequential order keyed to an index such as the data set name. Such a catalog may be optimized for random indexes. Unfortunately, repeatedly saving the information regarding the data set in such a catalog may cause unintended growth in a size of the catalog.

International Business Machines Corporation