Drain driver output terminals (lead lines) are divided into six groups (R1, R2, G1, G2, B1, B2) of positive polarity and negative polarity for three primary colors: respective ones are bundled together for connection to drain line common lines; and then, these drain line common lines are drawn out of a drain driver mount region. Gate driver output terminals (lead lines) are divided into three groups (GA, GB, GC) including a front stage and a next stage plus a rear stage; and respective ones are bundled together for connection to gate line common lines. These gate line common lines are drawn out of a gate driver mount region; and then, tests are preformed with probes attached to test terminals provided at such drain line common lines and gate line common lines.

1. Field of the Invention
The present invention relates generally to liquid crystal display devices and, more particularly, to liquid crystal display devices of the thin-film transistor type with test procedures made easier for inspection of functional operabilities of thin-film transistors and connection failures at scan line lead lines and/or signal line leads. This invention also relates to a method for manufacturing the same.
2. Description of the Related Art
Liquid crystal display devices are widely employed as high-precision color display devices for use in notebook computers and display monitor units.
Currently available liquid crystal display devices include those of the simple matrix type using a liquid crystal panel with a liquid crystal layer interposed between a pair of substrate having inside surfaces on which parallel electrodes are formed in a manner that these cross over each other, and the ones of the active matrix type using a liquid crystal display element (referred to also as liquid crystal panel hereinafter) having switching elements for selection in units of pixels on one of a pair of substrates.
Active-matrix liquid crystal display devices include a liquid crystal display device of the so-called longitudinal electric field scheme such as twisted nematic (TN) scheme (generally called TN type active-matrix liquid crystal display device) using a liquid crystal panel with a group of pixel selection electrodes formed on a respective one of a pair of upper and lower substrates, and a liquid crystal display device of the so-called lateral electric field scheme (generally known as IPS type liquid crystal display device) using a liquid crystal panel with such pixel selection electrode group formed on only one of a pair of upper and lower substrates.
Typically a liquid crystal panel making up the former Tn type active-matrix liquid crystal display device is such that liquid crystals are aligned to twist by 90xc2x0 within an interior space of a pair of substrates (two substrates consisting of a first substrate (lower substrate) and second substrate (upper substrate)), wherein two polarization plates are multilayered on outside surfaces of the upper and lower substrates of such liquid crystal panel respectively, with absorption axis directions being disposed in a cross polarization or xe2x80x9ccrossed Nicolxe2x80x9d fashion and also with light entrance side absorption axes being in parallel or at right angles to a rubbing direction.
In the TN type active-matrix liquid crystal display device thus arranged, incident light becomes linearly polarized light at an incidence side polarization plate upon application of no voltages. This linear polarized light travels along twisting of a liquid crystal layer and if the penetration axis of a light output side polarization plate is identical to the azimuth angle of the linear polarized light then all rays of the linear polarized light are permitted to go outwardly resulting in establishment of a white display (what is called the xe2x80x9cnormally open modexe2x80x9d).
In voltage application events a unit vector""s direction (director) indicating the average orientation direction of axes of liquid crystal molecules constituting the liquid crystal layer becomes perpendicular to substrate surfaces while the azimuth angle of incidence side linear polarized light is kept unchanged, thus resulting in coincidence with the absorption axis of the light output side polarization plate to thereby obtain a black display (see xe2x80x9cBasics and Applications of Liquid Crystals,xe2x80x9d issued by Industry Research Association. 1991).
On the other hand, in an IPS type liquid crystal display device with pixel selection electrodes and electrode leads formed on only one of a pair of substrates for permitting switching of its liquid crystal layer in a specified direction extending in parallel to substrate surfaces through voltage application between neighboring electrodes (between a pixel electrode and counter electrode) on this substrate, polarization plates are so disposed as to to provide the black display when no voltages are applied thereto (so called the xe2x80x9cnormally close modexe2x80x9d).
The IPS type liquid crystal display device""s liquid crystal layer exhibits homogeneous alignment or orientation parallel to the substrate surfaces in the initial state. Simultaneously the director of the liquid crystal layer in a plane parallel to the substrates is parallel or slightly angled to the electrode lead direction upon application of no voltages, causing the direction of the director of the liquid crystal layer in voltage application events to shift toward a direction perpendicular to the electrode lead direction upon application of a voltage thereto. When the liquid crystal layer""s director direction is tilted toward the electrode lead direction by 450xc2x0 in comparison with the director direction when no voltage are applied thereto, the liquid crystal layer upon application of the voltage causes the azimuth angle of polarized light to rotate 90xc2x0 as in {fraction (1/2)} wavelength plates resulting in coincidence between the light output side polarization plate""s transmission axis and the polarized light""s azimuth angle thus providing a white display.
This IPS type liquid crystal display device has its feature that changes in color phase and contrast stay less even at viewing angles thus enabling achievement of wide view-field angles (see Japanese Patent Laid-Open No. 505247/1993).
A major approach to attain full color image visualization of the respective types of liquid crystal display devices stated supra is to employ a color filter scheme. This is for realization by subdividing a pixel corresponding to a single dot of color display into three portions and disposing color filters of the three primary colorxe2x80x94e.g. red (R), green (G), and blue (B)xe2x80x94at such unit pixels respectively.
Although the present invention is applicable to the several types of liquid crystal display devices stated above, its outline will be explained below with a TN type active-matrix liquid crystal display device being as an example.
As previously stated, in a liquid crystal element (liquid crystal panel) making up the TN type active-matrix liquid crystal display device (referred to simply as active-matrix liquid crystal display device hereinafter for brevity purposes), there are formed on a liquid crystal layer side surface of one substrate of two transparent dielectric substrates typically made of glass plates mutually opposed with a liquid crystal layer interposed therebetween a group of scanning signal lines (referred to as gate lines hereinafter) extending in its xe2x80x9cxxe2x80x9d direction and being parallel disposed in xe2x80x9cyxe2x80x9d direction and a group of drain lines (video signal lines) isolated from this gate line group and extending in the y direction while being parallel disposed in the x direction.
A respective one of regions surrounded by these gate line group and drain line group becomes a pixel region in which a thin-film transistor (TFT) for use as an active element (switching element) and a transparent pixel electrode are formed by way of example.
When a scan signal is supplied to a gate line, the thin-film transistor turns on causing a video signal coming from a drain line to be supplied to the pixel electrode via this turned-on thin-film transistor.
Additionally each drain line of the drain line group and each gate line of the gate line group are extended up to the periphery of a substrate to constitute external terminals respectively, to which video drive circuits and gate scan drive circuitsxe2x80x94namely a plurality of drive IC chips (semiconductor integrated circuits as will be referred to simply as drive ICs or ICs hereinafter) making up these circuitsxe2x80x94are connected respectively, which are separately mounted at the substrate periphery. In other words a plurality of tape carrier packages (TCPs) with these respective drive ICs mounted thereon are externally bonded to peripheral portions of the substrate.
However, since such substrate is designed so that TCPs with drive ICs mounted are externally attached at the peripheral portions thereof, the occupation area of a region (generally called xe2x80x9cpicture framexe2x80x9d) defined between contour lines of a display region as formed of the substrate""s cross-over regions of the gate line group and drain line group and an outer frame of the substrate becomes larger undesirably, which is against a demand for reducing or minimizing the outside dimensions of a liquid crystal display module with the liquid crystal display element and an illuminance light source (backlight unit) and other associative optical elements integrated therein together.
Thus, in order to avoid this problem or at least minimize risks, i.e. to fully meet demands for high-density mountability of the liquid crystal display element and also downsizing of the outer size of liquid crystal display module, the so-called flip-chip scheme or alternatively chip-on glass (COG) scheme has been proposed for permitting direct mounting of drive ICs for video driving and drive ICs for scan driving on one substrate (lower substrate) without the use of any TCP components. And, the drive ICs are designed to employ the so-called FCA scheme for permitting electrodes formed on back surfaces of such drive ICs to be directly connected to electrical wiring leads formed on the substrate.
FIG. 10 is a perspective view diagram for explanation of main part of a liquid crystal display device of the FCA mount scheme. This liquid crystal display device is arranged so that a liquid crystal layer is interposed between one substrate SUB1 with a matrix array of thin-film transistors formed thereon and a remaining substrate SUB2 with color filters formed thereon.
The one substrate SUB1 has its one peripheral side along which scan line drive ICs (referred to as gate drivers hereafter) GDR are mounted by the FCA scheme. In addition signal line drive circuit ICs (drain drivers) DDR are similarly mounted by FCA scheme along another side of the substrate.
Outputs of the gate drivers GDR are connected to scan line extension leads GTM whereas inputs thereof are connected to wiring lines of a flexible printed circuit board FPC1. Outputs of the drain drivers DDR are connected to signal line leads DTM; their inputs are coupled to wiring lines of a flexible printed circuit board FPC2.
As shown by arrows In FIG. 10, the flexible printed circuit boards FPC1, FPC2 are such that the flexible printed circuit board FPC1 is bent in a direction BENT1 toward the back surface of one substrate SUB1; then, a curvature portion JT2 of the flexible printed circuit board FPC2 is folded along a fold line BTL in the BENT1 direction and then folded in a direction BENT3 for accordion-like folding onto the back surface of flexible printed circuit board FPC1.
Under this condition, let the flexible printed circuit board FPC2""s connector CT4 be connected to a connector, not shown, as provided on the flexible printed circuit board FPC1. An adhesive tape BAT is interposed on the inner surface of the folded portion of the flexible printed circuit board FPC2, resulting in fixture to flexible printed circuit board FPC2.
Note here that reference characters xe2x80x9cCHGxe2x80x9d and xe2x80x9cCHDxe2x80x9d designate electronics components such as capacitors and others; ALMG, ALMD denote alignment marks; POL2 is a polarization plate; AR, a display region.
In the liquid crystal display device with the above arrangement, let probes of test/inspection equipment be attached to extension leads of the gate lines and extension leads of the drain lines which are extended from the thin-film transistors formed on one substrate SUB1 to thereby perform several tests for inspection of thin-film transistor characteristics and connection failures at respective electrical leads and turn-on or xe2x80x9clightingxe2x80x9d tests after adhesion with the other substrate.
FIG. 11 is a layout explanation diagram of test terminals in one prior art liquid crystal display device, wherein part (a) is a pictorial representation of the gate driver side whereas (b) depicts the drain driver side.
At the part (a), GTM designates gate line extension leads; TPC denotes test terminals; GDR indicates gate driver mount portions (shown by dot lines); LCT is a laser cut line; ASCL, a gate line side static electricity suppression common line; GTM, input terminals of the gate drivers GDR.
In the manufacture of one substrate SUB1 (thin-film transistor substrate), the gate line extension leads GTM are short-circuited by the static electricity suppression common line ASCL for protection against damages of thin-film transistors and wiring leads occurring due to invasion of static electricity. Thereafter, individually cut the gate line leads GTM along the laser cut line LCT; then, attach the probes to the test terminals TPC for inspection of connection failure or unwanted open-circuiting while performing lighting tests upon application of more than one signal thereto.
In part (b), DTM designates drain line extension lines; TPC denotes test terminals; DDR indicates drain driver mount portions (shown by dot lines); LCT is a laser cut line; ASCL, drain line side static electricity suppression common line; TTB, input terminals of the gate drivers GDR.
Similarly, on the drain driver side also, in the manufacture of such substrate, the drain line extension leads DTM are short-circuited by the static electricity suppression common line ASCL for preclusion of damages due to invasion of static electricity at thin-film transistors and wiring leads concerned. Thereafter, individually cut the drain line leads DTM along the laser cut line LCT: then, attach all the probes to the test terminals TPC at a time for open-circuit inspection while performing lighting tests upon application of a signal(s) thereto.
An example of this flip-chip scheme liquid crystal display device is disclosed in Japanese Patent Laid-Open No. 122806/1996.
In the prior art test terminal layout, the requisite number of gate drivers and drain driversxe2x80x94in particular drain driversxe2x80x94increases with growth in high-precision displayability, resulting in a decrease in pitch of output terminals thereof (pitches of GTM and DTM of FIG. 11).
As a result, it becomes impossible to provide sufficiently large widths and lengths of the test terminals (TPC of FIG. 11), which in turn makes it difficult to achieve simultaneous contacting of all probes as in the prior art, leading to occurrence of a problem as to a decrease in inspection accuracy due to probe deviation during open-circuit and lighting tests while externally applying test voltages to the test terminals involved. In addition, production of such probes applied to the output terminals with such narrow pitches is also becoming more difficult.
An object of the present invention is to avoid the problems faced with the prior art to thereby provide a liquid crystal display device having a wiring lead structure capable of execution of a variety of kinds of tests with simultaneous contact of probes to all terminals at a time and also capable of using test/inspection apparatus having probes with common useabilities for multiple types of products by standardization of a pattern of test terminals.
Another object of this invention is to provide a liquid crystal display device capable of facilitating production of the probes at low costs and a method for manufacturing the device.
A further object of the invention is to provide a liquid crystal display device similar to that stated above and capable of suppressing reduction of detection abilities as to display defects during inspection and a manufacturing method thereof.
To attain the foregoing objects the present invention provides as its representative means a technique for subdividing output terminals (lead lines) of drain drivers into six separate groups with regard to the three primary colors of red, green and blue, which groups are of a positive polarity of red, negative polarity of red. positive polarity of green, negative polarity of green, positive polarity of blue, and negative polarity of blue, wherein respective ones are bundled and connected together to drain line common lines, which are taken out of a drain driver mount region for permitting execution of inspection while letting probes be attached to test terminals as provided at the drain line common lines.
In addition, regarding the gate driver side, a technique is provided as a representative means for classifying output terminals (lead lines) of gate drivers into three groups of a front stage, next stage and rear stage or alternatively four groups for letting polarities become reversed in units of respective dots, wherein respective ones are bundled and connected together to gate line common lines, which are taken out of a gate driver mount region for permitting execution of inspection while letting probes be attached to test terminals as provided at the gate line common lines.
Some representative arrangements of the present invention will be set forth below.
(1) In a liquid crystal display device including:
a pair of substrates with a liquid crystal layer interposed therebetween, one of said substrates having thereon a matrix array of thin-film transistors, pixel electrodes as driven by the thin-film transistors, and a pattern of scanning lines and signal lines for supplying the thin-film transistors with voltage signals used for pixel formation, a remaining one of said substrates having color filters of three colors of red and green plus blue, the one substrate also having a peripheral si de with scan line lead terminals provided and another peripheral side with signal line lead terminals provided;
a scan line drive IC mount region and signal line drive IC mount region having output terminals connected to respective ones of said scan line lead terminals and said signal line lead terminals of the liquid crystal panel while permitting direct mount of more than one scan line drive IC and more than one signal drive IC respectively: and
more than one static electricity suppression common line provided in a cut removal region for commonly connecting said scan line lead terminals and signal line lead terminals together,
the device is specifically arranged to comprises:
six signal line side common lines provided in the signal line drive IC mount region of the signal line lead terminals connected to said static electricity suppression common line, for connection with six terminal groups as divided from the signal line lead terminals in a way such that the groups are of positive polarity of red, negative polarity of red, positive polarity of green, negative polarity of green, positive polarity of blue, and negative polarity of blue; and
test pads provided on said one substrate in an area excluding said signal line drive IC mount region for connection to said six signal line side common lines.
With such an arrangement, it is possible to enlarge the width and length plus pitch of test pads for connection to the signal line leads, thus making it possible to make easier production of the probes, resulting in an increase in contact accuracies.
(2) The test pads of said six signal line side common lines are disposed in the cut removal region of said one substrate.
It is possible to standardize patterns of the test pads, thereby enabling the intended inspection of liquid crystal display devices of multiple types of products to be done by use of test apparatus or equipment having a common probe or probes.
(3) In a liquid crystal display device including:
a pair of substrates with a liquid crystal layer interposed therebetween, one of said substrates having thereon a matrix array of thin-film transistors, pixel electrodes as driven by the thin-film transistors, and a pattern of scanning lines and signal lines for supplying the thin-film transistors with voltage signals used for pixel formation, a remaining one of said substrates having color filters of three colors of red and green plus blue, the one substrate also having a peripheral side with scan line lead terminals provided and another peripheral side with signal line lead terminals provided;
a scan line drive IC mount region and signal line drive IC mount region having output terminals connected to respective ones of said scan line lead terminals and said signal line lead terminals of the liquid crystal panel while permitting direct mount of more than one scan line drive IC and more than one signal drive IC respectively; and
more than one static electricity suppression common line provided in a cut removal region for commonly connecting said scan line lead terminals and signal line lead terminals together,
the device comprises: three scan line side common lines provided in the scan line drive IC mount region of the scan line lead terminals as connected to the static electricity suppression common line, for connection with three groups being divided from the scan signal line lead terminals and having a front stage and next stage plus rear stage or alternatively four terminal groups as divided therefrom in order to let the polarity become reversed in units of dots;
six signal line side common lines provided in the signal line drive IC mount region of the signal line lead terminals connected to said static electricity suppression common line, for connection with six terminal groups as divided from the signal line lead terminals in a way such that the groups are of positive polarity of red, negative polarity of red, positive polarity of green, negative polarity of green, positive polarity of blue, and negative polarity of blue; and
test pads provided on said one substrate in an area excluding said scan line drive IC mount region and said signal line drive IC mount region for being associated with said three or four scan line side common lines and said six signal line side common lines respectively.
With this arrangement, it is possible to enlarge the width and length plus pitch of test pads for connection to the signal line leads, thus making it possible to make easier production of the probes, resulting in an increase in contact accuracies.
(4) The test pads of said three or four scan line side common lines and said six signal line side common lines are disposed in the cut removal region of said one substrate.
(5) The test pads of said three or four scan line side common lines and said six signal line side common lines are laid out with equal intervals in the cut removal region of said one substrate.
It is possible to standardize patterns of the test pads including scan lead lines also, thereby enabling the intended inspection of liquid crystal display devices of multiple types of products to be done by use of test apparatus or equipment having a common probe or probes.
(6) Said remaining substrate has thereon more than one counter electrode, the test pads of said three or four scan line side common lines and said six signal line side common lines are disposed in the cut removal region of said one substrate, and a test pad for connection to a lead line of the counter electrode is disposed along with the test pads of said three or four scan line side common lines and said six signal line side common lines.
It is possible to further promote standardization of patterns of the test pads including scan lead lines also, thereby enabling the intended test of liquid crystal display devices of multiple types of products to be done by use of test apparatus or equipment having a common probe or probes.
(7) Said one substrate has thereon more than one counter electrode, the test pads of said three or four scan line side common lines and said six signal line side common lines are disposed in the cut removal region of said one substrate, and a test pad for connection to a lead line of the counter electrode is disposed along with the test pads of said three or four scan line side common lines and said six signal line side common lines.
Since it is possible to dispose those lead lines of counter electrodes required for turn-on or xe2x80x9clightingxe2x80x9d tests also in the form of a standard pattern along with the test pads of the scan line side common lines and signal line side common lines, it becomes possible to further promote standardization of the test pad patterns, thereby enabling the intended test of liquid crystal display devices of multiple types of products to be done by use of test apparatus or equipment having a common probe or probes.
One significant feature of the present invention as disclosed and claimed herein lies in separation of the signal side common lines at least in units of respective colors of the color filters in the way stated previously. This invention is not the one that excludes arrangements for performing inspection while causing only the same signal to input to a video signal line concerning each color in any events. However, separating the signal side common lines at least in units of colors of the color filters as stated above makes it possible to reduce probe costs due to reduction of the requisite number of test pads to thereby enable achievement of tests with colors being displayed while at the same time enabling execution of the intended test procedure with high accuracies. In cases where the color filters are of the three primary colors of red, green, and blue, any kinds of tests become available with respect to almost every color to be displayed at products through individual inspections of red, green and blue due to lighting in units of respective colors in addition to white displaying with all colors being brightened at a time, and further lighting while controlling the gray-scale gradation levels of each color.
This means that color purity tests of respective colors become possible, which is a significant advantage of the arrangement incorporating the principles of the invention. Further, demonstrable improvement in test accuracies of display irregularities is realized, which is an effect that will no longer be attained by exclusive use of all-color simultaneous lighting schemes. The color filters are formed by a process having the steps of performing deposition and exposure plus development separately in units of colors thereof or alternatively by letting the individual colors be impregnated. Accordingly in-plane uniformity or distribution within a plane of film thickness will take place in units of respective colors. In the case of lighting all colors at once, influences of these will normally become inappreciable. For example, in case only the film thickness of red locally changes, the resultant influence of such red film thickness""s local change upon brightness or luminance during simultaneous lighting of all of the three colors of red, green and blue becomes ⅓ of that during uni-color lighting of red. Accordingly, the only use of all-color simultaneous lighting would result in occurrence of luminance irregularitiesxe2x80x94in. particular, a decrease in inspection sensitivities as to color irregularities, which leads to risks of outflow of defective products into the market. With the instant invention, it is possible by separating the signal side common lines at least in units of respective colors of the color filters in the way stated supra to establish tests with the colors being lit individually, which in turn makes it possible to realize probe cost reduction and test cost reduction plus high-precision product""s lighting tests while retaining test accuracies concerning luminance and color irregularities.
Although this test scheme is advantageous especially for FCA, similar results are also obtainable in TCP schemes through separation of the signal side common lines at least in units of colors of the color filters.
Another significant feature of the invention is that the signal side common lines are separated at least in units of colors of the color filters and for use as positive and negative polarities. Whereby, if the color filters are of three colors by way of example, then the resulting signal side common lines become six lines. Currently available liquid crystal display device drive methods include two major ones: a common inversion driving method, and dot inversion drive method. The common inversion drive is such that at least three signal line side common lines are employed as discussed above due to the fact that in most cases the pixels neighboring in a scan signal line extension direction are the same as each other in polarity relative to the reference signal potential. On the contrary, the dot inversion drive method is such that neighboring pixels in the scan signal extension direction are ordinarily driven in such a way that these are of opposite polarities relative to the reference signal potential. Due to this, in the case of using three signal line side common lines in dot inversion events, six certain pixels neighboring in the scan line extension direction become xe2x80x9c+xe2x88x92++xe2x88x92+xe2x80x9d by way of examplexe2x80x94in this case, any intended polarity inversion is no longer realizable between B and R. Even in this case, the above-noted detection accuracies of luminance/color irregularities can be maintained almost perfectly. Regrettably this advantage does not come without accompanying a penalty which follows: it becomes difficult to accurately inspect flicker, i.e. on-screen flickering, to be checked during lighting test procedure. Generally this flicker will become problematic only with special patterns or only at special timings, which is less in influence during real in-use events than the above-noted color/luminance irregularities; however, if such flicker stays at levels greater than a level defined by clients then a product with the flicker must be regarded as a defective one. Accordingly, with the invention, separating the signal side common lines in units of colors of the color filters and for use as the positive and negative polarities, e.g. employing six signal side common lines for use with color filters of the three primary colors, makes it possible to cause an array of six pixels of RGBRGB to have reversed polarities between adjacent ones of them in a pattern of xe2x80x9c+xe2x88x92+xe2x88x92+xe2x88x92xe2x80x9d by way of example.
Further, the flicker inspection accuracy in particular is variable depending upon the influence of a very small voltage difference between pixels; thus, it is required to control any possible delays of signal waveforms during inspection. Thus it is desirable that an increased number of test pads for input of test signals to signal line side common lines be provided with respect to each signal line, which number is given as (nxe2x88x921)/2 or more where xe2x80x9cnxe2x80x9d is the number of pads per unit region, which may be a chip mount region or alternatively a region with an ensemble of signal wiring leads provided therein. In addition, to suppress probe cost increases, it is desirable that the pad number be set at 2xc3x97(n+1) or less.
It is also desirable that the number of test signal terminals for inputting test signals to scan signal lines is greater than the number of test signal terminals for input of test signals to video signal lines. This is based on a requirement for reducing input resistivities of the video signal line side while taking account of the fact that execution of the intended test/inspection with the above-noted arrangements requires that the input frequencies of certain test signals to be applied to the video signal lines during inspection be higher than or equal to input frequencies of test signals being applied to the scan signal lines.
In addition, advantages as to lower resistivities are obtainable by providing a region formed of a specific wiring layer with the lowest resistivity in the liquid crystal display device at any one of those wiring leads associated with the signal line side common lines or alternatively between the signal line side and test pads and leads associated with the scan line side common lines or between the scan line side common lines and test pads.
Furthermore, with the invention, the scan line side common lines are arranged by more than two lines. Use of a single line enables all-line simultaneous lighting. However, difficulties can occur in regard to the above-mentioned flicker lighting inspection. More specifically, for either one of the common inversion driving and dot inversion driving, drive is done in real in-use states in such a way that two neighboring pixels in an extension direction of video signal lines are reversed In polarity to each other. This is for the purpose of flicker suppression. Thus, in order to perform inspection as to flicker, it is required to drive in a way that two neighboring pixels in the video signal line extension direction are mutually reversed in polarity. As the use of a single scan line side common line must result in such two pixels being the same in polarity as each other, there is a problem that no flicker tests are achieved in real in-use states. In view of this, by employing two lines for permitting two neighboring pixels to be deviated or shifted in write timing, it becomes possible to drive in such a way that the two neighboring pixels in the video signal line extension direction to be mutually reversed in polarity, thus enabling the intended flicker test.
In addition, with regard to the flicker, the influence of a xe2x80x9cjump-inxe2x80x9d voltage upon writing into a TFT is also present. To let this be closer to a real-use state, it is desirable that more than three scan line side common lines be employed in specific liquid crystal display devices of the so-called Cadd scheme with a capacitor for storage of electrical charge as written into a pixel electrode being formed in particular between the pixel electrode and scan signal line at the rear stage. Since with this technique the front stage pixel""s Cadd is formed on a scan signal line at the self stage and, further, the self stage pixel""s Cadd is formed on a scan signal line at the rear stage, any intended writing into pixels in a way equivalent to real use events is realized by scanning a pixel at the self stage and its front and rear pixels in a specified order of sequence similar to that during real use states. Additionally, in certain schemes that do not constitute Cadd such as for example Cstg scheme or else, writing equivalent to real use events is possible even when the scan line side common lines consist of mere two lines; however, in regard to the influence of voltage potentials due to capacitive coupling between pixels, the use of more than three scan line side common lines in a similar manner exhibits an effect for approximation to real in-use states.
Note here that in the case of three lines, at six pixels ABCDEF aligned in a direction along the image signal line extension direction, the polarities of respective pixels relative to a reference signal potential become xe2x80x9c+xe2x88x92++xe2x88x92+xe2x80x9d by way of example, resulting in occurrence of a problem that pixels C and D, for example, are the same in polarity as each other. To avoid this problem, it will be desirable that the scan line side common lines consist of an even number of lines. In view of the problem in the Cadd scheme, it is deemed most effective to arrange them while employing four lines as a minimal number in the Cadd scheme or using two or four lines in the Cstg scheme.
The present invention should not be limited to the above stated arrangements or arrangements of embodiments to be set forth later in the description and ideas as disclosed therein. A variety of modifications and alterations will be possible without departing from the true spirit and scope of the invention.
Several preferred embodiments of the instant invention will now be explained in detail with reference to the accompanying drawings below. Although the following embodiments will be set forth in conjunction with liquid crystal display devices of the so-called TN type, the same goes with basic configurations of portions of devices of the IPS (lateral electric field) scheme to which the invention is applied except that counter electrode lead lines are drawn out on the thin-film transistor substrate side.
In addition, in the explanation presented below also, signal lines are also called drain lines whereas scan lines are called gate lines.

Liquid crystal display device and manufacturing method thereof


Disclosed are various embodiments for detecting Signaling System 7 (SS7) redirection attacks by measuring call audio round trip times between phones. Such redirection attacks force calls to travel longer physical distances than usual, thereby causing longer end-to-end delay. Accordingly, various embodiments implement a distance bounding-inspired protocol that allows for securely characterizing the round trip time between two call endpoints. As a result, telephone users can reliably detect SS7 redirection attacks and protect the information contained in their calls.

Telephony systems represent the most ubiquitous and trusted communications infrastructure in the world. In both the developed and developing worlds, these networks offer reliable audio connections that allow their subscribers to chat with distant family members, perform important business transactions and even exchange highly sensitive information. Many sectors of the global economy, especially finance and infrastructure, rely on telephony systems as a critical fallback to ensure that high value transactions or significant changes to operation indeed originate from an authorized party.
The content of calls over telephone networks has been viewed as secure from most adversaries solely due to limited access to core networks. Only a small number of providers and governments have historically been able to manipulate the underlying Signaling System 7 (SS7) network. As such, SS7 was designed on a foundation of implicit trust—that is, anyone with access is authorized to make any request. This assumption is convenient, especially in a mobile context, where providers other than a users' home network may legitimately need to quickly redirect traffic to a roaming client. Such features could also be used to maliciously redirect traffic intended for a specific user, to ensure that its delivery path included a system controlled by an adversarial party interested in intercepting such traffic. Such SS7 redirection attacks were long assumed to be rare; however, deregulation in the 1990s and the increased diversity of access technologies to these networks have eliminated this assumption. The impact of these changes has been obvious. As recent media coverage demonstrates, SS7 redirection attacks have become increasingly common and are rumored to be a favorite means of eavesdropping by intelligence agencies.
While many are calling for SS7 to be "made secure", it is unlikely that this global infrastructure will be fundamentally redesigned and redeployed in the foreseeable future. As such, the most practical solution in the short and medium terms is the development of tools that allow end users to be made aware of when their calls are likely experiencing malicious redirection.

Detecting SS7 redirection attacks with audio-based distance bounding

University of Florida Research Foundation, Inc.


A fuel reformer which can improve fuel cost is provided. The fuel reformer 1 is formed by filling a granular catalytic material 10 provided with a metal oxide layer having an oxygen deficit tilting structure formed on the surface by shot peening in a process chamber 24 formed in a casing 20 having a fuel inlet 21 and an outlet 22.

1. Field of the Invention
The present invention relates to a fuel reformer for reforming fuel, and particularly to a fuel reformer which reforms and activates fuel supplied to a combustion chamber of an apparatus or equipment for obtaining power, heat generation, etc. by combustion of fuel such as a boiler, a heat treat furnace, a heating furnace, an internal combustion engine, a space heater, a drier and others (they are generally called as "combustion apparatus" in this specification).
2. Description of Related Art
Various measures for improvement of air pollution have been taken recently for preservation of global environment, and taking the auto industry as an example, various measures to reduce emissions have been promoted.
Particularly, in the case of a diesel-engine vehicle, its emission contains NOx which is said to cause health hazards such as respiratory disorders, bronchitis, lung cancer, etc. as well as particulate materials (PM) causing black smoke and hazardous materials such as carbon dioxide causing global warming. Among them, the PM causes not only asthma but its carcinogenicity has been pointed out recently. It is very important to reduce emission of PM in addition to reduction of NOx as a measure against air pollution.
Therefore, in the emission material control for a diesel vehicle in large cities by a government, PM was included in addition to NOx which is the conventional target materials for regulation, and for the type of vehicle, a diesel standard-sized car was also included in addition to large-sized cars such as trucks and buses. And the necessity to reduce emission of these hazardous materials has been increased.
To be concrete, in order to meet the criteria of the regulation for a diesel vehicle passing through a large city in the future, it will be necessary to replace a vehicle with one provided with a new diesel engine or to attach an apparatus for reducing the emission of the hazardous materials.
In order to cope with such a situation, various apparatuses have been developed for reducing the hazardous materials in the emission of an automobile. For example, there is known as an emission purifying apparatus a "diesel particulate filter (hereinafter referred to as "DPF") placed in the middle of an exhaust passage for the emission for absorbing and removing PM exhausted by a diesel engine.
This DPF consists of a collection of porous ceramic cells in the honeycomb structure for capturing PM exhausted from the diesel engine when it passes through the wall of the cell and burning it so that diffusion of PM into the air is restrained.
However, DPF has the following problems.
Though the DPF can effectively reduce PM, it can not reduce both PM and NOx since a technology to remove NOx at the same time has not been established.
A catalyst capable of reducing both PM and NOx has been developed, but it is indispensable for the catalyst to use an engine provided with a common rail (electronic controlled fuel injection device). And moreover, diesel oil with high sulfur level can not be used due to the sulfur which makes lowering of purifying capability unavoidable, and the life depends on the quality of the diesel oil, which constitutes a problem.
Also, it is necessary to develop the DPF in combination with the engine control technology to securely burn the PM and to reduce the emission. Therefore, the DPF to be attached to new cars should be developed jointly with diesel engine manufacturers. And the DPF for post-attachment should be designed for each model, and since an engine is a core part of an automobile and is therefore developed for each affiliation, transaction outside the affiliation is difficult, compatibility is poor and after-sale service has a problem.
In the meantime, an emission purifying apparatus with the purpose of removing NOx contained in the emission is disclosed such as those using NOx reduction catalyst for reducing and dissolving NOx. But there is a problem that a high temperature is needed to activate the catalyst or the necessity to add fuel in the emission as a reducing agent complicates the constitution of the device.
The methods for removing the hazardous materials reduce the emission of the hazardous materials emitted into the air by removing the hazardous materials in the emission and then exhausting them, but if the fuel consumption itself required for obtaining the same workload can be decreased, the emission of the hazardous materials can be relatively reduced.
In this way, such a method with the purpose of improving fuel efficiency by activating fuel to be supplied to a combustion apparatus, more particularly, an internal combustion engine, is proposed in the Japanese Unexamined Patent Publication No. 10-196496 that a catalyst in which a precious metal is adsorbed to a porous ceramic is made and this is inputted and immersed in fuel liquid, or a paint in which a catalyst powder is diffused is applied in a tank so as to improve combustion efficiency with that catalyst.
Also, a fuel reformer for carrying out the fuel activation using a photocatalyst is proposed (Japanese Unexamined Patent Publications Nos. 10-176615, 10-265783 and 2004-52601).
Among the prior arts, the method in Japanese Unexamined Patent Publication No. 10-196496 describes that "NOx or SOx can not be removed safely as long as air is burned" through the fuel activation (Lines 29 to 31 on the Left column in Page 6). In order to remove NOx or others, it is necessary to add an additive to the fuel itself or to add a device to clean the emission with a special cleaning liquid in the exhaust system, which makes the apparatus itself large. And it also has various practical problems such as the necessity of drastic reform of the fuel supply and exhaust systems in the internal combustion engine.
In addition, a fuel reservoir tank using a photocatalyst as a fuel reformer catalyst is proposed in Japanese Unexamined Patent Publication No. 10-176615, but this photocatalyst exerts photocatalytic effect in response to the ultraviolet ray. Thus, in order to obtain the photocatalytic effect in the reservoir tank into which the ultraviolet ray does not reach, it is necessary to provide a light source for irradiating the photocatalyst with the ultraviolet, which makes the constitution of the device complicated and large. Therefore, the fuel reservoir tank in Japanese Unexamined Patent Publication No. 10-176615 becomes a relatively large apparatus, which causes a problem to restrict its installation location such that it can not be mounted on a vehicle.
Also, a fuel reformer which can be mounted on a vehicle and uses a photocatalyst supported by a porous material of a pellet-state particle as a fuel reforming catalyst is disclosed (Japanese Unexamined Patent Publication No. 10-265783), but the photocatalyst used in this apparatus also needs ultraviolet irradiation, and it is necessary to provide a special light source for irradiating ultraviolet rays when installed in a fuel supply system of an automobile into which the ultraviolet rays do not reach, and also, regular maintenance is required for the light source. Moreover, when the porous materials are contained closely in a sealed container of the fuel reformer apparatus, the ultraviolet irradiated from the light source is blocked by other porous materials and does not reach the porous materials with a distance from the light source, and the photocatalytic effect can not be fully exerted.
On the other hand, when the number of porous materials contained in the sealed container is decreased to enable full irradiation of the ultraviolet rays, the fuel reforming performance is lowered and problems can happen that the porous materials collide with each other and crush due to vibration when the automobile is driving or that broken pieces generated by the crush clog the fuel filter.
In the meantime, in the fuel reformer in the Japanese Unexamined Patent Publication No. 2004-52601, a porous plate made of lath-state mesh or honeycomb structure on the surface of which a layer of a photocatalytic material is formed is arranged in a chamber of a casing through which the fuel passes, and the layer of the photocatalytic material formed on this porous plate is brought into contact with the fuel for reforming the fuel. The photocatalytic material for reforming the fuel is a metal oxide layer having a structure which exerts the photocatalytic performance in response even to electromagnetic waves (gamma ray, X-ray, visible ray, infrared ray and electromagnetic wave) with the wavelength longer than that of the ultraviolet ray and a bond with oxygen is gradually decreased as goes from the surface to the inside (called as "oxygen deficit tilting structure" in this specification), and even if the fuel reformer is made by containing it in a casing through which the ultraviolet ray does not pass and a light source for irradiating the ultraviolet ray is not provided in the casing, fuel reform can be performed.
However, in the fuel reformer in this publication, the porous plate on the surface of which a layer of metal oxide having the oxygen deficit tilting structure is formed as a catalytic material contained in the casing is included, but the fuel reforming efficiency has hit a peak in the fuel reformer with such a structure, and a fuel reformer with higher efficiency can not be realized.
As an example, in the fuel reformer described as a Test Example 1 in the above Publication, "600 pieces of titanium lath" were used instead of "38 pieces of titanium lath+18 pieces of ceramic honeycombs" used as the porous plate, which is the catalytic material, and the fuel consumption rate was measured with the other conditions made common, but despite the increase in the surface area of the porous plate of about 10 times, improvement of the fuel consumption rate more than the fuel consumption rate described in the Example 1 of the Publication could not be achieved.
The above purpose such as improvement of fuel cost or prevention of generation of hazardous materials is not a problem specific to an internal combustion engine such as the diesel engine but is a common problem for various combustion apparatuses for obtaining generation of power or heat by burning fuel.
Thus, the present invention has an object to provide a fuel reformer which can reform fuel with higher efficiency, supplied to the combustion apparatuses obtaining power or heat by burning fuel such as a boiler, a heat treat furnace, a heating furnace, an internal combustion engine, a space heater, a drier and others, while keeping the advantageous characteristics in the fuel reformer in Japanese Unexamined Patent Publication No. 2004-52601 that provision of a light source or the like for irradiating the ultraviolet ray is not needed and the constitution is relatively simple, light-weight and small-sized so that a target for application is not limited, and it is also an object of the present invention to provide a fuel reformer which can relatively reduce emissions of nitrogen oxide (NOx), particulate material (PM), carbon dioxide, etc. generated with operation of a combustion apparatus by further improving the fuel consumption rate of these combustion apparatuses so as to reduce the fuel quantity to be used.

Abstract: The fuel introduced into this fuel reformer 1 is activated by contact with the metal oxide layer 12 formed on the surface of said catalytic material 10 so that the fuel cost of the combustion apparatus to which the fuel is supplied is improved.


A method of obtaining the spectra of a product wherein the product is pas through a gas chromatograph in a stream of helium to separate the product into components, with the components then being passed through a spectrometer to obtain the spectra of the components. The components are chilled to a temperature below about minus 10 degrees Celsius and preferably below about minus 20 degrees Celsius to render the components stable and non-volatile.

1. Field of the Invention
This invention relates to methods for obtaining the spectra of products.
2. Prior Art
It is known to obtain the spectra of a product by passing the product in a stream of helium through a gas chromatograph to separate the components of the product and then passing the components in series and at an elevated temperature through a Fourier transforn infrared spectrometer to obtain the spectra of the components of the product. The components are heated to an elevated temperature during this process. The disadvantage of this process is that the spectra of volatile or unstable components cannot be obtained.

Method for obtaining the spectra of an unstable product

The United States of America as represented by the Secretary of the Army


A hot-stamping formed body has a predetermined chemical composition and a microstructure including, by area ratio, 90% to 100% of martensite and 0% to 10% of a remainder in the microstructure. In the microstructure, a region in which an average GAIQ value in a unit grain is 60,000 or more is 30 area % or more, and a number density of carbides having a circle equivalent diameter of 0.20 μm or more is 50/mm2 or less.

In recent years, vehicle collision safety standards are being tightened, and vehicle members are required to have improved collision performance. For an improvement in collision performance, there are a deformation suppressing member for maintaining the shape as a member without being deformed even when subjected to an impact, and an impact absorbing member for absorbing collision energy by bending deformation. The deformation suppressing member is required to have high strength (specifically, a tensile strength of 1,800 MPa or more) and excellent toughness. The impact absorbing member is required to have a certain degree of high strength (specifically, a tensile strength of 1,500 MPa or more) and excellent bendability.
Patent Document 1 discloses inventions relating to a steel sheet for hot pressing which contains 0.8% to 2.0% of Cr by mass %, has a carbon equivalent Ceq of 0.43% to 0.7%, and has a martensitic transformation start temperature (Ms point) of 415° C. or higher, a hot press-formed article, and a method of manufacturing the same. In Patent Document 1, it is disclosed that a hot press-formed article having excellent ductility and a tensile strength of 1,500 MPa or more is obtained by setting an average cooling rate from the start of press forming to the Ms point to 20° C./s or more to obtain a metallographic structure primarily containing martensite and thereafter setting an average cooling rate at a temperature lower the Ms point is 0.1 to 300° C./s to obtain a metallographic structure in which carbides are finely dispersed.
Patent Document 2 discloses a hot stamping member having a tensile strength of 1,800 MPa or more, in which a prior austenite grain size is controlled to 10 μm or less by performing cooling in a temperature range from an Ms point to 150° C. after hot pressing at an average cooling rate of 10 to 500° C./s, and furthermore, toughness is improved by auto-tempering of martensite.


Provided is an aqueous battery configured to use hydroxide ions (OH−) as carrier ions. The aqueous battery is an aqueous battery comprising a cathode layer, an anode layer and an aqueous liquid electrolyte, wherein the cathode layer contains, as a cathode active material, a graphite having a rhombohedral crystal structure; wherein the anode layer contains, as an anode active material, at least one selected from the group consisting of an elemental Zn, an elemental Cd, an elemental Fe, a Zn alloy, a Cd alloy, an Fe alloy, ZnO, Cd(OH)2, Fe(OH)2 and a hydrogen storage alloy; and wherein, as an electrolyte, at least one selected from the group consisting of KOH and NaOH is dissolved in the aqueous liquid electrolyte.

In recent years, with the rapid spread of IT and communication devices such as personal computers, camcorders and cellular phones, great importance has been attached to the development of batteries that is usable as the power source of such devices.
Patent Literature 1 discloses a dual-ion secondary battery which uses graphite in the cathode and which uses insertion and extraction reactions of TFSI anions (N(SO2CF3)2−) between the graphite layers.
Patent Literature 1: Japanese Patent Application Laid-Open No. 2019-029077
For reduction of battery production costs, there is a demand for the development of a novel aqueous battery configured to use hydroxide ions (OH−) as carrier ions.


A test apparatus for testing electronic devices, comprising a control section for generating control signals based on a test program set in advance to test the electronic devices, a plurality of test modules for generating test signals to be supplied to the electronic devices on the basis of the control signals, a device interface having connectors, provided in correspondence to the plurality of test modules, for supplying the test signals generated by corresponding test modules to predetermined pins of the electronic devices, wherein a test module for generating source power to be supplied to the electronic device outputs the source power only when it is connected with a connector set in advance among the plurality of connectors and does not output source power when it is not connected with the connector set in advance.

1. Field of the Invention
The present invention relates to a test apparatus for testing electronic devices and more specifically to a test apparatus that supplies signals generated by a plurality of test modules to the electronic devices.
2. Description of Related Art
Conventionally, as a configuration of a test apparatus for testing electronic devices such as semiconductor circuits, there has been known one comprising a device interface for mounting electronic devices, a plurality of test modules, connected with the electronic devices through an intermediary of the device interface, for generating input signals to be input to the electronic devices and a control section for supplying signals for controlling the test modules. The test modules are installed in slots provided between the device interface and the control section.
The plurality of test modules are provided per each function, e.g., a module for generating electricity of power source (referred to simply as source power hereinafter) to be supplied to the electronic devices, a module for generating pattern signals to be supplied to the electronic devices, and so on.
The device interface is provided with a plurality of connectors in correspondence to the plurality of test modules. Each connector connects the corresponding test module with a predetermined input pin of the electronic device.
In such a conventional test apparatus, each test module must be connected with the predetermined connector, respectively. When the test module for generating the source power is connected with a different connector in particular, there is a possibility that a large power is supplied to a pattern-input pin of the electronic device.
Although a test apparatus, in which disposition of the test modules is fixed, does not causes such problem, a test apparatus wherein disposition of the test modules may be changed has come to be developed lately. Accordingly, there is a possibility of erroneously disposing the test modules in the test apparatus having such a configuration, connecting the power module to the pattern input pin of the electronic device for example.


A method can include obtaining a physical commodity that is divided into one or more physical units. The method can further include storing the physical commodity in a secure vault. Additionally, a map can be utilized to subdivide each of the one or more physical units into a plurality of segments. Each of the plurality of segments can be tangible portions of the physical unit that are distinct and identifiable. Subdividing each of the one or more physical units can render the physical units unaltered. Further, the map can be utilized to assign ownership of the plurality of segments to one or more owner users. The method can additionally include receiving an instruction to transfer ownership of a particular segment of the plurality of segments from a particular owner user to a buying user, and assigning in the map ownership of the particular segment to the buying user.

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Physical commodities, such as precious metals, are mainly used for fabrication, for consumption, and as a store of value. In the present day, however, the historic functions of physical commodities as a medium of exchange and unit of measurement of the value of goods and services have become largely replaced by deposit currencies. Such deposit currencies have certain advantages over physical commodities, e.g., deposit currencies may be less prone to theft, easier to transport, and have a lower risk of forgery and/or debasement. Nonetheless, some investors choose to own physical commodities as a hedge against volatility in stock markets, since over time they have produced similar returns as major stock indices without being correlated with them, as well as for other reasons. Thus, there is a need for a system and method that reduces or eliminates the disadvantages, while maintaining the advantages, of trading and storing physical commodities.

System and method for trading distinct and identifiable portions of a physical commodity


The high speed data pathway system is used to convey data signals to integrated circuits connected to mother and daughter boards. The integrated circuits include a package and an integrated circuit chip carried by the package. An internal transmission line is carried by the package and coupled to the integrated circuit chip. The package includes both input and output connections for the internal transmission line. A high speed pathway is formed by serially connecting the internal transmission lines with external transmission lines to form a unified transmission medium. Advantageously, the internal transmission lines, external transmission lines and the connection between them have substantially corresponding characteristic impedances.

The present invention is directed to electrical data pathway structures for very high-speed digital data transfer. High-speed integrated circuits such as gallium arsenide digital memory chips, microprocessors and logic components and superconductive Josephson junction devices have access or processing cycle times of about one nanosecond or less. However, a significant limitation on the performance of data processing systems utilizing such high speed devices is the speed of the data pathway system which interconnects the components of the system. Conventional data pathway backplane systems such as typical motherboard-daughterboard data pathway circuit board interconnection systems do not function at speeds adequate to realize the full potential of high speed integrated circuits. Very high speed backplane data pathway systems operating at speeds up to and greater than 500 megahertz would be desirable for more fully realizing the potential processing speed of such systems. Moreover, fast gallium arsenide or other very high speed digital data processing devices are typically synchronized with a master clock, requiring transmission of a clock signal to each circuit component or subsystem which is required to operate synchronously with the other components. However, while high speed signal transmission may be readily accomplished from one transmitter to one or two single receivers, the provision of data bus taps for multiple receivers distributed along a signal line creates complex, cumulatively interactive impedance variations which impede digital signal transmission at high speeds. Typically at high signal rates, interference from multiple taps (which generally increases with the number of taps) is so pronounced that component system fan out is significantly limited (e.g., to two clock ports), thus requiring excessive buffering for interconnection of multiple components, increased component count and resulting cycle delays. Accordingly, in order to fully utilize the high processing speed capabilities of integrated circuits such as those made from high electron mobility III-V materials, there is a need for passive and active high speed integrated circuit interconnection systems which are capable of transmitting and/or receiving digital data electrically at high speed from single or multiple sources to one or more of multiple target receivers. In this regard, passive high-speed data transmission systems including various array processing architectures, redundant processing architectures and systems utilizing logic fanout to multiple receiver barrels would be desirable which can function at speeds up to 500 MHz or more. There is also a need for active, high speed integrated circuit interconnection systems capable of both transmitting and receiving information from multiple sources and targets at very high data transmission rates, such as 500 MHz to 2 Gigahertz or more. Such systems would facilitate highly concurrent (pipelined) data processing structures, allow "handshake" capability for enhanced system designs, facilitate high performance systems utilizing multiple processor boards in complex systems, and provide multiple memory board designs without creating excessively large bus structures.
Accordingly, it is an object of the present invention to provide very high-speed (e.g., 500 megabit per second to 2 or more gigabits per second data transmission rate per channel) data transmission pathways for multiple receivers which permit effective utilization of very fast integrated circuit components. It is a further object to provide both passive and active high speed data transmission systems for transmitting to multiple receivers along the data pathway. It is a further object to provide integrated circuit components which are particularly suited for use in high speed data pathway systems. These and other objects of the invention will be apparent from the following description and the accompanying drawings.


A fan blade has an airfoil main body extending between a leading edge and a trailing edge. The airfoil also has suction and pressure sides. A cavity is formed into said main body, and receives a filler material. A cover closes off the cavity, and is attached to the main body, with the cover having a thickness defined in a direction perpendicular to the suction side. The main body has a spar which extends along the cavity, with a thickness of the spar at a central location between ends of the cavity which has a second thickness. A ratio of the first thickness to the second thickness is between 0.5 and 2. A fan rotor and a gas turbine engine are also disclosed.

This application relates to a hollow fan blade for a gas turbine engine.
Gas turbine engines may be provided with a fan for delivering air to a compressor section. The fan also delivers bypass air into a bypass duct. From the compressor section, the air is compressed and delivered into a combustion section. The combustion section mixes fuel with the air and combusts the combination. Products of the combustion pass downstream over turbine rotors which are driven to rotate and in turn rotate the compressor and fan.
The fan may include a rotor having a plurality of blades.
One type of fan blade is a hollow fan blade having an internal cavity defined forwardly of a spar, which defines one side of the fan blade. Some filler material, such as a honeycomb filler, is received within the cavity, and a cover is placed over the honeycomb material, closing off the cavity. In the prior art, the cover was not structural, and was made to be much thinner than the thickness of the spar wall. In one example, the cover was one-sixth the thickness of the spar wall. Thus, the spar wall provided all structural integrity for the central areas of the fan blade. The blades are subject to a number of challenges, including internal stresses that vary along the length of the fan blade.
Recently, fans have been provided with a gear drive from a turbine. This has enabled a dramatic increase in the fan's diameter. With this enlarged fan blade, there are much greater structural challenges along the fan blade. In addition, the larger fan blade is more likely to be impacted by debris, or by bird strikes.


A multi-port semiconductor memory in which wrong read-out due to coupling noise is hardly generated and operation speed is fast is provided. When data are written in memory cells from a pair of bit lines for one port, NMOS transistors become on. Electrical potential only at a low-level side is pulled up between the pair of bit lines, because electrical potential at a high-level side is approximately equivalent to power potential. Accordingly, when one of adjacent bit lines is on high-level and the other is on low-level, potential difference is reduced by the pull-up, resulting in reduction of generating time of the coupling noise. Although read-out of data can not be performed while the coupling noise is being generated, since the concerned generating time is reduced in the invention, the operation speed is substantially fast.

1. Field of the Invention
The present invention relates to a multi-port semiconductor memory, or a semiconductor memory having multiple input and output ports.
2. Description of the Related Art
The multi-port semiconductor memory has been used for, for example, a register file for microprocessor or image memory for graphics. Each of the multiple ports of the multi-port semiconductor memory can perform write-in or read-out of data independently. That is, input and output of data through respective input and output ports are performed concurrently. Therefore, since waiting time for the input and output of data is reduced, processing capacity of the processor is improved as a whole. For example, in a microprocessor using a two-port semiconductor memory, two data can be loaded in one cycle.
As the literatures regarding the multi-port semiconductor memory, for example, JP-A-07-230692, JP-A-09-7373, and JP-A-11-261017 are known, of which the contents are incorporated herein by reference.
Typically, in the two-port semiconductor memory, one memory cell is connected to two sets of bit line pairs. For example, in the two-port semiconductor memory described in FIG. 3 in the above JP-A-09-7373, one memory cell 11 is connected to a bit line pair WBL, WBL/ and a bit line pair RBL, RBL/.
In such configured memory, coupling capacitance is produced between adjacent bit lines. For example, in the two-port semiconductor memory described in FIG. 3 in JP-A-9-7373, the coupling capacitance is produced between the bit lines WBL and RBL, in addition, the coupling capacitance is produced between the bit lines WBL/ and RBL/. The coupling capacitance is a cause of coupling noise. For example, if electrical potential of the bit line RBL is changed from high-level to low-level while the bit line WBL is being on high level, electrical potential of the bit line WBL is temporarily dropped. If the electrical potential of the bit line WBL is read out while the coupling noise is being generated, the read-out data value may be wrong.
The coupling noise disappears after a certain period of time has passed since the noise was generated. Therefore, if it is determined that the electrical potential of one of the bit line pairs must not be read out before the predetermined time has passed since the electrical potential of the other of the bit line pairs was changed, the wrong read-out can be prevented. That is, influence of the coupling noise can be eliminated by staggering the read-out timing from the write-in timing.
Here, when the coupling capacitance is small, since generating time of the coupling noise is short, the wrong read-out can be prevented only by staggering the read-out from the write-in for a short time. On the other hand, when the coupling capacitance is large, the generating time of the coupling noise is long, therefore the read-out time of the two-port semiconductor memory is substantially lengthened. Today, distance among the bit lines is apt to be shortened with progress of fining of an integrated circuit, furthermore, bit line length is apt to be elongated according to increase of memory capacity. Each of them is a factor for increasing the coupling capacitance, or factor for lengthening the generating time of the coupling noise. Therefore, the read-out time becomes substantially longer as the fining of memory and increase of the memory capacity are progressed.
The subject of the invention is to provide a multi-port semiconductor memory in which the wrong read-out due to the coupling noise is hardly generated and operation speed is substantially fast.


A problem to be resolved by the invention resides in providing a multifunction analyzing apparatus for detecting a shape with high resolution and physical property information capable of not only successively reading a base arrangement from end to end but also specifying a position hybridized by known RNA with regard to a single piece of DNA elongated in one direction on a board. A microscope system of the invention is provided with a fluorescence microscope, a scanning near field microscope and a scanning probe microscope as a detecting system, the microscopes are fixed to a switching mechanism and can be moved to a position at which the various microscopes can observe the same portion of a sample by switching operation of the mechanism. The microscope system of the invention is provided with a function capable of directly detecting a shape and physical property information of one piece of DNA by the scanning probe microscope by multifunction scanning.

1. Field of the Invention
The present invention relates to a scanning probe microscope suitable for observing a sample of a long body elongated to be long on a board, particularly relates to a scanning probe microscope (SPM) technology capable of reading information of a single piece of DNA without modification.
2. Description of Related Art
In present age, DNA arrangement analysis becomes a technology which is extremely important in biological researches and medical diagnoses. DNA forms two pieces of chains in a spiral shape based on base pairs of A-T, G-C, and when heated, two pieces of chains are disentangled to constitute one piece chain. The basis of DNA arrangement analysis is constituted by retaining a state of the single piece of chain by rapidly cooling the single piece chain DNA and successively reading information inscribed to the single piece chain DNA.
Further, it is known that when the single piece chain DNA which has been constituted by being heated is gradually cooled, an original pair of the single piece chains DNA is combined to recover to the two pieces chain DNA. The phenomenon is referred to as hybridization and the term is used also for the phenomenon in which ribonucleic acid (RNA) having gene information is combined with a single piece of chain DNA at pairing arrangement positions. Medical or biological diagnoses are carried out by inspecting whether RNA to which attention is paid differs in a standard position with regard to DNA a standard arrangement of which has already been known.
Now, although in such analysis, it is requested to read DNA information from an end thereof, at present, there has not been developed a technology of forming a sample in a state in which a single piece of long DNA is elongated from end to end and successively reading information inscribed thereto from the end. In a DNA sequencer of the related art, information of single piece chain DNA is provided by an enormously troublesome operation of cutting two pieces of chains of DNA constituting a chromosome to a specific length hierarchically by using a restriction enzyme, modifying a fluorescent substance at an end thereof, reading information of individual cut DNA, ascribing DNA which has been continuous in an original single piece chain from information of the end portion, and resynthesizing hierarchical cutting. Although the operation has been carried out by a large-scaled computer, enormous time is taken and further, resynthesis is frequently failed.
Under such a situation, Patent Reference 1 has been provided with an object of providing a gene arrangement reading apparatus capable of directly reading respective code arrangement of four bases of A (adenine), C (cytosine) , G (guanine), or U (uracil) or T (thymine) of a single piece chain of RNA or DNA. According to the technology, in order to detect a specific one base of A, C, G or U or T, by bonding a base having gene information to a tip portion of a metal stylus via an adhesive binder of nanometer order having a strong bonding affinity with an organic function group such as a carbon nanotube at the tip portion of the metal stylus of a scanning probe microscope (SPM), an attraction force produced by a hydrogen bond utilizing complimentarity particular to the base is detected.
Although Patent Reference 1 explains that base arrangement information can be read by the above-described constitution with regard to the hierarchically cut DNA, an explanation has not been given of how riobonucleic acid constituting a sample is linearly fixed onto a board such that the stylus (hereinafter, described as probe for simplification) of the scanning microscope can trace, further, of a method of firmly tracking the elongated single piece chain of RNA or DNA by a probe.
The inventors have started to develop a general apparatus of detecting a number of kinds of information with regard to an elongated single piece DNA in view of establishing a prospect of a pretreatment technology of a sample in which long DNA is fixed in a state of being elongated in one direction by a method of constituting a single piece chain DNA which is normally in a state of two pieces of chains in an aqueous solution, hybridizing the single piece DNA by known RNA, DNA or polypeptide nucleic acid (PNA), labeling by fluorescence or metal colloid, and thereafter temporarily sinking and pulling up a board by traversing a gas/liquid interface of the aqueous solution of DNA.
[Patent Reference 1] JP-A-2002-350435 "Apparatus of reading gene arrangement", publication date: Dec. 4, 2002

Probe microscope system suitable for observing sample of long body


The invention relates to a sensor (1) for detecting environmental parameters, comprising a transmission device (3) by means of which an output signal of the sensor (1) can be emitted, and a correction device (4) by means of which the sensor measurement value can be corrected for the emission of a correct output signal, which sensor is to be easy to produce, and wherein only a small output is to be required for a method for calibrating a sensor of this type. According to the invention, the sensor is calibrated by means of the correction device thereof, on the basis of cloud-based data.

Sensors of this kind for detecting environmental parameters have been commonplace for some time and are used for a large variety of purposes. The aim is to produce sensors of this kind for detecting environmental parameters at the lowest possible economic cost, wherein reliable functionality of these sensors should be guaranteed over the longest possible period of use.
Due to cost considerations, low-price sensor elements, for example moisture sensors, temperature sensors, etc., are used in low-cost sensors. These usually have an inadequate or low level of accuracy.
Calibration is performed in order to increase the accuracy of the sensor that usually includes a sensor element, signal processing and an interface. The adjustment values in this case are determined and stored individually for each sensor. Using the stored adjustment values, the sensor measurement of the sensor can be adjusted in such a manner that the output signal emitted by the sensor has a greater accuracy and therefore quality.
The problem in this case is that methods for calibration known from the state of the art are associated with substantial effort and expense. Particularly among users of these sensors, there is no, or only low, acceptance of routine calibration of the sensors.
In this case, the degradation of sensors of this kind over their service life is, in particular, fraught with problems, since in the absence of accurate and expensive calibration devices and methods known from the state of the art, the quality of measurements taken by such sensors deteriorates considerably as the period of use increases. Reasons for the degradation of sensors of this kind include, for example, dirt and contamination of the actual sensor elements of such sensors.

Sensor for detecting environmental parameters and method of calibrating the sensor


An optical information recording-reproducing system is provided using a laser diode with independent pulsating emission for recording and/or reproducing information, with the laser pulse period T (sec) and the distance L (m) between the semiconductor laser and information recording medium being set to meet the inequality: EQU (n-1).times.0.8.times.c/2L<i/T<n.times.0.7.times.c/2L. where c is the velocity of light, and n is a natural number. By virtue of this arrangement, the relative noise intensity inherent to the optical feedback from the information recording medium is reduced below 10.sup.-3 Hz.sup.-1.

The present invention relates to an optical information recording and reproducing system using a semiconductor laser as a light source for recording and/or reproducing information on the information recording medium.
There have been used, as a semiconductor laser source with less noises inherent to the optical feedback, a semiconductor laser with the superimposition of a high-frequency current of 500-1000 MHz and a semiconductor laser (a laser diode with independent pulsating emission) which operates at 1 GHz or higher on a direct current basis. In order to further reduce noises inherent to the optical feedback, the overall system using the semiconductor laser must be constructed suitably. It is known that a system using a semiconductor laser with the superimposition of a high-frequency current has its noise level increasing or decreasing depending on the high-frequency current superimposed and the arrangement of the optical system (JP-A-59-210541, JP-A-60-101735). In contrast, it is not yet clear how to construct the system suitably for reducing the optical feedback noise in the case of the laser diode with independent pulsating emission.

System having a function of reproducing optical information


A charge pump circuit includes a test mode control unit for generating a plurality of control signals according to a test mode enable signal and an input signal and fixing one of the plurality of the control signals depending upon whether a fuse has been cut or not, a ring oscillator for outputting an output frequency of which varies according to an output of the test mode control unit, and a charge pump for generating a high voltage, which is higher than an external voltage, according to an output of the ring oscillator.

1. Field of the Invention
The present invention relates to a charge pump circuit, and more specifically, to a charge pump circuit which can freely control the speed of a charge pump.
2. Discussion of Related Art
A high voltage pulse that is higher than an external power supply Vcc has been widely used in DRAM circuits since it can compensate for the loss of threshold voltage of transistors. More particularly, circuits which employ the high voltage pulse include a word line driver circuit, a bit line separation circuit, a data output buffer and the like
This high voltage pulse is generated by means of a VPP circuit. Load of the Vpp circuit is usually composed of a capacitor component. Two kinds of current flow in the load of the Vpp circuit. One of the current is a minute inverse bias leakage current that always flows through a PN junction, and the other of the current is a high excessive current for driving internal circuits whenever a chip is activated. Accordingly, the VPP level can be constantly maintained only when such charge loss is compensated for.
In the prior art, if such variation in the level occurs, charge pump circuits are driven by detecting lowering in the level and charges are pumped into the capacitor, so that a lower VPP level returns to its original value. In this case, however, there is a disadvantage in that it is not easy to control the pumping speed even when more rapid return of the level is needed. In order to make the pumping speed fast, the cycle of a ring oscillator within a charge pump circuit has to be made fast. For this, after a FIB (Focused Ion Beam) work is performed on options, a test has to be performed. A mask re-work is needed according to the test result. Thus, there is problem in that lots of time and cost is consumed.

This patent is subject to a terminal disclaimer.


A hospital privacy gown is provided, which consists of a body garment having a front portion, a vertically split rear portion divided into two segments, a pair of sleeves and a neck opening, so that the body garment can be worn by a patient. A fastener is for retaining the two segments of the vertically split rear portion together at the neck opening. A structure is for covering up a lower separation of the two segments of the vertically split rear portion of the body garment. A component is for securing in an adjustable manner, the covering up structure at a waist location of the body garment to properly cover the body of the patient for personal modesty and be quickly opened for examination and access thereto.

1. Field of the Invention The instant invention relates generally to medical garments and more specifically it relates to a hospital privacy gown.
2. Description of the Prior Art
Numerous medical garments have been provided in prior art that are adapted to be worn by patients for hospital, surgery and examination purposes. While these units may be suitable for the particular purpose to which they address, they would not be as suitable for the purposes of the present invention as heretofore described.


A method  An apparatus and system for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (Hsnyc)  (Hsync) that controls a line scan rate, and a vertical synchronizing signal (Vsnyc)  (Vsync) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated. The actual width W is compared with the expected width E. When E does not equal W, at least one of a frequency component and a phase component of the pixel clock signal is adjusted until E equals W.

Presentations using multimedia projection display systems have become popular for purposes such as sales demonstrations, business meetings, and classroom sessions. In a common mode of operation, multimedia projection display systems receive analog video signals from a personal computer (PC). The video signals represent still, partial-, or full-motion display images of the type rendered by the PC. The analog video signals are converted into digital video signals to control a digitally-driven display object, such as a transmissive liquid crystal display (LCD), to form the display images for projection onto a display screen.
Two common types of multimedia projection display systems are LCD projectors and LCD projection panels. An LCD projector includes a transmissive LCD, a light source, and projection optics to form ad  and project display images in the manner describes  described above. An LCD projection panel includes a similar transmissive LCD to form the display image, but operates with a conventional overhead projector (OHP) having a light source and projection optics, to project the display image onto a display screen. Examples of such LCD projectors and LCD projection panels are sold under the respective trademarks LITEPRO and PANELBOOK by In Focus Systems, Inc. of Wilsonville, Ore., the assignee of the present application.
One desirable feature for multimedia display systems is compatibility with the various analog video signal modes generated by various PC's. These modes generally range from 640×480 to 1600×1200 resolutions provided at image refresh rates of 60 to 100 Hz. The resolution expresses the number of horizontal and vertical pixel elements that can be turned on and off. Given the variety of resolution modes, multimedia display systems include an interface that converts analog video signals of various modes to digital video signals capable of controlling the LCD.
In general, analog video signals comprise an analog image data signal for each of the primary colors red, green and blue, and digital timing signals, which may include a pulsed horizontal synchronizing signal (Hsync) and a pulsed vertical synchronizing signal (Vsync), or a composite sync signal. The individual analog color signals are generated from bit data in a memory portion of the PC, using three digital-to-analog (D/A) converters, one for each of red, green and blue. FIG. 1a shows an exemplary analog signal waveform 1, with plateau regions (pixel data components) 2 that correspond to the color level of individual pixels of the image display. Consecutive pixel data components 2 are connected by signal transition regions 3. The digital timing signal controls the raster-scanning of the analog video data signals across the monitor screen. The Hsync pulse controls the horizontal raster scan rate, and the Vsync pulse controls the image (or frame) refresh rate. In the case of a composite sync signal, a conventional sync separator is first used to obtain the horizontal and refresh signals.
As shown in FIG. 1d, each video frame 9 is usually produced to have a central active video region 11 surrounded by an inactive ("blanked") margin 13. The resolution refers to only the pixels in the active video region.
Because the LCD used in multimedia display systems require  requires digital video signals, either the LCD or the system normally has an analog to digital (A/D) signal converter for converting the PC-generated analog video signals into a digital format suitable for driving the LCD. The A/D signal converter is usually combined with a phase-locked loop (PLL), which may comprise a phase comparator, a low-pass loop filter, and a voltage-controlled oscillator (VCO) formed in a loop to generate a feedback signal that locks into Hsync. In order to generate a selected multiple n of clock pulses for each period of Hsync, a divide-by-n counter is added to the feedback loop between the VCO output and the phase comparator.
An example of a pixel clock waveform 4 is shown in FIG. 1a. The number n of individual pixel pulses per Hsync pulse may be set by reference to the resolution mode of the analog video source. To set the resolution mode, certain characteristics of the analog video signal, such as Hsync and Vsync, may be used to refer to a mode look-up table stored in the display system CPU. The number n should be set to equal the number of pixel data components in each horizontal line of the scanned analog signal, including those active video data region 11 and the blanked margin regions 13 (see FIG. 1d) on either side of the active region. For example, for a screen resolution of 640×480, n may be set at about 800 to include the blanked regions on either side of the 640 pixel-wide active video data region. Thus, the pixel clock would sample the continuous stream of / image data 800 times along each horizontal line of the frame.
FIG. 1a shows the desired relationship between the analog video data signal 1 and the pixel clock signal 4. The number n of pixel clocks 5 is set to establish a one-to-one relationship between pixel clock pulses 5 and pixel data components 2 of the / data signal 1. This one-to-one relationship requires that the pixel clock signal frequency be equal to the analog video data signal frequency. Under this relationship, each pixel data component 2 of the analog signal is sampled by a single pixel clock pulse 5, which reads the instantaneous voltage value of the pixel data component so that it can be digitized. Since the pixel clock pulses 5 have "jitter" zones 6 at their leading and trailing edges, the clock pulses 5 should be registered with the centers of the pixel data components 2, so that the sampling is not randomly pushed by the jitter into the transition regions 3 of the analog video signal.
The stream of digitized values form  forms the digital video data signal, which is addressed to the LCD to appropriately set LCD pixels at blank (black) or selected activated (non-black) status to replicate the image defined by the analog video signal.
Unfortunately, such A/D conversion is often imperfect due to errors in the pixel clock sampling of the analog signal. Such sampling imprecision gives rise to frequency (also know as "tracking") and "phase" errors, both of which may degrade the quality of the LCD image.
Referring to the analog video signal 1 and pixel clock signal 4′ in FIG. 1b, tracking error results from the number n of pixel clocks being improperly set. As discussed above, the number n of pixel clocks should be equal to the number of pixel data components 2 of each horizontal line of analog video data signal. In FIG. 1b, the improper setting of n results in the pixel data components 2 not being sampled at a consistent point. For instance, n is set too large in clock signal 4′ (i.e. the clock signal frequency is too high). The resulting crowding of the pixel clock pulses 5′ yields an additive leftward drift of the pixel clock pulses 5′ relative to the pixel data components 2 of the analog video data signal 1. Such drift causes sampling in the transition regions 3. For instance, as indicated by positional bracket A, the leading edges 7′ of the third through the sixth clock pulses 5′ sample in transition zones 3 of the analog video signal 1. Accordingly, the transition zone data will be erroneous and the image information from adjacent non-sampled pixel data components 2 will be missing from the digitized video signal. If n is erroneously set large enough, the pixel clock pulses may be so crowed   crowded that individual analog pixel data components 2 may be double-sampled. On the other hand, if n is set too small (i.e. the pixel clock signal frequency is too low), the dispersion of the pixel clock pulses results in a rightward drift wherein sampling may also occur in the transition regions. In all of these cases, the erroneous sampling provides erroneous video signal data that may degrade the LCD image quality.
Phase error may occur even if the pixel clock signal frequency equals the analog video data signal frequency. As shown in pixel clock signal 4′ in FIG. 1c, the clock phase may be erroneously set such that every pixel clock pulse samples a transition region 3 of the analog video data signal. Leading edge jitter makes such phase error more likely, since if the jitter zones straddle the intersections 8 of the pixel data components 2 and transition regions 3 of the analog video data signal 1, the voltage will be randomly sampled on either side of the intersection 8. In any case, phase error is undesirable in generating undesirable noise, or "snow" in the LCD video image.
In order to eliminate tracking and phase errors in existing projection systems, manual controls are provided on projection systems which permit an operator to adjust the number n of clocks 5 and the phase of the pixel clock waveform. These controls are adjusted until the projected image appears satisfactory to the eye of the system operator. While such manual error control is usually effective in achieving an acceptable image quality, such manual control is time-consuming and inhibits the user-friendliness of the projection system.
Thus, in light of these disadvantages, it is a principle  principal object of the present invention to provide an apparatus and a method for producing a digital video signal from a  an analog video signal that automatically corrects phase and tracking errors.
It is another object of the present invention to provide such automatic phase and tracking error correction for a wide range of analog video signal resolution modes.
It is another object of the present invention to provide an apparatus and a method for producing a digital video signal from a  an analog video signal that automatically corrects the horizontal position of a video image on the display object.
In accordance with a preferred method of the present invention, a digital video signal is produced from an analog video signal which includes an analog video data signal that is operable to be raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (Hsync) that controls a line scan rate, and a vertical synchronizing signal (Vsync) that controls a frame refresh rate, to produce consecutive frames of video information. The digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the active image width of the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the actual video image producible by the analog video signal is calculated. The actual width W is compared with the expected width E. When E does not equal W, at least one of a frequency component and a phase component of the pixel clock signal is adjusted until E equals W.

Method and apparatus for automatic pixel clock phase and frequency correction in analog to digital video signal conversion