A system for diagnosing electronic control systems mounted in a motor vehicle has a signal receiver for receiving a data demand signal from a diagnosis device, an interpreter for interpreting a content of the received data demand signal and a signal transmitter for transmitting an output signal to the diagnosis device in accordance with the interpretation. A signal receiving line connects all of the signal receivers with each other in parallel, and a signal transmitting line connects all of the signal transmitters with each other in parallel. The signal receiving line and signal transmitting line are connected with the diagnosis device by a connector.

The present invention relates to a diagnosis system for a motor vehicle.
Recently, a motor vehicle was equipped with an electronic control system for controlling various components of an engine, such as fuel injectors, thereby improving driveability, exhaust gas emission, fuel consumption and engine power. The electronic control system controls the components based on information represented by output signals from various sensors for detecting engine operating conditions. Accordingly, if malfunctioning of the components and sensors occur, the engine does not properly operate.
However, because of complexity of the electronic control system, it is difficult to immediately recognize the trouble. Accordingly, a trouble diagnosis device for easily checking the electronic control system should be equipped in an auto shop. The electronic control system has a memory and a communication system to be connected to the trouble diagnosis device.
Japanese Utility Model Application Laid-Open 60-25974 discloses a diagnosis system in which a plurality of connectors are provided between various sensors and control circuits or between various actuators and control circuits. A plurality of decision circuits, holding means and displays are connected to the connectors for detecting an abnormality of the system. Since a plurality of connectors, decision circuits holding means and displays are provided, the system becomes complicated in structure.
Recently, a diagnosis system has been proposed, in which a bidirectional communication system is provided between the electronic control system and the trouble diagnosis device, thereby diagnosing data based on output signals from various sensors and control data for various actuators in the control system through a single diagnosis device.
However, in a motor vehicle, a plurality of electronic control systems for the engine, transmission, brake and cruise are provided. In order to diagnose trouble in these control systems, connectors for respective control systems must be connected to a connector of the diagnosis device, which is troublesome work. When a plurality of control systems are in trouble at one time, it is difficult to diagnose those troubles and it takes time to determine the trouble.


A computer-based method for analyzing the incentives and predicting the future actions of agents is described. The method includes storing, in a computer memory, data relating to previously observed behavior of at least one of an agent of interest and agents that can be assumed to hold similar utilities to the agent of interest, thereby defining an agent class, deriving with a processing device and based on the stored data, a set of unique incentives that agents in the agent class would have to hold for their observed behavior to be considered rational by an observer of the behavior, observing a short sequence of behavior of the agent of interest, inputting the observed behavior sequence to an analyzer, deriving specific goals of the agent driving that behavior instance, and predicting future actions of the agent of interest based on a maximization of reward for the agent of interest and the derived goals, the reward based on the derived incentives.

The field of the disclosure relates generally to surveillance data analysis, and more specifically, to methods and systems for estimating subject intent from surveillance.
Analysis of surveillance data is a major bottleneck in improving the situational awareness in security applications. Such security applications can be considered to range from public space surveillance to war theatre surveillance operations. Specifically, there is an abundance of video data available to consumers of such data, many times more than there are available man-hours to watch such video data. Automating analysis tasks is therefore a highly desirable goal. Among the tasks of an intelligence analyst is the estimation of what an observable agent (a person, or, by extension, a vehicle) intends to do, based on its previous behavior. Such observation is typically from video. While the above appears to be directed to a military intelligence context, other related contexts are contemplated.
The above described problem in the automating of the analysis tasks is challenging because the space of possible utility functions is very large. The essence of a successful application of an automated analysis method lies in devising a-priori value function representations that enable a compact representation of the large function space so that the computations become tractable.
The problem can be cast in terms of utility determination. One related approach is termed "Inverse Reinforcement Learning" in machine learning and artificial intelligence literature. Rather, work in Inverse Reinforcement Learning work typically has the goal of repeating a behavior shown in a set of examples typically performed by a person.

Methods and systems for estimating subject intent from surveillance


A seat integrated seat belt system. A three point seat belt system includes a belt having one end affixed to the seat and an opposite end mounted to a retractor secured to the seat. A seat belt tongue is mounted to the belt intermediate the belt ends and is releasably lockable with a belt buckle on the opposite side of the seat thereby pulling one portion of the belt across the passenger lap and another portion of the belt across the passenger upper torso. The belt extends through a guide located at the top of the seat. A seat tether includes a second belt having one end attached to the seat at the location of the guide and a second end mounted to a second retractor located beneath the seat. The second retractor is operable to limit motion of the seat thereby minimizing the impact of vehicle motion on the first belt securing the passenger to the seat.

1. Field of the Invention
This invention is in the field of seat belt systems.
2. Description of the Prior Art
Seat belt systems are available combining a lap belt and upper torso belt. Typically, a single belt having its opposite ends mounted to a pair of retractors has a seat belt tongue mounted to the belt intermediate the belt ends. The tongue may then be swung across the person and engaged with a buckle affixed to the seat thereby positioning one portion of the belt across the lap and another portion of the belt across the upper torso. Instead of mounting both ends of the belt to a pair of retractors, some systems have only one end of the belt mounted to a retractor whereas the opposite end of the belt is affixed to the vehicle.
Rough riding equipment, such as trucks, provide special problems in relationship to seat belt systems. Slack inducing mechanisms are typically required to isolate the driver from belt pressure created by retractor lock up. Certain slack inducing mechanisms do not automatically provide for constant belt tensioning and constant belt pressure applied to the driver. The system disclosed herein reduces or eliminates the discomfort from belt pressure and cinching without the use of slack inducing mechanisms.
It has been the prior approach to increase the strength of the vehicle floor and seat in order to reduce the motion between the seat and vehicle which occurs during a crash. Such modifications are costly and require more expensive seats. Disclosed herein is a tether system which minimizes such relative motion while allowing for use of relatively inexpensive seats and elimination of any additional strengthening or rigidizing of the vehicle floor.


An infrared imaging system (10) includes a catheter (11). The catheter is inserted into a small passageway, such as a blood vein (23), in order to collect infrared information from the vein. The information is refracted by at least one lens (32, 46, 52, 57, 63) in a collecting section (17, 45, 56, 61) of the catheter, and is imaged onto the ends (38) of an array of optical fibers (34). The fibers transmit the information to a relay lens (42), which images the information onto respective detector elements of an infrared detector (12). The infrared detector converts the information received from the relay lens into electrical information, which is transmitted to a circuit (13). The circuit generates electrical data that is transmitted to a display (16), which displays a visible image based on the infrared radiation emitted by the scene.

This invention relates in general to infrared imaging and, more particularly, to infrared imaging in a passageway.
Thermal imaging has developed rapidly over the past several years. Obtaining information based on temperature differences has proven to be an effective and accurate way to gather information in certain applications. Thermal imaging systems generally include a collecting component, an infrared detector, a circuit, and a display. The collecting component images infrared radiation onto the infrared detector. The infrared detector then generates electrical information that is sent to the circuit. The circuit converts the electrical information into electrical data which is displayed on the display. Thus, the display shows a visible image which represents the infrared radiation collected by the collecting component. These thermal imaging systems have been generally adequate for their intended purposes, but have not been satisfactory in all respects.
A problem with current thermal imaging systems is that they are too large to be used to gather information within the interior of small passageways. In the area of medicine, such passageways include a blood vein or artery. For example, in diagnosing potential heart problems, early detection of weaknesses or blockages of blood veins or arteries is critical. One cause of heart attacks is the presence of lesions within blood veins. The lesions can become inflamed and erupt, introducing debris into the veins which can trigger a heart attack, even when the blockage within veins and arteries is low. When inflamed, the lesions have a higher temperature than surrounding portions of the interior surface of the blood veins, and could thus theoretically be detected by infrared imaging techniques. However, as noted above, existing infrared imaging equipment is too large to be used within a passageway as small as a blood vein.
There are also industrial applications in which thermal imaging within a very small space is of interest, for example for inspection of certain types of equipment. Again, existing infrared imaging systems are too big to be inserted into such small spaces.
A further consideration is that prior systems used an infrared detector that had to be cooled, and the presence of a cooling mechanism makes the overall system relatively expensive.
From the foregoing, it may be appreciated that a need has arisen for a method and apparatus for infrared imaging in places such as a small passageway. According to the present invention, a method and apparatus are provided to address this need, and involve: transmitting infrared image information through an elongate optical portion from a first end thereof to a second end thereof; collecting infrared image information and supplying it to the first end of the optical portion; and receiving infrared information at a section which includes an infrared image detector and which directs infrared image information from the second end of the optical portion onto the image detector.

Method and apparatus for infrared imaging in small passageways


A spacecraft system and method includes a platform with a dock and an umbilical payout device. A robot is connected to an umbilical paid out by the umbilical payout device and is repeatedly deployable from the dock. The robot includes one or more imagers, an inertial measurement unit, and a plurality of thrusters. A command module receives image data from the one or more robot imagers and orientation data from the inertial measurement unit. An object recognition module is configured to recognize one or more objects from the received image data. The command module determines the robot's orientation with respect to an object and issues thruster control commands to control movement of the robot based on the robot's orientation. The combination of the space platform and robot on umbilical line can be used for towing another object to different orbital location, inspection including self-inspection of the robot carrying platform and for robotic servicing.

Various proposals have attempted to address the space debris problem. See published U.S. Patent Application Nos. 2012/0286098; 2012/0286100; and 2012/0175466 and U.S. Pat. No. 5,421,540 all incorporated herein by this reference. In U.S. Pat. No. 7,207,525, incorporated herein by this reference, a free-flying grasper unit is tethered to an orbital platform (e.g., a satellite) and used to grasp a target object. The grasper unit includes cameras which transmit images back to a ground control station with a human operator. The human operator then transmits control commands to the grasper unit via the orbital platform.
Problems with such a proposal include the fact that communication delays and/or interruptions between the ground control station and the orbital platform might result in a grasper unit failing to grasp a target object and/or striking the target object damaging it and/or its components, possibly causing additional space debris, or damaging the grasper unit and/or the orbital platform. If the object to be grasped is an expensive satellite, the satellite could be damaged.

Spacecraft system for debris disposal and other operations and methods pertaining to the same


An ultrasound imaging system and method includes acquiring ultrasound image data while moving an ultrasound probe, automatically identifying a plurality of segments of interest in the ultrasound image data, automatically applying temporal scaling to at least one of the plurality of segments of interest, and displaying the ultrasound image data as a panoramic view comprising a plurality of videos, where each of the plurality of videos is based on a different one of the plurality of the segments of interest, and where, based on the temporal scaling, each of the plurality of videos in the panoramic view takes the same amount of time to play.

Ultrasound imaging is an imaging modality capable of acquiring ultrasound image data that may be viewed in real-time or stored and reviewed at times subsequent to the acquisition. Ultrasound imaging systems also have the ability to acquire and store one or more videos, each including a plurality of image frames acquired at different points in time. Displaying ultrasound image data as videos allows the clinician to see how a person's anatomy changes over time. The size of the field-of-view (FOV) of an ultrasound probe used with the ultrasound imaging system dictates the maximum area or the maximum volume that may be acquired in a single frame of ultrasound data. A clinician operating the ultrasound imaging system may miss one or more items of interest during an ultrasound examination due to the size of the FOV, especially when trying to examine large organs or large regions of the person's body.
In order to minimize the likelihood of missing one or more items of interest in the ultrasound image data, particularly when imaging organs that are relatively large in comparison to the FOV, some conventional ultrasound imaging system are configured to generate panoramic views. A panoramic view may be generated from multiple ultrasound images acquired at different spatial locations. The ultrasound images may be combined or stitched together in order to provide a single panoramic view that covers a larger area or volume than would be possible with a single ultrasound image due to constraints imposed by the size of the FOV.
The ultrasound images used to generate a panoramic view may either be still frames, each representing a person's anatomy at a single point in time, or each of the ultrasound images in the panoramic view may be a video. For embodiments where each of the ultrasound images in the panoramic view is a video, there are challenges to displaying the videos in a way that is easy to interpret for the clinician. Since each of the individual videos was acquired at a different time, various patient vitals, such as heartrate or respiratory rate may be different between the various videos. It is known to temporally synchronize the individual videos based on a parameter such as respiratory rate or heartrate. However, this does not address a fundamental issue when displaying ultrasound images as videos in a panoramic view. Each of the videos may be displayed as a repeating loop so that it plays continuously. This means that each of the videos may have a different period. When a plurality of different video loops, each with a different period, are combined into a panoramic view and played at the same time, the result can be visually confusing for the clinician. The mismatch between the various video loops can be distracting for the clinician. The visual changes due to the mismatch between video lengths may attract the clinician's attention, making it harder to identify clinically important features in the videos. As such, there is a need for an improved ultrasound imaging system and method of ultrasound imaging where the videos in the panoramic view are automatically temporally scaled so that all of them take the same amount of time to play.


A fast recovery diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. A p-doped anode layer is arranged on the anode side. The anode layer has a doping profile and includes at least two sublayers. A first one of the sublayers has a first maximum doping concentration, which is between 2*1016 cm−3 and 2*1017 cm−3 and which is higher than the maximum doping concentration of any other sublayer. A last one of the sublayers has a last sublayer depth, which is larger than any other sublayer depth. The last sublayer depth is between 90 to 120 μm. The doping profile of the anode layer declines such that a doping concentration in a range of 5*1014 cm−3 and 1*1015 cm−3 is reached between a first depth, which is at least 20 μm, and a second depth, which is at maximum 50 μm. Such a profile of the doping concentration is achieved by using aluminum diffused layers as the at least two sublayers.

A known diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. On the anode side, a p-doped anode layer is arranged, and a metal layer which functions as an anode electrode is arranged on top of the p-doped anode layer. A higher (n+) doped cathode buffer layer is arranged on the cathode side. A metal layer in the form of a cathode electrode is arranged on top of the (n+) doped cathode buffer layer.
FIG. 1 shows the doping profile of a known p-doped anode layer 5, which includes two sublayers 56, 57. The sublayer 56 is a boron or gallium diffused layer, which has a high maximum doping concentration 565 of around 1*1018/cm3 or higher. Another sublayer with a higher sublayer depth 570 than the other sublayer and a lower maximum doping concentration is an aluminum diffused layer. Due to the high maximum doping concentration 565, the doping profile declines steeply to the sublayer depth 570.
Under fast reverse recovery with steep changes of current (high di/dt), the safe operation area (SOA) of fast recovery diodes is seriously limited by dynamic avalanche breakdown. This is the avalanche breakdown when the electric field is strongly increased by free carriers passing through the high electric field region with saturation velocity. The adjective "dynamic" reflects the fact that this occurs during transient device operation (see S. Linder, Power Semiconductors, EPFL Press, 2006). With increasing recovery di/dt, the dynamic avalanche gets stronger and leads to a device failure under much lower supply voltages as compared to a static breakdown voltage.
Methods for the suppression of dynamic avalanche are based on a proper shaping of the ON-state plasma distribution in the n-base layer of diodes by means of lifetime control. This can be done by single defect peak proton or helium irradiation combined with electron irradiation or heavy metal diffusion, multiple defect peak proton or helium irradiation, or a combination of proton or helium irradiation. Also, a controlled and low anode injection efficiency combined with lifetime control is a possible way to suppress the dynamic avalanche.
The above-mentioned methods are widely used in practice. However, they just remove the effect by decreasing the amount of free carriers passing through the high electric field region and not the cause, which is the high electric field. A method that suppresses the origin of dynamic avalanche and postpones its appearance towards higher supply voltages is based on the introduction of a thick buried low doped p-type layer, which is created by high energy Palladium ion irradiation followed by a diffusion step, and which layer is connected to an anode p-layer (see Vobecky et al, Radiation-Enhanced Diffusion of Palladium for a Local Lifetime Control in Power Devices, IEEE Transactions on Electron Devices, Vol. 54, 1521-1526). The p-layer has very low concentration of acceptors that smoothes out the peak electric field at the anode junction that is responsible for impact ionization leading to an avalanche breakdown. The beneficial effect of this layer increases with increasing thickness while the concentration is kept as close as possible to that of the n-base layer doping. However, this method requires high energy ion irradiation, for which special apparatus are needed. Furthermore, the concentration of the buried P-type layer depends on the quality of the anode surface. For wafers with a large diameter, this method requires delicate application, because a homogeneous temperature distribution during annealing, which is required for a controlled p-layer, is difficult to achieve. There is also a contamination risk during the manufacturing process due to the usage of Palladium.


A method of forming an integrated circuit capacitor includes the steps of forming an insulating layer on an integrated circuit substrate, and forming a conductive layer on the insulating layer opposite the integrated circuit substrate. A patterned ozone tetraethylorthosilicate undoped silicate layer is formed on the conductive layer, and conductive spacers are formed along sidewalls of the ozone tetraethylorthosilicate undoped silicate layer. A dielectric layer is formed on the conductive spacers and on the first conductive layer, and a second conductive layer is formed on the dielectric layer opposite the first conductive layer in the conductive spacers.

As dynamic random access memory (DRAM) devices become more highly integrated, the sizes of individual memory cells are reduced. The decrease in size of a memory cell is thus proportional to the increase in the capacity of a DRAM device. As the surface area of the integrated circuit substrate available for each memory cell is reduced, the height of the stacked chip structure may increase.
In order to provide normal memory device operation, the capacitance of the memory cell capacitors and the voltage applied to the elements of the memory device are preferably maintained at predetermined levels as the integration densities increase. Stated in other words, effective voltage ranges and capacitances for the elements of highly integrated DRAM devices should be maintained at predetermined levels as the size of the device elements are reduced. Accordingly, more complex device structures may be needed to provide a desired level of performance in a highly integrated DRAM device. Unit cell structures including a memory cell capacitor and a memory cell access transistor have changed significantly as higher levels of integration have been obtained.
For example, a memory cell capacitor for a 1M DRAM device may have a dielectric layer having a planar silicon oxide layer structure. A memory cell capacitor for a 4M DRAM may have a dielectric layer having a stacked O-N-O layered structure wherein silicon oxide and silicon nitride layers are stacked. A memory cell capacitor for a 16M DRAM device may have a dielectric layer having a stacked N-O layered structure wherein a silicon nitride layer and a silicon oxide layer are stacked. The memory cell capacitor for a 64M DRAM may have a dielectric layer having a cylindrical N-O layered structure or a stacked N-O layered structure on an electrode having hemispherical grains (HSG). Memory cell capacitors for 245M and 1 G DRAM devices may include three-dimensional electrode structures such as stacked, cylindrical, or capacitor-on-bit-line structures together with hemispherical grain (HSG) electrode surfaces and ferroelectric dielectric layers.
As will be understood by one having skill in the art, a capacitor includes two electrodes and a dielectric layer therebetween. The capacitance is directly proportional to the permittivity of the dielectric layer and the surface area of the electrodes. The capacitance is inversely proportional to the thickness of the dielectric layer.
Conventional dielectric layers have been provided using silicon oxide layers, silicon nitride layers, and combinations thereof. More recently, ferroelectric materials such as Ta.sub.2 O.sub.5 have been used to provide dielectric layers. These ferroelectric materials may have a permittivity three to four times higher than that of silicon nitride allowing an increase in capacitance.
Ferroelectric materials, however, have been difficult to use in certain DRAM applications, and it may difficult to reduce the thickness of a dielectric layer beyond a certain point. Accordingly, past attempts to increase memory cell capacitance have been primarily directed to increasing the surface area of the capacitor electrodes. In particular, conventional planar electrode structures have been replaced by three-dimensional structures or by providing structural distortions thereon. For example, stacked electrode structures, trench electrode structures, cylindrical electrode structures, and capacitor-on-bit-line electrode structures have been used to increase capacitor electrode surface areas.
The development of these three-dimensional electrode structures, however, may require more complicated processing steps. accordingly, these three-dimensional structures may result in increased expense due to the increased complexity of the processing steps and design rule limitations. Furthermore, sufficiently large and predictable capacitances may be difficult to obtain using these three-dimensional structures in a highly integrated memory device.
Capacitor electrode surface areas have also been increased by providing hemispherical grains on the surfaces of the electrodes. The use of hemispherical grains (HSG) on a capacitor electrode has been discussed by Watanabe in the reference entitled "Hemispherical Grained Silicon Formation On In-Situ Porous Doped Amorphous-Si Using The Seeding Method". SSDM, 1992, pp. 422-424. As discussed, silicon forms hemispherical-shaped regions due to silicon migration in the transition temperature range of crystalline silicon and amorphous silicon, as the surface energy is most stable in this range. The formation of the hemispherical grains produces a rough surface having a plurality of protrusions which are formed from a surface active silicic gas such as Si.sub.2 H.sub.6, SiH.sub.4 or silicon inside the layers. The surface active silicic gas uses some structurally abnormal or deposited particles of the wafer surface as seeds to enlarge the capacitor surface thereby increasing the capacitance of the capacitor including the electrodes having rough surfaces. Difficulties, however, may result from the use of electrodes having hemispherical grains thereon.
For example, when the lower electrode of the capacitor is doped, the size of the hemispherical grains may increase resulting in the reduction of capacitance due to insufficient impurity diffusion outside the lower electrode. When the lower electrode is doped by a POCl.sub.3 deposition, however, a wet etch may be needed to remove a P.sub.2 O.sub.5 layer formed thereon. This wet etch may abrade some of the protrusions hereby reducing the effect of the capacitor electrode enlargement. The protrusions can also be abraded by the impact of implanted ions.
In addition, the hemispherical grains may be formed between the lower electrodes wherein the hemispherical grains are formed on the lower electrode surfaces thereby shorting lower electrodes. A dry etch may thus be needed to remove hemispherical grained silicon portions on the insulating layer between the lower electrodes. This dry etch, however, may also etch the hemispherical grains formed on the electrode surface thereby reducing the enlargement of the electrode surface area.
Furthermore, the hemispherical grains may also form on the backside of the semiconductor substrate when using a low pressure chemical vapor deposition (LPCVD) to form the hemispherical grains. Accordingly, there is an increased probability that the hemispherical grains may generate particles during subsequent processing steps. Additional processing steps such as backside coating, wet etching, and backside coating removal have been used to reduce the formation of hemispherical grains on the backside of the substrate. The formation of hemispherical grains may also involve steps having relatively narrow processing margins. In particular, hemispherical grains may be formed at the transition temperature of amorphous silicon to polysilicon. The formation of the hemispherical grains is thus sensitive to the temperature controls so that it may be difficult to maintain a uniform size and density of hemispherical grains from wafer to wafer and run to run. Accordingly, there continues to exist a need in the art for improved methods of increasing memory cell capacitances.

Methods of forming three-dimensional capacitor structures including ozone tetraethylorthosilicate undoped silicate


In an approach for determining temporal solar capacity navigation routes, a computer receives navigation criteria navigation criteria that includes at least a starting location, a destination, a date, a time, and a temporal solar capacity. The computer determines one or more navigation routes based on the received navigation criteria. The computer creates a temporal solar capacity navigation map based on the received navigation criteria. The computer determines one or more suggested navigation routes from the determining one or more navigation routes based on the created temporal solar capacity navigation map.

The present invention relates generally to the field of navigation systems, and more particularly to providing a navigation route through integration of a temporal solar capacity map.
Renewable energy is capable of replacing conventional fuels in four distinct areas: electricity generation, air and water heating/cooling, motor fuels, and rural (off-grid) energy services. Renewable energy occurs through naturally replenishing resources, based on a human timescale, such as sunlight (e.g., solar energy), wind (e.g., wind power), water (e.g. hydropower), and geothermal heat (e.g., geothermal energy). Solar energy occurs either directly using photovoltaic (PV), or indirectly using concentrated solar power (CSP). Photovoltaic is a method of converting solar energy into direct current electricity using semiconducting materials that exhibit the photovoltaic effect (e.g., creation of voltage or electric current in a material upon exposure to light). A photovoltaic system employs solar panels composed of a number of solar cells that absorb light, separate the charges of carriers, and extract the charges to an external site, the resulting in the supply of usable solar power. Concentrated solar power systems use lenses or mirrors and tracking systems to focus a large area of sunlight into a small beam. Solar vehicles are electric vehicles that are powered completely or substantially by direct solar energy. The term "solar vehicle" usually implies that solar energy is used to power all or part of a vehicle's propulsion, however the solar power may be also used to provide power for communications, controls, or other auxiliary functions.
Through technological advancements, the manner in which individuals navigate and/or plan routes to a destination has evolved. Route planning software designs an optimal route between two geographic locations (e.g., origin and destination, start point and end point, etc.) using a journey planning engine. The journey planning engine suggests one or more routes between the origin and destination that may be optimized for different criteria (e.g., fastest, shortest, least turns, toll roads, expressways, etc.) and marks the routes within an interactive map. The integration of the route planning software into global positioning systems (GPS) and portable navigation systems, allows the combination of positioning capabilities (e.g., GPS) and navigation functions, in order to monitor and control the movement of a vehicle from one location to another along the route. The navigation systems receives signals from satellites through a GPS antenna and combines the data from the satellites with the information received from onboard sensors (e.g., direction sensor, speed sensor, etc.) to identify the position and direction of the vehicle on the route. The navigation system displays the current position and direction of the vehicle on a visual output device (e.g., handheld, embedded console screen, etc.) with respect to the route, and updates the route and electronic maps real time, until reaching the destination.

International Business Machines Corporation


The invention provides a neck-worn sensor that is a single, body-worn system that measures the following parameters from an ambulatory patient: heart rate, pulse rate, pulse oximetry, respiratory rate, temperature, thoracic fluid levels, stroke volume, cardiac output, and a parameter sensitive to blood pressure called pulse transit time. From stroke volume, a first algorithm employing a linear model can estimate the patient's pulse pressure. And from pulse pressure and pulse transit time, a second algorithm, also employing a linear algorithm, can estimate systolic blood pressure and diastolic blood pressure. Thus, the sensor can measure all five vital signs along with hemodynamic parameters. It also includes a motion-detecting accelerometer, from which it can determine motion-related parameters such as posture, degree of motion, activity level, respiratory-induced heaving of the chest, and falls.

Field of the Invention
The invention relates to sensors that measure physiological signals from patients and the use of such sensors.
General Background
There are a number of physiological parameters that can be assessed by measuring physiological or physiologically influenced electrical signals from a patient. Some signals, such as thoracic bioimpedance (TBI) and electrocardiogram (ECG) waveforms, are measured with electrodes that attach to the patient's skin. Processing of these waveforms yields parameters such as heart rate (HR), respiration rate (RR), heart rate variability (HRV), stroke volume (SV), cardiac output (CO), and parameters related to thoracic fluids, e.g. thoracic fluid content (TFC). Certain physiological conditions can be identified from these parameters when they are obtained at a single point in time; others require assessment over some period of time to identify trends in the parameters. In both cases, it is important to obtain the parameters consistently and with high repeatability and accuracy.
Some conditions require measuring parameters over a relatively short or modest period of time. For example, Holter monitors can characterize various types of cardiac arrhythmias by measuring HR, HRV, and ECG waveforms over a 24 to 48-hour period of time. On the other hand, chronic diseases such as congestive heart failure (CHF) and end-stage renal disease (ESRD) can require periodic measurements of fluids and weight throughout the patient's life. Not surprisingly, patient compliance typically decreases as the measurement period increases. This is particularly true when measurements are made outside of a conventional medical facility, e.g., at the patient's home or in a residential facility such as a nursing home.
Measuring some physiological parameters does not require a high degree of precision and/or consistency in the body location at which a measurement is taken. For example, measuring a patient's temperature is frequently performed with an oral thermometer that is simply placed somewhere under the tongue. Here, the exact placement of the thermometer does not have a big impact on the measured temperature value. Likewise, parameters that depend on time-dependent features in waveforms, such as HR, which depends on the time-dependent variation of R-R intervals in the ECG waveforms, are relatively insensitive to sensor positioning. In this case, the R-R intervals show almost no variation with positioning of electrodes on the patient's thoracic cavity. Blood pressure, in contrast, shows some sensitivity to measurement location. When measured with a sphygmomanometer, the blood pressure value is relatively insensitive to the general alignment of the cuff over the brachial artery, but will vary when measured at other locations on the body, such as the wrist, thigh, or even the opposing arm. On the contrary, measuring amplitude-dependent features in waveforms, such as TFC, will be strongly dependent on the positioning of electrodes. In this case, the value of TFC depends strongly on the impedance between the electrodes, and this in turn will vary with the electrodes' placement. Here, deviation in day-to-day placement of electrodes can result in measurement errors, particularly when trends of the measured parameters are extracted. This, in turn, can lead to misinformation, nullify the value of such measurements, and thus negatively impact treatment.
Known Devices and Relevant Physiology
Medical devices that measure time-dependent ECG and TBI waveforms from patients typically connect through cables or lead wires to disposable electrodes adhered at various locations on a patient's body. Analog circuits within a given device, which are typically located remote from the patient's body in the device, process the signals to generate the waveforms. With further analysis, such waveforms yield parameters such as HR, TFC, SV, CO, and RR. Other systems within a given medical device might measure vital signs such as pulse oximetry (SpO2), pulse rate (PR), systolic (SYS) and diastolic (DIA) blood pressure, and temperature (TEMP).
Disposable electrodes that measure ECG and TBI waveforms are typically worn on the patient's chest or legs and include: i) a conductive hydrogel that contacts the patient; ii) a Ag/AgCl-coated eyelet that contacts the hydrogel; iii) a conductive metal post that connects to a lead wire or cable extending from the device; and iv) an adhesive backing that adheres the electrode to the patient. Unfortunately, during a measurement, the lead wires can pull on the electrodes if the device is moved relative to the patient's body, or if the patient ambulates and snags the lead wires on various objects. Such pulling can be uncomfortable or even painful, particularly where the electrodes are attached to hirsute parts of the body, which can inhibit patient compliance with long-term monitoring. Moreover, such pulling can degrade or even completely eliminate adhesion of the electrodes to the patient's skin, thereby degrading or completely destroying the ability of the electrodes to sense the physiolectrical signals at various electrode locations.
Some devices that measure ECG and TBI waveforms are worn entirely on the patient's body. These devices have been improved to feature simple, patch-type systems that include both analog and digital electronics connected directly to underlying electrodes. Such devices are typically prescribed for relatively short periods of time, e.g. for a time period ranging from a few days to several weeks. They are typically wireless, and include technologies such as Bluetooth® transceivers to transmit information over a short range to a second device, which then includes a cellular radio to transmit the information to a web-based system.
Measurement of SpO2 values is almost always done from the patient's fingers, earlobes, or in some cases toes. In these cases, patients wear an optical sensor to measure photoplethysmogram (PPG) waveforms, which are then processed to yield SpO2 and PR. TEMP is typically measured with a thermometer inserted in the patient's mouth.
Assessing TFC, weight, and hydration status is important in the diagnosis and management of many diseases. For example, ESRD occurs when a patient's kidneys are no longer able to work at a level needed for day-to-day life. The disease is most commonly caused by diabetes and high blood pressure, and is characterized by swings in SYS and DIA along with a gradual increase in fluids throughout the body. Patients suffering from ESRD typically require hemodialysis or ultrafiltration to remove excess fluids. Thus to characterize ESRD, accurate measurement of these TFC can eliminate the need for empirical clinical estimations that often lead to over-removal or under-removal of fluid during dialysis, thereby preventing hemodynamic instability and hypotensive episodes (Anand et al., "Monitoring Changes in Fluid Status With a Wireless Multisensor Monitor: Results From the Fluid Removal During Adherent Renal Monitoring (FARM) Study," Congest Heart Fail. 2012; 18:32-36). A similar situation exists with respect to CHF, which is a complicated disease typically monitored using a "constellation" of physiological factors, i.e., fluid status (e.g. TFC), vital signs (i.e. HR, RR, TEMP, SYS, DIA, and SpO2), and hemodynamic parameters (e.g. CO, SV). Accurate measurement of these parameters can aid in managing patients, particularly for dispersing diuretic medications, thereby reducing expensive hospital readmissions (Packer et al., "Utility of Impedance Cardiography for the Identification of Short-Term Risk of Clinical Decompensation in Stable Patients With Chronic Heart Failure," J Am Coll Cardiol 2006; 47:2245-52).
CHF is a particular type of heart failure (HF), which is a chronic disease driven by complex pathophysiology. In general terms, this condition occurs when SV and CO are insufficient in adequately perfusing the kidneys and lungs. Causes of this disease are well known and typically include coronary heart disease, diabetes, hypertension, obesity, smoking, and valvular heart disease. In systolic HF, ejection fraction (EF) can be diminished (<50%), whereas in diastolic HF this parameter is typically normal (>65%). The common signifying characteristic of both forms of heart failure is time-dependent elevation of the pressure within the left atrium at the end of its contraction cycle, or left ventricular end-diastolic pressure (LVEDP). Chronic elevation of LVEDP causes transudation of fluid from the pulmonary veins into the lungs, resulting in shortness of breath (dyspnea), rapid breathing (tachypnea), and fatigue with exertion due to the mismatch of oxygen delivery and oxygen demand throughout the body. Thus, early compensatory mechanisms for HF that can be detected fairly easily include increased RR and HR.
As CO is compromised, the kidneys respond with decreased filtration capabilities, thus driving retention of sodium and water, and leading to an increase in intravascular volume. As the LVEDP rises, pulmonary venous congestion worsens. Body weight increases incrementally, and fluids may shift into the lower extremities. Medications for HF are designed to interrupt the kidneys' hormonal responses to diminished perfusion, and they also work to help excrete excess sodium and water from the body. However, an extremely delicate balance between these two biological treatment modalities needs to be maintained, since an increase in blood pressure (which relates to afterload) or fluid retention (which relates to preload), or a significant change in heart rate due to a tachyarrhythmia, can lead to decompensated HF. Unfortunately, this condition is often unresponsive to oral medications. In that situation, admission to a hospital is often necessary for intravenous diuretic therapy.
In medical centers, HF is typically detected using Doppler/ultrasound, which measures parameters such as SV, CO, and EF. In the home environment, on the other hand, gradual weight gain measured with a simple weight scale is one method to indicate CHF. However, this parameter is typically not sensitive enough to detect the early onset of CHF—a particularly important time when the condition may be ameliorated by a change in medication or diet.
SV is the mathematical difference between left ventricular end-diastolic volume (EDV) and end-systolic volume (ESV) and represents the volume of blood ejected by the left ventricle with each heartbeat; a typical value is about 70-100 mL. EF relates to EDV and ESV as described below in Equation 1:
                    EF        =                              SV            EDV                    =                                    EDV              -              ESV                        EDV                                              (        1        )
CO is the average, time-dependent volume of blood ejected from the left ventricle into the aorta and, informally, indicates how efficiently a patient's heart pumps blood through their arterial tree; a typical value is about 5-7 L/min. CO is the product of HR and SV, i.e.,CO=SV×HR  (2)
CHF patients, and in particular those suffering from systolic HF, may receive implanted devices such as pacemakers and/or implantable cardioverter-defibrillators to increase EF and subsequent blood flow throughout the body. These devices may include circuitry and algorithms to measure the electrical impedance between different leads of the device. As thoracic fluid increases in the CHF patient, the impedance typically is reduced. Thus, this parameter, when read by an interrogating device placed outside the patient's body, can indicate the onset of heart failure.
Monitoring Solutions
As illustrated in FIG. 1, many of the above-mentioned parameters can be used as early markers of the onset of CHF. EF is typically low in patients suffering from this chronic disease, and can be further diminished by factors such as a change in physiology, an increase in sodium in the patient's diet, or non-compliance with medications. This is manifested by a gradual decrease in SV, CO, and SYS that typically occurs between two and three weeks before a hospitalization event. The reduction in SV and CO diminishes perfusion to the kidneys. As described above, these organs then respond with a decrease in their filtering capacity, thus causing the patient to retain sodium and water and leading to an increase in intravascular volume. This, in turn, leads to congestion, which is manifested to some extent by a build-up of fluids in the patient's thoracic cavity (e.g. TFC). Typically, a detectable increase in TFC occurs about 1-2 weeks before hospitalization becomes necessary. Body weight increases after this event, typically by between three and five pounds, causing fluids to shift into the lower extremities. At this point, the patient may experience an increase in both HR and RR to increase perfusion. Nausea, dyspnea, and weight gain typically grow more pronounced a few days before hospitalization becomes necessary. As noted above, a characteristic of decompensated HF is that it is often unresponsive to oral medications; thus, at this point, intravenous diuretic therapy in a hospital setting often becomes mandatory. A hospital stay for intravenous diuretic therapy typically lasts about 4 days, after which the patient is discharged and the cycle shown in FIG. 1 can start over once more.
Not only is such cyclical pathology and treatment physically taxing on the patient, it is economically taxing on society as well. In this regard, CHF and ESRD affect, respectively, about 5.3 million and 3 million Americans, resulting in annual healthcare costs estimated at $45 billion for CHF and $35 billion for ESRD. CHF patients account for approximately 43% of annual Medicare expenditures, which is more than the combined expenditures for all types of cancer. Somewhat disconcertingly, roughly $17 billion of this is attributed to hospital readmissions. CHF is also the leading cause of mortality for patients with ESRD, and this demographic costs Medicare nearly $90,000/patient annually. Thus, there understandably exists a profound financial incentive to keep patients suffering from these diseases out of the hospital. Starting in 2012, U.S. hospitals have been penalized for above-normal readmission rates. Currently, the penalty has a cap of 1% of payments, growing to over 3% in the next three years.
Of some promise, however, is the fact that CHF-related hospital readmissions can be reduced when clinicians have access to detailed information that allows them to remotely titrate medications, monitor diet, and promote exercise. In fact, Medicare has estimated that 75% of all patients with ESRD and/or CHF could potentially avoid hospital readmissions if treated by simple, effective programs.
Thus, with the aim of identifying precursors to conditions such as CHF and ESRD, physicians can prescribe monitoring solutions to patients living at home. Typically such solutions include multiple, standard medical devices, e.g. blood pressure cuffs, weight scales, and pulse oximeters. In certain cases, patients use these devices daily and in a sequential manner, i.e. one device at a time. The patient then calls a central call center to relay their measured parameters. In more advanced systems, the devices are still used in a sequential manner, but automatically connect through a short-range wireless link (e.g. Bluetooth®) to a "hub", which then forwards the information off to a call center. Often the hub features a simple user interface that poses basic questions to the patient, e.g. questions concerning their diet, how they are feeling, and whether or not medications were taken.
Patients can also wear ambulatory cardiac monitors for periods of time ranging from several days to weeks to characterize cardiac conditions, such as arrhythmias. Such devices are called Holter or event monitors, and measure parameters such as HR, HRV, and ECG waveforms. They typically include a collection of chest-worn ECG electrodes (typically 3 or 5); an ECG circuit that collects analog signals from the ECG electrodes and converts them into multi-lead ECG waveforms; and a processing unit that analyzes the ECG waveforms to determine cardiac information. Typically, the patient wears the entire system on their body, but such systems can be awkward, cumbersome, and/or uncomfortable, e.g., due to the electrodes pulling the patient's skin/hair. Some ambulatory systems may simply include on-board memory that stores information for retrieval at a later time, at which point the information is analyzed to generate a report describing the patient's cardiac rhythm. More modern systems include wireless capabilities to transmit ECG waveforms and other numerical data through a cellular interface to an Internet-based system, where the report is generated using automated algorithms. In most cases, the report is imported into the patient's electronic medical record (EMR), which avails the report to cardiologists or other clinicians who can then use it to help characterize and treat the patient.
In order for such monitoring to be therapeutically effective, however, it is important for the patient to use their equipment consistently, both in terms of the duration and manner in which it is used. Less-than-satisfactory consistency with the use of any medical device (in terms of duration and/or methodology) may be particularly likely in an environment such as the patient's home or a nursing home, where direct supervision may be less than optimal.

This patent is subject to a terminal disclaimer.


Example methods are provided for a first endpoint to perform congestion control during communication with a second endpoint over a public network, the second endpoint being in a private network. The method may comprise generating a plurality of tunnel segments containing unreliable transport protocol data destined for the second endpoint; and determining whether congestion control is required based on a data amount of the plurality of tunnel segments and a congestion window associated with a tunnel connecting the first endpoint with the private network. The method may further comprise, in response to determination that congestion control is required, performing congestion control by dropping at least some of the plurality of tunnel segments; otherwise, sending the plurality of tunnel segments through the tunnel supported by the reliable transport protocol connection.

Unless otherwise indicated herein, the approaches described in this section are not admitted to be prior art by inclusion in this section.
A private network, such as a virtual private network (VPN), is a way to use a public network infrastructure (e.g., the Internet) to provide remote users at remote locations with secure access to their organization's network. A VPN is generally less expensive to run compared to a dedicated network owned or leased by the one organization. Although shared public network infrastructure is used, privacy may be maintained through security procedures and tunnelling protocols. For example, using a tunnelling protocol, a remote user is able to access the private network from a remote location via a tunnel connecting the remote user with the private network.
In practice, the tunnel may be implemented over a reliable transport protocol connection, such as a Transmission Control Protocol (TCP) connection that guarantees data delivery. Any suitable data may be communicated over the tunnel, including User Dat gram Protocol (UDP) datagrams. Compared to TCP, UDP is an unreliable transport protocol that provides a connection-less service and does not guarantee data delivery, making it suitable for more delay-sensitive applications. However, communicating unreliable UDP data rams via a reliable TCP connection may adversely affect latency and performance.

Congestion control during communication with a private network


A single use needleless hypodermic injector includes an elongate housing with a proximal end, a distal end, an axis and a hollow bore therethrough. The housing has a reservoir at the distal end with a generally cylindrical chamber for containing an injectable liquid. The chamber has a axis aligned with the housing longitudinal axis. The chamber has a first open end adjacent the housing with a resilient stopper mounted therein. The reservoir has a distal second end with an orifice in fluid communication with the chamber. The resilient stopper seals the chamber and ejects the liquid from the chamber, forming a stream at the orifice when the stopper is moved distally in the chamber. The injector has an piston mounted for axial movement within the housing bore and elements to axially bias the piston distally within the bore. The piston has an armed position wherein it is positioned proximally within the bore. The injector has elements to retain the piston in the armed position and to release the piston from the armed position. When the injector release elements are released, the piston moves distally to engage and move the resilient stopper distally, ejecting the liquid in the chamber through the orifice in a stream which will make a hypodermic penetration when the orifice is placed adjacent dermal tissue. The injector further has elements which prevent the piston from being retained in the armed position once the release elements are released, thereby rendering the injector non-resuable.

1. Field of the Invention
This invention relates generally to hypodermic injection devices, and more particularly to a single use needleless injection device that utilizes a fine high pressure stream of the liquid medicament to penetrate the skin and deliver the desired dosage into a patient's body.
2. Description of Related Information
The needleless jet injection art dates from the 1940's. The ability to perform needleless hypodermic penetrations developed as a result of observations of accidental injection of fluids into workers handling high pressure hydraulic lines having pinhole leaks.
The resultant early jet injector devices actually commercialized tended toward being large, complex units generally adapted to retain sufficient quantities of medicament for repeated injections. Most of these devices were intended for usage in fixed site situations such as army induction centers or mass inoculations at clinics.
Smaller portable devices also have been developed which are powered by compressed gas or springs. For the most part, these devices are complex and multi-component as well as requiring dismantling, reassembly and sterilization between uses.
Attempts have been made to simplify the usage of needleless injectors and make them more practical for individuals required to self-administer medicaments. Several devices have been developed with single use cartridges containing a liquid medicament intended for use with a reusable driver mechanism. Representative of these are U.S. Pat. No. 4,874,367 which teaches a single use cartridge and a reusable spring powered driver mechanism and U.S. Pat. No. 4,941,880 which teaches a prefilled medicament ampule with a reusable compressed gas powered drive mechanism. The devices taught in the '367 and '880 patents are complex and multi-component. They have a mass and size similar to a two cell "C" flashlight.
A single use device employing a gas powered drive mechanism is taught in U.S. Pat. No. 5,009,637. The teachings describe a threaded socket for a filled vial to vary the dose delivered. The '637 device has numerous parts and requires a fracturable high pressure cylinder or ampule to contain the compressed gas.
Size and complexity of the drive mechanism has largely precluded the use of needleless injectors for stand-by self administration of medicaments for acute insect bite allergy reactions, migraine attacks, infertility, impotence and the like. The majority of the devices in the prior art are designed to be reusable, hence they must be reloadable, thereby increasing their physical complexity and mass. As a result, most stand-by self administration kits currently available use either prefilled hypodermic syringes, or sealed ampules and a standard hypodermic syringe. While these kits are satisfactory for their intended use, in many states possession and disposal of syringes is regulated, thereby affecting their availability and use. Further, self administration of an injectable medicament, either with a prefilled syringe or a sealed ampule with a standard syringe, particularly under conditions of a physical stress such as an allergy or migraine attack requires a high level of control and skill on the part of the patient. A single use prefilled needleless hypodermic injection device which was simple to use, not complex to manufacture, hence available at a reasonable cost, designed not to be reuseable, thus likely not subject to the regulatory requirements regarding possession and disposal of hypodermic syringes, would represent an advance to the art. Such a device is described hereinbelow.

Single use disposable needleless injector


Color management using a vector-based color difference metric. A color difference map is comprised of color difference vectors for each of a plurality of pixels of an original image. The color difference vector for each pixel includes both a magnitude and a directionality representing a difference for color data in each pixel in the original image, relative to color data in a corresponding mapped pixel in a color mapped image. Pixels in the color difference map having large color differences in color movement relative to nearby pixels are identified in the color difference map, by applying an edge-detection algorithm to the color difference map. For each pixel that is identified in a smooth area in the original image and is identified as having a large color difference in the color difference map, a correction algorithm is applied, so as to provide a corrected color mapped image.

In the field of this disclosure, it is common to use a color difference metric to measure the "color difference" or "color movement" between an original color and a mapped color. For example, a commonly used metric is the deltaE color difference metric, which is evaluated in the Lab 3-D color space. The deltaE metric is the magnitude of the 3-D color distance between the original color and the mapped color (in the 3-D color space).
Given an original color (L1, a1, b1) and a mapped color (L2, a2, b2), the deltaE color distance is the Euclidean distance, or the straight line distance between the two color points in Lab space, as represented by Equation 1:deltaE=√{square root over ((L1−L2)2+(a1−a2)2+(b1−b2)2)}{square root over ((L1−L2)2+(a1−a2)2+(b1−b2)2)}{square root over ((L1−L2)2+(a1−a2)2+(b1−b2)2)}  (Equation 1)
Thus, the deltaE metric represents the magnitude of the 3-D color distance between the original color and the mapped color.

Vector-based color difference metric for color mapping


A semiconductor memory device according to the present invention includes a memory cell array, internal circuits for reading and writing of data of the memory cell array, a test mode controller, and power-on-reset circuits. The test mode controller sets a test mode of the memory cell array in response to a predetermined pattern of change of logic levels of at least several control signals out of a plurality of control signals for controlling the internal circuits. The power-on-reset circuits set the test mode controller in an initial state over a variable period which is defined based on a timing of change of a logic level of a control signal determining a timing of setting of the test mode out of the at least several control signals, in response to power-on. As a result, it is possible to prevent the semiconductor memory device from erroneously entering the test mode caused by a noise or the like after power-on.

1. Field of the Invention
The present invention generally relates to semiconductor memory devices and a method of setting a test mode, and more particularly, to a semiconductor memory device having a test mode which is set based on an external control signal and a method of setting the test mode.
2. Description of the Background Art
With a semiconductor memory device made large in memory capacity in recent years, a function test of a memory cell array in the semiconductor memory device after manufacture has become more important. However, a time required for such a function test becomes longer as the number of memory cells included in the memory cell array increases, that is, the memory capacity of the semiconductor memory device increases. Therefore, increase of a time required for such a function test in the semiconductor memory device with large memory capacity has become a problem in recent years.
In order to shorten a time required for such a function test, a so-called on-chip test circuit system is employed recently in many cases in which a circuit unit for such a function test (hereinafter referred to as a "test circuit") is provided on the same chip together with circuits constituting a semiconductor memory device. For example, such an on-chip test circuit system is used in a DRAM (Dynamic Random Access Memory) in many cases.
FIG. 7 is a block diagram showing the entire configuration of a DRAM in which the on-chip test circuit system is employed. Referring to FIG. 7, a memory cell array 1 includes memory cells (not shown) arranged in rows and columns in a matrix manner, word lines (not shown) provided one for each row, and bit line pairs (not shown) provided one pair for each column. Each of the memory cells is connected to a word line of a corresponding row and a bit line pair of a corresponding column.
Selection of any word line is carried out by a row decoder 2, and selection of any bit line pair is carried out by a column decoder 3. Word line selection by row decoder 2 and bit line pair selection by column decoder 3 are carried out in response to a row address signal RA0 to RA9 and a column address signal CA0 to CA9 provided from an address buffer 4, respectively.
Address buffer 4 incorporate either an internal address signal Q0 to Q9 provided from a refresh counter 8 or an external address signal A0 to A10, based on an internal row address strobe signal intRAS provided from a RAS input circuit 10 and an internal column address strobe signal intCAS provided from a CAS input circuit 12.
Furthermore, address buffer 4 provides the row address signal RA0 to RA10 and the column address signal. CA0 to CA10 corresponding to the incorporated address signal. In the normal data reading operation and the normal data writing operation, address buffer 4 incorporates the external address signal A0 to A10. In the refresh operation in which data is rewritten in the memory cells before memory data of the memory cells in memory cell array 1 disappears, address buffer 4 incorporates the internal address signal Q0 to Q9 from refresh counter 8.
A refresh controller 9 instructs output of the internal address signal to refresh counter 8 at a predetermined timing, based on the internal row address strobe signal intRAS from RAS input circuit 10. Refresh counter 8 generates the internal address signal Q0 to Q9 indicating the address of the memory cell having memory data to be refreshed, in response to instruction from refresh controller 9.
Row decoder 2 carries out word line selection based on the row address signal RA0 to RA9 from address buffer 4 at a timing based on the internal row address strobe signal intRAS from RAS input circuit 10. On the other hand, column decoder 3 carries out bit line pair selection based on the column address signal CA0 to CA9 from address buffer 4 at a timing based on the internal column address strobe signal intCAS from CAS input circuit 12.
More specifically, column decoder 3 controls an I/0 gate 5 in order to electrically connect only a bit line pair corresponding to the column address signal CA0 to CA10 out of bit line pairs in memory cell array 1 to an input buffer 6 or an output buffer 7 at a timing corresponding to the internal column address strobe signal intCAS.
I/O gate 5 includes transfer gates (not shown) provided corresponding to respective bit line pairs in order to connect bit line pairs in memory cell array 1 to input buffer 6 and output buffer 7. Column decoder 3 carries out bit line pair selection by bringing into an on state only a transfer gate corresponding to a bit line pair of a column address indicated by the column address signal CA0 to CA9 out of the transfer gates included in I/O gate 5.
A sense amplifier 15 amplifies data (read out data) which appears in each of the bit line pairs in memory cell array 1 in the data reading operation. By bit line pair selection operation of column decoder 3, only a bit line pair corresponding to the address signal out of the bit line pairs in memory cell array 1 is connected to output buffer 7 through I/O gate 5. Therefore, only read out data which appears in the corresponding bit line pair out of the bit line pairs in memory cell array 1 is applied to a data output terminal D.sub.out through output buffer 7 after being amplified by sense amplifier 15.
In the data writing operation, data applied to a data input terminal D.sub.in is applied to I/O gate 5 through input buffer 6. As a result, externally applied data is written in a selected memory cell through a bit line pair selected by column decoder 3 out of the bit line pairs in memory cell array 1.
Reception and transmission of data among I/O gate 5, input buffer 6 and output buffer 7 are carried out on the 8-bit basis in maximum. However, in the normal data writing operation and the normal data reading operation, an I/O controller 11 controls input buffer 6 and output buffer 7 so that reception and transmission of data among I/O gate 5, input buffer 6 and output buffer 7 are carried out on the 4-bit basis.
I/O controller 11 controls input buffer 6 and output buffer 7, based on the least significant bits RA10 and CA10 in the row address signal RA0 to RA0 and the column address signal CA0 to CA10, respectively, provided from address buffer 4 and the internal write enable signal intWE provided from WE input circuit 13.
More specifically, in the data reading operation in which the internal write enable signal intWE is at a logic high or "H" level, I/O controller 11 controls operation of output buffer 7 based on the row address signal bit RA10 and the column address signal bit CA10 so that output buffer 7 provides only 1-bit data corresponding to the address designated by the row address signal bit RA0 and the column address signal bit CA10 out of 4-bit data incorporated from I/O gate 5.
Similarly, in the data writing operation in which the internal write enable signal intWE is at a logic low or "L" level, I/O controller 11 controls operation of input buffer 6 based on the row address signal bit RA10 and the column address signal bit CA10 so that input buffer 6 incorporates data applied from the data input terminal D.sub.in to apply the same to a transfer gate corresponding to a bit line pair of the address designated by the row address signal bit RA10 and the column address signal bit CA10 out of the transfer gates in I/O gate 5.
In the refresh operation, data read out to output buffer 7 is again applied to I/O gate 5 as writing data. Since address buffer 4 incorporates the internal address signal Q0 to Q9 from refresh counter 8 in the refresh operation, memory data of the memory cell of the address instructed by the internal address signal Q0 to Q9 is refreshed.
In a test mode in which a function test of memory cells in memory cell array 1 is carried out, reception and transmission of data among I/O gate 5, input buffer 6 and output buffer 7 are carried out on the 8-bit basis. More specifically, in the test mode, column decoder 3, input buffer 6 and output buffer 7 operate in response to a test enable signal TE of an "L" level from a test mode controller 14.
When described more specifically, column decoder 3 ignores the least significant bit CA10 of the column address signal, and decodes only the higher bits CA0 to CA9 of the column address signal to carry out bit line selection, during a period when it receives the test enable signal TE of an "L" level from test mode controller 14. As a result, the number of bit line pairs selected by column decoder 3 at one time is made double of that in the normal data reading operation and the normal data writing operation.
On the other hand, during a period when input buffer 6 receives the test enable signal TE of an "L" level from test mode controller 14, it is controlled by I/O controller 11 to apply 8-bit data provided at the data input terminal D.sub.in to I/O gate 5 in parallel.
Similarly, during a period when output buffer 7 receives the test enable signal TE of an "L" level from test mode controller 14, output buffer 7, controlled by I/O controller 11, detects match and mismatch of the 8-bit data applied from I/O gate 5 in parallel with written data to provide the result to the data output terminal D.sub.out.
Therefore, the result of determination of whether or not all the data read out to eight pairs of bit line pairs selected by column decoder 3 in the test mode matches the written data is provided outside through output buffer 7. The externally applied 8-bit writing data is applied to the eight pairs of bit line pairs in parallel through input buffer 6.
A function test of a memory cell array is carried out by, after writing a predetermined data in all or a part of the memory cells included in the memory cell array, reading out data from the memory cell in which the data is written, to determine whether or not the read out data matches the data written in advance. Therefore, by the above-described operation of column decoder 3, input buffer 6 and output buffer 7 in the test mode, tests for eight memory cells are automatically carried out simultaneously. More specifically, in the test mode, the memory cells in memory cell array 1 are tested automatically for every eight memory cells. It should be noted that a pattern and the like of the data written in the memory cell array for testing depend on the kind of the test.
Test mode controller 14 is a circuit for setting the DRAM in the test mode based on the internal row address strobe signal intRAS from RAS input circuit 10, the internal column address strobe signal intCAS from CAS input circuit 12, and the internal write enable signal intWE from WE input circuit 13.
RAS input circuit 10, CAS input circuit 12, and WE input circuit 13 buffer the external row address strobe signal RAS, the external column address strobe signal CAS, and the external write enable signal WE which are external control signals, to provide the buffered signals as the internal row address strobe signal intRAS, the internal column address strobe signal intCAS, and the internal write enable signal intWE, respectively. Therefore, the internal control signals intRAS, intCAS, and intWE have waveforms substantially the same as those of the external control signals RAS, CAS, and WE, respectively.
Description will now be given on specific operation of test mode controller 14 with reference to FIG. 8. FIG. 8 is a waveform diagram showing waveforms of the external row address strobe signal RAS (a), the internal row address strobe signal intRAS (b), the external column address strobe signal CAS (c), the internal column address strobe signal intCAS (d), the external write enable signal WE (e), the internal write enable signal intWE (f) and the test enable signal TE (g), when test mode controller 14 sets the DRAM in the test mode.
Referring to FIG. 8, test mode controller 14 is activated when the internal signals intCAS (FIG. 8 (d)) and intWE (FIG. 8 (f)) both are already at an "L" level at a time t1 of the fall of the internal signal intRAS (FIG. 8 (b)). Activated test mode controller 14 causes the test enable signal TE (FIG. 8 (g)) to fall to an "L" level. As a result, column decoder 3, input buffer 6 and output buffer 7 in FIG. 5 carry out operation for a test as described above.
Since test mode controller 14 operates as described above, a user may set timings of respective signals so as to cause the external control signal RAS to fall to an "L" level during a period when the external control signals CAS and WE both are at an "L" level, in order to set the DRAM in the test mode. A method of setting a test mode is determined internationally by Joint Electron Device Engineering Council (JEDEC).
Referring again to FIG. 7, a power-on-reset circuit 16 receives a voltage V.sub.CC supplied from an external power source (not shown). Power-on-reset circuit 16 applies a one-shot pulse of an "H" level to predetermined circuit units in the DRAM in response to the rise of the power supply voltage V.sub.CC, that is, power-on to the DRAM. The one-shot pulse is called a power-on-reset signal POR.
Potentials of predetermined nodes in the predetermined circuit units are forced to respective levels to be taken in the initial state by the power-on-reset signal POR. As a result, the predetermined circuit units are brought into reset states at the initiation of operation. The power-on-reset signal POR is applied to, for example, RAS input circuit 10 as well as test mode controller 14. As described above, a semiconductor memory device generating a reset signal at the time of power-on is disclosed in, for example, Japanese Patent Laying-Open No. 2-29118 and Japanese Patent Laying-Open No. 63-98213.
Although it is shown in FIG. 7 that the output POR of power-on-reset circuit 16 is applied only to RAS input circuit 10 and test mode controller 14, the output POR is actually applied to the other circuit units as necessary.
In response to the applied power-on-reset signal POR, test mode controller 14 forcibly maintains the test enable signal TE at an "H" level during a period when the power-on-reset signal POR is at an "H" level, and retains the reset state so that the DRAM will not enter the test mode.
FIGS. 9 and 10 are waveform diagrams showing reset operation of the test mode controller by the above-described power-on-reset signal POR. FIG. 9 shows operation in the state where the external row address strobe signal RAS (c), the external column address strobe signal CAS (e), and the external write enable signal WE (g) all are already at an "H" level at the time of power-on (time t.sub.2) to the DRAM.
In the case of FIG. 9, as the power supply voltage V.sub.CC (a) rises after power-on at the time t.sub.2, the power-on-reset signal POR (b), the internal row address strobe signal intRAS (d), the internal column address strobe signal intCAS (f), the internal write enable signal intWE (h) and the test enable signal TE (i) rise to an "H" level simultaneously to reach the respective initial states. As described above, the power-on-reset signal POR maintains an "H" level during a predetermined reset period since its rise, and falls to an "L" level at a time t.sub.3.
The power-on-reset signal POR is supplied to each unit in the DRAM such as RAS input circuit 10 and test mode controller 14 as shown in FIG. 7. Therefore, during the reset period, signals in respective units in the DRAM shown in FIG. 9 maintain the respective initial states. Especially when focusing on the test mode, the test enable signal TE is maintained at an "H" level during a reset period as shown in FIG. 9 (i), and the DRAM is prevented from entering the test mode during this period.
On the other hand, FIG. 10 shows operation in the state where the external row address strobe signal RAS, the external column address strobe signal CAS, and the external write enable signal WE rise simultaneously after power-on to the DRAM and after a lapse of the above-mentioned reset period. In the case of FIG. 10, the above-described three external control signals slowly rise from a certain time after the time t.sub.3 to attain an "H" level. Accordingly, corresponding three internal control signals, that is, the internal row address strobe signal intRAS, the internal column address strobe signal intCAS, and the internal write enable signal intWE respectively rise to an "H" level rapidly at the timings when the corresponding external control signals attain respective threshold levels for recognizing as an "H" level.
The test enable signal TE is initialized to an "H" level during the reset period, thereby preventing the DRAM from entering the test mode during the reset period.
In the operation shown in FIG. 10, there is a case where the rises of the three internal control signals sometimes occur at the timings slightly different from one another as described above. For example, as shown in FIG. 10, there may be a case where the internal row address strobe signal intRAS rapidly rises at a time t.sub.4, while the internal column address strobe signal intCAS and the internal write enable signal WE rise rapidly at a time t.sub.5 with a little delay. In such a case, between the times t.sub.4 and t.sub.5, the internal row address strobe signal intRAS accidentally attains an "H" level, and the internal column address strobe signal intCAS and the internal write enable signal intWE accidentally attain an "L" level. Test mode controller 14 results in erroneous recognition that the precondition for setting of the test mode by the above-described JEDEC standard are satisfied.
Therefore, in such a case, if the internal row address strobe signal intRAS temporarily falls from an "H" level to an "L" level (a portion shown by a broken line of FIG. 10 (d) and FIG. 11)) by variation caused by a noise or the like in the vicinity of a threshold value of, for example, the external row address strobe signal RAS, test mode controller 14 erroneously generates the test enable signal TE designating the test mode accordingly (a portion shown by a broken line of FIG. 10 (i)). As a result, contrary to the user's intention, the DRAM unnecessarily enters the test mode right after power-on, causing malfunction of the DRAM.

Semiconductor memory device having test mode and method of setting test mode


An access point receives notification of a bit rate setting specifying a throughput needed to transmit corresponding content to a communication device. Based on the bit rate setting, the wireless access point identifies a set of multiple possible modulation-coding options supporting transmission of data at different bit rates greater than the bit rate setting needed to transmit the corresponding content. The wireless access point selects a respective modulation-coding option that provides a throughput bit rate that is lower than a modulation-coding option in the set providing a highest possible throughput bit rate. Selection of the lower bit rate modulation-coding option provides adequate capacity to transmit the corresponding content, yet does so with a higher signal to noise ratio than would be provided by the higher bit rate modulation-coding option. Subsequent to selection, the wireless access point transmits the corresponding content to the communication device via the selected modulation-coding option.

Conventional computer devices can initiate communications with a respective WiFi™ access point in a network to establish a corresponding wireless communication link between the computer device and the selected WiFi™ access point.
Via the established wireless communication link, the computer device is able to communicate a request for content to the WiFi™ access point. The WiFi™ access point, on behalf of the computer device, forwards the request for content to an appropriate server resource. In response to receiving the request, the server resource transmits the requested content to the WiFi™ access point. Thereafter, the WiFi™ access point transmits the requested content over the wireless communication link to the computer device. Accordingly, a computer device can use a wireless access point as an intermediary to retrieve requested data.
A modulation-coding option for communicating between the computer device and WiFi™ access point can be selected depending on an amount of wireless signal attenuation between the between the WiFi™ access point and the corresponding computer device. For example, the amount of signal attenuation can vary based on a number of factors such as distance of separation between the computer device and the WiFi™ access point, a number or types of objects disposed in a respective path between the computer device and the WiFi™ access point, and so on.
Based at least in part on the amount of detected attenuation, the WiFi™ access point dynamically assigns one of multiple different modulation coding options that support a highest possible wireless bit transmission rate.
As mentioned above, the amount of wireless signal attenuation can vary over time. For example, a computer user can move from one location to another, increasing the amount of signal attenuation between the wireless access point and a corresponding computer device.
Thus, according to conventional WiFi™ standards, to accommodate changing conditions, the computer device and/or WiFi™ access point constantly re-negotiates for a highest possible bit rate modulation-coding option possible depending on a current amount of signal attenuation.
Current WiFi™ standards such as IEEE 802.11b/g/n/ac achieve ever-higher rates ranging from 1.1 Mega Bits per Second to 1.3 Gigabits per second by making use of multiple streams (MIMO), Beam-forming and Modulation Coding Options (MCS). These conventional techniques are all designed to maintain a maximum data rate at any particular range and radio frequency link budget.


Liquid crystal display (LCD) structures and methods for forming the same. The black matrix and the color filter layer of the LCD are moved from color filter substrate to TFT substrate to form a color filter on TFT (COT) structure. Besides, the spacers are composed of photoresist or color photoresist can be located on portions of areas covered by the black matrix to maximize the aperture ratio.

1. Field of Invention
The present invention relates to liquid crystal display (LCD) structures and methods of forming them. More particularly, the present invention relates to LCD structures of integrating a black matrix and a color filter into a substrate having a control circuit thereon and methods of forming the same.
2. Description of Related Art
Liquid crystal display (LCD) has many advantages over other conventional types of displays including high picture quality, small volume occupation, lightweight, low voltage driven and low power consumption. Hence, LCD is widely used in small portable televisions, mobile telephones, video recording units, notebook computers, desktop monitors, projector televisions and so on. LCD gradually replaces conventional cathode ray tube (CRT) as a mainstream display unit.
The main part of LCD is liquid crystal (LC) unit composed of two parallel transparent substrates and LC sealed therein. The mainstream of the LCD is thin film transistor (TFT) LCD. The fabrication processes of a TFT-LCD can be divided into four parts: TFT array, process, color filter (CF) process, LC cell assembly process, liquid crystal module (LCM) process.
The TFT array process is used to fabricate a TFT substrate. Each TFT respectively aligns with one pixel electrode. The CF process is used to fabricate color filter substrate. A color filter layer composed of different color filter sheet is on the color filter substrate, and a black matrix layer surrounds each color filter sheet.
The LC cell assembly process is used to parallel assembles TFT substrate and CF substrate, and bead spacers spread between them to maintain a fixed distance, i.e. cell gap, between TFT substrate and CF substrate. LC is injected into the cell gap then the injection opening is sealed. Basically, each pixel electrode is respectively corresponding to one color filter sheet, and the black matrix layer covers on TFTs and metal lines that connect different TFT.
The LCM process is used to attach a polarizer to a panel, and electrically connect driver IC and panel circuit. Then a reflector and a back-light are assembled on the panel. After a burn-in step, the LCM process is finished.
Generally speaking, the direction of liquid crystal molecule axes, which are controlled by TFT, determines whether each pixel is pervious to light or not. The color of each pixel is determined by the color of color filter sheet. For example, when light passes through a red color filter sheet, a red spot is shown on the panel. Mixing red, green and blue colors can show full-color images.
Since the molecular axes of liquid crystal molecules, which are between pixel electrodes and color filter sheets, have to be controlled precisely, the color filter and the TFT substrate must be aligned precisely. The tolerable error of alignment is only within several micron meters.
The heat coefficients of color filter substrate and TFT substrate are different, hence the precise alignment of pixel electrodes and color filter sheets is hard to achieve. Decreasing the product yield and increasing the production cost are caused by this problem. With growing size of substrates, the problem is getting serious. Therefore, light leakage and coin mura on panel is produced. But for increasing the size of black matrix to increase the alignment precision, the color contrast and brightness of LCD is decreased.
Another problem is the random distribution of bead spacers. The bead spacers may block some of the pixel area. Hence the aperture ratio of LCD is decreased. For smaller pixel area or for high-resolution panel, the problem is more serious.
An object of the invention is to provide a liquid crystal display structure, wherein a black matrix and a color filter layer both are on a control circuit substrate and pixel electrodes are on the color filter layer to increase the align preciseness of the color filter layer and the pixel electrodes. Besides, photoresist spacers are used to replace the conventional bead spacers to increase the brightness and color contrast of a liquid crystal display.
The liquid crystal display structure comprises a first substrate having a control circuit on it, and a black matrix layer, a color filter layer, a pixel electrode layer, a plurality of photoresist spacers, a liquid crystal layer, a common electrode and a second substrate are in turn on it.
A plurality of openings are in the black matrix layer to expose the first substrate. The color filter layer is composed of a plurality of color filter sheets aligning with each opening. Each pixel electrode aligns with each color filter sheet. The photoresist spacers are located on portions of areas covered by the black matrix, and their hardness is preferred to be about 2H to about 4H and their height is preferred to be about 1 to about 10 xcexcm. The photoresist spacers also can be composed of multi-layered color photoresist.
Another object of the invention is to provide methods of forming a liquid crystal display to increase alignment preciseness between color filter sheets and pixel electrodes, and photoresist spacers are used to replace conventional bead spacers.
Accordingly, in an embodiment, a black matrix layer is formed on a first substrate having a control circuit thereon. A plurality of openings are formed in the black matrix layer to expose the first substrate. A color filter layer is formed on the black matrix layer. A plurality of pixel electrodes are formed on the color filter to align with each of the openings. A plurality of photoresist spacers are formed on the first substrate to be located on portions of areas covered by the black matrix. The first substrate and a second substrate having a common electrode thereon are parallel assembled, wherein the photoresist spacers and the common electrode are between the first substrate and the second substrate. A liquid crystal layer is formed between the first substrate and the second substrate. The order of the step of forming the photoresist spacers and the step of the pixel electrodes can be exchanged.
In another embodiment, a black matrix layer is formed on a first substrate having a control circuit thereon. A plurality of openings are formed in the black matrix layer to expose the first substrate. A color filter layer is formed on the black matrix layer. A plurality of pixel electrodes are formed on the color filter layer to align with each of the openings. A plurality of photoresist spacers are formed on a second substrate having a common electrode thereon the first substrate and the second substrate are parallel assembled, wherein the photoresist spacers and the pixel electrodes are between the first substrate and the second substrate. A liquid crystal layer is formed between the first substrate and the second substrate.
A further object of this invention is to provide a method of forming a liquid crystal display, wherein multi-layered color photoresist are stacked to form photoresist spacers.
In this embodiment, a black matrix layer is formed on a first substrate having a control circuit thereon. A plurality of first, second and third openings are formed in the black matrix layer to expose the first substrate. A first color photoresist is formed on the first substrate. The first color photoresist is patterned to form a plurality of first filter sheets aligning with each of the first openings and a plurality of first spacers located on portions of areas covered by the black matrix. A second color photoresist is formed on the first substrate. The second color photoresist is patterned to form a plurality of second filter sheets aligning with each of the second openings and a plurality of second spacers overlapping with the first spacers. A third color photoresist is formed on the first substrate. The third color photoresist is patterned to form a plurality of third filter sheets aligning with each of the third openings and a plurality of third spacers overlapping with the second spacers. A plurality of pixel electrodes are respectively formed on the first, second and third filter sheets. The first substrate and a second substrate having a common electrode thereon are parallel assembled, wherein the photoresist spacers and the common electrode are between the first substrate and the second substrate. A liquid crystal layer is formed between the first substrate and the second substrate.
As embodied and broadly described herein, the invention provides liquid crystal structures and methods of forming the same, wherein the black matrix and the color filter are moved from the color substrate to the control circuit substrate. Since the alignment preciseness is mostly controlled by photolithography, the alignment error can be greatly reduced to below micron meter. Moreover, the photoresist spacers are located on portions of areas covered by the black matrix, the brightness and the color contrast of the liquid crystal display can be highly raised. Beside, the color photoresist is also used to form spacers, the production cost can be largely reduced and the production yield can be largely promoted.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

Liquid crystal display structures and methods of forming the same