The present invention aims to provide a particulate composition containing anhydrous crystalline 2-O-α-D-glucosyl-L-ascorbic acid having a significantly, hardly solidifiable property compared to conventional ones in a grade for use in quasi-drugs; a process for producing the same; and uses thereof. The present invention solves the above object by providing a particulate composition containing anhydrous crystalline 2-O-α-D-glucosyl-L-ascorbic in an amount of over 98.0% by weight but less than 99.9% by weight, on a dry solid basis; or a degree of crystallinity of 90% or higher for anhydrous crystalline 2-O-α-D-glucosyl-L-ascorbic acid; and by providing a process for producing the same and uses thereof.

1. Field of the Invention
The present invention relates to a particulate composition containing anhydrous crystalline 2-O-α-D-glucosyl-L-ascorbic acid, process for producing the same, and uses thereof, more particularly, to a hardly solidifiable particulate composition containing anhydrous crystalline 2-O-α-D-glucosyl-L-ascorbic acid, process for producing the same, and uses thereof as a material for food products, cosmetics, quasi-drugs, and pharmaceuticals.
2. Description of the Prior Art
Due to its advantageous physiological activities and antioxidant action, L-ascorbic acid has been used for various purposes, including those for food products and cosmetics. L-Ascorbic acid, however, is unstable because of its direct reducibility, and it is susceptible to receive oxidative degradation and to lose its physiological activity as the crucial defect. To overcome the defect, the present applicant, as one of the co-applicants of Patent Literature 1, disclosed 2-O-α-D-glucosyl-L-ascorbic acid that is composed of one molecule of D-glucose bound to the hydroxyl group at the C-2 position of L-ascorbic acid (hereinafter, abbreviated as "ascorbic acid 2-glucoside", throughout the specification). As outstanding characteristics, ascorbic acid 2-glucoside does not exhibit direct reducibility but has a satisfactory stability, and it exerts the physiological activities inherent to L-ascorbic acid after being decomposed in living bodies into L-ascorbic acid and D-glucose by an in vivo enzyme inherently existing in the living bodies. According to the process disclosed in Patent Literature 1, ascorbic acid 2-glucoside is formed by allowing a saccharide-transferring enzyme such as cyclomaltodextrin glucanotransferase (abbreviated as "CGTase", hereinafter) or α-glucosidase to act on a solution containing L-ascorbic acid and α-glucosyl saccharide compound.
In Patent Literature 2, the present applicant succeeded in crystallizing ascorbic acid 2-glucoside from a saturated solution of ascorbic acid 2-glucoside and disclosed crystalline ascorbic acid 2-glucoside and a particulate composition containing the same. Until now, crystalline ascorbic acid 2-glucoside has been known to merely exist in an anhydrous crystalline form. Non-Patent Literatures 1 and 2 reported data on X-ray structure analysis for crystalline ascorbic acid 2-glucoside.
In Patent Literatures 3 and 4, the same applicant as the present invention disclosed a process for collecting a high ascorbic acid 2-glucoside content fraction, comprising subjecting a solution containing ascorbic acid 2-glucoside formed by an enzymatic reaction to column chromatography using a strong-acid cation exchange resin, and collecting the fraction. In Patent Literature 5, the same applicant disclosed a process for producing a high ascorbic acid 2-glucoside content product, comprising subjecting a solution containing ascorbic acid 2-glucoside formed by an enzymatic reaction to electrodialysis using an anion-exchange membrane to remove impurities such as L-ascorbic acid and saccharides from the solution; and in Patent Literature 6, the same applicant disclosed a process for producing a high ascorbic acid 2-glucoside content product, comprising subjecting a solution containing ascorbic acid 2-glucoside to an anion-exchange resin and selectively desorbing the ingredients adsorbed on the resin to obtain a fraction rich in ascorbic acid 2-glucoside.
In Patent Literature 7, the same applicant as the present invention disclosed a process for producing ascorbic acid 2-glucoside, comprising allowing α-isomaltosyl glucosaccharide-forming enzyme or α-isomaltosyl glucosaccharide-forming enzyme in combination with CGTase to act on a solution containing L-ascorbic acid and α-glucosyl saccharide compound to form ascorbic acid 2-glucoside. Patent Literatures 8 and 9 applied for by the same applicant as the present invention disclose that α-isomaltosyl glucosaccharide-forming enzyme and α-isomaltosyl-transferring enzyme catalyze saccharide transferring to L-ascorbic acid to form ascorbic acid 2-glucoside.
Referring to uses of ascorbic acid 2-glucoside, many proposals have been made as shown in, for example, Patent Literatures 10 to 29. Depending on its advantageous characteristics, ascorbic acid 2-glucoside has been conventionally used as a material for food products, cosmetics, quasi-drugs, or pharmaceuticals; and it has been extensively used in other uses where L-ascorbic acid could not be used due to its instability, to say nothing of conventional uses of L-ascorbic acid.
As described above, ascorbic acid 2-glucoside is now known to be produced by using L-ascorbic acid and amylaceous substances as materials and various saccharide-transferring enzymes. According to the findings already obtained by the present applicant so far, the method for allowing CGTase as a saccharide-transferring enzyme to act on a solution containing L-ascorbic acid and amylaceous substance is an industrially advantageous method because of its highest production yield of ascorbic acid 2-glucoside. Based on this finding, the present applicant has been producing particulate compositions containing anhydrous crystalline ascorbic acid 2-glucoside by the method of allowing CGTase to act on a solution containing L-ascorbic acid and amylaceous substance, and commercializing the particulate compositions as materials for cosmetics/quasi-drugs and for food products, which are respectively commercialized as "AA2G" and "ASCOFRESH", product names of such particulate compositions and commercialized by Hayashibara Biochemical Laboratories, Inc., Okayama, Japan, and Hayashibara Shoji Inc., Okayama, Japan, respectively (these conventional particulate compositions containing anhydrous crystalline ascorbic acid 2-glucoside that have been commercialized as materials for cosmetics/quasi-drugs and for food products are abbreviated as "quasi-drug grade powders", hereinafter.)
Although quasi-drug-grade powders have, as a quality standard, a relatively high purity as high as 98.0% by weight or higher in terms of the purity of ascorbic acid 2-glucoside and retain a satisfactory free-flowing ability as a powder (throughout the specification, "powder(s)" means "particulate composition(s)", unless specified otherwise") just after production, they have the defect that they may solidify due to their dead load or moisture absorbency, when allowed to stand under a relatively high temperature and humid conditions for a relatively long period of time. Considering such defect, conventional quasi-drug-grade powders have been commercialized being packed in polyethylene bags by 10 kg aliquots thereof and placed, along with desiccants, in steel cans with covers. Even with the form of such product form, quasi-drug-grade powders, however, still have the problem that they may occasionally solidify and lose their usefulness as powders, when stored for a relatively long period of time. Solidification of particulate compositions, which contain anhydrous crystalline ascorbic acid 2-glucoside to be used as a material for cosmetics, quasi-drugs, or food products, may usually cause troublesome event in the steps of, for example, transporting, sieving, or mixing materials, when a production plant is designed on the premises that materials with satisfactory free-flowing ability will be used.

Particulate composition containing anhydrous crystalline 2-O-alpha-D-glucosyl-L-ascorbic acid, process for producing the same, and uses thereof


A flexible display panel, comprising: a first flexible substrate and a second flexible substrate cell-aligned to each other; a blue phase liquid crystal layer disposed between the first flexible substrate and the second flexible substrate and strip electrodes arranged on the second flexible substrate at a side close to the blue phase liquid crystal layer at intervals; a reflective layer disposed on the second flexible substrate at a side far away from the blue phase liquid crystal layer; and a ¼ wave plate and a polarizer successively arranged on the first flexible substrate at a side far away from the blue phase liquid crystal layer, with an included angle between a light transmitting axis of the polarizer and an optical axis of the ¼ wave plate being 45° and an included angle between each of the strip electrodes and the optical axis of the ¼ wave plate being 90°.

At present, Liquid Crystal Displays (LCDs) have become mainstream display products in market due to their excellent performances and mature technologies.
As one key component in a liquid crystal display, a liquid crystal panel is mainly formed by cell alignment of a color filter substrate and an array substrate, and liquid crystal is filled between the color filter substrate and the array substrate to form a liquid crystal cell. In order that the liquid crystal panel can realize normal display, liquid crystal is required to have a function of changing the polarization state of light, that is, the polarization state of light is changed by an optical delay generated by the liquid crystal and thus bright and dark display is realized. Moreover, the function of the liquid crystal of changing the polarization state of light depends on the optical delay Δnd (where Δn is a difference between the refractivity in a slow axis direction and the refractivity in a fast axis direction of the liquid crystal and d is the thickness of the liquid crystal cell) of the liquid crystal. Ideally, the thickness d of the whole liquid crystal cell should be identical, so that the controllability and uniformity of the display effect are ensured. Therefore, the control of the thickness of the liquid crystal cell is of great importance to the liquid crystal display.
In addition, to meet the demand of market, there are more and more researches on flexible display and flexible display products, and flexible liquid crystal displays are also widely researched and tried. For flexible liquid crystal displays, one of key problems is that it is difficult to ensure the controllability and uniformity of the display effect because the thickness d of a liquid crystal cell is difficult to maintain during deflection.

Flexible display panel and flexible display


A system for regulating temperature of a developer is provided. The system includes a plurality of optical fibers, each optical fiber directing radiation to respective portions of the developer. Radiation reflected from the respective portions are collected by a measuring system which processes the collected radiation. The reflected radiation are indicative of the temperature of the respective portions of the developer. The measuring system provides developer temperature related data to a processor which determines the temperature of the respective portions of the developer. The system also includes a plurality of heating devices; each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the developer.

In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller features sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the coating through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Due to the extremely fine patterns which are exposed on the photoresist, application and maintaining a desired temperature of the developer are significant factors in achieving desired critical dimensions. The developer should be maintained at a uniform temperature in order to insure uniformity and quality of the underlying photoresist layer to be developed. Small changes in the time/temperature history of the developer can substantially alter image sizes, resulting in lack of image line control--a few degrees in temperature difference may drastically effect critical dimensions. For example, often substantial line size deviations occur when the developer temperature is not maintained within 0.5 degree tolerance across a silicon wafer.
An efficient system/method to maintain developer temperature is therefore desired to increase fidelity in image transfer.

CD uniformity by active control of developer temperature


The present invention relates to a high speed transmission cable that includes a first conductor set, a dielectric film at least partially concentrically disposed around the first conductor set and a pinched portion forming an insulating envelope around the first conductor set. The dielectric film includes a base layer having a plurality of first protrusions formed on a first major surface of the base layer, wherein the dielectric film is disposed such that the base layer is partially concentric with the conductor set and wherein a portion of the first protrusions is disposed between the first conductor set and the base layer in a region where the base layer is concentric with the first conductor set.

Electrical cables for the high speed transmission of electrical signals are well known. One common type of electrical cable is a coaxial cable. High speed transmission cables generally include an electrically conductive central conductor(s) or wire(s) surrounded by an insulating dielectric layer. An exemplary high speed transmission cable is a coaxial cable. In a coaxial cable, the electrically conductive conductor and insulating dielectric layer can further include an outer conductor and a protective outer jacket.
The insulating dielectric layer can be composed of any material or combination of materials that electrically separate the central conductor from other conductors within the cable. The material properties of the dielectric layer can significantly affect the transmission of the electrical signal along the length of a high speed transmission cable. Minimal interaction between the electric field and the dielectric layer is generally desired to maintain the signal integrity and to reduce the capacitance of the electrical signal. Capacitance slows the propagation rate of the electrical signal and reduces the signal strength. Additionally, capacitance is a strong contributor to the cable's impedance, and therefore the dielectric layer has the role of influencing the magnitude and uniformity of the cable impedance, which is generally desired to be a constant along the length of a given insulated wire. Key electrical properties influenced by the material properties of the dielectric layer include signal attenuation, signal propagation rate, capacitance per given cable length, impedance, and the uniformity of these electrical properties along the length of the cable. Conversely, it may be desirable for the cable to have prescribed electrical properties, such as a known impedance value. Prescribing these electrical properties will impact the structure and dimensions of the dielectric layer. The dielectric structure and the material's dielectric constant will directly influence the required thickness of the dielectric layer and hence the cable diameter, the cable flexibility, and related properties.
For example, the velocity of propagation (VOP) of electrical signal along a coax cable relative to the speed of the electrical signal along a conductor surrounded by air is:
      V        O        P    =      1                  ɛ        eff
where εeff is the effective dielectric constant of the dielectric layer surrounding the central conductor. The dielectric constant of air is virtually equal to one while solid dielectric materials have a dielectric constant of greater than one. In order to maximize the velocity of propagation of the electrical signal, the effective dielectric constant of the dielectric layer should be minimized. The inclusion of air into the dielectric layer is one way to reduce the effective dielectric constant of the dielectric layer.
Although electrical properties of the transmission cable generally improve with the incorporation of air into the dielectric structure, air alone (at ambient pressure) can not provide adequate support to counteract external forces that can be applied to the cable during manufacture, installation and use of the cable. Failure to support the external load at any point can result in local distortions of the spacing between the central conductor and surrounding structures of the cable, thereby changing the distribution of the electric and magnetic fields around the central conductor, creating local impedance changes which can result in signal reflections and degraded signal integrity. If these distortions are significantly large (like a kink in the cable) or numerous, the cable may no longer be suitable as a high speed transmission line. Because air alone is not a sufficient support, the dielectric layer will also include a higher stiffness material form and maintain the space between the inner conductor and the surrounding structures of the cable.
Three types of dielectric layer structures which include a significant amount of air surrounding the central conductor are routinely practiced in the art: A) foamed and expanded polymers, B) thin helically wound monofilaments and, C) axially-extruded channels.
Foamed or expanded structures can have air content up to about 70% resulting in an effective dielectric constant to 1.3-1.5. However, the stiffness of the resulting dielectric layer can be quite low, and may fail to provide sufficient support to the central conductor under applied loads and may allow the central conductor to kink when tightly bent. When loaded, these structures readily buckle and crush.
The helically-wound structures typically utilize a monofilament or deviations thereof that are wrapped around a central conductor. An insulator tube is extruded over the wrapped conductor structure. These helically-wound structures can also have low effective dielectric constants (−1.3), but typically provide support against external forces at one point around the circumference of the central conductor at any given cross-section. This individual contact point can also be insufficient to support external load exerted at any point around the circumference of the central conductor that is not directly adjacent to the wrapped filament which can lead to local deformations or kinking of the central conductor on bending and result in attendant signal integrity issues.
The third type of dielectric layer structures which include a significant amount of air are longitudinally extruded structures formed along the conductor axis with a modified extrusion tip. These extruded structures can generally result in an effective dielectric constant of 1.45 or higher, but the axial extrusion process of a molten polymer is not well-suited to providing small, closely-spaced features since surface tension and the dynamics of extruding a liquid material in this manner drives rounding of the features. Additionally, this process cannot readily form features that vary along the axial direction, (i.e. each cross section profile is the same). Also, the process is limited to materials that can be extruded around a conductor at the required thickness.
In summary, the prior art dielectric structures do not have sufficient ability to provide low effective dielectric constants combined with sufficient mechanical integrity and design flexibility. A need exists for high speed transmission cables that include a dielectric layer that incorporates a significant amount of air adjacent to and around the central conductor while providing more uniform support around the central conductor resulting in a dielectric layer having greater mechanical stability while simultaneously having a low effective dielectric constant.


Communication networks and methods are disclosed for delivering messages over LTE networks. One embodiment comprises a universal message center operable to deliver messages over an LTE network. The universal message center receives a message intended for a destination mobile device, and determines if the destination mobile device is LTE enabled. If the destination mobile device is LTE enabled, then the universal message center identifies a mobile IP address assigned to the destination mobile device in the LTE network. The universal message center then attempts to forward the message to the destination mobile device over the LTE network based on the mobile IP address. If the destination mobile device is not LTE enabled, then the universal message center identifies a store-and-forward (SFD) message center for an originator of the message, and forwards the message to the SFD message center for store-and-forward processing.

1. Field of the Invention
The invention is related to the field of communication networks and, in particular, to message delivery over LTE networks.
2. Statement of the Problem
Service providers provide numerous voice and/or data services to subscribers using mobile devices, one of which is text and multimedia messaging. In many mobile networks, text/multimedia messaging has become a very popular mode of communication. One example of a text messaging service is Short Message Service (SMS), which is a communication protocol allowing the exchange of short text messages (i.e., 160 characters) between mobile devices. One example of a multimedia messaging service is Multimedia Message Service (MMS), which is a communication protocol allowing the exchange of multimedia messages (i.e., digital pictures, media clips, etc) between mobile devices. Often times, mobile users more frequently use text or multimedia messaging for communication than voice calls.
There are a variety of types of networks operable to provide voice and data communications for mobile users. The 3rd Generation Partnership Project (3GPP, 3GPP2) puts forth specifications defining standards for communicating over these networks. One present project within the 3GPP is the Long Term Evolution (LTE) which is a project to improve the UMTS mobile phone standard to cope with future requirements. The architecture defined by this project is referred to as the Evolved Packet System (EPS). The EPS architecture comprehends E-UTRAN (Evolved UTRAN) on the access side and EPC (Evolved Packet Core) on the core side.
Presently, the 3GPP specifications rely on legacy Short Messaging Service Centers (SMSC) and Multimedia Messaging Service Centers (MMSC) for message delivery. Legacy SMSCs and MMSCs are not able to deliver messages to a mobile device over an LTE network. Thus, even if a mobile device is registered with an LTE network, the mobile device is not able to receive SMS or MMS messages over the LTE network.


An apparatus useful in the assembly of printer cartridges includes a plurality of accumulator bags removeably secured to a carrier sheet. Each accumulator bag includes a first polymer film panel and a second polymer film panel welded together to form a pressurizable chamber with an aperture formed in the bag to provide access to the pressurizable chamber. An annular adhesive element is secured to each bag such that an aperture of the annular adhesive element is generally concentric with the aperture of the accumulator bag. The carrier sheet includes an upper adhesive stripe, a lower adhesive stripe, and a silicone stripe. The plurality of accumulator bags is removeably secured to the carrier sheet by adhering an upper portion of each bag to the upper adhesive stripe, adhering a lower portion of each bag to the lower adhesive stripe, and positioning the annular adhesive element in contact with the silicone stripe.

Digital and computer controlled printers often utilize printer cartridges to deposit ink onto media such as paper, cardboard, plastics, clothing, and other such materials. Within a printer cartridge, ink is typically stored in an ink reservoir and is deposited onto media through a print head. The printer and, thus, the printer cartridge can be arranged to be in either an idle state or a printing state. While in an idle state, the printer is dormant and awaiting instructions to print. While in a printing state, the printer is processing instructions and actively printing onto media.
The internal pressure of the ink reservoir can be important for both the idle state and the printing state. While in an idle state, the internal pressure of the ink reservoir is typically less than the pressure required to dispense ink through the print head. This is so that ink from the ink reservoir does not unintentionally leak or drop from the print head when the printer is not directed to print. While in a printing state, the internal pressure of the ink reservoir is typically greater than the pressure required to dispense ink through the print head. This is so that ink from the ink reservoir is dispensed through the print head and deposited onto media when the printer is directed to print.
Print cartridges are often equipped with an accumulator assembly to regulate the pressure applied to the ink reservoir. Accumulator assemblies typically include one or more accumulator bags. Accumulator bags can be arranged to apply a generally constant pressure to ink reservoirs during both idle states and printing states. While the printer is in an idle state, an accumulator bag can apply a back pressure to the ink reservoir so that the internal pressure in the ink reservoir is less than the pressure required to dispense ink through the print head. While a printer is in a printing state, an accumulator bag can apply a positive pressure to the ink reservoir so that the internal pressure in the ink reservoir is greater than the pressure required to dispense ink through the print head.

Accumulator bag and carrier sheet for use in manufacturing printer cartridges and methods of making same


A system and method for calibrating a pyrometer used in temperature detection in a chemical vapor deposition system is provided. A calibration wafer with a reference region including a metal such as Al or Ag for forming a eutectic, and an exposed non-reference region without such a metal, are provided. Reflectivity measurements are taken from the reference region, and temperature measurements are taken from the non-reference region, over a range of temperatures including a known melting point for the metal eutectic. The pyrometer is calibrated based on the correlation of the known eutectic melting point with the change in reflectivity data obtained in the reference region, in light of the temperature data obtained from the non-reference region.

The present application relates to systems and methods for pyrometry calibration, and more particularly relates to systems and methods for calibrating pyrometers for use in chemical vapor deposition systems using reflectivity and temperature measurements obtained from a eutectic calibration target.
Accurate temperature readings are essential for many industrial processes such as, for example, epitaxial growth of layers on wafers in susceptor-based chemical vapor deposition ("CVD") systems. Uniform deposition in such systems is dependent on even temperature distribution along with other variables such as, for example, reactor pressure, reactant gas ratios, reactant gas flow rates, and the like. Thus, accurate in situ measurements of CVD reactor temperature are desirable. These temperature measurements preferably should be accurate enough to ensure uniform deposition of layers of material on wafers to be processed.
To measure temperature in CVD systems, a high temperature non-contact thermometry device such as a pyrometer may be employed. A pyrometer detects temperature by measurement of emissions from the internal surfaces of a CVD reactor.
To ensure the accuracy of pyrometer readings, though, the pyrometer should be properly calibrated to a temperature scale. Calibration devices can employ bonded thermocouples, emissivity detectors, and/or can employ these techniques in combination with calibration wafers that exhibit known properties at particular temperatures. In some pyrometer-based temperature measurement systems, calibration of the pyrometer sometimes requires that the pyrometry system be taken off-line - or in some circumstances even off-site during recalibration. Such off-site time or off-line time can result in decreased efficiency through lost processing time.
Some calibration systems employ a eutectic calibration wafer with a layer of material that melts into a eutectic at a known temperature. By measuring the temperature of the wafer using the pyrometer, and observing the layer to determine when melting occurs. These systems can be used to calibrate the pyrometer in place on the CVD apparatus, and can approximate the temperature of the melting and correlate the melting point of the eutectic to the measurements obtained by the pyrometer. For example, melting can be observed by monitoring reflectivity of the surface to detect the change in reflectance due to melting.
A problem with these systems as they currently exist is that the pyrometer is attempting to determine temperature readings from surfaces that typically have low emissivity because of their metal contents, making temperature difficult to read accurately.
Accuracy may also be reduced because at the point of melting of the eutectic wafer, other changes in phase, emissivity, and reflectivity may occur that could interfere with accurate temperature measurements and calibration. In addition, many eutectic wafers require a complex, many-layered design, raising quality control issues and making the wafers more expensive to produce.
What is needed is a pyrometer calibration system for a heated environment that solves these problems while providing accurate, simple, efficient and non-interruptive calibration of a pyrometer.

Calibration wafer and method of calibrating in situ temperatures


A screen printer 100 for paste material printing is disclosed herein. In a described embodiment, the screen printer 100 comprises a printing chamber 104; and a plurality of support members in the form of lifting tables 114, 116 arranged adjacent to one another along a single conveying path for individually supporting a respective PCB 202, 240 in the printing chamber 104. The screen printer 100 further includes a stencil 120 having a plurality of print patterns 124, 126 with each print pattern 124, 126 arranged adjacent to another print pattern to correspond to the positions of the lifting tables 114, 116 with each print pattern 124, 126 corresponding to a desired paste pattern to be printed onto the PCBs. The screen printer 100 also includes a paste printer arranged to print paste material on the at least one substrate using at least one of the print patterns. A screen printing method is also disclosed.

This invention relates to a screen printer, more particularly but not exclusively, for the printing of paste material. This invention also relates to a screen printing method.
In a conventional surface mount technology ("SMT") production line, there is usually one screen printer. However, two or more screen printers may be used to achieve a higher throughput, especially when printing high-volume consumer products such as printed circuit boards ("PCBs") for mobile phones, automotive components etc. Having more than one screen printer is useful in high mix environments where batch sizes are smaller and the number of line changeovers is higher since when one printer is being reconfigured, the other printer may continue in operation and this reduces line downtime. However, when there is a lull period, the value of the screen printing goes up as compared to the costs of the total line since the two printers are not utilized to their maximum capacity.

Apparatus for paste material printing, and printing method


A method of correlating a plurality of event logs surrounding abnormal program termination of a plurality of networked computers, includes continuously generating event records that includes operating system events, information technology (IT) infrastructure events and program application events, transmitting and storing the event records to a monitoring database, generating and transmitting an abnormal program termination event record when a computer experiences abnormal program termination to the monitoring database, and synchronizing the stored event records and the abnormal program termination event record of the computer based on receiving the abnormal program termination event record at the monitoring database, and with respect to the abnormal program termination event record. The method further includes creating and storing a specific synchronized event log based on the synchronizing of the event records and comparing it with previously stored synchronized event logs to determine if one of a match and a specific degree of similarity exists.

1. Field of the Invention
The present invention generally relates to reducing application MTBF (mean time before failure) rates in large-scale and/or widely distributed PLM (product lifecycle management) applications within an IT (information technology) infrastructure environment by the generation and extraction of data from workstations within the PLM environment that experience abnormal program termination.
2. Description of the Related Art
Current IT departments are not able to create an accurate problem description of an abnormal program termination since they traditionally only have access to abnormal program termination logs that are incapable of creating a comprehensive and detailed event history in the workstation leading up to the abnormal program termination of an application.
In a PLM environment, each designer has his own workstation with a PLM application running on it. While the PLM application is running, the application may experience an abnormal program termination, known as an "abend," (abnormal end), from time to time. In most cases, the designer will not inform the IT department about this crash, but will reboot the workstation on his own and continues with his work. At the time of the abend, the PLM application creates a log detailing the nature of the abend. This situation may happen hundreds of times with workstations across the PLM design department or a multi-location collaborative environment. These abends, and their lack of proper reporting, cause significant deterioration of performance of individual design departments and the total PLM environment.
The IT department typically recognizes the abend logs some time after the occurrence of the abend. The IT department may create problem descriptions for these abends to supply a correction from the software supplier, via a PMR (problem record). To create a problem report, the IT department needs to know the statistically significant pattern of events surrounding abnormal program termination. Normally, statistics on these pattern of events must be created manually to determine which set of abnormal program termination events need to be prioritized for fixing.
Currently, there is no information collected immediately preceding the abnormal program termination detailing the events that occur in the operating system (OS) and the IT-infrastructure of a workstation.
Without this information, statistically significant groups of events leading to abnormal program termination cannot be accurately determined and meaningfully analyzed in conjunction with OS and IT-infrastructure events.

Method for determining correlation of synchronized event logs corresponding to abnormal program termination

International Business Machines Corporation


The present patent application provides an interference cavity for precisely controlling an optical path including a cavity formed by two equal distance arms, wherein a positive adjusting plate and a negative adjusting plate are disposed in the interference cavity for compensating the change of a cavity length with temperature and thereby ensuring that the interference cavity length is a constant. The present patent application utilizes the matching relationship between the change of the refractive index of the positive adjustment plate with the temperature and the change of the refractive index of the negative adjusting plates with the temperature to make the optical path difference OPL invariant with changes in the environment temperature and thereby to ensure the precision of the optical path.

In the field of optical communication, differential phase-shift keying (DPSK) is a promising modulation scheme that provides high receiver sensitivity, high tolerance for main nonlinearities in high speed transmission and coherent crosstalk. The appearance of the interleaver technologies upgrades the design concept of wave separating/combining devices in dense wavelength division multiplexing (DWDM) and greatly reduces the design pressure of dense wavelength division multiplexor, while these devices are based on interferometers. The interferometer enables two light beams to transmit with the optical path difference (OPD) thereof being an expected value. However, the control of the interference cavity length difference is difficult. The change of the optical path difference directly affects the light interference intensity, thus the ambient temperature needs to be controlled so as to ensure the stability of the optical path difference. To balance the change due to the environment temperature variation, U.S. Pat. No. 6,924,894 discloses through disposing two heater and environment temperature sensors connected with a controller at the two interference arms, controlling the heaters and thereby balancing the influence of the environment temperature. This means must use complex electric circuits to eliminate the influence of the environment temperature. The cost is relatively high and the electric circuits are complex.

Interference cavity for controlling optical path


A process for the production of 4-hydroxybutyraldehyde is described. The process comprises reacting allyl alcohol with a mixture of carbon monoxide and hydrogen in the presence of a solvent and a catalyst system comprising a rhodium complex and a 2,3-O-isopropylidene-2,3-dihydroxy-1,4-bis[bis(3,5-di-n-alkylphenyl)phosphino]butane. The process gives high yield of 4-hydroxybutyraldehyde compared to 3-hydroxy-2-methylpropionaldehyde.

The hydroformylation of allyl alcohol is a well-known and commercially practiced process. See, for example, U.S. Pat. Nos. 4,064,145, 4,215,077, 4,238,419, 4,678,857, and 5,290,743. In the hydroformylation reaction, allyl alcohol is reacted with a CO/H2 gas mixture in the presence of a catalyst to form 4-hydroxybutyraldehyde (HBA). The HBA may then be separated from the catalyst, e.g., by water extraction, and hydrogenated to form 1,4-butanediol (BDO). See U.S. Pat. No. 5,504,261.
Various catalyst systems have been employed for the hydroformylation reaction, most notably a rhodium complex together with a phosphine ligand (see, e.g., U.S. Pat. Nos. 4,064,145, 4,238,419, and 4,567,305). Commonly employed phosphine ligands are trisubstituted phosphines such as triphenyl phosphine. One disadvantage of the hydroformylation process is that other co-products or byproducts are also formed in addition to the desired HBA linear product. The hydroformylation of allyl alcohol typically produces some 3-hydroxy-2-methylpropionaldehyde (HMPA) branched co-product and C3 byproducts such as n-propanol and propionaldehyde. Although HMPA may be hydrogenated to produce 1,3-methyl propanediol (MPD), which is a useful material, the MPD co-product reduces the yield of BDO. Formation of the C3 byproducts effectively represents another yield loss in the process which can have a severe adverse effect on the process economics.
To increase BDO yields, research continues to improve the hydroformylation process and reduce less desired co-product/byproducts. U.S. Pat. No. 6,127,584 discloses the use of a trialkyl phosphine ligand having at least 2 methyl groups results in increased HBA:HMPA ratio. The use of disphosphine ligands has also been found to improve the HBA:HMPA ratio. The hydroformylation of allyl alcohol using rhodium complex catalysts and DIOP diphosphine ligand is shown in the art, notably in Japan Kokai Nos. 06-279345 and 06-279344 and U.S. Pat. No. 4,306,087. In addition, U.S. Pat. No. 6,225,509 discloses that maintaining the concentration of CO in the reaction liquid above about 4.5 mmols/liter reduces the make of undesirable C3 co-products in the hydroformylation of allyl alcohol using a catalyst comprised of a rhodium complex and a ligand such as DIOP.
In sum, new processes for the hydroformylating allyl alcohol to produce 4-hydroxybutyraldehyde are needed. Particularly valuable processes would result in high ratios of 4-hydroxybutyraldehyde (HBA) compared to 3-hydroxy-2-methylpropionaldehyde (HMPA).


A gel-like emulsion is prepared by adding an oil to a surfactant continuous phase formed of a monoalkyl phosphate salt, polyhydric alcohol and water.. The gel-like emulsion is scarcely dependent on temperature, and a fine and uniform O/W emulsion prepared from the gel-like emulsion reveals excellent stability at the time of production and at storage. The gel-like emulsion contains only a small amount of alkyl phosphate surface active agent of low irritativeness, so that it is usable for cosmetics, pharmaceuticals, industrial products and the like, which are required to have low irritation and high safety.

1) Field of the Invention
This invention relates to a gel-like emulsion comprising a surface active agent phase as a continuous phase. More particularly, the invention relates to a gel-like emulsion which can readily yield O/W emulsion of high quality by addition of an aqueous phase and to the thus obtained O/W emulsion.
2) Description of the Prior Art
Emulsification methods for obtaining a fine, uniform emulsion generally include a phase inversion emulsification method using nonionic or ionic surface active agents and a gel emulsification method using nonionic surface active agents.
According to the phase inversion emulsification method, a surface active agent is dissolved or dispersed in oil, followed by addition of water phase to the system. As water phase is added, the system is inversed from a W/O state to an O/W state. Through this phase inversion, a fine and uniform emulsion is obtained.
However, there is a limit to an amount of the oil which can be emulsified by a certain amount of surface active agent, and relatively a large amount of surface active agent is required to obtain an emulsion consisting of fine particles. Further, in order to obtain an emulsion in a proper state, it is necessary to adjust a hydrophilic lipophobic balance (HLB) of the surfactant system depending upon a type of oil to be emulsified. In addition, since a particle size of emulsion depends largely on mechanical shear which is imposed to the system during the emulsification, there are some cumbersome problems for determining conditions for the emulsion preparation.
According to the gel emulsification method using nonionic surface active agents, O/W emulsions are obtained by dissolving a nonionic surface active agent in a water-soluble solvent with or without addition of an aqueous phase to give a continuous surface active agent phase, gradually adding an oil to the continuous phase to obtain a gel-like emulsion, and further adding water to the gel-like emulsion. A fine and uniform emulsion can be obtained by this method, however it is necessary to select a proper nonionic surface active agent suitable for the oil to be emulsified. Since H/L balance of a nonionic surface active agent is much affected by temperature, the state of emulsion also depends upon the emulsification temperature. Therefore, in preparing and preserving the above described gel-like emulsion, as well as in producing an O/W emulsion by using the gel-like emulsion and preserving it, temperature is one of very important factors with regard to the emulsion stability. For instance, there is a case where even if a gel-like emulsion can be formed at a low temperature, it cannot be formed at a higher temperature, or an O/W emulsion prepared by a gel-like emulsion is unstable at a high temperature. The gel emulsification method using nonionic surface active agent thus involves such disadvantages on production and quality of emulsion.

Gel-like emulsion and O/W emulsion obtained from the gel-like emulsion


A phase change memory using an ovonic threshold switch selection device may be programmed from one state to another by first turning on the ovonic threshold switch. After the voltage across the cell has fallen, the cell may then be biased to program the cell to the desired state.

This relates generally to phase change memories.
As used herein, a phase change memory is a device which uses a chalcogenide material as a memory element. A memory element is the element that actually stores information. Thus, as used herein, a phase change memory stores information on a memory element by changing the phase of the element between amorphous and crystalline phases. Generally, the amorphous phase is associated with what is called a reset state and the crystalline state is associated with what is called a set state. Multilevel memories may have a number of states intermediate between set and reset states.
In the programming operation, a phase change memory may be transitioned through the application of bias voltages and resulting currents to transition from amorphous to crystalline states or from crystalline to amorphous states. Generally, in these transitions, it is desirable to only change the phase of the cells you want to change and not the cells that you do not want to change.
Phase change memories are arranged in what is called a cross point memory where address lines are arranged in a grid. These address lines, normally called the bitline and word line, cross and memory elements span between the word lines and the bitlines. Generally, to select a memory element, a select device is added to each memory cell. That is, a memory cell may include a series connected select device and memory element.
In some phase change memories, an ovonic threshold switch is used as the select device. The ovonic threshold switch includes a chalcogenide material that does not change phase. Thus, the ovonic threshold switch does not meet the definition of a memory element set forth above.

Programming phase change memories using ovonic threshold switches


A network monitoring and network congestion analysis can be performed based on a comparison of data packets at multiple different network nodes installed at different locations on a communication path. A downstream network node may be installed at a user location while an upstream network may be installed at an access router further up the network. A network congestion analyzer may receive data packet information including timestamps from both network nodes, and may compare the data packet information to group the data packets into application flows and match the corresponding packets from the different network nodes. Based on the data packet matching, the network congestion analyzer may calculate packet loss, packet delay, packet delay variation, and perform other network congestion analysis techniques for the application flows corresponding to a user's various devices and the applications executing on those devices.

Modern network environments often include several different computing devices at an end user's location connected to an external network over a single communication path. For example, a user's home or office may have multiple computers, televisions and set-top boxes, mobile devices, gaming consoles, and other communication devices connected to an interface such as a gateway and/or modem, so that the devices compete for network bandwidth. Users typically purchase a finite amount of upstream and downstream bandwidth from a network provider, and these amounts may be enforced by the user's gateway or other network component. When the combined network usage of the user's devices exceeds the available bandwidth, the user may experience delays and performance degradation on one or more of the devices. However, the user may have no way of determining which network devices are taking up significant amounts of bandwidth at that particular time. Moreover, the user might not even be sure that the performance problems are related to the user's bandwidth limitations. For example, the user may suspect that the performance problems of the devices are caused by congestion further upstream on the network (e.g., at a shared access router, central office, etc.), or by problems within the devices themselves (e.g., hardware malfunctions or software errors).
Thus, although a user may attempt to remedy performance problems, neither the user nor the provider may know the precise cause or location of the performance problems. One attempted solution is for the user to purchase additional bandwidth from the network provider. However, this solution is entirely speculative and will not correct the user's problem if the cause of the problem is within the devices themselves, or if the problem is further upstream on the network. Thus, the user will be reluctant to make the additional purchase without greater assurance that the additional bandwidth will correct the problems with the user's devices. Additionally, if the performance problems are caused by excessive bandwidth usage of one of the user's devices, then simply purchasing more bandwidth will not allow the user to identify the offending device or reconfigure the device to correct the problem.
Accordingly, there remains a need for network monitoring and network congestion analysis techniques that support additional abilities to coordinate growing numbers of user devices and applications that compete for finite network bandwidth.

This patent is subject to a terminal disclaimer.


Methods for modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device, and methods for fabricating an integrated circuit, are provided. In an embodiment, a method includes providing a circuit design layout that has a plurality of element patterns. A first library of problematic sections is provided. An initial circuit section and an additional circuit section within the circuit design layout are determined to match problematic sections in the first library, and the initial and additional circuit sections have overlapping peripheral boundaries. A second library of replacement sections is provided. The replacement sections correspond to the problematic sections. The circuit sections that match the problematic sections are replaced with a replacement section that corresponds to the respective problematic sections to form the final circuit layout. Boundary characteristics of the replacement sections are substantially the same as the circuit sections replaced thereby.

Modern integrated circuits (ICs), can include millions of transistors fabricated in and on a semiconductor substrate. In making a mask to fabricate such a complex device, a circuit design layout will pass through a variety of filters, checks, and modifications before being taped out to a mask. Ideally, the process results in a mask that is used to lithographically fabricate a final circuit design layout on a semiconductor substrate without printing defects and without defects in the fabricated final circuit layout.
The circuit design layout may contain standard cells and standard device designs as well as new cell and device designs, and generally complies with rigid design rules that include minimum feature size, minimum spacing between device elements, and the like. To improve functional and yield characteristics of the circuit design layout, the circuit design layout generally passes through multiple simulations, many of which are time consuming. Short cuts are available to reduce simulation time, and hence cost, without sacrificing accuracy of the final circuit layout. One method for providing approximate but fast evaluation of sensitivity of the circuit design layout to lithographic effects that can affect variability and yield is pattern matching. Pattern matching is particularly known for use to determine lithographic or printability problems. Printability problems are problems in which a circuit design layout on a mask, for example a particular array of lines and spaces, cannot be accurately reproduced in or on a semiconductor substrate by etching through the circuit design layout on the mask. In conventional pattern matching techniques, element patterns in the circuit design layout that are known to cause printability problems are first identified by comparing element patterns in the circuit design layout at sensitive locations to a library of problematic element patterns. The library of problematic element patterns is generally developed in collaboration between a design house and their foundry partner and is further recorded to enable the problematic element patterns to be avoided in implementing future designs or design revisions. In practice, an evolving layout pattern can be subjected to pattern matching software to identify patterns in the layout design that are similar to the library patterns.
Upon identifying element patterns in the circuit design layout that are similar to problematic element patterns in the library, existing techniques involve changing the problematic element patterns through a global rule change that is applied based upon the identified defect in the problematic element pattern. In particular, the global rule change involves modifying a particular design parameter that is responsible for the problems associated with particular problematic element features, with the modification applied across the entire circuit design layout. However, the global approach to modifying the entire circuit design layout may result in modifications to the circuit design layout that may be unnecessary or that may cause unintended problems at various locations within the circuit design layout.
Accordingly, it is desirable to provide methods for modifying the physical design of an electrical circuit used in the manufacture of a semiconductor device that enables a local approach to alleviating problematic element patterns and that avoids unintended modifications to the circuit design layout that may be unnecessary or that may cause unintended problems after modification of the problematic element patterns. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

Methods of modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device


A device for closing a motor vehicle front end air intake is disclosed. The device has a support frame in which at least one set of pivoting slats is installed. At least one control element that controls the positioning of the slats includes an actuator having fixing holes, a housing that receives the actuator, and a cap that comes to cover the housing. The cooperation between the cap and the housing being effected by clipping. The housing includes positioning elements to be inserted into the fixing holes, and the cap includes at least one specific shape that keeps the actuator fixed relative to the positioning elements when clipping the cap onto the housing.

The front panels of motor vehicles are generally made up of two main air intakes, referred to as the high channel and the low channel, separated by a bumper. Generally placed behind this bumper are heat exchangers of the motor vehicle, such as for example that for air conditioning the passenger compartment and/or that for cooling the engine.
It is also known to dispose in the paths of air passing through the main air intakes, and more generally the low channel, a support frame including a multiplicity of slats mounted to pivot about parallel axes and able to assume a multiplicity of different angular positions between an open position and a closing position inclusive, under the control of appropriate control means, thereby forming a closing device similar to a venetian blind. This closing device is sometimes referred to as an active grille shutter or controlled air intake module. A closing device of this kind may also be referred to as an AGS (standing for active grille shutter).
The closing device enables adjustment of the flow rate of air through the air intakes and reaching the heat exchangers. It is therefore possible to optimize the efficacy of those heat exchangers as a function of what is required by varying the quantity of air that they receive. Moreover, the slats in the closing position make it possible to reduce the drag coefficient of the motor vehicle and thus to improve the aerodynamics of said motor vehicle. The closing device therefore makes it possible to reduce energy consumption and pollution if the engine does not need to be cooled by air from the outside.
The closing device conventionally comprises an actuating device (also referred to as an actuator or motor) controlling the slats and enabling opening or closing of the air intake: the slats are open when the engine of the motor vehicle needs to be cooled and the slats are closed when the engine of the motor vehicle is cooled sufficiently.
Known in the prior art are housings on the support frame intended to receive the actuator. However, the actuator is installed in that housing and retained by means of fixing screws. Fixing screws of this kind are additional components of the closing device. Moreover, the use of these fixing screws necessitates a specific assembly step during the manufacture of the closing device, and that specific step therefore increases the time to manufacture this closing device and therefore has a cost. Also, during manufacture of this closing device it is possible to encounter problems linked to the travel of the screws or to screwing in these fixing screws that can lead to manufacturing defects of the closing device necessitating rejection of this closing device. Also, such fixing screws may become detached from the support frame because of vibrations that the closing device may suffer during operation of the motor vehicle for example. This detachment may compromise the correct functioning of the closing device and can damage the actuator.

Device for closing an air intake of a motor vehicle and method for manufacturing such a closing device


A method and system for displaying program representation. Program rating information derived from a plurality of identified users regarding a plurality of programs is obtained. A social rank of the plurality of programs is determined based on the rating information. A plurality of program representations are displayed to a viewer, wherein the program representations represent corresponding ones of the plurality of programs and wherein a differentiating visual characteristic of each of the plurality of program representations is based on the social ranking.

Today's content providers, such as cable companies, provide hundreds of programming channels for viewers. Consequently, selecting a program to watch can be daunting. Because friends frequently have common interests, it would be useful at times to know what your friends, or like-minded people, are watching, or have otherwise indicated that they enjoy. Having access to such information with respect to current program options would quickly distinguish some programs from the hundreds of available choices. There is a need therefore, for a mechanism that provides a viewer an intuitive representation regarding how friends, or like-minded individuals, collectively rank programs which are currently available to be viewed.

Method and system for socially ranking programs


A media docking station and is provided. A detachable media-content-receiving receiving component (MCRC) includes a connector that mates with a connection port of a docking base. The connection port operationally receives the connector. The docking base is equipped with a plurality of communications ports for communicating media content to a receiving devices inputted thorough said communications ports. In an alternative embodiment, an adapter is provided for mating a conventional MCRC with a base member.

Not applicable.
Not applicable.
This invention is related to the field of docking bases. More particularly, the present invention provides a new and useful docking base for media set-top boxes.
Today, certain media content such as digital cable television (CATV) requires a set-top box, or some other form of media-content-receiving component (MCRC), to communicate an incoming signal to a television. Similarly, satellite TV often requires a set-top box. Moreover, a separate box is required for each wall outlet. A wall outlet is the communications port that communicates a data stream to the set-top box. Thus, one box is required for a TV in a living room and a second box is needed for a TV in a home office. In the alternative, a customer could laboriously detach all the communications-port connections interacting with the set-top box of one location and reconnect connections at a second site.
Thus, the current state of the art necessitates duplicating resources, including set-top boxes, and provides no easy way to migrate a connected box from one location to another. These exemplary shortcomings could be overcome by providing a method and system for conserving box resources and/or easily moving a box from one location to another.
The present invention solves at least the above problems by providing a set-top box docking-station system and method. Offering several practical applications in the technical arts, the present invention reduces the number of set-top boxes needed to view a media-content stream on different TVs and provides a new and useful way of easily transferring a set-top box from one location to another.
In a first aspect of the invention, a docking base is provided. The base has a receiving area that mates with a media-content-receiving component (MCRC). The receiving area has a connection port When the MCRC is placed into the base-member-receiving area, media content can be communicated through the base member and MCRC to a receiving device. Thus, the docking base can remain wired to an end-user""s wall, other devices, and television With multiple docking bases, only the MCRC need be removed and slid into another base.
In another aspect of the invention, an improved MCRC is provided. This MCRC has a connector to operationally couple itself to the docking base. Media content is communicated from said docking base to a receiving device when said MCRC is mated with said docking base.
In another aspect of the invention, an MCRC-docking system is provided. A detachable MCRC is equipped with a connector. A docking base has a connection port and can operationally receive the connector on the MCRC. Again, the docking base has a plurality of communications ports for communicating media content to a receiving device.
In another aspect of the invention, a media-component-docking adapter for coupling an MCRC to a docking base having a connection port is provided. The adapter has at least two sides. On one side, the adapter is equipped with a set of communications ports. These ports mate with the ports of the MCRC. On the other side of the adapter is a connection port which is used to mate the MCRC with the base unit The base unit is connected to the end-user""s cable outlet, media components, and display device. In this aspect, many adapters can be manufactured to mate specific MCRCs to the same docking station.
Finally, yet not exhaustively, a method for using a single set-top box between multiple bases to communicate media streams on multiple TVs is provided.


The present disclosure relates to a device-to-device (D2D) communication for direct communication between nodes in a wireless communication system, wherein an operation method of a terminal includes the steps of: generating sequences, which belong to an orthogonal sequence set, according to a sequence pattern corresponding to a priority of a link; and transmitting the sequences, as signals for measurement of a reception electric power of a counterpart terminal, through sub-blocks within a channel, wherein one sequence is transmitted through each of the sub-blocks.

In a D2D (Device-to-Device) communication environment, each node such as a mobile phone searches for another node physically adjacent to the node by itself, configures a communication session, and then directly transmits traffic to the counterpart node. Accordingly, the D2D communication distributes traffic concentrated on an evolved NodeB (eNB), and thus is spotlighted as an element technology of a next generation mobile communication technology, which can solve a traffic overload problem. Accordingly, a standardization organization such as 3GPP (3rd Generation Partnership Project) or IEEE (Institute of Electrical and Electronic Engineers) proceeds with a D2D communication standard based on LTE-A (Long Term Evolution-Advanced) or Wi-Fi (Wireless Fidelity).
In order to perform the D2D communication, a frame structure, a signal procedure, a scheduling procedure, and the like for direct communication between terminals should be defined in detail. Particularly, it is important to exclude interference to a cellular system or interference to D2D communication by other terminals. Accordingly, a technology, which has been known as the D2D communication, includes "FlashLinQ" of Qualcomm. The FlashLinQ defines a physical layer channel structure, a scheduling procedure, and the like for the D2D communication. Further, the FlashLinQ measures channel quality between terminals to perform the D2D communication for the scheduling procedure, and defines a reference for determining whether to perform communication based on the channel quality. More specifically, in the FlashLinQ, a transmission terminal transmits a DPS (Direct Power Signal) through an inherent single tone allocated to the transmission terminal and estimates received power and a SIR (Signal to Interference Ratio) through the DSP. Further, whether to perform the communication is determined based on the received power and the SIR.
As described above, whether to perform the communication is determined based on the signal transmitted through the single tone. Thereafter, the D2D communication is performed using a whole band for the D2D communication. That is, data communication through the whole band is performed based on channel quality estimated through the signal of the single tone. However, the channel quality estimated through the signal of the single tone provides inaccurate channel quality information on the whole band depending on a channel environment. For example, in a multi-path channel environment, there may be a large difference between reception channel power of the single tone and reception channel power of the whole band due to an influence of frequency selective fading. For example, the inaccurate measurement of the reception channel power is illustrated in FIG. 1. FIG. 1 illustrates an example of a result of channel measurement using a single tone power signal. Referring to FIG. 1, a terminal A 111 receives a DPS transmitted from each of a terminal B 112, a terminal C 113, and a terminal D 114 and estimates reception channel power. At this time, the terminal B 112, the terminal C 113, and the terminal D 114 transmit the DPSs through the single tone. Accordingly, depending on a frequency of the single tone, a measurement result different from average channel power may be made. Referring to FIG. 1, in a case of the terminal B 112, channel power lower than the average channel power may be measured using a frequency having channel power lower than the average channel power. However, in a case of the terminal C 113, channel power higher than the average channel power may be measured using a frequency having channel power higher than the average channel power.
As described above, by estimating the channel quality through the single tone power signal, a result different from the channel quality of the whole band may be created. In this case, when an SIR for an actual whole band is considered by inaccurate channel quality information, communication may be abandoned due to a measurement error even though the communication is possible. Alternatively, even though it is difficult to perform the communication, a scheduling process error, which attempts the communication due to a measurement error, may be generated. When the scheduling error is generated, a problem in terms of fairness may occur and also a transmission rate loss for entire cells may be caused.

Method and apparatus for measuring link quality in wireless communication system supporting device-to-device communication


The present invention relates to physically modified sago starch which exhibits an increased onset of gelatinization temperature and controlled viscosity development, yet retains significant hot and cold viscosity, the process of making such starch, and the use thereof. Such starches are useful in a variety of products, particularly as viscosifiers.

The present invention relates to physically modified sago starch which exhibits an increased onset of gelatinization temperature and controlled viscosity development, yet retains significant viscosity, the process of making such starch, and the use thereof.
It is known that starch can be used to add texture to products by taking advantage of its viscosifying properties. For example, starch is used in sauces and gravies, soups, creamers, salad dressings, and other food and industrial products to thicken or even gel the products and provide a variety of functionality.

Physically modified sago starch and uses of same


In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.

The present invention relates to a semiconductor device in which a plurality of semiconductor elements have a SOI (Silicon On Insulator)-Si layer and a method of manufacturing the same. More particularly, the present invention relates to a structure of an element isolation film and a method of manufacturing the same.
In a conventionally-known semiconductor device, a CMOS element and a bipolar element are integrally formed on a SOI substrate (U.S. Pat. No. 5,212,397). The SOI substrate is constituted of a silicon semiconductor substrate (Si-sub) 1 and a buried oxide film (BOX) 2 formed thereon, as shown in FIG. 23. The buried oxide film 2 is formed by doping oxygen ions into the semiconductor substrate. The SOI substrate has a bipolar region 9 and a CMOS region 10. CMOS elements 7 and 8 are formed in the CMOS region 10, whereas a bipolar element is formed in the bipolar region 9. More specifically, the CMOS elements 7 and 8 are formed in a thin single crystalline silicon layer 3 formed on the buried oxide film (BOX) 2 within the CMOS region 10. The buried oxide film (BOX) 2 is deeply etched within the bipolar region 9. Within the etched region of the buried oxide film (BOX) 2, a thick single crystalline silicon layer 4 is formed by epitaxial deposition. A semiconductor element (bipolar element) is formed in the single crystalline layer 4. Although only a single bipolar element is shown in the figure, bipolar elements are separated by an element isolation silicon oxide film 6 formed in the element isolation region. On the other hand, the CMOS elements 7 and 8 are separated by an element isolation silicon oxide film 5 in the element isolation region. The element isolation film 6 of the bipolar region 9 is formed thicker than the element isolation film 5 of the CMOS region 10 and therefore the height of the film 6 from the surface of the substrate is larger than that of the film 5. To explain more specifically, the element isolation film 6 of the bipolar region 9 differs in thickness from the element isolation film 5 of the CMOS region 10, and therefore, their heights from the surface of the substrate differ.
A bipolar transistor has an emitter, base, collector, and collector extraction layer which are formed in the single crystalline silicon layer 4 of the bipolar region 9, and an emitter electrode, base electrode, and a collector electrode which are formed on the single crystalline silicon layer 4. A PMOS transistor of a CMOS transistor structure has a P+ source/drain region formed in the single crystalline silicon layer 3 of the CMOS region, a gate oxide film formed on the single crystalline silicon layer 3, and a gate electrode 7 formed on the gate oxide film. An NMOS transistor of the CMOS transistor structure has an N+ source/drain region formed in the single crystalline silicon layer 3 of the CMOS region, a gate oxide film formed on the single crystalline silicon layer 3, and a gate electrode 8 formed on the gate oxide film.
As described in the above, in the conventional semiconductor device, the element isolation film 6 of the bipolar region 9 is formed thicker than the element isolation film 5 of the CMOS region 10. Thus, the height of the element isolation film 6 from the surface of the substrate is larger than the element isolation film 5. In other words, since the thickness of the element isolation film 6 of the bipolar region differs in thickness from the element isolation film 5 of the CMOS region 10, their heights from the surface of the substrate differ from each other. This makes it difficult to process a wiring layer formed over the bipolar region 9 and the CMOS region 10. More specifically, in the manufacturing process of a semiconductor device having a plurality of SOI-Si layers different in thickness on a single SOI substrate, since element isolation is performed after a plurality of SOI-Si layers different in thickness are formed, the heights of the insulating films of the element isolation region differ. Therefore, it is difficult to process a wiring layer in a wiring formation step performed later. Furthermore, as a result of the insulating films of the element isolation region differing in height, xe2x80x9cout-of-focusxe2x80x9d occurs in a lithography step later performed, rendering it difficult to perform a micro gate processing.
There is another publication (U.S. Pat. No. 5,294,823) besides the aforementioned publication (U.S. Pat. No. 5,212,397) in which a plurality of single crystalline semiconductor layers different in thickness which are formed on a buried insulating film, are integrally formed into a single chip. However, in this conventional example, the element isolation regions of the bipolar region and the CMOS region 10 differ in height from the surface of a semiconductor substrate. Therefore, the same problems as in U.S. Pat. No. 5,212,397 resides also in U.S. Pat. No. 5,294,823.
The present invention has been made under the aforementioned problems. An object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device in which the insulating films of the element isolation region in a bipolar region have substantially the same height as that in the CMOS region, enabling micro wiring processing easier.
The present invention is directed to a semiconductor device having a plurality of semiconductor elements having a SOI-Si layer, which is characterized in that the element isolation films of a plurality of semiconductor elements have the substantially the same height from the surface of the semiconductor substrate, that is, the surfaces of the element isolation films form substantially the same plane. Furthermore, the present invention is characterized in that after element isolation regions are formed so as to form the same plane having the same height from the surface of the semiconductor substrate a plurality of SOI-Si films (single crystalline silicon film) different in thickness are formed.
According to the present invention, element isolation insulating films have substantially the same height from a semiconductor substrate. Therefore, wiring processing can be performed easier. Furthermore, according to the present invention, it is possible to manufacture a semiconductor device having a plurality of semiconductor elements having SOI-Si layers different in thickness without increasing the number of steps.
In a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a buried insulating film formed on the semiconductor substrate; a plurality of single crystalline semiconductor layers, each having a semiconductor element formed therein and being formed on the buried insulating film; and an element isolation region formed between adjacent single crystalline semiconductor layers, the element isolation insulating films formed in the element isolation region and having substantially the same height from the surface of the semiconductor substrate.
In the semiconductor device according to the first aspect of the present invention, at least one of the plurality of single crystalline semiconductor layers may differ in thickness from other single crystalline semiconductor layers. In the semiconductor device, the single crystalline semiconductor layers may include a first single crystalline semiconductor layer having a MOS transistor formed therein and a second single crystalline semiconductor layer having a bipolar transistor formed therein, the first and second single crystalline semiconductor layers having substantially the same film thickness and a thickness of the semiconductor layer lower than the gate electrode of the MOS transistor being lower than the film thickness of the second single crystalline semiconductor layer. In the semiconductor device, in the single crystalline semiconductor layers, a full depletion element and a partially Depletion element may be formed.
In the semiconductor device according to the first aspect of the present invention, the single crystalline semiconductor layers may include a first single crystalline semiconductor layer having a MOS transistor formed therein and a second single crystalline semiconductor layer having a bipolar transistor formed therein, the first and second single crystalline semiconductor layers having substantially the same film thickness and a thickness of the semiconductor layer lower than the gate electrode of the MOS transistor being lower than the film thickness of the second single crystalline semiconductor layer. In the semiconductor device, in the single crystalline semiconductor layers, a full depletion element and a partially Depletion element may be formed.
In the semiconductor device according to the first aspect of the present invention, in the single crystalline semiconductor layers, a full depletion element and a partially Depletion element may be formed.
In a second aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having a first region and a second region; a buried insulating film formed in the first region of the semiconductor substrate; at least one first single crystalline semiconductor layer having a semiconductor element formed therein and formed in the buried insulating film and; at least one second single crystalline semiconductor layer formed in the second region and in contact with the semiconductor substrate; and an element isolation region for isolating the single crystalline semiconductor layers from each other, wherein all the element isolation insulating films in the element isolation region have the same height from the semiconductor substrate.
In the semiconductor device according to the second aspect of the present invention, the first single crystalline semiconductor layer formed in the first region may consist of a plurality of semiconductor layers having a plurality of film thicknesses. In the semiconductor device, a CMOS element may be formed in the first region and a bipolar element may be formed in the second region. In the semiconductor device, a MOS transistor may be formed in a predetermined first single crystalline semiconductor layer of the first region; a bipolar transistor may be formed in a predetermined second single crystalline semiconductor layer of the second region; the first and second single crystalline semiconductor layers have substantially the same height from the surface of the semiconductor substrate; and the thickness of the semiconductor layer lower than the gate electrode of the MOS transistor is substantially the same as the thickness of a predetermined second single crystalline semiconductor layer.
In the semiconductor device according to the second aspect of the present invention, a CMOS element may be formed in the first region and a bipolar element may be formed in the second region. In the semiconductor device, a MOS transistor may be formed in a predetermined first single crystalline semiconductor layer of the first region; a bipolar transistor may be formed in a predetermined second single crystalline semiconductor layer of the second region; the first and second single crystalline semiconductor layers have substantially the same height from the surface of the semiconductor substrate; and the thickness of the semiconductor layer lower than the gate electrode of the MOS transistor is substantially the same as the thickness of a predetermined second single crystalline semiconductor layer.
In the semiconductor device according to the second aspect of the present invention, a MOS transistor may formed in a predetermined first single crystalline semiconductor layer of the first region; a bipolar transistor may formed in a predetermined second single crystalline semiconductor layer of the second region; the first and second single crystalline semiconductor layers have substantially the same height from the surface of the semiconductor substrate; and the thickness of the semiconductor layer lower than the gate electrode of the MOS transistor is substantially the same as the thickness of a predetermined second single crystalline semiconductor layer.
In a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor substrate by laminating a buried insulating film, a single crystalline semiconductor layer, a first insulating film subsequently in this order; etching the first insulating film and the single crystalline semiconductor layer to form a plurality of laminate films consisting of the single crystalline semiconductor layer and the first insulating film in the buried insulating film; forming a second insulating film on the semiconductor substrate so as to cover the laminate films; flattening the second insulating film until the height of the second insulating film from the semiconductor substrate becomes the same as that of the first insulating film, thereby forming an element isolation region; etching away the first insulating film constituting at least one laminate film to expose a surface of the single crystalline semiconductor layer under the first insulating film; and depositing the single crystalline semiconductor to a predetermined depth on the exposed single crystalline semiconductor layer.
In a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor substrate by laminating a buried insulating film, a single crystalline semiconductor element, a first insulating film subsequently in this order; etching the first insulating film and the single crystalline semiconductor layer to form a plurality of laminate films consisting of the single crystalline semiconductor layer and the first insulating film on the buried insulating film; forming a second insulating film on the semiconductor substrate so as to cover the laminate films; flattening the second insulating film until the height of the second insulating film becomes substantially the same as that of the first insulating film to from an element isolation region; etching away at least one laminate film and simultaneously etching away the buried insulating film under the removed laminate film, thereby exposing a surface of the semiconductor substrate; etching the first insulating film constituting at least one laminate film excluding the removed laminate film, thereby exposing a surface of the single crystalline semiconductor layer under the first insulating film; and depositing a single crystalline semiconductor on the exposed single crystal semiconductor layer to thicken the single crystalline semiconductor layer, and simultaneously forming a single crystalline semiconductor layer on an exposed surface of the semiconductor substrate, thicker than the single crystalline semiconductor layer formed on the buried insulating film.
In a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor substrate by laminating a buried insulating film, a single crystalline semiconductor layer, a first insulating film subsequently in this order; etching the first insulating film and the single crystalline semiconductor layer to form a plurality of laminate films consisting of the single crystalline semiconductor layer and the first insulating film on the buried insulating film; forming a second insulating film on the semiconductor substrate so as to cover the laminate films; flattening the second insulating film until the height of the second insulating film from the semiconductor surface becomes substantially the same as that of the first insulating film to from an element isolation region; etching away the first insulating film constituting at least one laminate film to expose a surface of the single crystalline semiconductor layer under the first insulating film; forming a MOS transistor on the single crystalline semiconductor layer whose surface is exposed; etching away the first insulating film formed on a predetermined single crystalline semiconductor layer within the single crystalline semiconductor layer covered with the first insulating film; depositing a single crystalline semiconductor on the single crystalline semiconductor layer having the MOS transistor formed therein and on the single crystal semiconductor layer whose surface is exposed; and forming a bipolar transistor on a predetermined single crystalline semiconductor layer whose surface is exposed.
In a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor substrate by laminating a buried insulating film, a single crystalline semiconductor layer, and a first insulating film subsequently; etching the first insulating film and the single crystalline semiconductor layer to form a plurality of laminate films consisting of the single crystalline semiconductor layer and the first insulating film on the buried insulating film; forming a second insulating film on the semiconductor substrate so as to cover the laminate films; flattening the second insulating film until the height of the second insulating film from the semiconductor surface becomes substantially the same as that of the first insulating film to from an element isolation region; etching away at least one laminate film and simultaneously etching away the buried insulating film under the removed laminate film to expose a surface of the underlying semiconductor substrate; depositing the single crystalline semiconductor layer in contact with the surface of the exposed semiconductor substrate; etching away the first insulating film constituting at least one laminate film excluding the removed laminate film to expose a surface of the single crystalline semiconductor surface; forming a MOS transistor on the exposed single crystalline semiconductor layer; depositing a single crystalline semiconductor on the single crystalline semiconductor layer having the MOS transistor formed therein and simultaneously depositing on the single crystal semiconductor layer formed on the semiconductor substrate whose surface is exposed, thereby rendering the height of the single crystalline semiconductor layer having the MOS transistor therein, from the surface of the semiconductor substrate, substantially the same as that of the single crystalline semiconductor layer formed on the semiconductor substrate whose surface is exposed; and depositing the single crystalline semiconductor and forming a bipolar transistor on the single crystalline semiconductor layer formed on the semiconductor substrate whose surface is exposed.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.

Semiconductor device and method of manufacturing the same


The present invention 18 discloses a device which will release a vehicular seal 12 in the event tile vehicle air bag 25 is deployed, for example, in the event of an accident. The apparatus discloses an electromagnetic lock assembly 24 attached to the vehicle seat 12 wherein the lock assembly 24 is releasably attached to a track 22 and wheel assembly 26 which it fixedly mounted to the vehicle in such a manner that the electromagnetic lock assembly 24 can slide back and forth upon the track 22 and wheel assembly 26. The electromagnetic lock assembly 24 of the present invention, normally keeps the lock assembly 24 in a closed position so that the seat 12 will not move. However, a sensor 44 is provided which recognizes the deployment of the vehicle air bag 25 and thereby sends an output signal to a relay switch 46 which opens the circuit which normally keeps the electromagnetic lock assembly 24 in its closed position thereby releasing the electromagnetic lock 24 and allowing the vehicle seat 12 to move in a rearward direction which movement is caused by the air bag 25 making contact with the occupant 16 and thereby pushing the occupant 16 and tie occupant's seat 12 in the rearward direction.

1. Field of the Invention
The present invention relates generally to air bag deployment systems and, more specifically, to a car seat mounted on a track and having an electromagnetic lock maintaining a preselected position during normal operation of a vehicle and wherein an air bag deployment sensor will disengage said electromagnetic car seat upon deployment of said air bag allowing the force of the deployment of the air bag against the occupants of said car seat to move said seat in a rearward direction until said air bag is fully deployed and all conditions of said deployment have been met wherein said circuit will be closed therein engaging said electromagnetic lock.
2. Description of the Prior Art
There are other air bag seat restraint systems designed to prevent injury to the occupants of the vehicle. Typical of these is U.S. Pat. No. 5,765,893 issued to Ziegler on Jun. 16, 1998.
Another patent was issued to Meister et al on Oct. 21, 1997 as U.S. Pat. No. 5,678,854. Yet another U.S. Pat. No. 5,570,903 was issued to Meister et al on Nov. 5, 1996 and still yet another was issued on Sep. 3, 1996 to Sedlack et al as U.S. Pat. No. 5,551,751.

Electromagnetic car seat release upon deployment of vehicular air bag