The subject invention is a standardized system that provides for the methodical performance of a variety of procedures, which is designed to be configured as a variety of single-use devices, each in the form of a procedure kit which corresponds to a particular type of procedure, organized with all the exact components necessary to perform such particular type of procedure, in accordance with the included step-by-step instructions of a proprietary protocol with which such components correlate. This standardized system for performing a variety of procedures, and the methodical approach for performing each corresponding proprietary protocol, can improve the precision and efficiency of each procedure and, thereby reduce the chance of errors, minimize waste, increase productivity and provide for consistent outcomes.

Many processes and procedures are performed as a sequence of steps. Each step of such processes and procedures utilizes materials and techniques to achieve a particular outcome. In some cases, these steps can be performed in a different order, using different materials, or by using different techniques and a similar outcome can still be achieved. In some circumstances, however, it could be beneficial if the same sequence of steps were followed, and the same materials and techniques were used, each time a procedure was performed. By doing so, it would be more likely to achieve the same outcome each time the same type of procedure was to be performed, no matter who performs the procedure or where the procedure was performed. Further, such a methodical approach to performing a procedure could improve precision and efficiency, reduce errors, minimize waste, increase productivity and reduce costs.
The benefit of performing procedures with a methodical step-by-step sequence, and with materials and techniques specific to each step, would be even greater if the materials used were correlated with a protocol that was specific to each procedure. Using such protocols could ensure that the steps of each particular procedure were always conducted in the same sequence, using the same types and amounts of materials, and using essentially the same techniques every time such a procedure was performed. When performing a procedure according to a protocol in this manner, should an error occur, it would be easier to determine the factors that caused the error within the sequence of steps.
Regenerative medicine is a field of medical practice that utilizes biomaterials for patient treatments. It has been recognized that there is a lack of standardization in the field of regenerative medicine and a lack of consistency in the way that treatments are prepared for patient needs. The order of steps of various regenerative treatment preparation processes, the materials used, techniques, and other factors can vary. This lack of a methodical approach can inhibit the precise and efficient preparation of regenerative treatments. Also, the lack of consistency in the preparation of treatments for a particular patient can lead to inconsistent outcomes. This problem is not limited to the field of regenerative medicine. There are many other medical, quasi-medical, or even non-medical procedures that are not performed with an approach that is methodical and consistent.
It would be beneficial, therefore, if a standardized system could be configured to create a variety of single-use procedure kits. It would be advantageous if each type of procedure kit contained the type and quantity of materials necessary to perform a procedure, in accordance with the pre-determined steps of a specific protocol. It would be further beneficial if such a procedure kit provided for a discrete separation of the materials needed for each step of a protocol, and if the materials were organized to correlate with the protocol for the particular procedure being performed. Then, the user could select the appropriate procedure kit and methodically conduct the specific protocol required to successfully complete the procedure for which the procedure kit has been selected, with the expectation that the protocol could be conducted with precision and efficiency and that the desired outcome could be consistently achieved each time the same type of procedure kit was selected and used.

Methods and devices for performing sequential procedures utilizing a standardized system


A PLL may include a voltage regulator for providing a regulated voltage to one or more PLL components (e.g. a charge pump, a voltage controlled oscillator, etc.). The PLL components may be noise sensitive components, and the regulated voltage may reduce noise received from the power supply. Additionally, a level shifter may be coupled between the PLL components and a phase/frequency detector. The level shifter may be supplied by the regulated voltage from the voltage detector. In another implementation, a PLL may include a programmable charge pump and a programmable loop filter. For example, the reference current to the charge pump may be changed, thus changing the rate at which the charge pump can change an output voltage (the control voltage to a voltage controlled oscillator in the PLL). The loop filter components may be changed to change the frequency ranges filtered by the loop filter.

1. Field of the Invention
This invention is related to the field of phase locked loops (PLLs).
2. Description of the Related Art
PLLs are used in a wide variety of applications. In integrated circuits, especially modern integrated circuits operating at high clock frequencies, PLLs are often used to generate the internal clocks for the integrated circuit and to lock the internal clocks to the phase of the clock supplied externally. Phase locking the internal clock to the external clock may aid in providing reasonable setup and hold times for communications on the pins of the integrated circuit. PLLs are also used for clock recovery, data transmission/reception, etc.
Integrated circuits are often designed to be scaleable to different clock frequencies, allowing the integrated circuits to be marketed at different frequency levels/price points and enhancing the usefulness of the integrated circuit in a variety of systems. Accordingly, it is desirable for PLLs to operate properly over a wide range of frequencies while achieving a high degree of noise rejection and fast lock times (the amount of time needed to lock the phase of the internal clock to the external clock).
A PLL may include a voltage regulator for providing a regulated voltage to one or more PLL components (e.g. a charge pump, a voltage controlled oscillator, etc.). The PLL components may be noise sensitive components, and the regulated voltage may reduce noise received from the power supply. Additionally, a level shifter may be coupled between the PLL components and a phase/frequency detector. The level shifter may be supplied by the regulated voltage from the voltage detector. The level shifter may thus attenuate noise present on the input signals to the level shifter, isolating the PLL components from the noise. Noise rejection in the PLL may thus be provided.
In another implementation, a PLL may include a programmable charge pump and a programmable loop filter. For example, the reference current to the charge pump may be changed, thus changing the rate at which the charge pump can change an output voltage (the control voltage to a voltage controlled oscillator in the PLL). The loop filter components may be changed to change the frequency ranges filtered by the loop filter. Accordingly, the PLL response may be adjusted for more optimal operation at a given operation frequency. The flexibility of the PLL for use over a wide range of operating frequencies may thus be enhanced.
Broadly speaking, a PLL is contemplated. The PLL includes a voltage regulator configured to provide a regulated voltage; a phase/frequency detector supplied by a second voltage different from the regulated voltage; one or more PLL components supplied by the regulated voltage; and a level shifter coupled between the phase/frequency detector and the PLL components and supplied by the regulated voltage.
Additionally, a method comprising is contemplated. A regulated voltage is supplied to one or more phase locked loop (PLL) components. A second voltage different from the regulated voltage is supplied to a phase/frequency detector of the PLL. The PLL components are isolated from the phase/frequency detector with a level shifter which also shifts an output of the phase/frequency detector from the second voltage domain to the regulated voltage domain.
Furthermore, a PLL is contemplated, comprising a charge pump configured to provide a voltage on an output node; and a loop filter coupled to the output node. A rate at which the charge pump is able to change the voltage is programmable and frequencies filtered by the loop filter are programmable.
Still further, a method is contemplated. A charge pump in a PLL is programmed. The programming including setting a rate at which the charge pump is able to change a voltage at an output of the charge pump. A loop filter in the PLL is also programmed, the programming includes setting frequencies filtered by the loop filter.

High speed, wide bandwidth phase locked loop


A first balloon catheter having a tip extends through the stem portion and first leg portion of a first expandable tubular member and a second balloon catheter having a tip through said stem portion and extends out of a branch aperture such that its tip is longer than that of the first balloon catheter. The first, expandable tubular member, first balloon catheter and second balloon catheter are delivered to a bifurcated vessel having a first lumen and a second lumen with the tip of the second balloon catheter leading the rest of the elements so that the tip of said second balloon catheter can be aligned with and enter into the second lumen before the first expandable tubular member and the tip of said first balloon catheter reach the area of said second lumen and interfere with the second balloon catheter.

The present invention relates to stents, and more particularly methods of delivering a bifurcated stent.
Stents are well known in the art. They are typically formed of a cylindrical metal mesh, which can expand when pressure is internally applied. Alternatively, they can be formed of wire wrapped into a cylindrical shape or sheets of material formed into a cylindrical shape.
Stents are devices that are usually implanted within bodily conduits including the vascular system to reinforce collapsing, partially occluded, weakened, or abnormally dilated sections of the blood vessel. Stents also have been successfully implanted in other areas, e.g., the urinary tract or the bile duct to reinforce such bodily conduits.
U.S. Pat. No. 4,994,071 (MacGregor) discloses an expandable, bifurcating stent having a main cylindrical lattice formed from interconnected, flexible wire. Two additional cylindrical lattices, having smaller diameters than the main lattice, are similarly constructed. The main lattice includes a flexible wire interconnecting the main lattice to one of the additional lattices. A second flexible wire interconnects the main lattice to the other additional lattice. The flexible wires form backbones that extend axially along the length of the main lattice and along each of the additional lattices. One disadvantage of this bifurcating stent is the complex nature of the interconnection of the flexible wires forming the backbones with the loop structure of each lattice.
Thus, embodiments described in the aforementioned U.S. Pat. No. 6,251,133 provide methods of making a stent which includes a first tubular member having a branch aperture. The tubular member may be inserted in a blood vessel, for example, with the branch aperture aligned with a side branch vessel. A second tubular member having a longitudinal bore may then be disposed and secured within the branch aperture of the first tubular member and, for example, extending into the branch vessel, with the longitudinal bore of the second tubular member in fluid communication with the longitudinal bore of the first tubular member.
One delivery method of a bifurcated stent, such as the stents disclosed in U.S. Pat. No. 6,251,133, to the target area includes mounting the stent on two expandable balloons of the same length. Both expandable balloons are advanced toward the target site together, or are advanced individually in sequential order. One expandable balloon is to be disposed in the main vessel, and one the other is to be disposed in the side branch lumen of the bifurcated vessel. Typically, the side branch balloon is the same length or shorter than the main vessel balloon. Upon reaching the target area in the vessel, the main vessel becomes very crowded due to both balloons filling up the lumen of the main vessel. This causes the tip of the side branch balloon to be pressed against the main vessel, and causes difficulty in orienting the balloon into the side branch lumen, and hinders the ability of the side branch balloon to bend into the side branch vessel.
Embodiments of the present invention solves these and other disadvantages of the prior art by providing a side branch balloon catheter whose tip leads the tip of the main vessel balloon catheter by few millimeters, so that the side branch balloon leads the delivery system while advancing towards the target area. The side branch balloon catheter reaches the target area first, allowing for greater freedom of the side branch balloon to bend into the aperture of the side branch vessel, due to less crowding of balloon catheter in the main vessel.


A liquid crystal display includes: a first gate line; a first data line crossing the first gate line; a first switching element connected with the first gate line and the first data line; a second switching element connected with the first gate line and the first data line; a first liquid crystal capacitor connected with the first switching element; a second liquid crystal capacitor connected with the second switching element; a boost switching element which is turned on during a time period not overlapping a time period during which the first switching element is turned on; and a boost capacitor including a first terminal connected with the boost switching element and a second terminal connected with the first liquid crystal capacitor.

(a) Field of the Invention
Exemplary embodiments of the invention relate to a liquid crystal display and a driving method thereof.
(b) Description of the Related Art
A liquid crystal display, which is one of widely used types of flat panel display devices, generally includes field generating electrodes, such as a pixel electrode and a common electrode, and a liquid crystal layer. The liquid crystal display generates an electric field in the liquid crystal layer by applying voltage to the field generating electrodes, to determine orientations of liquid crystal molecules of the liquid crystal layer and control polarization of incident light, thereby displaying an image.
Among the liquid crystal display, a vertically aligned mode liquid crystal display, in which a longitudinal axis of the liquid crystal molecules is arranged to be substantially perpendicular to upper and lower panels when the electric field is not applied, has been widely used due to a high contrast ratio and effective implementation of a wide reference viewing angle thereof.
In the vertically aligned mode liquid crystal display, since side visibility is deteriorated compared to front visibility, a method in which one pixel is divided into two subpixels and voltages of two subpixels are different has been proposed to improve the deteriorated side visibility.

Liquid crystal display and driving method thereof


A circuit includes an emergency lighting system and an AC/DC converter. An output terminal of the emergency lighting system is electrically connected to a LED load, and the other output terminal DIM of the emergency lighting system is electrically connected to a switch S2. The switch S2 is controlled by the emergency lighting system. The emergency lighting system includes an AC input detection module, a switching time detection module and a lithium battery. The AC input detection module is electrically connected to a neutral wire VN and a live wire VL. The switching time detection module is electrically connected between an output terminal of the AC input detection module and the terminal DIM. An output terminal of the AC/DC converter is electrically connected to a positive electrode of the lithium battery, and the other output terminal of the AC/DC converter is electrically connected to the LED load.

For simply controlling an emergency lighting system, a switch used for turning luminaires on and off is provided for an emergency lighting system. For example, in the emergency lighting system shown in FIG. 1, when the switch is closed the alternating current (AC) network power supply normally supplies the AC network, and the emergency lighting control chip detects the AC network voltage and turns off the emergency lighting. The AC/DC converter charges the battery while supplying power to the output LED. If the AC network stops supplying the power to the system, there is low resistance between the neutral wire VN and the live wire VL and there is no AC high-voltage signal. This low resistance is detected by the emergency lighting control chip and the emergency lighting is turned on.
When the switch is open, regardless of whether the AC power supply on, the emergency lighting control chip cannot detect the AC network voltage, and can detect the high resistance between VN and VL. In this case, the emergency lighting control chip turns off the emergency lighting.
FIG. 1 shows the circuit, having the simply controlled emergency lighting control system. When the system is working in an emergency lighting state, the drive current of the emergency lighting is a fixed drive current and cannot be changed. Thus, the system has two disadvantages as follows: 1) in the emergency lighting state, the actual lighting brightness of the luminaires is different during different working conditions; 2) since the battery is used to supply the power for the emergency lighting luminaires the users need to change the drive current of the emergency lighting to reduce the brightness. This reduction in brightness will prolong the working time of the emergency lighting luminaire.

Circuit and method for controlling brightness of emergency lighting luminaires by a switch

SHANGHAI SINCERETEK MICROELECTRONICS TECHNOLOGY CO , LTD.


Methods for identifying compounds that modulate the activity and/or expression of a calcium-sensing receptor, wherein said compounds can be incorporated into flavor compositions that can be used to modify the kokumi taste and/or palatability of pet food products.

Taste profiles for edible compositions include basic tastes such as sweet, salt, bitter, sour, umami and kokumi. Taste profiles have also been described as including free fatty acid tastes. Chemical compounds that elicit these tastes are often referred to as tastants. Without being bound by theory, it is hypothesized that tastants are sensed by taste receptors in the mouth and throat which transmit signals to the brain where the tastants and resulting taste profiles are registered. Taste receptors include the calcium-sensing receptor (CaSR), which is a G-protein coupled receptor (GPCR) that detects changes in extracellular calcium levels and a close relative to the T1R1, T1R2 and T1R3 receptors, i.e., the sweet and umami receptors. The calcium-sensing receptor has been shown to enhance sweet, salty and umami tastes, and function as a receptor for kokumi taste.
Pet food manufacturers have a long-standing desire to provide pet food products that have high nutritional value. In addition, and with particular regard to cat and dog foods, pet food manufacturers desire a high degree of palatability so that pets can receive the full nutritional benefit from their food. Domestic animals, especially cats, are notoriously fickle in their food preferences, and often refuse to eat a pet food product that it has accepted over time or refuse to eat any more than a minimal amount of a pet food product. This phenomenon may be, in part, due to the subtle differences in the sensory profiles of the raw material, which can be perceived by the domestic animals because of their gustatory and olfactory systems. As a result, pet owners frequently change types and brands of pet food in order to maintain their pets in a healthy and contented condition.
While there have been recent advances in taste and flavor technologies, there remains a need for compounds that can enhance or modify the palatability of pet food products by enhancing or modifying the taste, texture and/or flavor profiles of the pet food product. The enhancement or modification can be to increase the intensity of a desirable attribute, to replace a desirable attribute not present or somehow lost in the pet food product, or to decrease the intensity of an undesirable attribute. In particular, it is desirable to increase the intensity of a desirable tastant in a pet food product.
Therefore, there remains a need in the art for methods to identify compounds that enhance the palatability and/or modulate the kokumi taste of pet food products and for flavor compositions comprising these compounds.

This patent is subject to a terminal disclaimer.

Methods for identifying modulators of calcium-sensing receptors


A method of designing an alignment target system to minimize lens aberrations is disclosed. A first layer alignment target""s pitch is selected based on the minimum feature size of the circuit. The second layer alignment target""s pitch is selected based on the diffraction pattern of the first layer""s target and the illumination settings of the second layer. Displacement errors are minimized when the second layer target""s 1st diffraction order overlaps the first layer target""s 0th diffraction order.

The invention relates to an overlay target design method for semiconductor fabrication to minimize the impact of lens aberrations on target projection.
Typically semiconductor devices are fabricated by optical lithography techniques using a projection imaging systems. A typical projection image system 20 is illustrated in FIG. 1. The system 20 at a minimum includes an illumination controller 22 and an illumination source 24 coupled with and controlled by controller 22. Illumination source 24 may include, for example, a mirror, a lamp, a light filter, and a condenser lens system. As used herein, the term xe2x80x9clightxe2x80x9d refers to light used in photolithography. The term xe2x80x9clightxe2x80x9d need not be restricted to visible light, but may also include other forms of radiation and lithography. For example, energy supplied by lasers, photons, ion beams, electron beams, or X-rays are included within the term xe2x80x9clightxe2x80x9d.
Illumination source 24 emits light or radiation that can pass through openings in mask 26. System 20 shows mask 26 positioned adjacent to light source 24; optionally, other devices such as one or more optical lenses could separate light source 24 and mask 26. The term xe2x80x9cmaskxe2x80x9d is not limited to a physical structure, but also includes a digitized image used in, for example, electron beam and ion beam lithography systems. For example, mask 26 may include a pattern for projecting a wiring or feature pattern of an integrated circuit. The pattern of mask 26 may include various image structures, for example, clear areas, opaque areas, phase shifting areas, and overlay targets. Mask 26 generally is a combination of clear areas and opaque areas, where the clear areas allow light from light source 24 to pass through mask 26 to form the mask""s image. Light passing through mask 26 is further transmitted by projection lens 30, which may be, for example, a reduction lens or a combination of lenses for focusing the mask pattern onto a projection surface 111, such as a semiconductor wafer covered with a photoresist layer. Typical semiconductor fabrication involves a four to ten times reduction of mask size 26 by projection lens 30. Projection surface 111 is held in position by a holding device (not shown), which may be part of or controlled by a stepper (not shown). Also shown in FIG. 1 is lens pupil 28 of projection imaging lens 30, which defines the numerical aperture of lens 30.
As the dimension of features on integrated circuits continue to decrease, the resolution limits of optical lithography are quickly being reached. One limit is caused by lens aberration, which is the failure of a lens, such as projection lens 30, to produce exact point-to-point correspondence between a received image, such as from mask 26, and a projection surface 111, such as a semiconductor die 100 a portion of which is illustrated in FIG. 2. One of the many types of lens aberrations in semiconductor device fabrication is coma aberrations which are optical aberrations that cause the image of a mask 26 to appear comet-shaped or blurred on die surface 113 (FIG. 2). Coma aberrations result in not only line width variations and/or pattern asymmetry, but also affect the location or placement of the mask image on the die surface 113. As discussed in Takashi Saito and Hisashi Watanabe""s article xe2x80x9cInvestigation of New Overlay Measurement Marks for Optical Lithography,xe2x80x9d J. Vac Sci Technol. B 16(6), November/December 1998, pp. 3415, 3418, during sub-micron device fabrication using optical lithography lens aberrations cause different displacement errors for overlay targets and device patterns.
A target is a feature on a mask 26, usually at the perimeter of the mask 26, that is transferred to die surface 113 during the illumination phase. The target helps to determine if the image transfer from mask 26 to die surface 113 was properly aligned relative to lower layers. Typically, the quality of the lithographic image alignment is measured by determining the alignment of a target on a lower level to a target on an upper or overlay level. In general the image transfer is successful if the target of the upper-layer is approximately centered with the lower-level target. An, overlay measurement system is used to measure the distances and spaces between edges or boundaries of the upper and lower targets. It is critically important that the circuit pattern on one layer is accurately aligned with that of earlier layers. To evaluate the alignment of two layers, a target is formed on each layer. FIG. 2 is an illustration of a single integrated circuit (IC) die 100 fabricated on a semiconductor wafer. The locations of the electrical circuit or pattern and targets are represented by large box 120, hereinafter referred to as pattern, and small boxes 110, hereinafter referred to as targets, respectively. Typical dimensions for die 100 are 5 millimeters by 5 millimeters and typical dimensions for targets 110 are 10 microns by 10 microns.
A prior art method of mask alignment measurement will be described with respect to FIGS. 3 and 4. FIG. 3 is a top view of a prior art box-in-box target 110 of FIG. 2. FIG. 4 is a cross-sectional view of FIG. 3 along line IIIxe2x80x94III. The accuracy of the transfer of the targets 110 approximates the accuracy of the pattern 120 transfer. A first target 112 with a box pattern can be formed on surface 113 in a first layer or under layer 115 using well known lithography techniques. Typically, a silicon oxide material is deposited over first layer 115 to form a second layer 116. The second target 114 is formed in second layer 116 with dimensions smaller than target 112 using well known lithography techniques. The perimeter 117 of first target 112 and perimeter 118 of second target 114 can be viewed by optical measurement equipment. By measuring the distance between the two perimeters or isolated edges 117, 118 at several locations, the center positions of targets 112, 114 can be determined and positional deviations between the two targets 112, 114 can be determined. The overlay measurement provides a comparison of the alignment of the underlay target 112 of layer 115 with that of overlay target 114 of layer 116.
In the article by Saito and Watanabe the benefits of using fine pattern targets made up of thin lines instead of large box shaped patterns is discussed. Fine patterns targets, such as targets formed with thin line widths, are generally much closer to the actual circuit features dimensions than conventional large box patterns. Since lens aberrations typically induce line width variations and create alignment errors, using fine pattern targets allows more accurate detection of lens aberrations and alignment errors. In other words, the use of the typical box-in-box method (FIGS. 3-4) to determine mask 26 displacement errors is not very accurate for small device patterns, such as a quarter micron device fabrication (0.25 micron device feature size). Using targets with feature dimensions (size and pitch) similar to those of the circuit improves the detection of displacement errors.
For example, FIG. 5 is an illustration of a conventional fine pattern target system 200. Fine pattern targets 210, 220 are formed in a first layer 215 (FIG. 6) over surface 213. Fine pattern targets 230, 240 are formed in a second layer 216 (FIG. 6) over first layer 215. FIG. 6 is a cross-sectional view of FIG. 5 along line VIxe2x80x94VI. In known target systems such as target system 200 (FIG. 5), the first layer targets 210, 220 and second layer targets 230, 240 generally have the same pitch (P1). The term xe2x80x9cpitchxe2x80x9d refers to the distance between the outside edge of a first target and the outside edge of a second target. For example in FIGS. 5-6, the pitch of targets 210 and 220 are the distance between the perimeter 211 of target 210 and the perimeter 212 of target 220. In known target systems 200 the pitches for targets in layers 215, 216 are generally the same. In addition, target line widths (W1) are generally the same for targets in layers 215, 216. However even for targets in two different layers 215, 216 with the same line width W1 and pitch P1, changes in the illumination settings of light source 24, such as wave length, intensity, and annular size, used to form the targets 210, 220, 230, 240 can cause misplacement of the second layer targets 230, 240 due to projection lens 30 aberrations.
Illumination settings are an important design factor for optimizing circuit feature dimensions, as the settings often change from one layer to another. For example, if the second layer 216 targets 230, 240 of FIGS. 5-6 are formed using different illumination settings than that used for first layer 215 targets 210, 220 the light will be diffracted differently by the mask 26. Since the target patterns have different diffraction patterns, light will enter and exit lens 30 (FIG. 1) at different locations. Due to normal variations in lens surfaces, if light passes through different locations, lens aberrations will cause the light to diffract differently causing target displacement in the second layer 216.
The displacement error is a function of the mechanical placement capability of the system 20 and the projection lens 30 aberrations. The mechanical displacement is the same for both the pattern 120 and targets 110. However, lens aberrations affect the pattern 120 and targets 110 differently. In most cases, the lens induced error for the pattern 120 is smaller than the lens induced error in typical box-in-box targets 110. The lens error is more pronounced when different illumination shapes are used on two different layers. Since the aberrations change across the lens 30 the light is subject to different aberration patterns. Hence corrections based on typical box-in-box targets 110 induce displacement errors into the pattern 120.
There is a need and desire for a new method of designing feature dimensions, such as the pitch of second layer alignment targets, to minimize the impact of lens aberrations. Moreover there is a need to maximize the lens region overlap of light diffracted from two, different illumination shapes. Furthermore, there is a need and desire for a new method for determining the pitch of a second layer targets based on the pitch and light diffraction patterns of a first layer target that minimizes displacement of the second layer targets by lens aberrations due to changes in illumination settings.
The invention relates to a method of determining a dimension for a semiconductor feature, in particular a second layer alignment target""s pitch, to minimize the impact of lens aberrations during optical projection. In an exemplary embodiment, the design method determines the pitch of a second layer fine pattern alignment target based on the light diffraction patterns of a first layer fine pattern alignment target. The first layer target is designed to have a pitch similar to that of a periodic feature of the integrated circuit, such as a capacitor. The second layer target is designed to have a pitch that minimizes displacement of the second layer target by optimizing the light diffraction patterns of the second layer target based on the first layer target.
The pitch of the second layer target is determined by several steps. First, projection lens locations of the light diffraction patterns created by the first layer target for a particular illumination setting are determined. Second, the projection lens locations of the 0th order light diffraction pattern for the second layer illumination settings are determined. Finally, the second layer target""s pitch is selected which optimizes overlap of the 1st order light diffraction patterns of the second layer target with that of the 0th order diffraction pattern of the first layer target. The more overlap between the respective diffraction patterns of the first and second layer targets, the more the displacement error caused by lens aberrations is reduced.

Overlay target design method to minimize impact of lens aberrations


A storage device includes storage media and a controller to control access of the storage media. The controller receives an erase command used to specify an erase operation of at least one portion of the storage media. The erase command has a control field controllable by a requestor device that submitted the erase command to the storage device, where the control field has one or more portions settable to cause the storage device to perform one or more of: reporting a progress of the erase operation, and modifying an operational state of the erase operation.

Storage devices such as disk drives include storage media used for storing data, such as files, directories, and other types of data objects. Typically, when a user deletes a data object, the information that is actually deleted is the reference information to the data object. The actual data object still remains on the storage media even after deletion, which poses security or privacy concerns.
To actually remove data objects stored on storage media, storage device native secure erase commands have been defined that overwrite everything on a storage media in the storage device by repeatedly writing a predefined pattern (e.g., a pattern including a given number, followed by the given number's inverse, then the given number again and then sometimes followed by a zero, or some other pattern). The effect of writing theses patterns on storage media is that it reverses the polarity of the storage media in such a fashion that makes it very difficult to extract the original data from the media. This effectively destroys the original data stored on the storage media and renders the original data inaccessible. With some forms of storage media, reversing the polarity of a number in the pattern may not have to be performed. As yet another alternative, other mechanisms may be employed to ensure that the original data cannot be easily recovered.
An issue associated with conventional secure erase commands is that they may not provide some features that may be desirable to end users.

Storage device erase command having a control field controllable by a requestor device

Hewlett-Packard Development Company, L.P.


A passive convection cooling system for photovoltaic panels utilizing principles of aerodynamics to channel natural air flow under the photovoltaic panels and to increase the rate of heat transfer to greatly increase the convection rate and decrease the temperature of the photovoltaic panels thereby increasing the efficiency of the solar cells and decreasing failures of the photovoltaic system is disclosed. The photovoltaic cooling system comprises of multiple members arranged in predetermined configurations and affixed under the photovoltaic panel to direct natural air flow, according to aerodynamic principles, to increase rate of heat transfer under the photovoltaic panel to greatly increase the convection rate to effectively cool the photovoltaic system.

The present invention relates generally to a photovoltaic cooling system. More specifically, the present invention is a passive cooling system for photovoltaic panels.
The collection of solar energy takes many forms. The most desirable configuration is the direct conversation of solar energy to electricity. The heart of the photovoltaic system is a thin flat layer of semiconductor material. When the material is struck by sunlight, electrons are freed, producing an electric current. The direct-current (DC) power is passed through a DC load, into a storage battery, or converted to alternating current (AC) for general use in electric utility grid. Typically, individual solar cells are ganged together to form photovoltaic modules. Typically, about half the cost of a solar system lies with the solar cell modules, and the remainder is directed toward power conditioning, electrical wiring, installation, and site preparation.
Typically, silicone or gallium arsenide is used to fabricate solar cells, although other semiconductor materials are being developed. Silicone technology is the most advanced because it is the least expensive, and takes many different forms including single-crystal, polycrystal, and amorphous configurations.
The efficiency of solar cells decreases as the temperature of the solar cells increases. Furthermore, increasing temperature also has detrimental effects on other components of the photovoltaic system, including thermal stress which may result in failures in the photovoltaic system. Therefore, a method to cool the photovoltaic system is desirable.
Cooling can be provided by both active and passive systems. Active cooling systems include Rankine cycle system and absorption system, both of which require additional hardware and costs. Passive cooling systems make use of three natural processes: convection cooling; radiative cooling; and evaporative cooling from water surfaces exposed to the atmosphere.
The present invention is a passive convection cooling system for photovoltaic panels utilizing principles of aerodynamics to channel natural air flow under the photovoltaic panels and to increase the rate of heat transfer to greatly increase the convection rate and decrease the temperature of the photovoltaic panels thereby increasing the efficiency of the solar cells and decreasing failures of the photovoltaic system. The photovoltaic cooling system comprises of multiple members arranged in predetermined configurations and affixed under the photovoltaic panel to direct natural air flow, according to aerodynamic principles, to increase the rate of heat transfer under the photovoltaic panel to greatly increase the convection rate to effectively cool the photovoltaic system.


A cure degree evaluation method for evaluating a cure degree of an active energy ray-curable resin composition is a method for evaluating the cure degree of the active energy ray-curable resin composition includes the steps of: irradiating the active energy ray-curable resin composition with an active energy ray; and evaluating the cure degree of the active energy ray-curable resin composition in accordance with a color of the active energy ray-curable resin composition. The active energy ray-curable resin composition contains at least a radical polymerization compound, a leuco dye, and a radical polymerization initiator.

An active energy ray-curable resin composition can be cured by use of an active energy ray such as an ultraviolet ray or an electron beam. The active energy ray-curable resin composition is used in many industrial sectors as a surface coat agent, an adhesive, a pressure sensitive adhesive, a sealing agent, a paint, and the like in view of its transparency, quick-curability, fixability, and the like.
Since the active energy ray-curable resin composition is transparent or semi-transparent, it is difficult to visually determine a cure state of the active energy ray-curable resin composition or presence or absence of a quality abnormality in the active energy ray-curable resin composition. Especially the active energy ray-curable resin composition which is used as an adhesive and insufficiently cured causes many cases of complaints about products. Normally, it is necessary to test a quality of each of the products in terms of a cure degree of the active energy ray-curable resin composition. However, actually, there is no effective and realistic method for testing a product quality.
Therefore, in order to cure the active energy ray-curable resin composition, an excess active energy ray whose amount is not less than a sufficient amount is directed to the active energy ray-curable resin composition, so as to guarantee a cure state of the active energy ray-curable resin composition.
However, even active energy ray irradiation in a sufficient amount cannot determine whether or not a part to which the active energy ray-curable resin composition is applied is irradiated with the active energy ray. Further, it is impossible to detect an unsteady production state such as a deterioration in active energy ray irradiation lamp and/or defocusing of the active energy ray irradiation lamp. Therefore, a method for checking a curing reaction state of the active energy ray-curable resin composition is desired. A method has been known for checking a cure state of a resin composition by a Fourier transform infrared spectroscopy (hereinafter referred to as an FT-IR method) or a method for finding a hardness change (e.g., a Young's modulus) (see the description of "New Technology of UV/EB Curing and Application, p. 55, CMC Publishing CO., LTD.).
The FT-IR method is an analysis method in which an infrared absorbed amount in accordance with a specific functional group is measured by infrared irradiation and a conversion degree of the specific functional group is found by fluctuations in the infrared absorbed amount, so that a cure degree is measured.
In contrast, according to the method for finding a Young's modulus, it is possible to find a cure degree by a change in Young's modulus of a resin composition.
However, such check methods as described above are insufficient in accuracy and require time and cost for carrying out a test. In view of the circumstances, a method is required for more simply checking a curing reaction state of the active energy ray-curable resin composition.
Patent Literature 1 discloses a method for visually checking, by a colored degree of a leuco dye, whether or not an ultraviolet-curable epoxy resin is cured.
Patent Literature 2 discloses a curable pressure sensitive adhesive sheet in which it can be easily visually checked, by a color change, whether or not the curable pressure sensitive adhesive sheet is being cured without fail by light irradiation.
These methods are very simple methods which allow visually checking, by a color change, whether or not a resin is cured.
Patent Literature 3 discloses a method for producing a printed circuit board which is characterized by causing a photosensitive electrodeposition paint to contain a leuco dye. What is disclosed in Patent Literature 3 is as follows: A resist can develop color in a case where a photosensitive resist is formed by use of the photosensitive electrodeposition paint containing the leuco dye. This makes it possible to (i) visually check that the resist has been formed in accordance with a pattern mask and (ii) reduce a rejection rate in a manufacturing process without losing a photosensitivity of an electrodeposition resist.

Cure degree evaluation method, cure degree evaluation sheet, and cure degree evaluation system for evaluating cure degree of active energy ray-curable resin composition


The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.

The present invention relates to electronics, and more particularly, to a method for making a dynamic random access memory (DRAM).
A DRAM includes a plurality of memory cells. Each DRAM cell defined by a bit line and a word line, includes a semiconductor/dielectric/semiconductor type capacitance to store binary data and a transistor operating as a switch. In an overlay type DRAM cell architecture, the capacitance is formed above the transistor between the word line and the bit line. Such an architecture is shown in FIG. 1.
More particularly, each DRAM cell comprises a MOS type access transistor 3 with N+ dopant implantations 4. A contact block 5 enables the contact between the transistor and the capacitance. The capacitance is produced by litho-etching by making a slot in the silicon oxide TEOS, thus forming a ring 6 for the capacitance. The capacitance is formed by a lower electrode elec 1 and an upper electrode elec 2. Both electrodes are separated by a dielectric 7. Another contact block 8 is used to make the contact between the bit line 2 and the transistor 3.
To increase the surface for the capacitance without increasing the size of the ring 6, the lower electrode elec 1 is deposited in the form of hemispherical polysilicon grains according to a hemispherical grain polysilicon (HSG) method. This method makes it possible to double the surface, and therefore, the capacitance. The capacitance C=xcex5*S/E, where E is the thickness of the dielectric, S the surface of the capacitance and E the dielectric constant.
However, in such an architecture, the size of the capacitance is limited by alignment tolerances which are necessary for the insertion of the bit line contact. Contact is prohibited between the capacitance and the bit line. In this way, when it is necessary to increase the integration density, i.e., to produce more memory cells in the same surface unit, the implementation of the contact 8 of the bit line becomes problematic. The corresponding explanation is given with reference to FIG. 2.
First of all, it is necessary to etch a wide opening 9 in the upper electrode plate elec 2 in the middle of the capacitance to insert the contact of the bit line 8. The photoetching step of the upper electrode uses a specific mask, which is referred to as elec 2 grid. This specific mask has very strict alignment constraints with respect to the alignment of an elec 1 grid mask used at the lower level to produce the opening of the capacitance.
A first alignment rule of the upper electrode elec 2 of the capacitance with respect to the lower electrode elec 1 must be observed. Photolithography technique limitations make it necessary to account for a minimum distance with reference as marked in FIG. 2, so that the electrode elec 2 never projects onto the electrode elec 1.
A preliminary step prior to the contact photoetching step includes depositing silicon oxide to fill the rings of the capacitances, and the opening produced in the upper electrode plate elec 2. The purpose of this step is to planarize the surface and prevent any contact between the capacitance and the bit line.
The next step includes etching the contact. This step requires the use of a specific contact mask referred to as a contact grid. The contact grid must also be perfectly aligned to be able to insert the contact at the center of the opening 9 previously produced in the electrode plate elec 2. This condition is imposed by the need to connect the contact 8 with a block 5 of the tungsten interconnection level which enables the contact with the transistor.
In addition, it is necessary to prevent the metal part of the contact 8 from coming into electrical contact with the upper electrode elec 2 of the capacitance. In this way, a second alignment rule of the contact with respect to the electrode plate elec 2 must be observed. This alignment rule makes it necessary to account for a minimum distance with the reference b as marked in FIG. 2 to protect the etching of the contact 8. This ensures that the dimensions of the contact grid are included in the dimensions of the elec 2 gird used to etch the opening of the electrode plate elec 2.
Therefore, the alignment rules that must be observed to produce the contact 8 of the bit line make it necessary to account for alignment margins a and b, respectively, which are specific to the limitations of the photolithography equipment used. Therefore, this architecture limits the integration capacity of DRAM memory cells. Any reduction in the dimensions of the cell should adhere to the alignment margins, which are inherent to the photolithography tools used. The size of the capacitance is thus limited by the two alignment tolerances required for the insertion of the bit line contact.
Therefore, unless improvements in the equipment enabling the alignment of the etching masks of one level with reference to another are considered, it is not possible to reduce any dimensions in the memory cell, and consequently, integration density will not be increased. Increasing integration density of DRAM cells is very important, particularly relating to embedded memories. Irrespective of the application, for an equivalent capacitance, it is important that the memory takes up as little space as possible on the chip on which it is embedded in order to integrate the maximum number of logic functions on the chip.
The drawback of the prior art architecture discussed above therefore hinders the development of DRAM applications given that they limit the integration density of the memory cells. Another disadvantage of the prior art architecture relates to the reliability of the application method. When the dimensions of the elec 2 grid are incorrect or when it is excessively offset, a recycling loop must be used before starting the etching step. Therefore, the architecture of the prior art results in limitations in terms of productivity and cycle time.
In view of the foregoing background, an object of the present invention is to provide a DRAM architecture which makes it possible to improve the integration density, and retain the same capacitance while making up for the drawbacks of the prior art.
This and other objects, advantages and features of the present invention are provided by the removal of the elec 2 grid in the insertion of the bit line contact, thus enabling the insertion to be avoided for new generations of photolithography equipment. The invention thus also represents a benefit in terms of cost reduction.
The DRAM cell architecture according to the invention makes it possible to do away with the alignment margin, which must normally be observed during the photoetching step of the upper electrode plate elec 2. To do this, the opening of the upper electrode elec 2 for the insertion of the bit line contact is self-defined with reference to the lower electrode elec 1 of the capacitance. The invention then makes it possible to carry out a self-alignment of elec 2 on elec 1, and thus carry out the etching of the opening in the upper electrode plate elec 2 without having to take any photos. This does away with the alignment constraints inherent to the positioning of the elec 2 grid with reference to the lower level.
Advantageously, the self-alignment of the removal of the upper electrode layer elec 2 on the lower electrode elec 1 is obtained by forming a difference in topography at the point where the opening of the upper electrode plate elec 2 is to be made for the insertion of the bit line contact.
Therefore, the invention relates to a DRAM memory integration method, where each memory cell, as defined by a bit line and a word line, comprises a storage capacitance and an access transistor. The method is characterized in that it comprises the following steps:
a) depositing a barrier layer followed by a silicon oxide layer;
b) photoetching the silicon oxide to define cylinders in which the capacitances are to be formed;
c) depositing a first polysilicon layer to form the lower electrode of the capacitances;
d) mechanical-chemical polishing to remove the polysilicon from the first layer between the capacitances;
e) removing part of the silicon oxide layer to create a difference in topography between each lower electrode and the silicon oxide layer;
f) depositing a dielectric layer;
g) depositing a second doped polysilicon layer to form a continuous upper electrode plate, the difference in topography being only retained in a zone where it is necessary to open the upper electrode plate to insert the bit line contact;
h) depositing a third non-doped polysilicon layer;
i) implanting dopants in the third non-doped polysilicon layer so as only to implant the upper part of the layer located in the zone showing the difference in the topography;
j) selective etching to only remove the part of the non-doped polysilicon layer located in the lower part of the zone; and
k) etching to remove the entire remainder of the third polysilicon layer and the part of the upper electrode layer located in the lower part, with the removal of the upper electrode layer being self-aligned on the lower electrode.


In the case of a narrow band in which the number of sub-carriers to be used for the concurrent transmission is smaller than a predetermined value, an RSRP estimation unit carries out processes in an order of time-wise in-phase addition, frequency-wise averaging, and conjugate multiplication, with respect to the channel estimation values estimated by the channel estimation unit; and in the case of a wide band in which the number of sub-carriers to be used for the concurrent transmission is greater than the predetermined value, the RSRP estimation unit carries out processes in an order of frequency-wise averaging, conjugate multiplication, and time-wise in-phase addition, with respect to the channel estimation values estimated by the channel estimation unit.

An Orthogonal Frequency Division Multiplexing (OFDM) method, such as Long Term Evolution (LTE), standardized by 3rd Generation Partnership Project (3GPP) attracts attention as a communication method for the next generation. In a communication method such as LTE, a receiver needs to report reference signal received power (RSRP) to a higher-level layer, as stipulated in NPL1. On the basis of such information as RSRP that a receiver estimates, it is judged whether a handover process is performed between base stations or not. In order to perform the handover process with an appropriate base station, it is needed to improve the accuracy of power estimation by the receiver.
In a conventional communication method of Code Division Multiple Access (CDMA), a measurement of RSRP is performed by way of in-phase addition of pilot signals after Rake combining, for example, as described in NPL2. Then, in order to improve the estimation accuracy, proposed are, for example, a method of estimating RSRP with a high degree of accuracy by using a signal before Rake combining, as described in PTL1; as well as another method that applies a value with high accuracy while concurrently using in-addition and root-mean-square of received signals, as described in PTL2.
Unfortunately, in a communication method of OFDM for concurrently transmitting information by using a plurality of sub-carriers (sub-carrier waves), channel estimation values turns if an offset exists on the timing of FFT (Fast Fourier Transformation). Therefore, if in-phase addition is performed with those channel estimation values as they are, sometimes RSRP may be estimated to be smaller than it should actually be. FIG. 5 shows such an example. NPL3 discloses an introduction of a method in which in-phase addition is performed after conjugate multiplication between neighboring channel estimation values, for solving such a challenge.
On the other hand, LTE needs to estimate RSRP with accuracy stipulated in NPL4. Meanwhile, it is difficult for the method disclosed in NPL3 to estimate RSRP with accuracy that meets those stipulated specifications.

Receiver and signal received power estimation method


A first conduction part (12) coated with a conductive paint is formed on a back housing (1CAR) to be attached to one housing of a portable telephone unit at a position near a hinge mechanism (9) which connects the one housing to the other housing of the portable telephone unit. A GPS antenna is disposed on the hinge mechanism (9) side inside the other housing. The first conduction part (12) is in contact with a conductive connection terminal (21). A condenser element (22C) and a coil element (22L) are connected in parallel between the connection terminal (21) and a reference potential line (10G) of a first circuit board (10) disposed inside the aforementioned one housing.

Wireless terminal devices having wireless functions, such as mobile phones, have technologies with which, by regarding circuit boards inside housings as conductors and by integrating these into some sections of dipole antennas, radiation characteristics of the antennas are improved. For example, in the patent document 1, wireless terminal devices in which, by establishing conductivity with the ground of the respective circuit boards using a connecting section of an upper housing and a lower housing, the full length of the dipole antenna is deployed, and in which the radiation characteristics are improved even in the state in which the housings are open, are disclosed. Moreover, in the patent document 2, it has been disclosed that by electrically connecting the circuit component that is mounted on the lower circuit boards of the lower housing to the circuit component that is mounted on the upper circuit board of the upper housing with flexible cables, the full length of the dipole antenna is deployed.


A system and method for assisting a user in navigation of an image dataset are disclosed. The method includes receiving a user's text query, retrieving images responsive to the query from an image dataset, providing for receiving the user's selection of a first feature selected from a set of available first features via a graphical user interface, providing for receiving the user's selection of a second feature selected from a set of available second features different from the first features via the graphical user interface, and displaying at least some of the retrieved images on the graphical user interface. The displayed images are arranged, e.g., grouped, according to levels and/or combinations of levels of the user-selected first and second features.

The exemplary embodiment relates to the field of image retrieval and selection. It finds particular application in the context of a navigation system and method for searching a database of images.
Digital images are acquired and stored in large numbers for later use in connection with a variety of applications, such as commercial design, editorial work, professional digital photography, and asset management. Retrieval of images by conventional searching techniques is often time consuming. For example, if a collection has been tagged appropriately, a user may enter a textual query, such as "flower," and retrieve a large number of images responsive to the query, e.g., those which have been manually tagged as containing flowers. Other methods for retrieval are based on feature extraction techniques. For example, an automated system may propagate tags of manually labeled images to unlabeled images based on similarity of extracted features. Or, the user may input an image of a flower and similar images are retrieved automatically by comparing the features of the input image with those of the stored images.
Image searching generally entails a compromise between narrowly defining and delimiting the search space through the use of explicit criteria, and browsing a sufficiently large sample of the available images to ensure that the most suitable or aesthetically appealing ones are not missed. This leaves the user with a relatively large subset of images. Thus, browsing remains the primary method for section of images.
Current systems, such as Google Images™ and FLICKR™ image systems, perform image searches based on content and provide very basic options for aesthetic refinement. However, they do not provide tools for feature combination searches. At best, they allow users to select and chain together a sequence of refinement criteria. For example in Google Images, a user can search by content such as the query "sky" and then click on the "blue" box to get the blue sky images. This type of browsing makes moving back and forth between selected feature refinements and exploration of different combinations of features impractical.

System for creative image navigation and exploration


Catalysts useful for epoxidizing olefins are disclosed. The catalysts comprise a vinylpyridine polymer and a titanium zeolite. Preferably, the vinylpyridine polymer encapsulates the titanium zeolite. The catalysts are easy to prepare and use, they are easy to recover and reuse, and they convert olefins to epoxides in good yields with high selectivity. Surprisingly, ring-opening reactions that form glycol or glycol ether by-products are minimized by using the vinylpyridine polymer-containing catalysts. The catalysts are valuable for making propylene oxide from propylene and hydrogen peroxide. Vinylpyridine polymer-encapsulated transition metals and their use to produce hydrogen peroxide from hydrogen and oxygen is also disclosed.

Titanium zeolites, i.e., synthetic molecular sieves that incorporate titanium atoms in a silicate framework, catalyze a wide variety of valuable oxidative organic reactions. The versatility of titanium zeolites, particularly TS-1, for arene hydroxylation, alkane oxidation, olefin epoxidation, thioether oxidation, Baeyer-Villiger oxidation reactions, and other important transformations is well known. For a review, see P. Kumar et al., Synlett. (1995) 289. Titanium zeolites catalyze the epoxidation of propylene with hydrogen peroxide. The hydrogen peroxide can be supplied (see, e.g., U.S. Pat. No. 6,037,484) or it can be generated "in situ" by using titanium zeolites that incorporate a transition metal, especially palladium (see U.S. Pat. No. 6,008,388 and references cited therein).
Unwanted hydrogenation of propylene to propane complicates the "in situ" epoxidation of propylene using hydrogen, oxygen, and a transition metal-containing titanium zeolite. Nitrogen compounds such as ammonium hydroxide or ammonium bromide have been added to suppress propane formation (see U.S. Pat. No. 6,008,388). Nitrogen-containing polymers were not suggested.
Another side reaction is common to olefin epoxidations with hydrogen peroxide: zeolite-promoted ring opening of the epoxide with water and/or alcohol solvents to give glycols and glycol ethers. For example, when PO is made from propylene using TS-1 as a catalyst in aqueous methanol, ring opening reactions typically limit the PO/POE (molar ratio of propylene oxide to propylene oxide plus ring-opening products that derive from PO) to about 91% at 50° C. Selectivity deteriorates as temperature increases. In addition to sacrificing valuable epoxide product, ring opening introduces impurities that must be removed. U.S. Pat. No. 6,037,484 teaches to add 2,4-lutidine or another substituted pyridine compound to the hydrogen peroxide feed to suppress ring opening. Soluble pyridines such as these must be continually replenished in any continuous process for making an epoxide. Polymers containing pyridine moieties are not suggested.
Recently, we discovered that polymer-encapsulated titanium zeolites are valuable oxidation catalysts (see, e.g., copending application Ser. No. 10/796,842, filed Mar. 9, 2004), particularly for olefin epoxidations. In particular, we found that polymer encapsulation improves catalyst filterability (an advantage for both catalyst preparation and catalyst recovery) and provides a significant improvement in selectivity to propylene oxide (from 91% to 93% PO/POE). We also found that polymer-encapsulated transition metals effectively catalyze the reaction of hydrogen and oxygen to make hydrogen peroxide (see copending application Ser. No. 10/796,810, filed Mar. 9, 2004). Vinylpyridine polymers were not disclosed.
While the pharmaceutical industry has used polymer encapsulation for years to mask taste, impart storage stability, reduce stomach irritation, target delivery, or control release of drugs, benefits of the technique for catalysis are just now being realized (for examples, see Chem. Commun. (2003) 449 and references cited therein; Angew. Chem. Int. Ed. 40 (2001) 3469; J. Am. Chem. Soc. 120 (1998) 2985).
In sum, the industry would benefit from improved oxidation catalysts. In particular, the industry needs olefin epoxidation catalysts that provide good selectivity while minimizing ring-opening side reactions. Catalysts that can provide good selectivity over a wide temperature range would be especially valuable. Ideally, the catalysts would be inexpensive and easy to make. Catalysts for making hydrogen peroxide directly from hydrogen and oxygen are also needed.


A modular power connector includes an insulation main body, at least one conducting element, at least one electricity-delivering element, and at least one engaging element. The conducting element is partially accommodated within the insulation main body, and includes a perforation. The electricity-delivering element has a bare part at an end thereof. The engaging element is fixed on the bare part of the electricity-delivering element, and includes an elastic extension part and a stopping part. The elastic extension part is subject to elastic deformation during the elastic extension part is penetrated through the perforation of the conducting element. The elastic extension part is restored to an original shape after the elastic extension part is penetrated through the perforation, so that the conducting element is clamped between the elastic extension part and the stopping part.

Power connectors are used as connective interfaces in various power delivery systems. For assuring secure contact between two power connectors, these two power connectors have respective mechanical fastening elements for fixing the conductors within the power input sides of the power connectors.
FIG. 1A is a schematic perspective view illustrating a modular power connector according to the prior art. The modular power connector 10 comprises an insulation main body 101, a first conducting terminal 103, a second conducting terminal 104, a first conducting pin (not shown), a second conducting pin 105 and two power wires 106. A receptacle 102 is disposed within the insulation main body 101 for accommodating the first conducting terminal 103 and the second conducting terminal 104. The first conducting terminal 103 and the second conducting terminal 104 penetrate through corresponding holes (not shown), which are formed in the backside of the insulation main body 101. The first conducting terminal 103 and the second conducting terminal 104 are respectively coupled with the first conducting pin and the second conducting pin 105 by a welding means or a riveting means. In addition, one of the two power wires 106 has a first end connected to the first conducting pin and a second end connected to an internal circuit board (not shown) of the electronic device. The other of the two power wires 106 has a first end connected to the second conducting pin 106 and a second end connected to the internal circuit board of the electronic device. As such, the modular power connector 10 could be electrically connected with the internal circuit board of the electronic device.
FIG. 1B is a schematic perspective view illustrating the second conducting pin of the modular power connector as shown in FIG. 1A. As shown in FIG. 1B, the second conducting pin 105 comprises an opening 1051, a perforation 1052 and a wire-securing part 1053. The second conducting pin 105 is aligned with a corresponding hole of the backside of the insulation main body 101. Through the hole and the opening 1051, the second conducting terminal 104 is coupled with the second conducting pin 105 by welding or riveting. A bare part 1061 at the first end of the power wire 106 is penetrated through the perforation 1052 of the second conducting pin 105, and then wrapped around the wire-securing part 1053 for at least one turn (see FIG. 1C). Then, solder paste 107 is applied on the bare part 1061 of the power wire 106, so that the bare part 1061 of the power wire 106 is fastened onto the wire-securing part 1053 by welding (see FIG. 1D).
Although the connection between the power wire 106 and the second conducting pin 105 meets the electrical safety regulation, there are still some drawbacks. For example, the power wire 106 is mechanically fastened onto the second conducting pin 105 after the bare part 1061 of the power wire 106 is penetrated through the perforation 1052 of the second conducting pin 105 and wrapped around the wire-securing part 1053. Since the power wire 106 and the second conducting pin 105 are very small in sizes, it is difficult to penetrate the power wire 106 through the perforation 1052 and wrap the power wire 106 around the wire-securing part 1053 at the lateral side of the insulation main body 101. Under this circumstance, the assembling process of the power connector is troublesome and the throughput thereof is undesired.
Therefore, there is a need of providing a modular power connector so as to obviate the drawbacks encountered in the prior art.


A method of producing cellulase includes steps (1) to (3): (1) subjecting an aqueous solution of cellulase derived from filamentous fungi to filtration through an ultrafiltration membrane with a molecular weight cut off of 100,000 to 200,000 to obtain a filtrate and concurrently obtain a concentrated enzyme liquid as a retentate; (2) further subjecting the filtrate obtained in step (1) to filtration through a second ultrafiltration membrane with a molecular weight cut off of 5,000 to 50,000 to obtain a second concentrated enzyme liquid as a retentate; and (3) mixing the concentrated enzyme liquid obtained in steps (1) and (2) to obtain cellulase derived from filamentous fungi.

Polysaccharides such as starch or cellulose are available as biomass resources. A method of producing monosaccharides such as glucose or xylose by enzymatically hydrolyzing such polysaccharides has been known. The sugar liquid obtained by breaking down such polysaccharides is widely used as carbon sources in microorganism culture. In particular, as an enzyme that hydrolyzes cellulose, cellulase is known. As microorganisms that produce this cellulase, filamentous fungi are known. The filamentous fungi produce a large amount of cellulases as extracellular enzymes by setting up culture conditions to inductively produce the cellulase. As these filamentous fungi, available are filamentous fungi such as the genus Aspergillus, the genus Humicola, the genus Mucor, the genus Trichoderma, and the genus Acremonium, which are widely used in production of cellulase.
Enzyme components that exhibit various substrate specificities are present in cellulase derived from filamentous fungi. Specifically, present are cellobiohydrolase that acts on the crystalline region of cellulose, endoglucanase that acts from within cellulose molecular chain to reduce the molecular weight thereof, β-glucosidase that acts on water-soluble oligosaccharides or cellobiose, and hemicellulase that acts on hemicellulose. It has been known that each of these enzyme components with varied substrate specificity acts synergistically on cellulose fibers and thereby efficient degradation of cellulose is taken place (see Encyclopedia of Cellulose, Chapter 6, Biodegradation of Cellulose (edited by The Cellulose Society of Japan, 2000)). It has also been known that, in such a cellulase derived from filamentous fungi, each of the enzyme components whose molecular weight varies in size from small to large is present, wherein the molecular weight ranges from 20 to 100 kDa.
With regard to cellulase derived from filamentous fungi, methods of membrane separation and concentration using an ultrafiltration membrane in the same manner as common enzymes are known. For instance, methods of separation and recovery of cellulases using an ultrafiltration membrane have been known, which method comprises membrane separation and concentration of cellulases from a culture of microorganisms such as filamentous fungi or a cellulose hydrolysate obtained by using the cellulase (see WO 2007/034999 and Japanese Patent Application Laid-Open Publication Nos. 2010-221136 and 2009-240167). As a treatment prior to the step of the membrane separation and concentration through such an ultrafiltration membrane, methods have been suggested, which method comprises removing in advance solids contained in an aqueous solution of cellulase from a microorganism culture or cellulose hydrolysate by use of, for example, a ceramic spin filter (see JP '136) or a non-woven fabric with a pore diameter of 20 to 200 μm (see JP '167). Yet, for the membrane separation and concentration of each of the cellulase components, it has been common to use an ultrafiltration membrane having a fine pore diameter or molecular weight cut off that sufficiently blocks molecular weight corresponding to the cellulase component to be recovered.
In the membrane separation and concentration of filamentous fungi cellulase using a conventional ultrafiltration membrane, problems have included fouling of the ultrafiltration membrane and inactivation or aggregation of the cellulase component. These problems have caused a filtration treatment speed of the ultrafiltration membrane to become slower or have caused a cellulase activity obtained by the ultrafiltration membrane to become lower, which has been also problematic.
In view of this, it could be helpful to provide a method of efficient membrane separation and concentration of cellulase components derived from Trichoderma by using an ultrafiltration membrane and to provide a device therefor.

Method for producing cellulase and apparatus for said method


A power conversion circuit includes an input terminal, a first switching element, a second switching element, a third switching element, a fourth switching element, a capacitor; an inductor; and a controller configured to control the switching elements to be switched ON/OFF, such that a voltage at the load is regulated by repetitively (1) charging the inductor with a first current before charging the capacitor causing a second current to flow in the inductor and (2) charging the inductor with a third current before discharging the capacitor causing a fourth current to flow in the inductor.

Various electronic devices such as computers and mobile phones are powered by regulated DC power sources. A power conversion circuit is used as, for example, a DC-to-DC converter that charges/discharges a capacitor by a switching operation of transistors to convert a high voltage input from a battery or another power source into a predetermined output voltage.
As electronic devices become smaller, lighter and more compact, the size and the performance of the dedicated power conversion circuits need to be improved. Increasing the switching frequency of the power conversion circuit has been one of the primary solutions provided to reduce the size and the cost of the large passive components. However, as the switching frequency of the power conversion circuit increases, the switching losses increase too.
Furthermore, the power handling performance is usually limited to the spec of the resonant components (e.g., capacitors and inductors) used in the power conversion circuit. When the size of the resonant components is reduced, the power handling performance of the power conversion circuit may be deteriorated. That is, there is a trade-off relationship between the switching frequency and the power handling performance of the power conversion circuit.

Power conversion circuit and associated operating method


According to one embodiment, a multi-bit delta-sigma time digitizer circuit includes a delay array including delay selection circuits respectively including a delay element and a multiplexer, a phase comparator calculating a time difference, an integrator integrating the time difference output, a flash A/D converter executing digital conversion, a ring oscillation circuit including the delay array, a counter measuring a number of clock signal pulses, a memory storing a delay value of the delay element, and a processor correcting an output result of the A/D converter based on the delay value when the rising timing interval is measured.

In recent years, a ΔΣ TDC (Time-to-Digital Converter) which is required to measure a time difference between two repetitive clocks with high time resolution and by a simple circuit has been proposed. By configuring this ΔΣ TDC as a multi-bit circuit, finer measurement can be attained for an identical measurement time compared to a 1-bit circuit.
However, in the multi-bit circuit, since the number of delay elements increases, delay values of a plurality of delay elements may vary relatively. When such delay mismatch has occurred, if an output calculation is made intact, an output result becomes nonlinear, thus causing a measurement error.
Also, a method of making error correction by estimating error components of an internal DAC of a ΔΣ ADC in a digital manner has been reported. With this method, correction is attained by subtracting estimated error components at the output timing. However, this error correction method is not used in the TDC.

Multi-bit delta-sigma time digitizer circuit and calibration method thereof

Semiconductor Technology Academic Research Center


A circuit for improving the control of a change in state of a signal in an electronic device between a first state and a second state, wherein a first change in state occurs when the state changes from the second state to the first state and a second change in state occurs when the state changes from the first state to the second state and wherein the first and second changes in state have associated therewith a first and a second time delay over which each change in state occurs, characterized in that said circuit comprises a determining unit for measuring the first time delay and a calculator for calculating a common delay to replace one or more of the first and second delays to thereby improve the control of the change in state of the signal.

Pulse width modulation (PWM) is a technology which modulates an electronic signal or a power source in order to transmit information to an electronic device or to control the amount of power sent to an electronic device. PWM occurs in many applications such as power lighting applications for example.
With PWM technology the amount of power sent to a light device such as a Light Emitting Diode (LED), through a switch such as a MOS power transistor or MOSFET (Metal Oxide Semiconductor Field Effect Transistor), can be controlled. The use of PWM technology with low duty cycles requires that the time delay for switching on the MOSFET and the corresponding time delay for switching off the MOSFET are nearly symmetrical. The aim is to ensure that the ON time of the input control signal of the MOSFET equals the ON time of the output voltage of the MOSFET. Thus, the MOSFET can run with low duty cycle. Therefore, the power of the LED is modulated and the lifetime of the LED is greatly enhanced. However, the MOSFET takes generally more time to switch off than to switch on. The unsymmetrical time delays for switching on and off the MOSFET come from the manufacturing process and dynamic characteristics of MOSFET technology.
Indeed the manufacturing process gives rise to mistakes caused by etching and metallization process for example. With these, there is no guarantee that each integrated circuit will have exactly same characteristics for each component thereon. This difference in behaviour of various components of the MOSFET leads further additional time delay between the switching off and switching on processes of a lighting device such as an LED.
US 2003/201811 discloses a method and device for symmetrical slew rate calibration. The aim of US2003/201811 is to directly measure slew rates for push pull driver devices in order to calibrate slew rates. The method uses a driver acting as an oscillator.
U.S. Pat. No. 7,133,790 discloses a method and system of calibrating a control delay time. The method uses a comparison step which uses a predefined pattern.

System and method to improve switching in power switching applications


Various embodiments are described to enable improved inter-network/inter-technology handover of mobile devices. A network device (131, 132) collects dynamic information corresponding to mobile devices (101, 102), such as wireless measurement information at the device's location, and/or information corresponding to wireless network nodes (121-124), such loading levels/loading distributions. The network device then sends some or all of the dynamic information collected and/or statistical information generated from the dynamic information collected to a neighboring network information server (150) for access by other communication networks. By maintaining dynamic and/or statistical information in a neighboring network information server, such information can be made available to all the communication networks in a given region. One potential benefit to making this information available is improved inter-network handoff decision-making.

Mobile devices with multi-technology radio interfaces (a.k.a., multi-modal terminals) are emerging. It is widely expected that multi-modal mobile terminals will soon allow handover of active sessions from one access network to another (i.e., an inter-technology handover). Standards for supporting seamless inter-technology handover of multi-modal mobile terminals have been under development in, e.g., 3GPP, 3GPP2, WiMax, and IEEE802. And a key component proposed in the standards for enabling seamless inter-technology handover is a technology independent (a.k.a., a media independent) handover information service that can provide neighboring network information for a given location to a handover decision engine located in either the terminal or the network. At the present, neighboring network information service proposals include configured/provisioned information, such as the network type, operation IDs, designed capability, policy of access networks available in the area, the owner and service specifics of each available network, and the specifics of each Access Point (AP) or Base Station (BS) of each available network. However, in view of the ongoing work in this area, new techniques able to improve the inter-technology handover by multi-modal mobile terminals are clearly desirable for advancing the art.
Specific embodiments of the present invention are disclosed below with reference to FIGS. 1-5. Both the description and the illustrations have been drafted with the intent to enhance understanding. For example, the dimensions of some of the figure elements may be exaggerated relative to other elements, and well-known elements that are beneficial or even necessary to a commercially successful implementation may not be depicted so that a less obstructed and a more clear presentation of embodiments may be achieved. In addition, although the signaling flow diagrams and/or the logic flow diagrams above are described and shown with reference to specific signaling exchanged and/or specific functionality performed in a specific order, some of the signaling/functionality may be omitted or some of the signaling/functionality may be combined, sub-divided, or reordered without departing from the scope of the claims. Thus, unless specifically indicated, the order and grouping of the signaling/functionality depicted is not a limitation of other embodiments that may lie within the scope of the claims.
Simplicity and clarity in both illustration and description are sought to effectively enable a person of skill in the art to make, use, and best practice the present invention in view of what is already known in the art. One of skill in the art will appreciate that various modifications and changes may be made to the specific embodiments described below without departing from the spirit and scope of the present invention. Thus, the specification and drawings are to be regarded as illustrative and exemplary rather than restrictive or all-encompassing, and all such modifications to the specific embodiments described below are intended to be included within the scope of the present invention.

Facilitating mobility between multiple communication networks


An optical resin film is provided and fulfills the following formulae (A) to (D) concerning retardations and is formed by using a polymer or a copolymer of a cycloolefin compound:0.1<Re(450)/Re(550)<0.95;  (A)1.03<Re(650)/Re(550)<1.93;  (B)0.4<(Re(450)/Rth(450)/Re(550)/Rth(550))<0.95; and  (C)1.05<(Re(650)/Rth(650)/Re(550)/Rth(550))<1.9.  (D)

Liquid crystal displays have been widely used in monitors of personal computers and mobile telephones, TV sets and so on because of having a number of merits such as running at low voltage, requiring little electricity and being available in downsized and thinned modes. These liquid crystal displays have been proposed in various modes depending on the aligned states of liquid crystal molecules in liquid crystal cells. Among all, the TN mode, wherein liquid crystal molecules are aligned at a twist angle of about 90° from the lower substrate of a liquid crystal cell toward the upper substrate, has been mainly employed.
A liquid crystal display is usually made up of a liquid crystal cell, an optically compensatory sheet and a polarizer. As the optically compensatory sheet, which is employed to relieve image coloration or enlarge viewing angle, use has been made of films obtained by coating a stretched birefringent film or a transparent film with liquid crystals. For example, Patent Document 1 discloses a technique wherein an optically compensatory sheet, which is obtained by coating discotic liquid crystals on a triacetylcellulose film and then fixing by orientation, is applied to a TN mode liquid crystal cell to thereby enlarge the viewing angle. In a liquid crystal display for a wide-screen TV likely watched from various angles, however, accurate viewing angle-dependency is required and this requirement cannot be fulfilled by using the techniques as discussed above. Thus, studies have been made on liquid crystal displays in modes different from the TN mode, for example, the IPS (in-plane switching) mode, the OCB (optically compensatory bend) mode and the VA (vertically aligned) mode. Among all, the VA mode has attracted public attention as a liquid crystal display for TV since it establishes a high contrast and can be produced at a relatively high yield.
However, the VA mode suffers from a problem that though it provides almost complete black display in the normal line direction of the panel, light leakage arises in observing the panel from an angle and thus the viewing angle is narrowed. To solve this problem, there has been proposed a method of relieving the light leakage by the combined use of a first phase contrast plat having a positive refractive index anisotropy (nx>ny=nz) with a second phase contrast plat having a negative refractive index anisotropy (nx=ny>nz) (see, for example, Japanese Patent No. 3027805). It has been also proposed to improve the viewing angle characteristics of a VA mode liquid crystal display by using an optically biaxial phase contrast plate (nx>ny>nz) (see, for example, Japanese Patent No. 3330574), wherein nx, ny and nz respectively stand for the refractive indexes in the X-axis, Y-axis and Z-axis directions. The X-axis direction corresponds to the direction showing the maximum refractive index in the in-plane direction of the phase contrast plate, the Y-axis direction corresponds to the direction perpendicular to the X-axis direction in plane, and the Z-axis direction corresponds to the thickness direction perpendicular to the X-axis and Y-axis directions as described above.
By these methods, however, light leakage within a certain wavelength range (for example, green light at around 550 nm) can be exclusively relieved and no attention is paid to light leakage in other wavelength ranges (for example, blue light at around 450 n, or red light at around 650 nm). Therefore, so-called color shift (i.e., coloration in blue or red in the case of, for example, looking black display at an angle) cannot be improved thereby.
To obtain a definite image in vivid colors, a phase plate for liquid crystal displays should have a birefringent layer being optically even on the whole face and show no change in the optical characteristics due to changes in temperature or humidity. As materials for these phase plates, there have been proposed to use thermoplastic resin films as reported in Japanese Patent No. 3273046.
However, color shift as discussed above cannot be improved even by using such films as reported in Japanese Patent No. 3273046.

Optical resin film and polarizing plate and liquid crystal display using same


A system (100) includes a first end feeder device (103-1), and a second end feeder device (103-2) upstream in a media transport path from the first end feeder device (103-1). Each of the feeder devices (103-1, 103-2, 105-1, 105-2) is configured to feed a piece of a print medium (205) to a neighboring device (103-2, 105-1, 105-2) downstream in the media transport path only after receiving a logical token from the neighboring downstream device (103-2, 105-1, 105-2) corresponding to the piece of print media (205).

Printing devices are used to produce desired images, such as text and graphics, on various types of media. Due to the wide scope of applications for which printing is sought and the versatility of printing technology, printing devices are prevalent in modern offices and homes.
In some cases, printing devices may be designed to print to a variety of different types of print media, thus enhancing the versatility and utility of the devices. Many such printing devices include automatic media feeder devices that store different types of print media (i.e. different sizes and/or compositions) in separate trays. Additionally, some automatic media feeder devices may store one type of media in multiple trays, particularly when that particular type of media is used more often by the printing device than other types of media.
When such a printing device begins a printing job, it typically designates a piece of media from those available in the feeder device and requests the feeder device to provide the selected media type. The feeder device can then transport the requested piece of print media to the printing device using a print medium feed mechanism which may include, for example, motorized rollers, belts, and/or suction.
Some printing devices are coupled to several concatenated feeder devices to allow access to greater amounts of media storage and/or more types of print media. In a system of concatenated feeder devices, print media may be transported through more than one of the feeder devices before being received by the printing device.
Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.

Systems and methods of printing using concatenated media feeder devices


A cold cathode fluorescent lamp (30) includes a working gas (32), a transparent tube (34), a cold cathode (36), and an anode (38). The transparent tube receives the working gas therein, and the transparent tube has an inner surface (340). A coating (342) is formed on the inner surface of the transparent tube. The cold cathode and the anode are disposed at two ends of the transparent tube separately. A backlight module (50) includes a light guide plate (52) having a light incident surface (520), and the cold cathode fluorescent lamp as described above disposed adjacent the light incident surface.

A CCFL is a kind of gas-discharge light source, which is widely used as light source for light source device such as backlight module used in thin film transistor liquid crystal display (TFT-LCD), LCD-TV, notebook, or portable digital video disc (DVD).
Referring to FIG. 3, generally a CCFL 10 includes a transparent tube 12, a cold cathode 14, an anode 16, and a fluorescent layer 18. The fluorescent layer 18 is formed on an inner surface of the transparent tube 12. The cold cathode 14 and the anode 16 are respectively disposed at two ends of the transparent tube 12 and are electrically connected to an exterior power source. The transparent tube 12 is filled with mercury vapor and an inert gas.
When the power source supplies a current to the cold cathode and the anode, an electric field therebetween is produced and electrons are emitted from the cold cathode. The electrons are accelerated by the electric field and then collide with gaseous molecules of the mercury vapor and the inert gas. This causes excitation of the mercury vapor and radiation of ultraviolet rays. The ultraviolet rays irradiate a fluorescent material of the fluorescent layer, whereby a part of the ultraviolet rays are converted into visible lights.
The CCFLs are more efficiently than light emitting diodes (LEDs) when they are used in the backlight modules. However, the brightness and the efficiency of CCFLs are not high enough.
What is needed, therefore, is a cold cathode fluorescent lamp with high efficiency and high brightness.

Cold cathode fluorescent lamp with mixing gas filled therein and backlight module using same