Apparatuses, systems, and methods for determining and verifying operational states of fifth wheels. Certain methods for determining the operational state of the fifth wheel may include sensing, with at least one sensor, magnetic flux caused by a magnet on a movable component movable to lock the fifth wheel to a kingpin of a towed vehicle and determining an end position of the movable component based on the magnetic flux. The end position of the movable component is then compared to a threshold position and an operational state of the fifth wheel is determined based on the comparison of the end position of the movable component to the threshold position.

The following U.S. Patents are incorporated herein by reference in entirety.
U.S. Pat. No. 5,516,138 discloses a mechanism for locking and unlocking of a kingpin of a fifth wheel. The mechanism includes a jaw member, a wedge member, a bumper member and a lever member interconnecting the jaw member, the wedge and the bumper member. A handle member includes a handle extension member.
U.S. Pat. No. 5,641,174 discloses an interconnection of the jaw, wedge and operating handle in a fifth wheel facilitates the provision of an indicator on a secondary locking mechanism which further ensures the security of the system. The jaw is connected to the operating handle by a pivoting timing lever which pivots off a pin on the jaw such that the jaw remains engaged with the fifth wheel until the wedge is substantially removed from engagement with the jaw.
U.S. Pat. No. 7,735,849 discloses a fifth wheel hitch, a locking mechanism for retaining a trailer kingpin within a fifth wheel slot. The locking mechanism includes a jaw assembly comprised of two opposing jaw members pivotally attached at one end to the underside of the hitch plate, a longitudinally sliding cam interposed between the jaw members with a tip that contacts a bumper. The bumper is pivotally attached to tie bar that has its rear most end pivotally attached to the underside of the hitch plate. The mechanism also includes a wedge member and a secondary lock member pivotally attached thereto, where the lock member has a guide extension inserted through a guide hole in the tie bar.
U.S. Pat. No. 8,210,558 discloses a secondary lock assembly for a fifth wheel, where the fifth wheel includes a hitch plate with a rearward opening slot to receive a trailer kingpin and a transversely sliding primary locking member for retaining the kingpin within the slot. The assembly comprises a tie bar pivotally connected at its middle to the primary locking member and a transversely oriented pull bar pivotally connected at an inner end to the forward end of the tie bar. The pull bar comprises a rearward offset tab. A latch is pivotally connected roughly at the center of the latch to the forward end of the tie bar.
U.S. Pat. No. 9,302,557 discloses a fifth wheel includes a top plate having a throat that is adapted to receive a kingpin of a trailer. The fifth wheel is equipped with a locking mechanism including a jaw slidably connected to the top plate and slidable between a closed position where the jaw blocks passage of a kingpin out of the throat of the fifth wheel and an open position where a kingpin may pass into and out of the throat of the fifth wheel. The jaw has an edge adapted to engage a kingpin positioned in the throat of the fifth wheel when the jaw is in the closed position.
U.S. Pat. No. 9,327,782 discloses a fifth wheel includes a top plate having a throat that is adapted to receive a kingpin of a trailer. The fifth wheel is equipped with a locking mechanism including a jaw slidably connected to the top plate and slidable between a closed position where the jaw blocks passage of a kingpin out of the throat of the fifth wheel and an open position where a kingpin may pass into and out of the throat of the fifth wheel. The jaw has an edge adapted to engage a kingpin positioned in the throat of the fifth wheel when the jaw is in the closed position.
U.S. Pat. No. 9,738,333 discloses a fifth wheel includes a top plate having a throat that is adapted to receive a kingpin of a trailer. A pair of locking jaws are pivotally connected to the top plate and pivotal between a closed configuration where the pair of locking jaws block passage of a kingpin out of the throat and the locking jaws are held primarily in compression and an open configuration where a kingpin may pass into and out of the throat.


A semiconductor integrated circuit includes a first power supply line which supplies an external power supply voltage provided from an exterior of the circuit, a second power supply line which supply an internal power supply voltage to an interior circuit, a plurality of NMOS transistors which are situated at different locations, and have drain nodes thereof coupled to the first power supply line and source nodes thereof coupled to the second power supply line, and a regulator circuit which supplies a reference voltage to gate nodes of the plurality of NMOS transistors.

The present application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2002-172770 filed on Jun. 13, 2002, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and particularly relates to a semiconductor integrated circuit which is provided with a built-in DCxe2x80x94DC regulator.
2. Description of the Related Art
Semiconductor integrated circuits in recent years tend to use a reduced power supply voltage to drive internal circuitry due to an increasing degree of finer fabrication and higher circuit density. To this end, a DCxe2x80x94DC regulator is provided inside devices for the purpose of reducing an externally provided power supply voltage to generate an internal power supply voltage. This internal power supply voltage is supplied to each circuit part inside the integrated circuit.
FIG. 1 is an illustrative drawing showing a structure relating to the supply of a power-supply voltage in a related-art semiconductor integrated circuit.
In the semiconductor integrated circuit of FIG. 1, an external power supply voltage VCC applied to a power-supply input terminal 11 is led to a DCxe2x80x94DC regulator 12. The DCxe2x80x94DC regulator 12 generates an internal power supply voltage by reducing the external power supply voltage VCC, and transmits the internal power supply voltage to power supply lines 13. The power supply lines 13 are laid out to reach each corner of the semiconductor integrated circuit in order to supply the internal power supply voltage to each interior circuit 15. Further, the power supply lines 13 are connected to a terminal 14 to which a condenser is to be coupled for the purpose of suppressing oscillation. A ground voltage VSS is supplied to ground terminals 16 from the exterior, and is supplied to each circuit unit inside the semiconductor integrated circuit.
FIG. 2 is an illustrative drawing for explaining an operation of the mechanism as shown in FIG. 1 that supplies a power supply voltage.
In FIG. 2, an external power supply voltage is denoted as V1, and an internal power supply voltage is designated as V2. The DCxe2x80x94DC regulator 12 receives the external power supply voltage V1, and reduces it to generate the internal power supply voltage V2. The internal power supply voltage V2 is transmitted to the power supply line 13. The power supply line 13 extends a long distance, so that a potential drop as shown in the upper half of FIG. 2 is observed. In the upper half of FIG. 2, the horizontal axis represents the extension of the line, and the vertical axis represents the power supply voltage.
A drop in the power supply voltage caused by line resistance inside semiconductor integrated circuits has been recognized as a cause of circuit malfunction. In order to obviate this problem, software may be used to estimate electric current running through the power supply lines, and the power supply lines may be widened through optimization based on the software analysis. This method, however, offers only a limited effect of voltage-drop reduction. As a different measure, regulators may be provided for respective circuit modules that consume power supply, thereby stabilizing a power supply voltage at each of the circuit modules. Since a power supply circuit occupies a relatively large area inside semiconductor integrated circuits, this method is not practical from an economic standpoint. It is conceivable to adopt a circuit design that provides a voltage margin by taking into account a power supply voltage drop. This is not desirable because such a design puts a limit on performance. Since a power supply voltage of recent semiconductor integrated circuits has been lowered significantly, a tolerable range of an internal power supply voltage is now quite narrow. As a result, it is becoming increasingly difficult to cope with this issue through simple design modification.
Accordingly, there is a need for a semiconductor integrated circuit which can prevent a drop in an internal power supply voltage generated by a DCxe2x80x94DC regulator without increasing chip size.
It is a general object of the present invention to provide a semiconductor integrated circuit that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be presented in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor integrated circuit particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages in accordance with the purpose of the invention, the invention provides a semiconductor integrated circuit, including a first power supply line which supplies an external power supply voltage provided from an exterior of the circuit, a second power supply line which supply an internal power supply voltage to an interior circuit, a plurality of NMOS transistors which are situated at different locations, and have drain nodes thereof coupled to the first power supply line and source nodes thereof coupled to the second power supply line, and a regulator circuit which supplies a reference voltage to gate nodes of the plurality of NMOS transistors.
In the semiconductor integrated circuit as described above, a voltage drop may be generated by line resistance along the first power supply line when it extends a long distance. Even if this is the case, the NMOS transistors receiving the reference voltage at their gate nodes generate the internal power supply voltage at their source nodes based on the external power supply voltage. The internal power supply voltage is thus lower than the reference voltage by the threshold voltage of the NMOS transistors. In this manner, the semiconductor integrated circuit of the present invention can maintain a constant internal power supply voltage on the second power supply line at any given locations.
The regulator serves only to apply the reference voltage to the gates of the NMOS transistors, and almost no current flows from the regulator the gate of each NMOS transistor. Even if lines extend a long distance from the regulator to the gates of the NMOS transistors, therefore, almost no voltage drop occurs along the lines.
In the construction as described above, the NMOS transistors can be regarded as transistors for supplying outputs that are generally provided at the outputting part of a DCxe2x80x94DC regulator. One way to look at the present invention is that the regulator has a plurality of power supply points, which are distributed at various locations, and that these power supply points distributed at various locations in the semiconductor integrated circuit can control voltages even when the external power supply voltage is lowered due to line resistance, thereby achieving a predetermined voltage level.
The number of the power supply points may be increased if necessary. It is thus possible to supply a stable power supply voltage to circuits that consume a large amount of electric currents, without resorting to the use of widened power supply lines. When the output transistors of a DCxe2x80x94DC regulator are distributed to various points along the power supply tree, distances between the power supply points and the locations of actual power consumption tend to be short. Further, the provision of more than one power supply point results in a reduced amount of an electric current per power supply point. It is thus possible to suppress a voltage drop to a minimum level when it is caused by line resistance of the power supply lines.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.

Semiconductor integrated circuit with constant internal power supply voltage


A test device includes a virtual machine. The device has a virtual bridge which, when receiving a packet transmitted from the virtual machine to a computer connected via a network, transmits the packet to the computer via a physical interface of the test device. The device has a load generating unit for generating a first packet that provides a communication load and transmitting the generated first packet to the virtual bridge. The device has a return unit for receiving the generated first packet from the virtual bridge, not transmitting the generated first packet to the computer, returning the first packet to the second virtual machine by changing a destination address, and terminating the transmission.

Recently, a cloud environment, which allows a user to use a plurality of computer resources on a network as his or her own computing resources, has been attracting attention. To use a cloud environment, it is necessary to conduct a performance evaluation or performance tuning of a virtual ICT (Information and Communication Technology) system created on the cloud environment (see Japanese Laid-open Patent Publication No. H1-152545).
Conventionally, as shown in FIG. 1, when conducting a performance evaluation or performance tuning of the above system, a local test environment is created instead of a cloud environment. Then, the performance evaluation and the performance tuning are conducted on an ICT system to be tested while adding a primary load to the ICT system from a physical or a virtual load generator (a measuring device or a load generation program). Thereafter, in the conventional method, the ICT system is moved to a cloud environment.
In addition, as shown in FIG. 2, there is a method in which the ICT system is directly created in a cloud environment without creating the ICT system in a local environment. In this method, the performance evaluation and the performance tuning are conducted on the ICT system to be tested while adding a primary load from a virtual load generator (a load generation program on a virtual machine).

Computer-readable medium storing test environment creation program, test environment creation method, and test device


This transformer core and coil assembly comprises (a) a low voltage coil surrounding a coil window and including first and second coil legs on opposite sides of the coil window, (b) a first plurality of side-by-side amorphous-steel core loops surrounding one of the coil legs, and (c) a second plurality of side-by-side amorphous-steel core loops surrounding the other of the coil legs. Extending between said coil legs in a position between two of said side-by-side core loops in the first plurality and between two of said side-by-side loops in the second plurality is a brace of plate form and of electrical insulating material for blocking motion of said coil legs toward each other in response to coil-collapsing forces developed by short-circuit currents through the low voltage coil, thereby protecting the amorphous-steel core loops from damage by these short-circuit produced forces tending to collapse the coil.

In the usual power transformer the coil structure comprises a low voltage coil surrounding a coil window and a high voltage coil surrounding the low voltage coil. The core structure in such a transformer comprises a core loop having a leg extending through the coil window. Should a short circuit occur on the load side of the transformer as a result of an equipment or cable failure, short-circuit currents, typically of high magnitude, will flow through the low voltage coil and produce high mechanical forces tending to collapse the low voltage coil onto the leg of the core loop.
In the traditional transformer having a core of silicon steel, the core leg has been able to resist such collapse of the surrounding low voltage coil without significant impairment. Such silicon steel core has sufficient stiffness and other properties to enable it to resist this mode of collapse without significant damage to the core. But in certain other types of transformers, the core does not have sufficient stiffness to resist such collapse of the surrounding coil without impairment. An example of such a transformer is one having a core of amorphous steel. Although amorphous steel cores have many advantages, they are subject to the disadvantage that they are sensitive to mechanical stresses, and core loss in such cores will significantly increase if they are subjected to the type of short-circuit produced stresses described hereinabove.

Core and coil assembly for an amorphous-steel cored electric transformer


The disclosed technology relates to a process of evaluating any number of different identity providers (IDPs) and their respective set of credentials that are used to authenticate corresponding users to assist with the onboarding of the different IDPs in connection with Wi-Fi identity federations. In particular, the process allows a person's electronic identity and attributes (stored across one or more IDPs) to be determined once using a standard. Once trust has been established for the user, that trust can then be utilized across a number of different systems (e.g., Single-sign on). The same trust determination can be used without the need for the authenticity of the user identity to be re-evaluated with each new access request.

Wi-Fi identity federations (such as EDUroam, AnyRoam, Cisco's OpenRoaming) aim to connect mobile devices to Wi-Fi networks automatically. This automated connection is implemented by creating a link between identity providers (IDPs), service providers, and enterprises so that credentials and access can be shared. In order to have the automated access, the Wi-Fi identity federations need to validate an authenticity of the user in an efficient and low-cost manner while preserving the integrity of the credentials used during the authentication process. With classic mobile-operator federations (e.g., WRX), trust in the identity is implicit and is based on the reputation of the identity provider (IDP). However, in a federation with many lesser-known or non-traditional IDPs, the intrinsic value of the identity is less certain.
Issues arise when the access providers are required to onboard any number of different lesser-known or non-traditional IDPs with different set of credentials which cannot be easily or reliably assessed. It may not be feasible to instruct each access provider how to specifically evaluate credentials for each user for each of the lesser-known or non-traditional IDPs. Therefore, these issues limit what IDPs may typically be accepted by different access points.

Wireless LAN (WLAN) public identity federation trust architecture


Disclosed are methods of detection for output short circuit of a flyback power supply, which detect the current sense signal provided by a current sense resistor serially connected to a power switch of the flyback power supply, and thus quickly identify whether or not the flyback power supply suffers output short circuit.

Output short circuit has become an important item in the safety test of power supplies. Commercial power management integrated circuits (ICs) are all provided with built-in protection mechanism against output short circuit of power supplies. For example, as shown in FIG. 1, in a typical flyback power supply 10, the input alternating-current (AC) voltage Vac is first rectified and filtered by a diode bridge 12 and a capacitor 14 to a direct-current (DC) input voltage Vin to apply to a primary coil Lp of a transformer 18, and a power switch 20 is serially connected to the primary coil Lp and switched by a control signal Gate_BM provided by a power management IC 16 for the transformer 18 to deliver power from the primary coil Lp to a secondary coil Ls to thereby generate an output voltage Vout at a power output. A current sense resistor 22 is connected in series to the power switch 20 to sense the current Ip of the primary coil Lp, and the power management IC 16 determines the duty of the power switch 20 according to the current sense signal Vcs from the current sense resistor 22 and a feedback signal Vcomp derived from the power output Vout. Without any additional pins, the power management IC 16 usually carries out the detection for output short circuit of the flyback power supply 10 by using the feedback pin COMP or the power pin VDD, for triggering the built-in protection mechanism thereof. However, the information provided by the feedback pin COMP contains the message of the feedback open circuit, and the power pin VDD is connected to a capacitor, so that the output information cannot be immediately reflected. Conventionally, regardless of using the feedback pin COMP or the power pin VDD in the detection for output short circuit, it always takes tens to hundreds of milliseconds to determine if an output short circuit occurs. When the flyback power supply 10 suffers output short circuit, it will blowout a large current, which will induce considerable power consumption if the detection for output short circuit needs a long time, and thereby cause the flyback power supply 10 overheated.
Therefore, it is desired a method of quick and immediate detection for output short circuit of a flyback power supply.

Method of detection for output short circuit of a flyback power supply


The invention provides a plasma processing device, wherein the upper electrode and the lower electrode are in the vacuum chamber. The chip is placed in the lower electrode. The first plate is placed between the upper electrode and the lower electrode, and the first plate includes a plurality of first voids. The second plate is placed between the first plate and the lower electrode, and the second plate includes a plurality of second voids. The high frequency power is provided by the upper electrode and the lower electrode in the vacuum chamber, and the plasma is generated between the third plate and the upper electrode. The plasma is filtered by the third void, the first void, and the second void.

1. Field of the Invention
This invention relates to a plasma processing device and plasma processing method thereof, and particularly to a plasma processing device having the upper plate and the lower plate and plasma processing method thereof.
2. Description of the Prior Art
The plasma has already been widely applied to various fields, such as the semiconductor integrated circuit industry. The growth of film from different material and the etching of circuit are achieved by the plasma technology generally. In addition, as for the semiconductor packaging, the plasma is used to wash and change the material surface, in order to achieve special function and effect.
As for an example, the plasma processing device is used for washing the chip. Conventionally, a great amount of water is required for washing the chip in the semiconductor process. The semiconductor process moves towards the miniaturized process gradually. The requirement for the cleanliness of chip itself is raised constantly. Accompany with deeper and longer groove on the chip, the wet etching is hard to be used because of its congenital shortcoming. The dry etching has become better solution at present gradually.
The plasma processing device can be used for dry cleaning. The plasma cleaning principle is similar to the plasma etching. The high frequency power is provided by the electrode to ionize the gas into the plasma. This plasma impacts the chip surface to remove the polluted particles from its surface, and then achieves the goal of cleaning. Similarly, this plasma can also etch or film the chip surface for pretreatment. The above-mentioned plasma has been applied to the process of IC packaging and the liquid crystal module widely at present.
However, the plasma itself has relatively high destruction ability, which is apt to damage the chip or chip surface in cleaning process. Therefore, as for the example of common downstream plasma device and remote plasma device, the improvement way is to increase the distance between the chip and the plasma, in order to reduce the destruction of chip surface by the plasma directly.
The integrated circuit has already been developed to the complicated device gradually. The advancement of chip design needs faster circuit system and more intensive circuit density. Because the speed of circuit and number of executable function will increase with the density of circuit structure, the circuit density will play an important role. The factors affecting the speed of integrated circuit and the design characteristics of circuit density include the resistance and thickness of material. This material is used to form the circuit structure layer on the substrate.
The metal material is applied to design the circuit structure, such as similar structure, such as the metal line, channel, and electrode etc. The metal structure is very important to the function of integrated circuit. The material with low resistance coefficient has good ability to inhibit the permeation of poly-silicon. This makes that the physical property of material with low resistance coefficient still be able to be maintained in substrate process and device use.
In order to reach the highest circuit density, the thickness of metal layer with low resistance coefficient has to be reduced in the circuit structure. But in the process, it shall be careful to avoid damaging those thin layers. The damaged thin layer will cause the poor circuit structure and increase the rejected rate of substrate. The growth of film and etching of circuit can be achieved by the plasma technique generally. The etching process is apt to damage the thin layer. The plasma can be used for strengthening the effect of etching. However, maintaining the steady plasma will cause the increase of ions impacting the substrate surface, and damage the circuit on the substrate.
Therefore, it is necessary to provide a plasma processing device and plasma processing method thereof, in order to improve the damage of chip or wafer by the plasma processing device.


Resource-validation-based event scheduling in a social network. A method identifies, based on activity in a social network, planning of an event. The method determines event parameters of the event, for instance by determining an anticipated number of attendees of the event, and profiling predicted attendees of the event to identify attendee preferences. The method solicits resource validation information from device(s) corresponding to resource(s) at a location for the event. The resource validation information indicates ability of the device(s) to support estimated resource consumption for each of the resource(s), the estimated resource consumption based on the determined event parameters. The method receives the resource validation information, and schedules the event based on the resource validation information.

Users in a social network communicate and collaborate with each other, share photographs and other media, comment on posts, and perform various other activities. One such activity is creating calendar events and planning those events, including the distribution of invitations and the coordination of event details such as the timing and location of the event. Meanwhile, an ever-increasing number of devices around our homes and other spaces that frequently serve as venues for a hosted event are becoming network-connected such that users can interact with and control these devices from a remote location. It is becoming more common to incorporate network-connectivity into conventionally unintelligent devices like dishwashers, water filters, and HVAC systems in order to add intelligence, flexibility, and adaptability to them. Interaction with these smart devices may include periodic maintenance, powering-on, starting, switching-off, and changing parameters, as examples. The potential for integrating event planning with smart device capability has not been exploited.

Resource validation based event scheduling in a social network

INTERNATIONAL BUSINESS MACHINES CORPORATION


This invention is an apparatus and method of real time determination of particle size and optionally chemical composition or both. An aerosol beam generator focuses a beam containing sample particles that passes through a sizing laser beam of approximately constant width to produce light scattering that is detected by a light detection means, allowing generation of electrical pulses that may be used to compute particle velocity. In being formed into a beam, the particles are accelerated to terminal velocities that are functions of their sizes. The duration of time elapsed while a particle passes through the width of the sizing laser beam is a function of its velocity which, in turn, is a function of its size. Chemical composition of the particle is determined by suitable analytical means included in the apparatus, such as mass spectrometry.

A rise in concern over terrorism has increased interest in real time detection and identification of aerosol particles, as radiological, chemical, biological, and explosive materials and their precursors can all be found in aerosolized form.
Recent advances in aerosol mass spectrometry enable real time analysis of aerosol particles in the field, critically important at high value terrorism targets, such as centers of government, airports, and sports venues. Aerosol mass spectrometry requires conditioning the aerosol under analysis, forming a particle beam, and analyzing individual particles by laser desorption/ionization mass spectrometry. Conditioning can include generating the aerosol, if the particles are not already aerosolized, and adjusting the concentration of particles. A particle beam is formed by the supersonic expansion of the gas surrounding the particles through focusing apertures. Particles in a liquid stream may similarly be formed into a beam. Individual particles in the particle beam are then analyzed by mass spectrometry.
Dense particle concentrations can adversely impact the ability of aerosol mass spectrometers to accurately track, resolve, and analyze individual particles. Inaccurate velocity measurement can skew the timing necessary for precise actuation of an ionizing laser. Further, resolving high particle density has historically taken increased complexity and expense.
For instance, the rapid single particle spectrometer (RSMS), disclosed in McKeown et al., "On-Line Single Particle Analysis by Laser Desorption Mass Spectromerty," 63 Anal. Chem. 1906, 2069 (1991), the disclosure of which is incorporated by reference, utilizes a continuous wave laser for detecting the presence of a particle within an aerosol beam. Each particle scatters light while crossing a continuous laser beam. A photomultiplier tube (PMT) measures light scattering intensity to provide an approximate measure of particle size using the particle's reflective index, an inherently inaccurate size measurement. A pulsed laser is aimed adjacent to the continuous laser beam and is actuated upon detection of the particle. A mass spectrum is collected from material desorbed/ionized from the particle.
An aerosol time-of-flight mass spectrometer (ATOFMS), disclosed in U.S. Pat. No. 5,998,215, issued to Prather et al., the disclosure of which is incorporated by reference, sizes aerosol particles based on estimated velocity. Particle traversal time over the distance spanned by two continuous lasers is measured and extrapolated to trigger actuation of a mass spectrometer pulsed laser. Particle velocity yields more accurate particle size determination than does light scattering intensity, but the ability to track individual particles suffers as aerosol concentration increases, thereby limiting analytic throughput. Additionally, utilization of two lasers increases complexity over single laser designs.
An aerosol mass spectrometer system employing an array of six continuous lasers is disclosed in U.S. Pat. No. 7,260,483, issued to Gard et al., the disclosure of which is incorporated by reference. Throughput is improved by using a six-laser array to track the trajectories of individual aerosol particles. Higher performance at increased particle concentrations is achieved, but at the expense of size, cost, and complexity.

System and method for real time determination of size and chemical composition of aerosol particles


Methods and apparatus are disclosed for synthesizing a plurality of biopolymers at predetermined feature locations on a surface of a substrate. One or more of the feature locations comprises degenerate biopolymers. One or more biopolymer subunit precursors are added, in multiple rounds of subunit additions, at each of multiple feature locations on the surface to form the plurality of biopolymers on the surface. For each feature location comprising degenerate biopolymers, the biopolymer subunit precursors comprise a mixture of biopolymer subunit precursors for forming the degenerate biopolymers at the feature location.

Molecular methods using DNA probes, nucleic acid hybridizations and in vitro amplification techniques are promising methods offering advantages to conventional methods used for patient diagnoses, biomedical research or basic biology research. Recent advances in such methods often include the introduction of parallelism, i.e., performing many experiments with the same effort previously used to perform a single experiment. However, the introduction of parallelism often forces changes in the methods used to design such experiments.
Nucleic acid hybridization has been employed for investigating the identity and establishing the presence of nucleic acids. Hybridization is based on complementary base pairing. When complementary single stranded nucleic acids are incubated together, the complementary base sequences pair to form double stranded hybrid molecules. The ability of single stranded deoxyribonucleic acid (ssDNA) or ribonucleic acid (RNA) to form a hydrogen bonded structure with a complementary nucleic acid sequence has been employed as an analytical tool in molecular biology research. The availability of radioactively, chemically and fluorescently labeled nucleoside triphosphates of high specific activity have made it possible to identify, isolate, and characterize various nucleic acid sequences of biological interest. Nucleic acid hybridization has great potential in diagnosing or characterizing diseased or altered tissue function associated with unique nucleic acid sequences or gene expression states. Unique nucleic acid sequences may result from genetic or environmental change in DNA by insertions, deletions, point mutations, or by acquiring foreign DNA or RNA by means of infection by bacteria, molds, fungi, and viruses. Altered gene expression states may arise from neoplastic transformation, viral infection, environmental insult or drug treatment. It is desirable to perform such experiments in parallel; earlier methods for introducing modest parallelism include Southern blots, Northern blots and slot blots.
Such blot techniques are examples of methods for detecting nucleic acids that employ nucleic acid probes that have sequences complementary to sequences in the target nucleic acid. A nucleic acid probe may be, or may be capable of being, labeled with a reporter group or may be, or may be capable of becoming, bound to a support. Detection of signal depends upon the nature of the label or reporter group. Usually, the probe is comprised of natural nucleotides such as ribonucleotides and deoxyribonucleotides and their derivatives although unnatural nucleotide mimetics such as peptide nucleic acids and oligomeric nucleoside phosphonates are also used. Commonly, binding of the probes to the target is detected by means of a label incorporated into the probe. Alternatively, the probe may be unlabeled and the target nucleic acid labeled. Binding can be detected by separating the bound probe or target from the free probe or target and detecting the label. In one approach, a sandwich is formed comprised of one probe, which may be labeled, the target and a probe that is or can become bound to a surface. Alternatively, binding can be detected by a change in the signal-producing properties of the label upon binding, such as a change in the emission efficiency of a fluorescent or chemiluminescent label. This permits detection to be carried out without a separation step. Finally, binding can be detected by labeling the target, allowing the target to hybridize to a surface-bound probe, washing away the unbound target and detecting the labeled target that remains.
Direct detection of labeled target hybridized to surface-bound probes is particularly advantageous if the surface contains a mosaic of different probes that are individually localized to discrete, known areas of the surface. Such ordered arrays containing a large number of oligonucleotide probes have been developed as tools for high throughput analyses of genotype and gene expression. Oligonucleotides synthesized on a solid support recognize uniquely complementary nucleic acids by hybridization, and arrays can be designed to define specific target sequences, analyze gene expression patterns or identify specific allelic variations. One difficulty in the design of oligonucleotide arrays is that oligonucleotides targeted to different regions of the same gene can show large differences in hybridization efficiency, presumably due to the interplay between the secondary structures of the oligonucleotides and their targets and the stability of the final probe/target hybridization product.
Recently, a method or algorithm was described for predicting oligonucleotides specific for a target nucleic acid where the oligonucleotides exhibit a high potential for hybridization (Shannon, et al., Method for evaluating oligonucleotide probe sequences, U.S. Pat. No. 6,251,588 (2001)). The algorithm uses parameters of the oligonucleotide and the oligonucleotide:target nucleotide sequence duplex, which can be readily predicted from the primary sequences of the target polynucleotide and candidate oligonucleotides. In the method, oligonucleotides are filtered based on one or more of these parameters, then further filtered based on the sizes of clusters of oligonucleotides. The basic steps involved in the disclosed method involve parsing a sequence that is complementary to a target nucleotide sequence into a set of overlapping oligonucleotide sequences, calculating one or more parameters for each of the oligonucleotide sequences with respect to its hybridization to the target nucleotide sequence, filtering the oligonucleotide sequences based on the values for each parameter, filtering the oligonucleotide sequences based on the length of contiguous sequence elements and ranking the contiguous sequence elements based on their length. Certain oligonucleotides within the longest contiguous sequence elements generally showed the highest hybridization efficiencies.
In many assays there may be one or more target or non-target nucleic acids present that have nucleotide sequences that are closely related to one another differing by only a few, e.g., one to five nucleotides, at one or more sites within the nucleotide sequence. One such instance of related sequences is a family of genes that are phylogenetically related and that share stretches of conserved and/or hypervariable domains.
Recently, methods, reagents and kits were disclosed for selecting target-specific oligonucleotide probes, which may be used in analyzing a target nucleic acid sequence (see, for example, U.S. Pat. No. 6,461,816 B1 and Agilent Technologies Inc. (Palo Alto, Calif.) brochure dated Nov. 1, 2001, entitled "Development of an in situ synthesized oligonucleotide microarray for gene expression monitoring of the budding yeast Saccharomyces cerevisiae," by Stephanie Fulmer-Smentek, et al.). In the method a cross-hybridization oligonucleotide probe is identified based on a candidate target-specific oligonucleotide probe for the target nucleic acid sequence. The cross-hybridization oligonucleotide probe measures the extent of occurrence of a cross-hybridization event having a predetermined probability. Cross-hybridization results are determined employing the cross-hybridization oligonucleotide probe and the target-specific oligonucleotide probe. The target-specific oligonucleotide probe is selected or rejected for the set based on the cross-hybridization results. The process for identifying and selecting the minimum number of cross-hybridization oligonucleotide probes may be carried out using different approaches such as mismatch probe design by homology, mismatch probes that incorporate base combinations, mismatch probes that delete bases, mismatch probes that insert bases, and combinations thereof.
There remains, however, a need to prepare arrays that efficiently and effectively detect and estimate subgroups of gene families by the relative abundance of nucleic acid sequences among pools of phylogenetically related sequences that share stretches of conserved and/or hypervariable domains. Ideally, the methods should be able to employ current manufacturing techniques for the preparation of arrays with some or no modifications except to the extent of carrying out the present methods.

Methods and apparatus for preparing arrays comprising features having degenerate biopolymers


The present disclosure provides a power management device, including an initial voltage input terminal, a power management circuit, and a plurality of gamma correction circuits. The initial voltage input terminal is configured to provide an initial voltage; the power management circuit includes at least one follower amplifier sub-circuit, each follower amplifier sub-circuit is configured to output a corresponding target operating voltage according to the initial voltage, a reference voltage, and a target operating voltage setting parameter; and each gamma correction circuit is configured to output a corresponding gamma correction voltage according to the initial voltage, the reference voltage, and a corresponding gamma parameter. The present disclosure further provides a display device.

A power management device is an important component of a display device, and is generally configured to convert a voltage signal output by a power supply into a signal required for driving a display panel to display. At present, the power management device is redundant in structure and thus cannot meet users' demand for light electronic equipment.

Power management device and display device

BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.

BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.


A reference voltage generation circuit for a plurality of reference generation voltages and a pipe line analog-to-digital converter (ADC) using the same are provided. The reference voltage generation circuit including a charging capacitor for stabilizing the reference voltages charges the charging capacitor prior to the generation of the reference voltages, thus decreasing the time for the pipe line ADC to operate stably.

1. Field of the Invention
The present invention is related to a reference voltage generation circuit for generating a reference voltage and an ADC (Analog-to-Digital Converter) for converting an analog signal to a digital signal on the basis of the reference voltage, and in particular, relates to a reference voltage generation circuit for generating a plurality of reference voltages and a pipe line ADC using the same.
2. Description of the Related Art
A conventional pipe line ADC has a reference voltage generation circuit which generates a plurality of reference voltages to internal circuits. A conventional phase-locked loop circuit (hereinafter "PLL circuit") also has a reference voltage generation circuit. A reference voltage generation circuit, which generates a plurality of reference voltages to internal circuits having a large circuit dimension, includes an external capacitor with a large capacitance so as to stabilize the reference voltages and decrease electric power consumption. In the reference voltage generation circuit including the external capacitor with a large capacitance, it takes a long time to electrically charge the external capacitor, thus influencing a start-up duration of a pipe line ADC using the reference voltage generation circuit. Various improvements to solve the problem have been proposed. Technologies for overcoming the problem are disclosed in, for example, Japanese Patent Application Laid-Open Publication No. H09-55656 (document D1), Japanese Patent Application Laid-Open Publication No. 2001-168713 (document D2), and Japanese Patent Application Laid-Open Publication No. 2001-285069 (Document D3).
In the document D1, a PLL circuit which decreases a start-up duration at a power down mode is disclosed.
In the document D2, a pipe line ADC is described. In the document D3, an electric potential controlling circuit, which suppresses electric current consumption and decreases a start-up duration, is described.
The conventional pipe line ADC disclosed in the document D2 will now be described with reference to FIGS. 2 to 4 of the accompanying drawings. FIG. 1 is a block diagram showing the conventional pipe line ADC described in the document D2.
As shown in FIG. 1, the conventional pipe line ADC has an analog-to-digital (A/D) conversion part 1, an error correction circuit 16, a timing signal generation circuit 17, and a reference voltage generation circuit 20. The conventional pipe line ADC also has an input terminal VIN, a clock input terminal CLKX, and output terminals D0 to D9. The conventional pipe line ADC inputs continuous analog signals from the input terminal VIN thereof, converts sequentially continuous analog signals to digital signals in response to a clock signal from the clock input terminal CLKX, and then sequentially outputs the digital signals to the output terminals D0 to D9 thereof. The A/D conversion part 1 has pipe line ADC's of nine stages which sequentially convert continuous analog input signals provided from the input terminal VIN to digital signals. The error correction circuit 16, which receives the sequential digital signals generated by the A/D conversion part 1, corrects the digital signals and provides the corrected digital signals (for example, digital signals of ten bits, d0 to d9) to the output terminals D0 to D9, respectively. The timing signal generation circuit 17 generates timing signals trig to the A/D conversion part 1 in response to a clock signal clkx given from the clock input terminal CLKX. The Reference voltage generation circuit 20 outputs reference voltages (refp, vp1, refpq, cm, refnq, vn1, refn) from corresponding reference voltage output terminals (REFP, VP1, REFPQ, CM, REFNQ, REFNQ, VN1, REFN) to the A/D conversion part 1. Internal circuits of the A/D conversion part 1 operate on the basis of the reference voltages (refp, vp1, refpq, cm, refnq, vn1, refn).
The AD conversion part 1 is configured by a sampling and holding circuit 2 and nine pipe line stages (Stg1 to Stg9) 10-1 to 10-9. The nine pipe line stages (Stg1-Stg9) 10-1 to 10-9 are cascade-connected to the sampling and holding circuit 2. The sampling and holding circuit 2 operates on the basis of the reference voltage cm. The sampling and holding circuit 2 samples analog signals given to the input terminal IN in response to the timing signal trig and holds the analog signal for a given duration. The first to eight pipe line stages 10-1 to 10-8, which are cascade-connected to an output terminal of the sampling and holding circuit 2, sequentially convert the output analog signals generated by the sampling and holding circuit 2 into digital signals of 1.5 bits in response to the timing signals trig and the reference voltages refpq, refnq, refp, and refn. The first to eight pipe line stages 10-1 to 10-8 sequentially supply the digital signals of 1.5 bits to the error correction circuit 16. The ninth pipe line stage 10-9 converts an analog signal generated by the eighth pipe line stage 10-8 to a digital signal of 2 bits and supplies the digital signal of 2 bits to the error correction circuit 16 in response to reference voltage vp1, refpq, refnq, vn1, and a timing signal trig.
FIG. 2A is a block diagram showing first to eighth pipe line stages 10-1 to 10-8 (Stg1-Stg8) of FIG. 1, and FIG. 2B is a block diagram showing the ninth pipe line stage 10-9 (Stg9) of FIG. 1.
As shown in FIG. 2A, each of the first to eighth pipe line stages has a sub-ADC 11, a sub-DAC (sub-Digital-to-Analog Converter) 12, and an amplifier 14. Each of the first to eighth pipe line stages also has an input terminal to which an input analog signal vin is supplies and an output terminal from which an output analog signal vout is provided. The sub-ADC 11 compares the input analog signal vin to the reference voltages refpq, refnq, and encodes a resultant comparative signal so as to generate a digital signal of 1.5 bits. The sub-DAC 12 compares the digital signal of 1.5 bits generated by the sub-ADC 11 to the referential voltages refp, refn, and then converts a resultant comparative signal to an analog signal. The subtraction circuit 13 subtracts the analog signal generated by the sub-DAC 12 from the input analog signal vin. The amplifier 14 amplifies the analog signal generated by the subtraction circuit 13 by a factor of two times and then generates the amplified analog signal as an output analog signal vout.
As shown in FIG. 2B, the ninth pipe line stage 10-9 has an sub-ADC 15. The sub-ADC 15 compares an input analog signal vin (the output analog signal vout generated by the eighth pipe line stage 10-8) to the referential voltages vp1, refpq, refnq, and vn1, and encodes a resultant comparative signal so as to generate a digital signal of 2 bits.
FIG. 3 is a block diagram showing the sub-ADC 11 of FIG. 2A. The sub-ADC 11 has comparators 11a, 11b, and an encoder 11c. The comparator 11a and 11b compare an input analog signal vin and the reference voltages refpq, refnq, respectively, and generates resultant comparative signals, respectively. By encoding the respective comparative resultant signals generated by the comparators 11a and 11b, the encoder 11c generates a digital signal.
Operations of the pipe line ADC shown in FIGS. 1 to 3 will now be described. An analog signal given to an input terminal VIN of FIG. 1 is supplied to the sampling and holding circuit 2. The sampling and holding circuit 2 samples and holds the analog signal. And then the analog signal is given to the first pipe line stage 10-1 as a input analog signal vin. In the first pipeline stage 10-1 shown in FIGS. 2A and 3, the comparators 11a and 11b compare the input analog signal vin generated by the sampling and holding circuit 2 to the reference voltages refpq, refnq, respectively. The encoder 11c encodes resultant comparative signals to a digital signal of 1.5 bits. Therefore, the input analog signal vin is converted into the digital signal of 1.5 bits by the first pipe line stage 10-1. The digital signal of 1.5 bits is supplies to the error correcting circuit 16 and the sub-DAC 12.
The sub-DAC 12 converts the digital signal of 1.5 bits from the sub-ADC 11 to an analog signal and supplies the analog signal to the subtraction circuit 13. The subtraction circuit 13 subtracts the analog signal generated by sub-DAC12 from the input analog signal vin and supplied the subtracted analog signal to the amplifier 14. The amplifier 14 amplifies the subtracted analog signal by a factor of two times and supplies the amplified analog signal to the second pipe line stage 10-2.
The second to eighth pipe line stages 10-2 to 10-8 operates in the same way as the first pipe line stage 10-1. An amplified analog signal generated by the eighth pipe line stage is given to the ninth pipe line stage 10-9 as an input analog signal vin. The sub-ADC 15 of the ninth pipe line stage 10-9 shown in FIG. 2B compares an input analog signal vin, which corresponds to the amplified analog signal generated by the eighth pipe line stage, to the reference voltages vp1, refpq, refnq, and vn1 and encodes a resultant comparative signal so as to generate a digital signal of 2 bits to the error correction circuit 16.
The correction circuit 16 sequentially corrects errors in the digital signals respectively generated by the first to ninth pipe line stages 10-1 to 10-9, and supplies the corrected digital signals d0 to d9, each corresponding to the input analog signals from the input terminal VIN, to the output terminals D0 to D9, respectively.
Subsequently, the reference voltage generation circuit 20 shown in FIG. 1 will now be described with reference to FIG. 4. FIG. 4 is a circuit diagram showing the reference voltage generation circuit 20 of FIG. 1. As shown in FIG. 4, the reference voltage generation circuit 20 has an electric current source 21 and nine resistors 22-1 to 22-9, which are arranged in a LSI chip. The electric current source 21 flows a substantially constant electric current. The electric current source 21 has two P channel type MOS transistors (PMOSs) 21a and 21b whose gates are controlled by bias voltages vpbias1 and vpbias2, respectively. The PMOSs 21a and 21b are connected in series across a power terminal VDD and a reference voltage output terminal REFP.
The nine resistors 22-1 to 22-9 are connected in series across the reference voltage output terminal REFP and an earth terminal GND. A reference voltage output terminal VP1 is connected across the resistors 22-1 and 22-2. A reference voltage output terminal REFPQ is connected across the resistors 22-3 and 22-4. A reference voltage output terminal CM is connected across the resistors 22-4 and 22-5. A reference voltage output terminal REFNQ is connected across the resistors 22-5 and 22-6. A reference voltage output terminal VN1 is connected across the resistors 22-7 and 22-8. A reference voltage output terminal REFN is connected across the resistors 22-8 and 22-9.
The reference voltage output terminals REFP and REFN, both of which are provided in the LSI chip, are respectively connected to pads REFP_PAD and REFN_PAD outside the LSI chip. Across the pads REFP_PAD and REFN_PAD, an external capacitor 23 is connected. An input range of the input analog signal of the conventional pipe line ADC is dependent upon a difference between the reference voltage refp on the terminal REFP and the reference voltage refn on the terminal REFN. A reference voltage cm on the terminal CM is utilized as a common mode voltage of the conventional pipe line ADC. Reference voltages vp1, vn1, refpq, and refnq on corresponding reference voltage output terminals VP1, VN1, REFPQ, and REFNQ are utilized as the reference voltages supplied to the comparator 11a and 11b of the conventional ADC.
The reference voltage generation circuit 20 of the conventional pipe line ADC is provided with the external capacitor 23 outside of the LSI chip. The conventional pipe line ADC is turned on at the same time of the generations of the reference voltages and the charging of the external capacitor 23. Thus, it takes much time to increase the difference between the reference voltage refp on the terminal REFP and the reference voltage refn on the terminal REFN to a predetermined level. The difference between the reference voltages is dependent upon the input range of the input analog signal of the ADC. Therefore, there was a difficulty of increasing the time necessary for stabilizing the A/D converting operation after the conventional pipe line ADC is turned on or after the power down mode is released.
To solve the problem, it is considered that technologies disclosed in documents 1 and 3 are applied to the reference voltage generation circuit 20 disclosed in document D2. Since the reference voltage generation circuit 20 is completely different from the circuit structures disclosed in the documents D1 and D3, the technologies disclosed in the documents 1 and 3 can not be simply applied to the conventional reference voltage generation circuit 20, so that the problem has not been easily solved by providing a reference voltage generation circuit having a relatively simple circuit structure.

Reference voltage generation circuit and pipe line analog-to-digital converter using the same


A system determines to use at least two independent renderers to render at least two output streams that are to be synchronized. The independent renderers are provided with a shared synchronization object when instructed to render the respective output stream. A time when all of the independent renderers can render a respective first buffer of the respective output stream is determined from the shared synchronization object. Rendering of the output streams utilizing the independent renderers is begun at the determined time. In this way, rendering of the output streams may be synchronized.

Electronic devices may render streams of audio to drive components such as speakers, actuators, and so on. Typically, such electronic devices may render multiple streams of audio within a particular period of time. In some cases, the rendering of such multiple streams of audio may need to be synchronized with another type of output, such as a haptic or visual output.
For example, a haptic output device may include both a tactile and an audio component as part of a haptic output. The components that produce the tactile and audio components may be driven by data that is delivered ("streamed") from an internal processing unit. In such an example, many electronic devices simply output the tactile and audio outputs as they are received from the processing unit, according to a time stamp in the data streams of the tactile and audio data, or otherwise approximate rendering the two output types are roughly the same time.
However, these approaches do not necessarily yield true synchronized output. For example, the latency between the processing unit and one of the rendering components may be different than the latency between the processing unit and another of the rendering components. Likewise, data for one type of output may be ready or transmitted before the other type of data. Further, it may simply take more time for one of the rendering components to prepare and output its data.
Additionally, some electronic devices that utilize independent renderers to render each of the multiple output streams may not synchronize the renderings. To the contrary, such an electronic device may instruct independent renderers to render the various multiple streams and accept any lack of synchronization that occurs. Other electronic devices may combine rendering of the multiple streams into a single, unitary process. However, in such a case the rendering of the various multiple streams is not performed independently.
In the above cases, there may be a perceptible dissonance between the various types of output. They may appear to be out of sync, thereby losing their effectiveness and creating an unpleasant sensation in a user.
Accordingly, an improved apparatus and method for synchronizing output rendering may be useful.

Synchronization of independent output streams


The invention concerns a starter for a line start electric motor having at least one main winding (4) and at least one start winding (12) and which start winding is connected in series with a run capacitor (14) with which a start capacitor (17) and a PTC-thermistor (19) are connected in parallel. In order to make a simply constructed starter for a line start electric motor the start capacitor (17) and the PTC-thermistor (19) are connected in series with a switch mechanism (20). The series connected circuit made up of the start capacitor (17), the PTC-thermistor (19) and the switch mechanism (20) is connected in parallel with the run capacitor (14).

From US patent application US 2002/0190595 A1, a line start electric motor is known wherein a start capacitor and a PTC-thermistor are connected in parallel with a run capacitor and in series with a start winding. The PTC-thermistor serves to separate the voltage source from the start capacitor when the line start electric motor reaches a given rotational speed. In the patent application it is mentioned that the PTC-thermistor can be replaced by a centrifugal force switch. Such a centrifugal force switch requires a relatively high construction expense. Moreover, the movable parts of the centrifugal force switch must be lubricated in operation in order to assure a disturbance-free continuous operation. The lubricating means can be injured by the electric contacts, for example, as a result of being burned by electric arcs.
From U.S. Pat. No. 6,356,047 B1, a starter for an electric motor is known in which a PTC-thermistor and a relay are connected in parallel with a run capacitor. When the motor is started, the relay closes and the PTC-thermistor is subjected to current flowing through it. During the initial motor rotations, the PTC-thermistor heats itself so that the current flow is reduced. When the motor has reached the desired rotational speed, the relay is opened again. The circuitry known from the American patent is not suited for a line start electric motor, since no start capacitor is provided.


A switching device for medium, high, or extremely high voltage, wherein at least one voltaged component of the switching device is enclosed in an enclosure and the enclosure is filled with a filling medium. The filling medium includes at least one compound from the group of fluorinated ketones, or consists of the same.

All the components that are voltaged in at least one operating state of the switching device can be understood to be voltaged components. However, they need not actually be voltaged in every operating state of the switching device. Depending upon its setting, for example, a switch is not always voltaged, even though by means of a switching process it can be translated into an operating state in which it is voltaged.
Depending upon the definitions used the demarcations of the regions of medium, high or extremely high voltage can vary. According to one prevalent definition, the medium voltage region extends from 1 kV to 52 kV and the high-voltage region from 52 kV to 110 kV. According to another definition the high-voltage region starts earlier at 50 kV. Voltages greater than 110 kV are designated as extremely high voltages. Accordingly a switching device for medium, high or extremely high voltage can be understood to be a switching device for voltages from 1 kV upwards.
Switchgear and switching equipment for medium, high or extremely high-voltage are also included amongst these switching devices. A multiplicity of switching devices of this type are of known prior art.
An exemplary item of switching equipment for medium, high or extremely high voltage is a switch for voltages such as are also used, for example, in switchgear for medium, high or extremely high voltage. Switchgear of this type allow, by means of appropriate switching the formation of connections between different conductors, and thus, for example, the supply of energy to various consumers, or the reaction to failures of particular conducting paths, in that these are bridged by the selection of alternative energy supply paths.
Switching devices for medium, high or extremely high voltage must often satisfy high requirements with respect to their reliability and human safety. These include, for example, in switches for medium, high or extremely high-voltage, such as power switches, power disconnectors, load switches, circuit breakers, load disconnectors, etc., the requirement that arcs occurring between the contacts during the switching processes can be rapidly extinguished, or that their occurrence can be prevented. To satisfy these requirements various solutions have been proposed in the past. Thus switches for medium, high or extremely high voltages can be assigned extinguishing coils that have the task of extinguishing switching arcs. Likewise voltaged components of switching devices for medium, high or extremely high voltage can be enclosed in an enclosure that is filled with a filling medium. As an example it should be stated here that the contacts of switches for medium, high or extremely high voltage are often enclosed in an enclosure that is filled with a filling medium. The filling medium can have the property of rapidly extinguishing any arcs that occur, i.e. it can act as an arc extinguishing medium.
Voltaged components of switchgear for medium, high or extremely high voltage, for example, busbars, can be enclosed in an enclosure that can, for example, be designed as a separate chamber or bulkhead compartment in the housing of the switchgear. A suitable filling medium with which this enclosure is filled can act as an electrical insulation medium and can insulate voltaged components from other components of the switchgear. Equally it can act as an arc extinguishing medium for any fault arcs that may occur within the switchgear. The personal safety of operators of the switchgear can be increased both by means of an electrical insulation action of a filling medium and also by means of a fault arc extinguishing action of a filling medium. If fault arcs are extinguished promptly after they appear down times and maintenance requirements can be reduced. Instead of filling with a filling medium a vacuum is also often generated in the enclosure of switching devices for medium, high or extremely high voltage.
Air, oil and a "solid gas", i.e. a material that translates into a gaseous state only when the arc develops can be named as filling media, amongst others. DE 598 450 A discloses a circuit breaker. The breaker contacts of the circuit breaker are accommodated in containers filled with oil. From DE 641 963 A a metal-clad electrical switchgear is of known art, in which components such as a power switch and a transformer are accommodated in a vessel filled with oil as an insulation fluid.
However, sulphur hexafluoride (SF6) is also often used as a filling medium that is suitable both as an arc extinguishing medium and also as an electrical insulation medium. In comparison to air SF6 offers the advantage of a higher breakdown resistance by a factor of approximately 2.5 at standard pressure. This makes possible small insulation separation distances, and thus allows the design of more compact switching devices for medium, high or extremely high-voltage. From DE 195 19 301 A1 a breaker for a metal-enclosed gas-insulated high-voltage switchgear is of known art. Here a contact pin and an opposing contact are arranged in a housing that is filled with SF6 as an insulation gas. DE 32 15 234 C2 describes enclosed medium voltage switchgear, in which switching blades are arranged in a housing filled with an insulation gas; the blades can be brought into three switching positions.
From the point of view of environmental protection, and in particular climate protection, however, SF6 is beset with many disadvantages. Its global warming potential (GWP), also known as its CO2-equivalent, is 22,800. Thus 1 kg of SF6 over a time period of 100 years is considered to be just as damaging as 22,800 kg of CO2. Moreover its atmospheric lifespan is extremely high at 3200 years. Thus in Europe, for example, the handling and use of SF6 is subject to stringent regulations. Stocks of SF6 and its consumption must be monitored, for example.

Fluorinated ketones as high-voltage insulating medium


A system and method are described for decreasing the synthesis time required for realizing digital circuit net lists using library logic elements. The system consists of a logic processor working in concert with a cell library register, a hierarchical cell array memory, and a match register, for the purpose of hierarchically ordering, matching and eliminating equivalencies in the canonical forms of library cells. The method includes the reduction of all library elements to their canonical forms and the hierarchical ordering of the these canonicals based on the number of nodes contained in each element. Once ordered, the canonicals are mapped by logic elements having fewer nodes, beginning with the simplest of the canonical forms. Redundantly mapped logical elements are eliminated and the resulting reduced set is stored for subsequent use.

1. Field of the Invention
This invention relates to the design of digital logic systems and more particularly to the use of a hierarchically ordered library of canonical digital logic elements to facilitate the design of optimized digital logic systems.
2. Description of the Background Art
In the design of digital logic systems, the reduction of the logic equations to a hardware implementation is referred to as logic synthesis. This synthesis process consists of two discrete steps. The first step involves the optimization of the logic equations into a minimum number of realizable steps. Most digital equations expressed in boolean (binary logic) form are capable of multiple equivalent representations. This optimization process requires that the designer choose among the various forms of the boolean equation, that expression which may be implemented using the fewest gate delays and the least amount of geometrical area or component floor space.
The second step of the logic synthesis process consists of identifying digital components available to the designer which may be used to realize the optimized boolean equation. Each designer has a finite list of components available for implementing the target equation. These components are often stored as design cells in a computer aided design environment. The mapping process involves the substitution by the designer of cell components for terms in the optimized boolean equation. Complicating the efforts of the designer is the usual availability of a variety of cell design implementations from which the designer may choose to implement any given cell function. As the number of available cells in a cell library increases, the various possible implementations of an optimized boolean equation increases exponentially. As in the optimization step above, the designer must choose among the various cell realizations for the implementation which produces the fastest result while using the least amount of geometrical area to build.
A basic tenet of Boolean arithmetic is that any boolean equation may be realized using one or more appropriate combinations of inverters and two input NAND gates (NAND2). It should be noted that inverters and two input NOR (NOR2) gates work equally well, however, NAND2 gates are used throughout this specification to simplify the description. To implement an AND function, for instance, a NAND function is followed by an inverter. This construction of an AND gate using an inverter and a NAND2 gate is referred to as the "canonical form" of the AND function. Library cells consist of components designed and represented in their canonical form.
In order to implement the optimized Boolean function using canonical form cell components, the optimized Boolean function must first be decomposed into a canonical form net list. A typical canonical form net list 14 for a simple boolean equation is shown in FIG. 1. Once the net list 14 is decomposed into a canonical form, the various canonical logic subcomponents available in the cell library are compared with each section of the canonical net list to determine which of the cells will "map" or match with sections of the net list. This mapping of the cell library to the net list is generally very time consuming, particularly since most cell functions have multiple equivalent canonical representations. What is needed is a system for reducing the number of combinations of library cells and net list sections which must be checked.

Hierarchical ordering of logical elements in the canonical mapping of net lists


An emotion estimator of a dialogue control device estimates a dialogue partner's emotion based on the dialogue partner's facial expression or voice prosody. A dialogue controller controls the dialogue with the dialogue partner using a topic selected based on whether the emotion estimated by the emotion estimator is good or bad. Specifically, the dialogue controller controls the dialogue with the dialogue partner based on a topic map created by a topic mapper and including a topic that the dialogue partner likes.

Recently, a technology for realizing an interactive dialogue between a human and a machine has become widespread. For having a dialogue between a human and a machine with communication, artificial intelligence (AI) and voice recognition technologies are required, but with a context analysis and a response alone, communication cannot be established. A technology for estimating a human's emotion and the like is required.
For example, Patent Literature 1, Unexamined Japanese Patent Application Kokai Publication No. 2006-178063 discloses a technology for estimating emotion of a user who is a dialogue partner and utilizing the estimated emotion for a dialogue. In Patent Literature 1, utterance contents are converted to text every time a user makes an utterance and the user's emotion is estimated by whether a word showing good or bad emotion is included in the text. A device replies depending on the estimated emotion (for example, if the estimated emotion is negative, the device utters "Are you OK?" or the like).
Patent Literature 2, Unexamined Japanese Patent Application Kokai Publication No. 2014-219594 discloses a technology of recognizing emotion of a user from user's voice and selecting a conversation algorithm that corresponds to the emotion of the user.

Dialogue control device, dialogue control method and non-transitory computer-readable information recording medium


At the time of spinning a tip reduced portion 3, an angle of inclination of the outer periphery of the tip reduced portion 3 with respect to an axis of a tube stock 2 is increased on a center side of the tube stock 2 and reduced on an end edge side thereof. By this, a generating line of an outer peripheral surface of the tip reduced portion 3 is made into a form like a center recessed curved surface.

This invention relates to a method for forming an end portion of a tube used for a muffler of a vehicle, etc. and more particularly to a method for forming an end portion of a flattened tube which has a short axis direction and a long axis direction in section, the flattened tube having such a configuration in section as elliptic, rectangular, or the like.
In recent vehicles, a tube having an elliptic configuration in section is often used as a tube constituting a muffler. The reason is that the tube having an elliptic configuration in section has a long axis direction and a short axis direction and therefore, it can exhibit such an advantage in respect of layout as being able to reduce the width in the up and down direction compared with a sectional area thereof by placing the tube such that the short axis direction is oriented to the up and down direction.
Incidentally, an exhaust tube connected to the muffler has a circular configuration in section and in addition, it has a smaller diameter than the elliptic tube constituting the muffler. For this reason, as shown in FIGS. 16 through 18, a taper-like tip reduced portion a and a connecting portion b having a circular configuration in section and having an even diameter are formed on opposite end portions of an elliptic tube A constituting the muffler by spinning. The connecting portion b is fittingly connected to an exhaust tube (not shown).
When the tip reduced portion a is formed on the end portion of the elliptic tube A by spinning, a projection c projecting in a short axis direction is, as shown in FIG. 17, formed on an intersection part between the outer periphery of the elliptic tube A in the short axis direction and the outer periphery of the tip reduced portion a on the enlarged diameter side end portion. This projection c brings about such a problem that it interferes with other members of the vehicle. In order to avoid this problem, it is generally practiced that a post machining is executed in order to depress the projection c so as to be roughly flattened after the process for machining the tip reduced portion a. However, in the case where a projecting amount d1 of the projection c is overly large, the area of the intersection part where the projection c is formed is depressed or a waving phenomenon occurs in which wrinkles are formed on the tip reduced portion a, after the post machining. Therefore, it is demanded that the projecting amount d1 is diminished as much as possible.
The present invention has been made in order meet with the above-mentioned demand. According to the present invention, there is provided in a method for forming, on an end portion of a tube stock, a tip reduced portion having a circular configuration in section which is gradually reduced in diameter from a center side of the tube stock towards an end edge side thereof by relatively rotating a forming tool about an axis of the tube stock and moving the forming roll towards the axis of the tube stock as the forming roll is moved from the center side of the tube stock towards the end edge side thereof while pressing the forming tool against an outer periphery of the end portion of the tube stock which outer periphery has a sectional configuration having different lengths in two mutually orthogonal directions, a method for forming a tube end comprising the step for forming the tip reduced portion of the tube stock such that an angle of inclination of an outer periphery of the tip reduced portion with respect to an axis of the tube stock is gradually reduced from the center side of the tube stock towards the end edge side thereof so that a generating line of the outer periphery of the tip reduced portion becomes a center recessed curve.
It is accepted that the forming process by the forming tool is repeated plural times so that the tip reduced portion is gradually finished from the center side of the tube stock in every forming process or that through repetition of the forming process plural times using the forming tool, the end portion of the tube stock is reduced in diameter in every forming process and the entirety of the tip reduced portion is formed in a final forming process.


Disclosed herein is a method to enhance detection and quantification of features in the wafer edge/wafer roll off regions. Modifications and improvements have been made to earlier methods which enable improved accuracy and increased scope of feature detection.

As integrated circuits become faster and denser, requirements for control of topographical features such as planarity, shape, and thickness become increasingly stringent. The necessity for verifying that a given wafer is sufficiently planar and within specifications, i.e. in qualifying and selecting wafers even before processing begins or during processing, is becoming ever greater. A critical component in the characterization of wafers is the wafer topography, sometimes termed substrate geometry. In particular it is necessary to characterize the surface profile in order to determine whether there is perturbation of the profile to the extent that would prevent the wafer from being processed into a finished product. This characterization is particularly critical in the edge regions of semiconductor wafers, where there is generally a slope roll off. In these regions traditional thickness measurements are unlikely to effectively and accurately reveal and characterize such perturbations. Present techniques utilize wafer front & back surface and thickness measurements, which are processed to provide a curvature profile by taking the second derivative of the data curve.

Systems and methods for wafer edge feature detection and quantification


An iontophoresis system comprises a power supply apparatus having a chargeable battery, a positive output terminal, a negative output terminal and a positive charge terminal, and a preparation having input terminals connected to output terminals of the power supply apparatus. The negative output terminal of the power supply apparatus also serves as a negative charge terminal for charging the battery. During charging, the preparation is removed, and terminals of a charger are connected to terminals of the power supply apparatus, respectively. The power supply apparatus comprises a power supply monitoring portion which gives a warning when a battery voltage becomes a predetermined value or lower and a control portion for controlling a power supply state from the output terminal.

The present invention relates to an iontophoresis system applied percutaneously or trans-mucosally, and in particular to a portable iontophoresis system.
Iontophoresis is a percutaneous absorption-promoting system which employs electricity for external stimulation. Its principle is such that skin barrier permeability of drug molecules is promoted by movements of positively-charged molecules from an anode to a cathode and those of negatively-charged molecules from the cathode to the anode in an electric field mainly produced between the anode and the cathode by power supply [refer to Journal of Controlled Release, Vol. 18, pages 213 to 220, 1992; Advanced Drug Delivery Review, Vol. 9, page 119, 1992; and Pharmaceutical Research, Vol. 3, pages 318 to 326, 1986].
Thus, in iontophoresis, an anode and a cathode are provided in pair and a current is generated between the anode and cathode, thereby moving a drug. In recent years, a constant current unit is employed so that a current can be maintained at a predetermined value irrespective of an impedance difference due to individual difference. This constant current unit can keep a drug delivery rate constant irrespectively of impedance because the drug delivery rate correlates with a current quantity. A unit of such type is disclosed in Japanese Patent Laid-Open Publication No. 5-245214, for example. In addition, a unit for controlling a drug supply rate with a program as required is disclosed in Japanese Patent Laid-Open Publication No. 7-124265, for example.
In the meantime, in order to achieve a small iontophoresis system suitable to be portable, in particular, it is required to minimize the number of circuit parts of a power supply apparatus and miniaturize the unit. Among them, in particular, it is desired to reduce a battery incorporated in the power supply apparatus in size and in weight. When a small battery is employed, in general, frequent battery replacement is required because of its small battery capacity, which requires a user to do cumbersome operation of battery replacement, and thus, is not preferable. In addition, it is desirable that battery replacement can be avoided as far as possible from an economical aspect or an environmental aspect including disposal of used battery.
Further, another problem with a portable power supply apparatus includes circuit malfunction caused by faults of components. At the time of designing a circuit for the power supply apparatus, safety is taken into account to avoid such discrepancies that, a high output current exceeding a set level is generated or an output cannot be stopped completely when it must be stopped, even if the above malfunction occurs. For example, such a system is disclosed in National Publication of International Patent Application No. 8-505541.
However, when any of the parts constituting a power supply apparatus fails, influence on operation of the power supply apparatus greatly differs depending on which of these parts fails. When a power supply apparatus itself cannot identify a failure, a user may use the failed unit repeatedly until the failure is found. In order to overcome these problems, a large-scale circuit is generally required, which acts against reductions in size and weights of a power supply apparatus.
In view of the foregoing circumstance, an object of the present invention is to provide a small and light iontophoresis system with superior usability.
The present inventors made efforts earnestly to reduce an iontophoresis system in size and weight. As a result, they found out that if a small secondary battery is employed for a power supply and at least one of charge terminals for charging the battery is also used as an output terminal, a small and light-weight iontophoresis system with superior usability could be used, and accomplished the present invention.
An iontophoresis system according to the present invention comprises a power supply apparatus having a chargeable battery and a plurality of output terminals and a preparation which is connected to the output terminals of the power supply apparatus and which is adopted to administer a drug percutaneously or trans-mucosally, wherein at least one of the output terminals of the power supply apparatus is also used as a charge terminal for charging the battery. Here, a secondary lithium battery, for example, is employed as a chargeable battery.
An iontophoresis power supply apparatus according to the present invention comprises a chargeable battery, a plurality of output terminals for outputting electric energy from the battery, and a charge terminal for charging the battery, wherein at least one of the output terminals is also used as a charge terminal. In addition, the present iontophoresis power supply apparatus preferably comprises a power supply monitoring portion that monitors a battery voltage and gives warning when the battery voltage becomes a predetermined value or lower. Further, the present power supply apparatus preferably comprises a control portion for controlling power supply of electric energy outputted from the output terminals. The control portion is adopted to record a power supply state of electric energy or to externally incorporate a program for power supply control of electric energy.
An iontophoresis charger according to the present invention is adopted to charge a battery of the iontophoresis power supply apparatus. This charger comprises an operational check portion which performs operational check of the power supply apparatus based on an inputted power supply record of the electric energy outputted from the power supply apparatus. This charger can comprise a display portion for displaying a power supply record of the power supply apparatus. In addition, the charger may comprise a program storage portion that stores a program for power supply control of the power supply apparatus.


A method and apparatus for testing the integrity of the dielectric coating on an elongated member. The apparatus includes a pair of opposing, conducting surfaces that can be biased against the dielectric surface, a source of high voltge that can be switchably imposed on the conducting surfaces, a ground for completing an electrical circuit between the elongated member and the source of high voltage, and an electrical circuit for detecting the passage of current through the electrical ground. A first visible indicator on the apparatus shows when the high voltage is applied to the conducting surfaces and a second visible indicator shows when a current is detected through the electrical ground. This apparatus allows the conducting surfaces to be moved longitudinally along the elongated member to test the dielectric integrity of virtually the entire dielectric surface in a single pass. If small gaps exist between the two conducting surfaces in a longitudinal direction, the apparatus can be rotated through an angle about the longitudinal direction and the apparatus passed along the elongated member a second time.

It is typically necessary to run metallic lines, such as tubing carrying hydraulic fluid or fuel through aircraft structures. In many instances, such lines necessarily closely approach fuel tanks or other sources of ignitable materials. In order to prevent an electrical arc from occurring due to a lightning strike on the aircraft structure, possibly igniting these materials, it is necessary to apply a dielectric insulation to the outer surface of the metallic lines.
This is a particular problem in aircraft structures made from low-conductivity composite materials. A high current surge imposed in a composite material aircraft structure by a lightning strike will cause a high voltage to be generated between the low-conductivity structure and the metallic tubing. This generated high voltage is particularly hazardous where the tubing is supported by clamps. The dielectric insulation presently used is one or more layers of MIL-I-23053/8 (Kynar) heat shrink tubing or some form of Kapton film.
One difficulty with the use of such insulating material is that it is difficult to check the dielectric strength of the material after it has been installed on the tubing. This is particularly so after the tubing has been placed in the aircraft structure. Since the dielectric material is fragile, it can easily and unknowingly be damaged during assembly or subsequent servicing, with a resultant loss of its dielectric strength. A lightning strike could then cause a spark near a fuel tank and result in the loss of the aircraft.
Various apparatus have been proposed in the past for testing dielectric coating on tubing and the like. For example, Saw, in U.S. Pat. No. 2,920,270, discloses a high-voltage insulation tester for detecting flaws in coated pipes. Saw's invention, which is intended for use with pipes which have been buried in the ground, incorporates a test instrument having a grounding lead that can be connected to a spike driven into the ground and a high-voltage lead with a "bracelet" made from a helical metal spring. The metal spring is stretched around the outer surface of the pipe whose coating is to be tested and the voltage applied. The test instrument detects any current passing through an external leakage path which includes a break in the dielectric coating formed around the pipe. The bracelet can slide along the pipe to test the dielectric coating. However, since the spring bracelet only touches the coated pipe at those discrete points where the helix of the spring is closest to the pipe, the apparatus disclosed by Saw can provide only a rough test of the integrity of the coating on the pipe. For example, breaks in the dielectric coating which are smaller than the separation between adjacent wraps of the spring bracelet may not be detected by the apparatus disclosed in Saw, even if the bracelet makes multiple passes along the pipe.
Mantilla, in U.S. Pat. No. 2,237,187, discloses a trouble detector which checks for electrical faults by penetrating the insulation around electrical conductors. The apparatus disclosed by Mantilla therefore destroys the integrity of the dielectric coating at discrete points and, accordingly, is unsuitable for testing the integrity of the dielectric coating formed around a hydraulic fluid or fuel line. In addition, the apparatus disclosed by Mantilla is incapable of being moved along the length of the tubing while performing its testing function.
Kamper, in U.S. Pat. No. 2,229,927, discloses an electrical tester for checking automotive electrical systems. Kamper's apparatus consists of a hand-held tool having electrical connectors and indicator lights. Kamper's tool makes probing contact with electrical conductors at single points. Once a connection has been made between the tool and the electrical conductor, the tool cannot be moved along the conductor without breaking the connection.
Further, Wiseman et al., in U.S. Pat. No. 3,810,007, disclose a "holiday" detector and coating resistivity checker which incorporates a ring-shaped probe employing a sponge which is saturated with a suitable electrolyte. The probe is slipped over a pipe whose coating is to be tested and is then longitudinally moved along the pipe to test for breaks in the dielectric coating. Wiseman et al. disclose a second form of a probe having a rectangular contact surface attached to a handle for use in checking portions of nonconducting coatings on large vessels or large-diameter pipes. Wiseman et al. do not disclose a probe which can simultaneously test substantially the full circumference of a pipe which does not have at least one end accessible.
Accordingly, it is desirable to have a method and apparatus for testing a dielectric coating which can simply and efficiently test the integrity of a dielectric coating formed on the outer surface of an elongated member which does not necessarily have at least one end accessible.

Method and apparatus for testing a dielectric coating


Crystallizer, or inner portion, of a mold for the continuous curved casting of thin slabs, which has at least its outer curved extrados plate (10) containing a substantially central enlargement hollow (11) starting from the upper surface (13) of the outer plate (10) and being reduced progressively, to zero in the curved inner surface (12) of the plate (10) for sliding of the molten metal, the enlargement hollow (11) being defined by a determined profile, the profile being determined lengthwise by an angle ".alpha." and crosswise by an angle ".beta.", wherein the angle ".alpha." should not exceed a maximum value of 5.degree. and may vary, from the center line to the sides of the hollow (11), according to a linear development contained within a field limited at its upper end by that maximum value and at its lower end by zero.

This invention concerns a crystallizer, or inner portion, of a mold for the continuous curved casting of thin slabs. To be more exact, this invention concerns a crystallizer which contains in its upper portion at a position in the center of the inner side of its longer sidewalls an enlargement hollow for introduction of the discharge nozzle of tundishes.
This enlargement hollow is necessary for introduction of the discharge nozzle since the width of the space for passage of the molten metal varies from 25 to 70 mm.; this enlargement hollow is disclosed in U.S. Pat. No. 2,564,723, which teaches the symmetrical enlargement of a straight, vertical crystallizer and is therefore not suitable for curved crystallizers.
SU-A-143.215 teaches that this enlargement should be shaped with a substantially cylindrical development, and this document too concerns a straight, vertical crystallizer.
EP-A-0.230.886 is associated with a straight, vertical crystallizer and discloses a symmetrical enlargement with inclined, vertical walls having a substantially rectangular development.
DE-A-3.501.422, EP-A-0.149.734 and DE-A-3.907.351 too disclose a straight, vertical crystallizer with a symmetrical enlargement.
EP-A-0.300.953 discloses a crystallizer of which the upper portion in which the discharge nozzle of the tundish is inserted is straight and vertical, whereas the lower portion is curved; the upper portion of the crystallizer may also include an arcuate part, which can be on one long side or the other, but the document does not give any geometric defining parameter; it does not in any way disclose the case of a wholly curved crystallizer but does provide for a change of direction of the skin of the thin slab being formed. This change of direction takes place where the straight, vertical portion is joined to the lower curved portion, and creates problems for the skin being formed owing to separations, interruptions in the surface, localized melting and reduced extraction speeds.
In the technology of the state of the art, the steel during continuous casting with partly curved molds of a known type undergoes dynamic effects due to the extraction movement and to the effects of shrinkage caused by cooling.
EP-A-0.276.418 and JP-A-58-97466 disclose lateral closure elements to determine the length of the casting chamber; the former document concerns straight, vertical crystallizers, while the latter concerns curved crystallizers.
Next, it should be borne in mind that it has been deemed hitherto that an enlargement having a lenticular shape without special limitations of a geometric type would be enough for the purpose.
Since in actual practice in enlargements having a lenticular shape, that is to say, in enlargements shaped with a curve having a radius of a given value there remains a concentration of tensions, caused by the geometric configuration, in the skin forming in contact with the zone uniting the lenticular shape to the surrounding surfaces, DE-A-3.907.351 teaches the inclusion of connecting curves, which, however, are not quantified dimensionally and are therefore contained in the state of the art, which teaches that a union should be created and that a sharp edge should not be left.
Moreover, according to the teachings of the state of the art relating, in particular, to partly curved molds there remains a tendency for the removal and/or tearing of the skin during the downward movement.
In fact, the skin tends to follow a line at a tangent to its own trajectory and the present applicants have found that if this line at a tangent forms, together with the surface of the crystallizer, an angle greater than a given value, separation may occur.
Such separation takes place when the skin is consolidated enough and the ferrostatic pressure is not high enough. In such cases a breakage of the skin by tearing may take place directly.