A semiconductor memory device comprises a first bit line, a second bit line paired with the first bit line, a third bit line branch-connected with the first bit line, a fourth bit line paired with the third bit line and branch-connected with the second bit line, a memory cell array connected to the bit lines, a first reference cell, and a second reference cell. The first reference cell is connected to the first bit line and the third bit line, constituted by a cell which is formed of substantially the same area, capacity and structure as the memory cell array, and providing a reference potential at the time of reading out data from memory cells in the memory cell array. And the second reference cell is connected to the second bit line and the fourth bit line, constituted by a cell which is formed of substantially the same area, capacity and structure as the memory cell array, and providing a reference potential at the time of reading out data from the memory cells in the memory cell array. The memory cell array is a non-volatile type constituted by ferroelectric cells.

1. Field of the Invention
The present invention relates to a cell data sense circuit for a non-volatile semiconductor memory using a ferroelectric cell and requiring no refresh operation, and, in particular, to a semiconductor memory employed, for example, as a semiconductor disc substituted for a magnetic disc, or a buffer memory of image data for image processing.
2. Description of the Related Art
As shown in FIG. 16, a conventional DRAM (dynamic random-access memory) employs a memory cell comprising a capacitor C1 for retaining information and a MOS transistor T1 for charge transfer. In this memory cell, a predetermined cell plate voltage Vp is applied to one end of the capacitor C1. When the potential on a word line WL is set to a high level and the MOS transistor T1 is turned on, electric charge flows into the capacitor C1 from a bit line BL through the MOS transistor T1. When the potential on the word line WL is set to a low level and the MOS transistor T1 is turned off, the charge (data) is retained in the capacitor C1.
As described above, since the DRAM has a simple cell structure, the cell area is small. Thus, as a high-density memory element, the DRAM is the most popular of all types of semiconductor memories. However, the DRAM has a disadvantage. Namely, since data is retained by cell charge stored in the capacitor, there is a concern that the charge is lost because of a sub-threshold leak in the charge transfer transistor. As is well known, in order to retain cell data, a refresh operation is repeated at a predetermined interval to supply charge.
Though high-speed write/read operation can be performed in the DRAM, the DRAM is a so-called volatile semiconductor memory wherein a refresh operation is not carried out once the power is turned off, and the stored data is lost. Under the circumstances, a study has been made of a RAM having the same high-density as a DRAM, being subjected to high-speed read/write operation, and being free from the need for the refresh operation or volatility at the time of turning-off. In particular, a ferroelectric cell has been proposed as a non-volatile memory element in which data can be easily rewritten (Electronics/Feb. 4, 1988, p. 32: Electronics/Feb. 18, 1988, pp. 91-95). In this ferroelectric cell, the spontaneous polarization characteristic of a ferroelectric body (lead zirconium titanate) is utilized to retain data.
In general, the ferroelectric cell is applied to a RAM such that an additional element is provided in a SRAM cell. Thus, the area of a cell is not decreased. Even if a structure similar to that of a DRAM cell is employed, two cells are needed for one bit, and a read operation of cell data is complex.
In the above-described conventional method of applying a ferroelectric cell to the RAM, the area of the cell becomes large and the read operation of cell data is complex. Under the circumstances, there is proposed a non-volatile semiconductor memory in which the ferroelectric cell can be used where a refresh operation is not required. This semiconductor memory can be realized without using unconventional DRAM circuit design techniques or process techniques.
This proposed semiconductor memory has a sense amplifier system for detecting and amplifying a potential variation in paired bit lines which is caused by the operation of a memory cell. In this memory cell, a ferroelectric body is interposed between the electrodes of a capacitor. The potential of one electrode of the ferroelectric capacitor is set to an intermediate level between potentials corresponding to logical "1" and "0" levels of the bit lines. A charge transfer transistor is connected between the other electrode of the ferroelectric capacitor and the bit lines. Where the maximum distance between the electrodes of the ferroelectric capacitor is represented by d (cm) and the intensity of a electric field needed for inverting the spontaneous polarization of the ferroelectric body and stabilizing the inverted polarization is represented by Et (v/cm), the value of Et.times.d is smaller than half the value of the potential difference between the logical "1" and "0" levels of the bit lines.
Until the access to cell data is started, the paired bit lines are equalized to a level substantially equal to the potential level of a cell plate. After the access is started and just before the charge transfer transistor of the memory cell and a charge transfer transistor for the reference cell are turned on, the potentials of the paired bit lines are set to a level near one of the two levels of power source potentials Vcc and Vss. Thereafter, the charge transfer transistor of the memory cell and the charge transfer transistor for the reference cell, connected to a bit line paired with the bit line connected to the memory cell, are turned on. One of the bit lines is supplied with a reference level potential by the reference cell, and the other is supplied with a data level potential by the data from the memory cell. Then, as in a conventional DRAM, the potential levels of the paired bit lines are sense-amplified.
Hereinafter, the above semiconductor memory will be described in detail with reference to the accompanying drawings. FIG. 5 shows a semiconductor memory having a sense amplifier system for detecting and amplifying a potential variation in paired bit lines due to the operation of a memory cell. Namely, FIG. 5 shows a portion (corresponding to one column of a matrix-shaped memory cell array) of a memory employing a reference cell and a memory cell having a ferroelectric capacitor in a cell data sense system of a conventional DRAM.
Symbols BL and BL denote a pair of bit lines. Memory cells MC1 and MC3 are connected to the bit line BL, and memory cells MC2 and MC4 are connected to the bit line BL. Word lines WL1 and WL2 are connected to the gates of charge transfer transistors T1 and T3 of memory cells connected to the bit line BL. Word lines WL1 and WL2 are connected to the gates of charge transfer transistors T2 and T4 of the memory cells connected to the bit line BL. A reference level generating circuit REF supplies a reference level corresponding to a memory cell readout level to the bit lines. Symbol PR indicates a bit line precharge circuit, symbol SA indicates a sense amplifier for detecting and amplifying a potential variation in the bit lines, symbols DQ and DQ denote a pair of data lines, and symbols G1 and G2 denote bit line selection transistors connected between the bit lines and the data lines and switched by a column selection signal CSL.
As shown in FIGS. 6A and 6B, each of the memory cells MC1 to MC4 has a structure wherein a ferroelectric body 20 is interposed between capacitor electrodes 21 and 22 formed of a conductor, such as metal. Each of the memory cells MC1 to MC4 comprises a ferroelectric capacitor CF, a potential VPF of one of the electrodes which is set to (VH+VL)/2 or an intermediate level. Potential VH corresponds to logical "1" level of the bit line and potential level VL corresponds to logical "0" level of the bit line. Charge transfer transistor TF is connected between the other electrode of the ferroelectric capacitor CF and the bit line BL (or BL) and has its gate connected to the word line WL. A maximum distance d (cm) between the electrodes of the ferroelectric capacitor CF is less than a predetermined value, as described later.
The reference level generating circuit REF is constituted by a reference cell comprising two reference ferroelectric capacitors having substantially half the area and half the capacity of the ferroelectric capacitor CF of each of memory cells MC1 to MC4, and two charge transfer transistors each connected between the two reference ferroelectric capacitors and one bit line.
FIG. 8 is a graph showing the characteristic of the ferroelectric body. The abscissa of the graph indicates the value E(V/cm)=V(V)/d (cm), in the case where an external electric field or a voltage V(V) is applied to the ferroelectric body, i.e., between the electrodes 21 and 22 of the ferroelectric capacitor. The ordinate of the graph indicates spontaneous polarization P. The relationship between P and E of the ferroelectric body is a hysteresis relationship.
Suppose that an electric field is applied to the ferroelectric body in which domains of polarization are non-uniform and polarization does not occur as a whole. When the electric field E is increased in the positive direction, the degree of polarization increases from point 0 to point A. At the point A, all domains are polarized in one direction and the degree of polarization reaches a maximum value. The intensity of the electric field applied at this time is expressed by Et. Thereafter, even if the intensity of electric field E is lowered to zero, the degree of polarization does not decrease to zero and remains at point PS. Then, if the intensity of electric field E is increased in the negative direction, the degree of polarization changes from point A to point B (curve 41 in FIG. 8). At point B, all domains of the ferroelectric body are polarized in a direction opposite to the direction of polarization at point A. The electric field at this time is represented by -Et. If the intensity of electric field E is increased once again, the degree of polarization changes from point B to point A along a curve 42 in FIG. 8. In this case, even if the intensity of the electric field E is lowered to zero, the degree of polarization is kept at -PS.
As described above, once a voltage for generating the electric field Et is applied to the ferroelectric capacitor having the ferroelectric body between its electrodes, the direction of polarization is maintained as spontaneous polarization even if the electrodes are set in a floating state. The surface charge of the ferroelectric body due to the spontaneous polarization is not naturally lost owing to leakage, etc. Unless an electric field of the opposite direction is applied to set the degree of polarization to zero, the direction of polarization due to the electric field Et is maintained, and the degree of polarization remains at .vertline.PS.vertline..
The maximum distance d (cm) between the electrodes of the ferroelectric capacitor shown in FIG. 6B must be set so that the direction of polarization of the ferroelectric body may be reversed by the potential VH corresponding to the logical "1" level of the bit line and the potential VL corresponding to the logical "0" level of the bit line. In other words, the following condition must be satisfied: ##EQU1## where VPF is a cell plate potential.
In this condition, the intensity of electric field Et is determined by the ferroelectric body, and is sufficient for reversing the direction of the polarization and keeping the degree of polarization to a maximum value. For example, if Et=1000 V/cm, VH=5 V, and VL=0 V, then VPF=2.5 V. Thus, EQU d<2.5 V+1000 V/cm=25 .mu.m
If the distance d between the electrodes is set, as described above, the direction of polarization can be reversed between the case where the voltage VH is applied to the bit line and the case where the voltage VL is applied to the bit line. In addition, spontaneous polarization representative of given data is retained until the direction of polarization is forcibly reversed.
A description will now be given of a specific structure of the memory cell having the ferroelectric capacitor as shown in FIG. 6A. The direction of polarization of only a portion of the ferroelectric body, to which an electric field is applied, is changed. Namely, the polarized portion has a single domain structure. Thus, the direction of polarization of respective portions of a continuous ferroelectric layer can be changed. Thus, the ferroelectric layer can be used, like an oxide layer in a memory cell of a conventional DRAM, and the data represented by the direction of polarization can be retained in a non-volatile manner. In handling the non-volatile memory, the ratio of a diffusion layer of a node connected directly to the electrode of the memory cell should be a lowest possible value, to reduce the possibility of coupling between the memory cell and a substrate potential level. If the possibility of coupling is not reduced, noise may reverse the direction of spontaneous polarization in the memory cell because of the substrate potential level at the time of switching power on or off.
FIGS. 9A and 9B show a plane pattern and a cross section, respectively of the above-described memory cell. After a field oxide film 2 for element separation is formed on the surface of a silicon substrate 1, a first conductive layer (polysilicon), which becomes a gate electrode (and word line) 4 of a charge transfer transistor, is patterned and formed on the surface of the substrate in an element region, with a gate insulation film 3 interposed. Then, with the gate electrode 4 being used as a mask, impurity diffusion regions 5 and 5-2 serving as a source or a drain of the charge transfer transistor are formed, and an insulation layer 6 such as an oxide film is formed on the substrate.
A contact hole is formed in the insulation layer 6 so as to reach the impurity diffusion region 5 serving as the source (or drain) of the charge transfer transistor. Then, a second conductive layer 7 or a polysilicon layer is deposited on the insulation layer 6 and is put in electrically conductive contact with the impurity diffusion region 5. The polysilicon layer 7 is patterned in an island-shape, and one electrode 7 of an independent ferroelectric capacitor of each memory cell can be formed.
A ferroelectric layer 8 used in common with the memory cells is formed over the surface of the substrate. A third conductive layer 9 or a polysilicon layer is deposited over the ferroelectric layer 8. The polysilicon layer 9 and ferroelectric layer 8 are patterned to form the other electrode (plate electrode) 9 of the ferroelectric capacitor in common with the respective memory cells. Consequently, that portion of the ferroelectric layer, which is not located below the third conductive layer or polysilicon layer 9, is removed.
An interlayer insulation layer 10 such as an oxide film is formed on the substrate. After a contact hole is formed in the interlayer insulation layer 10 to reach the impurity diffusion region 5-2, serving as the drain (or the source) of the charge transfer transistor, a forth conductive layer 11, which is formed of an aluminum layer, polysilicon layer, or a polysilicon/silicide composite layer, is deposited over the interlayer insulation layer 10 and is brought into electrically conductive contact with the impurity diffusion region 5-2. The fourth conductive layer 11 is patterned to form a bit line 11.
In the above process, a memory cell having a ferroelectric capacitor is formed, with a structure substantially similar to a "stacking" structure of a memory cell of a conventional DRAM. Thus, the area occupied by the memory cell is small, and the degree of integration is substantially the same as that of the conventional DRAM.
The operation of sensing memory cell data in the RAM having the above-described sense system will now be described.
First, the amount of charge transferred between a memory cell and a bit line will be described. FIGS. 10A and 10B schematically show potentials at respective points in the initial state wherein the memory cell is not connected to the bit line, and in the final state wherein the memory cell is connected to the bit line (selection state). The potential at the cell plate of a ferroelectric capacitor CF of the memory cell is VPF. Depending on whether the data written in the memory cell is "0" or "1", a potential Vi of a counter electrode (an electrode connected to a charge transfer transistor) is given by EQU VL.ltoreq.Vi.ltoreq.VPF, or VPF.ltoreq.Vi.ltoreq.VH
When the written data is "0", the potential Vi is equal to VL at first, and the spontaneous polarization corresponding to "0" is produced. Then, the charge transfer transistor is actuated with a low current, so that Vi becomes equal to VPF if the memory cell is not accessed for a long time in a time period other than a read time period. Consequently, Vi is set to an intermediate level between VL and VPF, in a certain access interval.
Similarly, when the written data is "1", Vi is set to VH to produce the spontaneous polarization corresponding to "1". Thus, Vi may be set to an intermediate level between VH and VPF. The potential Vi is finally set to VPF, since, when the electrode is set in the complete floating state, it is possible that the written spontaneous polarization may be reversed by the potential of the electrode owing to the leakage of charge (for example, when the charge leaks and decreases to a substrate potential level).
Supposing that an initial level of bit line capacity CB is VSS, the degree of spontaneous polarization is PS, a counter area of the ferroelectric capacitor CF is A, and the capacity of the capacitor CF is C, FIG. 10B shows the bit line potential Vf, in the final state (selection state) wherein the memory cell has been connected to the bit line, in relation to the potential Vi. When the written data is "0", EQU Vf=C.multidot.Vi/(C+CB)
When the written data is "1", EQU Vf=2.multidot.A.multidot.PS/(C+CB)+C.multidot.Vi/(C+CB)
In the case of the memory cell in which data "0" is written and in the case of the memory cell in which data "1" is written, a difference represented by: EQU 2.multidot.A PS/(C+CB)
exists in the bit line potential vf. Thus, if a level VREF can be set as a reference level of data "0" and data "1", as shown in FIG. 10B, the data in the memory cell can be sensed, irrespective of the potential Vi of the counter electrode.
On the other hand, when the bit line potential VB, in the state prior to reading, is VCC, the bit line potential Vf in the final state (selection state) is represented by value obtained by adding EQU CB.multidot.VCC/(C+CB)
to the value of Vf, shown in FIG. 10B.
The operation of setting the above-mentioned reference level will now be described with reference to FIG. 11A and FIG. 11B. FIGS. 11A and 11B schematically show potentials at respective points, in the initial state wherein the reference cell in the reference level generating circuit REF shown in FIG. 7 is not connected to the bit line, and in the final state (selection state) wherein the reference cell is connected to the bit line. Each of two reference ferroelectric capacitors DCA and DCB in the reference cell has about half the area A/2 and half the capacity C/2 of the ferroelectric capacitor CF in the memory cell.
The cell plate potential of the reference ferroelectric capacitor DCA is represented by VPF (equal to the cell plate potential of the ferroelectric capacitor CF of the memory cell), and the cell plate potential of the reference ferroelectric capacitor DCB is represented by VP (potential VCC or potential VSS). The potential corresponding to Vi in FIG. 10 is VPF. Depending on whether the bit line potential VB prior to the read operation is VSS or VCC, the initial state of the reference ferroelectric capacitor DCA is set, as shown in FIG. 11B.
Namely, when VB=VSS, data "1" is written in the reference ferroelectric capacitor DCA. When VB=VCC, data "0" is written in the reference ferroelectric capacitor DCA. In the initial state of the reference ferroelectric capacitor DCB, data "0" is stored when VP=VCC and data "1" is stored when VP=VSS since the potential of the counter electrode is VPF. When the reference cell is connected to the bit line, the state "0" or "1" of the ferroelectric body in the reference ferroelectric capacitor DCB is unchanged, even if the bit line potential VB prior to the read operation is VSS or VCC. In the reference ferroelectric capacitor DCA, the relationship between the bit line potential VB and the potential VPF is established such that the value of data in the capacitor DCA is inverted once the reference cell is connected to the bit line. Thus, in the final state (selection state), wherein the reference cell has been connected to the bit line, when the bit line potential VB prior to the read operation is VSS, EQU Vf=A.multidot.PS/(C+CB)+C.multidot.VPF/(C+CB)
This value corresponds to the reference level VREF shown in FIG. 10B.
Even when the bit line potential VB prior to the read operation is VCC, the potential Vf is set to the reference level obtained in the case where the bit line potential VB prior to the read operation, which is obtained by adding CB.multidot.VCC/(C+CB) to the reference level VREF shown in FIG. 10B, is VCC.
FIG. 7 shows a structure of the above-described reference level generating circuit REF for generating the reference level, wherein the bit line potential VB prior to the read operation is VSS. In FIG. 7, a bit line BL is connected to a single reference cell RC, and a bit line BL is connected to a single reference cell RC. The paired bit lines are connected to a bit line level set circuit LS. The reference cell RC, connected to the bit line BL, comprises two reference ferroelectric capacitors (DC1 and DC2), each having about half the area A/2 and half the capacity C/2 of the ferroelectric capacitor CF of the memory cell, and two charge transfer transistors (DT1 and DT2) connected between first electrodes of the two reference ferroelectric capacitors and the bit line BL.
Similarly, the reference cell RC connected to the bit line BL comprises two reference ferroelectric capacitors (DC3 and DC4), each having about half the area A/2 and half the capacity C/2 of the ferroelectric capacitor of the memory cell, and two charge transfer transistors (DT3 and DT4) connected between first electrodes of the two reference ferroelectric capacitors and the other bit line BL.
The gates of the two charge transfer transistors (DT1 and DT2) connected to the bit line BL receive dummy word signals through a dummy word line DWL. Second electrodes of the reference ferroelectric capacitors (DC1 and DC2), connected to the two charge transfer transistors (DT1 and DT2), are constantly supplied, respectively, with the potential VSS and an intermediate level potential (VH+VL)/2 between the potential VH corresponding to logical bit line level "1" and the potential VL corresponding to logical bit line level "0". The spontaneous polarization of the reference ferroelectric capacitor DC2 supplied with the intermediate level potential is set such that the direction of polarization is reversed when the charge transfer transistor DT2 connected to the capacitor DC2 is turned on at the data sense time.
A reset transistor DS1 is connected between the potential source VCC and a connection node Nd of the reference ferroelectric capacitor DC2 supplied with the intermediate level potential and the charge transfer transistor DT2. The reset transistor DS1 resets the potential at the connection node Nd at every one-memory cycle. The gate of the reset transistor DS1 is supplied with a reset signal DCST through a reset line.
Similarly, the gates of the two charge transfer transistors (DT3 and DT4) connected to the other bit line BL are supplied with dummy word signals through an inversion-side dummy word line DWL. Second terminals of the reference ferroelectric capacitors (DC2 and DC4) connected to the two charge transfer transistors (DT3 and DT4) are constantly supplied, respectively, with the intermediate level potential and the potential VSS. The spontaneous polarization of the reference ferroelectric capacitor DC3 supplied with the intermediate level potential is set such that the direction of polarization is reversed when the charge transfer transistor DT3 connected to the capacitor DC3 is turned on at the data sense time.
A reset transistor DS2 is connected between the potential source VCC and a connection node Nd of the reference ferroelectric capacitor DC supplied with the intermediate level potential and the charge transfer transistor DT3. The reset transistor DS2 resets the 5 potential at the connection node Nd at every one-memory cycle. The gate of the reset transistor DS2 is supplied with the reset signal DCST through the reset line.
The operation of the memory having the cell data sense system shown in FIG. 5 will now be described with reference to operation waveforms shown in FIG. 12 and the reference level generating circuit REF shown in FIG. 7. Until access to the memory cell data is started, the potential level of the bit line pair is substantially equal to the cell plate potential level VPF. After access is started and just before the charge transfer transistor of the memory cell and the charge transfer transistor of the reference cell are turned on, the level of the bit line pair is set to a level close to the potential VCC or the potential VSS (in this embodiment, potential VSS).
Then, the charge transfer transistor of the memory cell and the charge transfer transistor of the reference cell, which is connected to the bit line paired with the bit line of this memory cell, are turned on. The spontaneous polarization of one of the reference ferroelectric capacitors of the reference cell is reversed, so that one of the bit lines is set to a level corresponding to the memory cell data. Thereafter, as with a conventional DRAM, the level of the bit line pair is sense-amplified.
This operation will now be described in greater detail. Suppose that the level of the word line WL1 is raised, and the memory cell MC1 is accessed. Before the access is started, the dummy word lines DWL and DWL are set to the "H" level, the charge transfer transistors DT1 to DT4 of the reference cell are fully turned on, and the levels of all word lines WL1, WL1, WL2 . . . are set to such levels that the charge transfer transistors T2 to T4 may be turned on. Also, the BLP signal has the "H" level, transistors P1 to P3 of a precharge circuit PR are turned on, and the bit lines BL and BL are set to the VPF level.
Thus, the potentials of the bit line-side electrodes (connection node Nd and Nd) of the reference ferroelectric capacitors DC2 and DC3 are set to VPF, and the potentials of the bit line-side electrodes of the ferroelectric capacitors C1 to C4 of the memory cell are set to a level close to VPF. The reference ferroelectric capacitors DC1 and DC4 having the cell plate potential VSS are set to the "1" level. The reference ferroelectric capacitors DC2 and DC3 having the cell plate potential VPF are set to the "1" level at the end of the previous access operation.
When a data address is set and the access of data is started, the potentials on the dummy word lines DWL DWL and the word lines WL1, WL1, WL2 . . . are set to VSS. The charge transfer transistors DT1 to DT4 of the reference cells and the charge transfer transistors T1 to T4 of the memory cells are turned off. Then, a BLP signal falls, and transistors P1 to P3 of a pre-charge circuit PR are turned off. The potential levels of bit lines BL and BL are made to differ from the VPF level. Then, a BLST signal rises, and transistors S1 to S3 of the bit line level set circuit LS are turned on. Consequently, the bit lines BL and BL are set to levels for cell data detection. In this example, the bit lines BL and BL are set to VSS level.
Thereafter, when the BLST signal falls, only the word line WL1 and the dummy word line DWL are activated to transfer data to the bit lines BL and BL, thereby rendering the charge transfer transistor T1 of the memory cell and the charge transfer transistors (DT1 and DT2) of the reference cell fully conductive. The transfer level for transferring data to the bit lines BL and BL is as shown in FIGS. 10B and 11A, and a difference in level corresponding substantially to A. PS/(C+CB) occurs between the paired bit lines.
Consequently, in the ferroelectric capacitor, the greater the area A, the greater the degree of spontaneous polarization PS of ferroelectric body; and the smaller the bit line capacity CB, the greater the data transfer amount. However, unlike the conventional DRAM, it is desirable that the capacity of the memory cell be small. In this case, since the area A cannot be decreased, it is better to increase the thickness of ferroelectric body as long as the inversion condition for the spontaneous polarization PS is satisfied.
Regarding the sense amplification after the data is transferred to the bit lines BL and BL, like in the conventional DRAM, the levels in the bit lines BL and BL are set to VSS-side value. In this embodiment, when the sense amplification is performed, the level of a SEP signal is raised, and then PMOS transistors SP1 and SP2 of a sense amplifier SA make the potential of the bit line varied toward VCC-side. Then, the level of a SEN signal is lowered, to maintain the level of the bit line on the VSS-side by NMOS transistors SN1 and SN2. After the level difference between the paired bit lines is sufficiently amplified, the level of a selected CSL signal is raised, to turn on transistors G1 and G2. Data are transferred to data lines DQ and DQ through the transistors G1 and G2, and the readout operation is completed.
For the next cycle, the operation for initialization is started. At first, the raised levels of the word line WL1 and dummy word line DWL are lowered. Then, the level of the SEP signal lowered, and the level of the SEN signal is raised. The sense amplifier SA is reset, and simultaneously the level of the DCST signal is raised to turn on the transistors DS1 and DS2. The potentials at connection nodes Nd and Nd are set substantially to VCC level. The reference ferroelectric capacitors DC2 and DC3, the cell plate potentials of which are VPF, are set in the write state of "1", the level of the DCST signal is lowered. At this time, the level of the BLP signal is raised to turn on the transistors P1 to P3, and the bit lines BL and BL are precharged/equalized to the VPF level.
When the precharging/equalizing step is completed, the levels of dummy word lines DWL and DWL and all word lines WL1, WL1 , WL2 . . . are raised, and the potential at the electrode of the memory cell is set to VPF level. In this case, it is necessary that the levels of the dummy word lines DWL and DWL be sufficiently raised and the potential of the electrode of each of reference ferroelectric capacitors DC1 to DC4 be set to VPF level for the preparation for the next cycle. However, regarding the memory cell, it is sufficient that the charge transfer transistors T1 to T4 are slightly turned on, so that an electric field which may reverse the spontaneous polarity may not be applied to the cell, and so that power is supplied to the electrode of the cell to compensate the potential which has leaked to nodes other than VPF. Namely, it is sufficient that the levels of word lines WL1, WL1, WL2 . . . are slowly raised to the level close to a threshold voltage V.sub.TH of each of charge transfer transistors T1 to T4 of the memory cells added to the VpF level V.sub.TH +VpF.
Consequently, the levels of all word lines WL1, WL1, WL2 . . . can be raised with a lowest possible power and current peak. Thus, when the access is repeated with a minimum cycle, it is possible that the charge transfer transistors T1 to T4 of the memory cell are not turned on.
In the case of a long access cycle, the destruction of the cell data can be prevented as follows. Namely, when the paired bit lines are equalized and kept at the intermediate potential level for a long time, before the memory cell data access is started, the charge transfer transistor of the memory cell is turned on so as to compensate leaked potential at the memory cell electrode, maintain the potential at the electrode in the VPF level, and prevent the ferroelectric spontaneous polarization from being reversed.
The read operation with the bit line potential VB, prior to readout, equal to VSS has been described. The VCC system wherein the bit line potential VS prior to the readout, is VCC differs from the VSS system in the following respects:
(1) One terminal of each of transistors S1 and S3, controlled by the BLST signal, is connected to VCC potential in order to cause the transistors S1 and S3 to set the levels of bit lines BL and BL near the VCC level,
(2) One terminal of each of transistors DS1 to DS2, controlled by the DCST signal, is connected to VSS potential in order to cause the transistors DS1 to DS2 to write "0" in the reference ferroelectric capacitors DC2 and DC3, and
(3) The order of operation steps of PMOS transistors SP1 and SP2 and NMOS transistors SN1 and SN2 for operating the sense amplifier SA is reversed, compared to the above-described operation steps.
The data write process for writing data in the memory cell is the same as is employed in a conventional DRAM. Thus, a detailed description thereof may be omitted.
The above description has been directed to the operation of the data sense amplification. When the above memory device is utilized as a non-volatile RAM, attention should be paid to the order of set/reset of internal signals at the time of the switching ON/OFF of the power. If the attention is not fully paid, the contents of the ferroelectric capacitor may be written owing to transient voltage. In particular, the potential level VPF, which is the cell plate level and the level of paired bit lines, has a large load capacity and varies slowly at the power ON/OFF time. Thus, the VPF level and the word line activation timing must be determined in a predetermined order of operation steps.
If the word line is activated before the cell plate level and the bit line level reach the VPF level, the cell contents may be destroyed. FIG. 13 schematically shows the node level raising process at the time of power "ON".
In FIG. 13 a cell plate level detecting circuit 91 monitors the cell plate level. An output .psi.P at the time of power "ON" is "L". When the cell plate level becomes close to VPF, the output .psi.P becomes "H". A bit line precharge level detecting circuit 92 monitors the bit line potential level. At the time of power "ON", the output .psi.B is "L". When the level of the BLP signal rises upon power "ON" and the bit line is precharged so that the level of the bit line may reach VPF, and the output .psi.B becomes "H". After the two signals .psi.P and .psi.B are fed to an AND gate 93, the outputs of a word line level generating circuit 94 and a dummy word line level generating circuit 95 are supplied to the word line and the dummy word line through the AND gates 96 and 97. Consequently, the potential at the bit line-side electrodes of the memory cell and the reference cell is changed to VPF. Until this time, the charge transfer transistor is turned off, and the bit line-side electrode is set in a floating state. Thus, an electric field for reversing the spontaneous polarization is not applied to the ferroelectric body of the ferroelectric capacitor.
Further, after the level of the dummy word line is fully raised by the output of the dummy word line level generating circuit 95, and the bit line-side electrode level of the reference cell is set to VPF, a memory control external signal is received by an AND gate 98. Thus, without erroneous sense operation, the memory cell can be accessed.
In other words, after the cell plate level and the bit line level are fully raised by the sequence of the operation for raising the potential levels at electrode nodes at the power "ON" time, the charge transfer transistor between the cell and the bit line is turned on. Thereafter, the memory control external signal is received, and the internal signal is generated to enable the cell data sense to be performed.
At the power "OFF" time, unless the bit line level and the cell plate level are lowered after the memory cell and the reference cell are completely cut off from the bit line, it is possible that a transient voltage which may reverse the spontaneous polarization of the ferroelectric capacitor of the memory cell can be produced. Therefore, it is necessary that the cell plate level VPF and the drive signal SEN for driving NMOS transistors SN1 and SN2 of sense amplifier SA follow the change in VCC with a sufficient time constant. A circuit structure for meeting this condition is shown in FIG. 14.
In the circuit shown in FIG. 14, the output VPF of a cell plate level generating circuit 101 and the output SEN of an SEN level generating circuit 102 are provided with sufficiently large capacitances, as indicated by broken lines. Thus, even if the potential VCC is lowered to VSS, the level of the VCC slowly lowers if charge is not supplied directly to the potential VCC. For this purpose, a diode 103 is connected between a VCC node and the two level generating circuits 101 and 102.
The outputs SEN and VPF are turned off at the inherent time constant of the circuit. Thus, these outputs are turned off with sufficient time allowance after the word line level generating circuit 94 and the dummy word line level generating circuit 95 shown, in FIG. 13, are turned off in response to the power "OFF". For this reason, the cell is not destroyed.
According to the sequence of the operation for lowering the potential levels at respective electrodes at the power "OFF" time, the outputs of the cell plate level generating circuit and the sense amplifier drive level generating circuit are completely turned off, after the circuit for receiving the memory control external signal to produce the internal signal and the circuit for generating the signal for turning on the charge transfer transistor are turned off.
In the above description, the two reference ferroelectric capacitors of the reference cell are connected to one bit line through different charge transfer transistors. However, the same operation and advantage can be attained, even if two reference ferroelectric capacitors (DC1 and DC2) are connected commonly to one bit line BL through a single charge transfer transistor DT1, and two reference ferroelectric capacitors (DC3 and DC4) are connected commonly to the other bit line BL through a single charge transfer transistor DT3, as shown in FIG. 15.
In putting the above-proposed semiconductor memory to practical use, it is difficult to reduce the area and capacity of each of the two reference ferroelectric capacitors of the reference cell to substantially half the area and capacity of the ferroelectric capacitor of the memory cell. If a three-dimensional cell structure is employed, it becomes difficult to pattern the capacitor of the reference cell to have substantially half the area and capacity of the capacitor of the memory cell, and to attain a desired capacity because of variation in quality arising from manufacturing processes. Under the circumstances, in the cell data sense system of the above-proposed semiconductor memory, it is necessary to reduce the area and capacity of each of the two reference ferroelectric capacitors to substantially half the area and capacity of the ferroelectric capacitor of the memory cell, to thereby ensure highly reliable operation. Consequently, it the manufacturing margin as well as operational reliability are lowered and the yield of manufacture.


Breaker units (3, 4) of three-phases are enclosed in a common container (25). The three-phase breaker units and lead conductors (27a, 28a) connected to both ends of the breaker units are arranged on imaginary straight lines that are in parallel each other nearly passing through vertexes of an equilateral triangle. A common operation unit (7) for driving the three-phase breaker units is accommodated outside the container (25) and juxtaposed at a position opposed to one side (28b-28c) of the equilateral triangle. A zero-phase sequence current transformer (ZCT) is provided surrounding the lead conductors of three phases outside the container.

A general three-phase common container-type circuit breaker can be represented by a cylindrical three-phase common tank-type circuit breaker that is employed for a transmission system of higher than 70 kV as shown in FIG. 5, namely in FIG. 1 of Japanese Patent Laid-Open No. 52-27562 distributed on Mar. 1, 1977 and entitled "Gas circuit breaker".
In this circuit breaker, the breaker units of three phases are arranged in the axial direction thereof in a cylindrical container 25 filled with an SF.sub.6 gas, branch tubes 40, 41 are protruded in the radial direction at both ends in the axial direction of the cylindrical container 25, and lead conductors 27, 28 extending in the axial direction of the branch tubes are connected to insulating spacers 26a, 26b that hermetically seal the branch tubes, thereby to form a generally U-shaped current path 27-81-28.
Further, a similar example of three-phase common container-type circuit breaker shown in FIG. 5 can be represented by a cubic type pole switch 2 shown in FIG. 1. The pole switch 2 is constituted at an upper portion of a distribution pole 1 as shown in FIG. 1, and in which distribution lines 29 and 30 are connected to lead conductors 27 and 28 that are lead out nearly horizontally from both ends thereof. Details of the breaker units are constituted in a metal casing filled with the SF.sub.6 gas as shown in FIG. 2 which is a vertical section view of FIG. 1 and as shown in FIG. 3 which is a section view along the line XII--XII in FIG. 2. An insulating cylinder 6 is coupled between a bushing 23a and a bushing 23b mounted on the metal casing 25, and is also filled with the SF.sub.6 gas. The insulating cylinder 6 contains a fixed contact 3 and a moving contact 4 that are electrically connected to the bushings 23a and 23b, respectively, and the moving contact is opened or closed by an operation unit 7 in the metal casing 25 via a drive lever 5. In the insulating cylinder 6 are formed a heating chamber 8 in the vicinity of the fixed contact 3 and a downstream chamber 10 on the side of the moving contact 4. A zero-phase sequence current transformer ZCT for ground protection is arranged to surround three phases along the periphery of the bushing 23a in the metal casing 25, and another current transformer CT for over-current protection is arranged to surround the two-phase bushing 23b, thereby to constitute a sequence that is shown in FIG. 4. The breaker units of three phases are arranged in line in the horizontal direction in the insulating cylinder 6 of a unitary structure as shown in FIG. 3, and are operated by the operation unit 7.
In recent years, it has been studied to replace such a switch having a load current breaking ability only by a pole circuit breaker that has accident current breaking ability. This is because, by imparting accident current breaking ability, the section of power failure can be minimized in case of an accident and the accident can be restored very fast, contributing to strikingly improve reliability in supplying the electric power.
Under the above-mentioned circumstances, it has been studied to upgrade the pole switch shown in FIG. 2 to the pole circuit breaker that has accident current breaking ability, and to constitute the pole circuit breaker using the circuit breaker that is constituted as shown in FIG. 5.
When the conventional cubic type pole switch shown in FIGS. 1 to 3 is to be used as a pole circuit breaker having accident current breaking ability, the zero-phase sequence current transformer ZCT must be arranged at an end of the breaker unit as shown in FIG. 4. According to the conventional constitution in which the lead conductors 27 of three phases arranged horizontally and parallel in line are surrounded as shown in FIG. 2, however, the constitution is in no way desirable for the zero-phase sequence current transformer ZCT that detects ground current based on minute imbalance among the three-phase current, and the precision of detection must be further increased.
When the circuit breaker shown in FIG. 5 is used as a pole circuit breaker, furthermore, it can be contrived to arrange the zero-phase sequence current transformer ZCT in the vicinity of, for example, the insulating spacer 26a. However, the lead conductors 27 positioned at this portion have dissimilar lengths between two phases as shown. Furthermore, a length between support conductors 31 which support the fixed contact of the breaker unit and the lead conductors 27, and the zero-phase sequence current transformer ZCT is different from each other in each phase. Therefore, the constitution is not desirable for the zero-phase sequence current transformer ZCT that detects ground current based upon minute imbalance among the three-phase currents. Furthermore, it is contrived that distribution lines 29 and 30 are led out in a shape of L-type from the U-shaped current path 27-81-28 shown in FIG. 5. However, such an arrangement has same drawback explained in FIG. 5, since the distribution lines 29 and 30 of three phases are not arranged in straight lines but in the shape of the L-type. Accordingly, it is difficult to use the circuit breaker of FIG. 5 as the pole circuit breaker.

Three-phase common container-type circuit breaker


According to one embodiment, a backlight device includes a light guide including an emission surface including a flat area and an inclined area inclined in an out-of-plane direction from an edge of the flat area, a light source emitting light into the light guide, and an optical diffusion sheet on the emission surface. The optical diffusion sheet includes a diffusion flat area overlapping the flat area of the emission surface and a diffusion inclined area overlapping the inclined area of the emission surface, and a haze of the diffusion inclined area is higher than that of the diffusion flat area.

Liquid crystal display devices are widely used as a display device of smartphones, tablet computers, vehicle-navigation systems, etc. In general, a liquid crystal display device comprises a liquid crystal display panel and a planer illumination device (backlight device) overlaid on the rear surface of the liquid crystal display panel and illuminates the liquid crystal panel. The backlight device comprises a reflective layer, a light guide plate (light guide), an optical sheet (a prism sheet or a diffusion sheet), an LED as and a light source, etc. The reflective layer and the optical sheet are stacked one on another.
Meanwhile, such a liquid crystal display is proposed that the display screen is partially or entirely inclined or curved. In such a liquid crystal display device, the backlight device is also partially or entirely inclined or curved.
The viewing angle characteristics of a liquid crystal display device are dependent on the viewing angle characteristics of the backlight device. In many cases, the backlight device is adjusted so as to exhibit its maximum luminance in a normal direction to the light-emitting surface. That is, high-intensity light is emitted to a front direction in a flat region and to an oblique direction in an inclined region (curved region). Therefore, when the display screen is observed from the front direction, a significant difference in luminance is created between the flat region and the inclined region or curved region of the display screen, thereby degrading the display quality.
Here, when a high-haze diffusion sheet (in-plane uniform haze) is placed on the outermost surface of the emission face of the backlight device, frontal luminance of the inclined region increases and front luminance of the flat region decreases. In this manner, the difference in luminance between the flat region and the inclined region can be lessened to improve reduced, thereby improving the display quality. However, in this case, the luminance of the flat region decreases to degrade the commodity value itself.

Backlight device and liquid crystal display device comprising the same


The present invention relates to an elongate intravascular device adapted to be advanced through a vessel of a subject. The present invention further includes an antenna which is disposed on an inflatable member such that the antenna can be increased or decreased in size to more accurately tune the system in which it is employed.

The present invention relates generally to intravascular devices. More particularly, the present invention relates to antennae used in intravascular magnetic resonance imaging (MRI) devices. Intravascular imaging involves generating an image of tissue surrounding an intravascular device. Visualization involves generating an image of a catheter or other intravascular device on another image, or by itself, usually through localized signals from tissue immediately adjacent the device.
Imaging, visualization and tracking of catheters and other devices positioned within a body may be achieved by means of a magnetic resonance imaging (MRI) system. Typically, such a magnetic resonance imaging system may be comprised of a magnet, a pulsed magnetic field gradient generator, a transmitter for electromagnetic waves in radio frequency (RF), a radio frequency receiver, and a controller. In a common implementation, an antenna is disposed either on the device to be tracked or on a guidewire or catheter (commonly referred to as an MR catheter) used to assist in the delivery of the device to its destination. In one known implementation, the antenna comprises an electrically conductive coil that is coupled to a pair of elongated electrical conductors that are electrically insulated from each other and that together comprise a transmission line adapted to transmit the detected signal to the RF receiver.
In one embodiment, the coil is arranged in a solenoid configuration. The patient is placed into or proximate the magnet and the device is inserted into the patient. The magnetic resonance imaging system generates electromagnetic waves in radio frequency and magnetic field gradient pulses that are transmitted into the patient and that induce a resonant response signal from selected nuclear spins within the patient. This response signal induces current in the coil of electrically conductive wire attached to the device. The coil thus detects the nuclear spins in the vicinity of the coil. The transmission line transmits the detected response signal to the radio frequency receiver, which processes it and then stores it with the controller. This is repeated in three orthogonal directions. The gradients cause the frequency of the detected signal to be directly proportional to the position of the radio-frequency coil along each applied gradient.
The position of the radio frequency coil inside the patient may therefore be calculated by processing the data using Fourier transformations so that a positional picture of the coil is achieved. In one implementation this positional picture is superposed with a magnetic resonance image of the region of interest. This picture of the region may be taken and stored at the same time as the positional picture or at any earlier time.
In a coil-type antenna such as that described above, it is desirable that the impedance of the antenna coil substantially match the impedance of the transmission line. In traditional impedance matching of MRI coils, shunt-series or series shunt capacitor combinations suffice to tune the coil. In such traditional applications, the capacitors almost never pose a size constraint.
However, for intravascular coils, miniaturization of the tuning capacitors is necessary. Discrete components have been employed to construct matching and tuning circuits on intravascular devices. But such components are bulky and are not easily incorporated into the design of the device. Also, placement of the tuning capacitors away from the coil without a reduction in the signal-to-noise ratio (SNR) is desirable. It has been proposed to use open circuit stub transmission lines as a means of fabricating arbitrary or trimmable capacitors and to use short-circuited stubs as tuning inductors. Such probes are tuned by trimming the length of the coaxial cables. However, these circuits still result in a relatively large device that is not ideal for intravascular navigation. Also, the circuits require many connections and the fabrication process is relatively complex.
Another problem that arises with intravascular MRI antenna devices is that present day devices have a number of limitations. Such antennas include single loops, and saddle coils. Those antennas are resonant at some frequency, but that frequency is typically in the gigahertz range which is quite high. The antennae are typically small compared to the wavelength of the signal to be detected. Therefore, it is very difficult to tune a conventional coil antenna to optimize for that wavelength. In prior systems, the circuit was tuned using the discrete inductors and capacitors on the coil antenna mentioned above.
It can thus be seen that, often, it is desirable to make the antenna as large as possible. However, the diameter of the antenna is limited by the need to access the vessel. Simple expanding loops partially address this limitation, but they can be difficult to deploy in the vessel.
The present invention addresses at least one, and possibly more, of these, problems and offers advantages over the prior art.


A dual redundant electronic postage meter and associated method is provided for increasing the reliability of meter operation, comprising a first meter module including triple redundant memory technique/dual redundant means and dual redundant microprocessor means, a second meter module including triple redundant rechniques/dual redundant memory means and dual redundant microprocessor means, the dual redundant microprocessor means of the first meter module selectively communicating with a data entry means and external output means, and the dual redundant microprocessor means of the second meter module selectively communicating with the data entry means and the external output means, the second meter module being activiated in response to a failure in the operation of the first meter module.

The present invention relates to electronic postage meters, and more particularly to a dual redundant electronic postage meter for increasing the reliability of the meter operation.
Various electronic postage meter systems have been developed, see for example, the systems disclosed in U.S. Pat. No. 3,978,457 for Microcomputerized Electronic Postage Meter Systems, U.S. Pat. No. 3,938,095 for Computer Responsive Postage Meter, European Patent Application 80400603.9, filed May 5, 1980, for Electronic Postage Meter Having Improved Security and Fault Tolerance Features, U.S. Pat. No. 4,301,507, for Electronic Postage Meter Having Plural Computing Systems, and co-pending application Ser. No. 447,815, filed Dec. 8, 1982, for Stand-Alone Electronic Mailing Machine, now U.S. Pat. No. 4,579,054.
Generally electronic postage meters include some form of non-volatile memory capability to store critical postage accounting information. This information includes, for example, the amount of postage remaining in the meter for subsequent printing and the total amount of postage already printed by the meter. Other types of accounting or operating data may also be stored in the non-volatile memory, as desired.
However, conditions can occur in electronic postage meters where information stored in non-volatile memory may be lost. A total line power failure or fluctuation in voltage conditions can cause the microprocessor associated with the meter to operate erratically and either cause erasure of data or the writing of spurious data in the non-volatile memory. The erasure of data or the writing of spurious data in the non-volatile memory result in a loss of critical accounting information. Since the accounting data changes with the printing of postage and is not permanently stored elsewhere, there is no way to recapture or reconstruct the lost accounting information. Under such circumstances, it is possible that a user may suffer a loss of postage funds.
To minimize the likelihood of a loss of information stored in the non-volatile memory, various approaches have been adopted to insure the high reliability of electronic postage meters. It is known from aforementioned U.S. Pat. No. 3,978,457 and aforementioned co-pending application Ser. No. 447,815, now U.S. Pat. No. 4,579,054 to provide a microprocessor controlled electronic postage meter having memory architecture which includes a temporary storage memory for storing accounting data reflecting each meter transaction and a non-volatile memory to which the accounting data is transferred during the power down cycle of the meter.
Another approach for preserving the stored accounting data has been the use of redundant non-volatile memories. One such redundant memory system is disclosed in patent application Ser. No. 343,877, filed Jan. 29, 1982, in the name of Frank T. Check, Jr., and entitled Electronic Postage Meter Having Redundant Memory, now abandoned in favor of application Ser. No. 723,001, filed Apr. 15, 1985 which issued on Jan. 21, 1986 as U.S. Pat. No. 4,566,106. With such redundant memory system the two redundant non-volatile memories are interconnected with a microprocessor by way of completely separate data and address lines to eliminate error conditions. The data stored in each memory is the same, although the data may be stored in a different form in each memory, e.g., it may be coded. The data is applied to the memories simultaneously or sequentially at different times during the postage transactions.
Another redundant memory system is disclosed in the aforementioned European Patent Application 80400603.9. In such patent application, the same accounting data is written into each of the two non-volatile memories, designated BAMs, by updating the specific registers of the BAMs twice during each postage meter transaction, once in temporary form and once in permanent form to minimize the loss of accounting data during microprocessor failure.
Pending patent application Ser. No. 643,113 filed Aug. 22, 1984 and entitled, Electronic Postage Meter Having Multiple Non-Volatile Memories For Storing Different Historical Information Reflecting Postage Transactions, now U.S. Pat. No. 4,731,749, disclosed a first non-volatile memory having cumulative historical information of postage transactions written therein during the power down cycle of the meter and a second non-volatile memory having a greater data storage capacity than the first non-volatile memory for sequentially writing historical information regarding each trip cycle of the meter in a different address in the second non-volatile memory in real time as each postage transaction occurs so that two different records of historical information regarding the postage transactions are provided.
Pending patent application Ser. No. 643,112 filed on Aug. 22, 1984, and entitled Memory Address Location System For An Electronic Postage Meter Having Multiple Non-Volatile Memories, now U.S. Pat. No. 4,627,016, discloses a non-volatile memory for storing data in which data is used to locate the next memory address in which to write data in another non-volatile memory.
However, although the aforementioned systems have contributed to increased meter reliability, occasions may occur during meter operation when it is desirable to provide increased meter reliability. For example, if there is microprocessor failure and/or a failure of both NVMs.
This invention deals both with the primary function "accounting" arithmetic process, and data storage by providing for redundant microprocessors and memory means. The methodology described allows for detecting and locating source of critical process and data storage errors. Consequently dual redundancy within a module and dual redundant modules provides a significant increase in meter reliability.


Content capture and distribution systems and techniques are described. In an example, radio frequency signals that carry content are captured by one or more antennas of a content capture system. The content is converted from radio frequency signals the carry the content into an internet protocol format by the content capture system. The converted content is transmitted by the content capture system via a network transfer protocol (e.g., HTTP) for receipt by a content distribution system via a network. The converted content is configured by the content distribution system for streaming via a network streaming protocol. The content is then streamed by the content distribution system via the network using the network streaming protocol for receipt and rendering by at least one client device.

Users have access to an ever expanding variety of devices that may be used to consume content. For example, users have progressed from dedicated devices such as television and radio to mobile phones and tablet computers to consume content. To address this, content providers have also expanded the ways in which this content may be accessed.
An example of this is a content broadcast system. Conventional content broadcast systems typically relied on an "over the air" broadcast of content or a dedicated delivery system that requires specialized equipment (e.g., cable or satellite system) to broadcast content such as television and radio. In order to make this content available to users of mobile phones and tablets, techniques have then been developed by the content broadcast systems to stream the content over a network. However, these conventional techniques rely on complicated and expensive hardware systems that are specialized by the content broadcast systems to do so. Accordingly, this complexity and expense limits availability of these hardware systems and functionality made available by these systems.


A system and method to prevent eavesdropping by a device. An anti-eavesdrop component is installed on the device. The anti-eavesdrop component is configured to actively prevent the device from capturing audio from the environment. In response to installing the anti-eavesdrop component, the device recognizes the anti-eavesdrop component as a primary audio input for the device. The anti-eavesdrop component then proceeds to block the device from capturing outside audio by injecting noise or otherwise interfering with the primary audio input.

The present disclosure relates to preventing or limiting the ability for a device to eavesdrop on communications occurring around the device when the user is not using the device.
Electronic snooping or surveillance occurs through many devices that consumers have is fairly common. Many devices are actively listening for audio input from the user to enable particular features of the device. As the device is waiting for a specific audio input the device is constantly listening and capturing audio from the surrounding environment. This captured audio can be used by the device for legitimate purposes or for illicit purposes.

International Business Machines Corporation


By controlling reverse rates among mobile stations to reduce reverse-link interference, reverse-link throughput can be increased.

We use the following acronyms in our discussion:
We use the following notations in our discussion.
FIG. 1 shows a general configuration of cellular wireless communication systems. A large geographic area is divided into cells 10. Each cell can be further divided into sectors 12. Typically three sectors per cell are used as shown in the figure. We will use the term sector even when there is only one sector per cell. In each cell, a BS 14, 20, 22 serves three sectors and communicates with multiple MS""s 16, 18 in its cell.
High Data Rate (HDR) is an emerging mobile wireless access technology that enables personal broadband Internet services which can be accessed from anywhere, anytime. Developed by Qualcomm, HDR is a new air interface optimized for IP packet data services. HDR can deliver a shared forward link transmission rate of up to 2.4576 Mbit/s per sector using only (1xc3x97) 1.25 MHz of spectrum. HDR has been adopted by TIA as a new standard in the CDMA2000 family, an EVolution of the current 1xc3x97RTT standard for high-speed data-only (DO) services, formally referred to as 1xc3x97EV-DO or IS-856.
IS-856 defines AN, AT, and sector as follows:
Access Network (AN): The network equipment providing data connectivity between a packet switched data network (typically the Internet) and the access terminals. An access network is equivalent to a base station in the CDMA-2000 standard.
Access Terminal (AT): A device providing data connectivity to a user. An access terminal may be connected to a computing device such as a laptop personal computer or it may be a self-contained data device such as a personal digital assistant. An access terminal is equivalent to a mobile station in the CDMA-2000 standard.
Sector: The part of the access network that provides one CDMA channel.
We will use BS and AN interchangeably and MS and AT interchangeably.
In HDR, the forward-link channel is time-shared among MS""s. Actual forward throughput becomes smaller than the instantaneous rates if there are more than one MS.
The MS periodically monitors the quality of its forward channels by measuring the forward-link SIR values from several sectors. The MS chooses the sector among active sectors whose SIR is the highest and calculates the maximum possible forward-link rate supported at this SIR. The MS then sends a DRC value in every slot (one slot is 1.66 msec) that indicates this rate to the BS. The following table shows the DRC value and the corresponding rate in Kbps. Packet length shows how many slots a forward packet needs at each rate.
In HDR, the reverse link (from MS to BS) can support bit rates 9.6, 19.2, 38.4, 76.8, and 153.6 Kbps in a 1.25 MHz spectrum (no overlap with the forward-link spectrum). Since the reverse link is shared using CDMA, these are the actual rates each MS can get.
A MS can communicate with several sectors. A MS is in soft handoff if decoding of the reverse packet is done at several sectors and an error-free frame, if any, is finally chosen. A MS is in softer handoff, if several sectors in the same cell jointly decode the reverse packet.
Due to the unpredictable nature of the reverse traffic and delay, it is difficult to schedule individual reverse traffic together at the BS. As we will show later, there is a limit on the aggregate reverse rate in each sector at which MS""s can send data reliably. Therefore, it is important to be able to control the reverse rate of each MS so that their aggregate rate rarely exceed the limit. We briefly describe how this is done in HDR.
In HDR, there are four variables for reverse rate control, i.e., MaxRate, CurrentRate, CombindedBusyBit, and CurrentRateLimit. CurrentRate is the actual rate at which a MS sent data last time. The BS can send broadcast (to all MS""s in the sector) or unicast (to a specific MS) RateLimit messages. After receiving the RateLimit message (unicast or broadcast), the MS sets its CurrentRateLimit equal to the RateLimit value. CurrentRateLimit is initially 9.6 Kbps.
The BS can send another broadcast control signal, RAB (reverse activity bit), to all active MS""s. The MS collects all RAB""s from active base stations and determines CombinedBusyBit. The CombinedBusyBit is 1 if any of these RAB""s is 1 and is 0 otherwise. The MS then computes the MaxRate with a certain probability depending on the CombinedBusyBit. This probability is a function of both the CurrentRate and the CombinedBusyBit. The MS then chooses a rate that does not exceed either of MaxRate or CurrentRateLimit. The rate is also limited by the transmission power of the MS (in general more power is needed for transmitting at a higher rate). If the payload size is small enough to be transmitted using a lower rate, then the MS choose the lower rate. The following summarizes the reverse rate variables:
CurrentRateLimit
1. initially 9.6 Kbps
2. after receiving broadcast or unicast RateLimit message, an MS updates it as follows:
a. if the RateLimit less than =CurrentRateLimit, set CurrentRateLimit=RateLimit immediately.
b. if the RateLimit greater than CurrentRateLimit, set CurrentRateLimit=RateLimit after one frame (16 slots).
CombinedBusyBit
1 if and only if any RAB is 1 from any sector.
MaxRate
2.0*CurrentRate if CombinedBusyBit=0 and with probability x.
0.5*CurrentRate if CombinedBusyBit=1 and with probability x.
MaxRate cannot be set to 0 in any case.
MaxRate cannot exceed 153.6 Kbps.
MS selects a transmission rate (becomes CurrentRate) such that
1. rate less than =MaxRate
2. rate less than =CurrentRateLimit
3. rate less than =highest rate that can be accommodated by the transmission power
4. rate less than =highest rate such that the number of minimum payload bits is less than the number of bits to send.
Default values of the transition probability x are:
In general, in one aspect, the invention features a method that includes (a) at a mobile wireless communication device operating in a cell, transmitting data to sectors, and (b) at the base station controlling the reverse data rate of the mobile device based on an estimated amount of interference the mobile device is causing to other sectors. Implementations of the invention may include one or more of the following features. The estimated amount of interference is based on a forward-link SIR for the mobile device. The forward-link SIR is averaged over a period of time. The estimated amount of interference is based on pilot power from the mobile device received at the base station or on total power received from the mobile device at the base station or on the mobile device""s request forward-link data rate. The request data rate is averaged over a certain period of time. The reverse rate of the mobile device is set by the base station. The reverse rate is set as a target rate based on the queue status of the mobile device or on the status of the sector in which the mobile device is operating. The status of the sector comprises a number of mobile devices or a reverse rate of other devices operating in the sector. The reverse rate of the mobile device is set by the mobile device. The reverse rate is set based on a determined rate limit. The rate limit is communicated to the mobile device from the base station. The reverse rate is limited by sending rate control bits from the base station to the mobile device. The mobile device sets a value of MaxRate according to a message from the base station, the MaxRate being dependent on the current rate of the mobile device and given transition probabilities. The mobile device sets a MaxRate deterministically. The aggregate rate from all mobile devices in all sectors is maximized. The rate of each mobile device is restricted by a condition. The condition includes fairness among the mobile devices.
In general, in another aspect, the invention features a method that includes (a) generating one or more reverse rate control bit or bits for each of several mobile devices operating in a sector of a cell, and controlling the reverse rates of the respective mobile devices based on the reveres rate control bits.
In general, in another aspect, the invention features a method that includes (a) at a mobile wireless communication device operating in a sector of a cell, transmitting data to the base station in the sector, and (b) controlling its reverse data rate based on an estimated amount of interference the mobile device is causing to base stations in other sectors. Implementations of the invention may include one or more of the following features. The estimated amount of interference is based on its forward-link SIR. The estimated amount of interference is based on its forward-link rate. The estimated amount of interference is based on its request forward-link data rate. The estimated amount of interference is based on the received power from the base station. The reverse rate is limited by a command from the base station.
Other advantages and features will become apparent from the following description and from the claims.

Enhanced reverse-link rate control in wireless communication


A user interface display method of a terminal includes receiving, by the terminal, a first operation from a user to unlock the terminal when a screen of the terminal is off or the terminal displays a first interface, where the first interface is a lock screen of the terminal, displaying, by the terminal, a third user interface when the first operation meets a preset unlock condition and when the user continues to operate the terminal after entering the first operation, receiving, by the terminal in the third user interface, a second operation from the user, and executing a function corresponding to the second operation.

In the prior art, as shown in FIG. 1, to prevent a misoperation of a user or protect user privacy, a terminal usually displays a lock screen 1 after a screen of the terminal is lit up, and the terminal is in a lock screen state. If the terminal is not unlocked, the user cannot enter an unlocked interface to use a complete function of the terminal. Only after unlocking, the user can use the complete function of the terminal, for example, use a system function of the terminal or an installed application program ("application" or "APP" for short). The user can unlock the terminal in a plurality of manners, such as sliding to unlock, fingerprint unlocking, iris unlocking, and facial recognition unlocking. For example, referring to FIG. 3A, the terminal has a rear-facing fingerprint module 3. As shown in FIG. 3B, in the lock screen 1, the user needs to perform at least one operation of touching or pressing the rear-facing fingerprint module 3 for unlocking. As shown in FIG. 3C and FIG. 3D, after unlocking, the terminal displays an unlocked interface. In this case, the user further needs to perform at least another operation to trigger the terminal to execute a function of an operating system. For example, the user needs to tap an icon of an application, for example, WeChat, in the unlocked interface to open the application.
In addition, some terminals provide, in lock screens, some application quick entries that do not relate to user privacy and security, for example, provide a shortcut of "Camera" (for example, an icon of "Camera") in the lock screens. As shown in FIG. 4A, FIG. 4B, and FIG. 4C, the user can tap the shortcut, or touch and hold the shortcut and drag the shortcut along a preset direction by a distance, to open the "Camera" application and use a photographing function of "Camera". In this case, the user can use the "Camera" application, but cannot use the complete function of the terminal within rights of the user because the operating system of the terminal is not unlocked. After the "Camera" application entered by using this shortcut is exited, the terminal still keeps a lock screen state. For example, the terminal returns to the lock screen 1, and prompts the user to unlock the terminal.
It can be learned from the foregoing description that in the prior art, a user cannot use a continuous operation to both unlock a screen of a terminal and execute a function (for example, open an application), and therefore the user has poor operation experience.

User interface display method of terminal, and terminal


The present invention relates to a method of repairing a fiber composite solid member having a locally deteriorated surface area, such as having cracks or creases. The solid member may e.g. be a mold for the manufacturing of wind turbine blades or such blades. The method comprises machining a surface section comprising the locally deteriorated surface area in order to obtain a recess having a predefined depth and circumferential shape, placing a repair patch having a predefined thickness and circumferential shape matching the recess in the recess, and fastening the repair patch to the solid member by use of a binder material. At least some of the elastic and thermal properties of the repair patch and the binder material are so that after fastening, the repair patch and the binder material in combination have elastic and thermal properties which are substantially the same as the corresponding properties of the surface section before machining.

Fibre reinforced resin composites are used in the wind turbine industry e.g. for rotor blades. The manufacturing process typically comprises use of a mould to obtain the desired shape of the blades. A known problem is that the mould occasionally gets damaged e.g. due to small surface parts being torn off when a blade is removed from the mould after manufacturing, or due to accidental indents, cracks or scratches obtained during handling of the mould. Since such a mould is typically expensive and takes up much storage space, the number of moulds at a manufacturing site is kept to a minimum, and no or very few spare moulds may be available if some are taken out of the production line for maintenance. A known method of repairing a deteriorated surface area of such a mould is by grinding followed by manual application of repair material to obtain a repaired surface having a geometry and mechanical and thermal properties as close to the original as possible. The repaired area is typically made to have a larger thickness than the final one, so that the desired surface quality is obtained by removing excess material by grinding and polishing. Such a repair process is difficult to carry out, especially on surfaces having double curvature. The result of a repair process is therefore very dependent on the skills of the person carrying out the repair, and it is difficult to ensure that a desired quality is obtained.
Hence, an improved method of repairing a fibre composite solid member, such as a mould for manufacturing of wind turbine blades, would be advantageous, and in particular a more efficient and/or reliable repair method would be advantageous.

Method of repairing a fibre composite solid member


The field of the invention is that of articles adhesive to the skin for medical or paramedical use. The invention relates to an article adhesive to the skin.

1. Field of the Invention
The field of the invention is that of skin-adhesive articles for medical or paramedical use.
2. Description of Related Art
It is very difficult to adhere materials to low-surface-energy plastics films such as films made of polyester or polyurethane. Copiously described in the prior art are adhesion primers for silicone gels to low-surface-energy plastics films. Typically, the methylhydrogensiloxane polymer solutions produce satisfactory adhesion of the silicone gels to the polyurethane films for cushions and mattresses for preventing bedsores or for external mammary prostheses. In these applications, the silicone gel is completely integrated in a polyurethane film pouch in such a way that no contact is possible between the gel and the exterior.
When, by contrast, tacky silicone gels are used as adhesives for producing, for example, adhesive strips for dressings, the devices for attaching stoma bags, or in certain apparel applications, the methylhydrogensiloxane polymer solutions produce satisfactory adhesion of the silicone gels to the polyurethane films, but the tack of the gels is lost or greatly reduced, such that the adhesive strip no longer exhibits the required performance, this being a problem which may rule it out for this type of application.


A developing unit which includes a conveying shaft; a developing conveying portion conveying a developer in an axial direction as the conveying shaft rotates; a discharge opening discharging the developer from the inner wall surface; an accumulating chamber accumulating the discharged developer; and an opening/closing member opening and closing the discharge opening due to its own weight as the rotating body rotates, and being in an open state at the developing position, an opening/closing fulcrum of the opening/closing member being at a lower end portion of the opening/closing member at the developing position, the developing unit being held at a rotating body, and successively being made to oppose a developing position of an image carrier due to rotation of the rotating body.

1. Technical Field
The present invention relates to a developing unit.
2. Related Art
In the trickle method, a developer, in which toner and carrier are mixed-together in advance, is housed in a developer cartridge, and, simultaneously with the supplying of the toner from the developer cartridge to a developing unit, new carrier also is supplied bit-by-bit. Because the amount of the developer within the developing unit increases at this time, when an amount which is greater than or equal to a given amount has accumulated, the excess developer is discharged to the exterior of the developing unit. Accordingly, the developer is stable and does not deteriorate, i.e., the charge amount thereof does not fall to less than or equal to a predetermined value.

Developing unit with developer opening/closing member


An optical modulation device including: bias power supplies that output a signal having a bias voltage corresponding to the null point of an optical modulation unit to the optical modulation unit; and synchronous detection circuits that determine whether an intensity of a QAM signal at a drift non-occurrence time where no drift occurs in the bias voltage becomes larger or smaller than the intensity of the QAM signal at a drift occurrence time where a drift occurs in the bias voltage, adjust the bias voltage to maximize the intensity of the QAM signal when determining that the intensity of the QAM signal at the drift non-occurrence time becomes larger than the intensity of the QAM signal at the drift occurrence time, and adjust the bias voltage to minimize the intensity of the QAM signal when determining that the intensity of the QAM signal at the drift non-occurrence time becomes smaller than the intensity of the QAM signal at the drift occurrence time.

1. Field of the Disclosure
The present disclosure relates to an automatic bias voltage control of an optical modulation device for use in multi Quadrature Amplitude Modulation (QAM). In particular, the present disclosure is suitable for the automatic bias voltage control of an optical modulation device that sends a quaternary or larger value QAM signal.
2. Discussion of the Background Art
As a transmission code for use in an optical transmission system, a QAM signal, capable of sending a large amount of optical signals at a low symbol rate has been paid attention. The simplest QAM is quaternary QAM and called Quadrature Phase Shift Keying (QPSK). The present disclosure is applicable to any multi-QAM modulators including QPSK, however for simplicity, a description will be mainly given of a 16 QAM system in the present disclosure. Here, some symbols have a bar placed on characters in figures, however   placed before the characters indicates that the symbols have the bar on the characters in the specification.
FIG. 1 shows the configuration of an optical modulation device in the related art. A continuous optical signal input to an IQ optical modulator M is divided into two signals by a first optical coupler 1 and input to the first and second optical modulation units which are an I-component optical modulation unit 2 and a Q-component optical modulation unit 3 (hereinafter first and second optical modulation units 2 and 3, respectively). The first and second optical modulation units 2 and 3 are generally composed of Mach-Zehnder Interferometer (MZI) type optical modulators and have the function of relatively changing an optical phase and optical intensity corresponding to the logic of the first quaternary data signals Data1 and  Data1 and that of second quaternary data signals Data2 and  Data2. Here, the relationship between the optical phase and optical intensity with respect to the four values of the data signals will be described below. In addition, the first and second bias voltages applied to the first and second optical modulation units 2 and 3, respectively, will be described below.
After the addition of a phase difference θ3 by an optical phase shifter 4 having an orthogonal bias electrode 101 to which a third bias voltage to be described below is applied, the outputs of the first and second optical modulation units 2 and 3 are multiplexed by the second optical coupler 5 and output as a 16 optical QAM signal. If θ3 is ±π/2, an ideal waveform can be obtained. It is equivalent to ¼ of a carrier wavelength, and general wavelength is of the order of micrometer, so then the adjustment must be performed really precisely. In addition, since the optical quality of an optical QAM signal is sensitive to an error in the optical phase shifter 4, it is really important to adjust the amount of phase shift induced by the optical phase shifter 4 to an appropriate value.
In general, this adjustment is made in such a manner that a third bias voltage (also called an orthogonal bias voltage) Vbias3 supplied from a third bias power supply 10 to the optical phase shifter 4 is adjusted. The optical phase shifter 4 is arranged on the rear stage of the second optical modulation unit 3 in FIG. 1, however it may be arranged on the rear stage of the first optical modulation unit 2, arranged on those of both the first and second optical modulation units 2 and 3, or arranged on the front stage. Hereinafter, for simplicity, it is assumed that the optical phase shifter 4 is arranged only on the rear stage of the second optical modulation unit 3.
Next, a description will be given of the relationship between the optical phase and optical intensity in the outputs of the first and second optical modulation units 2 and 3 with respect to the four values of the first and second quaternary data signals. As described above, it is general to use MZI type optical modulators as the first and second optical modulation units 2 and 3. The first and second optical modulation units 2 and 3 are driven by the first and second quaternary data signals, respectively. Each of these data signals is a quaternary NRZ Non Return-to-Zero (NRZ) signal. The first driving amplifier 6 amplifies the first quaternary data signal into the two complementary signals, and generates Data1 and  Data1. The second driving amplifier 7 amplifies the second quaternary data signal into the two complementary signals, and generates Data2 and  Data2.
The respective amplified quaternary data signals Data1 and  Data1 are applied to the two arms of the first optical modulation unit 2 via a first driving electrode 61 to generate a phase shift ±φ1. The respective amplified quaternary data signals Data2 and  Data2 are applied to the two arms of the second optical modulation unit 3 via a second driving electrode 71 to generate a phase shift ±φ2. The values of the phase delays φ1 and φ2 change with the four values of the respective data signals. In addition, DC voltages (data bias voltages) Vbias1 and V′bias1 are generated by a first bias power supply 8, and optical phase shifts +θ1 and −θ′1 are further added via a first bias electrode 81. Moreover, DC voltages (data bias voltages) Vbias2 and V′bias2 are generated by a second bias power supply 9, and optical phase shifts +θ2 and −θ′2 are further added via a second bias electrode 91.
Next, the expression of the various voltages described above is defined as follows. The four signal levels of a differential signal (Data1-  Data1) generated by the first driving amplifier 6 are expressed as V0, V1, −V1, and −V0, and it is assumed that V0>V1>−V1>−V0 is established. Since the optical characteristics of the first optical modulation unit 2 are generally the same as those of the second optical modulation unit 3, the four signal levels of a differential signal (Data2-  Data2) generated by the second driving amplifier 7 are also expressed as V0, V1, −V1, and −V0.
Vbias1, V′bias1, Vbias2, and V′bias2 select the null points of the first and second optical modulation units 2 and 3. In other words, the output light of the first and second optical modulation units 2 and 3 is set to extinguish when the differential voltages of the signals generated by the first and second driving amplifiers 6 and 7 are 0. In addition, the maximum amplitudes of the differential outputs of the first and second driving amplifiers 6 and 7 are set so as not to exceed twice the half wavelength voltages Vπ of the first and second optical modulation units 2 and 3. Accordingly, 2Vπ≧V0−(−V0)=2V0 is established.
Here, a description will be given, with reference to FIG. 1, of the half wavelength voltage Vπ of the first optical modulation unit 2. The first optical modulation unit 2 is a MZI type modulator and incorporates two waveguides. It is assumed that a data bias is adjusted to extinguish the output of the first optical modulation unit 2 when both of the voltages Data1 and  Data1 applied to the two waveguides are 0. In general, complementary driving signals are applied to the two waveguides, and 2Vx is called the half wavelength voltage Vπ of the first optical modulation unit 2 if the optical output of the first optical modulation unit 2 reaches maximum intensity under Data1=Vx and  Data1=−Vx. The optical output of the first optical modulation unit 2 reaches the maximum intensity even under Data1=−Vx and  Data1=Vx, however the optical phase of the optical output in this case is made different by π compared with the former example. Since the first optical modulation unit 2 changes an optical phase by making use of the property, each of Data1 and  Data1 is set to have an amplitude of 2Vx=Vπ at the maximum and (Data1-  Data1) is set to have an amplitude of 2Vπ at the maximum. The second optical modulation unit 3 is configured in the same manner as the first optical modulation unit 2.
Here, in the IQ optical modulator M shown in FIG. 1, each of the driving signal electrodes is configured to apply positive and negative complementary voltages to the two waveguides, and thus four electrodes in total exist. The IQ optical modulator M of this type is called a dual drive type. On the other hand, a single drive type IQ optical modulator M has only two driving signal electrodes. In such a configuration, the first driving electrode 61 simultaneously applies electric fields to the two waveguides inside the first optical modulation unit 2, and the second driving electrode 71 simultaneously applies electric fields to the two waveguides inside the second optical modulation unit 3. With the anisotropy of the four waveguides, the single drive type IQ optical modulator M can realize the same function as that of the dual drive type. Also in this configuration, the quaternary data signals applied to the first and second driving electrodes 61 and 71 are the four voltages V0, V1, −V1, and −V0, and the amplitude of each of the driving signals is set so as not to exceed twice the half wavelength voltage Vπ.
FIG. 2 shows the characteristics of the optical modulation device in a case in which no bias drift occurs. FIG. 2 shows the relationship between the electric field E1 of the output light of the first optical modulation unit 2 and V0, V1, −V1, −V0, and Vbias1, and the relationship between the electric field E2 of the output light of the second optical modulation unit 3 and V0, V1, −V1, −V0, and Vbias2 is also expressed just like FIG. 2. When the sum of the potentials V0, V1, −V1, and −V0 of a driving signal and the data bias Vbias1 is shown in the horizontal axis and the electric field E1 of the output light is shown in the vertical axis, a sine wave is drawn. When the optimum data bias is applied, V0, V1, −V1, and −V0 are arranged symmetrically to the null point and the electric fields E11, E12, E13, and E14 of the output light generated by V0, V1, −V1, and −V0 are also arranged symmetrically to the 0 level.
FIG. 3 shows a constellation in a case in which no bias drift occurs. Since θ3=π/2 is established when optimum Vbias3 is applied to the optical phase shifter 4 and the optical phase of the output light of the first optical modulation unit 2 and that of the second optical modulation unit 3 are kept to be orthogonal to each other, the constellation of the output light of the IQ optical modulator M is one having a lattice pattern as shown in FIG. 3. Here, it is important that the respective symbols of the constellation are arranged symmetrically to the origin. This symmetry is a property common to QAM in addition to 16QAM. Here, since E1 and E2 are orthogonal to each other when θ3=π/2 is kept, an In-Phase component and a Quadrarure-Phase component are sometimes briefly called an I-component and a Q-component, respectively.
The optical power Ptotal of a 16QAM signal is proportional to the sum of the square of the electric field of each of the symbols of the constellation. Ptotal is expressed by Equation 1.Ptotal∝Σ(|E1K|2+|E2L|2)  (Equation 1)
Here, K and L have the sum of 1 to 4.
In a case in which Vbias1 and Vbias2 are kept at optimum values even if a bias drift occurs in Vbias3 and θ3 has a value different from π/2, the total of the optical power Ptotal does not change as described in detail in Non-Patent Literature 1. Therefore, it is relatively difficult to detect a drift occurring in Vbias3. However, it becomes possible to detect a drift occurring in Vbias3 with the application of dithering to Vbias1 and Vbias2 using the technique of asymmetric bias dithering described in Non-Patent Literature 1.
Next, consideration will be given to a case in which a bias drift occurs in the data bias Vbias1 or Vbias2. In the case of quaternary QAM, i.e., a QPSK signal, since the optical power of modulation light immediately decreases after a bias drift occurs in the data bias Vbias1 or Vbias2, it is relatively easy to detect the bias drift occurring in the data bias Vbias1 or Vbias2. Thus, it becomes possible to detect and correct bias drifts occurring in all the Vbias1, Vbias2, and Vbias3 of the QPSK modulator with the technique of the asymmetric bias dithering described above.

Optical modulation device and bias voltage control method

Nippon Telegraph and Telephone Corporation


Presenting an image of a scene may include capturing an image of a scene by a camera of an electronic device, wherein the electronic device comprises the camera and a display, and wherein the camera and the display have a first spatial relationship, determining a second spatial relationship between a viewpoint and the display of the electronic device, warping the image to obtain an image of a first portion of the scene based on the first spatial relationship and the second spatial relationship, and presenting the warped image on the display, wherein, from the viewpoint, the image of the first portion of the scene is substantially contiguous with a second portion of the scene visible outside an edge of the electronic device.

This disclosure relates generally to the field of digital image processing, and more specifically to the field of providing a camera-based transparent display.
Many multifunctional electronic devices, such as smart phones and tablets, include a camera and display device that allow a user to utilize the display to preview and view images captured by the camera. When a traditional multifunctional device is used in preview mode, the image displayed on the screen represents an image from the camera's point of view. Therefore, when a user holds the device in front of a scene and views the display, the image on the screen does not line up with the scene behind it. That is, the user's point of view differs from the point of view of the lens capturing the image, leading to a disconnect between the user's point of view and the real environment. That is, to the user, the image may appear in the wrong position and the wrong scale.


A method and apparatus to enable configuring of a management frame priority and security type. The method and the apparatus may set a priority level and a transmission data rate of a management frame. The apparatus includes a memory including a priority queue for each management frame and a transmitter to transmit said management frame according to the priority queue of said frame.

Wireless local area network (WLAN) standards, for the example IEEE 802.11 standard family, may define transmitting of management frames (such as, for example a beacon) at a highest data frame priority, and may define at the lowest data rates those transmitting criteria are applied to all management frame uniformly. Furthermore, the IEEE 802.11 standard family defines a plethora of management frames (e.g. IEEE 802.11k Radio Resource Measurements and IEEE 802.11v Wireless Network Management) which may negatively impact WLAN enterprise traffic characteristics. Traffic analysis indicates that in current infrastructure of some WLANs, over 25% of bandwidth is consumed by management frame traffic, which reduces the overall WLAN throughput. This is especially applicable for voice applications over the wireless medium where excessive management frame traffic may decrease available admission capacity of the WLAN.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

Apparatus, system and method of prioritizing a management frame of a wireless network