A method is provided for controlling charging of an energy storage system in a vehicle including an electric machine which is arranged for propulsion of the vehicle. The method includes initiating the charging upon connection of the energy storage system to an external power supply via connector elements; and transmitting, between the vehicle and the external power supply, a control signal including data related to the charging by a wireless transmission link. The method furthermore includes evaluating whether the control signal is received; and terminating the charging in the event that the control signal is not received. An arrangement for controlling charging of an energy storage system is also provided.

The present invention relates to a method for controlling charging of an energy storage system in a vehicle comprising an electric machine which is arranged for propulsion of said vehicle, said method comprising: initiating said charging upon connection of said energy storage system to an external power supply via connector elements; and transmitting, between said vehicle and said external power supply, a control signal comprising data related to said charging by means of a wireless transmission link.
The present invention also relates to an arrangement for controlling charging of an energy storage system in a vehicle comprising an electric machine which is arranged for propulsion of said vehicle, said arrangement comprising an external power supply arranged for initiating charging upon connection of said energy storage system to the external power supply via connector elements, and a transmitter unit and receiver unit arranged for wirelessly transmitting a control signal comprising data related to said charging between said vehicle and said external power supply.
In the field of vehicles, there is a steady increase in research and development related to propulsion of vehicles with alternative power sources, i.e. power sources being used as alternatives to conventional internal combustion engines.
An internal combustion engine, for example in the form of a gasoline engine or a diesel engine, offers high efficiency with relatively low fuel consumption. However, environmental concerns have led to an increase in development of more environmental-friendly power sources for vehicles. In particular, the development of electrically operated vehicles has emerged as a promising alternative.
Today, there exist various types of vehicle propulsion systems comprising electric machines. For example, a vehicle can be operated by means of an electric machine solely, or by means of an arrangement comprising both an electric machine and an internal combustion engine. The latter alternative is often referred to as a hybrid vehicle (HEV), and can for example be utilized in a manner in which an internal combustion engine is used for operating the vehicle while driving outside urban areas whereas the electric machine can be used in urban areas or in environments in which there is a need to limit the discharge of harmful pollutants such as carbon monoxide and oxides of nitrogen.
The technology involved in electrically operated vehicles is closely related to the development of electrical energy storage systems, for example in the form of battery-related technology for vehicles. Today's electrical energy storage systems for vehicles may comprise a set of rechargeable battery cells which, together with control circuits, forms a unit which is arranged in a vehicle and which is configured for operating an electric machine. A hybrid vehicle is also often arranged so that the energy storage system is charged during braking, by means of a process known as regenerative braking.
A vehicle being operated by means of an internal combustion engine and an electric machine supplied with power from a rechargeable electrical energy storage system is sometimes referred to as a plug-in hybrid electric vehicle (PHEV). A plug-in hybrid electric vehicle uses an energy storage system with rechargeable batteries or another suitable energy source which can be restored into a condition involving a full charge through a connection to an external electric power supply.
The external power supply can be in the form of the common electric grid power system which can be accessed via a conventional power cord, or can be in the form of other arrangements depending on the vehicles involved and the power need for the recharging process. In case of vehicles in the form of buses or heavy transport vehicles, more powerful charging devices and procedures are normally needed as compared with smaller cars and similar vehicles.
A challenge for today's electrically driven vehicles, in particular heavy vehicles such as buses and trucks, is that a high amount of energy must be charged into the energy storage system in a relatively short time in order to optimize the vehicle's range of driving. For this reason, the actual charging of the energy storage system is suitably implemented through a process in which a control unit on the vehicle requests a charging to be carried out by means of an external electric power supply. This is carried out after the energy storage system and the external power supply have been electrically connected by means of suitable connector elements. In such cases, a so-called pantograph can for example be used to connect the onboard energy storage system with an external power supply.
The recharging of an energy storage system in a bus, for example, may involve charging an electrical energy storage system comprising a number of battery cells with a charging current which is of the magnitude 200 A, whereas the electrical energy storage system may have a voltage of the magnitude of 600 V. Such a charging procedure involves certain safety risks, for example if the battery cells are exposed to excessive heat, impact or overcharging, or if electrically conducting parts of the energy storage system or charging system come into contact with persons. A particular situation in which there may arise a safety risk is if the vehicle should move out of its position during the charging procedure. Consequently, there are demands for protection of persons and material in the event of any error which may occur during charging.
Also, the battery cells of the energy storage system are both very expensive and also very sensitive to overcharging. This also means that overcharging of the energy storage system must not occur.
Consequently, there is a demand for methods and arrangements by means of which the charging of an energy storage system in a hybrid vehicle can be carried out in a secure manner, in particular in the event that unexpected changes in certain parameters and conditions (such as the position of the vehicle, the temperature of the energy storage system etc.) should arise. In such situations, it is important that the charging procedure does not lead to any safety risks.
The patent document US 2011/078092 discloses a method and apparatus for controlling a battery. The apparatus is arranged for establishing a wireless communication link in order to transmit data related to battery charge management. The apparatus also comprises a controller arranged for generating a control signal comprising information related to a target capacity of an electric vehicle battery.
Even though the above-mentioned solution according to US 2011/078092 offers a reliable solution for controlling the charging procedure in a vehicle with electric propulsion, there are still further demands for a sufficiently high level of safety for persons and for electric equipment during charging of an energy storage system, in particular in hybrid vehicles.
It is desirable to provide an improved method and arrangement by means of which the above-mentioned problems can be overcome and, in particular, by means of which a charging procedure can be monitored and controlled in the event that any unexpected errors should occur.
In accordance with an aspect of the invention, a method is provided for controlling charging of an energy storage system in a vehicle comprising an electric machine which is arranged for propulsion of said vehicle, said method comprising: initiating said charging upon connection of said energy storage system to an external power supply via connector elements; and transmitting, between said vehicle and said external power supply, a control signal comprising data related to said charging by means of a wireless transmission link. The method furthermore comprises:
evaluating whether said control signal is received; and terminating said charging in the event that said control signal is not received.
By means of a method as defined above, there is provided a method for charging an energy storage system in which a very high degree of safety is obtained. In particular, the fact that the invention comprises an evaluation whether the control signal is received or not allows the charging to be discontinued in a number of situations which can be perceived as being a risk as regards personal safety or damage to goods and objects.
Preferably, the control signal is transmitted from said vehicle to said external power supply, wherein said evaluating is carried out in the external power supply.
Furthermore, the control signal can be in the form of a modulated radio signal which is transmitted by means of a radio transmitter unit in the vehicle; wherein the control signal is received by means of a radio receiver unit in the external power supply. The radio signal can be transmitted and received by means of a wireless short-range radio network.
The control signal is provided in different forms, suitably in at least one of the following forms:
i) a generally continuous signal having a predetermined frequency and/or amplitude;
ii) a generally pulse-shaped signal with a predetermined pulse width and/or amplitude; and
iii) a repeated sequence comprising a signal as defined in i) or ii) and a pause of predetermined length.
Consequently, the control signal can be designed in a number of ways depending on the type of equipment used as a receiving unit, in order to carry out the detection of the control signal in a simple and efficient manner.
Also, the control signal is configured so as to contain certain data related to the charging of the energy storage system, in particular so that the control signal can be used to terminate the charging depending on the current values of at least one of the following parameters:
i) the current position of said vehicle;
ii) any occurring movement of said vehicle;
iii) the identity of said vehicle;
iv) the electrical isolation of said electrical storage system;
v) the status of contact elements of high voltage components of said vehicle;
vi) the charging current;
vii) the charging voltage; and
viii) the temperature of said connector elements.
By using input in the form of at least one of the above-mentioned parameters, the transmission of the control signal can be used to terminate the charging process in the event that said at least one parameter deviates from a predetermined value.
Furthermore, according to an embodiment, the invention can be arranged to generate an alarm signal in the event that said charging is terminated due to the control signal not being received.
According to a particular embodiment, the invention can be arranged for providing a predetermined modulation of said control signal; and evaluating whether the charging supplied to said energy storage system comprises said predetermined modulation; and, if this is not the case, indicating that said charging of the energy storage system is erroneous. Suitably, the invention may comprise disconnecting the energy storage system from the external power supply in the event that said charging is terminated.
The above-mentioned problem is also solved by means of an arrangement for controlling charging of an energy storage system in a vehicle comprising an electric machine which is arranged for propulsion of said vehicle, said arrangement comprising an external power supply arranged for initiating charging upon connection of said energy storage system to the external power supply via connector elements, and a transmitter unit and receiver unit arranged for wirelessly transmitting a control signal comprising data related to said charging between said vehicle and said external power supply. The arrangement is configured for evaluating whether said control signal is received in said receiver unit and for terminating said charging in the event that said control signal is not received.
An advantage with the invention is that it provides a fast and reliable transfer of information related to commands for shutting down the charging of the energy storage system. This is provided by transmission, in a wireless manner, of a control signal in the form of a radio communication carrier wave.
If the carrier wave is not received in a proper manner, due to a high voltage-related error having been discovered in the vehicle, or due to any occurring interference or disturbance on the communication link, this should be interpreted as a command to terminate the charging of the energy storage system.
The invention can be implemented in a manner in which the control signal is transmitted from the vehicle to the external power supply or, inversely, from the external power supply to the vehicle.
The term "charging pattern" as used below refers to a predetermined schedule, sequence or progression of the recharging process of the energy storage system. Such a charging pattern can for example be in the form of a "quick charge", i.e. involving a relatively high charging current during a relatively short time period, or a "standard charge", i.e. involving a lower charging current during a relatively long time period. A charging pattern of the "quick charge" type can for example be suitable for recharging the energy storage system of a bus while the bus is being parked briefly during a lunch break or between two consecutive rounds. Consequently, a "charging pattern" is a charging sequence with a certain charging current and voltage which occurs for a certain time or until a certain state of charge has be achieved by the energy storage system
Furthermore, the term "modulation" refers to any predetermined variation, deviation or adaptation of the charging current or charging voltage which can be controlled by the vehicles control unit and requested to be supplied from the external power supply. According to a particular embodiment which is described below, such a "modulated" charging pattern can subsequently be detected and evaluated by the vehicles control unit in order to determine whether the charging supplied by the external power supply corresponds to the requested charging. Any difference between the requested charging pattern and the supplied charging pattern can be interpreted as an error of the charging process.

Method and arrangement for controlling charging of an energy storage system


Technologies for an operating system identifying SSD and CSSD devices based on a corresponding descriptor, and for optimizing operating system functionalities with respect to the SSD/CSSD device. Optimizations include disabling non-SSD/CSSD functionalities, such as HDD defragmentation, and by enabling SSD/CSSD specific functionalities, such as write optimization storage functionalities.

Solid state drives ("SSD") are becoming economical for use as bootable mass storage devices. SSDs are commonly fabricated to include flash memory devices, such as nonvolatile flash memory devices including Not AND ("NAND") type devices. Composite SSDs ("CSSD") are typically fabricated with two or more performance classes of memory devices, high-speed memory devices (and thus higher cost) as well as lower-write-speed devices (and thus lower cost). Such composite SSDs tend to be less costly than SSDs fabricated solely of high-speed memory devices. Because write access on mass storage devices is often localized, composite SSDs are able to provide high-speed memory elements that can be leveraged for frequent write access combined with lower-write-speed memory elements for providing readable mass storage with less frequent write access. Since the introduction of SSD devices, manufactures have typically configured them to appear to a computing system as a conventional hard disk drive ("HDD"). But there tends to be significant performance differences between SSDs and HDDs. As many SSD devices are fabricated using flash memory, typical write operations have different considerations than do those of a conventional HDD that can over-write invalid (deleted) data with valid (new) data at the same physical location on the disk. SSD write operations typically require a write-merge operation so as to merge the new data with other existing data of the same memory block into a new memory block. Such merge operations typically involve a block erase operation that can be slow and reduce the life-span of the device. Thus, unnecessary write operations can contribute to reduced SSD performance and/or reliability.

Composite solid state drive identification and optimization technologies


A piezoresistive micromechanical sensor component includes a substrate, a seismic mass, at least one piezoresistive bar, and a measuring device. The seismic mass is suspended from the substrate such that it can be deflected. The at least one piezoresistive bar is provided between the substrate and the seismic mass and is subject to a change in resistance when the seismic mass is deflected. The at least one piezoresistive bar has a lateral and/or upper and/or lower conductor track which at least partially covers the piezoresistive bar and extends into the region of the substrate. The measuring device is electrically connected to the substrate and to the conductor track and is configured to measure the change in resistance over a circuit path which runs from the substrate through the piezoresistive bar and from the piezoresistive bar through the lateral and/or upper and/or lower conductor track.

The present disclosure relates to a piezoresistive micromechanical sensor component and to a corresponding measuring method.
Although applicable to any piezoresistive micromechanical sensor components, the present disclosure and the problem which it is intended to resolve will be explained with reference to a piezoresistive micromechanical acceleration sensor.
Modern acceleration sensors are conventionally evaluated capacitively. The piezoresistive evaluation which is also practiced, however, offers greater potential with regard to the desired ever increasing miniaturization. In the case of piezoresistively evaluated acceleration sensors, here referred to as piezoresistive acceleration sensors, distinction may essentially be made between the following two variants.
One variant consists in structured doping, piezoresistors being doped at the positions on a bending beam where the maximum mechanical stress occurs during deflection.
The other variant consists in homogeneous doping, the entire homogeneously doped bending beam being used for the evaluation. To this end, a homogeneously distributed mechanical stress is required in the beam. Since the entire bending beam is used for the evaluation in the case of homogeneous doping, homogeneous doping offers advantages with regard to miniaturization.
J. Micromech. Microeng. 15 (2005), pages 993-1000 (Shusen Huang et al.) discloses a piezoresistive micromechanical acceleration sensor comprising homogeneously doped bending beams.
FIG. 6 is a perspective view of this known piezoresistive micromechanical acceleration sensor.
In FIG. 6, reference 1 denotes a substrate on which a sacrificial oxide layer S1 and a cover layer S2 are provided. Structured out of the cover layer S2, there is a seismic mass 3 which is anchored via an undoped bending beam B to the substrate 1. At the tip of the seismic mass 3, a stop 30 is provided, which protects the seismic mass 3 against excessive deflections. Below the seismic mass 3 and the bending beam B, there is a cavity K.
Next to the bending beam B, the seismic mass 3 is connected via two homogeneously doped piezoresistive beams PR1, PR2 to the substrate. In order to record a resistance change of the piezoresistive beams PR1, PR2 when the seismic mass 3 is deflected in the substrate plane, metallization regions M1, M2, M3, M4, M5 are provided, which are interconnected with the piezoresistive beam PR1, PR2 so as to permit half-bridge evaluation.
For signal feedback from the seismic mass 3 to the substrate 1, in this circuit arrangement the bending beam B is fundamentally necessary in addition to the piezoresistive beams PR1, PR2. The additional bending beam B, however, reduces the mechanical sensitivity and/or increases the process outlay with respect to the required trenches, when otherwise assuming the same requirements. In particular, trench isolation (STI) which is as narrow as possible is required between the beams PR1, B, PR2, which entails increased process outlay.

Piezoresistive micromechanical sensor component and corresponding measuring method


A high density network access server implements a tunneling protocol between a modem module and a route server module. PPP and routing control packets received from the PPP link are tunneled to the route server for processing. The IP data packet forwarding function for the network access server is distributed directly to the modem modules. The combination of distributed PPP processing and distributed IP data packet forwarding enables the capacity of the network access server to be scaled to orders of magnitude greater than previously known, to handle thousands or even tens of thousands of simultaneous data sessions.

A. Field of the Invention
This is a telecommunications invention that relates generally to the field of remote access to packet switched networks over point to point links. More particularly, the invention relates to a network access server and method for performing distributed processing of the Point-to-Point Protocol (PPP) and distributed packet forwarding of Internet Protocol (IP) packets using a tunneling protocol, such as the Layer 2 Tunneling Protocol (L2TP). The invention is particularly suitable for use in a high density remote access server, such as a remote access server simultaneously connecting a large number of remotely located users to a packet switched network, e.g., the Internet.
B. Description of Related Art
The methods and techniques disclosed herein can be performed by an element of communications equipment referred to herein as a xe2x80x9cnetwork access serverxe2x80x9d, also known as a xe2x80x9cremote access server.xe2x80x9d A network access server is a device that is capable of receiving a plurality of simultaneous incoming calls from remote users via a circuit switched network, such as the Public Switched Telephone Network (PSTN), and routing them to a packet switched computer network, such as a corporate backbone network, or Internet, for transmission to a host computer system or other device connected to the computer network. The network access server is also capable of handling multiple simultaneous calls from the computer network and directing them onto the PSTN for transmission to the remote user.
The patent to Dale M. Walsh et al., U.S. Pat. No. 5,528,595, which is fully incorporated by reference herein, describes a network access server. The network access server of the Walsh et al. patent has been commercialized widely by 3Com Corporation (previously U.S. Robotics Corp.) under the trade designation Total Control(trademark) Enterprise Network Hub. Network access servers similar in functionality, architecture and design are available from other companies, including Ascend Communication, Lucent Technologies, and others. The invention is suitable for implementation in network access servers from the above companies, and other similar devices.
Typically, the individual remotely located users dial in to the remote access server over a public switched telephone network, cable modem network, ADSL connection, wireless network connection, or other type of communications link. Part of the connection process is the establishment of a Point-to-Point Protocol connection between the remote user""s modem and the remote access server.
Industry and international standards bodies have established sets of functional requirements, conventions or rules that govern the transmission of data over circuit switched and packet switched computer networks. These functional requirements or rules are known in the art as xe2x80x9cprotocols.xe2x80x9d The implementation of protocols is necessary in order to bring order, and standardization, to the communications field and allow equipment of diverse manufacturers to interoperate. Some protocols are considered low level transmission media related protocols, such as modulation schemes implemented in a modem, for example V.34, V.90, etc. Other protocols are considered higher level, as they relate to functions performed at higher levels in the OSI model, and are concerned with such features as error control, transmission control protocols and network level routing and encapsulation of data.
The requirements of these latter protocols are typically prepared as an International Engineering Task Force xe2x80x9cRequest For Commentxe2x80x9d (RFC) document, circulated among the industry and eventually adopted by the standards bodies. Sometimes, they are introduced prior to formal approval by a standards body and adopted by players in the industry, becoming de facto standards. The present invention is concerned with the distributed processing of these higher-level network control protocols, and in particular the Point-to-Point Protocol (PPP). The PPP is well known in the art and described in RFC 1661, the contents of which are incorporated by reference herein.
Briefly, the PPP describes an encapsulation mechanism for transporting muliprotocol packets across layer 2 point-to-point links. Typically, a user obtains a OSI-model layer 2 (i.e., data link layer) connection to a network access server using a number of techniques (dialing up over the PSTN, over an ISDN line, over an ADSL connection, etc.) and then runs PPP over that connection. In such a connection, the layer 2 termination point and the PPP session endpoint reside on the same physical device, namely the network access server on one side and the remote user""s modem on the other side.
The patent to Daniel L. Schoo, et al., U.S. Pat. No. 6,009,101, the contents of which are incorporated by reference herein, describes a method by which the processing of the PPP is distributed among multiple computing platforms in the network access server, in order to increase the efficiency and throughput of the network access server. A first portion of the processing is performed in the modem digital signal processor (DSP) of the network access server, and the remainder of the processing is performed in the gateway computing platform, e.g., DSP or general purpose computing platform in the routing card in the network access server.
Tunneling protocols, by which frames of data are routed from one node to another on a network, are also known in the art. One of these tunneling protocols that can be used with the invention is the Layer 2 Tunneling Protocol or L2TP, which is described in RFC 2661, the contents of which are incorporated by reference herein. Persons skilled in the art are familiar with the contents of RFC 2661. The L2TP protocol describes a mechanism for tunneling PPP packets across an intervening network in a way that is transparent to both end users and applications. The L2TP extends the PPP model by allowing the layer 2 and PPP endpoints to reside on different devices interconnected by a packet switched network. With L2TP, a user has a layer 2 connection to an access concentrator (e.g., modem bank, or an ADSL Digital Subscriber Line Access Multiplexer or DSLAM), and the concentrator then tunnels the individual PPP frames to a remotely located remote access server over an IP network. This allows the actual processing of the PPP frames to be divorced from the termination of the layer 2 circuit.
One benefit of L2TP is that the separation between the processing of PPP frames and termination of the layer 2 circuit can avoid long distance telephone charges. The layer 2 connection may be a local call to a local switched circuit concentrator, which then extends the logical PPP session over a shared infrastructure such as a frame relay circuit or the Internet to the PPP terminating unit, which can be located anywhere. From the user""s perspective, there is no perceptible difference in having the layer 2 circuit terminate and PPP processing occur in a network access server directly, or the PPP frames processed in a remotely located remote access server using L2TP.
The distributed PPP processing techniques of the Schoo patent, and the off-loading of PPP processing entirely as described in L2TP are, in and of themselves, insufficient mechanisms for handling the processing requirements of next-generation, ultra-high capacity network access servers. The market is demanding that such devices meet performance, throughput, and high availability requirements that are orders of magnitude above what was typically provided for only a few years ago. This phenomenon is a result of the explosive growth in the Internet, and the need for Internet Service Providers to install remote access servers that can keep up with the demand for Internet access. These next-generation network access servers are being designed to handle thousands, and even tens of thousands of PPP sessions simultaneously in a single chassis.
The present invention provides a method and network access server architecture in which high speed Internet Protocol data forwarding is separated from control, route calculation and other configurations overhead using a tunneling protocol, within the network access server itself. It permits ultra-high capacity network access servers to meet the performance and availability requirements that the market demands, while enabling the processing of thousands or tens of thousands of PPP sessions at the same time. Moreover, the invention uses an existing tunneling protocol, albeit with slight modification. This allows for reuse of existing expertise and source code in the tunneling art for achieving this goal instead of developing a tunneling protocol from scratch.
In a first aspect of the invention, a method is provided for distributing the processing of Point-to-Point Protocol frames and distributed Internet Protocol packet forwarding in a network access server. The network access server provides simultaneous access to a packet switched network for a plurality of remote terminals connected to a first network, such as a circuit switched network like the Public Switched Telephone Network. The network access server also includes an egress or interface module providing an interface to the packet switched network.
The method includes the step of providing a tunneling protocol access concentrator function in a modem module in the network access server. The tunneling protocol access concentrator function in the illustrated embodiment is as L2TP Access Concentrator (LAC), similar to that described in the RFC 2661 specification. The LAC acts as one side or node of a L2TP tunnel endpoint. The network access server also has a route server processing module. The route server has software and hardware implementing a tunneling protocol network server function, i.e., a peer to the LAC function in the modem module. The tunneling protocol network server function in the illustrated embodiment is a L2TP Network Server (LNS). The LAC function in the modem module tunnels PPP control packets, e.g., link negotiation and authentication packets, and PPP packets with IP routing control data (such as IP RIP data and Internet Protocol Control Protocol (IPCP) data) to the route server LNS for termination. The route server module performs IP routing and PPP control functions for the PPP frames received from the modem module.
The modem module further includes a distributed forwarding module, preferably operating under instruction from the LNS function in the route server. The distributed forwarding module performs packet forwarding for incoming PPP frames and forwards IP data packets in the frames to the egress module for transmission on the packet switched network. Thus, for IP data traffic in the direction from the circuit switched network to the packet switched network, the LAC in the modem module strips off PPP headers, optionally performs data decompression or other processes on the data, and forwards encapsulated IP data packets directly to the egress module for transmission on the packet switched network. For data in the opposite direction, the egress module forwards IP data packets to the LAC in the modem module. The IP data packets are encapsulated with PPP headers, any required data compression is performed, and the PPP packets are transmitted over the PPP link to the remote terminal.
The tunneling protocol (e.g., L2TP), is thus a control mechanism for both distributed processing of the PPP, and control of distributed packet forwarding. This latter feature, distributed packet forwarding directly by the modem modules, is of particular significance in a high capacity network access server such as described herein. Whereas in the prior art IP data packet forwarding and routing for a single network access server chassis was typically performed in a single card or xe2x80x9cbladexe2x80x9d (i.e., one card served as a routing or gateway card for all the modems in the chassis), here the routing function is basically distributed to all the modem modules in the network access server, albeit with the route server performing routing control functions as set forth herein. The route server in the illustrated embodiment does not handle the actual IP data packet routing for the modems, rather it off-loads this function to the modem modules. The route server sends updated forwarding tables or information to the modem modules to assist in IP data packet routing, and also sends updated forwarding tables or information to the egress module to enable it to handle both the forwarded IP data packets, and the incoming IP data packets from the packet switched network.
While L2TP is the tunneling protocol used between the modem modules and the route server module in the illustrated embodiment, other tunneling protocols now known or later developed could of course be used, and the selection of a tunneling protocol is not particularly significant. Examples of other suitable tunneling protocols are the PPP Tunneling Protocol (PPTP) and Layer 2 Forwarding (L2F). L2TP was chosen in the illustrated embodiment because source code for implementing LAC and LNS functions in accordance with the L2TP protocol is known in the art or readily derived from RFC 2661, and does not require writing a new tunneling protocol from scratch. Thus, implementing the invention is very straightforward. The L2TP protocol is modified slightly to provide for distributed forwarding control messages between the route server module and the modem module to implement the distributed forwarding features of the invention.
In another aspect of the invention, a high efficiency, high capacity network access server is described in which Point-to-Point Protocol processing and packet forwarding functions are distributed among multiple computing platforms. The network access server includes an egress or interface module forming an interface to a packet switched network such as the Internet or a corporate backbone network. A plurality of modem modules are provided in the network access server, each of which are operatively connected to a circuit switched network (e.g., PSTN) so as to enable connections over the circuit switched network to the remote terminals.
Each of the modem modules comprises resident software and a computing platform together implementing a node for a tunneling protocol, such as a L2TP Access Concentrator function. The modem module further includes a distributed forwarding module performing IP or Internet Protocol Exchange (IPX) packet forwarding for incoming PPP frames, and forwarding the IP or IPX packets to the interface module.
The network access server further includes at least one route server comprising resident software and a computing platform for providing a peer to the modem tunneling node, such as a tunneling protocol network server function, e.g., an LNS. The route server module in the illustrated embodiment resides in a card or xe2x80x9cbladexe2x80x9d that is separate from the modem module, and separate from the egress or interface module. The route server module performs Internet IP or IPX routing and PPP control functions (e.g., negotiation, authentication) for PPP frames received from the remote terminals.
Further, the route server performs the tunneling node, IP routing and PPP control functions for a multitude of the modem modules. In a extremely high capacity network access server embodiment, there may be a large number of modem modules, more than one egress module, and perhaps two or even three route servers in the same chassis in order to further distribute the LNS tunneling functions and IP routing and PPP control functions among several route servers. However, in such an embodiment the IP data packet forwarding function is distributed to the modem modules, which transparently forward IP data packets directly to their assigned egress or interface module.
In yet another aspect of the invention, a method is provided for distributed protocol processing and IP data packet forwarding performed in a network access server. The method includes the steps of:
a) receiving PPP negotiation packets at the modem module,
b) tunneling the PPP negotiation packets to a route server in the network access server,
c) performing at least one of Link Control Protocol (LCP), PPP link negotiation, PPP authentication, Internet Protocol Routing Information Protocol (IP RIP) and Internet Protocol Control Protocol (IPCP) processing for the PPP connection in the route server;
d) the route server instructing the modem module to perform Internet Protocol (IP) data packet forwarding and providing forwarding information to the modem module;
e) the modem module responsively stripping PPP headers from further incoming PPP packets and forwarding IP data packets contained therein directly to the egress interface module for transmission on the packet switched network.
These and other features of the invention will be more apparent from the following detailed description of a presently preferred embodiment of the invention.

Distributed protocol processing and packet forwarding using tunneling protocols


Apparatus for providing a direct quantitative readout of the amplitudes of arious frequency lines that constitute the envelope of an amplitude-modulated broadband noise signal. A selected band of carrier frequencies is fed to an AGC circuit that provides a constant-input signal amplitude to a demodulator for a period of time that is greater than the period of the lowest frequency of the modulating signal for detection. The detected signal is fed to a spectrum analyzer for the direct reading of the percent modulation.

The present invention relates to signal processing and more particularly to signal processing of amplitude-modulated broadband noise signals.
In the detection and identification of selected modulated broadband noise signals, such as those generated by underwater driven equipment, it is desirable to have a quantitative measurement of the level of modulation. This allows for the immediate reaction to searching for and identifying the sources of the broadband noise supporting the modulation. Demodulation systems of this type presently in use do not have the sensitivity for short time samples to indicate the presence of the desired signal. Neither do they provide the actual amplitude of the modulating signal. Usually the frequency of the modulation line is a darkened trace on continuously moving paper and the level of modulation is a function of the darkness of the line trace. The time to develop the trace requires several minutes.

The United States of America as represented by the Secretary of the Navy


A computer-implemented method comprising: determining, by a computing device, characteristics of a social media message; selecting, by the computing device, a particular image, of a plurality of images, based on the characteristics of the social media message and characteristics of the particular image; and outputting, by the computing device, information identifying the selected image to incorporate the selected image in a user's social media profile.

The present invention generally relates to automatically modifying a user image and, more particularly, to automatically modifying a user image based on cognitive analysis of social media activity.
Social media are computer-mediated technologies that facilitate the creation and sharing of information, ideas, career interests and other forms of expression via virtual communities and networks. The variety of stand-alone and built-in social media services may include features such as: Interactive Web 2.0 Internet-based applications; User-generated content, such as text posts or comments, digital photos or videos, and data generated through all online interactions; User-created service-specific profiles for a social media platform; Development of online social networks by connecting a user's profile with those of other individuals or groups. Users typically access social media services via web-based technologies on desktop, computers, and laptops, or download services that offer social media functionality to their mobile devices (e.g., smartphones and tablet computers). When engaging with these services, users can create highly interactive platforms through which individuals, communities, and organizations can share, co-create, discuss, and modify user-generated content or pre-made content posted online.

Automatic modifications to a user image based on cognitive analysis of social media activity

INTERNATIONAL BUSINESS MACHINES CORPORATION


An axle assembly with a banjo beam and a coverpan. The banjo beam has an upper and lower beam members that are welded together to define a central carrier portion and a pair of tubes. The upper beam member has a pair of upper spring seats that are disposed on opposite sides of the central carrier portion. The lower beam member has a pair of lower spring seats that are disposed on opposite sides of the central carrier portion. The coverpan includes a weld flange and a cover portion. The weld flange is welded to the central carrier portion via a fillet weld to close a first aperture formed in the central carrier portion. The cover portion includes a wall member into which a pair of strengthening protrusions are formed. The strengthening protrusions are disposed on opposite lateral sides of a centerline of the central carrier portion.

This section provides background information related to the present disclosure which is not necessarily prior art.
A conventional housing for a "banjo-style" axle assembly includes a banjo beam, a carrier housing and a coverpan. The banjo beam is typically formed from two mating shells that are welded together over the length of the banjo beam. The carrier housing is typically bolted to the front of the banjo beam to close a front-facing aperture in the banjo beam. The coverpan is typically welded to the rear of the banjo beam to close a rear-facing aperture in the banjo beam.
We have determined that when certain banjo-style axle assemblies are loaded, a portion of the stress transmitted through their banjo beam may be transmitted into the coverpan. Accordingly, in those axle assemblies, the coverpan will have a certain, finite fatigue life.

Axle assembly having banjo beam and strengthened coverpan


The present disclosure generally relates to a vehicle glazing (e.g., vehicle windshield) having an opaque enamel printed opening for an information acquisition system and a darkening source within the opaque enamel printed opening to reduce optical transmittance distortion and improve performance of information acquisition systems (e.g., an imaging system, electric sensor(s), video camera(s), distance sensor(s)) associated with a vehicle. The darkening source, which may not undergo extreme heat treatment above 500 deg. C., provides a darkening source open area within the opaque enamel print open area, wherein the darkening source open area provides an opening through which the information acquisition system may receive information from outside a vehicle.

Information acquisition systems mounted inside a vehicle are increasingly popular for improving safety performance and/or comfort during, e.g., an auto-driving mode of a vehicle. This type of system may include imaging systems, anti-collision systems, brake assisting systems, driving assistance systems and/or auto-driving systems using various electric sensors and/or cameras.
The electronic sensors or cameras in information acquisition systems are typically mounted directly on an inner surface of a vehicle glazing or positioned near a vehicle glazing. The sensors or cameras may collect information on conditions outside of a vehicle by, for example, emitting and/or detecting infrared rays, near infrared rays, laser radar and/or visible light through a glazing, which may be laminated or a single glass substrate.
To hide the electronic sensors or cameras from view when outside of a vehicle, an opaque enamel layer (e.g., dark or black colored enamel printing) may be printed on an inner surface S2 of an outer glass (first glass) substrate or on an outer surface S4 of an inner glass (second glass) substrate. The opaque enamel print may be applied to mask such a system and provide an opaque enamel print open area through which the information acquisition system collects information, in addition to an opaque enamel printing region periphery of the laminated vehicle windshield.
For purposes of this disclosure, including with reference to the figures, a first glass substrate includes surfaces S1 and S2 and a second glass substrate includes surfaces S3 and S4. A surface S1 of an outer glass (first glass) substrate faces a vehicle exterior, a surface S2 of the outer glass substrate is opposite the S1 surface, S2 and S3 surfaces are inside the laminated vehicle glazing, and a S4 surface of an inner glass substrate faces a vehicle interior and is opposite the S3 surface.
There are several examples of a laminated vehicle windshield having information acquisition system opening region(s). For example, U.S. Patent Application Publication No. 2011/0027515 A1 generally discloses an opening arrangement in a laminated vehicle windshield for an electric detector mounted in the inner side of the windshield. Moreover, U.S. Patent Application Publication No. 2017/0015180 A1 generally discloses an opaque masking layer and opening for an information acquisition device.

Glazing having a frame for an information acquisition system


A turbine shroud for an air cycle machine includes a wall inner surface which at least partially defines a turbine flowpath, the wall inner surface defined by set of points in Table T-1 scaled by a desired factor.

The present disclosure relates to an air cycle machine, and more particularly to a turbine shroud therefor.
An air cycle machine may include a centrifugal compressor and a centrifugal turbine mounted for co-rotation on a shaft. The centrifugal compressor further compresses partially compressed air, such as bleed air received from a compressor of a gas turbine engine. The compressed air discharges to a downstream heat exchanger or other system before return to the centrifugal turbine. The compressed air expands in the turbine to thereby drive the compressor. The air output from the turbine may be utilized as an air supply for a vehicle such as the cabin of an aircraft.


A method for making an integrated circuit structure having both PMOS and NMOS devices with lightly doped (LDD) source and drain regions is disclosed utilizing a single photoresist mask in which a substrate is implanted with a low concentration dopant of a first conductivity type through a silicon nitride shielding layer. Spacers are then formed against the sidewalls of oxide and nitride coated polysilicon gate electrodes by RIE etching of a polysilicon layer formed over the nitride shielding layer subsequent to the first implantation. A separate photoresist mask layer is then formed over a portion of the structure and the remaining exposed portions of the shielding nitride layer are then etched, resulting in the formation of first el-shaped shielding members against the sides of the gate electrodes. The exposed polysilicon spacers are then removed and the substrate is implanted with a high concentration dopant of a second conductivity type at an energy level insufficient to penetrate through the el-shaped nitride spacer to form conventional source/drain regions in the substrate.

1. Field of the Invention
This invention relates to MOS devices having LDD regions with graded junctions and methods of making same.
2. Description of the Related Art
In the continuing design of VLSI devices or chips with an ever increasing number of transistors and associated circuitry formed on the same amount of space, shrinkage or sizing down of each component has created further problems which must be dealt with in the construction of the VLSI chip. The shrinkage in size of MOS transistors results in a shorter channel length and this has created problems with respect to the electric field created near the drain region which can cause short channel effects or punchthrough in which the current begins to flow in uncontrolled form through the substrate beneath the channel.
To remedy this short channel or punch through effect, it has been proposed to grade the doping or impurities in the substrate by forming a lightly doped drain region (LDD) adjacent the channel with a more heavily and deeper doped drain region, in turn, formed adjacent the LDD region. The reduced or spread out fields of the lightly doped drain structure mitigates short-channel effects, reduce hot-carrier generation, and increase the junction breakdown voltage.
The problems of lower junction breakdown voltage and hot electron injection due to the sharp impurity profile of the drain junction and the proposed remedy of forming a lightly doped drain region were first discussed by Bassous et al in an article entitled "Self-Aligned Polysilicon Gate MOSFETs with Tailored Source and Drain Profiles" which appeared in IBM Technical Disclosure Bulletin Vol. 22, No. 11, in April 1980. Bassous et al proposed thermally oxidizing a polysilicon gate and the silicon substrate followed by reactive ion etching to form an oxide sidewall on the polysilicon gate following which source and drain regions in the substrate were implanted N+ using the oxide sidewall as a shield. The oxide sidewall was then stripped followed by an N- implant to form N- or lightly doped source and drain regions in the substrate between the N+ source and drain regions and the channel beneath the gate electrode.
FIGS. 1 and 2 illustrate how such lightly doped source and drain regions (LDD regions) are typically formed in this method. Oxide spacers 14 are formed on the side of a polysilicon strip 10 which forms the gate electrode, over gate oxide 16, for several MOS transistors formed in exposed portions of silicon substrate 20 under field oxide 18 as best seen in FIG. 1. Oxide spacers 14 are formed by depositing or growing a layer of oxide (silicon dioxide) over the structure including polysilicon strip 10 and then RIE etching the structure to remove the majority of the oxide leaving only the oxide spacers 14 due to their increased thickness in the step region of the oxide layer caused by the raised polysilicon strip.
The structure may then be N+ implanted to form the N+ source and drain regions 17 shown in FIG. 2 with oxide shoulders 14 shielding the substrate region immediately adjacent the channel region to be formed under gate electrode 10. Subsequently oxide shoulders 14 are removed, thereby permitting an N- implant in the previously shielded regions of the substrate shown outlined in dotted lines at 15.
Earlier, in an article entitled "A Quadruply Self-Aligned MOS (QSA MOS) A New Short Channel High Speed High Density MOSFET for VLSI" published at pp. 581-584 in IEDM in 1979, Ohta et al had proposed controlling or grading the depth of a single implant by forming a layer of oxide over a polysilicon gate electrode and then forming a nitride layer over the oxide layer which was patterned to extend laterally beyond the polysilicon gate and over a portion of the oxide layer over the substrate. The oxide layer was then reactive ion etched, using this nitride portion as a mask, resulting in horizontal portions of oxide remaining on the substrate extending laterally from the polysilicon gate electrode. A subsequent source and drain ion implant gave rise to deeper implanted regions further away from the gate electrode and more shallow implantation where the ions passed through the oxide layer resulting in shallow and deep implanted source and drain regions.
Subsequent to these publications, others have also published proposed methods of forming such lightly doped drain regions. Ogura et al, in "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor", published in the IEEE Transactions on Electron Devices, Vol. ED-27, No. 8, in August of 1980, describe a method for forming such regions by first forming a column on a substrate comprising a polysilicon layer, a silicon nitride layer, and a silicon oxide layer. Using this column as a mask, the substrate is N+ implanted after which the polysilicon is overetched, undercutting the overlying nitride and oxide layers. The oxide and nitride layers are then removed and the substrate is then N- implanted to form N- regions in the substrate area beneath where the polysilicon was removed after the N+ implantation.
Tsang et al, in a paper entitled "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", published in the IEEE Transactions on Electron Devices, Vol. ED-29, No. 4, in April 1982, describe a method of forming LDD regions by first forming a polysilicon gate electrode, N- doping the substrate around the gate electrode, forming a silicon oxide layer over the structure which is then RIE etched to form oxide spacers on the sidewalls of the polysilicon gate electrode. Using these spacers as shields, the substrate is then N+ implanted. The original N- doping results in the formation of LDD regions between the channel under the gate electrode and the N+ regions source and drain subsequently implanted in the substrate.
Woo et al U.S. Pat. No. 4,728,617 discloses a method of fabricating a MOSFET with graded source and drain regions by growing a thermal oxide layer over a substrate on which has already been formed a gate electrode over gate oxide. A low temperature oxide is then deposited over the thermal oxide layer and the structure is then RIE etched to remove substantially all of the low temperature oxide except for spacers on the side of the raised thermal oxide layer adjacent the sides of the gate electrode. In one embodiment the structure is then implanted with a dopant which penetrates through the thermal oxide layer into the substrate except where the thermal oxide is shielded by the low temperature oxide spacers. The spacers are then removed, as well as the thermal oxide not previously shielded by the low temperature oxide, leaving only the thermal oxide portions previously below the spacers. The structure is then implanted a second time wherein the thermal oxide previously below the spacers acts to partially shield the substrate resulting in a shallow implant adjacent the channel portion below the gate electrode. In a second embodiment, the spacers are removed prior to any implantation and most of the thermal oxide layer not beneath the spacers is also removed, leaving only a thick thermal oxide, which may comprise either a single thickness or two thicknesses. The structure is then implanted with a dopant in a single implantation step wherein the remaining thermal oxide portions partially shield the substrate adjacent the channel region beneath the gate electrode resulting in a shallower implant beneath the thermal oxide portions.
Parillo et al, in an article entitled "A Versatile, High-Performance, Double-Level-Poly Double-Level-Metal, 1.2-Micron CMOS Technology", IDEM, 1986, pp. 244-247, describe constructing MOS devices using a disposable polysilicon spacer which is formed on the sidewall of the gate electrode following which an N+ implant to form source and drain regions is performed. The polysilicon spacers are then removed and an N- implant is made resulting in N- regions in the substrate adjacent to the gate electrode and separating the N+ regions from the channel formed in the substrate beneath the gate electrode.
Although many ways have thus been proposed to solve the short channel and punchthrough problem, including many ways of forming the lightly doped drain region, the use of oxide spacers has been the most widely used approach. However while the RIE etching of the oxide layer may use the underlying silicon 20 as an etch stop or end point for the etch, as shown in FIG. 2, in the field oxide region between adjacent MOS devices, there may be no silicon at the surface of the structure and the RIE etching will etch away grooves in the field oxide which, if not filled, can adversely affect the topography, and, if filled, can result in the formation of voids in the filler material which can subsequently result in reliability problems from inclusion of contaminants. Also if the voids are exposed, they may etch preferentially or oxidize which can, in turn, stress the substrate.
To avoid the problem of over etching into the field oxide between adjacent devices, it has been proposed, as discussed above, for example, with regard to the Parillo et al article, to replace the prior art oxide spacers or shoulders shown in FIGS. 1 and 2 with polysilicon spacers which would be formed by RIE etching a conformal polysilicon layer which would be formed over the structure (after first forming a thin oxide layer which would serve to separate the polysilicon gate strip from the conformal polysilicon layer). However, the use of a conductive material such as polysilicon to form the spacers adjacent the gate electrode necessitates the subsequent removal of such polysilicon spacers since they would be electrically floating and could cause threshold shifts.
Thus, there remained a need for solving the problem of short channel effects such as punchthrough in MOS transistors used in VLSI structures by constructing lightly doped drain regions without incurring the additional problems of the prior art which occurred when either oxide or polysilicon spacers were used in the course of the formation of such lightly doped source and drain regions.
European Patent Application 0,218,408 describes a process for forming LDD structures in integrated circuits. Three layers are formed over a gate electrode on a substrate. The bottom layer is an oxide layer; the middle layer is a nitride layer; and the top layer is a polysilicon layer. The polysilicon layer is then etched with an anisotropic dry etch to remove the polysilicon layer except for spacers left along the sides of the raised gate electrode. The substrate is then implanted with a heavy concentration of dopant, using the polysilicon spacers as a shield. After the first implantation, the polysilicon spacers are removed and the substrate is again implanted to form less heavily doped regions in the substrate in the areas previously shielded by the polysilicon spacers and adjoining the heavily doped regions of the substrate.
Komori et al Japanese Patent Document 60-241,267 describes a process to prevent damage to a substrate wherein a polysilicon sidewall is formed without completely etching a surface oxide film in a MOSFET of off-set structure. A gate oxide is first formed on a substrate followed by formation of a gate electrode over the gate oxide. A silicon oxide film is then formed over the entire structure and a nitride film is formed over the oxide layer. A polysilicon film is then formed which is RIE etched to form sidewalls or spacers on the side of the gate electrode (over the nitride and oxide layers). The nitride film acts an an etch stop during the etching of the polysilicon layer resulting in no removal of the underlying silicon oxide layer which, in turn, prevents damage to the substrate.
However, these teachings still utilize the spacers as the mask for shielding the structure when implanting to form the conventional source and drain regions in the substrate.
In copending U.S. patent application Ser. No. 127,995, filed Dec. 2, 1987, by Jacob Haskell and assigned to the assignee of this invention, entitled "METHOD OF MAKING A HIGH PERFORMANCE MOS DEVICE HAVING LDD REGIONS WITH GRADED JUNCTIONS", cross-reference to which is hereby made, there is described and claimed a method of making such LDD source and drain regions in MOS devices which comprises: forming over one or more gate electrodes on a substrate a shielding layer of an insulating material such as silicon nitride; forming another layer of a dissimilar material over the shielding layer such as an oxide or polysilicon layer; anisotropically etching the layer of dissimilar material over the shielding layer to remove the layer except for spacer portions over the shielding layer adjacent the sidewalls of the gate electrodes; removing the portions of the shielding layer not masked by the spacer portions, resulting in the formation of one or more el-shaped shielding members each having a vertical portion against the gate electrode and a horizontal leg extending over the substrate from the vertical portion; and then removing the spacer portions over the one or more el-shaped shielding members.
These el-shaped shielding members then serve as masks to permit the respective formation of conventional P+ or N+ doped source and drain regions in the substrate portion not masked by the el-shaped shielding members using a low energy, but high concentration, implantation which will not penetrate through the el-shaped shielding members. The substrate is also implanted with a low concentration of dopant material of the same type, but at an energy level sufficiently high to penetrate through the el-shaped shielding member to form lightly doped source/drain regions in the portions of the substrate beneath, i.e., shielded, by the el-shaped shielding members. This results in the formation of lightly doped source and drain regions, e.g., P- or N- LDD regions, in the substrate between the channel region of the substrate beneath the gate electrode and the conventional P+ or N+ source and drain regions formed in the substrate.
In one embodiment described therein, when one or more MOS devices of a first type are formed, the remaining portion of the substrate is masked with a first photoresist mask. Following formation of the MOS devices of the first type, the photoresist mask is removed and the MOS devices just formed are masked with a second photoresist mask while one or more MOS devices of a second (opposite) conductivity type are formed.
In a second embodiment described in the aforementioned Haskell patent application, after formation of the spacer members over the shielding layer, the first mask is applied, before removal of the portions of the underlying shielding layer not masked by the spacers. The portions of the shielding layer not covered by either the spacers or the photoresist mask are then removed followed by removal of the first photoresist mask. The remainder of the shielding layer, the el-shaped members, then act as a mask during formation of the MOS devices of the first type. However, while this second embodiment does eliminate the presence of the first photoresist mask during the implantation steps to form the MOS devices of the first type, the method still requires the use of two photoresist masks. Since each photoresist mask used may result in processing problems which negatively impact on the yield of chips from a wafer, it would be desirable from a standpoint of process economics, to completely eliminate the formation and use of one of the photoresist masks.

Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask


An aqueous cosmetic or dermatological preparation for application on wet or moist skin which is substantially emulsifier-free and comprises one or more lipophilic perfume ingredients, one or more lipophobic perfume ingredients, a weight ratio thereof being from about 0.5:1 to about 4:1, and at least about 13% by weight of microcrystalline wax, based on a total weight of the preparation.

1. Field of the Invention
The present invention relates to a substantially emulsifier-free aqueous cosmetic or dermatological preparation comprising at least about 13% by weight of microcrystalline wax and a ratio of lipophilic to lipophobic perfume ingredients of from about 0.5:1 to about 4:1. The preparation is suitable for application on wet skin and thus permits use while showering and imparts a scent-sensory impression both during use under the shower and also after it which has a long-lasting effect and can be readily perceived by the consumer.
2. Discussion of Background Information
Cosmetic or dermatological preparations can be divided on the basis of their application time and their application purpose. Some products are immediately washed off after use ("rinse-off"), others are intended to remain for longer on the skin and are effective there ("leave-on").
Cosmetic preparations for skin care are primarily developed for use on dry skin. This form of preparations are known as leave-on preparations, such as creams, lotions or body milk. Often, these are formulated as emulsions, in particular W/O, O/W, O/W/O or W/O/W emulsions.
Emulsions are generally understood as meaning heterogeneous systems which comprise two liquids that are immiscible or only miscible to a limited extent and which are usually referred to as phases. In an emulsion, one of the two liquids is dispersed in the form of very fine droplets in the other liquid. The liquids (pure or as solutions) are present in an emulsion in a more or less fine distribution which is generally stable only to a limited extent.
If the two liquids are water and oil and oil droplets are present in finely dispersed form in water, then this is an oil-in-water emulsion (O/W emulsion, e.g. milk). The basic character, for example electrical conductivity, sensory properties, ability of the continuous phase to stain, of an O/W emulsion is defined by the water. In the case of a water-in-oil emulsion (W/O emulsion, e.g. butter), the principle is reversed, with the basic character being determined here by the oil.
Leave-on preparations are not suitable for use on wet or moist skin. Due to the emulsifiers present, they are able to emulsify water and, due to the lipids, optionally leave behind an oily film.
By contrast, rinse-off preparations are designed for use under the shower or while bathing.
A long-term scent impression with prior art preparations can likewise be imparted only by two different products which are applied in succession. In order to experience scent impressions while showering, the user is directed to, for example, perfumed shower gels, although the scent impression of these is lost after showering. Afterwards, the user only achieves a long-lasting scent impression by virtue of perfumed cream and/or perfume.
Many cosmetic series therefore include several products with the same perfume which are to be applied in succession, such as shower gels, deodorant preparations and/or Eau de Toilette.
By contrast, rinse-off preparations involve the care aspect, as is obtained upon rubbing cream in, to a lesser extent.
It is desirable to provide a preparation which imparts a scent impression both while showering and also afterwards, without applying a second product.
One property of cosmetic products that is very important to the consumer but can only be measured quantitatively with difficulty is their texture and sensorics. The term "texture" is understood as meaning those properties of a cosmetic which can be attributed to the constitution of the preparation, perceived by a sense of feel and touch and optionally expressed in terms of mechanical or rheological flow properties. The texture can be tested in particular by means of sensorics. The texture of cosmetic products, which can optionally be influenced with the help of additives, is of virtually equal importance for the consumer as their effects which can be established objectively.
The term "sensorics" refers to the scientific discipline which deals with evaluating cosmetic preparations on the basis of sensory impressions. The sensory assessment of a cosmetic is made by reference to the visual, olfactory and haptic impression.                Visual impressions: all features that can be perceived by the eye (color, shape, structure).        Olfactory impressions: all scent impressions that can be perceived upon breathing in air through the nose, which can often be differentiated into initial odor (top note), main scent (heart note, body) and after-scent (fond note, base note). Top note, heart note and base note together form the total odor impression of the perfume. The volatile substances only released upon use also contribute to the olfactory impression.        Haptic impressions: all sensations of the sense of touch, which relates primarily to constitution and consistency of the product.
The sensory analysis makes use of the possibility of ascertaining the overall sensory impression of a product integrally. Disadvantages of sensory analysis are the subjectivity of the impression, the ease with which the test subjects can be influenced and the considerable scattering of the results caused as a consequence. These weaknesses are nowadays countered by using groups of trained test subjects, mutual shielding of the testers, and statistical evaluation of the mostly extensive analytical data.
In view of the foregoing, it was an object of the present invention to provide preparations which besides the criteria customary for cosmetics, such as compatibility, storage stability and the like, also offer essential, hitherto unknown cosmetic benefits for the consumer. In particular the sought preparations should be suitable for a use in the body care sector, i.e. for application to the entire body and at the same time be sensorily and especially olfactory attractive.
In principle, the known different application forms, such as shampoo, shower bath, shower gel, deodorant, antiperspirant, leave-on preparations, place different requirements on the perfuming. In the case of a shower bath, the perfume has to smell pleasant under the shower, i.e., at temperatures of up to about 40° C. The temperature stability and evaporation of the perfume ingredients lead to limited selection options. Here, the impact from the mass is the main aim. The particularly long adherence of the scent beyond the showering process was hitherto not required and/or not easily adjustable. This is the case especially since hydrophilic/lipophobic perfume ingredients are rapidly rinsed off with the water and optionally surfactants. In order to achieve a prolonged scent effect, lipophilic perfume ingredients, such as essential oils, would have to be incorporated which are not so rapidly washed off. As is known, however, the lipophilic substances lead to instabilities of the overall preparations since they shift the ratio of emulsifier to lipids and therefore often bring about an oil separation.
Another object of the present invention therefore was to provide a stable product which does not require the presence of emulsifiers therein. This was particularly difficult in view of the fact that the perfumes employed contain a high percentage of lipophilic components (e.g., more than 30% by weight).
By contrast, in the case of leave-on products with long-lasting scent impression, the challenges faced are quite different. According to experience, particular attention is placed on base note and fond note perfuming to lengthen the scent impression.
The perfume ingredients have to emphasize the cosmetic, caring character of the leave-on product. Here, a prolonged endurance of the perfume ingredients on the skin is obligatory and desired.
It also is an object of the present invention to satisfy the various challenges that are imposed on rinse-off and leave-on products.


A photodegradation catalyst or a photodegradation catalyst precursor comprises a plurality of domains of an oxide of a first metal distributed in a substrate of a halide or oxyhalide of a second metal, wherein the mole percentage of the halide or oxyhalide of the second metal is above 50%. Additionally, a method of preparing a photodegradation catalyst or a photodegradation catalyst precursor, a photodegradation catalyst or a photodegradation catalyst precursor obtained from the method and a method of treating organic pollutants or substances in air or water by using the photodegradation catalyst or the photodegradation catalyst precursor are illustrated.

Metal oxide semiconductor materials have been extensively investigated as photocatalysts for photodegradation of organic pollutants in water and air. Most of these investigations have focused on TiO2 and TiO2 catalysts doped with other metal ions and sometimes anions. Generally, such photodegradation catalysts are susceptible to limited photon efficiencies due to recombination of electron-hole pairs, therefore reducing the overall photon efficiencies of the catalysts. One measure of a catalyst's usefulness, however, is its efficiency. Thus, the relatively low efficiency of such oxide-based photocatalyst composition represents a limitation on their commercial viability. Accordingly, there is a need for a high-efficiency photodegradation catalyst or photodegradation catalyst precursor that has an improved control over the recombination of electron-hole pairs.

Photodegradation catalyst and photodegradation catalyst precursor comprising metal halide or metal oxyhalide


A method and structure for coupling a heat conductor (e.g., heat spreader, heat sink) to a semiconductor chip. In a first embodiment, a thermally conductive shape is formed on the heat conductor, a material in an uncured or partially cured state is dispensed on the chip and on peripheral portions of the chip, and the heat conductor is applied to the material to push the thermally conductive shape into the material such that the material is redistributed to contact both the thermally conductive shape and the chip. The material is then cured (e.g., by pressurization at elevated temperature). In a second embodiment, a thermally conductive shape is formed on the chip, a material (e.g., epoxy) in an uncured or partially cured state is dispensed on the thermally conductive shape and on peripheral portions of the chip, and the heat conductor is pushed into the material to make the material contact both the thermally conductive shape and the heat conductor. The material is then cured (e.g., by pressurization at elevated temperature). For both the first embodiment and the second embodiment, an average thickness of a peripheral portion of the cured material exceeds an average thickness of a central portion of the cured material.

1. Technical Field
The present invention relates to a method and structure for coupling a heat sink or heat spreader to a semiconductor chip.
2. Related Art
FIG. 1 illustrates an electronic package 10 with a semiconductor chip 14 coupled to a chip carrier 12. A heat spreader 16 is coupled to the chip 14 with an interfacing encapsulant 20 between the heat spreader 16 and the chip 14. If conductive fins 22 are present, then a heat sink comprises a composite of the heat spreader 16 and the conductive fins 22. Although the discussion infra in this Related Art section discusses only the heat spreader 16, it should be understood that the heat sink may be present and is analogous to the heat spreader 16. The encapsulant 20 serves to couple the heat spreader 16 to both the chip 14 and the chip carrier 12. A layer 21 of the encapsulant 20 between the chip 14 and the heat spreader 16 has a constant thickness (t), wherein t is in a direction that is normal to a surface 15 of the chip 14. An underfill 18 relieves thermally induced stresses, as well as consequent premature fatigue failure, that might otherwise be imposed on solder connections between the chip 14 and the chip carrier 12 due to differential thermal expansion between the chip 14 and the chip carrier 12. The differential thermal expansion is a consequence of a coefficient of thermal expansion (CTE) differences between the chip 14 (e.g., 3 to 6 ppm/.degree. C.) and the chip carrier 12 (e.g., 10 to 24 ppm/.degree. C. for an organic chip carrier; 6 to 10 ppm/.degree. C. for a ceramic chip carrier).
The encapsulant 20 typically has a much higher CTE (e.g., 17 to 70 ppm/.degree. C.) than a CTE of the chip 14 (e.g., 3 to 6 ppm/.degree. C.) which causes the encapsulant 20 to swell or contract more 5 than the chip 14 when the electronic structure 10 is heated or cooled, respectively. As the encapsulant 20 swells, the encapsulant 20 expands away from the chip 14 and lifts the heat spreader 16 away from the chip 14, which causes high thermally induced stresses at the interfaces with both the chip 14 and the heat spreader 16. Because of the aforementioned thermally induced stresses, the chip 14 or the heat spreader 16 may delaminate from the encapsulant 20, or a crack in the encapsulant 20 may form and propagate, with an accompanying loss of structural integrity and/or degradation of heat transfer capability. The thermally induced stresses at the interfaces of the chip 14 and the heat spreader 16 to the encapsulant 20 are highest near peripheral edges 24 of the chip 14.
A method that reduces interfacial thermally induced stresses and does not materially increase thermal resistance is needed for coupling a heat spreader or a heat sink to a chip.

Surface profiling in electronic packages for reducing thermally induced interfacial stresses

International Business Machines Corporation


A method for writing a logical data block to storage. The method includes receiving a request to write a logical data block to a storage pool, allocating a number of physical log blocks in a RAID log and a parity block for the logical data block, and writing the logical data block and the parity block to the physical log blocks. The number of the physical log blocks are less than a number of disks storing the RAID log. The method further includes allocating space in a physical slab block in a RAID slab for the logical data block, copying data including the logical data block to the space in the physical slab block, and updating, in the RAID slab, a checksum corresponding to the physical slab block and a parity block that includes the data stripe having the physical slab block based on the data copied.

A typical operating system includes a file system. The file system provides a mechanism for the storage and retrieval of files and a hierarchical directory structure for the naming of multiple files. More specifically, the file system stores information provided by the user (i.e., data) and information describing the characteristics of the data (i.e., metadata). The file system also provides extensive programming interfaces to enable the creation and deletion of files, reading and writing of files, performing seeks within a file, creating and deleting directories, managing directory contents, etc. In addition, the file system also provides management interfaces to create and delete file systems. File systems are typically controlled and restricted by operating system parameters. For example, most operating systems limit the maximum number of file names that can be handled within their file system. Some operating systems also limit the size of files that can be managed under a file system.
An application, which may reside on the local system (i.e., computer) or may be located on a remote system, uses files as an abstraction to address data. Conventionally, this data is stored on a storage device, such as a disk.
Data stored as files in a file system may be protected using one or more redundancy schemes. Redundancy schemes are typically used to enable recover data in the event of file system failures, data corruption, etc. Data redundancy ensures continuous availability and protection of data stored on disk. The follow is a non-exclusive list of common redundancy schemes: redundant arrays of independent disks (RAID) schemes, 2-way mirroring, 3-way mirroring, etc.
There are many RAID schemes currently available. One common RAID scheme is RAID-5. In general, RAID-5 is used to replicate data across multiple physical disks organized in an array. More specifically, the physical disks in the data storage system are typically segmented into blocks of data space. A block may comprise any appropriate number of bytes of data (e.g., 512 bytes, 1024 bytes, etc.). In RAID-5, data to be stored is divided into data blocks and the resulting data blocks are XOR'd to obtain a parity block. The parity block corresponds to a block that is used to recover part of the data in the event that the disk, upon which the data block is stored, fails. The data blocks and the parity block are written to the multiple disks by striping the data blocks across the multiple disks.
The following is a brief example, illustrating the operation of RAID-5. Initially, a request is received to write data to the disk. Assuming that there are five disks in the system, the data to be written is divided into data blocks. Further, one parity block is to be created for each set of four data blocks. The four data blocks and the parity block correspond to a stripe. Once all the parity blocks have been created, the data blocks and the corresponding parity blocks are written to disk, in stripes, where each stripe spans the entire five disks and includes four data blocks and one parity block.
In the event that an entire stripe is not written to the disks (i.e., one or more data blocks or the corresponding parity block is not written to disk), then the parity block of the stripe will be inconsistent with the data blocks in the stripe. As a result, the data blocks in the stripe cannot be recovered using the parity block. The aforementioned issue, commonly known as a "write-hole," has been addressed using hardware based solutions.

Two stage checksummed raid storage model