The present invention is directed to novel nucleotide and amino acid sequences of Torque teno virus (“TTV”), including novel genotypes thereof, all of which are useful in the preparation of vaccines for treating and preventing diseases in swine and other animals. Vaccines provided according to the practice of the invention are effective against multiple swine TTV genotypes and isolates. Diagnostic and therapeutic polyclonal and monoclonal antibodies are also a feature of the present invention, as are infectious clones useful in the propagation of the virus and in the preparation of vaccines. Particularly important aspects of the invention include vaccines that provide TTV ORF1 protein, or peptide fragments thereof, as antigen.

Torque Teno Virus ("TTV"), also referred to as transfusion-transmitted virus, is generally assigned to the Circoviridae family. It is generally recognized that TTV was first isolated from human transfusion patients (see for example, Nishizawa et al., Biochem. Biophys. Res. Comm. vol. 241, 1997, pp. 92-97). Subsequently, TTV or TTV-like viruses have been identified from other mammals, including swine, and numerous strains or isolates have been published (see for example, McKeown et al. Vet. Microbiol. vol. 104, 2004, pp 113-117).
Subsequent work as shown that TTV and TTV-like viruses are very common; however the pathogenesis of TTV, and the contributions it may make to other disease states (for example, those caused by other viruses and bacteria) remains unclear. For example, TTV infections appear to be common in humans, including even in healthy individuals, and such infections are often asymptomatic, and may remain for years. In addition, the general inability to propagate the virus in cell culture, and a lack of any clear mechanistic disease models, have made any overall characterization of TTV biology difficult. Notwithstanding that TTV viremia is elevated in human patients afflicted with other viral diseases, (such as hepatitis or HIV/AIDS), there is also considerable medical literature suggesting that TTVs are, in fact, avirulent, and await any clear actual association with known disease states. See, for example, Biagini et al., Vet. Microbiol. vol. 98, 2004, pp. 95-101.
In regard of swine, the situation is similar. There is considerable work suggesting that TTV infection is associated with, and contributes to, numerous diseases such as porcine circovirus disease (and its various clinical manefestations, such as postweaning multisystemic wasting syndrome and respiratory disease complicated by lung lesions), and PRRSV—associated disease (porcine respiratory and reproductive syndrome virus). See for example published international patent applications WO 2008/150275 and WO 2008/127279. Krakowka et al. also report on an often fatal disease in pigs referred to as PDNS (porcine dermatitis and neuropathy syndrome) which is described as a manifestation of disseminated intravascular coagulation, and for which combined infection by serotype 1 TTV and PRRSV virus was possibly implicated (Am. J. Vet Res, vol 69(12), 2008, pp. 1615-1622. PDNS disease was also correlated with porcine circovirus disease (notably PCV-2) and also with bacterial infections. Accordingly, while considerable work has been accomplished, there remains little work that definitively correlates porcine TTV infection with specific pathologies. Nonetheless, it has become reasonably clear that TTV infection can potentiate numerous disease states. Accordingly, there is a need for various classes of TTV reagents, such as high affinity antibodies, and for example, peptide fragments of TTV or whole virions that are highly immunizing, both to further our understanding of overall TTV biology and to vaccinate, directly or indirectly, against numerous disease states to which TTV may contribute.
Thus, although the possibility exists that TTV is the principle causative factor of diseases in swine, it seems more likely that numerous swine diseases either require the presence of more than one virus, or that the primary effect of certain "primary" pathogens is potentiated by TTV infection. As stated, the possibility exists that numerous diseases of swine can be treated or lessened by administering anti-TTV agents to affected or potentially affected animals. Notwithstanding the well established interest in TTV, effective vaccines have not emerged.
TTV is a small, non-enveloped virus comprised of negative polarity, single-strand circularized DNA. The genome includes three major open reading frames, ORF1, ORF2 and ORF3, which overlap, and ORF1 encodes the capsid protein. (Biagini et al., supra). For a detailed discussion thereof, please see the following references, which are incorporated by reference: Kakkola et al., Virology, vol. 382 (2008), pp. 182-189; Mushahwar et al., Proc. Natl. Acad. Sci, USA, vol 96, (1999) pp. 3177-3182; and T. Kekarainen and J. Segales, "Torque teno virus infection in the pig and its potential role as a model of human infection", The Veterinary Journal, accepted Dec. 13, 2007 for 2008.
Despite the relatively simple genome, it has been generally very difficult to propagate the virus in cell culture or by other in vitro methods. The present invention is directed to recombinant constructs whereby TTV can be propagated in vitro, including via infectious clones. More particularly, the invention is directed to the discovery that effective vaccines can in fact be made from TTV, most particularly when the TTV antigen is the expression product of a single ORF, or a fragment thereof. In a preferred embodiment, the invention provides for ORFI protein vaccines.


The invention features an apparatus and method for positioning and supporting a sprinkler head in a ceiling, floor, or wall. In one aspect of the invention, a sprinkler head may be received by a sleeve extending through a broad surface of the plate. The plate may be configured to be removably attached to a support structure in the ceiling, floor, or wall and having an exterior surface exposed to the room or the plate may be attached to a decorative panel which is configured to be removably attached to a support structure in the ceiling, floor, or wall and having an exterior surface exposed to the room. The sleeve may be defined by an opening in the plate or it may be a separate structure permanently or removably attached to the plate.

A typical automatic fire sprinkler system includes a network of pipes that carry a fire suppression fluid, e.g., water, to each room in the building. Conduit sections carry the fluid from the pipes to sprinkler heads strategically located in different rooms. The position and orientation of each sprinkler head is typically maintained in place by a support mechanism. When the room reaches an elevated temperature due to a fire, the sprinkler head is activated allowing a stream of fire suppression fluid to be directed over the intended area of coverage. During operation, the fluid pressure at each sprinkler head can reach significant levels of pressure (e.g., 175 psi), generating substantial back pressure on the sprinkler head's support system. The support mechanism must be capable of holding the sprinkler head securely in place during operation. Flexible fire protection sprinkler systems are described in U.S. Pat. No. 6,076,608 and U.S. Pat. No. 6,123,154, both of which are incorporated herein by reference.

This patent is subject to a terminal disclaimer.


Explosive devices may be formed from hollow members filled with explosive materials. The hollow members may be made of mating halves that are packed or loaded with explosive material prior to the mating halves being joined together. In some exemplary aspects, the hollow members are placed in fluid-filled containers such that the explosive reaction creates a wave of fluid that impacts a target. Components of the devices may be COTS items and items that may be manufacture with 3D printers.

Conventional technologies for disabling or disrupting explosive ordnance include water systems that use high explosive to propel the water. The targeted explosive ordnance may include, for example, bombs, Improvised Explosive Devices (IEDs) or other explosive devices. The acquisition, production, maintenance and disposal of EOD gear and tools are often logistically complex and time-consuming.
A need exists for EOD gear and tools that are simple enough to be manufactured using COTS (commercial off the shelf) components and/or additive manufacturing techniques, such as three-dimensional (3D) printing.

Apparatus and methods for disrupting/disabling explosive ordnance

The United States of America as represented by the Secretary of the Navy


Method and system for controlling areas of memory within a computer system to routines executing at a specific privilege levels in a modern computer architecture featuring protection keys, operating-system-routine calls and interrupts result in promotion of the current privilege level to the highest privilege level prior to dispatch to an operating system routine with concomitant demotion of the CPL Current Privilege Level to operating-system-privilege level. By partitioning the 24-bit protection queue space into multiple protection-key domains, each protection-key domain associated with a privilege level, and by invalidating protection-key registers during each protection of the current privilege level to a higher privilege level, regions of memory are provided that can only be accessed by routines running at low privilege levels and by routines at the highest privilege level, but not accessible to routines running at intermediate privilege levels.

The present invention relates to computer architecture and data security within computer systems and, in particular, to a method and system for providing, to processes operating at certain selected privilege levels, access to a memory region while preventing processes operating at other privilege levels from accessing the memory region.
The present invention is related to security and access privileges within a computer system that allow processes executing at certain privilege levels to access a region of memory while preventing processes executing at other privilege levels from accessing the memory region. The topics of computer architecture and memory security are far too complex to summarize comprehensively in this section. Instead, a simplified, but adequate, background is presented in this section as a basis for presenting a detailed description of several embodiments of the claimed invention in a subsequent section.
FIG. 1 is a block diagram showing hardware, operating-system, and application-program layers within a generalized computer system. A computer system 100 can be considered to comprise a hardware layer 102, an operating system layer 104, and an application-programming layer 106. Computer systems are quite complex, with many additional components, sub-layers, and logical entity interrelationships, but the 3-layer hierarchy shown in FIG. 1 represents a logical view of computer systems commonly employed within the computer software and hardware industries.
The hardware layer 102 comprises the physical components of a computer system. These physical components include, for many small computer systems, a processor 108, memory storage components 110, 112, and 114, internal buses and signal lines 116-119, bus interconnect devices 120 and 122, and various microprocessor-based peripheral interface cards 124-129. The processor 108 is an instruction-execution device that executes a stream of instructions obtained by the processor from internal memory components 110, 112, and 114. The processor contains a small number of memory storage components referred to as registers 130 that can be quickly accessed. Data and instructions are read from, and written to, the memory components 110, 112, and 114 via internal buses 116 and 117 and the bus interconnect device 120. Far greater data storage capacity resides in peripheral data storage devices such as disk drives, CD-ROM drives, DVD drives, and other such components that are accessed by the processor via internal buses 116, 118, and 119, interconnect devices 120 and 122, and one or more of the peripheral device interconnect cards 124-129. For example, the stored instructions of a large program may reside on a disk drive for retrieval and storage in internal memory components 110, 112, and 114 on an as-needed basis during execution of the program. More sophisticated computers may include multiple processors with correspondingly more complex internal bus interconnections and additional components.
The operating system layer 104 is a logical layer comprising various software routines that execute on the processor 108 or one or more of a set of processors and that manage the physical components of the computer system. Certain operating system routines, in a traditional computer system, run at higher priority then user-level application programs, coordinating concurrent execution of many application programs and providing each application program with a run-time environment that includes processor time, a region of memory addressed by an address space provided to the application program, and a variety of data input and output services, including access to memory components, peripheral devices, communications media, and other internal and external devices. Currently running programs are executed in the context of a process, a logical entity defined by various state variables and data structures managed by the operating system. One important internal data structure managed by the operating system is a process queue 132 that contains, for each currently active process, a process-control block or similar data structure that stores data that defines the state of the currently active process managed by the operating system.
The application-programming and user interface layer 106 is the user-visible layer of the computer system. The current invention relates primarily to the application program interface as well as to internal kernel and operating-system interfaces, and thus the application-programming and user interface layer will be discussed primarily with reference to the application program interface. An application program comprises a long set of stored instructions 134, a memory region addressed within an address space provided by the operating system to the process executing the application program 136, and a variety of services 138-142 provided through the operating-system interface that allow the application program to store data to, and retrieve data from, external devices, access system information, such as an internal clock and system configuration information, and to access additional services.
FIG. 2 illustrates the concept of privilege within a traditional computer system, such as the computer system diagrammed in FIG. 1. A privilege level is a value contained within a process-status control register of a processor within the hardware layer of the computer system. Many current computer systems employ two privilege levels: (1) a most privileged level, or kernel-privilege level; and (2) a less privileged level, or application-program privilege level. In computer systems providing two privilege levels, the current privilege level (xe2x80x9cCPLxe2x80x9d) for a currently executing process can be represented by a single CPL bit within the process status register. When the CPL bit has the value xe2x80x9c0,xe2x80x9d the currently executing process executes at kernel-privilege level, and when the CPL bit has a value of xe2x80x9c1,xe2x80x9d the currently executing process executes at application-privilege level. The privilege level at which a process executes determines the total range or ranges of virtual memory that the process can access and the range of instructions within the total instruction set that can be executed by the processor on behalf of the process. In FIG. 2, the area within outer circle 202 represents the resources accessible by a processor executing at kernel-privilege level, privilege level 0, and the area within the inner circle 204 represents resources accessible by a process executing at application-privilege level, privilege level 1. In FIG. 2, the left-hand rectangle 206 represents the entire instruction set provided by the processor architecture, and right-hand rectangle 208 represents the entire range of addressable virtual memory that can be accessed by a routine executing at the most privileged level. A process executing with privilege level 0 (202 in FIG. 2) can access the entire instruction set 206 and the entire addressable virtual memory 208 of the computer system. However, a process executing at privilege level 2 (204 in FIG. 2) can access only a portion of the instruction set 210 (represented by the cross-hatched region of the entire instruction set 206) and only a portion 212 of the entire addressable memory 208.
The privilege concept is used to prevent full access to computing resources by application programs. In order to obtain services that employ resources not directly available to application programs, application programs need to call operating system routines through the operating system interface. Operating system routines can promote the CPL to privilege level 0 in order to access the necessary resources, carry out a task requested by an application program, and then return control to the application program while simultaneously demoting the CPL back to privilege level 1. By restricting application-program access to computer resources, an operating system can maintain operating-system-only-accessible data structures for managing many different, concurrently executing programs, in the case of a single-processor computer, and, on a multi-processor computing system, many different concurrently executing application programs, a number of which execute in parallel. Privilege levels also prevent the processor from executing certain privileged instructions on behalf of application programs. For example, instructions that alter the contents of the process status register may be privileged, and may be executed by the processor only on behalf of an operating system routine running at privilege level 0. Generally, restricted instructions include instructions that manipulate the contents of control registers and special operating-system-specific data structures.
As an example of the use of privilege levels, consider concurrent execution of multiple processes, representing multiple application programs managed by the operating system in a single-processor computer system. The processor can execute instructions on behalf of only a single process at a time. The operating system may continuously schedule concurrently executing processes for brief periods of execution in order to provide, over time, a fraction of the total processing bandwidth of the computer system to each running application program. The operating system schedules a process for execution by removing the process-control block corresponding to the process from the process queue and writing the contents of various memory locations within the process-control block into various control registers and operating-system data structures. Similarly, the operating system removes a process from the executing state by storing the contents of control registers and operating-system data structures into the corresponding process-control block and re-queuing the process-control block to the process queue. Operating system routines are invoked through system calls, faults, traps, and interrupts during the course of execution of an application program. By maintaining the process queue in memory accessible only to routines executing at privilege level 0, and by ensuring that some or all instructions required to store and retrieve data from control registers are privilege level 0 instructions, the architecture of the computing system ensures that only operating-system routines can schedule application processes for execution. Thus, an application program may not manipulate the process queue and control registers in order to monopolize system resources and prevent other application programs from obtaining computing resources for concurrent execution.
The operating system, as part of providing an application programming environment, provides both application-specific and application-sharable memory to application programs. An application program may store private data that the application wishes to be inaccessible to other application programs in private memory regions, and may exchange data with other application programs by storing date in sharable memory. Access to memory is controlled by the operating system through address mapping and access privileges associated with memory pages, each memory page generally comprising some fixed number of 8-bit bytes. Because the instructions and operating-system data structures necessary for memory mapping and access privilege assignment include instructions and memory accessible only to routines executing at privilege level 0, an application program executing at privilege level 1 may not remap memory or reassign access privileges in order to gain access to the private memory of other application programs. The operating system routines that control memory mapping and access-privilege assignment protect one application program""s private memory from that of other application programs. As one example, an application program executing on behalf of one user may store data-encryption keys within private memory that allow the user to access confidential user-information via the Internet, including user-account information. By controlling access to memory and instructions via privilege levels, the computer system ensures that only trusted operating system routines and one application program can maintain the data encryption keys in memory private to the application program, so that application programs running on behalf of other users may not access the first user""s data encryption keys in order to access the first user""s account information. Unfortunately, most currently available operating systems are not verifiably secure, and contain security holes and breaches that may allow knowledgeable and malicious users to access private memory allocated to other users.
FIG. 3 shows logical layers that may intercooperate within a modern, 4-privilege-level computer system. In FIG. 3, the hardware level 302, operating system level 304, and application-programming level 306, are equivalent to the corresponding hardware, operating-system, and application program levels 102, 104, and 106 in the traditional computing system shown in FIG. 1. The 4-privilege-level computer system may also include two additional levels 308 and 310 between the hardware level 302 and the operating system level 304. The first logical level at these additional levels 308 represents certain fundamental, highly-privileged kernel routines that operate at privilege level 0. The second logical layer 310 represents a control-program level that includes various relatively highly privileged service routines that run at privilege level 1. The operating system level 304 includes operating system routines that run at privilege level 2. Application programs, in the 4-privilege-level computer system, run at privilege 3, the least privileged level. The highly-privileged kernel routines that together compose logical layer 308 may be designed to be verifiably correct and provide critical services, including encryption services, that require fully secure management. An application program, for example, running at privilege 3, may call a kernel routine that runs at privilege 0 in order to obtain data encryption keys that the application program can use to encrypt and decrypt sensitive data. While the routines of that run at privilege level 0 may be designed to be 308 verifiably correct, and fully secure, the operating system routines that run in the operating system level at privilege level 2 are not verifiably correct and are not fully secure. Thus, in order to guarantee data encryption key security at the application level, the application program must be able to obtain private memory that can be accessed only by itself and by routines of the secure kernel 308, but that cannot be accessed by routines that run at intervening privilege levels 1 and 2.
FIG. 4 illustrates partitioning of memory resources between privilege levels in a four-privilege-level computer system. Memory resources accessible to routines running at privilege level 0 are represented by the area within the outer circle 402 in FIG. 4. Memory resources accessible to routines running at privilege levels 1, 2, and 3 are represented by the areas within circles 404, 406, and 408, respectively. The total accessible memory is represented by rectangle 410. As shown in FIG. 4, a process running at privilege level 3 can only access a subset 412 of the total memory space. However, an operating-system routine operating at privilege level 2 can access memory accessible by an application program running at privilege 3 as well as additional memory 414-415 accessible to routines running at privilege levels 2-0. In similar fashion, a routine running at privilege level 1 can access memory accessible to routines running at privilege levels 3 and 2, as well as additional memory 416-417 accessible only to processes running at privilege levels 1 and 0. Finally, a routine running at privilege level 0 can access the entire memory space within the computer system.
In view of the nested accessibility of memory to routines running at the various privilege levels, as illustrated in FIG. 4, it is not possible, by privilege level alone, to provide memory to an application program that is accessible by both the application program and by routines running at privilege level 0. Instead, memory accessible to a routine running at privilege level 3 is generally accessible to routines running at privilege levels 2, 1, and 0. Thus, private memory provided to an application program can also be accessed by operating system routines. However, because operating systems are generally far too complex to be computationally verified and generally include security holes that can be exploited by malicious users to breach security policies adopted by the operating system, it is not possible, using privilege levels alone, to ensure security of private memory accessible to application routines running at privilege level 3. For these reasons, computer architects, software developers, Internet retailers, and computer users have all recognized the need for a method and system for providing memory accessible only to routines executing at arbitrary subsets of privilege levels, particularly at privilege levels 0 and 3.
The present invention is related to computer architecture and secure memory access within computer systems. Certain modern computer architectures provide multiple privilege levels at which processors may execute and which control access to memory pages. Generally, memory and instructions accessible at a lower privilege level are also accessible to processes running at one or more higher privilege levels. It is therefore not possible, using privilege levels alone, to provide memory accessible to a low privilege process and to a high privilege process, but not accessible to intermediate-level processes.
In certain modern computer architectures, memory is protected not only by privilege-level-based access rights, but also by protection keys. In certain modern computer architectures, a number of protection-key registers are included in the control registers accessible to routines running at the most privileged level. Memory pages are associated with 24-bit protection keys. An executing process may access a memory page if a valid protection key equal to the protection key associated with the memory page is currently contained within a protection-key register, if the privilege level associated with the memory page is less privileged or equally privileged to the privilege level of the currently executed process and, finally, if the access mode attempted by the currently executed process is compatible with access mode associated with the memory page and contained within the protection-key register. In certain modern computer architectures featuring protection keys, operating-system routine calls, interrupts, traps, and faults result in promotion of the current privilege level to the highest privilege privilege level prior to dispatch by a kernel routine to an operating system routine with concomitant demotion of the current privilege level to operating-system-privilege level. Any promotion of the current privilege level in such systems occurs via an initial promotion to the most privileged privilege level. By partitioning the 24-bit protection key space into multiple protection-key domains, each protection-key domain associated with a privilege level, by associating memory pages with protection keys selected from the protection-key domain corresponding to the privilege level associated with the memory page, and by invalidating protection-key registers during promotion of the current privilege level to a higher privilege level, it is possible to provide regions of memory that can only be accessed by routines running at low privilege levels and by routines running at the highest privilege level, but not accessible to routines running at intermediate privilege levels.

Method and system for privilege-level-access to memory within a computer

Hewlett-Packard Development Company, L.P.


A sheet material (1) includes a stiffness-increasing concave-convex part (20). A first reference plane (K1), an intermediate reference plane (K3), and a second reference plane (K2) serve as a reference system. The intermediate reference plane is partitioned by first lattice straight lines (L1), second lattice straight lines (L2), and third lattice straight lines (L3) so as to define hexagonal unit areas (24) and triangular unit areas (25) in the intermediate reference plane. Areas that include a plurality of the hexagonal unit areas and the triangular unit areas are designated as first, second and third reference areas (214, 224, 234), respectively. Combinations thereof constitute new first, second and third reference areas (213, 223, 233), respectively. The concave-convex part includes first areas (21) and second areas (22), which respectively include the new first reference areas and the new second reference areas, and third areas (23), which include the new third reference areas.

With the aim of reducing the weight of, for example, an automobile, the potential replacement of the material of components comprising steel sheets and the like with a lightweight material such as an aluminum alloy sheet is being studied and implemented. In such a case, assuming that the weight is reduced, it is necessary that the required stiffness be ensured.
To date, studies conducted to increase stiffness without increasing the thickness of the sheet material have provided the sheet material with a concave-convex pattern, and the stiffness has been increased by virtue of the shape.
As an example of implementing a convex-concave shape, one of the components, called a heat insulator, of an automobile is formed of a sheet material. As a material therefor, Patent Document 1 proposes the formation of numerous protruding parts by embossing in order to ensure sufficient stiffness without increasing sheet thickness. In addition, sheet materials have also been proposed (refer to Patent Documents 2-7) that increase stiffness not only in a heat insulator but also in various applications by forming a concave-convex part via embossing and the like.

Sheet material having a concave-convex part, and vehicle panel and laminated structure using the same


A circuit breaker comprises a magnetic trip mechanism configured to provide a first mechanical driving force, a low voltage trip mechanism configured to provide a second mechanical driving force, a first micro switch configured to generate and output a first trip signal indicating that the circuit breaker has performed a trip operation due to the occurrence of a fault current on a circuit, a second micro switch configured to generate and output a second trip signal indicating that the circuit breaker has performed a trip operation due to the occurrence of a low voltage on the circuit, a first driving force transmission mechanism configured to transmit the first mechanical driving force from the magnetic trip mechanism to the first micro switch, and a second driving force transmission mechanism configured to transmit the second mechanical driving force from the low voltage trip mechanism to the second micro switch.

1. Field of the Disclosure
The present disclosure relates to a circuit breaker capable of providing information on a trip cause, and more particularly, to a circuit breaker having a trip cause indicating mechanism for providing information on whether a trip cause results from a fault current or an under voltage.
2. Background of the Disclosure
Generally, a circuit breaker is an apparatus for protecting a circuit by opening or closing the circuit between a power side and a load side, or by breaking the circuit in the occurrence of an electrical fault such as a ground fault or an electrical shortage. That is, the circuit breaker converts a status of an electrical circuit to an 'OFF' or 'ON' status by a user's manipulation, and breaks the circuit automatically by trip operation in the occurrence of an overload or an electrical shortage, thereby protecting load side components and the circuit. In the conventional circuit breaker, when the trip operation is performed due to a fault current, a trip indicating contact switch for providing trip information to a manager of an electrical facility or a user is operated.
The conventional trip status indicating mechanism for a circuit breaker will be explained with reference to FIGS. 1 and 2.
FIG. 1 is a view showing that a trip indicating contact switch of a circuit breaker is not operated in accordance with the conventional art, and FIG. 2 is a view showing that a trip indicating contact switch of a circuit breaker is operated in accordance with the conventional art.
The conventional trip indicating contact switch of a circuit breaker comprises a trip indicating switch 1, a driving force transmission lever 2, a magnetic trip mechanism 3. Reference numeral 4 in FIGS. 1 and 2 denotes a switch driving lever 4 configured to operate the trip indicating switch 1 to an 'ON' or 'OFF' position.
The operation of the conventional trip indicating contact switch of a circuit breaker will be explained as follows.
In an electric power user such as a factory, a transformer is installed as an electricity receiving apparatus, and a large capacity circuit breaker such as an air circuit breaker is installed to connect with an output of the transformer. This large capacity circuit breaker comprises a controller called as 'Over Load Relay' or 'Over Current Relay' (which is abbreviated as OCR hereinafter). The OCR detects a fault of a current which flows on a circuit by being electrically connected to the circuit, such as an electrical shortage, an over current or a ground fault. Then, the OCR outputs a trip command signal to a trip mechanism when a fault has been detected. In response to the trip command signal, the trip mechanism triggers a switching mechanism for a trip operation.
Upon receiving a corresponding trip command signal transmitted from the OCR, the magnetic trip mechanism 3 triggers the switching mechanism so as to break a circuit. As a movable contact (not shown) is separated from a fixed contact, a trip operation is completed. Here, the driving force transmission lever 2 forwardly rotates by interlocking with components which move to a front side of the magnetic trip mechanism 3, thereby pushing a switch operation lever 6 of the trip indicating switch 1. As a result, the trip indicating switch 1 as a micro switch outputs a trip indicating signal. When the circuit breaker is reset after being tripped, the trip indicating switch 1 rotates to an initial position by a return spring (not shown). At the same time, the trip indicating switch 1 is also initialized to stop outputting a trip indicating signal.
The conventional circuit breaker may have a trip operation due to a low voltage on the circuit (hereinafter, will be referred to as 'Under Voltage Trip'), as well as a fault current such as an electrical shortage. However, the conventional circuit breaker is configured to output a trip indicating signal only when a trip operation occurs due to a fault current. Accordingly, it is difficult to check whether a trip operation has occurred due to a fault current or an under voltage.
In the event of an under voltage trip, a remote monitoring center or a central monitoring and supervising equipment could not recognize the under voltage trip. Accordingly, it was difficult to recognize a cause of a trip occurrence, and to determine a re-closing command for the circuit breaker after the trip occurrence.

Circuit breaker having trip cause indicating mechanism


One aspect of the present application relates to a method for limiting damage to neuronal cells by ischemic or epoxic conditions, e.g., such as may be manifest by a reduction in brain infarct volume, by administering to an individual a hedgehog therapeutic or ptc therapeutic in an amount effective for reducing cerebral infarct volume.

Stroke kills more than 150,000 people annually and accounts for about one of every 15 U.S. deaths. It is presently the third largest cause of death, ranking behind diseases of the heart and cancer, according to the National Center for Health Statistics.
On average, someone suffers a stroke in the United States every minute; every 3.4 minutes someone dies of a stroke. Based on the Framingham Heart Study, approximately 500,000 people suffer a new or recurrent brain attack each year. Approximately 3,890,000 stroke survivors are alive today. From 1984 to 1994, the death rate from stroke declined 19.8 percent, but the actual number of deaths from brain attack rose slightly.
Stroke is the leading cause of serious, long-term disability in the United States. Stroke accounts for half of all patients hospitalized for acute neurological disease. In 1991-92 one million Americans age 15 and older had disabilities resulting from stroke. According to the Framingham Heart Study, 31 percent of brain attack survivors needed help caring for themselves; 20 percent needed help walking; and 71 percent had an impaired ability to work when examined an average of seven years later. Sixteen percent had to be institutionalized. About 31 percent of people who have an initial stroke die within a year. This percentage is higher among people older than age 65. About two-thirds of men and women who have a brain attack die within 12 years; long-term survivorship is worse in men than in women. 407,000 males and 478,000 females were discharged from hospitals in 1994 after having a stroke.
Stroke is defined as a sudden impairment of body functions caused by a disruption in, e.g., the supply of blood to the brain. For instance, a stroke occurs when a blood vessel bringing oxygen and nutrients to the brain is interrupted by any method including low blood pressure, clogging by atherosclerotic plaque, a blood clot, or some other particle, or when a blood vessel bursts.
Because of the blockage or rupture, part of the brain fails to get the blood flow that it requires. Brain tissue that receives an inadequate supply of blood is said to be ischemic. Deprived of oxygen and nutrients, nerve cells and other cell types within the brain begin to fail, creating an infarct (an area of cell death, or necrosis). As nerve cells (neurons) fail and die, the part of the body controlled by those neurons cannot function either. The devastating effects of ischemia are often permanent because brain tissue has very limited repair capabilities and lost neurons are not usually replaced.
Cerebral ischemia may be incomplete (blood flow is reduced but not entirely cut off), complete (total loss of tissue perfusion), transient or permanent. If ischemia is incomplete and persists for no more than ten to fifteen minutes, neural death might not occur. More prolonged or complete ischemia results in infarction. Depending on the site and extent of the infarction, mild to severe neurological disability or death will follow. Thus, the chain of causality leading to neurological deficit in stroke has two principal components: loss of blood supply, and cell damage and death.
Thrombosis is the blockage of an artery by a large deposit that usually results from the combination of atherosclerosis and blood clotting. Thrombotic stroke (also called cerebral thrombosis) results when a deposit in a brain or neck artery reaches occlusive proportions. Most strokes are of this type.
Embolism is the blockage of an artery or vein by an embolus. Emboli are often small pieces of blood clot that break off from larger clots. Embolic stroke (also called cerebral embolism) occurs when an embolus is carried in the bloodstream to a brain or neck artery. If the embolus reaches an artery that is too small for it to pass through, it plugs the artery and cuts off the blood supply to downstream tissues. Embolic stroke is the clinical expression of this event.
To a modest extent, the brain is protected against cerebral ischemia by compensatory mechanisms that include: collateral circulation (overlapping local blood supplies), and arteriolar auto-regulation (local smooth muscle control of blood flow in the smallest arterial channels). If compensatory mechanisms operate efficiently, slightly diminished cerebral blood flow produces neither tissue ischemia nor abnormal signs and symptoms. Usually, such mechanisms must act within minutes to restore blood flow if permanent infarction damage is to be avoided or reduced. Arteriolar auto-regulation works by shunting blood from noncritical regions to infarct zones.
Even in the face of systemic hypotension, auto-regulation may be sufficient to adjust the circulation and thereby preserve the vitality and function of brain tissue. Alternatively, ischemia may be sufficiently prolonged and compensatory mechanisms sufficiently inadequate that a catastrophic stroke results. With these as the extremes, the gradation of ischemic stroke are described below.
A transient ischemic attack (TIA) is conventionally described as a loss of neurologic function caused by ischemia, abrupt in onset, persisting for less than 24 hours, and clearing without residual signs. Most TIAs last only a few minutes. However, neurologic disability may persist for more than 24 hours before clearing. Such an event is called a reversible ischemic neurological disability (RIND).
An ischemic event that is sufficiently severe to cause persistent disability but that is short of a calamitous stroke, is called a partial nonprogressing stroke (PNS). The penultimate ischemic event, a completed stroke, produces major functional loss. The ultimate ischemic insult is death.
Focal cerebral ischemia must be distinguished from global cerebral hypoxia. In cerebral hypoxia the oxygen supply to the brain is diminished even though blood flow and blood pressure may be normal. Discriminating between diagnoses of patients with acute neurological deficit is critical because patient management takes disparate paths.
There are generally distinct clinical outcomes in stroke versus cerebral hypoxia, although both sets of patients may suffer death or permanent damage. Hypoxia patients who survive past an acute life-threatening period usually show few immediate symptoms of long term damage. Instead, clinical manifestations such as mental deterioration, urinary and fecal incontinence, gait and speech disturbances, tremor and weakness are delayed for periods that may vary from days to weeks. However, as in stroke, progressive loss of neurons due to oxygen deprivation is believed to be a factor in such detrimental effects of hypoxia.
It is an objective of the present application to provide new drugs for treatment and prophylaxis of cerebral ischemia, such as stroke.
It is also an objective of the present application to provide new drugs for treatment and prophylaxis of cerebral hypoxia.
One aspect of the present application relates to a method for limiting damage to neuronal cells by ischemic or hypoxic conditions, e.g., such as may be manifest by a reduction in brain infarct volume, by administering to an individual a hedgehog therapeutic or ptc therapeutic in an amount effective for reducing cerebral infarct volume relative to the absence of administeration of the hedgehog therapeutic or ptc therapeutic.
In other embodiments, the subject method can be used for protecting cerebral tissue of a mammal against the repercussions of ischemia; for treating cerebral infarctions; for treating cerebral ischemia; for treatment of stroke; and/or for treating transient ischemia attacks. In embodiments wherein the patient is treated with a ptc therapeutic, such therapeutics are preferably small organic molecules which mimic hedgehog effects on patched-mediated signals.
Wherein the subject method is carried out using a hedgehog therapeutic, the hedgehog therapeutic preferably a polypeptide including a hedgehog portion comprising at least a bioactive extracellular portion of a hedgehog protein, e.g., the hedgehog portion includes at least 50, 100 or 150 amino acid residues of an N-terminal half of a hedgehog protein. In preferred embodiments, the hedgehog portion includes at least a portion of the hedgehog protein corresponding to a 19 kd fragment of the extracellular domain of a hedgehog protein.
In preferred embodiments, the hedgehog portion has an amino acid sequence at least 60, 75, 85, or 95 percent identical with a hedgehog protein of any of SEQ ID Nos. 10-18, though sequences identical to those sequence listing entries are also contemplated as useful in the present method. The hedgehog portion can be encoded by a nucleic acid which hybridizes under stringent conditions to a nucleic acid sequence of any of SEQ ID Nos. 1-9, e.g., the hedgehog portion can be encoded by a vertebrate hedgehog gene, especially a human hedgehog gene.
In other embodiments, the subject method can be carried out by administering a gene activation construct, wherein the gene activation construct is designed to recombine with a genomic hedgehog gene of the patient to provide a heterologous transcriptional regulatory sequence operatively linked to a coding sequence of the hedgehog gene.
In still other embodiments, the subject method can be practiced with the administration of a gene therapy construct encoding a hedgehog polypeptide. For instance, the gene therapy construct can be provided in a composition selected from a group consisting of a recombinant viral particle, a liposome, and a poly-cationic nucleic acid binding agent.
Where the subject method is carried out using a ptc therapeutic, the therapeutic can be, e.g., a molecule which binds to patched and mimics hedgehog-mediated patched signal transduction. For instance, the binding of the therapeutic to patched may result in upregulation of patched and/or gli expression.
In other embodiments, the ptc therapeutic mimics hedgehog-mediated patched signal transduction by altering the localization, protein-protein binding and/or enzymatic activity of an intracellular protein involved in a patched signal pathway.
In a preferred embodiment, the ptc therapeutic is a small organic molecule, e.g., less than 5 kd, more preferably less than 2.5 kd. For instance, the present invention contemplates the use of small organic molecules which interact with neuronal cells to mimic hedgehog-mediated patched signal transduction.
In a preferred embodiment, the ptc therapeutic is a PKA inhibitor. A variety of PKA inhibitors are known in the art, including both peptidyl and organic compounds. For instance, the ptc therapeutic can be a 5-isoquinolinesulfonamide, such as represented in the general formula:
wherein,
R1 and R2 each can independently represent hydrogen, and as valence and stability permit a lower alkyl, a lower alkenyl, a lower alkynyl, a carbonyl (such as a carboxyl, an ester, a formate, or a ketone), a thiocarbonyl (such as a thioester, a thioacetate, or a thioformate), an amino, an acylamino, an amido, a cyano, a nitro, an azido, a sulfate, a sulfonate, a sulfonamido, xe2x80x94(CH2)mxe2x80x94R8, xe2x80x94(CH2)mxe2x80x94OH, xe2x80x94(CH2)mxe2x80x94O-lower alkyl, xe2x80x94(CH2)mxe2x80x94O-lower alkenyl; xe2x80x94(CH2)nxe2x80x94Oxe2x80x94(CH2)mxe2x80x94R8, xe2x80x94(CH2)mxe2x80x94SH, xe2x80x94(CH2)mxe2x80x94S-lower alkyl, xe2x80x94(CH2)mxe2x80x94S-lower alkenyl, xe2x80x94(CH2)nxe2x80x94Sxe2x80x94(CH2)mxe2x80x94R8, or
R1 and R2 taken together with N form a heterocycle (substituted or unsubstituted);
R3 is absent or represents one or more substitutions to the isoquinoline ring such as a lower alkyl, a lower alkenyl, a lower alkynyl, a carbonyl (such as a carboxyl, an ester, a formate, or a ketone), a thiocarbonyl (such as a thioester, a thioacetate, or a thioformate), an amino, an acylamino, an amido, a cyano, a nitro, an azido, a sulfate, a sulfonate, a sulfonamido, xe2x80x94(CH2)mxe2x80x94R8, xe2x80x94(CH2)mxe2x80x94OH, xe2x80x94(CH2)mxe2x80x94O-lower alkyl, xe2x80x94(CH2)mxe2x80x94O-lower alkenyl, xe2x80x94(CH2)nxe2x80x94Oxe2x80x94(CH2)mxe2x80x94R8, xe2x80x94(CH2)mxe2x80x94SH, xe2x80x94(CH2)mxe2x80x94S-lower alkyl, xe2x80x94(CH2)mxe2x80x94S-lower alkenyl, xe2x80x94(CH2)nxe2x80x94Sxe2x80x94(CH2)mxe2x80x94R8;
R8 represents a substituted or unsubstituted aryl, aralkyl, cycloalkyl, cycloalkenyl, or heterocycle; and
n and m are independently for each occurrence zero or an integer in the range of 1 to 6.
Exemplary PKA inhibitors of this class include N-[2-((p-bromocinnamyl)amino)ethyl]-5-isoquinoline-sulfonamide and 1-(5-isoquinolinesulfonyl)-2-methylpiperazine. Other PKA inhibitors which can be used in the subject method include KT5720; and PKA Heat Stable Inhibitor (isoform xcex1).
In yet other embodiments of the present invention, the ptc therapeutic alters the level of expression of a hedgehog protein, a patched protein or another protein involved in the intracellular signal transduction pathway of patched. In this regard, the ptc therapeutic can be an antisense construct which inhibits the expression of a protein which is involved in the signal transduction pathway of patched and the expression of which antagonizes hedgehog-mediated signals. For example, the antisense molecule can be one which hyridizes to a patched transcript or genomic sequence, such as 5xe2x80x2-GTCCTGGCGCCGCCGCCGCCGTCGCC, 5xe2x80x2-TTCCGATGACCGGCCTTTCGCGGTGA or 5xe2x80x2-GTGCACGGAAAGGTGCAGGCCACACT (SEQ ID NOS: 24-26).
In yet other embodiments, the subject method can be carried out with a gene activation construct, which construct recombines with a genomic hedgehog gene of the patient, e.g., to form a chimeric gene, providing a heterologous transcriptional regulatory sequence operatively linked to a coding sequence of the hedgehog gene. The transcriptional regulatory sequence can provide for constitutive or inducible expression of the hedgehog gene.
The subject method can be used as part of a treatment for stroke, e.g., thrombotic stroke and/or embolic stroke.
The subject method can also be used to treat hypoxic conditions which otherwise result in cerebral hypoxia.
The subject method can be used prophylactically or as an ipso facto treatment. It can be used to treat patients who are hypotensive.
The subject method can also be used as part of a therapy including administering one or more of an anticoagulant, an antiplatelet agent, a thrombin inhibitor, and/or a thrombolytic agent, and/or in conjunction with vascular surgery, e.g., carotid endarterectomy.
In preferred embodiments, the subject method results in at least a 25%, 50%, 70%, 75%, or 90% reduction in cerebral infarct volumes relative to the absence of treatment with the therapeutic, e.g., as measured in a stroke model such as the MCAO model.


A user information storage unit stores user information associating, for each user, an electronic mail address and at least one location information piece of the user with each other. A registration unit generates a code for each user using the location information and electronic mail address according to a predetermined rule. An invoice information storage unit stores invoice information including the electronic mail address of a first user included in the user information. When receiving an access request for accessing invoice information from a second user whose user information is stored in the user information storage unit, the registration unit determines whether the first code of the first user matches the second code of the second user, and if the first and second codes match, grants the second user access rights to access invoice information generated by the first user and stored in the invoice information storage unit.

There has been known a system for managing invoices in a unified way. For example, there is a known method for compiling electronic invoices issued to each recipient and calculating a total amount.
Please see, for example, Japanese Laid-open Patent Publication Nos. 2005-537588 and 2003-187159, incorporated herein in their entirety.

Devices and methods for information processing and access control


Brake control device for controlling actuators for influencing a braking function of a vehicle, including at least one logic circuit for controlling at least one braking function, wherein the control device controls at least one function of an electronic braking system and one parking brake function, wherein the brake control device includes electric power supply connections of at least the first kind and the second kind, wherein the first kind is connected to a reference potential and the second kind is connected to a different potential than the reference potential, and wherein the first kind or second kind is electrically connected to at least one functional element for controlling the electronic braking system and to at least one functional element for controlling the parking brake function, and/or is electrically connected to at least one functional element for controlling the electronic braking system and the parking brake function.

Electronic brake control devices for performing open-loop and/or closed-loop control of braking functions in a motor vehicle brake system such as, for example, an antilock braking function (ABS: Antilock Brake System) or a vehicle movement dynamics control function (ESC: Electronic Stability Control) are known per se, for example, from DE 101 22 954 A1, which is incorporated by reference. The specified document also discloses that the multiple embodiment of supply lines or connections for brake-by-wire control devices allows increased availability of energy supply of individual functions or of the overall function to be achieved in the case of faults on the supply lines.
However, electronic brake control devices are more widespread for conventional hydraulic, i.e. not brake-by-wire, brake systems which only comprise one connection for a positive supply line for the motor of a hydraulic pump, one connection for a further positive supply line for the electrohydraulic valves and, if it is not also supplied by the latter, a further connection for a positive supply line for the logic component (microcontroller etc.) of the control device. Furthermore, a connection for a ground line (GND) is generally present.
In addition to the electronic brake control devices for the service brake of a motor vehicle, electronic control units, which are disconnected from the brake control devices, for an electric parking brake are also known. For reasons of safety, these control units have, to a certain extent, one or more connections for positive supply lines. Corresponding control units are also known in which the ground supply line is also embodied multiply by corresponding ground connections.
The invention therefore relates to the object of making available an improved brake control device which combines both the functions of an electronic parking brake control unit which is known per se and the essential open-loop and/or closed-loop control functions of a service brake in a common device in such a way that advantages are obtained over control devices or control units which are respectively disconnected with respect to the functions.

Brake control device for driving and/or controlling actuators for influencing a braking function of a motor vehicle


Provided herein are compounds, compositions, conjugates and methods for the treatment of diseases, and/or conditions such as, but not limited to, proliferative diseases. In certain embodiments, compounds, compositions, and conjugates are provided, which include cyclodextrin-based linker-payloads and protein conjugates thereof, and/or in combination with other agents. By administering these compounds, compositions, and conjugates as described herein to specific target cells, side-effects due to non-specific binding phenomena, for example, to non-target cells are reduced.

Antibody-drug conjugates (ADCs) use antibodies to deliver a potent drug selectively to target-expressing cells, leading to a potential reduction of off-target side effects and/or toxicity, and therefore, increasing therapeutic index.
The lipophilic nature of many payloads (i.e., drugs) can adversely affect the properties of the ADC to the extent that the payloads are not efficiently delivered to the target cells. Modulating ADC properties by affixing polar groups in linkers may reduce aggregation during conjugation, and improve physiochemical properties of the ADCs leading to improved pharmacokinetics (PK) and an improved therapeutic index of the ADC (see, for example, Nature Biotechnology, 2015, 33, 733-735). Modulation of the linker to effect a change in the polarity or charge of the final metabolite may improve activity toward multidrug resistant (MDR) cells owing to better retention of the payloads inside the cells (see, for example, Cancer Res; 70(6) Mar. 15, 2010, p 2528). The chemical moieties on linkers, e.g., polyethylene glycol (PEG), sugar, or sulfuric acid groups (See, for example, WO2014062697, US20100323973), not only affect the conjugation efficiency and the ease of production of ADCs, but also often remain as part of the metabolites and thus affect the ADC's activity and safety. Various strategies have been employed to improve ADCs (See, for example, Bioconjugate Chem., 2008, 19 (10), pp 1960-1963).
Cyclodextrins (CDs) are biodegradable soluble dietary fiber and food ingredients, and are also used as drug carriers. Their safety has been documented. CDs are more soluble than PEGs, and they have no charge like sulfonates, which allows them to be easily handled during processing. In addition, since the glucose units are covalently attached end-to-end via α-1, 4 linkages, every unit should have the same chemical property and also form a unique hydrophilic exterior surface and hydrophobic interior core.
Low bioavailability of lipophilic payloads can exacerbate therapeutic windows for ADC treatment. The development of cyclodextrin-including protein conjugates, e.g., ADCs, would allow for improved modulation of biological targets, improved bioavailability, and improved therapeutic windows, particularly when lipophilic payloads are included in the ADC. Therefore, there is a continuing need for effective treatments of, for example, diseases using agents in cyclodextrin protein drug conjugates.


A fluid level switch for a machine having a fluid reservoir adapted to contain a fluid at an acceptable level. The fluid level switch includes a mounting plate, a float housing, and a float assembly positioned within the float housing. The mounting plate retains first and second contacts. The float housing is configured to receive fluid from the fluid reservoir and the float assembly is movable in response to the level of fluid in the float housing. The float assembly includes a contact member electrically connecting the first and second contacts when the level of the fluid is below the acceptable level. The contact member is coupled to the float for movement with the float and for movement relative to the float.

The present invention relates to fluid level sensors, and more specifically to low oil sensors for engines.
Fluid level sensors are generally used to determine the level of fluid retained within an enclosure. Some fluid level sensors activate an indicator when the fluid level decreases below a desired fluid level while others automatically shut off the system using the fluid.
In operation, fluid level sensors are positioned directly in a fluid reservoir, or within a smaller enclosure in fluid communication with the fluid reservoir. The enclosure maintains a fluid level proportional to the amount of fluid in the reservoir. One example of an application of a fluid level sensor is a sensor for the oil level within the crankcase of an internal combustion engine. The engine requires a desired amount of oil within the crankcase to properly lubricate the engine during operation. If the oil level is too low, the engine can be damaged due to improper lubrication. A fluid level sensor can be used to determine when the oil level within the crankcase is below a desired level.
Prior art systems often employ the use of a float within a housing to move with the level of fluid as the level of fluid changes. A sensor or an electrical contact can be positioned in the vicinity of the float and can be used to detect when the level of fluid is not within a desired range. The sensor or contact can communicate the condition of the fluid level through a indicator such as a warning light or by automatically shutting off the device that is using the fluid to operate. For example, the float can complete an electrical connection between a ground and an ignition contact to shut off the engine when the float is in a position indicative of low fluid or complete an electrical circuit for an audible indicator or visual indicator.
The use of such a system is generally reliable in shutting off the engine when a low amount of fluid is present. However, signaling a low fluid condition can be inconsistent due to the effect of the vibrations caused by moving parts of the engine, for example. This causes the fluid to move and splash around in the reservoir, thereby causing movement of the float and an unstable contact between the ground and ignition contact. This movement has the potential to prevent the float from grounding the ignition long enough to completely shut down the engine.


The present invention is directed to method and apparatus for wireless management of articles. The method is implemented by a master RFID tag. The method includes transmitting at least one first RFID read signal to a plurality of RFID tags local to the master RFID tag and receiving a first RFID response signal from each of the plurality of RFID tags in response to the at least one first RFID read signal. Each of the first RFID response signals comprises an identifier associated with an article. The method further includes maintaining an article record indicating at least one expected article that is to be managed by the master RFID tag and comparing each of the identifiers with the article record in an attempt to compile contextual information associated with the article record. Finally, the method further includes transmitting a master signal comprising the contextual information associated with the article record. Embodiments of the present invention are also directed to a master RFID tag comprising a first communication unit, a memory unit, a processing unit and a second communication unit.

Inventory and asset systems are rapidly moving towards wireless, electronic management of goods. Data associated with the goods, for example an identification number, is stored in the memory of an electronic tag, which is attached to the goods. In some instances, the tags are attached to individual items. In other instances, tags are attached to the cases in which the items are shipped or to the pallets on which the cases are stacked. In some instances, cases on a pallet are wrapped in plastic to retain the cases on the pallet, and the tags may be placed on the plastic rather than the pallet itself. The data stored in the memory may be wirelessly retrieved by placing the tag in the proximity of an electronic tag reader. The electronic tag reader wirelessly retrieves the data by transmitting a read request to the tag, and the tag responds by transmitting the data to the reader.
A Radio Frequency IDentification (RFID) system, composed of RFID tags and RFID readers, is one example of a wireless electronic tag system being used today. Indeed, RFID devices have changed the manner in which many companies manage inventory and assets. Further, specifically related to management of inventory, many companies now demand that their suppliers place RFID tags on all shipped goods, at the pallet level and/or the case level and/or the item level or a combination. RFID tagged goods which arrive at a warehouse are passed by an RFID reader, which wirelessly retrieves the data stored on the RFID tags. In many cases, a company will only pay a supplier for the goods once the RFID tag has been read, either at the case level or the item level.
An RFID reader requires a period of time to retrieve the data from the RFID tag. When RFID tagged goods arrive at a warehouse, the pallets on which the cases are stacked, are generally passed near an RFID reader, often for only a brief period of time. For example, in some instances, the pallet is passed near the RFID reader only while the pallet is being moved from one part of the warehouse to another. In some circumstances, the time period that the pallet is in the proximity of the RFID reader may be less than the time required by the RFID reader to retrieve the data from all the RFID tags on the pallet. Hence, the data received from a given RFID tag may be incomplete, resulting in an inaccurate inventory count. This may, in turn, lead to an incomplete, disputed or delayed payment transmitted between various entities involved in the shipment of the goods.
There remains a need therefore for an improved method and apparatus for wireless management of articles.

Method and apparatus for wireless management of articles


The image processing apparatus includes: an abnormality detection unit configured to detect one or more abnormalities included in a target image and an abnormality exclusion processing unit configured to exclude a specific abnormality from the detected one or more abnormalities. In a case in which a detection area of a certain abnormality among the detected one or more abnormalities and a detection area of another abnormality overlap with each other and a type of the certain abnormality and a type of the another abnormality are different from each other, when brightness information of one of the certain abnormality and the another abnormality satisfies a specific condition, the abnormality exclusion processing unit excludes the one of the certain abnormality and the another abnormality from the detected one or more abnormalities.

The present disclosure relates to an image processing apparatus, an image processing method, and a non-transitory computer readable recording medium storing an image processing program.
An image processing apparatus detects, based on an image obtained by scanning a print product, an abnormality such as an unintended streak, dot, or unevenness occurring in the print product output by an image forming apparatus such as a multifunction peripheral or a printer, and estimates a cause of occurrence of each abnormality.
In general, in a case where an attempt is made to easily detect an abnormality, over detection occurs, and an image that is not abnormal may be detected as an abnormality. Although the above-described image processing apparatus can detect an abnormality, there is a possibility that an over detected abnormality (false abnormality) is included in a detection result. In addition, since post-stage processing such as estimation of the cause of occurrence is performed for such a false abnormality, extra calculation cost is required.

Image processing apparatus, method, and computer program product excludes specific anomalies among detected anomalies


An artificial hand assembly for use in training manicurists has a base upon which the hand is mounted at an upwardly extending angle thereto. The hand has removable fingertips having artificial nails therein. In one embodiment the hand is movable with respect to the base about one axis. In another embodiment of the invention, the hand is movable with respect to the base about two axes normal to each other. In still another embodiment the hand is movable with respect to the base in any desired direction or orientation without regard to any discrete axis, by means of a ball and socket connection to the base.

Artificial hands are commonly used as prosthetic devices which may be made from molded plastic material, such as polyurethane, polyvinyl chloride, or molded foam rubber. For realistic appearance, dyes or other coloring material may impart the desired flesh tones. Artificial hands are also used in dolls or other models of humans. In these, as in other artificial hands for whatever purpose, the finger nails may comprise synthetic polymers or elastomers which can be made to resemble closely real finger nails. Another area in which artificial hands or feet are of considerable utility is the medical training field, one such example being shown in U.S. Pat. No. 5,853,293 of Weber, et al., which discloses an artificial or model foot to which various facsimiles of foot conditions may be removably attached. In addition, artificial toenails can be added or removed. The foot may comprise a polyurethane foam, foam rubber, or a fiber filled latex material. The nails may be made of a suitable elastomeric material.
In U.S. Pat. No. 4,403,442 of Blanc et al, there is shown an artificial doll's hand having extendable fingernails which are made of synthetic polymers which are similar to human cutaneous material. The doll's fingernails (and toe nails) may be manicured and painted and, when desired, pulled out and cut off, thereby exposing new un-manicured nails. A similar arrangement is shown in U.S. Pat. No. 3,691,679 of Kersten.
U.S. Pat. No. 4,661,187 of Beasley shows a prosthetic device, such as a finger having replaceable fingernails made of suitable acrylic material.
In the foregoing prior art arrangements, a realistic hand or other appendage is, especially in the case of prosthetic devices, highly desirable. Thus the device is preferably made of a material that imitates the human hand or foot in pliability and tint. Also, where nails are part of the device, acrylic materials can be made to achieve the desired similarity to human nails. An artificial hand for use as a training device instead of as a doll's hand or as a prosthetic device seems to be lacking in the prior art. Such a training device would be highly desirable for teaching student manicurists, for example.


An opportunistic storage service, or system, identifies currently unused storage capacity on a plurality of physical storage components of computing devices dispersed throughout a provider network. In some embodiments, the currently unused storage capacity is provisioned as primary storage, but is not currently being used to store primary storage data. The opportunistic storage service advertises at least a portion of the currently unused storage capacity as opportunistic storage capacity and provisions the opportunistic storage capacity subject to revocation if additional storage capacity of the physical storage components is needed to store primary storage data to fulfill a primary storage commitment.

The recent revolution in technologies for dynamically sharing virtualizations of hardware resources, software, and information storage across networks has increased the reliability, scalability, and cost efficiency of computing. More specifically, the ability to provide on demand virtual computing resources and storage resources through the advent of virtualization has enabled consumers of processing resources and storage resources to flexibly structure their computing and storage costs in response to immediately perceived computing and storage needs.
Virtualized computing environments are frequently supported by block-based storage, object-based storage, database services, and/or other virtual storage services. In some situations, virtual storage resources may be able to interact with various computing resources through a series of standardized storage calls. The standardized storage calls may render the computing resources agnostic to structural and functional details of the physical storage devices that implement the virtual storage resources.
In some systems, such virtualized storage resources may be implemented using remote physical storage devices that are connected over a network to computing resources for which they provide storage availability. In such systems, transaction volumes and transaction latencies for transactions between the computing resources and virtualized storage resources may be limited due to delays and limitations associated with transmitting data between the computing resources and the remote storage devices, or may be limited for other reasons. In other systems, physical storage devices and physical computing devices may be located local to one another and may be offered to clients as integrated compute and storage virtualizations. In such arrangements, capacities of the local physical storage devices may be reserved for use by computing virtualizations implemented using associated local computing devices. In such arrangements, a significant portion of the storage capacities of the local storage devices may be unutilized to store data when exclusively reserved for one or more local compute instances.
While embodiments are described herein by way of example for several embodiments and illustrative drawings, those skilled in the art will recognize that the embodiments are not limited to the embodiments or drawings described. It should be understood, that the drawings and detailed description thereto are not intended to limit embodiments to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description or the claims. As used throughout this application, the word "may" is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words "include", "including", and "includes" mean including, but not limited to.


Apparatus for treating a floor surface includes a wheeled vehicle having a floor surface treating unit, a drive motor operable to propel the wheeled vehicle and a control system for controlling operation of the apparatus. A handle is mounted on the wheeled vehicle and has a traverse switch unit for selectively operating the apparatus between a traverse mode in which the vehicle is propelled by the drive motor to move relative to the floor surface and an idle mode in which the drive motor is ineffective to propel the vehicle. The traverse switch unit is mounted on the handle such that the traverse switch unit is accessible for movement by the operator toward the first position of the traverse switch unit corresponding to the traverse mode of the apparatus without the operator having to generally release the handle.

This invention generally relates to apparatus, such as a floor scrubber, for treating a floor surface. In particular, the apparatus as herein disclosed is regarded as involving three distinct inventions, including an improved head assembly, an improved operating control system, and an improved squeegee assembly, the improved operating control system constituting the invention claimed herein.
Floor scrubbers are typically classified in terms of the cleaning path width defined by the laterally outermost extent of the scrub brushes relative to the forward direction of travel of the floor scrubber. Conventional floor scrubbers are manufactured to sweep a cleaning path of fixed width. Choosing the right floor scrubber depends largely on the floor space and obstructions in the floor plan of the area being cleaned. A scrubber having a large cleaning path width is used to clean large, open floor spaces while a scrubber having a narrower cleaning path width is used to scrub in tight areas and narrow isles.
Conventional floor scrubbers also have a control system in electrical connection with the various operating components of the scrubber. A handle is provided for grasping by the operator to maneuver the scrubber. The scrubbers are typically provided with a drive motor for self-propelling the scrubber to move over the floor surface being cleaned, and a traverse switch unit for operating the scrubber between an idle mode and a traverse mode in which the motor is operated to self-propel the scrubber. One disadvantage of these conventional floor scrubbers is that the traverse switch unit is mounted on the scrubber separate from the handle, requiring the operator to let go of the handle while switching the scrubber from the traverse mode to the idle mode, increasing the risk of impacting the scrubber into a wall or other obstacle.
Finally, conventional floor scrubbers typically include a squeegee assembly for sweeping dirty solution from the floor surface and directing the dirty solution to a recovery system that suctions the dirty solution from the floor surface, leaving a clean floor. One disadvantage associated with conventional floor scrubbers is that the blades of the squeegee assembly are secured thereto by multiple screw fasteners, making replacement of the blades time consuming and cumbersome. Also, the squeegee assemblies of these conventional floor scrubbers have guide wheels that extend radially outward beyond the lateral ends of the blades for guiding the assembly along walls. However, the guide wheels typically leave a gap between the blades and the wall so that dirty solution remains on the floor surface adjacent the wall.
Among the several objects and features of the present invention is the provision of improvements in an apparatus for treating a floor surface; the provision of such apparatus in which the control system permits the operator to switch operation of the scrubber between a traverse mode and an idle mode without letting go of the handle of the control system; the provision of such apparatus in which the control system permits the operator to switch operation of the scrubber between a forward direction of travel and a reverse direction of travel without letting go of the handle of the control system; and the provision of such apparatus having a control system that is easy to operate.
In general, apparatus of the present invention for treating the surface of a floor comprises a wheeled vehicle having a floor surface treating unit for treating the floor surface upon movement of the wheeled vehicle relative to the floor surface, and a drive motor operable to propel said wheeled vehicle relative to the floor surface. A control system for controlling operation of the apparatus comprises a handle mounted on the wheeled vehicle for being grasped by an operator to maneuver the vehicle relative to the floor surface. A traverse switch unit is movable between a first position corresponding to a traverse mode of the apparatus in which the vehicle is propelled by the drive motor to move relative to the floor surface and a second position corresponding to an idle mode of the apparatus in which the drive motor is ineffective to propel the vehicle to move relative to the floor surface. The traverse switch unit is mounted on the handle such that the traverse switch unit is accessible for movement by the operator toward the first position of the traverse switch unit corresponding to the traverse mode of the apparatus without the operator having to generally release the handle.
Other objects and features will be in part apparent and in part pointed out hereinafter.

Apparatus for treating a floor surface utilizing a handle mounted traverse switch


An MOSFET manufacturing method, comprising: etching an oxide layer and a silicon nitride layer on a first conductivity type well region, and forming an opening exposing the first conductivity type well region; etching the first conductivity type well region to form a first trench; depositing a medium oxide layer and performing back etching; etching the first conductivity type well region to form a second trench that is connected to the first trench, and forming a grid on an inner wall of the second trench, forming a second conductivity type well region in the first conductivity type well region at the bottom of the second trench, and forming a source in the second conductivity type well region; and removing the oxide layer and the silicon nitride layer, and forming a drain at the first conductivity type well region outside of the trench.

As the integration of semiconductor integrated circuits becomes higher and higher, the size requirements for a single power unit are becoming more and more stringent. Miniaturized design has become one of the important indicators to measure the technological development of electronic components. In traditional high-voltage lateral devices, such as a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET), a source terminal and a drain terminal thereof are arranged side by side on the same side of the device, resulting in a larger size of the device. Especially when it is necessary to increase the withstand voltage value or on-resistance of the device, in order not to increase the size of the device, a spacer is generally formed at the drain terminal through a spacer process, and the spacer is used to increase the withstand voltage. However, at present, the spacer is usually formed by processes of photolithography and etching, and the alignment accuracy of the photolithography will have a certain deviation, which makes a thickness of a left spacer and a thickness of a right spacer of the drain terminal inconsistent, and the asymmetry of the thickness of the spacers will affect a performance of the device such as changing a breakdown voltage of the device.


The invention comprises a Security Program (SP), a Simultaneous Approval Program (SAP), an Access Approval Program (AAP), and a Security Table (ST). A user's ability to access low security and high security applications depends on the user's security clearance, which is recorded in the ST. The SP limits a user's access to the applications. When a plurality of authorized users have logged in, the SP runs the SAP and AAP as required to allow the users to access and modify the high security applications. The SAP allows a user to modify the high security application only when a specified number of users approve the modification. The AAP allows a user to access a high security application only upon another user's approval. The SP terminates the users' access to the high security applications if one of the users logs out.

Each year the cost of dealing with security attacks on computer networks increases. Concomitantly, the frequency of security attacks on computer networks increases. Therefore, the need for improved computer network security also increases. A basic method for computer network security is to limit physical and electronic access to the computer network. Limiting physical access to a computer network has been accomplished by placing computers in the network in a secure physical location and then limiting access to the secure physical location by using security guards to ensure that only authorized persons enter the secured location. Limiting electronic access to a computer network has traditionally been accomplished by requiring entry of both a user name and a password at login.
However, as the need for security increases, so does the need for more sophisticated computer network security systems. One type of physical security measure that has been effective in the military, financial, and governmental sectors is simultaneous turnkey authorization. Simultaneous turnkey authorization occurs when two people, each having a unique key, simultaneously insert, and turn their unique keys in order to indicate their dual approval of an action. The unique keys usually fit into locking cylinders which are far enough apart to prevent the same person from simultaneously turning both keys. A need exists for a method of taking the inherent double layer of physical security achieved by simultaneous turnkey authorization and applying the double layer of security electronically in a computer network.
A second physical security method is to require approval of actions or modifications to a sensitive or crucial system. In this type of security precaution, one person prepares and signs a transaction document and, at a later time, a second person reviews the document and indicates approval by also signing the document. The time delay in the subsequent review and approval provides an opportunity for the first person to identify gaps in the security which he may later exploit. Therefore, a need exists for an improvement in a dual signature method of security that provides real-time approval and accountability while preventing exposure of the security system to analysis by someone seeking to defeat the security system.
Another physical security method is to always have at least two people present when accessing a high security application. The dual access requirement deters wrongdoers with the knowledge that someone else will be aware of their access to the high security application. The second person is physically present and can monitor the first person's navigation of the high security application. Moreover, the second person who is physically present can approve any changes and or modification made by the first person. To this end, a need exists for a method of applying the physical security principle of dual access to electronic access in a computer network. A need also exists for a method of allowing the approving person to electronically monitor the accessing person's navigation of the high security application.
The prior art has previously attempted to solve the needs identified above. For example, U.S. Pat. No. 5,774,051 (hereinafter, the '051 patent) discloses a method of activating an alarm in which a pair of keys are simultaneously actuated. The '051 patent discloses a method for indicating alternative modes of operation by repeatedly actuating a single key. However, what is needed beyond the '051 patent is a method and apparatus for limiting access to high security applications and requiring simultaneous approval of any modifications to the high security applications.

International Business Machines Corporation


An insulated-gate transistor signal input device includes an insulating substrate, a first clock line formed on the insulating substrate to receive a clock signal externally supplied, a clock buffer formed on the insulating substrate to process the clock signal supplied from the first clock line, a second clock line formed on the insulating substrate to input a signal obtained from the clock buffer to a shift register serving as a load circuit formed on the insulating substrate. The insulated-gate transistor signal input device further includes a first protection diode circuit connected to the first clock line to remove electrostatic charge from the first clock line, and a second protection diode circuit connected to the second clock line to remove electrostatic charge from the second clock line.

This invention relates to an insulated-gate transistor signal input device formed on an insulating substrate such as an array substrate incorporated in a liquid-crystal display device.
A typical active matrix liquid-crystal display device includes an array substrate in which pixel electrodes are arrayed in a matrix form, a counter substrate in which a counter electrode is formed to face the pixel electrodes, and a liquid-crystal layer held between the array substrate and counter substrate. The pixel electrodes are connected to a liquid-crystal driving circuit placed outside the array substrate, via the switching elements which are formed on the array substrate together with the pixel electrodes.
The switching element is constituted by an insulated-gate transistor such as a thin-film transistor (TFT) which has an insulated gate and a semiconductor layer formed on the array substrate. In recent years, there is a case where the liquid-crystal driving circuit is formed on the array substrate. In this case, the liquid-crystal driving circuit is formed as an insulated-gate transistor circuit constituted by a group of thin-film transistors having the same structure as that of the switching element.
When the array substrate has been electrostatically charged in the process of manufacturing the liquid-crystal display device, the insulated-gate transistor tends to be damaged or destroyed due to a surge voltage applied thereto according to the electrostatic charge.
For example, Jpn. Pat. Appln. KOKAI Publication No. 6-51346 and Jpn. Pat. Appln. KOKAI Publication No. 9-80471 disclose a protection diode circuit disposed near an Outer Lead-Bonding (OLB) pad to protect insulated-gate transistors from destruction caused by electrostatic charge applied from the OLB pad.
FIG. 1 shows a conventional liquid-crystal driving circuit in which the protection diode circuit disposed near an OLB pad for inputting a clock signal. In the liquid-crystal driving circuit, the clock signal is supplied from an OLB pad 41 through a clock line LlN to a clock buffer 42, and then from the clock buffer 42 through a clock line L2N to a driver section DR. The clock buffer 42 has a series of inverters 41-1, 42-2, . . . , 42-n each constituted by p- and n-channel thin-film transistors, and performs a process of driving, in response to the clock signal, the total load capacitance of the clock line extending into the driver section DR.
A protection diode circuit DiN is constituted by a pair of p-channel thin-film transistors Tr1 and Tr2 whose current paths are connected in series between a power source line VDD and the clock line L1N and a pair of n-channel thin-film transistors Tr3 and Tr4 whose current paths are connected in series between a ground line GND and the clock line L1N. Each of the thin-film transistors Tr1, Tr2, Tr3 and Tr4 has a gate electrode connected to an end of the current path and constitute a diode reverse-biased by the power source voltage.
With the liquid-crystal driving circuit, the protection diode circuit D1N removes electrostatic charge applied from the OLB pad 41. Specifically, when the thin-film transistors Tr1 and Tr2 or thin-film transistors Tr3 and Tr4 are forward-biased by the electrostatic charge, they are turned on to remove the electrostatic charge to the power source line VDD or ground line GND. However, the clock line L2N is electrically separated from the clock line L1N by the gate insulating films of the thin-film transistors of the clock buffer 42, the protection diode circuit D1N cannot remove electrostatic charge applied to the clock line L2N. As a result, a thin-film transistor of the clock buffer 42 connected to the clock line L2N is damaged by the electrostatic charge. In this case, not only the reliability of the liquid-crystal driving circuit but also that of the liquid-crystal display device is impaired seriously. Furthermore, when the thin-film transistor of the clock buffer 42 is destroyed electrostatically, this leads to a decrease in the yield of the liquid-crystal display device.

Insulated-gate transistor signal input device


Technologies are generally described for dynamically distributing a processing load. In some examples, a method performed under control of a server may include receiving information regarding load distribution from an end device and dynamically distributing a processing load between the server and the end device based at least in part on the information regarding load distribution.

A graphics processing unit (GPU) is a specialized electronic circuit designed to rapidly manipulate and alter memory in order to accelerate the building of images in a frame buffer intended for output to a display. The GPU may be used in embedded systems, mobile phones, personal computers, workstations, game servers, game consoles, and the like. Rendering and encoding processes may be carried out on servers and/or end devices equipped with a GPU, such as mobile phones, personal computers, or game consoles.


A system for modeling computer software product line variants may include a model builder configured to construct a model of a plurality of variants of a computer software application. The model may include at least one common-to-variants element that may be common to a plurality of the variants, a plurality of variant-specific elements, and interface code configured to adapt any of the variant-specific elements to any of the common-to-variants elements. The model may further include an application generator configured to generate a plurality of computer software applications for a corresponding plurality of combinations of the common-to-variants elements and the variant-specific elements, where the model builder and the application generator may be implemented in at least one of computer hardware and computer software embodied in a tangible computer-readable storage medium.

The present disclosure relates generally to tools and techniques for modeling and generating computer software applications, and more particularly to modeling and generating variants thereof.
Computer software applications may be developed as variations of a base application that may correspond to distinct product lines in a product family. As application developers may become increasingly dependent on modeling tools that may support modeling computer software applications using paradigms such as the Unified Modeling Language (UML), as well as tools that may generate source code or executable code from such models, there may be a need to define product lines and their variations in a single model, and to do so in a way that may support the generation of code for each distinct product line.

Modeling and generating computer software product line variants


A system, an apparatus, and a method are provided for a modular flow cytometer with a compact size. In one embodiment, the modular flow cytometry system includes the following: a laser system for emitting laser beams; a flow cell assembly positioned to receive the laser beams at an interrogation region of a fluidics stream where fluoresced cells scatter the laser beams into fluorescent light; a fiber assembly positioned to collect the fluorescent light; and a grating system including a dispersive element and a receiver assembly, wherein the dispersive element is positioned to receive the fluorescent light from the fiber assembly and to direct spectrally dispersed light toward the receiver assembly.

A flow cytometer is a biological cell (bio-cell) analysis and counting instrument. It is used to analyze the physical and chemical characteristics of bio-cells in a fluid as they pass through one or more laser beams from lasers. The bio-cells are fluorescently labeled and then excited by the lasers to emit light at correspondent wavelengths. The fluorescence and the scattered light can be detected and measured to determine various properties of the cells. Up to thousands of cells per second can be analyzed by a flow cytometer.
Generally, a flow cytometer includes components of fluidics, optics and electronics. The fluidics system is to line up and transport cells in a stream of fluid to the laser beams where they are excited. Any cell of submicron to over 100-μm in size can be analyzed. The optics system consists of lasers which excite the cells in the stream and get scattered. Fluorescent labeled cells emit fluorescence, which is collected by a lens. The laser light scattered by the cells is captured at forward and side directions. Optical steering mirrors direct the light signals to the correspondent detectors, such as a photomultiplier tube (PMT), an avalanche photodiode (APD) or a PIN diode (diode with a wide, undoped intrinsic semiconductor region between a p-type semiconductor and an n-type semiconductor region). An electronics system converts the light signals detected into electronic signals for a computer to process. Data are collected on each cell. The characteristics of the cells are determined based on their fluorescent and light scattering properties. A large number of cells are analyzed to draw information on the heterogeneity and different subsets within the cell populations. The data are usually presented in the form of single parameter histograms or as plots of correlated parameters, which are referred to as cytograms, displaying data in the form of a dot plot, a contour plot, or a density plot.
Flow cytometry has been widely used in the diagnosis of leukemia and human immunodeficiency virus (HIV). Flow cytometry is also commonly used in basic research and clinical trials, such as molecular biology, immunology, and pathology. Flow cytometry has become an important lab process in transplantation, oncology, hematology, genetics and prenatal diagnosis. Flow cytometry can also be used to help identify cell surface protein variants.
Conventional flow cytometers are large in size due to their complicated system construction. Bench top space is always precious in a lab, especially when many diagnostic instruments compete for presence in the lab and the many tests that must be accommodated to service the various clients and patients. In a single core lab, there are normally many flow cytometers deployed for service where the size of the flow cytometer becomes of greater concern.