Molten metal dispensed upon the surface of an adjacent rotating drum produces a ribbon of solidified metal which separates from the drum while the drum is rotating. To prevent ripples from forming in the surface of the ribbon, a casting surface on the periphery of the rotating drum includes structure to minimize the ratio of transverse heat flow rate from the casting surface to radial heat flow rate.

Apparatus and processes for forming wires, sheets, strips, flakes, etc. by contacting molten metal with a rotating disk or drum are well established in the field and U.S. Pat. Nos. 4,705,095 and 4,813,472 are illustrative of techniques used to achieve the desired result. The terms ribbon, sheet and strip are often used interchangeably.
U.S. Pat. No. 4,705,095 deals with the structure of a casting surface on a rotating drum which is configured to allow relatively fast rotation of the drum for the rapid solidification of a cast metal ribbon sheet. That invention is directed to a knurled surface for the casting area on the rotating drum which prevents air bubbles from being trapped between the molten metal and the casting surface as the drum rotates. U.S. Pat. No. 4,813,472 is directed to melt overflow structures for feeding the molten metal to the cylindrical casting wheel.
A problem exists in the formation of metal strip in the fashion disclosed by these patents and others in the field. The problem is the formation of rippled or wavy edges along the opposite sides of the strip resulting from the rapid freezing process. Often ripples are so acute that the finished product must be passed between pinch rollers to smooth the surface. This is obviously time consuming and expensive. In an attempt to solve this problem, Applicant has theorized the ripples result from differential cooling of the metal transversely across the strip.
Casting drums or wheels used in the rapid solidification industry are traditionally formed to be hollow and within the hollow cavity is water or some other cooling fluid. The cooling fluid serves as a heat sink to draw off heat from the casting surface to keep it at a temperature sufficiently low to freeze the molten metal almost immediately upon contact.
It is accepted heat transfer theory that application of heat at a point on a body results in heat flowing in all directions in the body until the body achieves near uniform temperature. With the rotating casting surface, the edges of the cast metal sheet are believed to cool much faster than the central portion of the strip. Heat from the edge areas of the strip flows through the drum, both radially inwardly toward the water and transversely parallel to the metal cylindrical surface of the drum toward the ends thereof. Conversely, heat extracted from the center region of the strip flows essentially only radially inwardly toward the water in the hollow drum. Along most of the width of the strip being cast, heat conduction is confined principally to radial heat flow through the casting drum with edge effects near the edges where there is a progressively increasing transverse component of heat flow. The result is that the edges freeze first. Then the central portion freezes undergoing the usual contraction during cooling which longitudinally compresses the ribbon, creating residual stresses and compressing the already cooler edges into a wavy pattern.

Strip forming apparatus for rapid solidification


A network tap monitors network information flow over a particular connection. By duplicating the signal and diverting a copy, the information flow can be analyzed, both in real time and without interference through the monitoring process. When the power to the tap is either turned on or off, however, the change in impedance in the tap's circuit can create an interference spike in the connection that interrupts the information flow. By reducing or eliminating the impedance change in the tap circuitry, such disruptive interruptions can be eliminated.

1.A. Field of the Invention
The explosive growth of intercommunication between computers over the Internet has created a consequential need for means to monitor networks while they are working, in order to assure that the communication flows stay within acceptable limits of both speed and quality. To assure and measure a network's connections, the communications flowing through them must be monitored and the communication flow subjected to analysis.
Monitoring and analyzing the communication flows requires both physical and logical assessment. Physical assessment must test each of the several criteria (e.g. voltage drop, baud, clarity) that define a particular connection's physical constraints; while logical assessment must similarly test each of the several criteria (e.g. routing, authorization, timing) that define a particular communication's logical constraints. Recently it has become a normal procedure to tap into the signal flow over a connection being analyzed.
One problem that had to be solved, for both electrical/copper and optical/fiber connections, was how to tap into the communication flow without interfering with the traffic that was passing through the connection being tapped. Physically, any tap potentially creates interference (either from a drop in potential or timing delay); logically, a tap could become an unsought and unwanted network termination. In perhaps no other field is the Heisenberg principle (that the act of observation changes the behavior of whatever is being observed) more keenly felt. As the signal speed and sensitivity of communications and especially computer networks increased, the interference potential from any tap also went up, in linear, locked progression.
Generally, network taps need only be consulted a small portion of the time. The problem was that every time a tap's power was turned on or off, it would send a disruptive 'spike' through the communications flow, interrupting the process and requiring a retransmission of the temporarily-disrupted data. Leaving a tap permanently turned on, however, both increased the power consumption of the network as a whole and put additional usage time on the tap, potentially reducing its service life. The network needed taps to be available on call rather than continuously, but also needed taps which could be powered on or off without interfering with the communications flow.
1.B. Description of the Related Art
In the field of monitoring network performance, the prior art has focused on the development, and uses, of network taps devoted to analytical purpose and monitoring of the communications flow. The stabler a network the less it needs a tap to monitor non-existent problems; yet the more taps that are tuned in can create disruptive interference and interruption when they are turned on or off.
This is particularly crucial when taps must be turned on and off to properly assess and evaluate intermittent, context-dependent, or transient signal interference effects; or identifying and prioritizing sub-network stability. It is also important in the longer context as part of an ongoing management effort to train, maintain, and sustain a continuous and uninterrupted network communications flow where the periphery and set of connections will change over time, without disrupting the overall structure and process. For these and other reasons apparent to those skilled in the art, taps needed to be such that they could be turned on and off. Yet each time they were, they created an interruption which reduced the overall network capability.
With the increase in network traffic has also come an increase in the number, and differing natures, of problems which can afflict a network. The Internet in particular uses a packet-based protocol which presumes both a constantly changing set of network connections and that each connection is only semi-dependable. Signals can be mis-addressed, mis-routed, mis-timed, disordered, degraded, or otherwise interfered with. Connections can be formed, dropped, spoofed, or otherwise be imperfect; and they definitely change over time—sometimes, over a very short time indeed. The more taps, the better the monitoring could be, but the greater the overall drain on the network's power from just the taps would be. The prior art simply accepted the "fact" that turning a tap's power on or off generated a microsecond delay, which seemed to be fine—until we reached the age of gigabit, high-speed, and broadband network transmissions.
The prior art used a switching approach to turn on and off both the power to the monitoring network tap and to redirect the communication flow through the network tap and the attached monitoring device(s). Up until now, people simply designed into their networks an acceptance that a price of using a tap was the fact that every time the tap's power was turned on or off, there would be a microsecond delay and a signal-damaging spike caused by the impedance change to the circuit as a whole as the communications flow was switched.


A method and device for recording sequence information on biological compounds such as nucleotides and amino acids in as small amounts of data as possible are provided. The text data representing the sequence of a series of nucleotides constituting the DNA of the standard sample E is converted into binary data using a conversion table, and the binary data is divided into plural m-bit partial data (A(i,j)) arranged in plural columns and rows (m≧16). Then a first set of parities (B1(i)˜B3(i)) are computed by applying an operation of Galois field GF(2m) to the partial data (A(i,j)) of each column and a second set of parities (C1(j)˜C3(j)) are computed by applying an operation of Galois field GF(2m) to the partial data (A(i,j)) of each row. The sequence of the nucleotides is represented approximately by the parity information.

The sequences of nucleotides (or bases) in pairs of polymer strands constituting the DNA molecules of humans and other organisms (animals, plants, microorganisms, etc.) are being deciphered worldwide. In order to record the deciphered nucleotide sequences, four kinds of nucleotides which constitute DNA are expressed in four different one-byte (eight-bit) text data by allocating the character A, G, C, or T for the nucleotide including adenine, guanine, cytosine, or thymine respectively as the nitrogenous base. Consequently, sequence information on DNA which consists of two polymer strands with each strand comprising n (n is an integer) nucleotides is represented in n-byte text data by expressing each nucleotide of one strand one by one as the corresponding character selected from the four characters A, G, C, and T (or a, g, c, and t). Similarly, the sequence of n nucleotides constituting an RNA molecule is recorded in n-byte text data by allocating the character A, G, C, or U (or a, g, c, or u) for the nucleotide including adenine, guanine, cytosine, or uracil respectively.
In the case of humans, since each chain of the DNA molecules in the first or largest chromosome and in the 22nd or smallest one is a sequence of nearly 250,000,000 and 50,000,000 nucleotides respectively, the nucleotide sequence of the DNA in each chromosome can be expressed in about 250-50 MB text data. In addition, since the human genome (all DNA information) is expressed as the sequence of nearly 3,000,000,000 nucleotides, it is recorded in about 3 GB text data. For practical uses, the original text data may be recorded or transmitted as a compressed file of about half the size of the original data by applying the conventional file compression techniques.
Following the decipherment of nucleotide sequences of DNA, the functions of the proteins synthesized according to the genes in DNA are widely researched. In these researches, the sequence of a protein molecule which consists of n amino acids is represented by n-byte text data since each of 20 kinds of amino acids constituting protein molecules is expressed as the text data of three characters (for example, Ala, Cys, Glu, etc.) in three-Letter Code or one character (for example, A, C, E, etc.) in one-Letter Code. As ordinary proteins consist of the sequence of nearly 20 to 1000 amino acids, each of the sequences of those proteins may be recorded in about 1 KB text data, at the most. Moreover, it is estimated that there are nearly 30,000 human genes in total and there may be nearly 100,000 kinds of protein molecules including theoretical ones.
As described above, in order to record the human genome in the form of text data, about 3 GB of memory is necessary. Even if the conventional file compression techniques are employed, nearly 1 GB of memory may be needed. Recently, DNA sequences of living organisms other than humans such as colon bacilli and various viruses are also disclosed to the public. If these DNA sequences are collected in text data, we may need several hundred MB of memory for each of those organisms. Such is the case in recording sequence information on RNA.
Thus, when information on DNA sequences of humans or other organisms is recorded in the form of text files or the conventional compressed files, the recording medium with huge memory capacity such as a DVD-ROM disk capable of recording nearly 5 GB data is necessary. There is additionally an inconvenience that both the time needed for reading sequence information from the recording medium and the time needed for processing sequence information are long.
Moreover, since the transmission rate of the current general communications network is about 5 Mbps, when we transmit information on DNA sequences of the size of, for example, 1 GB via the communications network, the transmission time will be around thirty minutes. Especially recently the digital cellular phone system is being widespread as a communications medium. It may however be difficult to use it to transmit at least the DNA sequence information of humans since the transmission rate of the present cellular phone system is as low as nearly 1 Mbps.
There is also a problem of how to assure that the nucleotide sequences, which are assumed to be equal and held by two or more researchers as a standard sequence, are really equal. This happens, for example, when genes in the DNA of a certain microorganism are studied by the researchers. That is, it is not necessarily easy for two or more researchers to mutually verify in a short time that their text data expressing the nucleotide sequence of the DNA are completely equal when each of their text data has several MB data (data for several million characters).
In this connection, as a use of information on DNA sequences of humans or other organisms, we can think of a task to search the difference between a standard DNA sequence and a sample DNA sequence. Such a task will be needed when the SNP (Single Nucleotide Polymorphism) is searched. However, there is an inconvenience that a relatively long time is needed to compare the two text data and search the difference between them when both text data represent the huge nucleotide sequence of DNA.
Furthermore, a new business has started in which several suppliers offer many pieces of information on DNA sequences to users such as researchers of the pharmaceutical companies. In the business it is preferable for the suppliers to avoid offering overlapping information to the users. It is thus convenient for the users to be able to check easily whether the nucleotide sequences of DNA offered by the plural suppliers are equal or not without disclosing the entire information on the nucleotide sequences to the public. In addition, when the suppliers offer the users the DNA information through, for example, a communications network, a business model is needed in which necessary information can be transmitted to the users in as less data as possible so as to shorten the transmission time. Moreover, it is preferable that the users can easily check whether the offered DNA information contains transmission errors, etc. The above-mentioned problems are included similarly in treating information on nucleotide sequences of RNA.
In addition, the amino acid sequence of a protein is recorded by the text data of about 1 KB at the most and there are about 100,000 kinds of proteins including theoretical ones. Thus, if we express sequence information on all kinds of proteins in the form of text data, we will have a large amount of data. Accordingly, it is preferable to record the sequence of each protein in as less data as possible and we need a system by which we can easily verify whether two pieces of sequence information on proteins are equal.
It is therefore an object of the present invention to provide a method and device for recording approximate small amounts of data of sequence information on biological compounds such as a set of nucleotides of nucleic acids or a set of amino acids of proteins.
It is a second object of the invention to provide a method and device for detecting the difference between two pieces of sequence information on biological compounds by a small amount of data and, if necessary, recovering the difference.
It is a third object of the invention to provide a business model (or a method for supplying information) for making a user easily verify whether the user's data and the supplier's original data are equal and detect the difference between them using a small amount of data when supplying sequence information on biological compounds such as a set of nucleotides or a set of amino acids to the user.
It is a fourth object of the invention to provide a computer-readable medium in which approximate information on sequences of biological compounds is recorded with a small amount of data.

Method and device for recording sequence information on biological compounds


According to one embodiment, an electronic apparatus includes an interface circuit connectable to a first signal line, a second signal line, and a third signal line, and a controller. Before transmitting data using the first signal line, the controller is configured to transmit a first command using the first signal line while transmitting a first control signal using the second signal line, and transmit a first address using the first signal line while transmitting a second control signal using the third signal line. While transmitting the data using the first signal line, the controller is configured to transmit at least one of a second command and a second address using the second signal line and the third signal line.

An example of a storage device includes a solid-state drive (SSD). The SSD includes a nonvolatile memory (for example, NAND flash memory) and a memory controller. The toggle interface is used as an interface between the memory controller and the nonvolatile memory.
In the toggle interface, a command (and an address), and data are transferred by an I/O signal line. The I/O signal line is shared for command (and address) transfer and data transfer. Therefore, it is not possible to transfer the command (and the address) between the memory controller and the nonvolatile memory during the data transfer. Similarly, it is not possible to transfer the data during the command (and the address) transfer.
When a host transmits a read request or a write request to the SSD during the data transfer, issuing of a command from the memory controller to the nonvolatile memory is delayed until the data transfer is completed. A performance of the SSD is lowered by the latency.

Electronic apparatus and transfer method


One aspect of the present disclosure provides an electric working machine. The electric working machine includes a driver, a motor, and a control circuit. Attached to the driver is a selected tool. The motor drives the selected tool attached to the driver. The control circuit sets a target rotational frequency based on the selected tool. The control circuit controls the motor to rotate at the target rotational frequency.

The present disclosure relates to an electric working machine to which at least a first tool and a second tool are selectively attached.
Japanese Patent No. 6357116 discloses a brush cutter provided with an automatic speed shifting function by which a target rotational frequency of an electric motor is changed in two or more stages in accordance with a load imposed on the electric motor that drives a rotary blade. This brush cutter can rotate the rotary blade at a suitable rotational frequency in accordance with the load and reduce unnecessary power consumption.

Electric working machine and method for controlling motor of electric working machine


A system for the nondestructive evaluation of aircraft comprising a plurality of positional transmitters forming a perimeter around a test airplane and an inspection station within the perimeter. The inspection station includes a moveable cart, a nondestructive testing device coupled the cart, and a computer coupled to the cart and nondestructive testing device. The computer configured to receive aircraft positional data from positional receivers mounted on an aircraft and overlay a model of the aircraft on the received aircraft positional data to determine a coordinate system for the aircraft. The computer is further operable to determine the location of the cart from data received from onboard positional receivers, the location of the cart referenced to the coordinate system for the aircraft.

The periodic, nondestructive testing of large structures, such as passenger vehicles, is important to assist in the evaluation of structural integrity. For example, aircraft undergo nondestructive testing in order to detect structural variations or changes such as structural fatigue. An example of a aircraft component that is periodically inspected for structural changes or variations is the outer surface of the fuselage. However, the size of the fuselage makes nondestructive testing a difficult undertaking.
One approach used for nondestructive testing of an aircraft fuselage and other large structures involves a trained operator performing tests with portable equipment. This approach has a number of drawbacks including that it is a slow process and requires a specially trained individual. Another approach used for the nondestructive testing of large structures utilizes a robotic vehicle. The robotic vehicle automatically maneuvers itself to the test subject and performs nondestructive testing at various points on the test subject. However, this degree of automation results in high costs and complex systems. Additionally, the proper mounting and alignment of testing devices is difficult.
In view of the foregoing, it is desirable to provide a method for navigating a nondestructive evaluation device that addresses one or more of the foregoing deficiencies or other deficiencies not implicitly or expressly described. It is also desirable to provide an apparatus for navigating a nondestructive evaluation device that addresses one or more of the foregoing deficiencies or other deficiencies not implicitly or expressly described. Furthermore, other desirable factors and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

Method and system for navigating a nondestructive evaluation device


Disclosed is a data output buffer having a preset structure. The data output buffer comprises a plurality of groups, each group having two data output buffers, a preset driver for precharging or discharging any one output of two output buffers in each group, a control circuit for generating a control signal to drive the preset driver when outputs of the two output buffers in each group are same, and a set circuit connected between the outputs of the two data output buffers in each group, for making the outputs of the two data output buffer in each group the same level. Therefore, a data output speed of the data output buffer could be improved and the peak current could be also reduced.

1. Field of the Invention
The present invention relates to a data output buffer for semiconductor devices, and more particularly, to a data output buffer having a present structure.
2. Background of the Related Art
FIG. 1 is a block diagram for generating a control signal for use in semiconductor devices.
An address transition detecting unit 10 senses when an inputted address is shifted to generate an address transition detection signal atd. An equalization signal generating circuit 20 generates an equalization signal peq according to the address transition detection signal atd. A control and delay circuit 30 generates various control signals and delay signals (peqdly, poe . . . ) according to the inputted equalization signal peq.
FIG. 2 is a detailed circuit diagram of a conventional data output buffer. The operation of the data output buffer will be described by reference to FIG. 3. In FIG. 3, an address Add, a chip select signal/CS, an output enable signal/OE and a write enable signal/WE are signals used for the operation of the common semiconductor memory devices.
FIG. 2 has a structure in which in a given period of time after transition of an address is detected in a read operation and a read cycle then begins, a data sodin from a sense amplifier (not shown) reaches a data output buffer and at once a pulse output enable signal poe operates the data output buffer, which then outputs a data. This will be described in detail below.
If the read operation begins, the output signal sodin of the sense amplifier reaches the data output buffer. As the pulse output enable signal poe through inverters I1 and I2 is at a LOW level, that is, the outputs of NAND gates ND1 and ND2 are at HIGH levels in a standby mode, PMOS and NMOS transistors P1 and N1 are turned off. Thus, the output dout is changed to a HIGH impedance level by an external termination circuit 40. Thereafter, if the pulse output enable signal poe becomes HIGH, the output sodin of the sense amplifier is transferred to the output dout. If the output sodin of the sense amplifier is HIGH, the output of the NAND gate ND1 becomes LOW. The signal of the LOW level is applied to the gate terminal of the PMOS transistor P1 via the inverters I3 and I4. Accordingly, the PMOS transistor P1 is turned on, so that the output dout becomes HIGH.
On the contrary, the output of the NAND gate ND2 becomes HIGH. The signal of the HIGH level is inverted by the inverter 16 and is then applied to the gate terminal of the NMOS transistor N1. Therefore, the NMOS transistor N1 is turned off.
This type of the data output buffer has an external load and a rapid read cycle. Furthermore, if this data output buffer has to output data opposite to data of the previous cycle, the output dout must largely swing from 0V to Vcc. Therefore, there is a possibility that noise may occur due to delayed speed and increased peak current. In particular, if the data output buffer is constructed in a wide bit and has to output a plurality of data at the same time, the output dout is changed from a LOW level to a HIGH level or HIGH level to LOW level. Therefore, generation of noise due to increased peak current is inevitable.
Accordingly, the present invention is contrived to substantially obviate one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a data output buffer having a preset structure in which the output of the data output buffer is preset to an intermediate level in advance and is then converted to an effective data level depending on an input data.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a data output buffer having a preset structure according to the present invention is characterized in that it comprises a plurality of groups, each group having two data output buffers, a preset driver for precharging or discharging any one output of two output buffers in each group, a control circuit for generating a control signal to drive the preset driver when outputs of the two output buffers in each group are same, and a set circuit connected between the outputs of the two data output buffers in each group, for making the outputs of the two data output buffer in each group the same level.
In another aspect of the present invention, it is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Data output buffer having a preset structure


A specimen container includes a specimen storing portion for storing a specimen, wherein the specimen storing portion is provided with an opening on an upper end, a sealing member for sealing the opening, wherein the sealing member is enabled to be passed through by a suction tube for sucking a specimen stored in the specimen storing portion, and a cylindrical portion having a predetermined height to allow insertion of the suction tube, wherein the cylindrical portion is arranged in series with the specimen storing portion on a side provided with the opening.

1. Field of the Invention
The present invention relates to a specimen container for storing a specimen such as blood employed in the field of clinical tests or the like, and more particularly, it relates to a specimen container storing a small quantity of specimen such as a control sample employed for quality control of an automatic analyzer.
2. Description of the Background Art
Specimen measurement from transport of a specimen to pretreatment and multiple measurement has become automated with recent increase in the measurement number of patient specimens in the field of clinical tests. Measurement of a control sample for performing quality control of an automatic analyzer also has become automated.
In a case where quality control is performed in an automatic analyzer such as an automatic blood cell counter, a control sample such as control blood is stored in a predetermined specimen container to be used. The specimen container storing the control sample is placed on a specimen rack together with a plurality of specimen containers storing the patient specimens and is provided to the automatic analyzer. A bar code label for identifying the patient specimen is stuck on each specimen container storing the patient specimen, and a bar code label for identifying the control sample is stuck on the specimen container storing the control sample. The bar codes of these bar code labels stuck on the specimen containers are read by a bar code reader of the automatic analyzer, and it is identified whether the specimen stored in the specimen container is the patient specimen or the control sample.
At the time of measurement, in order to uniformly disperse components such as blood cells in the specimen container, the blood cells and the like in the specimen container are stirred. Thereafter, a suction tube is inserted into the specimen container, and sample suction and component measurement such as counting of the blood cells are performed.
A small quantity of the control sample is enough as the quantity of the specimen required for the measurement as compared with that of the patient specimen, and hence a volume of a normal specimen container is too large for the quantity of the control sample. Thus, when the control sample stored in the normal specimen container is stirred, the moving quantity of the control sample in the specimen container is increased. Consequently, there is a possibility that the specimen is damaged. The control sample is used (measured) a plurality of times dissimilarly to the patient specimen measured only once. Thus, the control sample is damaged due to stirring at the plurality of times, and this can greatly affect quality of the control sample. The volume of the specimen container is large as compared with the quantity of the control sample, and hence the rate of the control sample adhering and remaining on an inner surface of the specimen container is increased. Consequently, the stirring is conceivably insufficient.
When the specimen container itself is downsized depending on the quantity of the control sample, on the other hand, the size of the specimen container is different from that of the normal specimen container, and hence there is a possibility that a measuring operation such as stirring or suction can not be performed in a manner similar to that of the normal specimen container storing the patient specimen. Thus, an inconvenience that the control sample can not be automatically measured is caused. Further, an area for sticking the bar code label on an outer side surface of the specimen container can not be ensured, and whether the specimen stored in the specimen container is the patient specimen or the control sample can not be automatically identified by the bar code. This also makes automatic analysis difficult.
Japanese Utility Model Laying-Open No. 5-36364 discloses an invention of a "specimen container" as a container for storing a small quantity of specimen. This specimen container is a specimen container constituted by a cap and a cylindrical container body opened/closed by the cap and having an outer shape similar to the normal specimen container, in which a bottom of the container body is formed in the middle of the cylindrical body. In other words, the specimen container has a so-called push-up bottom, and the volume of storing the sample is smaller than that of the normal specimen container. According to this structure, the moving quantity of the sample in the specimen container is small even when a small quantity of the specimen is stored and stirred, and hence damage to the specimen is reduced. The outer shape of the specimen container is not downsized, and hence the specimen in the specimen container can be stirred in a manner similar to that performed for the normal specimen container by the automatic analyzer, and the area for sticking the bar code label can be ensured on the outer side surface.
In the aforementioned specimen container described in Japanese Utility Model Laying-Open No. 5-36364, however, while the specimen in the specimen container can be stirred in the manner similar to that performed for the normal specimen container and the bar code label can be stuck, the specimen container is formed to have the push-up bottom shape and hence a forward end of the suction tube may collide with the push-up bottom portion when the suction tube is inserted from above by the automatic analyzer. In order to avoid such a problem, means for adjusting a depth for inserting the suction tube depending on the shape of the specimen container is required and a structure of the analyzer is complicated.
Thus, in a case of a small quantity of the specimen sample, reduction in the volume of the specimen container is demanded in order not to damage and ununiformly stir the specimen sample. Further, the depth of the specimen container must be ensured so as not to collide with the bottom portion of the suction tube, while ensuring a height enough to smoothly perform the operation such as stirring by the automatic analyzer. The specimen container satisfying all of these demands is desired.


A floating contact assembly for use in a circuit breaker includes a contact, a floating member, a bearing element, a jaw member, and a flexible conductor. The floating member includes a joint surface and the contact is electrically connected to a surface of the floating member opposite the joint surface. The bearing element is configured to abut the joint surface of the floating member such that the floating member is configured to rotate about a first axis that passes through the bearing element. The jaw member is configured to electrically connect the floating contact assembly to an external electrical component and the flexible conductor electrically couples the jaw member to the floating member.

Circuit breakers provide automatic and manual current interruption to a circuit. The act of turning ON a circuit breaker and closing an electrical circuit typically involves a mechanical movement of a series of mechanical parts that results in a moveable contact making an electrical connection with a stationary contact. Because the moveable and stationary contacts are initially brought into physical contact with one another when the circuit breaker is turned ON, arcing can occur therebetween which, over time, can damage the contacts and can reduce the useful life of the circuit breaker. Similar arcing and damage can occur when the moveable and stationary contacts are disconnected in response to the circuit breaker turning OFF. Additionally, due to the nature of imperfections of the contacts, especially when damaged from arcing, for example, a planar engagement between the exposed surfaces of the contacts is not always established.
Thus, a need exists for an improved apparatus. The present disclosure is directed to satisfying one or more of these needs and solving other problems.

Floating stationary contact to create stable, low resistance contact joints


Various systems and methods for temperature measurement are disclosed. For example, some embodiments of the present invention provide methods for temperature measurement that include exciting a provided transistor with at least four sequential input signals of different magnitudes. In response, the transistor exhibits a sequence of output signals corresponding to the four sequential input signals. The sequence of output signals is sensed using a different gain for each of the output signals included in the sequence of output signals, and the output signals included in the sequence of output signals are combined such that the combined output signals eliminates a resistance error. The combined output signals are then used to calculate a temperature of the transistor.

The present invention is related to temperature measurement, and more particularly to temperature measurements using a transistor or diode as a sensor.
Temperature measurement using a transistor as a sensor is a common application in the semiconductor area. Such a temperature measurement is done by applying two different currents to the transistor each resulting in a respective base-emitter voltage. The difference between the two different base-emitter voltages is proportional to the absolute temperature of transistor 144. The following equation defines the relationship between the difference between base-emitter voltage measurements and absolute temperature:ΔVbe=Vbe2−Vbe1=n*kT/q*1n(I2/I1).The 'n' term is known as the non-ideality factor or emission coefficient is assumed to be a constant (n=1.008) for diodes and transistors.
An example of such a temperature measurement circuit 100 is shown in FIG. 1a. Turning to FIG. 1a, temperature measurement circuit 100 includes a transistor 120 that is used as a temperature sensor. The collector and the base of transistor 120 are electrically coupled to a variable current source 110. Further, the base of transistor 120 is electrically coupled to one input of an analog to digital converter 130, and the emitter of transistor 120 is electrically coupled to another input of analog to digital converter 130. Analog to digital converter 130 is operable to receive the voltages at the base and emitter of transistor 120, and to provide a ΔVbe output 135 representing the difference between two different base to emitter voltages. ΔVbe output 135 is provided to a temperature calculation circuit 140 that provides an uncorrected temperature output 145.
In some cases, an input filter 134 including a series resistor 131, a series resistor 132, a and a capacitor 133 is used. Input filter 134 is operable to filter noise from the voltages received from the base and emitter of transistor 120. While input filter 134 operates to increase the accuracy ΔVbe output 135 and thereby increase the accuracy of uncorrected temperature 145, the series resistance introduced by input filter 134 results in an error in uncorrected temperature 145. In particular, the resistance introduced by series resistor 131 and series resistor 132 (and in some cases non-idealities of transistor 120) causes a voltage drop that is a function of the magnitude of an applied current. This voltage drop is described by the following equation:ΔVbe=Vbe2−Vbe1=(Ie2−Ie1)*Rs+n*kT/q*ln(Ic2/Ic1).Ie1 is the current passing through the emitter upon application of a first current, and Ic1 is the current passing through the collector upon application of the same current. Ie2 and Ic2 are similarly emitter and collector currents corresponding to the application of a second current. Rs is the series resistance. The voltage drop described by the aforementioned equation will create a temperature measurement error if not taken into account by the circuit.
To correct for the aforementioned temperature error, some circuits have included a backend offset circuit designed to add or subtract a calculated constant from uncorrected temperature 145 and thereby achieve a corrected temperature. FIG. 1b shows an example of one such temperature calculation circuit 101. As shown, temperature calculation circuit 101 is substantially similar to temperature calculation circuit 100, except for the addition of a temperature offset adder circuit 150. Temperature offset adder circuit 150 receives uncorrected temperature 145 and a programmed temperature offset input 147. The two inputs are added together to create a corrected temperature output 155. While such an offset approach can effectively correct calculation errors at a given point on an operational curve, the inaccuracy of the calculated temperature still exists as operation moves farther from the aforementioned offset corrected point on the operational curve.
Thus, for at least the aforementioned reasons, there exists a need in the art for advanced systems and devices for temperature measurement.

Systems and methods for resistance compensation in a temperature measurement circuit


A locking mechanism for a differential assembly includes an adjusting ring and a retainer. The adjusting ring is rotatable about an axis and has an inner peripheral surface and an outer peripheral surface. The adjusting ring is adjustable to set a desired preload. A plurality of pockets is formed within the outer peripheral surface, and the pockets are circumferentially spaced apart from each other about the axis. The retainer has a portion that at least partially extends into one of the pockets to prevent rotation of the adjusting ring about the axis once the desired preload is achieved.

A differential assembly includes a differential gear set mounted within a differential case comprised of a flange case half and a plain case half. The differential assembly is positioned within a carrier bowl portion of an axle housing and is supported on a pair of differential bearings for rotation within the axle housing. The bowl portion includes bearing mount structures with differential leg caps that mount the bearings. One differential bearing is mounted between the flange case half and one bearing mount structure and the other differential bearing is mounted between the plain case half and another bearing mount structure.
Adjusting rings are attached to the bearing mount structures. The adjusting rings include a threaded portion on one side that is threaded into engagement with the bearing mount structure and a plurality of teeth are formed on an opposite side that are separated from each other by grooves. The teeth are formed on an inner peripheral surface of the ring and extend radially inward toward a center of the adjusting ring. Inboard end faces of the adjusting rings abut against the differential bearings such that rotation of the adjusting rings sets a desired bearing preload. Once the desired bearing preload is set, a lock tab is installed to lock the adjusting ring in place, i.e. the lock tab prevents any further rotation of the adjusting ring.
A traditional lock tab assembly includes a plate that is attached to the bearing mount structure with a pair of fasteners. The plate includes a curved lock finger that extends radially inward toward the center of the adjusting ring. A distal end of the curved lock finger is received within one of the grooves. Once the lock finger is positioned within a groove, the adjusting ring is no longer able to rotate.
For larger sized carriers, the flange side differential bearing and adjusting ring have increased outer diameters in order to provide a desired load carrying capacity and life requirement. These larger diameters have resulted in the lock tab being offset from a center of the differential to a point where the plate and fasteners protrude beyond a wall of the housing bowl portion, i.e. there is no longer sufficient clearance between the lock tab assembly and the housing bowl portion.


Data is estimated of a plurality of received spread spectrum signals. The plurality of received communications are received in a shared spectrum. The received communications are sampled to produce a received vector. The received vector is processed to produce a plurality of segments. Each segment is processed separately to estimate data of the received communications.

The invention generally relates to wireless communication systems. In particular, the invention relates to data detection in a wireless communication system.
FIG. 1 is an illustration of a wireless communication system 10. The communication system 10 has base stations 121 to 125 (12) which communicate with user equipments (UEs) 141 to 143 (14). Each base station 12 has an associated operational area, where it communicates with UEs 14 in its operational area.
In some communication systems, such as code division multiple access (CDMA) and time division duplex using code division multiple access (TDD/CDMA), multiple communications are sent over the same frequency spectrum. These communications are differentiated by their channelization codes. To more efficiently use the frequency spectrum, TDD/CDMA communication systems use repeating frames divided into time slots for communication. A communication sent in such a system will have one or multiple associated codes and time slots assigned to it. The use of one code in one time slot is referred to as a resource unit.
Since multiple communications may be sent in the same frequency spectrum and at the same time, a receiver in such a system must distinguish between the multiple communications. One approach to detecting such signals is joint detection. In joint detection, signals associated with all the UEs 14, users, are detected simultaneously. Approaches for joint detection include zero forcing block linear equalizers (ZF-BLE) and minimum mean square error (MMSE) BLE. The methods to realize ZF-BLE or MMSE-BLE include Cholesky decomposition based and fast Fourier transform (FFT) based approaches. These approaches have a high complexity. The high complexity leads to increased power consumption, which at the UE 14 results in reduced battery life. Accordingly, it is desirable to have alternate approaches to detecting received data.
Data is estimated of a plurality of received spread spectrum signals. The plurality of received communications are received in a shared spectrum. The received communications are sampled to produce a received vector. The received vector is processed to produce a plurality of segments. Each segment is processed separately to estimate data of the received communications.

Segment-wise channel equalization based data estimation


Systems and methods for analyzing image data depicting properties are disclosed According to certain aspects, an electronic device may analyze image data depicting a property to identify a set of attributes of the property. The electronic device may identify, based on the set of attributes, an architectural style of the property. Further, the electronic device may identify at least one additional property having the same architectural style. Data indicative of the at least one additional property may be presented to a user for viewing and assessment.

Individuals frequently browse or search for properties for sale or for rent, such as when looking to purchase (or rent) or sell a property, when gauging market conditions, or for other reasons. Technology and connected devices have made property searches easier and more efficient. In particular, certain mobile applications enable users to locate nearby properties for sale and view listing images associated with the properties, among other information.
Certain applications and platforms also enable users to configure filters in searching for properties. For example, users may specify number of bedrooms, number of bathrooms, price range, square footage, year built, lot size, garage information, and/or other filters. While these filters may help users locate properties that conform to desired metrics, the filters do not account for particular styles or appearances of properties. Additionally, the applications do not utilize image data to determine property attributes and identify similar properties.
Accordingly, there is an opportunity for systems and methods to analyze image data depicting properties to identify properties having a similar style or general appearance.

Real property image analysis system to identify similar properties

STATE FARM MUTUAL AUTOMOBILE INSURANCE COMPANY


The invention provides tooling and a method for hot forging pieces of sheet metal that are to form metal reinforcement mounted on the leading or trailing edge of a turbine engine blade, by means of bottom and top matrices each presenting a twisted elongate surface for use in shaping an initially plane piece of sheet metal, the shaping surface of the bottom matrix presenting a high portion, a low portion, and two end zones. The bottom matrix includes studs for positioning and guiding the piece, the studs being situated at the periphery of the corresponding shaping surface.

In order to reduce the weight and the cost of the blades of turbine engine fans, they are generally made out of composite material. Fan blades need to be capable of withstanding high levels of shock and impact because of their speed of rotation and because of collisions with particles or foreign bodies that may penetrate into the stream of air. For this purpose, composite blades are protected at their leading and/or trailing edges by metal reinforcement that is adhesively bonded to the airfoils of the blades.
Document EP 1 547 270-A1, in the name of the applicant, describes a method of fabricating such reinforcement by superplastic forming and diffusion bonding (SPF/DB), which method consists in:                bonding two pieces of sheet metal together by diffusion bonding in order to obtain a preform, some portions of the pieces being covered in an anti-diffusion substance in order to prevent them bonding together in determined zones;        curving and twisting the preform;        inflating the preform so that it is subjected to superplastic forming; and        cutting the preform in order to obtain the reinforcement.
That method does not make it possible to control the inside shape of the cavity in the reinforcement with accuracy. In particular, the junction zones between the pieces of sheet metal form stress concentration zones where break starters weaken the reinforcement.
In order to improve the mechanical strength of the reinforcement, patent application FR 10/51992, filed by the applicant and not yet published, proposes a method of making metal reinforcement, which method consists in:                shaping two pieces of sheet metal in order to bring them close to the final shape of the reinforcement that is to be made;        positioning the two pieces of sheet metal on either side of a core reproducing the inside shapes of the suction side and of the pressure side of the reinforcement;        assembling the two pieces of sheet metal together around the core in leaktight manner under a vacuum;        shaping the pieces of sheet metal on the core by hot isostatic compression; and        cutting the pieces of sheet metal in order to separate the reinforcement and release the core.
Hot isostatic compression enables the pieces of sheet metal to be shaped to have the same shape as the core, thus making it possible in the junction zone between the pieces of sheet metal to obtain a large radius of connection and consequently to avoid any zone of stress concentration or of break starters.
Prior to being positioned around the core, the shaping of the pieces of sheet metal is performed in a plurality of successive hot-forming operations.
Nevertheless, it is difficult to control accurately the shape, the thicknesses, and the surface states of the sheet metal pieces as formed in that way. In addition, the duration and the cost of such operations are relatively high. Finally, the shaped pieces need to be machined after forming, which is particularly difficult and expensive when they present a three-dimensional profile. It is easier to machine sheet metal while it is plane, i.e. before it is shaped.

Tooling and a method for hot forging pieces of sheet metal


An optical disk apparatus according to the present invention includes: a sub-data forming section for forming, from data to be recorded into an optical disk (3), element data (42a, 42b) constituting the data and parity data (42c) for reconstructing the data in a case where the element data (42a, 42b) becomes unreadable; and a recording position determining section for determining respective recording positions for the element data (42a, 42b) and the parity data (42c). The recording position determining section determines the respective recording positions for the element data (42a, 42b) and the parity data (42c) such that they do not overlap each other in a projection plane of the optical disk viewed in a light-irradiation direction. The arrangement makes it possible to improve reliability of data reconstruction in a case where data loss occurs in data recorded in the optical disk (3) in which data is recordable in a plurality of layers.

In a case where an error such as noise contamination happens when data is read via communications over a network or from a memory medium, it is detected from a redundant code preliminarily added to the data whether or not any error occurs. If there is an error, error correction is conventionally carried out so as to reproduce original data. However, in cases where a given data amount includes many errors, the data cannot be reconstructed properly. For example, there are some cases where a recording device, such as a hard disk or an optical disk apparatus, cannot carry out the error correction with respect to a storage medium because the storage medium is damaged due to an impact or the like. Especially, in a case where the storage medium is an optical disk, a recording surface thereof is touchable by hand directly. The direct touch to the recording surface may possibly cause so big a damage on the storage medium that the error correction cannot be performed on the storage medium. Further, in some cases, the optical disk itself deteriorates so much due to direct or indirect sunlight that the error correction cannot be performed on the storage medium.
There is a well-known technique for preventing such data deterioration or data loss. The technique is called RAID (Redundant Arrays of Inexpensive Disks). The RAID is a technique in which (i) original data to be recorded is split into a plurality of pieces of sub data, and (ii) the plurality of pieces of sub data are recorded into a plurality of hard disks, respectively, in a distributed manner. At the time when the pieces of sub data are recorded into to the respective plurality of hard disks in a distributed manner, parity information is added to the pieces of sub data. With this arrangement, even if reading of data from any of the plurality of hard disks is failed, it is still possible to reconstruct the original data properly based on the other piece(s) of data read from the other hard disk(s).
Other than the technique for recording data into a plurality of hard disks in a distributed manner, there is disclosed another technique in which a single hard disk is arranged in the following manner so as to a realize mirroring function (Patent Literature 1). More specifically, the technique disclosed in Patent Literature 1 is so arranged that data recording is carried out such that data is written into 2 portions in a data storage medium, and data reading is carried out such that the data is read from either one of the 2 portions. With the arrangement, even if either one of the pieces of data causes an error, the other one of the pieces of data can be read.
Further, as still another technique, there is disclosed an information processing apparatus for performing data recording on a single optical disk including a plurality of recording layers in such a manner that data and its backup data for reconstructing the data are recorded into respective recording layers among the plurality of recording layers or individually recorded into the same layer (Patent Literature 2). The information processing apparatus arranged as such can achieve an improvement in efficiency of recording data and its backup data.
However, with the conventional arrangement, it is difficult to increase reliability of reconstruction of lost data in the optical disk in which data has been recorded into the plurality of recording layers.
More specifically, the optical disk in which data is recorded into a plurality of layers is arranged such that in a case where respective pieces of data are read from or recorded into different recording layers (for example, a recording layer 100 and a recording layer 200), light emitted from an optical head toward the optical disk is focused on a target layer where data is to be read from or recorded in (see FIG. 23 and FIG. 24). FIG. 23 and FIG. 24 show the conventional technique, each illustrating how light from the optical head is irradiated to a recording layer (100, 200) at the time of data recording or data reading.
As illustrated in FIG. 25, when a protection layer 300 is partially scratched (damaged) such that the scratch gets in the way of the light that is irradiated to the recording layer 100 in which a target piece of data is recorded, there may arise such a problem that the piece of data cannot be read from the recording layer 100 due to the scratch. In addition, in a case where (i) another piece of data is recorded in the recording layer 200 and (ii) recording positions (where data is recorded) of the recording layers 100 and 200 overlap each other in a light-irradiation direction of the light from the optical head, there may occur such a problem that the another piece of data cannot be read from the recording layer 200, either (see FIG. 26). FIG. 25 and FIG. 26 show the conventional technique, each illustrating (i) data recorded in a recording layer (100, 200) and (ii) how light from an optical head is irradiated to the recording layer, in a case where a protection layer (300) of an optical disk is damaged.
That is, in the optical disk in which data is recordable in a plurality of layers, there are some cases where not only data recorded in a given recording area of the recording layer 100 but also data recorded in a given recording area of the recording layer 200 may become unreadable due to the scratch on the protection layer 300 (see FIG. 27). On this account, in a case where data and its reconstruction data for reconstructing the data are recorded in the recording layer 100 and the recording layer 200, respectively, in a distributed manner, both the data and the reconstruction data may become unreadable due to a single scratch on the protection layer 300, in some cases. Here, FIG. 27 illustrates a relationship between (i) how light from an optical head is irradiated, (ii) the scratch on the protection layer 300, and (iii) ranges in the recording layers 100 and 200 in which the scratch affects data writing and data reading.
Patent Literature 1 described above does not improve the reliability of reconstruction of lost data in the optical disk in which data is recordable in a plurality of layers. Further, Patent Literature 2 does not prevent the problem that both of the data and the reconstruction data become unreadable due to the single scratch on the protection layer 300.

Information processing apparatus, control method for controlling information processing apparatus, control program of information processing apparatus, and storage medium storing control program of information processing apparatus therein


Disclosed is a method for automatically compressing multi-task oriented pre-trained language model and a platform thereof. According to the method, a meta-network of a structure generator is designed, a knowledge distillation coding vector is constructed based on a knowledge distillation method of Transformer layer sampling, and a distillation structure model corresponding to a currently input coding vector is generated by using the structure generator; at the same time, a Bernoulli distribution sampling method is provided for training the structure generator; in each iteration, each encoder unit is transferred by Bernoulli distribution sampling to form a corresponding coding vector; by changing the coding vector input to the structure generator and a small batch of training data, the structure generator and the corresponding distillation structure are jointly trained, and a structure generator capable of generating weights for different distillation structures can be acquired.

Large-scale pre-trained language models have achieved excellent performance in natural language understanding and generation tasks. However, deploying pre-trained language models with massive parameters to devices with a limited memory still faces great challenges. In the field of model compression, the existing language model compression methods are all language model compression for specific tasks. Although knowledge distillation for specific tasks is very effective, fine-tuning and reasoning for large models is still time-consuming and costly. When facing other downstream tasks, the pre-trained model generated by distillation with specific task knowledge still needs to fine-tune the large model and generate relevant large model knowledge.
Most of the knowledge distillation strategies used in the existing model compression are layer-by-layer knowledge distillation, that is, given a teacher network and a student network, in order to supervise and train the student network, the method of layer-by-layer knowledge distillation is to minimize the distance between the feature maps of the two networks. When the training data is sufficient, this method can usually achieve better results. However, in the case of small sample data, training is easily affected by over-fitting, and the estimation error increases significantly and will spread layer by layer. Therefore, the core challenge of neural network compression in the case of small samples is that the compressed model is easy to over-fit on training instances with few samples, which leads to a large estimation error between the inference process and the original network. Estimation errors may accumulate and spread layer by layer, and eventually destroy the network output.
In addition, the existing knowledge distillation methods are mainly data-driven sparse constraints or artificially designed distillation strategies; considering that a Bidirectional Encoder Representations from Transformers (BERT) network usually has 12 layers of Transformer units, each unit contains 8 self-attention units; there are hundreds of millions of possible connection modes of self-attention units, and due to the limitation of computational resources, it is almost impossible to design all possible distillation structures manually and find the optimal structure.

Method for automatically compressing multitask-oriented pre-trained language model and platform thereof


A method of aligning two portions of an image, the portions being projected by projectors on a surface to form respective projected portions of the image, a calibration pattern being embedded in each of the two portions, the method comprising capturing from the surface an image of the pattern from the projected portions, the calibration pattern extending across a combined projection area of the projectors; locating an overlap area according to locations of calibration points; determining projector image coordinates dependent upon locations in the overlap area; and aligning the two portions of the image according to the locations of control points and the locations in the overlap area.

Projectors are widely-used display devices that can be used to produce an image on many surface types. Multiple projectors are commonly used to increase the size of a projection onto a projection surface whilst retaining high resolution and brightness. For example, four projectors can be arranged in a grid configuration to produce a single image that is four times larger than the image produced by a single projector.
A problem of such multi-projector systems is the need for geometric alignment of the projected images on the projection surface. It is important that a viewer perceives a single image that has no visible seams or brightness fluctuations. Precise alignment of the projected images is therefore very important. Many current multi-projection systems require a significant amount of manual effort to perform alignment.
One prior art technique requires the user to establish point correspondences manually. Given two overlapping projections, the user first manually chooses a point in the projection overlap region within the first projector image, and then manually searches and selects a corresponding point within the second projector image.
Some prior art systems perform an automatic alignment procedure at system installation time, for example using projected calibration patterns or structured light patterns, commonly known in the art.
To achieve high accuracy in alignment, an alignment refinement process is needed. Given an initial, approximate coarse alignment, an alignment refinement process can be used to adjust the initial alignment to achieve a more accurate fine alignment.
One prior art technique projects a regular grid like calibration pattern, uses simulated annealing to iteratively estimate alignment parameters and projects a corresponding updated calibration pattern. The alignment parameters are obtained when the algorithm converges. Some drawbacks of this prior art technique are that the calibration pattern is highly visible to human viewers and that the calibration process is slow to update since the technique requires many frames of calibration pattern to be projected, captured and processed.
Multi-projector systems may fall out of alignment over time, for example, due to physical movement of a projector or surface, building vibration, or heat fluctuations causing small movement of a projector's internal components. When such systems become misaligned, a manual or automatic alignment procedure typically needs to be performed.
Other prior art techniques are capable of continuous automatic alignment of multiple projectors. While visible content is being displayed (e.g. a video or image), calibration patterns are also displayed, and are photographed by one or more cameras. The calibration patterns may be in the infrared spectrum. Alternatively, the calibration patterns may be embedded in the projected content images, preferably in such a way that the viewer is unable to perceive the calibration patterns.


The metal-core-board reinforcing structure has a metal core board having a metal core and a resin plate having substantially the same extent as that of the metal core board and being fixedly attached to the metal core board substantially parallel to one side of the metal core board and spaced apart therefrom by a predetermined distance.

In recent years, an electric connection box using a metal core board which is excellent in heat radiation has been proposed in response to various requirements in the field of motorcar such as miniaturization, increase in the amount of electric current used, simplification of design change and so on.
The metal core board is a printed circuit board having at least one internal metal core which is made of metal such as copper or aluminum.
Generally, the soaking in the metal core board is improved as the thickness of the metal core board increases. On the other hand, the electric connection box for motorcar is requested to be formed as thin as possible for providing the soaking effect to the board while reinforcing the board since its weight and strength can be concerned.
In the past, there have been proposed various techniques for reinforcing printed circuit boards used in the electric connection boxes.
For example, Japanese Laid-Open Patent Publication No. 2001-237572 discloses a reinforcing structure in which a printed circuit board is supported on a support member in a housing through a reinforcing member (which will be referred to as the related art 1).
Japanese Laid-Open Patent Publication No. 2004-72881 discloses a structure in which a heat radiating plate is sandwiched between two metal core boards (which will be referred to as the related art 2).
Japanese Laid-Open Patent Publication Hei 7-321421 discloses a structure in which a reinforcing material is applied to a flexible printed circuit board (which will be referred to as the related art 3).
There is furthermore need for installing more boards in an electric connection box in response to the increased number of electrical and electronic parts in the motorcar.
However, the electric connection box according to the related art comprises a metal core board disposed horizontally relative to an upper or lower casing portion by fastening it to the casing through screws or the like at the corners of the board (at four corners in a square board) so that the desired strength of the metal core board is secured. In such a case, the total number of two boards, one on the upper casing portion and one on the lower casing portion, can be disposed in the electric connection box at the best. This technique will be referred to as the related art 4.
Patent Document 1:
Japanese Laid-Open Patent Publication No. 2001-237572 bulletin
Patent Document 2:
Japanese Laid-Open Patent Publication No. 2004-72881 bulletin
Patent Document 3:
Japanese Laid-Open Patent Publication Hei 7-321421 bulletin
The related art 1 raises a problem in that the size of the device is increased in a direction perpendicular to the plane of the printed circuit board since the reinforcing members are attached to the printed circuit board at the opposite ends thereof.
The related art 2 raises another problem in that it is difficult to reduce the weight of the reinforcing structure since the metallic heat radiating plate itself is heavy.
The related art 2 raises still another problem in that the connections for connecting the heat radiating plate to a vehicle body or the like extend outwardly from the main body of the heat radiating plate. This is disadvantageous to reduction of the size.
The related art 3 raises a further problem in that the heat radiation in the flexible printed circuit board cannot be secured since the flexible printed circuit board is applied to the reinforcing member.
The related art 4 raises a further problem in that the number of boards which can be disposed in the casing is limited since the board is disposed horizontally relative to the casing.
Therefore, the space within the casing cannot be used effectively.

Reinforcing structure for metal core board and electric connection box


Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.

The recent trend in designing a system LSI is that a system LSI is designed first at a high abstraction level and then an RTL description is generated through behavioral synthesis.
In this design method, the behavioral description, which implements the desired behavior of a system LSI, is designed first.
Next, the behavior simulation is performed to confirm if the designed behavioral description achieves the desired circuit behavior, that is, if the design is correct.
If the design is correct, the behavior description is transformed into an RTL description through behavioral synthesis.
When an LSI is designed using the design method described above, there is a requirement that the test vector used in the behavioral simulation is used also in the RTL simulation after the behavioral synthesis. For example, this requirement has first and second purposes described below.
The first purpose is to confirm if the behavioral description before behavioral synthesis and the RTL description after behavioral synthesis implement the same function.
If the behavioral description and the RTL description do not implement the same function, the behavioral simulation, if performed to confirm that the behavioral description achieves the desired behavior of the circuit, is meaningless. This is because the designed circuit does not eventually implement the desired behavior.
Conventionally, whether or not the behavioral description and the RTL description implement the same function is confirmed by using the same test vector for the behavioral simulation and the RTL simulation and comparing the results of both simulations.
The second purpose is to confirm the performance of the circuit after the behavioral synthesis.
Because time information is not usually included in the behavioral description, the circuit performance, for example, how much time is required to achieve a function, cannot be confirmed.
In contrast, the RTL simulation reveals how much time is required to achieve a function, that is, the RTL simulation shows the circuit performance.
Therefore, the related art technique checks whether or not the designed behavioral description achieves the desired performance by using the same test vector in both the behavioral simulation and the RTL simulation and evaluating the circuit performance measured in the RTL simulation.
The problem here is that the test vector used in the behavioral simulation cannot be used directly in the RTL simulation.
The reason is that the input application timing and the output observation timing differ between the behavioral simulation and the RTL simulation.
In general, there is no concept of timing (clock) in the behavioral description. Even if there is the concept of timing, the granularity of timing in the behavioral description is different from that of the RTL description. Therefore, the sequence of data that is used as the test vector in the behavioral simulation, if applied at each clock cycle during the RTL simulation, does not produce the same result as that produced by the behavioral simulation. Similarly, the output of the RTL simulation, if observed at each clock cycle, is not the same as that produced by the behavioral simulation.
Patent Document 1 (Japanese Patent Kokai Publication No. JP-P2005-78402A) discloses a behavioral synthesis system that solves the problems described above. The behavioral synthesis system described in Patent Document 1 is proposed primarily to solve the first problem described above (the sequence of data that is used as the test vector in the behavioral simulation, if applied at each clock cycle during the RTL simulation, does not produce the same result as that produced by the behavioral simulation). This conventional behavioral synthesis system assumes that the file read function, which reads the sequence of input from a file, and the file write function, which writes the sequence of output to a file, are described in the behavioral description. The file read function and the file write function are generically called a file function. This conventional behavioral synthesis system comprises syntax analysis means, control data flow graph construction means, scheduling/binding means, test bench generation means, and RTL generation means. The behavioral synthesis system having this configuration operates as follows.
That is, the syntax analysis means and the control data flow graph construction means leave the file functions, which are included in the behavioral description, undeleted.
Resource binding and scheduling are performed to create an RTL description based on the constructed control data flow graph.
The file input for a file function is represented in the created RTL description using the select signal of the multiplexer for input data. The file output condition is represented using the select signal of the multiplexer for output data.
However, the behavioral synthesis system described in Patent Document 1, which operates on the premise that the file functions are used in the behavioral description, is applicable only to a behavioral description satisfying this premise.
An example of the equivalence verification method is disclosed in Patent Document 2 (Japanese Patent Kokai Publication No. JP-P2004-145712A). The equivalence verification method disclosed in Patent Document 2 is proposed primarily to solve the first problem described above. This equivalence verification method finds a comparison time based on the number of delay cycles from the time the input signal is determined to the time the output signal is determined in the RTL simulation result and compares the value of the output signal of the RTL simulation result with the value of the output signal of the behavioral simulation at the comparison time. The problem with this method is that the kind of circuit to which this method is can be applied is limited.
This is because no consideration is made in this method for a circuit whose input value application time differs according to the input signal.
In addition, no consideration is made in this method for a case in which the comparison time cannot be determined based on "the number of delay cycles", for example, when the number of delay cycles depend on the input data.
Patent Document 3 (U.S. Pat. No. 6,845,341 B2) discloses a performance analysis system. The general operation of this performance analysis system is as follows. That is, a test bench for executing the behavioral simulation and the RTL simulation at the same time is created. A module for absorbing the difference in the input time and the output time of the behavioral simulation and the RTL simulation is inserted between the behavioral description and the test bench and between the RTL description and the test bench. In this configuration, the behavioral simulation and the RTL simulation receive the same test vector and the number of clocks required for the RTL description to execute simulation is measured to evaluate the performance.
[Patent Document 1]                Japanese Patent Kokai Publication No. JP-P2005-78402A
[Patent Document 2]                Japanese Patent Kokai Publication No. JP-P2004-145712A
[Patent Document 3]                U.S. Pat. No. 6,845,341 B2 (FIG. 2)
The above mentioned patent documents are incorporated by reference. The analysis on the related arts given by the present invention will be described in the below.
In the related art system, there is a problem that the test vector used in the behavioral simulation cannot be used directly in the RTL simulation.
This is because of the input application timing and the output observation timing as described above. The above discussion shows that various propositions for solving this problem are not satisfactory.
Another reason for the above problem is the sharing of input terminals and output terminals. In general, there is not always a one-to-one correspondence between the input/output terminals of a behavioral description and the input/output terminals of an RTL description.
A still another reason for the above problem is a behavior that cannot be represented by a behavioral description. There are many behavioral descriptions where the input/output behavior during a reset is not specified. For example, when the C language is used for behavioral description, the behavior of the input/output during a reset is not specified (there is also behavioral description language, such as SystemC language, in which the input/output behavior during a reset is specified).
This means that the application of an input value, or the observation of an output value, if performed during the reset period at RTL simulation, does not give the same result as that produced by the behavioral simulation.
A still another reason for the above problem is an external model (shared memory model, memory model, operation unit model, etc.). In behavioral synthesis, an array in the behavioral description is implemented by a memory in the RTL description, and a variable in the behavioral description is implemented by a register outside the module in the RTL description.
When an operation in the behavioral description is implemented by an operation unit in the RTL description, the operation is sometimes output as a black box whose detailed internal logic is omitted.
This means that, to perform the RTL simulation, a memory simulation model, a register outside the module, and an operation unit simulation model that is output as a block box must be prepared.
Accordingly, it is an object of the present invention to provide a behavioral synthesis apparatus, a behavioral synthesis method, and a behavioral synthesis program that allow a test vector, which is used before the behavioral synthesis, to be used also for a circuit obtained after the behavioral synthesis.
According to a first aspect of the present invention, there is provided a system (apparatus) comprising: input application/output observation timing signal generation means that creates an input application timing signal and an output observation timing signal for each input and output of a circuit and creates respective logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that applies an input to, and observes an output from, the circuit according to values of the input application timing signal and the output observation timing signal.
According to a second aspect of the present invention, there is provided a system (apparatus) comprising: test bench generation means that recognizes an input application timing signal and an output observation timing signal in a behavioral description of a circuit and generates a test bench that applies an input to, and observes an output from, the circuit according to values of the input application timing signal and the output observation timing signal.
According to a third aspect of the present invention, there is provided a system (apparatus) comprising: test bench generation means that generates a test bench that counts a number of clocks after a reset is released and, when the number of clocks matches a predetermined value, applies an input or observes an output.
According to a fourth aspect of the present invention, there is provided a system (apparatus) comprising: the test bench generation means that generates the test bench that does not apply an input or observe an output when a reset signal or a stall signal is effective.
According to a fourth aspect of the present invention, there is provided a system (apparatus) comprising: the test bench generation means that outputs the test bench that has a simulation model for a hardware resource that is output as a black box in an RTL (Register Transfer Level) description.
Also provided are the invention of methods and the invention of programs for the first to fifth aspects of systems (devices) described above.
The meritorious effects of the present invention are summarized as follows.
The present invention allows the same test vector to be used in a behavioral simulation and an RTL simulation. This is because, in the present invention, a test bench is output in such a way that a test vector used before behavioral synthesis can be used also in a circuit generated after behavioral synthesis.
Still other features and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings wherein examples of the invention are shown and described, simply by way of illustration of the mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different examples, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.

Behavioral synthesis apparatus, method, and program having test bench generation function


In one embodiment, a gateway label edge router (G-LER) receives a packet destined for a mobile domain that comprises a vehicle label edge router. The G-LER identifies, from among a plurality of primary domains, a particular primary domain that currently has a label switched connection with the mobile domain. The label switched connection connects the vehicle label edge router of the mobile domain and a cluster label edge router of the particular primary domain. The G-LER sends the packet to the cluster label edge router of the particular primary domain for transmission to the vehicle label edge router via the label switched connection. The G-LER tracks when the vehicle label edge router of the mobile domain establishes a new label switched connection with a second cluster label edge router of a different primary domain in the plurality of primary domains than that of the particular primary domain.

Label switched networks are networks wherein data packets are forwarded on the basis of labels. A practical implementation of label switching could be based on Multiprotocol Label Switching (MPLS), which is an Internet Engineering Task Force (IETF) standardized protocol. According to MPLS, data packets entering the network at one node, called ingress, are classified into a Forwarding Equivalence Class (FEC). All data packets with a same FEC follow a same primary path (called Label Switched Path or LSP) to a destination node, called egress. The nodes of the network, including intermediate ones, take per-packet forwarding decisions based on label Forwarding Information Base (FIB) tables.
Wireless communication in high-speed vehicular mobility scenarios poses complex technical challenges across several layers of the ISO-OSI stack, including the physical layer (Layer 1), the data layer (Layer 2) and the network layer (Layer 3). Unlike a stationary environment, where roaming is rare and deferred communication is tolerated, in high-speed vehicular mobility scenarios handoff is a certainty. Continuous reliable wireless connection with seamless handoff and sustained communication for smooth operation is required. Moreover, as the train speed increases, communications between the train and infrastructure encounter major difficulties of maintaining such high-quality communication and yet there is no effective solution able to cope with the specific constraints of high-speed trains.

Method and system for mobility management in communication networks


A microcontroller includes a CPU and a cryptographic circuit, and when a first program uses the cryptographic circuit, the second program transmits installation information of the first program and encrypted program installation information to the cryptographic circuit. The cryptographic circuit decrypts the encrypted program installation information and compares it with the installation information of the first program. In the case of match, the use of the cryptographic circuit by the first program is permitted.

The present disclosure relates to security techniques in microcontrollers and semiconductor device.
In the microcontroller, various measures are taken to prevent data tampering by a malicious program or leakage of a cryptographic key used for security data processing.
Programs executed by the microcontroller generally have a hierarchical structure such as firmware, an operating system (OS), drivers, middleware (also called libraries), and applications, but security measures must also be taken in consideration of this hierarchical structure.
Patent Document 1 describes a technique related to security measures in consideration of a hierarchical structure of software. More specifically, when a program composed of a main program and a sub-program called from the main program is executed, a return destination address at the time of returning from the sub-program to the main program is acquired. Based on the acquired return destination address, the OS is used to determine whether the main program is in the memory area in the executable state or whether the main program matches the attribute information registered in advance. If the main program is in the memory area in the executable state and the attribute information also matches, the main program is judged to be legitimate, otherwise, it is judged to be illegal, and the execution of the program is stopped.
Here, the sub-program is, for example, a plug-in that provides a security function.

Microcontroller and semiconductor device


A method and system for controlling access to computer resources by multiple software components is described. A locker manager is provided, which is adapted to manage access to shared computer resources by independent software components. If a particular hardware resource is not currently being used and is available, the locker manager grants a particular software component access to the particular computer resource and locks access thereto, wherein none of the other software components can access the particular computer resource until the particular software component has finished accessing the particular computer resource.

Remote Direct Memory Access (RDMA) is a technique for efficient movement of data over high-speed transports. RDMA enables a computer to directly place information in another computer's memory with minimal demands on memory bus bandwidth and CPU processing overhead, while preserving memory protection semantics. RNIC is an RDMA-enabled NIC (Network Interface Controller). The RNIC may provide support for RDMA over TCP (transport control protocol). RDMA RNIC is also referred to as intelligent RNIC.
In addition to providing RDMA capabilities, the intelligent RNIC is expected to support multiple semantics. For example, it may operate as a regular Ethernet NIC providing a widely-used partial offload of a hardware checksum generation and validation. It may operate as an intelligent NIC providing full TCP termination. It may interface to enable software implementation of socket semantics. It may serve as an iSCSI (Internet Small Computer System Interface) target or initiator adapter, providing partial iSCSI acceleration.
Each one of the semantics capabilities may require a different software environment and different drivers to implement it. The drivers are not necessarily coupled or capable of communicating one with another due to various reasons. For example, the software/drivers may be implemented by different vendors, or the software/drivers may run in a virtualized environment, while others may run on host or embedded CPUs, etc.
An operating system (OS) generally provides services like semaphores, mutexes, spin-locks, etc., for synchronizing different software components. The synchronization schemes may depend on the operating system, and may require different software components to be aware of each other. Alternatively, a single software component may be used that provides such synchronization facilities and exclusive access to the shared hardware.
Such standard synchronization schemes may work well in an application with a single software component, e.g., a standard NIC driver. However, such schemes do not work effectively with multiple software interfaces, such as in intelligent RNIC.

Locker manager for managing access to shared resources

International Business Machines Corporation