A method and system configured to provide a weather forecast for a selected zone is provided. The method and system is configured to receive meteorological reports and locally sensed measurements. The information is transmitted to a weather model preprocessor disposed on the device which generates an analysis field. This information is passed to the weather model which is an executable program also disposed on the device. The weather model processes the analysis field generated by meteorological reports, large-scale initialization data and in-situ sensor values to generate an initial weather forecast. The weather model updates the initial weather forecast with real-time, high-resolution atmospheric measurements to generate a weather forecast more representative of the user's zone than that available from Internet/media outlets. Furthermore, because the weather model is run on the mobile device itself, staleness of the forecast will no longer be an issue, as forecasts can be generated on demand.

Mobile devices having an application for providing a weather forecast are currently known and used. However, the weather forecast is based on temporally stale information. Specifically, the forecast is based upon a model that is typically run every 6 hours. Accordingly, the weather forecast information is based upon models that are not reflective of current atmospheric conditions.
Further, the weather forecast is based on global-scale models featuring coarse horizontal resolutions. For instance, current models used by forecasting entities may use a horizontal grid resolution of approximately 50-100 km for a forecast covering an area of 1000 km. Thus, current weather forecasts do not capture the influences of the local underlying topography and land use. Using global-scale models alone may suffice in non-dynamic weather conditions, but will typically be inadequate if weather conditions are changing rapidly or if the local area features significant terrain and/or dramatic land-use transitions.
Accordingly, it remains desirable to have a method or system configured to generate a weather forecast optimized for a local geographic zone by using a high-resolution (both horizontally and vertically) physics-based weather model with the best possible 3-d picture of the atmosphere for model initialization and by using built-in high resolution land use and topography datasets.

Device and system for generating a weather forecast for a selected zone

The United States of America as represented by the Secretary of the Army


A watercraft has an engine, a propeller, an electronic control unit (ECU), a throttle actuator, and a velocity control actuator separate from the throttle actuator. The velocity control actuator is movable between an inactive position and a plurality of active positions. When the velocity control actuator is in the inactive position, the ECU controls a speed of the engine based at least in part on a degree of actuation of the throttle actuator. When the velocity control actuator is moved from the inactive position to one of the plurality of active positions, the ECU reduces the speed of the engine based at least in part on a degree of actuation of the velocity control actuator independently of the degree of actuation of the throttle actuator. A method of controlling a watercraft is also described.

Many boats and other watercraft are propelled by one or more propellers that are driven by one or more inboard or outboard engines or a stern drive system. Each propeller typically has three or four blades, but may have as few as two or more than four. The base of each blade is mounted at an angle, or pitch, relative to a radial plane transverse to the axis of rotation of the propeller shaft. Some propellers have blades with a variable pitch, so that the pitch can be adjusted to provide increased efficiency, faster acceleration, or other desired performance characteristics at a wider range of speeds than blades having a fixed pitch. The variable pitch mechanism may be either manually actuated or regulated by an electronic control unit (ECU) based on one or more operating parameters of the watercraft such as vehicle speed and propeller rotation speed.
From time to time, the user of a watercraft may desire to slow down the watercraft quickly, for example to avoid striking an obstacle in the water. One method of slowing down a watercraft is to manually move the throttle actuator to an idle speed position, disengage the engine from the propeller or turn the engine off completely, and allow the friction created by the hull in the water to slow the forward motion of the watercraft. However, the user may wish to slow down the watercraft more quickly.
The user of a watercraft may alternatively attempt to rapidly decelerate the watercraft by quickly moving the throttle lever from a forward thrust position to a reverse thrust position. This method may cause damage to various components of the watercraft, particularly if the engine speed is relatively high. In particular, reversing the direction of rotation of the propeller at high speeds may cause stress on the propeller blades and hub, and the shift from forward gear to reverse gear at high engine speeds may damage the transmission gears. In addition, it may be difficult for the user to control the degree of deceleration of the watercraft. Furthermore, steering to avoid an obstacle with thrust directed in the reverse direction may be difficult or counter-intuitive to some users.
Therefore, there is a need for a watercraft providing an alternative system for slowing down.
There is also a need for a method of causing the deceleration of a watercraft having these properties.


A circuit and method is described which generates a high frequency clock signal whose frequency is accurate enough to be used for testing other circuitry, yet the circuit can be described using a hardware description language so that it is suitable for logic synthesis and automatic layout. The technique uses a plurality of programmable ring oscillators and means to select and enable one of the ring oscillators. The output frequency is measured relative to that of a lower frequency reference signal, and when the output frequency is incorrect, a different ring oscillator is selected or the present ring oscillator's frequency is changed. Circuitry is included to prevent glitches at the output of the clock generator when the frequency is changed, regardless of how the ring oscillators are constructed. One or more of the delay stages in the ring oscillators contain parallel 3-state logic gates which allow delay changes less than the delay of a single non-inverting delay gate, and this allows the frequency to be very accurately controlled.

When testing high speed Integrated Circuits (ICs), it is desirable to test them using signals whose frequencies are equal to the specified operating frequencies of the IC. Built-In Self-Test (BIST), which requires supplying on-chip generated patterns to a Circuit Under Test (CUT), is often able to generate signals at the required frequencies using only a master clock signal supplied to the IC at the appropriate frequency. However, generating even one high frequency clock for a high speed IC is difficult if the Automatic Test Equipment (ATE) testing the IC does not have a frequency range high enough. Some manufacturers place crystal oscillator on the ATE interface board to generate the high frequency clock (e.g. 50 to 200 MHz). However, this is not a general solution, especially for application-specific ICs (ASICs) in which logic circuits are designed using a hardware description language (HDL), synthesized into logic gates, and automatically arranged in a layout to form an ASIC's physical design. The crystal oscillator must be changed for each ASIC type tested, and several crystal oscillators may be required for a single ASIC.
For many years, designers have incorporated ring oscillators into IC designs to generate periodic signals. A ring oscillator of a basic design comprises an odd-number of inverting delay elements 12 connected in series to form a ring 10, as shown in FIG. 1. By using a control signal ENABLE 13, a reset logic gate 11 allows the oscillation to be stopped in a pre-determined state to have power, and allows controlled start-up of oscillation. The fewer the number of logic gates 11, 12, the higher the oscillation frequency of the output clock signal 14, but three is the minimum. The output of a single inverting gate whose output is connected to its input will simply settle to a stable DC voltage mid-way between logic 1 and logic 0.
When the delay elements 12 in a ring oscillator are simple loci inverters as shown in FIG. 1, the oscillation frequency is dependent on temperature, power supply voltage, and variations in the IC manufacturing process. For this reason, digital ring oscillators are generally not used when accurate frequencies are needed. Delay elements comprising analog circuits can be less sensitive, but are generally not suitable for automated design and layout because the exact layout is important for correct operation, and the deign must be re-optimized for each new IC manufacturing process.
Digitally programmable ring oscillators are one solution to the frequency inaccuracy of digital oscillators. In a digitally programmable ring oscillator, by digitally increasing or decreasing the number of delay elements in the ring, the oscillation frequency can be changed. Decreases in the number of delay elements are always achieved by bypassing some delay elements in one way or another, e.g., a programmable ring oscillator disclosed in U.S. Pat. No. 4,517,532 issued to Neidorff in May 1985. In this oscillator, the resolution of frequency changes is limited by the delay of each delay element used because an even number of inverters must always be added or subtracted from the ring to maintain oscillation. Also, each time the number of inverters in the ring is changed, a transient pulse or "glitch" can be generated at the output.
In a paper entitled, "Integrated Pin Electronics for VLSI Functional Testers" (Gasbarrow & Horowitz, April 1989, IEEE Journal of Solid-State Circuits), the authors show a circuit technique, as shown in circuit 20 of FIG. 2, to create a delay line with delay increments less than that of one logic gate. The circuit 20 is used to delay the rising edges of a series of pulses. The designers exploit "the difference in path delay through pairs of carefully sized inverters." The circuit 20 uses a conventional tapped delay line 24 and multiplexer 23 for the larger delay steps, and parallel inverters 21 and 22, and 25-27 for the smaller delay steps. The transistor sizes of the inverts 21-22, 25-27 are shown next to each inverter in FIG. 2.
Certain characteristics of the design by Gasbarrow & Horowitz can be improved. The authors do not explain how to construct their circuit using only logic gates of a single size. Also, the load capacitance presented by one or two logic gate inputs in present IC technologies is usually too small to cause a significant delay change when the drive of a gate is doubled. Their design, as described, is not suitable for automated design.
U.S. Pat. No. 5,013,944 issued to Fischer et al in May 1991 describes a "Programmable Delay Line Utilizing Measured Actual Delays to Provide a Highly Accurate Delay". The delay line is schematically depicted in the circuit 30 of FIG. 3. The delay of a series of delay stages 35, 36, 41 is measured by connecting them in a ring oscillator and the delay paths (e.g., path 33) are selectively bypassed with alternate delay paths (e.g., path 34) as needed until the oscillation frequency, and hence delay, is sufficiently close to a reference frequency. The difference in delay of each pair of paths (e.g., path 33 and path 34) is designed to be an approximate value, specifically, the delay of one or more non-inverting logic gates. The ratio of the delay difference of each pair (e.g., 35) to the next pair (e.g., 36) in the delay line is approximately a factor of two, thus achieving a binary-weighted programmable delay line 30. For smaller delay increments, one delay path 42 contains a first logic gate 37, and the other path 43 in the pair contains a second logic gate 38 that has additional logic gates 39 connected in parallel at its output, to increase its delay relative to the first logic gate 37 by less than one logic gate's delay.
Certain characteristics of the design by Fischer et al can cause problems. When the capacitive wire load on the gates in each of two paths is not well matched, the delay through the path 33 with fewer logic gates can inadvertently become longer than the path 34 with more logic gates in series. This prevents a binary search algorithm from working correctly. Also, because the two paths 42 and 43 are connected to different inputs of logic gate 40, the two inputs can have different switching point voltages which can cause the delay of the shorter path 42 to appear longer than the intended longer path 43. This effect is exacerbated when additional load capacitance is added to the output of a logic gate. These various effects make the design approach unsuitable for automatic layout. Lastly, for the larger delay changes, glitches can be introduced when switch settings are changed.
If accuracy is to be maintained while a ring oscillator's output is clocking other circuitry, the frequency may need to be changed when it varies significantly from its intended value due to changes in the supply voltage or temperature. Changes in the frequency of a programmable ring oscillator need to be `glitcheless` in such circumstances, otherwise a pulse or `glitch` can be generated which is shorter than the minimum that the clocked circuitry can tolerate, causing incorrect operation. U.S. Pat. No. 5,471,176 issued to Henson et al in November 1995 describes a Glitchless Frequency-Adjustable Ring Oscillator, an embodiment of which is schematically shown in the circuit 50 of FIG. 4. The circuit 50 seeks to avoid introducing glitches in the output signal 55 when delay stages of a tapped delay line 53 are bypassed by synchronizing the switch activation instant of a synchronized switch 54 to the signal in the oscillation ring 50. It also requires only incrementing or decrementing the binary control code and use of a binary-to-Gray code converter 51, so that only one switch is activated/deactivated for each frequency change. The frequency updates are made precisely when the delay line 53 taps immediately adjacent to the presently accessed tap are known to have the same logic value which is achieved by including delay gates 52. The smallest delay changes are limited to the delay of a single logic gate. When this delay gets very small, this approach is sensitive to wire capacitance and to differences in logic gate switching point voltages, and is therefore not suitable for automatic layout on an IC.
A variation 70 of the tapped delay line is shown in a ring oscillator 60 in FIG. 5 is similar to that disclosed in U.S. Pat. No. 5,815,043 issued to Chow et al in September 1998 entitled "Frequency Controlled Ring Oscillator Having By Passable States". The delay line 70 uses the same principle as that described by Fischer et al. The output frequency 65 of the ring oscillator 60 is compared with a reference frequency 66 in control unit 64, and the delay stages 71, 72 and 73 are selectively bypassed with switches 61, 62 and 63 as needed until the oscillation frequency is sufficiently close to the reference frequency. The bypass switches 61, 62 and 63 are connected across every delay stage 71, 72 or 73, instead of using the tapped delay line 53 of FIG. 4 in which a multiplexer 56 bypasses multiple delay stages. Each delay stage 71, 72 or 73 of the delay line 70 is designed to implement exactly twice the delay of the next smaller delay stage, though the patent recognizes that the factor two will be only approximated in the manufactured circuit. The ring oscillator 60 of FIG. 5 can generate glitches if the bypass switch for a delay stage is changed when the input and output of the delay sage have different logic values. The bypass switches described therein apparently `short-circuit` the input and output of each delay stage as a means of bypassing the delay stage. Bypass means could be used which do not employ a short-circuit, for example a multiplexer, though this is not mentioned in the patent. However, in this case, when the delay of a delay stage is less than a logic gate delay, differences in wire capacitance or multiplexer input switching point voltages can cause the problems previously described for FIG. 3. To achieve a wide range of frequencies, e.g. with 6 binary-weighted control bits, the maximum frequency is limited to that corresponding to the delay through 6 stages because the number of by-passable delay stages is equal to the number of bits. If fewer stages are used to attain a high maximum frequency, then the frequency range is proportionally reduced.
To allow automated creation of circuitry to perform built-in testing, it is desirable to automatically synthesize an on-chip oscillator whose frequency can be periodically or intermittently measured and adjusted to achieve high accuracy (e.g. <2%) at any frequency up to the maximum typically used in a particular technology. In the prior art described above, high accuracy was not an objective for the chosen applications. However, high accuracy is very important in production testing. It is therefore desirable to provide an accurate programmable ring oscillator whose design can be automatically synthesized from an HDL description to produce a digital circuit suitable for automatic layout in any IC manufacturing technology, with a conventional library of logic gates.

Programmable clock signal generation circuits and methods for generating accurate, high frequency, clock signals


Resistive paste comprises at least one metal hexaboride and a vitreous binder suspended in an organic vehicle, and is characterized in that said vitreous binder is composed of a glass frit consisting essentially of 0.5 to 5.0 mol % of niobium oxide and the balance of alkaline earth metal borosilicate. The resistive paste may further contain at least one nitride selected from the group consisting of aluminum nitride and boron nitride, the content of aluminum nitride or boron nitride in the inorganic solid component composed of metal hexaboride, vitreous binder and aluminum or boron nitride in the paste being 5 to 30 wt %.

Recently, there is an increasing tendency to employ base metals such as copper, nickel and the like as a material for electrodes or conductor patterns of thick film circuits. Such thick film circuits are generally produced, for example, by respectively printing a conductive pattern of base metal paste and a resistive pattern of resistive paste on substrates, and then firing the same in a non-oxidizing or reducing atmosphere to prevent the conductor patterns from oxidation. It is therefore required to use resistive paste with a high resistance to reduction.
To this end, there have been proposed a variety of resistive pastes generally comprising a conductive material such as metal hexaboride and a nonreducible vitreous binder suspended in an organic vehicle. For example, Japanese patent published No. 59-6481 and Japanese patent laid open Nos. 55-277700 and 55-29199 disclose resistive paste containing lanthanum hexaboride as the conductive material, and a nonreducible glass frit of calcium boroaluminate, barium borosilicate or calcium borosilicate glass as the vitreous binder.
Such a resistive paste can be applied to production of thick film circuits comprising resistors with sheet resistivity ranging from 10 .OMEGA. to 10 K.OMEGA.. However, such a resistive paste does not provide repeatable results since the sheet resistivity of the resistors produced varies greatly with a slight change of the ratio of glass frit to metal hexaboride. In addition, it is impossible with such resistive pastes to produce thick film resistors with a sheet resistivity of more than 10 K.OMEGA. since the sheet resistivity increases abruptly and becomes more than 1 G.OMEGA. when the ratio of the glass frit to metal hexaboride exceeds 50 wt% slightly. Further, the thick film resistors with a sheet resistivity of not less than 10 K.OMEGA. possess a temperature coefficient of resistance of not less than -1000ppm/.degree. C., thus making impossible to put them into practical use.


An embodiment of the present invention discloses a Wi-Fi device, including a radio frequency circuit, a signal processor, an application processor, and a Wi-Fi chip. The application processor is configured to preset the work mode of the Wi-Fi chip to a single input single output SISO mode, and is further configured to acquire a value of a parameter of an uplink wireless network, and when the value of the parameter of the uplink wireless network is determined to be greater than or equal to a preset value, set the work mode of the Wi-Fi chip to a multiple-input multiple-output MIMO mode. An embodiment of the present invention further discloses a method for setting a communications mode.

With the development of the 3rd-generation (3rd-generation, 3G) mobile communications technologies and long term evolution (Long Term Evolution, LTE) technology, wireless-fidelity (Wireless-Fidelity, Wi-Fi) devices, as portable devices that allow a plurality of Wi-Fi devices to share the uplink bandwidth of an LTE network or a 3G network, are increasingly popular among users. A Wi-Fi device has an in-built LTE/3G chip and Wi-Fi chip. In the uplink, it accesses the Internet via a wireless network such as the LTE network and the 3G network. In the downlink, it provides Internet access for other Wi-Fi devices via a Wi-Fi network complying with 802.11b/g/n. Mainstream Wi-Fi devices at present generally allow 10 or more Wi-Fi devices to access the LTE network or 3G network via Wi-Fi simultaneously. These Wi-Fi devices may be notebook computers, tablets, mobile phones, and the like.
The current highest downlink rate of the LTE network is capable of reaching 150 Mbps, around 10-20 times higher than the 3G network rate. To match the high rate of the LTE network and enable Wi-Fi users to surf the Internet at a higher rate, the latest Wi-Fi devices in the industry have used the Wi-Fi multiple-input multiple-output (Multiple-Input Single-Output, MIMO) technology that may increase the maximum rate of a Wi-Fi network to more than 100 Mbps by using multi-path radio frequency and antennas.
In the prior art, the Wi-Fi work mode is set to a MIMO mode when the Wi-Fi device is started, to meet the requirement of the Wi-Fi access rate. However, the requirement of enabling a plurality of radio frequency paths in the MIMO mode results in a problem of relatively high power consumption.

Method and Wi-Fi device for setting communications mode


To improve the measuring sensitivity of a measuring device to determine the istance between an electrically conducting part, which can be moved in a defined chamber, and a reference point, in particular to determine the upper dead point of the piston of an internal combustion engine, with an electronic evaluation circuit, in which a capacitive sensor can be positioned in a holding device, held in the wall of the chamber, and is connected to an evaluation circuit, the invention provides that the evaluation circuit has a measuring bridge, fed by an oscillator by means of output potential dependent switching elements, with at least two capacitors, that the sensor head of the sensor and the movable part, in particular the piston of the internal combustion engine form one of the two capacitors, and that there is a differential amplifier to which the transverse voltage, which can be picked off the measuring bridge, can be led, and that the outputs of the differential amplifier control the output potentials of the potential-dependent switching elements.

1. Field of the Invention
The invention relates to a measuring device to determine the distance between an electrically conducting part, which can be moved in a defined chamber, and a reference point, in particular to determine the upper dead point of the piston of an internal combustion engine, with an electronic evaluation circuit in which a capacitive sensor can be positioned in a holding device, held in the wall of the chamber, and is connected to an evalution circuit.
2. The Prior Art
In a known measuring device of the aforementioned kind one electrode is isolated in the combustion chamber of an internal combustion engine, the piston or the cylinder block forming the second electrode. Depending on the distance of the piston from the electrode, the capacitance of this system changes. In well-known cases, the change in capacitance is now evaluated in such a manner that said evaluation influences the modulation of a carrier frequency for which a relatively complicated evaluation circuit is necessary.
Due to this principle of measurement, the well-known system has proven to be relatively insensitive to small changes in capacitance and also exhibits a poor signal to noise ratio. In addition to this, one must work with relatively large sensors, resulting in the necessity of providing matching measurement openings, which permit the electrode to be inserted.
The object of the invention is to avoid the above drawbacks and to propose a measuring device of the aforementioned kind, which in particular can be used in a simple manner in conventional internal combustion engines and is characterized by a high degree of sensitivity.

Measuring device for determining distance

AVL Gesellschaft fur Verbrennungskraftmaschinen und Messtechnik m.b.H.


A system for detecting motion between a first body and a second body includes first and second detector-emitter pairs, disposed on the first body, and configured to transmit and receive first and second optical beams, respectively. At least a first optical rotator is disposed on the second body and configured to receive and reflect at least one of the first and second optical beams. First and second detectors of the detector-emitter pairs are configured to detect the first and second optical beams, respectively. Each of the first and second detectors is configured to detect motion between the first and second bodies in multiple degrees of freedom (DOFs). The first optical rotator includes a V-notch oriented to form an apex of an isosceles triangle with respect to a base of the isosceles triangle formed by the first and second detector-emitter pairs. The V-notch is configured to receive the first optical beam and reflect the first optical beam to both the first and second detectors. The V-notch is also configured to receive the second optical beam and reflect the second optical beam to both the first and second detectors.

There are many applications in optics and other fields where it is desirable to provide alignment information or relative motion tracking information in all six spatial degrees of freedom (DOF) for one or more locations on a body. In such case, there are a variety of metrology options to measure the displacement and orientation of the locations of interest. These options include isolated contact probes (such as feeler gauges, and linear voltage differential transform gauges), holography, auto-collimators, interferometers, capacitance distance measuring interferometers, laser tracking systems, etc.
The measurement is more challenging, when it must be done with limited access to locations on a body of interest. For example, in situ testing on a factory floor or integration of components is typically a situation in which access to a body or a component is limited. Under such condition, use of a coordinate measurement machine (CMM) where a body is entirely surrounded or scanned by a calibrated contact or non-contact probe is not feasible or practical.
In addition, it is difficult to measure relative motion between large bodies in a confined space with little real estate available for metrology components. Measurement of relative motion is even more difficult, if not impossible, when knowledge of motion in six degrees of freedom (DOF) is necessary.
The present invention addresses the above problems by providing a system and method for measuring displacement and orientation in six spatial DOF between two separate bodies.

Crossed beam roof target for motion tracking


A three-dimensional semiconductor device with two selectable manufacturing configurations includes a first module layer having a plurality of circuit blocks; and a second module layer formed substantially above the first module layer, wherein in a first selectable configuration a plurality of memory circuits are formed to store instructions to control a portion of the circuit blocks, and wherein in a second selectable configuration a predetermined conductive pattern is formed in lieu of the memory circuit to control substantially the same portion of the circuit blocks.

The present invention relates to multi-dimensional integrated circuits.
Traditionally, integrated circuit (IC) devices such as custom, semi-custom, or application specific integrated circuit (ASIC) devices have been used in electronic products to reduce cost, enhance performance or meet space constraints. However, the design and fabrication of custom or semi-custom ICs can be time consuming and expensive. The customization involves a lengthy design cycle during the product definition phase and high Non Recurring Engineering (NRE) costs during manufacturing phase. Further, should errors exist in the custom or semi-custom ICs, the design/fabrication cycle has to be repeated, further aggravating the time to market and engineering cost. As a result, ASICs serve only specific applications and are custom built for high volume and low cost applications.
Another type of semi custom device called a Gate Array customizes modular blocks at a reduced NRE cost by synthesizing the design using a software model similar to the ASIC. The missing silicon level design verification results in multiple spins and lengthy design iterations.
In recent years there has been a move away from custom or semi-custom ICs towards field programmable components whose function is determined not when the integrated circuit is fabricated, but by an end user xe2x80x9cin the fieldxe2x80x9d prior to use. Off the shelf, generic Programmable Logic Device (PLD) or Field Programmable Gate Array (FPGA) products greatly simplify the design cycle. These products offer user-friendly software to fit custom logic into the device through programmability, and the capability to tweak and optimize designs to optimize silicon performance. The flexibility of this programmability is expensive in terms of silicon real estate, but reduces design cycle and upfront NRE cost to the designer.
FPGAs offer the advantages of low non-recurring engineering costs, fast turnaround (designs can be placed and routed on an FPGA in typically a few minutes), and low risk since designs can be easily amended late on in the product design cycle. It is only for high volume production runs that there is a cost benefit in using the more traditional approaches. However, the conversion from an FPGA implementation to an ASIC implementation typically requires a complete redesign. Such redesign is undesirable in that the FPGA design effort is wasted.
Compared to PLD and FPGA, an ASIC has hard-wired logic connections, identified during the chip design phase, and need no configuration memory cells. This is a large chip area and cost saving for the ASIC. Smaller ASIC die sizes lead to better performance. A full custom ASIC also has customized logic functions which take less gate counts compared to PLD and FPGA configurations of the same functions. Thus, an ASIC is significantly smaller, faster, cheaper and more reliable than an equivalent gate-count PLD or FPGA. The trade-off is between time-to-market (PLD and FPGA advantage) versus low cost and better reliability (ASIC advantage).
There is no convenient migration path from a PLD or FPGA used as a design verification and prototyping vehicle to the lower die size ASIC. All of the SRAM or Anti-fuse configuration bits and programming circuitry has no value to the ASIC. Programmable module removal from the PLD or FPGA and the ensuing layout and design customization is time consuming with severe timing variations from the original design.
In one aspect, a three-dimensional semiconductor device with two selectable manufacturing configurations includes a first module layer having a plurality of circuit blocks; and a second module layer formed substantially above the first module layer, wherein in a first selectable configuration a plurality of memory circuits are formed to store instructions to control a portion of the circuit blocks, and wherein in a second selectable configuration a predetermined conductive pattern is formed in lieu of the memory circuit to control substantially the same portion of the circuit blocks.
Implementations of the above aspect may include one or more of the following. A third module layer can be formed substantially above the first module layer, wherein interconnect and routing signals are formed to connect the circuit modules within the first and second module layers. The second module layer in its first configuration can contain isolated through connections to connect the first module layer to the third module layer. A third module layer can be formed between the first and second module layers, wherein interconnect and routing signals are formed to connect the circuit modules within the first and second module layers. The first selectable configuration forms a programmable logic device (PLD) with one or more digital circuits formed on the first module layer; one or more programmable logic blocks formed on the first module layer and electrically coupled to the digital circuits; one or more memory blocks formed on the first module layer and electrically coupled to the digital circuits; one or more configurable memory elements formed on the second module layer and electrically coupled to the programmable logic blocks to customize the programmable content of the PLD; and one or more interconnect and routing signals formed in a third module layer, electrically coupled to first and second module layers to provide the functionality of the PLD. The second selectable configuration forms an Application Specific Integrated Circuit (ASIC) with one or more digital circuits formed on the first module layer; one or more programmable logic blocks formed on the first module layer and electrically coupled to the digital circuits; one or more memory blocks formed on the first module layer and electrically coupled to digital circuits; one or more predetermined connections formed on the second module layer and electrically coupled to the programmable logic blocks to customize the programmable content; and one or more interconnect and routing signals formed in a third module layer and electrically coupled to first and second module layers. The second module layer can be generic and user configurable to program and re-program to alter the functional response and performance of the PLD. The predetermined conductive pattern can be positioned substantially above the digital circuits. The predetermined conductive pattern can also be integrated in the first module layer or alternatively can be integrated in the third module layer. For every given memory pattern of the second module layer in the first configuration, a unique predetermined connection pattern can exist in the second configuration to substantially match logic customization. One or more of the circuit blocks within the first module layer can maintain substantially identical timing characteristics under both configurations of second module layer logic control. The memory circuit can include one or more thin film devices such as thin film transistors (TFTs), resistors and capacitors. The replaceable memory can be selected from the group consisting of fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, Flash cells, and Ferro-electric elements. The digital circuit can include a third-party IP core. The digital circuit includes a processor capable of executing software logic instructions and other programmable logic blocks, wherein the programmable logic block is selected from one or more of a pass gate logic, multiplexer logic, truth table logic, or an AND/OR logic. The module layer one can include a substrate layer, n-well and p-well layers, field isolation regions, NMOS and PMOS gate, drain, source regions of transistors built on substrate, N+ and P+ diodes, resistors and capacitors built on substrate, gate oxide, gate poly, salicided regions, inter layer dielectric and contacts.
In another aspect, a programmable logic device includes one or more digital circuits formed on a substrate; and a non-planar circuit electrically coupled to the digital circuits, the non-planar circuit being either a memory constructed to store data to define the logic outputs of the digital circuits to fabricate a field programmable gate array (FPGA) or a conductive pattern constructed to define the logic outputs of the digital circuits to fabricate an application specific integrated circuit (ASIC), wherein the memory and the conductive pattern options have substantially matching functionality timing characteristics.
Implementations of the above aspects may include one or more of the following. The IC product is re-programmable in its initial stage with turnkey conversion to an ASIC. The IC has the end ASIC cost structure and FPGA re-programmability. The IC product offering occurs in two phases: the first stage is a generic FPGA that has re-programmability containing a programmable module, and the second stage is an ASIC with the entire programmable module replaced by 1 to 2 customized hard-wire masks. Advantages of the IC may include one or more of the following. A series product families can be provided with a modularized programmable element in an FPGA version followed by a turnkey custom ASIC with the same base die with 1-2 custom masks. The vertically integrated programmable module does not consume valuable silicon real estate of a base die. Furthermore, the design and layout of these product families adhere to removable module concept: ensuring the functionality and timing of the product in its FPGA and ASIC canonicals. These IC products can replace existing PLD and FPGA products and compete with existing Gate Arrays and ASIC""s in cost and performance.
An easy turnkey customization of an ASIC from an original smaller PLD or FPGA would greatly enhance time to market, performance, low cost and better reliability.

Field programmable gate array with convertibility to application specific integrated circuit


To reduce the capacitance between wiring lines of a semiconductor device, while maintaining mechanical strength and reliability. A semiconductor device including: a multilayer wiring layer in which a plurality of interlayer films and a plurality of diffusion preventing films are alternately stacked, and a wiring line is formed in the interlayer films; a contact via that penetrates a via insulating layer formed on one surface of the multilayer wiring layer, and is electrically connected to the wiring line of the multilayer wiring layer; a through hole that penetrates at least one of the interlayer films and the diffusion preventing films from the other surface of the multilayer wiring layer on the opposite side from the one surface; and an air gap that is connected to the through hole, and is formed in at least one of the interlayer films, to expose the contact via.

As semiconductor devices have been becoming smaller and smaller in size these days, wiring delays that lower the operation speeds of semiconductor devices have been increasing. Specifically, in a semiconductor device, wiring resistance increases due to a decrease in the cross-sectional area of the wiring lines, and therefore, a delay proportional to the product of the wiring resistance and the capacitance between wiring lines increases (this delay is also referred to as an RC delay).
To reduce such a wiring delay, studies have been made to lower the dielectric constant of an interlayer film between wiring lines. However, no interlayer film material that achieves a sufficiently low dielectric constant has been found at present.
In view of this, consideration has been given to a method for further lowering the dielectric constant between wiring lines by removing the material between the wiring lines and forming a hollow layer (also referred to as an air gap) having a relative dielectric constant of 1 between the wiring lines.
For example, Patent Document 1 mentioned below discloses provision of a structure that does not damage wiring lines when an insulating film between the wiring lines is removed to form an air gap structure.

SONY SEMICONDUCTOR SOLUTIONS CORPORATION


A current detection circuit of the present invention has a switching device 1; an auxiliary switching device 2; an offset voltage source comprising an offset resistor device 7 and a current source circuit 8; a compensation circuit, comprising a differential amplifier 4 and a compensation transistor 5, for adjusting the output current of the auxiliary switching device 2 so that the potential obtained by subtracting the voltage drop across the offset resistor device 7 from the output potential of the switching device 1 is equal to the output potential of the auxiliary switching device 2, being configured that the detection level of the current flowing in the switching device 1 is shifted by an offset amount.

The present invention relates to a current detection circuit for detecting the current flowing in a switching device, such as a MIS FET (metal insulator semiconductor field effect transistor), and a switching power supply using the same.
In recent years, switching power supplies have been used in various electronic apparatuses because of their high efficiency and high power conversion characteristics. In particular, in the case that quick transient response characteristics are requested, the current mode control system, which is not affected by the resonance frequency of an inductor and an output capacitor constituting such a switching power supply, is used. The current mode control system detects the current flowing in the inductor and controls the current to carry out output control, and requires a current detection circuit. In the case that a current detection device, such as a resistor, is used in a current detection circuit, a conduction loss occurs and its efficiency is reduced. Hence, a current detection circuit for detecting the current flowing in a switching device, such as a MOS FET (metal-oxide semiconductor field effect transistor), has been proposed as described in International Publication No. WO00/079682, for example.
FIG. 11 is a circuit configuration diagram showing a current detection circuit described as a conventional current detection circuit in International Publication No. WO00/079682. In FIG. 11, an output transistor 101 is formed of an N-channel MOS FET. The drain of this output transistor 101 is connected to a DC power supply 110, and the source thereof is connected to one terminal of a load 103. The other terminal of the load 103 is grounded. An auxiliary transistor 102 is an N-channel MOS FET, the drain thereof is connected to the DC power supply 110, and the source thereof is connected to the source of a compensation transistor 105. The ratio I101/I102 of the source current I101 of the output transistor 101 to the source current I102 of the auxiliary transistor 102 is designed to have a substantially constant value (hereafter, n=I101/I102) in the case that the potentials of the drain, gate and source of one of the two switching devices are made equal to those of the other, respectively. This can be realized by making the gate length of the output transistor 101 equal to that of the auxiliary transistor 102 and by setting the ratio of the gate width of the output transistor 101 to that of the auxiliary transistor 102 at n:1 in the case that the current detection circuit is produced so as to be built in a monolithic integrated circuit, for example. The compensation transistor 105 is a P-channel MOS FET, and the drain thereof is connected to one terminal of a current detection resistor 106. The other terminal of the current detection resistor 106 is grounded. A differential amplifier 104 detects the potential difference between the connection point P of the output transistor 101 and the load 103 and the connection point Q of the auxiliary transistor 102 and the compensation transistor 105. The differential amplifier 104 amplifies the detected potential difference and outputs the amplified voltage to the gate of the compensation transistor 105. A drive circuit 111 outputs a common drive signal to the gates of the output transistor 101 and the auxiliary transistor 102.
The operation of the conventional current detection circuit shown in FIG. 11 will be described below.
First, when the potential at the connection point P with respect to the potential at the connection point Q increases in the positive direction by virtue of the differential amplifier 104 and the compensation transistor 105, the potential at the connection point Q rises. Conversely, when the potential at the connection point P increases in the negative direction, the potential at the connection point Q lowers. Hence, the source potential (the potential at the connection point P) of the output transistor 101 becomes substantially equal to the source potential (the potential at the connection point Q) of the auxiliary transistor 102. Furthermore, the drain potential and the gate potential of the output transistor 101 are equal to those of the auxiliary transistor 102, respectively, as clearly understood from the circuit configuration. Hence, the potentials of the drain, gate and source of the output transistor 101 are equal to those of the auxiliary transistor 102, respectively. The ratio I101/I102 of the source current I101 of the output transistor 101 and the source current I102 of the auxiliary transistor 102 is thus maintained at the constant value n. In other words, the source current I102 of the auxiliary transistor 102 is I102=I101/n, a detection voltage Vs proportionate to the source current I101 of the output transistor 101 is generated across the current detection resistor 106. When it is assumed that the resistance value of the current detection resistor 106 is Rs, the detection voltage Vs is Vs=Rs·I101/n.
In the case that the conventional current detection circuit configured as described above is applied to the detection of the current flowing in a switching device in a switching power supply, an inductor and a rectifier circuit are connected to a load. In the case of a step-down converter wherein a synchronous rectifier circuit is used in a rectifier circuit, the current of the switching device is passed in the reverse direction in some occasions so that power is regenerated from the output to the input in order to promptly suppress overshoots occurred in the output, for example. However, the conventional current detection circuit configured as described above can detect only the current flowing from the output transistor to the load. In other words, the conventional current detection circuit configured as described above cannot detect the reverse current flowing in the switching device of the switching power supply.

Current detection circuit and switching power supply


An unleaded high octane gasoline composition exhibiting reduced gum formation and improved air intake system and combustion chamber cleanliness is provided comprising at least (A) one reformate fraction produced by a continuous regeneration type reformer and/or (B) at least one reformate fraction produced by a fixed bed type reformer, said unleaded high octane gasoline composition satisfying the following conditions: EQU Z=(1/100)[.SIGMA.(ax)+(1/9).SIGMA.(by)]<0.010. wherein .SIGMA.(ax) is a summation of (ax) wherein (a) is content (vol %) of a fraction falling into reformate fraction A, (x) is content (vol %) of aromatic hydrocarbons having a carbon number of 11 or more in the fraction (a) and .SIGMA.(by) is a summation of (by) wherein (b) is content (vol %) of a fraction falling into reformate fraction B, (y) is content (vol %) of aromatic hydrocarbons having a carbon number of 11 or more in fraction B; the content of aromatic hydrocarbons having a carbon number of 7 to 8 being 30 vol % or more; and having a research octane number of 96.0 or more.

High-octane gasoline blending stocks produced by Fluid Catalytic Cracking (FCC) units and catalytic reformers have been more extensively used for automobile gasoline, since introduction of regulations on use of lead compounds, e.g., tetraethyl lead, as octane improvers. Furthermore, improvement of automobile mileage is increasingly socially required, which calls for higher engine compression ratio and hence higher-octane unleaded gasoline.
Such high-octane, unleaded gasoline contains large proportions of high-octane gasoline component stocks, e.g., those produced by FCC units and reformers, and toluene. For example, Japanese Patent Publication No. 3-21593 discloses unleaded, high-octane gasoline composed of reformate as the heavier fraction and FCC naphtha as the lighter fraction to have a research octane number of 96 or more. Japanese Patent Publication No. 7-10981 discloses unleaded, high-octane gasoline containing, as the essential components, reformate of specific properties, alkylate and isopentane, to have a research octane number of 99.5 or more. Octane number of reformate has been increased by increasing severity (high temperature operation) of reformers, fractionating reformate to extract higher-octane fraction and such like.
It is noted, however, that unleaded, high-octane gasoline causes several problems while it is stored or in service, such as accelerated formation of gums to clog devices associated with tank, and fuel systems (in particular, fuel filters) in the engine. The more functional gasoline engine is more sensitive to the effects of deposits in the air-intake system on engine performance. For example, the electronically controlled fuel injection device precisely controls air/fuel ratio to improve engine performance, and to improve mileage and exhaust gas composition. However, air/fuel ratio will be no longer adequately controlled when deposits are formed on the air-intake valve, because they will work as obstacles to flow of gasoline ejected out of the fuel injection device, with the result that its operability is lowered. Deposits formed on the combustion chamber walls, on the other hand, tend to increase octane requirements. Therefore, there have been strong requirements to control formation of deposits, both in air-intake system and combustion chamber.
A number of techniques have been proposed to reduce gums in gasoline. For example, Japanese Laid-open Patent Application No. 10-77486 discloses gasoline incorporated with an aliphatic nitroxide compound to control formation of gums. Japanese Laid-open Patent Application No. 9-95688 discloses gasoline aimed at improvement of cleanliness in an air-intake valve and port in a gasoline engine, claiming that formation of deposits on combustion chamber walls can be controlled when gasoline has an octane number of 98 or more, 50% distillation point of 75.degree. C. to 95.degree. C., 97% distillation point of 155.degree. C. or less, aromatic hydrocarbon content of 35 vol % or less, and content of 10 vol % or less for aromatic hydrocarbons having a carbon number of 8 or more. Japanese Laid-open Patent Application No. 9-286992 discloses that an unleaded gasoline composition shows excellent effects of cleaning an air-intake system and combustion chamber, when it is incorporated with a polyetheramine-based detergent at 70 ppm or more and satisfies a specific relationship involving aromatic hydrocarbon content and distillation temperature.
However, none of these techniques shows sufficient effects of controlling formation of gums, or improving cleanliness in air-intake system or combustion chamber. In particular, the technique which depends on use of an additive tends to increase gasoline production cost.
It is an object of the present invention to provide an unleaded, high-octane gasoline composition which forms little gums, and shows excellent effects of cleaning an air-intake system and combustion chamber of a gasoline engine.

Unleaded high-octane gasoline composition


A liner assembly for an aircraft engine housing includes a noise attenuation structure that is covered by a face sheet. The face sheet covering the noise attenuation structure includes a surface having a plurality of circumferentially spaced apart acoustic energy absorption areas that are interspersed between a corresponding plurality of acoustic energy reflective areas. The acoustic energy reflective areas scatter higher order acoustic modes into a plurality of lower order modes. The difficult to attenuate lower order acoustic modes produced by the various acoustic energy cancel each other out to provide significant improvement in liner noise reduction efficiency.

This invention generally relates to liners for aircraft engines. More particularly, this invention relates to an acoustic liner including acoustically inactive areas for attenuating noise generated by an aircraft engine.
An aircraft engine typically includes a plurality of fan blades that rotate within an engine case. The engine case includes an acoustically active lining forward of the fan blades to reduce the level of noise emitted from the aircraft engine. Conventional acoustic linings include a face sheet covering a honeycomb structure. Acoustic energy generated by rotation of the fan blades is transmitted through a plurality of openings in the face sheet to the honeycomb structure where the acoustic energy dissipates to provide an overall noise reduction.
Openings in the face sheet provide for the transfer of acoustic energy into the honeycomb structure. Therefore conventional acoustic liners are arranged to minimize splices, seams and other disruptions that prevent transmission of acoustic energy through the face sheet and scatter the noise energy into lower order acoustic modes that are difficult to attenuate by the liner. However, a splice free face sheet or honeycomb structure is not practical and minimizing the area of a splice or acoustically dead area of an acoustic liner requires efforts that in many instances are disproportionate to any realized benefits.
Accordingly, it is desirable to develop and design an acoustic liner that provides improved sound attenuating characteristics without the need to minimize or eliminate acoustically inactive zones.


According to various embodiments, there is provided a robot including: a spherical shell; a cart in the spherical shell, the cart including a plurality of wheels rotatable to move the cart along an inner surface of the spherical shell; a sensor coupled to the cart, the sensor configured to provide an inertial measurement of the cart; a motion encoder configured to measure an angular velocity of each wheel of the plurality of wheels; and a localizer configured to determine a location of the robot, based on the angular velocities of the plurality of wheels and the inertial measurement of the cart.

Autonomous systems, such as robots, are increasingly being miniaturized to suit a multitude of applications. The ability to navigate is an essential element of autonomous systems. In order to navigate, the autonomous systems need to know their locations. Existing technologies for localization include Global Positioning System (GPS), WiFi and beaconing. The high level of power consumption of these existing technologies render them unsuitable for use on miniature robots which cannot carry large-capacity batteries. There is a need to lower the power consumption of localization technologies so that these robots can operate for long hours without having to re-charge.

SINGAPORE UNIVERSITY OF TECHNOLOGY AND DESIGN


A surgical cannula and method may be constructed in disposable or reusable forms, and may have at least one outwardly extending projection or rib along an outer surface of a tubular shaft. Such a rib, or ribs, may also extend along an outer surface of a cannula tip. A bore in the tubular shaft may have a substantially circular cross-sectional shape, or alternatively in embodiments with outwardly extending ribs may be non-circular and include at least one lobe extending outward into at least one outwardly projecting rib. Some embodiments also include apertures having peripheries that are at least partly configured to form cutting edges.

Surgical cannulas have been used for many years to perform a variety of surgical procedures, such as liposuction.
To perform liposuction, for example, a hand-held instrument (known as a cannula) is inserted through a portal or incision in the patient's skin and into pockets of fat located between the patient's skin and muscles. Once inserted below the skin and into the fat pockets, the cannula is moved around by the surgeon to break up the fat cells. Parcels of the fat tissue are then aspirated through small openings along the sides of the cannula by vacuum applied by a syringe or a pump. The fat tissue is drawn through a central bore, known as a lumen, in the cannula, to a tissue canister connected in fluid communication between the cannula and the suction source.
A typical cannula, of the type used for liposuction, for example, includes an elongated tubular shaft, closed by a cannula tip at the distal end of the shaft which is inserted through the patient's skin. The aspirator tip, and shaft, may include small openings along the sides or at the end of the tip, to create a passage for movement of the tissue to be removed into the central bore of the cannula. The end of the tubular shaft opposite from the cannula tip is typically equipped with a surgical handle to be grasped by the surgeon or a fitting for connecting the cannula to a syringe or other vacuum source. The end of the cannula having the handle or fitting may also be configured for attachment to an infiltration syringe or other source of infiltration fluid.
During use, the vacuum created by suction within the bore of the cannula causes tissue to be pulled into the openings along the sides and at the aspirator tip of the cannula. In some procedures, a cannula of the type described hereinabove may also be used for injecting a fluid into the tissue, in a procedure known as infiltration or tumescent infiltration.
In use, therefore, a typical surgical cannula performs one or more of three basic functions. First, the cannula is used to penetrate, crush, tear, or avulse the fatty tissue in such a manner that it can be suctioned through the openings into the central bore of the cannula. Secondly, the cannula may be used to suction fatty tissue through the central bore to aspirate tissue fragments and fluids from the operative site. Thirdly, the cannula may be used for infiltrating the operative site with a fluid to facilitate breaking up and removing the fatty tissue. It is desirable to provide an improved cannula and method of use for a cannula which enhances the performance of any of these basic functions of the cannula. It is also desirable to provide an improved cannula which is safer for the patient, and which reduces fatigue on the surgeon performing a procedure utilizing the cannula.
It is specifically desirable to provide an improved cannula and method for use having an improved ability to effectively remove, crush, tear or avulse fatty tissue at the operative site. It has been noted that, during aspiration of fatty tissue and fluids from the surgical site, a seal can be created between the outer surface of prior cannulas and the fatty tissue which inhibits the flow of any ambient pressure fluid, such as air, to the operative site about the tip of the cannula. When suction is applied, such a seal prevents the flow of any ambient pressure fluid to the operative site about the shaft or tip of the cannula. When this occurs, the suction capacity of the cannula is substantially reduced, and the fatty tissue fragments and fluids move more slowly than is desirable through the cannula and any related suction equipment to the tissue canister.
Another area in which improvement is desirable, is the cost of such surgical cannulas. Primarily as a cost-saving measure, prior surgical cannulas are typically reused for multiple patients, with the cannulas being subjected to sterilization by steam, or other methods between uses. Although such sterilization has generally been sufficient to protect the subsequent patients, it is well-known that, due to the construction of a typical cannula, small tissue fragments may remain inside the cannula. It has also been prior practice in reusing cannulas to subject the cannulas to enzymatic cleaning agents, germicides, disinfectants, and other cleaning agents, which may also be partly retained inside the cannula. These residual tissue particles and/or chemical agents potentially subject the subsequent patient to an increased risk of complications during, or following a surgical procedure. It is highly desirable, therefore, to provide a surgical cannula and method which does not require or rely upon reuse of the cannulas.
It is also desirable that an improved cannula be configured and adapted for interchangeable use with commonly available suction and tissue removal, or aspiration equipment.
It is also desirable that an improved cannula be configured and adapted for interchangeable use with commonly available infiltration equipment.


A child resistant container made from blow-molded plastic which comprises: a vial having an outlet port; a pre-determined volume of aseptic fluid disposed sealed within the vial; a cap detachable from the vial; and, a resilient guard having a first and second ends which are integral to the vial on opposing sides. The resilient guard is designed to not be separated from contact with the vial and has a mid-portion which is initially positioned above the top of the cap to prevent cap removal. The safety container is preferably single use.

Blow-fill seal technology (BFS) refers to the manufacturing process used to produce various sized liquid filled vials ranging from as small as 0.1 mL to over 500 mL. Originally developed in Europe in the 1930s, it was introduced in the United States in the 1960s. Since the 1990s, BFS has become more prevalent within the pharmaceutical industry, and is now widely considered to be the superior form of aseptic processing by various medicine regulatory agencies including the U.S. Food and Drug Administration (FDA) in the packaging of pharmaceutical and healthcare products.
The basic concept of BFS is that a vial is formed, filled, and sealed in a continuous process without human intervention, in a sterile enclosed area inside a machine. Thus, BFS can be used to aseptically manufacture sterile pharmaceutical liquid dosage forms.
By way of example, machines sold under the trademark BOTTELPACK® by Rommelag® (www.rommelag.com) are used for production of various products using BFS. A machine sequence for the blow-fill seal process is described by Rommelag® as follows:
A plastic parison, extruded from polymer, is accepted by the opened blow mould and cut below the die of the parison head. The main mould closes and simultaneously seals the bottom. The special mandrel unit settles onto the neck area and forms the parison into a container using compressed air or vacuum. By way of the special mandrel unit, the product is precisely measured by the dosing unit and liquid is filled into the container. After the special mandrel unit retracts, the head mould closes and forms the required seal by vacuum. With the opening of the blow mould, the container exits from the machine and the cycle repeats itself.
U.S. Pat. No. 8,047,394 issued to Hansen discloses a safety device comprising a liquid medium which can be dispensed from a blow-molded vial utilizing the BOTTELPACK® process. In order to dispense the liquid, Hansen first requires that support points joining a head part to the vial body be broken and thereafter support points joining a head part to the vial body must be broken for removal of the head part exposing an opening for the liquid to be dispensed through. Hansen thus requires a two-step procedure for access to the liquid to be dispensed.
Hansen requires that an individual focus on the first step and once the support points of the first step have been broken, the individual can then focus on the support points of the second step. Because a child can focus its attention solely to breaking the support points of the first step and then to solely focus its attention on the second step, the current and predominant solution to making the product child-resistant is to incorporate secondary packaging. Such secondary packaging includes the use of foil wrap, over wrap, neck band, body band, etc. Unfortunately, implementation of secondary packaging increases manufacturing and labor costs, requires additional material, increases the time to manufacture, and further requires the use of multiple equipment as well as increased personnel training.
The required addition of secondary packaging which is necessary to ensure that a blow-fill seal constructed container is child-resistant has made sales of over the counter liquid medication in BFS packaging cost prohibitive.

Child resistant blow-fill seal container


A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a judging circuit. The cell array includes plural multi-level memory cells in an m×n array. The cell array is connected with m word lines and n lines. The current supply circuit provides one of plural reference currents according to a current control value. The path selecting circuit is connected with the current supply circuit and the n bit lines. The judging circuit is connected with the path selecting circuit, and generates n output data. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first judging device of the judging circuit is connected with the first path selector and generates a first output data.

As is well known, a non-volatile memory is able to continuously retain data after the supplied power is interrupted. Consequently, the non-volatile memory is widely applied to a variety of electronic devices. Generally, the non-volatile memories are classified into a one-time programmable non-volatile memory (also referred as an OTP non-volatile memory) and a multi-time programmable non-volatile memory (also referred as MTP non-volatile memory). The memory cells of the OTP non-volatile memory are OTP memory cells. The memory cells of the MTP non-volatile memory are MTP memory cells.
According to the stored data amount, the memory cells are classified into single-level memory cells and multi-level memory cells. Generally, one single-level memory cell is able to store a 1-bit data. That is, the data indicates a first storage state or a second storage state. Moreover, one multi-level memory cell is able to store a data with at least two bits.
For example, if the multi-level memory cell is able to store a 2-bit data, the data of the memory cell indicates one of a first storage state, a second storage state, a third storage state and a fourth storage state. Similarly, if the multi-level memory cell is able to store a 3-bit data, the multi-level memory cell has eight (=23) storage states. Similarly, if the multi-level memory cell is able to store a 4-bit data, the multi-level memory cell has sixteen (=24) storage states. Hereinafter, the circuitry structures of some types of non-volatile memory cells will be illustrated with reference to FIGS. 1A˜1E.
FIG. 1A is a schematic circuit diagram illustrating an OTP non-volatile memory cell. As shown in FIG. 1A, the OTP non-volatile memory cell c1 comprises a floating gate transistor F and a switching transistor M. The first terminal of the OTP non-volatile memory cell c1 is connected with a source line SL. The second terminal of the OTP non-volatile memory cell c1 is connected with a bit line BL. The control terminal of the OTP non-volatile memory cell c1 is connected with a word line WL.
Please refer to FIG. 1A again. The first source/drain terminal of the switching transistor M is connected with the source line SL. The gate terminal of the switching transistor M is connected with the word line WL. The first source/drain terminal of the floating gate transistor F is connected with the second source/drain terminal of the switching transistor M. The second source/drain terminal of the floating gate transistor F is connected with the bit line BL.
For writing the OTP non-volatile memory cell c1, proper bias voltages are provided to the OTP non-volatile memory cell c1. Consequently, the OTP non-volatile memory cell c1 is programmed. During the program action of the OTP non-volatile memory cell c1, the amount of hot carriers to be injected into the floating gate of the floating gate transistor F is controlled. Consequently, the storage state of the OTP non-volatile memory cell c1 is adjusted. Moreover, the hot carriers are electrons.
For example, when the write action is performed on the OTP non-volatile memory cell c1, a program voltage is provided to the source line SL, an on voltage is provided to the word line WL, and a ground voltage is provided to the bit line BL. Consequently, the hot carriers are injected into the floating gate through a channel region of the floating gate transistor F. Moreover, when the write action is performed, the adjustment of the time period of providing the bias voltages can control the amount of hot carriers injected into the floating gate. Consequently, the OTP non-volatile memory cell c1 has various storage states. If the time period of providing the bias voltages to the OTP non-volatile memory cell c1 is increased, the amount of hot carriers injected into the floating gate is increased. Whereas, if the time period of providing the bias voltages to the OTP non-volatile memory cell c1 is decreased, the amount of hot carriers injected into the floating gate is decreased.
According to the amount of hot carriers injected into the floating gate from low to high, the memory cell c1 has the storage states from a first storage state to an X-th storage state, wherein X is larger than or equal to 4. For example, if the multi-level memory cell c1 is able to store the 2-bit data, X=4. That is, the memory cell c1 is in one of a first storage state, a second storage state, a third storage state and a fourth storage state. Whereas, if the multi-level memory cell c1 is able to store the 3-bit data, X=8. That is, the memory cell c1 is in one of the storage states from the first storage state to the eighth storage state. Whereas, if the multi-level memory cell c1 is able to store the 4-bit data, X=16. That is, the memory cell c1 is in one of the storage states from the first storage state to the sixteenth storage state.
In addition to the time period of providing the bias voltages to the OTP non-volatile memory cell c1, the adjustment of the program voltage can adjust the storage state of the OTP non-volatile memory cell c1. Generally, as the magnitude of the program voltage is increased, the amount of hot carriers injected into the floating gate is increased. Whereas, as the magnitude of the program voltage is decreased, the amount of hot carriers injected into the floating gate is decreased.
For performing a read action, proper bias voltages are provided to the OTP non-volatile memory cell c1. Consequently, the OTP non-volatile memory cell c1 generates a cell current. According to the magnitude of the cell current, the storage state of the OTP non-volatile memory cell c1 can be judged. When the read action is performed, a read voltage is provided to the source line SL, the on voltage is provided to the word line WL, and the ground voltage is provided to the bit line BL. Consequently, the magnitude of the cell current is determined according to the storage state of the OTP non-volatile memory cell c1.
For example, if the multi-level memory cell c1 is able to store the 2-bit data, the magnitudes of the generated cell currents corresponding to the four storage states are different during the read action. For example, the generated cell current corresponding to the first storage state is 0.1 μA, the generated cell current corresponding to the second storage state is 0.6 μA, the generated cell current corresponding to the third storage state is 1.1 μA, and the generated cell current corresponding to the fourth storage state is 1.6 μA. Similarly, in case that the multi-level memory cell is able to store the 3-bit data, the magnitudes of the generated cell currents corresponding to the eight storage states are different during the read action. Similarly, in case that the multi-level memory cell is able to store the 4-bit data, the magnitudes of the generated cell currents corresponding to the sixteen storage states are different during the read action.
Generally, the magnitude of the program voltage is high. In order to prevent from damage of the switching transistor M during the write cycle, the OTP non-volatile memory cell may be further equipped with a following transistor. FIG. 1B is a schematic circuit diagram illustrating another OTP non-volatile memory cell. As shown in FIG. 1B, the OTP non-volatile memory cell c2 comprises a floating gate transistor F, a following transistor Mg and a switching transistor M. The first terminal of the OTP non-volatile memory cell c2 is connected with a source line SL. The second terminal of the OTP non-volatile memory cell c2 is connected with a bit line BL. The first control terminal of the OTP non-volatile memory cell c2 is connected with a word line WL. The second control terminal of the OTP non-volatile memory cell c2 is connected with a following line FL.
Please refer to FIG. 1B again. The first source/drain terminal of the switching transistor M is connected with the source line SL. The gate terminal of the switching transistor M is connected with the word line WL. The first source/drain terminal of the following transistor Mg is connected with the second source/drain terminal of the switching transistor M. The gate terminal of the following transistor Mg is connected with the following line FL. The first source/drain terminal of the floating gate transistor F is connected with the second source/drain terminal of the following line FL. The second source/drain terminal of the floating gate transistor F is connected with the bit line BL. Similarly, the OTP non-volatile memory cell c2 is also a multi-level memory cell. Generally, the operation of the switching transistor M and the operation of the following transistor Mg are similar. When the switching transistor M is turned on, the following transistor Mg is turned on. When the switching transistor M is turned off, the following transistor Mg is turned off. The bias voltages and the operating principles of the OTP non-volatile memory cell c2 for performing the write action and the read action are similar to those of the OTP non-volatile memory cell c1, and are not redundantly described herein.
FIG. 1C is a schematic circuit diagram illustrating an MTP non-volatile memory cell. In comparison with the OTP non-volatile memory cell c1 of FIG. 1A, the MTP non-volatile memory cell c3 further comprises an erase capacitor C. The erase capacitor C is connected between the floating gate of the floating gate transistor F and an erase line EL. When the write action and the read action are performed, a ground voltage is provided to the erase line EL, and the other bias voltages provided to the MTP non-volatile memory cell c3 are similar to those of the OTP non-volatile memory cell c1. The detailed operations are redundantly described herein. For performing an erase action, an erase voltage is provided to the erase line EL. Consequently, the hot carriers are moved from the erase capacitor C to the erase line EL and ejected from the floating gate.
FIG. 1D is a schematic circuit diagram illustrating another MTP non-volatile memory cell. In comparison with the OTP non-volatile memory cell c2 of FIG. 1B, the MTP non-volatile memory cell c4 further comprises an erase capacitor C. The erase capacitor C is connected between the floating gate of the floating gate transistor F and an erase line EL. When the write action and the read action are performed, a ground voltage is provided to the erase line EL, and the other bias voltages provided to the MTP non-volatile memory cell c4 are similar to those of the OTP non-volatile memory cell c2. The detailed operations are not redundantly described herein. Similarly, for performing an erase action, an erase voltage is provided to the erase line EL. Consequently, the hot carriers are moved from the erase capacitor C to the erase line EL and ejected from the floating gate.
In the non-volatile memory cells as shown in FIGS. 1A to 1D, the transistors are P-type transistors. Alternatively, the transistors of the OTP non-volatile memory cells and the MTP non-volatile memory cells are N-type transistors.
FIG. 1E is a schematic circuit diagram illustrating another MTP non-volatile memory cell. As shown in FIG. 1E, the MTP non-volatile memory cell c5 comprises a switching transistor M and a resistor R. The first terminal of the MTP non-volatile memory cell c5 is connected with a source line SL. The second terminal of the MTP non-volatile memory cell c5 is connected with a bit line BL. The control terminal of the MTP non-volatile memory cell c5 is connected with a word line WL.
The first source/drain terminal of the switching transistor M is connected with the source line SL. The gate terminal of the switching transistor M is connected with the word line WL. The second source/drain terminal of the switching transistor M is connected with the first terminal of the resistor R. The second terminal of the resistor R is connected with the bit line BL. The resistor R is made of transition metal oxide (TMO).
Generally, the resistance of the resistor R and the storage state of the resistor R can be determined according to the voltage difference between the first terminal and the second terminal of the resistor R. In other words, when the write action is performed, proper bias voltages are provided to the MTP non-volatile memory cell c5. Consequently, the storage state of the MTP non-volatile memory cell c5 is controllable.
FIG. 2 is a schematic circuit diagram illustrating a cell array of a non-volatile memory. As shown in FIG. 2, the cell array 200 comprises a plural memory cells c11˜cmn, which are arranged in an m×n array. Each of the memory cells c11˜cmn has the structure of the OTP non-volatile memory cell c1. It is noted that the structure of the memory cell is not restricted. That is, the memory cells c2˜c5 may be constituted as other cell arrays.
The memory cells c11˜cmn comprise switching transistors M1,1˜Mm,n and floating gate transistors F1,1˜Fm,n, respectively. Each of the memory cells c11˜cmn has the structure of the OTP non-volatile memory cell c1. The detailed structure of the memory cell is not redundantly described herein. The first terminals of the memory cells c11˜cmn are connected with a source line SL, wherein m and n are positive.
The control terminals of the n memory cells c11˜c1n in the first row are connected with a word line WL1. The second terminals of the n memory cells c11˜c1n in the first row are connected with the corresponding bit lines BL1˜BLn, respectively. The control terminals of the n memory cells c21˜c2n in the second row are connected with a word line WL2. The second terminals of the n memory cells c21˜c2n in the second row are connected with the corresponding bit lines BL1˜BLn, respectively. The rest may be deduced by analog.
Generally, during the write action or the read action of the non-volatile memory, only one of the m word lines WL1˜WLm of the cell array 200 is activated and the other word lines are inactivated. For example, if the word line WL1 is activated during the write action, the first row is the selected row. By controlling the time period of providing the bias voltages to the memory cells c11˜c1n of the selected row, the storage states of the memory cells c11˜c1n are controllable.

Non-volatile memory with multi-level cell array and associated read control method


Weaving heddles, intended for paired operation, are rendered spring-like resilient in the areas adjacent the end eyes to prevent breakage of the heddles in operation by the high degree of dynamic loading. Such spring-like resiliency is achieved by a provision of a shape change, such as a recess or inwardly bowed section, in the heddles adjacent the end eyes and at a location between the adjacent end eyes and the elongated shaft section of the heddle body.

This invention relates generally to paired heddles for weaving looms for the production of thickened warp in woven fabrics.
The heddles are paired on the weaving machine to facilitate the weaving of fabric with a heavy warp. Considering a single heddle pair, one of the two heddles is so shaped that its thread eye is positioned in a rear row, and the other heddle of the pair is so shaped that its thread eye is positioned in a forward row. Due to the offset of the thread eyes displaced from the center line of the frame bars on which the heddle pair is mounted upright, such arrangement assures that the passage for the warp even at the broadest part of the heddle, i.e., in the area of the thread eyes, is substantially increased.
Such heddles mounted in pairs are known in the art and are set forth in FIGS. 1, 2 and 9 of the drawings which will be described in more detail hereinafter.
Modern day weaving machines reach very high speeds of rotation resulting in that the loom shafts severely deform in operation because of the high dynamic loadings. This deformation reaches such a level that the play at which the heddles can arrange themselves orderly in a row on the heddle carrier bars of the loom shafts, disappears, and indeed is overcome. When the heddle play is overcome the heddles are stressed in tension along the length thereof. Heddles of modern design which are structured mainly to be symmetrical therefore are deformed into a shape which, at least partially, is inappropriate for the structural loads. Those heddles in the drawings designated 1, 8, 32 and 34 have a high degree of rigidity as compared with heddles 2 and 9. As a result heddles 1, 8, 32 and 34 tend to rapidly deform under tension.
Shown in FIG. 1 is a prior art heddle pair comprising heddles 1 and 2 respectively having centrally located thread eyes 4 and 6 respectively lying along the central axis of that portion of each heddle body which comprises an elongated shaft. The open thread eyes at opposing ends of the shaft provide, as is known in the art, for mounting the heddles in overlying relationship on upper and lower frame bars and/or shafts of the weaving machine (not shown). Thus the thread eyes are offset, to the left and to the right, from the central axis of the frame extending through the upper and lower frame bars.
Heddles 1 and 2 each has a row hole 17 as well as a stamping 18, as known in the art.
Similarly, the prior art heddle pair 8, 9 shown in FIG. 2 is essentially the same as aforedescribed with respect to FIG. 1 except that the end eyes at opposing ends of the shaft of the heddle body of each heddle are C-shaped rather than J-shaped. Thus heddles 8 and 9 respectively contain thread eyes 4 and 5 midway between their ends. In operation, heddle 1 of the heddle pair 1, 2 of FIG. 1 as well as heddle 8 of the heddle pair 8, 9 of FIG. 2, each exhibit a high tensile rigidity in a lengthwise direction, but have a tendency toward rupturing lengthwise, while the other heddles of the pairs, i.e., 2 and 9, respectively, remain undamaged under severe loadings. The reason for this difference in operational behavior could very well be attributed to the fact that the two heddles, 2 and 9, in the area between the end eyes and the thread eyes, i.e., between the end eyes and the heddle shaft, exhibit more resilience as compared to their respective heddles 1 and 8.


An apparatus for optical treatment using a light beam, which includes an apparatus body having a first control operation device for providing an optical treatment light and an optical fiber cable for introducing an optical treatment light from the apparatus body into a delivery unit. The apparatus comprises a light relaying device connected with both of the apparatus body and the delivery unit through the optical fiber cable, second control operation device provided in the light relaying device, optical communication device for transmitting and receiving light signals, the optical communication device being arranged in the apparatus body and the light relaying device respectively, an optical system for introducing the light signals which the optical communication device transmits and receives through the optical fiber cable.

1. Field of the Invention
The present invention relates to an apparatus for ophthalmic treatment using photocoagulation by a light beam.
2. Description of Related Art
There is known an apparatus for optical treatment to treat a patient's eye by irradiating a laser beam into its affected part, wherein the laser beam is introduced from an apparatus body into delivery unit, for example a probe or a microscope, through an optical fiber cable.
However, because the apparatus body is large in size and provided with a cooling system, it is impossible to move it easily.
In case of the use in different places such as a treatment room, an operating room, or plural operating rooms, plural apparatuses for ophthalmic treatment are generally provided. Additionally, use is made of an apparatus having an extended optical fiber cable and a control box which is connected to a body of the apparatus by a separate communication cable pulled from the body of the apparatus.
Further, an ophthalmic apparatus is proposed in Japanese patent Application No. HEI 2-312006 (Title of the invention: Adaptor for photocoagulation) by the present applicants, in which an optical fiber cable is provided with an adaptor for photocoagulation using a laser beam to compensate an emitting power of a semiconductor laser beam, the adaptor connected with the apparatus body through a communication cable.
During an ophthalmic operation using such apparatus mentioned above, it is possible to move easily the control box and the adaptor as needed for the operation. However, when the control box and the adaptor are frequently moved, the communication cable and line get entangled with each other, thereby causing the break down of the cable.
Additionally, when connected with plural control boxes arranged in different places, the communication cable is apt to affected by an electromagnetic and electrostatic influence from its surrounding environment, thereby causing a malfunction and attenuation of the signal.

Apparatus for ophthalmic treatment using a light beam


A user interface is animated and configurable to optimize, facilitate and simplify displaying on a display device and exploring via user input a hierarchy of information accessible by an electronic device.

A user interface in accordance with the present invention is easier to use than prior art user interfaces designed to serve the same purpose, primarily due to click focusing and node aggregation mechanisms. Parameters can be adjusted to display only a few nodes, in order to facilitate exploration, or thousands of nodes simultaneously, in order to facilitate an individual's understanding of the entire hierarchy of information.

This patent is subject to a terminal disclaimer.

Interface for displaying and exploring hierarchical information


A fuel supply device includes a fuel pump for delivering fuel within the fuel tank to the outside and a sub-tank having a temporary storage region capable of temporarily storing the fuel. The sub-tank includes an inflow opening to allow the fuel to flow into the sub-tank under its own weight. The temporary storage region includes a top part positioned above the inflow opening.

The present disclosure relates to a fuel supply device. More particularly, it relates to a fuel supply device for supplying fuel from within a fuel tank to an internal combustion engine, wherein the fuel tank is mounted to a vehicle, for example an automobile.
A fuel supply device used for supplying fuel from within a fuel tank to an internal combustion engine is widely known in the art. Japanese Laid-Open Patent Publication No. 2012-67736 discloses such a fuel supply device, with a configuration capable of temporarily storing fuel in one part of the device. In particular, this configuration enables fuel to naturally flow into a sub-tank through an inflow opening formed in the uppermost part of the sub-tank, wherein the fuel can be temporarily stored in the sub-tank. However, this configuration can still be further improved.


A method of operating a data processor when rendering a sequence of frames to produce a sequence of frames for display is disclosed. Each frame represents a view of a scene of one or more objects. The motion of one or more objects is tracked between frames in the sequence of frames. When data for a new frame in the sequence of frames is to be rendered, for a region of the new frame, the method involves determining, based on the tracked motion of one or more objects between frames in the sequence of frames, an amount of motion within the region between frames. The amount of motion is used to assign the region to a category of no, low, intermediate, or high motion. A rendering technique is selected for rendering the region based upon the category to which the region is assigned.

The technology disclosed herein relates to data processing systems, and methods of operating such systems, in particular in relation to the display of sequences of frames (images) on a display of a data processing system.
FIG. 1 shows an exemplary system on chip (SoC) data processing system 8 that comprises a host processor comprising a central processing unit (CPU) 1, a graphics processing unit (GPU) 2, a display processor 3, and a memory controller 5. The exemplary data processing system may also comprise a video engine (not shown in FIG. 1). As shown in FIG. 1, these units communicate via an interconnect 4 and have access to off-chip memory 6. In this system, the graphics processing unit (GPU) 2 will render frames (images) to be displayed, and the display processor 3 will then provide the frames to a display panel 7 for display.
In use of this system, an application such as a game, executing on the host processor (CPU) 1 will, for example, require the display of frames on the display panel 7. To do this, the application will submit appropriate commands and data to a driver for the graphics processing unit (GPU) 2 that is executing on the CPU 1. The driver will then generate appropriate commands and data to cause the graphics processing unit (GPU) 2 to render appropriate frames for display and to store those frames in appropriate frame buffers, e.g. in the main memory 5. The display processor 3 will then read those frames into a buffer for the display from where they are then read out and displayed on the display panel 7 of the display.
The data processing system 8 will be configured to provide frames for display, and the graphics processing unit (GPU) 2 will correspondingly be configured to render frames, at an appropriate rate, such as 30 frames per second. Modern electronic devices increasingly use higher resolution displays. For example, displays with a "4k" resolution are becoming more common (a so-called "4k display"). However, providing sequences of frames of the required resolution for display by such devices, at the refresh rate of the display, presents some challenges.
Various rendering techniques have been proposed to allow frames of a resolution and rate required for output, i.e. display, to be produced even where the frame producer, e.g. graphics processor, is unable to produce fully rendered frames at such a resolution and rate. Such techniques typically involve the frame producer generating new data for only a portion of a frame, with some form of processing then being performed to derive additional data to fill in the "missing" data in the remainder of the frame, and provide an output frame of the required level of resolution.
One such technique is known as "upscaling". In this technique, a lower resolution version of a frame is produced i.e. at a resolution level that the frame producer e.g. graphics processor is able to produce at the required rate. Thus, new data is generated in relation to only a portion of the frame. This lower resolution frame is then "upscaled" to provide a frame of a required resolution for output, (e.g. display). The process of upscaling may involve interpolating data in respect of portions, e.g. pixels, for which data has not been generated in the lower resolution version of the frame using the data in respect of adjacent portions e.g. pixels in the same frame.
Another technique which has been proposed more recently is known as "checkerboard rendering". In one example of this technique, for a first frame, new data is generated in respect to one half of the frame, i.e. the black blocks of a checkerboard pattern. In the next (second) frame, new data is generated in respect of the other half of the frame i.e. the white blocks of the checkerboard pattern. In a simple implementation, the "missing" data for any particular frame is based on the existing data generated in relation to the corresponding blocks of the previous frame. Thus, in the example, the data for the black blocks, which is newly generated in respect of the first frame, is used in providing the data for the black blocks in the second frame, along with the newly generated data for the white blocks. In the next frame, the data for the white blocks will be data based on that generated for the previous frame, while the data for the black blocks will be newly generated in respect of the new frame, and so on.
When implementing a checkerboard technique, the "missing" data in respect of certain blocks in a particular frame is based on data (newly) generated in a preceding frame in respect of those blocks. The data may simply correspond to the previously generated data for the blocks, or may be determined using some form of interpolation based on the previously (newly) generated data. In some more recent developments in relation to checkerboard rendering, the "missing" data for certain blocks in a frame is determined by interpolation based on tracking the movement of objects e.g. primitives between frames. It is possible to record the identity of individual objects e.g. primitives within a frame. For example, such functionality is provided by some modern Application Programming Interfaces (APIs), such as Vulkan. The ability to record the identity of individual objects within a frame correspondingly allows those objects to be tracked as they move between frames. Motion vectors may be derived for the objects.
It has been found that using checkerboard rendering in which data (newly) generated in respect of different subsets of blocks in different frames is combined, e.g. using interpolation based on the motion of objects between frames, to produce a frame of a desired resolution for output, may provide an improved version of a frame of a desired resolution level for output than may be achieved simply using an upscaling process based on a lower resolution version of the frame. The checkerboard rendering may thus provide the ability to reduce load on a graphics processor when providing higher resolution output frames, but with better image quality than may be achieved using an upscaling process. It will be appreciated that in an upscaling process, "missing" data is determined based upon newly generated data in the same frame, while in a checkerboard rendering process the "missing" data is determined using data (newly) generated in relation to a preceding frame.
Nonetheless, the Applicant has recognised that there remains scope for improvement in techniques for rendering a sequence of frames to produce a sequence of frames for display.
Like reference numerals are used for like components where appropriate in the drawings.