A device including a chirped Bragg grating, said grating having (a) a reflection bandwidth having a full-width at half maximum that is greater than 6 nm, and (b) a reflection delay ripple amplitude of less than xc2x150 ps.

The present invention relates generally to a device used for chromatically dispersing lightwave signals in fiber optics, and more specifically to a wide-bandwidth chirped fiber Bragg grating that has a low delay ripple amplitude.
Modern communication system providers are striving to increase the capacity of their systems to satisfy the rapidly growing exchange of information around the world. Increasing the data rate of a single wavelength channel is one strategy to increase the throughput on optical fibers. However, this approach is limited in that the data rate for a single optical channel will eventually reach practical limitations. An important strategy to further increase the available bandwidth is to add multiple wavelength channels. Multiple wavelength systems are referred to as being wavelength division multiplexed (WDM).
Optical communications systems are available with single-channel data rates at 10 Gbit/s and faster. To accommodate the spectral bandwidth of these signals, the channels in a WDM system are commonly spaced at 100 GHz, or xcx9c0.8 nm in the 1550 nm wavelength range. A device would have to be useful over bandwidths greater than xcx9c0.8 nm to be a truly multi-channel device in these WDM systems. Ideally a device would operate over a full communications band of wavelengths, so systems could be designed for any WDM or modulation scheme without needing to accommodate a specific dispersion correction module. Current communications bands are defined by optical amplifier operating ranges; for instance, the xe2x80x9cCxe2x80x9d band covers xcx9c1530 nm to xcx9c1560 nm and the xe2x80x9cLxe2x80x9d band covers xcx9c1570 nm to xcx9c1610 nm.
In these optical communications systems, short pulses of optical energy are sent through optical fibers to transmit information. These optical data pulse are comprised of a spectrum of wavelengths. Generally speaking, an unchirped pulse of duration xcfx84 has a spectral width of xcx9c1/xcfx84, e.g., a xcx9c1 nanosecond (10xe2x88x929 second) pulse has a xcx9c1 GHz (109 Hz) spectral width. As a pulse travels along standard singlemode fiber in the xcx9c1550 nm range, the shorter wavelength components travel faster than the longer-wavelength components. This effect, called chromatic dispersion, broadens the pulse to the point that it eventually interferes with neighboring pulses in a pulse train and introduces errors in the detected data stream. A number of solutions have been proposed for this problem, but only dispersion-compensating fiber (DCF) and chirped fiber gratings have been considered seriously as potential candidates for deployment.
Dispersion-compensating fiber has high levels of dispersion of opposite sign to that of standard fiber. To compensate for the dispersion introduced by an 80-km span of standard fiber, one would have to concatenate a xcx9c16-km length of DCF into the system. These compensation modules are bulky, and due to the fiber design, suffer high optical attenuation and increased optical nonlinear effects. However, DCF is used today since no serious alternative exists.
Fiber Bragg Gratings (FBGs) have emerged as a promising solution for dispersion compensation. An FBG is an optical fiber or other optical waveguide with periodic, aperiodic or pseudo-periodic variations of the refractive index along its length in the light guiding region of the waveguide. Gratings are usually written in optical fiber via the phenomenon of photosensitivity. Photosensitivity is defined as the effect whereby the refractive index of the glass is changed by actinic radiation-induced alterations of the glass structure. The term xe2x80x9cactinic radiationxe2x80x9d includes visible light, UV, IR radiation and other forms of radiation that induce refractive index changes in the glass. Typically an interferogram of UV radiation is made and then a photosensitive fiber is placed into it. The period of the resulting FBG in the fiber is the period of the interferogram scaled by the waveguides refractive index.
To function as a dispersion compensator, the grating period of an FBG is chirped to reflect lagging wavelengths before faster wavelengths, which must travel further into the grating before they are reflected. An optical circulator is used to separate the input of the device from the output. A dispersion compensating grating (DCG) module recompresses a data pulse that had been corrupted by chromatic dispersion, and optical system performance is enhanced. The longer the grating, the greater the DCG compression factor and the wider the bandwidth of the device.
As a practical matter, long length gratings for dispersion compensation are not available, since extreme tolerances must be maintained to manufacture quality long length gratings. Fabrication errors in chirped gratings create ripples in the group delay curve and thus inaccuracies in the dispersion correction. The impact of these ripples on optical system performance is poorly understood, but some system designers have predicted that these ripples must be less than xcx9c40 ps peak-to-peak for a DCG to be useful as dispersion compensators in most systems. However, the magnitude of the ripple needed to make a useful FBG dispersion correction device has not been verified. A ripple amplitude of xcx9c40 ps peak-to-peak can be caused by a 20% variation in the FBG UV-induced index change, a xcx9c0.3% dimensional change in a fiber core, or a xcx9c4 pm error in grating pitch. Given that the silicon-oxygen inter-atomic spacing in glass is xcx9c160 pm, it has been widely believed that holding these tolerances during grating inscription is not possible, and that fiber fabrication tolerances are limiting the quality of the gratings that they produce.
In 1995, a Swedish research group reported the fabrication of a long-length FBGs by stitching smaller FBGs together. A small grating was written, the fiber was translated by a grating period through a UV-interferogram with a high-precision linear stage, and then the fiber was irradiated again. This process was continued until a grating of the desired length was made. With their system, this group reported it fabricated gratings of up to 50 cm in length. Since this announcement, other groups have extended this work and have reportedly fabricated gratings up to 2.5-m-long. The range of motion of available high-precision staging has limited the length these FBGs.
Several groups have adapted stitching methods to make chirped long length gratings, but stitching errors have caused these gratings to have delay ripple amplitudes that are far too large for use as dispersion compensators in optical communications systems. To implement a stitching technique, one must have precise knowledge of a fiber location relative to the writing interferogram. The accuracy of location measurements is limited by the motion stage encoderxe2x80x94usually interferometer based, which is susceptible to several degradations, such as interpolator inaccuracies, noise in edge detection electronic circuitry, and random fluctuations in received interpolator-laser light.
Several feasibility studies have been completed where long-length FBGs, fabricated by stitching, have been used successfully at specific wavelengths as dispersion compensators in optical communication systems. Since the FBG delay ripple imposed very large distortion-derived system penalties at most wavelengths, the wavelength of the transmitting laser in the communication system had to be adjusted in these studies to obtain reasonable system performance.
A common procedure for determining chromatic dispersion of a device is the modulation-phase shift method, as described in Chapter 12 of Fiber Optic Test and Measurement (ed. D. Derickson, Prentice Hall PTR, NJ, 1998, ISBN #0-13-534330-5). The output of a narrowband, tunable optical source is intensity modulated and applied to the device under test. The transmitted (or reflected) signal is detected and the phase of its modulation is measured relative to the electrical modulation source. The phase measurement is repeated at intervals across the wavelength range of interest. The curve of the relative group delay is constructed by accumulating these group delay changes across the measurement wavelength range.
The group delay ripple is determined by fitting with least squares minimization a line or a low-order polynomial to the relative group delay curve, and then this polynomial is subtracted from the curve. The remainder of the subtraction is the delay ripple. Typically this ripple is considered as being xe2x80x9chigh frequencyxe2x80x9d ripple, i.e. ripple with a periodicity of less than the channel bandwidth of a communications system, and xe2x80x9clow frequencyxe2x80x9d ripple, i.e. ripple with a periodicity greater than that of a channel bandwidth. Herein high-frequency ripple will be considered as ripple with a periodicity of less than 80 pm (10 GHz @ xcx9c1550 nm), and low-frequency ripple will be ripple with a periodicity of greater than 80 pm. The high-frequency ripple adds an intra-pulse distortion to a communication signal that is difficult to correct, thus the high-frequency ripple is considered more critical than the low-frequency ripple, which merely adds a slight error to the dispersion correction.
Establishing a correlation between delay ripple amplitude and optical system performance has been confusing because different groups measure DCGs in different manners and, often, are not explicit about their measurement procedures.
Although several studies have demonstrated that DCGs could be used as dispersion compensators for a single communication channel, useful wide bandwidth devices have not been demonstrated, mainly because the delay ripple amplitude of these devices was too large. Widely chirped DCGs with several WDM channels operating across their bandwidth have been demonstrated, but because the wavelength of the transmitting laser in the communication system needs adjustment in all of these studies to obtain reasonable performance, these DCGs proved to have only very narrow sections of usable bandwidth across their entire bandwidth. If a wideband DCG with a large delay ripple is useful only over a very narrow range as a dispersion compensator, then the utility of this widely chirped device is lost. Others have demonstrated DCGs in laboratory systems where DCGs have been used to correct the dispersion in several channels of a communication system, but a DCG that covers only part of a communication band has limited appeal, since the system must be specially engineered to accommodate such a device. Gratings with a bandwidth of at least a third of a communications band (xcx9c10 nm) or half a band (xcx9c15 nm) have some appeal, since fewer accommodations for the device must be made to use it in a communications system than narrower devices.
Although DCF is used widely today to solve chromatic dispersion problems in high-speed optical communications systems, new DCF designs must attempt to match their dispersion and dispersion slope to be opposite to that of a given transmission fiber. But these DCF designs don""t exactly match the dispersion characteristics of their intended fiber and thus leave a residual dispersion that accumulates over multiple spans of transmission fiber. Since DCF designs can be complicated and difficult to manufacture, several transmission fibers do not yet have a matching DCF solution, and some fibers, due to their complex dispersion characteristics, seem unlikely that a perfectly matching DCF design is possible across a wide bandwidth.
There thus exists a need for wide bandwidth (i.e., greater than several WDM channel spacings and preferably a full communications band) fiber Bragg gratings that can compensate for the chromatic dispersion and dispersion-slope in lightwave communications systems across its bandwidth. There also exists a need in the art for a wide-bandwidth chirped fiber Bragg grating that has a low delay ripple amplitude (i.e.,  less than xc2x150 ps). These and other needs are met by the present invention, as hereinafter described.
In one aspect, the present invention relates to a device used for chromatically dispersing lightwave signals in fiber optics, and to a method for using this device to achieve chromatic dispersion. The device comprises a wide-bandwidth ( greater than 0.8 nm) chirped fiber Bragg grating that has a low delay ripple amplitude ( less than xc2x150 ps). These devices are useful as chromatic dispersion correction devices in high frequency (e.g., 10 Gbit/s) optical communications system. In contrast to previously known devices used for this purpose, these devices do not exhibit large fluctuations in system performance penalty across their bandwidth.
In another aspect, the present invention relates to a method and apparatus for fabricating long length FBGs. In accordance with this aspect of the invention, the fiber being written on is translated with xcx9c1 ppm (10xe2x88x926) velocity control. This is preferably accomplished by placing the fiber into a helical groove on a spool that is mounted to a rotary spindle. The spindle is rotated at a constant velocity, which is preferably regulated by a large flywheel. The groove on the spool acts like a thread on a screw so that, as the spindle turns, a linear stage is used to track the laser beam on the fiber, in a manner analogous to cutting threads on a lathe. Gratings that are tens of meters long can be fabricated with this method.

Wide-bandwidth chirped fiber bragg gratings with low delay ripple amplitude


An exterior trim assembly for use with a window or door surround in a building structure comprises at least one mantle for affixing above the window or door, and first and second pilaster assemblies for affixing on the sides of the window or door. The mantle comprises a mantle base and a corresponding mantle cover to affix to and cover the mantle base. Each pilaster assembly comprises a base and a cover element affixed to the base wherein each of the bases has a plurality of regularly repeating reinforced structural sections. At least two pilaster cover plates are provided, each pilaster cover plate is affixed to and covering one of the first and second pilaster bases.

1. Technical Field
This invention relates to decorative molding assemblies for framing openings of residential or commercial structures, and more particularly to a decorative surround molding apparatus for decoratively framing a doorway, window, patio door, garage door opening, etc. of a residential or commercial structure.
2. Discussion
Molding assemblies are used in a variety of applications to frame or xe2x80x9csurroundxe2x80x9d doorways, windows, patio doors, garage doors etc., to thus provide a decorative, aesthetically appealing framing for such doorways, windows or areas of a structure. In recent years, these surround-molding assemblies have been manufactured from plastics such as high-density polyurethane. In general, plastics provide significant advantages over natural wood. For example, door surround molding assemblies or components thereof manufactured from plastic are low in maintenance when compared with natural wood molding assemblies. Plastic molding assemblies are not susceptible to moisture and therefore will not decay, warp or splinter like natural wood. However, there is still a need to divert water away from the door or window. Advantageously, plastic surround molding assemblies or components thereof can be sawed, drilled, glued or nailed just like natural wood. Still further, during the manufacture of plastic molding assemblies, plastic can be tinted with dyes or other materials to provide molding assembly components which are of desired colors, thus obviating the need for painting prior or subsequent to installation on a structure.
Prior developed door surround molding assemblies have typically required the various components comprising the assembly to be secured directly to the structure via nails, threaded fasteners or other like securing implements. Most typically, the various components have been provided with one or more flanges including a plurality of apertures through which the nails or other like fastening elements are driven to secure each molding sub-component to the structure. While generally effective in securing the various door surround molding components to the structure, the requirement that nails or other like threaded fastening elements be used can sometimes add to the time and expense associated with installing the complete surround molding assembly. Once installed, should one component of the surround molding assembly need to be removed or replaced, the use of threaded fasteners or nails can sometimes complicate the task of removing and replacing the sub-components of the molding assembly. Also, there are times when flanges cannot be used and the molding components must be fastened to the structure in another manner such as fastening through the exterior face of the molding. However, because these fasteners are visible from the exterior face of the molding further work may be required to achieve an aesthetically pleasing appearance.
Accordingly, it is an object of the present invention to provide a surround molding for a doorway, window or other portion of a building to provide a decorative and aesthetically pleasing appearance, while hiding the fasteners that attach the molding to the support structure.
It is a further object to provide a versatile molding that can accommodate various other trim components that may abut the molding.
It is yet another object of the present invention to provide a surround molding assembly for a doorway, window, archway or other portion of a structure which provides a decorative, aesthetically pleasing appearance, and in which the components of the surround assembly include interlocking portions adapted to interconnecting two or more molding components together. In this manner, the decorative molding components of the assembly could be securely, yet releasably held to the structure, while reducing the use of nails, threaded fasteners or other like fastening elements.
Accordingly, it is another object of the present invention to provide a surround molding assembly for a doorway, window or other portion of a building to provide a decorative and aesthetically pleasing appearance, while enabling one or more sub-components of the molding assembly to be secured to the structure in a secure, yet releasable fashion, without the need for a large plurality of nails or threaded fasteners to be employed.
It is yet another object of the present invention to provide a surround molding assembly for a doorway, window, archway or other portion of a structure which provides a decorative, aesthetically pleasing appearance, and in which each of the components of the surround assembly include one or more securing portions adapted to releasably engage with one or more hanger members fixedly secured to the structure. In this manner, the decorative molding components of the assembly could be securely, yet releasably held to the structure, without the use of a large plurality of nails, threaded fasteners or other like fastening elements.
It is still another object of the present invention to provide a surround molding assembly adapted to be secured to a structure to surround a doorway, window, archway, etc., where the apparatus includes a pair of vertical molding members each including a securing portion which is releasably securable to a hanger member fixedly secured along vertical portions of the doorway or window, and an independent mantle molding member having a securing portion which is releasably securable to a hanger member secured to the structure.
It is yet another object of one or more embodiments of the present invention to provide a surround molding assembly for an oversized or any sized doorway, window, archway or other portion of a structure which provides a decorative, aesthetically pleasing appearance, and in which the components of the surround assembly include mantle bases and pilaster bases which interlock with corresponding trim elements in the same manner as one another for relative ease of assembly. Furthermore, the invention includes interconnecting cover molding components and may include a cap for covering any joint formed therebetween.
Further objects of invention may be understood from the following description and drawings, and the various claims.
The above and other objects are provided by a door surround molding apparatus and method of assembly in accordance with preferred embodiments of the present invention. A decorative molding strip comprises a base strip having spaced inside and outside edges and a plurality of apertures for attaching the base to a support structure. A decorative strip is spaced from the base strip and has spaced inside and outside edges for covering the base strip. A sidewall interconnects the inside edges of the strips and a living hinge interconnects the sidewall and the decorative strip. The sidewall also interconnects the base strip. The decorative strip may be pivoted about the living hinge to a closed position over the base strip to hide the apertures. A support member removeably interconnects the base strip and the decorative strip for supporting the decorative portion in a spaced relationship to the base strip in the closed position. A retaining mechanism retains the decorative strip over the base strip when the decorative strip is in the closed position.
The present invention also provides a decorative molding surround assembly for a door or window comprising a first decorative molding member having a first appendage, a second decorative molding member having an outer surface, and a third decorative molding member disposed between said first and second members. The third member interconnects the first and second members without external fasteners. The third member has a second appendage for receiving the first appendage for holding the first member in abutting relationship. The third member also includes an opening for retaining the outer surface of the second member.
In another aspect of the invention, the door surround molding apparatus, in one preferred embodiment, comprises at least one vertical molding member which is positioned closely adjacent a vertical portion of a doorway or window, and an associated hanger strip which is fixedly secured to the structure closely adjacent the vertical portion. The vertical molding member includes a securing portion which is engageable with its associated hanger member to enable the vertical molding member to be releasably secured to the structure without the use of nails or threaded fasteners extending through any portion of the vertical molding member itself.
The above-described preferred embodiment of the apparatus further includes a mantle molding member having a length sufficient to extend at least partially over, and preferably completely over, the doorway or window. The mantle molding member also includes a securing portion, which engages with a mantle hanger member fixedly secured to the structure over at least a portion of the doorway or window. The securing portion of the mantle molding member is releasably engageable with the mantle hanger member to thereby allow the mantle molding member to be at least partially secured to the structure by the mantle hanger member. In this manner, the assembly of the vertical molding members and mantle molding member are simplified considerably through the reduction in the number of nails or threaded fasteners which must be used to effect assembly of these components to the structure.
In the preferred embodiment described above, the apparatus further preferably includes an upper corner member associated with each one of the vertical molding members which is used to provide an aesthetically appealing interface or connection between upper terminal end portions of each of the vertical molding members and the terminal, length-wise end portions of the mantle molding member. In this manner, the upper corner members, when fixedly secured to the structure, provide the molding apparatus with a decorative, continuous-looking appearance which surrounds the doorway or window without any gaps or discontinuities between the various components of the apparatus which detract from the overall aesthetically pleasing appearance provided by the apparatus.
In the preferred embodiment described above, a pair of decorative base molding members are further preferably included for covering lower terminal end portions of each of the vertical molding members. The decorative base molding members thus provide an aesthetically appealing means for terminating the lower terminal end portions of the vertical molding members without significantly complicating the assembly of the overall molding surround apparatus.
In an alternative preferred embodiment of the present invention a molding member is disclosed which incorporates an enlarged lip portion extending along at least a major portion of the overall length of the molding member opposite longitudinal edges of the molding member. An alternative preferred embodiment of the hanger member is also disclosed which incorporates a pair of semi-circular channels adapted to receive the enlarged lip portions of the molding member when the molding member is secured to the hanger member. The hanger member further includes a plurality of upstanding support portions for providing support to the molding member such that the molding member will not readily flex if pressure is exerted against it after it is installed to the hanger member. To aid in installing the hanger member, an installation tool is also disclosed which permits the hanger member to be secured to the exterior surface of a building in a precise orientation.
Also disclosed are upper and lower installation supports adapted to be inserted within portions of a mantle molding member to provide support to the outer surfaces of the mantle molding member. The installation supports have outwardly extending legs that provide stability and further support to the outer surfaces.
The apparatus of the present invention also includes an internal corner member for draining away water collected on top of the mantle molding member so that the water does not enter behind any portion of the siding on the building. The internal corner member includes a channel, which receives water draining from an outer surface of the mantle molding member and directs the water away from the doorway opening in the exterior surface of the building. The internal corner member is easily covered by a decorative, outer corner member, which can be secured thereover.
In an alternative embodiment a window header assembly is disclosed which is adapted to be secured to an exterior flat surface of a structure, such as brick, or prior to the installation of siding on the structure. Another alternative embodiment of the window header assembly is securable directly over siding on the exterior surface of the structure.
In another embodiment of the present invention, a corner molding assembly is adapted for use with pilasters in a window or door surround of a structure having siding. The assembly has a base that is fastened to the structure. A corner block is positioned over the pilasters and siding and is fastened to the base through and access area in a front face portion. A decorative cover plate is secure to the front face portion to conceal the access area. The pilasters and base work together to direct water away from the door or window.
Also disclosed are decorative trim strips having first and second interlocking ends that may be interlocked with the ends of other trim strips to make a continuous trim strip. In this way, gaps caused by expansion in conventional mitered joints may be avoided.
In another trim assembly, a base having a decorative portion and a ring used to conceal a base flange may be used in conjunction with a mantle assembly to provide a decorative molding that directs water away from a door or window. Alternatively, the base and ring may be used alone to provide another decorative look.
In yet another embodiment, a surround molding assembly is provided for an oversized or any sized doorway, window, archway or other portion of a structure which provides a decorative, aesthetically pleasing appearance, and in which the components of the surround assembly include mantle bases and pilaster bases which interlock with corresponding trim elements in the same manner as one another for relative ease of assembly. Furthermore, the components may include interconnecting cover molding components and may also include a cap for covering any joint formed therebetween.


Embodiments of the present prevention disclose a service processing method, a communication system, and relevant devices to enable the user to more conveniently set ring tones and improve system security. The method includes: a management client located in a user terminal obtains a ring tone setting processing request of a user; and the management client sends the ring tone setting processing request to a service server through a mobile network so that the service server can perform corresponding processing according to the ring tone setting processing request. A communication system and the relevant devices are also disclosed in the embodiments of the present prevention. The embodiments of the present invention can enable the user to conveniently set the tone, reduce unnecessary network traffic, and improve system security.

With the continuous development of the data service, different types of customized services have now emerged. For example, a Customized Ring Back Tone service is a service that allows a terminal user to customize ring back tones.
The customized ring back tone means the customized ring back tone, also known as the color ring back tone, which is heard by the calling user before the called user goes off-hook while the called terminal begins ringing after the calling terminal originates a call to the called terminal.
This customized ring back tone service opens the network capabilities of operators to the user, and provides service support for the user to demonstrate personality. It caters for the strong desire of modern people to demonstrate personality, and accomplishes good market effects.
Currently, in order to implement the customized ring back tone service in the prior art, the user gets connected to the Internet through a computer and accesses the site specified by operators to set the customized ring back tone service. The settings made by the user for the customized ring back tone service include: playing different ring tones in different time segments, and providing different ring tones for different users. The user can add a new ring tone, modify or delete an existing ring tone, and set the relevant personal groups.
However, because to set the customized ring back tone service, a user needs to get access to the Internet through a computer and accesses the site specified by operators. For the users lacking a computer nearby or unable to access the Internet, the solutions in the prior art frustrate the users to set the customized ring back tone service in real time.
With popularization of Wireless Application Protocol (WAP), a method for the user to access the site specified by operators on a user terminal directly through the WAP emerges.
However, it is required that the corresponding site generates corresponding pages accessible to the user terminal, which increases the complexity and maintenance workload of the site. Moreover, the user is still unable to set the customized ring back tone if the site is not accessible for certain reasons (such as suffering malicious attacks or routine maintenance).
Secondly, the WAP protocol still involves connection to the Internet to access the site specified by operators. The user information is vulnerable to theft due to insecurity of the Internet.
Finally, when the user terminal directly accesses the site through the WAP, the site transmits some information unrelated to the ring tone setting (such as recommended ring tones, and pictures on the page) to the terminal, which generates unnecessary network traffic.

Service processing method, communication system and relevant devices


A computer-implemented method for classifying an unclassified process as a potentially trusted process based on dependencies of the unclassified process is described. A component loaded by the unclassified process is identified. A determination is made as to whether a hard dependency exists between the unclassified process and the loaded component. A hard dependency exists if the unclassified process depends on the loaded component in order to execute. The unclassified process is classified as a potentially trusted process if a hard dependency exists between the unclassified process and the loaded component.

The use of computer systems and computer-related technologies continues to increase at a rapid pace. This increased use of computer systems has influenced the advances made to computer-related technologies. Indeed, computer systems have increasingly become an integral part of the business world and the activities of individual consumers. Computer systems may be used to carry out several business, industry, and academic endeavors. The wide-spread use of computers has been accelerated by the increased use of computer networks, including the Internet. Many businesses use one or more computer networks to communicate and share data between the various computers connected to the networks. The productivity and efficiency of employees often requires human and computer interaction.
Users of computer technologies continue to demand that the efficiency of these technologies increase. These demands include demands to improve security related to sensitive information that may be stored on a computer and/or shared between users of multiple computers. For example, users of computer technologies may desire to identify unknown process as trusted or malicious before a malicious process damages or destroys information stored on a computer.
Malicious processes mask themselves as valid, trusted processes. Security measures implemented on a computer may not detect these malicious processes before they have rendered damage to sensitive data on the computer. As a result, benefits may be realized by providing systems and methods for correctly identifying or classifying processes as trusted or malicious. In particular, benefits may be realized by providing improved systems and methods for classifying an unclassified process as a potential trusted process based on dependencies of the unclassified process.

Systems and methods for classifying an unclassified process as a potential trusted process based on dependencies of the unclassified process


A tapered roller bearing (1a, 1b) satisfies the following three conditions: (a1) 0.8≦Hi/Dw≦1.2, (b1) 1.01≦dm/dh≦1.05, and (c1) 2.1≦L/Dw≦3.0, where a pitch circle diameter at a center of a roller length along an axis line (X) of each tapered roller (4) is (dm), the radial dimension of the inner ring (2) at an intersection of the inner ring raceway (2a) and a perpendicular line (v) extending from a position of the pitch circle diameter in a direction perpendicular to the axis line is the thickness (Hi) of the inner ring, a cross-sectional center diameter of the roller bearing is (dh), the length of the tapered roller (4) is the length (L) of the tapered roller, and a half of the sum of the large diameter dimension and the small diameter dimension of the tapered roller (4) is the diameter (Dw) of the tapered roller.

Conventionally, as roller bearings for ratably supporting the wheels of a heavy vehicle on the suspension system thereof, taper roller bearings having a large load capacity and high rigidity have been used favorably. In this kind of taper roller bearing, the outer ring is usually press-fitted into a housing with an interference and secured thereto, and the inner ring is secured to a shaft member with a very small clearance or an interference to prevent relative rotation therebetween; however, a creep phenomenon may occur in which the relative rotation therebetween is caused, for example, due to the change in load associated with the movement of the rolling elements. In particular, in a roller bearing being used under an outer-ring rotation load condition, in the case that the roller bearing is used under a heavy load condition in which P/C (P: bearing load, C: basic dynamic load rating) is more than 0.13, a creep phenomenon may occur at the inner ring serving as a stationary ring. This creep phenomenon may occur not only in taper roller bearings, but also in cylindrical roller bearings and spherical roller bearings being used under outer-ring rotation load conditions, such as in planetary gears for general industrial machinery.
While studying the creep phenomenon, the present inventors have found that the creep phenomenon is caused by the fact that when a heavy load is applied to a bearing, loads on the rolling elements thereof are increased, and local expansion and contraction on the surface of the inner ring raceway are increased at the time when the rolling elements pass.
More specifically, in the case that one point in the loaded area on the surface of the inner ring raceway is viewed, in a state in which a rolling element is placed on the surface of the inner ring raceway, the inner ring contracts in the radial direction and expands in the circumferential direction due to the load on the rolling element, and after the rolling element has passed, the inner ring returns to its original shape. Hence, each time each rolling element passes, the inner ring repeatedly expands and contracts in the circumferential direction, thereby causing a creep phenomenon in which the inner ring rotates with respect to the shaft. If this creep phenomenon is generated, wear occurs on the surface of the shaft, and abrasion powder on the surface gets into the bearing, thereby causing premature flaking.
It is conceivable to increase the interference of the shaft to suppress the creep phenomenon under the heavy load condition.
Furthermore, in the rolling element described in Patent Document 1, on the surface to be fitted on a mating member, a relief groove is formed in the stationary ring within a range not exceeding the width of the groove on the raceway surface. With this configuration, even if the raceway of the bearing is deformed elastically due to the passing of the rolling element, the elastic deformation is not transmitted to the mating member because the stationary ring is not made contact with the mating member, whereby the creep phenomenon can be suppressed.
Moreover, in the roller bearing described in Patent Document 2, the creep phenomenon is prevented by increasing the thicknesses of the inner ring and the outer ring.


A hollow, plastic sphere comprised of two equal halves fitted together with a strap protruding from within the hollow sphere. The sphere opens to allow storage of a baseball or softball and is placed into the pocket of a baseball or softball glove. The strap protruding from within the sphere is extended around the glove and tightened, snugly fitting the sphere in the pocket of the glove. The hollow sphere is strapped into the glove between uses of the glove to help protect and form the glove's pocket and allow for convenient storage of a baseball or softball.

1. Field of the Invention
This invention relates in general to softball and baseball. More specifically, this invention relates to a preferable and proper way of forming and protecting the pocket of a baseball or softball glove during the off-season and between uses during the season; and a convenient way to store a softball or baseball during the off-season and between uses of the baseball or softball glove during the season.
2. Prior Art
Creating a pocket in a softball or baseball glove helps players field balls and makes the glove more comfortable. Better fielding enhances the player's ability to play and fewer errors or missed balls makes the game of softball or baseball safer to play. This invention will also help protect the baseball or softball glove when not in use. When a glove is stored, or during travel, the glove is often flattened out and the user must re-form the pocket. Often, softball and baseball players will stuff clothes or other materials into their gloves to protect the pocket because no other alternative exists. Simply putting a softball or baseball into a glove when the glove is not in use will not help form a pocket because softballs and baseballs are not large enough and will easily roll out of the glove. But because so many players do like to keep their ball with their glove, this invention allows the player to continue this practice.


Some embodiments are directed to a surgical robotic system including a suspension structure 1, a carriage 2 arranged to be mounted to the suspension structure, and a manipulator arm 3 arranged to be detachably docked to the carriage via a docking mechanism. The docking mechanism includes a first docking connector on the manipulator arm and a second docking connector on the carriage. The first and the second docking connector may establish an electrical connection between the manipulator arm and the carriage when the manipulator arm is docked. The manipulator arm includes a connector for connecting the manipulator arm via a cable to an electric power supply, and be configured to supply the carriage with the electrical power via the electrical connection when the manipulator arm is docked.

Some embodiments of the presently disclosed subject matter relate to a surgical robotic system including a carriage and a manipulator unit, and a drape for use with the surgical robotic system.
Nowadays many surgeries are performed by surgical robots. These surgical robots may include so-called manipulator arms which generally have an end effector which handles a surgical tool acting upon the patient. It may be desirable for the manipulator arm to be movable along a suspension structure so as to allow the manipulator arm to be easily moved or repositioned during surgery.
For example, DE 10 2014 203 921 A1 describes a guide system for surgical robots. The guide system has a guide with at least one rail. At least one carriage is connected to and can be displaced along the guide. For that purpose, the carriage may include an electric motor. Furthermore, the carriage has a receptacle for at least one robot arm on which robot arm is detachably connectable with the receptacle.
Another example is US 20060149418 A1 which describes a robotic system for performing surgical operations using a plurality of robotic arms remotely controlled by at least one operator console. The system includes a track system configured for mounting to a patient support table and a plurality of base stations for operatively coupling each of the robotic arms to the track system, such that each of the base stations include a housing, a first connector for coupling the housing to the track system, the first connector configured for facilitating movement of the housing along the track system while coupled thereto, and a second connector for coupling the housing to the proximal end of at least one of the robotic arms, the second connector configured for providing at least one of power supply, control signaling, and data communication with respect to the coupled robotic arm.
Disadvantageously, the known robotic systems do not enable a user to attach and detach a manipulator arm during surgery in a sufficiently safe manner.

Surgical robotic system with carriage and manipulator unit


A vertical semiconductor power switch has a semiconductor body having a first surface and a second surface. At least one anode and one control electrode are positioned on the first surface and at least one cathode is positioned on the second surface. The cathode comprises a multi-layer contact structure which comprises an inner contact layer positioned directly on the second surface of the semiconductor body, and an outermost layer consisting essentially of a Ni-alloy.

A vertical semiconductor power switch may be provided by a vertical semiconductor transistor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Isolated Gate Bipolar Transistor) device. Since the device is vertical, contacts or electrodes are positioned on two opposing surfaces of the body of the device. Semiconductor power switches are typically packaged to form an electronic component which includes a rewiring structure which enables the two opposing surfaces of the switch to be electrically contacted from the outer contacts, e.g. pins, of the electronic component.
There is a general demand for increasingly miniaturized electronic components and/or increased performance from a package of a given size. This demand has lead to the development of electronic modules or so-called System-in-Packages which include several semiconductor components. The increasing miniaturization and performance of the electronic component has lead to a requirement for improved heat dissipation from the packages in order to avoid failure of the device due to over-heating. A consequence of these developments is an increase in the number of different types of package in which vertical semiconductor power devices are accommodated.

Vertical semiconductor power switch, electronic component and methods of producing the same


The present invention provides a human photoaged skin model and an animal model, and a method of making the same, for evaluating cosmetics and similar products in terms of their anti-aging or rejuvenating effect.

As we grow older, our skin—the human skin—ages; elasticity is lost and wrinkles appear. As compared with skin areas protected from light, other skin areas that tend to be constantly exposed to sunlight, especially to ultraviolet irradiation (UV), i.e., the face, neck, and shoulders, produce significant wrinkles, sagging skin, age spots, and freckles as a result of chronic exposure to UV rays. UV rays also act to lower elasticity of the skin, increase darkening or yellowing of the skin, and reduce the moisture content of the keratinous layer. The skin aging phenomenon uniquely occurring in UV-exposed skin areas is called photoaging. In order to elucidate the photoaging mechanism of the skin and to evaluate cosmetics, pharmaceuticals, and similar products which are thought to be useful for preventing or mitigating unfavorable outcomes of photoaging; i.e., wrinkles, age spots, and freckles, a photoaged skin model would be useful if it reflects conditions of the human photoaged skin more faithfully.
For creating a photoaged skin model or an animal model, chronic exposure to UV-rays has usually been performed. Hitherto, the following exemplary methods have been known: a method in which the back skin of a hairless mouse or the paw pad skin of a rat is continuously irradiated with UV rays every day for several weeks ((1) Bissett D L, Hannon D P, and Orr T V, Photochem Photobiol. 1987; 46(3): 367-78, (2) Imayama S., Nakamura K., Takeuchi M., Hori Y., Takema Y., Sakaino Y., and Imokawa G., J. Dermatol Sci. 1994 7(1): 32-8)) and a method in which a three-dimensional model skin is irradiated in vitro with a single dose of UV light ((3) Nelson D., Gay R J, Photochem Photobiol. 1993; 57(5): 830-7).
In relation to a model established on the basis of the human skin, there has been known a method in which a nude mouse to which human skin is transplanted is irradiated with a single dose of UV light ((4) Del Bino S., Vioux C., Rossio-Pasquier P., Jomard A., Demarchez M., Asselineau D., and Bernerd F., Br J. Dermatol. 2004; 150(4): 658-67). However, in this model system, daily, continuous irradiation for several weeks is not envisaged. Accordingly, although this prior art method makes use of human-derived skin, a sufficient photoaging condition cannot be induced in the transplanted human skin, because UV irradiation is performed for only a short period of time. Thus, the model requires improvements before being recognized as a satisfactory human photoaged skin model. Presently, there has never been obtained a satisfactory human skin model or an animal model that better mimics human photoaged skin.


Described herein are a channel, system and method for monitoring voltages. Typically, the system includes multiple channels, each for sampling one of the voltages. The channels are physically and electrically coupled to a back end board on which is mounted a field programmable gate array (FPGA) that instructs the channels to simultaneously sample the voltages. Optionally, the channel is powered using an power supply that is isolated from the back end board, and transmits information over an electrically isolated connection to the back end board. The channel also includes voltage signal processing circuitry for processing the voltage signal on board the channel, and has stored on it channel identification information composed of at least one of an operating mode of the channel and a serial number of the channel, which can assist with voltage signal processing.

A common manner of manufacturing a large voltage source capable of outputting a relatively large voltage is to connect in series a plurality of smaller voltage sources, each of which is capable of generating a relatively small voltage. The relatively small voltages generated by the plurality of smaller voltage sources connected in series cumulatively result in generation of the relatively large voltage. Such a technique is common and is used, for example, when generating a relatively large voltage using a stack of fuel cells or a series connection of battery cells for use in an electric vehicle.
Some challenges that arise when generating a relatively large voltage using a series connection of smaller voltage sources include those of inexpensively, accurately, quickly and simultaneously obtaining voltage measurements of any one of the smaller voltage sources. For example, when generating a relatively large voltage using a stack of fuel cells, monitoring the voltage generated by the individual fuel cells in the stack is important, for example, to ensure that the power being drawn from the stack does not force any individual cell into a detrimental or undesirable operating range. When generating a relatively large voltage using a series connection of battery cells in an electric vehicle, monitoring the voltage of individual battery cells is important, for example, to ensure that no cell is operating in an overcharged or undercharged state, as operation in such states can decrease overall battery performance and reduce battery life.
While systems and methods exist for measuring the voltage of individual or small groups of such smaller voltage sources, such systems and methods are lacking in several respects. Conventional systems and methods typically are limited to common mode voltage abilities of approximately 200 to 300 Volts, and their ability to be used in conjunction with a large voltage source capable of generating, for example, 1 kV or more is limited. Furthermore, conventional systems and methods are not very accurate, often having accuracies limited to about +/−5 mV.
Accordingly, there exists a need for a system and method for monitoring voltages that improves on at least one of the deficiencies of the prior art.

Channel, system and method for monitoring voltages


A nutcracker preferably includes a cracker unit, a support structure and a hand held base. The cracker unit preferably includes a support base, a crank unit, a nut base and a pair of jaws. The support base is slidably engaged with the nut base through a pair of guide rods. The pair of jaws are attached to the support base and nut bases. The crank unit preferably includes a lead screw, a ratchet mechanism and a crank arm. A lead screw retainer is retained on the support base and pivotally retains the lead screw. The lead screw nut is retained on the nut base and threadably receives the lead screw. A bottom of the support structure is attached to the hand held base and the nut base plate is attached to a top of the support structure.

1. Field of the Invention
The present invention relates generally to shelled nuts and more specifically to a nutcracker, which allows hard shell nuts, such as hickory nuts to be cracked in a controlled manner.
2. Discussion of the Prior Art
U.S. Pat. No. 1,227,570 to Black discloses a pecan cracker. U.S. Pat. No. 2,697,462 to Connor discloses a reciprocating jaw type nutcracker.
Accordingly, there is a clearly felt need in the art for a nutcracker, which includes a ratcheting crank for positioning a crank arm, a hand held base and replaceable jaw members.


A method for static analysis of a software model of a circuit clocked by two clocks where the two clocks' periods are multiples of a greatest common divisor period. In the invention, a composite clock is determined with a period equal to the least common multiple of the periods of the two clocks, and the model is statically analyzed relative to the composite clock.

This invention relates to static analysis of integrated circuit designs.
Prototyping a VLSI (very large scale integrated circuit) design is extremely expensive: fabbing (fabricating) a pass of a prototype full-custom VLSI chip would take several months and would cost several hundred thousand dollars. If the chip design is flawed, the chip itself is almost impossible to probe to isolate the problem and determine corrections to the design. For this reason, virtually all VLSI chips are designed and thoroughly verified by software modelling before the first actual silicon is fabbed.
A timing verifier is one program in the suite of tools used by a VLSI designer. Timing verification is the process of analyzing the circuit model to ensure that the signals propagate through the logic quickly enough to meet the timing requirements at a specified clock frequency. (A timing verifier may also have bundled in other analyses, for instance for race conditions or other logic problems.) Once the circuit has been largely designed using other tools of the suite, the timing verifier is used to improve it, e.g., to eliminate bottlenecks that would force the circuit to be run at a slow clock frequency. The timing verifier takes as input a description of the circuit and its interconnections, the impedances and/or loading of the wires, specifications of the devices in the logic path, and descriptions of the clocked elements, and produces as its output timing of the slowest paths, i.e., the "critical paths", from which the designer can deduce the maximum clock frequency at which the circuit can be run. The designer can then redesign the critical paths to speed them up, thus speeding up the entire circuit. This process is typically iterative: the designer runs the timing verifier, and modifies his circuit design using the information generated. He repeats this process until the number of critical paths with the same timing limit is so large that reducing the time of all of them becomes impractical.
In a synchronous integrated circuit (IC) design, major signals captured in latches at clock edges and are held at stable values when and while the clock is deasserted. The value of the signal at the output of a latch, a latched signal, is only allowed to change during the time the clock signal is asserted. During the time the clock is asserted, changes on the D input to the latch immediately propagate through the latch to the Q output; thus the clock assertion is said to make the latch transparent. The latched signals propagate downstream through combinatorial logic to other latches. The timing verifier reports any latches (or other clocked element) whose inputs are not stable in time to meet the requirements of the latch's clock.
FIG. 1 depicts a simple illustrative circuit, which will be considered under a simplified model of timing constraints and design rules. Two input signals A 100 and B 102 are latched by latches 108 and 110. Thus, signals A' 112 and B' 114 are stable except when the two latches 108 and 110 are transparent, which occurs when clocks Ck.sub.A 104 and Ck.sub.B 106 are asserted. Once A' and B' have been latched, they remain stable, and combinatorial logic CL.sub.1 116, CL.sub.2 120, and CL.sub.3 122 compute signals Y 124 and Z 126. Each of CL.sub.1, CL.sub.2, and CL.sub.3 impose a certain delay in this computation. The downstream part of the design (not shown) relies on Y 124 and Z 126 being latched by latches 132 and 134 on clocks Ck.sub.Y 128, and Ck.sub.Z 130. Thus, CL.sub.1, CL.sub.2, and CL.sub.3 must be fast enough to meet the setup requirements of latches 132 and 134.
FIG. 2 presents a timing diagram for the circuit of FIG. 1. The first three lines show the clocks Ck.sub.A 104, Ck.sub.B 106, Ck.sub.Y 128, and Ck.sub.Z 130. In this example, A and B are latched on the same clock. Signals A and B must be stable far enough before the falling edge of Ck.sub.A /Ck.sub.B 206 to accommodate a "setup time" 208, a characteristic of latches 108 and 110. Once latches 108 and 110 become transparent during Ck.sub.A /Ck.sub.B 204, (assuming that the setup time and the data-to-output time of the latches are equal) signals A' and B' are allowed to transition until they are latched on the falling edge of Ck.sub.A /Ck.sub.B 206. A' and B' drive CL.sub.1, CL.sub.2, and CL.sub.3, which in turn produce signals X, Y, and Z. Under the simplified timing rules, the timing constraints of the circuit are satisfied if the propagation delay 208 of latch 108 plus the propagation delays through CL.sub.1 216 plus CL.sub.2 220 plus the setup time 232 of latch 132 is less than the time from the fall of clock Ck.sub.A /Ck.sub.B to the fall of clock Ck.sub.Y 228, and if the propagation delay 208 of latch 110 plus the time delay through CL.sub.1 216 plus CL.sub.3 222 plus the setup time 234 of latch 134 is less than the time from the fall of clock Ck.sub.A /Ck.sub.B to the fall of clock Ck.sub.Z 230. The paths of A'--CL.sub.2 --Y and B'--CL.sub.3 --Z must also meet the timing requirements of latches 132 and 134, but these will be trivially satisfied because they are clearly faster than paths A'--CL.sub.1 --X--CL.sub.2 --Y and B'--CL.sub.1 --X--CL.sub.3 --Z. When all these conditions are satisfied, the circuit is said to pass timing verification.
If the circuit fails timing verification, the timing verifier will report the critical paths that failed. Either the logic on the slow paths needs to be redesigned to be faster, or the clock frequency needs to be slowed down to accommodate the timing of the circuit.
Timing verifiers operate on one of two general paradigms: dynamic or static.
In dynamic timing verification, the circuit design is simulated through time. The engineer must determine model input stimuli with which to drive the circuit model, called test vectors. Applying dynamic timing verification to the sample circuit to FIG. 1, the timing verifier would successively apply twelve stimuli where either A or B or both undergo transitions: AB->AB={00->01, 00->10, 00->11, 01->00, 01->10, 01->11, 10->00, 10->01, 10->11, 11->00, 11->01, 11->10 } and run a loop to simulate time, during which model clock Ck.sub.A /Ck.sub.B would undergo several transitions. The circuit model would be operated through time to see at what time signals Y and Z stabilize. Dynamic timing verification is effective in that it is capable of diagnosing all timing problems, at least for the test vectors applied. But in modern circuit designs, the super-exponential combinatorics on tens of thousands of signals is fatal to the dynamic approach: there simply isn't time to test all possible combinations of inputs (most of which would never arise in actual operation), nor for a human to filter out a set of meaningful test vectors that will test all the effective paths.
In the second paradigm, static analysis, there is no loop simulating the passage of time. Static analysis is to dynamic analysis as theorem proving is to case analysis: instead of attempting to simulate a "large enough" number of specific cases, a static timing verifier "reasons" about the circuit model and draws inferences about whether the circuit will meet its timing constraints. This generally involves analyzing every node--i.e., every wire--in a circuit and calculating transition times based on the arrival time of inputs and the propagation delay through the structures. As the times of the transitions of the inputs to a node are analyzed, only the latest transition (in time) is saved, and the algorithm immediately stops tracing any path that is known not to be the worst case. This process, called information pruning, is required to keep the execution times reasonable.
One known algorithm for static timing verification is a depth-first search (DFS) of the circuit starting at each signal guaranteed on a clock edge, labelling each node with the currently best-locally-known worst-case timing information. After all nodes have been labelled, a second pass examines all timing constraints to tell the designer whether the circuit as a whole meets its timing constraints.
Consider the circuit of FIG. 3, in which a first stage of the circuit has two paths of different delay times, which join at a multiplexer. The output of the multiplexer fans out in a second stage of two paths of different delay times, which are joined at a second multiplexer. The DFS algorithm represents each node of a circuit by a data structure as shown in FIG. 4. The node has a name, a "worst case arrival time," and a pointer to the node that drove this worst-case transition.
FIGS. 5a-e depict a DFS analysis of the circuit of FIG. 3: FIG. 5a shows a time-sequence of stack states, and FIGS. 5b-e show a time sequence of states of data structures.
In the DFS algorithm, the graph of the nodes of the circuit is walked in a depth-first order. The algorithm's walker maintains a "current arrival time," and a stack of nodes. (Since this is a static analyzer, note that the arrival time does not "tick" off time incrementally, it moves forward and back by the discrete amounts of delay of the logic walked.) The DFS walker pushes nodes onto the stack as it traces paths downstream, and pops them as it unwinds back upstream. The walker increments its arrival time as it walks downstream through logic by the time delay of the logic, and decrements it the same amount as it unwinds back. As the algorithm pushes each node, if the walker's arrival time is later than the current "worst case arrival time" (or simply ".time") of the node, then the node is updated with the value of the DFS arrival time, and the node's "worst case predecessor" (or simply ".predecessor") is pointed at the predecessor node down which the DFS walk came, and the DFS continues down the successor nodes. If the DFS arrival time is equal to or earlier than the current node's worst case arrival time, the probe of this path is abandoned, and the node is popped off the stack.
In FIG. 5a, each column depicts a step 300 identified by number, and the value of the DFS arrival time 302 during that step. The state of the DFS stack 304 is also shown, with the top of the stack in bold. The term "labelled" is used to describe information permanently (though overwritably) stored in the representation of the circuit. "Unvisited" is used in a local sense: a node is unvisited if it as not been visited via the current path, even if it has been previously visited via a different path.
step 1: FIG. 5b shows the configuration of the nodes for the circuit of FIG. 3 as the algorithm visits the first node of the circuit, node A 310. All the node names have been filled in. A.predecessor and A.time have been filled in (by the process about to be described in detail). PA0 step 2: Assume that A's list of successor nodes is ordered such that the algorithm visits C, then B. Thus, the algorithm walks to node C. Since the logic connecting A to C, CL.sub.2, consumes 11 ns, the DFS algorithm carries the arrival time 12 as it arrives at C. The algorithm, finding C not already labelled, labels C.time with 12 and points C.predecessor to A. PA0 step 3: The only successor of C is D, through logic consuming 1 ns, so the algorithm proceeds to D and sets D.time 13 and points D.predecessor to C. Assume that D's list of successor nodes is ordered such that the algorithm visits node E, then F. PA0 step 4: Node E is filled in with time 26 and predecessor D. PA0 step 5: Node G is filled in with time 29 and predecessor E. The walk would continue downstream from node G. PA0 step 6: DFS pops its stack to back E. E has no unvisited successors. PA0 step 7: DFS pops its stack back to D. D has an unvisited successor, F. PA0 step 8: Node F is filled in with time 32 and predecessor D. PA0 step 9: When DFS arrives at node G with arrival time 33, it finds the node already labelled, but with a time earlier than the current DFS arrival time. Thus, G is updated with time 33, and G.predecessor is updated to point to node F. Note that pointing G.predecessor from E to F "prunes" from the graph all analysis downstream of E that was computed between steps 5 and 6. The algorithm has proved that E cannot possibly be on the critical path to G nor any node downstream of G. Because G has been relabelled, the nodes downstream of G must be walked again to have their times updated. PA0 step 10: DFS pops its stack back to node F. PA0 step 11: DFS pops its stack back to node D. D has no unvisited successors. PA0 step 12: DFS pops its stack back to node C. PA0 step 13: DFS pops its stack back to node A. The next unvisited successor of A is B. PA0 step 14: B is labelled with time 8 and predecessor A. PA0 step 15: DFS arrives at node D with arrival time 9. The arrival time is earlier than the current time of node D; thus, the algorithm stops probing along this path: all paths downstream of node D through node B are also said to be "pruned."By the same reasoning used in step 9, the algorithm has proved that the critical path to all nodes downstream of D must pass through C, not B. PA0 step 16: DFS pops its stack back to node B. PA0 step 17: DFS pops its stack back to node A. Node A now has no unvisited successors.
The intermediate state after step 5 is shown in FIG. 5c. The "worst-case arrival times" 322 have been filled in with a preliminary estimate of the latest transition time. The .predecessor pointers 320 show a preliminary estimate of the critical path to G, A--C--D--E--G. After the algorithm has visited all downstream logic and popped its stack to G:
The intermediate state after step 9 is shown in FIG. 5d.
Finding no unvisited successors of A, the DFS algorithm is complete. The result of the algorithm is the critical path graph of FIG. 5e. For instance, the critical path to node G can be discovered by tracing the .predecessor pointers from a node; e.g., the critical path to G is seen to be A--C--D--F--G. The critical path graph will be of the form of a forest of trees, each tree rooted at one of the input nodes or interior latches. Paths B--D and E--G have been pruned; no larger path that would have used these paths will be analyzed.
There may be multiple critical path graphs built for a single circuit, for instance one for a rising clock edge and one for a falling edge. Each node will have at most a single out-edge pointing to the latest-transitioning driver node for the given clock edge (or to one of several equally-late transitioning). The critical path graphs superimpose without effect on each other. Without loss of generality, the disclosure will discuss single critical path graphs.
Once the timing verifier has identified the critical path to every node, the designer will redesign parts of the circuit to speed up the logic on the critical path, and then run the timing verifier again. If the designer successfully speeds up a structure on the critical path, subsequent runs of the timing verifier on the altered circuit will very likely produce a different critical path graph.
Pruning is essential to making static analysis practical. A naive DFS walk of a circuit would take time exponential in the number of edges between the nodes of the circuit. Though it is possible to construct artificial examples in which DFS algorithms, even with pruning, exhibit exponential time complexity, in practice pruning reduces the time complexity from exponential to nearly linear. With pruning, a single run of DFS and violation sorting of a full microprocessor design can take about fifteen CPU minutes. Without pruning, such analysis would be infeasible.
Static timing verifiers consider clocks as a distinct class of inputs from all other signals. Clocks are treated as independent variables--as the givens of the system. The times of all other signals are stated relative to the clock's phase boundaries.
Some systems have two (or more) subsystems operating at different frequencies, both derived by frequency dividing a single primary clock. For example, the frequency dividers 602 and 604 of FIG. 6 convert a 20 ns symmetric primary clock 600 into a fast 40 ns cycle time divided into four phases of clocks 610-613, and a slow 120 ns cycle time divided into three phases of clocks 620-622. The fast cycle has four phases, .phi..sub.1F, .phi..sub.2F, .phi..sub.3F and .phi..sub.4F, with each of the four phases asserted for 10 ns. The slow cycle has three phases, .phi..sub.1S, .phi..sub.2S and .phi..sub.3S, each phase asserted for 40 ns. The fast cycle might be used in the fast-executing CPU core while the slow cycle might be used in peripheral bus operations.
Known timing verifiers analyze systems relative to a single synchronous clock. FIG. 7 shows a timing diagram in the frame of reference in which these known timing verifiers analyze the circuit of FIG. 8 when the circuit is clocked by the clocks generated in FIG. 6. In this circuit, latch L.sub.1 drives combinatorial logic CL.sub.1, which in turn drives latch L.sub.2. Latches L.sub.1 and L.sub.2 are clocked by a signal derived by ANDing selected clock pulses of FIG. 6. Input signal A just meets the setup time requirements of latch L.sub.1, which is transparent when Z.sub.1 =.phi..sub.4F .multidot..phi..sub.1S is asserted. Thus, B must be assumed unstable during Z.sub.1. Because of the "single synchronous clock" constraint, the circuit must be analyzed relative to the fast .phi..sub.F clock, as shown in FIG. 7. Node B is unstable 630 during the time that latch L.sub.1 is transparent 632; in the four-phase .phi..sub.F system, this must be modelled as the time that clock .phi..sub.4F is asserted 634. Node C settles 10 ns later 636. In the four-phase system, latch L.sub.2 must be modelled as transparent 638 during the time that clock .phi..sub.1F is asserted 640. In the four-phase system, C settles too late to satisfy the set-up time requirements of latch L.sub.2, and thus the timing verifier reports a timing violation on L.sub.2. Known timing verifiers do not represent the relationship between Z.sub.1 and Z.sub.2, and therefore do not discern the additional four phases' delay between them.
Known timing verifiers have had facilities by which a user can, within the previous four-phase system, describe particular paths as being "false paths"--i.e., paths that, for reasons known to the user, will never occur in practice. Once the path from L.sub.1 to L.sub.2 has been identified as a false path, the timing verifier can modify its pruning method and analyze the next-most-critical path. However, this introduces a failure-prone manual step. Even with this feature, the timing verifier spuriously reports the path from L.sub.1 to L.sub.2 as a failure. The engineer must analyze the report, and then add this failure to a list of known spurious failures to ignore. He may subsequently modify the circuit in such a way that a previously-reported and now-ignored failure becomes important. But the timing verifier does not discover or communicate the new urgency of the failure.


A smart junction box for a photovoltaic solar power module, and related method of operation. The junction box includes a plurality of active bypass circuits for protecting the solar cells from reverse bias, a novel power supply circuit in several embodiments that can operate with input voltages of either positive or negative polarity, a capacitor for storing and supplying energy, and a master control circuit. The master control circuit is able to enable/disable the power supply, force the bypass switches to open, and modulate the on-resistance of the bypass switches. The master control circuit performs these functions in a coordinated way to maintain the voltage across the capacitor within predetermined limits, thereby ensuring the internal circuitry is powered under all operating conditions including: full sunlight, partial shading, full shading, and safe mode for reducing the risk of electrical shock to firefighters.

The present invention relates generally to the field of solar power, and more specifically to power supply circuits used in smart junction boxes (j-boxes) for photovoltaic (PV) solar power modules and related methods of operation.
FIG. 1 is a simplified schematic diagram of a conventional solar power module 10 including: a positive terminal 11 and a negative terminal 12 for connecting the module 10 to a solar array; a plurality of serially connected PV segments 13, each of the segments include a plurality of serially connected PV cells for converting sunlight into electricity; and a conventional j-box 14 that houses bypass diodes 15 (typically Schottky diodes) connected in parallel with each PV segment 13.
For purposes of the present application, there is no official definition of a "smart" j-box, but in the context of this document, a smart j-box is one that contains any kind of active circuitry, rather than just conventional Schottky bypass diodes 15.
FIG. 2 is a simplified schematic diagram of a solar power module 20 with a first type of smart j-box 21. This is the simplest form of a smart j-box 21, wherein the conventional bypass diodes 15 are replaced with active bypass circuits 16. Each active bypass circuit 16 includes: a bypass diode 22; an electronically controlled switch 23; and a control circuit 24 for controlling the switch 23.
When the PV segments 13 are partially shaded, their short-circuit output current (ISC) decreases. If ISC falls below the string current (ISTRING) the bypass diode 22 becomes forward biased. The anode voltage rises above the cathode voltage, causing the control circuit 24 to close the switch 23. When the shade is removed, the polarity of the anode-to-cathode voltage reverses, causing the control circuit 24 to open the switch 23 again.
The key advantage of active bypass is drastically reduced heat dissipation. For example, a typical Schottky bypass diode 15 will have a forward voltage drop of approximately 400 mV at 8 A current, producing 3.2 W of heat in the diode. In contrast, the switch 23 is typically a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with an on-resistance of about 5 mΩ. Such a MOSFET, conducting the same 8 A current, dissipates just 0.32 W of heat, or 90% less. Reducing the heat dissipation can greatly increase the reliability of the j-box 21, and may even reduce it's cost by eliminating the need for a heat sink.
In a smart j-box such as 21, each bypass diode 22 is typically the body-diode that is an integral part of the associated MOSFET switch 23, rather than being discrete components, like the conventional bypass diodes 15 of FIG. 1.
A smart j-box such as 21 requires a means for powering the control circuits 24. Some prior art examples (e.g., U.S. Pat. Nos. 8,618,864 B2 and 4,869,254 B2) provide this means by making each control circuit 24 a special kind of dc-to-dc converter. When the bypass diode 22 is forward biased, the control circuit 24 converts the relatively small anode-to-cathode voltage into a much larger output voltage that is applied to the gate of the MOSFET switch 23. Once the switch 23 is closed, the anode-to-cathode voltage drops to typically 50 mV. But the special power supply has so much voltage gain (typically at least 100) that it can continue producing enough voltage (typically at least 5V) to keep the associated MOSFET switch 23 fully enhance (completely turned on).
The special power supply circuit in 24 typically produces just a few microamps of output current. While this is perfectly adequate for the task of turning on the MOSFET switch 23, it's simply not enough to do much else.
Yet there is a strong desire in the PV industry for smart j-boxes that can do more than just active bypass. For example, a smart j-box could perform many other useful functions, such as: module-level shutdown (safe mode) for firefighter safety; module-level performance monitoring for improving system efficiency by identifying particular solar modules that are under-performing; arc-fault detection to reduce the risk of fires; and diagnostics (e.g., self-test and arc fault location) to reduce system down-time and maintenance costs.
But these functions require a lot more supply current, typically at least a few milliamps. Providing this much current is not a simple problem because there are at least two basic technical challenges that must be overcome. The first basic challenge is providing power continuously. In the example above, each control circuit 24 only provided power when it's diode 22 was forward biased, and was unpowered the rest of the time. But a smart j-box with all the functions listed above needs power all the time. One reason why providing power continuously is challenging is that the polarity of the voltage between the positive terminal 11 and negative terminal 12 can actually flip; normally the positive terminal 11 is at a higher potential than the negative terminal 12, but when all the bypass diodes are forward biased concurrently the negative terminal 12 is actually at a higher potential than positive terminal 11. Power supply circuits normally require the polarity of their input voltage to be fixed and predetermined.
The second basic challenge is the ultra-wide range of input voltage. When there is no shade on the PV segments 13, the solar module 20 can typically produce up to 36 Vdc between positive terminal 11 and negative terminal 12. But when all the switches 23 are closed concurrently the voltage typically drops below 200 mV. That's a huge ratio of 180:1, and a power supply that can operate over such a wide input voltage range is extremely unusual. The vast majority of power supply circuits operate over an input voltage range of less than 3:1. Furthermore, it is also extremely unusual for a power supply circuit to operate at the ulna-low input voltage of 200 mV.
FIG. 3 is a simplified schematic of a power supply 30 representing a conventional approach that would be obvious to anyone of ordinary skill in the art of power supply design. A battery 31 represents a voltage source that can have either polarity, because it is attached to the circuit via some connector contacts 32a and 32b, which makes it possible to install the battery backwards. Therefore, a polarity correction circuit 33 is included to ensure the input voltage to the dc-to-dc converter 34 is always correct. Typically, the polarity correction 33 is just a plain old bridge rectifier consisting of four diodes, as shown. But in a smart j-box that must operate in safe mode (wherein the input voltage is only about 200 mV), the two diode drops (approximately 1.2V) associated with a bridge rectifier 33 would be unacceptable. So each diode in the bridge would have to be replaced with a MOSFET switch, making a so-called "active bridge".
This active bridge approach has some obvious disadvantages. First, it requires at least five large MOSFETs (four in the polarity correction 33 and one for the switch inside the converter 34). These would take up a lot of area on an integrated circuit, making it relatively large, and therefore expensive. Second, the challenge of operating at very low input voltage (safe mode) is made more difficult because of the combined on-resistance of these MOSFETs. And third, there would have to be some relatively complex control circuits for opening and closing the four switches in the active bridge.
Therefore, there is a need in the PV solar power industry for a way of powering a smart j-box for PV solar power module that provides power continuously, in all situations including safe mode, and enough power to enable all the advanced functions of a smart PV j-box.

Smart junction box for photovoltaic solar power modules with novel power supply circuits and related method of operation


A hand-held line-casting and retrieval reel formed from a slab of material allows virtually drag-free unreeling and rapid retrieval of the line. The reel has a convenient, safe hook position for the reeled-in line.

In the casting of a line, usually with a weight on the end of the line, the energy to propel the weight for a distance is injected by the caster's arm propelling an end portion of the line with a circular rotation about the hand that grasps the line at the center of rotation. The line is then released and flies off in the direction intended. This is called hand casting.
As the line is propelled, it pulls a continuous source of line length until the weighted end reaches its destination and drops into the water. The supply of line for the aforementioned action might take the form of a coil of line lying on the ground or deck near the caster; it might be wrapped around a cylindrical object such as a coffee can or a soda bottle; or it might be wrapped around a rectangular object such as a board. The line can be retrieved by pulling it hand over hand, or by wrapping it around a board or cylinder.
There is on the market a manufactured plastic, round reel for hand casting and retrieving line. This is a ring about ten inches in diameter made of plastic which is about three inches wide. The ring is dished and rimmed along the outside diameter for holding line. It is rimmed on the inside of the ring to provide a handhold. The purpose of this product is to hold a line for fishing without a pole.
Native fishermen in many countries use handmade fishing boards with line wrapped around them. The line on these boards is wrapped lengthwise parallel to the grain of the wood. The user holds the board on one side. Sometimes an oval is cut into the board creating a handle for holding the board. The board is from three to eight inches wide (across the grain) and is from four to fourteen inches long. Its thickness ranges from one quarter inch to one inch. The length of the board on each end of the handle edge is often from one-half inch to one inch longer to help keep the line being wound from balling off the backside of the board onto the user's hand. A problem with this type of board is that heavy pulling loads, such as from a large fish, can split the board along its grain. Also, when wet, the grain of the board rises creating friction in the process of casting the line, thereby shortening the distance of the cast. Another problem with native boards is that the line can become wound around the use's fingers as line is inadvertently wrapped around the longer sections of the ends. Line that is inadvertently wrapped around the longer sections of the ends also can become dislodged during handling causing slack line that can fall off the reel in a knot.


There is provided a non-volatile memory circuit including: plural storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal during data reading; and wherein cathodes of respective zener zap devices of the plural storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading, wherein the output terminals of the plural storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage during data writing, and wherein the switch section is switched ON during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector.

Technical Field
The present invention relates to a non-volatile memory circuit (also referred to below as PROM) that employs zener zap devices (also referred to below as ZapFuses) and to a semiconductor device and reading method thereof. The present invention particularly relates to a non-volatile memory suitable for achieving increased capacities without causing a drop in reading speed, and to a semiconductor device of the same.
Related Art
As disclosed in for example Japanese Patent Application Laid-Open (JP-A) No. 2003-204069, in a zener zap device with a zap diode configured by forming a P-type well region to a surface layer of an N-type semiconductor layer, forming a P-type anode region and an N-type cathode region in the P-type well region, and with the P-type anode region and the N-type cathode region respectively connected through an anode electrode and a cathode electrode, the PN junction is broken down by applying a reverse bias voltage of a breakdown voltage or greater to the zap diode so as to short between the anode electrode and the cathode electrode and act as a resistor.
A PROM circuit employing zener zap devices as storage units for single bits operates in a data write mode that zaps the zener zap devices for each bit, and in a read mode that reads the written data. In the read mode, a method and a circuit configuration is employed in which a current is applied to each of the zener zap devices for every bit, and the data of each bit is read to be transmitted to an operation circuit.
For example JP-A No. 2005-182899, discloses a PROM circuit including: plural memory devices (zener zap devices) each having one end connected to a common write current input terminal and the other end connected to respective read terminals; plural ON/OFF state controllable switch elements (transistors) each having one end connected to the respective read terminal and the other end connected to a common reference voltage terminal; plural current sources respectively connected between the plural read terminals and the reference voltage terminal; and a diode having one end connected to the write current input terminal and the other end connected to a voltage source, with the diode connected in a direction so as to prevent a write current during writing from flowing to the voltage source. The PROM circuit is configured such that when selectively writing to the memory devices, the switch elements are selectively placed in an ON state, and changes in the resistance values of the memory devices are selectively induced by a current flowing from the write current input terminal and into a write current absorption terminal. When data written to the memory devices is read, all of the plural switch elements are placed in an OFF state, and a rise or fall in voltage with respect to the reference voltage terminal is induced in the plural read terminals (P2 to P3) due to differences in voltage fall occurring in the respective memory devices due to current flowing from the voltage source, through the diode and the plural memory devices, to the plural current sources.
According to the PROM circuit of JP-A No. 2005-182899, the previous need to provide an interference prevention diode to each of the PROM devices is eliminated, and a single switch suffices for devices over a large area. The surface area occupied in an IC can accordingly be reduced. Moreover, even should a large voltage occur at both ends of a PROM device during writing, the voltage applied to the switch elements for selective writing is low, and so there is no need to employ an element with a high withstand voltage. Moreover, the terminal potential of the selective writing switch elements increases due to the voltages arising at both ends of the PROM circuit, enabling difficulties in switch element control and inability to make sufficient write current flow to be resolved.
However, in the PROM circuit of JP-A No. 2005-182899, there is a need to form a thick A1 filament line in the zener zap devices to apply a constant zap current in the region of 150 mA to 200 mA such that the A1 filament line does not break when a read current flows during normal circuit operation.
As a result, there is the issue of an increase in cell size due to provision of the transistor for applying the zap current of 150 mA to 200 mA and the inflow prevention diode. In particular, the chip surface area of the product increases the higher the number of bits and the larger the surface area occupancy ratio of the PROM circuit.
JP-A No. 2007-265540 discloses a PROM circuit directed towards resolving such issues. The PROM circuit of JP-A No. 2007-265540 is configured including, for each single zener zap device: a diode that prevents inflow to another bit in a normal mode; a diode to protect a circuit on an output terminal side; a first transistor that selects the zener zap device and applies a zap current during writing; a second transistor that serves as a switch element controlling a read current; a resistor that causes a voltage fall during reading; and a latch circuit that holds data read through the zener zap device during read mode.
Such a configuration enables prolonged use even with a fine A1 filament zapped with a low current critical for zapping, enabling a reduction in cell size to be achieved. It is accordingly possible to provide a zener zap PROM circuit with reduced chip size.
For PROM circuits employing zener zap devices as storage units for single bits, various known technology is proposed, such as for example disclosed in JP-A No.
2003-204069, that enables economical electrical writing on a small-scale and features high reliability after writing, and also avoids an increase in surface area accompanying increasing capacities of PROM circuits.
However, in the technology of for example JP-A No. 2007-265540, the latch circuits and inflow prevention diodes etc. are provided for each storage unit, leading to an increase in layout surface area when the number of storage units is increased in order to achieve increased capacity.
Moreover, in each of the related technologies, a write power supply and a read power supply are each separately provided, and moreover the read power supply is configured for each of the storage units, leading to an increase in layout surface area when the number of storage units is increased in order to achieve increased capacity.
Moreover, in each of the related technologies, in PROM circuits configured to serially read the output of the storage units, namely PROM circuits configured to increase capacity with the cathodes of the zener zap devices (ZapFuse) commonly connected and only the zener zap devices and transistors for selecting the anode of the zener zap devices connected in parallel, no consideration is given to the voltage swing of the cathodes of the zener zap devices detected during data reading. In such PROM circuits configured to serially read the output of the storage units, when the number of storage units is increased to achieve increased capacity, an increase in read time occurs accompanying the increase in capacity of cathodes, with the issue of decreased read speed.
Accordingly, in the related technology, and in particular in PROM circuits configured to serially read the output of the storage units, an increase in surface area and an increase in read time is unavoidable when the number of storage units is increased to achieved increased capacity.

This patent is subject to a terminal disclaimer.

Non-volatile memory, semiconductor device and reading method