Apparatus and associated methods relate to a sensor holder adapted to float with a bobbing action when partially submerged in a liquid, while maintaining an air pocket within a first open holder end above the liquid, and removably retaining an electronic sensor in a liquid tight compartment disposed within a second holder end submerged in the liquid. In an illustrative example, the holder may be a substantially conical funnel. The open holder end may be, for example, open to the atmosphere, permitting wireless connection with the electronic sensor. In some examples, the holder may slidably retain a float rod adapted to allow the liquid to freely and vertically displace the holder as the liquid level varies. Various examples may advantageously provide automatic adjustment of the holder position to preserve a wireless connection with a retained electronic fishing sensor, maintaining the air pocket above the sensor as the liquid level varies.

A fish finder is a device that may be used to detect fish. Some fish finders may detect fish based on analysis of sound waves reflected by fish or other underwater objects. A fish finder using sound waves to detect fish may include a sound emitter and a sound sensor. Some fish finders may locate fish by detecting sound waves reflected by fish in the water beneath a fishing boat. For example, a fish finder may emit sound waves into the water beneath a fishing vessel, and analyze reflected sound waves detected by the sound sensor. Some fish finders are adapted to discriminate between fish and underwater structures based on computational analysis of sound waves reflected by underwater objects.
Some fish finders display fish or underwater structures via a user interface. In some examples, wires may connect the user interface to a fish finder. Some fish finders include wireless interfaces. Some mobile computing devices, such as smartphones and tablets, may be adapted to provide a wireless fish finder user interface. For example, some fish finder sensors may include a wireless interface configured to allow a mobile computing device to communicate with and control the wireless fish finder. For example, in some scenarios, a mobile application configured on a mobile computing device may allow a user to view fish or underwater structure, on the mobile device display wirelessly coupled with the fish finder.
A fish finder may not effectively detect fish or underwater structure if the fish finder's sound emitter or sound sensor is not submerged under water. Sound waves reflected back from the fish or underwater structure to a fish finder's sound sensor may efficiently propagate through the water without noticeable degradation of the reflected sonic signal. In some scenarios, a wireless fish finder submerged in water may lose the wireless connection to a wirelessly coupled mobile computing device. For example, the wireless signal from a fish finder submerged in water may be degraded due to attenuation of the wireless signal by the water.
In some scenarios, a user operating a wireless fish finder may be required to frequently adjust the wireless fish finder mount to maintain a wireless data connection between the wireless fish finder and a mobile device. For example, a user may need to adjust the fish finder mount so that the sonic emitter and sensor are under water while the wireless interface is above water. In some scenarios, such as using a fish finder from a kayak or canoe while trolling, the water level may continuously change, resulting in frequently lost fish finder signals and higher fish finder mount adjustment workload for the user.


A circuit substrate includes a plurality of dielectric members and a plurality of wiring patterns. The plurality of wiring patterns are stacked on one another through the plurality of dielectric members. The plurality of dielectric members includes a mount dielectric member. A first wiring pattern of the plurality of wiring patterns is provided on a side of the mount dielectric member. A second wiring pattern of the plurality of wiring patterns is provided on an opposite side of the mount dielectric member. A first length is a length between a reinforcing medium of the mount dielectric member and the opposite side of the mount dielectric member in a thickness direction. A second length is a length between the reinforcing medium of the mount dielectric member and the side of the mount dielectric member in the thickness direction. The first length is smaller than the second length.

1. Field of the Invention
The present invention relates to a circuit substrate, which includes a plurality of wiring patterns, and a manufacturing method of the circuit substrate. Here, each of the plurality of wiring patterns is stacked on another through a dielectric member and is electrically connected with one another.
2. Description of Related Art
Conventionally, Japanese Unexamined Patent Publication No. 2001-36253 discloses a circuit substrate, in which an influence of a generated stress is limited. Here the stress is generated due to a difference of coefficients of thermal expansion between the circuit substrate and an electric device mounted to the circuit substrate. FIG. 5 is a sectional view of a schematic structure of the circuit substrate disclosed in Japanese Unexamined Patent Publication No. 2001-36253.
The circuit substrate disclosed in Japanese Unexamined Patent Publication No. 2001-36253 includes a body substrate 100 and a film substrate 200. The body substrate 100 includes dielectric layers 110 made of a dielectric resin and body wiring patterns 120. The dielectric layers 110 and the body wiring patterns 120 are stacked on one anther. The film substrate 200 is joined to one side of the body substrate 100, and includes a film 220, a mount wiring pattern 240, via holes 230, and a low elastic resin layer 210. The film 220 is made of a resin, such as polyimide. The mount wiring pattern 240 is formed on one side of the film 220 and an electric device is mounted on the mount wiring pattern 240. The via holes 230 electrically connect the body wiring pattern 120 and the mount wiring pattern 240. The low elastic resin layer 210 is formed between the body substrate 100 and the mount wiring pattern 240, and is made of a low elastic resin, which is less elastic than a dielectric layer 110 of the body substrate 100. Here, the low elastic resin includes a dispersed nitrile-butadiene rubber (NBR) thermoset modified epoxy resin sheet.
In the circuit substrate disclosed in Japanese Unexamined Patent Publication No. 2001-36253, the low elastic resin layer 210 (i.e., resin layer having a small modulus of elasticity) easily deforms according to the stress caused by the thermal expansion of the mounted electric device and of the circuit substrate. Thus, the stress generated due to the difference of the coefficients of the thermal expansion between the electric device and the circuit substrate can be absorbed or mitigated.
However, in the circuit substrate disclosed in Japanese Unexamined Patent Publication No. 2001-36253, a resin sheet is formed (provided) between the mount wiring pattern 240 and the body wiring pattern 120. Thus, when a crack is formed on a surface of the circuit substrate due to thermal stress and the like, the mount wiring pattern 240 may be electrically connected with the body wiring pattern 120. As a result, a dielectric property of the film substrate 200 may deteriorate, and breaking of the body wiring pattern 120 may occur.
Also, the circuit substrate disclosed in Japanese Unexamined Patent Publication No. 2001-36253 can be manufactured only through a build up method. As a result, even when a circuit substrate does not require minute patterning, a manufacturing process thereof tends to be complex.

Circuit substrate and manufacturing method thereof


In an analog MOS semiconductor device, each of a plurality of MOS transistors includes a plurality of micro-unit transistors. In this way, even if a process error occurs in a transistor, a systematic offset voltage and a random offset voltage are suppressed to low levels. The micro-unit transistor has a channel width that is obtained by dividing, by an integer, a smallest channel width among those of the plurality of MOS transistors. Each micro-unit transistor includes two small transistors connected in parallel to each other, including a shared drain located in a central position, gates located on opposite sides of the drain, and sources located respectively on the outer side of the gates, i.e., at opposite ends of the micro-unit transistor.

The present invention relates to an analog MOS semiconductor device, such as an operational amplifier, a comparator, an analog switch, a sense amplifier for a memory, a low noise amplifier, or a mixer, including a MOS transistor, a capacitor, a resistor, an inductor, a diode, etc., and also relates to a method for manufacturing the same.
In recent years, along with the development in the system on chip technology, more and more LSIs including analog circuits and digital circuits integrated together have been developed each year. Accordingly, there is a demand for a significant reduction in the development time and the number of development steps and for improving the performance. There is also a demand for an automated layout process for an analog MOS semiconductor circuit.
A conventional analog MOS semiconductor device will now be described. FIG. 23 illustrates a circuit configuration of an operational amplifier as an analog MOS semiconductor device. The operational amplifier illustrated in the figure includes a P-channel transistor MP1 (21), a P-channel transistor MP2 (22), a P-channel transistor MP5 (25), a P-channel transistor MP6 (26), an N-channel transistor MN3 (23), an N-channel transistor MN4 (24), an N-channel transistor MN7 (27), a capacitor Cc (28), and a resistor Rc (29). The operational amplifier also includes a positive side input terminal V+ (30), a negative side input terminal Vxe2x88x92 (31), an output terminal Vo (32), a bias voltage input terminal VBIAS (33), a positive side power supply VDD (34), and a negative side power supply VSS (35).
Table 1 below shows the channel width W and the channel length L of each of the MOS transistors MP1 to MN7, the resistance value of the resistor Rc, and the capacitance value of the capacitor Cc of the operational amplifier of FIG. 23, as an example of the results of a design process.
FIG. 24 illustrates a conventional layout of the operational amplifier of FIG. 23. The size of each of the seven transistors MP1 (21) to MN7 (27) in FIG. 24 represents a layout area occupied by the transistor according to the channel width W and the channel length L thereof. This similarly applies to the capacitor Cc and the resistor Rc.
A condition for realizing systematic offset voltage SVoff=0 in a circuit design of an operational amplifier is shown by Expression (4.182) on page 210 in xe2x80x9cAnalog MOS Integrated Circuit For Signal Processingxe2x80x9d, R. Gregorian, G. C. Temes, John Wiley and Sons. Applying this expression to the operational amplifier of FIG. 23, the following expression needs to hold:
(W/L)MN3/(W/L)MN7
=(W/L)MN4/(W/L)MN7
=(W/L)MP5/(W/L)MP6/2xe2x80x83xe2x80x83(1)
The channel width W and the channel length L of the transistors are determined so as to satisfy Conditional Expression (1) above.
Furthermore, a condition for realizing random offset voltage RVoff=0 in a circuit design of an operational amplifier is shown by Expression (4.185) on page 211 in the same article. Applying the expression to the operational amplifier of FIG. 23, the following expression needs to hold:
(W/L)MP1=(W/L)MP2xe2x80x83xe2x80x83(2)
In the operational amplifier configuration, the P-channel transistor MP1 (21) and the P-channel transistor MP2 (22) are a pair of transistors that together form a differential input circuit.
Similarly, another condition for realizing random offset voltage RVoff=0 is shown by Expression (4.183) on page 211 in the same article. Applying the expression to the operational amplifier of FIG. 23, while taking into consideration the preconditions for the expression set forth in this article, the following expression needs to hold:
(W/L)MN3=(W/L)MN4xe2x80x83xe2x80x83(3)
In the operational amplifier configuration, the N-channel transistor MN3 (23) and the N-channel transistor MN4 (24) are a pair of transistors that together form a current mirror. The value of the capacitor Cc and the value of the resistor Rc are determined so that the phase margin of the operational amplifier is satisfied as described in the article.
However, even if the channel width W and the channel length L of the seven transistors MP1 (21) to MN7 (27) are designed so as to satisfy Conditional Expression (1) for realizing systematic offset voltage SVoff=0 as described above, the value of the channel width W of each transistor may be slightly shifted from the design value due to various process errors occurring in a semiconductor manufacturing process. As a result, seven transistors that are actually obtained as described above do not satisfy Conditional Expression (1) for realizing systematic offset voltage SVoff=0, whereby a systematic offset voltage SVoff occurs. A systematic uniform shift will now be described. This shift is shown in FIG. 25 with the P-channel transistor MP5 (25) as an example.
FIG. 25 shows, on the left side, an example of a layout of the P-channel transistor MP5 (25) using the design values described above. The transistor includes a gate 7 in the central position, and a source 6 and a drain 8 arranged on the opposite sides of the gate 7. The source 6 and the drain 8 are connected to aluminum wires 9 and 9 via contacts 10. Moreover, a P-type impurity diffusion region 11 is provided for forming a channel of a P-channel transistor, and the channel width W of the P-channel transistor MP5 (25) that is drawn on the left side of the figure is designed to be equal to the width of the P-type impurity diffusion region 11.
As an example, it is assumed that a uniform process error of xcex94W occurs in the decreasing direction in the semiconductor manufacturing process. FIG. 25 shows, on the right side, the manufactured P-channel transistor MP5 (25). The width of the P-type impurity diffusion region 11 of the P-channel transistor MP5 (25) that is drawn on the right side of the figure is reduced by xcex94W at each end, and thus the width is reduced by 2xcex94W in total. Therefore, the actual channel width W of the manufactured P-channel transistor MP5 (25) is expressed as follows:
(Wxe2x88x922xcex94W)MP5xe2x80x83xe2x80x83(4)
Similarly, the process error in the semiconductor manufacturing process occurs uniformly for other transistors of the operational amplifier illustrated in FIG. 23. Therefore, the actual channel widths W of the manufactured transistors are expressed as follows:
(Wxe2x88x922xcex94W)MN3xe2x80x83xe2x80x83(5)
(Wxe2x88x922xcex94W)MN4xe2x80x83xe2x80x83(6)
(Wxe2x88x922xcex94W)MP6xe2x80x83xe2x80x83(7)
(Wxe2x88x922xcex94W)MN7xe2x80x83xe2x80x83(8)
Therefore, substituting Expressions (3) to (8) into Expression (1) gives the following expression:
{(Wxe2x88x922xcex94W)/L}MN3/{(Wxe2x88x922xcex94W)/L}MN7
={(Wxe2x88x922xcex94W)/L}MN4/{(Wxe2x88x922xcex94W)/L}MN7
xe2x89xa0{(Wxe2x88x922xcex94W)/L}MP5/{(Wxe2x88x922xcex94W)/L}MP6/2xe2x80x83xe2x80x83(9)
Thus, the conditional expression for realizing systematic offset voltage SVoff=0 no longer holds. Therefore, the systematic offset voltage SVoff occurs due to various systematic process errors in the semiconductor manufacturing process.
On the other hand, the article, page 211, line 15 from the bottom to line 12 from the bottom, states that in the circuit configuration of an analog MOS semiconductor device, Conditional Expression (1) for realizing systematic offset voltage SVoff=0 can be satisfied as follows: xe2x80x9cIf ratios as large as (or larger than) two are required, then the wider transistor can be realized by the parallel connection of two (or more) xe2x80x9cunit transistorsxe2x80x9d of the size of the narrower onexe2x80x9d. Specifically, with a transistor (first transistor) having the minimum channel width W being a unit transistor, when a second transistor having a channel width kW (k is an integer) that is an integer multiple of the minimum channel width W is provided by the parallel connection of an integral number of unit transistors, even if a systematic process error occurs in each unit transistor, what occurs in the second transistor is an error that is an integer multiple of the process error, whereby the channel width of the second transistor remains to be an integer multiple of that of the first transistor, thus preventing the systematic offset voltage SVoff from occurring.
However, with a transistor of the minimum channel width W being used as a unit in an actual circuit design, it is only possible under the very rare condition xe2x80x9cIf ratios as large as (or larger than) two are requiredxe2x80x9d as stated in the article to provide each of the other transistors with a channel width W that is an integer multiple of the minimum channel width W.
Next, the influence of a random shift, rather than the systematic uniform shift as described above, will be described with reference to FIG. 26A and FIG. 26B using the pair of N-channel transistors MN3 (23) and MN4 (24) as an example.
FIG. 26A illustrates an example of a layout of the N-channel transistors MN3 (23) and MN4 (24) manufactured according to the design values shown in Table 1 above. Referring to FIG. 26A, an N-type impurity diffusion region 12 for forming a channel of an N-channel transistor is provided, and the channel width W of the transistors MN3 (23) and MN4 (24) is designed to be equal to the width of the N-type impurity diffusion region 12.
FIG. 26B illustrates an example of a layout of the pair of N-channel transistors MN3 (23) and MN4 (24) after the semiconductor manufacturing process, where a process error has occurred randomly in the semiconductor manufacturing process, thereby increasing only the channel width W of the transistor MN3 (23), among the pair of transistors, by xcex94W. Assuming that the width of the N-type impurity diffusion region 12 of the N-channel transistor MN3 (23) has increased by xcex94W at one end whereas the width of the N-type impurity diffusion region 12 of the N-channel transistor MN4 (24) has not increased or decreased, the actual channel widths W of the two manufactured N-channel transistors MN3 (23) and MN4 (24) are expressed as follows:
(W+xcex94W)MN3xe2x80x83xe2x80x83(10)
(W)MN4xe2x80x83xe2x80x83(11)
Therefore, substituting Expressions (10) and (11) into Conditional Expression (3) for realizing random offset voltage RVoff=0 gives the following expression:
{(W+xcex94W)/L}MN3xe2x89xa0(W/L)MN4xe2x80x83xe2x80x83(12)
Thus, the equation no longer holds, indicating that the random offset voltage RVoff occurs due to various random process errors in the semiconductor manufacturing process.
An object of the present invention is to provide an analog MOS semiconductor device in which even if a process error occurs in a semiconductor manufacturing process, the systematic offset voltage SVoff and the random offset voltage RVoff can be sufficiently suppressed.
In order to achieve the object, according to the present invention, the unit transistor is not a transistor having the smallest channel width, among a plurality of MOS transistors included in an analog MOS semiconductor device. Instead, a transistor having a channel width that is obtained by dividing the smallest channel width by an integer is used as a micro-unit transistor so that each of the plurality of MOS transistors includes a number of micro-unit transistors.
Specifically, an analog MOS semiconductor device of the present invention is an analog MOS semiconductor device, including a plurality of MOS transistors, wherein: a transistor having a channel width that is obtained by dividing, by an integer, a smallest channel width among those of the plurality of MOS transistors is used as a micro-unit transistor; and each of the plurality of MOS transistors includes a plurality of micro-unit transistors.
In one embodiment, the plurality of MOS transistors include two types of MOS transistors of P-type MOS transistors and N-type MOS transistors; and the micro-unit transistors include two types of micro-unit transistors of P-type micro-unit transistors and N-type micro-unit transistors.
In one embodiment, each of MOS transistors that are included in a conditional expression for realizing zero systematic offset voltage includes a number of micro-unit transistors that satisfies the conditional expression for realizing zero systematic offset voltage.
In one embodiment, the micro-unit transistors of each MOS transistor overlap with one another.
In one embodiment, each micro-unit transistor includes an even number of small transistors; the even number of small transistors are connected in parallel to one another; and two of the even number of small transistors connected in parallel to one another that are located at opposite ends each have a source located at one end of the micro-unit transistor.
In one embodiment, the micro-unit transistor is a pair transistor including two small transistors connected in parallel to each other; and a source of one of the small transistors is located at one end of the pair transistor, and a source of the other one of the small transistors is located at the other end of the pair transistor.
In one embodiment, the micro-unit transistor includes a substrate contact via which one or more of electrodes of the micro-unit transistor is connected to a semiconductor substrate.
In one embodiment, the micro-unit transistor includes a gate contact connected to a gate of the micro-unit transistor, and a gate wire connected to the gate contact for applying a gate voltage to the gate.
In one embodiment, dummy micro-unit transistors are provided for adjusting a power of one or more of the plurality of MOS transistors.
In one embodiment, the dummy micro-unit transistors include two types of dummy micro-unit transistors of P-type dummy micro-unit transistors and N-type dummy micro-unit transistors.
In one embodiment, two MOS transistors forming a pair, among the plurality of MOS transistors, each include a number of micro-unit transistors that is a multiple of four.
In one embodiment, the plurality of MOS transistors have an SOI structure or an SOS structure.
A method for manufacturing an analog MOS semiconductor device of the present invention is a method for manufacturing an analog MOS semiconductor device including a plurality of MOS transistors, including the steps of: preparing a plurality of micro-unit transistors each having a channel width that is obtained by dividing, by an integer, a smallest channel width among those of the plurality of MOS transistors; and manufacturing the plurality of MOS transistors using the plurality of micro-unit transistors so that each of the plurality of MOS transistors includes more than one of the micro-unit transistors.
In one embodiment, if the plurality of MOS transistors include two types of MOS transistors of P-type MOS transistors and N-type MOS transistors, two types of micro-unit transistors of P-type micro-unit transistors and N-type micro-unit transistors are prepared as the micro-unit transistors, so that each P-type MOS transistor includes more than one of the P-type micro-unit transistors and each N-type MOS transistor includes more than one of the N-type micro-unit transistors.
In one embodiment, when manufacturing MOS transistors that are included in a conditional expression for realizing zero systematic offset voltage, the number of micro-unit transistors to be included in each of the MOS transistors is set to be a number that satisfies the conditional expression for realizing zero systematic offset voltage.
A program for manufacturing an analog MOS semiconductor device of the present invention is a program for manufacturing an analog MOS semiconductor device including a plurality of MOS transistors, the program including the steps of: defining, as a micro-unit transistor, a transistor having a channel width that is obtained by dividing, by an integer, a smallest channel width among those of the plurality of MOS transistors; and designing the plurality of MOS transistors so that each of the plurality of MOS transistors includes a plurality of micro-unit transistors.
A program device of the present invention is a program device, including the manufacturing program as described above, wherein the program device has an EDA function or a CAD function for manufacturing an analog MOS semiconductor device including a plurality of MOS transistors based on the manufacturing program.
As described above, according to the present invention, a micro-unit transistor is used as a unit, and each MOS transistor includes a plurality of micro-unit transistors. Therefore, even if the channel width ratio among a plurality of MOS transistors is not an integer ratio, it is possible to sufficiently suppress the occurrence of the systematic offset voltage SVoff when a systematic process error occurs.
Particularly, according to the present invention, a plurality of micro-unit transistors are arranged in a layout in which they overlap with one another. Therefore, it is possible to reduce the layout area of each MOS transistor while satisfying the condition for realizing systematic offset voltage SVoff=0.
Moreover, according to the present invention, each micro-unit transistor includes an even number of small transistors connected in parallel to one other, wherein sources of two small transistors that are located at opposite ends are located at opposite ends of the micro-unit transistor. Therefore, when a substrate contact is provided around the micro-unit transistor so as to be connected to the sources, the sources of the small transistors and the substrate contact are located close to each other, thereby shortening the distance therebetween and thus reducing the layout area. Furthermore, since the even number of small transistors can share a drain, the drain area is reduced and thus the capacitance component that is parasitic on the drain is reduced, thereby increasing the operation speed of the micro-unit transistor.
Furthermore, according to the present invention, when each MOS transistor includes a plurality of micro-unit transistors, the plurality of micro-unit transistors each have a substrate contact, whereby the potential of the substrate of the MOS transistor is stably maintained at the same value irrespective of the position in the substrate, thus reducing the possibility for a latch-up phenomenon to occur.
In addition, according to the present invention, where a MOS transistor having a large channel width includes a number of micro-unit transistors, a gate voltage is individually applied to the gate of each of the number of micro-unit transistors via a corresponding gate wire. Therefore, a predetermined gate voltage is applied to the MOS transistor as a whole, whereby it is possible to obtain a driving power that is substantially equal to the design value.
Furthermore, according to the present invention, dummy micro-unit transistors are provided for adjusting the power of the MOS transistor. Therefore, a fine adjustment of the channel width of the MOS transistor can be made by connecting one or more of the dummy micro-unit transistors by modifying the wiring structure. Thus, it is possible to reduce the development time for an analog MOS semiconductor device by reducing the amount of time required for making prototypes.
Moreover, according to the present invention, each of two MOS transistors forming a pair includes a number of micro-unit transistors that is a multiple of four, whereby it is possible to arrange the pair of MOS transistors in a centroid structure. Therefore, it is possible to more effectively suppress the systematic offset voltage.
Furthermore, according to the present invention, a plurality of MOS transistors have an SOI structure or an SOS structure, whereby it is possible to realize an operation under an extremely low voltage and to reduce the influence of shot noise due to radioactive rays such as xcex1 rays. Furthermore, in an analog/digital mixed semiconductor device, it is possible to effectively reduce the influence of noise creeping into the analog section from the digital section.
In addition, according to the present invention, a circuit design process for a plurality of MOS transistors each including a plurality of micro-unit transistors can be automated, thereby effectively reducing the design/development time for an analog MOS semiconductor device and effectively reducing the development cost therefor.

Analog MOS semiconductor device, manufacturing method therefor, manufacturing program therefor, and program device therefor

Matsushita Electric Industrial Co., Ltd.


A nursing pad for placement inside a cup-like portion of a bra-like garment includes a conical structure of an absorbent material, such as layers of a fabric material or of a paper-like material. The conical structure has an apex, an outer boundary, and a V-shaped portion extending from the apex to the outer boundary, with the absorbent material being overlapped in the V-shaped portion. Preferably threaded stitching, such as zigzag stitching or surger stitching, secures the absorbent material overlapped in the V-shaped portion and around the outer boundary.

The present invention relates generally to a nursing pad which may be used by a woman during the lactation period of nursing a baby to absorb milk excretion from the woman's nipples, and more particularly to an improved nursing pad.
A variety of nursing pads comprising various layers of absorbable materials have been made and used by others. For example, the inventor is aware of four types of fabric nursing pads which may be washed between successive uses.
The first of the washable pads is made by the Natural Baby Company and is a flat, circular pad having seven layers of 100% cotton flannel fabric sewn around the periphery with a surger. A second washable pad has circular periphery and is formed by five layers of a 100% cotton stretch knit fabric with a surger hem about the periphery. A third known washable pad is sold under the registered trademark THE FIRST YEARS and includes three fabric layers having a circular periphery with surger stitching around the periphery. The fabric layers of THE FIRST YEARS pad include a first outer layer of 100% cotton, a second outer layer of 100% polyester, and a lining layer of 100% olefin between the outer layers. A fourth known washable pad is homemade and generally rectangular in shape. This homemade pad has six layers of 100% diaper flannel, with a zigzag stitching around the periphery of the pad.
The inventor is aware of five types of disposable nursing pads.
The first disposable pad is sold by the American Breast Pads Company, and is commonly available at J.C. Penney stores. This pad is circular and includes 18 layers of a very thin crepe paper sandwiched between two opposing outer layers of a nonwoven moisture-pervious paper. The layers are secured together by two parallel rows of chain stitching, with each row located along a chord of the circle defining the pad periphery. The parallel rows of chain stitching are equidistantly spaced from the center and located near the outer edges of the pad. This pad has a thumbprint-sized depression in the center of one side of the pad. The second known disposable nursing pad is sold under the registered trademark CURITY. The CURITY pad is circular and includes a soft absorbent top sheet, an outer plastic sheet, and inner layers of a cotton-like fluff material having a plurality of radially-directed channels extending from a central region of the pad toward the outer periphery. During wearing a woman, the outer plastic layer of the CURITY pad disadvantageously tends to rustle and crinkle making embarrassing sounds when the woman moves or stretches her arms. Furthermore, the plastic outer layer inhibits the evaporation of absorbed moisture from the pad. As the moisture trapped in the inner fluff layer cools to room temperature, the pads are cold, damp and uncomfortable to wear.
A third disposable nursing pad is sold under the JOHNSON'S trademark and is of a combination circular and rectangular shape. That is, two opposing sides are straight, parallel chords truncating a circular shape, and the remaining two opposing sides are arcuate, having a common radius centered at the center of the pad. The JOHNSON'S pad has a plurality of absorbent layers and what is believed to be a moisture-impervious outer layer. This outer layer includes an adhesive strip to hold the pad securely in place against the inside of a woman's bra. Once again, the moisture-impervious outer layer may disadvantageously rustle and crinkle during wear, causing embarrassing sounds. Furthermore, the adhesive strip may leave adhesive residue on the bra.
A fourth disposable nursing pad is made by the Gerber Products Company. The GERBER pad includes a special embossed design comprising six T-shaped radial spokes extending outwardly from a central region of the pad, with the top portion of the T-shape being at the periphery of the pad. The GERBER pad is circular in shape and includes a moisture-proof barrier shield outer layer.
The fifth known nursing pad is supplied by the Evenflo Products Company and is circular in shape. The EVENFLO pad includes a one-way moisture shield inner layer to be worn against the skin and which lets wetness enter the pad but not flow back to the skin. The pad also includes a breathable moisture barrier outer layer which protects clothing while letting air flow back through the pad to the skin. In between these two outer layers are multiple layers of a high-absorbency type of crepe paper that draws moisture away from the skin. Similar to the pad sold by the American Breast Pads Company, discussed above, the EVENFLO pad has a central thumbprint-sized depression on the inner layer side, and layers secured together by two rows of parallel stitching.
While some disadvantages have been discussed above, all of these known flat pads suffer several additional disadvantages. To state the obvious, a woman's breast is not flat, but generally of a conical nature, and these known flat pads must wrinkle to form a conical shape when worn. These wrinkles are often clearly and embarrassingly evident under a woman's blouse or dress, particularly if the garment is made of a stretch knit material or closely-fitting design.
Furthermore, in between nursings, a woman's breasts actually change shape and texture. After nursing, the breasts are empty and rather soft, then as milk is replenished, they become larger and firmer. So in addition to a woman's movement during an active day, the actual changes in the shape and texture of the breast itself tends to cause these known flat nursing pads to slip and move. The flat pads have a tendency to move into alignment against a flat surface, such as the side of a woman's breast, which may allow milk to embarrassingly leak through the woman's undergarment and outer clothing. In the worst case, the pads can work themselves completely out of the bra, and if the blouse is not tucked in, the pads may actually fall out of the blouse, creating an extremely embarrassing situation for the woman.
Thus, nursing mothers are faced with a variety of embarrassing and aggravating situations when using the currently-available flat nursing pads. A pregnant woman near the latter stages of pregnancy may also use nursing pads to absorb excretions from the nipples. Either woman may be particularly self-conscious concerning the personal nature of these bodily functions and anything tending to unnecessarily draw attention to these functions, such as the rustling, noisy pads or the wrinkles under clothing, can be particularly annoying.
Therefore, a need exists for an improved nursing pad which is not susceptible to the above limitations and disadvantages.


A computer-implemented system and method for detecting, by a mail server module, spam bot activity by a client device. An email session is conducted between the mail server module and the client device according to a predetermined protocol that includes exchange of messages between the mail server module and the client device. The mail server module probes compliance with the predetermined protocol including: purposefully introducing at least one irregularity into a first message from the mail server module; monitoring a subsequent message transmission from the client device; comparing the subsequent message against reference criteria; and producing a reputability determination for the client device based on an extent to which the subsequent message was a proper response to the at least one irregularity according to the predetermined protocol, the reputability determination being indicative of a likelihood that the client device conducts spam bot activity.

Every day throughout the world millions of electronic messages (e-mail) are sent over networks such as the Internet, however most of them are unsolicited and unwanted, so-called "spam." Electronic spam has been defined as messages containing commercial, political, and other forms of advertising, as well as malicious programs and links to phishing or other disreputable sites. The most unpleasant part of spam that it is routinely sent over the Internet to individuals who have not expressed a desire to receive such messages. Additionally, since each typical Internet user receives dozens or even hundreds of spam messages in a given day, statistics indicate that spam accounts for up to 90% of all sent messages. It is clear that the problem of fighting spam is extremely important.
One way to combat spam is to use various filters that allow finding a spam message by one or more keywords or by entering the sender's address in a blacklist. More advanced techniques, such as the use of histograms or categories, also allow users to raise the level of spam detection to values, sometimes approaching 100%. These techniques are currently implemented in commercial products such as Anti Spam Filter, Antispam Post, GFI MailEssentials, Kaspersky Internet Security or Kaspersky Anti-Spam—designed for both individual users and the corporate sector.
These solutions fight spam after it has been sent to a user's e-mail server, and do not solve the main problem itself, that is, the mass e-mailing of spam. These solutions also run the risk of indicating false positives, which means that legitimate email (e.g., from friends or colleagues) can appear as spam if they happen to trigger the filtering mechanisms.
Most spamming is currently performed by individual programs—known as spam bots—which are often covertly installed on users' computers to perform routine operations, such as sending spam. Spam e-mails are transmitted from various servers, which spammers rent for a short time, are not spam's main source, but rather serve for promotional purposes. Thus, one option for fighting spam is to detect spam bots on users' computers. The volume of spam for a home user with a channel bandwidth of 10-20 Mbps can reach up to 50-100 gigabytes of spam a day. Because of the large number of spam bots the aggregate amount of traffic can cause serious strain on email servers. There is therefore a pressing need for effective removal of spam bots from users' computers.

Systems and methods of probing data transmissions for detecting spam bots


Provided are a composition for an oxide semiconductor, a method of preparing the composition, methods of forming an oxide semiconductor thin film and an electronic device using the composition. The composition for an oxide semiconductor includes a tin compound, a zinc compound, and a low electronegativity metal compound containing a metal with an electronegativity lower than zinc.

The exemplary embodiments of the inventive concept relate to a composition for an oxide thin film, a method of preparing the composition, a method of forming the oxide thin film, and an electronic device including the oxide thin film.
Recently, researches have been widely conducted on oxide semiconductors which will replace typical silicon-based semiconductor devices. In terms of materials, results of the researches have been reported on single, binary, and tertiary compounds based on indium oxide (In2O3), zinc oxide (ZnO), and gallium oxide (Ga2O3) as the oxide semiconductors. Meanwhile, in process aspects of the oxide semiconductors, researches are conducted on a solution based process replacing typical vacuum deposition.
Indium oxide (In2O3) has been rapidly developed and used as a core material for transparent conductive oxides among the oxide semiconductors together with the advancement of a display field. However, researches on materials are required to replace indium oxide (In2O3) due to the imbalance of supply and demand, small reserves, high raw material cost, etc.

Composition for oxide thin film, method of preparing the composition, method of forming the oxide thin film, and electronic device using the composition

Industry-Academic Cooperation Foundation, Yonsei University


A process for affixing reclosable pouring fitments having pouring apertures to erected cartons. In a first embodiment, adhesive is initially applied to the rear of the fitment in two parallel strips on opposite edges of the fitment. Then, the fitment is rotated 90 degrees and two more parallel strips are applied to the other two edges of the fitment. The orientation of the second set of strips is generally perpendicular to that of the first set and is such that the strips form a rectangle which surrounds the pouring aperture of the fitment. The fitment is then applied to the carton over the dispensing aperture of the carton. The generally rectangular pattern of adhesive surrounding the carton's dispensing aperture effects a continuous seal between the fitment and the carton and minimizes leakage of the product out of the carton when fitment is closed.

Powdered laundry detergents are usually sold in paperboard cartons. Unfortunately, difficulties have sometimes been encountered by consumers in neatly pouring product from cartons. Access to the product in cartons has often been provided by means of die-cut perforations in the paperboard, along which the consumer is expected to make an opening in the carton. Frequently, however, consumers find it difficult to rupture the perforations so as to make an adequate opening in the carton. An additional drawback to perforated die-cut openings is that once an opening has been made it is often difficult to control the product during pouring due to the irregular shape of the pouring aperture created by the consumer. Furthermore, openings formed in the paperboard are usually not reclosable. As a result, a tendency exists for the product to spill from the carton if tipped, especially during transport. Moreover, products which are sensitive to moisture pick-up tend to cake because of the exposed opening.
Attempts to solve the aforementioned problems have included the use of plastic fitments. Gunn U.S. Pat. No. 4,732,315 discloses a plastic closure device having an aperture configured in a pentagonal, "home plate" shape having rounded corners. However, according to Gunn, when a thin, plastic fitment is affixed to the carton in its flat, tubular form problems may arise during stacking of the tubes due to an imbalance in the otherwise flat cartons caused by the extra thickness of the fitment. Gunn discloses that the problem can be overcome by balancing the fitment with means integral with the carton. The means may, for example, comprise score lines which are thickened to offset the extra thickness of the fitment.

Fitment application process and apparatus


A device and method for automatically detecting and optimally compensating die leakage current under a wide range of leakage conditions. A variable or reconfigurable (self-adaptive) keeper tracks current leakage online (in real time). The control input to the keeper is coupled to a leakage current sensor, which is in turn coupled to a dummy cell that generates the exact leakage current as the load. The current sensor regulates the control input in real time to produce a leakage compensation enable signal, which reconfigures and/or varies the strength of the keeper. Having the compensation capability of a strong keeper during elevated conditions and the capability of a weaker keeper during normal operational conditions, the self-adaptive keeper system offers high read/write performance, flexibility and circuit robustness in real time.

1. Technical Field
The present invention generally relates to integrated circuits and in particular to leakage current in integrated circuits. Still more particularly, the present invention relates to compensation of leakage current in integrated circuits.
2. Description of the Related Art
Continued development in integrated circuit (IC) technology is driven by a desire for the ever decreasing size of circuit components on the IC die. As the technology scales down to deep sub-micron levels, the inter-die leakage variation increases dramatically. Large variations in device threshold voltage exist among dies, which lead to a wide range of die-to-die leakage spread across process corners.
The traditional design for worst-corner process variation using a fixed-strength keeper often over-compensates the leakage in the majority of dies of the low leakage corner in order to satisfy a small number of dies of the high leakage corner. Unfortunately, the high leakage dies still do not satisfy the robustness requirements with a keeper sized for the faster corner leakage. This over-compensation degrades the overall performance of the chip. The inability to satisfy performance requirements reveals the drawbacks of a conventional keeper used under a wide range of inter or intra-die variations.

Automatic self-adaptive keeper system with current sensor for real-time/online compensation for leakage current variations

International Business Machines Corporation


A system for radar object simulation is provided. The system comprises a filter unit with a plurality of filter paths, a processing unit and a communication interface. In this context, each of the plurality of filter paths comprises a number of coefficients corresponding to the distance of a simulated object. In addition, the processing unit is configured to select a filter path of the plurality of filter paths based on the number of coefficients.

With an increasing application of radar in the industrial, automotive and private sectors, there is a growing need for testing the radar sensors in their operating environments. The common way of testing such systems is to simulate radar objects with a defined distance, velocity and size. However, the high-frequency components of the test simulator are prone to induce a frequency response and IQ imbalances that deteriorate the system performance. In general, the compensation is carried out by using filtering units, for instance Finite Impulse Response (FIR) filters or optical delay lines to provide sufficient delay and can completely compensate the abnormalities if the distance of the simulated object is sufficiently large. Disadvantageously, the said compensation cannot be performed for an object to be simulated close to the Radome since the compensation is deactivated in the transition area, which leads to a very long processing time and consequently a reduced system efficiency.
For example, US 2009/0309783 A1 demonstrates a millimeter wave radar target simulator that converts an incoming radar signal by an electrical-to-optical modulator. The converted signal is delayed through an optical delay line and then demodulated by an optical-to-electrical demodulator to a signal having a frequency that simulates a millimeter wave radar target return.
Accordingly, there is a need to provide a system and a corresponding method for radar object simulation that can compensate the frequency response and the IQ imbalances for objects, which are to be simulated very close to the Radome and hence improves system efficiency.

System and method for radar object simulation


A destructive inspection method of a vitreous silica crucible for pulling a silicon single crystal evaluates a crack state of an inner surface of the vitreous silica crucible supported by a graphite susceptor when a load is instantaneously applied to at least one point on the inner surface via an automatic center punch while pushing the tip portion of the automatic center punch against the inner surface. The destructive inspection method can inspect the vitreous silica crucible under conditions as close to the actual conditions of use as possible.

In the manufacture of a silicon single crystal by the Czochralski method (CZ method), a vitreous silica crucible is used. In the CZ method, silicon raw material is charged into the vitreous silica crucible and heated to melt. Then, a seed crystal is dipped into this silicon melt, and the seed crystal is gradually pulled up while rotating the crucible to grow a single crystal. In order to manufacture a silicon single crystal at low cost, it is necessary to improve the single crystal yield at one time of pulling process. For this purpose, it is necessary to use a large capacity crucible capable of holding a large amount of raw material.
In the preparatory stage of pulling the silicon single crystal by the CZ method, raw material blocks of polycrystalline silicon are filled in the vitreous silica crucible in advance. This filling operation is performed manually, and the raw material blocks are packed carefully one by one so that no impact will be applied to the crucible. At this time, the operation takes about 1 hour in the case of CZ pulling of a silicon single crystal having a diameter of 300 mm, for example. The vitreous silica crucible is very delicate and a breakage or a defect is easily generated. This is because the vitreous silica crucible is easily broken when a large amount of raw material is introduced vigorously. Further, in order to obtain as large a silicon single crystal ingot as possible at one time of pulling process, it is necessary to first fill as much raw material as possible in the crucible without gaps. For that purpose, a careful filling operation is required in consideration of the size, the shape and the like of the raw material blocks. Patent Document 1 describes a method of filling raw material blocks of polycrystalline silicon. In this filling method, the first layer of polycrystalline silicon blocks is formed in the crucible, and the second layer of polycrystalline silicon blocks is formed on the first layer. The height of the first layer is made lower than the height of the melt surface after all the polycrystalline silicon raw material has been melted, and the outer periphery of the second layer is separated from the inner peripheral surface of the crucible.
However, even if a careful filling operation is performed manually, a phenomenon where the vitreous silica crucible is broken suddenly during filling the small pieces of polycrystalline silicon is seen. When the vitreous silica crucible is broken, not only the crucible itself cannot be used, but also the filling operation of the raw material that has been done so far is wasted, resulting in a very large loss in terms of cost and man-hour. Such breakage is hard to be prevented completely, but it is possible to know the type and condition of an easily broken crucible, and the problem can be avoided by treating the easily broken crucible as a defective product. For that purpose, it is necessary to inspect the vitreous silica crucible in a condition as close as possible to the actual status of use.
As an inspection method of a vitreous silica crucible, for example, Patent Document 2 describes an optical non-destructive inspection method of inspecting bubbles existing in the inner surface of the vitreous silica crucible by using optical detecting means and image processing means. Further, Patent Document 3 describes a crucible inspection method of inspecting only the impurities contained in the outermost surface layer of the crucible inner surface, by specifying the impurity component from the wavelength and intensity of the fluorescence generated by laser light irradiation and calculating the content of the impurities. In addition, Patent Document 4 describes a method of inspecting an abnormal site in a vitreous silica crucible. In the method, at least one of an infrared absorption spectrum and a Raman spectrum is measured at a measurement point on the crucible inner surface, and whether or not an abnormal site such as brown ring or the like is generated at the measurement site is judged based on the obtained spectrum. Further, Patent Document 5 describes a method of obtaining the hardness of a silica sintered body crucible from the force of a release point after a load was continuously applied. In Patent Document 5, the hardness of a crucible is defined by pressing force.

Destructive inspection method and quality determination method for vitreous silica crucible


An apparatus and method for determining a source of an unauthorized copy of speech signals in a conference call session. A conference bridge receives a speech signal during a conference call session with a plurality of end user devices attending. The conference bridge provides one or more dynamic, end user specific watermarks corresponding to the one or more end user devices. Each watermark is adjusted based on characteristics of the speech signal to make the watermark imperceptible to a human being. The speech signal is then embedded with the adjusted watermark in real time to generate a modified speech signal.

Sharing speech signals in a conference call presents an opportunity for anyone in the conference call to duplicate and disseminate potentially sensitive information. Unscrupulous or nefarious individuals can copy and disseminate portions of a conference call to third parties, outside of the conference call. Since a conference call typically has three or more participants, it can be difficult or impossible to determine with any certainty the source of the unauthorized copying or dissemination.
Therefore, there exists an unmet need for a technology solution that can identify the source of any unauthorized copying or dissemination of any portion of a conference call.

This patent is subject to a terminal disclaimer.

Apparatus and method for watermarking a call signal


Methods, systems, and apparatuses may encode a media content item based on metadata from previous encoding. The encoding may also generate encoding metadata, which may comprise a qualitative or quantitative characterization of the encoded media content item. A prediction engine may, based on this metadata, determine new encoding settings for the same or a different video resolution. The prediction engine may cause an encoded media content item to be stored and may cause encoding of the media content item using the new encoding settings.

Adaptive streaming technologies allow content providers to deliver the same media content in a variety of formats, such as in different video resolutions and/or bitrates. Content providers may encode and store the same media content in a variety of formats. One approach to generating such a variety of formats is content-aware encoding, which analyzes portions of content (e.g., scenes of a television show) in order to determine appropriate encoding parameters. Content-aware encoding often requires extensive trial encodes using a one-size-fits-all approach in order to determine appropriate encoding parameters. Such processes may be computationally wasteful and time-consuming.


Disclosed is a single-mode optical fiber suitable for and optical transmission line used in WDM (Wavelength Division Multiplexing) system, which has low dispersion slope, sufficient dispersion value and large effective section area over S-, C- and L-band (1460˜1625 nm) to enable high-speed, large-capacity signal transmission. The optical fiber uses the wavelength region from 1460 to 1625 nm, and the optical fiber also has a dispersion value of 0.1˜3.0 ps/nm-km, more preferably 0.3˜2.4 ps/nm-km, at 1460 nm, a dispersion value of 3.0˜5.5 ps/nm-km, more preferably 3.2˜5.2 ps/nm-km, at 1550 nm, and a dispersion value of 4.5˜8.0 ps/nm-km, more preferably 4.8˜7.7 ps/nm-km, at 1625 nm. In addition, the optical fiber has a dispersion slope of 0.023˜0.05 ps/nm-km2 at 1550 nm, an effective sectional area of 35˜50 μm2 at 1550 nm, an effective section area of 35˜50 μm2 at 1460 nm. Thus, though the signal is transmitted through S-, C- and L-band, this optical fiber may suppress nonlinear phenomenon and signal distortion to the minimum.

A WDM system may effectively increase transmission capacity by higher transmission speed, narrower channel spacing, or wider transmission wavelength band.
The transmission speed of the system is recently increased from 2.5 Gb/s to 10 Gb/s, and it is estimated that 40 Gb/s transmission system will emerge in the market in a few years. In order to increase transmission speed, higher optical power per each channel should be provided, and due to higher optical power, non-linearity in an optical fiber is increased to deteriorate transmission characteristics.
In a system for long-distance transmission at a transmission speed of 40 Gb/s, a Raman amplifier may be used instead of existing EDFA (Erbium Doped Fiber Amplifier) to reduce non-linearity in the optical fiber. In addition, since the limit on the signal distortion by dispersion is in the inverse relation to the square of transmission speed, if the speed is increased four times, that limit is decreased to one sixteenth. Thus, the system with a transmission speed of 40 Gb/s requires accurate dispersion compensation so that accumulated dispersion of a transmission channel does not exceed the limit. For this purpose, RDS (Relative Dispersion Slope) of a dispersion compensating fiber should be similar to RDS of an optical fiber used as a transmission line. Here, RDS is defined as dispersion slope divided by dispersion, and each characteristic is described at the same wavelength.
In order to increase transmission capacity, channel spacing of the system is narrowed from 200 GHz (1.6 nm) to 100 GHz (0.8 nm) and even to less than 50 GHz (0.4 nm). However, if the channel spacing is narrowed, signal distortion is caused due to non-linear phenomenon such as four-wave mixing or cross phase modulation. In particular, in case that dispersion is not provided sufficient to prevent a phase matching condition, crosstalk power is generated by four wave mixing, thereby distorting signals.
Crosstalk power is related to channel power and channel spacing of the system, and dispersion and effective section area of the optical fiber. If the channel power is lowered to suppress non-linearity, OSNR (Optical Signal Noise Ratio) is deteriorated to make a transmission distance shorter, thereby increasing cost of the system required for longer distance transmission.
In addition, the larger dispersion of the optical fiber lowers the crosstalk power, but the length of the dispersion compensating fiber is extended in proportion to the dispersion of the optical fiber, and the loss in the part of dispersion compensation is increased. Thus, it is needed to optimize dispersion of an optical fiber according to features of a system.
Effective section area of an optical fiber shows optical intensity per unit area. As the effective section area is larger, non-linear phenomenon is more easily suppressed.
In case of increasing transmission capacity by using additional wavelength band other than C-band (1530 to 1565 nm) and L-band (1565 to 1625 nm), using a longer wavelength than L-band is not preferred because of increase in a bending loss of an optical fiber. Thus, S-band (1460 to 1530 nm) belonging to shorter wavelength bands than C-band is preferably used. However, in this case, sufficient dispersion value is required at or near 1460 nm in order to suppress four-wave mixing in the transmission wavelength band.
In addition, if dispersion slope of an optical fiber is low, dispersion in the longer wavelength region may be decreased, thereby making it possible to extend a transmittable distance without dispersion compensation over a wide wavelength band.
Along with the changes of circumstances around WDM system, various optical fibers suitable for the changes have been proposed.
U.S. Pat. No. 5,327,516 discloses an optical fiber with the dispersion in range of 1.5 to 4 ps/nm-km at 1550 nm in order to, solve the problem that a conventional dispersion shifted fiber having dispersion approximate to zero at 1550 nm causes a large amount of four-wave mixing to deteriorate transmission characteristics. However, the optical fiber proposed in U.S. Pat. No. 5,327,516 is directed to use in a system for 360 km repeater-less transmission with transmission speed of 5 Gb/s or more, channel spacing of 1.0 to 2.0 nm and four or more channels. Thus, when the optical fiber is used in a system with channel spacing of 1.0 nm or less, non-linearity is increased, which might deteriorate transmission characteristics due to signal distortion caused by four-wave mixing or cross phase modulation.
In addition, U.S. Pat. No. 5,835,655 discloses an optical fiber with an increased effective section area more than 70 μm2 and the zero dispersion wavelength is shifted out of the transmission wavelength band to suppress four-wave mixing. The optical fiber proposed in U.S. Pat. No. 5,835,655 is more effective in restraining signal distortion caused by non-linearity due to larger effective section area. In addition, since the zero-dispersion wavelength is located in 1500 to 1540 nm or 1560 to 1600 nm wavelength region, it is possible to restrain signal distortion in C-band that is caused by four-wave mixing. However, the larger effective section area makes dispersion slope higher, and that makes a dispersion value in a long wavelength band increased. As a consequence of larger effective section area and higher dispersion slope, the transmission wavelength region without dispersion compensation is narrowed.
U.S. Pat. No. 6,396,987 discloses an optical fiber capable of decreasing dispersion compensation costs rather than a general single-mode optical fiber in a system with transmission speed of 40 Gb/s. That is to say, the optical fiber of U.S. Pat. No. 6,396,987 has dispersion of 6 to 10 ps/nm-km at 1550 nm, dispersion slope of 0.07 ps/nm2-km or less, and effective section area of 60 μm2 or more. In this case, since zero-dispersion wavelength is located near 1460 nm, i.e. Raman amplification pump wavelength, signal distortion may be caused by four-wave mixing at the pump wavelength band.

Optical fiber suitable for high-speed large-scale wdm system, optical transmission line and optical transmission system using the same


A method and corresponding product whereby hydrophobic polyolefin-containing nonwoven materials are provided with sustainable hydrophilic properties for rewet purposes by incorporation into the appropriate spin melt composition an effective amount of an alkoxylated fatty amine in optional combination with up to 60% by weight of primary fatty acid amide.

While the manufacture and various uses of polyolefin-based fiber, fibrillated film, webs and corresponding nonwoven materials are well known in the textile art, attempts to broadly apply such knowledge to produce products in the area of personal hygiene, such as cover stocks for catamenial devices, disposable diapers, incontinence pads and the like, have met with limited success at best.
In general, such products must have a fluid-absorbent core, usually comprising one or more layers of fluid absorbent material such as wood pulp, rayon, gauze, tissue or the like, and, in some cases, synthetic hydrophilic material such as hydrophilic polyurethane foam.
The fluid-absorbing material is generally provided in the form of a thermally bonded pad, of wood pulp, fiber and conjugate fiber, which may have a rectangular or somewhat oval shape. To protect the clothing or areas around the user from being stained or wetted by fluids absorbed by the pad, it is generally backed by a fluid-impervious barrier sheet. In general, the absorbent product is positioned against the body with hydrophilic material facing and contacting the body and the fluid impervious barrier layer facing the outside.
To enhance a sense of comfort, such absorbent products also generally employ a facing or cover stock material which covers the body-facing surface of the product. The purpose of this cover is two-fold, namely (1) to structurally contain a loosely packed core of absorbent material as above described and (2) to protect the body from continued direct contact with the wetted absorbent material. The facing or cover stock must, therefore, be very pervious to fluids on the side of the product that is placed against the body, and yet be essentially nonabsorbent, so as to actively promote the immediate transfer of substantially all of the fluid into the absorbent core material with minimal surface fluid retention by the cover stock and minimal lateral migration of fluid along the cover stock surface.
Such material should also feel smooth and soft to the touch. In addition, certain additional characteristics are also sometimes desired, such as visual opacity plus specific coloring and luster on the outer surfaces.
In order to obtain many of above-listed characteristics, however it is imperative that cover stock utilizing essentially hydrophobic polymeric material, such as polyolefin fiber or film, be made at least temporarily hydrophilic and have the continuing ability to pass aqueous fluids through, even after several insults (i.e. wettings) without wash out or leach out of hydrophilic-promoting agents. This is particularly important in the case of diaper cover stock so as to avoid lateral liquid migration and side leakage without interfering with fabric bonding steps or wet strength of the final product.
Based on teaching in the paper-making art, it is known that short term hydrophilicity can be imparted to hydrophobic polymers such as polyolefin fiber by using flash evaporation techniques and treating the resulting fiber or filament with hydrophilizing agents such as polyvinyl alcohol or various nitrogen-containing water-soluble polymers (ref. U.S. Pat. Nos. 4,156,628, 4,035,229, 4,082,730, 4,154,647, 4,156,628, 4,035,229, 4,273,892 and 4,578,414).
For personal hygiene purposes, however, the lack of significant resistance to wash out and leaching of the art-recognized hydrophilic-promoting additives, plus interference with fiber or web bonding properties under high speed commercial operation, has justified continuing attempts to obtain improved additives and a longer term wettability. Such efforts include incorporating alkoxylated alkylphenols or corresponding polyoxyalkylenes into spun melt compositions (ref. U.S. Pat. No. 4,578,414). Serious high speed bonding and fluid control problems remain, however.
It is an object of the present invention to more effectively utilize inert hydrophobic polyolefin-containing nonwoven materials in the area of personal hygiene.
It is a further object of the present invention to efficiently utilize polyolefin-containing webs comprised of fiber, and/or fibrillated film as cover stock.
It is a still further object to obtain and retain hydrophilicity and liquid strike through properties in strong well bonded nonwoven hydrophobic materials such as continuous and/or staple fiber utilizing polyolefin component(s).

Rewettable polyolefin fiber and corresponding nonwovens


Example approaches for authenticating a device are described. In an example, a category, from a plurality of categories, is identified for a device, based on data packets exchanged between the device and a network element. The category is indicative of operational capabilities of the device. Based on the category identified for the device, an authentication order for the device is determined. The authentication order is indicative of a sequence in which a set of authentication tests is to be executed for authentication of the device.

In a network environment, network elements authenticate devices thereby enabling the devices to access data and resources in the network environment. Authentication of the devices may prevent misuse of the network environment by avoiding unauthorized access to the network environment and network-accessible resources. Authentication of the devices involves validation of different credentials, such as an assigned identifier (ID), a password, a device certificate or other authenticating information of the devices to allow or disallow access to the network environment. Authentication includes specifying access rights or privileges related to information security for the devices to control access to the network environment.

Hewlett Packard Enterprise Development LP


A part mounting method of mounting first mounting parts and a second mounting part to a board includes taking an image of a configuration of the second mounting part and performing an image-recognition, mounting the first mounting parts to the board based on a result of the image-recognition of the configuration of the second mounting part, and mounting the second mounting part to the board based on a result of an image-recognition of the first mounting parts mounted to the board.

As a mounting method for mounting electronic parts and optical parts to a board, there are face-up alignment mounting and face-down alignment mounting. The face-up alignment mounting is a mounting method of image-recognizing a mounting position on a board and a front surface (top surface) of a mounting part, and moving the mounting part to the mounting position. The face-down alignment mounting is a mounting method of image-recognizing a mounting position on a board and a back surface (bottom surface) of a mounting part, and moving the mounting part to the mounting position. Because an image-recognition mechanism (a camera, a mounting part supporting apparatus, etc.) used in the face-up alignment mounting and the image-recognition mechanism (a camera, a mounting part supporting apparatus, etc.) used in the face-down alignment mounting are different in their arrangements and configurations, the face-up alignment mounting and the face-down alignment mounting are carried out using different mounting apparatuses.
FIG. 1 is a perspective view illustrating an outline structure of a face-up alignment mounting apparatus. A mounting board 1 is placed on an XY-stage 2, and an optical part 3A, which is a mounting part, is supported by a head 5 attached to a Z-stage 4. The head 5 is formed of a transparent material such as glass. A camera 6 is arranged above the Z-stage 4 so that a front surface (top surface) of the optical part 3A supported by the transparent head 5 can be image-recognized through a through hole 4a penetrating through the Z-stage 4. The camera 6 can carry out image recognition of a mounting surface of the mounting board 1 through the transparent head 5. The camera 6 is movable up and down by a Z-axis moving mechanism 7, and, thereby, the focal position of the camera 6 can be located at the front surface of the optical part 3 or at the mounting surface of the mounting board 1.
FIG. 2 is a perspective view illustrating an outline structure of a face-down alignment mounting apparatus. A mounting board 1 is placed on an XY-stage 12. A camera 16 is arranged above the position where a mounting board 1 is placed. The camera 16 is capable of image-recognizing the mounting surface of the mounting board 1 on an XY-stage 12. The camera 16 is movable up and down by a Z-axis moving mechanism 17, and, thereby, the focal position of the camera 16 can be placed at the mounting surface of the mounting board 1.
In the face-down alignment mounting apparatus illustrated in FIG. 2, a Z-stage 14 is provided at a position shifted from the camera 16, and a mounting part supporting head 15 is attached to the Z-stage 14. The Z-stage 14 is movable up and down by a Z-axis moving mechanism 18. A camera 19 is provided above the XY-stage 12 so that the back surface (bottom surface) of the optical part 20, which is a mounting part supported by the head 15, can be image-recognized by the camera 19. It should be noted that the face-down alignment mounting illustrated in FIG. 2 is a process for mounting the optical part 20 on the optical parts 3A and 3B.
Here, a description will be given, with reference to FIG. 3A through FIG. 8, of a process of mounting the optical parts 3A, 3B and 20 to the mounting board 1 using the mounting apparatuses illustrated in FIG. 1 and FIG. 2.
FIG. 3A is a plan view of the mounting board 1. FIG. 3B is a side view of the mounting board 1. Alignment marks 1a for position detection are provided to the mounting board 1. FIG. 4A is a plan view of the mounting board 1 after mounting the optical part 3B. FIG. 4B is a side view of the mounting board 1 after mounting the optical part 3B. FIG. 5A is a plan view of the mounting board 1 after mounting the optical part 3A. FIG. 5B is a side view of the mounting board 1 after mounting the optical part 3A. FIG. 6A is a plan view of the mounting board 1 after mounting the optical part 20. FIG. 6B is a side view of the mounting board 1 after mounting the optical part 20. FIG. 7 is a flowchart of a process of mounting the optical parts 3A and 3B on the mounting board 1 using the face-up alignment mounting apparatus illustrated in FIG. 1. FIG. 8 is a flowchart of a process of mounting the optical part 20 on the mounting board 1 using the face-down alignment mounting apparatus illustrated in FIG. 2.
In the mounting process illustrated in FIG. 7, the optical parts 3A and 3B are mounted to the mounting board 1. First, in step S1, the alignment patterns 1a provided on the mounting surface of the mounting board 1 placed on the XY-stage 2 are detected by image recognition by the camera 6. At this time, the image recognition by the camera 6 is carried out by the picture of the mounting surface of the mounting board 1 taken through the through hole 4a of the Z-stage 4 and the transparent head 5.
Next, in step S2, a position where the optical part 3B is to be suction-attached and held by the head 5 is determined. The optical part 3B is accommodated in a part tray (not illustrated in the figure) provided on the XY-stage 2, and the suction-attaching position of the optical part 3B is detected by image-recognizing the optical part 3B by the cameral 6 by moving the part tray under the head 5 by driving the XY-stage 2.
Subsequently, in step S3, the optical part 3B is suction-attached and held by the head 5 in accordance with the suction-attaching position detected in step S2. Then, the mounting board 1 is located under the head 5 again by driving the XY-stage 2. Then, in step S4, the mounting surface of the mounting board 1 is image-recognized by the camera 6, and the mounting position of the optical part 3B is computed. Then, in step S5, the XY-stage 2 is moved so that the mounting position computed is located under the optical part 3B suction-attached by the head 5, and the optical part 3B is mounted on the mounting board 1 by moving the head 5 downward by driving the Z-stage 4. FIGS. 4A and 4B illustrate a state where the optical part 3B is mounted on the mounting board 1. Then, in step S6, the position where the optical part 3B is mounted is detected based on the image recognition of the camera 6.
Next, in step S7, the suction-attaching position of the optical part 3A is detected. The optical part 3A is accommodated in a part tray (not illustrated in the figure) provided on the XY-stage 2, and the suction-attaching position of the optical part 3A is detected by image-recognizing the optical part 3A in the part tray by the cameral 6 by moving the part tray under the head 5 by driving the XY-stage 2.
Then, in step S8, the optical part 3A is suction-attached and held by the head 5 based on the suction-attaching position detected in step S7. Then, the mounting board 1 is located under the head 5 again by driving the XY-stage 2. Then, in step S9, the mounting surface of the mounting board 1 is image-recognized by the camera 6, and the mounting position of the optical part 3A is computed. At this time, the mounting position of the optical part 3A is computed based on the position of the optical part 3A suction-attached to the head 5 and the position of the optical part 3B on the mounting board 1. Then, the XY-stage 2 is moved so that the mounting position computed in step S9 is located under the optical part 3A suction-attached by the head 5, and the optical part 3A is mounted on the mounting board 1 by moving the head 5 downward by driving the Z-stage 4. FIGS. 5A and 5B illustrate a state where the optical parts 3A and 3B are mounted on the mounting board 1.
According to the above-mentioned process, the optical parts 3A and 3B are mounted on the mounting board 1. Because the optical part 3A is mounted based on the result of detection of the position of the optical part 3B, which is mounted first, the optical parts 3A and 3B can be mounted with a highly accurate positional relationship.
After mounting the optical parts 3A and 3B to the mounting board 1, the process proceeds to a mounting process of the optical part 20. Here, the optical part 20 has on its back surface (bottom surface) functional parts, which cooperate with the optical parts 3A and 3B mounted previously, and the optical part must be arranged on the optical parts 3A and 3B so that the optical parts 3A and 3B and the functional parts are in an aligned state. Thus, a mounting operation of the optical part 20 to the mounting board 1 is performed in the mounting process illustrated in FIG. 8 using the face-down alignment mounting apparatus while image-recognizing the back surface (bottom surface) of the optical part 20. Therefore, after mounting the optical parts 3A and 3B to the mounting board 1, it is necessary to move the mounting board 1 to the XY-stage 12 of the face-down alignment mounting apparatus.
After moving and placing the mounting board 1 onto the XY-stage 12 of the face-down alignment mounting apparatus, first in step S11, the optical part 20 is suction-attached to and held by the head 15. The optical part 20 is accommodated in the part tray (not illustrated in the figure) provided on the XY-stage 12, and the XY-stage 12 is driven to move the part tray under the head 15 to hold the optical part 20 by the head 15. In this case, the position of the optical part 20 accommodated in the part tray has been image-recognized previously by the camera 16 and stored as image data, and the position of the optical part 20 can be detected from the image data as a result of the image-recognition and the optical part 20 can be held by the head 15.
After holding the optical part 20 by the head 15, the mounting board 1 is image-recognized, in step S12, by the camera 16 to detect the position of the optical part 3A previously mounted. Further, in step S13, the position of the optical part 3B previously mounted is also detected.
Subsequently, in step S14, the back surface (bottom surface) of the optical part 20 held by the head 15 is image-recognized to detect the present holding position of the optical part 20. Then, in step S15, the mounting position of the optical part 20 is computed based on the result of detection of the optical parts 3A and 3B in steps S12 and S13. Then, in step S16, the XY-stage 12 is driven to move the XY-stage 12 so that the computed mounting position is aligned with the optical part 20 held by the head 15, and the Z-stage 14 is moved downward to mount the optical part 20 to the mounting board 1. At this time, as illustrated in FIGS. 6A and 6B, the functional parts 20a of the optical part 20 is in an aligned state with the optical parts 3A and 3B.
As mentioned above, according to the conventional mounting method, face-up alignment mounting of the optical parts 3A and 3B is performed first, and, subsequently, face-down alignment mounting of the optical parts 20 is performed. That is, although the mounting apparatuses are different, the positions of the mounting board 1 and the optical parts 3A and 3B are image-recognized by the cameras 6 and 16 from the upper side and the back surface of the optical part 20 is image-recognized by the camera 19, and the mounting position of the optical part 20 is determined according to the thus-acquired image-recognition data.
Here, there is suggested a chip bonding apparatus which, when mounting a single semiconductor chip to a board according to face-down alignment mounting, performs positioning of the semiconductor chip by image-recognizing the back surface of the semiconductor chip by one camera and image-recognizing the mounting surface of the board by another camera (for example, refer to Japanese Laid-Open Patent Application No. 9-8104).
As mentioned above, in the case where after mounting a plurality of first mounting parts (corresponding to the optical parts 3A and 3B) to a board according to face-up alignment mounting, a second mounting part (corresponding to the optical part 20) is mounted to the board (corresponding to the mounting board 1) according to face-down alignment mounting, the plurality of mounting parts can be mounted on the board with high positional accuracy with each other and the second mounting part can be accurately positioned to the plurality of first mounting parts on the board. However, because there is a manufacturing variation in the position of the functional parts in the second mounting part, even if the relative position accuracy is raised, there may be a problem in that the first mounting parts cannot be accurately positioned to the respective functional parts of the second mounting part having variation in the relative positions.
Additionally, when performing face-down alignment mounting, there is a problem in that the camera for image-recognizing the mounting surface of the board and the camera for image-recognizing the back surface of the part are different cameras, and it is difficult to prevent an offset even if the positions and angles of the cameras are accurately corrected and the results of the image-recognition results are combined.
Further, if the resolution of the cameras is increased in order to perform highly accurate image-recognition, the view is narrowed and it becomes difficult to recognize the position of the part accommodated in the part tray. Thus, if a wide-view camera for recognizing the part positions is provided separately, it invites an increase in size and cost of the mounting apparatus.


A drill bit assembly having an electrically isolated gap joint for electromagnetic telemetry comprises a drill bit, a pin body, an electrically insulating gap joint therebetween, and an electrical conductor extending across the gap joint. The bit head has a cutting end and an opposite connecting end with an engagement section. The pin body has a tubular body with an axial bore therethrough, and comprises a connecting end with an engagement section. The pin body connecting end is connected to the bit head connecting end such that the engagement sections overlap. The electrically insulating gap joint fills an annular gap between the bit head and pin body engagement sections such that the bit head and pin body are mechanically connected together at the connecting ends but are electrically separated. The electrical conductor has one end electrically contacting one of the bit head and pin body, and the other end communicable with electronics equipment.

Modern drilling techniques employ an increasing number of sensors in downhole tools to determine downhole conditions and parameters such as pressure, spatial orientation, temperature, gamma ray count etc. that are encountered during drilling. These sensors are usually employed in logging while drilling (LWD) and 'measurement while drilling' (MWD). The data from such sensors are either transferred to a telemetry device, and thence up-hole to the surface, or are recorded in a memory device by logging tools to be used in a later time.
One type of telemetry method is electromagnetic (EM) telemetry, which uses a downhole EM transmitter to create very low frequency EM carrier waves in the formation adjacent to the well that are detected at the surface. In EM telemetry systems, the downhole carrier signal is produced by applying an alternating electric current across an electrically isolated (nonconductive) portion of the drill string. The required isolation is provided by a mechanically strong gap in a portion of drill string (called a 'gap sub') in order to maintain the torsional, bending etc. properties required for the drilling process. The EM signal originating across the gap is subsequently detected on the surface by, in general, measuring the induced electric potential difference between the drill rig and a grounding rod located in the earth some distance away.
Nonconductive materials forming the isolation section of the gap sub typically have inherently less strength and ductility than the conductive steel materials of the drill pipe, giving rise to complex designs that are necessary to complement the structural strength of gap within the drill pipe.
As described by several patent publications, many types of electrical isolation arrangements exist for the purpose of signal transmission in a drill string. Although these systems electrically isolate and seal while being subjected to drilling loads, they generally do so with a complicated multi-component design that thus becomes a relatively expensive device. Examples of such complicated and expensive designs are disclosed in U.S. Pat. Nos. 6,158,532 and 6,050,353 assigned to Ryan Energy Technologies, Inc. (Calgary, Calif.) whereby many separate components of the assembly are shown to be necessary in order to resist axial, bending and torsion forces.
It is also common knowledge in the oil and gas industry that a two-part epoxy-filled gap between coarse threads can be used to resist both axial and bending loads. Reverse torsion, which would tend to uncouple the joint, can be resisted by the insertion of dielectric pins into carefully fashioned slots. Since epoxy does not adequately seal against drilling pressures of typically 20,000 psi, additional components must be included to provide an elastomeric seal, again leading to mechanical complexity and added cost.

Drill bit assembly having electrically isolated gap joint for electromagnetic telemetry


A knife having a foldable blade includes a locking bar which holds the blade in an open position. A release lever is provided on the side of the handle for releasing the locking bar and allowing the blade to be moved to a closed position. The release lever has a laterally exposed portion which is flush with the outer surface of a bolster of the knife and a projection which extends into the recess which receives the blade when the knife is closed. The projection engages the bottom surface of the locking bar and urges it upward when the laterally exposed portion is depressed.

A wide variety of locking mechanisms are known for engaging the back of a foldable blade of a knife for securing the blade in an open position. In one known mechanism, a locking bar is pivotally mounted to an upper part of the frame of the knife, and the pivotal connection is at a location intermediate the ends of the locking bar. One end of the locking bar engages the upper surface of the blade when the blade is in the open position to hold it in that position. When the end of the locking bar remote from the end which engages the blade is depressed, the end which engages the blade is raised and releases the blade to allows it to pivot to a closed position.
This mechanism is awkward to use because the user's grip on the handle must be altered to be able to depress the end of the locking bar which is remote from the blade.


A fluid conducting system with cathodic corrosion protection is provided for at least one device that influences and/or acts upon a flow rate, such as a pump and/or valve. The device includes at least one connection device such as a device connection flange. At least one flow rate guiding device such as a pipe includes a connection means such as a pipe connection flange. The system includes annular anodes arranged between the connection devices and connection means, where anodes are electrically connected by electrical conducting lines to a monitoring device. The internal diameter of the anodes is preferably equal to the internal diameter of the flow rate guiding device and/or the inner diameter of the inlet and/or outlet of flow influencing device.

The invention relates to a fluid-conducting system with cathodic corrosion protection, having at least one device conveying and/or influencing a flow rate, in particular a pump and/or valve having at least one connection device, and having at least one device guiding a flow rate, in particular a pipe element, having connection means.
Fluid-conducting systems of this type having pumps or valves are widespread and are often used to convey and influence corrosive fluids or media, whereby the inner walls exposed to the fluid or medium sustain damage and parts of the system or of the devices have to be replaced after a certain time.
In order to protect pumps or valves against corrosion, it is known for example from South Korean patent document KR 100540390 B1 to attach a bolt connecting the casing of an valve to a water pipe to a sacrificial anode.
Pumps are also known that have sacrificial anodes arranged inside the casing. Examples for this include Japanese patent documents JP 2002295389 A, JP 2002295390 A or JP 2002242874 A.
The disadvantage with both variants lies in the fact that recurring maintenance works have to be performed and, in particular with internal sacrificial anodes, the entire system has to be switched off.
German utility patent document no. DE 7603732 U discloses a water container in the lower region of which an electric heating element is arranged. A passive anti-corrosion layer made of enamel is formed on the inner wall of the container. Furthermore, electrodes supplied with external current and providing cathodic corrosion protection are provided, wherein the electrodes can be set to an optimal potential by means of a potentiostat and a reference electrode, and at least one external current anode is arranged in the vicinity of the heating element. An arrangement of this type, however, has proven to be unsuitable for systems having a relatively high flow.
The object of the invention is to provide a fluid-conducting system or a device conveying or influencing a flow rate, having a cathodic corrosion protection system, in which the above-mentioned disadvantages are overcome, without disturbing the flow rate in the device or a pipe system connected thereto.
The object is achieved in accordance with the invention in that the fluid-conducting system comprises annular anodes, wherein an anode is arranged in each case between a first and a second connection device and/or between a first connection device and a connection means and/or between a second connection device and a connection means, the anodes are electrically connected to a monitoring arrangement by means of lines comprising one or more conductors, and the inner diameter of the anodes is equal to the inner diameter of the device guiding a flow rate and arranged on the respective anode.
According to the invention, in a further embodiment, the inner diameter of the anodes also corresponds to the inner diameter of the inflow or outflow opening, assigned to the respective anode, of the device conveying or influencing a flow rate. Turbulences and/or flow vortices in the fluid-conducting system are thus prevented.
In a further embodiment one or more threaded bores are provided in the casing, into which bores reference electrodes electrically conductively connected to the casing are screwed. It is thus possible to bring the reference electrodes into contact with the fluid or the flow rate within the casing without said electrodes protruding into the casing or without a dead space forming, i.e. a blind hole-like indentation. At the same time, this opening in the casing can be easily sealed.
The fact that the reference electrodes are arranged relative to one another in such a way that the greatest possible inner surface of the casing can be balanced in terms of the potential enables the system to be reliably operated. A state monitoring of all surfaces within the casing contacted by a medium or fluid is thus reliably ensured.
In accordance with a further embodiment, in order to optimize the operation, the monitoring arrangement comprises a control or regulation unit, a first rectifier, a second rectifier and a measuring module.
It is proposed in accordance with the invention for an annular and electrically insulating first insulation washer to be arranged between the anode and the first or the second connection device and also for an electrically insulating second insulation washer to be arranged between the anode and the connection means. It is thus possible to compensate for varying distances between the casing of the pump or the valve using insulation washers of different thickness or by using a number of insulation washers.
In order to ensure reliable insulation protection, bores are provided in accordance with the invention in the first and/or second connection device and in the connection device of the pipe elements, there being electrically insulating insulation sleeves arranged in said bores. These are preferably inserted into the bores for simple assembly.
In order to increase the insulation protection, the insulation sleeves at their free end have a collar.
The invention is also achieved by a device conveying or influencing a flow rate, in particular a pump arrangement or valve arrangement for a fluid-conducting system with cathodic corrosion protection.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of one or more preferred embodiments when considered in conjunction with the accompanying drawings.

Fluid-conducting system with cathodic corrosion protection


A method of producing titanium metal with titanium-containing material which includes mixing, pressing and drying the titanium-containing material with a carbonaceous reducing agent to obtain a resultant as a first anode. Using a metal or an alloy as a first cathode, and using an alkali metal chloride molten salt and/or an alkaline earth metal chloride molten salt as a first electrolyte to constitute a first electrolysis system, to perform pre-electrolysis in an inert atmosphere to obtain a residual anode. After the residual anode is washed, molded and dried, using the residual anode as a second anode, using a metal or an alloy as a second cathode, using an alkali metal chloride molten salt and/or an alkaline earth metal chloride molten salt as a second electrolyte to constitute a second electrolysis system, to perform electrolysis in an inert atmosphere to obtain titanium metal powder.

Field of the Invention
The present disclosure relates to a technical field of preparing a titanium metal by molten salt electrolysis, more particularly, to a method for directly producing a titanium metal powder with titanium-containing material such as high titanium slag and rutile.
Background Art
A titanium metal has many advantages such as low density, good corrosion resistance, plasticity, high specific strength and the like, which is widely used in fields such as aerospace, artificial satellite, military industry, chemical industry, petroleum, metallurgy, light industry, electric power, seawater desalination, naval ships, textile process and medical treatment, thus the titanium metal is acclaimed as the Metal of 21st.
Currently, the industrial production method of sponge titanium is still a magnesiothermic reduction process, which includes: a titanium mineral is enriched, chlorinated and rectified to prepare TiCl4, then after the TiCl4 is reduced to the sponge titanium using magnesium in argon or helium inert atmosphere, the magnesium and MgCl2 are separated and removed by performing vacuum distillation, finally the sponge titanium is finishing processed to obtain a finished sponge titanium. The method has a high productivity and facilitates commercialization, thus it seems that this method is irreplaceable so far. However, the method has disadvantages such as long process flow, long production period, low reduction ratio, high price of a reducing agent, and difficulty in achievement of continuous processes, resulting in high manufacturing cost of the sponge titanium.
There are many methods for preparing a titanium metal, and representative methods are as follows: an FFC method proposed by Cambridge University, an OS method proposed by Kyoto University, a PRP method proposed by Okabe etc. from Japan, and fluotitanate reduction etc. However, the industrialization has not been realized so far, because each method has technical problems that cannot be resolved currently.
A Chinese patent application with a publication number CN1712571 A discloses a method of preparing pure Ti through electrolysis directly from solid solution anode TiO.mTiC with metal conductivity. The solid solution anode TiO.mTiC in this method uses carbon and titanium dioxide or titanium carbide and titanium dioxide as raw material, the raw material is mixed in powder form based on reaction stoichiometry, then the raw material is pressed and molded and the raw material reacts in vacuum at 600-1600° C. to obtain the solid solution anode TiO.mTiC. The above method has the advantages such as simple process, and continuous electrolysis processes; however, the method needs to prepare solid solution TiO.mTiC under the conditions of vacuum and high temperature, thus the method has a high energy consumption and uses high-cost titanium dioxide as materials.
An United States patent document with a publication number U.S. Pat. No. 7,410,562B2 discloses a method of preparing a titanium metal using a composite anode of TiO2—C, which is a combination method of a thermal and an electrochemical process, and the key point of which is heating carbon and titanium-containing material to form a TiCxOy composite anode, then using the TiCxOy composite anode as a soluble anode to perform molten salt electrolysis, and obtaining the titanium metal at a cathode. The method has the similar advantages and disadvantages to those in the above Chinese patent application, that is, the method also needs to prepare composite anode by thermal reduction under the conditions of vacuum and high temperature, thus the method also has high energy consumption, and which also uses high-cost titanium dioxide as materials.

Method of producing titanium metal with titanium-containing material

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