A method of recording information on a recording medium includes generating a plurality of blocks, each having a certain, in the recording area of the recording medium and recording data and directories for effecting the control of the data in the same block in each of the blocks.

1. Field of the Invention
This invention relates to an information recording method for recording data and directories for controlling the data on a recording medium.
2. Related Background Art
A floppy disc using magnetism to effect recording and reproduction and a card-like optical information recording medium (hereinafter referred to as the optical card) using light to effect recording and reproduction are known as information recording mediums. In these information recording mediums, auxiliary data for controlling data for each type, i.e., so-called directories, are used to store a large capacity of data therein. A directory usually has written therein file information such as the name of the file, the length of the file and the head data track number, whereby file control of the data track portion is effected.
The optical card, particularly, the nonerasable postscript type optical card, has a large capacity of recording even if the dimensions thereof are the same as the size of a credit card. The dimensions of the credit card are about 85 mm .times. 55 mm, and when the information track pitch is 20 .mu.m and the record length of 1 bit is 5 .mu.m,
the number of tracks is 55.div.(20.times.10-3)=2750, PA1 the bit capacity/track is 85.div.(5.times.10-3)= 17000 (bits), PA1 the byte capacity/track is 17000.div.8=2000 (bytes). PA1 2750.times.2000=5500000=5.5 (M bytes).
Accordingly, the total data capacity is
To control such a large capacity of information, the information control technique using directories is indispensable.
FIG. 1 of the accompanying drawings a schematic plan view showing an example of such an optical card. In FIG. 1, data tracks 10.sub.1, 10.sub.2, . . . , 10.sub.n are recorded in the recording area of the optical card 1 in succession from one end thereof in the direction of arrow E. Each data track comprises a data portion 12 and an address portion 11 indicative of the track number. Also, directories 20.sub.1, 20.sub.2, 20.sub.3, 20.sub.4, . . . for controlling said data are written in the fashion of postscript in the direction of arrow D from the other end of the recording area. Such a recording method is described in detail in Japanese Laid-Open Patent Application No. 279957/1986.
However, in the above-described recording method, the data are arranged in order of time of recording. Therefore, when reproducing these data, the necessary files (the data groups associated with one another) are not always arranged in a grouping.
Assuming, for example, that there is an information recording medium on which a certain doctor has recorded data such as electrocardiograph information and brain-wave information of a certain patient from one year of age until fifteen years of age, the electrocardiograph information and the brain-wave information at one year of age, the electrocardiograph information and the brain-wave information at two years of age, and so on are recorded on that information recording medium in the fashion of postscript. Accordingly, when the need to reproduce only the electrocardiograph information from that information recording medium occurs, access to the data file will be desultory and the access time will be long.
Also, when there is a large defect in the information recording medium and there is an area in which recording and reproduction is impossible, it is desirable to use the recording medium while avoiding that area in order to improve the recording-reproducing speed. However, in the recording method according to the prior art, there has been the problem that directories become complex to evade the defective area and the control of data becomes cumbersome.

Information recording method for recording data and directories in a plurality of blocks comprising divided recording areas


Lamp oil compositions including methyl palmitate, methyl stearate, myristyl alcohol, an alcohol with less than six carbons, preferably ethyl alcohol, and fragrance. Also disclosed herein are lighter fluid compositions which include methyl laurate, methyl stearate, ethyl alcohol and fragrance.

1. Field of the Invention
This invention relates to compositions for lamp oil and lighter fluid.
2. Description of Related Art
Traditional lamp oils and lighter fluids are petroleum fuels, which inherently have many problems. These petroleum fuels containing known toxins and carcinogens can be harmful to people and the environment and can even be fatal if swallowed by small children.
These petroleum fuels have low flash points and are highly combustible. In the case of lighter fluids when they are being dispensed from a container onto burning material such as charcoal briquettes, the flame can travel up the fluid stream, seriously burning the user. Permits are needed to sell lighter fluids because of the flammability dangers. The high flammability also means that the transport of petroleum lamp oils and lighter fluids on aircraft is prohibited. Additionally, strict safety precautions need to be followed to manufacture these petroleum-based fuels and only specific manufacturers are used to manufacture them. The high combustibility also means that fragrance load therein must be low, typically less than three percent by volume, and thereby the ideal amount of fragrance often cannot be added into the fuel.
These fuels burn with soot emissions that often can cause visible black smoke and deposit. In the case of lamps oils, the wick undesirably emits black soot after being extinguished. Also, if spilled, these fuels can damage fabrics and other materials.
From the preceding descriptions, it is apparent that the devices currently being used have significant disadvantages. Thus, important aspects of the technology used in the field of invention remain amenable to useful refinement.

Lamp oil composition and lighter fluid composition


A system and method for determining popularity of a video based in part on requests for the video received from a referrer, grouping videos whose popularity based on requests from referrers exceeds a threshold and displaying those videos in a channel or providing them in a web feed.

1. Field of the Invention
The present invention relates generally to grouping videos for presentation to users of the Internet based on the website or websites from which other users watch the videos.
2. Description of the Background Art
Various web sites exist that provide hosted video content to viewers. One such site is the YOUTUBE™ site, provided by Google Inc. of Mountain View, Calif. Typically, videos are supplied to the video hosting website by content providers, and are then made available for viewing by the public at large. A third-party website can also embed a video player configured to play a video hosted at the video hosting site. When a user at the third-party website views the embedded video, the content is provided from the video hosting site and displayed to the user in the embedded player at the third-party website. A common problem with conventional video hosting sites is that users find it difficult to discover videos that interest them. Or while, users may discover some interesting videos, there may be many more videos that they would like that that they do not discover.

This patent is subject to a terminal disclaimer.


The disclosure relates to an apparatus for segregating particles on the basis of their ability to flow through a stepped passageway. At least some of the particles are unable to pass through a narrower passageway bounded by a segregating step, resulting in segregation of the particles. The breadth of the leading edge of at least one step of the apparatus is significantly greater than the overall width of the passageway in which the step occurs, permitting high and rapid sample throughput. The apparatus and methods described herein can be used to segregate particles of a wide variety of types. By way of example, they can be used to segregate circulating tumor cells from a human blood sample.

Mechanical devices intended for manipulation of biological cells and other small particles and having structural elements with dimensions ranging from tens of micrometers (the dimensions of biological cells) to nanometers (the dimensions of some biological macromolecules) have been described. For example, U.S. Pat. Nos. 5,928,880, 5,866,345, 5,744,366, 5,486,335, and 5,427,946 describe devices for handling cells and biological molecules. PCT Application Publication number WO 03/008931 describes a microstructure for particle and cell separation, identification, sorting, and manipulation.
U.S. Pat. No. 7,993,908 describes a microscale apparatus for separating cells and other particles based on their size. The apparatus described in that patent includes a stepped separation element interposed between two regions of a void formed by a cover and body, and separation of particles within the apparatus is governed by the ability of particles initially present in one region to traverse the stepped separation element to arrive at the other region. The subject matter disclosed herein is considered an improvement upon this apparatus.
The subject matter disclosed herein can be used to segregate and manipulate biological cells, organelles, cell conglomerates, and other particles from mixed populations of particles or cells.

Methods for segregating particles using an apparatus with a size-discriminating separation element having an elongate leading edge


A method to secure unique information about a handwritten document and to provide verification of document's authenticity, integrity and non-repudiation. The method includes the following steps: creating a document having an area of interest containing information, segmenting the area of interest on the document into a plurality of elements, obtaining the average gray scale of each element, inserting the average gray scale of each element into an identifier, and attaching the identifier to the document.

A prescription is a written document which contains directions for the preparation and administration of a remedy. Prescriptions originated at the beginning of history, when there were medications and a writing system to capture directions for their preparation and usage.
Modern prescriptions evolved with the separation of the role of the pharmacists, lens maker, dental technician, etc. from that of the physician, optician, or dentist. A prescription may direct a pharmacist to mix or compound medications in the pharmacy for the specific needs of the patient, or direct a lens maker to prepare optical lenses having particular characteristics. Prescriptions may also be used by dentists to direct dental technicians to prepare crowns as directed.
Pharmacists and physicians are regulated professions in most jurisdictions. A prescription as a communications mechanism between them is also regulated and is a legal document. Regulations may define what constitutes a prescription, the contents and format of the prescription. States may require that a prescription contain the following elements: the name or names and address of the patient or patients; the name and quantity of the drug or device prescribed and the directions for use; the date of issue of the prescription; the name, address, and telephone number of the prescriber, his or her license classification, and his or her federal registry number, if a controlled substance is prescribed; a legible, clear notice of the condition for which the drug is being prescribed, if requested by the patient or patients; and the signature of the prescriber issuing the order.
Currently, prescriptions are written on stationary paper pads. Thus, one of the problems of the prior art is that it is difficult for the pharmacist to authenticate the signature of the prescriber on the prescription or to identify that the same prescription was not reused.
Prescriptions are sometimes forged because someone may be a hypochondriac and a prescriber may not be willing to write a prescription for the hypochondriac. More often drug addicts, or drug pushers forge prescriptions for narcotics, because the narcotics may not be otherwise available, the narcotics are cheaper and safer as prescription drugs than as street drugs. Thus, an additional problem of the prior art is to reduce the amount of forged prescriptions.
Another problem of the prior art is that the holder of a valid prescription may change some of the information on the prescription, i.e., change the dosage of the prescribed medication from 10 mg to 100 mg, etc.

Secure prescription computer for generating prescriptions that can be authenticated and verified


A resin composition including 40 parts by weight or more and less than 95 parts by weight of a polycarbonate resin and 5 parts by weight or more and less than 60 parts by weight of a polyester-polyether copolymer as a base resin, wherein the polyester-polyether copolymer is a copolymer which is obtained by a polymerization using a germanium compound catalyst, includes aromatic polyester units and modified polyether units represented by the following general formula 1, and has an IV value within a range of 0.30 to 1.00 can be well-balanced in moldability, heat resistance, impact resistance, and low linear expansion property, without deteriorating a surface appearance of a molding obtained therefrom.

Polycarbonate resins have hitherto been known as they have the best impact resistance and a good heat resistance, among engineering plastics. For that reason, they are used in various fields utilizing these features; however, they have defects such as a poor chemical resistance, a poor molding processability, and a thickness dependence on the impact resistance.
On the other hand, thermoplastic polyesters have a good chemical resistance and a good molding processability, but they have defects of a poor impact resistance and a poor dimensional stability.
With the aim of utilizing the features of each resin and covering the defects, various resin compositions have been proposed. For example, it has been attempted that the impact resistance, the heat resistance, the chemical resistance, the weatherability, and the moldability, which are required for automobile parts, are simultaneously satisfied.
A resin composition including a polycarbonate resin and a polyester modified with polyethylene glycol, polytetramethylene glycol, or the like, is also proposed. However, the composition has an improved moldability, but the heat resistance thereof is insufficient for exterior parts for automobiles.
A resin composition including a polycarbonate resin, and a polyester-polyether copolymer having block units of a polyalkylnene glycol adduct of a bisphenol and produced using a germanium catalyst, is also proposed. For example, Patent Document 1 discloses a resin composition including 30 parts of a polyethylene terephthalate block-copolymer having 30% of a polyethylene oxide adduct of bisphenol A having a molecular weight, of 1000 and 70 parts of polycarbonate, whose moldability, heat resistance and impact resistance are well-balanced without deteriorating its surface appearance of the molded article. The publication discloses that in this composition, the impact resistance is improved by admixing a graft-copolymer including an elastomer as an impact resistance improver.
At the present day, in electric appliances such as cell phones and personal computer housings and parts for vehicles such as fenders, door panels, and back door panels for automobiles, weight reduction is strongly desired, and accordingly it is advanced to reduce a wall thickness of a molded article. In order to response this requirement, a resin composition, which is a molding material for the molded article, is desired to have a further improved moldability and impact resistance.
Patent Document 1 discloses, as described above, that the resin composition having a good thin-wall moldability can be obtained by using the polyester-polyether copolymer, and the composition can provide products with a high quality in electric appliances such as cell phones and personal computer housings, and large-sized molded articles such as fenders, door panels, and back door panels for automobiles, which are required to have a reduced wall-thickness. However, in order to response the requirement to further reduce the weight, if the composition in Patent Document 1 is used for a large-sized molding which is required to have a further reduced wall thickness, the resulting fluidity is sometimes insufficient. In such a case, a measure is taken in which a molding temperature is set at a higher temperature to improve the fluidity. As a result, the resin is thermally deteriorated to generate decomposed gases, thus resulting in worsened appearance of the molding, with the impact resistance and the heat resistance being also decreased.

Polycarbonate resin composition with superior fluidity and molding thereof


A battery management system for batteries at a geographical location may include wireless battery chargers at the geographical location for charging the batteries and wireless battery monitors at the geographical location and carried by associated ones of the batteries. The battery management system may also include a battery management cloud server for communicating with the wireless battery chargers and the wireless battery monitors to remotely collect battery charging status data from the wireless battery chargers based upon charging of the batteries and to remotely collect battery status data for the batteries from the wireless battery monitors. The battery management cloud server may also remotely process the battery and charger status data to schedule the batteries for use based upon the battery and charger status data.

Batteries are utilized in many traction and motive power applications to power electrical equipment and vehicles. Typical motive power applications include electric forklift trucks, reach trucks, pallet jacks, and automated guided vehicles.
In order to ensure proper operation of these vehicles, the batteries need to be charged regularly and may need to be monitored. Battery charging is the process of replenishing the discharged electrical energy from the electrical power network. This task is accomplished by employing battery chargers that are equipped with microprocessor controls to optimize the battery charging process.
Most battery chargers incorporate a power conversion stage for converting the incoming alternating current (AC) power from the electrical grid into a direct current (DC) power suitable for the battery. In addition, current chargers typically incorporate sense circuitry along with microprocessor controls to control the output current and voltage of the charger throughout the charge process, as well as save charge cycle records. Advanced chargers may also incorporate wired or wireless interfaces, such as RS-232, USB, ZigBee, Bluetooth, or WiFi, which allows end users to set up the charger parameters. The onboard microprocessor typically runs a firmware program that controls the charger operation, stores data, and communicates with a computer or handheld device to receive new charger set points.
Battery monitoring may also be desirable to monitor the status of batteries to ensure proper battery health and performance. A typical battery monitoring unit typically incorporates a microprocessor, memory for data storage, sensing circuitry, and some wired or wireless interface to set up the unit and download stored parameters. The battery monitor measures and stores battery voltage, battery current, battery temperature, and battery amp-hours throughout the charge and discharge (use) cycles. In addition, various settings are typically stored in these battery monitoring units including battery size, nameplate rating, battery ID and serial number, among other things. The battery monitor onboard microprocessor typically runs a firmware program that controls the charger operation, stores data, and communicates with a computer or handheld device to receive new charger set points and download stored data.
In most applications, the battery is sized to power an industrial truck for a single shift. As such, in multi-shift applications, battery changing may be desirable. This typically requires more than one battery per truck to power the truck throughout the day. When a depleted battery is removed from the truck, it is typically placed on a rack to be charged. Typical battery racks may have anywhere from a few batteries to hundreds of batteries stacked on shelves with chargers connected to each battery. Battery charging can take approximately eight (8) hours followed by a cool down period of a few hours. As battery racks may have multiple batteries connected to the chargers, the task of selecting the ready battery, namely a charged or a rested battery, can be daunting.
Battery light indicators have been used to alert users to batteries that are ready to be used for the next truck. However, in applications with large numbers of trucks and batteries, identifying the state of lights installed on each battery can be very difficult.
Battery management systems have been used to simplify the process of selecting the next battery that is ready to be used. These battery management systems typically include sensing devices (battery sensors) that are installed at the charger side (connected to the charger cable) that detect whether a battery is connected or not. These sensors are typically equipped with daisy chained communication ports (links) that ultimately connect to a central controller. Each sensor is assigned to a specific charger and specific battery bay with racks, where a given battery is placed. The combination of the central controller along with the battery sensors track connectivity of batteries, charge process, and duration of charge termination to identify the order of batteries to be selected. These systems may include visual and audio alerts notifying users which battery to select and/or alerting users when selecting the wrong battery.
One of the main drawbacks of most battery management systems is the cost involved in installing the added hardware and software to manage these batteries. Typical systems can costs thousands to tens of thousands of dollars, making their deployment limited to customers with very large fleets. In addition, many of the analytics and decisions made by these systems is limited as batteries cannot be uniquely identified. For example, if multiple batteries are ready to be selected, the system simply selects the first battery that reported being ready (first-in-first-out or FIFO system).
Another limitation of most battery management systems is that they are add-on devices that are separate from the chargers and do not report any charger status. For example, if the charge cycle did not terminate correctly due to battery fault or charger fault, the battery management system may still list the battery as being ready for use. In fact, since most batteries in use are flooded lead acid batteries, many of these batteries may require watering after a charge cycle to ensure proper operation. Yet, most battery management systems cannot even identify the batteries, and hence cannot assess any battery status issues.
Due to the drawbacks of many existing battery management systems, further improvements may be desirable for a cloud based battery management system.

Battery management system including cloud server to schedule batteries for use and related methods


A surfactant composition comprising alkylarylsulfonate molecules wherein more than 30 wt. % of the alkylarylsulfonate molecules of the surfactant composition are species of the formula:[R—X—Ar(SO3)−]a[Mn+]b wherein:    X is a linear acyclic aliphatic hydrocarbyl chain;    R is bound to a non-terminal carbon atom of X and is selected from H and C1 to C3 alkyl groups;    X and R together have 10 or less carbon atoms, preferably 9 or 10 carbon atoms, most preferably 10 carbon atoms;    Ar is an aromatic group;    M is a cation or cation mixture,    n is selected from 1, 2 and 3; and    a and b are selected such that the alkylarylsulfonate molecule is electroneutral.

This invention relates to improved surfactant compositions.
Alkylbenzene sulfonates, the sulfonated derivatives of alkylbenzenes, are known surfactants commonly used in a variety of applications where surfactants are required (detergents, hard-surface cleaners, drilling fluids, cutting fluids, etc.). An alkylbenzene molecule includes an acyclic aliphatic alkyl chain, typically produced by distilling a boiling range fraction of hydrocarbons from a petroleum based feedstock. This boiling range fraction typically contains mostly hydrocarbons having between 10 and 13 carbon atoms per molecule (C10-C13 hydrocarbons). This alkyl chain is typically dehydrogenated and alkylated with benzene to form alkylbenzene, the hydrophobic portion of the alkylbenzenesulfonate molecule. The alkylbenzene molecule is further derivatized, typically via sulfonation with sulfur trioxde, to produce the alkylbenzenesulfonate, where the sulfonate group is attached to the benzene portion of the alkylbenzene, and is the hydrophilic portion of the surfactant molecule.
Historically, highly branched alkylbenzenesulfonate (ABS) surfactants were used in detergents. However, these were found to be poorly biodegradable and were replaced by linear alkylbenzenesulfonates (LAS), which are readily biodegradable. Further improvements to LAS include the production of "modified LAS", or "MLAS" (MLAS), which consists of 2 modifications to the LAS molecule: a higher concentration of the 2-phenyl isomer, which improves surface activity, and the introduction of a limited amount of methyl-branching in the alkyl chain, which improve solubility.
Although typical alkylbenzenesulfonates are popular due to their availability and excellent cost/performance attributes, they are prone to interaction with hard-water ions (calcium & magnesium ions), which effectively reduces their solubility, and therefore their ability to act as surface active agents. Colder temperatures exacerbate this effect. Even C10-13 MLAS, although improved in terms of surface activity and solubility, is negatively impacted by water hardness ions and/or colder water temperatures.
In order to evaluate the effectiveness of surfactant or detergent compositions, it would therefore be important to measure various performance parameters such as intrinsic detergency performance (cleaning ability), Ca2+ (water hardness) tolerance, surface activity, salt (NaCl) tolerance and cold water detergency performance.
A test of Intrinsic Detergency gives an indication of a surfactant's cleaning ability, and is therefore a test of detergency performance. The Ca2+ tolerance/turbidity measurement provides information on the level of soluble surfactant available for interfacial activity in dependence of the water hardness. With increasing water hardness (increasing amounts of calcium ions) the solubility of LAS type surfactants usually decreases; the surfactant starts to precipitate and the solution becomes turbid.
In order to evaluate the interfacial activity of a surfactant composition, the surface tension of surfactant compositions can be determined in dependence of the water hardness. This measurement determines the optimum solubility conditions for the given surfactant in order to maximize interfacial activity.
The dynamic surface tension measurement is the determination of the surface tension (or interfacial activity) in dependence of the surface age. Especially for dynamic processes like washing and cleaning the dynamic properties of a surfactant are even more important than the static ones.
Salt (NaCl) tolerance is determined by measuring solubility of the surfactant in solutions of high ionic strength. The measurement of the transparency of the solution gives an indication of the surfactant's solubility at a specific salt concentration. High salt tolerance would be important for technical applications where high salt loads are found. Examples include enhanced oil recovery (EOR), emulsion polymerization or metal working fluids.
Lastly, it would also be important to evaluate a surfactant's cold water detergency performance by determining its ability to remove solid soil under cold water conditions.
It is an object of this invention to provide new surfactant compositions that, apart from being readily biodegradable, soluble and having good surface activity, have significantly improved hard water tolerance, good physical application (washing) properties at higher water hardness and low temperature conditions, and have excellent tolerance to ionic strength.


A recording/playback apparatus, includes a supplying device for supplying continuous data at a predetermined transfer rate. A recording device having a certain seek performance and recording mode records the continuous data on the recording medium in a recording unit, and a first setting device sets the size of the recording unit according to the transfer rate of the supplied continuous data or the seek performance of the recording device or the recording mode. The recording device includes a designating device for designating the transfer rate according to the recording mode. The apparatus further comprises a second setting device for setting the number of allowable retries to play back data from said recording medium according to the transfer rate or the seek performance or the recording unit size.

This invention relates to a recording/playback apparatus, a recording/playback method and a presentation medium. In particular, the present invention relates to a recording/playback apparatus capable of recording and playing back data with a high degree of efficiency by modifying the number of retries.
Data recorded or played back by a hard disc drive (abbreviated hereafter to an HDD) is controlled by a file v management function of an operating system (abbreviated hereafter to an OS) which runs on a host computer. For example, the HDD is not aware of a location or a free area into which data is to be recorded, so that, in a recording operation, data is written into a location specified by the host computer. In a playback operation, on the other hand, data recorded on a disc is read out from a location specified by the host computer.
In the case of such an OS as MS-DOS(trademark) and UNIX(trademark), a recording area of a disc is divided into data blocks or sectors each having a fixed size of 512 or 1,024 bytes during initialization. Data is recorded in data-block units. This method is referred to as a fixed-size division method.
In the case of the fixed-size division method, when a disc is initialized, a sector specific number, which is also referred to as a sector ID, is written into the beginning of a sector. A sector ID represents a physical location on a disc. Typically, a sector ID comprises an 8-bit sector number, a 16-bit track number, an 8-bit surface number and a 16-bit error-inspection code which is referred to hereafter as a CRC (Cyclic Redundancy Check) code.
The host computer controls sector IDs as a series of logical block addresses (LBAs). In an operation to record data, the host computer specifies an LBA representing a physical location on the disc into which the data is to be written.
FIG. 10 is a block diagram showing a typical configuration of the related art HDD. Assume that MS-DOS is used as an OS in this typical configuration. In the HDD 1, a microprocessor unit (abbreviated hereafter to an MPU, Micro Processing Unit) 11 controls all functions of the HDD 1. A servo circuit 12 generates a driving signal for controlling a voice coil motor (abbreviated hereafter to VCM) 13. The VCM 13 moves a magnetic head (not shown) to a predetermined track position on a disc 18. A buffer 16 is used for storing data received from an external source and data to be supplied to an external destination. A read/write channel processing unit 17 carries out processing to generate a signal to be recorded onto the disc 18 and processing to play back a signal read out from the disc 18. Controlled by the MPU 11, a hard-disc controller (abbreviated hereafter to an HDC) 15 controls operations to write and read out data into and from the buffer 16 and exchanges data with the R/W channel processing unit 17. The MPU 11, the servo circuit 12, the HDC 15 and the R/W channel processing unit 17 are connected to each other by an MPU bus 14.
ECCs (Error Correction Codes) are added to data to be recorded onto the disc 18. When an ECC error is detected for a sector in an operation to play back data from the sector, the MPU 11 issues a command to repeat the operation to read out data from the sector. This repeated operation is called as a retry. In an ordinary HDD, a number of retries are allowed and performed internally.
In a case where data can not be read out correctly from a sector, even if a number of allowable retries have been carried out, the MPU 11 treats the sector as a defective sector. In a following operation to write data into a defective sector, the data is written into a sector in an alternate area. This is called alternative-sector processing.
The HDD 1 is connected to the host computer 2 by a bus, such as an SCSI (Small Computer System Interface) bus or an IDE (Intelligent Drive Electronics) bus.
In the host computer 2, MS-DOS is used as an OS 21. A disc driver 22 is a program which allows the disc 18 to be accessed as a block device. A logical format program 23 is a program for writing necessary initialization information such as sector IDs and a file management table during initialization of the disc 18. Linked to the device driver 22 and the logical format program 23, a BIOS (Basic Input Output System) 24 renders I/O (Input/Output) services for inputting and outputting data from and to the HDD 1. The BIOS 24 can be regarded as a collection of routine programs dependent on hardware.
When data having a high rate such as AV (audio/video) data is recorded or edited on the HDD 1 in logical block units, the continuous data is scattered over the disc into small pieces of data. The scattering of data is known as fragmentation. When fragmented data is read out from a disc, the read operation frequently enters a wait state due to head seeks and disk revolutions to read target positions, breaking the continuity of the output data.
In order to solve this problem, data is recorded not in logical block units, but in cluster units each comprising several block units. Typically, the size of a cluster unit is 1,024 sectors. The size of a cluster unit is set at such a value that the continuity of output data in a playback operation is sustained, even if the data recorded on the disc is fragmented into cluster units.
The size of a cluster is made uniform for all data types in order to make operations to write and read out data easy to control. Typically, the size of a cluster is set at an extremely small value which is obtained with regular data such as text data taken as a reference. If the size of a cluster is too small, however, data recorded on the disc is prone to fragmentation described above. If a small amount of data is recorded in large cluster units, an excessively large recording area will be wasted.
The size of a cluster can also be determined from a simple proportional relation with a reference data transfer rate or an assumed transfer-channel count. In this case, however, the size of a cluster is not optimum. In addition, the type of data and the number of transfer channels are not reflected in an upper limit of the number of retries that can be carried out in the event of an error detected in a data recording or playback operation. As a result, the transfer rate is not guaranteed for data with a strict continuity requirement such as AV data.
It is thus an object of the present invention to provide a recording/playback apparatus and a recording/playback method wherein the number of retry operations is determined in accordance with the size of each of units in which data is written and/or read out so that the data can be recorded and/or played back with a high degree of efficiency without losing data continuity.
In order to attain the above objects, according to a first aspect of the present invention, there is provided recording/playback apparatus, a recording/playback method and a presentation medium. The apparatus comprises a supplying device for supplying the continuous data at a predetermined transfer rate, a recording device having a certain seek performance and recording mode for recording the continuous data on the recording medium in recording unit, and a first setting device for setting the size of the recording unit according to the transfer rate of the supplied continuous data. The first setting device sets the size of the recording unit according to the seek performance of the recording device. The recording device includes a designating device for designating the transfer rate according to recording mode. The first setting device includes a device for setting the recording unit size according to the recording mode. The apparatus further comprises a second setting device for setting the number of allowable retries according to the transfer rate. The apparatus further comprises a second setting device for setting the number of allowable retries according to the seek performance. The apparatus further comprises a second setting device for setting the number of allowable retries according to the recording unit size.

Recording/playback apparatus and method capable of modifying the number of retry operations


A source driver (20) includes: a first amplifier circuit and a second amplifier circuit each amplifying either one of input signals that are in-phase and antiphase; and a switching control circuit (29) which supplies an offset switching signal (4) for switching the input signals, the switching control circuit (29) supplying the offset switching signal (4) having a higher frequency than a horizontal synchronization signal. This provides a display drive circuit capable of enhancing a display quality while preventing a flicker from occurring in an entire display screen.

The following has been known about a conventional liquid crystal display device. An offset voltage which is incidentally produced by, for example, a manufacturing variation in a differential amplifier constituting an output circuit section (output circuit 4408 of FIG. 18) of a display drive circuit (source driver 3802 of FIG. 18) causes a difference from an ideal driving voltage to be supplied to a liquid crystal display element, so that a display image is not suitably displayed, and so-called display unevenness occurs. This causes a deterioration in display quality.
For example, Patent Literature 1 describes a technique for solving display unevenness caused by such an offset voltage. The following description discusses first to third conventional techniques described in Patent Literature 1.
(a) and (b) of FIG. 19 are block diagrams each illustrating an output circuit of a source driver IC in accordance with the first conventional technique, and also illustrating an example of an operation thereof. In (a) and (b) of FIG. 19, only blocks indicated by the respective reference numerals 4405, 4407, and 4408 in FIG. 18 are shown as circuits corresponding to two output terminals.
In (a) and (b) of FIG. 19, the reference numeral 4501 indicates a voltage follower which uses operational amplifiers in an output circuit which drives an odd-numbered output terminal, the reference numeral 4502 indicates a voltage follower which uses, in an output circuit which drives an even-numbered output terminal, operation amplifiers identical to those used in the voltage follower 4501. The reference numerals 4503, 4504, 4505, and 4506 each indicate an output alternation switch for switching a polarity of an output voltage of a liquid crystal drive output. The reference numeral 4507 indicates a D/A conversion circuit which carries out digital/analog conversion with respect to a positive-polarity voltage. The reference numeral 4508 indicates a D/A conversion circuit which carries out digital/analog conversion with respect to a negative-polarity voltage. The reference numerals 4509 and 4510 each indicate a hold memory in which display data is held. The reference numeral 4511 indicates an odd-numbered output terminal, and the reference numeral 4512 indicates an even-numbered output terminal. The reference numeral 4513 in the operational amplifier 4501 and the reference numeral 4514 in the operational amplifier 4502 each indicate an N-channel MOS input operational amplifier. The reference numeral 4515 in the operational amplifier 4501 and the reference numeral 4516 in the operational amplifier 4502 each indicate a P-channel MOS input operational amplifier.
According to the above configuration, the output circuit has two operational amplifiers, which are an operational amplifier that has an N-channel MOS transistor in its input stage and an operational amplifier that has a P-channel transistor in its input stage, are provided so that both a positive-polarity voltage and a negative-polarity voltage can be supplied (full-range supplied) to one output terminal. This makes it possible to cancel deviations A and −A caused by offset voltages in two frames (see FIG. 20).
However, according to the configuration of the first conventional technique, the output circuit has two operational amplifiers per output terminal. This causes a problem of an increase in circuit scale and electric power consumption.
In view of the above, a configuration (see (a) and (b) of FIG. 21) which allows a smaller circuit scale and lower electric power consumption by halving the number of operational amplifiers is taken as an example of the second conventional technique. However, according to the configuration, two operational amplifiers (operational amplifiers 4601 and 4602) each driving one output differ between a case where a positive-polarity voltage is outputted and a case where a negative-polarity voltage is outputted. Therefore, unlike the case of the first conventional technique, it is impossible to cancel offset voltages produced by, for example, a manufacturing variation. This is specifically described below with reference to FIG. 22.
FIG. 22 shows a waveform of a liquid crystal driving voltage in a case where the operational amplifier 4601 has an offset voltage A and the operational amplifier 4602 has an offset voltage B. In FIG. 22, deviations from respective expectation voltages differ between the case where a positive-polarity voltage is outputted and the case where a negative-polarity voltage is outputted. Accordingly, a component (=(A−B)/2) of a difference between the two deviations remains as an error voltage in an average voltage of driving voltages which are to be applied to liquid crystal display pixels. The error voltage, which is incidentally produced for each drive output terminal, causes a difference in applied voltage between pixels of a liquid crystal display device, so that display unevenness occurs.
The third conventional technique (e.g., techniques described in Patent Literatures 1 and 2) is taken as an example of a technique for solving the problems of the first and second conventional techniques.
FIG. 23 shows a configuration example of a differential amplifier circuit in accordance with the third conventional technique. Note that FIG. 23 shows a case where N-channel MOS transistors are used as input transistors.
The reference numerals in FIG. 23 indicate respective members as below. The reference numerals 101 and 102 each indicate an N-channel MOS input transistor. The reference numeral 103 indicates a constant current source that supplies an operational electric current to the differential amplifier circuit. The reference numeral 104 indicates a load resistor (resistance element) of the input transistor 101. The reference numeral 105 indicates a load resistor (resistance element) of the input transistor 102. The reference numerals 106 and 107 each indicate a switch for switching an input signal. The reference numerals 108 and 109 each indicate a switch for switching an output signal. The reference numeral 110 indicates an in-phase input terminal. The reference numeral 111 indicates an antiphase input terminal. The reference numeral 112 indicates an in-phase output terminal. The reference numeral 113 indicates an antiphase output terminal. The reference numeral 114 indicates a switching signal input terminal via which a switching signal for simultaneously switching the switches 106 to 109 is inputted.
The input transistor 101, the load resistor 104, the input transistor 102, and the load resistor 105 constitute an amplifier circuit. The transistors 101 and 102 constitute a differential pair. The switches 106 to 109 are simultaneously controlled by the switching signal 114. Note that the in-phase input terminal 110 corresponds to a + input terminal of the operational amplifier 4601 illustrated in FIG. 21 and that the antiphase input terminal 111 corresponds to a − input terminal of the operational amplifier 4601 illustrated in FIG. 21.
FIG. 24 illustrates a state in which the differential amplifier circuit illustrated in FIG. 23 operates. FIG. 25 illustrates another state in which the differential amplifier circuit illustrated in FIG. 23 operates. The following description discusses, with reference to FIGS. 24 and 25, how the differential amplifier circuit operates.
In the state illustrated in FIG. 24, the in-phase input terminal 110 is connected to a gate of the input transistor 101 via the switch 106. An input signal inputted via the in-phase input terminal 110 is outputted, by a function of the load resistor 104 connected to a drain of the input transistor 101, via the antiphase output terminal 113 as an antiphase output signal after passing through the switch 109. Meanwhile, the antiphase input terminal 111 is connected to a gate of the input transistor 102 via the switch 107. An input signal inputted via the antiphase input terminal 111 is outputted, by a function of the load resistor 105 connected to a drain of the input transistor 102, via the in-phase output terminal 112 as an in-phase output signal after passing through the switch 108. That is, the in-phase input signal is amplified by the input transistor 101 and the load resistor 104, whereas the antiphase input signal is amplified by the input transistor 102 and the load resistor 105.
In contrast, in the state illustrated in FIG. 25, the in-phase input terminal 110 is connected to the gate of the input transistor 102 via the switch 107. An input signal inputted via the in-phase input terminal 110 is outputted, by a function of the load resistor 105 connected to the drain of the input transistor 102, via the antiphase output terminal 113 as an antiphase output signal after passing through the switch 109. Meanwhile, the antiphase input terminal 111 is connected to the gate of the input transistor 101 via the switch 106. An input signal inputted via the antiphase input terminal 111 is outputted, by a function of the load resistor 104 connected to the drain of the input transistor 101, via the in-phase output terminal 112 as an in-phase output signal after passing through the switch 108. That is, the in-phase input signal is amplified by the input transistor 102 and the load resistor 105, whereas the antiphase input signal is amplified by the input transistor 101 and the load resistor 104.
As described above, an amplifier circuit for the in-phase input signal and an amplifier circuit for the antiphase input signal are used by being completely replaced with each other in the states illustrated in FIGS. 24 and 25.
Note here that the following description discusses, with reference to FIGS. 26 and 27, a case where there exists a difference in characteristic, which difference incidentally occurs due to, for example, a manufacturing variation, between the input transistors 101 and 102 and/or between the load resistors 104 and 105, which constitute the differential amplifier circuit.
In a case where a difference occurs between two elements of the differential amplifier circuit which are supposed to have an identical characteristic, an output voltage is in a state deviating from an ideal state, so that the differential amplifier circuit has an offset voltage. Such deviation can be modeled assuming that one of the input terminals is connected to a constant voltage source. FIGS. 26 and 27 each illustrate a state of the modeling. The reference numeral 115 in each of FIGS. 26 and 27 indicates a constant voltage source which models the offset voltage of the differential amplifier circuit. Note that switching elements illustrated in FIG. 26 are identical in state to those illustrated in FIG. 24 and that switching elements illustrated in FIG. 27 are in identical in state to those illustrated in FIG. 25.
In FIG. 26, the constant voltage source 115 is connected to the antiphase input terminal 111 via the switch 107. Meanwhile, in FIG. 27, the constant voltage source 115 is connected to the in-phase input terminal 110 via the switch 107. With this configuration, since the differential amplifier circuit uses the switches 106 through 109, it is possible to change states in which offset voltages of the differential amplifier circuit which are incidentally produced due to a variation are inputted via the antiphase input terminal 111 and the in-phase input terminal 110, respectively. In these two states, the offset voltages across the in-phase output terminal 110 and the antiphase output terminal 111, respectively, are counter in sign and identical in absolute value to each other.
With the above configuration, even if an operational amplifier has an offset voltage which is incidentally produced due to, for example, a manufacturing variation, deviations from respective expectation voltages are equal to each other between a case where a positive-polarity offset voltage is outputted and a case where a negative-polarity offset voltage is outputted. Therefore, no component of a difference between the two deviations remains as an error voltage in an average voltage of driving voltages which are to be applied to liquid crystal display pixels. Accordingly, in a case where the above operational amplifier is used in a liquid crystal drive circuit, there occurs no difference in applied voltage between pixels of a liquid crystal display device, so that display unevenness can be prevented.
FIG. 28 shows a case of the differential amplifier circuit in which P-channel MOS transistors are used as the input transistors.
The reference numerals in FIG. 28 indicate respective members as below. The reference numerals 601 and 602 each indicate a P-channel MOS input transistor. The reference numeral 603 indicates a constant current source that supplies an operational electric current to the differential amplifier circuit. The reference numeral 604 indicates a load resistor (resistance element) of the input transistor 601. The reference numeral 605 indicates a load resistor (resistance element) of the input transistor 602. The reference numerals 606 and 607 each indicate a switch for switching an input signal. The reference numerals 608 and 609 each indicate a switch for switching an output signal. The reference numeral 610 indicates an in-phase input terminal. The reference numeral 611 indicates an antiphase input terminal. The reference numeral 612 indicates an in-phase output terminal. The reference numeral 613 indicates an antiphase output terminal. The reference numeral 614 indicates a switching signal input terminal via which a switching signal for simultaneously switching the switches 606 to 609 is inputted.
The input transistor 601, the load resistor 604, the input transistor 602, and the load resistor 605 constitute an amplifier circuit. The transistors 601 and 602 constitute a differential pair. The switches 606 to 609 are simultaneously controlled by the switching signal 614. Note that the in-phase input terminal 610 corresponds to a + input terminal of the operational amplifier 4602 illustrated in FIG. 21 and that the antiphase input terminal 611 corresponds to a − input terminal of the operational amplifier 4602 illustrated in FIG. 21.
FIG. 29 illustrates a state in which the differential amplifier circuit illustrated in FIG. 28 operates. FIG. 30 illustrates another state in which the differential amplifier circuit illustrated in FIG. 28 operates. The following description discusses, with reference to FIGS. 29 and 30, how the differential amplifier circuit operates.
In the state illustrated in FIG. 29, the in-phase input terminal 610 is connected to a gate of the input transistor 601 via the switch 606. An input signal inputted via the in-phase input terminal 610 is outputted, by a function of the load resistor 604 connected to a drain of the input transistor 601, via the antiphase output terminal 613 as an antiphase output signal after passing through the switch 609. Meanwhile, the antiphase input terminal 611 is connected to a gate of the input transistor 602 via the switch 607. An input signal inputted via the antiphase input terminal 611 is outputted, by a function of the load resistor 605 connected to a drain of the input transistor 602, via the in-phase output terminal 612 as an in-phase output signal after passing through the switch 608. That is, the in-phase input signal is amplified by the input transistor 601 and the load resistor 604, whereas the antiphase input signal is amplified by the input transistor 602 and the load resistor 605.
In contrast, in the state illustrated in FIG. 30, the in-phase input terminal 610 is connected to the gate of the input transistor 602 via the switch 607. An input signal inputted via the in-phase input terminal 610 is outputted, by a function of the load resistor 605 connected to the drain of the input transistor 602, via the antiphase output terminal 613 as an antiphase output signal after passing through the switch 609. Meanwhile, the antiphase input terminal 611 is connected to the gate of the input transistor 601 via the switch 606. An input signal inputted via the antiphase input terminal 611 is outputted, by a function of the load resistor 604 connected to the drain of the input transistor 601, via the in-phase output terminal 612 as an in-phase output signal after passing through the switch 608. That is, the in-phase input signal is amplified by the input transistor 602 and the load resistor 605, whereas the antiphase input signal is amplified by the input transistor 601 and the load resistor 604.
As described above, an amplifier circuit for the in-phase input signal and an amplifier circuit for the antiphase input signal are used by being completely replaced with each other in the states illustrated in FIGS. 29 and 30.
Note here that the following description discusses, with reference to FIGS. 31 and 32, a case where there exists a difference in characteristic, which difference incidentally occurs due to, for example, a manufacturing variation, between the input transistors 601 and 602 and/or between the load resistors 604 and 605, which constitute the differential amplifier circuit.
In a case where a difference occurs between two elements of the differential amplifier circuit which are supposed to have an identical characteristic, an output voltage is in a state deviating from an ideal state, so that the differential amplifier circuit has an offset voltage. Such deviation can be modeled assuming that one of the input terminals is connected to a constant voltage source. FIGS. 31 and 32 each illustrate a state of the modeling. The reference numeral 615 in each of FIGS. 31 and 32 indicates a constant voltage source which models the offset voltage of the differential amplifier circuit. Note that switching elements illustrated in FIG. 31 are identical in state to those illustrated in FIG. 29 and that switching elements illustrated in FIG. 32 are in identical in state to those illustrated in FIG. 30.
In FIG. 31, the constant voltage source 615 is connected to the antiphase input terminal 611 via the switch 607. Meanwhile, in FIG. 32, the constant voltage source 615 is connected to the in-phase input terminal 610 via the switch 607. With this configuration, since the differential amplifier circuit uses the switches 606 through 609, it is possible to change states in which offset voltages of the differential amplifier circuit which are incidentally produced due to a variation are inputted via the antiphase input terminal 611 and the in-phase input terminal 610, respectively. In these two states, the offset voltages across the in-phase output terminal 610 and the antiphase output terminal 611, respectively, are counter in sign and identical in absolute value to each other.
With this configuration, as is the case described earlier, deviations from respective expectation voltages are equal to each other between a case where a positive-polarity offset voltage is outputted and a case where a negative-polarity offset voltage is outputted. Accordingly, in a case where the above operational amplifier is used in a liquid crystal drive circuit, there occurs no difference in applied voltage between pixels of a liquid crystal display device, so that display unevenness can be prevented.
FIG. 33 illustrates a circuit configuration in which load elements of the differential amplifier circuit of FIG. 23 are replaced with active loads having a current mirror configuration. Note that FIG. 33 illustrates a case where N-channel MOS transistors are used as the input transistors.
The reference numerals in FIG. 33 indicate respective members as below. The reference numerals 1101 and 1102 each indicate an N-channel MOS input transistor. The reference numeral 1103 indicates a constant current source that supplies an operational electric current to the differential amplifier circuit. The reference numeral 1104 indicates a P-channel MOS load transistor which serves as a load on the input transistor 1101. The reference numeral 1105 indicates a P-channel MOS load transistor which serves as a load on the input transistor 1102. The reference numerals 1106 and 1107 each indicate a switch for switching an input signal. The reference numerals 1108 and 1109 each indicate a switch for switching an output signal. The reference numeral 1110 indicates an in-phase input terminal. The reference numeral 1111 indicates an antiphase input terminal. The reference numeral 1112 indicates an in-phase output terminal. The reference numeral 1113 indicates an antiphase output terminal. The reference numeral 1114 indicates a switching signal input terminal via which a switching signal for simultaneously switching the switches 1106 to 1109 is inputted.
The differential amplifier circuit is different from the configuration example (passive load) of FIG. 23 in that the load elements are the active loads having a current mirror configuration made up of transistors. In a state corresponding to that of FIG. 24, an in-phase input signal is amplified by each of the input transistor 1101 and the load transistor 1104, whereas an antiphase input signal is amplified by each of the input transistor 1102 and the load transistor 1105. In contrast, in a state corresponding to that of FIG. 25, an in-phase input signal is amplified by each of the input transistor 1102 and the load transistor 1105, whereas an antiphase input signal is amplified by each of the input transistor 1101 and the load transistor 1104.
In any of the cases, the load transistors 1104 and 1105 have a current mirror configuration. Therefore, even if there is a variation in characteristic between the load transistors, electric currents which flow in the respective load transistors 1104 and 1105 are constantly equal to each other. Therefore, the in-phase input signal and the antiphase input signal are amplified at an identical amplification degree, so that an output waveform in bilateral symmetry is obtained.
As described above, also according to the differential amplifier circuit having the structure illustrated in FIG. 33, an amplifier circuit for the in-phase input signal and an amplifier circuit for the antiphase input signal can be used by being completely replaced with each other.
Furthermore, also in a case where there exists a difference in characteristic, which difference incidentally occurs due to, for example, a manufacturing reason, between the input transistors 1101 and 1102 which constitute the differential amplifier circuit, the differential amplifier circuit of FIG. 33 is identical in structure to the differential amplifier circuit of FIG. 23 (not specifically described). Accordingly, since the differential amplifier circuit uses the switches 1106 through 1109, it is possible to change states in which offset voltages of the differential amplifier circuit which are incidentally produced due to a variation are inputted via the antiphase input terminal 1111 and the in-phase input terminal 1110, respectively. In these two states, the offset voltages across the in-phase output terminal 1110 and the antiphase output terminal 1111, respectively, are counter in sign and identical in absolute value to each other.
With this configuration, as is the case described earlier, deviations from respective expectation voltages are equal to each other between a case where a positive-polarity offset voltage is outputted and a case where a negative-polarity offset voltage is outputted. Accordingly, in a case where the above operational amplifier is used in a liquid crystal drive circuit, there occurs no difference in applied voltage between pixels of a liquid crystal display device, so that display unevenness can be prevented.
FIG. 34 illustrates a circuit configuration in which load elements of the differential amplifier circuit of FIG. 28 are replaced with active loads having a current mirror configuration. Note that FIG. 34 illustrates a case where P-channel MOS transistors are used as the input transistors.
The reference numerals in FIG. 34 indicate respective members as below. The reference numerals 1201 and 1202 each indicate a P-channel MOS input transistor. The reference numeral 1203 indicates a constant current source that supplies an operational electric current to the differential amplifier circuit. The reference numeral 1204 indicates an N-channel MOS load transistor which serves as a load on the input transistor 1201. The reference numeral 1205 indicates an N-channel MOS load transistor which serves as a load on the input transistor 1202. The reference numerals 1206 and 1207 each indicate a switch for switching an input signal. The reference numerals 1208 and 1209 each indicate a switch for switching an output signal. The reference numeral 1210 indicates an in-phase input terminal. The reference numeral 1211 indicates an antiphase input terminal. The reference numeral 1212 indicates an in-phase output terminal. The reference numeral 1213 indicates an antiphase output terminal. The reference numeral 1214 indicates a switching signal input terminal via which a switching signal for simultaneously switching the switches 1206 to 1209 is inputted.
The configuration of FIG. 34 is different from the configuration (passive load) of FIG. 28 in that the load elements are the active loads having a current mirror configuration made up of transistors. In a state corresponding to that of FIG. 29, an in-phase input signal is amplified by each of the input transistor 1201 and the load transistor 1204, whereas an antiphase input signal is amplified by each of the input transistor 1202 and the load resistor 1205. In contrast, in a state corresponding to that of FIG. 30, an in-phase input signal is amplified by each of the input transistor 1202 and the load transistor 1205, whereas an antiphase input signal is amplified by each of the input transistor 1201 and the load transistor 1204.
In any of the cases, the load transistors 1204 and 1205 have a current mirror configuration. Therefore, even if there is a variation in characteristic between the load transistors, electric currents which flow in the respective load transistors 1204 and 1205 are constantly equal to each other. Therefore, the in-phase input signal and the antiphase input signal are amplified at an identical amplification degree, so that an output waveform in bilateral symmetry is obtained.
As described above, also according to the differential amplifier circuit having the structure illustrated in FIG. 34, an amplifier circuit for the in-phase input signal and an amplifier circuit for the antiphase input signal are used by being completely replaced with each other.
Furthermore, also in a case where there exists a difference in characteristic, which difference incidentally occurs due to, for example, a manufacturing reason, between the input transistors 1201 and 1202 which constitute the differential amplifier circuit, the differential amplifier circuit of FIG. 34 is identical in structure to the differential amplifier circuit of FIG. 28 (not specifically described). Accordingly, since the differential amplifier circuit uses the switches 1206 through 1209, it is possible to change states in which offset voltages of the differential amplifier circuit which are incidentally produced due to a variation are inputted via the antiphase input terminal 1211 and the in-phase input terminal 1210, respectively. In these two states, the offset voltages across the in-phase output terminal 1210 and the antiphase output terminal 1211, respectively, are counter in sign and identical in absolute value to each other.
With this configuration, as is the case described earlier, deviations from respective expectation voltages are equal to each other between a case where a positive-polarity offset voltage is outputted and a case where a negative-polarity offset voltage is outputted. Accordingly, in a case where the above operational amplifier is used in a liquid crystal drive circuit, there occurs no difference in applied voltage between pixels of a liquid crystal display device, so that display unevenness can be prevented.
FIG. 35 shows a configuration example in which a differential amplifier circuit 1301 equivalent to the differential amplifier circuit illustrated in FIG. 33, switches, and an output section are embodied. Note that FIG. 35 corresponds to an N-channel MOS input operational amplifier.
The reference numerals in FIG. 35 indicate respective members as below. The reference numeral 1301 indicates the differential amplifier circuit illustrated in FIG. 33. The reference numeral 1302 indicates an in-phase input terminal. The reference numeral 1303 indicates an antiphase input terminal. The reference numerals 1304 and 1305 each indicate a switch switching signal input terminal. The reference numerals 1306 to 1309 each indicate a switch. The reference numerals 1310 to 1313 each indicate a switch. The reference numerals 1314 and 1315 each indicate an N-channel MOS input transistor. The reference numerals 1316 and 1317 each indicate a P-channel MOS load transistor which serves as an active load on an input transistor. The reference numeral 1318 indicates a P-channel MOS output transistor. The reference numeral 1319 indicates an N-channel MOS output transistor. The reference numeral 1320 indicates an output terminal. The reference numeral 1321 indicates a bias voltage input terminal for providing the operational amplifier with an operating point. Note here that a circuit in which the differential amplifier circuit 1301 is replaced with a differential amplifier circuit including the resistor loads of FIG. 23 carries out an operation identical to that described below. Accordingly, a detailed description of the operation is omitted here.
In FIG. 35, the reference numerals 1314 and 1315 each correspond to the switch switching signal input terminal 1114 illustrated in FIG. 33, and the terminals 1304 and 1305 receive signals whose polarities are reversed to each other. The following description discusses, with reference to FIGS. 36 and 37, operations in accordance with an input of the switch switching signal.
In FIG. 35, the input transistors 1314 and 1315 correspond to the input transistors 1101 and 1102, respectively, illustrated in FIG. 33, and the load transistors 1316 and 1317 correspond to the load transistors 1104 and 1105, respectively, illustrated in FIG. 33.
Furthermore, the reference numerals in FIG. 35 correspond to the respective members as below. The reference numerals 1307 and 1309 each correspond to the switch 1106 illustrated in FIG. 33. The reference numerals 1306 and 1308 each correspond to the switch 1107 illustrated in FIG. 33. The reference numerals 1310 and 1313 each correspond to the switch 1108 illustrated in FIG. 33. The reference numerals 1311 and 1312 each correspond to the switch 1109 illustrated in FIG. 33. A transistor 1322 corresponds to the constant current source 1103 illustrated in FIG. 33.
When the switching input signal 1304 receives an L level (low level), the switches 1306, 1307, 1310, and 1311 are turned on since these switches are P-channel MOS transistors (see FIG. 36). In this case, the switches 1308, 1309, 1312 and 1313 are turned off since the switch switching signal input terminal 1305 receives an H level (high level). An in-phase input signal 1302 is supplied to the input transistor 1315 via the switch 1306. An antiphase input signal 1303 is supplied to the input transistor 1314 via the switch 1307. Furthermore, a gate signal is supplied to each of the load transistors 1316 and 1317 via the switch 1310, and the gate signal is supplied to the output transistor 1318 via the switch 1311. In the case of FIG. 36, the in-phase input signal is amplified by a circuit constituted by the transistor 1315 and the load transistor 1317, and the antiphase input signal is amplified by a circuit constituted by the transistor 1314 and the load transistor 1316.
When the switch switching signal input terminal 1305 receives an L level, the switches 1308, 1309, 1312, and 1313 are turned on in FIG. 37. In this case, the switches 1306, 1307, 1310 and 1311 are turned off since the switch switching signal input terminal 1304 receives an H level. In this configuration, an in-phase input signal 1302 is supplied to the input transistor 1314 via the switch 1308. An antiphase input signal 1303 is supplied to the input transistor 1315 via the switch 1309. Furthermore, a gate signal is supplied to each of the load transistors 1316 and 1317 via the switch 1313, and the gate signal is supplied to the output transistor 1318 via the switch 1312. In the case of FIG. 37, the in-phase input signal is amplified by a circuit constituted by the input transistor 1314 and the load transistor 1316, and the antiphase input signal is amplified by a circuit constituted by the input transistor 1315 and the load transistor 1317.
As illustrated in FIGS. 36 and 37, according to the present differential amplifier circuit, it is possible to replace the amplifier circuit for the in-phase input signal and the amplifier circuit for the antiphase input signal with each other by switching the switches 1306 to 1313. According to this, also in a case where offset voltages are incidentally produced in the differential amplifier circuit due to, for example, a manufacturing variation in characteristic, the offset voltages are counter in sign and identical in absolute value to each other in these two states (described earlier). Accordingly, in a case where the switches 1306 to 1313 are switched, offset voltages which vary in the operational amplifier can be counter in sign and identical in absolute value to each other, so that the offset voltages can be canceled. Note that a dotted line in each of FIGS. 36 and 37 indicates a signal flow.
FIG. 38 shows a configuration example in which a differential amplifier circuit 1601 equivalent to the differential amplifier circuit illustrated in FIG. 34, switches, and an output section are embodied. Note that FIG. 38 is a P-channel MOS input operational amplifier.
The reference numerals in FIG. 38 indicate respective members as below. The reference numeral 1602 indicates an in-phase input terminal. The reference numeral 1603 indicates an antiphase input terminal. The reference numerals 1604 and 1605 each indicate a switch switching signal input terminal. The reference numerals 1606 to 1609 each indicate a switch. The reference numerals 1610 to 1613 each indicate a switch. The reference numerals 1614 and 1615 each indicate a P-channel MOS input transistor. The reference numerals 1616 and 1617 each indicate an N-channel MOS load transistor which serves as an active load on an input transistor. The reference numeral 1618 indicates an N-channel MOS output transistor. The reference numeral 1619 indicates a P-channel MOS output transistor. The reference numeral 1620 indicates an output terminal. The reference numeral 1621 indicates a bias voltage input terminal for providing the operational amplifier with an operating point. Note here that a circuit in which the differential amplifier circuit 1601 is replaced with a differential amplifier circuit including the resistor loads described in FIG. 28 carries out an operation identical to that described below. Accordingly, a detailed description of the operation is omitted here.
The reference numerals in FIG. 38 correspond to the respective members as below. The input transistors 1614 and 1615 correspond to the input transistors 1201 and 1202, respectively, illustrated in FIG. 34, and the load transistors 1616 and 1617 correspond to the load transistors 1204 and 1205, respectively, illustrated in FIG. 34. Furthermore, the reference numerals 1607 and 1609 each correspond to the switch 1206 illustrated in FIG. 34. The reference numerals 1606 and 1608 each correspond to the switch 1207 illustrated in FIG. 34. The reference numerals 1610 and 1613 each correspond to the switch 1208 illustrated in FIG. 34. The reference numerals 1611 and 1612 each correspond to the switch 1209 illustrated in FIG. 34. A transistor 1622 corresponds to the constant current source 1203 illustrated in FIG. 34.
When the switch switching signal input terminal 1604 receives an H level (high level), the switches 1606, 1607, 1610, and 1611 are turned on since these switches are N-channel MOS transistors (see FIG. 39). In this case, the switches 1608, 1609, 1612 and 1613 are turned off since the switch switching signal input terminal 1605 receives an L level (low level). An in-phase input signal 1602 is supplied to the input transistor 1615 via the switch 1606. An antiphase input signal 1603 is supplied to the input transistor 1614 via the switch 1607. Furthermore, a gate signal is supplied to each of the load transistors 1616 and 1617 via the switch 1610, and the gate signal is supplied to the output transistor 1618 via the switch 1611. In the case of FIG. 39, the in-phase input signal is amplified by a circuit constituted by the input transistor 1615 and the load transistor 1617, and the antiphase input signal is amplified by a circuit constituted by the input transistor 1614 and the load transistor 1616.
When the switch switching signal input terminal 1605 receives an H level, the switches 1608, 1609, 1612, and 1613 are turned on in FIG. 40. In this case, the switches 1606, 1607, 1610 and 1611 are turned off since the switch switching signal input terminal 1604 receives an L level. In this configuration, an in-phase input signal 1602 is supplied to the input transistor 1614 via the switch 1608. An antiphase input signal 1603 is supplied to the input transistor 1615 via the switch 1609. Furthermore, a gate signal is supplied to each of the load transistors 1616 and 1617 via the switch 1613, and the gate signal is supplied to the output transistor 1618 via the switch 1612. In the case of FIG. 40, the in-phase input signal is amplified by a circuit constituted by the input transistor 1614 and the load transistor 1616, and the antiphase input signal is amplified by a circuit constituted by the input transistor 1615 and the load transistor 1617.
As illustrated in FIGS. 39 and 40, according to the present differential amplifier circuit, it is possible to replace the amplifier circuit for the in-phase input signal and the amplifier circuit for the antiphase input signal with each other by switching the switches 1606 to 1613. According to this, also in a case where offset voltages are incidentally produced in the differential amplifier circuit due to, for example, a manufacturing variation, the offset voltages are counter in sign and identical in absolute value to each other in these two states (described earlier). Accordingly, in a case where the switches 1606 to 1613 are switched, offset voltages which vary in the operational amplifier can be counter in sign and identical in absolute value to each other, so that the offset voltages can be canceled. Note that a dotted line in each of FIGS. 39 and 40 indicates a signal flow.
As described above, according to the third conventional technique, a positive-polarity voltage is supplied from the operational amplifier which uses an N-channel MOS transistor in its input stage, a negative-polarity voltage is supplied from the operational amplifier which uses a P-channel MOS transistor in its input stage, and the positive-polarity and negative-polarity voltages are full-range outputted by being switched by the switching switch. Furthermore, according to the third conventional technique, in a case where the in-phase input signal or the antiphase input signal is switched and supplied as an input signal to a corresponding input terminal (a corresponding one of the in-phase input terminal and antiphase input terminal) of the operational amplifier, in addition to the positive-polarity and negative-polarity voltages described above, new positive-polarity and negative-polarity voltages (obtained by reversing the positive-polarity and negative-polarity voltages described above) are generated by the switching of the input signal. This makes it possible to cancel the deviations A and −A, and B and −B in four frames by switching the deviations in the frames, the deviations A and −A each being caused by the offset voltage produced in the operational amplifier which uses an N-channel MOS transistor, and the deviations B and −B each being caused by the offset voltage produced in the operational amplifier which uses a P-channel MOS transistor (see FIG. 41). The third conventional technique thus makes it possible to prevent display unevenness.

Display drive circuit, display device and method for driving display drive circuit


This invention relates to isolated polynucleotides encoding WUS polypeptides. The invention further provides isolated WUS polypeptides. The invention also provides methods of using the polynucleotides to modulate the level of WUS, improve transformation efficiency, to stimulate plant cell growth, including stem cells, to stimulate organogenesis, to stimulate somatic embryogenesis, to induce apomixis, and to provide a positive selection for cells comprising the polynucleotide. The invention also relates to cells, plants and seeds comprising the polynucleotides of the invention or produced by the methods of the invention.

Organ formation in plants occurs via the activity of apical meristems. Plant meristems contain a pool of stem cells, which are able to self-maintain, give rise to a variety of cell types including cells required for organ initiation. The initiation and maintenance of stem cells and their integration into organ-forming meristems are thus the basis for continuous plant development.
The Wuschel protein, designated hereafter as WUS, plays a key role in the initiation and maintenance of the apical meristem, which contains a pool of pluripotent stem cells (Endrizzi, et al., (1996) Plant Journal 10:967-979; Laux, et al., (1996) Development 122:87-96; and Mayer, et al., (1998) Cell 95:805-815). Arabidopsis plants mutant for the WUS gene contain stem cells that are misspecified and that appear to undergo differentiation. WUS encodes a novel homeodomain protein which presumably functions as a transcriptional regulator (Mayer, et al., (1998) Cell 95:805-815). The stem cell population of Arabidopsis shoot meristems is believed to be maintained by a regulatory loop between the CLAVATA (CLV) genes which promote organ initiation and the WUS gene which is required for stem cell identity, with the CLV genes repressing WUS at the transcript level, and WUS expression being sufficient to induce meristem cell identity and the expression of the stem cell marker CLV3 (Brand, et al., (2000) Science 289:617-619; Schoof, et al., (2000) Cell 100:635-644). Constitutive expression of WUS in Arabidopsis has been recently shown to lead to adventitious shoot proliferation from leaves (in planta) (Laux, T., Talk Presented at the XVI International Botanical Congress Meeting, Aug. 1-7, 1999, St. Louis, Mo.).
There is a great deal of interest in identifying the genes that encode proteins involved in development in plants, generally toward the objective of altering plant growth and architecture. WUS represents one such gene. However, the WUS gene can also be used for the novel application of stimulating in vitro growth of plant tissue and improving transformation. In this manner, this gene can expand the range of tissues types targeted for transformation. Specifically, the WUS gene may be used to improve meristem transformation frequencies and could result in genotype independent transformation of many important crops such as maize, soybean and sunflower. Furthermore, transformation into meristems would stimulate the formation of new apical initials reducing the chimeric nature of the transgenic events. Lastly, ectopic expression into non-meristematic cells would stimulate adventive meristem formation. This could lead to transformation of non-traditional tissues such as leaves, leaf bases, stem tissue, etc. Alternatively, transformation of a more traditional target such as callus or the scutellum of immature embryos could promote a "non-traditional" growth response, i.e., meristems in place of somatic embryos. In addition, WUS may also be used as a genetic marker for meristems. Accordingly, the availability of nucleic acid sequences encoding all or a portion of a WUS protein would facilitate studies to better understand programmed development in plants, provide genetic tools to enhance the efficiency of gene transfer into meristem tissue and help provide alternative transformation methods in several important crops.


A picture construction is provided wherein a cabinet is formed with an overlying pivotally mounted transparent glass member secured to a bottommost surface of the cabinet. The cabinet includes a series of ramps and feed troughs for storage and viewing of animals, such as gerbils and the like, therewithin. Ventilation and lighting is arranged wherein optionally selectively replaceable pictures are positionable onto a rearward face of the cabinet, wherein the pictures include fiber optic filaments therethrough, wherein an overlying illumination source directs light through the pictures and through the translucent material forming the body of the picture to enhance the visual effect of the picture in association with the animals within the cabinet.

1. Field of the Invention
The field of the invention relates to picture organizations, and more particular pertains to a new and improved live picture construction wherein a zoo-like arrangement is provided for a wall supported construction for enhanced viewing thereof.
2. Description of the Prior Art
The use of wall supported aquariums has been utilized in the prior art to provide enhanced viewing by individuals for entertainment and soothing effect of such pictures. The prior art, however, has heretofore failed to provide an organization accommodating a more animated family of animals, such as gerbils and the like, in combination with visual effects to enhance the appearance and appeal of such a picture. Examples of the prior art include U.S. Pat. No. 4,400,905 to Brown setting forth a dual purpose picture organization wherein a picture positioned within a cabinet framework is impregnated with a pesticide to mask the purpose of the picture.
U.S. Pat. No. 3,874,336 to Murphy sets forth in aquarium mounted on a wall for securement thereto.
U.S. Pat. No. 4,353,327 to Shroyer sets forth an aquarium mounted within a three-dimensional pictorial representation for securement to a wall, including a frame and a glass-front portion.
U.S. Pat. No. 4,136,638 to Fedor provides a wall mounted aquarium with a tank for securement to the wall utilizing particular securement organization portions to receive and maintain the aquarium relative to a wall portion.
U.S. Pat. No. Des. 297,625 to Lehman provides a window greenhouse for positioning of plants therewithin.
As such, it may be appreciated that there is a continuing need for a new and improved live picture contruction as set forth by the instant invention which addresses both the problems of enhanced pictorial representations of a habitat in conjunction with mammal inhabitants secured within a cabinet organization and to this extent, the present invention substantially fulfills this need.


A manufacturing method of a semiconductor device of the present invention comprises a first step of exposing a periphery of a first region of a photoresist layer coating an insulating layer formed on a semiconductor substrate and a periphery of a second region for positioning, and a second step of heating said photoresist layer in ammonia atmosphere and forming an alkali insoluble portion in the periphery of the first region and that of the second region, a third step of exposing a third region, which is smaller than the first region, and the second region and developing these regions, a fourth step of etching the third region and the second region to a predetermined depth, and a fifth step of repeating the third and fourth steps once or more in a region, which is smaller than the third region, and the second region.

1. Field of the Invention
The present invention relates to a technique of lithography and, particularly to a manufacturing method for semiconductor device wherein a stepwise taper is formed in a contract hole, that is, a opening portion, which is formed in an insulating film and metal, by the combination of a resist patterning process and a dry etching process.
2. Description of the Related Art
As is known, the degree of integration of the semiconductor element has been improved with the advance of a fine process technique of the semiconductor element. For the purpose of fining, the so-called multilayered wiring element has been generally used. In order to control leak current generated in the element, the necessary an interlayered insulating film is formed to have the thickness of 1 .mu.m or more regardless of quality. Thereby, the depth of the opening portion, which is formed in the interlayered insulating film, is increased.
As one of the fine process techniques, the frequency in use of a dry etching such as a reactive ion etching, in which an anisotropic etching is performed, is increased. For this reason, the side wall of the opening portion, which is formed in the interlayered insulating film, becomes almost vertical. Therefore, in a case where the inside of the opening portion cannot be completely embedded with the metal layer for wiring, which is deposited on the interlayered insulating film, the connection between the electrode in the opening portion and the external wiring layer is defective. To overcome this problem, there is known a method for forming taper in the opening portion contacting the wiring metal layer, that is, 20 to 30% of the entire depth, by using the combination of a chemical reaction or a physical etching.
Also, an image reversal process which can be used as the fine process technique was disclosed in Vacuum, Vol. 29, No. 12, 1989, page 585. Specifically, a mask, in which a layer interrupting light is formed, is superimposed at a predetermined position of a positive resist of a novolak type, an exposing process, which is a part of a photo engraving process, is provided therein, so that a photosensitive portion is formed therein other than the light interrupting layer of the mask. However, if this lamination layer is processed in ammonia atmosphere, the exposed and photosensitive indene carboxylic acid generates decarboxylic acid, insoluble indene is formed in alkali developer. If this phenomenon is used, a pattern to be originally formed is reversed. FIG. 1 illustrates an example of forming taper by the combination of the chemical etching and the physical etching. More specifically, a wiring layer forming of Al or Al alloy or an electrode 2 is directly or indirectly deposited on a semiconductor substrate 1 via a coating layer, and an interlayered insulating layer 3 is entirely deposited thereon.
Then, an opening portion 4 is formed on the interlayered insulating layer 3 by CDE process as a chemical etching, in which radical, which is generated by plasma generated by a magnetron tube, is moved to the distant position and RIE process as a physical etching. The edge of the opening portion 4 is etched in a certain horizontal and vertical isotropic direction by CDE process. Due to this, as is obvious from the drawing, a taper 6 is formed and a double edge is formed in positioning marks 5, which are used in an aligner process, as shown in FIG. 2. FIG. 2 is a plane view of the opening portion 4 for the positioning marks 5 seen from the above.
Moreover, FIG. 3 is a cross sectional view showing the opening portion 4 formed by providing image reversal process in the interlayered insulating layer 3. However, the side wall of the opening portion 4 is not vertically formed, and the double edge is formed in the positioning marks which are formed at the same with the above process. This causes the deterioration of the accuracy of the positioning.
In a case where the taper is formed in the opening portion 4 by the combination of the chemical etching and the physical etching, the positioning marks 5 are shaped similarly and the edges of the positioning marks look double as shown in FIG. 2. In general, to detect the positioning marks 5, reflected light of the irradiated laser is electrically compared between a setting coordinate and a measuring coordinate. Then, if the edges are discriminated several times, a plurality of detection signals are obtained, so that the positioning step fails or the accuracy of positioning is deteriorated.
Moreover, if the opening portion and the positioning marks are formed by use of the image reversal process, both the opening portion and the positioning marks are simultaneously formed, so that the taper 6 is formed in the positioning marks. As a result, since a detection signal having a clear waveform is not obtained, the accuracy of the positioning is deteriorated. In addition, regarding etching, it is difficult to set conditions such as an angle of a reverse taper and controllability and there is problem in reproductivity.

Making a semiconductor device with ammonia treatment of photoresist


A refrigerator with a multipurpose storage chamber and a control method. In the refrigerator, the flow of cool air to the multipurpose storage chamber is selectively controlled in accordance with a variety of operational modes. In order to accomplish such a cool air flow control, a refrigerating compartment fan and a damper are provided at positions above a refrigerating compartment evaporator. In addition, a flap, controlled at an open angle thereof, is provided at the inlet of an air guide path guiding the cool air to the multipurpose storage chamber. The multipurpose storage chamber of this refrigerator can thus effectively be used to store a variety of foods in accordance with storage characteristics of the foods. In addition, a thawing mode operation of the refrigerator is performed under the condition that it is not necessary to perform a refrigerating compartment cooling operation. It is thus possible to prevent an excessive increase in the temperature of the refrigerating compartment caused by an operation of the defrosting heater during such a thawing mode.

This application claims the benefit of Korean Application No. 2001-74293, filed Nov. 27, 2001, in the Korean Industrial Property Office, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates, in general, to refrigerators with a multipurpose storage chamber and a control method thereof, and more particularly, to a refrigerator having a multipurpose storage chamber in its refrigerating compartment and a control method thereof, which controls the flow of cool air to the multipurpose storage chamber.
2. Description of the Prior Art
In conventional refrigerators using an independent temperature controller (ITC), the interior of the cabinet is divided into a freezing compartment and a refrigerating compartment by a partition wall. Two doors are hinged to the cabinet at positions in the front of the two compartments, thus allowing a user to open the freezing compartment and/or the refrigerating compartment as desired. In such a refrigerator of the ITC type, an evaporator and a fan are provided at the rear portion of the cabinet at a position corresponding to each of the refrigerating and freezing compartments, thus independently supplying cool air to an associated compartment. A defrosting heater is provided at each of the two evaporators installed at the two compartments.
In the conventional refrigerators, the freezing compartment preferably stores frozen food therein, while the refrigerating compartment preferably stores cold food therein. Additional storage chambers may be provided in the refrigerating compartment. For example, a vegetable storage chamber is provided at the lower portion of the refrigerating compartment for storing vegetables and/or fruits therein.
However, the temperature of the vegetable storage chamber varies in a similar manner to a variation in the temperature of the refrigerating compartment. It is thus necessary to provide a technique of effectively storing a variety of foods in accordance with different storage characteristics of the foods. For example, some foods, such as fish, are required to be kept cold in the refrigerating compartment rather than stored in the freezing compartment, but are not suitable to be kept in the vegetable storage chamber. Therefore, in order to more effectively store such foods in the refrigerating compartment while maintaining their freshness for a desired period of time, it is necessary to provide, in the refrigerating compartment, an additional storage chamber that can reduce its temperature to a desired point within a short period of time.
Accordingly, it is an object of the present invention to provide a refrigerator with a multipurpose storage chamber and a control method thereof, which controls the flow of cool air to the multipurpose storage chamber provided in the refrigerating compartment in accordance with different storage characteristics of foods stored in the multipurpose storage chamber.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
The foregoing and other objects of the present invention are achieved by providing a refrigerator, comprising: a multipurpose storage chamber provided in a refrigerating compartment; and a cool air supply device controlling a flow of cool air to the multipurpose storage chamber in accordance with a selected operational mode.
The foregoing and other objects of the present invention are also achieved by providing a method of controlling a refrigerator with a multipurpose storage chamber provided in the refrigerating compartment and a cool air supply device controlling the flow of cool air to the multipurpose storage chamber, comprising: determining an operational mode selected by a user; and selectively controlling the flow of cool air to the multipurpose storage chamber or the refrigerating compartment by an operation of the cool air control device in accordance with a selected operational mode, thus controlling the temperature of the multipurpose storage chamber.

Refrigerator with multipurpose storage chamber and control method thereof