A four-cycle, fuel lubricated, internal combustion engine system suited for a vehicle includes a fuel tank containing fuel at a remote location from the engine, a first fluid path for transporting fuel to the lubrication system of the engine, and a second fluid path for transporting fuel to said combustion system of the engine. In this way, the engine's fuel serves as the lubricant and the combustive agent.

In a conventional four-cycle internal combustion engine, the fuel and lubricating systems are maintained completely separate. Despite wide use, this division in the modern engine entails a number of shortcomings. For example, the oil is relied upon to not only reduce friction and wear, but also to serve as a coolant, an oxidation and corrosion inhibitor, and a transport fluid that removes wear metal particles and blow-by products (e.g., carbon, sludge, varnish, unburned fuel, and other combustion products) for subsequent filtration. Due to these requirements on the oil, the engine oil additives become depleted and the important characteristics of the lubricant are degraded. As a result, the oil over time will tend to experience an increase in viscosity and an accumulation of abrasive particles and oxides which, in turn, leads to the corrosion of engine components and increased wear. Moreover, replacement of the oil creates an added expense and a disposal problem with regard to the used oil. Finally, vehicles which are old or poorly maintained can experience considerable burning of the oil which leads to tailpipe emission problems.
A few engine systems have mixed oil and fuel together to facilitate oil replacement while the engine is in use. For instance, U.S. Pat. Nos. 5,431,138, 4,421,078, 4,869,346 and 4,495,909 disclose systems which pump a quantity of used oil into a fuel return line as the engine operates. Fresh oil in predetermined batches is also fed into the lubricating system to offset the oil which is removed. However, the maintenance of two fluid systems is still required. Moreover, as discussed above, the burning of oil creates undesirable pollution problems.
U.S. Pat. Nos. 4,572,120 and 4,615,305 to Matsumoto each discloses an outboard motor provided with a lubricant delivery tank mounted on the motor, and a storage tank which is mounted in the hull and fluidly coupled to the delivery tank. A pump feeds the lubricant in the delivery tank into the intake manifold of the motor. However, the outboard motor is a two-cycle engine, rather than a four-cycle engine. Moreover, this system requires the maintenance of separate oil and fuel systems and involves the burning of oil in the motor.
Other two-cycle, internal combustion engines have been produced which use an oil-fuel mixture for both lubrication and powering of the motor. However, these two-cycle engines are much different than modern four-cycle, internal combustion engines. For instance, these engines lack valves, rely upon oil-rich mixtures, and are very dirty engines which are not suitable for the high pollution standards now in existence for vehicles and other large engine applications.
Also, fuel lubrication is known to have advantages for an internal combustion engine, especially a diesel fuel engine. As a result, most diesel fuels have high lubricity, or contain lubrous additives, to ensure that the fuel injector pump and fuel injectors are adequately lubricated during normal operation. However, no four-cycle, internal combustion engine has been used in which the fuel serves as the lubricant for the engine.

Four-cycle fuel-lubricated internal combustion engine

Science Applications International Corp.


A method and system conduct built-in-self-test (BIST) in a circuit under test. After allocating at least one memory segment with a predetermined size in at least one memory module as a test result module, the built-in-self-test is conducted for the circuit under test without testing the test result module. The test results are stored in the test result module.

The present invention relates generally to memory tests, and more particularly to an improved Memory Built-In-Self-Test (MBIST) design or Logic Built-In-Self-Test (LBIST) design.
A memory chip is an integrated circuit (IC) made of millions of transistors and capacitors. There are a large variety of memory devices in the commercial world nowadays. There are types of memory known as ROM, PROM, EPROM, EEPROM and Flash memory. Each type having unique characteristics, but they all share store nonvolatile data. That is, it is not lost when power is removed. Data stored in these chips is either unchangeable or requires a special operation to change.
Random access memory (RAM) is another best known form of computer memory. RAM is considered "random access" because you can access any memory cell directly if you know the row and column that intersect at that cell. In the most common form of computer memory, dynamic random access memory (DRAM), a transistor and a capacitor are paired to create a memory cell, which represents a single bit of data. The capacitor holds the bit of information—a 0 or a 1. The transistor acts as a switch that lets the control circuitry on the memory chip read the capacitor or change its state. A capacitor is like a small bucket that is able to store electrons. To store a 1 in the memory cell, the bucket is filled with electrons. To store a 0, it is emptied. The problem with the capacitor's bucket is that it has a leak. In a matter of a few milliseconds a full bucket becomes empty. Therefore, for dynamic memory to work, either the CPU or the memory controller has to come along and recharge all of the capacitors holding a 1 before they discharge. To do this, the memory controller reads the memory and then writes it right back. This refresh operation happens automatically thousands of times per second.
Larger and more complex logic designs in integrated circuits (ICs) lead to demands for more sophisticated testing to ensure fault-free performance of those ICs. In a simple model, testing of an IC can include applying multiple test patterns to the inputs of a circuit and monitoring its outputs to detect the occurrence of faults. Fault coverage indicates the efficacy of the test patterns in detecting each fault in a universe of potential faults. Thus, if a set of test patterns is able to detect substantially every potential fault, then fault coverage approaching 100% has been achieved.
To facilitate better fault coverage and minimize test cost, automatic test pattern generation (ATPG) can be used to generate the minimum set of patterns while providing reasonable fault coverage. Specifically, in deterministic ATPG, each test pattern is designed to test for the maximum number of faults. Alternatively, and more frequently in current, complex ICs, structures can be added to the design that allow the IC to quickly test itself. These built-in self-test (BIST) structures can include various pattern generators, the most typical being a pseudorandom pattern generator. After the patterns generated are propagated through scan chains in the tested design, the outputs are analyzed to determine if a fault is detected. Memory Built-In-Self-Test (MBIST) refers to a system or method operative to generate patterns to test memories embedded in a computing system by itself.
The high level functional blocks in a memory device integrated with a MBIST system 100 are illustrated in FIGS. 1(a) and 1(b). The MBIST system 100 includes BIST module 102 that contains functional blocks such as address/data generators, one or more comparators 104, and a storage device 106 to save failure information, and one or more memory 108 under test. FIG. 1(a) shows a one-BIST-per-memory configuration, wherein each memory module 108 has a BIST module directly incorporated thereto. The BIST module 102 is responsible for generating suitable control, address, and input data to the memory module 108 under test based on predetermined test patterns. The memory under test will respond with suitable outputs in response to such stimulus. The comparator 104 compares the outputs from the memory with expected values. If the outputs do not match with the expected value, the fail code information is stored in the storage device such as a fail code storage module. The fail code information typically includes the test pattern number, pass number, X- and Y-addresses, and bit number.
FIG. 1(b) shows another configuration by using one BIST module 102 to test more than one memory modules. The operation of such a system is the same as the one in FIG. 1(a) except that the control, address, data inputs, and data outputs are passed from the memory module under test through one or more memory that is not under test if necessary to reach the BIST module 102 for testing. Those signals are normally arranged into one or multiple scan chains so that data can be shifted in and out more efficiently.
As the size of the memory device increases, the size of the fail code storage module may be huge. Especially when the defect density is high, memory capacity is large, or many memories are under test, the BIST module itself can be too expensive to be integrated.
As such, desirable in the art of memory designs are improved designs for a MBIST system.

Storage efficient memory system with integrated BIST function

Taiwan Semiconductor Manufacturing Co., Ltd.


Treatment and prophylaxis of endotoxin caused toxicity is disclosed. This is accomplished by administering a lipid into which the endotoxin of concern is associated, preferably together with a peptide which is not an apolipoprotein. Preferably, the two components are administered in the form of a reconstituted particle, although this is by no means required.

Normal serum contains a number of lipoprotein particles which are characterized according to their density, namely, chylomicrons, VLDL, LDL and HDL. They are composed of free and esterified cholesterol, triglycerides, phospholipids, several other minor lipid components, and protein. Low density lipoprotein (LDL) transports lipid soluble materials to the cells in the body, while high density lipoprotein (HDL) transports these materials to the liver for elimination. Normally, these lipoproteins are in balance, ensuring proper delivery and removal of lipid soluble materials. Abnormally low HDL can cause a number of diseased states as well as constitute a secondary complication in others.
Under normal conditions, a natural HDL particle is a solid with its surface covered by a phospholipid bilayer that encloses a hydrophobic core. Apolipoprotein A-I and A-II attach to the surface by interaction of the hydrophobic face of their alpha helical domains. In its nascent or newly secreted form the particle is disk-shaped and accepts free cholesterol into its bilayer. Cholesterol is esterified by the action of lecithin:cholesterol acyltransferase (LCAT) and is moved into the center of the disk. The movement of cholesterol ester to the center is the result of space limitations within the bilayer. The HDL particle "inflates" to a spheroidal particle as more and more cholesterol is esterified and moved to the center. Cholesterol ester and other water insoluble lipids which collect in the "inflated core" of the HDL are then cleared by the liver.
Jonas et al., Meth. Enzym. 128A: 553-582 (1986) have produced a wide variety of reconstituted particles resembling HDL. The technique involves the isolation and dilapidation of HDL by standard methods (Hatch et al., Adv. Lip. Res. 6: 1-68 (1968); Scanu et al., Anal. Biochem. 44: 576-588 (1971) to obtain apo-HDL proteins. The apoproteins are fractionated and reconstituted with phospholipid and with or without cholesterol using detergent dialysis.
Matz et al., J. Biol. Chem. 257(8): 4535-4540 (1982) describe a micelle of phosphatidylcholine, with apoliprotein A1. Various ratios of the two components are described, and it is suggested that the described method can be used to make other micelles. It is suggested as well to use the micelles as an enzyme substrate, or as a model for the HDL molecule. This paper does not, however discuss application of the micelles to cholesterol removal, nor does it give any suggestions as to diagnostic or therapeutic use.
Williams et al., Biochem. & Biophys. Acta 875: 183-194 (1986) teach phospholipid liposomes introduced to plasma which pick up apoproteins and cholesterol. Liposomes are disclosed, which pick up apoprotein in vivo, as well as cholesterol, and it is suggested that the uptake of cholesterol is enhanced in phospholipid liposomes which have interacted with, and picked up apoproteins.
Williams et al., Persp. Biol. & Med. 27(3): 417-431 1984) discuss lecithin liposomes as removing cholesterol. The paper summarizes earlier work showing that liposomes which contain apoproteins remove cholesterol form cells in vitro more effectively than liposomes which do not contain it. They do not discuss in vivo use of apoprotein containing liposomes or micelles, and counsel caution in any in vivo work with liposomes.
It is important to note that there is a clear and significant difference between the particles of the present invention, and the liposomes and micelles described in the prior art. The latter involve a bilayer structure of lipid-containing molecules, surrounding an internal space. The construction of liposomes and micelles precludes filling the internal space, however, and any molecular uptake is limited to the space defined between the two lipid layers. As a result, there is much less volume available for pick up and discharge of materials such as cholesterol and other lipid soluble materials than there is for the particles of this invention, which expand in a fashion similar to a balloon, with interior space filling with the material of choice.
Anantharamaiah, in Segrest et al., Meth. Enzymol. 128: 627-647 (1986) describe a series of peptides which form "helical wheels", as a result of the interaction of the amino acids in the peptide with each other. Such helical wheels present a nonpolar face, and a polar face in their configuration.
Endotoxic shock is a condition, often fatal, provoked by the outer membrane of most gram negative bacteria (e.g., Escherichia coli; Salmonella typhimurium). The structure of the bacterial outer membrane has been fairly well elucidated, and a unique molecule, referred to as lipid A, which is linked to acyl chains via lipid A molecule's glucosamine backbone. See Raetz, Ann. Rev. Biochem. 59: 129-170 (1990) in this regard.
The lipid A molecule serves as membrane anchor of a lipopolysaccharide structure ("LPS") and it is the LPS which is implicated in the development of endotoxic shock. It should be pointed out that LPS molecules are characterized by a lipid A type structure and a polysaccharide portion. This latter moiety may vary in molecular details in different LPS molecules, but it will retain the general structural motifs characteristic of endotoxins. It would be incorrect to say that the LPS molecule is the same from bacteria to bacteria (see Raetz, supra). It is common in the art to refer to the various LPS molecules as "endotoxins", and this term will be used hereafter to refer to LPS molecules collectively.
In U.S. Pat. No. 5,128,318 the disclosure of which is incorporated by reference, it was taught that reconstituted particles containing both an HDL associated apolipoprotein and a lipid capable of binding an endotoxin to inactivate it could be used as effective materials for alleviating endotoxin caused toxicity.
It has now been found that various other materials may be used to treat endotoxin caused toxicity. Specifically, it has been found that apolipoproteins are not required in reconstituted particles, and that the reconstituted particle may contain a peptide and a lipid as defined supra, wherein the peptide is not an apolipoprotein.
It has also been found that endotoxin caused toxicity may be treated via sequential administration of either an apolipoprotein or a peptide followed by a lipid as described supra. It appears that following sequential administration the components assemble as a reconstituted particle and then act to remove endotoxin.
It has also been found that at least some individuals possess native levels of apoliprotein which are higher than normal levels such that effective endotoxemia therapy may be effectuated by administering reconstituted particles containing no apolipoprotein or peptide, but containing the lipid described supra.
In addition, the invention involves the use of the reconstituted particles and the components discussed herein for prophylaxis against endotoxin caused toxicity, by administering prophylactically effective amounts to subjects in need of prophylaxis.
These and other aspects of the invention are described in the disclosure which follows.

Methods useful in endotoxin prophylaxis and therapy


A dental handpiece sterilizer includes a sterilization chamber with an internal manifold system having outlet connectors into which dental handpieces can be plugged. A sterilant vapor introduced to the manifold flows through the dental handpieces coupled to the manifold and into the interior of the chamber so that it contacts the exterior surfaces of the handpieces before exiting the sterilant chamber.

1. Field The present invention relates to the sterilization of dental handpieces and particularly to sterilization apparatus that provides for the sterilization of both the inside and outside surfaces of dental handpieces.
2. State of the Art
The need to sterilize dental equipment, particularly dental handpieces, between uses has long been recognized. An urgency to provide more effective sterilization procedures has developed with the increasing awareness of the communicable disease hazards confronting dentists and their patients. These hazards include hepatitis, which is extremely difficult to treat, and AIDS, for which there is presently no effective cure. The AIDS epidemic has made dentists very aware that they, and their patients, may be exposed to the HIV virus through contact with blood and other body fluids.
One of the shortcomings of sterilization processes and apparatus conventionally used in the dental field is that the sterilant often fails to penetrate into the openings and passageways of dental handpieces. Dental handpieces may have a single internal passage or they may have a plurality of such passages. They are generally constructed to receive plug-in utility lines. These lines are coupled to the passages during use of a handpiece, and decoupled from the lines and the handpiece following use. When a handpiece is turned off, a slight vacuum is characteristically created at its tip. This suction tends to pull contaminant fluids, such as saliva and/or blood, into the internal passages of the handpiece. The separated handpiece is then subjected to a sterilization procedure, usually in a hermetically sealed chamber.
Chemical vapors are presently the sterilants of choice, because they provide a less corrosive environment than steam, but these vapors cannot effect adequate sterilization unless brought into intimate contact with the contaminating organisms under attack. Penetration is essential to achieve this contact, but no suitable system for providing such contact of chemical vapors to the internal surfaces of dental handpieces has been available.
U.S. Pat. No. 4,752,444 discloses a method for sterilizing a dental handpiece. According to that patent, a pneumatic pump is used to force a liquid sterilant through the interior of the handpiece. Next, a supply of water is pumped through the handpiece to flush away any sterilant residue. Then a supply of oil is passed through the handpiece to lubricate its mechanical components, suck as a turbine assembly or bearings. At the same time the liquid sterilant is passed through the dental handpiece, the exterior of the handpiece is soaked in a bath of sterilant.
U.S. Pat. No. 4,410,492, discloses a method which comprises the circulation of a sterilant gas through a contaminated medical device to sterilize exposed surfaces. The sterilant gas remains within the lumen of the device for an effective period of time, and thereafter is removed by purging with sterile air or other inert gas. The apparatus disclosed includes a chamber having an access door through which materials to be sterilized are introduced and removed, a pump, and control valves. In practicing the methods, a contaminated object, such as an endoscope, is placed in the chamber and is coupled to a discharge outlet. A pump is connected to the discharge outlet, outside the chamber. The chamber is sealed. Atmosphere is pumped from the chamber. The chamber is heated. A sterilant gas (ethylene oxide vapor) is circulated and recirculated, using the pump and valves, through and around the object for a time sufficient to effect sterilization. The sterilant is pulled through an opening at one end of the object, through the object and out an opening in an end of the object at the coupling to the chamber. The sterilant gas is removed, and sterile air or other gas is admitted, circulated around and through the object and out of the chamber through the pump and control valves.
U.S. Pat. No. 4,810,469 discloses a method for sterilizing an artificial organ with high pressure steam in an autoclave. Sterilized high pressure liquid, maintained at a temperature sufficient for sterilization, is passed through the artificial organ to raise its inner temperature to approximately a sterilization temperature. The organ is simultaneously heated externally to a sterilizing temperature, and is maintained at that temperature for the time required to sterilize the organ. A low temperature sterilant is then passed through and around the organ to cool it.
None of the sterilization systems currently available fill the need for apparatus that can be conveniently used in a dental office to sterilize equipment that is needed on a repeat basis throughout a working day. Particularly, there remains a need for a system that can quickly, easily and effectively sterilize the dental handpieces used by dentists with successive patients. Ideally, such a system should be suitable for the delivery of chemical vapor sterilant.


A fence system for strengthening a vinyl fence which includes a plurality of fence posts having specified dimensions, and the posts have a hollow interior. A plurality of section panels include specified dimensions, and the section panels each including a slat portion. The section panels each include a fence railing coupled to a top and bottom of the slat portion. The fence railings each define a hollow interior, and the fence railings are coupled to the posts by a connecting portion of the fence railings passing through corresponding holes in the posts. A strengthening member for positioning in each of the hollow portions of the top and bottom fence railings. A plurality of post members for positioning within the hollow interior at the top of the fence posts. The post members being attachable to the connecting portion of the fence railing using a first attachment element.

Fences are commonly used to delineate borders between properties, such as between residential homes or lots, or commercial properties. Typical types and materials used for fencing may include vinyl, chain link, wood, or stone or brick.
Chain link fences have considerable strength but are considered by many to be aesthetically unattractive and may be easily damaged. Wood fences are considered by many to be more attractive than chain link. However, wood can quickly deteriorate from exposure to the weather, and consequently, wood fences are considered by many to be high maintenance. Vinyl fences, such as Polyvinyl Chloride (PVC), are preferred as requiring less maintenance than wood fences and more aesthetically pleasing than other types of fencing. However, vinyl fencing can be weak, especially regarding susceptibility to wind damage. Additionally, damaged vinyl fencing is not easily repaired or replaced, and often requires removal and replacement of fence posts to repair even a single slat.
It would therefore be desirable to provide a strengthened vinyl fence for longevity of the fence and being able to sustain wind challenges. It would further be desirable to provide a method and/or kit for strengthening existing vinyl fences, in one instance after construction of the fence. It would also be desirable to provide a method and/or kit for strengthening a fence, before construction, which is delivered in stock form, for strengthening the fence to sustain a specified wind velocity over a period of time.

System and fence kit for strengthening a fence


A memory architecture for image processing comprising a memory array having multiple multi-byte memory data paths of equal multi-byte data width, and a multiplexing structure connected to the output of the multiple multi-byte data paths, capable of selectively providing a multi-byte data path of a desired width containing a desired permutation of bytes chosen from one or more of the multiple data paths.

Image processing is an essential function of a vast majority of modern day devices, ranging from computing systems to consumer devices such as cell phones and Personal Digital Assistants (PDAs). The human interfaces for these devices are becoming increasingly graphical in nature in order to provide a more user friendly interface. These graphical user interfaces (GUIs) are also increasing in sophistication as greater computing power becomes available in these devices.
Conventional image processing systems typically require relatively large memory structures that store the images. The image processing activity involves the manipulation of this large amount of imaging data at very high speeds so as to enable real-time visualization of the images and the movement of those images. Typical operations include image translation and rotation. This high-speed manipulation of the image data is performed by signal processors, general purpose processors or special purpose image processors. These image processing engines access the image data in the memory through high-speed busses that connect them together.
Conventional memory systems are designed for meeting the needs of normal non-imaging data processing functions. As such, conventional memory systems are designed for normal sequential memory access. When such conventional memory systems are used for image processing, the image data (pixels) are packed to improve the memory utilization, for example, if memory data width is 64-bits then it will contain four 16-bit pixels or two 24-bit pixels and two bytes of the third pixel. The resulting performance is less than optimal as the typical frequently used functions of image translation or rotation very often require non-sequential memory access. Consequently, several memory accesses are required for each step of the image processing function resulting in inefficient and slow operation for a given clock speed.
Conventional systems attempt to improve the performance of a memory system that is used for image rotation by 90 degrees or a multiple of 90 degrees. For example, conventional system move image data from an initial position to a subsequent position involving rotation by 90 degrees or a multiple of 90 degrees with or without image translation. Typically, such systems focus on determining the optimum movement of the data regardless of the speed of accessing data from the memory without addresses the issues relating to the speed and efficiency of accessing the data from the memory, hence its effectiveness is limited by the memory access mechanism.
There is therefore a need for memory architectures for efficient image processing applications that involve image rotation by 90 degrees or a multiple of 90 degrees.

Memory structure for optimized image processing


A cushion system for use with a child safety seat has a plurality of bladders assembled to form a seat cushion that cooperates with the seat's safety harness. One or more sensors coupled to the safety harness sense tension therein and generate a signal indicative of the tension. Each of the bladders is individually pressurized by a pressurization system to define a support configuration of the seat cushion. The pressurization system is disabled when tension in the safety harness has attained a threshold level.

1. Field of the Invention
This invention relates to child safety seats. More specifically, the invention is adjustable cushion system for use with a child safety seat designed for a variety of uses.
2. Description of the Related Art
Over the years, the child safety seat has evolved from designs used exclusively in a vehicle to designs that provide for multiple uses. More specifically, today's child safety seats include a variety of mechanisms and/or attachments that allow the seat to be adapted for a variety of uses to include, for example, a car seat, a stroller, a high chair, a rocker, a bed, etc. In general, each adaptation changes the orientation of the seat to position the child sitting therein in one of a recumbent orientation, an upright orientation, or something in between. However, while seat orientations change, there is no mechanism to adjust the support provided by the seat as the conventional child safety seat comprises a foam-backed seat cushion fitted over a rigid frame.

Cushion system for multi-use child safety seat

United States of America as represented by the Administrator of the National Aeronautics and Space Administration


A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch, the input signals only carry crossbar switch data, and the connectivity is controlled by FPGA configuration data. The crossbar switch is implemented in two parts: a template of basic and constant routing to carry input signals through the switch array in one dimension and output signals from the array in another dimension, and a connectivity part controlled by a connectivity table or algorithm to generate partial reconfiguration bitstreams that determine which of the input signals is to be connected to which of the output signals.

The present invention relates to uses made of field programmable gate arrays (FPGAs), in particular to use of an FPGA to route information from selected input points to selected output points.
FPGAs are frequently used for telecommunication. An essential aspect of telecommunication is the ability to route information from any source to any desired destination. A crossbar switch accomplishes this purpose.
FIG. 1 shows a simple crossbar switch. Eight input lines IN0 through IN7 carry input signals and eight output lines OUT0 through OUT7 provide output signals. An array of connectors can be selectively turned on to provide any of the input signals as an output signal. For example, turning on connector C0,0 connects input line IN0 to output line OUT0. Turning on connector C0,7 connects input line IN0 to output line OUT7. It is important that an output line not be driven by more than one input signal so that no contention occurs, and for this reason, crossbar switches are often implemented as multiplexers.
FIG. 2 shows a multiplexer implementation of the crossbar switch of FIG. 1, in which multiplexer control signals select one and only one of the input signals to provide as an output signal. For example, multiplexer control signals A0 select which of the eight input signals IN0 through IN7 will be provided as output signal OUT0.
As the number of input and output signals increases, the size of the crossbar switch becomes larger in proportion to the product of the number of input and output signals. For example, an array accommodating 1000 input signals and 1000 output signals would require a million connectors. If implemented with multiplexers, the crossbar switch would require 1000 multiplexers, each with 1000 input signals. U.S. Pat. No. 6,288,568 to Bauer and Young entitled xe2x80x9cFPGA Architecture With Deep Look-Up Table RAMsxe2x80x9d describes an FPGA architecture having lookup tables that can generate a function of eight input signals.
FIG. 3 is a copy of FIG. 20 of the Bauer and Young patent and represents one configurable logic block (CLB) of to an FPGA. One possible function that can be generated by this flexible structure is a multiplexer. In FIG. 3, the lookup tables are 4-input lookup tables (LUTs), and thus each LUT can implement a 2-input multiplexer. The inputs applied on three of the lines F1, F2, F3, and F4 or G1, G2, G3, and G4 to each 4-input LUT are two multiplexer data inputs and one multiplexer control input. Eight lookup tables are present in the CLB of FIG. 3, each labeled LUT-F or LUT-G.
To form a conventional crossbar switch, the LUTs are each configured to implement a 2-input multiplexer with these three inputs. Sixteen data signals can be applied to these eight LUTs, two to each LUT. The lowest order multiplexer control bit C0 is applied to all eight LUTs and serves as the control bit for each of the eight 2:1 multiplexers. The next lowest order control bit C1 is applied to each of four multiplexers labeled F5, which receive outputs from pairs of the LUTs. Thus the outputs of the F5 multiplexers are 4:1 multiplexer outputs. Pairs of the F5 multiplexers feed F6 multiplexers as controlled by control bit C2, and pairs of the F6 multiplexers feed the F7 multiplexer as controlled by control bit C3. The F7 multiplexer thus provides the output of a 16:1 multiplexer. Another structure the same as FIG. 3 but receiving 16 different input signals receives the same control signals C0 through C3. The F8 multiplexer receives input signals from two F7 multiplexers and is controlled by a still higher order control bit C4 to produce a 32:1 multiplexer output signal. Thus an adjacent pair of CLBs can implement a 32:1 multiplexer.
Of course, providing these data and control signals requires routing through the FPGA. This routing has not been shown because it is easy to understand that the necessary route for each signal is formed by programmably connecting together the interconnect lines to get the data and control input signals from their origins and to get the output signals to their destinations.
Still wider multiplexer functions are formed by using another level of hierarchy. For example, a 1024:1 multiplexer can be formed in a very large FPGA by configuring 32 additional pairs of CLBs to each implement a 32:1 multiplexer, then finally forming a higher level structure, also from two CLBs, in which the input signals are the F8 output signals from the 32 pairs of CLBs. Thus the output of this final structure is the output of a 1024:1 multiplexer, and has consumed 64+2 CLBs or 66 CLBs. A square crossbar switch (1024 inputs and 1024 outputs) would require 1024 of these structures or a total of 67,584 CLBs.
One of the largest FPGA available from Xilinx Inc. today has on the order of 8,000 CLBs, so such a switch can not be implemented this way in such an FPGA but would require about 9 FPGAs.
It would be desirable to implement a large crossbar switch in an FPGA in a manner that is denser than this prior art implementation, preferably one that will fit into a single FPGA.
According to the invention, a switch such as a crossbar switch is implemented in an FPGA by using the FPGA""s configuration memory cells to control multiplexers that perform the routing of signals through the switch. Thus, the multiplexer control is established during configuration or reconfiguration of the FPGA and the multiplexer input data passes through the configuration multiplexers. This contrasts with the above described prior art implementation babe both the multiplexer input signals and the multiplexer control signals are applied to inputs pins of the FPGA after it has been configured. In one embodiment, the invention is implemented in an FPGA in which each CLB of the FPGA has several LUTs, for example eight 4-input LUTs, and an input multiplexer (IMUX) routes signals to each LUT. The IMUX receives control signals from the configuration memory cells. Rather than changing the switch configuration by changing control input signals, the switch configuration is changed by reconfiguring one or several IMUXs of the FPGA.
As an optional feature of the invention, an input signal applied to a single pin is deserialized and applied to several different internal input lines. In one embodiment, each input signal on one input pin is applied to four different input lines. Likewise, four output signals are serialized and placed onto a single output pin. For an FPGA with a given number of pins, this increases the amount of logic the FPGA can process. An FPGA having on the order of 250 input pins and 250 output pins (or 500 I/O pins) can implement a 1000xc3x971000 crossbar switch by making use of a 4:1 serializer/deserializer (SERDES) feature. If each input and output signal is applied to two pins as a low voltage differential signal (LVDS), and a 4:1 SERDES is used, 1000 physical pins are required for a 1000xc3x971000 crossbar switch.
Of course, consideration must be made for how the user changes or partly changes the configuration in order to reconfigure the IMUXs. Changing control signals in the IMUX is slower than simply applying a new multiplexer control signal to a LUT, as described above for a prior art crossbar switch implementation. However, in some applications this is acceptable because data needs to flow at high speed, but its destination changes only occasionally. Some FPGAs are reconfigured by shifting data into a configuration frame register in the FPGA and loading the frame register data into the designated frame. It may be necessary to load a full frame of data during a partial reconfiguration. In Virtex-II FPGAs available from Xilinx, Inc., this is true. An IMUX can be reconfigured by loading four frames of data. Typically, the user will want to disconnect one input terminal from an output terminal and connect another input terminal to the output terminal. This operation requires loading no more than six frames of configuration data and takes about 140 microseconds. This reconfiguration rate is fast enough for some communications applications. Importantly, the connectivity of the crossbar switch can be changed with a small amount of reconfiguration.
A benefit of the invention is that it is an order of magnitude more dense than the prior art method. For example, in a Virtex-II FPGA, a single CLB can implement eight 144:1 multiplexers, one in each LUT and associated IMUX. Making use of all these inputs may be impractical due to limitations in routing available in the Virtex-II FPGA. In one embodiment, eight 33:1 multiplexers are implemented in one CLB. That compares to the prior art method in which two CLBs can implement one 32:1 multiplexer. This is more than a 16:1 improvement in density. Of course other embodiments will differ in the details of the FPGA architecture, and thus in the relative improvement.
In communications use, FPGAS implementing crossbar switches are reconfigured to change which input is connected to which output, but most of the configuration is retained. In one embodiment, to change the connectivity, the lookup tables and routing are not reconfigured, and only the IMUXs are reconfigured. A table of configuration values may be stored in a computer that configures the FPGA, one set of bits to be turned on for each input-to-output connection, and used to set up the configuration bitstream for a partial reconfiguration due to changing connectivity of the crossbar switch. An algorithm for generating the bits may also be used. By taking advantage of the regularity and the fact that the CLBs are identical, the algorithm would simply generate bitstream instructions based on the desired location with a CLB.
In yet another optional feature of the invention, a pipelining structure can be included in the FPGA such that input signals routed on long horizontal or vertical paths are captured and retransmitted periodically. If it is necessary that all signal paths experience the same latency, shift registers can be implemented to delay signals on fast paths so that all signal paths experience the same latency.
It is typically desired to implement a crossbar switch as a static structure, but to change the connectivity every time there is a change in the use of the switch. It is desirable to make a change in connectivity without disruption of any other connections that the switch is currently providing. A Virtex-II FPGA can be partially reconfigured by changing a few frames of configuration data. Ongoing communication can continue on all paths except the ones being reconfigured. Those IMUXs that stay the same in the reconfigured column are unaffected and can continue to pass data.

Large crossbar switch implemented in FPGA


A digital to analog converter circuit is segmented into a main digital to analog converting unit including a plurality of current sources and a plurality of cascode units, each current source being connected to a cascode unit and a sub-digital to analog converting unit including a current source connected to a plurality of cascode units. A cascode bias unit is operatively connected to each cascode unit of the main digital to analog converting unit so as to bias each current source of the main digital to analog converting unit to operate at a same drain voltage. A second cascode bias unit is operatively connected to each cascode unit of the sub-digital to analog converting unit so as to bias the current source of the sub-digital to analog converting unit to operate at a same drain voltage. A reference voltage source is operatively connected to an input of the first cascode bias unit and connected to an input of the second cascode bias unit. The tying of the reference voltage source to both cascode bias circuits causes the operating emitter/source to collector/drain voltage of each current source transistor of the main digital to analog converting unit to be equal to the operating emitter/source to collector/drain voltage of the current source transistor of the sub-digital to analog converting unit.

The present invention is directed to a digital to analog converter (xe2x80x9cDACxe2x80x9d) that includes a main section of the DAC to convert a most significant bit portion of the digital input and a sub-DAC to convert a least significant bit portion of the digital input. More particularly, the present invention is directed to a digital to analog converter (xe2x80x9cDACxe2x80x9d) that includes a main section of the DAC to convert a most significant bit portion of the digital input and a sub-DAC to convert a least significant bit portion of the digital input wherein a gain of the sub-DAC matches and tracks the gain of the main section of the DAC.
Multicarrier radio architectures have conventionally used a single lower resolution digital to analog converter (xe2x80x9cDACxe2x80x9d) per carrier at a low baseband frequency followed by an analog channel combine and mix to an intermediate frequency (xe2x80x9cIFxe2x80x9d) and then to a radio frequency (xe2x80x9cRFxe2x80x9d). FIG. 1 illustrates a simple block diagram showing a conventional transmit architecture.
As illustrated in FIG. 1, a plurality of DACs 1, each corresponding to a separate carrier, receives digital data and converts the received signal into analog signals. The analog signals are combined in combiner 2 prior to being mixed with an intermediate frequency by intermediate frequency mixer 3. Thereafter, the mixed signal is further mixed with a radio frequency by a radio frequency mixer 4. It would be desirable to use a single higher resolution digital to analog converter in this application. However, there have been limits to achieving the necessary resolution. It is the aim of the present invention to address one such limit.
FIG. 2 illustrates an example of a conventional digital to analog converter 10 (xe2x80x9cDAC 10xe2x80x9d) used in the low resolution DACs of FIG. 1. The DAC 10 includes a plurality of unit cells 12, 12l . . . 12n. Each cell, illustrated with respect to cell 12, includes a current source 14, a trim circuit 16, a calibration switch 18, and a current output switch 20. All of the output switches provide their analog outputs on the analog output network 22 where the analog outputs are summed.
Each calibration switch 18 connects a current source 14 either over line 24 to the associated output switch 20 or over line 26 to a calibration reference circuit 28. Calibration reference circuit 28 communicates over line 30 with each of the trim circuits 16 communicating to each of them the amount of current that must be added or subtracted to the output current on line 32 from current source 14 to ensure that the output current from each of the current sources 14 in each of the cells 12, 12l, . . . 12n, are equal.
A control signal on line 34 sets calibration switch 18 either to the load mode where it connects current source 14 over line 24 to output switch 20 or over line 26 to calibration reference circuit 28 in the calibration mode. Each output switch 20 in addition to providing its output current on line 38 to analog output network 22 receives at its input data on lines 40 and 42.
FIG. 3 provides a more detail schematic of the digital to analog converter of FIG. 2. As illustrated in FIG. 3, an analog reference signal is fed to a plurality of current source transistors (M1, M2, . . . , M3, M4). Each current source transistor (M1, M2, . . . , M3, M4) is connected to current source bias circuit 15. As illustrated in FIG. 3, the digital signal is segmented between a most significant bit (xe2x80x9cMSBxe2x80x9d) section and a least significant bit (xe2x80x9cLSBxe2x80x9d) section, wherein the LSB section is a sub-DAC.
To implement this segmentation, the output of each current source transistor associated with the MSB section (in FIG. 3, these current source transistors are M1, M2, . . . , M3) is connected to a digital to analog converter output switch (20a, 20b, . . . , 20c). More specifically, the output of each current source transistor associated with the MSB section is connected to an isolation cascode transistor (M5, M6, . . . , M7) within the respective digital to analog converter output switches (20a, 20b, . . . , 20c).
Moreover, the output of the current source transistor associated with the LSB section (in FIG. 3, this current source transistor is M4) is connected to a plurality of digital to analog converter output switches (20d, 20e, . . . , 20f). More specifically, the output of the current source transistor associated with the LSB section is connected to a plurality of isolation cascode transistors (M8, M9, . . . , M10) within the respective digital to analog converter output switches (20d, 20e, . . . , 20f).
Each isolation cascode transistor (MS, M6, . . . , M7, M8, M9, . . . , M10) is connected to cascode bias circuit 104. Moreover, each output switch (20a, 20b, . . . , 20c, 20d, 20e, . . . , 20f) in addition to providing output current on lines 38 to analog output network 22 receives at its input data on lines (40a, 42a, 40b, 42b, 40c, 42c, 40d, 42d, 40e, 42e, 40f, and 42f).
The approach illustrated in FIG. 1 has been conventionally utilized in view of the DAC""s intermodulation distortion (xe2x80x9cIMDxe2x80x9d) limiting the dynamic range of the DAC. However, as carriers are added, the peak power remains the same, but the average power reduces by 10-log (# of carriers). Moreover, as carriers are added, spectral emissions of the composite-multicarrier output must still be maintained on a per carrier basis, requiring a larger dynamic range from the DAC and thus the need for higher resolution. Furthermore, where large peak to average ratios are used it is possible, in some modulation schemes, for the absolute noise power spectral density (xe2x80x9cNSDxe2x80x9d) of the DAC to limit the dynamic range of the DAC.
Therefore, it is desirable to provide a digital to analog converter that does not experience limitations to its dynamic range as carriers are added. In other words, it is desirable to provide a DAC wherein the DAC has IMD and NSD sufficient to meet multicarrier demands.
A first aspect of the present invention is a digital to analog converter circuit. The digital to analog converter circuit includes a main digital to analog converting unit including a plurality of current sources and a plurality of cascode units, each current source being connected to a cascode unit; a sub-digital to analog converting unit including a current source connected to a plurality of cascode units; a first cascode bias unit, operatively connected to each cascode unit of the main digital to analog converting unit, to bias each current source of the main digital to analog converting unit to operate at a same drain voltage, a second cascode bias unit, operatively connected to each cascode unit of the sub-digital to analog converting unit, to bias the current source of the sub-digital to analog converting unit to operate at a same drain voltage; and a reference voltage source, operatively connected to an input of the first cascode bias unit and connected to an input of the second cascode bias unit, to cause the operating emitter/source to collector/drain voltage of each current source of the main digital to analog converting unit to be equal to the operating emitter/source to collector/drain voltage of the current source of the sub-digital to analog converting unit.
A second aspect of the present invention is a digital to analog converter circuit. The digital to analog converter circuit includes a main digital to analog converting unit including a plurality of current source transistors and a plurality of cascode transistors, each current source transistor being connected to a cascode transistor; a sub-digital to analog converting unit including a current source transistor connected to a plurality of cascode transistors; a first cascode bias unit, operatively connected to a control terminal of each cascode transistor of the main digital to analog converting unit, to bias each current source of the main digital to analog converting unit to operate at a same drain voltage; a second cascode bias unit, operatively connected to a control terminal of each cascode transistor of the sub-digital to analog converting unit, to bias the current source transistor of the sub-digital to analog converting unit to operate at a same source to drain voltage; and a reference voltage source, operatively connected to an input of the first cascode bias unit and connected to an input of the second cascode bias unit, to cause the operating emitter/source to collector/drain voltage of each current source transistor of the main digital to analog converting unit to be equal to the operating emitter/source to collector/drain voltage of the current source transistor of the sub-digital to analog converting unit.

Digital/analog converter including gain control for a sub-digital/analog converter


An adjustable incubator/crib infant positioning blanket for holding a premature baby securely in an incubator. The blanket includes a pouch to securely hold the baby with its head in an upright position on an inclined plane such as a raised mattress and the blanket is secured to the mattress by a strap. The pouch securely prevents the baby from rolling or sliding toward the bottom of the inclined mattress.

New born and premature babies are often wrapped in a blanket or the covering in order to keep the enfant warm while sleeping.
Premature babies are often put on a mattress in an incubator which has the upper end elevated to hold the baby in a position where the baby's head is higher than the rest of the body. Unless otherwise restrained, the newborn babies roll down the incline or eventually wind up at the bottom due to squirming and the like, defeating the purpose of inclining the mattress to hold up the head. There are several types of blanket devices which are secured to a mattress in order to attach a sheet or blanket of a crib mattress and/or bumper pad to limit movement of the infant while sleeping. Some infants frequently change positions while sleeping so it is desirable to secure the baby in a desired sleeping position. Moreover, the risk of infant death due to Sudden infant Death Syndrome, "SIDS", is though to be reduced by placing babies on their backs to sleep.
Moreover, it is recommended to remove soft bedding from the baby's sleep area, keeping the baby's head and face uncovered during sleep and keeping blankets and other coverings away from a baby's mouth and nose by tucking the blanket in around the bottom of the crib mattress. However, merely tucking bedding around a crib mattress is not always sufficient to secure the bedding in view of the movement of active babies that kick and move around in bed.
Several devices have been utilized to secure the blanket to the mattress and hold the infant in a selected position upon the mattress.
U.S. Pat. No. 7,337,481 B2 by Gilbert for APPARATUS FOR SECURING BEDDING which issued on Mar. 4, 2008 teaches bedding including a pouch formed by two U-shaped semi-rigid members held together by magnets. The lower U-shaped member is secured to a blanket and the upper U-shaped member is attached to blanket portion which stretches across and covers the upper U-shaped member. The U-shaped members are removably held together by a plurality of magnets. The blanket and lower U-shaped member are secured to the mattress with two C-shaped frame members which are hooked around each side of the mattress. The inclusion of rigid U-shaped members and magnets and C-shaped hook members pose the problems of unnecessary bulk and problems associated with laundering and care of the bedding articles and storage of same.
U.S. Pat. No. 6,681,422 B2 for CRIB SAFETY SHEET/BLANKET by Landry which issued on Jan. 27, 2004 teaches a blanket portion sewn to the top central portion of a fitted sheet. The blanket is sewn down a centerline of the blanket portion, leaving the two halves of the blanket portion on either side of the stitching free to wrap around a baby. The blanket is fitted with hook and loop fasteners to secure the blanket around the baby. The fitted sheet is also secured around the mattress by a plurality of straps with hook and loop fasteners. If the Landry device was used on an inclined mattress, the baby could be left dangling from the stitched portion of the blanket and would be free to tip from side to side about the centrally stitched seam.
U.S. Pat. No. 7,603,732 B2 by Robles et al. for SLEEPING INFANT POSITIONING DEVICE which issued on Oct. 20, 2009 teaches bedding which is secured by straps which circumscribe the mattress. The bedding includes a waist panel secured to a bedding panel. The waist panel includes a belt securing an upper opening and two lower openings through which the baby's legs are passed while the upper opening contains the baby's lower abdomen. Robles includes several straps for holding the bedding to the mattress and for holding the baby within the waist panel requiring unnecessary time to secure the blanket to the mattress with conventional means. Further, Robles leaves the baby's legs exposed and unrestrained.
U.S. Patent Application Publication No. 20080307577 by Leckband for BABY CRIB SAFETY BLANKET published on Dec. 18, 2008 teaches a blanket including a pouch located in the middle of an extended length of blanket material. The extra blanket material on both sides of the pouch is rolled into a coils to help restrict movement of the baby within the bed such as rolling over. Leckband's blanket is not intended to be strapped to or otherwise connected to the mattress, and is therefore not secure on an inclined mattress.

Incubato/crib infant positioning blanket


The present provides a cryogenic thermal battery arrangement for maintaining a superconducting magnet coil or similar apparatus at cryogenic temperature for a required shipping period, such as thirty days, without consuming a significant amount of costly cryogen. According to another aspect, the invention allows extended shipping periods without incurring excessive costs.

Superconducting magnets are well known and used for producing very high strength magnetic fields in applications such as magnetic resonance imaging. The superconducting magnet is typically made up of a number of coils of superconducting wire which, in use, must be held at cryogenic temperatures typically of the order of 4K, the boiling point of liquid helium. Alternatively, systems using so-called high temperature superconductors are known. These may operate at the temperature of boiling neon, hydrogen or nitrogen. Critical temperatures in the region of 18-80K are typical for such materials. While the present invention will be described with particular reference to systems operating at about 4K, which are cooled by boiling helium, the present invention may be applied to high temperature superconducting arrangements.
A typical arrangement has superconducting coils immersed in a bath of liquid cryogen, for example helium. The liquid cryogen is allowed to boil, and maintains the coils at a steady temperature of its boiling point, about 4K in the case of helium. A recondensing refrigerator is provided, and provides cooling by recondensing the boiled-off cryogen vapour back into a liquid. Thus, the overall consumption of liquid cryogen is reduced to a low value, since most if not all of the boiled off cryogen is recondensed back into liquid form within the cryogen vessel. Cryogens other than helium may of course be used, depending on the cryogenic temperature required.
FIG. 1 shows a cross-section of a former 10 and superconducting coils 12 mounted thereon, typical of a solenoidal superconducting magnet for MRI or NMR imaging systems. The former 10 and coils 12 are housed within a cryogen vessel 14. The cryogen vessel 14 is typically partially filled with a liquid cryogen, not shown in the drawing. The cryogen vessel itself is housed within an outer vacuum chamber 16, and the space between the cryogen vessel 14 and the outer vacuum chamber 16 is evacuated. A thermal shield 18 is typically also provided, in the evacuated space between the cryogen vessel and the outer vacuum container. This shield reduces the incidence of radiated heat from the outer vacuum chamber which may reach the cryogen vessel. A service neck 20 is typically included. In operation, this neck may house a recondensing refrigerator.
A difficulty arises when the system is in transit, awaiting installation. Typically, the system is transported filled with liquid cryogen, but the recondensing refrigerator is unable to operate due to the absence of a suitable power source, or due to regulatory restrictions. During the transit time, the cryogen is allowed to boil, keeping the coils 12 at the required cryogenic temperature. The cryogen thus acts as a thermal battery. Service neck 20 provides an escape path for boiled off cryogen to leave the cryogen vessel 14. The boiled off cryogen is allowed to vent to atmosphere. The system may be required to be capable of remaining in this boiling thermal battery state for a duration of up to about 30 days. When a cryogen such as helium or neon is used, the cost of the cryogen lost by boiling may become significant. When hydrogen is used a cryogen, an explosion risk may result.
It is required to keep the coils at a cryogenic temperature, since otherwise the commissioning of the system on installation becomes expensive, difficult and time consuming. If the system has heated up to ambient temperature, which will happen if the liquid cryogen boils dry, the system must be cooled and refilled with the relatively costly liquid cryogen before being commissioned. In some regions of the world, it is very difficult to obtain the large supplies of the liquid cryogen required for such an operation if not planned for in advance. Such a re-cooling and refilling is also time consuming, and costly both in terms of the time a field engineer must spend on site installing the system, and the material cost of the cryogen used.
In magnet systems such as that illustrated in FIG. 1, the volume of the cryogen tank 14 is largely defined by the minimum allowable shipping time. To allow a shipping time with the recondenser inoperable of, say, thirty days, a large volume of liquid cryogen must be accommodated in the system to ensure that it does not run dry during transit. The volume of this required cryogen reservoir plays a large part in determining the final size of the whole system.

Method and apparatus for maintaining apparatus at cryogenic temperatures over an extended period without active refrigeration


A portable semiconductor memory device includes an internal memory for storing data, an address bus, a control bus, and a data bus which are connected to the internal memory, a connector for electrically connecting the address bus, the control bus, and the data bus to terminal equipment, and a contact confirmation/control circuit which is connected to the address bus, the control bus, and the data bus and in which known data is previously stored and which outputs the known data to the data bus when a read control signal is input from the terminal equipment over the control bus and when a given address is specified on the address bus to indicate the proper connection of the memory device to the terminal equipment through the connector.

1. Field of the Invention
The present invention relates to a portable semiconductor memory device and particularly, to a memory device which allows access to an internal memory when connected to terminal equipment through a connector.
2. Description of the Related Art
FIG. 7 shows the configuration of a circuit of a conventional portable semiconductor memory device. The memory, device has as an internal memory a static RAM 1, to which a battery 4 is connected through an internal power line 8 for supplying a voltage, a reverse charge preventing diode 6 and a current limiting resistor 5. A power input line 7 is connected to the internal power line 8 through a power control circuit 3 and to a connector 35. A buffer circuit 2 is connected to the internal power line 8, RAM 1, and the connector 35. The buffer circuit is connected to the connector 35 by an address bus 10, a control bus 11 and a data bus 12. The power control circuit 3 and the buffer circuit 2 are connected to each other by a control line 9. In the drawing, reference numeral 33 denotes a pull-up resistor connected between the internal power line 8 and the control bus 11.
When the memory device having the above-mentioned configuration is used, it is mounted on terminal equipment (not shown) through the connector 35. If a voltage greater than a defined value is applied to the power input line 7, the power control circuit 3 connects the power input line 7 and the internal power line 8 and sends a high level control signal to the buffer circuit 2 over the control line 9. This operation causes the voltage to be supplied to the RAM 1 and the buffer circuit 2 over the internal power line 8. The high level control signal brings the buffer circuit 2 into an enable (operable) state. In other words, the terminal equipment can get access to the RAM 1, i.e, reading from or writing in the RAM 1, over the address bus 10, the control bus 11 and the data bus 12. During this operation, since the potential of the internal power line 8 is set to a value higher than the potential of the positive side of the battery 4, the current of the battery 4 is not consumed.
When access to the RAM 1 is completed, and when a given power voltage is not applied to the input line 7, the power control circuit 3 detects that the voltage of the power input line 7 is less than the defined value and disconnects the power input line 7 from the internal power line 8 and sends a low level control signal to the buffer circuit 2 over the control line 9. The control signal brings the buffer circuit 2 into a disable (non-operating) state wherein any access to the RAM 1 is prohibited.
In this state, although no voltage is supplied to the RAM 1 through the power input line 7, the voltage of the battery 4 is supplied through the resistor 5 and the diode 6. Even if the memory device is removed from the terminal equipment, therefore, the data stored in the RAM 1 is not erased or lost but in the memory device.
However, since the connection between the memory device and the terminal equipment is effected through the connector 35 having many contact points, when foreign substances adhere to the contact points, when a contact point is deformed or broken or when the memory device is attached to the terminal equipment at an angle, in some cases unstable or poor contacts or contact errors occur. If writing to or reading from a given address area of the memory device is performed from the terminal equipment in these circumstances, there is danger of a malfunction. In particular, there is a danger of erasing the valuable data stored in the RAM 1. It is impossible to perfectly connect the connector 35 to accurately combine the memory device with the terminal equipment.


A method and system for rejecting interfering signals in a wireless communication system employing antenna diversity. According to the method, the angle between an interfering signal and a desired carrier signal is determined and used to estimate an offset angle. The offset angle is incrementally adjusted such that, when added to the received signal, the carrier-to-interference (C/I) ratio of the received signal is substantially maximized.

Mobile communication systems have experienced explosive growth, as an ever- increasing number of subscribers demand mobile communication services. To meet this demand, increased system capacity is necessary, and can be achieved in many ways. One way is to reduce the "cell" size (that is, the coverage area of an individual base station). However, this approach also results in frequencies being reused within a smaller area, thereby increasing interference and decreasing speech quality. While factors such as fading and noise can also reduce speech quality, interference is typically the dominating form of disturbance; therefore, methods to reduce the effects of interference are highly desirable to improve speech quality.
Interference typically manifests itself as discordant noise, and can be difficult to remove. There are generally two types of interference: co-channel interference and adjacent channel interference. Co-channel interference (interference between two or more channels which are assigned to the same frequency, as mentioned above) is typically the dominant type, and varies with frequency reuse distance. Adjacent channel interference is generally controlled more easily, as it can be reduced to an acceptable level through appropriate filtering of the received signal.
To improve speech quality, many conventional systems employ diversity schemes, in which communication signals are received at two or more input branches. The branches are combined according to one of a variety of diversity combining techniques. One known diversity algorithm uses equal-gain combining to reduce interference. Equal-gain combining is a co-phase combining technique in which a combined signal is generated as the sum of the instantaneous phase envelopes of the individual branches. While relatively simple, this technique does not adequately reduce the effects of co-channel interference.
It would be desirable to reduce the effects of co-channel interference in a communication system, particularly in a system employing antenna diversity.

Method and system for rejecting interfering signals


The present invention relates to a method for repairing components such as blades used in turbine engines. The method comprises the steps of placing a piece of refractory metal material over an area of the component to be repaired and depositing a repair filler metal material over the piece of refractory material in an amount sufficient to repair the component and welding the repair filler metal material in place. The refractory metal material may be selected from the group consisting of niobium, tantalum, molybdenum, tungsten, a metal having a melting point higher than the melting point of nickel, and alloys thereof and may be uncoated or coated.

The present invention relates to a method for repairing a component, such as a turbine blade or a vane, used in a gas turbine engine.
Currently, gas turbine blade tips and trailing edge regions are repaired using a welding process such as gas tungsten arc welding without a backing material. The weld bead is used to build up cracked and worn surfaces. Problems occur when blade tip cracks expose blade internal cavities. In this case, the weld will flow into the cavity and result in a rejectable condition. In other areas, such as a blade trailing edge, weld repair will result in closure of the internal cooling features that will then need to be re-established by labor intensive blending or electrodischarge machining.
Accordingly, it is an object of the present invention to provide an improved method for repairing turbine engine components.
It is a further object of the present invention to provide a method as above which allows welding over open cavities and which does not require extensive post welding blend processing or machining.
It is yet another object of the present invention to provide a method as above which allows re-establishment of internal cooling geometry.
The foregoing objects are attained by the method of the present invention.
In accordance with the present invention, a method for repairing a component used in a turbine engine broadly comprises the steps of placing a piece of refractory metal material over an area of the component to be repaired and depositing a repair filler metal material over the piece of refractory metal material in an amount sufficient to repair the component and welding same. The refractory metal material may be any refractory material having a melting point in excess of 1455xc2x0 C. (2651xc2x0 F.) and may be coated or uncoated.
Other details of the repair method of the present invention, as well as other objects and advantages attendant thereto, are set forth in the following detailed description and the accompanying drawings wherein like reference numerals depict like elements.

Refractory metal backing material for weld repair


The present invention is directed to a semiconductor memory device including a plurality of first level contacts arranged in an array with every third row vacant along a first direction, thereby forming multiple contact regions separated by multiple vacant regions along the first direction with each of the multiple contact regions including a first row and a second row of the first level contacts extending along a second direction; a first and second plurality of second level contacts formed on top of the first level contacts with the second plurality of second level contacts having elongated shape extending into the vacant regions adjacent thereto; and a first and second plurality of memory elements formed on top of the first and second plurality of second level contacts, respectively, thereby permitting the memory elements to have greater center-to-center distance between two closest neighbors than the first level contacts.

The present invention relates to a semiconductor memory device, and more particularly, to example embodiments of a memory cell structure that can maximize the separation spacing between closest adjacent memory elements for a given memory cell size.
A semiconductor memory device normally comprises an array of memory cells, each of which includes a memory element and a selection transistor coupled in series between two electrodes. The selection transistor functions like a switch to direct current or voltage through the selected memory element coupled thereto. Upon application of an appropriate voltage or current to the memory element, the electrical property of the memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
A semiconductor memory device may be either volatile or non-volatile, depending on the type of memory element and the memory architecture employed. An example of volatile memory device is dynamic random access memory (DRAM), which loses its stored information when power is interrupted or lost. Non-volatile memory device, such as magnetic random access memory (MRAM) or other types of resistance-based memory devices, can retain stored information when powered off.
A resistance-based memory element can be classified into at least one of several known groups based on its resistance switching mechanism. The memory element of Phase Change Random Access Memory (PCRAM) may comprise a phase change chalcogenide compound, which can switch between a resistive amorphous phase and a conductive crystalline phase. The memory element of Conductive Bridging Random Access Memory (CBRAM) relies on the statistical bridging of metal rich precipitates therein for its switching mechanism. The memory element of CBRAM normally comprises a nominally insulating metal oxide material, which can switch to a lower electrical resistance state as the metal rich precipitates grow and link to form conductive paths upon application of an appropriate voltage. The memory element of Magnetic Random Access Memory (MRAM) typically comprises at least two layers of ferromagnetic materials with an insulating tunnel junction layer interposed therebetween. When a switching current is applied to the memory element of a MRAM device, one of the ferromagnetic layers will switch its magnetization direction with respect to that of the other magnetic layer, thereby changing the electrical resistance of the element.
To be cost competitive, a small memory cell size is desired in order to increase device density on wafers. One way to achieve this is to simply shrink the minimum feature size, F, normally associated with a particular manufacturing process. In memory applications where memory cells are arranged in dense and repetitive patterns, photolithography is more constrained by the pitch of the feature pattern rather than the feature size itself. This is because the feature size can be modulated by photo lithography process conditions, such as exposure and resist development, but shrinkage of the feature pitch would require shorter wavelength light source and/or significant improvement in optics. In reality, the scaling of the device size in a dense array, such as that in memory applications, is limited by the minimum feature pitch of 2F. Moreover, it is normally assumed that the minimum feature size is half of the corresponding minimum pitch. Accordingly, the minimum pitch between two repetitive features on a same mask layer would be 2F, as would be understood by one of ordinary skill in the art.
Another approach to reduce the memory cell size is to use a compact cell structure. Recent advances in semiconductor processing, such as implementation of buried gate and oblique active region, have reduced the memory cell size of DRAM to 6F2. For example, FIG. 1 is a top view that illustrates the arrangement of an array of 6F2 memory cells for a memory device as disclosed by Baek et al. in U.S. Pat. No. 8,084,801. The memory device includes a semiconductor substrate 50 and a plurality of active regions 52 formed therein. The active regions 52 have an elongated shape extending along the x-direction and are arranged in a staggered pattern along the x-direction. Each active region 52 has two source contacts 54 formed on top of the end portions thereof and a bit contact 56 disposed on the central portion thereof. For reasons of clarity, word lines in the form of buried gate and bit lines are not shown herein. Each source contact 54 has a memory element (not shown) formed thereon. In the cell layout shown in FIG. 1, each memory cell, which includes a transistor and a memory element, has a cell size of 6F2 if the center-to-center spacing between two closest neighbors of the source contacts 54 is 2F. Assuming the source contacts 54 have a diameter of about 1F, then the gap between two closest neighbors is about 1F. The memory elements, which are formed on top of the source contacts 54, are subjected to the same geometric constraint with the center-to-center spacing between two closest neighbors being 2F. For 6F2 memory cell design, such as the one shown in FIG. 1, it is desirable to increase the minimum spacing between two adjacent memory elements to increase the gap therebetween for easing processing constraints or to increase the memory size for improving memory performance or both.
For the foregoing reasons, there is a need for a 6F2 memory device that has a center-to-center spacing between adjacent memory elements greater than 2F and that can be inexpensively manufactured.

Semiconductor memory device having increased separation between memory elements


A safety switch includes a housing including first and second compartments that are separated by a barrier, a switch mechanism in the first compartment, one or more fuse holders in the second compartment, a first door connected to the housing and covering the first compartment, a second door connected to the housing, a handle connected to the switch mechanism, and a locking mechanism operatively connected to the handle. The handle is movable between an off position and an on position. The locking mechanism configured such that: the second door is locked in a closed position when the handle is in the on position; the second door is movable from the closed position to an open position to expose the second compartment when the handle is in the off position; and the handle is locked in the off position when the second door is in the open position.

Safety switches are used in electrical power distribution systems to electrically isolate a load or a portion of a power circuit.
Purchasers and installers of electrical equipment are increasingly interested in the safety of those using the equipment. Standards have been introduced in an effort to reduce the exposure of individuals to live power over 48 Vac.
Safety switches typically include fuses behind a door. When a fuse clears (opens), the fuse must be replaced. The door of the safety switch must be opened to replace the fuse. The door of the safety switch may be interlocked such that the switch must be in the "OFF" position in order to open the door. However, the line side of the switch may not be disconnected from live voltage. Therefore, the individual replacing the fuse(s) may be exposed to live power which may be over 120 Vac.

Safety switch having interlocking handle and door


A columnar spacer is interposed between a first substrate and a second substrate for holding a liquid crystal layer between them. The columnar spacer is formed in such a manner as to have an area superposed, in each pixel, with the contact hole formed in the first substrate and an area not superposed with said contact hole. Even in the case where the first and second substrates attached to each other are displaced from each other, the columnar spacer never falls in the contact hole and a desired cell gap can be positively secured. Also, since the columnar spacer is not located in the contact hole, no margin for substrate attachment is required to form the contact hole in the first substrate, thereby improving the open area ratio effective for display for improved display quality.

1. Field of the Invention
The present invention relates to a liquid crystal display apparatus wherein a pair of substrates holding a liquid crystal layer therebetween are attached to each other through a columnar spacer.
2. Description of the Prior Art
In recent years, a liquid crystal display apparatus, taking advantage of the features that it is both thin and low in power consumption, has been widely used for OA equipment such as a word processor and a personal computer, the portable information equipment such as an electronic dictionary or a single-unit video tape recorder having a liquid crystal monitor.
The liquid crystal display apparatus, which is not a self luminous display apparatus such as a CRT (Braun tube) or EL (electroluminescence), is generally divided into a reflection type and a transmission type. In the transmission-type liquid crystal display apparatus, light from a lighting unit (what is called back light) arranged on the back of a liquid crystal display panel is used for display, while the reflection-type liquid crystal display apparatus uses ambient light for display.
The transmission-type liquid crystal display apparatus uses the light from the back light for display, and therefore has the advantage that it is hardly affected by the brightness of the ambiance, and can display an image with a high contrast. The provision of the back light, however, leads to the disadvantage of a large power consumption. Incidentally, about 50% or more of the entire power consumed by the normal transmission-type liquid crystal display apparatus is consumed by the back light. Also, in a very bright operating environment (such as outdoor under the cloudless sky), the visibility is decreased. If the brightness of the back light is increased to maintain the visibility, on the other hand, the power consumption is further increased.
The reflection-type liquid crystal display apparatus, on the other hand, has no back light and therefore has the advantage of a very low power consumption. This makes the reflection-type liquid crystal display apparatus a suitable display for outdoor use. The reflection-type liquid crystal display apparatus, however, has the disadvantage that the visibility is low in a dark operating environment.
As a liquid crystal display apparatus compensating for the disadvantages of the transmission-type and reflection-type liquid crystal display apparatuses, a transmission/reflection-type liquid crystal display apparatus has been proposed in recent years as a liquid display apparatus having the dual display functions of transmission and reflection types.
In the transmission/reflection-type liquid crystal display apparatus, both a reflection pixel electrode for reflecting the ambient light and a transmission pixel electrode for transmitting the light from the back light are arranged in one pixel area (picture element area). In accordance with the operating environment (ambient brightness), therefore, display can be switched between transmission mode and reflection mode or both modes can be used for display at the same time.
The transmission/reflection-type liquid crystal display apparatus, therefore, has both the feature of the reflection-type liquid crystal display apparatus that the power consumption is low and the feature of the transmission-type liquid crystal display apparatus that the operation is not hardly affected by the ambient brightness and an image can be brightly displayed with a high contrast. Further, the transmission/reflection-type liquid crystal display apparatus offsets the disadvantage of the transmission-type liquid crystal display apparatus that the visibility is decreased in a very bright operating environment (such as outdoor under the cloudless sky).
A transmission/reflection-type liquid crystal display apparatus has been proposed, in which the transmissive region and the reflective region on the TFT substrate have different thickness of the birefringent liquid crystal layer to realize what is called a multigap (see Patent Document 1, for example). The liquid crystal display apparatus of this type is described briefly below.
FIG. 15 is a sectional view showing a general configuration of a liquid crystal display apparatus of multigap type. FIG. 16 is a plan view of a first substrate 101 formed with a TFT 106 of the liquid crystal display apparatus. In this liquid crystal display apparatus, a liquid crystal layer 103 is held between the first substrate 101 and the second substrate 102.
As shown in FIG. 16, a plurality of gate wires 104 and a plurality of source wires 105 are formed at right angles to each other on the first substrate 101. The portion defined by adjacent gate wires 104 and adjacent source wires 105 forms one pixel. At each intersection between the gate wire 104 and the source wire 105, a TFT 106 is formed as a switching element. The drain electrode 106a of the TFT 106 is arranged in such a manner as to cross a gate insulating film 108 covering an auxiliary capacitance electrode 107, as shown in FIG. 15.
Also, a transparent electrode 109 electrically connected to the drain electrode 106a is formed on the first substrate 101. A partial area of the transparent electrode 109 makes up a transmissive region for controlling the light transmission. The area other than the transmissive region on the first substrate 101 is formed with an inter-layer insulating film 110. A reflection electrode 111 is formed on the inter-layer insulating film 110. The area in which the reflection electrode 111 is formed constitutes a reflective region for controlling the reflection of the ambient light. An orientation film 112 is formed on the transparent electrode 109 and the reflection electrode 111.
Also, the boundary between the transmissive region and the reflective region of the inter-layer insulating film 110 is formed with a taper, and the reflection electrode 111 is formed also on the surface of the taper. When light is radiated on the reflection electrode 111 formed on the tapered portion, the reflected light is contained between the pair of the substrates and cannot exit, with the result that the light utilization efficiency is reduced. The area of the reflection electrode 111 formed on the tapered portion is not contributive to the display of the incident light and therefore, hereinafter referred to as a taper ineffective region.
On the other hand, a colored layer 113, an opposite electrode 114 and an orientation film 115 are stacked in this order on the second substrate 102.
In the liquid crystal display apparatus described above, the first substrate 101 and the second substrate 102 are attached to each other with a columnar spacer 116 arranged in the reflective region so that the thickness Td of the liquid crystal layer 103 in the transmissive region is about twice as large as the thickness Rd of the liquid crystal layer 103 in the reflective region. In this way, by realizing different cell gaps for the transmissive region and the reflective region, the phase difference (And) is substantially equalized between the transmissive region and the reflective region thereby to improve the display characteristic.
Incidentally, in order to realize the multigap described above, it is necessary to form a thin inter-layer insulating film 110 or remove the inter-layer insulating film 110 on the first substrate 101 in the transmissive region. Generally, the inter-layer insulating film 110 is formed of a photosensitive resin, and the thickness thereof is controlled by photolithography. Specifically, by adjusting the time of light exposure to the transmissive region, the thickness of the inter-layer insulating layer 110 to be removed at the time of development can be determined.
Also, a configuration in which a columnar spacer is arranged between a pair of substrates holding the liquid crystal layer therebetween is disclosed, for example, in Patent Document 2.
FIG. 17 is a sectional view showing a general configuration of the liquid crystal display apparatus described in Patent Document 2. In this liquid crystal apparatus, an auxiliary capacitance electrode 204 is formed in the same layer as the data wire through a gate insulating film 203 on the address wire 202 of the surface of a first substrate 201, and an auxiliary capacitor 205 is formed of the auxiliary capacitance electrode 204 and the address wire 202. A contact hole 207 is formed in the portion of the inter-layer insulating film 206 formed with the auxiliary capacitor 205. The auxiliary capacitance electrode 204 and the pixel electrode 208 formed on the inter-layer insulating film 206 are electrically connected to each other by the contact hole 207.
On the other hand, a color filter 212 is formed on the one hand and a columnar spacer 213 is formed by a stack of colored layers on the second substrate 211. The first substrate 201 and the second substrate 211 are attached to each other through a liquid crystal layer 214 so that the forward end of the columnar spacer 213 is arranged in the contact hole 207.
In the liquid crystal display apparatus described in Patent Document 3, a columnar spacer for holding the pair of substrates at a predetermined interval to hold the liquid crystal is formed of a resin material blackened by nonelectrolyte plating thereby to prevent the irregular reflection of the light and thus to prevent the reduction in contrast.    [Patent Document 1] Japanese Unexamined Patent Publication No. 2002-72220    [Patent Document 2] Japanese Unexamined Patent Publication No. 10-96955    [Patent Document 3] Japanese Unexamined Patent Publication No. 2002-174817
The size of the columnar spacer 116 fails to be sufficiently studied in Patent Document 1. When the attachment between the first substrate 101 and the second substrate 102 is displaced, therefore, the columnar spacer 116 may fall in the contact hole (in the case of FIG. 15, the transmissive region portion free of the inter-layer insulating film 110), thereby posing the problem that a desired cell gap cannot be positively secured.
Similarly in the case where the columnar spacer 213 is located in the contact hole 207 as described in Patent Document 2, the displacement between the first substrate 201 and the second substrate 211 attached to each other and hence the displacement of the coordinates between the columnar spacer 213 and the contact hole 207 would make it impossible to contain the columnar spacer 213 in the contact hole 207 and thus to secure the desired thickness of the liquid crystal layer 214.
For example, assume that the attachment accuracy between the first substrate 201 and the second substrate 211 (attachment margin A) is 5 μm in horizontal and vertical directions and the diameter of the columnar spacer 213 is 12 μm. In order to contain the columnar spacer 213 securely in the contact hole 207, the inner diameter of the bottom portion of the contact hole 207 is required to be at least 22 μm.
In the case where the contact hole 207 is formed in the reflective region, for example, the liquid crystal layer 214 in the area formed with the contact hole 207 has no desired thickness and constitutes an ineffective region not contributive to display. This ineffective region is increased by the attachment margin A, thereby posing the problem of a reduced open area ratio. Also, in the attachment margin A, i.e. the region of at least 5 μm around the columnar spacer 213, an area remains where the thickness of the liquid layer 214 is larger than the desired value, thereby probably causing a reduced contrast (the particular area, even if contributive to the display, adversely affects the display).

Liquid crystal display apparatus with spacer positioned over contact hole


A method and an apparatus for encoding/decoding an image according to the present invention may determine a reference area that is a pre-reconstructed area spatially adjacent to a current block on the basis of reference information for specifying the position of a reference area used for predicting a current block and may predict the current block on the basis of the reference area.

Recently, demand for multimedia data such as moving pictures is increasing rapidly in the Internet. However, development of a bandwidth of a channel may not keep up with the rapidly increasing amount of the multimedia data. Accordingly, VCEG (Video Coding Expert Group) of ITU-T and Moving Picture Expert Group (MPEG) of ISO/IEC as an international standardization organization have established a video compression standard HEVC (High Efficiency Video Coding) version 1 on February 2014.
The HEVC defines methods such as intra prediction, inter prediction, transform, quantization, entropy encoding, and an in-loop filter, etc.

Method and apparatus for encoding/decoding image

INDUSTRY ACADEMY COOPERATION FOUNDATION OF SEJONG UNIVERSITY


A semiconductor structure includes a capacitor including a first electrode and a second electrode disposed over and electrically insulated from the first electrode. The semiconductor structure also includes a first conductive via extending through the first electrode and contacting a planar surface of the first electrode. The semiconductor structure further includes a second conductive via extending through the second electrode and contacting a planar surface of the second electrode.

In modern semiconductor devices and systems, integration and miniaturization of components have progressed at an increasingly rapid pace, in wireless applications, one of the growing challenges encountered by the integration process is the disposition of capacitors. Conventional capacitors associated with integrated circuits are usually designed with limited performance and capability due to the space constraints of the circuits. Thus, an improved integrated antenna structure is desired.

Semiconductor device with integrated capacitor and manufacturing method thereof

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.


A circuit includes a flexible circuit having an optical waveguide embedded therein, a first device attached to the flexible circuit and configured to convert a first electrical signal to an optical signal, the first device positioned to emit the optical signal to an input end of the optical waveguide, and a second device attached to the flexible circuit and configured to convert the optical signal into a second electrical signal, the second device positioned to receive the optical signal from an output end of the optical waveguide.

The invention relates generally to optical circuits and, more particularly, to a method and apparatus for conveying optical signals in a flexible package.
In recent years, processor speeds have increased while electronics packages have decreased in size. The increased processor speeds and decreased package size have enabled tremendous increases in digital data rate capabilities, thus enabling miniaturization of high-speed digital devices such as cell phones, camcorders, laptop and desktop computers, and digital televisions, as examples. In addition, because of the tighter space requirements and miniaturization, the processors and components are typically fabricated on small printed circuit boards or multi-layer flexible circuits. In a cell phone application, for instance, the components may be placed on a multiple layer flexible circuit so that a hinge may be formed between two halves of the circuit, thus enabling the cell phone to be opened and closed using the flexible nature of the circuit at the hinge, while enabling components to be placed on a single circuit.
In order to convey these tremendous rates of digital data in affordable and manufacturable devices, different solutions have been applied in the industry that include electronics-only and optical configurations that are typically mounted on a flex circuit or a board having a multi-layer flexible circuit therebetween. For instance, in an electronics-only solution, multiple parallel paths may be built into a multi-layer flexible circuit that enable high rates of digital data to be conveyed simultaneously and in parallel. As the number of parallel paths increases, so too does the capability for high-speed data transmission. However, such configurations also may increase the propensity for cross-talk and electromagnetic interference (EMI) in the parallel portions of the circuit. One option includes an electrical micro-coax, which becomes lossy, expensive and less flexible as frequency increases. Further, as the number of parallel paths increases, circuit cost and complexity increase as well. Thus, in such solutions, though circuits may meet the data rate needs, a trade off may be made in terms of manufacturing cost and yield, as well as performance and signal interference due to the parallel data transmissions.
Solutions using optical components may decrease the propensity for cross-talk, because optical signals typically do not emit EMI, nor are the optical components typically subject to EMI interference from other electrical components. The solutions that include optical devices typically include optical connectors with driving electronics on a main board or multiple separate optical transceiver modules. In such configurations, although the amount of cross-talk may be decreased when compared to an electronics-only solution, such configurations may find limited application because of the additional power requirements and space/packaging requirements for driving electronics or transceivers. In addition, such configurations typically may not be tested in the fabrication process until a final assembly is complete. For instance, in a cell phone application, when installing optical components, the optical links may not be tested or testable until the cell phone is at or near its final stage of manufacture. Thus, failure of a component may not be uncovered until late in the manufacturing process, resulting in costly trouble-shooting and re-work, or costly disposal of the entire device, including the transmitting and receiving components thereof.
Therefore, it would be desirable to design an apparatus and method providing increased data rate capabilities in digital electronics devices, while decreasing package size, power requirements, cross-talk, and overall manufacturing costs.

Optical link circuit and method of making same


A switching device includes: a switch that selects and connects one of input-output terminals to a common terminal; and a delay line that is connected in parallel to the switch between two terminals of the input-output terminals and delays a signal by using an acoustic wave.

The rapid spread of wireless devices as typified by mobile phones has promoted the use of switching devices. For example, mobile terminals for high frequency communications use a high frequency switch to select multiple high-frequency signals. The switches include mechanical switches and switches using a semiconductor transistor.
Japanese Patent Application Publication No. 2006-109084 (Patent Document 1) and U.S. Pat. No. 7,848,712 (Patent Document 2) disclose providing an inductor between input-output terminals to improve isolation characteristics between the input-output terminals of the switch.
The techniques of Patent Documents 1 and 2 can cancel out parasitic capacitance between the input-output terminals by a reactance component of the inductor and improve the isolation characteristics. However, a parasitic capacitance value between the input-output terminals is small, and thus the inductance of the inductor is made to be high. This makes downsizing difficult.