An improved drywall corner sander is provided with an elongated body having opposite sides, and a pair of spaced apart braces extending between the sides. An axle is pivotally mounted between the braces so as to define a first longitudinal pivot axis. A tab on the axle defines a second, perpendicular pivot axis. A handle is connected to the tab of the axle so as to be pivotal about the first and second axes for easy operation of the sander without forming grooves in the side wall adjacent the outer edges of the sander. The pivot axes both reside within the cavity defined by the side walls of the sander.

Sanders for drywall or sheet rock are well known. Generally, prior art sanders come in two forms, a flat sander for the primary, flat wall surfaces, and an angle or corner sander for sanding the inside corner of converging walls. Universally pivotal handles are known for both flat and corner sanders. For example, U.S. Pat. No. 2,711,059 discloses a flat sander with a universal handle which is pivotal about two perpendicular axes. U.S. Pat. No. 6,325,708 discloses a corner sander having a handle pivotal about two axes. However, the axes for such universal pivoting handles are located above or outside the body of the sander, thus adding to the bulk of the sander and increasing the storage space required for the sander. Also, the location of the pivot axes above or outside the outer edges of the base or body tend to transmit excessive sanding forces to the outer edges of the attached sanding pad, which may produce undesirable grooves in the drywall along the outer edges of the corner sander.
Therefore, a primary objective of the present invention is the provision of an improved drywall corner sander.
Another objective of the present invention is the provision of an improved corner sander having a universally pivotal handle.
A further objective of the present invention is the provision of a drywall corner sander having a pivotal handle which minimizes sanding forces which may produce grooves in the drywall.
Yet another objective of the present invention is the provision of an improved corner sander having a handle with pivot axes residing within the cavity of the sander.
Another objective of the present invention is the provision of an improved drywall corner sander which is economical to manufacture, and simple and efficient to use.
These and other objectives will become apparent from the following description of the invention.


An actuator includes a ram structure slidably mounted within a cylinder structure bore and defines with the cylinder structure a gap therebetween. A fluid passageway structure in the ram structure defines a path for fluid to flow through the ram structure and includes an outlet in a sidewall of the ram structure. A cushioning seal located between the ram structure and the cylinder structure can engage the ram structure and a cylinder cap during ram structure extension such that the seal substantially closes off a first portion of the gap extending from the seal toward an open end of the cylinder structure. The cushioning seal can move during ram structure retraction in a direction of ram structure retraction such that fluid flowing out of the ram structure sidewall outlet, when the outlet is in the gap first portion, flows between the seal and the cylinder cap.

U.S. Pat. No. 4,706,781 discloses a load lifting cylinder having a lateral hole 119, which communicates with a bore 106 of a piston element 105, see FIGS. 4-6. A piston rod 107 is coupled to the piston element 105. The '781 patent teaches in column 8, lines 23-34: "When the piston element 105 approaches the uppermost position, and the lateral hole 119 is closed by the rod guide 116, the working fluid in the upper cylinder chamber 104B is permitted to leak out of the chamber 104B into the bottom cylinder chamber 104A only via the small hole 118. That is, the flow rate is extremely limited, due to the closure of the lateral hole 119. As a result, the piston speed is decelerated by the resistance caused by the limited flow of the working fluid. Therefore, the piston element 105 reaches the uppermost position determined by the rod guide 117 at a sufficiently reduced speed without the occurrence of shock." The '781 patent further teaches in column 9, lines 20-26: "it should be noted that if the opening ends of the lateral hole 119 are vertically extended in a longitudinal direction of the piston rod 107, it is possible to delicately control the speed of the piston movement when the piston element 105 approaches or moves away from the uppermost position thereof."


The Intelligent DMA Controller (IDMAC) significantly reduces system latency by replacing one or more layers of software with hardware. The IDMAC uses controlwise and datawise intelligence. The controlwise intelligence of the IDMAC is given specific knowledge of the structure of certain pieces of memory or hardware registers, (e.g. parameter blocks), used for Inter Process Communication. This specific knowledge can be imparted during the design phase of the IDMAC, or dynamically provided during its operation as system requirements dictate. The IDMAC achieves its DMA controlwise intelligence by understanding parameter blocks (PBs). The IDMAC reads the structure of the PB from memory directly, gets all of its PB parameters directly from memory, dereferencing as required, and then begins transferring data between the source and destination as instructed by the PB(s). Examples of PB parameters are source address, destination address, transfer length, and data intelligence opcode. The IDMAC allows for bidirectional nesting of PBs, thereby allowing for complete error recovery. Additionally, the IDMAC provides datawise intelligence to effect manipulations on the data that is undergoing a DMA transfer.

Direct Memory Access (DMA) is a method for direct movement of data between two components, for example in a computer system. Specifically, the data is moved between the components via a bus without program intervention. A DMA Controller (DMAC) is typically a memory-mapped peripheral device that performs memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral data transfers. The specialized hardware of the DMAC maximizes utilization of the system bus so that transfers are performed quickly and efficiently. In this manner, DMA operations typically outperform data movement operations performed by a CPU. Additionally, DMA operations free up the CPU to do other operations.
FIG. 1 illustrates a typical prior art DMAC 100 instantiated into a conventional computing system including a CPU 110, a memory 120, and a peripheral device 130. CPU 110 executes the software instructions of the computing system, whereas memory 120 stores data and instructions for the computing system. Peripheral device 130 generally expresses output signals of or provides input signals to the computing system. Examples of peripheral device 130 include graphics cards, keyboard interfaces, and disk I/Os. The computing system further includes at least one bus 140 which facilitates communication between the various elements. For example, CPU 110 utilizes bus 140 to communicate data to or from peripheral device 130. Most prior art DMACs rely on bus 140 to conduct the DMA operation.
DMAC 100 typically includes a set of registers which hold information necessary to the DMA operation. For example, DMAC 100 includes a source register (Src) 101 for storing the contents of the source address of the DMA bus cycles, a destination register (Dest) 102 for storing the contents of the destination address of the DMA bus cycles, and a length register (Len) 103 for storing the number of pieces of data to transfer. In this embodiment, DMAC 100 also includes a next register (Next) 104 for storing the address of the next place in memory where the DMACs parameters are stored (explained in detail below). Note that herein the term "registers" may include counters, registers, or a combination therein.
A single channel DMAC contains one set of registers 101-104. Many prior art DMACs support multiple channels which are represented in FIG. 1 as the dashed line boxes under DMAC 100. In a typical multiple channel DMAC, registers 101-104 are simply instantiated once per channel. Thus, a four channel DMAC would include four sets of registers 101-104.
FIG. 2A is a typical example of the hierarchy of software and hardware in a conventional computing system. At the bottom of the hierarchy is hardware 200, typically the actual hardware in the computing system. A register interface 250 facilitates communication between hardware 200 and the software of the system.
Continuing up the hierarchy, driver software 210 is considered the software that communicates with, i.e. reads and writes to, hardware 200. Typically, driver software 210 is highly specialized software that is specific to the actual hardware of the computing system. For example, the driver software in an Apple Macintosh model 9500/120 computer cannot generally be used in place of the driver software in a Toshiba model Tecra 730 computer. However, hardware and software manufactures have gone to great lengths to standardize register interface 250 so that they can reuse driver software 210 in a variety of different computing systems. Examples of driver software 210 include hard disk drivers, floppy disk drivers, serial port drivers, parallel port drivers, graphics port drivers, and mouse drivers.
An Application Programming Interface (API) 240 is provided between driver software 210 and operating system software 220 as well as between operating software 220 and application software 230. API 240 is a means of communicating between various layers of software. Specifically, API 240 refers to a standardized means of passing data between two different pieces of software.
Operating system software (also referenced herein as OS software) 220 is the layer of software which generally handles the tasks of the computing system. These tasks would include items such as opening a file for input, prioritizing interrupts to the system, and scheduling events for later processing. Examples of current operating systems include: Apple Computer, Inc. MacOS Version 8.1; Sun, Inc. SunOS Version 5.5.1, and Microsoft, Inc. Windows '95.
OS software 220 communicates with driver software 210 and with application software 230 using different APIs 240. Each API 240 is different because of different data communication needs. For example, OS software 220 generally communicates only data to driver software 210, with a small overhead of control information. In contrast, OS software 220 often communicates task information to and/or from application software 230, even though a high percentage of that task information is data.
Application software 230 is generally the highest level of software in a computing system. Typically, the user of the computing system communicates with application software 230 using a graphical user interface. Illustrative application software, such as Claris, Inc. ClarisWorks 4.0 (a word processing program), allows the user to open a text file, read the file, view the file, make changes to the file, save the file, and print the file. Based upon the specific requests of the user, application software 230 makes calls to OS software 220 via API 240B to accomplish one or more of the above tasks. However, typically application software 230 is still responsible for the actual processing of the data. In some computing systems, OS software 220 is used to help draw graphics and text on the screen. In this manner, application software 230 is not burdened with extra software that could be standardized for other applications. Note that although FIG. 2A shows a single application software 230, in general, a set of application software 230 actually communicates via a set of APIs 240B to OS software 220.
FIG. 2B illustrates API 240A between OS software 220 and driver software 210 in more detail. In API 240A, four basic functions have been defined as a means of communication between the two software layers. These four functions are: Open, Close, Read, and Write. The Open function is used by OS software 220 to initialize driver software 210 for its first usage. Similarly, the Close function is used by OS software 220 to halt the operation of driver software 210. These functions are typically used by OS software 220 to dynamically start and stop software drivers so that the computing system resources can be shared by various higher level software. In addition to the Open and Close functions, this API 240A includes Read and Write functions which are generally used to either write data to or read data from hardware 200 via driver software 210.
FIG. 2B illustrates a number of parameter blocks (PBs), wherein PBs are generally designated locations in memory for specific parameters. For example, in a DMA transfer, the source address, destination address, and length of the transfer need to be designated. These values are placed in memory locations (i.e. PBs). These memory locations are predefined so that the memory can efficiently communicate the data to software (note that the software has had knowledge imparted to it that describes which locations of the PB contain which important data).
A DMAC process typically takes place in three stages: initialization, data transfer, and termination. Referring back to FIG. 1, during the initialization stage, CPU 110 sets up the DMA process by loading source register 101 with a starting source data address, destination register 102 with a starting destination data address, and length register 103 with a length count. After such loading, CPU 110 directs DMAC 100 to start the data transfer operation.
At this point, DMAC 100 initiates data transfers from the data source to the data destination. For example, if data is to be moved from memory 120 to peripheral device 130, then DMAC 100 controls the data transfer between those two components. As data is transferred, source and destination address and length count registers 101-103 are updated. When the length count is decremented to zero, DMAC 100 enters the termination stage. During termination, DMAC 100 updates its status register (not shown) and, in some designs, generates an interrupt request (also not shown) to CPU 110.
In some prior art systems, DMAC 100 supports data transfers of non-contiguous blocks of memory. These transfers of DMAC 100 need to allow for the continuous transferring of data without the assistance of CPU 110. These so-called "chained" operations are accomplished by adding more control logic (not shown) and next register 104 in DMAC 100. Additionally, CPU 110 must have set up a plurality of contiguous parameters in memory readable by DMAC 100. These contiguous parameters are often referred to as a request block, and typically include a source start address, a destination start address, a length count for this transfer, and a pointer to the memory location of the next request block.
Each set of contiguous data transfers requires its own request block. For example, assume the system must transfer two blocks of 1000 pieces of data, but each block of data resides in different memory locations. In this case, CPU 110 simply builds two request blocks and loads the parameters from the first request block into registers 101-104 of DMAC 100. Then, DMAC 100 transfers the DMA data, as indicated by the first request block. Once length count register 103 is zero, DMAC 100 uses a next register 104 to reload registers 101-104 from the parameters contained in the second request block (e.g., next register 104 is a pointer to a location in memory 120 where an address of the next request block is stored). DMAC 100 then transfers the data block referenced by the second request block until length count register 103 is zero again. DMAC 100 in turn looks at next register 104, wherein a special flag value in next register 104 (e.g., a specialized "stop" token, such as a "0" value) indicates to DMAC 100 that all DMA data has been transferred. Note that both blocks of DMA data have been transferred without CPU 110 intervention. Once both blocks had been transferred, DMAC 110 enters the termination stage which updates internal registers and otherwise completes the DMA process.
Although many types of DMACs exist, none compensate for their register interface to software or bus overhead. Thus, prior art DMACs typically have high software and hardware latency requirements. "Latency" is the time required before a given operation is actually begun after the command to begin the operation has been given. For example, the latency from Operating System software 220 initiating a DMA process to the actual starting of the process includes the time delays associated with Operating System software 220, driver software 210, and hardware 200. This time period is inherently long because the procedure consumes additional CPU bus cycles, memory bandwidth, and CPU calculation time. Latency periods are wasteful of time, and can cause significant negative impact to system functionality. For example, in video games, latency problems can show up as "mushy" controls. Therefore, a need arises for a method and apparatus to significantly reduce the latency due to the combinations of software and hardware operations in the DMA process.

Method for providing specific knowledge of a structure of parameter blocks to an intelligent direct memory access controller


A data writing system includes an array of cells for storing data and a write transducer that moves over a selected cell in the array of cells. The write transducer includes a writer producing a write magnetic field that intersects the selected cell. The write transducer also includes a plasmon resonator that is adjacent the writer. The plasmon resonator is shaped to receive lower power density radiation and to provide plasmon radiation at a higher power density to an optical spot intersecting with the selected cell. The plasmon radiation heats the selected cell above a write temperature.

As areal densities increase, smaller bit cells are required in the magnetic media (track width and bit length). As the size of the bit cells becomes smaller, the bit cells become increasingly susceptible to thermal energy flipping the bit cell (i.e., changing the magnetization of the bit cell) and creating an error. Materials and processing of the bit cells can be altered to increase the coercivity of the bit cells to a level high enough to avoid thermal errors. When this is done however, the coercivity becomes so high that it becomes difficult to design a write head that will produce a high enough magnetic field to flip a selected bit cell without also inadvertently flipping adjacent bit cells, resulting in errors.
A data writing system is needed that includes high density cells that are resistant to thermal flipping and in which a single cell can be accessed for writing without inadvertently flipping adjacent cells. A write transducer is needed that provides high levels of write magnetic fields for such high density cells. Embodiments of the present invention provide solutions to these and other problems, and offer other advantages over the prior art.


In a bit-line direction, a plurality of memory mats are arranged including a plurality of memory cells respectively coupled to bit lines and word lines, and a sense amplifier array is arranged including a plurality of latch circuits having input/output nodes connected to a half of bit-line pairs separately provided to the memory mats in a region between the memory mats placed in the bit-line direction, thereby making possible to replace with a redundant bit line pair and the corresponding redundant sense amplifier on a basis of each bit-line pair and sense amplifier connected thereto, thereby realizing effective and rational Y-system relief.

This invention relates to semiconductor memory devices and, more particularly, to a technology effective in utilizing for a Y-system-relief technology on a dynamic RAM (Random Access Memory) of so-called a one-cross-point scheme having dynamic memory cells arranged at cross points between the word lines and the bit lines.
In the research done after completing the present invention, there have been revealed Japanese Patent Laid-open No. 178698/1984 (hereinafter, referred to as Prior Art 1) and Japanese Patent Laid-open No. 20300/1986 (hereinafter, referred to as Prior Art 2) as the dynamic-RAM redundant relief technologies of the open-bit-line type (one-cross-point scheme), hereinafter explained, considered related to the present invention. The publication of Prior Art 1 discloses a 64K-bit dynamic RAM provided with spare arrays. The publication of Prior Art 2 discloses a one-cross-point dynamic type memory provided with a redundant relief circuit. However, there found no conception that a plurality of memory mats are provided in a direction of the bit line to effectively relieve a failed bit line on a mat-by-mat basis as disclosed in the dynamic RAM according to the present invention, hereinafter referred.
Various methods for memory relief are disclosed in the following references, Japanese Patent Laid-Open Nos. 151895/1985, 1511896/1985, 60489/1983, 77946/1986, 151899/1986 and 219597/1999.

Semiconductor device and memory circuit including a redundancy arrangement


The progress of medicine has brought with it the presence of many potent pills that are to be taken with a great accuracy. If these medications are not taken as ordered under or over medications will occur which can be serious. Also the progress of medicine has increased the longevity of the patients and the people live longer with use of many of these medications. However many times living longer is also complicated with weakness of memory which at times happens even in young age. At this point then at time a patient forgets about taking medications and sometimes does not know if has or has not taken a pill. This is at least worrisome if not dangerous and for these reasons this application introduces an automatic reminder for taking the pills as well as an automatic pill dispenser that is to help people to be able to be notified about timing of their medications and also to dispense them regularly. Although the patients with severe degree of impairment of their memory would not be able to use this system. However this is believed to be very useful in helping patients who have some but not a gross impairment of their memory. The inventor presents this as a unit which will help the human beings.

The human life is mixed with having different diseases which fortunately many are controlled or cured with medications. However unfortunately one problem with taking medications is that the people forget about the timing of the medications and then get confused about taking them. This brings problems such as over dosing, under dosing, and confusion of if a patient took an extra medication, or he missed a dose. In my own practice of medicine I have been called by panicked patients many times when they did not know what they have done with their medications, the patients did not remember weather they had taken their medications or not. I have admitted patients to the hospital due to accidental overdose of medications and this has thought me a lesson that there is a problem that needs to be solved. And this application is for such potential solution to help patients to organize their one week medications and to receive them on regular basis.


The present disclosure relates to a semiconductor apparatus and a potential measuring apparatus capable of preventing deterioration in signal characteristics due to parasitic capacitance caused by providing a configuration for realizing an electrode plating process when an electrode and an amplifier are provided on the same substrate. When a power source supplies a potential necessary for plating processing and a breaker reads a signal from liquid, and an amplifier amplifies and outputs the signal, the power source required for the plating processing is blocked with respect to the electrode. This is applicable to the potential measuring apparatus.

In recent years, a technology for measuring an action potential of nerve cells and contributing medical research regarding the nerve action has been required. For example, an electrode apparatus for measuring and recording the action potential of the nerve cells has been proposed (refer to Patent Documents 1 and 2).

This patent is subject to a terminal disclaimer.

Semiconductor apparatus and potential measuring apparatus

SONY SEMICONDUCTOR SOLUTIONS CORPORATION


An electric toothbrush includes an electric toothbrush main body that includes a grip portion; a brush member that includes a brush; a motor that moves the brush; an actuator that relatively rotates the brush member with respect to the electric toothbrush main body in order to change an orientation of the brush; an acceleration sensor that detects an attitude of the main body; and a CPU that controls the actuator such that a brush angle becomes a predetermined optimum value based on the detected attitude.

There is well known a type of electric toothbrush in which a brush moving at high speed abut on teeth to perform brushing of teeth (remove a food residue or dental plaque). In such electric toothbrushes, an obtained cleaning effect depends on an angle at which the brush abuts on the teeth. For example, when the brush abuts on a tooth axis at 90 degrees, the highest dental plaque removing force can be exerted with respect to a tooth plane. When the brush abuts on the tooth axis at 45 degrees, a tip of brush invades easily into an interdentium or a periodontal pocket (between tooth and gum-ridge), and the food residue or the dental plaque can effectively be scraped out from the interdentium or the periodontal pocket.
Thus, there is an optimum brush angle (angle of the brush with respect to the tooth axis) according to a brushing region or the desired cleaning effect. However, few users are conscious of the desired brush angle. Even if the user is conscious of the brush angle, because the user cannot confirm a state in which the brush abuts actually on the teeth during the brushing of teeth, the brush angle is hardly matched with the optimum value.
For example, Patent Document 1 discloses an idea in which an orientation of the toothbrush main body about an axis is detected at four or eight stages to estimate the brushing region from the detection result. Specifically, a plurality of fan-like partitions are circumferentially provided in the main body, and which partition a conductive sphere is in is detected from a change in electric resistance, thereby estimating the orientation of the toothbrush main body. However, the mechanism disclosed in Patent Document 1 is hardly miniaturized and implemented.


Proposed is a parallel inverter drive system including includes a plurality of inverter drives connected in parallel with each other, in which each inverter drive includes a switch; a PWM controller connected to the switch for controlling switching operations of the switch device according to a duty cycle signal; and a circulating current suppressor for collecting current information associated with the current of each inverter drive and a summation current, and generating an index according to the collected current information and the desired circulating current quantity. A zero-sequence voltage is generated for each phase of a three-phase voltage command according to the index and the voltage command and the operating mode of the inverter drive, thereby injecting the zero-sequence voltage into the voltage command with a feed-forward configuration so as to fix the voltage command. The PWM controller can generate the duty cycle signal according to the fixed voltage command.

Generally, a motor needs an inverter drive to control the rotor frequency of the motor and regulate the rotation speed of the motor, so as to drive the motor to operate. In order to increase the safety of the motor during the operation period, a parallel inverter drive system has been proposed. The parallel inverter drive system is made up of a plurality of inverter drives with their outputs being connected in parallel with each other, thereby driving the motor. The parallel inverter drive system is different from the conventional inverter drive system in that the parallel inverter drive system is made by substituting the bulky inverter drive with a number of small-volume inverter drives and allowing these small-sized volume inverter drives to output collaboratively for driving motor. The main features of the parallel inverter drive system are focused on modularity and redundancy. The modularity feature means that the controllers for individual inverter drives with small capacity are independent from other inverter drives. Thus, the user can expand or lessen the capacity of the inverter drive system depending on user's demands. The redundancy feature means that in case of malfunction, the damaged inverter drive can be replaced during the operation of the inverter drive system without overhauling the entire system. If the inverter drive system is appropriately designed, the motor can be driven to operate continuously on the condition that the other undamaged inverter drives are operating normally, while the damaged inverter drives are replaced without the need of shutting down the entire system. Nonetheless, as errors are existed among the individual inverter drives in the parallel inverter drive system, the currents of the inverter drives are not outputted to the motor in their entirety. Under this condition, currents are flowing among inverter drives. Such phenomenon is termed a circulating current. The error among the inverter drives that induces the circulating current may be the asynchrony of the pulse-width modulation (PWM) carrier waves, the asynchrony of the voltage commands, the system parameters, or the mismatch of the external reactors.
A contemporary technique for suppressing the circulating current in a parallel inverter drive system is accomplished by the detection of zero-sequence current. Using this technique, the detected zero-sequence current is used to change the duty cycle of the zero-voltage vector to allow the zero-sequence current of the slave inverter drive to be zero (certainly the zero-sequence current of the master inverter drive is also zero under this condition). Therefore, the circulating current is suppressed. Although the technique of changing the duty cycle of the zero-voltage vector by the detected zero-sequence current can suppress the circulating current, such technique has the following drawbacks. First of all, such technique can address the problem that the zero-sequence is not zero. However, the fact that the zero-sequence current is zero does not indicate that the circulating current is zero. Hence, such technique may allow the circulating current to linger even after the zero-sequence current is subdued. Second of all, such technique needs to adjust the duty cycle of the zero-voltage vector in a real-time manner. Hence, the micro-controller unit (MCU) of the controller in the parallel inverter drive system must support the function of dynamically adjusting the duty cycle signal. In this manner, the hardware arrangement of the parallel inverter drive system is constrained, and the cost of the parallel inverter drive system is hard to be controlled. Finally, such technique is feasible on the condition that the parallel inverter drive system is consisted of two inverter drives. If the parallel inverter drive system is consisted of three or more inverter drives, such technique does not disclose the operating mode of achieving circulating current suppression in such parallel inverter drive system.
Referring to FIG. 1, which is an operative block diagram of a parallel inverter drive system using the circulating current suppression technique with zero-sequence current detection according to the prior art. As shown, the parallel inverter drive system of FIG. 1 includes two parallel-connected inverter drives INV_1 and INV_2, in which the inverter drive INV_1 is a master inverter drive and the inverter drive INV_2 is a slave inverter drive. Va1*, Vb1*, Vc1* are the voltage commands inputted into the inverter drive INV_1, and Va2*, Vb2*, Vc2* are the voltage commands inputted into the inverter drive INV_2. The master inverter drive INV_1 includes a space-vector modulation (SVM) controller 102 for converting the voltage commands Va1*, Vb1*, Vc1* into duty cycle signals Ta1*, Tb1*, Tc1*, and includes a switch device 104 being driven by the duty cycle signals Ta1*, Tb1*, Tc1* and a duty cycle signal T01 with a zero-voltage vector to conduct switching operations. Thus, an AC output voltage and an AC output current are generated to drive the motor 106. Likewise, the slave inverter drive INV_2 includes a space-vector modulation (SVM) controller 108 for converting the voltage commands Va2*, Vb2*, Vc2* into duty cycle signals Ta2*, Tb2*, Tc2*, and includes a switch device 110 being driven by the duty cycle signals Ta2*, Tb2*, Tc2* and a control signal derived by adding a duty cycle signal T02 with a zero-voltage vector with an adjustment quantity K to conduct switching operations. Thus, an AC output voltage and an AC output current are generated to drive the motor 106. It is noteworthy that if the duty cycle signal T01 with a zero-voltage vector is zero, the space-vector modulation (SVM) controller 102 can be replaced with a sinusoidal pulse-width modulation (SPWM) controller. In this example, the operation of the slave inverter drive INV_2 is adjusted along with the operation of the master inverter drive INV_1. The slave inverter drive INV_2 includes an adder 112 for totaling the feedback currents of the slave inverter drive INV_2 to generate a summation current I0. The summation current I0 is subtracted with a signal with a current value of 0 by subtractor 114, and the output of the subtractor 114 is outputted to a proportional integrator (PI) 116. The proportional integrator 116 is used to convert the summation current I0 into an adjustment quantity K. An operator 118 is used to adjust the duty cycle signal T02 with a zero-voltage vector by the adjustment quantity K. The output of the operator 118 is outputted to the switch device 110 to control the switching operations of the switch device 110. Hence, with the adjustment of the summation current I0, the adjustment quantity K represents the dynamic change of the duty cycle signal T02 with a zero-voltage vector. It can be understood from FIG. 1 if the system includes a multiplicity of slave inverter drives, the index for calculating the control quantity (i.e. the summation current I0) can not be carried out.
A second solution to suppress the circulating current in a parallel inverter drive system is accomplished by a current sharing method to allow the phase output currents of the inverter drives to be equal with each other. Thus, the current flowing among the inverter drives is suppressed. Using such technique can efficiently balance the output currents of the inverter drives and prohibit the output currents of the parallel-connected inverter drives from interflowing with each other. Such technique is advantageous in that such technique is irrelevant to the space-vector pulse-width modulation (SVPWM), and thus the complicated calculation for generating the duty cycle signal of the zero-voltage vector and the function of dynamically adjusting the duty cycle signal of the zero-voltage vector are not necessary. Nonetheless, such technique still has the following drawbacks. First of all, such technique is antithetical to the aforementioned circulating current suppression technique using the detected zero-sequence current. That is, such technique can not theoretically guarantee that the zero-sequence current is zero even if the output current of the inverter drives are all equal. Second of all, such technique can be applied to a PWM-based control configuration, e.g. such technique can be applied to a sinusoidal pulse-width modulation (SPWM) configuration. However, such technique can not be appropriately linked with the space-vector pulse-width modulation (SVPWM) configuration. However, the inverter drives are generally required to operate under the space-vector pulse-width modulation (SVPWM) mode in practical applications for the purpose of improving voltage utilization. This would cause inconvenience if such technique is applied to the parallel inverter drive system.
Referring to FIG. 2, which is an operative block diagram of a parallel inverter drive system using the circulating current suppression technique with current sharing configuration according to the prior art. As shown, the parallel inverter drive system for driving a motor 106 is consisted of parallel-connected inverter drives INV_1, . . . , INV_n. Each inverter drive is configured to receive a three-phase voltage command (Va1*, Vb1*, Vc1*), . . . , (Van*, Vbn*, Vcn*). Each inverter drive includes a sinusoidal pulse-width modulation (SPWM) controller 201, and a switch device 200 connected to the sinusoidal pulse-width modulation (SPWM) controller 201. Each inverter drive includes a current averager Ave for obtaining the output currents of other inverter drives and calculating the average current of the output currents of all the inverter drives. The average current calculated by the current averager Ave is transmitted to the operator 202. The operator 202 is configured to compare the output current of the local inverter drive with the average current calculated by the current averager Ave, and in response thereto outputting an error value. A gain controller P is used to calculate a compensating voltage command for compensating the output current according to the error value. The compensating voltage command will be fed back to the sinusoidal pulse-width modulation (SPWM) controller 201, and an operator 203 is used to perform arithmetical operations to the three-phase voltage command (Va1*, Vb1*, Vc1*), . . . , (Van*, Vbn*, Vcn*) and the compensating voltage command, thereby generating a compensated three-phase voltage command. As can be understood from FIG. 2 that the feature of using a current sharing configuration to accomplish the circulating current suppression is that each inverter drive INV_1, . . . , INV_n receives a respective compensated voltage command to force each inverter drives INV_1, . . . , INV_n to have the same phase current with the average current (each phase has different average current to follow). Also, the current sharing configuration of FIG. 2 can be applied to the same control mechanism regardless of the number of the inverter drives. Nevertheless, the generation of the three-phase voltage command is actually accomplished under the sinusoidal pulse-width modulation (SPWM) mode as mentioned above. Also, the respective compensation topology for the phase current can not deal with the problem that the zero-sequence current may exist.
The third solution to suppress the circulating current in a parallel inverter drive system is accomplished by a current droop method. Such technique does not require each inverter drive to exchange current information with each other. Instead, such technique requires each inverter drive to compensate its phase current to enhance the modularity of the inverter drive. Referring to FIG. 3, which shows an operative block diagram of a parallel inverter drive system using the circulating current suppression technique with current droop configuration according to the prior art. Compared to the circuit topology of FIG. 2, the circuitry of FIG. 3 does not does not require each inverter drive to exchange current information with each other. Instead, the circuitry of FIG. 3 requires each inverter drive to compensate its phase current. Hence, the output phase current of each inverter drive is provided to the gain controller P for calculating a compensating voltage command for the output phase current. The compensating voltage command is fed back to the sinusoidal pulse-width modulation (SPWM) controller 201. The operator 203 is used to perform arithmetical operations to the three-phase voltage command (Va1*, Vb1*, Vc1*), . . . , (Van*, Vbn*, Vcn*) and the compensating voltage command, thereby generating a compensated three-phase voltage command. Nonetheless, such technique has the following drawbacks. First of all, such technique can result in similar output currents for the inverter drives only on the condition that the each inverter drive INV_1, . . . , INV_n has similar parameters with each other. In other words, the current sharing effects can be attained effectively on the condition that each inverter drive INV_1, . . . , INV_n has the same specification with each other. Second of all, if the method of phase current compensation is used, the compensation quantity will be large if the phase current is large. When the rotation speed of the motor 106 is increasing, a relatively large current will be outputted. Under this condition, if the current droop technique is used, the relatively output current will be subdued. Thus, the transient response will be damped to slow down the acceleration of the rotation speed of the motor. Finally, such technique can simplify the current sharing configuration and attain a better modularity. However, the aforementioned drawbacks are still unresolved.

Parallel inverter drive system and the apparatus and method for suppressing circulating current in such system


According to embodiments of the present disclosure is a water delivery system that continuously flows and recirculates clean water, diverting only water that has touched a user's hands. No sensing is required to activate the water flow and the actions of the user effectively divert the dirty water to a drain. The water delivery system comprises a clean water outlet, a clean water inlet, a dirty water drain, and a circulation pump. A stream of water continuously flows from the outlet and is received by the water inlet if the stream is uninterrupted. If the stream is disturbed, such as by the hand washing activities of the user, the stream is diverted from the inlet and instead falls into a sink and into the drain.

The invention relates generally to water delivery systems. More specifically, the invention relates to a water delivery system comprising a sink, faucet, and pumping devices that continuously circulates clean water and diverts dirty water that has touched a user's hands. By diverting only contaminated water and recirculating clean water, the water delivery system has the ability to improve water conservation.
Several prior art systems have been designed in an attempt to conserve water. For example, in public restrooms, some systems rely on sensors that automatically turn on the flow of water when a user's hands are placed below the faucet. To conserve water, the flow is terminated when the user's hands are removed. These widely used systems are often referred to as automatic faucets. Automatic faucets have two key parts: a sensor, such as an infrared sensor, that senses the proximity of the user's hands and an electrically switched valve that opens the water flow.
Theses automatic faucets suffer from problems associated with both the sensor and the switched valve. For example, the sensor is not always accurate and may start the water flow too early or keep it running after the user moves his hands away from the faucet. In addition to wasting water, the lack of accurate responsiveness of those sensors results in inconvenience to the user.
The main disadvantage with these types of systems is the added cost. In addition, automatic faucets require batteries, which deplete and run out over time, or require a dedicated power source. These components are vulnerable to failure. In fact, the fundamental disadvantage of the automatic faucets' water conservation methodology is that it relies on sensing and switching, both of which are carried out by extra components that require power, maintenance, and can fail.
Other water conserving systems include self-closing faucets, such as those used in airplanes and other public restrooms. With these systems, the user depresses a knob on the faucet to begin the flow of water. The knob slowly returns to the off position, at which time the water flow ceases. Users find these faucets inconvenient because the time period the faucet stays open is fixed and is normally too short for a particular user and she has to re-press the knob several times while using the faucet. If the faucet remains open too long, water is being wasted. Theses faucets are prone to failure of the mechanical timing mechanism that results in the time period becoming even shorter, leading to inconvenience, or longer and leading to water waste. Another disadvantage of self-closing faucets is the need to touch them with unclean hands, which is a hygiene hazard in public bathrooms and health facilities. It would therefore be advantageous to develop a water conservation system that does not suffer the drawbacks associated with the prior art.

Drain diverted dirty water and continuously circulated clean water system


A cooling device for use in an electric arc furnace is provided. The cooling device provides a novel and effective method for cooling burners, lances, enclosures, and other devices used in high heat environments, such as in Electric Arc Furnaces. According to one aspect of the invention used in a steel making process in an electric arc furnace, a cooling tube is inserted into a cooling cavity in a burner. Cooling fluid is injected through the cooling tube into the cavity to cool the portions of the burner adjacent the cooling cavity. The cooling fluid is then extracted from the cavity through a concentric space between the cooling tube and the cooling cavity. According to another aspect of the present invention, a cooling fluid distribution flange is provided to distribute cooling fluid to a plurality of cooling tubes to inject cooling fluid into a plurality of associated cooling cavities.

Electric arc furnaces (EAFs) make steel by using an electric arc to melt one or more charges of scrap metal, hot metal, iron based materials, or other meltable materials, which is placed within the furnace. Modern EAFs may also make steel by melting DRI (direct reduced iron) combined with the hot metal from a blast furnace. In addition to the electrical energy of the arc, chemical energy is provided by auxiliary burners using fuel and an oxidizing gas to produce combustion products with a high heat content to assist the arc.
If the EAF is used as a scrap melter, the scrap burden is charged by dumping it into the furnace through the roof opening from buckets, which also may include charged carbon and slag forming materials. A similar charging method using a ladle for the hot metal from a blast furnace may be used along with injection of the DRI to produce the burden. Additionally, these materials could be added through other openings in the furnace.
In the melting phase, the electric arc and burners melt the burden into a molten pool of metal, termed an iron carbon melt, which accumulates at the bottom or hearth of the furnace. Typically, after a flat bath has been formed by melting of all introduced burden, the electric arc furnace enters a refining and/or decarburization phase. In this phase, the metal continues to be heated by the arc until the slag forming materials combine with impurities in the iron carbon melt and rise to the surface as slag. During the heating of the iron carbon melt, it reaches the temperature and conditions when carbon in the melt combines with oxygen present in the bath to form carbon monoxide bubbles. Generally, flows of oxygen are blown into the bath with either lances or burner/lances to produce a decarburization of the bath by the oxidation of the carbon contained in the bath.
A furnace must reach very high temperatures to melt burden into molten metal. For example, scrap steel melts at approximately 2800° F. Additionally, it is typically desirable to raise the temperature of the melt sufficiently above the melting point (typically to 2950° F.-3050° F.) to allow the melt to be transferred from the furnace to a desired location and further processed without prematurely solidifying. In addition to melting the scrap, the electric arc and molten burden can damage the furnace itself as well as any devices placed inside the furnace, such as burners, lances, and enclosures for burners and lances.
To combat heat related problems, furnace and furnace component designers generally use water cooled devices and panels. Such devices and panels use a constant flow of cooling fluid through the devices, close to the surfaces that are exposed to heat, to help dissipate the heat. The cooling fluid thus cools the panels, from the inside, and lowers the temperature of the device.
Most fluid cooled devices use a serpentine arrangement to direct water through the device. While such arrangements are often effective at cooling furnace components, they are not sufficiently efficient and often allow hot spots to develop. One reason why a serpentine arrangement is not efficient is that as the water flows through the device, small bubbles often form along the walls of the water pipes. These bubbles can insulate a portion of the pipe and prevent the water from cooling the device sufficiently.
Within a cooling pipe, cooling fluid generally moves most rapidly and turbulently through the center of the pipe, and likewise it moves less rapidly and less turbulently along the walls of the pipe. Those skilled in the art may be familiar with the Reynolds number of a flow. The Reynolds number is indicative of the turbulence of the fluid. A low Reynolds number indicates that the fluid flow is laminar and a high Reynolds number indicates that the fluid flow is turbulent. In cooling operations, it is desirable for the fluid flow to be turbulent and thus a high Reynolds number is desired. Often, the turbulence of the fluid along the pipe wall is low even when the overall fluid flow through the pipe is high. One solution to solving this problem is to place material along the wall in the pipe to partially obstruct the flow and to increase the turbulence of the fluid along the pipe wall. While this solution may improve the turbulence of the fluid in a location, it may cause other areas of low turbulence to form.
Another remedy to this problem is to increase the velocity and turbulence of the water by increasing the flow of water through the pipe. This may help wash away the bubbles, but it requires significantly higher water flow and pressure, thereby increasing the cost of operations.
Further, certain portions of a furnace device may experience greater heat effects than other portions of the device. The serpentine structure does not allow a furnace device to receive more cooling in one area than another. Rather, the same force of water flows through all sections of the serpentine.
One solution used to address the problems associated with the serpentine structure is the use of spray nozzles to spray the walls of a furnace to keep them cool. One such solution is disclosed in U.S. Pat. No. 4,813,055 to Heggart et al (hereinafter "Heggart"). In Heggart, a furnace is built with an inner and an outer shell and spray nozzles are installed between the two shells to spray and cool the outside of the inner shell. While this solution often works effectively for furnace walls, it is not practical for use in furnace components due to space limitations.
Therefore, it would be advantageous to provide a method and apparatus for cooling furnace devices that overcome the problems associated with serpentine water cooling and spray system water cooling.
Additionally, it would be advantageous to provide a method and apparatus for cooling furnace devices that allows cooling fluid to be directed to specific portions of the furnace device.

Cooling device for use in an electric arc furnace


A non-volatile memory includes a substrate region, a barrier layer, an N-type well region, an isolation structure, a first gate structure, a first sidewall insulator, a first P-type doped region, a second P-type doped region and an N-type doped region. The isolation structure is arranged around the N-type well region and formed over the barrier layer. The N-type well region is surrounded by the isolation structure and the barrier layer. Consequently, the N-type well region is an isolation well region. The first gate structure is formed over a surface of the N-type well region. The first sidewall insulator is arranged around the first gate structure. The first P-type doped region, the second P-type doped region and the N-type doped region are formed under the surface of the N-type well region.

As known, a non-volatile memory can continuously record data after the power supply is interrupted. Consequently, the non-volatile memory has been widely used in various electronic devices. Generally, plural memory cells in the non-volatile memory are arranged as a memory cell array. Each memory cell comprises a floating gate transistor. Moreover, hot carriers can be stored in a floating gate of the floating gate transistor. By controlling the amount of hot carriers injected into the floating gate, a storage state of the memory cell can be determined. For example, the hot carriers are electrons.
Generally, the floating gate of the floating gate transistor is made of a conductive material (e.g., a polysilicon material). In the non-volatile memory, the floating gate of the floating gate transistor is not electrically connected to any part of the circuit. That is, the floating gate is in a floating state.

Memory cell with isolated well region and associated non-volatile memory


Methods, systems and apparatus for maintaining colors and color boundaries across multiple storage controllers by instructing a polling storage controller to poll a color control node for current color information, changing the current color to a new color, and instructing the polling storage controller to cease polling the color control node for the current color information.

Disaster recovery strategies for computer systems generally involve copying data stored at a primary site to a secondary site which is typically located some distance from the primary site. Copying from the primary copy to the secondary copy may be performed either synchronously or asynchronously. Where copying is performed synchronously, each time an update is written to the primary copy, the update is also sent to the secondary site to be written to the secondary copy. Only after the secondary site informs the primary site that the secondary copy has been updated does the primary site acknowledge the update to the primary copy and stand ready to write the next update. Thus, updates are written to the primary and secondary copies in the same order. Where copying is performed asynchronously, multiple updates may be written to the primary copy and acknowledged before any updates are sent to the secondary site, as the primary copy is maintained independently from the secondary copy. The updates are sent periodically to the secondary site, typically as a set of writes referred to herein as a "color," and are written to the secondary copy, not necessarily in the same order as they were written to the primary copy.
Where a single color is maintained across multiple storage controllers at the primary site, it is necessary when switching to the next color that all storage controllers switch to the next color in a coordinated fashion to maintain the integrity of "dependent writes" across color boundaries. For example, given the following typical sequence of dependent writes for a data base update transaction:    1. execute a write to update the data base log indicating that a data base update is about to take place, then    2. execute a second write to update the data base, and finally    3. execute a third write to update the data base log indicating that the data base update has completed successfully, it is imperative that these dependent writes either all belong to the same color, or, if they cross a color boundary, that the earlier write(s) belong to the old color and the later write(s) belong to the new color. In this example, assuming writes 1, 2, and 3 are each written by a different storage controller, if writes 1 and 3 are written as part of color group "red," and write 2 is written as part of the next color group "blue," should the primary copy be lost after the "red" group is written to the secondary copy but before the "blue" group is written to the secondary copy, the data base log in the secondary copy would incorrectly show that the second write to update the data base occurred, when in fact the data base was never updated.
In one technique for maintaining colors and color boundaries across multiple storage controllers at the primary site, before associating a write with a color, each storage controller polls a color control node which maintains the current color and requests the current color. The color control node apprises the storage controller of the current color, and the storage controller associates the write with that color. While this ensures the absolute color switchover of all storage controllers at effectively the same point in time and thereby ensures that the integrity of dependent writes is maintained across the color boundary, each write operation is delayed by the round trip to the color control node, and the color control node might become a bottleneck.
A method for maintaining colors and color boundaries across multiple storage controllers at the primary site that reduces write delay and the risk of bottleneck would therefore be advantageous.

Write set boundary management in support of asynchronous update of secondary storage

International Business Machines Corporation


The design and refinement of a tethered hovering platform into a feasible working system is presented. To determine a starting point for the design, a detailed historical search was conducted to find the history and the current state of such technology. Real world current needs are analyzed to produce a mission specification and to drive the preliminary vehicle design. Analysis of environmental conditions and decisions about an initial payload package are made in conjunction with motor and propeller sizing. Initial concept testing to discover feasibility and operational issues was performed; from this, instability issues were discovered. Analyzing these instability issues using known rotorcraft and momentum effects, in conjunction with flight testing, yields possible solutions to the problem. The use of constrained layer dampers as a means of passive stabilization is addressed and suggested as the preferred solution. Testing of passive constrained layer damping verifies the stability of the solution. The system components and manufacturing cost is presented in comparison to current systems using active stabilization.

1. Field of Invention
This invention relates generally to tethered hovering platforms (THP), and more specifically to tethered hovering platforms utilizing composite material, lightweight motors and lightweight high strength tethers.
2. Background Art
Inventors attempting to perfect early helicopter designs used tethers to add stability and safety during testing and development. The idea of using tethers was re-visited by the Germans and the French in World War II. The German Navy successfully deployed the Fa 330, an un-powered helicopter towed behind submarines. In the decade after WWII designs of extremely large, unmanned, single and multiple tethers hovering platforms such as the German KIEBITZ and the French Nord 510 were explored and prototypes were tested. These ideas were abandoned after only a few years of testing and development.
Hovering vehicles of today use onboard active stabilization systems for control. These systems after years of development have enabled vehicles such as the Sikorsky Cypher and Canadair C1-227 Sentinel to hover and fly in a stable manner and execute desired mission profiles. However, the stability of these craft comes at a very high cost, and the acquisition and maintenance costs of these craft are considerable. Intricate electronics of a complicated hovering vehicle include multiple piezoelectric gyroscopes, servos for actuation of control surfaces and motors, and occasionally onboard computers for autonomous flight. Two good examples of this type of vehicle are the Sikorsky Cypher and the Honeywell MAV. While these examples are very innovative, none have been commercially used for the missions that they were designed for. The problems with these concepts are that they are too expensive, difficult to maintain, have complicated deployment and recovery systems, and they are challenging to control.
Tethered observation balloons were first used for reconnaissance in the U.S. Civil War by both the Union and Confederate armies. Thaddeus Lowe helped develop the initial concept and helped establish the first balloon core, which he commanded. The first tethered observation balloon saw service on Sep. 24, 1861. On this date Lowe himself telegraphed intelligence about the Confederate troops at Falls Churce Va., over 3 miles from where his balloon was located. Un-powered Observation balloons remained in service with the both Allied and German ground and naval forces through WWII. These balloons became easy targets for aircraft and their usefulness was severely limited.
Tethered Rotorplatforms and Their Mission Potential by Wener Goller 1980 is an early publication on the topic of rotor platforms. The paper covers several topics of great importance to the topic at hand. The first is the definition and mission outline for these vehicles at the time. It states, "Tethered rotorplatforms are unmanned helicopters connected to the ground station by means of a tethering cable." It goes on to define the basic advantage and mission of these types of crafts. "The main objective of tethered rotorplatforms is to elevate sensors or transmitters to an operation height at which the maximum range of these systems can be utilized without considerable restriction by terrain roughness and vegetation." "The first tethered rotor platform, that was successfully flight tested up to a height of 45 m above the ground was constructed during World War I by Stefan Petroczy and Theodore von Karman."
"It was tethered by three cables fixed at the end of three cantilevers of the fuselage and driven by three aeroplane motors of 120 hp each." Petroczy and Karman's vehicle used a pilot/observer since no electronic means of performing the flight and observation tasks was available.
A similar 3 tether system was developed during World War II, by the German AEG company. Utilizing a 200 kw (268 HP) electric motor the craft could reach a maximum altitude of 750 m (2,460 ft) AGL. Their design was intended to carry one observer or a set of radio antennas. Development was stopped before the unit ever became operational.
During the post WWII years the Hiller Aircraft Company under contract with the office of naval research, developed the Hiller VZ-1 flying platform. Tethered flight experiments starting in 1953 eventually led to successful free flight in 1955. The craft used counter rotating ducted fan, upon which the pilot stood. The craft was controlled by the pilot shifting his weight in the direction he wanted the platform to move. Variants of several sizes were produced for analysis by the US Army, which after tested concluded the craft was impractical. The Hiller VZ-1 was limited to very slow speeds and calm conditions, and would not operate very far out of ground effect.
The first notable vehicle to undergo long term development is the German build Kiebitz. After a successful predecessor program in 1972, the German military awarded Dornier a contract to build and test the Kiebitz. The system had two main components, the ground station/base vehicle and the hovering platform; these two units were attached by the large single main tether.
Even at this point in history the rotorcraft used an onboard control system to give it defacto flight stability. Some of the exhaust gas was routed through a yaw control nozzle, and was used in conjunction with an onboard analog electric autopilot unit. The craft could operate in three control modes, attitude, position, and drift control.
The main cable attaching the flight vehicle to the ground station was quite complex since it carried jet fuel up to the turbine engine, as well as many electrical cables for control signals and sensor returns. This vehicle was designed to carry comparatively large sensor arrays into the air to detect aircraft or large ground vehicles approaching a position in central Europe. Alternatively it had options to operate as a mobile relay station for radio signals on the battle field. Since there are few obstacles on the open sea, an investigation of using the system aboard ships was made. The height advantage given by the vehicle would allow detection of ships at extreme range, and could even give over the horizon capabilities.
This vehicle was considered small and portable at the time, with a weight of several hundred pounds and a vehicle diameter of nearly 5 feet. By today's standards, the craft was quite large and very heavy. The materials used to construct the vehicle, as well as the propulsion system and payloads were orders of magnitudes higher in weight than modern systems.
Some have made mention of a small electric powered platform tethered by one tether that uses active control flaps. Similar ideas can be seen in some vehicles that are being developed today. Still as can be seen by the dimensions the craft is still quite large with a rotor diameter of 2.2 m. Some desired to see tethered rotorplatforms thrive and become useful for the perceived missions, but the opposite has seemed to happen. In fact they disappeared and were replaced with complex high dollar free-flight solutions.
The French developed an elegantly designed shrouded THP, called the Nord 510. It was powered by a turboprop engine, with a blade that was 5.9 ft in diameter. The platform was able to fly and hover above the ground vehicle up to a height of 1,000 ft. The vehicle had an empty weight of 990 lb, not including the weight of fuel or the tethers at altitude. The vehicle has an approximate diameter of 6 ft and a height of 8 ft, and is not much smaller than the DO32k. The ground vehicle and attached winch systems are approximately 12 ft tall and 25 ft long.
The "Rahfan" was a ducted fan free flying vehicle that used control tabs downstream of the propeller. The designers directly commented about the instability of the aircraft, and say that the design should be tailored to "off design conditions," implying mainly to windy weather conditions. The comments allude to the conclusion that the craft is not stable in a wind gust and suffers the same instabilities as other ducted fan UAV's of similar configuration.
In the paper Development of a Shrouded-Fan UAV for Environmental Monitoring the authors say that it does not really fly at all. The Department of Aerospace Engineering at the Polytechnic of Turin in Italy developed a new ducted fan vertical takeoff and landing (VTOL UAV), where the whole vehicle is enclosed in one large shroud. The vehicle uses a large gas engine for power. Work on the project began in 1997 and the paper was published in 2004. The performance specifications are noted as such.
"The UAV, has a maximum takeoff weight of 1,000 N (224 lb), and the shroud diameter and weight are 1.9 m (6.2 ft) and 110 N (25 lb), respectively. Expected maximum performance is as follows: Scientific payload weight 100 N (24.7 lb), altitude 2,000 m (6561 ft), speed 30 m/s (67 mph), range 100 km (62 ml), endurance 2 hours."
"Unfortunately, this system can be used only for tests of relatively small duration, where the vehicle remains in a nearly horizontal attitude, that is, hovering and low speed translation. If the fuel consumption of the engines is slightly different, an unbalanced weight distribution can result on the long run. The same unbalance can also be induced by the failure of one of the engines. Finally, fuel must be provided to all the three engines in any flight condition, and this may be difficult when the tanks are only partially filled and the vehicle has a pitch attitude of more than 20 deg, as in forward flight at high speed."
The designers at the Polytechnic of Turin vehicle have not addressed any pitch back instability due to the large shroud, or issues with center of gravity placement on the vertical axis. There is also little shown on the control mechanisms, whether they are control vanes or thrust vectoring or another system as seen on current free flight vehicles.
The design is very similar to the Sikorsky Cipher. The first proof of concept Cypher was flown in 1988, with the first free flight prototype taking flight in 1993. This vehicle went through extensive testing and development throughout the 1990s and led to development of the Cypher II The Sikhorsky Cipher never reached production stage, but the program may still be active.
The Canadair CL-227 Sentinel was first developed in 1978. Development of the Sentinel progressed through three separate phases over the span of over ten years. The CL-227 is a remotely piloted vehicle with a turboshaft engine that drives counter rotating rotors. The CL-227 can operate in tethered or free flight modes. The phase three variant is roughly 5 feet tall, weighs 419 lb (190 kg), and has a payload capacity of 99 lb (45 kg). It can reach a maximum level speed of 81 mph (130 km/h) and has a typical mission endurance of 3 to 4 hours.
The Sentinel was upgraded to the CL-327 Guardian. The Guardian offers approximately 6 hours of endurance, a maximum altitude of 18,000 ft, and an increased payload capacity of 220 lb. The Guardian is equipped with state of the art radar, optical sensors, and communications equipment, and is in production by the Bombardier Company.
The paper Improving Control System Effectiveness for Ducted Fan VTOL UAVS Operating in Crosswinds optimizes what has become the standard approach in the development of hovering platform type systems. It seems from all the vehicles being developed that they want a fully autonomous self controlled and stabilizing craft. For some missions this is indeed necessary; however for relatively close-in surveillance other options exist outside this paradigm. The instability problems of ducted fan VTOL UAVs, problems still haunt even the most successful modern vehicles. "There are two significant, inherent issues associated with ducted fan control in crosswinds; 1) lateral momentum drag and 2) a duct stabilizing torque which resist tipping into the wind." The authors worked on many projects including a DARPA funded project in conjunction with Honeywell called the "Kestrel" Organic Air Vehicle.
The instabilities and control of these types of free flight craft are so complicated that in addition to the CFD models a 6 degree of freedom test model was created and wind tunnel tested. Some really substantial work was conducted and involved a lot of time and money thrown at the same problem that has existed since the first ducted fan VTOL UAV. The following four pictures show how in a strong crosswind the conventional use of control vanes is problematic as the vanes loose effectiveness unevenly due to thrust cone bending. These images also demonstrate how these control vanes should be placed very close to the rotor plane to not lose effectiveness. However, placement in such a position decreases their moment arm and thus reduces significantly their control effectiveness.
These types of instabilities, and control issues caused by insufficient control power posed large challenges to the designers and engineers working on a piloted ducted fan vehicle in the 1950's.
Aero-Design & Development out of Israel has released a vehicle extremely similar to the Hiller VZ-1 concept, now named the AD & D Hummingbird. They performed tethered flight tests starting in August of 1997, and conducted free flight testing in October of 1998. Sale of the craft in kit form was scheduled to take place in 2000, but as of May 2008 this craft is still not for sale for unknown reasons.
The state of the art free flight vehicle being deployed to Iraq and Afghanistan is the Honeywell Micro Air Vehicle (MAV). This vehicle is the product of a long term DARPA development contract whose earlier vehicles included the Kestrel and Organic Air Vehicle (OAV). "The MAV is a scout reconnaissance type vehicle. It allows people to see over a hill or around a building." The vehicle weighs 12.5 lbs, is capable of operation in 20-knot winds, and has 40 minutes of endurance at 5,500 ft. The motors, ducted fan central body and other components can be recognized.
While this free flight vehicle is capable of flying at 50 kts airspeed and climbing at 25 feet/second, the mission profile for the vehicle is described as "hover and stare". The hover and stare mission profile consists of vertical takeoff and then hovering above a place of interest providing elevated reconnaissance images. The vehicle is equipped with forward and downward looking visual and infrared camera system. The 2nd Battalion, 5th Infantry Regiment has been undergone several months of training with the vehicle in the Military Operations in Urban Terrain training site.


A TDR for locating impairments in an HFC network is claimed. The network carries burst signals in an upstream band during burst intervals. The TDR comprises a transmitter, receiver, level detector, controller, accumulator, and probe detector. The transmitter transmits probe signals to the impairment, causing a reflection of the probe signals. Each probe signal is in the upstream band and has a bandwidth extending the width of the upstream band. The receiver receives the reflected probe signals during receiving intervals, and receives the burst signals during receiving intervals that overlap burst intervals. The level detector measures a level of the signals received during each receiving interval. The controller determines which of the receiving intervals are free of burst signals, based on the level measurement. The accumulator accumulates reflected probe signals received during intervals free of burst signals. The probe detector detects the impairment from the accumulated probe signals and estimates a time delay for the impairment. A distance to the impairment is estimated from the time delay.

Field of Invention
The present invention relates generally to monitoring impairments in a Hybrid Fiber-Coax (HFC) network, and more particularly to apparatus and methods for detecting and locating linear impairments such as, but not limited to, impedance mismatches causing micro-reflections in a coaxial cable plant of an HFC network.
Background Art
Micro-reflections are one of the most critical impairments in an HFC network, especially in the return path where signal losses in the cable are minimal and reflected signals from even remote impedance mismatches can impact upstream service signals from DOCSIS cable modems (CMs). Detection and location of mismatches can be a challenging problem in an HFC network carrying signal traffic or service signals ("live HFC network"). Traditional methods of detection and location have involved Time-Domain Reflectometry (TDR). In general, TDR involves the injection of high-powered probe signals or pulses into the network and the measurement of time delay, level and polarity of the reflected probe signal/pulse from mismatches in the network. Employment of TDR in a live HFC network is challenging because of the number of service signals present and the fact that the service signals can be disrupted by the probe signal and can interfere with the detection of reflected probe signals (e.g., a low-level reflected probe signal can be masked by strong service signals). Thus, heretofore, TDR has not been very practicable for testing in a live HFC network.
A technique for detecting mismatches in the return path of a live HFC network without injecting a probe signal has been developed by CableLabs® as part of the Proactive Network Maintenance (PNM) initiative. It is described in a published document entitled, DOCSIS® Best Practices and Guidelines, Proactive Network Maintenance Using Pre-Equalization, CM-GL-PNMP-V02-110623, by Cable Television Laboratories, Inc., Louisville, Colo., Jun. 23, 2011 (http://www.cablelabs.com/wp-content/uploads/2014/05/CM-GL-PNMP-V02-110623.pdf). The PNM technique is based on using pre-equalization coefficients from CMs operating in the HFC network. This technique can be classified as virtual TDR, because the upstream QAM service signals serve as the probe signals. Briefly, this technique can detect a micro-reflection of an upstream QAM signal (transmitted from a CM to a Cable Modem Termination System) and measure the time delay of the micro-reflection (relative to the initial signal) by analysis of pre-equalization coefficients. Then, by using electronic maps, a probable point in the network where the micro-reflection occurred (impedance mismatch) is located. The declared accuracy of the PNM technique is about +/−50 feet. This is not as accurate as traditional TDR using a wideband probe signal. The accuracy of the PNM technique is limited by the bandwidth of one upstream QAM channel (6.4 MHz in the U.S.) and by the number of pre-equalization coefficients. In addition, the PNM technique usually identifies only a branch in the coaxial cable portion of the network where the mismatch is located. Despite these limitations, PNM technology is widely used in cable TV HFC networks today.
Another technique for locating mismatches in a live HFC network uses downstream signals of the HFC network. This technique is disclosed in U.S. Pat. No. 6,385,237 to Tsui et al. This patent indicates that it discloses a method and system for non-invasive testing of a digital cable network. No probe signal is injected into the network. Amplitude measurements are made over a wide band of frequencies of the downstream spectrum and the resulting spectrum of measurements are then converted to the time domain. An adaptive filter then seeks to match its output to the time domain representation, thereby characterizing the communication channel (i.e., the cable). It is stated that impedance mismatches may be located using this technique and that the accuracy of location may be to within 0.7 meters (Col. 10, lines 6-11).
CableLabs® has also proposed to use the full downstream signal to detect and locate impedance mismatches in a live HFC network. See, e.g., presentation entitled, Distortion Testing in Home Terminals, CableLabs® SCTE Conference Demo, Oct. 21-24, 2013, by Thomas Williams and Alberto Campos. In this technique, the full-spectrum downstream signal is captured by a modern CM (e.g., containing a new Broadcom® chipset) and then the autocorrelation function of the signal (which may contain a reflected signal) is calculated. Again, no probe signal is injected into the network. If a reflection exists, it would appear as a spike (in addition to the main detection peak) in the autocorrelation function. Thus, the time-distance between the main peak and the reflection spike can be measured. This technique allows one to measure the time delay of a reflection more accurately (thus pinpointing the location more accurately) than the PNM upstream technique identified above. However, this downstream technique has some drawbacks. First, to provide good detection sensitivity, the accumulation time for estimating the autocorrelation function should be relatively long (e.g., tens of milliseconds), while the duration of the captured full downstream signal is limited to only tens of microseconds. The capture duration is limited to achieve a reasonable resolution bandwidth for spectral analysis (e.g., 30 kHz) and a reasonable data size (e.g., 30 Kbytes). Therefore, to achieve an adequate accumulation time it may be necessary to carry out a large number of captures, which could take time and impact CM signal traffic. Another limitation is that continuous wave (CW) or narrowband downstream signals, such as analog video carriers, AGC pilots, and OFDM pilot subcarriers, may be included in the autocorrelation, which could contribute flat or spread components to the function. These flat or spread components could mask actual reflection spikes and reduce sensitivity and time resolution (distance accuracy).
Another known technique, somewhat similar to CableLabs' full downstream capture technique, is disclosed in U.S. Pat. No. 7,271,596 to Furse et al. In Furse et al., reflections from impedance mismatches are also detected by obtaining an autocorrelation function of a full-spectrum service signal (an "operational signal"). However, in a modern HFC network, the capturing and processing of the full-spectrum operational signal and estimating its autocorrelation function is not a trivial task and has certain drawbacks as discussed above. A downstream signal in an HFC network has a very wide bandwidth (e.g., 1 GHz with a probable increase to 1.7 GHz under DOCSIS 3.1). Therefore, sampling and digitally processing this signal requires expensive and high power-consuming chipsets. Also, TDR is generally used in a section of a coaxial plant that contains only passive network devices ("passive section"), e.g., between adjacent trunk amplifiers. Downstream signals that pass through amplifiers may already contain reflected signals which could, in an autocorrelation function, mask reflections originating in the passive section under test.
The use of spread spectrum modulation of a TDR probe signal is also a known technique for testing a communications network carrying service signals. See, for example, U.S. Pat. No. 7,069,163 to Gunther, where a digital data signal is transmitted in an aircraft communication cable and a probe signal is created by spread spectrum modulating the digital data signal. Then, the spread spectrum probe signal is injected into the cable while the cable is carrying the original unaltered digital data signal. A reflected probe signal is received and cross-correlated with the original probe signal to obtain a correlation peak, which represents a time delay (roundtrip propagation time) associated with a mismatch. A matched filter implementation is also described in connection with FIG. 7. Direct Sequence Spread Spectrum, Frequency Hopped Spread Spectrum, and Zero Coding Spread Spectrum are listed as types of spread spectrum that could be used. This technique works well in the case where the digital data signal is fully random and its autocorrelation function approximates the Dirac delta function. But, the spectrum of service signals in the return path of an HFC cable television network contains a group of adjacent QAM signals separated by guard bands and also contains narrowband signals, such as set top box FSK signals. So, despite the random nature of each QAM signal, the autocorrelation function of a full return spectrum (to achieve optimal time resolution) will contain a number of high-level sidelobes which could mask the reflected signal. Another problem, as noted above, is potential interference by high-level service signals with the reflected signal. A further problem is that the return service signals may already be pre-corrected from PNM pre-equalization at the CM; thus, the autocorrelation function of these signals may contain extra peaks (caused by pre-equalization processing) and such peaks will produce false alarms (false detection) of impedance mismatches. Thus, the technique may not satisfy the need for an accurate, effective and reliable TDR test meter for the return path of an HFC cable television network.
As already suggested, the preferred approach to accurately pinpointing locations of micro-reflections in an HFC cable television network is to use a TDR meter in the field. Therefore, efforts have been made to develop handheld, battery-powered TDR test meters capable of being coupled to the network at an appropriate and convenient test point (e.g., amplifier test port). The meter is used to locate an impedance mismatch and, once a repair has been made, to confirm that the mismatch has been fixed. In the field, an opportunity may not be available to poll data from nearby CMs to determine the presence of micro-reflection distortion. Also, implementing a technique that captures the whole downstream signal in a handheld meter for analysis may not be cost effective, because high resolution analog-to-digital converter chips with 2 GHz plus sampling rates are needed to capture the downstream signal. The chips are still very expensive and have high power consumption (e.g., a few Watts). Further, to undertake the necessary signal processing of a full downstream spectrum, a powerful, high cost, high power-consuming, computer or processor would be required.
In view of the above discussion, it is apparent that a need exists for a non-invasive, low-cost, low power-consuming, handheld TDR meter for detecting micro-reflections and locating their cause in a live HFC cable television network.

Network traffic-compatible time domain reflectometer


A computer program product comprising computer-readable instructions that, when executed in a computer system including one or more computers, cause the computer system to generate or update a user interface of a software application, the computer program product including programmably interconnected objects, said objects including one or more model objects, one or more view objects, and one or more controller objects, wherein each model object is interconnected for data exchange with one or more view objects and/or with one or more controller objects; and each model object includes one or more sub-model objects including hierarchically structured data and representing a state of the user interface; and each view object is associated with at least one model object or at least one sub-model object and configured to generate the user interface or update the user interface in accordance with a change of the state.

A Graphical User Interface (GUI) software application may continuously update a representation of the software application state, whenever said state changes. A state may change in response to a user interaction with the user interface (UI) or in response to another external signal. A graphical user interface software application is a specific example of a user interface software application in general. The user may interact with other types of user interfaces, e.g., by way of haptic stimulus of the user, audio stimulus of the user, or the like.
A typical UI software application can handle many responsibilities which may include: Read a state from a persistent storage including de-serialize the state; hold a state in memory including, for example, the state of an opened document, the state of got data, or the state of UI elements, such as toolbar positions and scroll positions, and record the state history, for undo/redo functionality; write the state to persistent storage including serialize non-transient state; interface with the user including render an interactive graphical representation of the application state, and re-render whenever the software application state changes; react to user input by translating it into action message objects; behavior and business Logic customization including validate user input, in the form of action messages, handle action messages, by applying business logic which converts these into either side-effects or changes to the software application state, and allow third parties to customize the behavior and business logic, for example, to meet the user's personal preferences or the business rules of a corporation; and extensibility including standardize software application programming interface (APIs) for use by plugin modules, and facilitate the interoperability with other technologies and architectures.
It is desired to implement an UI software application that provides all of the above properties, especially including the more advanced ones, such as behavior and business logic customization, as well as extensibility and interoperability with other technologies and architectures.
Different software architectures for user interface software applications are already known. For example, the Model-View-View Model (MVVM) architecture is a modification of a Model-View-Controller (MVC) architecture. In the MVVM architecture, view objects (briefly: view/s) and model objects (briefly: model/s) do not know each other and are programmably connected via so called "bindings". Bindings connect parts of a model to parts of a view and can, essentially, be unidirectional and changes to the model may update the view. Bindings in the MVVM architecture can also be bidirectional which means that changes to the view update back the model. Control can be exerted by listening to change events of the model objects. By itself, the MVVM architecture provides no clear path for extensibility nor for control coordination. Additionally, there's no uniform notion of mutation nor the ability to centrally and generically modify what is going to be mutated from within a change event. Frequently, change events can only be cancelled in the MVVM architecture. Together, these characteristics result in controllers being scattered across models and in views which start being updated before the models have stabilized due to cascading changes and controls. This type of control and data flow is hard to reason about, debug and test. Hence, MVVM architectures have an inherent complexity which is often undesired.
Another type of architecture which applies a different "state store", which shall be understood as a single root model object preferably, is a variation of the MVC architecture, too. Sometimes this architecture is called "Uni-flow Architecture" employing a "uni-flow state store". This uni-flow architecture is implemented by known libraries, such as Redux and Flux. They are designed to work mostly within a unidirectional data flow architecture, for which a typical working example is as follows:                1. Action messages are dispatched to the state store.        2. The state store's controller (called a "reducer") processes the dispatched action messages by determining the new state of the state store.        3. The state store emits a "changed" event.        4. The view listens to the state store's "changed" event and re-renders in response.        5. The view translates user gestures into new action messages, dispatched to the state store.
The unidirectional data flow cycle is closed. The unidirectional flow makes it easier to reason about the behavior of the software application than the MVVM architecture. Testing is also less cumbersome with the uni-flow architecture. Typically, no direct references are held to a part of the state. Instead, a reference to the state store is kept and paths, called "selectors", are used to access parts/elements of the state. The fact that there is a single "change" event causes views to update all at the same time—at a time when all of the consequences of dispatching an action have been had. A single controller is associated with the state store. In other words, the uni-flow architecture owns some simplicity and functional style.
Notable differences between the uni-flow architecture and the MVVM architecture include:                a. State is concentrated within a state store.        b. There is a single way and point of entry for causing mutations: dispatching an action message to the state store.        c. There is a single controller, called a "reducer".        d. There is a single state "changed" event.
However, there are technical issues to be addressed associated with the uni-flow architecture, too. Parts of state may lose their identity. State is assumed to live in a closed, fixed, world, known a priori—there's no simple way to extend the structure of state or control with those of plugged-in modules; internal or from external parties. There's also no simple and general way to compose state stores, nor to integrate with components which follow different state management paradigms. In other words, there is a desire to improve especially modularity, composition and extensibility of the uni-flow architecture which maintains simplicity and unidirectional data flow.
Further points of desired improvement of the uni-flow architecture include that action messages are dispatched to the state store, the root, and then need to be internally dispatched to the actual target nodes/subtrees; this goes against modularization, abstraction, composability. Further, there's no ad hoc way to know the state changes to a certain level detail; it requires performing a tree difference operation with the previous state, every time. Further, the uni-flow architecture gives rise to boilerplate code needed to handle untyped objects, for building state objects and action messages. And, further, it may lead to scattered, harder to get information about the complete structure of state or action messages.

Method and computer program product for an UI software application


A composition having a bispecific antibody which binds a stem cell specific antigen and a tissue, differentiated cell or condition associated antigen and an agent that enhances expression of the tissue, differentiated cell or condition associated antigen, is provided. Also provided are methods of using the bispecific antibodies and/or agents to enhance cell therapy.

Stem/progenitor cell transplantation has emerged as a potential therapeutic modality for numerous conditions. For cardiac applications, cell injections have usually been accomplished under direct control through multiple epicardial punctures. However, to reduce the invasiveness of the procedure, percutaneous approaches are undergoing development. In the setting of these percutaneous techniques, the transvenous approach, using a specifically dedicated coronary sinus catheter, is particularly attractive because of its greater simplicity compared with the endoventricular route. Initial studies have established the effectiveness of bone marrow stem cell (BMC) transvenous transfer into the myocardium (Thomson et al., J. Am. Coll. Cardiol., 34:7514 (2002)). Intracoronary injections of bone marrow mononuclear cells concomitant with angioplasty at the acute stage of myocardial infarction (MI) have also shown promising results (Strauer et al., Circ., 106:1913 (2002); Assmus et al., Circ., 106:3009 (2002)).
More recent efficacy data from preliminary studies in which patients with an acute MI were treated by application of BMC showed a 7-9% improvement in global LV ejection fraction, as well as improvements in regional wall motion, perfusion, and LV end systolic volumes four to six months after intracoronary BMC transplantation (see Wollert et al., Circ. Res., 96:151 (2005); Haider et al., Am. J. Physiol. Circ. Physiol., 288:H2557 (2005); Dimmeler et al., J. Clin. Investig., 115:572 (2005)). In particular, the final one-year results of the TOPCARE-AMI trial, demonstrated a sustained improvement of LV function, reduced infarct size, and an absence of reactive hypertrophy after intracoronary BMC transplantation, suggesting functional regeneration of the infarcted ventricles and a prevention of remodeling (Schachinger et al., J. Am. Coll. Cardiol., 44:1690 (2004)). These findings are despite the observation that only 1.3-2.6% of the transplanted BMC are ultimately retained in the infarct after intracoronary transfer (Hofmann et al., Circ., 111:2198 (2005)).
However, most transplanted cells never initially engraft (Christman et al., J. Am. Coll. Cardiol., 44:465 (2004)), very few are viable within one week post injection (Gojo et al., Exp. Cell. Res., 288:51 (2003)), and the vast majority of transplanted cells die (Minami et al., J. Am. Coll. Cardiol., 41:1084 (2003)). Thus, regardless of the route of delivery, cell number and cell death remain major limitations of cell transplantation. For instance, it is uncertain whether multiplication of those that have survived can replace the high attrition rate.
What is needed is an improved method to enhance homing, engraftment and retention of transplanted therapeutic cells.

Bispecific antibodies and agents to enhance stem cell homing


A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.

The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package to which a fan-out packaging technique is applied and to a method of manufacturing the same.
Electronic products are required to process large amounts of data while being miniaturized. Accordingly, there is a growing need to increase the integration of semiconductor devices used in such electronic products. To this end, semiconductor chips are being stacked and electrically connected to one another using various packaging technologies. For example, semiconductor packages containing chips are stacked and electrically connected by wires in a process known as a wire bonding process. However, the use of a wire bonding process in this type of application requires the overall semiconductor package be rather thick, and it is difficult to stack more than 4 layers, and T-topology may appear when a redistribution layer is used for more than 2 loads. Recently, panel level package (PLP) and wafer level package (WLP) technologies for increasing integration and reducing unit cost are being researched and developed.

Semiconductor package and method of manufacturing the same