A method for playing a stand-alone and a bonus casino poker dice having X dice, each of the X dice having F faces with a different symbol thereon so as to form a set {S} of symbols on each of the X dice. The method of the present invention includes the steps of placing a wager; rolling the dice; holding none, any, or all of the rolled dice; ending the casino poker dice game when the dice are all held or when re-rolling occurs Y times; paying any winning combinations of symbols based on the placed wager and in response to the step of ending the game; re-rolling the non-held dice when less than all the X dice are held; and repeating various of these steps until the game ends. Variations on this basic method are set forth for stand-alone games, bonus games, used in conjunction with underlying gaming machines, and playing a bonus game of the present invention in parallel with an underlying game so that a number of hands are played.

1. Field of the Invention
This invention relates to betting games suitable for casino play and, more particularly, to poker dice casino games.
2. Statement of the Problem
The game of poker is typically played with a single deck of cards. In Stud Poker variations, each player receives a predetermined number of unique cards. In Hold""em Poker variations, community cards are utilized. In Draw Poker variations, players are given the opportunity to replace their cards from the unused pack. Cards need not be the only device which provides the means for rank and suit. Dice, too, have this feature.
In conventional poker dice, five poker dice whose six sides bear playing-card denominations (i.e., ace, king, queen, jack, ten and nine) are used. However, conventional dice can also be used in poker dice with ace being high followed by the numbers six, five, four, three, and two in that order. The one number may or may not be wild. In conventional play, after the first throw of the five dice, a player may stand pat or may draw (as in Draw Poker) by throwing one, two, or three dice again. The object of poker dice is to secure any combination such as five-of-a-kind, four-of-a-kind, full house, straight, three-of-a-kind, two pair, one pair. Scarne""s xe2x80x9cNew Complete Guide to Gamblingxe2x80x9d (1974).
Indeed, the popular game trademarked YAHTZEE by Hasbro, Inc. is basically a draw poker variation in which the players are allowed, twice, to xe2x80x9creplacexe2x80x9d existing rolls of five dice. Likewise, the casino games of Chuck-a-Luck and Sic Bo employ poker-like rankings with varying payoffs for obtaining one-, two-, or three-of-a-kind with a single roll of three dice. Likewise, the casino game of Craps refers to a pair occurring with the roll of two dice as xe2x80x9cthe hard wayxe2x80x9d and, for several wagers, differentiates this total from an xe2x80x9ceasyxe2x80x9d one. Some commercial recreational game products assign various card values to the faces of six-sided dice. These are used, in conjunction with subsequent rolls, to construct a xe2x80x9cpoker hand.xe2x80x9d
A continuing need exists for new casino games and, in particular, for modifications and improvements to poker, dice, and poker dice that can be used for wagering, bonusing, and/or as a payoff dispensing mechanism. A continuing need exists to provide new and exciting bonus conditions for players of underlying games.
A further need exists to adopt the conventional home game of YAHTZEE, and other similar home games to a gaming environment such as is found in casinos. In conventional YAHTZEE games, a hand is assigned a score which is entered onto a pad of paper called a xe2x80x9cscore cardxe2x80x9d and all scores entered are similar in size. In the YAHTZEE game, a xe2x80x9csmall straightxe2x80x9d box in the score card scores 30 points whenever four of the five rolled dice result in a sequence of four numbers. A xe2x80x9clarge straightxe2x80x9d box is scored 40 points whenever all five of the rolled dice result in a sequence of five numbers. The YAHTZEE box is scored 50 points when the five rolled dice show xe2x80x9c5 of a Kind.xe2x80x9d A xe2x80x9cchancexe2x80x9d box is scored when the player chooses to sum the values of the five dice together. In the YAHTZEE game, each player is allowed a maximum of three rolls although the player may stop after the first or second roll. For the second and third rolls, the player may selectively hold none, any or all the dice. A need exists in a corresponding casino game based on the YAHTZEE game to provide a broad range of payoffs from small to jackpot amounts. In conventional YAHTZEE games some scores are fixed (e.g., 30 points) and other scores are variable (e.g., sum of dice). A need exists in a corresponding casino game to simplify the scoring so as to eliminate any confusion especially for new players. In a YAHTZEE game one hand occurs quickly and a typical game of thirteen hands is lengthy. A need exists in a corresponding casino game to adapt the length of the game to be comparable to other conventional casino games. A conventional YAHTZEE game also requires skill by a player. A need exists in a corresponding casino game to play the game with no skill, but retain suspense and excitement. Finally, need exists to adopt a popular game such as YAHTZEE to a wagering game providing a fair house advantage to the casino.
1. Solution to the Problem
The present invention solves the above problems by providing (1) methods for wagering on and playing a poker dice game, (2) methods for providing bonusing games for underlying casino games, and (3) methods for dispensing payoffs.
The present invention also solves the above problems by providing a method for wagering on and playing a casino poker dice game either as a stand-alone game or as a bonus game for an underlying gaming machine. In a preferred method of play suitable for video adaptation as a bonus game for a gaming device, money, gaming chips, credits, or their equivalent may be wagered. Buttons, either on screen or adjacent to the monitor, are provided for players to indicate their choices. An executable computer software program, or a hardware equivalent such as an EPROM, brokers the casino game of the present invention according to the rules of play. A number of bonusing conditions initiate the bonus game of the present invention which can also be used to initiate other types of bonus games. In a second preferred method of play, a game table or a gaming machine is used to play the poker dice game as a stand-alone game.
The present invention, in part, adapts the conventional home game of YAHTZEE to the casino environment as a bonusing game in a variety of embodiments. The present invention differentiates hands and assigns payoff values in a broad range from minimal values to jackpot values. The payoff values provide clarity in that the payoff values are all fixed or all variable. The length of the casino game varies under different embodiments of the present invention. A one-hand version of the game is designed for players experienced in the standard YAHTZEE game. Another version of the game of the present invention is designed to play successive hands in order to avoid chance. And a third version of the game of the present invention provides a limited score card. Finally, the present invention provides a casino game in which no skill is involved, but which provides moves that build suspense and retain excitement.
2. Summary of the Invention
A method for playing a stand-alone and a bonus casino poker dice having X dice, each of the X dice having F faces with a different symbol thereon so as to form a set {S} of symbols on each of the X dice. The method of the present invention includes the steps of placing a wager; rolling the dice; holding none, any, or all of the rolled dice; ending the casino poker dice game when the dice are all held or when re-rolling occurs Y times; paying any winning combinations of symbols based on the placed wager and in response to the step of ending the game; re-rolling the non-held dice when less than all the X dice are held; and repeating various of these steps until the game ends. Variations on this basic method are set forth for stand-alone games, bonus games used in conjunction with underlying gaming machines or games, and playing a bonus game of the present invention in parallel with an underlying game so that a number of hands are played.


With a variable valve timing system, engine operability may be lost when performing open control of lift characteristic amounts to the minimum or the maximum of a variable range when a sensor error occurs. The present invention provides a lift operation angle changing mechanism that can continuously change intake valve lift amount and operation angle within a prescribed variable range. A target operation angle is calculated based on the number of engine revolutions and the accelerator pedal opening APO. An error is determined for the operation angle sensor that detects the actual operation angle. A normal control amount is calculated based on the target operation angle and the actual operation angle, and a failure control amount is calculated based on the number of engine revolutions. Therefore, an intermediate value within the variable range can be obtained as the failure control amount. The normal control amount is output to actuator 51 under normal operation, and the failure control amount is output to actuator 51 when an error occurs.

In the field of internal combustion engines for automobiles, a variety of variable valve mechanisms have conventionally been proposed, with changeable lift characteristic amounts such as the intake/exhaust valve lift amount, operation angle, and valve timing. Additional background on variable valve timing is described in Unexamined Japanese Patent Application Publication No. 2002-54466 and in U.S. Pat. No. 6,843,226, titled "Intake control apparatus for internal combustion engine," issued on Jan. 18, 2005, both of which are commonly assigned.
Feedback control is preferably performed based on the detected value of lift characteristic amounts to maintain lift characteristic amounts at their target values with good precision. As described in said Unexamined Japanese Patent Application Publication No. 2002-54466, such feedback control technology is commonly known. Simply explained, target values for the lift characteristic amounts are calculated according to the engine operating conditions (load, number of revolutions, etc.), detection values equivalent to the actual lift characteristic amount values are obtained using an appropriate sensor, and the command value for the variable valve mechanism actuator is calculated based on the deviation of these target values and detection values.
However, if feedback control is continued during a sensor error when the detection values cannot be accurately obtained due to sensor failure or error, the actual lift characteristic amount can be vastly different from the target value, and the risk of losing engine operability occurs. Therefore, in said Unexamined Japanese Patent Application Publication No. 2002-54466, when a sensor error occurs, the system switches to an open control toward the maximum or minimum side of the variable range for the lift characteristic amounts.

Variable valve mechanism control device and control method


A semiconductor memory device and a method for manufacturing the same are provided. The semiconductor memory device includes an oxide layer for isolating individual devices which define device areas so that a cell area and a peripheral circuit area are separated from each other on a semiconductor substrate, a plurality of MOS transistors, which are comprised of source areas, drain areas, and gates that are formed in the cell area and the peripheral circuit area, a bit line, which is formed on the plurality of MOS transistors and is electrically connected to the MOS transistor, a stack-shaped capacitor, which is comprised of a first electrode, a dielectric layer, and a second electrode between which the MOS transistors and the bit line in the cell area is interposed, a guard-ring pattern, which are interposed between the cell area and the peripheral circuit area, surrounds the cell area and is apart from the peripheral circuit area, and a contact fill for plate electrode, which is formed in the guard-ring pattern and is in contact with the second electrode that is formed on the internal sidewall and the bottom of the guard-ring pattern. The guard-ring pattern is formed in a boundary between the cell area and the peripheral circuit area while surrounding the cell area, and thereby step caused by manufacture of the stack-shaped capacitor are removed during a manufacturing process, and the contact fill for plate electrode is formed in the guard-ring pattern, and thereby the ground resistance of the capacitor is reduced, and the electrical characteristics of the memory device are improved.

This application claims priority under 35 U.S.C. xc2xa7119 from Korean Patent Application No. 2002-2509, filed on Jan. 16, 2002, the entirety of which is hereby incorporated by reference as if fully set forth herein.
1. Field of the Invention
The present invention relates to a semiconductor memory device and method for manufacturing the same, and more particularly, to a dynamic random access memory (DRAM) having a stack-shaped capacitor and a method for manufacturing the same.
2. Description of the Related Art
A dynamic random access memory (DRAM) among semiconductor memory devices is comprised of one transistor and one capacitor. Thus, in order to serve as a memory device, the DRAM must have sufficient capacitance. There is no problem when the design rule of the memory device is wide. However, as the memory device becomes highly integrated, its design rule becomes extremely dense and an area for each memory device becomes narrower, and thus, area per cell also decreases. A stack-shaped capacitor has been developed to obtain sufficient capacitance as the area becomes narrower. The stack-shaped capacitor can increase a surface area by forming an electrode with high depth even though the occupied area of the capacitor decreases. Thus the required capacitance of the capacitor can be obtained even though the design rule of the memory device becomes finer. However, in the stack-shaped capacitor, when the stack-shaped capacitor forms a storage node, a step between the cell area and a peripheral area becomes very severe. As a result, a metal interconnection process cannot be performed well due to an extreme pattern-thinning phenomenon caused by diffraction and irregular reflection of light, which is exposed due to a high step between a cell area and the peripheral area during a subsequent photolithographic process for metal interconnections in a case where a predetermined planarization process is not performed.
Thus, in a conventional planarization process between the cell area and the peripheral area, a very thick interlayer dielectric (ILD) film is formed on the surface of a semiconductor substrate after a capacitor process is completed. The cell area having a high step is opened after a predetermined photolithographic process, and then, the ILD film in the cell area is etched to a predetermined thickness through dry etching, and thereby removed. Then, the step between the cell area and the peripheral area is slightly decreased. The thick ILD film is again formed on the surface of the semiconductor substrate and is polished and removed and thereby planarized to enable the metal interconnection process on the entire surface of the semiconductor substrate through chemical mechanical polishing (CMP).
However, the photolithographic process for opening the cell area and a dry etching process is added to the conventional planarization process between the cell area and the peripheral area, and an additional planarization process using CMP is accompanied by a subsequent process, thus increasing the number of processes. Moreover, the photolithographic process and the CMP process are included, and thus the reliability of production is reduced, and the period of a manufacturing process becomes longer, and costs increase.
To solve the above problems, it is an object of the present invention to provide a semiconductor memory device and a method for manufacturing the same in which manufacturing processes are simplified, and a wide contact area is formed on a plate electrode for serving as the ground electrode of a capacitor so that a step between a cell area of a semiconductor chip and a peripheral area formed by a capacitor formed in the cell area is effectively decreased, thereby greatly reducing ground resistance, thus improving the electric characteristics of a memory device.
Accordingly, to achieve the above object, according to one embodiment, there is provided a semiconductor memory device. The semiconductor memory device includes an oxide layer for isolating individual devices which define device areas so that a cell area and a peripheral circuit area are separated from each other on a semiconductor substrate. The semiconductor memory device also includes: a plurality of MOS transistors, which are comprised of source areas, drain areas, and gates that are formed in the cell area and the peripheral circuit area; a bit line, which is formed on the plurality of MOS transistors and is electrically connected to the MOS transistors; a stack-shaped capacitor, which is comprised of a first electrode, a dielectric layer, and a second electrode between which the MOS transistors and the bit line in the cell area are interposed; a guard-ring pattern, which is interposed between the cell area and the peripheral circuit area; surrounds the cell area and is apart from the peripheral circuit area, and a contact fill for a plate electrode, which is formed in the guard-ring pattern and is in contact with the second electrode that is formed on the internal sidewall and the bottom of the guard-ring pattern.
The first electrode of the stack-shaped capacitor is electrically connected to the source areas and has a hollow cylindrical shape so that the area of a capacitor per area is increased, and capacitance is maximized. The first electrode is conductive polycrystalline silicon (polysilicon) such as an impurity-doped polycrystalline silicon, and further includes a barrier layer such as platinum (Pt), RuO, Rb, and RbO. The dielectric layer may be a combination layer of a silicon oxide layer and a silicon nitride layer, but is preferably formed of a high dielectric material that is at least one selected from Ta2O5, PZT, PZLT, BST, and Al2O3, such that the capacitance of the capacitor is increased for a given area.
The second electrode is formed in a block form to overlap a predetermined region adjacent to the peripheral circuit area including the entire cell area, and the second electrode is conductive polysilicon, such as an impurity-doped polysilicon, and the second electrode further includes a barrier layer, thereby preventing impurity atoms constituting a high dielectric layer from penetrating into junctions that are formed on a lower portion of the semiconductor memory device and thereby deteriorating electrical characteristics.
The guard-ring pattern is formed on the same surface as the bottom of the first electrode, and the second electrode is extended to the edge of the cell area on the bottom of the guard-ring pattern. At least a part of the contact fill for the plate electrode is electrically connected to the second electrode in the guard-ring pattern. The contact fill for the plate electrode includes a tungsten fill that is formed of tungsten in the center, and barrier metal that is formed outside of the tungsten fill adjacent to a recessed portion, thereby preventing the formation of fluoric components that penetrate into a lower MOS transistor from a tungsten (W) layer, which is a filling metal layer. The barrier metal is a combination layer of Ti and TiN.
To achieve the above object, according to another embodiment, there is provided a method for manufacturing a semiconductor memory device. A cell area is separated from a peripheral circuit area on a semiconductor substrate to form device active areas. A plurality of MOS transistors are formed in the device active areas of the cell area and the peripheral circuit area. A first interlayer dielectric (ILD) film is formed on the semiconductor substrate and a first electrode pattern and a guard-ring pattern surrounding the cell area are formed on the first ILD film. A conductive layer for a first electrode and an insulating layer for patterning are sequentially formed on the first electrode pattern and the guard-ring pattern. The entire cell area and a part of the guard-ring pattern are opened, and the conductive layer for the first electrode and the insulating layer for patterning are removed to the first ILD film, and a first electrode node in the cell area is formed. The insulating layer for patterning that is filled in the first electrode node is removed.
A dielectric layer and a conductive layer for a second electrode are formed on the semiconductor substrate. A pattern for the second electrode is formed on the conductive layer for the second electrode. A contact fill for a plate electrode is formed while being in contact with the second electrode that is formed on the sidewall and the bottom of the guard-ring pattern.
That is, in order to define the device active areas on the semiconductor substrate, the semiconductor substrate is partially recessed to a predetermined depth and forming a trench, and a silicon insulating layer is filled in the trench. Then, a gate insulating layer is formed on the device active areas, and a gate conductive layer is formed on the gate insulating layer. A mask insulating layer is formed on the gate conductive layer. In this case, preferably, the gate conductive layer is conductive polysilicon such as an impurity doped polysilicon or polycide, which is combined with metal silicide, thereby improving the conductivity of the gate. Then, a gate pattern is formed on a mask insulating layer and a gate conductive layer through a photolithographic process, and an insulating layer for a sidewall spacer is formed on the sidewall of the gate pattern, thereby completing a gate process. Then, source and drain junctions are formed by an ion implantation method using the gate as a mask. Here, the insulating layer for the sidewall spacer is a silicon nitride layer, thereby increasing dry etch selectivity with a silicon oxide layer when a self-aligned contact is formed. The source and drain areas form an N-type junction in the cell area, and form N-type and P-type junctions in the peripheral circuit area. A silicon insulating layer is formed, and a bit line conductive layer that is formed of polysilicon such as an impurity doped polysilicon and metal silicide, and a mask insulating layer for self-alignment that is formed of silicon nitride are formed on the silicon insulating layer. A bit line pattern is formed on the bit line conductive layer and the mask insulating layer for self-alignment, and then, an insulating layer spacer that is formed of silicon nitride is formed on the sidewall of the bit line pattern. In a case where the silicon insulating layer is formed, and the self-aligned contact is formed, the mask insulating layer and the insulating layer spacer that are formed of silicon nitride serve as a mask for dry etching.
A capacitor contact that is connected to the source area of the MOS transistor is formed to be electrically connected to the MOS transistor using a self-alignment method, and a capacitor contact pad is formed by filling a conductive layer in the capacitor contact. A first ILD film is thickly formed on the semiconductor substrate, and a photoresist is formed on the first ILD film.
A first electrode pattern is formed in the cell area in the photoresist and a band-shaped guard-ring pattern is formed in a boundary between the cell area and the peripheral circuit area while surrounding the cell area. In this case, the first ILD film includes a silicon nitride layer as an etch stopper in a lower portion of the first ILD film, and includes a silicon oxide layer that is formed on the etch stopper. As a result, another layer may be used as an etch stopper when a subsequent etching process having high selectivity is performed, and the silicon nitride layer, which is an etch stopper, is formed to be much thinner than the silicon oxide layer, thereby increasing the capacitor area after the silicon oxide layer is removed. Then, a first electrode pattern is formed in the cell area on the first ILD film through dry etching using the patterned photoresist as a mask, and a guard-ring pattern is formed in a boundary between the cell area and the peripheral circuit area while surrounding the cell area.
A conductive layer for a first electrode that is conductive polysilicon, such as an impurity doped polycrystalline silicon, and an insulating layer for patterning that is formed of silicon oxide by chemical vapor deposition (CVD) are sequentially formed in the first electrode pattern and the guard-ring pattern. Here, the insulating layer for patterning is formed in particular through plasma-enhanced CVD (PE CVD) using plasmas having a high deposition rate and a high etching rate in an etching solution. In this case, the conductive layer for the first electrode further includes a barrier layer that is one selected from TiN, RuO, Pt, Rb, and RbO, thereby preventing impurities that are contained in materials to be used later as a dielectric layer from into the MOS transistor and from deteriorating the electrical characteristics of the semiconductor memory device.
A photoresist is formed on the insulating layer for patterning, and a cell opening pattern is formed in the photoresist so that the peripheral circuit area is blocked and only the cell area is opened. The second insulating layer and the conductive layer for the first electrode are sequentially etched and removed through dry etching using the cell open pattern as a mask, thereby forming a first electrode node of the capacitor. The first electrode node is formed in the cell area, and the conductive layer for the first electrode is left in the peripheral circuit area, thereby protecting the first ILD film.
The insulating layer for patterning is wet etched and removed with an etching solution. Beneficially, the etching solution is a silicon oxide etchant containing hydrofluoric acid (HF) and buffered oxide etchant (BOE). As a result, the silicon nitride layer which composes the lower portion of the first ILD film is an etch stopper in the cell area, and polysilicon which composes the conductive layer for the first electrode is an etch stopper in the peripheral circuit area and the guard-ring pattern, thereby forming the first electrode node in the cell area, and the first ILD film that is formed of silicon oxide to the height of the first electrode is protected in the peripheral circuit area.
A dielectric layer is formed on the exposed surface of the first electrode node, and a conductive layer for a second electrode is formed on the dielectric layer so that the inside of the first electrode node is filled. In this case, the dielectric layer is formed of at least one selected from silicon nitride, silicon oxide, and a high dielectric material, and the high dielectric material is one selected from Ta2O5, Al2O3 and PZT, PLZT, and BST as perovskite-family ferroelectric materials. The conductive layer for the second electrode is conductive polysilicon, such as an impurity-doped polysilicon, and the conductive layer for the second electrode further includes a barrier layer, thereby preventing impurities from penetrating into a layer at an external side in a case where the dielectric layer is a high dielectric layer.
A photoresist is formed on the conductive layer for the second electrode, and a second electrode pattern having a block shape is formed in the photoresist so that a part of the second electrode pattern partially overlaps the peripheral circuit area including the cell area and the guard-ring pattern. The conductive layer for the second electrode, the dielectric layer and the conductive layer for the first electrode remaining in the peripheral circuit area are etched through dry etching using the patterned photoresist as a mask.
A second ILD film that is formed of silicon oxide through CVD is formed on the entire surface of the semiconductor substrate. A photoresist is formed on the second ILD film, and a contact pattern for a plate electrode having a block shape is formed in the photoresist to be larger than the actual size of an area where it overlaps the guard-ring pattern. The second ILD film in the guard-ring pattern is dry etched and completely removed by using the patterned photoresist as a mask, and a contact for the plate electrode is formed so that the sidewall and the bottom of the second electrode in the guard-ring pattern are completely exposed. Then, a contact filling conductive layer is formed of tungsten (W), and the contact filling conductive layer is removed evenly to the second ILD film, thereby forming a contact fill for the plate electrode. In this case, the contact filling conductive layer further includes Ti and TiN as a barrier layer.
In the semiconductor memory device and the method for manufacturing the same as disclosed herein, the guard-ring pattern is formed in a boundary between the cell area and the peripheral circuit area while surrounding the cell area, and thereby a step caused by manufacturing the stack-shaped capacitor is removed during a manufacturing process. In addition, the contact fill for the plate electrode is formed in the guard-ring pattern through a self-aligned contact method, and thereby the contact for the plate electrode is in direct contact with the bottom and the sidewall of the second electrode as a ground electrode. Thus, the contact area is increased greatly, the contact resistance is substantially reduced, and the electrical characteristics of the memory device are more stabilized.

Semiconductor memory device and method for manufacturing the same


Embodiments of the present invention include a method and system for control of a multiple-input-single output (MISO) device. For example, the method includes determining a change in power output level from a first power output level to a second power output level of the MISO device. The method also includes varying one or more weights associated with respective one or more controls of the MISO device to cause the change in power output. The one or more controls can include one or more of (a) a phase control of one or more input signals to the MISO device, (b) a bias control of the MISO device, and (c) an amplitude control of the input signals to the MISO device.

1. Field
Embodiments of the present invention relate generally to RF (radio frequency) power transmission, modulation, and amplification.
2. Background
Today's RF power amplifiers are required to generate complex RF signals with stringent output power and linearity requirements. For example, in order to comply with the requirements of a WCDMA waveform, a power amplifier needs to support approximately 30-40 dB of instantaneous output power dynamic range at a given power output level. This is mainly due to the ACPR (Adjacent Channel Power Ratio) and the ACLR (Adjacent Channel Leakage Ratio) requirements of the WCDMA waveform, which require very deep nulls as the output power waveform crosses zero,
Generally, the ACLR and ACPR that a power amplifier can achieve are related to the linearity of the power amplifier over the output power range of the desired waveform, Modern RF waveforms (e.g., OFDM, CDMA, WCDMA, etc.) are characterized by their associated PAP (Peak-to-Average Power) ratios. As such, in order to generate such waveforms, the power amplifier needs to be able to operate in a largely linear manner over a wide output power range that encompasses the output power range of the desired waveforms.
Outphasing amplification or LINC (Linear Amplification with Nonlinear Components) provides an amplification technique with the desirable linearity to amplify RF waveforms with large PAP ratios. Outphasing works by separating a signal into equal and constant envelope constituents, linearly amplifying the constituents, and combining the amplified constituents to generate the desired output signal. To preserve linearity when combining the amplified constituents, existing outphasing techniques use an isolating and/or a combining element, which provides the needed isolation between the branches of the outphasing amplifier to reduce non-linear distortion.
In several respects, however, existing outphasing techniques are not suitable for implementation in modern portable devices. For example, the isolating and/or combining element that they use causes a degradation in output signal power (due to insertion loss and limited bandwidth) and, correspondingly, low power amplifier efficiency. Further, the typically large size of isolating/combining elements precludes having them in monolithic amplifier designs.
There is a need therefore for outphasing amplification systems and methods that eliminate the isolating/combining element used in existing outphasing techniques, while providing substantially linear amplification over a wide output power dynamic range to support modern RF waveforms

Systems and methods of RF power transmission, modulation, and amplification, including varying weights of control signals


An antenna apparatus including: a first and second antenna elements which transmit or receive radio signal; a ground pattern; and a wiring pattern which is provided on a line segment connecting the first and second antenna elements, and directly connected to the ground pattern, wherein a circumventing path is formed by the wiring pattern and a part of the ground pattern.

For example, there is a diversity antenna as an antenna apparatus such that same radio signal is received by two antennas, and the signal received from the antenna with superior radio wave condition is preferentially used.
Further, for example, a multimode antenna structure is known in which, by connecting a conductive connection element between two antenna elements, current flowing to feed point of one of two antenna elements is shunted, and the two antenna elements are electrically isolated.
Further, for example, an integrated-type flat-plate multi-elements and electronic equipment are also known in which, by forming a cutout unit in end of a ground pattern, coupling coefficient between two antenna elements can be lowered.
Further, for example, a compact-type portable terminal apparatus for radio reception is also known in which a variable reactance or switch is provided in a concave portion cut out in an edge of an upper grounding conductor, and by the switch or variable reactance, correlation is lowered between antenna elements provided in tip portion of a plurality of convexes on the upper grounding conductor.
Patent Document 1: International Publication Pamphlet No. WO 2008/131157 A1
Patent Document 2: Japanese Laid-open Patent Publication No. 2007-13643
Patent Document 3: Japanese Laid-open Patent Publication No. 2007-243455
However, in the above-described technology of the prior art, when the connection element is directly connected between two antenna elements, characteristic of the antenna element changes. Hence, by further providing a matching circuit in the antenna apparatus, the antenna apparatus can correspond to change of characteristic and can keep reception or transmission frequency within a prescribed range. However, when the matching circuit is further provided in the antenna apparatus, the number of components increases to this extent, and setting space of various elements and similar within the antenna apparatus is reduced. The increase in the number of components or reduction in setting space renders difficult achievement of reduced space or smaller size for the antenna apparatus.
Further, in the above-described technology of the prior art, when the cutout portion is provided in the end of the ground pattern or the concave portion is provided in the upper grounding conductor, if the area of the cutout or concave portion is equal to or greater than a predetermined value, the setting space of various elements or similar set on the ground pattern is reduced by the amount of the cutout or concave portion.
On the other hand, by making the characteristic of the antenna element such as the coupling coefficient, correlation, or similar between antenna elements equal to or greater than a predetermined value, reception characteristic of the antenna apparatus and similar can be improved as well.

Antenna apparatus and radio terminal apparatus


An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a high-speed interface circuit block HB which transfers data through a serial bus using differential signals, and a circuit block other than HB. The high-speed interface circuit block HB is disposed as an Mth circuit block CBM (2≦M≦N−1) of the circuit blocks CB1 to CBN.

The present invention relates to an integrated circuit device and an electronic instrument.
In recent years, a high-speed serial transfer interface such as low voltage differential signaling (LVDS) has attracted attention as an interface aiming at reducing EMI noise or the like. In such a high-speed serial transfer, a transmitter circuit transmits serialized data by using differential signals, and a receiver circuit differentially amplifies the differential signals to realize data transfer (JP-A-2001-222249).
A portable telephone generally includes a first instrument section provided with buttons for inputting a telephone number or characters, a second instrument section provided with a display panel or a camera, and a connection section such as a hinge which connects the first and second instrument sections. Therefore, the number of interconnects passing through the connection section can be reduced by transferring data between a first substrate provided in the first instrument section and a second substrate provided in the second instrument section by serial transfer using differential signals.
A display driver (LCD driver) is an integrated circuit device which drives a display panel such as a liquid crystal panel. In order to realize the high-speed serial transfer between the first and second instrument sections, a high-speed interface circuit which transfers data through a serial bus must be incorporated in the display driver.
However, when mounting the integrated circuit device as the display driver by using a chip-on-glass (COG) technology, the high-speed serial transfer signal quality deteriorates due to contact resistance of a bump as an external connection terminal.
A reduction in chip size is required for the display driver in order to reduce cost. However, the size of the display panel incorporated in a portable telephone or the like is almost constant. Therefore, if the chip size is reduced by merely shrinking the integrated circuit device as the display driver by using a microfabrication technology, it becomes difficult to mount the integrated circuit device.

Integrated circuit device and electronic instrument


An apparatus for use in packaging containers and associated lids together includes a moveable gantry with a first support portion and a second support portion alongside the first support portion. The first and second support portions are sized and configured to support the containers and the lids. A container path and a lid path are included along which containers and lids, respectively, are directed to the gantry. The gantry has a first orientation in which the first support portion is aligned with the container path to receive containers and the second support portion is aligned with the lid path to receive lids. The gantry also has a second orientation in which the gantry is repositioned such that the first support portion is aligned with the lid path to receive lids and the second support portion is aligned with the container path to receive containers.

Cups are typically packaged for retail or commercial sale as nested stacks of cups. For example, it is not unusual to provide cups nested in two stacks (e.g., of 10 cups each for a total of 20 cups) within a plastic bag for retail sale, for example, in a grocery store, supermarket, gas station, etc.
Automated processes and machines have been provided to sort and arrange the cups into the nested stacks for packaging. Additionally, processes and machines have been proposed to handle nested stacks of cups. For example, a holding mechanism has been proposed having suction chambers with a lower suction opening for engaging a cup stack by negative pressure. The holding mechanism can be used to remove the cups stacks from a transport container.

Packaging machine for packaging containers and lids


A method of presenting an interactive user interface includes presenting member data within a social network interface, the member data being presented at a fixed position within the social network interface. A plurality of posts, arranged in a temporal order or according to category, are also presented within the social network interface. Further, a privacy bar interface element is presented at a first position within the social network interface. An action, as applied to a touch display of a client device, is detected, the action being to move the privacy bar interface element from the first position to a second position relative to the plurality of posts within the social network interface, and to divide the plurality of posts within the social network interface into a first subset of posts and a second subset of posts. First and second social profile access privileges are applied to the respective first and second subsets of posts responsive to the detecting of the action to move the privacy bar interface element from the first position to the second position, the first and second social profile access privileges being different from each other.

A social network service is an online service, platform or site that facilitates the building and maintenance of social relations among individuals. Each member of a social network service maintains a profile with user information and user posts, which may be comments, photographs, videos, endorsements and the like. The posts may be from the user and/or individuals that the user is affiliated with in the social network. In this way, social network sites allow users to share ideas, activities, events and interests with affiliated individuals.
Privacy is a growing concern with social networks. Information posted by a user or an affiliated individual may be distasteful or become outdated. The user may desire to restrict access to certain information on their profile while allowing access to other information. While most social networks have configurable privacy control settings, such privacy control settings may be hard to find and in many instances they are confusing, resulting in an unintended access to information. Given that users are generally able to see all of the content that they have contributed to their profile, it can be difficult to determine what content is visible to others and what is visible only to the user.
Accordingly, improved techniques for controlling social network profile access are desirable.

Interactive user-interface to adjust access privileges


Embodiments generally relate to summarizing a photo album in a social network system. In one embodiment, a method includes grouping photos into a plurality of groups of photos, and selecting a plurality of representative photos, where each representative photo represents a respective group from the plurality of groups, where the selecting is based on a quality score of each of the photos, and where each quality score is based on different types of attributes. The method also includes enabling the plurality of representative photos to be shared.

Social network systems often enable users to upload photos and create photo albums that contain the uploaded photos. After a user uploads photos to a social network system, the social network system typically enables the user to create one or more photo albums. The user can then determine which photos to include in each of the photo albums. The social network system typically enables the user to share the photo album with other users of the social network system. For example, a user may allow other users to access and view photos in particular photo albums.

Summarizing a photo album in a social network system


A processing node, a computer system, and a transaction conflict detection method, where the processing node includes a processor and a transactional cache. When obtaining a first operation instruction in a transaction for accessing shared data, the processor accesses the transactional cache for caching shared data of a transaction processed by the processing node. If the transactional cache determines that the first operation instruction fails to hit a cache line in the transactional cache, the transactional cache sends a first destination address in the operation instruction to a transactional cache in another processing node. After receiving status information of a cache line hit by the first destination address from the other processing node, the transactional cache determines, based on the received status information, whether the first operation instruction conflicts with a second operation instruction executed by the other processing node.

Transactional memory is a concurrent programming manner in a computer architecture, and is used to implement consistency of data shared by a plurality of processes. A transaction originates from a concept of transaction in a database management system (DBMS). A transaction is an instruction series, including a read operation and a write operation on storage. In the DBMS, the transaction needs to meet atomicity, consistency, isolation, and durability. Atomicity states that either all actions in the transaction are performed, or none are performed. Consistency states that a database needs to be in a consistent state at any time, that is, needs to meet some preset conditions. Isolation states that a status of an internal object in a transaction that is not committed is not visible to another transaction. Durability states that a change made to a database system by a committed transaction is permanent. A key of the transactional memory is to provide a critical region operation that has atomicity, consistency, and isolation such that a plurality of processes can securely access shared data without using a lock. Currently, the transactional memory has two implementations software transactional memory (STM) based on software and hardware transactional memory (HTM) based on hardware.
HTM in other approaches is generally implemented on a level 1, level 2, or level 3 cache of a central processing unit (CPU). For example, transaction conflict detection and transaction rollback mechanisms are implemented by adding a dedicated cache mechanism in the level 1 cache (also referred to as L1 cache). Further, during access of a process, whether a cache line is being operated by another process is determined by tracking all cache lines that are read or written during execution of a transaction. When it is detected that the transaction of the process conflicts with a transaction of the other process, execution of the transaction needs to be terminated. The cache line is used to indicate a segment of consecutive addresses, and the cache line may also be referred to as a data block. In some computer systems, a size of a cache line is 64 bytes. Because tracking detection is performed on all operated cache lines in such an implementation of the transactional memory, high system power consumption is caused. In addition, a detection granularity is relatively coarse, easily causing misdetection.

Processing node, computer system, and transaction conflict detection method


An electronic device with a display concurrently displays a device status region, and an application user interface that includes a content region and an application input field. While concurrently displaying the device status region and the application user interface, the device receives first input in the application input field. In response, the device concurrently displays respective content in the content region in accordance with the first input, and first text that corresponds to the first input in the application input field. While concurrently displaying the respective content and the first text, the device detects a second input that corresponds to a request to scroll the respective content in a first direction. In response, the device scrolls the respective content in the first direction, ceases to display the application input field, and displays, adjacent to the device status region, the first text.

The use of touch-sensitive surfaces as input devices for computers and other electronic computing devices has increased significantly in recent years. Exemplary touch-sensitive surfaces include touch pads and touch screen displays. Such surfaces are widely used to view and navigate content on a display. For example, a user can view and navigate content in a web browser application on the device. The web browser application typically includes one or more areas adjacent to the web page content that display application information, such as a status/input bar/field.
Application status bars serve useful functions, such as accepting input and displaying information about the application content being viewed. But these bars can take up valuable screen space, leaving less space for the content that the user wants to view. Particularly on portable devices, on which screen space is at a premium, status bars that take up too much screen space can degrade the user experience.

Device, method, and graphical user interface for displaying application status information


Provided is a quality-of-service (QoS)-guaranteed video stream method. The QoS-guaranteed video stream method includes transmitting, by a transmitting server, a video stream including different video stream data for a plurality of respective layers, to a relay server, receiving, by the transmitting server, first section network state information which is information about a network state between the relay server and the transmitting server, from the relay server, receiving, by the transmitting server, second section network state information which is information about a network state between the plurality of respective user terminals and the transmitting server, and adjusting, by the transmitting server, qualities of video streams which are transmitted to the plurality of respective user terminals through the relay server by using network state information of the first section and network state information of the second section.

1. Field of the Invention
The present invention relates to a QoS-guaranteed video stream method and system, and a transmitting server, and more particularly, to a QoS-guaranteed video stream method and system, and a transmitting server capable of guaranteeing QoS in a scheme of providing a video stream by using a plurality of layers.
2. Description of the Related Art
Along with development of a mobile device and a mobile network, a mobile voice over internet protocol (VoIP) service, through which images are exchanged between a plurality of users in real time by using a mobile device, is getting popular. Further, a real time streaming service such as a professional baseball game live broadcast in a mobile device is also getting popular.
A scalable video codec (SVC) may be user to transmit a video stream to a plurality of users. A scalable video codec such as H.264 SVC may form one video stream with a plurality of layers so as to be transmitted.
According to the technology of providing a video stream by using a SVC, a transmitting server transmits one video stream to a relay server, and a plurality of user terminals connect to the relay server and receive the video stream.
The technology of providing a video stream by using a SVC according to a conventional art transmits a video stream which is optimized in a network situation between a transmitting server and a relay server. Hence, the image quality of the layer received by the user terminal may provide only a scheme of selecting one layer from among video streams having the image quality for each defined layer based on the network situation between the transmitting server and the relay server. That is, there is a limit that the network state between the user terminal and the relay server does not affect the quality of the video stream which is transmitted by the transmitting server.

QoS-guaranteed video stream method and system, and transmitting server


A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.

Gallium Nitride (GaN) technology has widely been identified as a preferred high voltage (>600 V) power electronics technology due to its inherent high Johnson limit, which is a relationship between cutoff frequency (fT) and breakdown voltage. Quantitatively, the Johnson limit is a product of fT and breakdown voltage for a particular semiconductor technology such as GaN technology. The Johnson limit for GaN technology is significantly improved over the Johnson limit for silicon technology. As a result, GaN technology is being developed to realize relatively very compact and efficient switching regulators that require small passive filter elements in comparison to silicon technologies. However, challenges remain in utilizing GaN technology for compact and efficient switching regulators as well as other commercial applications. Some of the challenges include achieving low cost, normally off operation, low leakage of drain-to-source current (Ids) and low gate leakage current (Igate), as well as low channel on-resistance (R-on).
Moreover, greater than 600 V power electronic GaN switching transistor devices require low Ids leakage current under a high drain-to-source voltage (Vds) condition. A typical power electronic GaN switch requires less than 10-20 μA/mm of Ids leakage current under 1200 V Vds operation in an off-state in order to minimize the off-power dissipation and maximize switching efficiency. In addition, the same GaN switch requires a very low on-resistance of <200 milli-Ohms in the on-state in order to minimize on-power dissipation and maximize switching efficiency. The on-resistance may be reduced by increasing the overall size of the device by increasing the gate width. However, this will increase cost and the absolute value of Igate leakage current, which is proportional to the gate width.
Excessive leakage current is a common problem with lateral high electron mobility transistor (HEMT) devices. In a lateral HEMT device, a channel surface typically needs to be passivated to reduce surface states that contribute to electron leakage transport in a lateral direction. The leakage current that results from the surface states increases with higher voltage operation and the resulting electric fields. In particular, the leakage currents and breakdown voltages are strongly influenced by peak electric fields between the gate and drain regions of a device. Excessive leakage current is often mitigated with field distribution techniques such as employing sloped gate metal, gate field plates, and source field plates over the gate-drain regions of an active device.

High voltage field effect transistor finger terminations


A one-piece clip simultaneously supports and grips a shelf when the clip is secured between a support pole and the shelf edge by a screw which penetrates the pole, the clip and the shelf consecutively. The longitudinal clip is die-cut and has a central base portion which abuts an indentation in the pole. An aperture centered in the clip base portion is aligned with screw holes horizontally penetrating the pole prior to insertion of the screw. Parallel arms extend up from the base portion of the clip, elbows attached thereto connect angled arms which extend outwardly and terminate in clip ends which flushly abut the exterior surface of the support pole.

This invention relates generally to the field of component furniture and, more particularly, to a clip for mounting a shelf on a support pole.
Heretofore, various devices have been known for mounting shelves on walls or other supporting structures, such as poles, rods or the like. U.S. Pat. No. 4,037,813 to Loui et al discloses a one-piece plastic shelf support member comprised of an upper shoulder portion, a central portion having a gripping rib 26 and a lower flange portion for supporting a shelf. A shaft 16 which extends from the lower portion into a bore in a support board provides the only attachment, i.e., by friction, of the support device to the upright support member. The construction of the Loui et al shelf support imposes the restriction that the clip or support can only be used in one vertical direction, that is, it cannot be inverted or turned upside down and used equally as well, as is the case with the present shelf support clip. Furthermore, the Loui et al shelf support requires gussets 28 to withstand an increased shelf load; such is not the case with the new shelf support clip which independently provides sufficient support.
U.S. Pat. No. 4,541,600 to Vieglins teaches a shelf bracket made of a solid, yet elastically deformable material and having a through-hole for a screw and a transverse channel for holding the end edge of a shelf. Full insertion of the screw permits a clamping action to occur between the channel, or groove, and the shelf. Engagement of the Vieglins bracket with the upright support thereof is limited to the marginal portions 9 of the bracket. By contrast, the new die-cut shelf support clip permits full contact of the base portion as well as the end portions, with the support pole when properly attached thereto.
Conventional forms of attachment, such as simply screwing or nailing a shelf directly to a support pole suffer from the disadvantage that the shelf may tilt and cause the wood or other material thereof to split under the resultant force. Other known methods, such as supporting the shelf from beneath by slats which connect side poles, suffer from the disadvantage that they require more materials and thus are heavier, awkward to handle and more expensive. Furthermore, problems may be created in moving known shelving units because the shelves may be permanently attached to the support structures or at least be very difficult to disassemble. The inability to easily take apart a shelving unit also yields the disadvantage that the shelves cannot be selectably adjusted to other than the predetermined height.
Therefore, it is an object of the present invention to provide a clip for supporting a shelf on a support pole in such manner that the shelf is securely and stably maintained thereon by attaching with a single screw which penetrates both the pole and the shelf.
It is another object of the present invention to provide a shelf support clip having the features stated that permits the shelving unit to have shelves of a variable height, which height may be easily, selectably altered.
It is a further object of the present invention to provide a clip having the features stated which permits a shelving unit constructed therewith to be easily dissembled for shipping and/or storage.
It is a still further object of the present invention to provide a clip having the features stated which is inexpensive and relatively lightweight, such a clip being capable of use for assembling, for example, free-standing bookshelves, a movable cart or other component furniture.
It is yet another object of the present invention to provide a clip having the features stated which simultaneously supports and grips a shelf positioned therein.
It is still another object of the present invention to provide a clip having the features stated which is constructed in one piece, which may be manufactured in various sizes and which comprises clip ends adapted to fit snugly against a corresponding shelf support pole.
Briefly, in furtherance of the above objects, the present invention comprises a one-piece shelf support clip having a flat base portion centrally penetrated by an aperture and having first and second opposing ends. The aperture and the first and second opposing base ends create a plane. First and second opposing, parallel walls extend respectively from the first and second base ends and have outer ends. First and second elbow portions extend outwardly relative to the base portion and respectively from the outer ends of the first and second opposing parallel walls at substantially right angles thereto. First and second outwardly angled arms project respectively from the first and second elbow portions, away from the first and second opposing parallel walls, toward the plane created by the base portion and have detached ends. First and second parallel clip ends project respectively from the detached ends of the first and second angled arms and through the plane created by the base portion.
Other objects and features will be in part apparent and in part pointed out hereinbelow.


A method for composing a multilayer video image of which the values of the pixels of the image layers are stored in a memory. The video image may include at least one first image layer and a second image layer located in front of the at least one first layer and having an opaque area. The method may include defining a region of the at least one first image layer to be hidden by the opaque area, reading from the memory the stored pixel values, with the exception of the values of the pixels of the region of the at least one first image layer, and composing the video image at least from the read pixel values.

Multilayer video images include a plurality of layers, such as a background, a wallpaper and an opaque foreground, and a video layer in front of the background. Generally the video layer hides a portion of the background.
Typically the values of the pixels of all the layers of the image to be composed are stored in a memory. For composing the image, the values of the pixels of the image layers are read, then the image is composed from at least some of the values of the corresponding pixels in the various image layers.
However, the pixel values of the portion of the background hidden by the video layer are unimportant in composing the image, in that the pixels of this portion of the background are hidden by the video layer. The separate reading of the values of the pixels of all the layers of the image to be composed leads to a bandwidth in reading (i.e., the flow rate of data transferred from memory) which may be relatively high in some cases, whereas some background pixels will not be seen.

Method and device for composing a multilayer video image


A cover plate has an inner surface shaped to contact a closet flange and an opposing outer surface. The cover plate is adapted for covering a drain pipe end having a closet flange that extends perpendicular to the drain pipe end. The inner and outer surfaces terminate in an outer cover perimeter having approximately the same diameter as an outer flange perimeter of the closet flange. The outer cover perimeter has a protective sidewall that extends upwardly, normal to the outer surface, for protecting the closet flange and facilitating the installation of floor tile adjacent the closet flange. The cover plate includes cover apertures positioned to coincide with flange apertures of the closet flange. The cover plate further includes cover locking bolts and cover locking nuts adapted to be positioned through the flange apertures and the cover apertures for removably fastening the cover plate to the closet flange.

Not Applicable
Not Applicable
1. Field of the Invention
This invention relates generally to plug devices, and more particularly to a combination plug device and cover plate, the cover plate functioning to hold the plug device in a drain pipe end and also to protect a closet flange that extends perpendicular to the drain pipe end.
2. Description of Related Art
The following art defines the present state of this field:
Mathison et al., U.S. Pat. No. 4,493,344, teaches a mechanically operable plug device is for use with the end of a pipe or conduit. The plug device is for removably sealing the conduit end so that the conduit can be tested for leaks. The mechanically operable plug device is comprised of two spacially parallel plate members, a narrow, elastomeric, and radially expandable O-ring member which is disposed between the plate members, and adjustable lateral force means which is operable on the parallel plate members. The radially expandable O-ring member has a circumferentially disposed surface for engaging the interior surface of a conduit to be sealed, and a generally V-shaped cross section having inclined surfaces of a predetermined slope. The plate members have interiorly facing tapered shoulders of generally the same predetermined slope to engage the inclined surfaces of the O-ring. Subsequent to the placement of the plug device into a conduit end, the positive adjustment of the lateral force means causes the sloped opposing shoulders to impart lateral forces to the inclined surfaces of the O-ring to, thereby, cause it to expand outwardly to seal a conduit.
Condon, U.S. Pat. No. 5,329,971, teaches an apparatus for sealing the central opening in a conventional closet flange extending perpendicular to a drain pipe. A generally disk-shaped sealing member is connected to the lower end of a threaded shaft screwed through an intermediate hub in a diametrically extending mounting body. A pair of L-shaped retaining arms are pivotally connected to corresponding ends of the mounting body. Heads on the lower ends of the retaining arms may be inserted through diametrically spaced key-shaped slots in the closet flange and engaged with the underside of the flange. A handle connected to the upper end of the shaft may be turned to screw the shaft downwardly. This firmly presses an elastomeric boot on a convex underside of the sealing member against an inner edge of the central opening in the closet flange. This seals the opening in the closet flange to permit pressure testing of the drain and its associated sewer system.
Cornwall, U.S. Pat. No. 4,233,697, teaches a protective cover or cap for connection to a toilet mounting flange installed on a drain or discharge pipe. The cover protects the stems of bolts for connecting the flange to the toilet by means of at least two tubular extensions on the cover which surround the bolts and by means of nuts over washers on the bolt stems when the cover is installed on the flange. The cover makes it much easier to align the flange visually with the surrounding walls by means of the tubular extensions for the bolts. In addition, the cover is adapted for hydrostatic testing of the drainage system, prevents any foreign material from entering the discharge pipe and protects the slots and holes in the flange from becoming clogged or filled.
Various other similar devices are shown in the following: Wilson, U.S. Pat. No. 5,975,142; G. Steele, U.S. Pat. No. 2,512,041; J. F. Levan, U.S. Pat. No. 2,218,581; B. B. Kinkade, U.S. Pat. No. 986,297; A. Redenbaugh, U.S. Pat. No. 848,493; N. Santucci, U.S. Pat. No. 2,064,569; O. Benshadle, U.S. Pat. No. 1,557,966; Mathison, U.S. Des. 300,350; Berneski, WO 00/03172, and Hodges, U.S. Pat. No. 5,695,222. The above-described references are hereby incorporated by reference in full.
The prior art teaches various plug devices that can be used to temporarily close a drain pipe end. However, the prior art does not teach a combination plug device and cover plate, the cover plate functioning to hold the plug device in a drain pipe end and also to protect a closet flange that extends perpendicular to the drain pipe end. The present invention fulfills these needs and provides further related advantages as described in the following summary.
The present invention teaches certain benefits in construction and use which give rise to the objectives described below.
The present invention provides a cover plate for covering a drain pipe end having a closet flange that extends perpendicular to the drain pipe end. The cover plate includes an inner surface shaped to contact the closet flange and an opposing outer surface. The inner and outer surfaces terminate in an outer cover perimeter having approximately the same diameter as an outer flange perimeter of the closet flange. The outer cover perimeter has a protective sidewall that extends upwardly, normal to the outer surface. The cover plate further includes cover apertures positioned to coincide with the flange apertures of the closet flange, and a means for removably fastening the cover plate to the closet flange.
A primary objective of the present invention is to provide a cover plate having advantages not taught by the prior art.
Another objective is to provide a cover plate that will lock a plug device inside a drain pipe and prevent internal pressure from pushing the plug device out of the drain pipe.
Another objective is to provide a cover plate that functions to protect a closet flange of the drain pipe from being clogged with grout or other material.
A further objective is to provide a cover plate with a protective sidewall that provides a surface that can be used to guide installation of floor tile or other floor covering materials.
Other features and advantages of the present invention will become apparent from the following more detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention.


A computer server system comprises multiple computer server units, each computer server comprising a server processing system. Each computer server comprises a local subsystem access module which is standardized for the multiple computer servers and which provides virtual control function for a single instantiation of a hardware resource of the computer server system, wherein the hardware resource is shared between each of the computer servers.

Computer server systems are known in the art. Typically, computer server systems exhibit multiple computer servers mounted in a standard chassis. Such computer servers are available as rack-mounted servers or as so called Blades.
In a standard rack configuration, one rack unit (1 U) is the minimum possible size of any equipment. A component mounted in the rack can be of the size of one (1 U), two (2 U) or n rack units (nU). A rack unit is a unit of measure used to describe the height of a device mounted in a 19-inch or a 23-inch rack, wherein 19 inch and 23 inch refer to the width of the rack. One rack unit is 1.75 inch high. The most common computer rack form factor is 42 U high, which limits the number of discrete rack-mounted servers directly mounted. Blade units are not restricted to this number. The form factors of Blades are typically smaller than those of rack-mounted servers. Today 70 computers per rack and more are achievable with today's Blade generations.
Blade servers are high-density, self-contained computer servers. Blade servers have all functional components to be considered a computer, such as memory to read input commands and data, a processor to perform commands manipulating that data and memory to store the results. A Blade enclosure usually provides services such as power, cooling, networking, various interconnects and management, thus performing many of the non-core computing services found in most computers. Usually, for accessing the individual Blades, a display, a keyboard and a mouse can be attached to a specific Blade.
Besides the basic computer functions, the computer servers provide specific support functions like i.e. graphics controller or keyboard and mouse control. These functions are implemented as electrical components requiring electrical power and resulting in heat generation. Considering the maximum allowable thermal load to electronic components and reliable cooling capacities, the heat generation per Blade or per rack-mounted server is restricted to a few hundred Watt only.
In view of the foregoing, there is a need for an improved computer server and an improved computer server system where a higher density is possible. In addition, the overall energy consumption of computer systems is becoming more and more important, energy consumption reductions and optimization is a requirement for new systems in development.

Computer server system and computer server for a computer server system

International Business Machines Corporation


Amide compounds, amide polymers, compositions including amide compounds and amide polymers may be used to bind target ions, such as phosphorous-containing compounds in the gastrointestinal tract of animals. In some cases, amide compounds and amide polymers may include a core derived from an amide polyol and an organic polyacid or ester.

Hyperphosphatemia frequently accompanies diseases associated with inadequate renal function such as end stage renal disease (ESRD), hyperparathyroidism, and certain other medical conditions. The condition, especially it present over extended periods of time, leads to severe abnormalities in calcium and phosphorus metabolism and can be manifested by aberrant calcification in joints, lungs, and eyes.
Therapeutic efforts to reduce serum phosphate include dialysis, reduction in dietary phosphate, and oral administration of insoluble phosphate binders to reduce gastrointestinal absorption. Many such treatments have a variety of unwanted side effects and/or have less than optimal phosphate binding properties, including potency and efficacy. Accordingly, there is a need for compositions and treatments with good phosphate-binding properties and good side effect profiles.


Aspects of the disclosure relate to detecting unmapped drivable road surfaces. In one instance, sensor data captured by a sensor of an autonomous vehicle may be projected onto a grid having a plurality of cells. The plurality of cells may be classified by generating a label for each of the plurality of cells. Each label may identifies whether or not a corresponding cell contains a drivable surface. Ones of the plurality of cells may be clustered based on the labels to form a cluster of cells. An area of the cluster of cells may be compared to a map. Whether the area of the cluster of cells is an unmapped drivable road surface may be determined based on the comparison.

Autonomous vehicles, such as vehicles which do not require a human driver when operating in an autonomous driving mode, may be used to aid in the transport of passengers or items from one location to another. An important component of an autonomous vehicle is the vehicle's map information. This information is critical to allowing the vehicle's computing systems to localize itself and to make appropriate driving decisions for the vehicle. Thus, for vehicles which depend on maps to make driving decisions, it is critical that these maps are kept up to date and accurate. In this regard, changes to the world that make the map out of date or stale, such as when vehicle approaches an entire region of drivable road surface that is not reflected in the map can be extremely concerning. This can occur when a road, lane, driveway, alleyway, etc., is either not included in the original map or is added after the map is built.
Typical approaches for identifying changes to an already mapped road surface, for instance by looking for new or moved lane lines, etc., are simply not capable of detecting new driving surfaces. Other approaches, for instance, such as those that may involve identifying new traffic lights, may not provide sufficient information or context about the surrounding area. This can result in an autonomous vehicle not properly anticipating where another vehicle may come from or where another vehicle may drive into. In turn, these prediction errors can have safety consequences.

Automatically detecting unmapped drivable road surfaces for autonomous vehicles


A sealing glass paste which comprises at least one sealing glass frit powder and an aqueous binder which comprises an aqueous solution, dispersion or emulsion of a polymeric material and a water soluble oxidant which decomposes at a temperature of below 475.degree. C., the polymeric material burning out or decomposing at a temperature of below 475.degree. C., in the presence of the oxidant, to leave less than 2% of residues based on the total weight of the solids content of the binder. The sealing glass pastes may be used in the assembly of cathode ray tubes. The aqueous binder system which is used results in low carbonaceous residue levels after firing and does not contain volatile organic solvents. Furthermore, using this aqueous binder system sealing glass pastes can be prepared with sealing glasses which include PbO therein.

1. Field of the Invention
The present invention relates to sealing glass pastes, and, in particular, to sealing glass pastes for cathode ray tubes (CRT). Cathode ray tubes are fabricated by sealing together a glass faceplate or panel supporting the phosphorescent display screen of the tube and a glass funnel having an electrically conductive interior coating which forms part of the electronic circuitry of the tube. To seal the components together a sealing glass paste is applied to the edges of one part (either the face panel or the funnel) in the form of a ribbon, which is then dried. The remaining part is then placed in contact with the dried paste and the assembly is heated to evaporate the solvent, burn out the binder and fuse the sealing glass.
2. Description of the Related Art
Wet coating techniques for sealing glass or ceramic parts have been proposed and generally have involved pastes having a sealing glass distributed throughout a binder/solvent system in which the solvent is an organic solvent. When the assembly has been formed it is then heated to evaporated the solvent, burnout the binder and fuse the glass. For example, U.S. Pat. No. 4,014,845 discloses a binder/solvent system which comprises a polymeric material which is a polymer containing oxygen and a monomer of an alkyl methacrylate and a solvent for the polymeric material. For sealing glasses which contain PbO and which melt and flow at low temperatures, preferably at below 475.degree. C., such as PBO--B.sub.2 O.sub.3 --ZnO, the binder/solvent system which has been used commercially comprises nitrocellulose/amyl acetate or similar esters. Nitrocellulose has many disadvantages for use in such systems, but it has been tolerated because it does not cause the dielectric breakdown of the sealing glasses caused by reduction of PbO to Pb.
Other binders which have been tried in place of nitrocellulose do not prevent the reduction of PbO in the sealing glass to Pb metal during the sealing process. Thus, instead of a yellow seal being formed by the devitrified solder glass, a grey or grey-black seal is formed, which indicates the presence of metallic lead. Some of the discoloration may also be due to carbon residues formed on incomplete burn-out of the binder.
U.S. Pat. No. 3,973,975 discloses that the incorporation of Pb.sub.3 O.sub.4 in the sealing glasses containing PbO and the pastes made therewith, prevents the reduction of PbO to Pb. The Pb.sub.3 O.sub.4 is reduced to PbO, but the additional amount of PbO so formed does not affect the properties of the seal. The Pb.sub.3 O.sub.4 also acts to suppress the chemical reduction of the sealing glass by organic vapors during the sealing step.
U.S. Pat. No. 4,154,494 disclosed a method of preventing the chemical reduction of the devitrifiable solder glass by providing an oxygen-evolving agent with the bulb during the sealing step. The oxygen-containing compound is coated onto the funnel in an amount sufficient to suppress chemical reduction of the devitrifiable solder glass during sealing. Thus, the seal resists dielectric breakdown when very high voltages are subsequently applied.

Sealing glass paste for cathode ray tubes