When a non-oriented electrical steel sheet is manufactured, simultaneously having superior magnetic properties and high strengths, a composition containing 0.02% or less of C, 4.5% or less of Si, 5.0% or less (including 0) of Ni, and 0.2% to 4.0% of Cu is used, and a solute Cu is allowed to appropriately remain in finish annealing. In the steel sheet thus obtained, finely shaped Cu is precipitated by aging treatment, and while the magnetic properties are not degraded, the yield stress is increased to not less than CYS (MPa) represented by the following formula:noteCYS=180+5,600[% C]+95[% Si]+50[% Mn]+37[% Al]+435[% P]+25[% Ni]+22d−1/2                 where d is an average grain diameter (mm) of crystal grains.

In recent years, due to advancement of drive circuit systems of motors, it has become possible to perform frequency-control of drive power supply, and as a result, a high speed motor driven by adjustable speed control or driven at a higher frequency than a power frequency has been increasingly in demand. In the high speed motors driven as described above, it is necessary to use rotors having strengths capable of withstanding high speed rotation.
That is, a centrifugal force applied to a rotor is proportional to the rotating-radius and is increased in proportional to the square of a rotational speed. Hence, in medium-sized and large-sized high speed motors, a stress more than 600 MPa may be applied to rotors thereof in some cases. Accordingly, for the high speed motors as described above, increase in strengths of the rotor must be achieved.
In addition, in view of recent improvement in motor efficiency, a magnet-embedded type (IPM: Interior Permanent Magnet) DC inverter control motor, in which permanent magnets are embedded in a rotor, has also been increasingly in demand. In the motor described above, magnets embedded in the rotor are liable to jump out therefrom, and in order to prevent the magnets from jumping out, a large force is applied to an electrical steel sheet used for the rotor. From this point of view, an electrical steel sheet for use in the motor, in particular, for use in the rotor has been required to have high strengths.
Since rotating devices such as motors and generators exploit electromagnetic phenomena, core materials therefor are required to have magnetic properties. In particular, the core materials preferably have a low iron loss and a high magnetic flux density.
In general, for assembling an iron core of a rotor, non-oriented electrical steel sheets are formed by punching using a press machine and are then laminated to each other for the use. However, when a core material of rotors used for high speed motors cannot satisfy the mechanical strengths described above, instead of that, a rotor made of cast steel having higher strengths must be used. However, since the cast steel-made rotor mentioned above is a bulk product, compared to a rotor formed of electrical steel sheets laminated to each other, a ripple loss affecting the rotor is large, thereby primarily causing decrease in motor efficiency. The ripple loss indicates an eddy current loss caused by a high frequency magnetic flux.
Accordingly, an electrical steel sheet having superior magnetic properties and high strengths has been desired as a core material for rotors.
As a strengthening method from a metallurgical point of view, for example, solid solution strengthening, precipitation strengthening, and grain-refining strengthening have been known, and there are examples in which some methods mentioned above were applied to electrical steel sheets. For example, according to Japanese Unexamined Patent Application Publication No. 60-238421, based on the results of investigation on advantages and disadvantages of the each strengthening method mentioned above, as a method having the least influence on magnetic properties, the use of solid solution strengthening has been proposed. In addition, a method has been disclosed in which, besides increase of the content of Si to 3.5% to 7.0% (mass percent, hereinafter, the same as above), an element having high capability of solid solution strengthening is added.
In addition, in Japanese Unexamined Patent Application Publication No. 62-256917, a method for controlling the diameter of recrystallized grains has been disclosed in which the content of Si is set in the range of from 2.0% to 3.5%, the content of Ni or the contents of Ni and Mo are increased, and low-temperature annealing at a temperature of 650 to 850° C. is performed. Furthermore, as a method using precipitation strengthening, in Japanese Unexamined Patent Application Publication No. 6-330255, a method has been disclosed in which the content of Si is set in the range of from 2.0% to 4.0% and fine carbides and nitrides of Nb, Zr, Ti, and/or V are precipitated.
By the methods described above, electrical steel sheets can be obtained having a high strength to a certain extent. However, when steel is used in which the contents of Si and an element for solid solution strengthening are high, as disclosed in Japanese Unexamined Patent Application Publication No. 60-238421, cold rolling properties are extremely degraded, and as a result, it becomes disadvantageously difficult to perform stable industrial manufacturing. Furthermore, a problem may arise in that magnetic flux density B50 of the steel sheet obtained by this technique is also seriously decreased to 1.56 to 1.60 T.
In the method disclosed in Japanese Unexamined Patent Application Publication No. 62-256917, in order to increase the mechanical strengths, the growth of recrystallized grains must be suppressed by low-temperature annealing, and as a result, in a relatively low frequency range, for example, of from a power frequency (approximately 50 Hz) to several hundred Hertz, a problem occurs in that the iron loss is decreased.
Accordingly, the electrical steel sheet obtained by the method disclosed in Japanese Unexamined Patent Application Publication No. 62-256917 cannot be used as a material for a stator member since the iron loss of this application is important in this frequency range. Hence, an extreme decrease in yield of the electrical steel sheet according to this method could not been avoided. That is, when stator and rotor members are obtained by punching, a ring-shaped stator member is generally punched out from one steel sheet, and from a remaining central part of the same steel sheet, a rotor member is also obtained by punching, thereby reducing waste. However, in the method disclosed in Japanese Unexamined Patent Application Publication No. 62-256917, two types of members must be obtained from different steel sheets by punching, and as a result, the yield is unfavorably decreased.
On the other hand, according to the method disclosed in Japanese Unexamined Patent Application Publication No. 6-330255, since the carbides and nitrides themselves function as a barrier to magnetic wall movement and interfere with the growth of crystal grains of an electrical steel sheet, the degradation in iron loss is still disadvantageously large.
In addition, regardless of whether any of the methods described above is used, the electrical steel sheets manufactured thereby each have a high hardness, and as a result, the punchabilities thereof are inferior. That is, when the steel sheet for laminated core is punched out, die wear becomes very large, and hence large burrs are liable to be generated in an early stage.
As will be described later, as one of the features of the present invention, the composition of a steel sheet according to the present invention contains a predetermined amount of Cu. Hence, apart from the problems described above, the current status of Cu used in non-oriented electrical steel sheets will be described.
As an example in which Cu is added to an electrical steel sheet, a technique for improving punchabilities has been disclosed in Japanese Unexamined Patent Application Publication No. 62-89816 in which 0.1 to 1.0% of C is added to a steel sheet so as to precipitate graphite. As a method of recrystallization annealing (finish annealing), box annealing is recommended. In this technique, as an element facilitating the precipitation of graphite, Cu in an amount of 1.0% or less is recommended to be added; however, disadvantage in cost is also implied.
However, the electrical steel sheet described above having a composition containing 0.1% or more of C is an exceptional one, and in a general electrical steel sheet, the addition of Cu is not recommended in view of the magnetic properties and the like. For example, in Japanese Unexamined Patent Application Publication No. 9-67654, a non-oriented electrical steel sheet containing more than 1% to 3.5% of Si or the like has been disclosed; however, since the precipitation of CuS and the like has adverse influences on the magnetic properties, the content of Cu is limited to 0.05% or less.
In addition, as a technique which contain a larger amount of Cu than that described above, a method has been disclosed in Japanese Unexamined Patent Application Publication No. 8-295936 in which a non-oriented electrical steel sheet is manufactured from raw materials including scrap steel. In this technique, in order to reduce adverse influences on the magnetic properties caused by alloying elements (0.015% to 0.2% of Cu: 0.01% to 0.5% of Ni: 0.02% to 0.2% of Cr: 0.003% to 0.2% of Sn: and the like) contained in scrap, for example, measures are proposed in which the contents of V and Nb are limited, and in which the diameter of crystal grains after hot-rolled sheet annealing is controlled to 50 μm or less. However, also for this technique, the above elements such as Cu are naturally disadvantageous, and a primary object of this technique is only to reduce the adverse influences of the above elements. In addition, the contents of Cu and the like thus disclosed are small.
Furthermore, as steel which does not contain Si, high-strength steel used for electric machinery has been disclosed in Japanese Unexamined Patent Application Publication No. 49-83613, the steel being composed of 1% to 5% of Cu, 1% to 5% of Ni, and iron as the balance. According to this technique, after solution treatment-quenching and cold rolling are repeatedly performed for steel having the above composition, aging treatment is performed, and then steel having a high strength and a low iron loss can be obtained. However, degradation in iron loss caused by aging treatment has not been satisfactorily suppressed.

Non-oriented electrical steel sheet and method for manufacturing the same


Systems, apparatuses, methods, and computer-readable media, are provided for selecting edge or central servers for serving client systems based on network events monitored by one or more network elements. Embodiments may be relevant to multi-access edge computing (MEC) and Automotive Edge Computing Consorium (AECC) technologies. Other embodiments may be described and/or claimed.

Vehicular mobile communications is increasing in importance for applications/services to make driving safer, improve traffic flow, provide energy consumption efficiencies, and reduce emissions. Several emerging services, such as intelligent driving, the creation of maps with real-time data and driving assistance based on cloud computing, may require vehicles to be connected to a cloud computing service and one or more networks to facilitate the transfer of large amounts of data among vehicles and between vehicles and the cloud. Cellular networks may provide mobile connectivity for vehicles, and 3GPP has produced standards for vehicle-based mobile networks. Current 3GPP standards for vehicle-based mobile networks (e.g., cellular V2X) mainly covers latency-sensitive safety applications and may not fully ensure the big data capacity growth between vehicles and the cloud.
Automotive Edge Computing Consortium (AECC) is a consortium for supporting network and computing infrastructure needs of automotive big data. AECC focuses on increasing network and computing capacity to accommodate automotive big data between vehicles and the cloud using edge computing and efficient system design. The AECC system architecture uses cellular networks as the primary access technology. However, the AECC system architecture lacks access network assisted edge selection mechanisms.

Server selection for vehicle communications and applications


Provided are a fixing module and a motion assistance apparatus including the same, the fixing module including a base body, a plurality of side frames provided on both sides of the base body, and a height adjustment assembly provided on the base body, and on which a driving module is mounted to provide a power, wherein a distance between the plurality of side frames may be adjustable.

1. Field
Example embodiments relate to a fixing module and/or a motion assistance apparatus including the same.
2. Description
With the onset of a rapidly aging society, an increase number of people may experience inconvenience and agony from joint problems, and, therefore, there may be an increased interest in a motion assistance apparatus to assist these people with walking. In addition, motion assistance apparatuses that may increase a muscular strength of a human body are being developed for military purposes.
In general, a motion assistance apparatus may include one or more of a body frame disposed on a trunk of a user, a pelvic frame coupled to a lower side of the body frame to cover a pelvis of the user, a femoral frame disposed on a thigh of the user, a sural frame disposed on a calf of the user, and a pedial frame disposed on a foot of the user. The pelvic frame and the femoral frame may be connected rotatably by a hip joint portion, the femoral frame and the sural frame may be connected rotatably by a knee joint portion, and the sural frame and the pedial frame may be connected rotatably by an ankle joint portion.
The motion assistance apparatus may include an active joint structure including a hydraulic system and/or a driving motor to drive each joint portion to improve a muscular strength of a leg of the user. For example, two motors may be provided at both hip joint portions to transmit a driving power.

Fixing module and motion assistance apparatus including the same


Improved integrity of a payment system for paying for services or goods, for example, telephone facilities, through use of electronic payment cards. In any session to increase a card balance, a "flag" is placed ("1") on the payment card which indicates that the session must not be interrupted. After completion, the flag is removed again ("0"). A session to pay for the product or the service or to increase the balance can only be established if the flag is absent ("0") indicating that the last session to increase the balance was correctly completed. If, on the other hand, the flag is still "1" at the start of a session, a correction routine is first performed in which the previous session to increase the balance is then correctly concluded to prevent the flag being removed by fraud, the flag can only be removed by a central system (PSTN/ABS) through issurance of an authorized instruction.

The invention relates to a payment system in which use is made of electronic payment cards, in particular "chip cards" or "smart cards". Under consideration in the present application are, in particular, payment cards which can be used for paying call costs in public telephone terminals. However, other services and goods can also be paid for in this way. This development is in fact referred to as a so-called "electronic purse". Under consideration in this connection is the payment of generally .[.none too large.]. .Iadd.small .Iaddend.amounts by means of electronic payment cards on which a balance is previously entered. Payment takes place by reducing the balance on the card. Of course, measures have to be taken in order to arrange for the balance reduction to benefit the supplier; systems for this purpose are still being developed and tests are taking place in that field. To place an initial balance on the card and increase the balance later, there must be an infrastructure of terminals and the like if this form of payment is to be accepted. It appears possible to use the public telephone terminals for this purpose. Such terminals act as "charging stations" for the electronic payment cards. Of course, the public telephone terminals remain suitable as means for conducting telephone calls and offering any other telecommunication facilities via the downstream central telephone system or telecommunication system. Payment of such telephone calls and any other facilities may, at the same time, take place by means of the "electronic purse". Although the payment of telephone/telecommunication costs, in particular, is considered below, it is emphasized that the invention, as explained below, is not limited thereto and is equally applicable for payment for other services or goods by means of an "electronic purse". The "charging" of payment cards need not occur via telephone terminals either, but can equally well occur via other terminals, for example, terminals which are now used for issuing cash (so-called "cash points").
After a payment card has been provided with an initial balance, that balance is reduced by the telephone terminal in accordance with a rate for the telephone costs. The provision of an initial balance and the replenishment of the balance after the passing of time can also occur via the telephone terminal. To do this, .Iadd.a .Iaddend.connection has to be made to a central administration system which, .[.onto.]. .Iadd.on .Iaddend.the one hand, enters the amount desired by the user on the card and, on the other hand, ensures that the amount can be received, for example, by sending an account to the user or via (after authorization) electronic reduction of the balance of a bank account belonging to the user.
The measures proposed according to the present invention are intended to combat errors and frauds in the processes mentioned (the use/payment process and the "balance process").

Chip card based payment system having an on-card flag for specifying proper completion of a prior card balance replenishment session


Various exemplary embodiments relate to a method and related network node including one or more of the following: receiving, at a wake-up server, an indication that an agent device will be suspended, including at least one criterion for reestablishing the agent device; determining that the at least one criterion has been met; and, in response, reestablishing the agent device. Various exemplary embodiments relate to a method and related network node including one or more of the following: transmitting, by an agent device to a support server, a request message; transmitting, to a wake-up server, an indication that resources associated with the agent device will be released, including at least one criterion for reestablishing the agent device; transmitting, to the support server, an instruction to transmit a result message associated with the request message to the wake-up device; and releasing the system resources associated with the agent device.

With the emergence of new modular processing architectures for data centers, a new way of data processing is possible for both enterprises and consumers. A number of companies have set up data centers throughout the US as well as globally. An enterprise or individual consumer can subscribe to their services and can access their services through the Internet. When accessing these services, a subscriber can create virtual machines (VMs), request storage space, load applications from the virtual storage to the VM and activate the applications, etc. on an as-needed basis.
With this way of computing, users may off-load processing from their machines and use the services provided by the computing service providers. This form of the processing is commonly referred to as "cloud computing," as the data processing is virtualized and resides in the Internet "cloud". An example of cloud computing service provider is the EC2 service from Amazon.
Currently, VMs are charged by the hour by the clouding computing service provider. The size of the VM (in terms of computing power) would determine the rate. For some computing service providers, the basic service subscription comes with a number of "free" hours. Time used after that may be charged by the hour.

Support server for redirecting task results to a wake-up server


A method is disclosed for applying a multi-state barge-in acoustic model in a spoken dialogue system. The method includes receiving an audio speech input from the user during the presentation of a prompt, accumulating the audio speech input from the user, applying a non-speech component having at least two one-state Hidden Markov Models (HMMs) to the audio speech input from the user, applying a speech component having at least five three-state HMMs to the audio speech input from the user, in which each of the five three-state HMMs represents a different phonetic category, determining whether the audio speech input is a barge-in-speech input from the user, and if the audio speech input is determined to be the barge-in-speech input from the user, terminating the presentation of the prompt.

1. Field of the Invention
The present invention relates to spoken dialog systems in general and, more particularly, to a multi-state barge-in-model and its use in handling barge-in speech in a spoken dialog with an automated system.
2. Introduction
Speech processing technologies have since their inception been involved, in some way or another, with the problem of detecting speech, whatever the acoustic environment. The problem of accurately distinguishing speech from the background is still an active area of research.
In practice there are three different applications involving speech detection. They differ in their intent and the mechanisms used to achieve their targets. The first application determines if speech is present, it is commonly referred to as the Voice Activity Detection (VAD). The VAD application tries to detect every non-speech segment within a continuous utterance, for example, a short pause. Another application, most commonly encountered in automatic speech recognition (ASR) applications is the problem of endpointing. This is important when detecting the beginning and the end of an utterance, the ASR system is relied on to internally determine if there are any utterance internal pauses.
Barge-in is a unique speech detection problem that only occurs in dialog based applications. Barge-in happens when a user of an automated dialog system attempts to input speech during the playback/synthesis of a prompt generated by the dialog system. In this unique situation, two things are expected to occur, virtually instantaneously. First the prompt is immediately terminated, both to indicate to the user that the system is listening to him/her, and to allow uninterrupted recognition of the user's utterance. At the same time, the ASR engine starts processing the accumulated speech starting some short amount of time prior to the detected barge-in. In the case of barge-in, the system faces only a relatively small subset of the problems faced by the VAD systems. Conversely, the errors can have a significant impact to the perceived usability of the system and might cause it to be abandoned. A false barge-in, which happens when the system incorrectly believes that there is speech input by the user, will terminate the prompt. This termination of the prompt leaves the user without proper guidance for providing the appropriate input to the system. This can have a long term effect diverting the dialog away from the intended operation for many turns. Conversely, if by trying to minimize false alarms, the system becomes less sensitive to speech input and fails to barge-in, the user may find it uncomfortable speaking while the prompt is still active. The user's discomfort corrupts their delivery of the speech input affecting the ASR due to the unnaturalness of the input. In addition this often leads to unwanted echo and consequent poor recognition performance. This is assuming the ASR system is left active all the time, and not initiated by the barge-in detection, in which case the speech would be lost to the system.
The ideal barge-in response requires minimum latency, responding to the speech input as quickly as possible, while requiring high level of accuracy in detecting speech. Those two criteria are contradictory and are often traded off one against the other.
The overall dialog system scenario implies, to a large extent, that the barge-in performance is tightly coupled with the ASR system. In essence, a flawless barge-in performance that negatively impacts the ASR performance is detrimental to the system performance, and vice-versa. In many ways the best barge-in system is the ASR system, with the serious drawback that its latency is too long. Accordingly, what is needed in the art is an improved method of processing barge-in input from a user.

This patent is subject to a terminal disclaimer.

Multi-state barge-in models for spoken dialog systems


A dip net apparatus for catching fish includes in a preferred embodiment a transparent monofilament netting attached to a substantially-transparent, hollow, tubular rim, which is attached to a substantially-transparent, hollow, tubular handle. An opening within the handle allows water to flow into the hollow interior of both the rim and the handle when immersed underwater, and which renders the rim and handle visually undetectable to nearby fish. The handle includes two openings for receiving the two ends of the rim. An elliptical cross-section of both the rim and the openings in the handle afford assembly of the dip net apparatus by inserting the ends of the rim into the corresponding handle openings and friction locking the rim by twisting the rim relative to the handle.

1. Field of the Invention
This invention relates to fishing nets, and more specifically, to recreational dip nets typically used to catch bait fish and other small fish.
2. Description of Related Art
The art of dip nets for catching fish extends well back in time. A great many examples of dip nets can be found which exhibit a variety of construction techniques for connecting a rim to a handle and for connecting a net to the rim. Aluminum, wood, and fiberglass are frequently used for the rim and the handle, with small metallic hardware frequently used to connect the rim to the handle. Consequently, hand tools are typically required to change the net or to assemble the rim to the handle. Colored netting material, such as nylon, is frequently used.


An embodiment includes an X-ray detecting section including an X-ray detector having a first visual field size and a high-resolution detector and having a second visual field size, an X-ray generating section for irradiating a subject with X-rays, an image processing section for generating a first X-ray image by means of the X-ray detector and a second X-ray image, a display section, a region defining section for displaying a spot corresponding to part of the second X-ray image or a region corresponding to the second X-ray image on the first X-ray image and specifying the position of the high-resolution detector by moving the spot or the region, a positional displacement calculating section for determining the coordinate difference between the center position of the first X-ray image and the position of the spot indicating the specified position and a move control section for controlling the top plate or the holding section.

In known X-ray image diagnosing apparatus having a C-arm type holder unit, an X-ray generating section and an X-ray detecting section are arranged at the respective opposite ends of the C-arm. A transparent image and a photographic image are displayed on a display monitor as a function of the dimensions of the X-ray detector (I.I: image intensifier or FPD: flat panel detector) and the values specified for visual field size.
In recent years, efforts have been paid to raise the level of diagnosis and therapeutic manual procedures by arranging a compact high-resolution X-ray detector in addition to an ordinary X-ray detector that provides an image size of about 8 to 16 inches in order to obtain a clearer image of a region of interest (ROI) such as a morbid area.
Apparatus having two X-ray detectors includes those having a switching arm mechanism disposed in the X-ray detecting section of the apparatus to place, when necessary, the compact high-resolution detector in front of the ordinary visual field size X-ray detector to collect high-resolution images but, when not necessary, retract the high-resolution detector.
The switching arm mechanism of this configuration is arranged so as to make the center of the image obtained by means of the ordinary X-ray detector agree with center of the image obtained by means of the compact high-resolution detector and the images obtained by means of the two detectors agree with the center of the focus of X-rays.
With an X-ray image diagnosing apparatus equipped with a compact high-resolution detector having a small visual field, the visual field becomes small as the ordinary X-ray detector is switched to the compact high-resolution detector. Thus, either the ROI needs to be aligned with the image center before selecting the small visual field or, after selecting the small visual field, the C-arm needs to be driven or the bed needs to be moved for an adjustment operation of putting the ROI into the small visual field. This gives rise to a problem of making the system rather inconvenient and the therapeutic manual procedures inefficient.
On the other hand, there are known X-ray image diagnosing apparatus having two X-ray detectors of the type where the operator of such an X-ray image diagnosing apparatus specifies the spot he or she wants to look at in detail, for example, the position where a stent 4 is buried in a blood vessel 3, on X-ray image 1 obtained by means of the ordinary X-ray detector by means of a marker 2 so as to make the spot includes the ROI.
Then, only the compact high-resolution detector is moved according to the coordinate data of the specified marker (ROI) and the whole image is displayed, including the ROI part that is displayed as a high-resolution image. However, with such an X-ray image diagnosing apparatus, the ROI image can be displayed at a side position in the displayed whole image to make it inconvenient for image diagnosis.
In such an instance, the operator is required to carry out an additional operation of making the ROI part displayed at the center of the whole X-ray image. Furthermore, from the structural point of view, a complex switching arm mechanism is required for such an operation because it needs to have an independent drive mechanism for moving only the compact high-resolution detector.
Therefore, the object of the present invention is to dissolve the above-identified problems and provide an X-ray image diagnosing apparatus that can carry out an examination operation promptly if a compact high-resolution detector having a small visual field is employed in it.


Techniques are generally described for predicting text relevant to image data. In various examples, the techniques may include receiving image data comprising a first portion. The first portion of the image data may correspond to a first plurality of pixels when rendered on the display. Text data comprising a first text related to the first portion of the image data may be received. A first vector representation of the first portion of the image data may be determined. In some examples, a correspondence between the first portion of the image data and the first text may be determined based at least in part on the first vector representation. A first identifier of the first portion of image data may be stored in a data structure in association with a second identifier of the first text.

Graphical user interfaces (GUIs) are often used to display graphics, photographs and/or other images representing physical and/or digital objects. In many cases, the depiction of the objects is associated with text describing and/or discussing the objects. Often, depending on the object and the context there may be several pages of text related to different components of the object. For example, each component of the object depicted may be associated with a textual description of the function and/or characteristics of that component. In some examples, associations may be formed between a component of an image and text relevant to that image by inserting a link into a web-based markup language such as hypertext markup language (HTML). Thereafter, a user may click on a link and/or a linked portion of an image to be redirected to different data associated with the link.
Provided herein are technical solutions to improve graphical user interfaces and determination of related content.

Relevant text identification based on image feature selection


Embodiments of a planar asymmetric antenna structure with shifted feed position for multi-protocol operations are disclosed The antenna structure includes two elliptically tapering right and left arms, each with a different radius, and an off-center feed point positioned between the right and left arms. One arm has a smaller elliptical tapering than the other arm and the feed point is positioned closer to one arm than the other arm. A method of synthesizing a multiprotocol antenna pattern is also disclosed. The method includes providing substantially equally surface currents on both arms of an antenna structure to generate a near-horizontal pattern in far-field at a lower frequency band, providing greater surface currents on the right arm to generate a far-field pattern with a large horizontal component at a higher frequency band, and providing greater surface currents on the left arm to generate an asymmetric far-field pattern at a middle frequency band.

Portable computing and communication devices, such as laptop, notebook and netbook computers, are generally configured with wireless capability and include one or more internal antennas to communicate with access points or base stations. These internal antennas generally provide an antenna pattern with similar gain in both vertical and horizontal directions. Since access points and base stations are generally located in a more horizontal direction, much of the gain of these antennas is wasted in the vertical direction. An internal antenna with an increased gain in the horizontal direction and reduced gain in the vertical direction (i.e., a more donut shaped radiation pattern) would be more suitable for use in portable computing and communication devices, however conventional antennas are generally unable to provide such a radiation pattern due to form factor restrictions. Furthermore, these conventional antennas are generally unable to support a multi-protocol system (e.g., WiMAX and WiFi).
Thus, there are general needs for multiprotocol antenna structures suitable for use in flat panel displays and other planar devices.

Multiprotocol antenna structure and method for synthesizing a multiprotocol antenna pattern


An illuminated shifter linkage apparatus for coupling the shifter pedal and the transmission of a motorcycle includes an inner rod having a plurality of light-emitting elements seated within a corresponding set of inner rod apertures, and an open-ended outer hollow shaft into which the inner rod is received. When fully assembled, the light-emitting elements align with the corresponding apertures in the outer hollow shaft to facilitate the passage of light through the shaft apertures, thereby providing an aesthetically pleasing appearance and enhancing the visibility of the motorcycle at night and in poorly lit areas.

1. Field of the Invention
The present invention relates generally to motorcycle shifter arms or linkages, and more particularly to an illuminated shifter linkage apparatus.
2. Description of the Prior Art
Motorcycle riders generally have a great concern with safety while riding their vehicles. Of particular concern is the lack of visibility of a rider""s motorcycle at night and in poorly lit areas. For this reason, many motorcycle owners find to be desirable to incorporate auxiliary lighting. According to the prior art, one means of providing enhanced lighting is to attach additional lighting components to the existing motorcycle body. For example, U.S. Pat. No. 5,590,947 discloses an illuminated windscreen for a motorcycle fairing, incorporating a plurality of light bulbs adjacent a lower edge portion of the windscreen and attached by mechanical clips. While such auxiliary attachment may serve the purpose of improving visibility, many motorcycle owners would prefer to incorporate lighting into an existing feature of the motorcycle in a manner enhancing the aesthetic appearance of the vehicle. Such enhancements may also be desirable for distinguishing an owners motorcycle from his fellow riders"" bikes. Where the lighting is to be incorporated into an existing structure, an important consideration is that the chosen structure has either limited or smooth movement during operation, thereby minimizing agitation of the lighting components.
Most conventional motorcycles have a toe shift pedal enabling the motorcycle operator to shift transmission gears via elevation or depression of the pedal by foot. In many conventional types of motorcycles, the shifter pedal and the transmission lever are separated by a distance and, therefore, require a shifter rod or linkage coupled at opposite ends to the shift pedal and transmission lever to enable gear shifting. In this manner, the pedal is used to shift transmission gears indirectly via back-and-forth movement of the shift rod.
The class of motorcycle that would typically need a shifter rod are so-called touring and cruiser classes which have the floor board or foot peg positioned forward to provide a better seating position for a longer comfortable ride. Typically, American-made motorcycles, such as Harley Davidson brand motorcycles, have a rear mounted transmission behind the engine housing. Consequently, they require such a shift linkage to connect the transmission via the linkage to the shifting pedal or lever. Likewise, Japanese motorcycles available in the cruiser or touring classes have the foot controls moved slightly forward and require such a shift linkage. Still other motorcycles having transmissions incorporated directly into the engine housing utilize a shifter linkage.
In operation, when the shifter pedal is pressed downwardly it causes the shifter lever downward, pulling the shifter linkage forward, which also pulls the lever on the transmission forward to put it into first gear. Subsequently, the rider can lift the pedal up one click, urging the lever backwards and putting the transmission into neutral. The rider can then successively lift the pedal, each time shifting up one gear. The shifter linkage is limited to smooth back-and-forth movement during operation and would therefore provide a desirable structural element in which to incorporate auxiliary lighting. Furthermore, the positioning of the shifter linkage along the side of the motorcycle makes it a desirable location for enhancing visibility of the motorcycle.
Accordingly, it would be desirable to provide a shift linkage apparatus incorporating illumination means for enhancing both the aesthetics and visibility of the motorcycle.
The invention is directed to a motorcycle shift linkage apparatus incorporating internal illumination means for enhancing the aesthetic appearance of the shift linkage as well as the visibility of the motorcycle at night and in poorly lit areas.
In one general aspect of the present invention, the illuminated shift linkage apparatus comprises a substantially rigid, longitudinally extending shaft having a hollowed portion defining an interior shaft space, and a light-emitting source disposed within the interior shaft space. Portions of the shaft wall have apertures or otherwise decorative cut regions provided therein for enabling transmission of the emitted light therethrough. Opposite ends of the shaft are configured for coupling to corresponding shift pedal and transmission of the motorcycle.
In another aspect of the invention, the illuminated shift linkage apparatus comprises a rigid open-ended substantially hollow shaft member having disposed therein a longitudinal base member supporting a plurality of light-emitting elements. The light-emitting elements are seated within spaced-apart base member apertures aligned with corresponding shaft member apertures to facilitate transmission of the emitted light therethrough.
In a further aspect of the invention, opposite ends of the base member beyond the open ends of the hollow shaft member and are adapted for coupling to corresponding shift pedal and transmission portions of the motorcycle.
In still another aspect of the invention an electronic circuit is provided electrically coupled to a power source and to the light-emitting source for controlling one or more output characteristics, such as controlling the intensity or rate of blinking of the light-emitting source.


A liquid crystal display (LCD) device and a method of manufacturing the same are proposed. A first transparent conducting layer is disposed on a first via for forming a testing point. A second transparent conducting layer is disposed on a second via and a third via. The first transparent conducting layer is connected to the second transparent conducting layer. By means of the method of manufacturing, the first transparent conducting layer and the second transparent conducting layer are still connected to each other after a process of edge exposure. It ensures that the testing point could be connected to a first metallic wiring layer and a second metallic wiring layer, preventing the testing point from malfunctioning.

1. Field of the Invention
The present invention relates to the field of liquid crystal displays (LCDs), and more particularly, to an LCD device and a method of manufacturing the same.
2. Description of the Prior Art
Referring to FIG. 1, a conventional LCD device comprises a substrate 11 and a metallic wiring layer 12 disposed on the substrate 11. A first via 121 and a second 122 are disposed on the metallic wiring layer 12. A first transparent conducting layer 123 is disposed on the first via 121 for forming a testing point 13. A second transparent conducting layer 124 is disposed on the second via 122. The first transparent conducting layer 123 and the second transparent conducting layer 124 are disposed respectively. The testing point 13 is connected to the metallic wiring layer 12 through the first via 121.
One process for manufacturing the LCD device is that the edge of the metallic wiring layer 12 is exposed. That is, metal along an exposed edge 125 and the edge of the substrate 11 is washed out.
Referring to FIG. 2, when the exposed edge 125 is closer to an inner side of the substrate 11, the metallic wiring layer 12, which is outside the exposed edge 125, would be washed out. However, the testing point 13 is disposed outside the exposed edge 125 of the metallic wiring layer 12, so the metallic wiring layer 12 between the testing point 13 and the second via 122 would be washed out. Accordingly, the testing point 13 and the second via 122 are disconnected, causing the testing point 13 to be ineffective.
Therefore, there is a need for an LCD device and a method of manufacturing the same for solving the above-mentioned problem.

Shenzhen China Star Optoelectronics Technology Co., Ltd


A drive voltage generator circuit is provided for developing drive voltages used for driving an LCD panel. The drive voltage generator circuit is composed of a breeder, a buffer amplifier, a switch circuitry, and a set of first to N-th output terminals on which the drive voltages are developed, respectively. The breeder develops a set of first to N-th different voltages on first to N-th nodes, respectively, N being any integer equal to or more than 2, and the first to N-th voltages being associated with grayscale levels, respectively. The switch circuitry switches connections among an input and an output of the buffer amplifier, the first to N-th nodes, and the first to N-th output terminals.

1. Field of the Invention
The present invention relates to drive voltage generator circuits, LCD (liquid crystal display) drivers, and liquid crystal display apparatuses. More particularly, the present invention relates to generation of drive voltages (which may be called grayscale voltages) within LCD drivers.
2. Description of the Related Art
Recent mobile electronic apparatus, such as cellular phones, often incorporate liquid crystal display apparatuses for man-machine interface. Requirements of liquid crystal display apparatuses incorporated within mobile electronic apparatuses include reduction in the circuit size and power consumption of hardware implementations. One approach for reducing the circuit size and power consumption is to incorporate a reduced number of circuitries within liquid crystal display apparatuses.
A typical liquid crystal display apparatus is composed of an LCD driver and an LCD panel. A typical LCD driver includes a grayscale voltage generator and a drive circuitry. The grayscale voltage generator generates a set of different grayscale voltages. The drive circuitry selects the grayscale voltages in response to pixel data, which are digital data representative of desired grayscale levels of the associated pixels, and outputs the selected grayscale voltages to drive the associated signal lines (or data lines) within the LCD panel.
In order to drive signal lines within an LCD panel immediately, driving the signal lines are often achieved by using buffer amplifiers incorporated within the LCD driver, which are each composed of a source follower having a gain of 1.
In a typical LCD driver configuration, as disclosed as a prior art in Japanese Laid-Open Patent Application No. P2002-108301A, buffer amplifiers are provided for respective LCD driver outputs used for providing desired drive voltages for signal lines of an LCD panel.
FIG. 1 illustrates the disclosed LCD driver structure. The disclosed LCD driver is composed of a serial-parallel shift register 1, a set of m data latches 2, a load latch circuit 3, a level shifter 4, a digital/analog (D/A) converter 5, a buffer amplifier circuit 6, and a breeder 7, m being a natural number. The buffer amplifier circuit 6 composed of a set of m buffer amplifiers 61 to 6m, outputs of which are respectively connected to m signal lines disposed within an LCD panel through a set of m outputs terminals of the LCD driver.
The shift register 1 is used to develop a set of m latch signals in response to an externally inputted shift pulse signal and transfer clock. The shift register 1 sequentially latches and shifts data bits of the shift pulse signal in synchronization with a transfer clock, and thereby develops the set of m latch signals on the parallel outputs.
The data latches 2 are each designed to latch the associated pixel data in synchronization with the associated latch signal.
The load latch circuit 3 latches the outputs of the data latches 2 in response to a load signal at the same timing.
The level shifter 4 provides level shifting between the outputs of the load latch circuit 3 and the inputs of the D/A converter 5.
The breeder 7 divides an external voltage by using a set of serially connected resistors, and thereby generates a set of n (=2k) different grayscale voltages, k being a natural number.
The D/A converter 5 selects one of the grayscale voltages for each signal line in response to the associated pixel data.
The buffer amplifiers 61 to 6m receive the associated grayscale voltages from the D/A converter 5, and provide buffering for the received grayscale voltages to develop a set of drive voltages. The drive voltages outputted from the buffer amplifiers 61 to 6m are substantially identical to the associated grayscale voltages, received from the D/A converter 5. The drive voltages are outputted to the signal lines of the LCD panel.
One drawback of this LCD driver architecture is that this LCD driver architecture requires increasing the number of the buffer amplifiers 61 to 6m for increasing the number of the outputs of the LCD driver. Increasing the screen size and/or fineness of the liquid crystal panel requires increasing the number of the signal lines of the liquid crystal panel, that is, the number of the buffer amplifiers disposed within the LCD driver. The increased number of the buffer amplifiers undesirably increases the circuit size and power consumption of the LCD driver.
In order to solve this drawback, an improved LCD driver structure has been proposed in the aforementioned Japanese Laid-Open Patent Application No. P2002-108301A, which incorporates one buffer amplifier for each grayscale voltage. This effectively allows increasing the number of LCD driver outputs without increasing the number of buffer amplifiers.
FIGS. 2 and 3 illustrate the proposed LCD driver structure. Referring to FIG. 2, the disclosed LCD driver is composed of a serial-parallel shift register 1, a set of m data latches 2, a load latch circuit 3, a level shifter 4, a decoder circuit 21, an output selector circuit 22, a buffer amplifier circuit 6, and a breeder 7; it should be noted that same numerals denote the same, similar, or equivalent elements in the specification. The disclosed LCD driver additionally includes a pixel data enable circuit 23, a pixel mode circuit 24, and an amplifier enable circuit 25.
As shown in FIG. 3, the buffer amplifier circuit 6 and the breeder 7 constitute a drive voltage generator circuit 10 that generates a set of drive voltages associated with grayscale levels, while the load latch circuit 3, the decoder circuit 21, and the output selector circuit 22 constitute a drive circuitry 20 designed to output a selected one of the drive voltages on each output terminal.
The breeder 7 is composed of a set of resistor elements R0 to Rn serially connected between the power supply VH and ground VL to generate n different grayscale voltages associated with different grayscale levels; n is the number of available grayscale levels, equal to 2k, where k is the number of data bits of each pixel data. The resistor element Rw is connected to the adjacent resistor element Rw−1 with a node TPw disposed therebetween, where w is any integer ranging from 1 to n. Such connection provides different voltages on the nodes TP1 to TPn; the voltages developed on the nodes TP1 to TPn are denoted by numerals V1 to Vn, respectively.
The buffer amplifier circuit 6 includes a set of n buffer amplifiers AM1 to AMn each having a gain of 1. The inputs of the buffer amplifiers AM1 to AMn are connected to the node TP1 to Tpn, respectively. The buffer amplifiers AM1 to AMn provide buffering for the grayscale voltages received from the nodes TP1 to TPn, respectively. The buffer amplifiers AM1 to AMn develops drive voltages on the output terminals, denoted by numerals LV1 to LV1, respectively. The drive voltages developed on the output terminals LV1 to LVn are ideally identical to the voltages V1 to Vn developed on the nodes TP1 to TPn, respectively. The drive voltages developed on the output terminals LV1 to LVn are used for driving the signal lines of the LCD panel, denoted by numeral 30 in FIG. 3.
The load latch circuit 3 is composed of a set of m latches 31 to 3m, and the decoder circuit 21 is composed of a set of m decoders 211 to 21m. Additionally, the output selector circuit 22 is composed of a set of multiplexers 221 to 22m that functions as D/A converters. The outputs of the latches 31 to 3m are connected to the inputs of the decoders 211 to 21m, respectively. The outputs of the decoders 211 to 21m are connected to the select inputs of the multiplexers 221 to 22m, respectively. The outputs of the multiplexers 221 to 22m are connected to the output terminals of the LCD driver, which are denoted by symbols OUT1 to OUTm, respectively. The output terminals OUT1 to OUTm are connected to the signal lines of the LCD panel 30.
The latches 31 to 3m latch externally inputted k-bit pixel data D1 to Dm, respectively, in synchronization with an externally inputted transfer clock CLK. The latched k-bit pixel data D1 to Dm are provided for the decoders 211 to 22m.
The decoders 211 to 22m decode the pixel data D1 to Dm.
The multiplexers 221 to 22m are each designed to select among the voltages V1 to Vn developed on the output terminals LV1 to LVn in response to the decoded pixel data D1 to Dm, respectively. When a pixel data Dv is "111111" with k=6, v being a natural number ranging from 1 to n, the multiplexer 22v selects the voltage Vn out of the voltages V1 to Vn. When a pixel data Dv is "000000", on the other hand, the multiplexer 22v selects the voltage V1 out of the voltages V1 to Vn. The multiplexers 221 to 22m provide the selected voltages for the LCD panel 30 through the associated output terminals OUT1 to OUTm.
An advantageous feature of the LCD driver structure shown in FIG. 3 is that the LCD driver is allowed to have an increased number of output terminals without increasing the number of the buffer amplifiers; the number of the buffer amplifiers is limited to the number of the available grayscale levels.
Recent requirements include the increase in the number of available grayscale levels; however, the LCD driver structure shown in FIG. 3 suffers from a problem that the number of the buffer amplifiers is increased in proportion to the number of available grayscale levels. In order to achieve 260k-color display, for example, the LCD driver structure shown in FIG. 3 requires 64 buffer amplifiers; it should be noted that 260k-color display requires 64 grayscale levels for each R, G, B color component. The LCD driver structure shown in FIG. 3 requires 256 or 1024 buffer amplifiers for achieving natural grayscale display, involving 256 (=28) or 1024 (216) grayscale levels for each R, G, B color component. As described above, the LCD driver structure shown in FIG. 3 requires increasing the number of the buffer amplifiers for increasing the number of available grayscale levels. This undesirably increases the circuit size and power consumption of the hardware implementation of the LCD driver.
Japanese Laid Open Patent Application No. P2000-98331A discloses another LCD driver structure for reducing the number of voltage followers within an LCD driver; however, this LCD driver structure addresses achieving frame-inversion driving of LCD segment display panels with a reduced number of voltage followers, and does not provide grayscale display.

Drive voltage generator circuit for driving LCD panel


A sensing system includes a housing having an inlet for receiving a fluid flow from a source and an outlet with for directing a fluid flow from the housing, wherein a longitudinal axis transverses a center of the inlet and the outlet; a flow conduit disposed in the housing and in fluid communication with the inlet and the outlet, the flow conduit having a cross-sectional area that is substantially the same as a cross-sectional area of the inlet and the outlet, wherein a first length of the flow conduit along a second axis, and wherein the first axis and the second axis are perpendicular to the longitudinal axis; a light source for illuminating the fluid in the flow conduit along the first axis; and a sensor for detecting contaminants in the fluid.

Systems for sensing the presence of particulate contaminants in transient fluids have been available for many years. In order to sense small particles, the sensor is made quite small. Typically, instead of actually measuring a complete fluid stream, a sampling of the main flow of a fluid is required. In order to obtain a representative, accurate sample, kinetic sampling must be done. However, this is very difficult to accomplish in practice, because sample flow rates must be tied to full stream flow rates.
In very clean conditions, with low particle concentrations, statistical methods to tie sample measurements to the main flow provide poor correlation. In some applications, sampling is not desired. For example, where the detection of a single particle is critical, sampling and associated statistical methods cannot be tolerated. As a result, a full flow sensor is required.
It would be desirable to develop a sensor system and a method for detecting contamination in fluids, wherein the sensor system and the method provide detection of small particles with maximized flow rates.

Full-flow sensor for contamination in fluids


A display device and a manufacturing method thereof with improved performance and low manufacturing complexity are provided. One inventive aspect includes: a first control electrode, a semiconductor layer, an etch stop layer, a first input electrode and a first output electrode, a third control electrode, a passivation layer and a pixel electrode. The third control electrode is formed on the etch stop layer. The passivation layer is formed on the first electrode, the first output electrode and the third control electrode. The pixel electrode is formed on the passivation layer and connects to the first output electrode.

1. Field
The disclosed technology relates to a display device and a manufacturing method thereof with improved performance and low manufacturing complexity.
2. Description of the Related Technology
A thin film transistor (TFT) for a flat panel display device, such as a liquid crystal display element, an electroluminescence display element or an inorganic electroluminescent element, is used as a switching element to control the operation of each pixel and a driving element to drive pixels.
In general, a TFT includes source and drain regions that are highly doped with impurities, an active layer, a gate electrode, and source and drain electrodes. The gate electrode is positioned at a position corresponding to the channel region and the source and drain electrodes respectively contact the source and drain regions.
The active layer is formed of a semiconductor material, such as amorphous silicon or polysilicon, and has a channel region, which is formed between the source and drain regions.
When the active layer is formed of amorphous silicon, it usually is difficult to embody a high speed driving circuit because carrier mobility, the mobility of electrons and holes, is low. When the active layer is formed of polysilicon, an additional compensation circuit is needed because the carrier mobility can be high and a threshold voltage Vth is not uniform. Recently, research for using an oxide semiconductor as an active layer have been conducted in order to solve the problem described above.
An oxide TFT using the oxide semiconductor as the active layer is easily implemented and can have a large area when manufactured in a low temperature process. In addition, an oxide TFT has a very favorable electrical property like polysilicon.
The above information disclosed in this Background section is only for understanding of the invention. It may contain information that does not constitute prior art.

Display device and manufacturing method thereof


A memory system with delay locked loop (DLL) bypass control including a method for accessing memory that includes receiving a memory read command at a memory device. The memory device is configured to operate in a DLL off-mode to bypass a DLL clock as input to generating a read clock. A DLL power-on command is received at the memory device and in response to receiving the DLL power-on command a DLL initialization process is performed at the memory device. The memory read command is serviced at the memory device operating in the DLL off-mode, the servicing overlapping in time with performing the DLL initialization process. The memory device is configured to operate in a DLL on-mode to utilize the DLL clock as input to generating the read clock in response to a specified period of time elapsing. The specified period of time is relative to receiving the DLL power-on command.

The present invention relates to memory systems, and more specifically, to delay locked loop (DLL) bypass control circuitry for use in a memory system.
As processor speeds continue to increase, memory performance becomes more of a limiting factor in system performance and therefore, memory performance must increase as well. An important aspect of increasing memory performance is increasing the speed at which data can be transmitted between elements (e.g., memory device, memory controller) in the memory system. In a typical memory system, synchronous communication is used to achieve high data transmission rates to and from the memory devices. Memory systems that communicate synchronously use a clock signal as a timing reference so that data can be transmitted and received with a known relationship to this reference. A difficulty in maintaining this relationship is that process, voltage, and temperature variations can alter the timing relationship between the clock and data signals, resulting in reduced timing margins. This problem can get worse as signaling speeds increase and may impact the ability of systems to communicate data at higher speeds.
Clock synchronous circuits such as phase lock loops (PLLs) and DLLs are typically used for maintaining the timing relationship between clock and data signals in a memory system. If the reference (or external) clock signal is different in frequency from an internal clock signal used to drive the data signals, then it is necessary to employ a frequency multiplying function, such as that provided by a PLL circuit. If the external clock signal is equal in frequency to the internal clock signal, then a DLL circuit is typically used to synchronize the internal clock signal used for inputting/outputting the data with the external clock signal.
A drawback to the use of DLLs is that they take a relatively large number of clock cycles to power-up once they have been turned off. This power-up delay time in DLLs contributes to an increased latency in memory access time. To avoid a DLL power-up delay from being added to memory access latency, a DLL may be left running (i.e., powered-on) when a memory device is in a reduced power mode, such as a standby mode. However, when the DLL is left running during standby mode, the DLL consumes a relatively large portion of the power required during memory standby, thus reducing power savings that can be achieved by putting a memory device in a low power mode.
Accordingly, and while existing memory systems may be suitable for their intended purpose, there remains a need in the art for memory systems that overcome these drawbacks.

Memory system with delay locked loop (DLL) bypass control

International Business Machines Corporation


A solid state accelerometer having an all silicon sensor for measuring accelerational and gravitational forces. The accelerometer measuring system also has associated electronics that include an analog rebalance loop and a digitizer loop.

The related art includes accelerometers of the piezo electric, silicon piezo resistive and capacitive kinds. However, there has been a need for an advanced-technology, near-chip-size accelerometer with high reliability and long-term accuracy. The present invention is a response to that need. The invention, the electrostatic silicon accelerometer, is a solid state accelerometer having the capabilities of complementing future inertial navigational systems based on either ring laser or fiber optic gyroscopes. The greatest problem plaguing present-day accelerometers is long term drift that is virtually eliminated by the present invention. The invention has exceptional stability in terms of accuracy over extended periods of time, thereby eschewing the typical periodic calibrations necessary for related-art accelerometers. The major factor contributing to such stability is the single-material construction of the accelerometer.

Method of making an electrostatic silicon accelerometer


A photosensitive polysiloxane composition for forming a protective film having superior sensitivity is disclosed. A protective film formed from the photosensitive polysiloxane composition and an element including the protective film are also disclosed. The photosensitive polysiloxane composition includes a polysiloxane, an o-naphthoquinonediazidesulfonic acid ester, a urethane(meth)acrylate compound having at least six (meth)acryloyl groups in a molecule, and a solvent.

1. Field of the Invention
This invention relates to a photosensitive polysiloxane composition, more particularly to a positive photosensitive polysiloxane composition including a polysiloxane and a urethane (meth)acrylate compound having at least six (meth)acryloyl groups in a molecule. This invention also relates to a protective film formed from the photosensitive polysiloxane composition, and an element containing the protective film.
2. Description of the Related Art
In recent years, in the field of semiconductor industry, liquid crystal displays, and organic electroluminescence displays, it is required that the pattern details in photolithography process be higher due to element miniaturization.
Positive type photosensitive materials with high resolution and high sensitivity are adopted to obtain miniaturized patterns via exposure and development. The positive type photosensitive material containing a polysiloxane composition has been widely used in the art.
JP 2008-107529 discloses a photosensitive resin composition capable of forming a cured film. The photosensitive resin composition includes a polysiloxane, a quinonediazidesulfonic acid ester, and a solvent. The polysiloxane contains an oxetanyl group or a succinic anhydride group, and is obtained by subjecting a silane monomer containing an oxetanyl group or a succinic anhydride group to hydrolysis and partial condensation. The polysiloxane is formed with a hydrophilic structure via a ring-opening reaction during copolymerization, and thus has high dissolution in a dilute alkali developer. However, the sensitivity of the photosensitive resin composition is inferior and is not acceptable in the art.
It is still required in the art to provide a photosensitive resin composition which can be used to form a protective film having superior sensitivity which is acceptable in the art.

Photosensitive polysiloxane composition and applications thereof


A metal nanoparticle composition for the fabrication of conductive features. The metal nanoparticle composition advantageously has a low viscosity permitting deposition of the composition by direct-write tools. The metal nanoparticle composition advantageously also has a low conversion temperature, permitting its deposition and conversion to an electrical feature on polymeric substrates.

1. Field of the Invention
The present invention relates to metal nanoparticle compositions that are useful for the production of electrically conductive features. The compositions may advantageously be deposited on a variety of substrates and processed into electrically conductive features at low temperatures. The compositions can also have a viscosity which allows the deposition of the compositions using direct-write tools, such as ink jet devices.
2. Discussion of Background Information
The electronics, display and energy industries rely on the formation of coatings and patterns of conductive materials to form circuits on organic and inorganic substrates. The primary methods for generating these patterns are screen printing for features larger than about 100 μm and thin film and etching methods for features smaller than about 100 μm. Other subtractive methods to attain fine feature sizes include the use of photo-patternable pastes and laser trimming.
One consideration with respect to patterning of conductors is cost. Non-vacuum, additive methods generally entail lower costs than vacuum and subtractive approaches. Some of these printing approaches utilize high viscosity flowable liquids. Screen-printing, for example, uses flowable mediums with viscosities of thousands of centipoise. At the other extreme, low viscosity compositions can be deposited by methods such as ink jet printing. However, low viscosity compositions are not as well developed as the high viscosity compositions.
Ink-jet printing of conductors has been explored, but the approaches to date have been inadequate for producing well-defined features with good electrical properties, particularly at relatively low temperatures.
There exists a need for compositions for the fabrication of conductive features for use in electronics, displays, and other applications. Further, there is a need for compositions that have low processing temperatures to allow deposition onto organic substrates and subsequent thermal treatment. It would also be advantageous if the compositions could be deposited with a fine feature size, such as not greater than about 100 μm, while still providing electronic features with adequate electrical and mechanical properties.
An advantageous metal nanoparticle composition and its associated deposition technique for the fabrication of electrically conductive features would combine a number of attributes. The conductive feature would have high conductivity, preferably close to that of the pure bulk metal. The processing temperature would be low enough to allow formation of conductors on a variety of organic substrates (polymers). The deposition technique would allow deposition onto surfaces that are non-planar (e.g., not flat). The conductor would also have good adhesion to the substrate. The composition would desirably be inkjet printable, allowing the introduction of cost-effective material deposition for production of devices such as flat panel displays (PDP, AMLCD, OLED). The composition would desirably also be flexo, gravure, or offset printable, again enabling lower cost and higher yield production processes as compared to screen printing.
Further, there is a need for electronic circuit elements and complete electronic circuits fabricated on inexpensive, thin and/or flexible substrates, such as paper, using high volume printing techniques such as reel-to-reel printing. Recent developments in organic thin film transistor (TFT) technology and organic light emitting device (OLED) technology have accelerated the need for complimentary circuit elements that can be written directly onto low cost substrates. Such elements include conductive interconnects, electrodes, conductive contacts and via fills.


A vehicular image synthesis apparatus include a plurality of cameras mounted on a vehicle for capturing an image of a driver. The plurality of images captured by the plurality of cameras may be compared to detect a boundary suitable for synthesis. The plurality of images may be synthesized at the boundary.

There is a device in which (i) a face image of a driver is captured by a camera while a driver is driving a vehicle, (ii) the driver's state such as dozing or looking aside is detected based on the captured face image, and (iii) an alarm is issued when it is determined that the driver cannot drive safely. Since the driver visually recognizes the meter on the instrument panel of the vehicle during driving, the camera for capturing the driver's face is installed near the meter of the vehicle.


There is provided a data processing apparatus for segmental processing of input data. The apparatus includes a plurality of data processors connected in a series configuration, the plurality of data processors being able to transmit discrete data packets over a video bus to one another, with the plurality of data processors being divided into a plurality of data processing sets; and a central controller coupled to the plurality of data processors for controlling allocation of the input data to the plurality of data processing sets, the central controller being also for controlling transmission of output data from the apparatus. The apparatus incorporates several varying methods for data transmittal amongst data processors and has several applications which will be described.

Advances in quantitative computing power for data processors has led to improvements in apparatus used for reproduction of media content for users. Typically, the media content may be said to be in a high definition format, with high definition being in relation to image quality of the media content and the clarity of the audio quality of the media content. It should be appreciated that high definition image quality is typically understood to mean a resolution of at least 1080 p (resolution of 1920×1080) while the high definition audio quality is typically understood to mean audio quality (including speech, background sounds and effects) which is clearly perceptible to a listener. It should also be noted that media content may include a video conferencing stream.
The aforementioned apparatus for facilitating reproduction of high definition media content typically requires higher performance than what is usually available from a single data processor. Typically, two or more data processors may be used to achieve the required performance, but may fail if data is unable to be transmitted between the data processors at an adequate speed (transfer rate). In order to manage the cost of the aforementioned apparatus, the processors being selected for use in the apparatus are typically low cost processors that do not have a large number of available data pins to serve as processor-to-processor connections.
Typically, a low cost processor used primarily for processing of media content would have an output video bus for driving a display, and would similarly have an input bus for accepting data from a sensor. An output video bus of one processor may be joined to an input bus of another processor to form a data transmission channel if the protocols are compatible. However, video buses are designed to stream data continuously and are not suitable for transmitting discrete data packets. Furthermore, a well known property of video relates to how it repeats every frame with the same timing, and this property is typically used to load data in a FIFO manner in preparation for the next frame. The continuous nature of video transmission makes it difficult to use the same protocol for conventional data transmission which takes place when required and without periodic behaviour.
Thus, it is desirable to provide an apparatus for data processing of media content using video bus as a data transmission channel without suffering any detriment in relation to both cost and performance of the apparatus.

Data processing apparatus for segmental processing of input data, systems using the apparatus and methods for data transmittal


An output feedback control circuit for an integrated circuit (IC) device is disclosed which includes an I/O line sense amplifier for amplifying the weak signals read out from cells, a read driver for amplifying the output of the I/O line sense amplifier, an output latch/transmission block for latching or transmitting the output signals of the read driver, a precharge block for precharging the output node of the output latch/transmission block, and a state transition detecting block for generating feedback control clocks. If the circuit of the present invention is installed to the output terminal of an IC decive, the data latched at the output node can be maintained regardless of the intruding of an external noise until a precharge clock is generated at a new cycle. Further, the sense amplifier and the read driver are disabled after having amplified the input signals within a single cycle, and therefore, the DC power consumption can be prevented.

In the semiconductor manufacturing fields, the motive for developing high density semiconductor devices, i.e.. ICs of over the VLSI scale lies in the fact that the price per IC unit can be lowered by increasing the chip density. In this connection, the structure of transistors and the design of cells have been developed to reduce the occupied area for a basic cell.
For example, in designing the cells of RAM (random access memory) in which writing and reading of data are possible, the structure of the cell has been advanced from a dynamic 4-transistor cell derived from a flip-flop circuit, via a 3-transistor cell sharing the feedback paths between cells, to a 1-transistor cell consisting of a single MOS transistor and a single capacitor for storing charges.
However, in the process of increasing the density by reducing the occupied area of the basic cell or by simplifying the structure for the basic cell which constitutes a certain function block, various problems have been produced due to the very simplicity of the structure. For example, in the case of a RAM consisting of 1-transistor cells, the gate capacitance itself is not enough for the storage capacitor.
For this reason, there is the hazard that the stored data can be damaged when reading out the data, and further, a highly sensitive amplifier is needed because of extreme weakness of the output voltage (Refer to "Storage Array and Sense/Refresh Circuit for Single Transistor Memory Cells" by Stein, K.U. et al., IEEE Journal of Solid State Circuits, SC-7, No. 5, pp. 336-40).
However, even if an amplifier capable of amplifying the extreme weak voltage with a high amplifying ratio is provided, and further if the amplifier consists of a static amplifier, when an external noise intrudes upon the output of the cell, then the static amplifier will amplify the deformed cell output including the external noise, with the result that undesirable signals will be continuously outputted.

Output feedback control circuit for integrated circuit device


A screwholder adapted to be mounted over a screwdriver shank that includes an outwardly flared blade section adjacent a screwdriver tip is disclosed. The screwholder includes a hollow extension tube that mounts over the screwdriver shank. One end of the hollow extension tube has an enlarged section for engagement and displacement along the screwdriver shank by the thumb of a user. The other end of the hollow extension tube includes screw gripping fingers for gripping a screw. The screw gripping fingers extend upwardly from the hollow extension tube and are captured between an inner retaining plate and an outer housing. The screw gripping fingers further have outer free ends for gripping opposed areas of a screw. A compressible spring is positioned within the outer housing between the inner retaining plate and the hollow extension tube. The inner retaining plate includes a restricted opening for engaging the outwardly flared blade section of the screwdriver which causes compression of the compressible spring to enable the outer free ends of the screw gripping fingers to be moved apart for release or gripping of opposite areas of a screw.

The present invention relates to a screwholder for a screwdriver, and more particularly, to a low cost and reliable screwholder for a screwdriver.
As screwdrivers have been developed over the years, efforts have also been underway in developing various types of devices for holding a screw in cooperating engagement with the screw engaging/driving or tip end of a screwdriver. For example, in the early 1900's, several types of screwholders for screwdrivers were developed as represented by U.S. Pat. Nos. 864,633 (1907); 951,526 (1910); and 1,212,743 (1917). Each of these patents disclose spring urged gripping fingers where an exposed coil spring surrounds a screwdriver shank and functions to urge a pair of screw gripping fingers into gripping engagement with a screw adjacent the screw engaging/driving or tip end of a screwdriver. There are other examples in the prior art where an outer housing protectively surrounds a coil spring operating to urge screw gripping fingers of a screwholder into gripping engagement with the screw. Examples of such screwholder devices include U.S. Pat. No. 1,641,307 which employs a hexagonally shaped enclosed outer housing and U.S. Pat. No. 2,633,168 where a cylindrically shaped enclosed outer housing as disclosed. At the same time, it has been found desirable to provide a thumb disk or shoulder adjacent the screwdriver handle to operate the screwholder device. Examples of thumb disk/shoulder operative screwholder devices are shown, for example, in U.S. Pat. Nos. 2,762,408 and 2,933,114.
While each of the aforementioned and other prior art screwholder devices provide some of the features desirable in a preferred screwholder device, it is apparent that such prior art devices have not fully met market demands. In this connection, it has been determined from market studies that a screwholder with the following functional and structural features would be most desirable:
1. Single handed screwholder operation.
2. Thumb operation of the screwholder device.
3. Expanding/retracting screw gripping fingers associated with the screwholder.
4. Reduced screwholder components using standard parts where possible.
5. Improved manufacturability and assembly of screwholders.
6. Improved screwholder reliability during repeated use.
The screwholder device of the present invention has been developed with the foregoing design criteria in mind, as will become apparent from the description that follows.


A voice packet forwarding apparatus and method is provided in a digital communication system including a switched vocoder module to directly pass a voice packet received from a packet terminal to a digital communication network or a PCM signal decoded from the voice packet to the digital communication network. The switched vocoder module is also provided to directly pass a voice packet received from the digital communication network to the packet terminal or transmit a voice packet coded from a PCM signal received from the digital communication network. In the presence of additional data to be transmitted to the packet terminal, a data inserter is provided to insert the additional data in the voice packet received from the switched vocoder module and transmit the voice packet with the additional data to the packet terminal. A controller is provided to control the switched vocoder module and the data inserter.

1. Field of the Invention
The present invention relates generally to a digital communication system. In particular, the present invention relates to an apparatus and method for forwarding voice packets over a network.
2. Description of the Related Art
A voice coder, namely a vocoder is used to reduce the amount of data taken to transmit information in digital voice communications. The vocoder, which is a combination of a voice encoder and a voice decoder, exists between a terminal and a communication system. The voice encoder converts an input Pulse Code Modulation (PCM) voice signal to a very small-size voice packet by using a predetermined coding algorithm. The voice packet is delivered to a destination through the communication system and the voice decoder recovers the voice packet to the original PCM voice signal by using a predetermined algorithm. Under this typical communication environment, voice communications are conducted in the order of input-coding-transmission-decoding-output. Coding-decoding can be repeated many times in a particular communication environment.
Many types of vocoders are available to digital mobile communication systems like Voice over Internet Protocol (VoIP), but different vocoders are not compatible with each other. Some vocoders support generation of voice packets at a plurality of data rates. These vocoders are called variable-rate vocoders. Typical examples of the variable-rate vocoders are Qualcomm Code Excited Linear Prediction (QCELP) and Enhanced Variable Rate Codec (EVRC) used for Code Division Multiple Access (CDMA). The variable-rate vocoders encode a voice signal according to the characteristics of the input voice signal or at a data rate requested by the communication system. With respect to a full rate, QCELP and EVRC can encode voice packets at a rate of ½, ¼ or ⅛.
There are generally two types of terminals in digital communications. One is a packet terminal that includes a vocoder and which transmits/receives voice packets to/from a communication system. A mobile terminal for digital mobile communications is a typical example. The other is a Public Switched Telephone Network (PSTN) terminal connected directly to a PSTN, for voice communications. The PSTN terminal does not have a vocoder and transmits/receives an analog signal to/from the communication system.
In the digital communication system, the transport format of a voice packet is determined according to the types of terminals and the positions and operations of vocoders, and communication performance is correspondingly determined. Best performance can be achieved by appropriately determining the position and operation of at least one vocoder according to the characteristics of two terminals connected for communication and their communication environment. The factors affecting the determination include the types of the terminals, the types of vocoders used in the terminals, packet data rate, transmission or non-transmission of additional data, and transmission or non-transmission of a message.
During communications between a packet terminal and a PSTN terminal, upon receipt of a voice packet from the packet terminal, a voice decoder in a communication system converts the voice packet to a PCM signal and provides it to the PSTN terminal. Upon receipt of a PCM signal from the PSTN terminal, a voice encoder in the communication system converts the PCM signal to a voice packet and provides it to the packet terminal. In the case of transmitting voice information together with a message to the packet terminal, the communication system decreases the data rate of the voice packet, relying on the features of the variable-rate voice encoder and inserts as much of the message as the rate decrease in the voice packet allows, prior to transmission. For this purpose, such a module generates control/signaling messages and adjusts the data rates of voice packets that may reside in the communication system. The packet terminal extracts the voice information and the message separately from the received voice packet and recovers the voice information to the PCM voice signal.
In a CDMA mobile communication system, for example, upon generation of a message to be transmitted to a Mobile Station (MS) on a radio channel, a Base Station (BS) decreases the rate of a voice packet destined for the MS to, for example, ½ and inserts the message in the voice packet. This message transmission scheme is called "Dim and Burst". In an extreme case, the rate of the voice packet is decreased to zero and only the message is constructed into a packet. This scheme is called "Blank and Burst". Due to the entire loss of the voice information at a message transmission time point, the Blank and Burst method is inferior to the Dim and Burst method in terms of voice quality.
In communications between two terminals, if each use the same kind of vocoders, the communication system forwards an input voice packet to the peer terminal for normal communications. This is called "Packet Bypass". However, if the two terminals use different, incompatible kinds of vocoders, the communication system converts an input voice packet appropriately. As described above, if additional data is to be inserted in a voice packet, even when the same kind of vocoders are used, the rate of the voice packet typically must be reduced. Consequently, voice packet conversion is required for transmission.
The steps by which voice packets are transmitted and processed depend on a communication environment in the digital communication system. Traditionally, voice packets are forwarded in the following way.
FIG. 1 illustrates a configuration of a typical PSTN-based voice packet forwarding system.
Referring to FIG. 1, when a call is set up between a first packet terminal 110 and a PSTN terminal 102, a voice encoder of the first packet terminal 110 converts an input voice signal to a voice packet 112. A first voice decoder 114 generates a PCM voice signal 116 from the voice packet 112 by using the same voice decoding scheme as used in the first packet terminal 110. A PSTN switch (not shown) in a network 100 converts the PCM voice signal 116 to an analog signal 104 and provides the analog signal 104 to the PSTN terminal 102.
The PSTN switch of the network 100 converts an analog signal 106 received from the PSTN terminal 102 to a PCM signal 118. A first voice encoder 120 converts the PCM signal 118 to a voice packet 122 by using the same voice coding scheme as used in the first packet terminal 110.
If there is no need for inserting additional data such as a control/signaling message, the voice packet 122 bypasses a first data inserter 124, thus maintaining its data rate. This voice packet 126 with the same data rate, is provided to the first packet terminal 110. However, in the presence of additional data to be transmitted to the first packet terminal 110, the first voice encoder 120 generates the voice packet 122 at a decreased rate. The first data inserter 124 inserts the additional data in the voice packet 122 and transmits the resulting voice packet 126 to the first packet terminal 110. The first packet terminal 110 converts the voice packet 122 to a PCM signal by using its voice decoding operation and outputs the PCM signal audibly to a user.
Regarding packet transmission and processing between the first packet terminal 110 and a second packet terminal 130, the first voice decoder 114 converts the voice packet 112 from the first packet terminal 110 to the PCM signal 116 and transmits the PCM signal 116 to a second voice encoder 136 through the network 100. As the PCM signal 116 passes through the network 100, it becomes a PCM signal 134. The second voice encoder 136 generates a voice packet 138 from the PCM signal 134 by using the same voice encoding scheme as used in the second packet terminal 130. A second data inserter 140 generates a voice packet 142 by inserting additional data in the voice packet 138 and transmits the voice packet 142 to the second packet terminal 130. Communications in the direction from the second packet terminal 130 to the first packet terminal 110 are conducted in substantially the same manner through a second voice decoder 132, the network 100, the first voice encoder 120, and the first data inserter 124.
As described above, coding-decoding is repeated in the process of input-coding-decoding-coding-decoding-output in a total single direction communication path. This is called Tandem Coding. In contrast, one coding-decoding is performed for communications between the first packet terminal 110 and the PSTN terminal 102.
While the typical system configuration illustrated in FIG. 1 is applicable to all communication environments, it suffers from communication quality degradation caused by information loss from repeated coding-decoding operations. To solve this problem, another system configuration has been developed and is illustrated in FIG. 2.
FIG. 2 illustrates the configuration of a typical voice packet forwarding system supporting packet bypass. As illustrated in FIG. 2, if first and second packet terminals 202 and 210 use the same type of vocoders, each of them can interpret voice packets received from the peer terminal. Hence, no particular processing is needed for packet transmission between the first and second packet terminals 202 and 210.
Referring to FIG. 2, a voice packet from the first packet terminal 202 is directly provided to a network 200 by use of a bypass 204. The network 200 forwards the voice packet to the peer party in substantially the same manner. The voice packet is output from the network 200 by use of a bypass 214. If the bypassed voice packet from the network 200 has a full rate and a second data inserter 216 is to insert additional data in the voice packet, the second data inserter 216 deletes voice information in the voice packet and forms a new voice packet with the additional data only by using a Blank and Burst method.
In the opposite direction, a voice packet from the second packet terminal 210 is directly provided to the network 200 by use of a bypass 212. The network 200 forwards the voice packet to a first data inserter 208 by use of a bypass 206. Similarly, the first data inserter 208 forwards the bypassed voice packet to the first packet terminal 202, or when needed, generates a new voice packet with additional data only, and transmits the new voice packet to the first packet terminal 202.
Since one coding-decoding is sufficient in the system illustrated in FIG. 2, voice quality is improved relative to that in the system of FIG. 1. Forwarding a voice packet without any further processing is called "Packet Bypass" or "Tandem-Free Operation".
Despite the benefit of improved voice quality between packet terminals, the above system has many constraints in its applicability. If the two packet terminals 202 and 210 use different kinds of vocoders, the Tandem-Free Operation is not viable. In addition, since Dim and Burst is used in the case of decreasing a packet rate to insert additional data during packet transmission, voice quality is decreased.
FIG. 3 illustrates the configuration of another typical voice packet forwarding system using a packet converter and a bypass instead of a voice decoder and a voice encoder.
Referring to FIG. 3, during communications from a first packet terminal 222 to a second packet terminal 230, a voice packet from the first packet terminal 222 is provided to a second packet converter 236 through a bypass 224 and a network 220. The second packet converter 236 converts the voice packet in substantially the same manner as used in a vocoder of the second packet terminal 230 or at a system-requested data rate. If data is to be inserted, a second data inserter 234 inserts the data in the converted voice packet. An empty space for the data insertion is prepared by the second packet converter 236. The voice packet from the second data inserter 234 is then forwarded to the second packet terminal 230.
In the opposite direction, a voice packet from the second packet terminal 230 is provided to the network 220 through a bypass 232. The network 220 forwards the voice packet to a first data inserter 228 through a first packet converter 226. The first data inserter 228, when needed, inserts additional data in the voice packet and provides it to the first packet terminal 222. An empty space for the data insertion is prepared by the first packet converter 226.
If the two terminals 222 and 230 use the same kind of vocoders and no rate conversion is required, the packet converters 226 and 236 function virtually as bypasses without any practical packet conversion. Voice packet forwarding performance is determined predominantly by the performance of the packet converters 226 and 236, and the tandem operation as illustrated in FIG. 1 is avoided. Therefore, the system of FIG. 3 outperforms that of FIG. 1. Furthermore, additional data transmission is possible in the Dim and Burst manner by using rate conversion in the packet converters 226 and 236.
However, voice packet conversion involves re-search or quantization of many voice parameters that determine the characteristics of an input voice signal beyond simple bit reordering or format conversion. Therefore, the voice packet conversion requires very complex mathematical computations.
In this regard, the above-described voice packet forwarding methods have their own drawbacks. The communication system illustrated in FIG. 1 is most typical and applicable to any communication environment, but faces the problem of voice quality degradation caused by tandem coding. Despite increased voice quality through voice packet bypass compared to the communication system of FIG. 1, the applicability of the communication system illustrated in FIG. 2 is limited to an environment where two terminals use the same kind of vocoders. In addition, when additional data such as a control/signaling message is generated, voice quality is decreased because of the Blank and Burst method used.
While the system illustrated in FIG. 3 is effective in solving the problems of the systems illustrated in FIGS. 1 and 2, packet conversion is performed on all possible combinations of different voice packets for every kind of vocoder available for communications, and rate conversion is also needed for each variable-rate vocoder. Moreover, in the case of using a new kind of vocoder, the system configuration and operation needs to be modified to support packet conversion between the new kind of vocoder and every existing vocoder.
Once one of the schemes illustrated in FIGS. 1, 2 and 3 is chosen at a call connection according to a communication environment, the chosen scheme is kept unchanged during the call. That is, the voice packet forwarding schemes are mutually independent without compatibility between them. However, it may occur that a communication environment for a packet terminal is changed during a call due to handoff in mobile communications, for example, such that the type of vocoder is changed or the data rate of a channel is restricted. In this case, the use of the above described technology brings distinctive interruptions when the environment is changed, thereby decreasing voice quality and creating noise.
Accordingly, there exists a need for developing a voice packet forwarding system and method that ensures excellent performance against frequent changes in communication environments.

Apparatus and method for forwarding voice packet in a digital communication system