A method and system are described herein for obtaining IGP network information useful in determining network routing topologies. The method involves querying a router for its router identifier and all its area identifiers, counting the router""s number of area identifiers to determine whether the router is an ABR or an ASBR, and querying the router""s link state database for the lowest area identifier on the router. The method further involves importing all Type 1 and Type 2 LSAs for that area into the database of a network discovery software engine, importing from the router""s link state database only those networks outside the router""s autonomous system that are also directly connected to an ASBR, then moving to the next highest area identifier in the router""s database to repeat importing Type 1 and Type 2 LSAs for that area into the database. Next, the method involves importing from the router""s link state database only those networks outside the router""s autonomous system that are also directly connected to an ASBR. This process is repeated until there are no more areas on the router that have not been processed. Then, starting with the lowest area identifier discovered, all networks in the area making LSAs other than Type 1 or Type 2 are swept. The entire process is repeated for every router discovered.

A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
This invention relates to computer networks. More particularly, the invention relates to methods and systems for determining a routing topology of a computer network by obtaining and utilizing Interior Gateway Protocol (IGP) routing information or Exterior Gateway Protocol (EGP) routing information.
Computer networks are growing in complexity and criticality. For example, a large corporation may support a computer network with tens of thousands of individual computers and thousands of network routers, hubs, repeaters or other network connectivity hardware. These networks are in many cases vital to an organization""s functioning, and in some cases are mission- or life-critical.
Because of increasing network size and complexity, service provider networks (such as Internet service providers or application service providers) in particular are quickly growing beyond the ability of current methods to manage them. For example, the typical level of modification and reconfiguration in a complex service provider network is at best difficult and time-consuming to understand or document.
Although several commercially and freely available software packages attempt to address network complexity problems, and some theoretical work has been done in this field, effective solutions to comprehensive network management problems in complex networks remain elusive or non-existent.
Increasingly, the problem in a large, complex network is not a change in the actual physical topology. There are known methods for solving the problem of single points of failure and link layer failures. For example, protection switching on the SONET layer of a network, as known to one skilled in the art, can address physical topology management issues such as single points of failure or link layer failures among other things. The automatic protection switching (APS) feature is supported, for example, on Cisco 7500 series routers and Cisco 12000 series routers, which allow switchover of packet-over-SONET (POS) circuits in the event of circuit failure, and is often required when connecting SONET equipment to Telco equipment. Here, APS refers to the mechanism of using a xe2x80x9cprotectxe2x80x9d POS interface in the SONET network as the backup for a xe2x80x9cworkingxe2x80x9d POS interface. When the working interface fails, the protect interface quickly assumes its traffic load.
The problem in many service provider networks is the topology change produced by the routing protocols. Routing protocols and routing policies are how service providers control traffic and manage traffic across their network and with other service provider networks. For example, a large service provider network may have a relatively stable configuration of computing nodes and interconnection hardware, which can dynamically load balance a variety of incoming network traffic primarily through packet traffic rerouting. Thus, when one node on the service provider network is overwhelmed by traffic, software methods can be used to reconfigure routers and compute nodes so that incoming traffic is redistributed and congestion is decreased or eliminated.
The existing efforts in this area are concerned with discovering physical networks and physical topologies, not routing topologies. However, physical topologies alone do not necessarily provide a complete and accurate representation of the topology of information flow in a network or networks, which is affected not only by the topology but also by routing considerations. For example, even though a router may be directly connected to a particular network or networks, traffic bound for that network or those networks may never cross that router. The actual flow of packets through the network or networks is controlled by the routing protocols via techniques known to those skilled in the art of network management, such as, for example, route summarization (where an internetwork is divided into logical areas, with each area""s border router advertising only a single summary route to other areas in order to reduce routing table size), route filters (where an additional metric rates relative reliability of individual networks as a source from which to determine optimal routes), and related routing polices.
As a further example, physical topology alone does not take into account information flow within a network as affected by multiple routers being directly connected to a particular network. How the traffic bound for that network is distributed, if at all, across those routers is a result of specific settings in the routing protocols. Thus, by changing settings in the routing protocols, traffic distribution, and thus routing topology, is fundamentally altered.
In terms of the ISO/OSI network model, (described in Douglas Comer""s two volume work entitled xe2x80x9cInternetworking with TCP/IP,xe2x80x9d which is hereby incorporated by reference), previous work is focussed on understanding layer 2 and layer 3 topologies. The previous work does not analyze or take into account actual traffic flow.
While several commercial products for determining network topology are available, these products have serious drawbacks relating to their inability to take into account routing topology. For example, HP""s Openview does not consider subnet masks. Other commercial products such as Riversoft""s Openriver do not take into account routing protocols at all.
As recognized by the inventors, IGP information, such as may be obtained by IGP link state databases, may be particularly useful in determining routing topologies. However, the existing methods do not utilize IGP information in routing topology determination. Thus, there is a need in the art for a method of determining routing topology of a computer network, particularly in the context of complex networks, and for obtaining IGP information useful in determining routing topology of a computer network.
It is an object of the present invention to solve the problems described above associated with existing methods of determining network topologies.
It is still another object of the invention to provide a method for determining routing topologies in networks, including complex networks.
It is still another object of the invention to provide a method for determining routing topologies in networks, including complex networks, that takes into account actual packet routing traffic flows and routing topologies.
In one embodiment, the invention provides a method and system for determining routing topology in a computer network, and comprises obtaining IGP information, obtaining EGP information, and utilizing the IGP and EGP information to determine network topologies.
In another embodiment, the invention provides a method and system for determining routing topology in a computer network, and comprises obtaining IGP information to determine the effects of routing protocols on network topology; obtaining EGP information by obtaining Border Gateway Protocol (BGP) information utilizing an EGP peer; and utilizing the IGP and EGP information to create topological network views.
In still another embodiment, the invention provides a method and system for obtaining IGP information by querying IGP link state databases.
In still another embodiment, the invention comprises a method for obtaining IGP network information useful in determining network routing topologies, comprising querying a router for its router identifier and all its area identifiers, counting the router""s number of area identifiers to determine whether the router is an ABR or an ASBR, querying the router""s link state database for the lowest area identifier on the router, importing all the Type 1 and Type 2 LSAs for that area into the database of the network discovery software engine, importing from the router""s link state database only those networks outside the router""s autonomous system that are also directly connected to an ASBR, then moving to the next highest area identifier in the router""s database to repeat importing Type 1 and Type 2 LSAs for that area into the database of the network discovery software engine and importing from the router""s link state database only those networks outside the router""s autonomous system that are also directly connected to an ASBR repeating this process until there are no more areas on the router that have not been processed, then starting with the lowest area identifier discovered, sweeping all networks in the area making LSAs other than Type 1 or Type 2, and repeating the entire process for every router discovered.
In still another embodiment, a method in accordance with the invention comprises obtaining EGP information, useful in determining network routing topologies, by obtaining BGP information utilizing an EGP peer, by using a software based routing engine on a host that the network discovery software is installed on, configuring the routing software to enable the specific EGP and to announce only the host route to the software-based router, establishing a peer relationship with an EGP speaking router in the network, loading the EGP database from the EGP router, and importing the EGP database into the network discovery software for processing.
In still another embodiment, a method in accordance with the invention comprises obtaining and utilizing the IGP and EGP information, useful in creating topological network views, by instantiating the routing protocol created topology using routing and software methods described in U.S. Pat. No. 6,108,702 titled xe2x80x9cMethod and Apparatus for Determining Accurate Topology Features of a Network,xe2x80x9d issued Aug. 22, 2000 and incorporated herein by reference in its entirety, drawing a map of the network starting with IGP areas and allowing the user to select the BGP topology or the EGP topology including confederations, communities, and route reflectors.
In still another embodiment, the invention provides a method and system for determining routing topology in a computer network, and comprises obtaining IGP information to determine the effects of routing protocols on network topology using techniques described herein; obtaining EGP information by obtaining BGP information utilizing an EGP peer by using a software based routing engine on a host that the network discovery software is installed on, configuring the routing software to enable specific the EGP and to announce only the host route to the software-based router, establishing a peer relationship with an EGP speaking router in the network, loading the EGP database from the EGP router, and importing the EGP database into the network discovery software for processing; and utilizing the IGP and EGP information to create topological network views by instantiating the routing protocol created topology using routing and software methods described, for example, in the above referenced U.S. Pat. No. 6,108,702. The method further involves drawing a map of the network starting with IGP areas and allowing the user to select the BGP topology or the EGP topology including confederations, communities, and route reflectors.

Method and system for determining network characteristics using routing protocols


Certain embodiments described herein relate to a scanning controller configured produce a horizontal (H) and vertical (V) scanning control signal that is used to control a bi-axial scanning mirror of a scanning laser projector device, a system including such a scanning controller, and a method for generating such an H and V scanning control signal. In an embodiment, the H and V scanning control signal includes H scanning frequency content that is used to control a H scanning frequency of the bi-axial scanning mirror, and V scanning frequency content that is used to control a V scanning frequency of the bi-axial scanning mirror. To avoid cross talk, the scanning controller is configured to produce the H and V scanning control signal such that the H scanning frequency content has a null at DC, and the V scanning frequency content has a null at the H scanning frequency.

Miniature scanning projector devices can be integrated with or attached various types of devices, such as mobile phones, computers, media players and automotive heads up displays. Such scanning projector devices display images by producing light beams and using one or more scanning mirrors to raster-scan reflected light onto a surface. The scanning mirror(s) are controlled using a horizontal (H) scanning control signal and a vertical (V) scanning control signal, where the H scanning frequency has a much higher frequency than the relatively slower V scanning frequency. For example, the H scanning frequency can be about 22.5 KHz, whereas the V scanning frequency can be about 60 Hz. These systems suffer from crosstalk between the H and V scanning control signals, which has been shown to adversely affect the horizontal and vertical scanning control of the scanning mirror(s), which adversely affects the resulting image.

Systems and methods for controlling scanning mirrors for a display device


The present invention can include a panel assembly and method to make the panel assembly to be installed in an instrument panel, the panel assembly having a front panel and a side panel. The front panel and side panel can be covered with a flexible covering. The flexible covering on the front panel and the flexible covering on the side panel can be wrapped around the respective panel in a joint area where the front panel and side panel meet. A compression force in the joint area can help secure the flexible coverings. The front panel and/or the side panel can also have one or more attachment means, such as clips, fastener holes and the like for attaching the panel assembly to the instrument panel.

Instrument panels and instrument panel assemblies in modern vehicles continue to get more complicated and luxurious with every new model year. These instrument panel assemblies can include features such as air vents, speaker holes, storage areas and the like. To allow installation of these features, an increased amount of holes or apertures are required to be placed in the panel members themselves. Panel assemblies are also increasing in their complexity and luxuriousness in that they are being given various surface treatments or flexible coverings, such as leather, synthetic leather, fabric, flexible plastic and the like, to increase the luxury look and feel of the panels.
As panel assemblies grow in complexity in both shape and various coverings, a problem arises in that applying the flexible covering for the panel assembly having multiple or complicated features becomes difficult. The flexible covering can be difficult to adhere in areas around the holes for the vents, speakers and such, and also difficult to adhere in joining areas between panels. In addition, the flexible covering may have visible imperfections such as wrinkles, folds, or creases arising from the complicated shapes.
As such, it can be difficult to assemble and install the instrument panel assembly having the flexible covering. In addition, this creates a need for a new panel assembly design and method for installation that provides an acceptable product that does not have wrinkles, folds, or creases in the flexible covering on the panel.

Two-piece assembly for a wrapped panel having a hole or unique feature

Toyota Motor Engineering & Manufacturing North America, Inc.


A process for casting aluminum alloy parts is disclosed. The process includes the steps as follows: raising a liquid aluminum alloy; filling a mold; increasing pressure; solidifying formed by at least two stages of different pressure settings; and relieving pressure.

With the development of society, vehicles have become an indispensable means of transportation for people. Vehicle wheels are important parts in vehicles, which directly affect the safety of vehicles. Aluminum alloy wheels have the advantages of light weight, easy molding, good mechanical properties, physical properties, corrosion resistance, and the like, so they are widely used in the vehicle field.
For casting aluminum alloy wheels, low-pressure casting process is mainly used, and the low-pressure casting has the advantages of easy mechanization, good filling, high yield, suitable for mass production and the like, and the aluminum liquid is solidified under pressure during the casting process, so that the strength of the finished product after solidification is high. However, with the rapid development of the vehicle industry and the continuous improvement of safety requirements for aluminum alloy wheels, the problem of the insufficient comprehensive performance of wheel castings, especially the low elongation rate, is becoming increasingly prominent.

Process for casting aluminum alloy parts


The present invention provides a DC high voltage converter having an oscillator driver, main switch array and topological enhanced capacitors. The switch array utilizes MEM cantilevers and topological capacitors for charge storages for the generation of a high voltage output from a low voltage input.

The present invention relates to the field of micro-mechanical switching converters using micro-mechanical transducers. Micro-mechanical switching circuits provide many applications such as voltage converters, switching regulators, phase matching, etc. Mechanical and electronic switching circuits are widely used and micro-mechanical switching circuits can additionally be complimented with traditional switching devices.
MEMS switching converters are known in the art. The many benefits of a MEMS implementation for switching converters include; no voltage loss due to p-n junction, low ohm losses, radiation resistance, ability to convert voltage up and down, prolonged operation using hermetic seal with He gas, prolonged operation using Ir contacts, ability to charge all capacitors simultaneously or based on charge transfer, only simple vibrations necessary to drive the circuits, need for two power supplies for some converters. In the art, large surface area, low tolerance valued capacitors, such as topological capacitors, are integrated to realize these MEMS switching converters.
A prior art switching circuit configuration is illustrated with reference to FIG. 1. FIG. 1(a) illustrates a parallel-series converter as is known in the art. In this embodiment, the input and the output voltages are 1.5V and 12V, respectively. FIG. 1(b) illustrates a charge transfer converter as is known in the art which also has an input voltage of 1.5V and an output voltage of 12V. With reference to FIG. 2, in these embodiments, the required capacitor value for the charge transfer converter, operating frequency 1 kHz at 10% ripple, will be 1.5 nF to realize 12V from a 1.5V supply. In these prior art embodiments, solid-state switches are employed, such as transistors or diodes.
Accordingly, what is needed in the art is an efficient DC to DC high voltage converter that requires only simple vibrations to drive the circuits.


A compensation circuit and method for constant current regulation of switching mode power supply are disclosed. The ringing waveform of a feedback signal, indicative of the output current of the power supply, causes error. To eliminate the error, a current source charges a capacitor in response to a demagnetizing oscillation signal indicative of the error caused by the ringing waveform of the feedback signal. The voltage across the capacitor is compared to a reference signal to generate a more accurate signal indicative of the conductive time of a secondary diode in a secondary winding of the switching mode power supply. This more accurate signal is inputted to a logic circuit to generate a constant current control signal to control a power switch of the power supply.

There are many control methods for controlling an output current in switching mode power supplies (SMPS). BCD Semiconductor provides a primary side controller AP3708 (Preliminary Datasheet, Rev.1.0, 2008.09, http://www.bcdsemi.com) for controlling an output voltage and an output current. FIG. 1A schematically shows a switching mode power supply incorporating the controller AP3708.
In FIG. 1A, an input signal is applied to a first terminal of a primary winding Np. A second terminal of the primary winding Np is coupled to a transistor Q1, which is controlled to be on and off by the controller AP3708. When the transistor Q1 is turned on, a primary current Ip flows through the primary winding Np, which starts building up a magnetic energy. A secondary winding Ns coupled with a secondary diode D1 and a capacitor Co is magnetically coupled to the primary winding Np, wherein the capacitor Co has a relatively high capacity to stabilize the variation of a voltage Vo supplying to a load. The polarity (winding sense) of the secondary winding Ns is configured such that the magnetic field produced by the primary current Ip (when the transistor Q1 is turned on) induces a voltage that reverse biases the secondary diode D1. When the transistor Q1 is turned off, the sign of the time derivative of the magnetic field is reversed and a current Is is induced in the secondary winding Ns. A part of the current Is charges the capacitor Co and the rest is supplied to the load Ro. The capacitor Co maintains an output current lo flowing in the load by partly discharging while the secondary current Is stops flowing. This is the case when the energy in the magnetic field has been completely discharged.
In order to maintain a constant current at the load Ro, an auxiliary winding NAUX may be used. In this example, the auxiliary winding NAUX has the same polarity as that of the secondary winding Ns, and is coupled with a auxiliary diode D2 and a capacitor CAUX The auxiliary diode D2 coupled to the auxiliary winding NAUX is also reverse biased when the transistor Q1 is turned on; and an induced current is flowing through the auxiliary winding NAUX when the transistor Q1 is turned off. The induced current flowing through the auxiliary winding NAUX could be used as an indicator for the controller AP3708 to control switching the transistor Q1 to obtain a constant load current. However, the induced current could not be easily monitored. An alternative solution is to monitor a voltage waveform at the node 101 of the auxiliary winding NAUX. A resistor R1 is coupled to the node 101 to pick up the voltage waveform at the node 101, which may be further attenuated with a resistor R2 to form a feedback signal VFB at the node 102. In one embodiment, the feedback signal VFB may be an image of the voltage Vs across the secondary winding Ns, i.e., VFB is in the first order linearly proportional to the voltage at node 103 adjusted by a turns ratio and the voltage divider ratio.
While the transistor Q1 is turned on, the primary current Ip flows through a current sensing resistor Rcs, which produces a voltage Vcs to the controller AP3708. In one embodiment, the transistor Q1 is turned on when Vcs is below a predetermined value, and the transistor Q1 is turned off when Vcs is above the predetermined value.
FIG. 1B schematically shows a block diagram of the controller AP3708. In FIG. 1B, the constant current control circuit of the controller AP3708 comprises: a first comparator 201, a Tons (Tons represents the conduction time of the secondary diode D1) detector 202, a first current source 203, a second current source 204, a first switch 205, a second switch 206, a capacitor 207, a second comparator 208 and a flip-flop 209.
The feedback signal VFB is compared to a reference signal, e.g., 0.1 Volts by the comparator 201. When the feedback signal VFB is larger than 0.1 Volts, the comparator 201 generates a logical low signal. Otherwise, the comparator generates a logical high signal.
The output of the comparator 201 is coupled to the Tons detector 202. Based on the output of the comparator 201 and a signal pfm which controls the on and off of the transistor Q1, the Tons detector 202 generates a conduction time interval signal Tons indicative of the conduction of the secondary diode D1.
In FIG. 1B, the conduction time interval signal Tons and a non-conduction time interval signal Toffs, which is opposite from the signal Tons, have a ratio of 4/3, i.e., Tons has a relative interval time of 4 whereas Toffs has a relative interval time of 3.
The capacitor 207 is charged by the first current source 203 when the first switch 205 is turned on and is discharged by the second current source 204 when the second switch 206 is turned on. The first switch 205 and the second switch 206 is controlled by the signal Tons. An inverter 210 allows the second switch 206 to be off (i.e., open) when the first switch 205 is turned on (i.e., closed), and to be on when the first switch 205 is turned off. The ratio of the first current source 203 and the second current source 204 is fixed to 4/3.
When the controller AP3708 works under constant current mode, Tons/Toffs=4/3, wherein Toffs=T−Tons, and T represents a switching cycle time period of the transistor Q1. Ideally, when the controller AP3708 works under constant current mode, the output current is:
                    Io        =                              1            2                    ×          n          ×          Ipk          ×                      Tons            T                                              (        1        )
Wherein Ipk represents the peak current of the primary winding Np, and n represents the turn ratio of the primary winding Np and the secondary winding Ns. So n×Ipk represents the peak current of the current flowing through the secondary winding Ns.
In a given system, n and Ipk are fixed. The output current Io could be constant by fixing the ratio of the cycle time T and the conduction time interval signal Tons. So detecting and controlling the conduction time interval signal Tons is the key to the constant current control. The common way to generate the signal Tons is to detect the zero cross of the voltage VAUX across the auxiliary winding NAUX. The controller AP3708 gets the conduction time interval signal Tons by comparing the feedback signal VFB to a reference signal 0.1V.
In real world application, when the secondary diode D1 is turned off, the voltage VAUX across the auxiliary winding NAUX will cross zero after a demagnetizing oscillation, which means that when the voltage Vs across the secondary winding Ns reduces to zero, the feedback signal VFB is still larger than zero because of the demagnetizing oscillation of the auxiliary winding NAUX. FIG. 2 shows typical waveforms of the feedback signal VFB and the current Is flowing through the secondary winding when the transistor Q1 is turned on and off. At time t0, the transistor Q1 is turned off, and the energy of the magnetic field in the primary winding Np is transferred to the respective secondary and auxiliary windings Ns and NAUX. The secondary diode D1 and the auxiliary diode D2 are conducted. Accordingly, a peak current Ipk flows through the secondary diode D1, and the feedback signal VFB shows some ringing or oscillations before settling down to an average value while the current Is is flowing. At time t1, the energy of the magnetic field stored in the primary winding Np is completely discharged, there are no currents flowing in the primary, secondary and auxiliary windings. As the current Is flowing through the secondary winding Ns drops to zero, the feedback signal VFB shows a series of undershoots and overshoots with damping magnitudes around the ground potential. The undershoots and overshoots have a damped sinusoid ringing waveform with an approximately constant frequency, and the DC level of the ringing waveform is zero. At time t4, the transistor Q1 is turned on, VFB is going negative, i.e., the secondary diode D1 and the diode coupled to the auxiliary winding NAUX are reverse-biased. The current Ip starts to flow through the primary winding Np, which stores the energy of the magnetic field and releases it again to the secondary Ns and the auxiliary windings NAUX at time t0′ when transistor Q1 is turned off. The frequency f of the sinusoidal ringing waveform is determined by the inductance Lp of the primary winding Np, its parasitic capacitance, and the other capacitances related to the PCB layout of the power supply. The frequency f of the sinusoidal ringing waveform is calculated by the following expression:
                    f        =                  1                      2                        π                                                      Lp                ×                Ctot                                                                        (        2        )
Wherein Ctot represents the total capacitance. So a period T of the sinusoidal ringing waveform is:T=2π√{square root over (Lp×Ctot)}  (3)
As shown in FIG. 2, while the current Is drops to zero at time t1, the feedback signal VFB is not yet zero due to the ringing waveform. In some examples, the feedback signal VFB goes to zero after approximately a quarter of one cycle period of the sinusoidal. When a PWM (pulse width modulation) or PFM (pulse frequency modulation) controller utilizes the zero crossing of the feedback signal VFB as an indicator for the conduction time of the diode D1, as shown in FIG. 2, an error ΔT is likely to be included, which corresponds to about a quarter of one cycle period of the sinusoidal waveform.
FIG. 3 schematically shows the section of the constant current control circuit of the controller AP3708. The value of the first current source 203 is marked as 4I and the value of the second current source 204 is marked as 3I for illustration purpose. Ideally, when the controller AP3708 works under constant current mode, Tons/Toffs=4/3. If the error ΔT is considered, we could get the expression:3I×(Tons+ΔT)=4I×(Toffs−ΔT)   (4)
Substitution of Eq. (4) into Eq. (1) and the solution for the signal Tons yields:
                    Io        =                                            2              7                        ×            n            ×            Ipk            ×                          Tons                              Tons                +                                  Δ                                                                                T                                                              =                                    2              ×              n              ×              Lp              ×                              Ipk                2                                                    7                                            (                                                      Lp                    ×                    Ipk                                    +                                      n                    ×                    Δ                                                                                T                    ×                    Vo                                                  )                                                                        (        5        )
Wherein Vo represents the output voltage of the secondary winding. As seen from FIG. 2, the real zero cross of the voltage VFB is happened at t2 because of the demagnetizing oscillation. In Eq. (5), nΔTVo is an error in the output current lo caused by the error ΔT in the time interval of the signal Tons. The output voltage Vo is varied with the load in constant current control mode, thus the output current lo could not be constant because of the varying error nΔTVo.
To solve the above problem, there are several methods. For example, technology in the patent application US 2010/0238689 suggests compensating the time error to the conduction time interval signal Tons. It may solve the problem, but complicated circuits and a substantially similar capacitor set are needed to be configured. Also, a pair of substantially similar capacitor needed in the patent application US 2010/0238689 is hard to realize in real world.
The present disclosure provides a precisely controlled constant current controller which is realized with simple circuit.

Compensation circuit for constant current regulation of power supply and method thereof

Chengdu Monolithic Power Systems Co., Ltd.


A method for managing access to data in a database system includes receiving requests to update data stored in one or more fields of a record in a database table. The method further identifies lock information of the one or more fields from a look-up table associated with the record. The look-up table associated with the record includes lock information of each field of the record. The method then handles the requests based on the identified lock information of the one or more fields.

In a multi-user environment, Relational Data Base Management System (RDBMS) efficiently manages and executes concurrent user queries. The user queries are performed in separate threads of execution and are framed to access data entities associated with the RDBMS, hereinafter referred as database system. In the database system, a single data-entity, for example a database, a table, a row, a cell, and the like, is shared and accessed by multiple threads, which brings the issues of concurrency and data consistency. In an example, the row is a record of the database table.
Presently, for concurrency and data consistency, a mechanism of locking is used in the database system that enforces mutually exclusive access to shared data entities. As a result, only one thread can access a shared data entity at a time. However, this mechanism degrades the database system performance depending upon lock's granularity. For example, a row-lock is more granular than a table-lock. Thus, when a column (or a field) in a row (or a record) is being accessed, then all the other columns corresponding to that row are locked and no update operations can be performed on the other columns.
The database system maintains a global list of locks where each lock entry contains information about a thread that has acquired the lock and information about the shared object being locked. Therefore, if a thread wants to access a shared data object, it will first request a lock from the database system. The database system will then scan through the global lock-list, and check whether the same shared object has been locked by any other thread or not. If the object is not locked, then the database system adds a new entry into lock-list referring to the new thread's exclusive access to the data object. Thus, the thread is allowed to access and modify the contents of the shared object.
After accessing the data object, the thread can request the database system to release the lock that, in turn, deletes the earlier-added entry. The shared data object is then unlocked and is free for access by other threads. Thus, the task of maintaining lock consumes considerable amount of memory and CPU resources. Further, it becomes memory and CPU intensive when large number of data objects is being locked.
Currently, the row level lock is the most granular lock offered by the current implementations of locking mechanism. Therefore, to increase the performance, the row-level locking enables a table scan that allows only read operations on the locked columns of the row, provided that the read operation does not involve the columns being modified by a writer thread. Thus, in a database table, when a transaction intends to perform an update query on a column of the row, the locking mechanism locks the complete row while the update operation is being performed on the column. Hence, other transactions can only perform read operations on the unlocked columns of the row, and cannot update the column. This degrades the performance of the database system.

Managing concurrent access to data in database system

International Business Machines Corporation


A method of deinterlacing interlaced fields of video for display in a progressive display device includes providing at least one candidate motion vector per scan line and determining, at least one final motion vector per scan line of interlaced video, for use in deinterlacing the interlaced fields, by iteratively changing the at least one candidate motion vector per scan line based on pixel intensities from each of a plurality of same polarity fields at locations along a single dimension.

For computer monitors that are mostly non-interlaced or progressive type display devices, video images or graphic images must be displayed by sequentially displaying each successive line of pixel data sequentially for a frame of an image. In contrast, inter-laced display devices, such as conventional television displays, typically display images using even and odd line interlacing.
The process of producing one progressive frame on every incoming interlaced field is called de-interlacing. When such interlaced signals are received for display in a progressive display, such as a computer display or other suitable display, picture quality problems can arise especially when motion is occurring in the picture where inferior methods of de-interlacing are used.
Two interpolation techniques are often involved in de-interlacing, these are temporal interpolation and spatial interpolation. Temporal interpolation creates the missing pixels using pixels that were incorrect in time but have the correct spatial coordinates. Temporal interpolation (e.g. weave) is typically best suited if the video sequence consist of static images but does not work well with moving video. Spatial interpolation (e.g. bob) creates missing pixels using pixels that are correct in time but have incorrect spatial coordinates. Techniques vary from simply averaging the pixels above and below the missing pixel to more elaborate methods that utilize many nearby pixels in order to derive edge orientation and reproduce edges without jagged artifacts. It is also known to control a blend of spatial versus temporal interpolation along, for example, edges of detected motion.
In the deinterlacing process, interlaced video with moving ticker symbols, such as those that are scrolled across the bottom or top of a display screen to indicate stock market ticker symbols and stock prices, can suffer from resolution degradation due to the blending from neighboring pixels to fill the missing pixels in the current field. Furthermore, the degradation is highly noticeable because viewers are interested at tracking the text in motion. One type of deinterlacing technique, sometimes referred to as motion adaptive deinterlacing, does not use motion vector detection, it uses multiple fields and attempts to determine the presence of movement, but not the direction or speed of movement for example. In addition, another technique sometimes referred to as motion correct deinterlacing attempts to detect the direction of motion and the speed of the motion, however it is typically done on a block by block basis. Such motion estimation techniques can require large amount of computation. Other techniques may employ, for example, the use of a two dimensional search window to get a coarse level of motion detection such as, for example, starting with a 16×16 pixel block and if motion is detected within the block then an iterative approach searches for motion in 4×4 pixel sub-blocks. Again, this technique can be expensive to implement and can take large amount of time due to the iterative nature of the process. Also one or more of the above techniques may attempt to analyze motion in an entire field or frame whereas horizontal moving ticker symbols may only be located in the upper or lower one third of a viewing area.
Accordingly, a need exists for a method and apparatus that overcomes one or more of the above problems.

Method and apparatus for deinterlacing interleaved video


The present disclosure provides a tip-enhanced Raman spectroscope system. The system includes a laser emitting unit, a laser excitation unit, a first dichroic beam splitter, a first Raman spectrometer, and a confocal detecting unit. The laser excitation unit includes a sample stage and a first scanning probe. The sample stage is configured to have a sample disposed thereon such that a first incident laser beam emitted from the laser emitting unit is transmitted to the sample to excite first scattered light. The first dichroic beam splitter is configured to split a first Raman scattered light from the first Rayleigh scattered light. The first Raman spectrometer is disposed on a first Raman optical path of the first Raman scattered light. The confocal detecting unit is disposed on a first Rayleigh optical path of the first Rayleigh scattered light to image the sample.

Traditional optical microscopy is difficult to apply in analysis and characterize in nanoscale, atomic-scale or molecular-scale under the quantum effect of the specimen. Scanning probe microscopy is more effective in these precision measurements, adopting a scanning probe with a micro-tip to interact with the surface of the sample to obtain structural parameters and properties. The scanning probes can be used in atomic force microscopy (AFM), scanning tunneling microscopy (STM), near-field scanning optical microscopy (NSOM), tip-enhanced Raman spectroscopy (TERS), and so on, which are different types of the scanning probe microscopy or cooperation between the scanning probe microscopy and other measurement techniques. These microscope systems form a nanoscale interaction between light, micro-tip, and specimen, and achieve high-efficiency, high-stability, and high-resolution analysis and characterization of the specimen by extracting the interacting signals.
Raman spectroscopy has been widely used in the fields such as medicine development, drug identification, biology, and gem identification. A micro-area confocal Raman spectroscopy not only obtains Raman spectrum, but also has a three-dimensional imaging ability for the sample. As the Raman scattering signal of the sample can be excited and detected even if the laser is in a defocus position, the Raman spectrum obtained is often deviate from the imaging location, and is difficult to correctly characterize the sample at the imaging location.


A device for the concurrent oxygen generation and control of carbon dioxide for life support system involves two stages, where a first stage removes CO2 from an exhalent side of a ventilation loop and a second stage employs Ceramic Oxygen Generators (COGs) to convert CO2 into carbon and O2. The first stage includes a plurality of chambers and means to switch the ventilation loop through at least one of the chambers, where CO2 removal is carried out before discharge of the CO2 depleted gas to an inhalant side of the ventilation loop, and to exclude the ventilation loop from the remaining chambers of the first stage, where these chambers are placed in communication with the second stage. The second stage has two portions separated by the COGs such that CO2 and the formed carbon remain on an intake portion from the O2 rich atmosphere on the exhaust side, which is plumbed via a metering valve to introduce the O2 rich atmosphere to the inhalant side of the ventilation loop.

Weight is one of the most crucial factors in determining the viability of manned space travel, such as a mission to mars. Ostensibly, much of the technology needed for manned space travel is already in place but its weight is prohibitive. Particularly, life support related technologies are currently too heavy for an astronaut to carry for a reasonable duration without exhaustion. The deficit caused by weight for a life support system is also a deficit for other endeavors where a relatively long use of the system, including the use in a mining or other environment during emergency or other situations where the atmosphere is not conducive to breathing.
There are two crucial parts of such a life support system, those being carbon dioxide (CO2) removal and oxygen (O2) supply. Current CO2 removal technologies are not suitable for use on a long space mission, such as a mars mission, because of their weight and may not be appropriate for interaction with the Martian environment. State of the art advanced CO2 removal systems employ lithium hydroxide canisters for CO2 removal. Such a system requires approximately sixty pounds of consumable lithium hydroxide for a proposed five day Mars surface mission. To decrease such weight penalties on a mission to mars, it is imperative to employ an alternative system. Cycling bed and permeable membranes systems are also unsuitable because the high CO2 concentration in the Martian atmosphere, along with other environmental variables, precludes simply venting the CO2 after its removal from a spacesuit. Additionally a source of O2 is also a requirement for the life support system, and again the weight of an O2 source, such as an oxygen tank, must be considered. Vital O2 is bound up in the CO2 molecule, yet, none of the CO2 removal technologies mentioned above capitalize on the use of the CO2 as an O2 source.
Hence, new methods must be developed or older/existing alternatives must be perfected to remove CO2 from the space suit, without the need for venting, and to recover the oxygen from the CO2 molecule. Indeed, if a system is able to capture and recycle all the oxygen from the exhaled CO2, it may be possible to considerably reduce the need for additional O2 sources (such as oxygen tanks) and hence gain significant weight savings.

University of Florida Research Foundation, Inc.


A device to repel and disperse waterfowl entering a proscribed area consists of a laser beam generator generating a laser beam, and a photoelectric switch is provided so that the inventive device is only activated from dusk to dawn. A motion sensor senses the presence of waterfowl and activates the light beam source that is aimed into the area. In the preferred embodiment, a timer is provided that may be set for a desired duration. When the desired duration has elapsed, the controller deactivates the light beam source. The light beam source may consist of a single laser beam or a multiplicity of laser beams shining into the protected area. In one preferred embodiment of the present invention, a single laser beam is split into a plurality or multiplicity of beams using a suitable beam splitter. The inventive device may be equipped with a system that enables one or more laser beams to sweep and oscillate through the protected area so that not only is full coverage of the area assured, but the elevation of the beams is at least, at some points in time, at the level of the eyes of the waterfowl so that the waterfowl can detect the presence of the laser beams and quickly flee the area.

The present invention relates to a laser waterfowl repellent. Waterfowl such as geese and ducks are beautiful to observe from a distance. However, they are often a nuisance when they "graze" on one's yard, particularly, when they leave large deposits of feces behind. Geese, in particular, are stubborn animals. If they are chased away, more often than not, they will return over and over again. Studies have shown that migratory waterfowl are responsible for international spread of Avian flu. As such, it has become important to avoid contact with these wild animals.
Even in this day and age, solutions to the problems of nuisance waterfowl are few and far between. Chemical repellents are often used in grassy areas to make the grass unpalatable for eating waterfowl. Such chemicals are useless when trying to keep waterfowl off a dock, pier or other non-grassy area.
Noisemakers are often used, particularly at airports, to control when large waterfowl and other birds take off to best avoid having them sucked into gas turbine engines with the resultant engine failure. However, employing a device in a residential neighborhood that emits large blasts of sound is not the most neighborly thing to do. Other possible solutions to rid areas of nuisance waterfowl include placement of fake owls, installation of inflatable balloons having large eyes printed thereon, and barriers that preclude the waterfowl from entering areas where such restriction is desired. Animals such as border collies are also employed, but it is expensive to obtain and care for them.
In the case of barriers, they also make those areas inhospitable for people who must traverse the barriers to enter the area. It is also known that devices such as fake owls, inflatable balloons and fake inflatable snakes only deter waterfowl for short periods of time unless they are continually moved to different locations and orientations.
It is generally known to use laser energy to disperse waterfowl. A website at www.birdcontrolsupplies.com sells a "Bird Phazer PRO Laser" which basically consists of a hand-held laser beam generating device, battery powered, that may be used in the user's hand to shine a laser beam on the offending waterfowl to disperse them. Such a device, while generally effective, requires the presence of the user manipulating it.
In the particular situation of a floating dock, typically, the waterfowl enter onto the dock sometime after dusk and leave sometime before dawn. During these hours, it is often inconvenient for a property owner to use a hand-held device to disperse the waterfowl. Thus, a need has developed for a device that may effectively repel waterfowl and that does not require the presence of the property owner to do so.
It is with these issues in mind that the present invention was developed.
The concept of the laser beam generating device is extremely well known as of this date. Laser beam generating devices commonly generate laser beams of either red or green color. Red colored laser beams are at the edge of the visible light spectrum for humans and most animals. As such, when a red colored laser beam is generated, typically, all that may be seen is a dot where the beam impinges on a solid surface. By contrast, green colored laser beams are more toward the middle of the visible spectrum. What this means is that when a green colored laser beam is activated, not only is a dot visible on a solid surface where the beam impinges, at night, the beam emanating from the generator is also somewhat visible. The visibility of the entire beam from the source to where it impinges on a solid surface has been found to be an advantageous feature when attempting to disperse and repel waterfowl.
Laser beams may be split into a plurality of separate beams by any known means such as fiberoptic beam splitters, prisms, mirrors or some combination of these devices. The following U.S. patents teach various kinds of optical light beam splitters:
U.S. Pat. No. 6,084,717 to Wood et al.
U.S. Pat. No. 6,381,073 to Wilson
U.S. Pat. No. 6,609,815 to Waibel et al.


A device for the application of foaming reaction mixtures to a substrate which makes it possible to apply that foaming reaction mixture uniformly, a process for the production of foaming reaction mixtures using this device, apparatus for producing composites which include the device of the present invention and composites produced using such apparatus are disclosed. Use of the device of the present invention to produce foams makes it possible to produce foams having improved surface quality at higher production rates than were previously possible. The device of the present invention is particularly useful for the production of sandwich composite elements.

There has long been a need for devices for the continuous production of sandwich composite elements at high production rates. Oscillating mixing heads have hitherto been known from the prior art for the continuous production of sandwich composite elements. The mixing head performs an oscillating movement over the width of a lower outer layer and applies the still liquid reaction mixture to the lower outer layer by means of a casting rake or fan/spoon nozzle which is arranged at a right angle relative to the mixing head and parallel to the lower outer layer.
The mixing head is fixed to a guide rail, the so-called portal, above the lower outer layer and is accelerated with the aid of electric motors and slowed down before the reversal points. The raw materials for foaming are fed to the mixing head via flexible hose lines. Furthermore, in some cases hydraulic or pneumatic hoses lead to the mixing head. The raw materials for foaming are introduced into the mixing head via nozzles and are mixed.
The reaction mixture then flows into the casting rake and emerges through regularly spaced bores. As a result of the length of the casting rake and its bores, as well as the oscillating movement of the mixing head, distribution of the reaction mixture obliquely to the production direction is achieved.
After application, the reaction mixture foams and rises to the upper outer layer. During the foaming process it bonds the two outer layers before the foam solidifies and cures.
This production process is limited in terms of manufacturing technology as regards the production rate. Even if sufficiently strong motors, guide rails, hoses, mixing heads and casting rakes or fan/spoon nozzles were used, the reaction mixture would be carried beyond the edges of the outer layers at the reversal points owing to excessively high centrifugal forces. According to the prior art, production rates of more than 15 m/minute cannot be achieved in the continuous production of sandwich composite elements with this application technique.
The technique of increasing the production rate to up to 60 m/minute by means of stationary mixing head technology and rigid delivery systems is sufficiently well known. This process is called US technology. US technology (high-speed machines) consists substantially of three identical metering lines with separate feed and separate mixing heads and delivery systems. However, this technology does not have a distributor head. This process further has the disadvantage that the reaction mixture emerging from each of the individual mixing heads can also be subject to different physical conditions as regards pressure and temperature, and this manifests itself in the resulting foam as reductions in product quality, such as, for example, uneven surface, smaller cells, different thermal conductivity values due to punctually different reaction kinetics.
EP 1 857 248 A2 solves that problem by not providing every discharge line with a separate mixing head. Rather, only a central mixing head is provided, via which a plurality of delivery lines are fed.
WO 2008/018787 A1 relates to a device for applying a viscous mixture to a surface by means of one or more outlet openings which are fed by a feed element. The specification relates further to a process for the production of an insulating element, comprising the steps of applying a viscous mixture which forms a foam on a substrate layer, the foam subsequently being crosslinked and the foam layer optionally being further coated. A mixing head 3 is supplied with raw material with components from supply pipes 1 and 2. Via a rigid main pipe 8, a casting rake 6 is controlled by a plurality of intermediate webs 5 via a sub-distributor 4. The casting rake is accordingly rigidly connected to the mixing head and can only be moved to the left or right together with the mixing head in order to allow the application region to be adjusted as a whole to the correct position relative to the substrate. Moreover, cleaning of the system is very complex.
WO 2008/104492 A2 discloses a process for the production of composite elements, wherein the application of the liquid starting material for the isocyanate-based rigid foam is carried out by means of a stationary pipe which is arranged parallel and at a right angle to the direction of movement relative to the outer layer and is provided with bores.


A semiconductor pressure sensor comprising two pressure sensing diaphragms attached to a support frame embedded within a bonding agent joining two parts of a housing which defines therein fluid passages in communication with two pressure sensing diaphragms. The support frame includes a support plate portion and terminal portions having the inner ends embedded within the bonding agent and the outer ends projecting outwardly of the bonding agent for external connections. The support frame is formed by cutting a lead frame, which has a support frame portion, terminal portions and a surrounding frame integrally connected together, substantially along the outer contour of the housing except for the terminals. A method for manufacturing the pressure sensor is also disclosed.

This invention relates to a semiconductor pressure sensor and more particularly to a semiconductor pressure sensor useful in detecting pressure difference of two pressure sources.
One example of the conventional semiconductor pressure sensor is disclosed in Japanese Pat. Laid-Open No. 60-100026 for example, in which two sets of semiconductor pressure sensing units each including a diaphragm portion and four piezo-electric resistor elements connected in a bridge circuit are formed on a single common semiconductor substrate, and in which the fluid of which pressure is to be measured is applied to one of the pressure sensing units and two outputs from the respective bridge circuits are compared to make a subtraction, whereby any error due to residual distortions can be eliminated.
Another example of a semiconductor pressure sensor is disclosed in Japanese U. M. Laid-Open Pat. No. 61-87338. In this conventional pressure sensor, an opening is provided at the central portion cf a base and a pressure introducing conduit extends downwardly from the opening, and other openings for atmosphere are disposed remotely from the central opening. A pressure sensing diaphragm for detecting the pressure difference between the pressure introducing conduit and the atmospheric pressure is centrally disposed, and the opening for the atmospheric pressure is covered by the semiconductor chip which is covered by a cap.
In U.S. Pat. No. 4,895,026 to Tada, a disclosure is made as to a semiconductor pressure sensor comprising a first and a second identical pressure sensing diaphragm each having first and second pressure receiving surfaces and supported to align in a common plane in the same orientation. Two pressure sensing diaphragms have connected thereto similar bridge circuits made of piezoelectric elements for generating electrical signals indicative of the fluid pressure acting on the pressure sensing diaphragms. The semiconductor diaphragms are directly supported on an electrically insulating support frame held in a sensor housing. A first fluid passage connectable to a first pressure source is on communication with the first pressure receiving surface of the first diaphragm and the second pressure receiving surface of the second diaphragm, and a second fluid passage is in communication with a second pressure receiving surface of the first diaphragm and the first pressure receiving surface of the second diaphragm. The two electrical signals are supplied to a differential amplifier where two signals are subtracted and an output electrical signal proportional to the magnitude of the result of the subtracted between the first and the second electrical signals. During assembly, electrical terminals are molded in the housing, and the signal generating elements are mounted to one of the housing halves by the support plate, and then, the inner ends of the terminals and the signal generating elements are electrically connected by wires. These electrical components are covered by the second housing half.
Since the conventional semiconductor pressure sensors are constructed as above described, the support plate and the terminals are separate and discrete components, leading to the need for the separate manufacture and a poor productivity.


A control device for controlling a front wheel drive force and a rear wheel drive force of a vehicle that includes a transmission comprises: a first controller for controlling a drive force of a main drive wheel and a drive force of an auxiliary drive wheel, the drive force of the main drive wheel being one of the front-wheel drive force and the rear-wheel drive force, and the drive force of the auxiliary drive wheel being another of the front-wheel drive force and the rear-wheel drive force; and a second controller for detecting whether a speed-change ratio of the transmission has changed. In a case that the second controller has detected that the speed-change ratio has changed, the first controller increases the drive force of the auxiliary drive wheel and reduces the drive force of the main drive wheel.

Vehicles, e.g., automobiles, generally have four wheels; i.e., two front wheels and two rear wheels, and can have an electronic control device for driving the wheels.
Japanese Laid-open Patent Application (JP-A) No. 2006-256605 discloses a four-wheel-drive electronic control unit (4WD-ECU) as such an electronic control device. The 4WD-ECU disclosed in Japanese Laid-open Patent Application No. 2006-256605 together with a vehicle stability assist (VSA)-ECU controls the drive force that operates on the vehicle; and, specifically, sets the four-wheel-drive force in terms of units of, e.g., torque.
Japanese Laid-open Patent Application (JP-A) No. 07-186758 discloses a drive force distribution control device 4 (controller 58) for controlling drive force distribution produced by a drive force transmission system 3 as an electronic control device.
The drive force distribution control device 4 (entire flowchart shown in FIG. 6) disclosed in JP 07-186578 A includes drive force distribution correction means (steps S2, S3, S6, S13, S16 of FIG. 6). The drive force distribution correction means is capable of correcting control signals for adjusting the drive force distribution between main and auxiliary drive wheels for the front and rear wheels in accordance with the detection values of the change-in-rotational-state detection means (deviation of the rotational state detection value of each front and rear wheel corresponding to a main drive wheel and a auxiliary drive wheel). Specifically, when a rapid increasing change has been detected after rapid decrease in the absolute value of the deviation in the detection values of the rotational state of the front and rear wheels, the drive force distribution correction means corrects the change amount of the control signal for adjusting the drive force distribution between main and auxiliary drive wheels for the front and rear wheels in order to reduce the drive force distributed to the main drive wheels. At this time, the state of distribution of the drive force between the front and rear wheels is made the same as the state immediately before the reduction in the absolute value of the deviation in the detection values of the rotational state of the front and rear wheels, and alternatively the ratio of drive force distribution to the auxiliary drive wheels is made to be slightly less than the state immediately before the above-noted reduction, so that the amount of reduction in the drive force to the auxiliary wheels is essentially reduced.
Thus, the inventors recognized that the drive force to the main drive wheels may remain at a high level even if the amount of reduction in the drive force to the auxiliary drive wheels is made less. In other words, the inventors recognized that the main drive wheels may slip in the particular case that the drive force to the main drive wheels was originally high, even if the amount of reduction in the drive force to the auxiliary drive wheels is made less. It is this phenomenon that has not been formally known to those skilled in the art.

Control device for controlling drive force that operates on vehicle


The present disclosure describes method, apparatus, and storage medium for identifying an identification code. The method includes obtaining, by a computer device, a to-be-detected picture. The computer device includes a memory storing instructions and a processor in communication with the memory. The method also includes detecting, by the computer device, an identification code in the to-be-detected picture to obtain a detection result, the detection result comprising target information of a target code corresponding to the identification code; sampling, by the computer device, the target code according to the target information, to obtain a sampled image; and decoding, by the computer device, the sampled image, to obtain an identification result corresponding to the identification code.

With the development of computer information technologies, an identification code technology has emerged, and the emergence of the identification code technology makes people's lifestyles become more convenient and efficient. For example, the convenient and efficient lifestyles such as riding through an identification code, payment through an identification code, and running an applet through an identification code cannot be implemented without the support of the identification code technology.
The identification code identification manner in the related art is performing operations such as sampling and decoding on an entire to-be-detected picture. This identification manner usually has the following problems: As shown in FIG. 1, the entire to-be-detected picture may be quite large, but the identification code occupies only a quite small part of the entire picture; or as shown in FIG. 2, the entire to-be-detected picture may have much interference information. For the foregoing two cases, the entire identification process may consume a lot of time in identification of a non-identification code region. Therefore, the identification efficiency is low.

Method, apparatus, and storage medium for identifying identification code

TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED


Provided by the present disclosure are data transmission method and device. In an embodiment of the present disclosure, data transmission conditions of each serving cell among at least two serving cells is detected by means of a terminal so that the terminal may, according to the data transmission conditions of each serving cell, execute random access on a serving cell experiencing wave beam failure so as to update a service beam of the serving cell. Thus, when the terminal experiences wave beam failure in a serving cell in a carrier aggregation (CA) scenario, reliable data transmission may be achieved, and the reliability of data transmission may be effectively ensured.

The present disclosure relates to data transmission technology, and in particular, to a data transmission method and device.
In a wireless communication system with carrier aggregation (CA) characteristics, a terminal can communicate with network equipment through multiple serving cells. Among the multiple serving cells, one serving cell is a primary cell (PCell), and the other serving cells are secondary cells (SCells). The terminal may send uplink signals to network equipment through different serving cells.
In the actual application process, the terminal may have a beam failure situation of the serving cell, that is, the primary cell or the secondary cell.

GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.


An encapsulation method enabling high throughput production of semiconductor die packages. In an exemplary embodiment, a mold is provided with an upper mold platen having a plurality of cavities for encapsulating interconnections on a first side of a multi-chip carrier substrate. The mold further includes a lower mold platen having a cavity for encapsulating substantially the entire second side of the carrier substrate, including a plurality IC chips mounted thereon. Substrate support elements, in the form of standoff pins, are provided for supporting the carrier substrate during the encapsulation process to prevent substrate deflection. The standoff pins may be integral to a mold cavity or may be removable. The standoff pins may further be aligned along lines representing individual device package edges. Cutting along marks left in the encapsulant by the support elements provides individual device packages.

1. Field of the Invention
This invention relates generally to the molding and encapsulation of semiconductor devices. More particularly, the invention pertains to a method and mold apparatus for encapsulating a multi-chip substrate array.
2. State of the Art
Integrated circuit semiconductor dice, sometimes referred to as chips, are manufactured from a semiconductor material such as silicon, germanium or gallium arsenide, and contain microscopic circuits which are formed on each chip by photolithographic techniques xe2x80x9cactive surfacexe2x80x9d of a semiconductor die is further formed with a plurality of external connections, typically referred to as bond pads, which are designed for soldering wire bonds and thus enable the semiconductor die to be electrically interconnected to an external electrical device, substrate or apparatus.
Present methods used in the fabrication of semiconductor die packages involve the process steps of die bonding, wire bonding, molding, deflashing, and singulation. In the die bonding process, semiconductor dice are bonded or soldered to a lead frame strip, printed wiring board, or other conductive substrate by various well-known techniques usually involving a conductive adhesive. During wire bonding, conductive wires usually formed of gold or aluminum are attached, one at a time, from bond pads on the active surface of a semiconductor die to corresponding electrode pads on the conductive substrate. Following die attach and wire bonding, a mold assembly for transfer molding is typically used for component encapsulation of individual semiconductor dice mounted on the conductive substrate, including encapsulation of the wire bond interconnections formed between the semiconductor dice and conductive substrate. In the deflashing process, resin bleed formed by mold compound that may have escaped from minute gaps between the mold assembly and the conductive substrate is removed from leads or bond pads on the conductive substrate. In the singulation process, an encapsulated semiconductor die mounted on a conductive substrate containing multiple semiconductor dice is typically isolated from other encapsulated semiconductor dice by cutting or segmenting the conductive substrate such that the electronic components comprising an individual semiconductor device package are separated from other individual semiconductor device packages.
It is well known in the art that a critical step in the semiconductor device fabrication process is the encapsulation of semiconductor dice and their interconnections. The encapsulation or xe2x80x9csealingxe2x80x9d of a semiconductor die and its wire bond interconnections within a xe2x80x9cpackagexe2x80x9d of plastic or other moldable material serves to protect their materials and components from physical and environmental stresses such as dust, heat, moisture, static electricity, and mechanical shocks.
In a typical encapsulation process for surface-mounted semiconductor dice, a conductive substrate strip, with mounted and wire bonded semiconductor dice placed along the length of the strip, is placed in the lower mold plate of a xe2x80x9csplit cavityxe2x80x9d mold comprising an upper and lower member. The upper and lower members of the mold are frequently referred to as xe2x80x9cplatensxe2x80x9d or xe2x80x9chalves.xe2x80x9d With the upper mold platen raised, the conductive substrate strip is positioned on the lower mold platen such that the component portions to be encapsulated are in registration with multiple mold cavities formed in the lower mold platen. The mold is closed when the upper platen is lowered onto the lower platen. When the mold is closed, a peripheral portion of the conductive substrate strip is typically compressed between the upper and lower platens to seal the mold cavities in order to prevent leakage of liquified plastic molding compound. The force required to compress the platens together is generally of the order of tons, even for molding machines having only a few mold cavities.
Depending upon the type of semiconductor die and substrate to be encapsulated, the upper platen may also contain mold cavities in registration with component portions of the conductive substrate strip to be encapsulated. In other devices, such as those having a heat sink attached to a semiconductor die, or in certain semiconductor dice having a ball grid array (BGA) or similar array on a circuit board, the molding process is conducted so that the outer surface of the heat sink or circuit board forms an exterior surface of the package which rests against a mold cavity or platen surface. With these semiconductor devices, the molding process may be conducted such that the exterior surface is free from coverage by the plastic encapsulant material.
Liquified encapsulant is fed to the cavities of the mold by xe2x80x9crunnersxe2x80x9d (i.e., channels) that extend the length of the conductive substrate strip. The runners, in turn, are fed from a xe2x80x9ctransfer potxe2x80x9d or reservoir which pressurizes, heats and holds the encapsulant molding compound until delivery. In some package applications, a single runner may be sufficient to supply encapsulant to feed more than one conductive substrate strip. For larger packages, however, the consumption of greater amounts of molding compound dictates that the larger package be supplied with its own dedicated runner. Usually, constricted channels known as xe2x80x9cgatesxe2x80x9d are located at the entrance to each mold cavity to limit the flow rate and injection velocity of liquified encapsulant into the cavity. Gates may be located in either the top half or bottom half of the mold, or both. If a gate is located in only one half of a mold with upper and lower cavities, a conductive substrate can be designed with an aperture extending through opposing surfaces of the conductive substrate so that the encapsulant has the ability to flow from one cavity side to the other.
Typically, preheated powdered or pelletized plastic, e.g., thermosetting resin, is placed in the transfer pot and compressed by a transfer cylinder, or ram. The heated, pressurized plastic becomes liquified and flows through the runners and gates where it eventually fills each mold cavity, thereby flowing over the semiconductor die, conductive substrate, and wire bonding areas to be encapsulated. The transfer pressures employed to push the liquified plastic through the runners, gates and into the mold cavities typically range from 200-1200 psi. This results in relatively high velocity flows out of the gates which diminish somewhat as the plastic moves into the cavity and assumes a plug-type flow configuration. Lower transfer pressures are undesirable because of the potential for polymerization or gelling of the plastic mold compound prior to completely filling the mold cavities. After the cavities are filled, the encapsulant is maintained at a specified pressure until cure.
The molding compound is then allowed a curing period, where it subsequently hardens to encapsulate the conductive substrate and the devices attached to it. Air is expelled from each cavity through one or more runners or vents as the plastic melt fills the mold cavities. Following hardening by partial cure of the thermoset plastic, the mold plates are separated along the parting line and the encapsulated semiconductor devices are removed and trimmed of excess plastic which has solidified in the runners and gates. Additional thermal treatment may complete the curing of the plastic package. The shape of the mold cavities and the configuration of the conductive substrate determine the final shape of the semiconductor package.
The molding process is then repeated with a new batch of mounted conductive substrate strips. The molding process described herein is known in the art to be subject to automation, as well as manual operation, at each phase of the molding process.
Exemplary patents describing various apparatus and methods for encapsulating surface-mount electronic packages are described by U.S. Pat. No. 6,036,908 to Nishida, U.S. Pat. No. 5,723,156 to Matumoto, U.S. Pat. No. 5,609,889 to Weber, U.S. Pat. No. 5,304,512 to Arai, U.S. Pat. No. 5,254,501 to Tung et al., U.S. Pat. No. 4,954,301 to Saeki et al., and U.S. Pat. No. 4,332,537 to Slepcevic.
At the high pressures used for delivery of encapsulant, mold cavities and their gates must be carefully designed to prevent the conductive wires from dislodging or moving into contact with one anotherxe2x80x94a condition known as wire sweep. Also factored into the design of the molding apparatus are provisions for flow characteristics sufficient to meet the essential requirement of a void-free encapsulation. A related concern in mold apparatus with upper and lower mold body cavities fed by a single gate is that when liquified plastic is transferred from the gate to the upper and lower cavities, the lower cavities tend to fill first, which can result in an upward buildup of pressure sufficient to temporarily deflect the carrier substrate during encapsulation. Upon removal from the mold plates, the residual forces from the deflection of the carrier substrate may cause cracking, spalling, etc., in the package. Controlling air bubbles is a further consideration: air bubbles potentially caused by multiple layers of wire bonding, air pockets adjacent to the semiconductor die, insufficient pressure packing, or the gasification of substrate materials due to the elevated temperatures of the transfer molding process and the like.
Several patents include disclosures which relate to solutions for conditions which cause a warping or deflection in a lead frame or other substrate during the filling of the mold cavities with liquified encapsulant. For example, U.S. Pat. No. 4,954,301 to Saeki et al. discloses a transfer cylinder whose downward displacement is controlled by a microcomputer in order to decrease void formation and deformation of the carrier insert. U.S. Pat. No. 5,723,156 to Matumoto discloses a gate arrangement designed to transfer encapsulant equally into the upper and lower cavities of the mold.
With regard to devices having an attached heat sink, U.S. Pat. No. 5,776,512 to Weber describes a mold which has a biased plug in a lower mold cavity that exerts pressure on a heat sink in contact with an upper mold half to prevent molding compound from covering the heat sink. Weber further utilizes an extending portion of the carrier substrate to contact the lower mold platen, thus stopping the carrier substrate from deflecting from the downward push of the biased plug.
U.S. Pat. No. 5,682,673 to Fehr discloses a mold for encapsulating integrated circuit chips mounted in conventional fashion to die attach pads of lead frames. The lower mold cavity of Fehr is provided with one or more installed support pins, soldered into holes in the mold, for furnishing support under the die attach pad during injection of molding compound into upper and lower mold cavities. The support pins are provided to counteract the forces resulting from the flow of encapsulant over the chip during the filling of the upper mold cavity, and thus prevent the die attach pad from undesirably contacting the lower mold cavity. In one embodiment, Fehr discloses a single support pin located directly under the center of the die attach pad. A second embodiment of Fehr shows several support pins positioned in a rectangular array under the die attach pad of a wide-area, thin package requiring increased support. The support pins of Fehr are disclosed to preferably have tapered ends of a generally conical shape to provide a small area for contact with the die attach pad.
In recent years, there has been an increased demand for high-density mounting of semiconductor packages which has coincided with advances in the performance and functionality of integrated circuits. These demands have led to numerous innovations in semiconductor die and carrier substrate design.
One form of interconnection recently developed to meet the needs of industry is known as xe2x80x9cboard-on-chipxe2x80x9d (BOC). In this arrangement, a semiconductor die (chip) is mounted, active side up, under a carrier substrate configured with one or more slots for accepting the conductive wires of the semiconductor die. The conductive wires of the semiconductor die extend through the slot in the carrier substrate where they are connected to wire bond pads of the carrier substrate""s surface.
In order to increase throughput in the mounting and encapsulation of board-on-chip devices, semiconductor dice can be mounted in various board-on-chip matrices or arrays, e.g., three devices across a width of a lead frame strip, printed wiring board or other conductive substrate, thus maximizing the number of packages to be formed per array strip. In these types of array arrangements, it may be considered advantageous, for reasons of simplicity in die tooling, molding, and economies of scale, to utilize a mold with a semiconductor die side cavity large enough to cover the entire semiconductor die side of the substrate array with encapsulant, rather than to use individual molded bodies for encapsulating each semiconductor die.
Since array-mounting does not easily allow encapsulant to be transferred from one cavity to another by flow around the substrate, both the upper and lower mold cavities may be fed encapsulant simultaneously. The relatively large semiconductor die side mold cavity area being unsupported to allow for the flow of encapsulant under the die, the problems previously discussed concerning temporary deflection of the carrier substrate during encapsulation become particularly acute in this type of board-on-chip substrate array. If no support is provided under this area, the residual forces in the substrate resulting from the deflection may, upon cure and removal of the encapsulated package from the mold plates, cause cracking, spalling, etc., in the package. Cracking and spalling are costly defects since the package""s protective abilities are compromised, and the package cannot be repaired or reworked even though an expensive semiconductor die may be inside.
Therefore, a need exists for an encapsulation method and apparatus that will allow high throughput production of reliable, high-quality semiconductor device packages from board-on-chip arrays or other conductive substrate array arrangements.
The present invention provides a mold and method suitable for the transfer molding encapsulation of a multi-chip substrate array, and the fabrication of an encapsulated semiconductor device package, while minimizing the attendant problems of voids, wire sweep and substrate deflection during encapsulant fill.
Split or injection molds can be used to achieve encapsulation of semiconductor device packages arranged on a carrier substrate with a plurality of integrated circuit semiconductor dice affixed thereto. The molds for such encapsulation are provided with cavities in each side of each respective mold half. Under the pressure of injection molding, the carrier substrate may deflect, causing voids, cracks, spalling, etc., in the package. Although deflection of the substrate depends on many factors, including, but not limited to, mold design, the primary deflection of the carrier substrate is towards the semiconductor die side of the mold, as hereinafter described.
The present invention provides an apparatus and method of encapsulating a multi-chip substrate array using transfer molding apparatus which prevents or minimizes substrate deflection into a mold cavity during encapsulant transfer. In one embodiment, a board-on-chip array is provided in which the carrier substrate is supported or otherwise fixtured during encapsulation. In this arrangement, a plurality of semiconductor dice is mounted, active side up in an array arrangement, under a carrier substrate surface. The carrier substrate is further configured with a plurality of wire bonding apertures for accepting the conductive wires of each semiconductor die. The conductive wires of each semiconductor die extend through the aperture in the carrier substrate where they are connected to wire bond pads on the carrier substrate surface. The wire bond pads on the carrier substrate surface may further be electrically connected to other conductors on the carrier substrate surface in the form of circuit traces, solder ball contact pads, and solder balls, etc. In a preferred embodiment, connective components of the conductors are arranged in a ball grid array of a preselected configuration around each aperture of the carrier substrate, the ball grid array allowing for electrical communication of the semiconductor die with external components. The carrier substrate may also be provided with alignment rails for automated transfer operations and easy mounting within the mold. The board-on-chip array is then placed in a mold assembly with a plurality of first mold cavities configured for encapsulating the electrical interconnections on the first side of the substrate, and a second mold cavity for encapsulating substantially the entire second side of the substrate, to include the plurality of array-mounted semiconductor dice.
In this aspect of the invention, substrate support elements, in the form of standoff pins or bosses, are provided for supporting the carrier substrate of the board-on-chip array during the encapsulation process. The standoff pins or bosses are configured to contact, or nearly contact, the die side area of the carrier substrate to prevent or minimize substrate deflection during the fill of the mold cavities with encapsulant material. Upon cure of the encapsulant, the carrier substrate is removed from the mold, and individual board-on-chip packages may be obtained upon segmenting the carrier substrate array.
Preferably, the standoff pins or bosses are used in a mold cavity to support the semiconductor die side of the carrier substrate. These support elements may be aligned, or non-aligned along lines representing one or more edge areas of individual board-on-chip packages. Individual chip packages may be obtained by sawing along imaginary lines extending through indentations found in the semiconductor die side of the encapsulated array, the indentations left by the aligned standoff pins or bosses during the process of substrate support. The standoff pins or bosses may be integral to the mold cavity, or may be removable. Integral standoff pins or bosses may be machined, cast, or otherwise fabricated into one or both sides of the mold. In one embodiment, the standoff pins or bosses may be resiliently mounted to a mold cavity surface to bias a substrate array against deflection during a molding process. The standoff pins or bosses preferably have elongated portions which extend outwardly from the mold cavity, and the elongated portions are preferably tapered in nature. As removable elements, the standoff pins or bosses may be incorporated into the encapsulant material of the package, once cured. The removable standoff pins or bosses may also be interlinked, and may be formed of the same, or a similar, material to that of the encapsulant.
The invention thus provides a mold and process which may be reliably used for mass production of encapsulated semiconductor packages, and which may be used in a manual or automated fashion. In one embodiment, the semiconductor packages formed by the methods of the present invention can be used to construct a semiconductor device assembly, such as a multi-chip module or a series of stacked BGA packages.
Other features and advantages of the present invention will become apparent to those of skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.

Method for encapsulating a multi-chip substrate array


A first semiconductor fin and a second semiconductor fin are disposed over a substrate. The second semiconductor fin and the first semiconductor fin are aligned substantially along a same line and spaced apart from each other. The first semiconductor fin has a first end portion, the second semiconductor fin has a second end portion, and an end sidewall of the first end portion and is spaced apart from an end sidewall of the second end portion. The gate structure extends substantially perpendicularly to the first semiconductor fin. When viewed from above, the gate structure overlaps with the first end portion of the first semiconductor fin. When viewed from above, the end sidewall of the first end portion of the first semiconductor fin facing the end sidewall of the second end portion of the second semiconductor fin has a re-entrant profile.

The semiconductor integrated circuit (IC) industry has experienced rapid growth. As the semiconductor industry continues on its path to improve its productivity and profitability, technological advances in semiconductor materials and IC designs have produced smaller and more complex circuits. These advanced materials and designs have been realized as the processing or manufacturing-related technologies and have also advanced. In the course of semiconductor evolution, functional density (defined as the number of interconnected devices per unit of area) has increased as the feature size has decreased. A scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. One of the developments is the replacement or supplementation of a conventional planar metal-oxide-semiconductor field-effect transistor by a vertical field-effect transistor. However, existing vertical field-effect transistors have not been satisfactory in all aspects, and similar developments of tools and methods for improving the performance of the semiconductor device are needed.

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.


A control memory error correcting apparatus includes a control memory, a microinstruction register, a control pattern generator, a control pattern storage register, and an operation inhibit signal generator. The control memory stores a microinstruction including a first field for controlling a first operation unit by a microinstruction pattern and a second field for generating a control pattern for controlling a second operation unit. The microinstruction register stores the microinstruction from the control memory. The control pattern generator generates the control pattern in accordance with the second field from the microinstruction register. The control pattern storage register stores the control pattern from the control pattern generator. The operation inhibit signal generator changes timings and destinations of the operation inhibit signals output to the first and second operation units and the control pattern storage register in accordance with the types of the error-detected fields when a correctable error is detected in any of the first and second fields stored in the microinstruction register.

The present invention relates to a microprogram control apparatus in an information processing apparatus and, more particularly, to a control memory error correcting apparatus having functions of detecting/correcting an operation of a correctable error and inhibiting an operation of an operation unit during an error detection.
A conventional example will be described below with reference to the accompanying drawings.
FIG. 4 shows an arrangement of the conventional microprogram control apparatus. Referring to FIG. 4, a microinstruction is stored in a control memory 21. This microinstruction is constituted by the following components: an address field A representing next address information; an arithmetic control field B for causing a pattern of the microinstruction to directly control an arithmetic circuit 25; a control pattern field C for generating a control pattern of an arithmetic circuit 26; and an error correcting code according to a Hamming code given to a series of bit patterns. The microinstruction read out from the control memory 21 is stored in a microinstruction register 22.
The control pattern field C of the microinstruction stored in the microinstruction register 22 is input to a control pattern generator 23. The control pattern generator 23 generates a control pattern in accordance with the microinstruction represented by the control pattern field C, and inputs/stores it in a control pattern storage register 24. The control pattern storage register 24 outputs the stored control pattern to the arithmetic circuit 26 to control it. Two typical methods of generating a control pattern will be shown below with reference to FIGS. 6 and 7. FIG. 6 shows a hardware decoding method for causing a decoder 72 to decode a second field of a microinstruction, thereby obtaining a control pattern. FIG. 7 shows a RAM decoding method of obtaining a control pattern from a control pattern memory 73 by using the second field of the microinstruction as an address. By using the above methods, the control pattern can be obtained. The arithmetic circuit 26 stores an arithmetic result in an arithmetic result register 30.
The arithmetic control field B of the microinstruction stored in the microinstruction register 22 is input to the arithmetic circuit 25. The arithmetic circuit 25 performs the operation in accordance with the microinstruction represented by the arithmetic control field B, and inputs/stores the arithmetic result in an arithmetic result storage register 29. Note that the arithmetic circuit 25 and the arithmetic result storage register 29 constitute an operation unit 33, and the arithmetic circuit 26 and the arithmetic result storage register 30 constitute an operation unit 34.
If error detectors 271 to 273 in an operation inhibit signal generator 27 detect errors in any of the address field A, the arithmetic control field B, and the control pattern field C of the microinstruction stored in the microinstruction register 22, the detectors 271 to 273 generate an operation inhibit signal D through an OR circuit 274 and inhibit the updating of the control pattern storage register 24 and the arithmetic result storage registers 29 and 30 in the operation units 33 and 34. Therefore, these registers are not adversely affected by the microinstruction including the errors. The error correction circuit 28 corrects the error of the microinstruction and stores it in the microinstruction register 22 during the generation of the operation inhibit signal.
A series of the above operations will be described below with reference to the timing chart shown in FIG. 5. When an error-including microinstruction Ei' is stored in the microinstruction register 22, the operation inhibit signal D is generated, updating of the control pattern storage register 24 and the arithmetic result storage registers 29 and 30 is inhibited, and the registers 24, 29 and 30 respectively keep holding data F1.sub.i-1, R1.sub.i-1 and R2.sub.i-2. An error-corrected microinstruction Ei is stored in the microinstruction register 22 in the next clock cycle. The operation inhibit signal D is canceled and a normal operation restarts. Therefore, operations of the control pattern storage register 24 and the arithmetic result storage registers 29 and 30 are not adversely affected by the microinstruction Ei' and can be properly performed.
In the control memory error correcting apparatus of this type, the correctable error is detected in all fields of the microinstruction and the updating of the control pattern storage register 24 and the arithmetic result storage registers 29 and 30 in the operation units 33 and 34 is inhibited in an error-detected clock cycle.
In the conventional control memory error correcting apparatus as described above, the correctable error is detected in all fields of the microinstruction and the operation of the operation units is inhibited in an error-detected clock cycle.
A microprogram control apparatus, generally, comprises a plurality of LSIs. Some LSIs are arranged near an arithmetic circuit, and some LSIs are arranged away from an arithmetic circuit. The microinstruction register is realized by the plurality of LSIs in a distributed manner. For this reason, when an error is detected in all the fields of the microinstruction and the operation inhibit signal D is generated, the delay time of the operation inhibit signal D during its propagation from the microinstruction register 22 of the remote LSI to the control pattern storage register 24 and the arithmetic result storage registers 29 and 30 is prolonged. Therefore, the clock cycle is also prolonged.

Control memory error correcting apparatus