In a steam-heating apparatus in which a heating section (2) formed in a heat exchanger (1) is connected to a steam supply pipe (3) for receiving supply of heating steam and connected also to a condensate recovering unit (6) for discharging condensate produced as a result of heating, the apparatus includes a steam ejector (5) including a suction chamber (13) connected to the heating section (2) and an inlet for receiving supply of the steam. When the temperature of the heating section (2) or between the heating section (2) and the condensate recovering unit (6) is dropped by a predetermined value, steam is supplied from the steam supply pipe (3) to the inlet of the steam ejector (5) and gas in the heating section (2) is sucked into the suction chamber (13) of the steam ejector (5).

The present invention relates to a steam-heating apparatus in which a heating section formed in a heat exchanger is connected with a steam supply pipe for receiving supply of heating steam and connected also with a condensate recovering unit for discharging condensate produced as a result of heating.
An example of such steam-heating apparatus is known from Japanese paten application laid-open No. Hei. 7-328423. In this steam-heating apparatus, as shown in FIG. 6, a reaction vessel 1 is provided as a heat exchanger. The reaction vessel includes, as a heating section thereof, a jacket section 2, to which a steam supply pipe 3 for receiving supply of heating steam and a condensate recovering unit 6 for discharging condensate produced as a result of heating are connected. More particularly, the steam supply pipe 3 is connected to an inlet of a steam ejector 5 and the jacket section 5 as a heating section is connected to a suction chamber 13 formed in an outer periphery of a nozzle communicated with the inlet of the steam ejector 5. Also, a shutoff valve 47 is connected to an outlet communicated with the suction chamber 13.
In operation, by opening the shutoff valve 47, air remaining within the jacket section 2 will be drawn into the suction chamber 13 to evacuate the inside of the jacket section 2. Thereafter, by dosing the shutoff valve 47, low-pressure steam is supplied into the jacket section 2, so that an object in the reaction vessel 1 may be heated by low-temperature steam of 100xc2x0 C. or lower.
With the conventional steam-heating apparatus described above, the apparatus is capable of steam-heating an object with the air remaining at the initial stage of the heating process being removed by suction. However, this apparatus cannot exhaust air which may be gradually accumulated with progress of the heating process, so that the apparatus becomes unable to maintain a predetermined heating temperature precisely. Specifically, when the heating apparatus is placed under the evacuated condition below the atmospheric pressure, atmospheric air may be inadvertently drawn through in the respective joints of the apparatus, thus leading to gradual accumulation of air inside the heating section. Moreover, the heating steam supplied to the apparatus may contain some air therein. Therefore, disadvantageous accumulation of air inside the heating section occurs not only in the initial stage of the heating process but also during the subsequent heating stage thereof
Accordingly, an object of the present invention is to provide a steam-heating apparatus capable of adjusting the heating temperature with high precision by effectively eliminating air which may be accumulated not only in the initial stage of the steam-heating process but also during the subsequent heating stage thereof.
For accomplishing the object noted above, a steam-heating apparatus proposed by the present invention comprises a steam ejector including a suction chamber connected to the heating section and an inlet for receiving supply of heating steam, the steam ejector being actuated in response to a drop in a temperature of the heating section by a predetermined value so as to suck air (an example of gas) in the heating section into the suction chamber of the steam ejector
That is, in response a drop by a predetermined value in the temperature in e.g. the heating section or in a condensate tank disposed between this heating section and the condensate recovering device, the steam ejector is actuated and steam is supplied to the inlet of the steam ejector, whereby a suction force is developed in the suction chamber for sucking the air accumulated in the heating section therein and subsequently exhausting this air to the outside.
Therefore, in the steam-heating apparatus, whenever the temperature of the heating section drops by a predetermined value due to presence of air therein not only in the initial stage of heating, but also during subsequent heating stage thereof, the steam ejector is actuated for sucking and exhausting this air.
Further, in addition to the above-described construction of the steam-heating apparatus, the steam-heating apparatus of the invention may filer comprise a temperature-responsive valve disposed at the inlet of the steam ejector, the temperature-responsive valve being opened in response to the drop by the predetermined value of the temperature of the heating section so as to supply the steam to the inlet of the steam ejector.
That is, by providing the temperature-responsive valve connected to the inlet of the steam ejector, when air has accumulated in the heating section to cause the temperature thereof to drop by a predetermined value, the temperature-responsive valve is opened to introduce steam into the inlet of the steam ejector and the air accumulated in the heating section is withdrawn by the resultant suction force developed in the suction chamber to be exhausted to the outside.
In addition to the above-described construction of the steam-heating apparatus, the steam-heating apparatus of the invention may further comprise a check valve disposed at a connection between the heating section and the suction chamber of the steam ejector, the check valve allowing only unidirectional passage of the air from the heating section to the suction chamber of the steam ejector.
That is, by providing the check valve disposed between the suction chamber of the steam ejector and the heating section or the condensate tank in addition to the temperature-responsive valve connected to the inlet of the steam ejector, when the temperature drops by a predetermined value as a result of accumulation of air inside the heating section or the condensate tank, the temperature-responsive valve is opened to supply steam to the inlet of the steam ejector and the check valve is opened by the resultant suction force of the steam ejector to allow communication of air from the heating section to the suction chamber thereby to suck and exhaust the air accumulated inside the heating section to the outside.
Further, the steam-heating apparatus of the present invention, in addition to the above-described construction of the steam-heating apparatus, further comprises a temperature-responsive valve disposed at a connection between the heating section and the suction chamber of the steam ejector, the temperature-responsive valve being opened in response to a drop by a predetermined value in the temperature of the heating section so as to allow suction of the air from the heating section to the suction chamber of the steam ejector.
That is, by providing a temperature-responsive valve disposed at a connection between the heating section and the suction chamber of the steam ejector, when air has accumulated inside the heating section thus causing a drop in its temperature by a predetermined value, the temperature-responsive valve is opened to establish communication between the heating section and the suction chamber of the steam ejector, whereby the air accumulated in the heating section can be sucked and exhausted to the outside by the resultant suction force developed in the suction chamber.
For accomplishing the object of this invention, the steam-heating apparatus of the present invention comprises a condensate tank disposed between the eating section and the condensate recovering unit and a steam ejector having a suction chamber connected to the heating section or to the condensate tank and an inlet for receiving supply of steam, the steam ejector being actuated in response to a drop by a predetermined value in the temperature inside the heating section or the condensate tank so as to suck air in the heating section or the condensate tank into the suction chamber of the steam ejector.
That is, when the temperature inside the heating section or the condensate tank interposed between the heating section and the condensate recovering unit drops by a predetermined value, the steam ejector is actuated to cause the air in the heating section or the condensate tank to be sucked into the suction chamber of the steam ejector. With this, when air has accumulated inside the heating section and the condensate tank resulting in a temperature drop by a predetermined value, the steam ejector is actuated so that steam is supplied to the inlet of the steam ejector from e.g. a steam supply pipe an the resultant suction force developed in the suction chamber can suck the air accumulated inside the heating section and the condensate tank and exhaust the air to the outside.
Accordingly, in the steam-heating apparatus, both in the initial stage of heating and during the subsequent heating stage, whenever air has accumulated inside the heating section or the condensate tank thus resulting in such temperature drop, the steam ejector is actuated to suck and exhaust the air.
Further, the steam-heating apparatus of this invention, in addition to the above-described construction of the steam-heating apparatus, further comprises a temperature-responsive valve disposed at the inlet of the steam ejector, the temperature-responsive valve being opened in response to a drop by a predetermined value in the temperature inside the heating section or the condensate tank so as to supply the steam of the steam supply pipe to the inlet of the steam ejector.
That is to say, m case the steam-heating apparatus includes a condensate tank, there is provided the temperature-responsive valve connected to the inlet of the steam ejector. With this, when air has accumulated inside the heating section or the condensate tank resulting in a temperature drop by a predetermined value, the temperature-responsive valve is opened so as to supply steam to the inlet of the steam ejector and a suction force is developed in the suction chamber. With this, the air accumulated in the heating section and the condensate tank may be sucked into the suction chamber via a check valve or the like provided between the suction chamber of the steam ejector and the condensate tank and the air may be exhausted to the outside subsequently.
Further, the steam-heating apparatus of the present invention, in addition to the above-described construction of the steam-heating apparatus, further comprises a check valve provided at a connection between the heating section or the condensate tank and the suction chamber of the steam ejector, the check valve allowing only unidirectional gas passage from the heating section or the condensate tank to the suction chamber of the steam ejector.
That is, by providing a check valve between the suction chamber of the steam ejector and the heating section or the condensate tank in addition to the temperature-responsive valve connected to the inlet of the steam ejector, when air has accumulated inside the heating section or the condensate tank thus resulting in a drop in its temperature by a predetermined value, the temperature-responsive valve is opened to supply steam to the inlet of the steam ejector and the check valve is opened by the resultant suction force from the steam ejector so as to allow communication of air from the heating section or the condensate tank to the suction chamber, so that the air accumulated inside the heating section or the condensate tank may be sucked and exhausted to the outside by the suction force in the suction chamber.
For accomplishing the object of this invention, with the steam-heating apparatus of the present invention, the condensate recovering unit includes a high-pressure control fluid inlet for receiving supply of high-pressure control fluid for pressure-transporting and discharging the condensate, the apparatus comprises an ejector including a suction chamber connected to the heating section, an inlet for receiving supply of the high-pressure control fluid and an outlet connected to the high-pressure control fluid inlet and further comprises a valve means provided at a connection between the heating section and the suction chamber of the steam ejector.
That is to say, the ejector is incorporated in a high-pressure control fluid passage for passing the high-pressure control fluid; the outlet of the ejector is connected to the high-pressure control fluid inlet of the condensate recovering unit; and the suction chamber of the ejector and the heating section are connected to each other via the valve means comprising e.g. a shutoff valve. In operation, when the high-pressure control fluid is introduced into the condensate recovering unit thereby to pass the high-pressure control fluid through the ejector, a suction force is developed in the suction chamber of the ejector, whereby air accumulated inside the heating section may by sucked and exhausted via the valve means.
Accordingly, both in the initial stage of the heating and the subsequent heating stage, each time the high-pressure control fluid is introduced into the condensate recovering unit, a suction force is developed in the ejector, so that the air accumulated in the heating section may be eliminated.
For accomplishing the object of this invention, with the steam-heating apparatus of the present invention, the condensate recovering unit includes a high-pressure control fluid inlet for receiving supply of high-pressure control fluid for pressure-transporting and exhausting the condensate and a condensate returning outlet for exhausting the pressure-transported condensate, the apparatus comprises an ejector including a suction chamber connected to the heating section and an inlet connected to the condensate returning outlet, and the apparatus further comprises a valve means provided at a connection between the heating section and the suction chamber of the steam ejector.
That is to say, the ejector is incorporated in a high-pressure control fluid passage connected to the condensate returning outlet of the condensate recovering unit and the suction chamber of the ejector and the heating section are connected to each other via the valve means comprising e.g. a shutoff valve. In operation, when the high-pressure control fluid is introduced from the condensate pressure-transporting passage thereby to pass the condensate through the ejector, a suction force is developed in the suction chamber of the ejector, whereby air accumulated inside the heating section may by sucked and exhausted via the valve means.
During both the initial stage of the heating process and the subsequent heating stage of the same, a suction force is developed in the ejector every time the condensate is pressure-transported from the condensate pressure-transporting passage of the condensate recovering unit, whereby air accumulated inside the heating section may be sucked and exhausted,
Further, with the steam-heating apparatus of the present invention, in addition to the above-described construction, the valve means comprises a temperature-responsive valve which is opened in response to a drop in the temperature by a predetermined value in the heating section or between the heating section or the condensate recovering unit so as to allow suction of air from the heating section into the suction chamber of the ejector.
That is to say, when the temperature in the heating section or between the heating section and the condensate recovering unit, such as the condensate tank, drops by a predetermined value, the temperature-responsive valve as the valve means is opened to establish communication between the heating section and the suction chamber of the steam ejector, so that the resultant suction force developed in the suction chamber sucks and exhausts the air accumulated inside the heating section to the outside.


An example engine system is disclosed. The engine system may control a turbocharger of an internal combustion engine, and more particularly control a boost pressure provided by a turbocharger to an internal combustion engine. An example method for controlling a boost pressure provided by a turbocharger may include receiving a boost pressure demand and identifying a compressor speed demand to achieve the received boost pressure demand. The method may also include converting the compressor speed demand into a kinetic energy demand of the turbocharger rotating components and controlling the kinetic energy of the turbocharger rotating components to meet the kinetic energy demand by controlling power supplied by the turbine and the electric motor assist.

Turbochargers are often used to increase a boost intake air charge pressure (e.g., defined as force per unit area or energy per unit volume) to the intake manifold of an internal combustion engine. Turbochargers typically include a compressor and a turbine attached to a shaft. The turbine is designed to utilize the expansion/flow of exhaust gases from the internal combustion engine to drive the shaft, and thus the compressor. The compressor then compress air from an ambient inlet air pressure to a compressed boost pressure, which is then fed to the intake manifold of the internal combustion engine, often through an intercooler. An increased amount of fuel is mixed with the increased boost pressure to achieve an air/fuel ratio that is suitable for optimum combustion in the internal combustion engine. This results in more power that can be delivered by the internal combustion engine.
In some cases, such as at low RPMs of the internal combustion engine, the expansion/flow of exhaust gases is relatively low. When subsequent rapid increased power is desired from the internal combustion engine, it may take some time for the exhaust gases to spin up the turbocharger to deliver the desired boost pressure. This delay in responsiveness of the turbocharger is often referred to as turbo lag. In some cases, an electric motor assist may be coupled to the shaft of the turbocharger to assist in the acceleration and/or deceleration of the turbocharger shaft under certain operating conditions.
Controlling such turbochargers under dynamic operating conditions can be a challenge. The control algorithms are often non-linear and resource intensive. What would be desirable are improved methods, devices, and/or systems for controlling a turbocharger of an internal combustion engine.

Boost pressure control for electrically assisted turbochargers


The escapement comprises an escapement wheel (1) and an anchor (2). In the place of the traditional limiting walls or pins, the escapement comprises, on the anchor (2) and/or the escapement wheel (1), means (17, 18) for limiting the oscillations of the anchor (2) during normal operation of the escapement. In order to prevent contact between the impulse beak (10) of the pallets (6, 7) and the escapement wheel (1) upon impacts, the escapement wheel (1) has protrusions (20, 21, 22) at its periphery.

1. Field of the Invention
The present invention relates to an anchor escapement for a timepiece, such as a Swiss lever escapement.
2. Description of the Related Art
Anchor escapements generally comprise fixed limitation members in the form of walls called "solid bankings" machined in the bottom plate or in a bridge, or in the form of pins fixed to the bottom plate. These fixed limitation members serve as abutments for the anchor in order to limit the amplitude of its oscillations and define two lock positions where the anchor is in abutment against a respective one of these fixed limitation members, while a tooth of the escapement wheel is itself in abutment against the locking plane of the entry or exit pallet of the anchor. These fixed limitation members also act to protect the escapement against impacts in that they prevent the anchor from moving beyond its lock positions when the watch is subjected to impacts and thus prevent the pallets of the anchor from being able to strike the escapement wheel.
However, there are anchor escapements which do not have such fixed limitation members. In this case it is a particular arrangement or shape of the toothing of the escapement wheel and/or of the pallets which fulfils the function of limiting oscillations of the anchor during normal operation of the escapement, i.e. which defines the lock positions of the anchor. Examples of such escapements are described in the documents CH 101651, CH 569997, CH 343898, DE 1162290, GB 682566 and U.S. Pat. No. 3,146,581. With the exception of that described in document CH 569997, these escapements all have the disadvantage that, when the watch is subjected to impacts, the anchor can move beyond its lock positions until the impulse beak of one of the pallets strikes the escapement wheel. By way of illustration, FIG. 1 shows the position of an anchor escapement without fixed limitation members after an impact which has displaced the anchor in the direction indicated by the arrow F1, while the anchor was in its lock position where its entry pallet was blocking the escapement wheel. It can be seen that the impulse beak of the entry pallet is in contact with the rim of the escapement wheel. In a similar manner, upon an impact having the effect of displacing the anchor in the opposite direction (FIG. 2, arrow F2), the impulse beak of the exit pallet comes into contact with the rim of the escapement wheel. Such contacts between an edge (impulse beak) and the escapement wheel can cause considerable damage to the anchor and/or the escapement wheel, in particular if these elements, or one of them, is/are produced from a fragile material such as silicon. Furthermore, the chips which can result therefrom can move into the movement of the watch, cause damage to other components and disrupt operation of the movement.
The escapement in accordance with document CH 569997 has dihedral recesses formed in the rim of the escapement wheel, which recesses are intended to receive and lock the pallets in the lock positions of the anchor. In the event of the watch being subjected to an impact, these recesses prevent the anchor from moving beyond its lock positions. In some embodiments, small clearance gaps are also provided in the escapement wheel to prevent the impulse beak of the pallets from coming into contact with the said wheel in the said lock positions. Nevertheless, this escapement has a major disadvantage in that it requires the pallets to be of the same shape and to have identical drawing angles, which prevents the efficiency of the escapement from being optimised by adapting the shapes and dimensions of the pallets.


To achieve further weight reduction and thinning of a seat structure. A configuration in which a side frame cover 212 composed of a laminated body 1 provided with a planar member made of cloth and planar members made of synthetic resin laminated on both sides of the planar member made of cloth via adhesive agent and formed in a predetermined shape is joined to a side frame base body 211 composed of a metal member is obtained. Therefore, the thickness of the metal member used can be reduced by an amount corresponding to a strength the laminated body compensates for, which results in achievement of further weight reduction from a conventional structural member composed of only metal members that are used at the same site. Further, when an impact force is applied, the impact force can be consumed as a force that causes delamination of the laminated body from the metal member at a portion where they are joined via the adhesive agent.

In a transport machine such as an automobile, in order to achieve weight reduction, the rate of usage of synthetic resin members has increased. For example, in Patent Document 1, a vehicle body structure where a synthetic resin member is positively used for a portion which does not substantially contribute as a strengthening member, and where the synthetic resin member is joined to a metal member with adhesive agent, is disclosed.    Patent Document 1: Japanese Patent Application Laid-open No. H09-86445

Structural member and seat structure for transport machine


An apparatus for testing a memory device having a plurality of data lines includes an input circuit, a compression circuit, and an output circuit. The input circuit is adapted to receive at least a first subset of the data lines and a plurality of enable signals. Each enable signal is associated with at least one of the first subset of data lines. The compression circuit is coupled to the input circuit and is adapted to detect a predetermined pattern on the first subset of data lines. The output circuit is coupled to the compression circuit and adapted to provide at least a pass signal when the predetermined pattern is detected on the first subset of data lines. The input circuit is capable of masking at least one of the first subset of data lines from the compression circuit based on the associated enable signal.

1. Field of the Invention
This invention relates generally to the testing of memory devices, and more particularly to the testing of memory devices using a compression circuit.
2. Description of the Related Art
Memory devices, such as a synchronous dynamic random access memory (SDRAM), are being developed with ever-increasing densities. During the manufacturing process, the memory device is tested to verify proper operation. If improperly functioning cells are identified, the memory device may be repaired or discarded, depending on the number, type, and arrangement of faulty memory cells. Also, if a sample of memory devices is tested and the individual memory devices are found to have faults in common locations, certain stages in the manufacturing process may be examined and/or altered to correct possible systemic defects.
As the density of memory devices increases, the time required to test the devices also increases. Compression circuits have been developed to simultaneously test blocks of memory cells and provide information regarding the success or failure of the test. A test using a compression circuit indicates that one of the cells in the block of cells is faulty. Further testing is required to identify the specific cell. Typically, the further test involves a time consuming cell-by-cell test to identify the faulty cell.
FIG. 1 illustrates a logic diagram of a prior art compression circuit 10. The compression circuit 10 of FIG. 1 receives sixteen input lines, D1-D16 (e.g., I/O lines) and provides an output based on the success of the test. The compression circuit 10 includes a first portion 14 adapted to provide an indication that all logic ones are present on the input lines D1-D16, and a second portion 16 adapted to provide an indication that all logic zeros are present on the input lines D1-D16. If any of the input lines D1-D16 on the first portion 14 receive a logic xe2x80x9c0xe2x80x9d, the first portion 14 of the compression circuit 10 will indicate a fail condition. Likewise, if any of the input lines on the second portion 16 receives a logic xe2x80x9c1xe2x80x9d, the second portion 14 of the compression circuit 10 will indicate a fail condition.
The first portion 14 of the compression circuit 10 includes an arrangement of NAND gates 18, NOR gates 20, and an inverter 22 that collectively perform a logical 16-bit wide NAND function. Conversely, the second portion 16 of the compression circuit 10 includes NOR gates 24, NAND gates 26, and an inverter 28 that collectively perform a logical 16-bit wide NOR function. The compression ratio of the compression circuit 10 may be altered by increasing or decreasing the number of cascaded rows of NAND gates 18, 24 and NOR gates 20, 26.
The compression circuit 10 also includes an output circuit 30 adapted to tailor the output format into one of two output modes, tristate and JEDEC. The JEDEC mode of operation corresponds to a mode of error detection defined by Joint Electron Device Engineering Council (JEDEC) standards. The output circuit 30 includes multiplexers 32, 33 that are enabled during the tristate mode of operation, and multiplexers 34, 35 that are enabled during the JEDEC mode of operation. Mutually exclusive logic signals, TRI and JED on lines 36, 37, respectively, determine the particular multiplexers 32, 33, 34, 35 that are enabled.
To operate in the tristate output mode, the TRI signal is held at a logically high state to enable the multiplexers 32, 33. The JED signal is held at a logically low state to disable the multiplexers 34, 35. The multiplexer 32 receives the output of the first portion 14 of the compression circuit 10, where the first portion 14 outputs a logic xe2x80x9c0xe2x80x9d to indicate a pass condition and a logic xe2x80x9c1xe2x80x9d to indicate a fail condition. The output of the multiplexer 32 is coupled to the gate input of a p-type transistor 38. The transistor 38 is connected between a voltage source 39 (e.g., about 2.2V) and an output terminal 40. When the first portion 14 of the compression circuit 10 indicates a pass condition (i.e., logic xe2x80x9c0xe2x80x9d), the transistor 38 is enabled and the voltage at the output terminal 40 is pulled to a logically high state by the voltage source 39. During a fail condition (i.e., logic xe2x80x9c1xe2x80x9d) the transistor 38 is disabled, disconnecting the power source 39 from the output terminal 40.
The multiplexer 33 receives the output of the second portion 16 of the compression circuit 10, where the second portion 16 outputs a logic xe2x80x9c1xe2x80x9d to indicate a pass condition and a logic xe2x80x9c0xe2x80x9d to indicate a fail condition. The output of the multiplexer 33 is coupled to the gate input of an n-type transistor 42. The transistor 42 is connected between the output terminal 40 and ground. When the second portion 16 of the compression circuit 10 indicates a pass condition (i.e., logic xe2x80x9c1xe2x80x9d), the transistor 42 is enabled and the voltage at the output terminal 40 is pulled to a logically low state. During a fail condition (i.e., logic xe2x80x9c0xe2x80x9d) the transistor 42 is disabled, disconnecting the output terminal 40 from ground.
The portion 14, 16 of the compression circuit 10 that indicates a passing condition will control the voltage on the output terminal 40. The voltage on the output terminal 40 is read to determine the success or failure of the test. The value on the output terminal 40 of the compression circuit 10 matches the actual value that was written to the cells during the test. For example, if all logic xe2x80x9c1xe2x80x9d values were successfully read from the memory device, the first portion 14 would pass and the second portion 16 would fail. The compression circuit 10 would output a logic xe2x80x9c1xe2x80x9d to indicate the successful test. Conversely, if all logic xe2x80x9c0xe2x80x9d values were successfully read from the memory device, the second portion 16 would pass and the first portion 14 would fail. The compression circuit 10 would output a logic xe2x80x9c0xe2x80x9d to indicate the successful test. If both portions 14, 16 indicate a fail condition, the output terminal 40 is tristated and has a voltage of about 1.1V.
To operate in the JEDEC output mode, the JED signal is held at a logically high state to enable the multiplexers 34, 35, and the TRI signal is held at a logically low state to disable the multiplexers 32, 33. The outputs of the first and second portions 14, 16 of the compression circuit 10 are received by an XOR gate 44. In the circuit of FIG. 1, the XOR gate 44 is a two input gate, however, the actual transistors (not shown) that define the XOR gate 44 require the both the input signal and its compliment to operate. Accordingly, the output of the inverter 22, its compliment (i.e., the input to the inverter 22), the input of the inverter 28, and its compliment (i.e., the output of the inverter 28) are provided to the XOR gate 44. Unlike the example described above for the tristate mode, the input of the inverter 28 indicates pass or fail as opposed to the output of the inverter 28. Accordingly, a pass condition is denoted by a logic xe2x80x9c0xe2x80x9d at the input of the inverter 28.
The output of the XOR gate 44 is inverted by an inverter 46. The output of the inverter 46 is provided to the multiplexers 34, 35. If only one of the first and second portions 14, 16 of the compression circuit 10 indicates a pass condition (i.e., one portion 14, 16 has a logic xe2x80x9c0xe2x80x9d and the other has a logic xe2x80x9c1xe2x80x9d), the XOR gate 44 outputs a logic xe2x80x9c1xe2x80x9d, which is inverted by the inverter 46. The resulting logic xe2x80x9c0xe2x80x9d is provided to the multiplexers 34, 35, thus enabling the transistor 38 and pulling the voltage at the output terminal 40 to a logically high state. Conversely, if both the first and second portion 14, 16 pass or both fail, the XOR gate 44 outputs a logic xe2x80x9c0xe2x80x9d, which is inverted by the inverter 46. The resulting logic xe2x80x9c1xe2x80x9d is provided to the multiplexers 34, 35, thus enabling the transistor 42 and pulling the voltage at the output terminal 40 to ground.
FIG. 2 is a timing diagram of the response of the compression circuit 10 to various passed and failed tests. In the tristate mode of operation, the TRI signal 50 is held at a logically high state. The JED signal (not shown) is held at a logically low state. A failure signal 52 is used to simulate a test failure. During alternating tests, the compression circuit output signal 54 alternates between a logic xe2x80x9c1xe2x80x9d level and a logic xe2x80x9c0xe2x80x9d level to indicate the successful logic xe2x80x9c1xe2x80x9d tests and logic xe2x80x9c0xe2x80x9d tests. During a simulated failure 56, both the first portion 14 and the second portion 16 indicate a failed condition and the compression circuit output signal 54 is tristated.
In the JED mode (JEDEC), the ACT signal 50 is held at a logically low state. The JED signal (not shown) is held at a logically high state. During alternating tests the compression circuit output signal 54 maintains a logic xe2x80x9c1xe2x80x9d level to indicate the successful logic xe2x80x9c1xe2x80x9d tests and logic xe2x80x9c0xe2x80x9d tests. During a simulated failure 58, both the first portion 14 and the second portion 16 indicate a failed condition on successive tests and the compression circuit output signal 54 transitions to a logic xe2x80x9c0xe2x80x9d state to indicate the failure.
Compression circuits are typically included on the die of the memory device along with the memory device core. In embedded devices with multiple memory cores, each core typically has its own compression circuitry. The compression circuit typically receives inputs from a plurality of local or intermediate input/output (I/O) lines and provides an output indicating that either all lines passed or one of the lines failed. One or more compression circuits may be used, depending on the degree of desired compression. For example, if it was desired to simultaneously test 64 lines, and each compression circuit was adapted to receive eight input lines, eight compression circuits would be required.
The outputs of the compression circuit are typically tied to the external data in/data out (DQ) lines of the memory device. Changes in the memory device density and/or architecture of the memory device often require that the routing and logic gate arrangement of the compression circuit be redesigned.
During the testing process, the compression circuit adds a finite amount of delay to the stage of the memory device including the compression circuit. In a three cycle latency memory device, the compression circuit is typically included in the third stage, prior to the DQ outputs. Consider the case where, without the compression circuit enabled, the time required to complete the third stage is equal to or less than the time to complete the other two stages. The overall speed of the memory device is determined by the longest stage (i.e., the clock used to drive the memory device cannot have a period shorter than the length of the slowest stage). Now, add the additional delay contributed by the compression circuit (i.e., logic gate propagation times) to the third stage. With the additional delay, the third stage may become the speed limiting stage, and as a result, the speed of the memory device may need to be downgraded because the memory device cannot be tested at full speed. Reducing the clock frequency of the input clock used to test the memory device also lengthens the amount of time required to test the memory device.
As is common in memory device design, the memory device may have lines with differing data topologies. For example, if a logic xe2x80x9c1xe2x80x9d is written into a cell of a first topology type, a logic xe2x80x9c1xe2x80x9d is stored in the cell. If the same logic xe2x80x9c1xe2x80x9d is written into a cell of a second topology, a logic xe2x80x9c0xe2x80x9d may actually be stored in the cell. During the testing of the memory device, lines of one topology type may not be compressed with lines of a second topology type.
One of the lines coupling the memory device to the compression circuit may be shorted to another of the lines. If all the lines of the same topology type were to run in parallel from the memory device to the compression circuit, it is possible that the compression circuit might illegally pass the test (i.e., fail to detect the fault). Another possible error might arise due to capacitive coupling between adjacent lines. For example, if sixteen adjacent lines are coupled to one compression circuit, capacitive coupling could occur between the lines. A failed line may be coupled by the other fifteen lines, which are going to a logically high state, and forced to a logically high state. Coupling of this nature could disguise faults in the memory device.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, an apparatus is provided for testing a memory device having a plurality of data lines. The apparatus includes an input circuit, a compression circuit, and an output circuit. The input circuit is adapted to receive at least a first subset of the data lines and a plurality of enable signals. Each enable signal is associated with at least one of the first subset of data lines. The compression circuit is coupled to the input circuit and is adapted to detect a predetermined pattern on the first subset of data lines. The output circuit is coupled to the compression circuit and adapted to provide at least a pass signal when the predetermined pattern is detected on the first subset of data lines. The input circuit is capable of masking at least one of the first subset of data lines from the compression circuit based on the associated enable signal.
In another aspect of the present invention, a method is provided for testing a memory device having a plurality of data lines. The method includes reading data present on at least a subset of the plurality of data lines. The data associated with at least one data line of the subset is masked. It is determined if the data matches a predetermined pattern. At least a pass signal is provided if the data matches the predetermined pattern.

Compression circuit for testing a memory device


A screw-type extruder has a housing and at least one screw which is rotatably arranged in a bore in the housing and which conveys material while melting or plasticizing in a conveying direction to a discharge channel, a starting valve and a throttle for generating a back pressure on the molten or plasticized material being arranged in the area of the discharge channel. In order to avoid long flow paths of the molten or plasticized material via the throttle and starting valve, there is provided a starting valve/throttle unit having a starting valve and throttle body which is displaceable at right angles to the conveying direction out of a starting position into a throttling position.

Particularly when processing materials which are sensitive to shear and dwell time, for example commercial plastics or food compounds, on screw-type machines, that is particularly extruders, it is often necessary to influence the plasticizing or melting of these materials or the temperature thereof and other parameters by a throttling action at the end of the machine before the plasticized or molten materials are discharged. Furthermore, it is necessary to some extent to provide so-called starting valves which enable the materials to be channeled out of the machine during the starting operation until the plasticizing or melting process is set in such a manner that the material can be fed to the standard discharge element, that is for example an extrusion die, where it is brought into any form, for example for granulating. The normally used tandem arrangement of the throttle on one side and starting valve on the other side results in relatively long material flow paths in the discharge elements, which is unacceptable particularly in the case of materials sensitive to dwell time because the material can suffer thermal damage. In addition, deposits of the material on the discharge channel walls can occur.
A screw-type machine is known from German published patent application No. 21 21 305, in which discharge channel a throttle body is arranged, which throttle body can be actuated via a drive arrangement at right angles to the conveying direction. A starting valve is not provided in this case.
A screw-type machine having a so-called vane-type throttle is known from German patent specification No. 28 33 057 (corresponding to U.S. patent application Ser. No. 819,227), which throttle is arranged in a double screw bore and can be pivoted by pivoting movements about its longitudinal axis into positions having a variable throttling effect.
German published patent application No. 19 37 862 discloses a screw-type machine with a starting valve arranged in the discharge channel which allows the molten material alternately to be drawn off through a starting outlet opening or fed to the discharge element, for example an extrusion die. A throttle is not provided in this case.

Screw-type extruder having a starting valve and throttle


Various methods and systems for weighting material density images based on the material imaged are disclosed. In one embodiment, a method for dual energy imaging of a material comprises generating an odd material density image, generating an even material density image, applying a first weight to the odd material density image and a second weight to the even material density image, and generating a material density image based on a combination of the weighted odd material density image and the weighted even material density image. In this way, the image quality may be improved without increasing a radiation dosage.

Dual or multi-energy spectral computed tomography (CT) systems can reveal the densities of different materials in an object and generate images acquired at multiple monochromatic x-ray energy levels. In the absence of object scatter, a system derives the behavior at a different energy based on a signal from two regions of photon energy in the spectrum: the low-energy and the high-energy portions of the incident x-ray spectrum. In a given energy region of medical CT, two physical processes dominate the x-ray attenuation: Compton scattering and the photoelectric effect. The detected signals from two energy regions provide sufficient information to resolve the energy dependence of the material being imaged. Detected signals from the two energy regions provide sufficient information to determine the relative composition of an object composed of two hypothetical materials.
Different approaches have been developed to realize dual energy or spectral imaging. To name a few, dual x-ray source and detector, single x-ray source and detector with multiple acquisitions at different peak kilovoltage (kVp) or interleaved with fast kVp switching capability, and single x-ray source with an energy discriminative detector are leading techniques. In a single x-ray source and detector arrangement, a conventional third generation CT system may acquire projections sequentially at different kVp levels, which changes the peak and spectrum of energy of the incident photons comprising the emitted x-ray beams. Two scans are acquired—either back-to-back sequentially in time where the scans require two rotations around the subject, hereinafter referred to as rotate-rotate dual energy, or interleaved as a function of the rotation angle requiring one rotation around the subject, hereinafter referred to as fast-switching dual energy, in which the x-ray tube operates, for instance, at 80 kVp and 140 kVp potentials.
Once dual or multi-energy data is obtained, a basis material decomposition (BMD) algorithm may be applied in order to image two distinct materials, such as water and iodine, as examples. A conventional BMD algorithm is based on the concept that, in an energy region for medical CT, the x-ray attenuation of any given material can be represented by a proper density mix of two materials with distinct x-ray attenuation properties, referred to as the basis materials. The BMD algorithm computes two material density images that represent the equivalent density of one of the basis materials based on the measured projections at high and low x-ray photon energy spectra, respectively. The material density images may be further converted to form monochromatic images at other desired monochromatic energies.
Typically the measured projections at high and low x-ray photon energy spectra are equally treated when generating material density images. However, the x-ray attenuation properties of the basis materials may affect the material density differently at different energy levels. Furthermore, fast-switching dual energy CT systems may interpolate high and low energy projection data to obtain complete projection datasets, potentially introducing noise to the data. As a result, material density images and subsequently formed monochromatic images may feature a degraded image quality due to an unnecessary dependence on interpolated data.

Methods and systems for task-based data generation and weighting for CT spectral imaging


A circuit and method for suppressing the effect of noise on a data strobe signal DQS in a double data rate (DDR) SDRAM is provided. The circuit includes a data input latch circuit for receiving data to be stored and for latching the data in a memory array in response to a control signal; and a control signal generator for generating the control signal in response to a data strobe signal wherein the control signal has a predetermined minimum pulse width of the data strobe signal. The control signal generator includes a reset/set flip-flop for generating the control signal, wherein the flip-flop is set by the data strobe signal; and a low pass filter for receiving the data strobe signal and for outputting a reset signal to the flip-flop if the data strobe signal is greater than the predetermined minimum pulse width.

1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a circuit and method for suppressing noise of a postamble data strobe signal (DQS) in a double data rate (DDR) synchronous dynamic random access memory (SDRAM).
2. Description of the Related Art
Synchronous dynamic random access memories (hereinafter, referred to as SDRAMs) have been developed for achieving a high speed of operation in DRAM devices. The SDRAM operates in synchronization with an external clock signal and includes a single data rate (SDR) SDRAM, a double data rate (DDR) SDRAM and the like.
The SDR SDRAM operates in synchronization with rising edges of the external clock, so that one data is processed within one period of the external clock. On the contrary, the DDR SDRAM operates in synchronization with rising and falling edges of a data strobe signal (DQS), so that two successive data are processed within one period of the external clock. Therefore, compared with the SDR SDRAM, the DDR SDRAM achieves at least twice the operation speed without increasing a frequency of the external clock.
FIG. 1(a) is a timing diagram illustrating an operation of a conventional DDR SDRAM. In DDR SDRAMs, data arrives centered to both edges of the DQS signal, i.e., a rising edge and a falling edge. The DQS signal can advance or trail a clock signal (VCLK), generated by an external clock, by up to +/xe2x88x9225% of the cycle time, i.e., tDQSSmin and tDQSSmax respectively. After the initial latching, the data is divided on separate data lines (SRWD) which direct the data further into a memory array according to the edge of the DQS signal they were originally centered to (even/odd data). With the falling edge of the DQS signal, the data is driven onto those separate data lines (SRWD). The data is driven into the memory array after being internally latched with the rising edge of a signal derived from a CAS (Column Address Strobe) signal (see Latchpoint in FIG. 1). This CAS signal is ignorant to the tDQSS value (a cycle period of the DQS signal). After the last valid DQS pulse, the DQS signal is not driven anymore and the system termination pulls the DQS signal into a tristate level, as shown in FIG. 1(a) at point A.
After the last valid DQS edge, an off-chip driver driving the DQS signal stops driving and the DQS signal is pulled from a postamble state, which is defined as a low DQS signal before data issues, into the tristate level. At this point, the DQS line is subject to noise from outside the chip or memory device, e.g., switching noise, ringing, etc. Referring to FIG. 1(b), in the case of tDQSSmin (Early DQS signal), noise on the DQS line can cause a false falling edge, possibly forcing invalid data (iDATA) onto the separate data lines (SRWDea) before the correct data can be latched with the rising edge of the CAS signal (see point B in FIG. 1(b)). Additionally, in the case of tDQSSmax (Late DQS signal) as shown in FIG. 1(c), noise can possibly force invalid data (iDATA) onto the separate data lines at point C, however, this will not effect the integrity of the data stored in the memory device since it occurs after the rising edge of the CAS signal and will not be latched into the memory array.
Accordingly, it is an aspect of the present invention to provide a circuit and method for storing data in a memory device which prevents noise from latching invalid data into a memory array of the memory device.
It is another aspect of the present invention to provide a circuit and method for storing data in a memory device which forces a data strobe signal to have a minimum pulse width effectively eliminating invalid data latched by unwanted noise.
According to one aspect of the present invention, a circuit for storing data in a memory device is provided including a data input latch circuit for receiving data to be stored and for latching the data in a memory array in response to a control signal; and a control signal generator for generating the control signal in response to a data strobe signal wherein the control signal has a predetermined minimum pulse width of the data strobe signal.
According to another aspect of the present invention, the control signal generator includes a reset/set flip-flop for generating the control signal, wherein the flip-flop is set by the data strobe signal; and a low pass filter for receiving the data strobe signal and for outputting a reset signal to the flip-flop if the data strobe signal is greater than the predetermined minimum pulse width. The control signal generator further includes a delay element coupled between the low pass filter and the flip-flop for delaying the resetting of the flip-flop for a period greater than the predetermined minimum pulse width.
In another aspect of the present invention, a method for storing data in a memory device includes the steps of receiving data on a data bus; latching the data from the data bus in response to a data strobe signal; and latching the data into a memory array in response to a control signal wherein the control signal has a predetermined minimum pulse width of the data strobe signal.

DQS postamble noise suppression by forcing a minimum pulse length


The invention provides compounds of formula I:

U.S. Pat. No. 4,629,493 discloses herbicidal compounds of the following formula:
wherein A is —CH— or —N—; X is a halogen; n is 0, 1, or 2; R1 is hydrogen or a lower alkyl group; and R2 is —OH, among other values. One of these compounds is currently sold commercially for the control of annual and perennial grass weeds in broadleaf crops. This compound has the following formula:

Corbett et al, Investigational New Drugs, 16 129-139 (1998) evaluated a series of quinoxaline compounds for activity against solid tumors in mice. The following compound (referred to as XK469) was reported to have broad activity against transplantable mouse tumors.
The compound was also reported to have a relatively low potency, and to produce several undesirable side effects, including in vivo toxicity, e.g., paralytic ileus, GI-epithelial damage, marrow toxicity, neuromuscular toxicity and weight loss. There is currently a need for additional antitumor agents.

This patent is subject to a terminal disclaimer.

Abstract: wherein Y is F, Cl, Br, methyl or methoxy; and pharmaceutically acceptable salts thereof. The compounds are effective antitumor agent. The invention also provides pharmaceutical compositions comprising a compound of formula I or a salt thereof, intermediates useful for preparing a compound of formula I, and therapeutic methods comprising administering a compound of formula I or a salt thereof to a mammal in need thereof.


A collapsible core device for molding articles around the core device in a mold cavity includes a first sleeve, a second sleeve and an expansion member. The first sleeve includes a plurality of first ribs extending from a first base in an axial direction and defining a discontinuous first perimeter surrounding a channel. The second sleeve includes a plurality of second ribs extending from a second base in an axial direction and defining a discontinuous second perimeter surrounding the central channel. Each of the second ribs is arranged between adjacent ones of the first ribs. The expansion member is fittable within the central channel to displace the first and second ribs outwardly to form an overall perimeter defined by the first and second ribs.

Collapsible cores have been manufactured for many years, as shown in U.S. Pat. No. 3,247,548. This patent discloses a collapsible core for molding threaded container caps. According to this patent, a one-piece core is longitudinally divided into a plurality of circumferentially disposed sections. The sections include inner and outer ribs that are formed into a common base. The sections are resilient in a radial direction and when radially unsupported are in a collapsed position. When a pin is inserted into a central channel of the sections, the sections are held in an expanded condition, used for molding. When molding is completed, the pin is withdrawn, and the sections collapse so that the cap can be removed.
The present inventor has recognized that the core as described in the aforementioned patent suffers the drawback that the core is expensive and difficult to manufacture. The present inventor has recognized that it would be desirable to provide collapsible core that was more cost effectively manufactured and more effectively operated.

Collapsible core assembly for a molding apparatus

Progressive Components International Corporation


A controllable magnetorheological (MR) damper having first, second and third portions is disclosed. The first and second portions have a translational degree of freedom therebetween, and the third portion has a rotational degree of freedom with respect to the first and second portions. The first and third portions are coupled via a translation-to-rotation converter, and the second and third portions are coupled via a magnetorheological (MR) fluid. A bearing is disposed between the first and second portions for supporting a side load therebetween, a magnetic field generator is in field communication with the magnetorheological fluid, and a signal path is in signal communication with the magnetic field generator. The third portion is rotationally responsive to translational motion between the first and second portions, the shear stress characteristic of the magnetorheological fluid is responsive to the magnetic field generator, and the magnetic field generator is controllably responsive to an excitation signal from the signal path.

The present disclosure relates generally to a magnetorheological damper, and particularly to a controllable magnetorheological damper for damping the suspension system of a vehicle, and a control system and method for using the same.
Vehicle suspension systems utilize damping devices or shock absorbers for controlling the vibrations of the body and wheel due to road disturbances imposed on the mass-spring system of the vehicle body, wheel and suspension springs. A vehicle suspension damper usually provides a resistive force proportional to the relative velocity between the body and the wheel. Passive dampers may employ an oil-filled cylinder and piston arrangement, while active and controllable dampers may employ a magnetorheological (MR) fluid-filled cylinder and piston arrangement where the viscosity of the MR fluid may be changed by the introduction of a magnetic field. Such MR dampers, however, employ large quantities of MR fluid, such as in excess of one liter per vehicle, need special finishes on the piston rod and the inner surface of the cylinder wall, and need special seals to minimize abrasion from the MR fluid. Passive and active dampers may be used in struts at the front of a vehicle and/or as shock absorbers at the rear of the vehicle.
While existing dampers, suspension damping systems and methods for controlling suspension damping systems may be suitable for their intended purpose, there remains a need in the art for improvements that overcome existing drawbacks.

Magnetorheological device and system and method for using the same


The rotor position of a synchronous motor is determined, in that for a plurality of current vectors distributed over one electrical rotation of the synchronous motor, the amount of the current vector which is necessary to attain a defined deflection of the rotor is determined. The position of the rotor may be calculated from the position of the minima of the amounts thus determined, taking into account the direction of rotation of the rotor. The engagement of a brake may ensure that grooving forces and machine vibrations play no role for the method to determine the rotor position.

Numerous methods are conventional by which it is possible to determine the position of the rotor of a synchronous motor in order to permit the electrical commutation of the motor, even without position information from a position-measuring instrument. Many of these methods are based on complicated measurements of the inductances of the primary-circuit coils or the measurement and evaluation of the electromotive counterforce. Such methods make it possible to operate a synchronous motor completely without a position-measuring instrument.
If for the start-up or when putting the synchronous motor into operation, the desire is merely to determine the rotor position, for instance, to determine an offset between the position-measuring instrument and the rotor, or to operate the motor to a reference point, then simpler methods are sufficient for determining the rotor position. Of importance for the operation of a synchronous motor may be actually the position of the vector of the magnetic moment of the rotor, but in simplified terms, the position of the rotor is spoken of in the following.
European Published Patent Application No. 1 085 650 describes a method, according to which initially a first motor phase is energized. Based on the resulting movement direction of the rotor, it is possible to electrically pin down the rotor position to an angular range of 180°. If a second phase which is situated centrally in this range is then energized, the rotor position can be electrically pinned down to an angular range of 90° based on the resulting direction of rotation of the rotor. With each further step, this range is halved, so that the method can be aborted when the desired exactitude has been achieved. A disadvantage in this method, however, is that relatively large movements of the rotor must be brought about before the resulting direction of rotation can be unequivocally detected with the aid of a position-measuring instrument. If these movements are selected to be too small, then grooving forces and machine vibrations can lead to a false result. The rotor position is then no longer correctly detected. However, larger movements are problematic and are not allowed in all cases, for instance, when a synchronous motor is driving a tool that is already engaged with a workpiece. Another disadvantage of this method is that the current necessary for generating a movement of the rotor becomes increasingly greater, the narrower the angular range becomes. Namely, if the magnetic field generated by the current vector is already nearly parallel to the rotor, then, given a constant current, the torque generated becomes increasingly smaller. The accuracy of the method is thus limited by the maximum possible current.

Method for determining the rotor position of a synchronous motor


There is provided a light-emitting element having a semiconductor film which includes a p-type current-spreading layer of GaInP or GaP; a first p-clad of AlInP; a second p-clad of AlGaInP; an active layer including of GaInP or AlGaInP; a first n-clad having a carrier density of 1×1018 cm−3 to 5×1018 cm−3; a second n-clad having a carrier density of 1×1018 cm−3 to 5×1018 cm−3; wherein the thickness proportion of the first p-clad in an entire p-clad, is 50% to 80%; the thickness of an entire n-clad is equal to or greater than 2 μm; the thickness proportion of the first n-clad in the entire n-clad is equal to or greater than 80%; and the thickness of the second n-clad is equal to or greater than 100 nm.

1. Technical Field
The present invention relates to light-emitting elements such as a light-emitting diode (LED).
2. Description of the Related Art
An AlGaInP-based LED has a layered structure in which, e.g., an n-clad layer, an active layer, and a p-clad layer made from AlGaInP are layered on an n-type GaAs substrate; a p-type current-spreading layer made from GaP is formed on the p-clad layer if required; and an electrode is formed on a surface of each of the GaAs substrate and the current-spreading layer. The n-clad layer and the p-clad layer have the composition ratio of Al and Ga adjusted so that the bandgap is greater than that of the active layer, and form a so-called double heterostructure.
Meanwhile, there has been proposed a structure in which, in order to make it possible to increase the brightness of the LED and allow the LED to be driven using a large current, the GaAs substrate used for crystal growth for a semiconductor film is removed, and an Si substrate is bonded onto the semiconductor film interposed by a light-reflecting layer. An Si substrate has a thermal conductivity that is higher than that of a GaAs substrate, which results in an improvement in heat-radiating performance, making it possible for the LED to be driven with a large current.
There are techniques disclosed in, for example, JP-A 2008-053425 (also referred to hereafter as Patent Reference 1) and JP-A 2010-50318 (also referred to hereafter as Patent Reference 2).

Semiconductor light-emitting element and method for manufacturing semiconductor light-emitting element


A deposition system that mitigates feathering in a directly deposited pattern of organic material is disclosed. Deposition systems in accordance with the present disclosure include an evaporation source, an electrically conductive shadow mask, and an electrically conductive field plate. The source imparts a negative charge on vaporized organic molecules as they are emitted toward a target substrate. The source and substrate are biased to produce an electric field having field lines that extend normally between them. The shadow mask and field plate are located between the source and substrate and each functions as an electrostatic lens that directs the charged vapor molecules toward propagation directions aligned with the field lines as the charged vapor molecules approach and pass through them. As a result, the charged vapor molecules pass through the shadow mask to the substrate along directions that are substantially normal to the substrate surface, thereby mitigating feathering in the deposited material pattern.

Semiconductor fabrication requires the formation of one or more patterned layers of material on the surface of a substrate. The most common approach for forming a material pattern is to deposit a full-surface layer of the material over the entire surface of the substrate and then remove the material everywhere except where it is desired. This is commonly referred to as "subtractive patterning."
Unwanted material is removed in a multi-step process in which a layer of photoresist is formed over the material layer and illuminated with a pattern of light that is based on the desired material pattern. After it has been exposed, the photoresist covering the unwanted material is dissolved in a strongly basic developer solution, which leaves behind a photoresist mask that covers the material to remain on the substrate. An etchant is then used to remove the exposed material, thus patterning the material pattern as desired. Afterward, the photoresist mask must be removed and the substrate must be thoroughly cleaned to ensure no residue of photoresist or etch product remains on any of its surfaces.
During a subtractive patterning process, everything on the substrate (i.e., any previously defined structures and materials, etc.) is exposed to harsh chemicals, including the photoresist developer solution, the etchant used to pattern the material layer, and the chemicals used to clean the substrate. Unfortunately, many materials, such as organic and biological materials, cannot survive exposure to one or more of these chemicals. As a result, subtractive patterning cannot be used for such "sensitive materials" or to pattern any material layer formed subsequent to deposition of a sensitive material on a substrate. For such operations, therefore, a direct patterning process must be used.
A direct patterning process forms a desired pattern of material as it is deposited, thereby avoiding the need for post-deposition treatments and the harsh chemicals they normally involve. One such direct-patterning process is shadow-mask deposition, which is analogous to stencil-based printing techniques, such as stencil painting, silk screen printing, and the like.
A shadow mask used in semiconductor fabrication often includes a thin layer of structural material having a pattern of apertures (i.e., openings) that matches the pattern desired for the deposited material. During shadow-mask deposition, vapor molecules of the material is generated such that they flow from a source toward the substrate surface. The vapor molecules can be generated via any of a variety of processes, such as thermal evaporation, sputtering, and the like. The shadow mask is positioned just in front of (but typically not in contact with) the substrate surface. When the flow of material reaches the shadow mask, the passage of material to the substrate is blocked everywhere except at the apertures. As a result, the material layer is directly patterned during its deposition on the substrate and no additional post-deposition processing is required.
Historically, shadow-mask deposition has been used in semiconductor fabrication to define patterns of relatively large (>50 micron) features, such as wire-bond pads, etc. A typical shadow mask used in such applications is a thin, patterned metal layer held in an annular frame. While the minimum feature size and minimum separation between apertures for such shadow masks is quite large (typically greater than several tens of microns), such shadow masks are perfectly suitable for defining large-feature-size, sparse patterns of material like wire-bond pad patterns.
More recently, it has become desirable to employ shadow-mask deposition in the formation of electronic devices based on organic materials, such as organic light-emitting diodes (OLED), active-matrix OLED displays, organic solar cells, biological-material-based sensors, and the like. In many cases, much higher resolution and pattern density is required than can be achieved with a conventional metal-based shadow mask. As a result, high-performance shadow masks based on thin dielectric or semiconductor layers have been developed that enable feature sizes and pattern densities that are less than or equal to ten microns.
Such high-performance shadow masks typically have a very thin (<1 micron) layer of structural material (e.g., silicon nitride, silicon, etc.) disposed on an annular frame formed from a semiconductor or glass handle substrate. The apertures are formed in the thin structural layer, after which the center portion of the handle substrate is removed, leaving the central region of the structural layer as a patterned edge-supported membrane.
Theoretically, during shadow-mask deposition, material deposits only on the surface of the substrate in those regions located directly behind the apertures. In practice, however, as the vapor of the material travels from the source to the shadow mask, many vapor molecules propagate along directions that are not perfectly normal to the shadow mask and substrate. As a result, some molecules continue to travel laterally after passing through the shadow mask such that the resultant patterned regions extend beyond the edges of the apertures. The magnitude of this lateral spreading of the features (referred to as "feathering") is a function of the separation distance between the substrate surface and the shadow mask, which is preferably very small—a few microns at most, as well as the orientation of the source relative to the center of the shadow mask.
While feathering is not a critical issue when forming large, widely spaced features (e.g., wire-bond pads, etc.), it can be highly problematic when forming small-feature, highly dense patterns. For example, feathering can result in electrical shorts between adjacent electrical components, color mixing between different pixels or sub-pixels in an OLED display, and the like. In fact, feathering has been a limiting factor for the minimum feature size and pattern density attainable using shadow-mask deposition.
To improve the fidelity between the shadow-mask pattern and the material pattern realized on a substrate, collimators have been developed in the prior art. A collimator is a relatively thick plate containing an arrangement of narrow through-holes. The through holes are designed to enable the passage of only vaporized atoms traveling along directions that are nearly normal to the surface of the substrate. As a result, the vaporized atoms that pass through the shadow mask apertures have little or no lateral component to their propagation direction and, therefore, feathering is reduced. Unfortunately, the inclusion of a collimator leads to material waste and longer process times. Furthermore, even with the use of collimation, the problem of feathering remains severe for deposition systems having long substrate-to-source distances.
The need for a practical direct-deposition approach suitable for defining high-resolution material layers remains, as yet, unmet in the prior art.

Apparatus and method for direct patterning of an organic material using an electrostatic mask


A method is provided for determining the integrity of a domain defined in a network. The method includes processes and systems to facilitate the discovery a conceptual ring topology of the domain in the network, and the determination of the integrity of the domain based on the conceptual ring topology that was discovered.

Many Metropolitan Area Networks (MANs) and some Local Area Networks (LANs) have a ring topology, such as a bridged, layer-2 network like the Ethernet. A problem with bus and ring networks like the Ethernet is the possibility of a single point of failure causing the system to breakdown. A common solution is to design the network with redundant segments and loops so that there is more than one route to each node in an approach that is similar to that employed in a Synchronous Optical NETwork (SONET), a layer-1 technology that was developed in the mid-1980s for the public telephone network and adopted by the American National Standards Institute (ANSI) as a standard for fiber optic networks. Redundancy and loops can, however, present another problem in which a broadcast packet or an unknown unicast packet results in a broadcast storm where each node receives and rebroadcasts the packet causing potentially severe network congestion.
One way of preventing broadcast storms and other unwanted side effects of looping is to use the Spanning Tree Protocol (STP), which has been standardized in the 802.1D specification by the Institute of Electrical and Electronic Engineers (IEEE Std. 802.1D-1998, IEEE Standard for Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Common specifications). With STP, the bridges in the network dynamically calculate an optimum subset of the topology that is loop-free and allows a path to each node. Alternate paths are blocked and unblocked as necessary to keep the routes of communication open when a fault occurs.
Another way of preventing broadcast storms and other unwanted side effects of looping is to use the Ethernet Automatic Protection Switching (EAPS) protocol, described in an informational Request For Comment (RFC) 3619 in October of 2003 as well as in U.S. Pat. Nos. 6,766,482 and 7,003,705, assigned to Extreme Networks, Inc., of Santa Clara, Calif., the assignee of the present application. Among other advantages, EAPS offers improved recovery times over STP, and provides LANS and MANS having a ring topology with resilience comparable to that provided by SONET rings at lower cost and with fewer constraints.
Regardless of whether STP or EAPS is used to prevent loops in a layer-2 network having a ring topology, it is sometimes difficult to insure that they are deployed correctly. For example, among other uses, the EAPS protocol is used to define a protection domain, referred to as an EAPS domain, using a control Virtual Local Area Network (control VLAN) on a single Ethernet ring. Because the configuration of a network in which EAPS is deployed may change, the integrity of an EAPS domain may be broken. It is also possible that the EAPS domain may not have been correctly defined. From a network management point of view, it may be necessary to periodically review EAPS domains to insure their proper operation.


More than 90% of mutations found in the p53 protein produce a conformational change in p53 which results in the exposure of an epitope, which is otherwise hidden in the hydrophobic core of the molecule. A single chain antibody (scFv) which specifically recognizes this common mutant epitope in mutant p53 but not in wild type p53 is disclosed. Also described are a DNA molecule encoding the scFv, pharmaceutical compositions comprising the antibody and methods of treatment using the pharmaceutical compositions.

The following references are referenced in the specification and may be relevant to understanding the invention:    1. Gamble, J. and Milner, J. (1988). Evidence that immunological variants of p53 represent alternative protein conformations. Virology, 162, 452-458.    2. Harlow, E., Crawford, L. V., Pim, D. C. and Williamson, N. H. (1981). Monoclonal antibodies specific for simian virus 40 tumor antigens. J. Virol, 39, 861-869.    3. Yewdell, J. W., Gannon, J. V. and Lane, D. P. (1986). Monoclonal antibody analysis of p53 expression in normal and transformed cells. J. Virol. 59, 444-452.    4. Milner, J., Cook, A. and Sheldon, M. (1987). A new anti-p53 monoclonal antibody, previously reported to be directed against the large T antigen of simian virus-40. Oncogene, 1, 453-455.    5. Gannon, J. V., Greaves, R., Iggo, R. and Lane, D. P. (1990). Activating mutations in p53 produce common conformation effects. A monoclonal antibody specific for the mutant form. EMBO J. 9, 1595-1602.    6. Marasco, W. A. (1995) Intracellular antibodies (intrabodies) as research reagents and therapeutic molecules for gene therapy. Immunotechnology, 1, 1-19.    7. Stephen. C. W. and Lane, D. P. (1992). Mutant conformation of p53 precise epitope mapping using a filamentous phage epitope library. J Mol Biol. 225, 577-583.    8. Jannot. C. B. and Hynes, N. E. (1997). Biochem. Biophys. Res. Commun., 230, 242-246.    9. Cohen, P. A., Mani, J. C. and Lane, D. P. (1998). Characterization of a new intrabody directed against the N-terminal region of human p53. Oncogene, 17, 2445-2456.
The p53 gene encodes a protein which is 53 kD in size (hence the name). The p53 protein is situated in the nexus of intermingled pathways controlling cell proliferation, cell survival and differentiation. It can sense and integrate various external and internal stimuli, such as DNA damage, hypoxia, oxidative stress, deregulated oncogene expression and ribonucleotide depletion. In response to these stimuli, it may trigger cell cycle arrest, apoptosis, senescence, differentiation or antiangiogenesis. It appears that the p53 protein is involved in regulation of critical growth controlling checkpoints. It is capable of exercising a tumor suppressor function by preventing cells, that are in unfavorable environmental conditions or are carrying damaged DNA, from entering a cell cycle.
Mutations within the p53 gene have been found in more than 50% of all human cancers, rendering it the most frequently mutated single gene in human cancer known so far. Most of the mutations in the p53 gene discovered in cancers are of a missense type. They cause not just abrogation of the tumor suppressor function of wild-type p53, but often actively contribute to the tumor transformation function of mutant p53. Inactivation of p53 is one of the most common molecular events in cancer development.
As mentioned above, the p53 protein, which is both a regulator for cell proliferation and a suppressor of tumor development, can prevent the development of cancer by blocking the division of cells which have sustained DNA damage, or by triggering apoptosis. It has been proposed that the effect of mutant p53 on tumor progression is due to a dominant negative interaction of the wild type and mutant proteins. Thus, wild-type and mutant p53 proteins are respectively capable of contrasting suppressor and promoter effects on tumor development.
The ability of p53 to act both as a suppressor and a promoter of tumor development may reflect the ability of the protein to adopt different conformations. Mitogenic stimulation of primary T cells induces a change in the immunoreactivity of p53 and this may be due to a change in the tertiary structure of the p53 protein. To ascertain whether the 'mutant' conformation of wild-type p53 has physiological relevance, attempts have been made to associate it with a biochemical activity. Conformation-specific monoclonal antibodies, previously shown to discriminate between wild-type and mutant p53 proteins, have been used to demonstrate structural changes in wild-type p53 following sequence-specific binding to DNA (1). These studies suggested that wild-type p53 can physiologically adopt distinct conformations, which determine its DNA binding activity. Mutations that render p53 oncogenic may lock p53 into one of the few conformational states it physiologically adopts, rather than distort its tertiary structure.
Two important cellular factors appear necessary for this conversion: (1) binding of an 'activating' polypeptide that causes neutralization of the C-terminal negative regulatory domain, and (2) a highly reduced environment which can maintain p53 in an activated state. Given the clear association between the DNA binding activity and tumor suppressor functions of p53, these results imply that in many tumor cells there are high levels of mutant p53 that can potentially be activated to restore significant wild type function.
A variety of monoclonal antibodies have been prepared against various epitopes of p53.
A panel of anti-p53 mouse monoclonal antibodies has been used to characterize the immunoreactivities of the native p53-Ala35 and the mutant p53-Val 35 translated under various conditions. Two monoclonal antibodies, PAb421 and PAb248, were able to recognize discrete denaturation-stable epitopes on the p53-polypeptide (2,3). These antibodies immunoprecipitated both p53-Ala35 and p53-Val 35 translated at 30° C. and 37° C., and were also able to immunoprecipitate p53 from a variety of murine cell lines (4).
Three additional monoclonal antibodies, PAb246, PAb 1620 and PAb240, were found to detect conformational changes in the p53 protein (5). Molecules in the mutant conformation are distinguished from wild-type molecules, inter alia, by the appearance of a new, normally cryptic epitope recognized by Pab240. This epitope was localized to residues 213 to 217 of the p53 protein and has the sequence RHSVV, preceded by F in human and mouse p53 (7). More than 90% of mutations found in p53 produce a conformational change in the p53 protein which results in the exposure of this epitope, which is otherwise hidden in the hydrophobic core of the molecule. This epitope will be referred to hereinafter as the common mutant epitope of p53.
Recent advances in antibody engineering have allowed the genes encoding antibodies to be manipulated, so that antigen binding molecules can be expressed within mammalian cells in a controlled way (6). Application of gene technologies to antibody engineering has enabled the synthesis of single-chain fragment variable (scFv) antibodies that combine within a single polypeptide chain the light and heavy chain variable domains of an antibody molecule covalently joined by a predesigned peptide linker. The resultant scFv gene can be expressed in bacterial expression systems such as E. coli. Bundled in the "gene display package" single-chain antibodies displayed at the surface of filamentous phages of the M13 family provided the possibility to create antibody libraries both from various living sources and products of diversification of a single scFv molecule. Antibodies with the desired specificity can be isolated from such libraries employing effective selection techniques (biopanning) in which the antigen is immobilized on a solid support.
The ability to create scFv antibodies, when combined with their stable expression in precise intracellular locations in mammalian cells, has enabled the creation of a powerful new family of antibody molecules for basic research or gene therapy. These intracellular antibodies (intrabodies) can be used to modulate cellular physiology and metabolism through a variety of mechanisms, including the blocking, stabilizing or mimicking of protein-protein interactions, by altering enzyme function, or by diverting proteins from their usual intracellular compartments. Intrabodies can be directed to the relevant cellular compartments by modifying the genes that encode them to specify N- or C-terminal polypeptide extensions for providing intracellular-trafficking signals. This approach has been described for a number of different antigens, including several HIV proteins.
Several scFv antibodies against p53 have been previously described. The scFv-421 antibody recognizes a C-terminal epitope of the protein (8). When expressed in vitro in the cytoplasm or in the nucleus of COS-1 cells, it was found to be non-functional and prone to rapid degradation. An important determinant of correct antibody folding is the formation of intra-chain disulfide bonds in the variable regions; possibly the reducing environment of the cytosol may lead to a decrease in the stability of the scFv (9). Nevertheless, some scFv antibodies have been expressed in the cytoplasm and shown to have biological effects, indicating that other features, such as the primary sequence of the antibody and/or its specific cellular location may be important for their proper function.
The scFv DO-i antibody was found to recognize an N-terminal epitope of human p53 (9). The DO-1 scFv was targeted to the cytoplasm and to the nucleus of mammalian cells. Interestingly, insertion of the CK domain into scFv to create a scFvCK fusion protein, led to a dramatic increase in the level of intracellular expression. However, in other studies in which CK fusions to scFv were made, the effects on stability and expression were much less marked. It is clear that each scFv is a particular and individual case (9).

Single chain antibody against mutant p53