An islanding detection and protection method of a parallel-type power converter is proposed, which performs perturbation to a power system to detect the frequency of the system voltage and the variation of the magnitude of the negative-sequence voltage as the basis for deciding the occurrence of an islanding operation. When the system operates normally, the frequency or phase and magnitude of the system voltage and the magnitude of the negative-sequence voltage won't be affected by the perturbation. On the other hand, if an islanding operation occurs, this perturbation will cause an apparent drift of the frequency or phase and magnitude of the system voltage and the magnitude of the negative-sequence voltage. Through detection of this apparent drift, the perturbation can be amplified by means of positive feedback to quickly detect the islanding operation phenomenon and trigger the protection mechanism.

1. Field of the Invention
The present invention relates to an islanding detection and protection method and, more particularly, to a method of performing perturbation to a power system to quickly detect islanding operation of the power system and trigger the protection mechanism for the power system.
2. Description of Related Art
Liberation of the power industry is the future trend of power development. Small distributed energy or renewable energy generating equipment such as cogeneration systems, solar energy generating systems and wind energy generating systems are usually incorporated into the public power system for parallel operation. When the public power system trips due to an abnormality, if the distributed energy generating equipment cannot detect that the public power system has tripped and still provides power, a stand-alone state will arise to form an islanding zone, which is called an islanding operation.
The key factor is that each distributed energy generating equipment usually belongs to a private owner but is not directly controlled by the power company. Therefore, when the public power system breaks off, if each distributed energy generating equipment cannot detect this situation and still provides power, the voltage and frequency will be unstable which leads to the damaging of electric equipment or even causes electric shock hazards to power maintenance men. Furthermore, when the public power system is restored, the distributed energy generating equipment or electric equipment may be damaged due to asynchronization.
Therefore, there are many documents concerning detection of an islanding operations, many of which are base on detection of the magnitude and frequency of voltage at the point of the common coupling (PCC) terminal of the power system. As shown in FIG. 1, once the voltage or frequency exceeds (beyond or below) the operating window, the distributed power system is disconnected from the public power system to avoid an islanding operation; or the voltage phase of the power system is detected momentarily to detect whether there is a voltage phase jump, representing the occurrence of an islanding operation.
The above methods of detecting voltage, frequency or phase jump are usually restricted by the form of load, and may be unable to detect the state of an islanding operation due to the load state. This is called a non-detection zone (NDZ).
Another method is to detect the total harmonic distortion (THD) of the PCC. When this THD exceeds a preset level, it represents the occurrence of an islanding operation. This method is based on the nonlinear hysteresis of the B-H curve of a transformer. When the power system operates normally, this nonlinear current is provided by the power system and does not affect the voltage harmonics. When the power system trips, this nonlinear current is provided by the distributed power system. At this time, high-order harmonics of voltage will be generated. Therefore, the THD can be used as a base to determine whether an islanding operation is occuring or not.
However, it is difficult to obtain the magnitude of the THD to determine whether an islanding operation has occurred or not. A method of using the power line carrier for direct communication to determine whether islanding operation occurs can also be used. However, it is necessary to simultaneously install communication equipment at both ends, hence causing additional expenses. The above methods are commonly called the passive islanding detection method.
Another important detection method is called the active anti-islanding detection method. For instance, in the detection technique developed by the Sandia National Lab, the frequency or magnitude of the output current of a power regulator is adjusted to perturb the power system, and the frequency or magnitude of the voltage of the power system is detected. When there is any change in the frequency or magnitude of the voltage of the power system, the frequency or magnitude of the output current of the power regulator is varied by means of positive feedback so as to accomplish the object of detecting an islanding operation.
If the power system operates normally, this small component won't affect the magnitude of the voltage. When the power system trips, the produced voltage change will enlarge the voltage drift through positive feedback. Therefore, whether an islanding operation occurs or not can be determined according to whether the voltage exceeds the operating window or not.
Using solar power regulators as an example, when a plurality of solar power regulators is parallel connected, the influences to the voltage drift may easily cancel out one another because a certain one has a smaller sunlight illumination while another has a larger sunlight illumination. Moreover, general solar power regulators operate near the load point with maximum power, but cannot provide a larger output current to perturb the voltage of the power system. Therefore, the phenomenon of an islanding operation is difficult to detect.
Another islanding detection method, called Sandia Frequency Shift (SFS), developed by the Sandia National Lab makes use of a frequency positive-feedback system. As shown in FIG. 2, the current frequency fn2 (E) is a curve equation that describes the relation between an error and an increment/decrement of the frequency.
When the power system operates normally, the change of the current frequency won't cause any drift in the voltage of the power system. If the power system trips, the voltage frequency will drift due to the change in the current frequency. Through positive feedback, the frequency of the output current will increase to exceed the normal operating window (too large or too small). An islanding operation can thus be detected.
With passive components (an inductor, a capacitor and a resistor) as the load, the lag angle is:arg tan(R−1+j ωc−j( ωL)−1)  (1)
From (1), if the operating frequency point is at the resonance point of the inductor and the capacitor, the error angle will be zero, and there is no drift in the frequency of the output current, hence not being able to detect an islanding operation. Furthermore, the detection time is too long to meet standards.
As shown in FIG. 3, U.S. Pat. No. 5,493,485 discloses a protection device for stopping operation of an inverter, which makes use of such factors as current and voltage phase drift, frequency variation, voltage variation and THD variation to determine the phase drift between the output current and voltage. Moreover, the equation describing the relation between frequency and phase difference can be among various kinds of nonlinear functions. Because the decision algorithm is complex, this system is hard to realize.
Additionally, there are some methods making use of the sliding mode of frequency and phase difference to adjust the phase difference between the injected current and the voltage when any drift in the voltage frequency is detected, thereby making the operation point reach another stable point along this sliding curve. This stable point lies outside the normal operating window. This sliding curve is shown in FIG. 4. Similarly, if the operating frequency point is at the resonance point of the inductor and the capacitor, the error angle will be zero, and there is no drift in the frequency of the output current, hence not being able to detect an islanding operation. Furthermore, the detection time is too long to meet standards.
Accordingly, the present invention aims to propose an islanding detection and protection method and system to solve the above problems in the prior art. In the present invention, the magnitude of error is converted to an error differential directional component (S value) and a counter (weighting factor Ws). The weighting factor Ws is used to adjust the variation of a negative-sequence current of a distributed power system to avoid the problem that the adjustment diminishes with decrease of the feedback error, thereby accurately and quickly detecting the occurrence of an islanding operation.

Islanding detection and protection method

Industrial Technology Research Institute


To ensure satisfactory visibility even when the light emitting area of the light emitting element for displaying the operation state is small. At least one of a light projector or a light receiver is provided with a display portion for displaying an operation state of the multi-optical axis photoelectric sensor at a side position in the vicinity of the light projecting portion or the light receiving portion of the front surface of the housing. The display portion includes a plurality of light emitting elements arranged in a line in the longitudinal direction while facing the front surface of the housing in the housing, and a plurality of light guiding bodies for guiding the light emitted by each of light emitting elements to the front surface of the housing. Each of light guiding bodies is arranged with the incident end face facing the light emitting element and the exit end face facing the front surface of the housing. Each of light guiding bodies includes, in a light guiding path for guiding the light flux entered from the incident end face to the exit end face, at least two reflection surfaces for diffusing some or all of the light flux in a width direction of the housing by sequentially changing an advancing path of the light.

1. Technical Field
The present invention relates to multi-optical axis photoelectric sensors having a light projector and a light receiver, the light projector being equipped with a plurality of light projecting elements arranged in a line inside a housing, and the light receiver being equipped with a plurality of light receiving elements for receiving light from the light projecting elements arranged in a line in a longitudinal direction of the housing, the light projector and the light receiver being disposed so that light from each of the light projecting elements is projected to the corresponding each of the light receiving elements to thereby constitute multiple light axis, and in particular, to a multi-optical axis photoelectric sensor having a display portion for displaying an operation state of the multi-optical axis photoelectric sensor on the front surface of the housing.
2. Related Art
As shown in FIG. 10, a typical multi-optical axis electronic sensor is configured by a light projector 100 and a light receiver 200, the light projector 100 being equipped with a plurality of light projecting elements 102 arranged in a line in a longitudinal direction inside a housing 101 having a rectangular shape, and the light receiver 200 being equipped with light receiving elements 202 of the same number as the light projecting elements 102 arranged in a line in a longitudinal direction inside a housing 201 having the same rectangular shape. The light projector 100 and the light receiver 200 are disposed at an adequate distance so that light from each of the light projecting elements 102 is projected to the corresponding each of the light receiving elements 202 to thereby constitute multiple light axis. Optical axes L connecting the respective light projecting elements 102 and the respective light receiving elements 202 are parallel to each other, and form a two-dimensional object detecting area for detecting the presence of an object. The light projector 100 and the light receiver 200 cause each of the light projecting elements 102 of the light projector 100 to sequentially emit light, and each of the light receiving elements 202 of the light receiver 200 corresponding to each of the light projecting elements 102 to perform the light receiving operation, respectively. The light shielding state of each of the optical axes L is detected by turns based on the light receiving quantity of the light at each of the light receiving elements 202, and whether or not an object is in the object detecting area is determined.
At least one (both in the illustrated example) of the light projector 100 and the light receiver 200 incorporates a plurality of light emitting elements 103 for displaying an operation state of the multi-optical axis photoelectric sensor (see. e.g., Japanese Unexamined Patent Publication No. 2008-180649). A display region by the light emitting elements 103 is generally arranged on the front surfaces (surfaces opposing each other) of the housings 101, 201 in relation to attaching a cover (not shown) for reinforcement or a protective cover (not shown) for preventing breakage of a front surface cover 112 (shown in FIG. 11), to be described later, to the side surface and the back surface of the housings 101, 201 of the light projector 100 and the light receiver 200, where operation abnormality of the multi-optical axis photoelectric sensor, the state (light receiving level) of alignment between the light projector 100 and the light receiver 200, and the like are displayed by a lighted state and a non-lighted state of the light emitting element 103 in addition to the presence of power supply and the presence of object detection.
FIG. 11 shows an internal structure of the light projector 100. The basic configuration of the internal structure of the light receiver 200 is common with the light projector 100, and thus the illustration and the description thereof will not be given here.
A circuit substrate 104 having the plurality of light projecting elements 102 mounted in a line at the surface, and a plurality of holders 106 made of synthetic resin holding a light projecting lens 105 for collecting the light emitted by each of the light projecting elements 102 are arranged and housed in the housing 101 of the light projector 100.
Each of the holders 106 has both ends supported by opposing side wall portions of the housing 101, and has a holding hole 109 passed through at the middle for holding the light projecting lens 105 and the light projecting element 102 in a state facing each other. The housing 101 is configured by a case main body 101 having the front surface opened, and a transparent front surface cover 110 for blocking the opening at the front surface of the case main body 111.
The plurality of light emitting elements 103 are respectively mounted at the side positions of the line of light projecting elements 102 on the circuit substrate 104 so that the light emitting surface faces the front surface cover 110, and a columnar light guiding body 108 for guiding the light emitted from each of the light emitting elements 103 to the front surface cover 110 is held by each of the holders 106. Each of the light guiding bodies 108 has an incident end face 108a for entering the light inside facing the light emitting surface of the light emitting element 103, and an exit end face 108b for exiting the incident light to the outside facing the front surface cover 110. The light flux emitted from the light emitting element 103 enters into the light guiding body 108 from the incident end face 108a, straightly advances through the light guiding body 108, and exits from the exit end face 108b.
The light emitted from each of the light projecting elements 102 is projected towards the light receiver 200 from a central portion of the width of the front surface cover 110, and the light emitted from each of the light emitting elements 103 is guided to the side position in the width direction with respect to the light projecting portion at the central portion of the width.

Multi-optical axis photoelectric sensor with reflection surfaces


A printing device for dispending material on a heated substrate is provided. The device may include a printing head having one or more nozzles and a heat shield that partially masks a side of the printing head that faces the heated substrate when printing so as to reduce heat transfer from the substrate to the printing head. The shield includes a slot aligned with the one or more nozzles to enable passage of material from the one or more nozzles to the heated substrate.

Non-contact deposition printing systems, such as inkjet printing systems, are being increasingly utilized in the manufacture of printable electronics. For example, such systems may be used to metallize layers by depositing an electrically conductive material (ink) on various substrates for applications such as radio-frequency identification (RFID), organic light-emitting diodes (OLED), photovoltaic (PV) solar cells, and other printable electronics products.
In some applications, for example, metallization of silicon wafers during production of solar cells, it is desirable to deposit the material on a hot substrate surface. The hot substrate may undesirably heat the nozzle plate and may adversely affect the quality of the printing. Additionally, fumes evaporating from the liquid material dispensed onto the heated substrate may also adversely affect the operation of the printing head as the fumes may condense onto the nozzle plate in the form of droplets.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn accurately or to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the drawings to indicate corresponding or analogous elements. Moreover, some of the blocks depicted in the drawings may be combined into a single function.

Method and device for printing on heated substrates


A device provides a user interface that includes a list of push-to-talk contacts, and receives, via the user interface, a gesture indicating a request to establish a push-to-talk call with a particular contact in the list of push-to-talk contacts. The device initiates the push-to-talk call with another device associated with the particular contact, and the push-to-talk call is initiated with the other device based on the gesture and directly from within the user interface. The device provides for display a visual indicator associated with the push-to-talk call.

A push-to-talk (PTT) service provides direct one-to-one and/or one-to-many audio communication. PTT may include a mechanism that provides instantaneous communication between parties, and that utilizes a button to switch user equipment (UE) from a voice transmission mode to a voice reception mode. The operation of UEs in this manner may be similar to how walkie talkies operate. A PTT service may switch a UE from a full duplex mode, where both parties may hear each other simultaneously, to a half duplex mode, where a single party may speak at one time. Multiple parties or a group conversation may also be provided by a PTT service. Availabilities of parties may be checked before a call with the help of a presence function.


Some examples relate generally to computer architecture software for data classification and information security and, in some more particular aspects, to verifying audit events in a file system.

The sheer volume and complexity of data that is collected, analyzed and stored is increasing rapidly over time. The computer infrastructure used to handle this data is also becoming more complex, with more processing power and more portability. As a result, data management and storage is becoming increasingly important. Significant aspects of these processes include access to reliable data backup and storage, and fast data recovery in cases of failure. Other aspects include data portability across locations and platforms.
At the same time, unauthorized access to systems and ransomware have become major cyber-security threats in recent times. In this regard, data security regulations such as those mandated in the General Data Protection Regulation 2016/679 (GDPR) place strict notification obligations on data holders. The GDPR is a regulation in EU law relating to data protection and privacy for all individuals within the European Union and the European Economic Area. The regulation also addresses the export of personal data outside the EU and EEA areas, such as into the United States. Under the GDPR regulation, if there is a data breach the data holder is required to notify all affected users very quickly. Thus, the rapid detection of ransomware or unauthorized access to data is critical.

Data correlation using file object cache


A liquid treatment apparatus includes a supply chamber for receiving a fluid, a discharge chamber for discharging the fluid, and a cavitation generating chamber extending from the supply chamber to the discharge chamber. The cavitation generating chamber is operable to generate cavitation bubbles. A method of treating a liquid comprises directing a fluid from a supply chamber into a cavitation generating chamber by constricting the fluid through an orifice, wherein the orifice has a cross dimension that is substantially less than a cross dimension of the supply chamber, such that a fluid jet is formed. The method further includes allowing the fluid jet to expand downstream of the orifice such that the velocity of the fluid is reduced so that the jet axial velocity head at the chamber outlet is less than the difference between the static pressure within the discharge chamber and the vapor pressure of the fluid. The method also includes discharging the fluid into a discharge chamber via a chamber outlet.

Cavitation is the formation and implosion or collapse of cavities, or bubbles, in a liquid that are the consequence of forces acting upon the liquid. Cavitation usually occurs when the local pressure within a liquid is reduced to less than the vapor pressure of the liquid.
Many industrial processes rely on various chemical reactions in a liquid medium to achieve a certain end product. Accordingly, manufacturers and others that perform these industrial processes continually seek improvements to these processes so as to improve their efficiency and provide a cost benefit. By way of example, increasing the efficiency in chemical reactions occurring in a liquid medium may result in a decrease in processing time, which may lead to an increase in overall production and decrease in operating costs, and/or a decrease in chemical consumption in the liquid medium for achieving the desired result which may reduce operating costs. These are only exemplary and, depending on the specific application, many other benefits may be gained by improving the efficiency of various chemical reactions.
There are numerous industrial applications that may benefit from improved chemical reactions using cavitation. For example, the use of cavitation in the treatment of contaminated water, e.g., wastewater, is documented. In these cavitation methods, the goal is to generate many fine bubbles, which upon their implosion create intense, but highly localized temperatures and pressures. This energy release then causes dissolution of the water molecules and the creation of free hydroxyl radicals. The potential of these powerful radicals for the beneficial treatment of the water has been well recognized for many years. However, the inefficiencies in the known processes for generating cavitation within a liquid (e.g., ultrasonic, spinning impeller, or jet cavitation) have limited commercial acceptance of cavitation.
It should be noted that in cavitation, the process of generating bubbles is often considered secondary in importance to the subsequent process of collapsing the bubbles, since it is the collapse which produces the effecting high temperatures and pressures. More intense bubble collapse results in higher temperatures and allows more energetic bonds to be broken. This increases the ability of the cavitation process to kill microorganisms and separate particulate matter, such as breaking bonds between or within molecules. Maximum bubble collapse temperatures and pressures are achieved by maximizing bubble collapse velocities.
Preferably, in order to maximize effectiveness, bubbles collapse in rapid succession in a process referred to as cavitation cloud collapse, generating high amplitude/frequency pressure waves which can be used to generate high pressure differentials around and across the bubbles. Cavitation cloud collapse can generate pressures that are orders of magnitude higher than those produced by single bubble collapse. However, this synchronization is difficult to achieve. When an individual bubble collapses under uniform ambient pressure, the collapse rate is restrained due to the inertia of the surrounding fluid. Following collapse, a pressure wave is generated which radiates energy spherically outward from its center. The amplitude of the pressure wave is reduced as a function of the square of the distance from the center of the bubble collapse, such that the amplitude decreases relatively rapidly. If several bubbles collapse in a random manner, pressure waves generated from these collapses impact upon other bubbles in a random manner. The amplitudes of the resulting pressure waves will also vary in a random manner. Due to the random nature of these pressure waves, cavitation cloud collapse will not be initiated, and maximum bubble collapse temperatures and pressures will not be achieved. However, if a uniform, coherent, high frequency pressure wave encounters a cloud of bubbles, then the increase in differential pressure applied to the bubbles will tend to cause the bubbles to collapse in the direction of the pressure wave, such that the energy from the bubble collapses will be added to the original pressure wave, increasing its amplitude. This will tend to increase the amplitude of the individual pressure pulses generated by successive bubble collapses, and will also tend to increase the frequency of these pressure pulses.
When uncontrolled, hydrodynamic cavitation can be very damaging. Studies have shown that cloud collapse can be more violent than collapse of individual bubbles. Typically, the damage is most severe on solid surfaces close to the location of the cloud collapse. Shock waves formed by clouds of cavitation bubbles that implode on or near a metal surface can cause cyclic stress through repeated implosion, resulting in surface fatigue of the metal. As a result, leaks can eventually form in the walls of a device in which cloud cavitation occurs. Therefore, the implosion of cavitation bubble clouds must be controlled in order to harness their energy and reduce or eliminate damage to the surrounding walls.
A wide variety of cavitation generators exist in the prior art. For example, U.S. Pat. No. 4,474,251 to Virgil E. Johnson, Jr. describes an acoustic-hydrodynamic resonator which may utilize an organ-pipe oscillator in conjunction with a Helmholtz resonator chamber to produce a pulsed liquid jet for eroding a solid surface. In one embodiment, liquid is directed through a first orifice and a jet is formed by directing the liquid through a second orifice, and the jet is pulsed by oscillating the pressure of the liquid after it exits the first orifice through hydrodynamic and acoustic interactions. Typically, a Helmholtz chamber is formed between the first and second orifices, wherein the pressure of the liquid is oscillated within the Helmholtz chamber, and a portion of the energy of the high velocity liquid is utilized to pulse the liquid. The cavitation bubble collapse occurs within the discharge stream and not within the device. The device in the '251 patent may be termed a pure fluid device since it is entirely passive and requires no outside energy supply. The energy for its operation comes only from the fluid and it depends on hydrodynamic and acoustic interactions for its operation. In addition, several hydrodynamic cavitation generators have been invented by Oleg V. Kozyuk and others. However, none of these devices adequately generate cavitation bubble cloud collapse, and in particular, capture and utilize residual pressure wave energy to enhance formation and collapse of subsequent cavitation bubble clouds.
It is therefore an object of the present invention to provide a cavitation generator which maximizes the utilization of fluid energy for cavitation bubble formation and which maximizes the temperatures and pressures generated during bubble collapse.

Pulse cavitation processor and method of using same


A fault location estimation device includes: a faulty scan chain identification unit that identifies a faulty scan chain and its fault type based on result of operation verification test; a faulty scan FF narrowing unit that compares test result of the faulty scan chain with simulation result for determining a faulty scan FF range beginning at the location of a scan FF where both results differ; and a path trace narrowing unit that references logic circuit configuration information, signal line expected value, a failure-observed scan FF, and test result of a defective circuit to extract a scan FF on the faulty scan chain, which may be reached from a failure-observed scan FF observed on a normal scan chain by tracing back a failure propagation path while performing implication procedure for an input side, and thereby further narrows the faulty scan FF range determined by the faulty scan FF narrowing unit.

An example of a prior-art fault location estimation method for estimating a fault location on a scan chain (or scan path) of a scan circuit is the fault location estimation device described in Non-Patent Document 1. This fault location estimation device tests a defective circuit, which is a logic circuit found failed in the scan chain operation verification test and recognized as having a single scan chain fault, using a particular test pattern. And, based on the obtained test result, the fault location estimation device narrows the fault range of faulty scan flip-flops (scan FFs) for identifying the fault location by the fault simulation.
First, the following describes the technical terms on a scan circuit and the scan operation with reference to FIG. 14.
FIG. 14 is a diagram showing a scan chain composed of 10 scan FFs. Index numbers are assigned to the scan FFs sequentially beginning at the scan out (Sout) terminal side. In this example, the index numbers 0-9 are assigned. In the scan operation, data flows from the scan-in (Sin) terminal to the scan-out (Sout) terminal.
In FIG. 14, the Sin side of a particular scan FF is called the upstream, and the Sout side is called the downstream. For example, in FIG. 14, there are scan FF6-FF9 in the upstream of scan FF5, and scan FF0-FF4 in the downstream. In this case, the particular scan FF itself is sometimes included in the downstream. Inputting values from the Sin terminal into the scan FFs while shifting through those scan FFs is called 'loading', and outputting values of the scan FFs from the Sout terminal is called 'unloading'.
Loading is also called scan-in or shift-in. And, unloading is also called scan-out or shift-out.
Load data and unload data are represented using the notation method in which the logic values are sequentially written beginning at the value in the scan FF nearest to the Sin terminal. For example, in the notation {00110011}, the left end represents data nearest to the Sin terminal and the right end represents the data nearest to the Sout terminal.
FIG. 15 is a diagram showing a scan circuit that includes one scan chain. The outmost solid line indicates the whole scan circuit, the dotted line within the solid line indicates the scan chain, a small square on the dotted line indicates a scan FF, the rectangular portion surrounded by the dotted line indicates a combinational circuit partitioned by the scan chain. The scan operation is performed in such a way that data is supplied to the scan FFs, beginning at the scan FF on the Sin side, to determine the state values of the scan FFs (this operation is called as the load operation) and, after that, the system clock (or capture clock) is applied to supply data to the combinational circuit (this operation is called the capture operation) and, finally, data is output from the scan FF terminal on the Sout side. By performing this operation, the internal information on the combinational circuit may be obtained. The scan operation is also called a scan test.
The fault diagnosis of a scan circuit is performed based on data obtained by the scan operation described above. Therefore, the fault diagnosis of a scan circuit requires the normal operation of the scan chain that supplies data to the combinational circuit and outputs the result. The present invention relates to a method for isolating a fault location on a scan chain when the scan chain itself is faulty.
One of the ways to confirm the normal operation of a scan chain is a scan chain operation verification test (flush test, scan check). In the scan chain operation verification test, the special patterns such as {000000} {all 0s}, {111111}(all 1s), and {00110011} are used to check the operation of the scan chain.
Next, the following describes in detail a fault location estimation device in the prior art with reference to the drawings. FIG. 16 is a block diagram showing a configuration of the fault location estimation device in the prior art.
Referring to FIG. 16, the fault location estimation device in the prior art includes an input device 1 that has a keyboard and an interface unit for interface with the external system, a data processing device 2 that operates under program control, a storage device 3 such as a hard disk or a memory in which information is stored, and an output device 4 such as a display device or a printer that is an interface unit for interface with the external system.
Referring to FIG. 16, the storage device 3 includes a logic circuit test result information storage unit 41, a faulty scan chain storage unit 42, and a faulty scan FF storage unit 43.
The logic circuit test result information storage unit 41 stores information on the logic state of the signal lines, logic state (expected value) of the signal lines when the circuit is normal, and the scan FFs in which the fail signal was detected in the test (called 'failure-observed scan FF') and, at the same time, stores information on the configuration of the logic circuit (for example, gate type, connection relation between gates, connection relation between gate and signal line, connection relation between signal lines). Here, a node refers to a part configuring the circuit (for example, gate, gate terminal, net, circuit terminal), and a failure observation node refers to a node at which the logic state can be observed (for example, external output terminal of the circuit or scan FF).
The faulty scan chain storage unit 42 stores information on a faulty scan chain and its fault type produced as a result of the analysis of the scan chain operation verification test result.
The faulty scan FF storage unit 43 stores information on the range of faulty scan FFs on a faulty scan chain.
Referring to FIG. 16, the data processing device 2 includes an initialization unit 21, a faulty scan chain identification unit 22, a faulty scan FF narrowing unit 23, and a fault simulation comparison unit 24.
The initialization unit 21 references the logic circuit test result information storage unit 41 to set the logic circuit types and the logic states of the input/output terminals and initialize the logic states of the signal lines.
The faulty scan chain identification unit 22 references the logic circuit test result information storage unit 41 to analyze the scan chain operation verification test result and records a failed scan chain (that is, faulty scan chain) and its fault type in the faulty scan chain storage unit 42.
The faulty scan FF narrowing unit 23 references the logic circuit test result information storage unit 41 and the faulty scan chain storage unit 42, compares the observed value (output value) of scan FFs on the faulty scan chain with the simulation value (expected value) based on the test result, calculates the range of scan FFs in which a fault may be present, and records the calculation result in the faulty scan FF storage unit 43.
The fault simulation comparison unit 24 references the logic circuit test result information storage unit 41, faulty scan chain storage unit 42, and faulty scan FF storage unit 43, performs the fault simulation with a fault type specified for each faulty scan FF, and outputs a scan FF and a fault type that is the best match between the simulation result and the test result.
FIG. 17 is a flowchart showing an operation of the prior-art fault location estimation device that estimates the fault location of a scan chain fault. The following describes the operation of the prior-art fault location estimation device in detail with reference to FIG. 17.
Referring to FIG. 17, the initialization unit 21 references the logic circuit test result information storage unit 41, sets the types of the logic circuits and the logic states of the input/output terminals, and initializes the logic states of the signal lines (step D1).
Next, the faulty scan chain identification unit 22 references the data stored in the logic circuit test result information storage unit 41 to perform the scan chain operation verification test, identifies the scan chain in which a failure-observed scan FF is included, collects the state value of the failure-observed scan FF of each scan chain, determines the fault type of the faulty scan chain whether the fault is a permanent fault or an undefined fault (step D2), and stores the faulty scan chain and the fault type in the faulty scan chain storage unit 42. If there are two or more faulty scan chains or if the fault type of the faulty scan chain is undefined, the diagnosis processing is terminated.
The faulty scan FF narrowing unit 23 references the data, recorded in the logic circuit test result information storage unit 41, to test a defective circuit using a pattern, in which the logic value applied to the faulty scan chain is all undefined value 'X', based on the faulty scan chain information stored in the faulty scan chain storage unit 42. The faulty scan FF narrowing unit 23 compares the observed value of the faulty scan chain, obtained as a result of the test, with the simulation value, calculates a faulty scan FF range from the location of the scan FF at which the two values are different, and records the faulty scan FF range in the faulty scan FF storage unit 43 (step D3).
FIG. 18 is a diagram showing the faulty scan FF isolation method used by the prior-art fault location estimation device. Referring to FIG. 18, the following describes the fault range isolation method for a stuck-at-1 fault as an example of permanent-fault isolation. Because a stuck-at-1 fault is a fault in which the state value is set to '1', a fault is generated if the observed value is '1' when the normal value is '0'. The sensitive bits where a fault may be generated are scan FF3 and FF6. Because the normal value of scan FF5 is '1', the stuck-at-1 fault is not activated. The comparison between the simulation value and the observed value in scan FF3 and scan FF6 indicates that scan FF3 is the normal value and scan FF6 is the fault value. This implies that the stuck-at-1 fault is present in the upstream of scan FF3 and in the down stream of scan FF6. In this case, scan FF6 is called the upstream bound (UB) and scan FF3 is called the downstream bound (LB).
To detect a transition fault and a hold time fault, the state values of the two neighboring scan FFs are considered. For example, when a slow-to-fall fault is generated, the possible location at which the slow-to-fall failure is generated in FIG. 18 is between scan FF2 and scan FF3 and between scan FF5 and scan FF6 where the value changes from 1 to 0. The observed value and the simulation value match between scan FF2 and scan FF3. On the other hand, the observed value and the simulation value do not match between scan FF5 and scan FF6 because the observed value of scan FF6 is '1', meaning that a failure is observed and that a slow-to-fall fault is generated. Therefore, the upstream bound of the slow-to-fall fault is scan FF5, and the downstream bound is scan FF2.
Finally, the fault simulation comparison unit 24 references the logic circuit test result information storage unit 41 to set the logic values of the signal lines, references the faulty scan chain storage unit 42 and the faulty scan FF storage unit 43 to set the fault type for each scan FF in the faulty scan FF range, performs the fault simulation, and outputs a scan FF, which is the best match (highest score) between the simulation result and the test result, to the output device 4 as the faulty scan FF candidate (step D4).
Now, referring to FIG. 19, the following describes how to calculate the score. To calculate the score, the following four elements shown in FIG. 19 are used.    TFSF: Number of scan FFs that failed test by a tester and failed fault simulation    TFSP: Number of scan FFs that failed test by a tester and passed fault simulation    TPSF: Number of scan FFs that passed test by a tester and failed fault simulation    TPSP: Number of scan FFs that passed test by a tester and passed fault simulationThe calculation expression shown in FIG. 19 is a general calculation expression for calculating the score. When the result values of the fault simulation and the observed value of the tester completely match, the relation TFSP=TPSF=0 is satisfied and the score of the calculation expression in FIG. 19 becomes the maximum value of 100.
The prior-art fault location estimation device compares the fault-affected observed value generated at unload time with the simulation value and calculates the fault range. However, when an undefined fault is generated, a fault is more likely to occur randomly whether the value is '0' or '1'. Therefore, the most downstream failure that is observed cannot be determined as the first failure with the result that the faulty scan FF range cannot be identified.
In addition, if the same logic value as that of a fault value is continuously observed on the downstream side beginning at a faulty scan FF, the isolation range becomes wide. In this case, the problem is that the need to perform fault simulation for a wide range of faulty scan FFs prevents the diagnosis from being terminated within a practical time.
FIG. 20 is a diagram showing an example of the actual operation of the faulty scan FF narrowing unit 23 in the prior-art fault location estimation device. Referring to FIG. 20, all observed value of the scan FFs in the scan chain on the upstream side of the faulty scan FF, indicated by the dotted arrow, are the same as the fault value '1'. As a result, the prior-art fault location estimation device cannot limit the faulty scan FF range, because those scan FFs are also considered as equivalent faulty scan FF candidates. In addition, if the observed value of one or more scan FFs in the scan chain on the downstream side of the faulty scan FF, indicated by the dotted arrow, are continuously the same logical value as that of the faulty scan FF, the scan FFs included in that range may be faulty and so the range of the faulty scan FFs becomes even wider.
In addition, when the fault simulation is performed, the prior art assumes a fault in the scan FFs with no consideration for a signal line branch point between FFs. This decreases both fault simulation accuracy and diagnosis accuracy.
FIGS. 21A and 21B are diagrams showing an example of the output of the scan chain fault diagnosis result obtained by the prior-art fault location estimation device. The prior-art fault location estimation device, which performs the fault simulation assuming that a fault is generated in scan FFs, outputs the scan chain name, scan FF number, fault type, and matching rate (rate) as the output content as shown in FIG. 21A. However, as indicated by the dotted arrows in FIG. 21B, the range of a fault candidate indicated by this output result extends over two signal lines on both sides of a fault candidate scan FF. And, on one signal line that has a branch point, no consideration is given to a change in the failure propagation path caused by the branch. This requires the user of the prior-art fault location estimation device to manually verify a location at which a fault is likely to occur.
[Non-Patent Document 1]
    R. Guo et al., "A Technique for Fault Diagnosis of Defects in Scan Chains," ITC (International Test Conference), 2001, pp. 268-277[Non-Patent Document 2]    K. Stanley, "High-Accuracy Flush-and-Scan Software Diagnostic," IEEE Design & Test of Computers, 2001, Vol. 18, No. 6, pp. 56-62[Non-Patent Document 3]    Yu Huang et al., "Using Fault Model Relaxation to Diagnose Real Scan Chain Defects," ASP-DAC, 2005, pp. 1176-1179

Fault location estimation device, fault location estimation method, and program


A via hole is formed by a first step of forming an opening in a resin insulating film by laser radiation, a second step of forming an opening in said resin insulating film by dry etching and a third step of performing reverse sputtering in a plasma environment.

1. Field of the Invention
The present invention relates to a semiconductor apparatus in which vias are formed and a method of fabricating the same.
2. Description of the Related Art
With portable electronic appliances such as mobile phones, PDAs, DVCs and DSCs becoming more and more advanced in their capabilities, miniaturization and weight reduction of products have become essential for market acceptance. Accordingly, highly-integrated system LSIs for achieving these goals are demanded. Also, better ease and convenience of use are required of these electronic appliances. In this respect, high capabilities and high performance are required of LSIs used in these appliances. While the number of I/Os is increasing as a result of increasingly high integration of LSI chips, there is also a persistent requirement for miniaturization of packages themselves. In order to meet these incompatible demands, development of a semiconductor package adapted for high-density substrate mounting of semiconductor components is in serious demand. A packaging technology called chip size packaging (CSP) has been developed in a variety of forms to address these requirements. For example, the patent document No. 1 discloses a CSP technology.
In a semiconductor package fabricated using the CSP technology, a signal from a semiconductor chip is brought out via an electrode pad. Therefore, vias are formed on the electrode pad. Since the semiconductor chip is formed under the electrode pad, it is necessary to form a via without applying high heat.
It is to be noted that copper has come to be used as a material for electric connection in association with an increasingly high speed of the operation of electronic appliances. A problem with copper is that, when heat is applied to a pad electrode formed by copper, the surface of the pad electrode is oxidized. The patent document No. 1 describes an embodiment in which the top of the pad electrode is capped by an antioxidant Al pad electrode to address the above-mentioned problem.
Related document
    1. JP 2003-249498 A    2. JP 2002-110717 A

Semiconductor apparatus and method of fabricating the apparatus


A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array of field-effect transistors. All of the field-effect transistors are initially in an xe2x80x9cONxe2x80x9d state having a threshold voltage at a first value. At least one layer of metal interconnection is formed over the first dielectric layer within the ROM region and Is covered by a second dielectric layer. A coding photoresist layer is formed on the second dielectric layer and patterned to form a plurality of apertures defining exposure windows. Using the patterning coding photoresist layer as a dielectric etching and implantation hard mask, the underlying field-effect transistors to be coded permanently to a logic xe2x80x9cOFFxe2x80x9d state through the apertures, thereby raising the threshold voltage of the field-effect transistors to a second value.

1. Field of the Invention
The present invention relates generally to a method for manufacturing read only memory (ROM) devices. More specifically, a method is disclosed for minimizing the product turn-around time for making semiconductor permanent store ROM cells with small cell size. This invention particularly involves the use of boron implantation through single or multi-level metal interconnections, which are formed within a ROM region.
2. Description of the Prior Art
Read-only memory (ROM), also known as firmware, is an integrated circuit programmed with specific data when it is manufactured. ROM chips are used not only, in computers, but in most other electronic items as well. The process of programming data is also referred to as coding. Hitherto, numerous coding methods have been developed to program data into the memory cells during different phases of their manufacture. One development that has gained wide use is the threshold voltage implant method, which changes a transistor""s threshold voltage by ion implanting the transistor gates for programmed cells. By way of example, for coding an N-channel memory cell, a predetermined dosage of impurities such as boron are implanted into the channel area under the gate of the transistor to raise its threshold voltage, thereby turning this memory cell into an xe2x80x9coffxe2x80x9d state.
It is often desirable to apply the ROM code onto the partially completed devices during a latter part of the manufacturing process. By applying the code at the latter part of the process, it takes less time to complete wafer processing. Customers require the product turn-around time between receipt of the ROM code for a custom order and delivery of finished parts to be kept as short as possible. Less time for completion means a shorter product turn-around time.
U.S. Pat. No. 4,268,950, filed Jun. 5, 1978 by Chatterjee et al., assigned to Texas Instruments discloses a process for making an N-channel silicon gate MOS read only memory that may be programmed at a late stage in the manufacturing process. The cell array is programmed by boron implantation through a protective nitride, polysilicon strips, and gate oxides to raise the threshold voltage of selected cells to a value above that which will be turned on by the voltage on the selected address line. According to U.S. Pat. No. 4,268,950, no metal lines are used in the cell array, only in the peripheral areas.
U.S. Pat. No. 5,514,609, filed May 13, 1994 by Chen et al., assigned to Mosel Vitelic discloses the manufacture of a ROM cell that is coded before metallization. ROM code impurities are implanted first through a dielectric layer overlying gate electrodes, and then through the underlying selected gate electrodes.
U.S. Pat. No. 6,020,241, filed Dec. 22, 1997 by You et al., assigned to Taiwan Semiconductor Manufacturing Company discloses a method of manufacturing a ROM that is code implanted late in the process after the first level metal thus reducing the turn-around time to ship a customer order. It is noted that the first level metal is not formed in the cell areas, but is formed over the peripheral areas. The code implantation implants impurities through a first dielectric layer overlying gates and a second dielectric layer overlying the first dielectric layer, and through a portion of the word lines.
For today""s high-density ROM device, to reach a highest packing density, some metal interconnections such as bit lines are inevitably formed within the memory array area overlying word lines, instead of buried diffusion bit lines in the substrate as disclosed in the prior art, which occupy a lot of chip area. However, none of the above-mentioned prior art references teaches a method capable of coping with difficulties that occur when coding a ROM integrated circuit device having multilevel metal interconnections formed within the ROM region or cell array area while maintaining a short product turn-around time.
It is therefore a primary objective of this invention to provide a method for manufacturing high-density read only memory (ROM) devices that may be programmed at a selected level of multilevel metal interconnections that are formed within the ROM region, thereby shortening the product turn-around time.
It is a further objective of this invention to provide a method for manufacturing high-density read only memory (ROM) devices that involves the use of relatively high energy ion implantation to program selected transistors though multilevel metal interconnections, Inter-layer dielectric (ILD), polysilicon gates, and gate oxides.
Briefly summarized, the preferred embodiment of the present invention discloses a method for manufacturing a read only memory (ROM) device capable of shortening product turn-around time. The ROM device includes a semiconductor substrate having thereon an array of enhancement-mode metal-oxide-semiconductor field-effect transistors (MOSFETs) within a ROM region and a first dielectric layer covering the MOSFETs within the ROM region. Each of the MOSFETs has a polysilicon gate, a source, a drain, and a gate oxide between the polysilicon gate and the substrate. All of the MOSFETs are initially in a logic xe2x80x9c0xe2x80x9d, state at a first threshold voltage. After planarizing the first dielectric layer, m layers of metal interconnections are formed over the first dielectric layer within the ROM region. According to the first preferred embodiment of the present invention, the top layer of the m layers of metal interconnections (m-th layer metal) within the ROM region is further covered by a top inter-metal dielectric (IMD) layer corresponding to the IMD layer of the m+1 layer metal interconnection that is fabricated in the peripheral area. According to the second preferred embodiment of the present invention, the top layer of the m layers of metal interconnections is covered by a plurality of IMD layers each of which corresponds to one of the IMD layers from the m+1 layer to the Xth layer metal interconnections that are fabricated in the peripheral area.
In accordance with the first preferred embodiment of the present invention, the method generally includes the steps of: forming a mask layer on the top IMD layer, the mask layer having an opening exposing the entire ROM region; etching away a thickness of the top IMD layer through the opening without exposing the top layer of the m layers of metal interconnections to form a recess over the ROM region; removing the mask layer; forming a coding photoresist layer on the remaining top IMD layer in the recess; patterning the coding photoresist layer to form a plurality of apertures defining exposure windows where the underlying MOSFETs are to be coded from the logic xe2x80x9c0xe2x80x9d state into a logic xe2x80x9c1xe2x80x9d state; using the patterning coding photoresist layer as an implant hard mask to implant the underlying MOSFETs to be coded through the apertures, m layers of metal interconnections, polysilicon gates, and gate oxides into the substrate, thereby transforming the MOSFETs to be coded into the logic xe2x80x9c1xe2x80x9d state at a second threshold voltage, wherein the second threshold voltage is higher than the first threshold voltage; and stripping the coding photoresist layer.
In accordance with the second preferred embodiment of the present invention, the method includes forming a mask layer on the plurality of IMD layers. The mask layer has an opening exposing the entire ROM region. A thickness of the plurality of IMD layers is etched away through the opening without exposing the top layer of the m layers of metal interconnections to form a recess over the ROM region. The mask layer is removed. A coding photoresist layer is formed on the remaining top IMD layer in the recess. The coding photoresist layer is then patterned to form a plurality of apertures defining exposure windows where the underlying MOSFETs are to be coded from the logic xe2x80x9c0xe2x80x9d state into a logic xe2x80x9c1xe2x80x9d state. The patterning coding photoresist layer is used as an implant hard mask to implant the underlying MOSFETs to be coded through the apertures, m layers of metal interconnections, polysilicon gates, and gate oxides into the substrate, thereby transforming the MOSFETs to be coded into the logic xe2x80x9c1xe2x80x9d state at a second threshold voltage, wherein the second threshold voltage is higher than the first threshold voltage; and stripping the coding photoresist layer.
According to one aspect of the present invention, an alternative method for manufacturing a ROM device is disclosed. A semiconductor substrate having thereon an array of field-effect transistors within a ROM region is provided. A first dielectric layer covers the array of field-effect transistors. All of the field-effect transistors are initially in an xe2x80x9cONxe2x80x9d state having a threshold voltage at a first value. Over the first dielectric layer within the ROM region, m layers of metal interconnections are formed. The m layers of metal interconnections are further covered by composite dielectric layers. The composite dielectric layers are introduced for the remaining metal isolation after m-th layer are formed in the peripheral area. The device is held awaiting the details of a custom""s order, which will determine the exact configuration of the code implantation. A coding photoresist layer is then formed on the composite dielectric layers. The coding photoresist layer is patterned to form a plurality of apertures defining exposure windows where the underlying field-effect transistors are to be coded permanently to an xe2x80x9cOFFxe2x80x9d state. Using the patterned coding photoresist layer as a dielectric etching mask and also animplant hard mask, a thickness of the composite dielectric layers is etched away through the apertures, and the underlying field-effect transistors to be coded are then code implanted through the apertures, the layer of metal interconnections, polysilicon gates, and gate oxides into the substrate, thereby raising the threshold voltage of the field-effect transistors to be coded to a second value.
In short, according to the present invention, the ROM code implantation may be accomplished through either a 2-mask procedure or a single-mask procedure. The 2-mask procedure includes the use of a first mask defining one big opening through which the composite dielectric is etched back to the m-th layer. The second mask is used to pattern the ROM code with many small openings. Each small opening represents a program address for each individual ROM memory cell to logic xe2x80x9c1xe2x80x9d state. Alternatively, the ROM code implantation may be accomplished through single-mask procedure, in which the ROM code is defined with many small openings omitting the first mask. This means that etching of the dielectric and code implanting are carried out through the same code openings. It is advantageous to use the 2-mask procedure since the product turn-around time is shorter than that of using single-mask procedure. After etching the composite dielectric with the first mask,the ROM device is stored and kept in the state awaiting the customer code mask. There is no etching step after receiving the customer code mask. On the other hand,the single-mask method requires both etch and implantation with the same mask after receiving the customer code mask. It is a trade off when choosing one between the 2-mask and single-mask methods because using single-mask method results in reduced cost (only one mask) but relatively longer turn around time.
Other objects, advantages, and novel features of the claimed invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.

Method for minimizing product turn-around time for making semiconductor permanent store ROM cell


Image processing apparatus comprises a demosaic processor for receiving a video signal comprising pixel data from an array of photosensors each having a respective color filter so as to restrict the sensitivity of that photosensor to a primary color range selected from a set of three or more primary color ranges, the array being such that the photosensors in alternate rows are sensitive to a first primary color range, and photosensors in intervening rows are sensitive to the other primary color ranges. The pixel data including pixel data from a first subset of the rows sensitive to the first primary color range, the first subset being the same from image to image of the video signal; and pixel data from a second subset of the rows of photosensors sensitive to the other primary color ranges, the second subset changing from image to image of the video signal.

1. Field of the Invention
This invention relates to image processing.
2. Description of the Related Art
An example image processing application will now be described in connection with a digital video camera.
In order to generate a colour image using a solid state image sensor (such as a charge coupled device (CCD) image sensor) it is necessary to ensure that different colour components are detected in respect of each pixel position. Some arrangement of colour filters is needed because typically the individual photosensors in an image sensor detect light intensity with little or no wavelength specificity, and therefore cannot themselves detect separate colour information.
One way to provide colour detection is to employ multiple image sensors, each detecting a respective colour component. For example, many digital video cameras use a three CCD system, with each CCD detecting a respective one of green, red and blue colour components. This arrangement requires the three CCDs to be optically aligned with one another to a sub-pixel accuracy, and also needs a light splitter and colour filter arrangement. Optical filters such as dichroic (or thin film) filters may be used for this task, as they have the useful property of passing light of a range of wavelengths while deflecting (rather than absorbing) light outside that range.
However, many digital cameras instead make use of a single CCD operating in conjunction with a colour filter array (CFA). The CFA is a mosaic of tiny colour filters fabricated over the individual pixel sensors of the image sensor.
The colour filters filter the light by wavelength range, such that the separate filtered intensities include information about the colour of light. Absorption (rather than dichroic) filters are generally used.
An example of the use of a CFA is shown schematically in FIG. 1 of the accompanying drawings. A scene 10 is captured by a camera 90 comprising a lens arrangement 20, a CFA 30 arranged on a CCD image sensor 40, and an image processor 50. The CFA 30 comprises an array of individual filter elements 80, generally one per individual pixel sensor of the CCD image sensor 40, each arranged to pass light of a respective colour. Although in FIG. 1 the CFA 30 is shown as an overlay on the CCD image sensor 40, in practice the optical filter elements can be fabricated directly on top of the pixels sensors as part of an overall semiconductor fabrication process.
There are many types of CFA. For example, a so-called Bayer filter, originally proposed in U.S. Pat. No. 3,971,065, contains filter elements giving information about the intensity of light in red, green, and blue (RGB) wavelength regions. An example of the pixel filter layout of a Bayer filter is shown in FIG. 2 of the accompanying drawings, which schematically illustrates the filter layout across a small number of pixel positions 100, with R representing a filter which passes red light, G representing a filter which passes green light, and B representing a filter which passes blue light. A basic pattern of four pixels (a square array of 2×2 pixels) 110 is repeated across the full extent of the CCD sensor.
One reason that more green elements are provided than red or blue elements is that the human eye is generally more sensitive to green light than to the other primary colours. So, the additional resolution in respect of green light mimics the colour response of the human eye. It is also useful because when red, green and blue colour component signals are electrically combined together to form a monochromatic luminance signal (Y), contributions from each colour component are weighted so that the luminance signal contains a greater proportion of the green component than either of the other two components.
The raw image data captured by the image sensor is then converted to the full-colour image, with intensities of all three primary colours represented at each pixel, by a so-called demosaicing algorithm which is tailored for each type of colour filter. In other words, the mosaic relationship of the detected colour components is undone by the demosaicing algorithm so as to provide, for each pixel, all three colour components in respect of a single effective pixel position. In the system of FIG. 1 this function is provided by the image processor 50, which generates an output colour image 60. The spectral transmittance of the CFA elements along with the demosaicing algorithm jointly determine the colour rendition of the camera.


An operator sequentially inserts into an automated system for making armatures for electrodynamic machines loaded magazines containing a required number of hairpin conductors for an armature to be made, an armature core comprising a plurality of substantially aligned laminations preassembled to form the core and a commutator, and removes armatures completed by assembling these components. All the insertion and removal steps are performed from an operator's position such that operation of the system embodying the present invention is easily and conveniently performed even though the components and completed armatures can be of substantial weight. The use of a hairpin magazine, including the hairpin conductors required for an armature, permits simultaneous transfer of all the hairpin conductors into upper twist tooling wherein upper ends of the hairpin conductors adjacent end turn portions of the conductors are moved apart relative to one another. The frog leg conductors thus formed are removed from the upper twist tooling and inserted into slots of an armature core which has been earlier inserted into the system. The frog leg conductors are fully pressed through the armature core into lower twist tooling which then is operated to move the ends of the conductors extending beyond the armature core away from one another and into alignment with other conductors for insertion into a commutator for the armature, which commutator was earlier placed into the system. The commutator is properly positioned beneath the armature core which is then pressed onto the commutator. The completed armature is moved to the operator's position where the operator removes the completed armature and replaces it with a commutator for the next armature. The operator continues to insert components of armatures into the system and removes completed armatures made up by assembling the components so inserted.

The present invention relates generally to electrodynamic machines (also called dynamoelectric machines) and, more particularly, to methods and apparatus for making armatures for such machines by forming and inserting a plurality of single-turn hairpin conductors into peripheral slots of an armature core and securing the free distal ends of the hairpin conductors in a commutator which is pressed onto the armature core.
In the manufacture of armatures for electric motors used for example in golf carts, lift trucks and similar applications, a stack of armature laminations are pressed onto an armature shaft to form an armature core. The laminations have circumferentially spaced openings adjacent or extending to their edges which openings are substantially aligned as the laminations are stacked to define a plurality of radially extending slots around the periphery of the core. Rectangular wire is formed into single-turn coils taking the form of loops, commonly called hairpins, for insertion into the armature core slots. Prior to insertion, the hairpin conductors are shaped such that the legs of the hairpin conductors are spread and oriented to be inserted into different slots of the armature core. After shaping, the hairpin conductors are often referred to as frog legs.
To facilitate assembly of armatures, particularly hand assembly, the slots are open, i.e. extend to the edges of the laminations, and are made sufficiently wide that the hairpin conductors can be moved into the open slots from the cylindrical side face of the core. However, for such wide open slots, insulating wedges are also fitted into the slots or other arrangements are made to retain the hairpins within the slots during rotation of the armature. One hairpin retaining arrangement is to make the slots closed or with only a narrow opening at the edges of the laminations. If the slots are closed or have openings which are not as wide as a hairpin conductor, the hairpin conductors must be inserted into the armature core from the ends of the core.
The free ends of the hairpin conductors emerging from the opposite end of the armature core are also spread and oriented to be received within risers or other conductor receiving structure of a commutator. Finally, a commutator is pressed onto the armature shaft engaging the free ends of the hairpin conductors which are ultimately brazed, welded or otherwise secured to the commutator.
In an effort to automate the manufacture of electric motors, a number of systems have been developed to perform one or more of the noted operations required to produce an armature. For example, U.S. Pat. No. 1,555,931 discloses assembly of an armature wherein an armature core is initially formed and hairpin conductors are preformed into frog legs. The frog leg conductors are manually inserted into an armature core and then simultaneously driven through the armature core by a press.
U.S. Pat. No. 1,544,623, which was reissued as Re. 16,823, discloses a machine for receiving an armature core having frog leg conductors already inserted therein, holding slot insulators in place while forcing the conductors through the core, and bending the ends of the conductors which extend beyond the core to predetermined positions.
U.S. Pat. No. 1,661,344 discloses armature assembling apparatus wherein frog leg conductors are initially partially inserted into slots of an armature core which is then loaded into the assembling apparatus. A cylinder is operated to force all conductors through the core in one operation.
U.S. Pat. No. 1,556,893 discloses apparatus for making armatures wherein a commutator is press fitted onto an otherwise completed armature core. Cam operated slides force free ends of hairpin conductors extending through the armature core inwardly to be received within a commutator.
U.S. Pat. No. 1,556,892 discloses apparatus for making armatures wherein cam driven slides clamp deformable riser tangs on a commutator to simultaneously connect all commutator bars to armature conductors.
U.S. Pat. No. 1,556,891 discloses apparatus for simultaneously twisting the ends of hairpin conductors already inserted into an armature core to align them with commutator bars. Cam inserted forming members ensure that the bending does not materially weaken hairpin insulation.
U.S. Pat. No. 1,690,336 discloses apparatus for bending the ends of hairpin conductors already inserted into an armature core.
U.S. Pat. No. 1,703,188 discloses a machine for receiving an armature core with hairpins inserted therein and for bending the ends of the hairpins toward a central armature shaft prior to bending the hairpins for alignment with commutator bars.
U.S. Patent No. 4,437,230 discloses preliminarily bending ends of hairpin windings in an armature core such that a layer of insulation is not required between terminal portions which extend between the armature core and a commutator.
U.S. Pat. No. 4,207,669 discloses a partially automated system which begins with coiled wire and produces an armature core ready to receive a commutator. Wire is formed into hairpin loops which are individually inserted into a retaining mechanism. Once fully loaded, the mechanism is transported to a working zone where the mechanism is operated to form a set of coils. The mechanism containing the coils is conveyed to a table where it is manually oriented and the table is moved toward a head which removes the coils from the mechanism- The empty mechanism is returned for reuse. The head next inserts the coils into slots of an armature core which is manually installed into a receiver as the coils are being removed from the mechanism. The armature sores are then manually installed in a storing station. The armature cores are fed into a mechanism for pressing the coils into the armature core. The ends of the coils are then moved apart from one another by operation of the mechanism.
In spite of these substantial efforts, armatures for electric motors are still commonly hand assembled resulting in high expense and product inconsistencies which are characteristic of hand assembly. Thus, a need remains for methods and apparatus for automating the manufacture of armatures for electrodynamic machines by mechanically combining a plurality of single-turn hairpin conductors with an armature core and a commutator to form inexpensively and consistently such armatures without manual assembly.

Apparatus for making armatures for electrodynamic machines


A maintenance tool for a planetary gear comprises a force generating device (101) comprising an actuator (102) for fastening to an end of a planet wheel pin of the planetary gear and for directing axial force to the planet wheel pin, and a body structure (104) for mechanically supporting a frame of the force generating device with respect to the planet carrier of the planetary gear so as to allow the actuator to move the planet wheel pin axially with respect to the planet carrier. In many cases, the maintenance tool enables removal of a planet wheel pin and installing, the same or another planet wheel pin at an operating site of the planetary gear. Thus, there is no need to move the planetary gear away from its operating site, e.g. a nacelle of a wind power plant, for maintenance work comprising removal of one or more planet wheel pins.

A planetary gear comprises a planet carrier, a sun shaft, a gear ring, and planet wheels supported by the planet carrier so that the planet wheels are meshing with the sun shaft and with the gear ring. In cases where the gear ring is stationary, the gear ratio between the sun shaft and the planet wheel carrier is ZR/ZS+1, where ZR is the number of teeth of the gear ring and ZS is the number of teeth of the sun shaft. The planet carrier in its simple form comprises a first end-section for supporting first ends of the planet wheel pins and a second end-section for supporting the second ends of the planet wheel pins. The planet wheel pins can be attached for example with thermal shrink fits to the respective holes of the end-sections of the planet carrier. In order to increase the mechanical stiffness, the planet carrier may further comprise support sections between its end-sections.
Maintenance of a planetary gear comprises often, or at least sometimes, removal of one or more planet wheel pins from the planetary gear in order to be able to remove one or more planet wheels that need to be replaced with new ones or repaired. In many cases, maintenance work of the kind described above requires moving the planetary gear away from its operating site to a mechanical repair plant where there are appropriate means for detaching planet wheel pins from the planet carrier of the planetary gear and means for installing planet wheel pins on the planet carrier. Moving the planetary gear from its operating site to the mechanical repair plant can be a laborious task especially in conjunction with wind power applications where the operating site of the planetary gear is typically a nacelle that is located at the top of a tower.


The present invention relates to a process used for packaging a product in a web of material that has a zipper attached thereto. The process includes providing a web of material having first and second edges and a zipper including first and second interlocking members. The first and second interlocking members of the zipper are interlocked together. The first interlocking member of the zipper is attached to the web at an intermediate portion of the web between the first and second edges of the web. The second interlocking member has an attachment region that is facing away from the web. One edge of the web is folded away from the zipper and toward the other edge of the web. Unit operations are performed on the zipper to create zipper segments from the zipper while the zipper is exposed. Each of the zipper segments is associated with an individual food package made from the web.

Plastic packages are popular for storing food products and other items. Recloseable packages that can be securely closed and reopened are particularly popular due to their ability to maintain freshness of the food stored in the package and to minimize leakage to and from the package. Thus, recloseable packages are very common, especially in the food industry. For example, nuts, candy, snacks, cheese, other food, and non-food products can be packed in these packages by form, fill, and seal machines and sold to consumers.
Recloseable packages are typically made to be recloseable via the use of a recloseable feature such as a resealable adhesive seal or a recloseable zipper. Recloseable zippers can be opened and closed either by finger pressure or by use of an auxiliary slider mechanism. Because of the mechanical sealing provided by a zipper, the zipper has become the preferred type of recloseable feature.
Plastic bags with recloseable zippers are commonly formed on vertical and horizontal form, fill, and seal machines. Vertical form, fill, and seal machines typically wrap film around a tube. A vertical seal at the free edges of the web of material is made to develop the tube and a seal at the top or bottom of the tube is made to form a bag. The product is dropped through the tube into the bag. Overwrap form, fill, and seal machines typically wrap film around a product and seal the film to form a bag. Horizontal form, fill, and seal machines generally fold the web and provide two seals that are perpendicular to the fold to create a three-sided package. The product is then placed through the opening in the package and the opening is then sealed.
The recloseable zippers are placed along the web of material at the region that will eventually be the opening of the package. During the form, fill, and seal process, the zipper is usually closed and the two tracks of the zipper are sealed to the web. To form and fill bags with the slider for the zippers requires mounting sliders onto zippers, securing the zippers to bag film, forming a bag from the film, and filling the bag with product. It is desirable to perform all of these steps continuously in order to maximize efficiency and minimize the cost of the bags.

Process for making a recloseable package


A method for fabrication of features of an integrated circuit and device thereof include patterning a first structure on a surface of a semiconductor device and forming spacers about a periphery of the first structure. An angled ion implantation is applied to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions. The unprotected portions and the first structure are selectively removed with respect to the protected portions. A layer below the protected portions of the spacer is patterned to form integrated circuit features.

1. Technical Field
The present invention relates to integrated circuit processing and more particularly to a device and method which employ angle ion implantation to selectively alter an etch rate to re-shape sidewall image transfer patterns.
2. Description of the Related Art
Sidewall Image Transfer (SIT) has been widely used, for example, to form narrow fins for FinFETs (fin field effect transistors). The conventional SIT process requires an additional mask level to remove the undesirable or unwanted parts/sides of the SIT structure. For example, after fin sidewall imaging transfer, the additional mask is used to cut the ends of the fins. Using an extra mask level has drawbacks such as increased mask cost, process cost and process complexity.
Current integration uses SIT to double pattern densities and requires an extra resist mask step to remove the undesirable or un-wanted parts/sides formed by the SIT integration process. Using an extra resist mask step, a few ways exist to etch off the undesirable or un-wanted parts/sides. All of these ways require very high etching selectivity to remove the undesirable or un-wanted parts/sides over a lower layer, to form a final desirable or wanted pattern.
A typical process flow creates a poly silicon mandrel, forms spacers wrapping around the mandrel and uses the spacers as masks to open a lower oxide layer. Remaining spacers are etched off to reduce topography, and a resist mask is processed to expose undesirable parts of oxide masks. Using resist masks, the undesirable parts of the oxide masks are removed. The resist masks are stripped. Then, the oxide masks are employed to etch silicon of a silicon-on-insulator structure to form more densely pitched fin lines.

Angle ion implant to re-shape sidewall image transfer patterns

International Business Machines Corporation


A male type USB (universal serial bus) connector includes a substantially rectangular connector body, a cable connected to the connector body and extended out of a hole at a rear side wall of the connector body, two symmetrical insulative shells fastened together and covered on the rear side wall and two opposite lateral side walls of the connector body and a part of the cable to secure the cable in place, and an insulative cap fastened to the connector body and the insulative shells at a front side, the cap having a center coupling hole, which receives a front side wall of the connector body, and a backward coupling flange coupled to the insulative shells.

The present invention relates to USB (universal serial bus) connectors, and more particularly to a male type USB connector which comprises a connector body, two symmetrical insulative shells covered on rear and lateral side walls of the connector body to secure a cable to the connector body, and a front cap fastened to the connector body at a front side and coupled to the insulative shells.
An USB (universal serial bus) is a standard data transmission media commonly used in communication products, particularly computers and the related peripheral equipment, for the advantages of higher data transmission speed than earlier RS232 connectors, ease of installation and maintenance. A connector for use in a USB is called a USB connector. A USB connector is generally comprised of a connector body, a cable connected to the connector body, and an insulative shell covered on the connector body and a part of the cable to secure the connector body and the cable together. Because the insulative shell is directly molded on the connector body and a part of the cable, molten plastics may pass through gaps in the connector body during the molding process, causing the terminals of the connector body to be covered with residual plastics. It is complicated to clear residual plastics from the terminals.