A capacitor includes: a lower electrode; a capacitor insulating film made of a metal oxide and formed on the lower electrode; an upper electrode formed on the capacitor insulating film; and a buried insulating film surrounding the lower electrode. The lower electrode includes a conductive barrier layer that prevents diffusion of oxygen, and an insulating barrier layer that prevents diffusion of hydrogen is formed so as to be in contact with at least a side surface of the conductive barrier layer in a side surface of the lower electrode.

The present invention relates to a capacitor using a metal oxide in a capacitor insulating film, a semiconductor memory device using such a capacitor, and a method for manufacturing the same.
In recent years, along with developments in the digital technology for electronic equipment, the amount of data to be processed and stored has been increasing. Meanwhile, the level of functionality required for such electronic equipment has also been increasing, and the size of a semiconductor device used in electronic equipment and the size of a semiconductor element used in the semiconductor device have been rapidly reduced.
Along with this trend, techniques have been widely researched and developed in the art that allow the use of a high-permittivity dielectric material as a capacitor insulating film, instead of using silicon oxide or silicon nitride as in the prior art, in order to realize a higher degree of integration of a dynamic RAM device, for example.
Furthermore, ferroelectric films, which are spontaneously polarized, have been actively researched and developed in the art, aiming to realize a non-volatile RAM device that operates at a lower voltage than in the prior art and is capable of performing high-speed write and read operations. In a semiconductor memory device using such a high-permittivity dielectric material or a ferroelectric material in a capacitor insulating film, stacked memory cells have been used, instead of using planar memory cells as in the prior art, for highly-integrated memory devices whose storage capacity is on the order of megabits.
A conventional semiconductor memory device will now be described with reference to the drawings.
FIG. 15 is a cross-sectional view illustrating an important part of a conventional semiconductor memory device disclosed in Japanese Laid-Open Patent Publication No. 11-8355.
As illustrated in FIG. 15, the conventional semiconductor memory device includes a transistor 105, which includes source/drain regions 102 formed in an upper portion of a semiconductor substrate 101, and a gate electrode 104 formed over a channel region of the semiconductor substrate 101 via a gate insulating film 103. An interlayer insulating film 106 is formed on the semiconductor substrate 101 so as to cover the entire surface thereof including the transistor 105, and a contact plug 107 electrically connected to one of the source/drain regions 102 is formed in the interlayer insulating film 106.
An insulating hydrogen barrier layer 108 made of silicon nitride (Si3N4) is formed on the interlayer insulating film 106, and a conductive hydrogen barrier layer 109 made of titanium nitride (TiN) is formed on an upper end of the contact plug 107.
A lower electrode 110 containing iridium dioxide (IrO2) or ruthenium dioxide (RuO2) is formed on the insulating hydrogen barrier layer 108 so as to be connected to the conductive hydrogen barrier layer 109.
A buried insulating film 111 made of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), etc., is formed on the insulating hydrogen barrier layer 108 between the lower electrodes 110.
A capacitor insulating film 112 made of a ferroelectric material such as lead zirconate titanate (Pb(Zr, Ti)O3) or strontium bismuth tantalate (SrBi2Ta2O9) is formed on the buried insulating film 111 including the lower electrode 110, and an upper electrode 113 containing iridium dioxide or ruthenium dioxide is formed on the capacitor insulating film 112. Moreover, an insulating hydrogen barrier layer 114 made of silicon nitride, etc., is formed on the upper electrode 113.
However, the conventional semiconductor memory device as described above has two problems as follows.
First, the conductive oxide film of the lower electrode 110, which is made of iridium dioxide or ruthenium dioxide and serves as a barrier against oxygen, is reduced by hydrogen that is generated during the manufacturing process, whereby the barrier property thereof against oxygen is deteriorated.
Second, the high-permittivity dielectric material or the ferroelectric material of the capacitor insulating film 112 is reduced by hydrogen that is generated during the manufacturing process, whereby the electrical characteristics thereof as a capacitor are deteriorated.
The first problem, i.e., the reduction of the lower electrode having an oxygen barrier property during the manufacturing process, will first be described with reference to FIG. 16A and FIG. 16B.
As illustrated in FIG. 16A, when a buried insulating film 111A is deposited after patterning the lower electrode 110 containing iridium dioxide or ruthenium dioxide, hydrogen ions are generated from monosilane (SiH4) or ammonia (NH3), which is a material gas, and iridium dioxide or ruthenium dioxide is easily reduced by the hydrogen ions. The reduction reaction is particularly pronounced in a case where a plasma CVD method is used for depositing the buried insulating film 111A.
As a result, the diffusion barrier property against oxygen atoms in the buried insulating film 111 is deteriorated. Therefore, during an oxygen annealing process performed at about 650xc2x0 C. to 800xc2x0 C., which is necessary for crystallization of the capacitor insulating film 112, which is made of a high-permittivity dielectric material or a ferroelectric material and formed on the lower electrode 110, oxygen ions diffused from the capacitor insulating film 112 are diffused through the lower electrode 110 to reach the interface between the lower electrode 110 and the contact plug 107, as illustrated in FIG. 16B. This causes a contact failure, e.g., an increase in the contact resistance.
Next, the second problem, i.e., the reduction of the capacitor insulating film made of a high-permittivity dielectric material or a ferroelectric material during the manufacturing process, will be described with reference to FIG. 17.
In an actual semiconductor memory device, a plurality of capacitors and transistors are both arranged two-dimensionally in a so-called xe2x80x9carray patternxe2x80x9d, as illustrated in FIG. 15 or FIG. 17. In a case where the capacitor insulating film 112 of the capacitors, which are arranged in an array pattern, is made of a high-permittivity dielectric material or a ferroelectric material, a metal oxide is used in many cases, as described above. Therefore, it is not possible to prevent some of the capacitors arranged in an array pattern that are located along a periphery 100 of the array pattern from being reduced by hydrogen ions, only with the insulating hydrogen barrier layer 108 provided under the capacitors and the insulating hydrogen barrier layer 114 provided over the capacitors, for the following reason. As illustrated in FIG. 17, although the diffusion of hydrogen ions into the capacitors in the upward direction and the downward direction of the semiconductor substrate 101 can be prevented, it is not possible to prevent the diffusion of hydrogen ions in a lateral direction, i.e., in a direction parallel to the substrate plane, into those capacitors that are located along the periphery 100.
Japanese Laid-Open Patent Publication No. 2001-237393 discloses a semiconductor memory device in which a capacitor is covered completely with a hydrogen barrier layer. However, in a semiconductor memory device in which a plurality of capacitors are arranged in a two-dimensional array pattern, the deterioration of the characteristics of the capacitors cannot be prevented unless all of the plurality of capacitors are covered completely with the hydrogen barrier layer.
Moreover, Japanese Laid-Open Patent Publication No. 11-126881 discloses a semiconductor memory device in which a plurality of capacitors are covered completely with a hydrogen barrier layer. However, this publication does not disclose means for applying a voltage to an upper electrode 110 shown in FIG. 1 of the publication. Assuming that a contact hole is provided for the application of a voltage to the upper electrode 110, a hydrogen barrier layer 111 covering the upper electrode 110 needs to be etched. If such an etching process is performed for making an opening in the hydrogen barrier layer 111, the capacitors are deteriorated by hydrogen that is generated during a resist ashing process, which is performed after the opening is made, or by hydrogen that is generated during the subsequent wiring steps (i.e., a series of processes, including filling the contact hole with a plug, depositing and patterning a wiring layer, sintering the obtained wires using a hydrogen gas, and forming an insulating film that fills the space between the wires), as stated in Japanese Laid-Open Patent Publication No. 2001-44376.
As described above, in the conventional semiconductor memory device, it is difficult to completely cover the memory cell array, including a plurality of capacitors arranged in an array pattern, with a hydrogen barrier layer.
The present invention has been made to solve these problems in the prior art, and a first object thereof is to make it possible to maintain the oxygen barrier property of a lower electrode in a capacitor, a second object thereof is to make it possible to prevent a capacitor insulating film of a capacitor made of a metal oxide from being reduced, and a third object thereof is to make it possible to reliably prevent the characteristics of a capacitor from being deteriorated in a case where a memory cell array is divided into blocks, and the memory cell array is covered for every one or more blocks.
In order to achieve the first object, the present invention employs a structure in which the side surface of the lower electrode of a capacitor is covered with a first insulating barrier layer that prevents the diffusion of oxygen and hydrogen. In order to achieve the second object, the present invention employs a structure in which the side surface of the capacitor insulating film of a capacitor is covered with a second insulating barrier layer that prevents the diffusion of hydrogen. In order to achieve the third object, the present invention employs a structure in which a memory cell array is divided into blocks, and capacitors are covered, for every one or more blocks, with an insulating barrier layer that prevents the diffusion of hydrogen.
Specifically, a first capacitor of the present invention, which achieves the first object set forth above, includes: a lower electrode; a capacitor insulating film made of a metal oxide and formed on the lower electrode; an upper electrode formed on the capacitor insulating film; and a buried insulating film surrounding the-lower electrode, wherein: the lower electrode includes a conductive barrier layer that prevents diffusion of oxygen; and an insulating barrier layer that prevents diffusion of hydrogen is formed so as to be in contact with at least a side surface of the conductive barrier layer in a side surface of the lower electrode.
With the first capacitor, hydrogen that is generated during the deposition of the buried insulating film surrounding the lower electrode is prevented from being diffused into the lower electrode by the insulating barrier layer formed on the side surface of the lower electrode. As a result, in a case where the conductive barrier layer of the lower electrode that prevents diffusion of oxygen is made of a metal oxide, for example, the conductive barrier layer is prevented from being reduced by hydrogen, whereby the conductive barrier layer can maintain its barrier property against oxygen.
In the first capacitor, it is preferred that the buried insulating film is formed in a hydrogen-containing atmosphere.
In the first capacitor, it is preferred that the buried insulating film is made of silicon oxide (SiO2) or silicon nitride (Si3N4).
In the first capacitor, it is preferred that the insulating barrier layer also prevents diffusion of oxygen.
In the first capacitor, it is preferred that the conductive barrier layer includes a layered film made of a first conductive barrier layer that prevents diffusion of oxygen and hydrogen, and a second conductive barrier layer that prevents diffusion of oxygen.
In such a case, it is preferred that the first conductive barrier layer includes one of, or is a layered film including at least two of, titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and tantalum aluminum (TaAl).
Moreover, in such a case, it is preferred that the second conductive barrier layer includes one of, or is a layered film including at least two of, iridium dioxide (IrO2), a layered film including a lower layer made of iridium (Ir) and an upper layer made of iridium dioxide (IrO2), ruthenium dioxide (RuO2), and a layered film including a lower layer made of ruthenium (Ru) and an upper layer made of ruthenium dioxide (RuO2).
In the first capacitor, it is preferred that the insulating barrier layer includes one of aluminum oxide (Al2O3), titanium aluminum oxide (TiAlO), and tantalum aluminum oxide (TaAlO).
A second capacitor of the present invention, which achieves the first object set forth above, includes: a lower electrode; a capacitor insulating film made of a metal oxide and formed on the lower electrode; an upper electrode formed on the capacitor insulating film; and a buried insulating film surrounding the lower electrode, wherein: the lower electrode includes a conductive barrier layer that includes one of, or is a layered film including at least two of, iridium dioxide (IrO2), a layered film including a lower layer made of iridium (Ir) and an upper layer made of iridium dioxide (IrO2), ruthenium dioxide (RuO2), and a layered film including a lower layer made of ruthenium (Ru) and an upper layer made of ruthenium dioxide (RuO2); and an insulating barrier layer including at least one of aluminum oxide (Al2O3), titanium aluminum oxide (TiAlO), and tantalum aluminum oxide (TaAlO), is formed so as to be in contact with at least a side surface of the conductive barrier layer in a side surface of the lower electrode.
With the second capacitor, hydrogen that is generated during the deposition of the buried insulating film is prevented from being diffused into the lower electrode by the insulating barrier layer formed on the side surface of the lower electrode. As a result, the conductive barrier layer is prevented from being reduced by hydrogen, whereby the conductive barrier layer can maintain its barrier property against oxygen.
A first semiconductor memory device of the present invention, which achieves the first object set forth above, includes: a transistor formed on a semiconductor substrate and including a source region and a drain region; an interlayer insulating film formed on the semiconductor substrate so as to cover the transistor; a contact plug formed in the interlayer insulating film so as to be electrically connected to the source region or the drain region of the transistor; and the first or second capacitor of the present invention in which the lower electrode is formed on the contact plug.
The first semiconductor memory device includes the first or second capacitor of the present invention, whereby hydrogen that is generated during the deposition of the buried insulating film is prevented from being diffused into the lower electrode by the insulating barrier layer formed on the side surface of the lower electrode. As a result, in a case where the conductive barrier layer of the lower electrode that prevents diffusion of oxygen is made of a metal oxide, for example, the conductive barrier layer is prevented from being reduced by hydrogen, thereby preventing the deterioration of the characteristics of the capacitor.
A first method for manufacturing a semiconductor memory device of the present invention, which achieves the first object set forth above, includes: a first step of forming a gate electrode on a semiconductor substrate, and then forming a source region and a drain region in the semiconductor substrate on opposite sides of the gate electrode, thereby forming a transistor; a second step of forming an interlayer insulating film on the semiconductor substrate including the transistor; a third step of forming a contact plug in the interlayer insulating film so as to be electrically connected to the source region or the drain region; a fourth step of forming a first conductive film on the interlayer insulating film, the first conductive film including a conductive barrier layer that prevents diffusion of oxygen; a fifth step of patterning the first conductive film so as to be electrically connected to the contact plug, thereby forming a lower electrode from the first conductive film on the interlayer insulating film; a sixth step of forming an insulating barrier layer that prevents diffusion of hydrogen on the interlayer insulating film so as to cover an upper surface and a side surface of the lower electrode; a seventh step of forming a first insulating film on the insulating barrier layer, and then flattening the first insulating film and the insulating barrier layer so that the lower electrode is exposed; an eighth step of forming a second insulating film made of a metal oxide on the first insulating film and the insulating barrier layer, which have been flattened, including the exposed upper surface of the lower electrode, and forming a second conductive film on the second insulating film; and a ninth step of patterning the second conductive film, the second insulating film and the first insulating film so that a remaining portion extends over the lower electrode, thereby forming, on the lower electrode, an upper electrode from the second conductive film and a capacitor insulating film from the second insulating film, and forming a buried insulating film from the first insulating film, the buried insulating film surrounding the lower electrode.
With the first method for manufacturing a semiconductor memory device, in a case where the conductive barrier layer of the lower electrode that prevents diffusion of oxygen is made of a metal oxide, the conductive barrier layer is prevented from being reduced by hydrogen, whereby the conductive barrier layer can maintain its barrier property against oxygen.
In the first method for manufacturing a semiconductor memory device, it is preferred that the buried insulating film is formed in a hydrogen-containing atmosphere.
In the first method for manufacturing a semiconductor memory device, it is preferred that the fourth step includes a step of forming a first conductive barrier layer that prevents diffusion of oxygen and hydrogen, and a step of forming a second conductive barrier layer that prevents diffusion of oxygen.
A third capacitor of the present invention, which achieves the second object set forth above, includes: a lower electrode; a capacitor insulating film made of a metal oxide and formed on the lower electrode; an upper electrode formed on the capacitor insulating film; and a buried insulating film surrounding the lower electrode, wherein: the lower electrode includes a conductive barrier layer that prevents diffusion of oxygen and hydrogen; a first insulating barrier layer that prevents diffusion of hydrogen is formed so as to be in contact with at least a side surface of the conductive barrier layer in a side surface of the lower electrode; a second insulating barrier layer that prevents diffusion of hydrogen is formed so as to cover an upper surface and a side surface of the upper electrode and a side surface of the capacitor insulating film; and the second insulating barrier layer covers the lower electrode and is in contact with the first insulating barrier layer.
With the third capacitor, hydrogen that is generated during the manufacturing process is not diffused into the capacitor insulating film through the side surface thereof, whereby the metal oxide is not reduced. In addition, the capacitor is covered with the second insulating barrier layer with no gap, whereby the capacitor is prevented from being reduced by hydrogen. As a result, it is possible to obtain a capacitor having predetermined electrical characteristics.
In the third capacitor, it is preferred that the buried insulating film is formed in a hydrogen-containing atmosphere.
In the third capacitor, it is preferred that the buried insulating film is made of silicon oxide (SiO2) or silicon nitride (Si3N4).
In the third capacitor, it is preferred that the first insulating barrier layer also prevents diffusion of oxygen.
In the third capacitor, it is preferred that the conductive barrier layer includes a layered film made of a first conductive barrier layer that prevents diffusion of oxygen and hydrogen, and a second conductive barrier layer that prevents diffusion of oxygen.
In such a case, it is preferred that the first conductive barrier layer includes one of, or is a layered film including at least two of, titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and tantalum aluminum (TaAl).
Moreover, in such a case, it is preferred that the second conductive barrier layer includes one of, or is a layered film including at least two of, iridium dioxide (IrO2), a layered film including a lower layer made of iridium (Ir) and an upper layer made of iridium dioxide (IrO2), ruthenium dioxide (RuO2), and a layered film including a lower layer made of ruthenium (Ru) and an upper layer made of ruthenium dioxide (RuO2).
In the third capacitor, it is preferred that the first insulating barrier layer and the second insulating barrier layer are made of aluminum oxide (Al2O3), titanium aluminum oxide (TiAlO), or tantalum aluminum oxide (TaAlO).
A fourth capacitor of the present invention, which achieves the second object set forth above, includes: a lower electrode; a capacitor insulating film made of a metal oxide and formed on the lower electrode; an upper electrode formed on the capacitor insulating film; and a buried insulating film surrounding the lower electrode, wherein: the lower electrode includes a conductive barrier layer that includes one of, or is a layered film including at least two of, titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and tantalum aluminum (TaAl); a first insulating barrier layer including at least one of aluminum oxide (Al2O3), titanium aluminum oxide (TiAlO), and tantalum aluminum oxide (TaAlO), is formed so as to be in contact with at least a side surface of the conductive barrier layer in a side surface of the lower electrode; a second insulating barrier layer including at least one of aluminum oxide (Al2O3), titanium aluminum oxide (TiAlO), and tantalum aluminum oxide (TaAlO), is formed so as to cover an upper surface and a side surface of the upper electrode and a side surface of the capacitor insulating film; and the second insulating barrier layer covers the lower electrode and is in contact with the first insulating barrier layer.
With the fourth capacitor, the second insulating barrier layer, which is made of one material selected from the same group of materials as that for the first insulating barrier layer, is formed so as to cover the upper surface and the side surface of the upper electrode, the side surface of the capacitor insulating film and the lower electrode and to be in contact with the first insulating barrier layer. Thus, the capacitor is covered with the second insulating barrier layer with no gap, whereby the capacitor is prevented from being reduced by hydrogen.
A second semiconductor memory device of the present invention includes: a transistor formed on a semiconductor substrate and including a source region and a drain region; an interlayer insulating film formed on the semiconductor substrate so as to cover the transistor; a contact plug formed in the interlayer insulating film so as to be electrically connected to the source region or the drain region of the transistor; and the third or fourth capacitor of the present invention in which the lower electrode is formed on the contact plug.
The second semiconductor memory device includes the third or fourth capacitor of the present invention, whereby hydrogen that is generated during the deposition of the buried insulating film is prevented from being diffused into the lower electrode by the insulating barrier layer formed on the side surface of the lower electrode. Furthermore, hydrogen that is generated during the manufacturing process is not diffused into the capacitor insulating film through the side surface thereof, whereby the metal oxide is not reduced. In addition, the capacitor is covered with the second insulating barrier layer with no gap, whereby the capacitor is prevented from being reduced by hydrogen.
A second method for manufacturing a semiconductor memory device of the present invention includes: a first step of forming a gate electrode on a semiconductor substrate, and then forming a source region and a drain region in the semiconductor substrate on opposite sides of the gate electrode, thereby forming a transistor; a second step of forming an interlayer insulating film on the semiconductor substrate including the transistor; a third step of forming a contact plug in the interlayer insulating film so as to be electrically connected to the source region or the drain region; a fourth step of forming a first conductive film on the interlayer insulating film, the first conductive film including a conductive barrier layer that prevents diffusion of oxygen and hydrogen; a fifth step of patterning the first conductive film so as to be electrically connected to the contact plug, thereby forming a lower electrode from the first conductive film on the interlayer insulating film; a sixth step of forming a first insulating barrier layer that prevents diffusion of hydrogen on the interlayer insulating film so as to cover an upper surface and a side surface of the lower electrode; a seventh step of forming a first insulating film on the first insulating barrier layer, and then flattening the first insulating film and the first insulating barrier layer so that the lower electrode is exposed; an eighth step of forming a second insulating film made of a metal oxide on the first insulating film and the first insulating barrier layer, which have been flattened, including the exposed upper surface of the lower electrode, and forming a second conductive film on the second insulating film; a ninth step of patterning the second conductive film, the second insulating film and the first insulating film so that a remaining portion extends over the lower electrode, thereby forming, on the lower electrode, an upper electrode from the second conductive film and a capacitor insulating film from the second insulating film, and forming a buried insulating film from the first insulating film, the buried insulating film surrounding the lower electrode; and a tenth step of forming a second insulating barrier layer that prevents diffusion of hydrogen so as to cover the upper electrode, the capacitor insulating film and the buried insulating film and to be in contact with the first insulating barrier layer beside the lower electrode.
With the second method for manufacturing a semiconductor memory device, it is possible to prevent the capacitor insulating film made of a metal oxide of the capacitor from being reduced during the manufacturing process, in addition to the effects of the first method for manufacturing a semiconductor memory device as described above.
In the second method for manufacturing a semiconductor memory device, it is preferred that the first insulating film is formed in a hydrogen-containing atmosphere.
In the second method for manufacturing a semiconductor memory device, it is preferred that the ninth step includes a step of, after the patterning of the first insulating film, patterning the first insulating barrier layer into substantially the same shape as the patterned first insulating film.
In the second method for manufacturing a semiconductor memory device, it is preferred that the fourth step includes a step of forming a first conductive barrier layer that prevents diffusion of oxygen and hydrogen, and a step of forming a second conductive barrier layer that prevents diffusion of oxygen.
A third semiconductor memory device of the present invention, which achieves the third object set forth above, includes: a first transistor formed on a semiconductor substrate and including a source region and a drain region; an interlayer insulating film formed on the semiconductor substrate so as to cover the first transistor; a first contact plug formed in the interlayer insulating film so as to be electrically connected to the source region or the drain region of the first transistor; a lower electrode formed on the interlayer insulating film so as to be electrically connected to the first contact plug, the lower electrode including a conductive barrier layer that prevents diffusion of hydrogen; a capacitor insulating film made of a metal oxide and formed on the lower electrode; and a memory cell array including an upper electrode formed on the capacitor insulating film, the upper electrode being provided for one or more blocks each including a plurality of lower electrodes, wherein an insulating barrier layer that prevents diffusion of hydrogen is formed so as to cover a periphery of one or more of the blocks.
With the third semiconductor memory device, the insulating barrier layer that prevents diffusion of hydrogen is formed so as to cover the periphery of one or more blocks of the memory cell array, whereby it is possible to reliably prevent the deterioration of the characteristics of the capacitor.
It is preferred that in the block of the third semiconductor memory device, the upper electrode is electrically connected to a second contact plug, which is connected to a source region or a drain region of a second transistor, via a conductive barrier film that prevents diffusion of hydrogen.
It is preferred that in the block of the third semiconductor memory device, the upper electrode is electrically connected to a second contact plug, which is connected to a source region or a drain region of a second transistor, via the lower electrode.
A fourth semiconductor memory device of the present invention, which achieves the third object set forth above, includes: a first transistor formed on a semiconductor substrate and including a source region and a drain region; an interlayer insulating film formed on the semiconductor substrate so as to cover the first transistor; a first contact plug formed in the interlayer insulating film so as to be electrically connected to the source region or the drain region of the first transistor; a lower electrode formed on the interlayer insulating film so as to be electrically connected to the first contact plug, the lower electrode including a conductive barrier layer that prevents diffusion of hydrogen; a capacitor insulating film made of a metal oxide and formed on the lower electrode; and a memory cell array including an upper electrode formed on the capacitor insulating film, the upper electrode being provided for one or more blocks each including a plurality of lower electrodes, wherein: a first insulating barrier layer that prevents diffusion of hydrogen is formed so as to be in contact with the plurality of lower electrodes and to cover a bottom surface of the block; a second insulating barrier layer that prevents diffusion of hydrogen is formed so as to cover an upper surface and a side surface of the upper electrode and a side surface of the capacitor insulating film, thereby covering an upper surface and a side surface of the block; and the second insulating barrier layer is in contact with the first insulating barrier layer along a periphery of one or more of the blocks.
With the fourth semiconductor memory device, the first insulating barrier layer that prevents diffusion of hydrogen is formed so as to be in contact with the plurality of lower electrodes and to cover the bottom surface of the block, in addition to the effects of the third semiconductor memory device as described above, whereby it is possible to more reliably prevent the deterioration of the characteristics of the capacitor.
In the fourth semiconductor memory device, it is preferred that the conductive barrier layer includes one of, or is a layered film including at least two of, titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and tantalum aluminum (TaAl).
In the fourth semiconductor memory device, it is preferred that the first insulating barrier layer or the second insulating barrier layer includes at least one of aluminum oxide (Al2O3), titanium aluminum oxide (TiAlO), and tantalum aluminum oxide (TaAlO).
In the fourth semiconductor memory device, it is preferred that the first insulating barrier layer is made of silicon nitride (Si3N4).
A third method for manufacturing a semiconductor memory device of the present invention includes: a first step of forming a gate electrode on a semiconductor substrate, and then forming a source region and a drain region in the semiconductor substrate on opposite sides of the gate electrode, thereby forming a transistor; a second step of forming an interlayer insulating film on the semiconductor substrate including the transistor; a third step of forming a contact plug in the interlayer insulating film so as to be electrically connected to the source region or the drain region; a fourth step of forming a first conductive film on the interlayer insulating film, the first conductive film including a conductive barrier layer that prevents diffusion of oxygen and hydrogen; a fifth step of patterning the first conductive film so as to be electrically connected to the contact plug, thereby forming a plurality of lower electrodes from the first conductive film on the interlayer insulating film; a sixth step of forming a first insulating barrier layer that prevents diffusion of hydrogen on the interlayer insulating film so as to cover an upper surface and a side surface of the plurality of lower electrodes; a seventh step of forming a first insulating film on the first insulating barrier layer, and then flattening the first insulating film and the first insulating barrier layer so that the plurality of lower electrodes are exposed; an eighth step of forming a second insulating film made of a metal oxide entirely across an upper surface of the first insulating film and the first insulating barrier layer, which have been flattened, including an upper surface of the exposed lower electrodes; a ninth step of forming a second conductive film on the second insulating film; a tenth step of patterning the second conductive film, the second insulating film and the first insulating film so that a remaining portion extends over a block including the plurality of lower electrodes, thereby forming an upper electrode from the second conductive film so as to cover the block, forming a capacitor insulating film from the second insulating film, and forming a buried insulating film from the first insulating film, the buried insulating film filling a space between the plurality of lower electrodes; and an eleventh step of forming a second insulating barrier layer that prevents diffusion of hydrogen so as to cover the upper electrode, the capacitor insulating film and the buried insulating film in the block and to be in contact with the first insulating barrier layer along a periphery of the block.
With the third method for manufacturing a semiconductor memory device, the second insulating barrier layer is formed so as to cover the upper electrode, the capacitor insulating film and the buried insulating film in the block and to be in contact with the first insulating barrier layer along the periphery of the block, whereby it is possible to prevent the characteristics of the capacitor from being deteriorated during the manufacturing process.
A fourth method for manufacturing a semiconductor memory device of the present invention includes: a first step of forming gate electrodes on a semiconductor substrate, and then forming source regions and drain regions in the semiconductor substrate on opposite sides of the gate electrodes, thereby forming a first transistor and a second transistor; a second step of forming an interlayer insulating film on the semiconductor substrate including the first transistor and the second transistor; a third step of forming a first contact plug and a second contact plug in the interlayer insulating film so as to be electrically connected to the source region or the drain region of the first transistor and the second transistor, respectively; a fourth step of forming a first conductive film on the interlayer insulating film, the first conductive film including a conductive barrier layer that prevents diffusion of oxygen and hydrogen; a fifth step of patterning the first conductive film so as to be electrically connected to the first contact plug and the second contact plug, thereby forming a plurality of lower electrodes from the first conductive film on the interlayer insulating film; a sixth step of forming a first insulating barrier layer that prevents diffusion of hydrogen on the interlayer insulating film so as to cover an upper surface and a side surface of the plurality of lower electrodes; a seventh step of forming a first insulating film on the first insulating barrier layer, and then flattening the first insulating film and the first insulating barrier layer so that the plurality of lower electrodes are exposed; an eighth step of forming a second insulating film made of a metal oxide entirely across an upper surface of the first insulating film and the first insulating barrier layer, which have been flattened, including an upper surface of the exposed lower electrodes; a ninth step of removing a portion of the second insulating film over the lower electrode that is connected to the second contact plug in a block including the plurality of lower electrodes; a tenth step of forming a second conductive film on the second insulating film and on the lower electrode that is connected to the second contact plug; an eleventh step of patterning the second conductive film, the second insulating film and the first insulating film so that a remaining portion extends over the block, thereby forming an upper electrode from the second conductive film so as to cover the block, forming a capacitor insulating film from the second insulating film, and forming a buried insulating film from the first insulating film, the buried insulating film filling a space between the plurality of lower electrodes; and a twelfth step of forming a second insulating barrier layer that prevents diffusion of hydrogen so as to cover the upper electrode, the capacitor insulating film and the buried insulating film in the block and to be in contact with the first insulating barrier layer along a periphery of the block.
With the fourth method for manufacturing a semiconductor memory device, a voltage can be applied to the upper electrode from the second transistor through the second contact plug without making an opening in the second insulating barrier layer, in addition to the effects of the third method for manufacturing a semiconductor memory device as described above. As a result, it is no longer necessary to provide an opening and wiring in the second insulating barrier layer covering the upper electrode, and thus the exposure to hydrogen is eliminated, whereby it is possible to prevent the deterioration of the characteristics of the capacitor.
A fifth method for manufacturing a semiconductor memory device of the present invention includes: a first step of forming a gate electrode on a semiconductor substrate, and then forming a source region and a drain region in the semiconductor substrate on opposite sides of the gate electrode, thereby forming a transistor; a second step of forming an interlayer insulating film on the semiconductor substrate including the transistor; a third step of forming a first insulating barrier layer that prevents diffusion of hydrogen on the interlayer insulating film; a fourth step of forming a contact plug in the interlayer insulating film and the first insulating barrier layer so as to be electrically connected to the source region or the drain region; a fifth step of forming a first conductive film on the first insulating barrier layer, the first conductive film including a conductive barrier layer that prevents diffusion of hydrogen; a sixth step of patterning the first conductive film so as to be electrically connected to the contact plug, thereby forming a plurality of lower electrodes from the first conductive film on the first insulating barrier layer; a seventh step of forming a first insulating film on the first insulating barrier layer including an upper surface of the plurality of lower electrodes, and then flattening the first insulating film so that the plurality of lower electrodes are exposed; an eighth step of forming a second insulating film made of a metal oxide entirely across an upper surface of the first insulating film, which has been flattened, including an upper surface of the exposed lower electrodes; a ninth step of forming a second conductive film on the second insulating film; a tenth step of patterning the second conductive film, the second insulating film and the first insulating film so that a remaining portion extends over a block including the plurality of lower electrodes, thereby forming an upper electrode from the second conductive film so as to cover the block, forming a capacitor insulating film from the second insulating film, and forming a buried insulating film from the first insulating film, the buried insulating film filling a space between the plurality of lower electrodes; and an eleventh step of forming a second insulating barrier layer that prevents diffusion of hydrogen so as to cover the upper electrode, the capacitor insulating film and the buried insulating film in the block and to be in contact with the first insulating barrier layer along a periphery of the block.
With the fifth method for manufacturing a semiconductor memory device, the second insulating barrier layer is formed so as to cover the upper electrode, the capacitor insulating film and the buried insulating film in the block and to be in contact with the first insulating barrier layer along the periphery of the block, whereby it is possible to prevent the characteristics of the capacitor from being deteriorated during the manufacturing process.
A sixth method for manufacturing a semiconductor memory device of the present invention includes: a first step of forming gate electrodes on a semiconductor substrate, and then forming source regions and drain regions in the semiconductor substrate on opposite sides of the gate electrodes, thereby forming a first transistor and a second transistor; a second step of forming an interlayer insulating film on the semiconductor substrate including the first transistor and the second transistor; a third step of forming a first insulating barrier layer that prevents diffusion of hydrogen on the interlayer insulating film; a fourth step of forming a first contact plug and a second contact plug in the interlayer insulating film and the first insulating barrier layer so as to be electrically connected to the source region or the drain region of the first transistor and the second transistor, respectively; a fifth step of forming a first conductive film on the first insulating barrier layer, the first conductive film including a conductive barrier layer that prevents diffusion of hydrogen; a sixth step of patterning the first conductive film so as to be electrically connected to the first contact plug and the second contact plug, thereby forming a plurality of lower electrodes from the first conductive film on the first insulating barrier layer; a seventh step of forming a first insulating film on the first insulating barrier layer including an upper surface of the plurality of lower electrodes, and then flattening the first insulating film so that the plurality of lower electrodes are exposed; an eighth step of forming a second insulating film made of a metal oxide entirely across an upper surface of the first insulating film, which has been flattened, including an upper surface of the exposed lower electrodes; a ninth step of removing a portion of the second insulating film over the lower electrode that is connected to the second contact plug in a block including the plurality of lower electrodes; a tenth step of forming a second conductive film on the second insulating film and on the lower electrode that is connected to the second contact plug; an eleventh step of patterning the second conductive film, the second insulating film and the first insulating film so that a remaining portion extends over the block, thereby forming an upper electrode from the second conductive film so as to cover the block, forming a capacitor insulating film from the second insulating film, and forming a buried insulating film from the first insulating film, the buried insulating film filling a space between the plurality of lower electrodes; and a twelfth step of forming a second insulating barrier layer that prevents diffusion of hydrogen so as to cover the upper electrode, the capacitor insulating film and the buried insulating film in the block and to be in contact with the first insulating barrier layer along a periphery of the block.
With the sixth method for manufacturing a semiconductor memory device, a voltage can be applied to the upper electrode from the second transistor through the second contact plug without making an opening in the second insulating barrier layer, in addition to the effects of the fifth method for manufacturing a semiconductor memory device as described above. As a result, it is no longer necessary to provide an opening and wiring in the second insulating barrier layer covering the upper electrode, and thus the exposure to hydrogen is eliminated, whereby it is possible to prevent the deterioration of the characteristics of the capacitor.
In the third or fifth method for manufacturing a semiconductor memory device, it is preferred that the tenth step includes a step of, after the patterning of the first insulating film, patterning the first insulating barrier layer into substantially the same shape as the patterned first insulating film.
In the fourth or sixth method for manufacturing a semiconductor memory device, it is preferred that the eleventh step includes a step of, after the patterning of the first insulating film, patterning the first insulating barrier layer into substantially the same shape as the patterned first insulating film.

Capacitor, semiconductor memory device, and method for manufacturing the same

Matsushita Electric Industrial Co., Ltd.


A border router includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code is configured to, with the at least one processor, cause the border router to: identify, in response to receiving a label mapping message from a network node, a backup border router as a hop in a backup path between a leaf node and a root node in a multicast network including an autonomous system, the label mapping message including a type-length-value; determine whether the backup border router is an originating border router having generated the label mapping message based on the type-length-value; and suppress mapping of the hop in the backup path in response to determining that the backup border router is the originating border router.

Multicast only Fast Re-Route (MoFRR) provides primary and backup paths for multicast streams between a root node and a leaf node within an autonomous system (AS). The root node streams multicast content toward the leaf node on both the primary and backup paths, but the leaf node and all the intermediate nodes only listen to the primary path while dropping (discarding) redundant packets received on the backup path until a failure necessitates listening to the backup path. Autonomous system boundary router (ASBR) MoFRR takes this concept a step further, wherein the multicast stream is protected via a primary and backup autonomous system boundary router. As such, two multicast streams are transmitted to the leaf node, one from a primary autonomous system boundary router and another from a backup autonomous system boundary router. The leaf node listens to the primary autonomous system boundary router while dropping the redundant traffic from the backup autonomous system boundary router.

Border routers in multicast networks and methods of operating the same


An ecological greening wall and a construction method thereof are provided. The ecological greening wall comprises a plurality of fixed poles (2) arranged at intervals on the ground (1), and a reinforcement (3) with openings is fixedly connected between the fixed poles (2) and arranged along the fixed poles (2) in a vertical direction. Stacked vegetation bags (4) for greening are provided on at least one side of the reinforcement (3), and each includes a breathable and permeable bag body (41) and a vegetation base material (42) filled in the bag body (41). The bag body (41) and the reinforcement (3) are fixedly connected together by a reinforcing wall (6) so as to form a whole body by the reinforcing wall (6), the reinforcement (3) and the vegetation bag (4). The ecological greening wall has a simple and firm structure, and it is easy to be constructed.

Along with the fastened urbanization and the advanced industrialization, the ecological problem has become the focus of world's attention. At present, infrastructure construction increases gradually due to the fast and sustainable economy development, thus the conflict between the construction of, e.g., highway, house and soundproof walls and the ecological environment protection becomes increasingly significant because the current walls, such as a middle isolation barrier or side guardrails of highway and infrastructural walls of house, are mostly constructed through cement casting or metal bridge joint, for example. As such, these walls increase ambient temperature and noise, and greening of the walls is difficult and expensive and cannot achieve the desired effect. Therefore, the applicant brings forward an ecological wall, for the purposes of heat insulation, sound insulation, greening and environment protection.

Ecological greening wall and construction method thereof


A method for processing an incoming call, includes: an accessing call mark being preset in a called terminal; the called terminal, on receiving a call initiated by a calling party, determining whether the call contains the accessing call mark of the called terminal; if the call contains the accessing call mark of the called terminal, the called terminal putting through the call; otherwise, the called terminal terminating the call. The invention may solve the problems caused by various methods used in the prior art to avoid being disturbed by phone calls, such as missing important calls, extra service fee, partial protection against harassing telephone calls, and etc. The solution may ensure that the called user will not be disturbed by unimportant calls or harassing calls when the called user does not want to be disturbed, while ensuring that the called user will not miss any important call.

The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
Along with the popularization of terminal devices such as fixed telephones and mobile phones, people's work and life have become more convenient as they may communicate with each other through the terminal devices at any time. However, terminal devices also bring troubles to their users. For example, as no user wants to be disturbed by unimportant phone calls at night or during leisure time, a user may turn off the terminal device, which, however, makes it possible for the user to miss important calls. If the user keeps the terminal on at night or during leisure time, there are indeed unimportant calls coming in during such periods, some of which are even harassing calls.
Terminal devices include fixed terminals and mobile terminals, and it is comparatively easy to turn off mobile terminals while the only way to turn off a fixed phone is to disconnect the telephone line, which is very inconvenient for the user. Moreover, turning off terminals, mobile or fixed, will bring other problems: the user will not get any phone calls when the terminal device is turned off, and others will not be able to contact the user even with very important business matters. And the user needs to turn on the terminal again when he needs to use the terminal. It is convenient to turn off or turn on mobile terminals, but it is common that a user forgets to turn on a fixed terminal. Thus the user will not get the phone calls from anyone through the terminal if it is not turned on again.
A user may also utilize the secretary service currently offered by a mobile communication system, but the service is applied to mobile terminals only. The user of a mobile terminal may customize the settings of his secretary station; for instance, the user who does not want to be disturbed by phone calls may request the secretary station to record voice messages for the calling users and send the messages to the called user. Therefore when the secretary receives a phone call for the user, it will ask the calling user to leave a message and then inform the called user by a short message or other means. The called user calls the secretary station to get the voice message left for him by the calling user. The called user may decide whether to call back according to the contents of the voice message, and thus will not be disturbed by incoming calls.
However, the secretary service is a paid service, i.e. the users of the service need to pay for it. The secretary station only converts incoming calls into short messages or other forms of notice to the called user, so the called user receives short messages or other messages instead of calls and is still somewhat disturbed. In this sense, the solution is not a perfect one. Besides, the short messages from the secretary station to the called user may be delayed or even lost, and the called user may not read the short messages in time. For example, as short messages are not real-time communication and users usually set gentle, weak or even mute short-message notifying sounds, it is common for a user to fail to handle a short message in time and accordingly fail to handle an urgent business in time.
Another solution is to set an incoming call filter. For instance, blacklists and whitelists can be used to protect users from the disturbance of unimportant phone calls while guaranteeing that important calls will never be missed. For example, the whitelist solution comprises: setting a whitelist of calling numbers that are allowed to access the called terminal; when the called terminal enables the whitelist function, only the calling numbers in the whitelist may access the called terminal. The whitelist solution may solve the above-mentioned problem to a large extent, but the authorized calling numbers are limited in the solution. When a user A needs to call a user C in emergency, although the cellular phone number of the user A is in the whitelist, the user A, as his cellular phone is out of power, may have to call with a user B's cellular phone, the number of which is not in the whitelist. In that case, the user A is unable to call through a number in the whitelist so that the user A will not be able to contact user C. The blacklist solution comprises: setting a blacklist of calling numbers that are not allowed to access the called terminal, when the called terminal enables the blacklist function, the incoming calls from the numbers in the blacklist will be refused. The blacklist solution is unable to block incoming calls from the number outside the blacklist. For example, harassing calls from public telephones are not blocked by the blacklist solution. What's more, the maintenance of the blacklist and the whitelist is complicated.


A tool for foaming of a component to a pane for a motor vehicle, which forms at least one part of a boundary of an area to be peripherally foamed and includes a rigid insert for holding the component. The insert includes a bottom having an opening for insertion of an end of the component facing away from the peripheral foaming area. An elastic sealing ring surrounds the opening and lies on the bottom. A pressure element is used to press the sealing ring against the bottom to deform the sealing ring in the lateral direction to make tight lateral contact with a part of the component which has been inserted through the opening.

1. Field of the Invention
This invention relates to a tool for foaming components to a pane for a motor vehicle, especially a vehicle roof pane.
2. Description of Related Art
In tools for foaming-on of components, the problem arises that the components, on the one hand, must be held in the foaming process and, on the other hand, in the holding area, no foam should emerge from the area to be peripherally foamed. In generic foaming tools, it is well known for this purpose to provide the foaming tool with built-in rubber sealing rings, inflatable sealing elements, or milled-out recesses in the tool into which pockets of polyurethane are inserted, wherein the components are inserted into these elements.
It is a disadvantage in this process that when the components are inserted, serious friction can occur by which, on the one hand, a large amount of force must be applied and, on the other hand, distortion or bending of the component can occur upon insertion. Upon removal from the mold after the foaming process, deformations remaining in the foamed-on material can occur which leads to an adverse optical impression. On the other hand, the sealing action is often not sufficient or the insertion of the components can be unreliable due to remaining foam residues in the sealing elements. Replacement of worn sealing elements is complex and the service life of the sealing elements is relatively short. For inflatable sealing elements, investment costs are higher and a large installation space is required.
It is therefore one object of the present invention to overcome the deficiencies of the prior art and to provide a foaming tool which enables simple and low-wear insertion of the components to be foamed on.
It is another object of the present invention to provide a foaming tool which enables good sealing action and stress-free peripheral foaming.
Yet another object of the present invention is to provide a foaming tool which keeps tool costs low.
The above object and other objects are achieved in accordance with the present invention by providing a tool for foaming a component to a pane for a motor vehicle, wherein the tool forms at least one part of a boundary of an area to be peripherally foamed and comprises a rigid insert for holding the component. The rigid insert includes a bottom having an opening for insertion of an end of the component facing away from the peripheral foaming area. The tool also includes an elastic sealing ring surrounding the opening and positioned on the bottom of the rigid insert. A pressure element is provided to press the sealing ring against the bottom of the insert to deform the sealing ring in a lateral direction sufficiently to cause the sealing ring to make tight lateral contact with a part of the component which has been inserted through the opening.
The present invention is advantageous in that the components can be inserted quickly, with low friction, and free of distortion, while achieving very good sealing action with respect to the foaming material. Also, a long service life of the tool components is attained. Moreover, the dimensions when foaming-in can be reliably maintained in the process, and the tool costs are kept low. Tools can be used, without additional modifications, which are provided with a milled-out area for conventional polyurethane pockets. Furthermore, the amount of installation space required is much less than for inflatable polyurethane pockets.

Tool for foaming components to a pane for a motor vehicle

Webasto Vehicle Systems International GmbH


An example method for identifying a reading location in a text source as a user reads the text source aloud includes determining phoneme data of the text source, the text source comprising a sequence of words; receiving audio data comprising a spoken word associated with the text source; comparing, by a processing device, the phoneme data of the text source and phoneme data of the audio data; and identifying a location in the sequence of words based on the comparing phoneme data.

The capabilities and usage of virtual assistants are expanding rapidly. Traditional virtual assistants include some form of computer human interface that enables a human to interact with the virtual assistant and cause the virtual assistant to perform a task or service. Virtual assistants often record and understand human speech and can respond by synthesizing a reply. The virtual assistants may be initiated in response to a touch or gesture based command or may continuously analyze its environment to detect a spoken command. When the command is detected, the virtual assistant may respond or perform one or more actions.

Reading progress estimation based on phonetic fuzzy matching and confidence interval


A process for generating a vector for testing a digital circuit for a given fault first creates a composite circuit including a fault-present version of the circuit and a fault-free version. An implication graph is developed for the composite circuit and its energy function is derived as a combination of binary and ternary terms. All signal states that are consistent with the circuit function minimize the energy function to zero value. The transitive closure is computed for the binary terms, and redundancies, contradictions, fixations, identification and exclusions are identified. By iteration of implication graphs and transitive closures together with arbitrarily assigned signal values all ternary terms of the energy function are converted to binary terms, after which transitive closure recomputes a set of literals that can be used to generate the desired test vector by a standard branch and bound procedure.

As the number of components in VLSI circuitry has grown, the testing of such circuitry has become complex. The testing is complicated because it is impractical to probe internal nodes of the circuit. As a consequence, the usual manner of testing such circuits is to apply a set of input vectors to the input terminals of the circuit and for each input vector to observe the resulting output vector at the output terminals to ascertain whether the output vector observed corresponds to the output vector expected for the particular applied input vector. Each input vector typically is chosen to test for a particular one of the faults thought possibly to be found in the circuit. For complex circuits the number of possible faults tends to be large so that a large set of test vectors is needed. An important factor in this process is having a set of input vectors for use in the testing that will provide the maximum amount of relevant information in the shortest time of testing. Generally, the testing is done automatically by equipment designed to provide a prescribed set of input vectors sequentially to a sample circuit being tested to check the output vectors observed for conformance with the output vectors expected and to reject nonconforming samples..
Typically, choosing a set of test vectors is part of the design process of the integrated circuit. Normally, even before a phototype chip of a desired integrated circuit is built, there is developed an appropriate set of vectors for use in testing the eventual chip. This process involves establishing various faults that possibly might arise in the circuit and developing a set of vectors for testing for all or most of such possible faults.
Various techniques are in use for developing such sets of test vectors but there remains room for improvement. Typically previous techniques do not guarantee the identification of all logical consequences of a partial set of signal assignments. It is desirable to identify all such consequences so that a branch and bound method can effectively avoid signal assignments that will not lead to a test vector. Also previous techniques generally do not establish the complexity of determining the logical consequences, and it remains unclear if it is at all possible to determine all the consequences using reasonable amount of resources. Finally, these techniques tend not to be easily parallelizable.

Transitive closure based process for generating test vectors for VLSI circuit


The present invention provides a method for presenting a web page which presents a preview of a web page when loading the web page. The preview may be a smaller version of the web page, which is fitted to be completely contained in one screen. The preview may include a smaller version of each module on the web page, and may be expanded to a web page in full size when the loading is finished. If a user expresses interests in one module, that module may be loaded and displayed first.

1. Field of the Invention
The present invention relates generally to the Internet, and more particularly to a method of providing a preview of content on a web page.
2. Description of Related Art
The Internet has become a major information resource to users. To attract more users, content providers are putting more and more information on their websites, causing the quantity and complexity of content of a web page to be significantly increased. As one consequence, it may take longer to load a web page. Since existing methods do not display anything on the screen until the loading of the web page is finished, users have to spend more time waiting.
As another consequence, web pages are becoming longer, with more modules stacked thereon. Users might not think to scroll down to see content on a lower portion of a web page, thus missing significant amount of information and services provided by the web page. When a user does scroll down, the upper portion of the web page may move out of the screen, so that the user cannot see all the content on the web page at one time. Besides, constantly operating a mouse to scroll up and down the web page is inconvenient, time consuming and tiring, especially when the user does not know in advance whether he/she is interested in the content below the fold.
Therefore, it would be desirable to provide a more user friendly web page presentation method, which presents a preview of a long web page when loading the web page.


A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate.

The present invention relates to a semiconductor device having a 4F2 structure and a method for manufacturing the same.
As the integration of semiconductor devices has been increased, a two-dimensional area occupied by each unit cell has been decreased. With the decrease of the area occupied by the unit cell, various methods have been introduced to form a transistor, a bit line, a word line and a capacitor in a limited area.
As one of those methods, a semiconductor device having a vertical transistor has been suggested. In such a semiconductor device, a source region and a drain region of the vertical transistor are arranged upward and downward in an active region so that a vertical channel may be formed.
In the vertical transistor, a gate is formed on sidewalls of a silicon pillar included in the active region. With respect to the gate, the source region is formed at an upper side of the silicon pillar, and the drain region is formed in a silicon substrate disposed below the silicon pillar. In the semiconductor device including this vertical transistor, a cell scheme is reduced to a 4F2 structure, resulting in increasing a net die. However, a manufacturing process of the semiconductor device including the vertical transistor is complicated.

Method for manufacturing semiconductor device with first and second gates over buried bit line


Multimode distribution systems and methods are described. A multimode distribution system includes a first source interface for coupling to a first power source, a second source interface for coupling to a second power source, and a first selection device to be coupled via a first connection matrix and the first source interface with the first power source to provide main power to one or more power consumption devices. The multimode distribution system includes a second selection device to be coupled via a second connection matrix and the first source interface with the first power source to provide main power to one or more additional power consumption devices. The second selection device is to be coupled via the second connection matrix and the second source interface with the second power source to provide alternative power to the additional power consumption devices.

A data center is a facility that holds telecommunication equipment, e.g., computers, servers, telecommunication devices, storage systems, security devices, and power supplies. A data center can occupy a room, a floor, or even an entire building. Usually, most of the equipment in a data center includes servers that are placed in racks. People can access the servers between the racks. In the data center, there is a supply of power from various power sources to the telecommunication equipment. However, it is costly to obtain the power sources to support the data center.
It is in this context that various embodiments of the present invention arise.

Multimode distribution systems and methods for providing power from power sources to power consuming devices


The invention relates to a triple-deck elevator equipment planning support system, arranged such that the average number of times of being stopped per going-round is calculated on the basis of a given building specification and cage specification data in a triple-deck elevator system; a total value of getting-on/off time periods of passengers, a total value of door-opening/closing time periods, and the total value of running time periods are calculated based on the average number; and a going-round time period of an elevator is calculated from these calculation results, and a practical transportation capacity per on triple-deck elevator is calculated.

In normally selecting elevator equipment (the number of elevators, velocity, and capacity), a calculation method referred to as "traffic calculation" is adopted. This is a method of calculating the number of passengers capable of being transported in a unit time (normally 5 minutes) with this elevator when specified building specification and cage specification (e.g., velocity and capacity) are given. The procedure of comparing this calculation result and the building resident population, and of determining the required number of elevators, is generally adopted. (For example, refer to the Japanese Patent Publication (unexamined) No. 75308/2004 (Patent Document 1))
Furthermore, in non-Patent Document 1, a calculation expression, in which this traffic calculation is extended to a double-deck elevator, is reported.
First, prior to description of the invention, the schematic procedure of traffic calculation to be applied in the case of a normal elevator system (SD) described in Patent Document 1 is described.
Normally, the traffic calculation is performed on the assumption that all passengers get on from the reference floor (1F), and do not get on from the other floor, for example, in the case of an office building when cage and building specifications such as cage velocity and acceleration, capacity (number of passengers), door-opening/closing time period, the number of building stories, the number of service floors, and story height, are given. This calculation is made for the purpose of obtaining the number of elevators capable of transporting a large number of passengers that are generated at the time of office-going hour (UP Peak) of the building.
First of all, a predicted number of being stopped S of the cage after it has started from the reference floor toward upper floors until it is moved back, and an average number of being moved back of the cage are calculated. Herein, a building of (N+1) stories in which the reference floor is the lowermost floor is supposed.
                    [                  Expression                                                              1                ]                                                            S        =                  N                                {                          1              -                                                (                                      1                    -                                          1                      N                                                        )                                P                                      }                                              (        1        )                                [                  Expression                                                              2                ]                                                            H        =                  N          -                                    ∑                              i                =                1                                            N                -                1                                                                                (                                  i                  N                                )                            P                                                          (        2        )
Where: S indicates the predicted number of being stopped, N indicates the number of service floors except for the reference floor, P indicates the number of passengers in the cage at the time of starting from the reference floor, and H indicates the average highlighted floor.
Next, on the basis of the above-mentioned Expressions (1) and (2), the total value of getting-on/off time periods of passengers, the total value of door-opening/closing time periods, and the total value of running time periods will be obtained as follows.[Expression 3]Total value of getting-on time periods=P×ton,total value of getting-off time periods=P×toff,total value of door-opening/closing time periods=(S+1)(to+tc)total value of running time periods=(S+1)(tf(1)−tv(1))+2H×tv(1)  (3)
Where: ton is a getting-on time period per person, toff is a getting-off time period per person, to is a door-opening time period, tc is a door-closing time period, tf(1) is a running time period per floor, and tv(1) is a passing time period per floor.
When calculating each value as described above, one going-round time period RTT will be calculated with the following expression as the total sum of these values.[Expression 4]RTT=P(ton+toff)+(S+1)(to+tc+tf(1)−tv(1))+H/2×tv(1)  (4)
Furthermore, with this value, the transportation capacity per unit time HC of one elevator (the number of passengers capable of being transported per unit time) will be obtained with the following expression.[Expression 5]HC=300P/RTT  (5)
From the expressions of traffic calculation as described above, on the supposition of, for example, HC=50 persons/5 minutes, that is, 300/50=6, thus the required number of elevators will be calculated to be 6.
In addition, now expressions of the traffic calculation of DD described in the above-mentioned non-Patent Document 1 is described. Herein, the operation in which the lower cage of DD is stopped only at the odd-numbered floor, and the upper cage thereof is stopped only at the even-numbered floor is assumed; and a building of 2(N+1) stories is supposed.
                    [                  Expression                                                              6                ]                                                            predicted                                                  number                                                  of                                                  DD                                                  being                                                  stopped                            (        6        )                                          S          d                =                              N                                      {                              1                -                                                      (                                          1                      -                                              1                        N                                                              )                                                        2                                        P                                                              }                                =                                    2                            S                        -                                          S                2                            N                                                                      total value of getting-on time periods=P×ton,total value of getting-off time periods=P(2−S/N)toff,total value of door-opening/closing time periods=(Sd+1)(to+tc)total value of running time periods=(Sd+1)(tf(2)−tv(2))+2H×tv(2),
tf(2): running time period per two floors, and
tv(2): passing time period per two floors.
When calculating each value as described above, one going-round time period RTTDD of DD will be calculated with the following expression as the total sum of these values.[Expression 7]RTTDD=Pton+P(2−S/N)toff+(S(2−S/N)+1)(to+tc+tf(2)−tv(2))+H×tv(2)  (7)
Furthermore, with this value, the transportation capacity per unit time HCDD of one DD (the number of passengers capable of being transported in unit time) will be obtained with the following expression.[Expression 8]HCDD=300×2P/RTT  (8)    patent Document 1: the Japanese Patent Publication (unexamined) No. 75308/2004    Non-Patent Document 1: G. T. Kavounas: Elevatoring Analysis with Double-deck Elevators, Elevator World, November, pp. 65-72 (1989)

Equipment planning support system for triple-deck elevator


A socket assembly includes a rectangular socket body and two ejector mechanisms. The socket body has two opposed sides, a top surface, a bottom surface, a row of terminal-receiving holes formed in the top surface on at least the two opposed sides for receiving terminal pins of an integrated circuit chip therein, and a plurality of terminal pins extending from the bottom surface and corresponding to the terminal-receiving holes. Each of the ejector mechanisms includes an elongated pivot plate. Each of the pivot plates has a lower end mounted pivotally on a corresponding one of the two opposed sides of the socket body and further has a levering rib extending transversely from an inner surface thereof and extending normally above the top surface. The levering rib has a longitudinal distal edge which is formed with a row of terminal-receiving notches aligned with a corresponding one of the rows of terminal-receiving holes in the socket body.

1. Field Of The Invention
This invention relates to a socket assembly for an integrated circuit chip, more particularly to a socket assembly which is constructed to facilitate extraction of an integrated circuit chip therefrom.
2. Description Of The Related Art
Pins of an integrated circuit chip, such as those of a central processing unit (CPU), are easily deformed when the integrated circuit chip is extracted from a conventional socket. It is a pity to discard an integrated circuit chip having deformed pins even though the integrated circuit chip is operable.

Socket assembly for an integrated circuit chip


Described herein is a method for the production of electronic or optoelectronic devices with an anisotropic molecular structure of an organic semiconductor material. Also described herein are electronic or optoelectronic devices including an organic semiconductor material with anisotropic molecular structure. Also described herein are fibers comprising a hollow core and a shell comprising an organic semiconductor material.

The macroscopic electronic and optoelectronic properties of organic semiconductor thin films frequently rely on the inherent anisotropy of the molecular structure of the organic semiconductor. This has been found to be reflected in the performance of electronic and optoelectronic devices, such as organic field effect transistors (OTFTs), organic light-emitting diodes (OLEDs), organic photodetectors (OPDs) or organic photovoltaic cells (OPVs). For OTFTs, the current densities and carrier mobilities can differ by orders of magnitude depending on the direction of the charge-carrier transport. In OLEDs the emission efficiency can be strongly dependent on the orientation of the emitter materials. The development of techniques that enable control of the deposition of organic semiconductor materials on the molecular scale is of utmost importance for the optimization of device performance.
The possibility to process organic electronic materials, such as organic semiconductor materials, in solution provides access to industrial coating and printing methods that would permit low-cost high-throughput manufacturing of electronics, also on flexible and transparent substrates. However, such coating and printing methods generally introduce a high degree of disorder in the molecular arrangement in the so-formed films due to the drying of the films, thereby resulting in undesired morphologies (e.g. grain boundaries, glass-like structures, amorphous regions or phase separation).
Research in this field has led to a number of methods leading to high orientation on a molecular level using processes like off-center spin coating, bar coating (e.g. k-bar coating), substrate ribbing, the use of wetting and/or de-wetting structures, mechanical rubbing and shearing, nano-patterning of the processed layer by imprinting or processing with crystalline agents have shown promising results for controlling the orientation of macroscopic films on the molecular level.
Crystallization of conjugated polymer systems, such as organic semiconductor materials, is, for example, disclosed in C. Müller et al., Adv. Funct. Mater. 2013, 23, 2368-2377; B. Dörling et al., J. Mater. Chem. C 2014, 2, 3303-3310; M. Brinkmann, J. C. Wittmann, Adv. Mater. 2006, 18, 860-863; M. Brinkmann, P. Rannou, Adv. Funct. Mater. 2007, 17, 101-108; M. Brinkmann, Macromolecules 2007, 40, 7532-7541; J. C. Wittmann, B. Lotz, Journal of Polymer Science: Polymer Physics Edition, Vol. 19, 1837-1851 (1981); and J. C. Wittmann, B. Lotz, Journal of Polymer Science: Polymer Physics Edition, Vol. 19, 1853-1864 (1981).
However, such process are frequently not compatible or not applicable on an industrial scale or lack the lateral resolution required for the integration of devices in more complex applications (e.g. logical circuits or backplanes).
So as to improve the performance of electronic and optoelectronic devices it is highly desirable that the organic semiconductor materials are present in said devices in a highly ordered structure.
There is therefore a need in industry for a process allowing the deposition of an organic semiconductor material in a highly ordered structure. It is consequently an object of the present application to provide for a process allowing to control the molecular orientation in organic semiconductor thin films. It is a further object of the present application to provide for electronic and/or optoelectronic devices that may be produced on an industrial scale and preferably have anisotropic properties. Furthermore, it Is an object of the present application to provide for a process allowing for the deposition of organic semiconductor material in any geometry and orientation.

Electronic and optoelectronic devices having anisotropic properties and method for their production


A wind turbine blade comprising a system for monitoring the deflection of a wind turbine blade is described. The system comprises a wireless range-measurement system, having at least one wireless communication device located towards the root end of the blade and at least one wireless communication device located towards the tip end of the blade, the communication devices comprising antennas polarized substantially perpendicular to the suction side of the blade and substantially parallel to the leading edge of the wind turbine blade.

Modern wind turbine designs seek to incorporate various blade monitoring systems, in order to provide for reliable and controlled operation of the wind turbine. Such monitoring systems can include blade deflection monitoring systems, which are used to provide an indication of wind turbine blade deflection or flexing during turbine operation. This information can be used to monitor for the risk of a future tower strike by the wind turbine blades, and to perform appropriate controller actions, e.g. blade pitching or turbine braking to minimize or eliminate such risk.
An example of such a deflection monitoring system is provided in U.S. Pat. No. 7,883,316, which describes a deflection monitoring system utilising a wireless communication network, operable to detect the position of various points along the length of the blade, and to determine blade bending from this information.
WO 2014 027032 suggests the use of external transceivers mounted at the root end of the wind turbine blade in communication with transceivers mounted at the tip end of the blade. Based on, for example, radio communication, measures the distance between the transceivers is measured. Positioning of the transceivers is optimized with respect to path loss between the devices.
US 2010/021298 discloses a wireless deflection monitoring system comprising a nacelle communication device.
WO 2009/143848 discloses an optical monitoring system.
However, it has been found that such wireless monitoring systems are vulnerable to various operational factors that may interfere with—and obscure the communication signal, for example, signal reflections, multipath effects, signal attenuation caused by passing through layers of different materials, etc., thereby reducing the precision and effectiveness of the monitoring system.
It is an object of the invention to provide an improved blade deflection monitoring system which is less susceptible to the above-described factors.


A vehicle-top carrier for bicycles which allows bicycles to be attached alongside the vehicle, then pivoted up to its top. A base is attached to the vehicle. A rack pivots from the base about a generally horizontal axis, between a vehicle-top carrying position and a loading position extending horizontally outward from the vehicle. A bicycle can be attached to the underside of the extended rack and pivoted to the vehicle top for transport.

1. Field of Invention
This invention relates to vehicle-top bicycle carriers, specifically to such carriers which facilitate lifting the bicycle to the vehicle top and which have alternative use as a repair stand.
2. Description of Prior Art
A- Loading
As bicycling became attractive to adults as a hobby, a need developed for transporting bicycles to and from riding locations. Bicycles are ungainly things that don't pack easily, so carrying them by car is awkward. At first Bicyclists devised home-made carriers, such as one described in The Complete Book of Bicycling, 1970. This was a common utility-type carrier consisting of two parallel bars attached to the car's rain gutters. Bicycles were carried in an inverted position with their seats strapped to one bar and their handlebars to the other. Alternate bikes were oriented forward and rearward for a compact fit.
As the hobby grew, commercial carriers designed specifically for bicycles became available. Several inventors devised specific ways to support a bicycle on a roof rack, such as those shown in U.S. Pat. Nos. 4,524,893 to Cole (1985), 4,452,384 to Graber (1984), 3,901,421 to Kalicki (1975), and 3,931,919 to Gerber and Benson (1976). None of these, however, address the problem of lifting the bicycle to the rack.
To reduce the difficulty of loading, carriers which attach to lower parts of the vehicle have been devised. An example which carries the bicycle over the trunk is shown in U.S. Pat. No. 5,056,700 to Blackburn and Lee (1991). While this somewhat reduces the lifting, it leaves the bicycles vulnerable to damage from minor traffic accidents. Other carriers which attach to the front or rear bumper leave the bicycles even more vulnerable.
Besides leaving the bicycle vulnerable, the front, rear, and trunk-mounted carriers have another limitation: They can't accommodate the extra length of tandem bicycles. Thus the heaviest and most awkward bicycles can't use the easier-to-load carriers. The problem of loading tandem bicycles is so difficult that many people buy long vans that they would not otherwise want, or expensive specialty trailers.
While several inventions have been made which facilitate loading of car-top carriers, non are particularly applicable to the uniquely delicate and awkward bicycle. Considerable attention has been given to the loading of boats, for example. U.S. Pat. No. 4,603,798 to Griswold (1986) shows loading a boat by lifting one end to a pivot, then lifting the other end and walking it around to a mounting bar. U.S. Pat. No. 4,630,990 to Whiting (1986) describes a roller on which the boat can be placed, then pushed to a mounting position. The invention shown in U.S. Pat. No. 3,885,689 to Grove et al. (1975) lifts the bow until the boat is in a vertical position behind the vehicle, then pivots it to horizontal above the vehicle. Each of these is particularly well suited to the specific problem of boat loading, but not adaptable for loading a bicycle U.S. Pat. Nos. 3,762,587 to Longee (1973) and 3,746,194 to Koenig (1973) show pivoted platforms for raising a boat to the top of a pickup-mounted camper. These are not conveniently adaptable to cars and vans because they require a side-mounted pivot, and the loading position would be awkward for a bicycle. Further, they are too complex, expensive, and cumbersome for use with bicycles.
A somewhat similar device for storing elongated articles on a vehicle is described in U.S. Pat. No. 3,013,681 to Garnett (1961). It shows loading an object such as a ladder by pivoting it from a position extending from the side of the vehicle to an upright position above the vehicle. This appears to require a truck to provide a reasonable pivot location. The device doesn't adapt well to cars and vans. If the pivot axis is above the vehicle the load will be carried too high, and if the pivot is at the vehicle side it is difficult to build. In any case the loading position would be awkward for bicycles. Garnett also shows an alternative where the holder hangs vertically alongside the vehicle and pivots to an upright position above the vehicle. This also appears unsuitable for bicycles; a frame in the lowered position would be awkward for attaching a bicycle, and extremely awkward for attaching more than one.
Several inventions have been made in which a load is placed on a vertical or inclined platform beside the car, then moved to the car top by a combination of rotation and lateral movement. In U.S. Pat. No. 4,826,387 (1989), Audet shows a carrier for ladders, pipes, and the like. It hangs from the side of a roof rack for loading. It is pivoted to horizontal, then pushed toward the center of the vehicle. A similar device for spare tires is shown in U.S. Pat. No. 4,350,471 to Lehmann (1982). U.S. Pat. Nos. 4,682,719 to Ernst et al. (1987) and 4,291,823 to Freeman et al. (1981) work in a similar way, with a luggage-carrier type of frame. The devices described by Ernst in U.S. Pat. No. 4,240,571 (1980) and by Edgerton in U.S. Pat. No. 4,003,485 (1977) accept their load similarly, in an inclined position. In these the load is first pushed up the incline, then pivoted to the vehicle top. None of the inclined-loading devices is convenient for bicycles, because the bicycles would have to be lifted to an awkward attitude for loading. Their complexity and expense are further disadvantages.
B- Field Maintenance
Another problem faced by bicyclists is the difficulty of supporting a bicycle during repairs. In shops bicycles are commonly supported on stands which clamp to their frames and leave the wheels and other moving parts free. This is convenient for adjusting such items as shifters and brakes which require operation of the pedals and wheels.
It is frequently necessary to perform maintenance away from home. Bicycles are relatively delicate because of the need to minimize weight, and therefore need occasional adjustment and repair. In the field it is awkward to perform such maintenance. The old method of turning the bicycle upside down generally can't be used because it damages such parts as brake levers and cables. An attachment for utility roof-top carriers has been invented, U.S. Pat. No. 4,887,754 to Boyer et al. (1989). It attaches to one of the carrier bars of a common roof-top utility carrier, and has a clamp to hold the bicycle frame. This appears to be a satisfactory work stand, but does require purchasing and transporting the special-purpose device. It doesn't attempt to solve the loading problem.

Easy to load vehicle-top carrier for bicycles


A digital deemphasis circuit for the BTSC multichannel television standard includes a square-root extractor, a digital filter having the transfer function F(z)=(b-ac)/(z+a), where a, b and c are constants that determine the frequency response of the digital filter. The digital deemphasis circuit further includes a subcircuit that transforms the output signal from the square-root extractor into three quantities w1, w2, w3 that are applied as multiplicands to three multipliers to control the operation of the deemphasis circuit.

1. Field of the Invention
The present invention is in the field of digital deemphasis circuits for volume-compressed, amplitude-normalized audio signals which are digitized in the two's complement binary system, and, in particular, in the field of digital deemphasis circuits which can be implemented in the audio sections of television receivers designed to receive the Electronics Industries Association (EIA) Broadcast Television Systems Committee (BTSC) multichannel television standard
2. Description of the Related Art
The EIA BTSC is a relatively new standard for transmission of stereo information with the simultaneous opportunity for broadcasting a separate second audio program. The system of this standard is described in detail, for example, in Leslie B. Tyler, et al., "A COMPANDING SYSTEM FOR MULTICHANNEL TV SOUND," IEEE Transactions on Consumer Electronics, November 1984, pp. 633-640. In that article, the individual subcircuits in the described system are presented as analog-signal-processing circuits. Of particular interest in connection with the present invention are FIGS. 5 and 15 and the text of the description on pages 636.639.
It is desirable to use digital circuits in place of analog circuits in modern television receivers. The prior-art analog circuits described in the Tyler, et al., article, like many other analog circuits, cannot be readily converted to corresponding digital circuits for processing signals digitized by an analog-to-digital converter because, in the present case for example, such a direct replacement of analog circuits by corresponding digital circuits would lead to a feedback control loop without delay, which cannot be implemented digitally.