A high-powered sanitary pump includes an impeller (20) axially mounted inside a case (10) and rotating by a motor (M) in order to inhale and discharge fluid by a rotational centrifugal force of the impeller. The impeller (20) has discharge pipes (22) radially connected to the cylindrical inhalation groove part (21) so as to be able to run at low noise and at low vibration and provide high performance with high pump-up head and flow rate while inhaling and discharging fluid not by forced pressure that forcedly pushes the fluid by a conventional rotor blade but by pressure inducing a gentle flow, by high pressure or by vacuum pressure.

The present invention relates to a high-powered sanitary pump for inhaling and discharging fluid by a rotational centrifugal force of an impeller, and more particularly, to a high-powered sanitary pump, which can run at low noise and at low vibration and provide high performance with high pump-up head and flow rate while inhaling and discharging fluid not by forced pressure that forcedly pushes the impeller by a conventional rotor blade but by pressure inducing a gentle flow through discharge pipes radially formed on the circumference of an inhalation groove part and by high pressure.
In general, pumps are divided into various kinds, such as a reciprocating pump, a rotary pump, a centrifugal pump, an axial-flow pump, a friction pump, and others according to structures and uses. The centrifugal pump is one of pumps which are used the most in the industry field.
The centrifugal pump has a passage of a spiral form formed outside a rotating impeller so that fluid entering the central part of the centrifugal pump through an inlet passes the rotating impeller and is discharged to the external circumference while pressure gets higher, and then, passes the spiral passage and is discharged to a pump outlet.
The impeller of the conventional centrifugal pump has rotor blades radially formed on the circumference in a curved form at equal angles and inhales and discharges the fluid by centrifugal force while rotating the rotor blades in a state where the rotor blades abuts on a cover on the front surface of a case. Because the rotor blades of the impeller inhale and discharge the fluid while forcedly pushing the fluid, lots of vibration and noise are generated by frictional shock on the fluid and it is difficult to realize high performance by high pump-up head and flow rate.
As described above, lots of technical efforts to precisely design rotor blades of an impeller have been made in order to reduce vibration and noise caused by the operation of the impeller of the pump and to improve efficiency. However, such efforts have a limit in that they cannot fundamentally solve the problems of vibration, noise and performance since the rotor blades of the impeller forcedly push the fluid.
Patent Document 1: Korean Utility Model Publication No. 20-1991-2819 (Feb. 25, 1992)
Patent Document 2: Korean Patent Publication No. 10-2006-39836 (May 9, 2006)


The disclosed embodiments provide a method, system, and apparatus for facilitating use of a software library project. During operation, the system obtains a set of data associated with use of the software library project, wherein the data comprises a set of dependencies of calls and objects associated with the software library project. Next, the system applies a set of business rules to the data to assess one or more characteristics associated with the software library project. The system then enables use of the data and the one or more characteristics in assessing a health of the software library project.

1. Field
The disclosed embodiments relate to software library projects. More specifically, the disclosed embodiments relate to techniques for performing analysis and assessment of software library projects.
2. Related Art
Source code of newly developed software projects typically calls or references external application programming interfaces (APIs) of existing software libraries. By making calls to the external APIs, developers of the software project may reuse the functionality provided by the corresponding libraries and avoid reimplementation of the functionality in the software project.
However, external APIs and/or software libraries may be in various states of health, reliability, stability, and/or compatibility with the software project. For example, open source libraries may have varying numbers of contributors, commits, ingoing and outgoing dependencies, versions, and/or issues and bugs. Similarly, different versions of the same library may have different features or components, and as a result, may or may not be compatible with the software project.
As a result, development of the software project may be significantly impacted by the selection of specific libraries for use with the software project. For example, the calling of APIs in libraries that are stable, popular, actively managed, and/or otherwise healthy may simplify the development and implementation of the software project. On the other hand, the calling of APIs in libraries that are unstable, buggy, poorly maintained, and/or otherwise unhealthy may incur overhead associated with adapting the software project to changes in the libraries and/or taking on the responsibility of maintaining the libraries.
Consequently, use of software libraries may be facilitated by mechanisms for assessing the health of the software libraries.
In the figures, like reference numerals refer to the same figure elements.

Analysis and assessment of software library projects


A furnace is provided for combusting liquid or gaseous fuel which has a combustion assembly with an internal cavity that has a mixing chamber and a combustion chamber. A flame tube is disposed intermediate the mixing chamber and the combustion chamber. The combustion assembly has an outlet which is adapted to exhaust the gases which result from combustion of the air-fuel mixture. An ignitor rod for igniting the air fuel mixture is also provided.

Furnaces for use in heating the rooms of residential or commercial buildings are well known. Various types of fuel have been used for furnaces, including natural gas, propane and oil. Equally well known in the art, and recently introduced in the market place, are furnaces known as pulse-type furnaces. Such furnaces burn discrete charges of natural gas or propane, and frequently incorporate features which allow the furnace to operate at above 90% efficiency.
An example of a gas-burning pulse type furnace is disclosed in U.S. Pat. No. 4,568,265, issued to Mullen, et al. Such a furnace includes a combustion chamber into which slightly pressurized natural gas and air at atmospheric pressure are discretely introduced as successive charges resulting in the pulsating delivery of an air-fuel mixture. To start the furnace, air is initially forced into the combustion assembly by activating a purge fan and fuel is delivered by opening the natural gas valve. The first charge of the air-natural gas mixture is ignited by a spark ignitor located in the mixer head. As the first charge combusts, one-way flapper valves on the combustion air supply line and the natural gas supply line close, preventing flow of the exhaust gases thereinto, and forcing the flame front and expanding gases to move upwardly through the combustion chamber and out its exit into the tail pipe assembly. As the expanding gases depart the combustion chamber, a vacuum is formed therein which causes a sequential charge of air and fuel to be drawn into the combustion chamber. Due to the vacuum, this sequential charge does not require the purge fan to force combustion air into the chamber. Due to the heat generated by the combustion of the first charge, the successive charge ignites without the sparking of the ignitor. The furnace continues to operate by such pulsating combustion of successively introduced charges until such time that the fuel supply is turned off.
The outlet of the combustion chamber is connected to a tail pipe, whose length helps determine the frequency of the pulses. The tail pipe is formed in several loops extending from the combustion chamber and joins into an exhaust gas decoupler. From the decoupler, the exhaust gases are directed to a secondary heat exchanger disposed between a blower fan and the combustion chamber.
In order to heat the cold air returned from the living space, the blower fan draws air from the living space and forces the air first through the secondary heat exchanger, which causes the temperature of the exhaust gases flowing therethrough to drop below its dew point temperature. This causes the liquid vapor contained in the exhaust gases to condense, thereby transferring the vapor's latent heat of energy to the room air being heated. At the outlet of the secondary heat exchanger, the exhaust gases are approximately 130.degree. F. or less (i.e. generally below the dew point of the flue gas), and condensed liquid is discharged. After being initially heated by passing through the secondary heat exchanger, the room air to be heated is directed around the tail pipe, the exhaust gas decoupler, the combustion chamber, and the mixer head. The combustion chamber includes fins formed on its exterior surface parallel to the flow of air being heated. In this manner, heat is transferred to the room air from the air-fuel mixture combusting inside of the mixer head-combustion chamber, and from the movement of the flue gases through the tail pipe assembly, exhaust decoupler and secondary heat exchanger. The room air then exits the furnace, and is delivered to the living space being heated.
As mentioned above, in order to constrain the flow of the exhaust gases and flame front to one direction, one-way flapper valves are located on the combustion air supply and the natural gas supply. Additionally, there is an air-intake decoupler and a gas decoupler which are designed to minimize the noise produced by the furnace. The flapper valves are located upstream of the combustion assembly a distance sufficient to minimize the amount of heat transferred thereto. The operation of these flapper valves is well known in the industry.
As identified above, there are numerous sources of fuel which may be used with furnaces. However, there have been problems in developing pulse-type furnaces which operate on oil or other liquid fuels. Heretofore, the gas pulse-type furnace described above could not be modified to operate efficiently with oil or other liquid fuels. The problems encountered resulted from the significant differences between the combustion characteristics of liquid fuels and gaseous fuels. As used herein, gas fuel or gaseous fuels refers to any fuel burned in the gaseous state and not only to natural gas.
In addition to the lack of commercially successful and operational liquid fuel pulse furnaces, there are no pulse furnaces which can burn either liquid or gaseous fuels. There are numerous advantages of such a furnace. For example, a manufacturer would only need to manufacture, stock, and sell one type and size of furnace heat exchanger or heat train, and cabinet, which could be used by customers utilizing gaseous fuel as well as by customers utilizing liquid fuel for any particular range of heat input requirements. Particularly, one size heat exchanger and cabinet could cover a range of heating inputs (e.g. btu/hr. requirements) for both liquid and gaseous fuels, a larger heat exchanger and cabinet for a higher range of heating inputs, etc. Additionally, a customer who wished to switch from liquid fuel to gaseous fuel, or from gaseous fuel to liquid fuel can do so very simply and economically, without having to buy a new furnace. Equally advantageous as the furnace which may run on either gaseous fuel or liquid fuel without modifications is the pulse furnace which can be easily adapted to run on either type of fuel by installing certain minor parts designed for the specific type of fuel to be used, while all of the other components of the furnace remain the same, independent of the type of fuel used. A modular furnace (i.e. one in which the components that vary according to the type of fuel combusted are interchangeable with each other) in which the combustion assembly and heat train components remain the same, while the fuel delivery system is modular is particularly advantageous.
In particular, a major drawback has been the dramatic differences in designs between liquid fuel burning furnaces and gaseous fuel burning furnaces. External to the respective combustion assemblies, it is a relatively simple matter to adapt the fuel delivery system of the furnace to the particular type of fuel selected. However, the prior art combustion assemblies cannot be easily adapted to burn either liquid or gaseous fuels, and none of them can successfully burn liquid fuel in a pulsating combustion manner as described above. Clearly, there is a need for a pulse furnace that is easily and inexpensively adaptable to operate on either liquid fuels or gaseous fuels, depending upon the needs of the buyer. The simpler the adaptation of the furnace, and the greater the commonality of components, the easier and more practical it is for a manufacturer to stock and convert such furnaces, as well as providing corresponding reduced costs to the ultimate consumer and the ability to switch from one fuel to another.


The kit for suppressing drug craving K is used by connecting an instrument for suppressing drug craving 1 to a syringe 2 and the instrument for suppressing drug craving 1 has a cylindrical housing 11, a pouch 12 provided in the housing and containing pseudo-blood B and a connecting member 13 with which the distal end of a syringe is coupled and which cause the syringe to communicate with the interior of the pouch. When the syringe accommodating pseudo-drug M is connected to the instrument and the plunger is moved forward (pseudo-priming), the pseudo-drug M flows into a pouch and the pouch inflates (FIG. 2(b)), and if the plunger 4 is pulled back from this condition, the pouch 12 deflates and the pseudo-blood B flows back from the pouch 12 to the syringe 2 (flashback) (FIG. 2(C)).

Conventionally, therapy of drug addicts of repeated abuse of drugs including stimulant drugs is conducted, but there are no established therapeutic methods yet and various therapeutic methods are being tried.
Among such therapeutic methods, there is a proposal of a method of repeating a process of giving conditional stimuli suggestive of use of a drug to a drug addict and actually preventing the drug addict from administering the drug to cause the drug addict to lose any significance of the conditional stimuli and eventually suppress conditioned reflex (Non-Patent Document 1).
According to this Non-Patent Document 1, in the process from acquiring the drug to actually administering the drug, looking at the drug dealer's face, the pack containing the drug or syringe or the like, the drug addict is exposed to conditional stimuli and these conditional stimuli form a conditioned reflex circuit in the brain.
Therefore, although the drug addict does not administer the drug, the drug addict is believed to crave for the drug by means of conditioned reflex when he/she looks at the drug itself, the drug dealer's face, the pack containing the drug or syringe or the like.
Repeating the process of giving such conditional stimuli to the drug addict and actually not allowing him/her to administer the drug is expected to make less the significance of the conditional stimuli and thereby suppress the craving for the drug by means of conditioned reflex.
Here, in the above described conditional stimuli, examples of those having a great influence on the drug addict include the act itself of the drug addict operating the syringe and administering the drug, causing the blood to flow back into the syringe (flashback) to confirm whether or not the needle is inserted into the blood vessel and visually recognizing the insertion.
To treat by giving such conditional stimuli to the drug addict, a saline instead of the drug may be put into the syringe to let the drug addict administer this saline or visually recognize the backflow of the blood into the syringe. Non-Patent Document 1: Monthly "Psychiatry" Vol. 8, No. 6, issued on Jun. 28, 2006, "Treating Idiosyncrasy of Stimulant Drug Addiction" by Shinji Hirai

Instrument for suppressing drug craving and kit for suppressing drug craving


The present application discloses a wireless charging device. The wireless charging device comprises: a portable container, the portable container being provided with an induction coil and a mounting base for mounting a mobile device, when the mobile device is mounted in the mounting base, the induction coil and the mobile device forming a closed loop; and a wireless charging terminal, the wireless charging terminal comprising an electrified coil, the electrified coil being electrified with an alternating current so as to generate a magnetic field, when the induction coil is located in the magnetic field, an induction current will be generated in the induction coil and the mobile device can be charged.

At present, people use mobile devices very frequently, such that the mobile devices have to be charged regularly.
The charging method for the mobile device in the prior art is mainly wired charging, i.e., connecting the mobile device to the socket through a charging wire. On the one hand, this charging method is limited by the number of spare sockets, on the other hand, the user has to connect the mobile device to the socket specially, which is inconvenient for use.

Wireless charging device, portable container, and wireless charging terminal

BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.


A multi-tier scheduling approach includes a first tier comprising virtual cluster allocators that receive scheduling requests from processes and aggregate those requests and provide them to a second tier, namely a single resource distributor for the entire set of computing devices. The resource distributor, based on the requests from virtual cluster allocators, and also from information received from the computing devices themselves, generates a flow graph to identify an optimal scheduling of the assignment of resources to specific ones of the virtual clusters. Each virtual cluster allocator then, based on the assignment of resources assigned to it by the resource distributor, solves its own flow graph to identify an optimal scheduling of processes on the resources assigned. The scheduling of processes is performed iteratively by initially assigning resources to those processes having a high priority, and then, in subsequent iterations, assigning opportunistic resources to those processes having a lower priority.

Not every task that a user seeks to have performed by a computing device can be efficiently performed by that user's personal computing device. Instead, collections of powerful, multi-processor computing devices can provide greater processing capabilities, thereby enabling users to perform tasks that could not efficiently be performed by their personal computing devices, without having to themselves purchase such costly computing hardware. Typically, groups of users share such collections of computing devices such that each user can have access to the collection of computing devices to perform complex and time-consuming data processing. The more users' data processing that can be accommodated by a collection of computing devices, the more value can be realized from such a collection. Consequently, it is desirable to utilize as much of the data processing capability of a collection of computing devices as possible without negatively impacting those users who seek to utilize such collection of computing devices to perform data processing.
Unfortunately, scheduling the processing of users' tasks across multiple computing devices is often not straightforward. For example, some data processing requested by users involves the reading or writing of large quantities of data that may not be able to be efficiently performed if the data processing is being performed by a computing device that is remote from the computer readable storage medium on which such data is to be read from or to be written to. As another example, the data processing requested by users can typically be broken down into individual jobs and processes that can be scheduled individually. If delays are introduced between the performance of one process and the performance of the subsequent process then, over the course of performing a single task, the accumulated delay can quickly become unacceptably large. As yet another example, to provide users with a minimum threshold of service, each user can be guaranteed a certain amount of data processing capability that can be provided by the collection of computing devices. In many cases, however, not every user of the collection of computing devices will be simultaneously utilizing their guaranteed data processing capability. Consequently, in those instances, much of the data processing capabilities of the collection of computing devices can remain unutilized, resulting in underutilization of the overall system, and the attendant inefficiencies that such underutilization introduces. However, were the available processing capability distributed to those users currently desiring it, then it may not be available for other users to whom it was guaranteed.
For small collections of computing devices, the scheduling of processes to be executed by those computing devices can be solved through known mathematical strategies for solving flow graphs. More specifically, each process to be executed can be modeled as a node, or "vertex" in a flow graph, as can each computing device on which such a process could be executed. However, as will be recognized by those skilled in the art, the complexity of such flow graphs, and the efficiency with which they can be solved, is proportional to the number of edges in the flow graph, where each connection between a vertex is an "edge". Thus, for example, were a process agnostic as to the computing device on which it was executed, an edge would exist from such a process to each computing device. The complexity of such a flow graph could, theoretically, be as high as the number of processes to be scheduled multiplied by the number of computing devices on which such processes could be executed. As can be seen, such a flow graph can quickly become too complex to be solved efficiently as the number of computing devices and the number of processes to be scheduled increases beyond a few dozen. Consequently, such an approach is not practical for modern data processing computer clusters that can comprise thousands of computing devices.

Scalable scheduling for distributed data processing


The present invention features an elegantly-mounted pinwheel comprising alternating holographic red and silver non-metallic tape-like material. The pinwheel uses connector bolts and hexagonal coupling nuts to be mounted or positioned directly onto various components of a power pole or utility pole system such as bushings, fuse cutouts, regulators, reclosures, lightning arresters, or underground primary dips. The invention will deter animals such as birds and squirrels from scaling or landing on the power pole or utility pole system when the invention is properly mounted. The invention takes advantage of the alternating colors of the pinwheel to scare the animals. The present invention requires no housing, rotors, drums, or support plates. The invention does not rely on sound, and it requires no electricity or motor. The stainless steel hex standoff coupling nut comes preferably in ⅜″ and can be ordered in different sizes to accommodate the device.

For a transformer bushing to work successfully over a period of years, its insulation material must remain effective in design, composition, and upkeep. Bushings sometimes fail and discharge due to the slow and progressive degradation of the insulation over years of energized service. When bushing contamination degrades the insulation, the voltage will conduct to the nearest earthed material. This process is called "tracking," and causes burning and arcing. Keeping bushings clean is therefore a key factor in their survival. At present, there is great interest by the electricity supply industry in monitoring the condition of high voltage bushings.
Birds and bird droppings are a significant degrader of bushings, and current bird scarers/repellers often cause as many problems than they ameliorate. Snap-on shed-style mount guards collect dirt and contaminate bushings. Bees also build hives in these shed-style mounts, which can lead to quicker destruction of the guards.
Some primitive animal repellants are rubber hose-type protective devices. These devices are easily moved out of place by weather, animals, or line repair workers. They also collect dirt and, when drenched with rain, create mud piles on top of the bushings.
The electricity supply industry has recognized the bird-deterring quality of flapping wing-type devices. For example, the invention of U.S. Pat. No. 6,557,482 has mounted fins which respond to wind currents by rotating. The invention of '482, however, requires a rotor and at least one separate support member. The invention of '482 also fails to utilize the scaring-effect of reflective, alternating colors. The invention of '482 also relies on sound.
The invention of U.S. Pat. No. 4,131,079 relies on a pair of large, thin, light weight, light-reflective discs to scare and repel animals. It is rotatably suspended from a remote end of a wire which is suspended from a vertically-extending post.
The invention of patent '079 structurally requires a post and wires. The invention of '079 does not utilize the scaring-effect of alternating colors, and its main scaring function is limited to the angles of light reflecting from its two circling reflective cups.
The invention of Chinese Patent CN20387937U uses flaps, but it comprises a central drum and support plates. In addition, '937 relies on sound as well as reflective light. Nor does the invention of '937 discuss detailed shapes of the pinwheel fins so as to capture maximal angles of visibility.
Other examples of wind-driven flapping devices include U.S. Pat. No. 4,597,357, U.S. Patent Application 2013/0014692A1, Chinese Patents CN203884532U CN203827937U, CN201178650Y, CN201256600Y, European Patent Publication WO1997011600A1 and a 2013 YouTube publication "How to make a bird scaring windmill from a plastic bottle!"
These inventions all either require fixed attachment means like posts or boxes, require support members, rotors, drums, plates or wires, rely on sound or require electronic prompts, use only one color or uni-directional fins, or they fail to alternate colors and angles of visibility.
For the foregoing reasons, there is a need for a reliable, durable, wind-powered device for powerline preservation made from sustainable material that is easy to service and maintain.
More Reference to, and discussion of, the foregoing background is not presented as prior art and is respectfully submitted that none of the above-indicated patents and patent applications disclose, teach, suggest, show, or otherwise render obvious, either singly or when considered in combination, the invention described and claimed herein.

Rotating fin device for powerline preservation


The systems and methods may identify order requests from internal messaging or collaboration systems. Once order requests are identified, the systems and methods determine purchase orders based on the requests, and generate tokens (e.g., virtual credit cards) specific to a purchase order, to be used by the requestor to complete the purchase of requested items or services. Once the tokens are used, the systems and methods may then track the purchases in various databases, providing the organization with various views or insights into their employee's expenditures.

Purchasing departments in companies and other organizations handle many different tasks—from provisioning supplies to authorizing purchases of computing and other infrastructure resources. These task may be simple or complex, but often have associated procedures that employees follow to initiate and complete a purchase. For example, an employee may fill out various order forms and approval documentation before submitting a request for an item, service, or other expenditure.
Further, organizations may have and/or apply a complex set of rules to such processes. The rules may identify, among other things, the level of authorization assigned to an employee or group, the types of purchases, budgets or general approval processes, and so on. As an organization grows, its ability to track and efficiently manage the many different ongoing processes may decrease, leading to inefficiencies of workflows, poor utilization of its internal resources, and costlier operations, among other drawbacks.
Therefore, it would be advantageous to an organization, company, or entity to have access to an efficient and simplified system that manages its internal purchasing operations.
The drawings have not necessarily been drawn to scale. Similarly, some components and/or operations may be separated into different blocks or combined into a single block for the purposes of discussion of some of the embodiments of the present technology. Moreover, while the technology is amenable to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail below. The intention, however, is not to limit the technology to the particular embodiments described. On the contrary, the technology is intended to cover all modifications, equivalents, and alternatives falling within the scope of the technology as defined by the appended claims.

System and method of purchase request management using plain text messages


A pulse wave measuring device includes a light emitter unit, a light receiver unit, a pulse wave measuring unit and a contact portion. The light receiver unit receives reflected light, which is reflected from a finger after transmission of the light from the light emitter unit. The pulse wave measuring unit measures a pulse wave based on the reflected light, which is received with the light receiver unit. The finger contacts the contact portion at a time of measuring the pulse wave. The contact portion has a recess, which receives at least a portion of the finger at the time of measuring the pulse wave, and a protrusion is provided in an inside of the recess.

The following type of pulse wave measuring device has been known. Specifically, the known pulse wave measuring device includes a portion (hereinafter referred to as a contact portion), against which a fingertip of a user contacts at the time of measuring the pulse wave, a light emitting element and a light receiving element. The light emitting element emits the light to the fingertip that contacts the contact portion. The light receiving element receives a reflected light, which is reflected from the fingertip, or a transmitted light, which is transmitted through the fingertip. The pulse wave measuring device measures the pulse wave based on an oscillatory change in the amount of light that is received through the light receiving element (see, for example, JPH07-213498A).
In order to accurately measure the pulse wave, the fingertip needs to contact the contact portion with an appropriate pressing force. In the case of the previously proposed pulse wave measuring device, it is difficult for the user to sense a location of the contact portion, and the fingertip sometimes deviates from the contact portion. Furthermore, in the case of the previously proposed pulse wave measuring device, the pressing force for pressing the fingertip against the contact portion sometimes becomes excessively large or excessively small.


In a replacement gate approach, the dielectric material for laterally encapsulating the gate electrode structures may be provided in the form of a first interlayer dielectric material having superior gap filling capabilities and a second interlayer dielectric material that provides high etch resistivity and robustness during a planarization process. In this manner, undue material erosion upon replacing the placeholder material may be avoided, which results in reduced yield loss and superior device uniformity.

1. Field of the Invention
Generally, the present disclosure relates to sophisticated integrated circuits including transistor elements comprising gate structures formed on the basis of a high-k gate dielectric material and a metal-containing electrode material.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry including field effect transistors, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, the scaling of the channel length, and associated therewith the reduction of channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice in the near future for circuits designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows performing subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material of the gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously reduced to improve switching speed and drive current capability. Since the transistor performance in terms of switching speed and drive current is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be ensured. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel dimension. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current, while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although generally usage of high speed transistor elements having an extremely short channel may be substantially restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with thermal design power requirements for performance driven circuits.
Therefore, replacing silicon dioxide-based dielectrics as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide-based gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance based on the same thickness as a silicon dioxide-based layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, in combination with other metals, may be formed so as to connect to the gate dielectric, thereby substantially avoiding the presence of a depletion zone. Since the threshold voltage of the transistors, which represents the voltage at which a conductive channel forms in the channel region, is significantly determined by the work function of the metal-containing gate material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
Providing different metal species for adjusting the work function of the gate electrode structures for P-channel transistors and N-channel transistors at an early manufacturing stage may, however, be associated with a plurality of difficulties, which may stem from the fact that a complex patterning sequence may be required during the formation of the sophisticated high-k metal gate stack, which may result in a significant variability of the resulting work function and thus threshold of the completed transistor structures.
For this reason, in some approaches, the initial gate electrode stack may be provided with a high degree of compatibility with conventional polysilicon-based process strategies and the actual electrode metal, possibly in combination with a high-k dielectric material, and the final adjustment of the work function of the transistors may be accomplished in a very advanced manufacturing stage, i.e., after completing the basic transistor structure. In a corresponding replacement gate approach, a standard polysilicon or amorphous silicon material may be patterned on the basis of well-established advanced lithography and etch techniques. After patterning the gate electrode structure, conventional and well-established process techniques for forming the drain and source regions having the desired complex dopant profile are typically performed. After any high temperature processes, the further processing may be continued by the deposition of an interlayer dielectric material, such as silicon nitride in combination with silicon dioxide and the like.
In this manufacturing stage, a top surface of the gate electrode structures embedded in the interlayer dielectric material has to be exposed, which is accomplished by chemical mechanical polishing (CMP). The polysilicon material exposed during the CMP process is then removed and, thereafter, an appropriate masking regime may be applied in order to selectively fill in an appropriate metal for any type of transistors.
Although, in general, this approach may provide advantages in view of reducing process-related non-uniformities in the threshold voltages of the transistors, the complex process sequence for exposing and then removing the placeholder material and providing appropriate work function materials for the different types of transistors may also result in a significant degree of variability of the transistor characteristics, which may thus result in offsetting at least some of the advantages obtained by the common processing of the gate electrode structures until the basic transistor configuration is completed.
For example, an efficient removal of the polysilicon material may have a significant influence on the overall characteristics of the replacement gate, i.e., on the provision of appropriate work function metals for the N-channel transistor and P-channel transistor and the subsequent deposition of the actual metal-containing electrode material.
Typically, a dielectric cap material may be preserved throughout the entire processing of the semiconductor devices, which may be advantageous in terms of maintaining integrity of the gate electrode structure prior to replacing the polysilicon material. It turns out, however, that the exposure of the top surface of the polysilicon material may represent a very critical process phase during the replacement gate approach, in particular when a dielectric cap layer, for instance provided in the form of a silicon nitride material, is present on the polysilicon material, as will be explained in more detail with reference to FIGS. 1a-1b.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an advanced manufacturing stage. As illustrated, the device 100 comprises a substrate 101, above which is formed a semiconductor layer 102. The semiconductor layer 102 is typically provided in the form of any appropriate semiconductor material, such as silicon and the like, wherein, if a silicon-on-insulator (SOI) architecture is considered, a buried insulating material (not shown) is typically formed directly below the semiconductor layer 102. In other cases, the semiconductor layer 102 represents a portion of a crystalline semiconductor material of the substrate 101, if a bulk architecture is considered. The semiconductor layer 102 comprises a plurality of active regions, wherein, for convenience, a single active region 102a is illustrated in FIG. 1a. Generally, an active region is to be understood as a semiconductor region in and above which one or more transistors are formed. In the example shown in FIG. 1a, a plurality of transistors 150 are formed in and above the active region 102a and may represent transistors of the same conductivity type in a device region in which a plurality of densely packed transistors are required. The transistors 150 typically comprise gate electrode structures 160, the final configuration of which is still to be established on the basis of a replacement gate approach, as discussed above. The gate electrode structures 160 in this manufacturing stage comprise a dielectric material 161, such as a silicon dioxide material and the like, in combination with a polysilicon material 162, which is to be considered as a placeholder material since at least the material 162 is to be removed in a later manufacturing stage. Moreover, a sidewall spacer structure 164 is typically provided which, for instance, enables a desired lateral and vertical profiling of drain and source regions 151. Furthermore, as discussed above, frequently, a dielectric cap layer or cap layer system 163 is provided, which has been removed during the subsequent processing, while in other cases the cap layer 163 may be omitted. Furthermore, a contact level 120 comprising an interlayer dielectric material 121 is provided so as to laterally enclose the gate electrode structures 160. It should be appreciated that, in the manufacturing stage shown, a top surface of the polysilicon material 162 may be exposed, as is required for the subsequent replacement of the material 162 with at least a metal-containing electrode material.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of the following processes. The active region 102a is formed on the basis of well-established process techniques, for instance forming isolation structures (not shown), thereby defining the lateral size, position and shape of any active regions in the semiconductor layer 102. Prior to or after forming the corresponding isolation structures, the basic doping characteristics may be adjusted, for instance by ion implantation in combination with appropriate masking regimes, as is well known in the art. Next, the gate electrode structures 160 are formed by depositing or otherwise forming the dielectric material 161, followed by the deposition of the placeholder material 162, for instance in the form of a polysilicon material. Typically, additional hard mask material and other sacrificial materials are to be provided in order to enable the patterning of the resulting layer stack on the basis of sophisticated lateral dimensions as are typically required in advanced semiconductor devices. For example, a critical dimension of the gate electrode structures 160 may be 50 nm and significantly less. For example, the resulting layer stack may also comprise the dielectric cap material 163, for instance in the form of silicon nitride and the like, which may be used as a hard mask material upon patterning the underlying material layers based on sophisticated lithography and etch techniques. Thereafter, a portion of the drain and source regions 151 may be formed, for instance by ion implantation, selective epitaxial growth techniques and the like, depending on the overall process strategy and the device requirements. It should be appreciated that additional processes may be implemented, for instance in order to incorporate strain-inducing semiconductor alloys (not shown) and the like. Moreover, the spacer structure 164 may be completed followed by further implantation processes, if required, in order to establish the final vertical and lateral dopant profile of the drain and source regions 151. This may also involve the application of anneal processes based on any appropriate process techniques. If required, additional metal silicide regions may be formed in the drain and source regions 151, which may also be accomplished on the basis of the sidewall spacer structure 164, wherein the dielectric cap layer 163, if still in place, may efficiently prevent silicidation of the placeholder material 162. In other cases, the formation of a metal silicide in the drain and source regions 151, or at least in a portion thereof, may be accomplished in a later manufacturing stage.
Next, the contact level 120 comprising the interlayer dielectric material 121 is formed, for instance by depositing the dielectric material 121 so as to attempt to substantially completely fill the spaces between the closely spaced gate electrode structures 160. As discussed above, in sophisticated semiconductor devices, the packing density is significantly increased by reducing the critical dimensions and thus also reducing the distance between neighboring circuit components, wherein, in particular, in densely packed device areas such as memory areas and the like, the resulting high aspect ratio created by the closely spaced gate electrode structures 160 may result in deposition-related irregularities, such as the formation of voids in the material 121 between the closely spaced gate electrode structures 160.
As is well known, particularly silicon dioxide is a well-established interlayer dielectric material which may be deposited on the basis of a plurality of deposition recipes, which may have significant differences with respect to their process results. For example, well-established silicon dioxide deposition recipes are available which provide a substantially flow-like deposition behavior, which results in a reliable filling of openings of even high aspect ratio, such as the spaces between the closely spaced gate electrode structures 160. Other deposition techniques for providing a silicon dioxide-like material with superior gap filling capabilities is the spin coating of a dielectric base material having a low viscous state, wherein subsequently a heat treatment may be performed so as to obtain a silicon dioxide-like material upon initiating a material modification and removing any solvents therefrom. It turns out, however, that the deposition techniques providing the superior gap filling capability result in the generation of a silicon dioxide-like material of inferior density and thus quality with respect to the further processing of the semiconductor device 100. That is, typically any such materials may have a reduced density and/or a significantly reduced etch resistivity with respect to a plurality of efficient wet chemical etch recipes, which are typically used for removing contaminants, etching silicon material and the like. Similarly, these deposition recipes providing the superior gap filling capabilities may also result in a material having a significantly reduced resistivity during well-established polishing processes, which are frequently used for removing an excess portion 121e of the interlayer dielectric material 121 in order to finally expose the placeholder material 162.
On the other hand, process techniques are available in which silicon dioxide-like materials with superior density and thus enhanced etch resistivity and mechanical strength may be provided, however, with a pronounced tendency of producing voids upon filling high aspect ratios, such as the spaces between the densely packed gate electrode structures 160. Since any such voids may result in significant device failures upon further processing of the semiconductor device 100, conventional process strategies rely on superior gap filling capabilities and attempt to cope with inferior etch resistivity and/or increased removal rate during a polishing process.
Thus, the material 121 may be provided in a substantially void-free manner on the basis of spin coating, flow-like CVD deposition techniques and the like. Thereafter, the excess material 121e is removed during a planarization process 103, which comprises one or more polishing steps, wherein, at least in a final phase, the dielectric cap layer 163 is to be removed and subsequently the surface of the polysilicon material 162 is exposed. As discussed above, due to the inferior mechanical characteristics of the material 121, however, the polishing rate may be increased, thereby creating recesses 121r laterally adjacent to the gate electrode structures 160, which may be particularly pronounced when the cap layer 163 has to be removed in a final phase of the planarization process 103, since typically it is extremely difficult to obtain a similar removal rate for silicon nitride and silicon dioxide-based materials.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, the gate electrode structures 160 are now provided in the form of high-k metal gate electrode structures and comprise a high-k dielectric material 165 in combination with two or more metal-containing electrode materials 166, 167. For example, the material 166 may represent any appropriate metal-containing material for adjusting an appropriate work function of the gate electrode structures 160, while the material 167 may be provided in the form of a highly conductive electrode material such as aluminum, aluminum alloys and the like.
The device 100 as shown in FIG. 1b may be formed on the basis of well-established replacement gate strategies in which at least the placeholder material 162 is removed, for instance by using highly selective wet chemical etch recipes, for instance based on tetra methyl ammonium hydroxide (TMAH) or any other ammonium-based etch chemistries. In other cases, in addition to or alternatively, plasma-based etch recipes may be used. During the removal process, the material 161 (FIG. 1a) may act as an efficient etch stop material, which may have to be removed in a further etch process. Consequently, during this process sequence, the material 121 is exposed to various etch atmospheres, thereby also contributing to surface irregularities due to the inferior etch resistivity of the material 121. Furthermore, upon depositing various gate dielectric materials of the layer 165 and various work function adjusting metal layers 166, which may have to be partially removed in some of the gate electrode structures, additional exposure to reactive etch atmospheres may occur, thereby further damaging the material 121. Finally, the actual fill metal 167 is deposited by any appropriate deposition techniques and excess materials of the previous process sequence are removed, for instance on the basis of CMP and the like. Due to the damaged material 121 and the previously created recesses 121r (FIG. 1a), there is a significant probability that metal residues 167r remain on the material 121, wherein at least some of these residues 167r may cause leakage paths or even short-circuits between neighboring gate electrode structures or between contact elements still to be formed in the material 121 in a later manufacturing stage.
Consequently, although a replacement gate strategy provides a very efficient manufacturing process for providing high-k metal gate electrode structures in a late manufacturing stage, i.e., after performing any high temperature processes, significant yield losses may occur during conventional process strategies due to significant damage of the interlayer dielectric material 121 prior to and upon replacing the placeholder material with at least a metal-containing electrode material.
In view of the situation described above the present disclosure relates to manufacturing techniques and semiconductor devices in which a replacement gate approach may be applied while avoiding or at least reducing the effects of one or more of the problems identified above.

Replacement gate approach for high-k metal gate stacks by using a multi-layer contact level


Described examples include a hybrid circuit having a component. The component has a first conductive element on a substrate having a configuration and having a first periphery and having an extension at the first periphery. The component also has a dielectric on the first conductive element. The component also has a second conductive element having the configuration on the dielectric that is proximate to and aligned with the first conductive element, and has a second periphery, the extension of the first conductive element extending past the second periphery.

Circuit designers use integrated and hybrid devices in some very harsh environments. For example, some industrial applications require devices to withstand voltages of 600V or more. The small size of integrated devices and hybrid devices makes them vulnerable to damage from such high voltages. This vulnerability occurs even if the devices themselves are not operating at high voltages. Stray voltage spikes and strong fields can cause damage.
One way of addressing these problems is the use of galvanic isolation. In galvanic isolation one integrated or hybrid circuit communicates with another through a transformer or a capacitor. The circuits communicate by altering the current through the transformer or the voltage on a capacitor. In some applications, a transmitting circuit applies a carrier frequency that is encoded with a digital signal, which the receiving circuit then decodes. Because there is no conductive connection between the circuits, stray voltage spikes in one circuit are not conducted to the other circuit.
In some hybrid devices, integrated circuits use galvanic isolation using solid state transformers or capacitors. Sometimes the transformer or capacitor is formed on one of the integrated circuits. Even with a separate passive device, voltage spikes can be transmitted through one of the circuits to the passive device. In addition, in the harsh environments where these circuits are employed, strong electric fields from outside of the circuits can occur. Even if the passive component does not break down, exposure to high fields can alter characteristics of a dielectric in a transformer or capacitor. This can make the dielectric more susceptible to breakdown under a subsequent high field or can alter the electrical parameters of the passive device to the point where the connected circuits can no longer reliably communicate. Therefore, it is desirable to mitigate the effects of high electric fields on the passive components.

Passive components with improved characteristics


A storage system comprises a plurality of storage nodes and a controller coupling unit interconnecting controllers within the storage nodes. A memory in the controller has a plurality of shared memory areas each associated with a combination of one CPU core with one logical unit controller. When a network controller of a first storage node receives a host command addressed to a logical unit of a second storage node, the CPU core of the first storage node stores the host command in the shared memory area associated with the logical unit controller of the second storage node. The logical unit controller of the second storage node acquires the stored host command in the shared memory area via the controller coupling unit.

The present invention relates to a storage system, and relates in particular to technology for switching between processors that perform processing in response to commands in a storage system.
Data processing systems including a host computer and a storage system are utilized in various applications. Here, a storage system refers to a system composed of at least one storage node that has disks for storing data and a controller for controlling the disks. Typically, within a storage node there are configured one or a plurality of logical memory areas (called "logical units" for example) with the disks. The host computer issues a command addressed to a logical unit configured within a storage node of the storage system, while executing data processing tasks. Within the storage node that received the command from the host computer, a processor within the controller (e.g. a CPU core) carries out processing in response to the command.
In a storage system of this kind, an excessive load may be imposed on a particular processor within a particular storage node, due to an increase in the amount of data stored in a logical unit, or an increase in access frequency by the host computer.
Technology for migrating data from a logical unit in a first storage node to a logical unit in a second storage node in a storage system has been disclosed (e.g. JP2000-187608A). With this technology, after data has been migrated, commands from the host computer are handled by the second storage node. Thus, processing in response to a command from the host computer being executed by the processor in the first storage node prior to data migration will, after data migration, now be executed by the processor in the second storage node. In the event of excessive load on a particular processor as mentioned above, by switching among processors executing processing in response to commands from the host computer in this way, the processing load can be distributed throughout the system.
A problem with the conventional technology discussed above is that, when switching between processors executing processing in response to a command, it is necessary to migrate the data and to modify various settings in association therewith, making processing extremely complex.

Storage system with designated CPU cores processing transactions across storage nodes


A distributed antenna system includes a plurality of head-end units for each receiving mobile communication signals from at least one corresponding base station, a hub unit communicatively coupled to the plurality of head-end units, and a plurality of remote units communicatively coupled to the hub unit, wherein the hub unit configured to distribute the mobile communication signals received from each of the plurality of head-end units to the plurality of remote units, wherein each of the plurality of remote units is remotely disposed to transmit the distributed mobile communication signals to a terminal in service coverage, and wherein the hub unit includes a mixing processing stage configured to perform digital mixing processing on the mobile communication signals respectively received from the plurality of head-end units, and a crest factor reduction (CFR) module disposed posterior to the mixing processing stage, with respect to a signal transmission direction.

1. Field
The inventive concept relates to a distributed antenna system (DAS), and more particularly, to a DAS including a crest factor reduction (CFR) module.
2. Description of Related Art
Crest factor reduction (CFR) is frequently used as a technique for reducing a peak-to-average power ratio (PAPR) of a signal. Particularly, in a system using a digital pre-distorter (DPD), the CFR is implemented at the front end of the DPD.
In a distributed antenna system (DAS), the CFR is generally implemented at the front end of a DPD in a remote unit (RU) among node units constituting the DAS. However, when the number of RUs is large, the complexity and cost for implementing the RUs may increase. Moreover, when it is required to perform multi-band signal processing on the RUs in the DAS, the CFR is required by the number of bands, and therefore, the complexity for implementing the RUs considerably increases.

Distributed antenna system including crest factor reduction module disposed at optimum position


A floating magnetic head used in a hard disk drive has a substantially rectangular slider made of a non-magnetic material. The slider has rails mounted on a surface of the slider that is opposite to a magnetic recording medium to produce a floating force. A cut-out is formed in the slider, for example, at one corner of the slider for providing access for winding a coil and a bridge spans the cut-out portion. A head core having a read/write gap is bonded to an outer periphery of the slider adjacent the cut-out portion. In particular, a winding portion of the head core is bonded to the bridge spanning the cut-out portion for receiving a portion of a winding coil. Accordingly, if a large force acts on the head core during winding of the coil or mounting of the floating magnetic head to a suspension, the head core can withstand the force without incurring damage or adversely affecting its ability to function.

A floating magnetic head of the composite type which has been heretofore frequently used is generally indicated by reference numeral 1 in FIG. 8. This head 1 comprises a substantially rectangular slider 2 made of a nonmagnetic material of a high density such as calcium titanate ceramic. Rails 3 and 4 are mounted on the top surface of the slider 2 which is opposite to a magnetic recording medium (not shown) to produce a floating force. A slit 5 of a given depth is formed at one corner of the slider 2 which lies under one rail 3. The slit 5 extends in a direction perpendicular to the direction in which the medium moves. A thin head core 7 which has a read/write gap 6 and acts to read and write information to and from the medium is inserted in the slit 5. The core 7 is sealed by glass or other bonding means. One corner of the slider 2 is cut out to form a window 8 that permits winding of a coil 9. The window 8 extends along the rails 3 and 4 to two side surfaces of the slider 2. The coil 9 is wound on that portion of the head core 7 which faces the window 8.
The floating magnetic head of the composite type shown in FIG. 9 is disclosed in detail in copending U.S. application Ser. No. 08/059,297 to Egawa et al. head, indicated by 1a, comprising a thinned head core 7 to reduce eddy current loss at high frequencies. The head core 7 is adhesively bonded to the outer periphery of a nonmagnetic slider 2a. This floating magnetic head la is characterized in that the head core 7 can be thinned by a known machining technique such as grinding, lapping, or polishing after the core is bonded. This is permitted by the fact that one side of the core 7 is exposed. The head core 7 can be made thinner than the head core of the floating magnetic head 1 described already in connection with FIG. 8.
However, in the floating magnetic head la shown in FIG. 9, when the coil 9 is wound or the head is mounted to a suspension in a following step, or when the hard disk drive is mounted or otherwise treated, distortion or impact directly acts on the head core 7. As a result, the core 7 may get damaged or the characteristics may be deteriorated. Furthermore, the coil 9 on the head core embodiment shown in FIG. 9 has a tendency to be disarranged more easily than the floating magnetic head 1 shown in FIG. 8. The disarranged coil may come into contact with the disk, resulting in electrical leakage, breakage, or other trouble. In accordance with U.S. application Ser. No. 08/059,297, additional embodiments, for example, a bobbin (not shown) are used to prevent the coil from being disarranged or to prevent layer short between the wire of the core and the head core. If the bobbin is attached to the very thin head core, there arises the possibility that the core 7 is damaged.

Floating magnetic head with a head core-reinforcing portion


A spin-transfer-torque magnetoresistive memory comprises apparatus and method of manufacturing a three terminal magnetoresistive memory element having highly conductive bottom electrodes overlaid on top of a SHE-metal layer in the regions outside of an MTJ stack. The memory cell comprises a bit line positioned adjacent to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two highly conductive bottom electrodes overlaid and electrically contacting on top of a SHE-metal layer in the outside of an MTJ region and to supply a bi-directional spin Hall effect recording current, and accordingly to switch the magnetization of the recording layer. Thus magnetization of a recording layer can be readily switched or reversed to the direction in accordance with a direction of a current along the SHE-metal layer by applying a low write current.

1. Field of the Invention
This invention relates generally to a three-terminal spin-transfer-torque magnetic-random-access memory (MRAM) element having spin hall effect writing and a method of manufacturing the same magnetoresistive element.
2. Description of the Related Art
In recent years, magnetic random access memories (hereinafter referred to as MRAMs) using the magnetoresistive effect of magnetic tunnel junction(s) (MTJ(s)) have been drawing increasing attention as the next-generation solid-state nonvolatile memories that can also cope with high-speed reading and writing. A ferromagnetic tunnel junction has a three-layer stack structure formed by stacking a recording layer having a changeable magnetization direction, an insulating tunnel barrier layer, and a fixed layer that is located on the opposite side from the recording layer and maintains a predetermined magnetization direction. Corresponding to the parallel and anti-parallel magnetic states between the recording layer magnetization and the reference layer magnetization, the magnetic memory element has low and high electrical resistance states, respectively. Accordingly, a detection of the resistance allows a magnetoresistive element to provide information stored in the magnetic memory device.
Typically, MRAM devices are classified by different write methods. A traditional MRAM is a magnetic field-switched MRAM utilizing electric line currents to generate magnetic fields and switch the magnetization direction of the recording layer in a magnetoresistive element at their cross-point location during the programming write. A spin-transfer torque (or STT)-MRAM has a different write method utilizing electrons' spin momentum transfer. Specifically, the angular momentum of the spin-polarized electrons is transmitted to the electrons in the magnetic material serving as the magnetic recording layer. According to this method, the magnetization direction of a recording layer is reversed by applying a spin-polarized current to the magnetoresistive element. As the volume of the magnetic layer forming the recording layer is smaller, the injected spin-polarized current to write or switch can be also smaller.
To record information or change resistance state, typically a recording current is provided by its CMOS transistor to flow in the stacked direction of the magnetoresistive element, which is hereinafter referred to as a "vertical spin-transfer method." Generally, constant-voltage recording is performed when recording is performed in a memory device accompanied by a resistance change. In a STT-MRAM, the majority of the applied voltage is acting on a thin oxide layer (tunnel barrier layer) which is about 10 angstroms thick, and, if an excessive voltage is applied, the tunnel barrier breaks down. More, even when the tunnel barrier does not immediately break down, if recording operations are repeated, the element may still become nonfunctional such that the resistance value changes (decreases) and information readout errors increase, making the element un-recordable. Furthermore, recording is not performed unless a sufficient voltage or sufficient spin current is applied. Accordingly, problems with insufficient recording arise before possible tunnel barrier breaks down.
Reading STT MRAM involves applying a voltage to the MTJ stack to discover whether the MTJ element states at high resistance or low. However, a relatively high voltage needs to be applied to the MTJ to correctly determine whether its resistance is high or low, and the current passed at this voltage leaves little difference between the read-voltage and the write-voltage. Any fluctuation in the electrical characteristics of individual MTJs at advanced technology nodes could cause what was intended as a read-current, to have the effect of a write-current, thus reversing the direction of magnetization of the recording layer in MTJ.
It has been known that a spin current can, alternatively, be generated in non-magnetic transition metal material by a so-called Spin Hall Effect (SHE), in which spin-orbit coupling causes electrons with different spins to deflect in different directions yielding a pure spin current transverse to an applied charge current. Recently discovered Giant Spin Hall Effect (GSHE), the generation of large spin currents transverse to the charge current direction in specific high-Z metals (such as Pt, β-Ta, β-W, doped Cu) is a promising solution to the voltage, current scaling and reliability problems in a spin torque transfer MRAM.
Due to the relatively low resistivity of GSHE-metals compared to MTJs, the write voltages compatible with future CMOS technology nodes can be expected while the required current density is reduced. However, the spin hall injection efficiency, or ratio of spin current injected to the charge current in the electrode, as a function of electrode thickness has an optimum value at 2-3 nm electrode thickness. Since the thin GSHE-metal layer in outside regions is connected with MTJs in series as electrodes having a large resistance, the effective magnetoresistive ratio is reduced and degrades output signal and reading performance.
Thus, it is desirable to provide a SHE STT-MRAM structure and method of making the same that the geometry is easy to fabricate and has comparable efficiency to conventional two-terminal MTJs while providing greatly improved reliability while keeping high read output signal levels, and therefore offers a superior approach for magnetic memory and non-volatile spin logic applications.

MRAM having spin hall effect writing and method of making the same


A method is described for facilitating use of a first pattern utilizing XOR data formatting in an electronic tester. The method includes dividing the first pattern into at least a first group and a second group, the tester to successively execute the first group and the second group. The method further includes assuming an entry state for each group is one of two binary conditions and inverting programmed commands for the second group if an ending state of the first group is not equal to the assumed entry state.

Integrated circuit devices are typically tested after fabrication to ensure device performance according to functional specifications. Typically, an automatic electrical test system is programmed to provide an integrated circuit device with a simulated operating environment. Very-large-scale-integration (VLSI) devices require an automatic electrical test system capable of processing a large number of high-speed input/output pins.
In a typical automatic electrical test system, an interface between a timing generator and the driving pin electronics of the system must accommodate the data rate of the device under test (DUT). High DUT data rates necessitate high IO bandwidth between the timing generator and the driving pin electronics, which can be very costly to implement. To reduce the IO bandwidth between the timing generator and the driving pin electronics, while accommodating the high DUT data rate, typically two channels, each having half the required data rate, are XORed together.
For testing, circuitry in the electrical test system applies a test pattern utilizing XOR data formatting to the DUT and receives outputs from the DUT in response to the test patterns. Typically, the entire pattern is compiled and loaded onto the Deep Pattern Memory (DPM) of the tester to be executed by the tester and converted from a representation of driven ONEs and ZEROs to a representation which drives a change from one signal state of the DUT to another signal state. A change from one signal state to another is called a transition. Because a state in the pattern depends on the previous state, typically any change to the pattern ripples through the entire pattern sequence. To avoid the ripples, a corrected pattern from the location of the change to the end of the pattern must be recompiled and loaded. This is prohibitively time consuming for all but short patterns.
Additionally, complete patterns are concatenated from many short pattern segments. Pattern segments can be reused and will behave differently depending on whether the entry state to the segment is a ONE or a ZERO.


A thin film transistor, a method for manufacturing the thin film transistor, and an organic electroluminescence display using the thin film transistor are disclosed. The thin film transistor includes a gate electrode, a semiconductor layer that overlaps the gate electrode, a first insulating layer disposed between the semiconductor layer and the gate electrode, and first and second electrodes that use the semiconductor layer as a channel, and are disposed at different layers. The thin film transistor further includes a second insulating layer disposed between the semiconductor layer and one of the first and second electrodes, and a first doping semiconductor layer disposed between the semiconductor layer and the other of the first and second electrodes.

Currently, a thin film transistor is comprised of source and drain electrodes to supply electrons to a semiconductor layer or to bring the electrons out of the semiconductor layer, and a gate electrode overlapped with the semiconductor layer. An insulating layer is disposed between the gate electrode and the semiconductor layer to thereby control a current. The thin film transistor may be used as an integrated driving circuit, as a switching device to independently drive each sub-pixel of a liquid crystal display (LCD), or as a switching and driving device to independently drive each sub-pixel of an organic light-emitting diode display (OLED). The thin film transistor for driving the sub-pixel of LCD is used as a voltage-supplying device, and the switching and driving thin film transistor for driving the sub-pixel of OLED is used as a current-supplying device.
For example, each sub-pixel of an active-matrix OLED includes an organic light-emitting diode, which is comprised of an organic light-emitting layer between the cathode and the anode, and a pixel driving unit, which independently drives the organic light-emitting diode. The pixel driving unit adjusts the current amount supplied to the organic light-emitting diode based on a data signal to thereby control the brightness of the organic light-emitting diode. Accordingly, the pixel driving unit includes a switching thin film transistor, a capacitor, and a driving thin film transistor at least.
At this time, the driving thin film transistor directly controls the current amount supplied to the organic light-emitting diode based on a voltage charged in the capacitor through the switching thin film transistor, whereby it requires the rapid current supply. For the rapid current supply, the related art thin film transistor has an increased plane area to increase a channel width where the source and drain electrodes face. However, the pixel driving unit including the driving thin film transistor is disposed in a non-luminescence area which has no organic light-emitting layer. To increase an aperture ratio, it is preferable to decrease the plane area of the thin film transistor. For the thin film transistor that supplies the current to the organic light-emitting diode, it is thus preferable to have both the rapid current supply and the decreased size.

Tunneling-effect thin film transistor, method of manufacturing the same, and organic light-emitting diode display


Embodiments of the present invention comprise systems and methods for providing transmission priority to stations in a wireless LAN system.

This invention relates to Quality of Service improvements in wireless LAN systems. Some embodiments relate specifically to quality of service enhancements in the IEEE 802.11 WLAN standard.
The IEEE's standard for wireless LANs, designated IEEE 802.11, provides two different ways to configure a network: ad-hoc and infrastructure. In an ad-hoc network, computers form a network on the fly, wherein each computer or 802.11 device joining the network is able to send and receive signals. There is no defined structure in an ad-hoc network; there are no fixed points; and every node in the network is able to communicate with every other node in the network. Although it may seem that order would be difficult to maintain in this type of network, sufficient algorithms, such as the spokesman election algorithm (SEA), are provided and are designed to elect one machine as the base, or master, station of the network, with the others machines being slaves. Another algorithm in ad-hoc network architectures uses a broadcast and flooding method to all other nodes to establish the identity of all nodes in the network.
The infrastructure architecture of an exemplary network comprising 802.11-like wireless devices and connectivity is shown in FIG. 1. In a typical network, wireless network stations 32 & 34 that share wireless connectivity in a first Basic Service Area (BSA) 40 may be organized into a first Basic Service Set (BSS1) 42 that can be controlled by a single coordination function. A network may comprise a plurality of BSSs that are linked together. A second BSS 44 (BSS2), comprising wireless stations 46 & 48 that may exist within a network, but outside the BSA 40 of a first BSS 42. These stations may be able to communicate with each other within a second BSA 50, but do not have the range or other capability to access stations 32 & 34 outside their BSA 50. Coordination within a BSS 42 & 44 may be controlled by coordination functions comprising a Distributed Coordination Function (DCF) and a Point Coordination Function (PCF). When using a PCF, a single station 32, 34, 46 or 48 within a BSS 42 or 44 performs coordination function logic. This PCF station may also serve as an Access Point (AP) 34, 46 that controls access to network elements outside of the BSS 42, 44.
Wired networks 52 may also be connected to wireless network BSSs 42, 44 through portals 54 that implement distribution system service (DSS) functions to access a distribution system (DS) 56 that connects to BSS APs 34, 46 thereby forming a single functional network. A plurality of BSSs 42, 44 may also be linked through an Extended Service Set (ESS) 58 that links BSSs into a single logical network.
APs may act as fixed network access points for communications with mobile stations. These APs may be connected to land lines to widen the LAN's capability by bridging wireless nodes to other wired nodes. If service areas overlap, handoffs may occur between wireless LANs. This structure is very similar to that used in cellular networks.
The IEEE 802.11 standard places specifications on the parameters of both the physical (PHY) and medium access control (MAC) layers of the network. The PHY layer, which actually handles the transmission of data between nodes, may use either direct sequence spread spectrum, frequency-hopping spread spectrum, or infrared (IR) pulse position modulation. IEEE 802.11 makes provisions for data rates of up to 11 Mbps, and requires operation in the 2.4-2.4835 GHz frequency band, in the case of spread-spectrum transmission, which is an unlicensed band for industrial, scientific, and medical (ISM) applications; and in the 300-428,000 GHz frequency band for IR transmission. Infrared is generally considered to be more secure to eavesdropping, because IR transmissions require absolute line-of-sight links, i.e., no transmission is possible outside any simply connected space or around corners, as opposed to radio frequency transmissions, which can penetrate walls and be intercepted by third parties unknowingly. However, infrared transmissions can be adversely affected by sunlight, and the spread-spectrum protocol of 802.11 does provide some rudimentary security for typical data transfers. The 802.11b physical layer (PHY) provides data rates up to 11 Mbps using a direct sequence spread spectrum (DSSS) approach; while 802.11a provides data rates up to 54 Mbps using an orthogonal frequency division multiplex (OFDM) approach.
The MAC layer includes a set of protocols which is responsible for maintaining order in the use of a shared medium. The 802.11 standard specifies a carrier sense multiple access with collision avoidance (CSMA/CA) protocol. In this protocol, when a node receives a packet to be transmitted, it first listens to ensure no other node is transmitting. If the channel is clear, it then transmits the packet. Otherwise, it chooses a random backoff factor, which determines the amount of time the node must wait until it is allowed to transmit its packet. During periods in which the channel is clear, the transmitting node decrements its backoff counter. When the channel is busy it does not decrement its backoff counter. When the backoff counter reaches zero, the node transmits the packet. Because the probability that two nodes will choose the same backoff factor is small, collisions between packets are minimized.
Collision detection, as is employed in Ethernet®, cannot be used for the radio frequency transmissions of IEEE 802.11, because when a node is transmitting, it cannot hear any other node in the system which may be transmitting, because its own signal will block any other signals arriving at the node. Whenever a packet is to be transmitted, the transmitting node may first send out a short ready-to-send (RTS) packet containing information on the length of the packet. If the receiving node hears the RTS, it responds with a short clear-to-send (CTS) packet. After this exchange, the transmitting node sends its packet. When the packet is received successfully, as determined by a cyclic redundancy check (CRC), the receiving node transmits an acknowledgment (ACK) packet. This back-and-forth exchange is necessary to avoid the hidden node problem, i.e., node A can communicate with node B, and node B can communicate with node C. However, node A cannot communicate with node C. Thus, for instance, although node A may sense the channel to be clear, node C may in fact be transmitting to node B. The protocol described above alerts node A that node B is busy, and requires node A to wait before transmitting its packet.
Although 802.11 provides a reliable means of wireless data transfer, some improvements to it have been proposed. The use of wireless LANs is expected to increase dramatically in the future as businesses discover the enhanced productivity and the increased mobility that wireless communications can provide.
IEEE Standard 802.11 (1999) for wireless local area networks (WLAN) does not support Quality of Service (QoS) traffic delivery in its MAC layer. A method to provide Quality of Service traffic delivery for IEEE Standard 802.11 WLAN systems is desirable to enhance communications reliability for 802.11 devices.
There is an 802.11 Task Group e (TGe) joint proposal to support QoS enhancements. Virtual streams having QoS parameter values including priority, data rate, delay bounds and jitter bounds, are supported. The proposal uses an enhanced point coordination (PC) function (EPCF), featuring centralized contention control for sending reservation request frames to request new bandwidth allocations. Several new data and management frames are used. New acknowledgement policies, direct station-to-station transfers, basic service set (BSS) overlap management, and dynamic wireless repeater functions are included. This proposal requires modification of the existing 802.11 standard, and may not support, or be supported by, legacy 802.11 devices.
The subject IEEE standard is set forth in ISO/IEC 8802:1999(E) IEEE Std 802.11, 1999 edition, International Standard [for] Information Technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific Requirements—Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications.
QoS issues are discussed in the following references:U.S. Pat. No. 6,049,549 to Ganz et al., granted Apr. 11, 2000, for Adaptive medium control, describes an approach to QoS having a polling manager, which uses just in time polling based on allocated bandwidth, and a resource manager, which provides admission control and allocates network resources.
U.S. Pat. No. 5,970,062 to Bauchot, granted Oct. 19, 1999, for Method and apparatus for providing wireless access to an ATM network, describes an ATM MAC approach to QoS.
U.S. Patent No. 5,787,080 to Hulyalkar et al., granted Jul. 28, 1998, for Method and apparatus for reservation-based wireless ATM local area network, describes a reservation-based mobile wireless MAC-arbitrated QoS method for use with automated teller machines. The techniques are not compatible with packet-data WLANs.
U.S. Pat. No. 5,745,480 to Behtash et al., granted Apr. 28, 1998, for Multi-rate wireless communications system, describes a communication-negotiated QoS for use in a wireless radio system provided by directly modifying the encoding used to allocate the desired bandwidth, however, such a system is not compatible with packet-data WLANs.

Methods and systems for quality of service in networks comprising wireless devices


A gas sensor including a gas sensor element having a first measurement chamber (16); a first pumping cell (11); a second measurement chamber (18) into which a gas to be measured having a controlled oxygen partial pressure is introduced; and a second pumping cell (13) having a second inner pump electrode (13b) and a second counterpart electrode (13c) pump electrode configured to detect a specific gas component. The second inner pump electrode is made of a material that contains, as a principal ingredient, two kinds of Pt particles having different particle sizes and whose particle size ratio measured by a sedimentation particle-size distribution ranges from 1.75 to 14.2. A mixing ratio between large Pt particles and small Pt particles has a mass ratio of 10/90 to 50/50. A 10 kHz-1 Hz resistance value across the second pumping cell at 600° C. is 150Ω or less.

1. Field of the Invention
The present invention relates to a gas sensor having a gas sensor element that detects the concentration of a specific gas, such as NOx, contained in a combustion gas or an exhaust gas of, for instance, a combustor, an engine, and the like, as well as to a method for manufacturing the gas sensor.
2. Description of Related Art
There is a need for further reduction in the amount of nitrogen oxide (NOx) contained in exhaust gas as regulations on the exhaust gas of an engine, such as an automobile, became more strict. In this regard, an NOx sensor capable of directly measuring the concentration of NOx has been developed.
The NOx sensor has a gas sensor element with one or a plurality of cells, each of which has a pair of electrodes formed on the surface of an oxygen-ion-conductive solid electrolyte layer, such as zirconia. A first pumping cell evacuates oxygen in a first measurement chamber while remaining in mutual communication with a second chamber for receiving the gas to be measured. Further, an oxygen concentration detection cell measures the concentration of oxygen in the first measurement chamber and controls the first pumping cell in such a way that a predetermined oxygen concentration is achieved within the first measurement chamber. Moreover, the gas to be measured having a controlled oxygen concentration flows into the second measurement chamber from the first measurement chamber. NOx contained in the gas to be measured is decomposed into N2 and O2 by applying a given voltage to the second pumping cell. A second pump current flowing between a pair of electrodes of the second pumping cell is measured, whereby the concentration of NOx in the gas to be measured is detected.
In such an NOx sensor, an inner second pump electrode of the second pumping cell is provided in the second measurement chamber and has the primary function of pumping the O2 component originating from decomposition of a trace amount of NOx contained in the gas to be measured. In order to enhance durability of the inner second pump electrode, a technique has been developed using, as an electrode material, cermet consisting of a Pt—Rh alloy and ceramic (see Patent Document 1). A technique for using, as a material for the inner second pump electrode, a mixture consisting of Pt—Rh powder and zirconia powder has also been developed (see Patent Document 2).    [Patent Document 1] JP-A-11-183434    [Patent Document 2] JP-A-2005-283240
3. Problems to be Solved by the Invention
The second pumping cell has a primary function of pumping O2 originating from decomposition of a trace amount of NOx gas. The concentration of NOx gas to be pumped is equivalent to several microamperes in terms of a second pump current. Therefore, even in a case where the pumping capability of the second pumping cell is low, the pumping capability is sufficient for decomposing the trace amount of NOx gas at the time of measuring NOx concentration.
In the meantime, at the time of heating the NOx sensor to activate the solid electrolytes of the sensor element so that they are capable of transporting oxygen, it is necessary to forcefully pump out a high concentration of O2 present in the second measurement chamber. In this regard, the pumping capability of the second pumping cell becomes deficient. Consequently, a problem arises in that there is an increase in the length of the so-called light-off time, namely, a duration from the beginning of start-up control of the sensor until the concentration of O2 in the second measurement chamber (the second pump current) is reduced to a given level by pumping.

Gas sensor and method for manufacturing the same


Efficient and effective communications with customers is a cornerstone of many businesses. Automation, such as in the form of automated agents that can engage in a communication with a customer, furthers those efficient and effective communications. However, textual messages are a series of messages that are often limited to factual statements and direct questions, leaving many customers, such as those that prefer or require high-context communications, may have the impression that the organization with which they are communicating is cold and uncaring or unconcerned about them. By selectively altering the series of messages, an appropriate degree of concern or empathy may be conveyed to facilitate a better relationship and more effective and efficient communications.

In a contact center, serving outbound, inbound and chat and email operations, handling customers efficiently is of prime importance. Agents are trained in real time to answer the customers in best possible manner. This real time training to the agents include agent scripting and prompting to ask better questions, seek information from the customer based on their conversation, provide better options, suggestions, and/or solutions so to the customer for their described problem. It is often preferable to utilize automated agents when possible.

Systems and methods for adaptive emotion based automated emails and/or chat replies


The invented anti-contamination orthodontic device dispenser includes a container for housing orthodontic devices, an aperture in the container through with the devices are dispensed, and a guide structure which directs the devices to the aperture for dispensing. The dispenser is gravity and friction controlled so that when one device is dispensed, the next device is presented and ready for dispensing. The container and guide structure are constructed so that the devices are stacked on top of each other and touching because of gravity. Each device has a tooth on its upper surface and ridges on its lower surface. When a device is dispensed, its tooth contacts the ridges on the device immediately above it creating friction which positions the next device for dispensing. The invented dispenser is particularly effective for dispensing orthodontic O-rings mounted on a carrier or stick.

There has recently been a concern in the medical fields about cross-contamination between patients. Particularly, persons who work with patients suffering from an affliction have tried to protect other patients and themselves from being exposed to the affliction. One specific area with a high potential for cross-contamination is orthodontics.
While working on a patient, an orthodontist might employ several devices. Accordingly, the orthodontist may reach from a patient's mouth, select a device and then continue working on the patient. If, while selecting the device, the orthodonist touches other devices or the packaging of the devices, they may be contaminated. Subsequently, when the orthodonist works on another patient, reaches for the same device or an adjacent device and then returns to work, the new patient may be exposed to the contamination.
For example, orthodontic O-rings are often packaged together in selected quantities to minimize the packaging costs. When an orthodontist reaches into a package of O-rings to select some for use, he risks touching and contaminating the remaining stock. Thereafter, any use of the remaining stock may result in cross-contamination between patients.
To prevent contamination, orthodontic devices may be individually packaged. Nevertheless, the orthodontist must still touch each individual package to expose the device. Additionally, it is more expensive for manufactures to individually package orthodontic devices. Alternatively, each device can be sterilized, but sterilization is time consuming and expensive.
The invented anti-contamination orthodontic device dispenser allows manufacturers to package "patient-specific" selected quantities of devices, organized into cohesive dispense-groups each containing a predetermined quantity of devices--such quantity being that typically expected to be, at the most, required for a single treatment session for each individual patient. The dispenser also allows an orthodontist to select such a dispense-group of devices without touching either the dispenser or the remaining clean stock of devices. Accordingly, the invention protects devices from contamination without requiring individual packaging or sterilization.

Anti-contamination orthodontic device dispenser