text:
|Publication number
|Publication type
|Application number
|Publication date
|Nov 14, 2000
|Filing date
|Nov 5, 1998
|Priority date
|Dec 31, 1996
|Fee status
|Also published as
|Publication number
|Bassam Elkhoury, Christopher J. Pettey, Dwight Riley, Thomas R. Seeman, Brian S. Hausauer
|Original Assignee
|Compaq Computer Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (6), Referenced by (23), Classifications (9), Legal Events (6)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a continuation of application Ser. No. 08/777,597 filed Dec. 31, 1996, now U.S. Pat. No. 5,835,741, issued Nov. 10, 1998.
This invention relates to computer systems, and more particularly to a memory access protocol for a computer system bus which uses a bridge between a processor bus and a standardized system bus.
Computer systems of the PC type usually employ a so-called expansion bus to handle various data transfers and transactions related to I/O and disk access. The expansion bus is separate from the system bus or from the bus to which the processor is connected, but is coupled to the system bus by a bridge circuit.
For some time, all PC's employed the ISA (Industry Standard Architecture) expansion bus, which was an 8-MHz, 16-bit device (actually clocked at 8.33 MHz). Using two cycles of the bus clock to complete a transfer, the theoretical maximum transfer rate was 8.33 MBytes/sec. Next, the EISA (Extension to ISA) bus was widely used, this being a 32-bit bus clocked at 8-MHz, allowing burst transfers at one per clock cycle, so the theoretical maximum was increased to 33-MBytes/sec. As performance requirements increased, with faster processors and memory, and increased video bandwidth needs, a high performance bus standard was a necessity. Several standards were proposed, including a Micro Channel architecture which was a 10-MHz, 32-bit bus, allowing 40-MByte/sec, as well as an enhanced Micro Channel using a 64-bit data width and 64-bit data streaming, theoretically permitting 80-to-160 MByte/sec transfer The requirements imposed by use of video and graphics transfer on networks, however, necessitate even faster transfer rates. One approach was the VESA (Video Electronics Standards Association) bus which was a 33 MHz, 32-bit local bus standard specifically for a 486 processor, providing a theoretical maximum transfer rate of 132-MByte/sec for burst, or 66-MByte/sec for non-burst; the 486 had limited burst transfer capability. The VESA bus was a short-term solution as higher-performance processors, e.g., the Intel P5 and P6 or Pentium and Pentium Pro processors, became the standard.
The PCI (Peripheral Component Interconnect) bus was proposed by Intel as a longer-term solution to the expansion bus standard, particularly to address the burst transfer issue. The original PCI bus standard has been upgraded several times, with the current standard being Revision 2.1, available from a trade association group referred to as PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214. The PCI Specification, Rev. 2.1, is incorporated herein by reference. Construction of computer systems using the PCI bus, and the PCI bus itself, are described in many publications, including "PCI System Architecture," 3rd Ed., by Shanley et al, published by Addison-Wesley Pub. Co., also incorporated herein by reference. The PCI bus provides for 32-bit or 64-bit transfers at 33- or 66-MHz; it can be populated with adapters requiring fast access to each other and/or with system memory, and that can be accessed by the host processor at speeds approaching that of the processor's native bus speed. A 64-bit, 66-MHz PCI bus has a theoretical maximum transfer rate of 528-MByte/sec. All read and write transfers over the bus can be burst transfers. The length of the burst can be negotiated between initiator and target devices, and can be any length.
System and component manufacturers have implemented PCI bus interfaces in various ways. For example, Intel Corporation manufactures and sells a PCI Bridge device under the part number 8245OGX, which is a single-chip host-to-PCI bridge, allowing CPU-to-PCI and PCI-to-CPU transactions, and permitting up to four P6 processors and two PCI bridges to be operated on a system bus. Another example is offered by VLSI Technology, Inc., is a PCI chipset under the part number VL82C59x SuperCore, providing logic for designing a Pentium based system that uses both PCI and ISA buses. The chipset includes a bridge between the host bus and the PCI bus, a bridge between the PCI bus and the ISA bus, an a PCI bus arbiter. Posted memory write buffers are provided in both bridges, and provision is made for Pentium's pipelined bus cycles and burst transactions.
The "Pentium Pro" processor, commercially available from Intel Corporation, uses a processor bus structure as defined in the specification for this device, particularly as set forth in the publication "Pentium Pro Family Developer's Manual" Vols. 1-3, Intel Corp., 1996, available from McGraw-Hill, and incorporated herein by reference; this manual is also available from Intel by accessing <http://www.intel.com>.
The P6 bus is "super pipelined" in that the groups of signals on the bus which define a given transaction are interleaved with similar signals which define a subsequent transaction. One transaction does not need to complete before another is initiated. There are multiple phases of a transaction on the P6 bus, and each phase is a subset of signals on the bus, but these phases or stages overlap one another. An address for request #1 is put out on the bus, and addresses for requests #2 and #3 go out before the result for #1 comes back. A target of a bus transaction sends back an encoded "response" that says what the target is going to do, rather than sending the data itself, usually. The response can be a "retry," or that the target is sending the data immediately, or that it is latching a unique ID and it will come back on the bus later and send the data when it is available (a split transaction). Thus, the data completion phases can be out-of-order, for these retry or deferred responses. The preferred mode of operation, often, is to send bursts of data, rather than reads or writes of one 64-bit quadword. For example, if the bridge receives a series of posted writes, these are all posted, and there are a limited number of buffers in the queues of the bridge. In the example, when the address for cache line #1 is put on the bus, preferably the address for cache line #2 immediately follows, but if the request for cache line #1 is retried, then the ordering rules are violated; the rules dictate that #1 has to complete before #2, and if the address for #2 is put out on the bus and it completes in order, its too late, since a retry already is out for #1. To guarantee ordering, it would be necessary to put out address #1, wait until it is known that #1 is not retried or deferred, then put out address #2, etc. This would destroy the benefits of superpipelining on the P6 bus. Now, main memory can usually be accessed in the clock periods allowed on the P6 bus without deferring or retrying; no out of order responses are needed. To the extent that most transactions on the P6 bus are to system memory, it is a penalty to put out the address and ADS#, wait around for the snoop phase (e.g., six clocks), then put out the next address for a burst; it is known, by the nature of the requests to system memory, that these transactions will complete in order. It is for this reason that the fast burst memory range is employed, as will be explained.
It is therefore one object of the present invention to provide an improved way of handling fast burst transactions on a bus in a computer system.
It is another object of the present invention to provide an improved computer system having enhanced performance when making accesses to devices on an expansion bus, using a bridge between a processor bus and an expansion bus.
It is a further object of the present invention to provide an improved bridge circuit for connecting a processor bus to an expansion bus, particularly one allowing fast burst transactions.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
According to one embodiment of the invention, a computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E)ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. According to a feature of the invention, provision is made for fast burst transactions, i.e., read requests which can be satisfied without deferring or retrying are applied to the system bus without waiting for the snoop phase. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. Because it is known there will be no out-of-order responses, the initiator (processor) can send out a burst of eight write transactions in quick succession, knowing that all will complete in order. The range values are stored in configuration registers in the bridge, written at the time the machine is turned on; the boot up includes interrogating the main memory to see what its range is, then that range is programmed into the bridge. Thereafter, when a transaction reaches the bridge interface from the expansion bus, and it is recognized that the address is within the range, then the fast burst mode is allowed, and write addresses are allowed to follow one another without the usual delay.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIG. 1 is an electrical diagram in block form of a computer system in which a delayed transaction protocol may be implemented according to an embodiment of the invention;
FIG. 2 is an electrical diagram in block form of a bridge circuit for use in the system of FIG. 1, according to one embodiment; and
FIGS. 3a-3g are timing diagrams showing events occurring on the buses in the system of FIG. 1.
Referring to FIG. 1, a computer system 10 is shown which may use features of the invention, according to one embodiment. The system includes multiple processors 11, 12, 13 and 14 in this example, although the improvements may be used in a single processor environment. The processors are of the type manufactured and sold by Intel Corporation under the trade name "Pentium Pro," although the processors are also referred to as "P6" devices. The structure and operation of these processors 11, 12, 13, and 14 are described in detail in the above-mentioned Intel publications, as well as in numerous other publications. The processors are connected to a processor bus 15 which is generally of the structure specified by the processor specification, in this case a Pentium Pro specification. The bus 15 operates at a submultiple of the processor clock, so if the processors are 166 MHz or 200 MHz devices, for example, then the bus 15 is operated based on some multiple of the base clock rate. The main memory is shown connected to the processor bus 15, and includes a memory controller 16 and DRAM memory 17. The processors 11, 12, 13, and 14 each have a level-two cache L2 as a separate chip within the same package as the CPU chip itself, and of course the CPU chips have level-one L1 data and instruction caches included on-chip.
According to the invention, a bridge 18 or 19 is provided between the processor bus 15 and a PCI bus 20 or 21. Two bridges 18 and 19 are shown, although it is understood that many systems would require only one, and other systems may use more than two. In one example, up to four of the bridges may be used. The reason for using more than one bridge is to increase the potential data throughput. A PCI bus, as mentioned above, is a standardized bus structure that is built according to a specification agreed upon by a number of equipment manufacturers so that cards for disk controllers, video controllers, modems, network cards, and the like can be made in a standard configuration, rather than having to be customized for each system manufacturer. One of the bridges 18 or 19 is the primary bridge, and the remaining bridges (if any) are designated secondary bridges. The primary bridge 18 in this example carries traffic for the "legacy" devices such as (E)ISA bus, 8259 interrupt controller, VGA graphics, IDE hard disk controller, etc. The secondary bridge 19 does not usually incorporate any PC legacy items.
All traffic between devices on the concurrent PCI buses 20 and 21 and the system memory 17 must traverse the processor bus 15. Peer-to-peer transactions are allowed between a master and target device on the same PCI bus 20 or 21; these are called "standard" peer-to-peer transactions. Transactions between a master on one PCI bus and a target device on another PCI bus must traverse the processor bus 15, and these are "traversing" transactions; memory and I/O reads and writes are allowed in this case but not locked cycles and some other special events.
In an example embodiment as seen in FIG. 1, PC legacy devices are coupled to the PCI bus 20 by an (E)ISA bridge 23 to an EISA/ISA bus 24. Attached to the bus 24 are components such as a controller 25 (e.g., an 8042) for keyboard and mouse inputs 26, flash ROM 27, NVRAM 28, and a controller 29 for floppy drive 30 and serial/parallel ports 31. A video controller 32 for a monitor 33 is also connected to the bus 20. On the other PCI bus 21, connected by bridge 19 to the processor bus 15, are other resources such as a SCSI disk controller 34 for hard disk resources 35 and 36, and a network adapter 37. A network 38 is accessed by the adapter 37, and a large number of other stations (computer systems) 39 are coupled to the network. Thus, transactions on the buses 15, 20, and 21 may originate in or be directed to another station or server 39 on the network 38. The embodiment of FIG. 1 is that of a server, rather than a standalone computer system, but the bridge features can be used as well in a workstation or standalone desktop computer. The controllers such as 32, 34, and 37 would usually be cards fitted into PCI bus slots on the motherboard. If additional slots are needed, a PCI-to-PCI bridge 40 may be placed on the PCI bus 21 to access another PCI bus 41; this would not provide additional bandwidth, but would allow more adapter cards to be added. Various other server resources can be connected to the PCI buses 20, 21, and 41, using commercially-available controller cards, such as CD-ROM drives, tape drives, modems, connections to ISDN lines for internet access, etc.
The processor bus 15 contains a number of standard signal or data lines as defined in the specification for the Pentium Pro or P6 processor, mentioned above. In addition, certain special signals are included for the unique operation of the bridges 18 and 19, as will be described. The bus 15 contains thirty-three address lines 15a, sixty-four data lines 15b, and a number of control lines 15c. Most of the control lines are not material here and will not be referred to; also, data and address signals have parity lines associated with them which will not be treated here. The control signals of interest here are described in Appendix A, and include the address strobe ADS#, data ready DRDY#, lock LOCK#, data busy DBSY#, defer DEFER#, request command REQ[4:0]# (five lines), response status RS[2:0]#, etc.
The PCI bus 20 (or 21) also contains a number of standard signal and data lines as defined in the PCI specification. This bus is a multiplexed address/data type, and contains sixty-four AD lines 20a, eight command/byte-enable lines 20b, and a number of control lines 20c as will be described. The definition of the control lines of interest here is given in Appendix B, including frame FRAME#, initiator ready IRDY#, lock P-- LOCK#, target ready TRDY#, STOP#, etc. In addition, there are PCI arbiter signals 20d, also described in Appendix B, including request REQx#, grant P-- GNTx#, MEMACK#, etc.
Referring to FIG. 2, the bridge circuit 18 (or 19) is shown in more detail. This bridge includes an interface circuit 43 serving to acquire data and signals from the processor bus 15 and to drive the processor bus with signals and data according to Appendix A. An interface 44 serves to drive the PCI bus 20 and to acquire signals and data from the PCI bus according to Appendix B. Internally, the bridge is divided into an upstream queue block 45 (US QBLK) and a downstream queue block 46 (DS QBLK). The term downstream means any transaction going from the processor bus 15 to the PCI bus 20, and the term upstream means any transaction going from the PCI bus back toward the processor bus 15. The bridge interfaces on the upstream side with the processor bus 15 which operates at a bus speed related to the processor clock rate which is, for example, 133 MHz, 166 MHz, or 200 MHz for Pentium Pro processors, whereas it interfaces on the downstream side with the PCI bus which operates at 33 or 66 MHz. Thus, one function of the bridge 18 is that of a buffer between asynchronous buses, and buses which differ in address/data presentation, i.e., the processor bus 15 has separate address and data lines, whereas the PCI bus uses multiplexed address and data lines. To accomplish these translations, all bus transactions are buffered in FIFO's.
For transactions traversing the bridge 18, all memory writes are posted writes and all reads are split transactions. A memory write transaction initiated by a processor device on the processor bus 15 is posted to the interface 43 of FIG. 2 and the processor goes on with instruction execution as if the write had been completed. A read requested by a processor 11-14 is not implemented at once, due to mismatch in the speed of operation of all of the data storage devices (except for caches) compared to the processor speed, so the reads are all treated as split transactions in some manner. An internal bus 47 conveys processor bus write transactions or read data from the interface 43 to a downstream delayed completion queue DSDCQ 48 and a RAM 49 for this queue, or to a downstream posted write queue 50 and a RAM 51 for this queue. Read requests going downstream are stored in a downstream delayed request queue DSDRQ 52. An arbiter 53 monitors all pending downstream posted writes and read requests via valid bits on lines 54 in the downstream queues and schedules which one will be allowed to execute next on the PCI bus according to the read and write ordering rules set forth in the PCI bus specification. Commands to the interface 44 from the arbiter 53 are on lines 55.
The components of upstream queue block 45 are similar to those of the downstream queue block 46, i.e., the bridge 18 is essentially symmetrical for downstream and upstream transactions. A memory write transaction initiated by a device on the processor bus 20 is posted to the PCI interface 44 of FIG. 2 and the master device proceeds as if the write had been completed. A read requested by a device on the PCI bus 20 is not implemented at once by a target device on the processor bus 15, so these reads are again treated as delayed transactions. An internal bus 57 conveys PCI bus write transactions or read data from the interface 44 to an upstream delayed completion queue USDCQ 58 and a RAM 59 for this queue, or to an upstream posted write queue 60 and a RAM 61 for this queue. Read requests going upstream are stored in an upstream delayed request queue USDRQ 62. An arbiter 63 monitors all pending upstream posted writes and read requests via valid bits on lines 64 in the upstream queues and schedules which one will be allowed to execute next on the processor bus according to the read and write ordering rules set forth in the PCI bus specification. Commands to the interface 43 from the arbiter 63 are on lines 65.
The structure and functions of the FIFO buffers or queues in the bridge 18 will now be described. Each buffer in a delayed request queue, i.e., DSDRQ 52 or USDRQ 62, stores a delayed request that is waiting for execution, and this delayed request consists of a command field, an address field, a write data field (not needed if this is a read request), and a valid bit. The upstream USDRQ 62 holds requests originating from masters on the PCI bus and directed to targets on the processor bus 15 and has eight buffers (in an example embodiment), corresponding one-to-one with eight buffers in the downstream delayed completion queue DSDCQ 48. The downstream delayed request queue DSDRQ 52 holds requests originating on the processor bus 15 and directed to targets on the PCI bus 20 and has four buffers, corresponding one-to-one with four buffers in the upstream delayed completion queue USDCQ 58. The DSDRQ 52 is loaded with a request from the interface 43 via bus 72 and the USDCQ 58. Similarly, the USDRQ 62 is loaded from interface 44 via bus 73 and DSDCQ 48. The reason for going through the DCQ logic is to check to see if a read request is a repeat of a request previously made. Thus, a read request from the bus 15 is latched into the interface 43 in response to an ADS#, capturing an address, a read command, byte enables, etc. This information is applied to the USDCQ 58 via lines 74, where it is compared with all enqueued prior downstream read requests; if it is a duplicate, this new request is discarded if the data is not available to satisfy the request, but if it is not a duplicate, the information is forwarded to the DSDRQ 52 via bus 72. The same mechanism is used for upstream read requests; information defining the request is latched into interface 44 from bus 20, forwarded to DSDCQ 48 via lines 75, and if not a duplicate of an enqueued request it is forwarded to USDRQ 62 via bus 73.
The delayed completion queues each include a control block 48 or 58 and a dual port RAM 49 or 59. Each buffer in a DCQ stores completion status and read data for one delayed request. When a delayable request is sent from one of the interfaces 43 or 44 to the queue block 45 or 46, the first step is to check within the DCQ 48 or 58 to see if a buffer for this same request has already been allocated. The address and the commands and byte enables are checked against the eight buffers in DCQ 48 or 58. If not a match, then a buffer is allocated (if one is available) the request is delayed (or deferred for the bus 15), and the request is forwarded to the DRQ 52 or 62 in the opposite side via lines 72 or 73. This request is run on the opposite bus, under control of the arbiter 53 or 63, and the completion status and data are forwarded back to the DCQ 48 or 58 via bus 47 or 57. After status/data are placed in the allocated buffer in the DCQ in this manner, this buffer is not valid until ordering rules are satisfied; e.g., a read cannot be completed until previous writes are completed. When a delayable request "matches" a DCQ buffer and the requested data is valid, then the request cycle is ready for immediate completion.
The downstream DCQ 48 stores status/read data for PCI-to-host delayed requests, and the upstream DCQ 58 stores status/read data for Host-to-PCI delayed or deferred requests. The upstream and downstream operation is slightly different in this regard. The bridge control circuitry causes prefetch of data into the DSDCQ buffers 48 on behalf of the master, attempting to stream data with zero wait states after the delayed request completes. DSDCQ buffers are kept coherent with the host bus 15 via snooping, which allows the buffers to be discarded as seldom as possible. Requests going the other direction are not subjected to prefetching, however, since many PCI memory regions have "read side effects" (e.g., stacks and FIFO's) so the bridge never prefetches data into these buffers on behalf of the master, and USDCQ buffers are flushed as soon as their associated deferred reply completes.
The posted write queues each contain a control block 50 or 60 and a dual port RAM memory 51 or 61, with each one of the buffers in these RAMs storing command and data for one write. Only memory writes are posted, i.e., writes to I/O space are not posted. Because memory writes flow through dedicated queues within the bridge, they cannot be blocked be delayed requests that precede them; this is a requirement of the PCI specification. Each of the four buffers in DSPWQ 50, 51 stores 32-Bytes of data plus commands for a host-to-PCI write; this is a cache line--the bridge might receive a cacheline-sized write if the system has a PCI video card that supports the P6 USWC memory type. The four buffers in the DSPWQ 50, 51 provide a total data storage of 128-bytes. Each of the four buffers in USPWQ 60, 61 stores 256-Bytes of data plus commands for a PCI-to-host write; this is eight cache lines (total data storage=1-KByte). Burst memory writes that are longer than eight cache lines can cascade continuously from one buffer to the next in the USPWQ. Often, an entire page (e.g., 4-KB) is written from disk to main memory in a virtual memory system that is switching between tasks; for this reason, the bridge has more capacity for bulk upstream memory writes than for downstream.
The arbiters 53 and 63 control event ordering in the QBLKs 45 and 46. These arbiters make certain that any transaction in the DRQ 52 or 62 is not attempted until posted writes that preceded it are flushed, and that no datum in a DRQ is marked valid until posted writes that arrived in the QBLK ahead of it are flushed.
Referring to FIG. 3a, the data and control signal protocol on the bus 15 is defined by the processors 11-14, which in the example are Intel "Pentium Pro" devices. The processors 11-14 have a bus interface circuit within each chip which provides the bus arbitration and snoop functions for the bus 15. A P6 bus cycle includes six phases: an arbitration phase, a request phase, an error phase, a snoop phase, a response phase, and a data phase. A simple read cycle where data is immediately available (i.e., a read from main memory 17) is illustrated in FIG. 3a. This read is initiated by first acquiring the bus; a bus request is asserted on the BREQn# line during T1; if no other processors having a higher priority (using a rotating scheme) assert their BREQn#, a grant is assumed and an address strobe signal ADS# is asserted in T2 for one clock only. The address, byte enables and command signals are asserted on the A# lines, beginning at the same time as ADS#, and continuing during two cycles, T3 and T4, i.e., the asserted information is multiplexed onto the A# lines in two cycles. During the first of these, the address is applied, and during the second, the byte enables and the commands are applied. The error phase is a parity check on the address bits, and if a parity error is detected an AERR# signal is asserted during T5, and the transaction aborts. The snoop phase occurs during T7; if the address asserted during T3 matches the tag of any of the L2 cache lines and is modified, or any other resource on bus 15 for which coherency is maintained, a modified HITM# signal is asserted during T7, and a writeback must be executed before the transaction proceeds. That is, if the processor 11 attempts to read a location in main memory 17 which is cached and modified at that time in the L2 cache of processor 12, the read is not allowed to proceed until a writeback of the line from L2 of processor 12 to memory 17 is completed, so the read is delayed. Assuming that no parity error or snoop hit occurs, the transaction enters the response phase during T9. On lines RS[2:0]#, a response code is asserted during T9; the response code indicates "normal data," "retry," "deferred," etc., depending on when the data is going to be available in response to the read request. Assuming the data is immediately available, the response code is "normal data" and the data itself is asserted on data lines D[63:0]# during T9 and T12 (the data phase); usually a read request to main memory is for a cache line, 32-bytes, so the cache line data appears on the data lines during four cycles, 8-bytes each cycle, as shown. The data bus busy line DBSY# is sampled before data is asserted, and if free then the responding agent asserts DBSY# itself during T9-T11 to hold the bus, and asserts data ready on the DRDY# line to indicate that valid data is being applied to the data lines.
Several read requests can be pending on the bus 15 at the same time. That is, another request can be asserted by any agent which is granted the bus (the same processor, or by a different processor), during T5, indicated by dotted lines for the ADS# signal, and the same sequence of error, snoop, response, and data phases would play out in the same order as discussed. Up to eight transactions can be pending on the bus 15 at one time. The transactions complete in order unless they are split with a deferred response. Transactions that receive a deferred response may complete out of order.
A simple write transaction on the P6 bus 15 is illustrated in FIG. 3b. As in a read transaction, after being granted the bus, in T3 the initiator asserts ADS# and asserts the REQa0# (command and B/E's). TRDY# is asserted three clocks later in T6. TRDY# is active and DBSY# is inactive in T8, so data transfer can begin in T9; DRDY# is asserted at this time. The initiator drives data onto the data bus D[63:0]# during T9.
A burst or full-speed read transaction is illustrated in FIG. 3c. Back-to-back read data transfers from the same agent with no wait states. Note that the request for transaction-4 is being driven onto the bus while data for transaction-1 is just completing in T10, illustrating the overlapping of several transactions. DBSY# is asserted for transaction-1 in T7 and remains asserted until T10. Snoop results indicate no implicit writeback data transfers so TRDY# is not asserted.
Likewise, a burst or full-speed write transaction with no wait states and no implicit writebacks is illustrated in FIG. 3d. TRDY# for transaction-2 can be driven the cycle after RS[2:0]# is driven. In T11, the target samples TRDY# active and DBSY# inactive and accepts data transfer starting in T12. Because the snoop results for transaction-2 have been observed in T9, the target is free to drive the response in T12.
A deferred read transaction is illustrated in FIG. 3e. This is a split transaction, meaning the request is put out on the bus, then at some time later the target initiates a reply to complete the transaction, while other transactions occur on the bus in the intervening time. Agents use the deferred response mechanism of the P6 bus when an operation has significantly greater latency than the normal in-order response. During the request phase on the P6 bus 15, an agent can assert Defer Enable DEN# to indicate if the transaction can be given a deferred response. If DEN# is inactive, the transaction cannot receive a deferred response; some transactions must always be issued with DEN# inactive, e.g., bus-locked transactions, deferred replies, writebacks. When DEN# is inactive, the transaction may be completed in-order or it may be retried, but it cannot be deferred. A deferred transaction is signalled by asserting DEFER# during the snoop phase followed by a deferred response in the response phase. On a deferred response, the response agent must latch the deferred ID, DID[7:0]#, issued during the request phase, and after the response agent completes the original request, it must issue a matching deferred-reply bus transaction, using the deferred ID as the address in the reply transaction's request phase. The deferred ID is eight bits transferred on pins Ab[23:16] in the second clock of the original transaction's request phase.
A read transaction on the PCI bus 20 (or 21) is illustrated in FIG. 3f. It is assumed that the bus master has already arbitrated for and been granted access to the bus. The bus master must then wait for the bus to become idle, which is done by sampling FRAME# and IRDY# on the rising edge of each clock (along with GNT#); when both are sampled deasserted, the bus is idle and a transaction can be initiated by the bus master. At start of clock T1, the initiator asserts FRAME#, indicating that the transaction has begun and that a valid start address and command are on the bus. FRAME# must remain asserted until the initiator is ready to complete the last data phase. When the initiator asserts FRAME#, it also drives the start address onto the AD bus and the transaction type onto the Command/Byte Enable lines, C/BE[3:0]#. A turn-around cycle (i.e., a dead cycle) is required on all signals that may be driven by more than one PCI bus agent, to avoid collisions. At the start of clock T2, the initiator ceases driving the AD bus, allowing the target to take control of the AD bus to drive the first requested data item back to the initiator. Also at the start of clock T2, the initiator ceases to drive the command onto the C/BE lines and uses them to indicate the bytes to be transferred in the currently addressed doubleword (typically, all bytes are asserted during a read). The initiator also asserts IRDY# during T2 to indicate it is ready to receive the first data item from the target. The initiator asserts IRDY# sand deasserts FRAME# simultaneously to indicate that it is ready to complete the last data phase (T5 in FIG. 3f). During clock T3, the target asserts DEVSEL# to indicate that it recognized its address and will participate in the transaction, and begins to drive the first data item onto the AD bus while it asserts TRDY# to indicate the presence of the requested data. When the initiator sees TRDY# asserted in T3 it reads the first data item from the bus. The initiator keeps IRDY# asserted upon entry into the second data phase in T4, and does not deassert FRAME#, indicating it is ready to accept the second data item. In a multiple-data phase transaction (e.g., a burst), the target latches the start address into an address counter, and increments this address to generate the subsequent addresses.
A write transaction on the PCI bus 20 (or 21) is illustrated in FIG. 3g. At start of clock T1, the write initiator asserts FRAME#, indicating that the transaction has begun and that a valid start address and command are on the bus. FRAME# remains asserted until the initiator is ready to complete the last data phase. When the initiator asserts FRAME#, it also drives the start address onto the AD bus and the transaction type onto the C/BE[3:0]# lines. In clock T2, the initiator switches to driving the AD bus with the data to be written; no turn-around cycle is needed since the initiator continues to drive the bus itself. The initiator also asserts IRDY# in T2 to indicate the presence of data on the bus. FRAME# is not deasserted until the last data phase. During clock T2, the target decodes the address and command and asserts DEVSEL# to claim the transaction, and asserts TRDY# to indicate readiness to accept the first data item.
The system bus 15 is superpipelined, in that transactions overlap. According to a feature of -the invention, provision is made for fast burst transactions, i.e., read or write requests which can be satisfied without deferring or retrying are applied to the system bus 15 without waiting for the snoop phase. A range of addresses (e.g., system memory 17 addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge 18 or 19 is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. Because it is known there will be no out-of-order responses, the initiator (PCI agent) can send out a burst of eight write transactions in quick succession, knowing that all will complete in order. The range values are stored in configuration registers in the bridge 18 or 19, written at the time the system 10 is turned on; the boot up includes interrogating the main memory 17 or its controller 16 to see what its range is, then that range is programmed into the interface 43 of the bridge. Thereafter, when a PCI-to-main memory transaction reaches the bridge interface 43, and it is recognized that the address is within the range, then the fast burst mode is allowed, and write addresses are allowed to follow one another without the usual delay.
In one embodiment, the fast burst region is defined to be region from 1-MByte to the Top of Memory. The properties of the fast burst region are that any memory transaction to this region will be guaranteed to never be retried or deferred. With this guarantee, the bridge 18 or 19 can issue multi-cachline accesses to this region every three clocks without having to wait for the snoop phase, knowing that these transactions will never be retried or deferred. Multi-transactions will only be issued in this fast burst region without waiting for the snoop phase if a "fast burst memory mode enable" bit is set in an address decode modes register in the bridge.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
|Cited Patent
|Filing date
|Publication date
|Jul 12, 1994
|Jul 9, 1996
|Intel Corporation
|Method and apparatus for skipping a snoop phase in sequential accesses by a processor in a shared multiprocessor memory system
|Jan 20, 1995
|May 13, 1997
|Intel Corporation
|Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions
|Nov 30, 1994
|Sep 2, 1997
|International Business Machines Corporation
|Bridge between two buses of a computer system that latches signals from the bus for use on the bridge and responds according to the bus protocols
|Jun 7, 1995
|Dec 2, 1997
|International Business Machines Corporation
|Data processing system including buffering mechanism for inbound and outbound reads and posted writes
|Jul 14, 1995
|Feb 10, 1998
|Dell Usa, L.P.
|Method and apparatus for reducing write cycle wait states in a non-zero wait state cache system
|Dec 31, 1996
|Nov 10, 1998
|Compaq Computer Corporation
|Bus-to-bus bridge in computer system, with fast burst memory range
|Citing Patent
|Filing date
|Publication date
|Sep 30, 1998
|Aug 14, 2001
|Compaq Computer Corp.
|System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache
|Feb 18, 2000
|Oct 21, 2003
|Hewlett-Packard Development Company, L.P.
|Write posting with global ordering in multi-path systems
|May 17, 2001
|Jun 29, 2004
|Cisco Technology, Inc.
|Apparatus and technique for maintaining order among requests issued over an external bus of an intermediate network node
|May 17, 2001
|Dec 14, 2004
|Cisco Systems, Inc.
|Apparatus and technique for maintaining order among requests directed to a same address on an external bus of an intermediate network node
|Jul 16, 2002
|Aug 16, 2005
|International Business Machines Corporation
|Data transfer via Host/PCI-X bridges
|Mar 7, 2003
|May 2, 2006
|Cisco Technology, Inc.
|Message processing in network forwarding engine by tracking order of assigned thread in order group
|Jun 2, 2003
|May 9, 2006
|Fujitsu Siemens Computers Llc
|Compute node to mesh interface for highly scalable parallel processing system and method of exchanging data
|Apr 3, 2006
|Oct 23, 2007
|Cisco Technology, Inc.
|System and method for dynamic ordering in a network processor
|Mar 18, 2003
|Dec 25, 2007
|Matsushita Electric Industrial Co., Ltd.
|Bus bridge arbitration method
|Mar 28, 2002
|Aug 11, 2009
|Infineon Technologies Ag
|Method for operating a processor bus
|Mar 20, 2009
|Aug 2, 2011
|Apple Inc.
|Retry mechanism
|Aug 10, 2004
|Oct 16, 2012
|Hewlett-Packard Development Company, L.P.
|Method and apparatus for setting a primary port on a PCI bridge
|Jun 21, 2011
|Jan 22, 2013
|Apple Inc.
|Retry mechanism
|Mar 28, 2002
|Oct 24, 2002
|Holger Sedlak
|Method for operating a processor bus
|Mar 18, 2003
|Oct 23, 2003
|Kenichi Kawaguchi
|Bus bridge arbitration method
|Jun 27, 2002
|Jan 1, 2004
|Patrick Boily
|PCI bridge and data transfer methods
|Jul 16, 2002
|Jan 22, 2004
|International Business Machines Corporation
|Data transfer via Host/PXCI-X bridges
|Jun 2, 2003
|Mar 4, 2004
|Mark Myers
|Compute node to mesh interface for highly scalable parallel processing system and method of exchanging data
|Mar 7, 2003
|Sep 23, 2004
|Potter Kenneth H.
|System and method for dynamic ordering in a network processor
|Apr 3, 2006
|Sep 7, 2006
|Potter Kenneth H Jr
|System and method for dynamic ordering in a network processor
|Nov 7, 2007
|Jul 31, 2008
|Kenichi Kawaguchi
|Bus bridge and arbitration method
|Mar 20, 2009
|Jul 9, 2009
|Keller James B
|Retry Mechanism
|Nov 3, 2000
|Feb 4, 2003
|Compaq Computer Corporation
|Bus-to-bus bridge in computer system, with fast burst memory range
|U.S. Classification
|710/311, 711/146, 710/107, 710/35
|International Classification
|Cooperative Classification
|European Classification
|Dec 31, 2001
Owner name: COMPAQ INFORMATION TECHNOLOGIES GROUP, L.P., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:COMPAQ COMPUTER CORPORATION;REEL/FRAME:012418/0222
Effective date: 20010620
|Jan 21, 2004
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS
Free format text: CHANGE OF NAME;ASSIGNOR:COMPAQ INFORMATION TECHNOLOGIES GROUP, LP;REEL/FRAME:015000/0305
Effective date: 20021001
|Apr 8, 2004
|Fee payment
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|May 14, 2008
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|May 14, 2012
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|Nov 9, 2015
Owner name: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.;REEL/FRAME:037079/0001
Effective date: 20151027


text:
FOOT Locker is to open a store in Sunderland.
The chain, inspired by American sportswear, will move into a 3,216 sq ft unit in Walworth Way South, The Bridges, this summer.
"This is fantastic news," said Gerald Jennings, of Bridges owner Land Securities.
"Foot Locker has a wide appeal and the store's opening is another great example of our commitment to increasing the diversity of our high street offer in the scheme.
"More importantly, Foot Locker is not only new to The Bridges, but new to Sunderland.
"To welcome such a popular brand into the centre is a huge achievement and testament to the growing profile of the centre."
Tim Cincotta, of Foot Locker Europe, said: "We're delighted that Foot Locker will be opening at The Bridges, the first of its kind on Sunderland's high street.
"In our commitment to providing our customers with the latest sneakers and apparel to keep them ahead of the game, we're confident that the locals will enjoy our diverse range of brands and take advantage of the pieces that are exclusive to Foot Locker.
"We look forward to welcoming a brand new sneaker community in the North East."
Mr Jennings added: "We work hard to create the right retail mix within the centre and to ensure that we have a diverse mix of leading high street retailers such as Superdry, Debenhams, JD Sport, Topshop, Lush, Next, H&M and Caffe Nero all under one roof – and we will continue to work hand in hand with retailers to strengthen the diversity of stores for our shoppers.
"Since 2012 we've had several retailers open in the centre, including international brands such as Krispy Kreme and Superdry.
"We will continue to work hand in hand with retailers to strengthen the diversity of stores for our shoppers.
"This is a great success for The Bridges and for the city of Sunderland."
He added: "We are continually working to improve the retail offer at the centre and are committed to creating a better shopping environment and an attractive destination for the 20million annual visitors.
"Sunderland is the biggest city between Leeds and Edinburgh, and we continue to invest in the scheme and the city as a whole to ensure the scheme sits alongside Metro Centre and Eldon Square, in Newcastle, as a major retail location in the North East."

subset: commoncrawl


text:
Musica Latina Translates To Big Profits
Musica Latina Translates To Big Profits
By John
Music is something that virtually everyone enjoys. There are lot of variations, forms, and styles. Music has brought people together and has been instrumental in bringing a lot of happiness and joy. Music has also been a wedge between groups and classes of people. It has been the source of conflict between young and old and sometimes between nations. From the very beginning starting with the most simple of music, parents have always believe music was an evil thing and preferred their children not listen to it or least not what their children wanted to listen. As we grow older and age we become the parents and think our children's music is evil and our children will likewise go through the same thing.
Eventually when other look back at us they will wonder why we drew such a huge distinction between something so similar.
Among cultures we have similar things occurring. We may dislike other people's music simply because of political reasons. It does not have to be that way, but our political orientation life experiences and influences keep us from enjoying music from around the world. When there is no such political influence or other subjective reasons, we can and often do enjoy foreign music. When we listen with an open mind often we are persuaded that it is damn good music.
Our distaste for foreign language music such as Latin Music is often because of the language barrier. Sometimes it is because we don't understand the lyrics that we may choose not to listen to foreign music. With the huge influx of immigrants from Mexico and Latin America, we have been left with a dislike for Latin American music not because it may not be pleasing, but because of the dislike for the huge influx of day laborers on our streets. Until we listen Latin Music or until it is translated for us, we don't know if we actually like. At first there is a strong reluctance to even consider listening to Latin Music, especially with the anti-immigrant sentiment, but often the music is translated for us and wow ! We may think it is the greatest thing ever. Then you may travel to Mexico, or Columbia, or Puerto Rico and discover that the particular style or sound is pretty generic. All it took was a little effort to translate the lyrics from Spanish to English and there you go -an instant hit from the latest Latin Artist. We then shower them with awards and enrich them with our dollars for bringing us Latin Music that had been around for a long time, but noone had bothered to translate. We even forgive them for being from a Latin American country. Latin music, especially Mexican music has had a profound influence in more recent times. It is mostly because it was brought by immigrants and there a lot of them. As they assimilate they don't automatically discard their entire culture, but instead they fuse it and before you know the fusion has become our own. The same is true of many things, such as the Pinata, Taquitos, Burritos, and Tamales. The assimilation is not limited to any one particular culture either, we have bagels, pizza, spaghetti, and hiros go back to the founding years and noone would know what any of that is.
A few thousand years from now, archeologists will have a hard time understanding the great nation known as the United States of America. They will have a hard time discerning the difference between American Music and Mexican Music, and Latin Music, and Caribbean Music, and the same will be true of many things that have enriched our nation.
Learn how to hire a Latin band at a bargain, here Banda Musical
Article source: http://www.artipot.com/articles/1048532/musica-latina-translates-to-big-profits.htm
Related articles
- UMPG Taps John Echevarria As EVP/Latin America (allaccess.com)
- Critic's Notebook: Calle 13 at the Latin Alternative Music Conference (nytimes.com)
- VIDEO: 'La Bamba' band on Latin music hits in US (bbc.co.uk)
- Free Latin Music Roal D. Smeets (roalsmeets.wordpress.com)
- Latin jazz Grammy category reinstated, two others added (latimesblogs.latimes.com)
- The Either/Orchestra Completes Summer Stand at Lily Pad in Cambridge, Prepares for Debut at Jazz Standard in NYC; Performances Feature Jazz, Latin, Ethiopian Music (prweb.com)
- The Big Apple Gets A Taste Of Latin Music (wnyc.org)
- Latin Music: Not Just Music Roal D. Smeets (roalsmeets.wordpress.com)
- The 2012 Hispanic Fiesta Hits Penn's Landing July 14-15 With Latin American Music, Dance, Food And Crafts (uwishunu.com)
- Latin Music by Roal D. Smeets (roalsmeets.wordpress.com)


text:
DIY HOME | Quick Bathroom Backsplash With Adhesive Tiles
DIY PROJECT, Home DIY
Thank you for all the social media love on my guest bathroom makeover! So many of you were surprised to hear the tile is adhesive! It was perfect for this project because I did not want to take the one million pound iron sink off the wall. And it's perfect for you all who are renting and need a removable tile option. I was super excited when Smart Tile asked me to try out their product, because when we were originally renovating my bathroom, I wanted to add tile behind the sink, but since we were under a time crunch for the HGTV pilot we had to scrap it. Smart Tile's hexagon pattern worked so well with the design of the bathroom, I really like the size of the hexagons against the oversized greenery on the wallpaper pattern and the large hexagon tile on the floor. And the best news is that I could install it in less then 2 hours without removing the sink, my kinda weekend project! Stop by Home Depot's blog for more details!
Tips for installing after the break! (more…)
EXPLORE MORE: DIY PROJECT, Home DIY


text:
Bernat Blanket and Blanket Brights Yarn 300g
These 8ply garter st baby shoes have two i-cord bars over the foot. Please note that this pattern is protected by copyright and you do not have permission to copy or resell this pattern. You may, however, sell the knitted product. BASIC SKILLS NECESSARY Knit garter stitch. GAUGE 24 sts and 48 rows to 10cm [4 inches] over garter st, using 3.75mm needles. SIZING / FINISHED MEASUREMENTS Pattern sizes: 0 (3-6-9) months. To fit foot: 7 (8-9-10) cm [23/4 (31/4-31/2-4) inches].


text:
Usmanpura Cross Roads, Ashram Road,
Starting fromOn Request
Hotel Overview
Fortune Hotel Landmark is a 3 Star Hotel offering you a first class, full-service hotel with tastefully furnished rooms offering a range of amenities, large meeting rooms, state-of-the-art business facilities and full catering services.
Fortune Hotel Landmark has 96 well-appointed rooms and suites including Presidential Suites, Fortune Club Suites, and Deluxe Rooms. Presidential Suites: - A luxurious three bay suite with a bedroom, a sitting area and a dining area with TV and bathroom in both the bedroom and sitting area. Fortune Club Suites : - A tastefully furnished two bay suite with a bedroom and a sitting area. Choose from smoking / Non-smoking suites. Deluxe Rooms : - An aptly furnished room with twin / king bed option and a writing table. Carpeted / Non-carpeted and Smoking / Non-smoking rooms available on request / availability.
Orchid, the multi-cuisine restaurant, servers a sumptuous buffet from breakfast to dinner, as well as an a-la-carte menu with a variety of Indian, Chinese and Continental cuisines. Desserts by Design, An extension of Orchid, is the pastry shop for the dessert lovers. Khyber, the barbeque restaurant under the stars, serves you delicious Indian and Continental cuisine.
Fortune Hotel Landmark
Usmanpura Cross Roads, Ashram Road, Gujarat, India, - 380013


text:
iSpy Live Adult Chat
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iSpy Live also has a games section, which allows you to play against other users and, if you win, you'll receive their tokens. This is a great way to watch camgirls for free if you're any good at the available games, it won't be hard for you to come out on top. I thoroughly recommend this as a top chat site that dominates the competition. Oh, and if you find a live chat platform that's better than this, be sure to let Mr. Porn Geek know by shooting me an email. Have fun, folks!
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text:
19 Dec 2016
T & A Limited – (Planet FM ) Jobs in Nigeria : IT Manager
Welcome to Jobsinnigeria.careers. This website helps you to achieve your career dream by linking you to vacancies from Top Companies in Nigeria. Job Seekers are also exposed to best articles for career growth and development. Click Here to Subscribe for Job Alerts We strongly advise graduates not to pay money before getting a Job. Report fraudulent jobs to [email protected]
- Company: Taf & Associates Limited
- Location: Akwa Ibom, Nigeria
- State: Akwa Ibom Jobs
- Job type: Full-Time
- Job category: IT/Telecom Jobs in Nigeria
Taf & Associates Limited, Operators of planet firm – Our Client, a reputable Radio station in Uyo, Akwa Ibom, requires a professional to fill the position below in their station.
Job Title: IT Manager
Job Role
- Manage the IT Department on a day to day basis and motivate team to work in the most efficient manner
- Be on the forefront of emerging industry practices.
- IT Policy, Strategy, Procedures and Controls Development and Formulation
- Holds regular meetings with IT team and effectively manages these sessions.
- Inspires colleagues to attain goals and pursue excellence.
- Ensuring adherence to company backup and disaster recovery plan
- Supervise and Ensure timely resolution of IT Related help desk issues.
- Recruitment of new IT Team members.
- Serves as main point of contact on all IT-related matters for the company.
- Oversee Network Design/Configuration, Implementation and Maintenance,
- Implementation of network security as required by Company policy.
- Oversees troubleshooting and resolution of general user problems,
- System Administration – Oversees Upgrades of New hardware/ software and configuration, and related patches.
- Mail Servers Management
- Management of websites, apps, social media sites, live streaming etc
- System Administration – Oversees Upgrades of New hardware/ software and configuration, and related patches.
- Monitoring service and performance levels of IT Suppliers
- Staff and User Training
- Managing Mail and exchange servers.
- Programming and Website Design/Management Skills
- Monitor stability, connectivity and performance of the Information access interfaces environment and related storage capacity
- Suggests areas for improvement in internal processes along with possible solutions. Completes other digital media projects as assigned.
- 5 Years work experience in Related Industry with 2 years at Management level.
- Bachelors Degree or HND in IT or Computer Science or related field.
- Knowledge of: Visual Basic, VB.Net, JAVA,C++, VISUAL C++, CSS, JAVA SCRIPT, MYSQL DATABASE, Joomla, WordPress, PHP.
- Strong Analytical and Decision Making Skills
- Proven Leadership and Management Qualities
- Excellent Communication, problem solving and negotiation skills.
- Self-starter with strong leadership and consensus building skills
- Ability to multi-task , Self disciplined
- Ability to work under pressure and meet tight deadlines
- Team player with good interpersonal skills
Application Closing Date
6th January, 2017.
How to ApplyInterested and qualified candidates should send their applications and CV's to: [email protected]
Dont Miss Latest Jobs In Nigeria. Subscribe Today. CLICK HERE


text:
IQbuds™ Achieve USA Certification
PERTH, Western Australia – Nuheara Limited (Company), Australia's only ASX listed consumer wearables technology company, is pleased to announce that IQbuds™ have achieved FCC certification for the USA. The Company is now approved to commence the fulfillment process for USA pre-order customers and, as these orders are cleared, then commence broader retail sales.
Figure 1: Federal Communications Commission (FCC) approved mark on IQbuds™ for sale in the USA.
"As we wrap up our very successful CES activities here in the US, the announcement of IQbuds™ achieving certification for sale in the US is very well timed. It has been an extremely successful week for the Company and we look forward to providing a further update on all CES activities over the course of the next week", said Nuheara CEO Justin Miller.
Justin Miller
CEO and Managing Director
+61 8 6555 9999
David Cannington
Vice President of Sales & Marketing
About Nuheara
Nuheara is an innovative audio Wearables company. It has developed proprietary hardware and software to deliver multi-functional intelligent hearing technology that augments a user's hearing and facilitates cable free connection to smart devices. With Nuheara's IQbuds™, consumers are able to augment their hearing according to their personal hearing preferences and connect hands free with their voice enabled smart devices. Nuheara's mission is to improve people's lives by allowing them to seamlessly listen, communicate and connect to their physical and digital world. Learn more about Nuheara: www.nuheara.com.


text:
Rail workers at Greater Anglia are to go on strike - in a row over the role of guards and driver-only trains.
The RMT Union says members voted overwhelmingly in favour of industrial action after Abellio - which runs the franchise - failed to give assurances on their future.
They claim the potential extension of the Driver Only Operation is "a clear threat to passenger safety".
Over 200 Greater Anglia guards voted nine to one for strike action, while the drivers vote was two to one for action.
RMT General Secretary Mick Cash said: "Greater Anglia have been given every opportunity to give a guarantee on the future role of the guard on their services.
"They have failed to do so and that left us with no alternative but to move to a ballot in the interests of rail safety.
"Our members have now voted by massive majorities for action and it's now down to the company to wake up and take note and to seize the opportunity to give us the very simple assurances on the future of the guards, and the guarantee of a second safety critical member of staff on current services.
"The union remains available for further talks around the crucial issue of the guard guarantee."
The result will now be considered by RMT's executive who will decide on the next steps in the dispute.
Greater Anglia insists it's got no plans to axe guards on services.


text:
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Lincoln's Inn Fields is the 4th Club Quarters hotel in London. The hotel is an ideal accommodation choice for business and leisure travellers with close links More
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The Clarendon Hotel London
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Thistle Holborn, The Kingsley
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Kingsway Hall Hotel London ( 1 minutes)
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Club Quarters Lincoln's Inn Fields ( 3 minutes)
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Strand Palace Hotel London ( 5 minutes)
Radisson Blu Edwardian Mercer Street ( 5 minutes)
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text:
In the last hour the St. Louis Rams cemented them selves as the 2016 Super Bowl champions. The Rams traded the 2nd overall pick to the Washington Redskins for three first round picks and a second round pick. The Dallas Cowboys-Minnesota trade has been considered the greatest trade in NFL history, as it led to the Cowboys dominance in the 90s. For now, at least until we see how these picks pan out, it shall remain a close second.
The Rams have been lacking a receiving core that their former first overall pick QB Sam bradford could throw too. Well now with the 6th overall pick, the Rams may be able to select OK ST WR Justin Blackmon. Bradford and Blackmon could prove to be a lethal combination. As well, with 4 first round picks in the next two years, the Rams will be able to add as much depth as a team could possibly need.
Now on the Redskins front, the 'Skins have now shown that they intend to draft Baylor QB Robert Griffin the 3rd. Although this could prove to be a great pick, the trade doesn't make a lot of sense. Let's say Griffin proves to be everything we thought he could be and more, who will he pass the ball to? Who will block for him? Who will play defense on the 'Skins? Even with a great QB, you still need a great team to win a Super Bowl and you can't have a great team without draft picks. If free agency is all you needed then the 'Skins would have been a contender for the last 10 years.
From the beginning St Louis has been trying to shop this pick and the only possible team to make the trade was the Washington Redskins. The asking price was too high for any other team and the 'Skins Owner, Dan Snyder has been known to make insane moves (i.e Albert Haynesworth's 100 million dollar contract…).
Peyton Manning Watch Day 2
As of today QB Peyton Manning is talking to the Denver Broncos. This is the first of plenty of teams that the future hall of fame QB will talk to. Now a lot of people seem to think that Manning could end up there and with the 'Skins, who were already a long shot and have now all but dropped out, the Broncos have moved into 4th place in a lot of peoples minds. I can't see Manning signing with the Broncos. Manning is a future hall of famer why would he want to sign with a team that already has a famous QB in John Elway, Manning doesn't want to compete with that legend. Now many people say that the trade would end Tim Tebow's career but really it would only improve his career. Manning could teach Tebow the way of the QB or they could trade him to the Jaguars, who have been rumoured to be shopping for the Floridian legend. The Broncos aren't stable enough for Manning, John Fox has not proven to be a great Coach, granted he made the Super Bowl with the Panthers, but since then all his teams have been failures. I still see Manning either going to the Cards, Fins or Jets.
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text:
November 4, 2008
Dr. Smith,
Your letters dated May 12 and July 7 reached me on August 21. Your statements deliberately misstate the truth and your words seem to have been chosen to imply the worst about me, but they are easily refuted by the facts. Never have I made false statements about anyone to anyone, nor would I. In this letter, and in all other communications on this issue, I've clearly said what I know to be true and what I believe to be true. I have always distinguished the two: what I witnessed and what students said they witnessed. This is my second and final letter to you.
I witnessed a bad scene in April 2007. The other was reported to me by two students independently of each other and was said to have occurred in the fall of 2007. These events were the bullying of students by administrators. I was prepared to give you the details, but you decided to attack me instead. It was I who asked the policeman to speak to you. You met him at your office the very next day. He related that you were sincerely concerned about the matter and would take some measures. So why did you respond with icy hauteur and avoidance when I asked to see you? Why were you not interested in meeting with the person who said she was a witness to the worst offense?
You and I spoke only on two occasions, and both times you called me. Check your long-distance bill because I'm sure the calls did not exceed 15 minutes in total. You and I discussed nothing of value during the second, the brief conference call stunt. With the children's welfare at stake this is not a "significant" amount of time. How wrong I was to contact you and expect you'd care!
As for the implied dozens, scores or hundreds of calls you say I made to your office, that's simply not true and would have been a colossal waste of my time. It's moot because it cannot be proved or disproved. I did leave a few messages in a futile effort to nudge your conscience into acting for the kids. Besides, had it been...


text:
The tragic downfall of 80s heartthrob Jan-Michael Vincent
Acting roles dried up for Vincent as his demons got the better of him.
He also suffered his fair share of bad luck including two serious car accidents.
In the first incident in 1996, Vincent broke three vertebrae in his neck and sustained a permanent injury to his vocal cords that left him with a permanently raspy voice.
Vincent had admitted to issues with drugs and alcohol and admits that he still struggles with alcoholism.


text:
Just in time for raising temperatures and sunny skies, CAVA Grill, is rolling out its spring menu at all locations beginning on March 20th. CAVA recently opened three locations Irvine, Woodland Hills, and Westwood Village, and a Culver City location is opening next week.
Laden with herbs like turmeric, mint, and ginger, the spring menu, developed by Executive Chef and Founder Dimitri Moshovitis, places an emphasis on health and locally-sourced, seasonal vegetables. All three herbs provide anti-inflammatory and antioxidant properties and aid in digestion, and boast robust flavor profiles and a low calorie count – perfect for diners searching for full-flavored foods without the guilt.
The new menu will feature an assortment of light and refreshing house-made juices, using vegetable-forward ingredients and natural sweeteners like agave and cane sugar. New beverages include Raspberry + Mint Grapefruit Shrub, Strawberry Mint Lime, Ginger + Lime Turmeric Tonic, and Hibiscus Green Tea.
New dressings, which can be used as a topper on any grain bowl, salad, or pita, include Charred Leek Vinaigrette, and Sumac Radishes from California – spiced radishes from California using a CAVA spice blend – will be introduced as an optional addition to any meal. Carrot Ginger Soup will also be featured as a limited-time only menu addition. For more information visit www.cava.com
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text:
Template >> Flyer - Travel Flyer Template 181420 by Decorwith.me Shop @ CreativeMarket
File Size: 1.17 MB; Vector: Yes.
Illustration of vector travel flat design flyer template.
ZIP included.
- editable EPS10 vector file format
- high quality JPG
Keywords: booking, business, composition, design, holiday, icon, journey, rest, set, summer, tour, tourism, travel, trip, vacation, travelling, web, infographics, background, airplane.


text:
Bio & Incident Details
Age: 30
Tour: Not available
Badge # Not available
Cause: Automobile crash
· Leave a Reflection
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· Update this memorial
Deputy Banks was killed when his cruiser was struck by a vehicle which had run a stop sign. The driver of the other vehicle had turned his lights off to see if any other cars were coming. If he he did not see any headlights he would run the stop sign. The suspect was sentenced to two years in jail.


text:
GraphicRiver Grunge Paper Patterns 5915672
GraphicRiver Grunge Paper Patterns 5915672
Add-on \ Photoshop \ Texture \ Fills \ Patterns \ Miscellaneous
Rough \ Rustic \ Retro \ Pattern \ Paper \ Parchment \ Scrapbook \ Sheet \ Vintage
Add-on - Grunge Paper Patterns 5915672 by TanyDi @ GraphicRiver
Add-on \ Photoshop \ Texture \ Fills \ Patterns \ Miscellaneous
Add-on Files Included: Layered PSD, JPG Image, Photoshop PAT ; Minimum Adobe CS Version: CS ; Works With: PSD, JPG .
The package contains 12 grunge paper patterns. Paper textures and patterns can be useful for various purposes in web and print design. PSD file is layered with 12 patterns + custom color adjustment layer and can be useful for faster customization of size and color.
- 12 JPG 1024 x 1024px / 72ppi
- 1 PAT file - 12 patterns 1024 x 1024px
- 1 PSD file 1024 x 1024 / 72ppi
- 2 Help files
You can use this package in your own design, in web & print design, backgrounds, textures, posters, flyers, cards, booklets, brochures, artworks, blogs, any kind of presentations & promotions, screensaver, wallpapers.
I'd really appreciate it if you could rate my file.
Feel free to contact me through my profile page if you have any questions, feedback, or need assistance.
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Watercolor Autumn Leaves Patterns; Abstract Colorful Squares; Happy chimney sweep talisman; Pink Granite; Yellow-green Rounded Autumn Leaves; Pine Cones; Abstract Light Circles.
Keywords: aged, ancient, antique, background, brown, canvas, cardboard, crumpled, design, dirty, grunge, grungy, manuscript, material, old, page, paper, parchment, pattern, retro, rough, rustic, scrapbook, sheet, stained, surface, texture, vintage, wrinkled.


text:
Trade Show/Exhibition organiser
- Posted
- Proposals 1
- Remote
- #15566
- Expired
Experience Level: Intermediate
Experienced exhibition organiser to assist with the planning and launch of a unique trade expo in London, schedule for mid-year 2010. This is a niche market with very great potential - (a how come no one thought about it project ?) The project is an extension of a print media that reach out to the target audience. Remuneration to be discussed .
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text: I was asked recently if I could present rational evidence for the existence of God. My knee jerk reaction is I do not need proof I know cause I know<< "wrote a poem about it" I thank God that He gave me insight and direction to present my understanding of Him and His design of His creation. It was really good for me too because I see the worms I raise in a whole new light. Yes I am a worm farmer. Worms and God I see Gods design in everything, although I am awe struck by His speaking the heavens into existence, illuminating it with everything in its place. He knows the stars by name all display light praising their creator. All the planets set into motion moving in perfect harmony with each other displaying Gods glory throughout the universe (one verse) We do have an awesome God! These are things I see, I do not know much about them. I do know about worms, so I will talk about them. I raise three different kinds of earth worms all are composting worms. What does this have do with God? What rational evidence do earth worms provide of God? They are part of an awesome design of an awesome God. I want to ask a few questions for you to answer for yourselves and ponder your answers as I present earth worms God's awesome design. Do you or anyone you know have house plants? How often do you re pot your plants? Do you know why you re pot them? Now I would like to take you through the forest in the fall leaves are thick covering the ground limbs and other debris are visible. Should we walk this same path mid summer there are traces of the previous fall but most has disappeared into the forest floor. This is God's design from fungus to worms and microbes continue working year round replenishing the nutrients to sustain the forest. I ask people what happens with it they say it rots, this is true but there is more to it than that. There are billions of little creatures of God's design feeding the plant life and trees and maintaining the forest floor. Now back to the worms I raise red worms aka Red Wigglers this is a great little worm it devours its half its body weight(1000 = 1 pound) daily. The casting (worm poo) are one of if not the most sought after organic fertilizer there is. Who would have thunk it? God's Design! He feeds His creation with the best. Plants grown using worm castings are much healthier more resistant to bugs and disease. Who would have thunk it? God's Design! On top of that it improves the soil with no side affects. Worm castings can be used to make a tea which not only fertilizes but when sprayed directly on the plant it will stop insects from hurting the plants. The worm casting will not burn plants even when fresh unlike horse or cow manure. We do have an awesome God! I told you about my red worms, I also raise European night crawlers a bigger worm (500 - 600 make a pound) They do not eat half their body weight but close being a big worm they do produce their share of compost. My third worm is an African night crawler they get up to 10 inches in length and eat anything (250-300 = pound) these monsters devour 1 and a half of their body weight everyday. 1 pound of worms 10 days 15 pounds of the best fertilizer known to man. Chemical fertilizers were a quick fix becoming a hazard to our rivers lakes and streams even man. Killing off animals, insects and all the beneficial critters that made the soil fertile to start with. Do you remember in school when you were taught that people used to think the earth was flat. Had they believed the scriptures that said it was a sphere they would not have feared falling off the edge. For me it is a no brain er to except that He got it right and left no need for improvement. I think Gods design is plainly seen when you understand the working of the forest floor.


text:
- 17 March 2017 17:11
Capgemini named a 2017 World's Most Ethical Company® by the Ethisphere Institute for the 5th consecutive year
Capgemini has achieved this global recognition consecutively for the last five years––one of only two in the consulting industry to do so, underscoring its commitment to maintaining high standards of ethics and corporate integrity across the Group and throughout its global business practices.
Nicolas Aidoud, Capgemini CEO ANZ said: "It's fantastic to be acknowledged as one of the World's Most Ethical Companies, and for the fifth year running. In Australia and New Zealand, our culture is what sets us apart for our employees to clients and the community, and as we enter into our 50th Anniversary year as a company this is an important recognition of our strong and sustainable ethical values. Having travelled from Capgemini France to Capgemini Australia in the last year, I was delighted to see this is a culture that is inherit across the globe, throughout the Group."
Timothy Erblich, Chief Executive Officer at Ethisphere said: "It is our mission to define and advance the standards of ethical business practices that fuel corporate character, marketplace trust and business success. The World's Most Ethical Companies recognition is first and foremost a measurement exercise with the honour being reserved for those who excel. We would like to congratulate Capgemini for consecutively maintaining its position as a World's Most Ethical Company for the last five years. It has set a high benchmark for the industry, by evolving with the changing business environment while remaining steadfast in its commitment to corporate ethics and compliance."
This is the eleventh year that Ethisphere has honoured those companies who recognise their role in society to influence and drive positive change, consider the impact of their actions on their employees, investors, customers and other key stakeholders, and use their values and culture as an underpinning to the decisions they make every day.
Methodology & Scoring The World's Most Ethical Company assessment is based upon the Ethisphere Institute's Ethics Quotient® (EQ) framework which offers a quantitative way to assess a company's performance in an objective, consistent and standardised way. The information collected provides a comprehensive sampling of definitive criteria of core competencies, rather than all aspects of corporate governance, risk, sustainability, compliance and ethics.
Scores are generated in five key categories: ethics and compliance program (35%), corporate citizenship and responsibility (20%), culture of ethics (20%), governance (15%) and leadership, innovation and reputation (10%) and provided to all companies who participate in the process.
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text:
The Enormous Evan dildo offers plenty of length and girth for men and women to enjoy deep, probing penetration. This dildo has a detailed look and feel from the cock head all the way to the balls-shaped base. You can even mount Evan to almost any flat surface, giving you an opportunity for hands-free stimulation.
All prices are in USD.


text:
GraphicRiver Multi-Eyed Monster in Front of a Hospital 7995375
Stock Vector \ Characters \ Monsters
Monster \ Hospital \ Streetside \ Support \ Street \ Roadside
Stock Vector - Multi-Eyed Monster in Front of a Hospital 7995375 by interactimages @ GraphicRiver
Stock Vector \ Characters \ Monsters
Illustration of a multi-eyed monster in front of the hospital building
Layered: No; Graphics Files Included: JPG Image, Vector EPS; Minimum Adobe CS Version: CS.
Fork and Spoon; Dessert; Pink Toys; Fish and Reef; Cooking; Knitting; Colour.
Keywords: accident, alien, bandaged, bandaging, blob, blue, cartoon, character, clouds, creature, critter, cross, crossing, crutches, fractured, hospital, lane, monster, multi-eyed, outdoor, outside, pedestrian, road, roadside, sky, street, streetside, support, wood, wooden.


text:
We may be in the dead of winter, but Muse head to the beach anyway in their new video for "Supremacy." They also bring along a few new friends: a crew of black-metal fans who out to catch a few rays and waves. As the band bashes out the monstrous cut from their latest album, The 2nd Law, the face-painted masses gather beachside for a series of activities: surfing, skating, biking while hoisting flaming swords and even hosting a sunset wedding. Nothing says "good day at the beach" like headbanging with your bros around the ol' bonfire.
- 50 Best Songs of 2012: Muse, 'Madness'
- 50 Best Albums of 2012: Muse, 'The 2nd Law'
- Muse Open U.S. Tour With a Bang
This article originally appeared on Rolling Stone: Muse Bring Black Metal to the Beach in 'Supremacy'


text:
Economic Geology
- © 2012 Society of Economic Geologists.
Volcanogenic massive sulfide (VMS) deposits typically contain significant proportions of magma-derived chalcophile (Cu affinity) and siderophile (Fe affinity) elements such as Au, Cu, V, Zn, Mo, Bi, Sb, and As that relate to the composition of associated (host) magmatic rocks. Here, we combine new and published trace element data for lavas recovered from 15 volcanic centers along the Kermadec arc. The data show that mafic back-arc and arc-front lavas are enriched in most of the chalcophile and siderophile elements when compared with mid-ocean ridge basalts (MORB). Elevated (Cu, Zn, V, Mo, Pb)/Yb, Ba/La, As/Ce, and Sb/Pr ratios indicate that the chalcophile and siderophile elements are either transported into the mantle wedge via hydrous fluids derived from the subducting slab, or are liberated from residual mantle wedge sulfides that are oxidized by hydrous fluids. Lower ratios of (Cu, Zn, Mo, Sb, and Pb)/(MREE, HREE) in basalts from the Kermadec back arc (Havre Trough) when compared to the arc front suggests decreasing slab-related input into the mantle source away from the arc front. Unusually high contents of LILE, Ag, Sn, Mo, Th, LREE, MREE, Nb, Zr, Hf, and positive trends in (Ag, Sn)/Yb with Th/Yb, Hf/Y, (La/Sm)N, but low Sr/Y, in dacites from the Brothers volcanic center, southern Kermadec arc, indicate the additional transport of Ag and Sn via a solute-rich supercritical fluid, or via a sediment-derived melt. Magmas generated through partial melting of a sub-arc mantle metasomatized by hydrous melts thus appear to play an important role in the formation of Cu-Au-Ag−rich arc-type VMS deposits.
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SEG Members should visit www.segweb.org/access for instructions on accessing the journal or log in at SEG and restart your search.


text:
Labour Brexit secretary accuses Theresa May of swerving immigration questions
THERESA MAY has been accused of dodging important questions, such as on immigration, during her first live interview of the year, by Labour's Brexit secretary.
The Prime Minister said she would reveal more plans for Britain's exit from the European Union over the coming weeks but offered little in clarity, according to Keir Starmer.
The Labour Party MP, speaking on Sky News, bemoaned her lack of detail claiming that the country needed to know more about the key issues of single market access or immigration policy.
The 54-year-old said: "I don't think that we have learnt much at all from the Prime Minister.
"It was very telling, I think, that she had one question put to her three times and still didn't answer it which is, 'Are you prioritising immigration over access to the single market?'
Keir Starmer criticised Theresa May for her lack of clarity
We need more clarity than that and we haven't got it
"That was the question she didn't want to answer and I think now, 10 to 11 weeks from the triggering of Article 50 and the most important negotiations for a generation, we need more clarity than that and we haven't got it."
But Britain's Brexiteers will be left more encouraged by Mrs May's words, after dropping perhaps the biggest hint yet that Britain is destined to leave the European Union's single market.
Having reaffirmed that her Government's Brexit thinking "isn't muddled", the Prime Minister said she would not try to "keep bits of membership".
She told Sky News: "We are leaving, we are coming out, we are not going to be a member of the EU any longer.
The Prime Minister told Sky News that more Brexit details will be unveiled in weeks
"We will have control of our borders, control of our laws, but we still want the best possible deal for UK companies to trade with and operate within the European Union and also European companies to trade with and operate within the UK.
"We must not think about this as somehow we are coming out of membership but we want to keep bits of membership.
"What we must say is what the right relationship for a United Kingdom that is no longer a member of the European Union. The best possible deal for the UK will also be a good deal for the EU.
"I am ambitious for what we can get for the UK in terms of our relationship because I also think that's going to be good for the EU."
Senior Conservative MP Steve Baker welcomed Mrs May's comments, suggesting it was enough "clarification".
He said: "This is welcome clarification of a sensible position by the PM.
"We won't be clinging onto bits of EU membership."
However, Open Britain campaigner and Labour MP Chuka Umunna said: "There is no cost-free option for leaving the single market. Any trading arrangement outside the single market would erect barriers with our largest trading partner and would be disastrous for the UK economy, jobs and business.
"The PM should be ambitious for our country and set as her goal being in the single market with new immigration arrangements that move towards fair movement, giving more control while meeting the needs of our economy.
"Rather than evasive interviews, the country wants a clear plan for how the Government will avoid economic self-harm and protect our prosperity."


text:
Something happened between now and when I left NYC, nearly a year ago. I am not sure of what it was, but I know it was/is destructive. I left NYC not just to see the world and the places I have always dreamed of seeing before it was too late, but also because I sought another option. I refused to see the five year sentence I was given as the only way. I was open to any other possibility. Another way. From countless medical professionals I kept hearing "you will not get better." And while I can not deny that this was a huge possibility, I refused to give in to this reductive thinking. I refused to accept that this was the only way.
And I did just that. I found many things that have inhibited the further decay of my kidneys. I actually raised my GFR numbers, something my doctor told me was impossible. I refused to let his reductive thinking beat me.
Then over the past six weeks or so I forgot about the person who believed any of this. I lost my way. I got stuck in the silt of a swiftly moving river, with no way out and rising water almost overtaking me, as soon as even the idea that my Lupus may have returned. It crippled me. No wonder my body is failing me. I had gone from having faith that a solution may be out there, that I could find another way of living, to living an existence based on the very flawed concept of determinism.
I went from struggling to accepting, without even blinking. I gave into the notion that my prescribed path of dialysis and ultimate quick death was a ever swiftly increasing nonnegotiable fact. I shed a major part of who I have recently blossomed into being and became a sad shadow of myself. And really, I think that is mostly what happened. I became so depressed by recent events that I allowed myself to plummet back into wondering just how long I have left, spiraling downwards just because my Lupus is back.
What could be worse for me to think right now? Why do I tempt fate by giving it an opening to afflict me again? Why do I forget that, even though it was under rather dramatic circumstances, which I refuse to put myself through again, I beat this beast once? With concentrated effort coupled with Tibetan medicine I must believe I can do it again. Anything else is hopeless. And I am not hopeless. If I was, I never would have started this journey.
My nephologist told me that going into remission again is near impossible. As stated above, he also told me raising my GFR numbers was impossible. Yet I did. So just why should I believe him now? Why should I remain in his shallow area of thinking where his desire to treat my Lupus will harm another portion of me? How is this even an option, let alone the only one?
So in order to twist myself out of this funk I have made a big choice. No longer will I stew in the bile of western medical ideology where the plan — "there is no plan B" — consists of something that may "heal" one of my conditions while irrevocably doing damage to me elsewhere. This line of thought is unacceptable. Totally and Completely. I am not going to go so far as to fire my western doctor, but he is no longer going to be whom I refer to as my primary care doctor. As I continue to delve into the Tibetan medical tradition in order to understand it on a physical, mental and spiritual level, I keep coming back to the essential idea that the patient is responsible for his/her own recovery. My primary doctor should only be a guide for my journey to a more healthful existence.
So far my Tibetan doctor has been just this. My western doctors…. not so much.
I am not suggesting that jettisoning western meds in favor of Tibetan meds will cure me or even make my life easier. I have no idea if this will be the effect, but I know just embracing a system that empowers me as the patient, rather than speaks down to me as the ignorant patient, has lead to a swell of hopefulness and likely better health (currently waiting on results from my latest 2 week battery of Tibetan meds*). But once I made this decision two week, I was instantly transported to a far better place mentally than I have been in months. And this HAS to count for something.
As I continue to delve into the Tibetan med tradition, in order to understand it on a physical, mental, and spiritual level, I keep coming back to the idea that the patient is responsible for his/her recovery. My doctor is just a knowledgeable guide on my journey back towards health. And so far she has provided me with a map of well being that I would be extremely foolish to forgo in favor of a more destructive, invasive western treatment that would gurantee further complications. Umm… these are what I want to avoid. My Tibetan doctor's treatmetns allow for choice. She never dictates to me. She does push me towards the health of my whole being, complete being rather than just in one area, but that is her job.
She does not just focus on medicine based treatment. And neither should I.
* Since I wrote this my results from using the Tibetan meds for two weeks have come in. The level of protein in my urine stayed the same for the 1st time on months. While this is not ideal, decreasing numbers would be idea, it is very very welcome, as before the kept rising so swiftly. Exponentially.
I also got some amazing news on my GFR numbers. They went up a point to 47. Or exactly one point below where they were in June of last year.
So yes, the next battery of Tibetan meds begins on the 22nd.


text:
Written on: 28/09/2009
The food was plentiful but had no taste and lacked healthy choices. The entertainment was not very good. Staff were quite efficient and the cabin was ok. Princess Cruises, Sapphire Princess definitely not a holiday I would recommend unless all you want to do is get away to rest.
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