text:
|Publication number
|Publication type
|Application number
|Publication date
|10 Feb 2004
|Filing date
|22 Feb 2000
|Priority date
|22 Feb 2000
|Fee status
|Also published as
|Publication number
|Christian D. Kasper
|Original Assignee
|Stmicroelectronics, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (13), Referenced by (14), Classifications (18), Legal Events (4)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is also related to co-pending U.S. Patent Applications entitled "METHOD AND SYSTEM OF CONTROLLING TRANSFER OF DATA BY UPDATING DESCRIPTORS IN DESCRIPTOR RINGS"; "METHOD AND SYSTEM OF ROUTING NETWORK BASED DATA USING FRAME ADDRESS NOTIFICATION"; and "METHOD AND APPARATUS FOR CONTROLLING NETWORK DATA CONGESTION" all filed Sep. 30, 1998, in the name of the same inventor as this application and assigned to the same assignee. Accordingly, the contents of all the related applications are incorporated by reference into this application.
1. Field of the Invention
This invention relates generally to a method and system for controlling the transfer of network based data arranged in frames between a host and controller having shared memory and, more particularly, to a fencepost caching mechanism for receiving and transmitting descriptor ring updates.
2. Background of the Prior Art
Data networks have become increasingly important in day-to-day activities and business applications. Most of these networks are a packet-switched network, such as the Internet, which uses a transmission control protocol, frequently referred to as TCP/IP. The Transmission Control Protocol (TCP) manages the reliable reception and transmission of network traffic, while the Internet Protocol (IP) is responsible for routing and ensuring that the packets are sent to a correct destination.
In a typical network, a mesh of transmission links are provided, as well as switching nodes and end nodes. End nodes typically ensure that any packet is received and transmitted on the correct outgoing link to reach its destination. The switching nodes are typically referred to as packet switches, or routers, or intermediate systems. The sources and destinations in data traffic (the end nodes) can be referred to as hosts and end systems. These host and end systems typically consist of personal computers, workstations, and other terminals.
The network infrastructure employs routers that can determine optimum paths by using routing algorithms. The routers also switch packets arriving at an input port to an output port based on the routing path for each packet. The routing algorithms (or routing protocol) are used to initialize and maintain routing tables that consist of entries that point to a next router to send a packet with a given destination address. Typically, fixed costs are assigned to each link in the network and the cost reflects link bandwidth and/or cost. The least cost paths can be determined by a router after it exchanges network topology and link cost information with other routers. A traditional router is basically a computer dedicated to the task of moving packets of data from one channel to the next. Like most computers, it consists of a central MPU, bus, and memory but distinguished by its possession of multiple I/O channels usually managed by dedicated communication controllers.
A communication controller relieves a central MPU of many of the tasks associated with transmitting and receiving frames. A frame (sometimes referred to as a packet) is a single communication element which can be used for both link-control and data transfer purposes.
Most controllers include a direct memory access (DMA) device or function which provides access to an external shared memory resource. The controller allows either DMA or non-DMA data transfers. The controller accepts a command from the MPU, executes the command, and provides an interrupt and result back to the MPU.
These command operations often entail movement or control of various data structures. Data structures are used for the temporary storage of frames. They play a key role in the architecture of any successful router. Implementations vary, but generally one finds two species: ring buffers and linked lists.
A ring buffer consists of two components: descriptors and frame data buffers. Descriptors both describe and point to a respective frame data buffer within a shared system memory between the host and a controller. The descriptor ring is a circular queue composed of multiple descriptor entries containing pointers and information describing data buffers. Each descriptor ring is dedicated to a specific memory and mapped to specific channels within the controller. Each two-word descriptor entry within a descriptor ring is associated with one specific buffer in a system memory, such as the shared system memory between a network device, such as a controller and host.
The frame buffers are typically defined as blocks of memory containing frames for transmission or providing space for frame reception. Each transmit channel and each receive channel would use a dedicated descriptor ring. Whenever a frame exceeds the finite capacity of a single frame data buffer, the frame is said to "span" the buffer. An ownership bit in the first word of each descriptor indicates whether the host or controller owns the associated frame data buffer.
Ownership follows a specific protocol that must be adhered to by the controller and the host. Once ownership of a descriptor has been relinquished to the other device or host, no part of the descriptor or its associated buffer may be altered. The host gives the network device ownership of empty frame data buffers for frame transmission. Conversely, the network device passes ownership back to the host for transmit frame data buffers it has used and receive frame data buffers it has filled.
For frame reception, the host is required to provide the controller or other network device with ownership of contiguous descriptors pointing to empty frame data buffers. Once a frame is fully received by the controller, ownership of its constituent descriptors is then reassigned. The host is signaled regarding the event via an interrupt. The host is typically obligated to read a Master Interrupt Register (MIR) in order to surmise the meaning of the signal. Once this is accomplished, the frame may then be dispatched in some fashion and ownership of the relevant descriptors return to the controller.
In typical operation, the host "follows" the controller or other network device around the ring leaving "empty" descriptors in its wake for the controller to use. If the device gets too far ahead of the host, it can wrap around the descriptor ring and encounter descriptors it does not own. As a result, incoming frames could be lost if this were to occur.
For frame transmission, the device "follows" the host round a transmit descriptor ring leaving used descriptors in its wake for the host to reclaim. The host transfers ownership of descriptors to the device when it has one or more frames ready for transmission. Once a frame is fully transmitted by the device, ownership of its constituent descriptors is transferred back to the host for reuse. The host is signaled regarding this event via an interrupt.
In certain applications, the host may elect to use data buffers which are smaller in size than the frames that are actually received or transmitted. A single frame may therefore be forced to span multiple buffers. This type of system would allow frames to be dissected (scattered on reception) or assembled (gathered on transmission) by the controller. Multiple buffers can hold the constituent pieces of a frame by "chaining" or grouping the associated descriptors together. The chained descriptors are consecutive entries in a descriptor ring with the end-of-frame flag set in the terminating descriptor of the chain. In other words, data buffer of a descriptor entry which is owned but whose end-of-frame flag (EOF) is not set is considered to be part of a frame and not an entire frame. Scatter/gather buffering benefits frames crossing multiple layers of communication protocol. Rather than laboriously copying large buffers from one service layer to the next, small pointers are passed instead. These pointers are ultimately converted into or generated from frame descriptors.
During reception of large frames, the device "chains" or groups the descriptors together one by one as it fills each successive frame data buffer. When the end of the frame is received and transferred to the shared system memory, the end-of-frame flag is set in the terminating descriptor of the chain. During transmission, the controller is able to construct sequentially a single frame from contents of chained buffers. Transmission of the frame terminates only when it encounters a buffer whose descriptor has set the end-of-frame flag.
Fencepost buffering gets its name from the idea that rather than successively updating each spanned descriptor, only the terminal descriptors need to be altered. Thus, at most one, in the case that a packet spans a single descriptor, or at most two descriptors ever need to be updated. This relaxes the dependency between packet size and buffer management overhead. While the reduction of descriptor activity in turn reduces total bus traffic and further reduces packet latency, latency issues persist.
Therefore, a need existed to provide a system and method which reduces frame transfer latency in fencepost procedures. The system and method must permit descriptor transfer to and from memory in a reliable and efficient manner. The system and method must further reduce complications arising from instrumenting a ringbuffer. The system and method must further avoid resource race conditions between DMA and the CPU.
Accordingly, it is an object of this invention to provide a caching mechanism and method to support fencepost procedures.
It is a further object of this invention to provide a system and method which reduces frame transfer latency in fencepost procedures.
It is another object of this invention to provide a system and method which permit descriptor transfer to and from memory in a reliable and efficient manner.
It is still another object of this invention to provide a system and method which reduce complications arising from instrumenting a ringbuffer.
It is another object of this invention to provide a system and method which avoid resource race conditions between DMA and the CPU.
In accordance with one embodiment of this invention, a method for reducing transfer latencies in fencepost buffering is disclosed. In the method a cache is provided between a network controller and a host entity with shared memory. The cache is divided into a dual cache having a top cache and a bottom cache. A first and second descriptor address location are fetched from shared memory. The two descriptors are discriminated from one another in that the first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a reserve descriptor. The active descriptor is copied to the top cache. A command is issued to DMA for transfer of the active descriptor. The second descriptor address location is then copied into the first descriptor address. The next descriptor address location from external memory is then fetched and placed in the second descriptor address location.
In accordance with another embodiment of this invention, a method for reducing transfer latencies in fencepost buffering having chained descriptors is disclosed. The method provides a cache between a network controller and a network controller having shared memory wherein the cache has a top cache and a bottom cache. A first and second descriptor address location is fetched from shared memory. The first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a look-ahead descriptor. The ownership of the terminal descriptors describing a frame need to be updated. This requires writing a modified End of Frame (EOF) descriptor to cache before writing the Start of Package (SOP) descriptor. Commands are then issued to DMA for transfer of both cached descriptors to external shared memory. The second descriptor address location is then copied into the first descriptor address. The next descriptor address location from external memory is then fetched and placed in the second descriptor address location.
The foregoing and other objects, features and advantages of this invention will be apparent from the following more particular description of the preferred embodiments of the invention as illustrated in the accompanying drawings.
FIG. 1 is a high level block diagram of a plurality of network devices which are connected to a system bus and showing the host system microprocessor, bus arbitration logic and shared memory subsystem.
FIG. 2 is a high level block diagram of a network controller showing a plurality of ports, a communications processor, and a system bus interface control unit.
FIG. 3 is a high level block diagram of a buffer management and system memory used by an apparatus and network controller and showing the various descriptor rings.
FIG. 4 is a high level block diagram of the data structure and system memory showing the administration block, descriptor rings, and frame data buffer.
FIG. 5 is a high level block diagram of a descriptor and a buffer.
FIG. 6 is a high level block diagram of the fencepost descriptor caching mechanism of the present invention.
FIG. 7 is a high level block diagram of the TPR scoreboard.
FIG. 8 is a flowchart illustrating the process of using the fencepost caching mechanism of the present invention.
FIG. 9 is a flowchart illustrating the receive versus transmit interrupt state machines.
FIG. 10 shows the frame reception dialog.
FIG. 11 shows the frame transmission dialog.
FIG. 12A shows the DMA Command register and a description of the associated bits of the DMA Command register.
FIG. 12B provides a description of additional bits of the DMA Command register.
FIG. 13 is a high level block diagram of the DMA Command Queue.
Referring to FIGS. 1-5, a high level system diagram, which is illustrative of a system which would use the present invention is shown. As illustrated, a plurality of network controllers 40, also known as network devices, are coupled to a system bus 42, which is coupled to a host system 43. A host microprocessor 44 is coupled to the system bus 42, as is a shared memory subsystem 46. Each controller 40 has four ports 50, 52, 54, 56, that connect to respective high-level data link control layers, full duplex protocol lines 58.
Each network controller 40 is a high performance, four port, high speed network controller designed for use in next generation bridge and router equipment, as well, as any equipment requiring HDLC operation at T1 or T3 speeds. Each network controller 40 is preferably manufactured as a single chip.
As shown in FIG. 2, on the network side, the network controller 40 contains four ports 50, 52, 54, and 56, each with separate transmit and receive FIFOs allowing half or full duplex operation. Each port 50-56 has transmit data handler 60 that receives transmit clock signals (TCLK) and forwards data signals (T Data) to line transceivers 62. The receive data handler 64 also receives clock signals (RCLK) and sends data to and from the line transceiver 62. The ports also each include the illustrated transmit and receive First-In/First-Out (FIFO) logic circuits 66,68; the 512 byte transmit FIFO 70, control circuit 74, and the 512 byte receive FIFO 72. The 512 byte FIFOs 70,72 connect to the frame bus 76 and the control circuit 74 connects to the management bus 78. The FIFO logic circuits 66,68, and data handler 60,64 and the control circuit 74 work as appropriate transmit and receive circuitry for the transmit (Tx) and receive (Rx) 512 byte FIFOs.
On the system side, the controller 40 has a high speed, 32-bit system bus interface control unit (SBI) 80 which uses single cycle word transfers to minimize the controller's system bus usage and maximize its performance. The direct memory access unit (DMA) operation enables the device to become a bus master, and can use an efficient buffer management algorithm for store-and-forward or cut-through applications. The system bus interface control unit 80 includes the shared bus interface circuitry 82, bus FIFO controller 84, DMA bus master controller, also DMA controller, or direct memory access unit 85, the configuration data transfer engine 86, management data transfer engine 88 (which both communicate to the management bus 78), and frame data transfer engine 90, which communicates to the frame bus 76.
Although not directly accessible by the host, the network controller also contains an embedded 32-bit RISC processor called the Communication Processor Core (CPC) 92. The CPC 92 handles such activities as gathering the per port statistics, DMA mode buffer management and data transfers, chip self-test and host/chip primitive command/response exchanges. The CPC 92 contains a CPU 94, ALU 96, timers 98, RAM 100, firmware ROM 102, and interrupt handlers 104.
Internal buses tie all of the controller's subsystems together to support management and frame data transfers in an efficient manner. Separate buses, as well as the management bus 78 and frame bus 76, are used for respective management data and frame data to increase parallelism and thereby increase performance.
Designed for store-and-forward or cut-through applications, the network controller 40 uses an on-chip DMA engine and an efficient buffer management algorithm to transfer frames between system memory and the eight on-chip 512 byte FIFOs 70,74 via the 32-bit data or frame bus 42. In this operation, the controller 40 negotiates to become a bus master, takes ownership of the system bus, and then directly moves frames and administration data between the chip and system memory 46.
A typical frame transmission takes place as follows. All frames are transmitted by the network controller 40 from transmit frame data buffer 204 assigned to entries in a transmit descriptor ring 202 (FIG. 3). When the system is ready for the network controller 40 to transmit a frame, it relinquishes ownership of the associated transmit descriptor(s) and then does one of two things: (1) waits for the controller's transmit poll timer to expire causing the chip to poll the Tx descriptor in search of a buffer it owns, or (2) is issued a Transmit Demand (TDMD) via the System Mode Register (SMR) by the host. In either case, the firmware instructs the DMA to begin fetching burst-size amounts of frame data from the buffer and placing it in the appropriate port's transmit FIFO. This will continue until the FIFO is filled above the programmed watermark or until the end of the frame is encountered.
Once enough words to satisfy the programmed transmit start point are in the transmit FIFO 70, the transmitter circuitry, which includes the transmit FIFO logic 66, and line transceiver 62, initiates the transmission. The transmitter circuitry performs a parallel to serial conversion sending a continuous serial data stream. Opening flag(s) are sent followed by the frame data and then the Cycle Redundancy Check (CRC) or Frame Check Sequence (FCS) for the frame. FCS calculation starts with the first octet of the frame. As the transmit FIFO 70 empties below a watermark setting, the transmitter circuitry issues a private interrupt to the on-chip firmware 102 requesting more data be copied from system memory.
A cycle of emptying (by transmitter unit) and filling (by DMA) continues until the end of frame (EOF) has been written into the FIFO. When the transmitter removes the last data of the frame from the transmit FIFO, it optionally appends the FCS it has calculated (FCS appending by controller can be controlled on a frame by frame basis). The transmitter closes the frame by sending a closing flag(s).
As noted before, each transmit channel and each receive channel within each port 50,52,54, and 56 use a dedicated descriptor ring 202. A descriptor ring 202 is a circular queue comprising of several two-word entries called "descriptors 206". Each descriptor 206 (DTE) describes one frame data buffer 204. The first word 208 of a descriptor 206 entry contains information about its frame data buffer 204 and the frame, or partial frame, that the frame data buffer contains. The second word 210 of a descriptor 206 is a system address, a pointer to the top of its associated frame data buffer. Descriptor rings 202 can range in size from 1 to 8K entries. The network controller 40 is given a pointer to the top of each ring in the administration block 200 at initialization. Descriptor entries 206 are always accessed sequentially starting at the top of the ring. The last descriptor in a descriptor ring 202 contains a flag marking the end of the ring. The controller returns or wraps to the first entry in the ring whenever it encounters an end-of-ring flag (EOR) 213.
An ownership bit (OB) 212 in the first word of each descriptor 206 indicates whether the host or controller owns the associated frame data buffer. Ownership follows a specific protocol that must be adhered to by the controller and the host. The rule is simple:
once ownership of a descriptor 206 has been relinquished to the other part, no part of the descriptor or its associated buffer may be altered. The host gives the controller ownership of empty buffers for frame reception and full frame data buffers for frame transmission. Conversely, the network controller passes ownership back to the host for transmit buffers it has used and receives buffers it has filled.
For frame reception on any given port, the host 44 is required to provide the controller 40 with ownership of contiguous descriptors pointing to empty frame data buffers 204. After the very first words of the frame have been transferred to memory 46, a Frame Address Notification (FAN) interrupt is issued. Frame Address Notification interrupts are disclosed more throughly in co-pending application entitle "METHOD AND SYSTEM OF ROUTING NETWORK BASED DATA USING FRAME ADDRESS NOTIFICATION" filed Sep. 30, 1998, in the name of the same inventor as this application and assigned to the same assignee. The contents of the related application is hereby incorporated by reference. Once a frame is fully received by the controller, ownership of its constituent descriptors is then reassigned. The host is signaled regarding this event via an RINT interrupt. The host 44 is obligated to read a master interrupt register (MIR) in order to surmise the specific port issuing the signal. Once this is accomplished, the frame may then be dispatched in some fashion and ownership of the relevant descriptors returned to the controller.
In typical operation, the host 44 "follows" the network controller 40 around the descriptor ring 202 leaving "empty" buffer descriptors 206 in its wake for the network controller 40 to use. If the network controller 40 gets too far ahead of the host 44, it can wrap around the descriptor ring 202 and encounter descriptors 206 it does not own. Incoming frames may be lost if this occurs. The host is informed of any receive FIFO 70 overflows via an Early Congestion Notification (ECN) interrupt. Early Congestion Notification (ECN) interrupts are disclosed more throughly in co-pending application entitled "METHOD AND APPARATUS FOR CONTROLLING NETWORK DATA CONGESTION" filed Sep. 30, 1998, in the name of the same inventor as this application and assigned to the same assignee. The contents of the related application is hereby incorporated by reference. The host may then react to alter its behavior in order to avoid additional lost frames.
For frame transmission on a given port, the network controller 40 "follows" the host 44 around a transmit descriptor ring 202 leaving used buffer descriptors in its wake for the host to reclaim. The host only gives the controller 40 ownership of descriptors 206 when it has one or more frames ready for transmission. Once a frame is fully transmitted by the controller, ownership of its constituent descriptors 206 is passed back to the host 44 for reuse. The host 44 is signaled regarding this event via a TINT interrupt.
For some applications, the host 44 may elect to use frame data buffers 206 which are smaller in size than the frames received or transmitted. A single frame spans multiple buffers. This allows frames to be dissected (scattered on reception) or assembled (gathered on transmission) by the network controller 40. Multiple data buffers can hold the constituent pieces of a frame by "chaining" the associated descriptors 206 together. By definition, chained descriptors are consecutive entries in a descriptor ring with the end-of-frame (EOF) flag 214 set in the terminating descriptor of the chain. In other words, the buffer of a descriptor entry, which is owned but whose end-of-frame flag is not set, is considered to be part of a frame, not an entire frame. Scatter/gather buffering benefits frames crossing multiple layers of communication protocol. Rather than laboriously copying large buffers from one service layer to the next, small pointers are passed instead. These pointers are ultimately converted into or generated from frame descriptors.
During reception of a large frame, the network controller 40 chains descriptors 206 together one by one as it completely fills each frame data buffer 204. When the end of frame is received and transferred to system memory, the end-of-frame (EOF) flag is set in the terminal descriptor of the chain.
During transmission, the network controller 40 is able to sequentially reconstruct a single frame from the contents of chained buffers. Transmission of the frame terminates when it encounters a buffer whose descriptor has set the end-of-frame bit.
The network controller 40 optimizes bus utilization whenever three or more frames data buffers are chained together by updating the first and last descriptor entries involved. When the network controller 40 is finished with the buffers involved in a chained frame, it first returns ownership of the last descriptor and then it returns ownership of the first descriptor. These are the "fence posts" of the frame. Fencepost buffering gets its name from the idea that rather than successively updating each spanned descriptor, only the terminal descriptors need to be altered. Thus at most one, in the case that a packet spans a single descriptor, or at most two descriptors ever need to be updated. The host 44 assumes ownership of all the intervening frame data buffers even though they remain marked as owned by the controller. Hence, whenever the host encounters a host owned descriptor (not marked by the end-of-frame flag), it should assume ownership of all successive descriptors up to and including the next host-owned descriptor (with the end-of-frame flag set).
The flags and fields of the first and last descriptor in a "fence-posted" chain are updated by the controller 40 to provide accurate information about a frame once it has been fully transmitted or received. The first word 208 of the descriptor also includes a buffer size 216 and message size 218. For receive frames, the message size 218 (MSIZE) field of the first descriptor in the chain is updated with the byte count of the entire frame, not simply the byte count of the associated frame data buffer (since this is equal to the buffer size). However, the message size field 218 of the terminal descriptor will contain only the actual number of bytes occupied by frame data in its associated buffer. This allows the host to easily locate the receive status word stored in the first complete word following the frame data in the buffer (note that the four bytes of the status word are not included in the count stored in the MSIZE fields).
Fenceposting may be utilized quite effectively in transmit windowing applications. In this scenario the host has designated a set of frames to be sent. After transmission, if a remote host fails to reply with an acknowledgment within some finite amount of time, the entire set or "window" maybe resent. Rather than update the descriptors of each and every frame sent, the device may delay until the entire set of frames has been successfully transmitted. At which point only the two terminal descriptors of the entire set need be updated.
Referring to FIGS. 6-11, a caching mechanism 300 may be used to support fencepost procedures in a receive or transmit mode. The caching mechanism 300 would permit descriptor transfer to and from memory in a reliable and efficient fashion. The caching mechanism 300 would further reduce complications arising from instrumenting a ringbuffer. The caching mechanism 300 would also help avoid resource race conditions between DMA and CPU, and reduce frame transfer latency.
The CPU has access to limited local RAM which it divides between storage for traffic statistics, descriptor ring operations, command and control functions, and various scratch calculations required to construct and maintain a steady stream of commands to the DMA. The CPU spends the majority of its time deciding which commands (FIGS. 12A-12B) must be built, building the commands and then relaying them to the DMA. Access to local RAM can be blocked and the CPU stalled if the CPU is waiting for the DMA to complete a R/W operation.
The DMA in turn spends its time servicing the command stack, parsing the commands, arbitrating for the external system bus, and transferring data between external shared memory, the transmit and receive FIFO's, and local tri-port RAM. The DMA possesses a register stack (FIG. 13) which can hold up to a dozen commands. The depth of the stack was computed as a function of the maximum expected delay that four similar devices might experience from sharing a common bus. The stack frees the DMA to act in parallel with the CPU to a certain degree. It does however add an element of indeterminacy as the CPU generally can't be certain when any one particular command has been completed. Although the CPU is not required to poll or wait for the DMA to complete an operation, the DMA is obligated to stall the CPU whenever it accesses the local RAM.
A fencepost descriptor caching mechanism 300 was developed to support fence-posting operation. This is a non-blocking operation designed to avoid any resource constraints. The caching mechanism 300 has a two section cache 310: a top cache 312 and a bottom cache 314. The top cache 312 is used to store the End of Frame descriptor prior to a memory write back. The bottom cache 314 is similarly used to temporarily store the Start of Packet (SOP) descriptor.
The caching mechanism 300 requires every active channel to support a minimum of two, contiguous, resident, on-chip descriptors. Both descriptors are fetched from external memory at initialization time. Subsequent activation of the channel "consumes" the descriptors as their associated buffers are either filled or emptied.
The two descriptor locations are discriminated from one another via "TOP" 316 and "BOT" 318 address designations. The TOP 316 address is always the active or current descriptor in use. The BOT 318 descriptor is a descriptor which is held in reserve. When the TOP 316 descriptor is consumed, the BOT 318 descriptor is copied into the TOP 316 location and the DMA is instructed to fetch the next descriptor in the external ring. The DMA accomplishes this in a non-blocking fashion and the device is not stalled pending completion of this operation. Once the next descriptor is fetched, it is immediately written into the BOT 318 location. This procedure continues until one of two events occur: either an End of Frame (EOF) will be detected, or less probable, but still possible, a network or host interface error will occur.
Ring protocol requires that before ownership of a frame can be reassigned, the terminal descriptors must flip their ownership flags (OB). For this reason, the EOF descriptor is written back to external memory before the starting (SOP) descriptor. At EOF, the TOP 316 descriptor is edited to reflect the contents of the buffer and the OB is flipped. The descriptor is then copied to a predefined location in local memory (i.e., TOP-CACHE 312) while a two word command is issued to the DMA requesting transfer of the descriptor to the external ring. The DMA decodes the command and performs the transfer in parallel with the CPU.
Frame descriptors have been purposefully compressed to fit into two words in order to minimize the enormous overhead of bus traffic associated with data-structures. Use of the cache allows two descriptors per channel to be managed in local RAM. While one descriptor is active the other serves in a look-ahead or reserve role. Only the first word of each 2-word descriptor is actually stored in the cache and returned to the external ring. The first word contains the flipped ownership bit, relevant error flags, and byte count of the buffer. There is no need to store the second word, the buffer pointer, as it is never actually altered from the original image in the ring. The stall time for the CPU and the load on the system bus are both effectively reduced through these measures. The CPU avoids contention for local memory with the DMA by moving pending descriptor transfer to the cache. The DMA in turn minimizes both CPU stalls and bus overhead by a reduction of descriptor R/W cycles.
All receive and transmit frame activity has been split into three "event" horizons referred to as "SOP", "COP", and "EOP". The Start of Packet (SOP) event functions as a transition phase providing necessary state setup and performing various house-keeping chores. Data transfers are handled exclusively within the Continuation of Packet (COP) phase. There is considerable descriptor activity during this phase: descriptors (DTE) are consumed as their associated buffers fill up; and DTE's are fetched as needed whenever additional external memory buffers are required. The final transition is accomplished with the End-of-Packet (EOP) phase. Ownership of the frame is effectively transferred to the host entity while various data structures are updated locally in tri-port RAM (TPR) and in external shared memory.
All of the frame handling events are interrupt-mediated (FIG. 9). The receipt of a frame on any channel triggers a succession of interrupts beginning with a channel-specific SOP followed by one or more response vectors (RV) from the DMA as needed. A SOP generates an RV when it discovers that it does not own the current DTE image. As data accumulates in the RX FIFO, one or more COP's are generally issued until the DMA has successfully transferred the entire frame. The DMA identifies the end of the frame by triggering an EOP interrupt.
Several important differences exist between RX and TX operations beyond the obvious direction in data transfer. In contrast to frame reception, where the channel is responsible for initiating the sequence of events, transmission is initiated solely by the host via a Transmit Demand (TDMD) interrupt. The initial DMA data burst for RX is initiated from a SOP that transitioned to COP without an intervening interrupt source. All TX COP phases are entered via interrupts. In addition, during transmission, the DMA is not required to detect the terminal byte of a frame since the length of the frame is already known from the descriptor table entry (DTE) image. Control transitions to the EOP phase once the transmit COP phase issues a command to the DMA instructing it to transfer the terminating data-burst. There is no intervening EOP interrupt.
A more detailed description of the frame reception process can be followed from FIG. 10. The arrival of a frame on any receive channel generates an SOP interrupt which is then enqueued on one of three priority queues. Once all intervening interrupts have been serviced, the CPU will then relinquish control to this SOP, which will then proceed to check an on-board (TPR) channel-specific descriptor for ownership. If the device owns the descriptor (TOP) control will then transition to the COP phase. Otherwise, a command is built and issued to the DMA requesting that both descriptors (TOP and BOT) be refreshed from external memory. The SOP interrupt then immediately exits. The DMA wakes the SOP thread via a Response Vector (RV) interrupt when the descriptor R/W operation has completed. Although the SOP transitions into the initial COP phase, all subsequent COP interrupts are generated by the channel. The COP process consists of building and issuing commands to the DMA instructing it to either transfer a predefined data "burst" from the RX FIFO or, if the current buffer has been filled, to fetch the next DTE from the descriptor ring in external memory. Once the DMA detects it has transferred the terminal byte of the frame it proceeds to enqueue an EOP interrupt for the appropriate channel.
The EOP interrupt is the last phase in the transfer of a frame involving the device. The fencepost caching mechanism has been implemented primarily as a component of the EOP phase. The fields of the current or "TOP" descriptor are updated with the length of the frame and relevant error information while the ownership flag is flipped to "HOST". The frame is then evaluated whether it spans more than one descriptor. If not, then only the updated word of this DTE is copied to the TOP-CACHE address and the DMA is issued a command to return the word to its ring location in external memory. The 2-word descriptor in the BOT location (channel-specific) of the TPR is then copied directly into TOP in preparation for the next frame. The final EOP command to the DMA fetches the next available descriptor from the DTE ring and writes it into BOT.
A frame is said to "SPAN" descriptors if it requires multiple descriptors and their associated buffers for storage. In order to "hand-off" the spanning frame to the host entity, two descriptors must be returned to the ring: 1. the SOP DTE, or starting descriptor; and 2. the EOP DTE, or terminating descriptor. Ownership of both DTE's must be reassigned via setting the "OB" field in the first word of the descriptor. Any intervening descriptors are ignored and their ownership fields remain assigned to "DEVICE". Once the EOP DTE descriptor word is built and copied to TOP-CACHE a DMA transfer command will be issued. The first word of the SOP DTE descriptor is then reconstructed, and copied to BA-CACHE. A DMA transfer command is then issued with the additional request for a RINT interrupt to be signaled to the host entity once the transfer operation has completed. By delaying the RINT until the SOP DTE has been written back to the ring we effectively block the host from acquiring the frame too early. Non-spanning frames employ their single descriptor-transfer command to signal RINT. The RINT informs the host that a frame has been successfully received and that it may now proceed along the ring and retrieve the frame. The RINT is not channel-specific however and the host is obligated to read the Master Interrupt Register (MIR) in order to discern the responsible channel.
The device is no longer involved with the frame beyond this point. The host, however, must decide what to do with the frame now that it has control (forward it or delete it). Ultimately the host must release the descriptors and buffers back to the device pool. It runs the risk of dropping frames if it stalls or delays beyond a reasonable, calculable, interval. The rate of DTE consumption may be estimated by averaging frame size over some finite arrival interval for the effective arrival rate and dividing this into the product of the number of used descriptors and their respective buffer sizes. Studies of the Internet have demonstrated that arrival rates and frame sizes exhibit fractal behavior so reliance on these estimates may be unreliable.
Frame transmission is initiated by the host entity (FIG. 11). This is accomplished by a write to the System Mode Register (SMR). The four transmit channels are bit-mapped to the lowest nibble. A write will cause the DMA to generate a Transmit Demand interrupt (TDMD). If all previous transmit demand operations have either completed or been initiated, a copy of the SMR is then made for future reference while the SMR transmit control nibble is read-cleared. The four channels are serviced in a round-robin fashion and the SOP phase is entered for the first appropriate channel. Back-to-back TDMD's may be initiated by the host without any destructive, or for that matter useful, effects. Optimal transmit control requires the host to track channel-specific activity based on TINT acknowledgments.
The transmit SOP phase immediately commands the DMA to fetch two descriptors from the external shared memory rings and execution exits. The SOP thread is subsequently reentered via a Transmit Vector (TV) signal from the DMA after it has completed the transfer. The FIFO control logic is then enabled to generate COP interrupts via the Port Control Register (PCR) and the SOP phase terminates. The data and descriptor transfer operations of the transmit COP phase are effectively similar to the receive COP phase except that there is no interrupt transition to the EOP phase. After the last data transfer, the PCR register is cleared in order to disable further COP interrupts. The transition to EOP is then made. There is no necessity for an explicit transmit EOP interrupt since the end-of-packet field of the TOP descriptor image (previously set by the host) is readable during COP.
The transmit descriptor ring is updated in the same manner as the receive ring. For frames spanning multiple DTE's, the terminal or EOP DTE is written back first while the SOP DTE is written second. The BOT DTE is copied into the TOP address location and a look-ahead read is issued to the DMA for the next DTE in the ring. After the DMA completes the SOP DTE write to external memory it issues a TINT interrupt to the host. The host may then read the MIR to learn which channel was responsible for the signal. In the event the new TOP DTE is owned by the device a direct transition back to SOP can be made, albeit with a different entry point. Multiple or "chained" frames may be transmitted in this way without the necessity or incurring the overhead costs for individual TDMD's by the host.
The host should observe that the ownership of spanned descriptors will remain flagged as "DEVICE" owned. The descriptors may be reused for transmit but the ownership fields of the intervening DTE's must be reset otherwise the host runs the risk of issuing an additional or "babbling" frame. Alternatively, the "empty" descriptors may be added to the RX device pool after ownership of the terminal descriptors has been reassigned. In order to avoid descriptor ring collisions, reassignment of DTE ownership by the host should be done in the same reverse order as the device.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.
|Cited Patent
|Filing date
|Publication date
|24 Apr 1987
|12 Jun 1990
|Network Systems Corporation
|Network communications adapter with dual interleaved memory banks servicing multiple processors
|19 Apr 1989
|28 Aug 1990
|American Telephone And Telegraph Company
|Programmable data packet buffer prioritization arrangement
|29 May 1990
|4 Aug 1992
|Advanced Micro Devices, Inc.
|Memory management system and method for network controller
|28 Jul 1992
|29 Mar 1994
|3Com Corporation
|Network interface with host independent buffer management
|9 May 1995
|2 Jul 1996
|Advanced Micro Devices, Inc.
|Start of packet receive interrupt for ethernet controller
|6 Mar 1997
|28 Apr 1998
|Sun Microsystems, Inc.
|Method and apparatus for reporting the status of asynchronous data transfer
|29 Sep 1995
|14 Jul 1998
|Cirrus Logic, Inc.
|DMA controller arrangement having plurality of DMA controllers and buffer pool having plurality of buffers accessible to each of the channels of the controllers
|17 Dec 1997
|21 Mar 2000
|Advanced Micro Devices, Inc.
|Tracking availability of elements within a shared list of elements from an index and count mechanism
|27 May 1997
|11 Apr 2000
|Emc Corporation
|Method and apparatus for controlling the contents of a cache memory
|3 Sep 1998
|7 Nov 2000
|Advanced Micro Devices, Inc.
|System for transferring frame data by transferring the descriptor index data to identify a specified amount of data to be transferred stored in the host computer
|3 Dec 1998
|30 Jan 2001
|Advanced Micro Devices, Inc.
|Minimizing cache overhead by storing data for communications between a peripheral device and a host system into separate locations in memory
|18 Mar 1998
|6 Feb 2001
|National Semiconductor Corp.
|DMA configurable receive channel with memory width N and with steering logic compressing N multiplexors
|17 Dec 1999
|26 Mar 2002
|3Com Corporation
|Slave processor to slave memory data transfer with master processor writing address to slave memory and providing control input to slave processor and slave memory
|Citing Patent
|Filing date
|Publication date
|28 Mar 2003
|11 Oct 2005
|Fujitsu Limited
|Data transfer apparatus and method
|14 Oct 2003
|27 Dec 2005
|Broadcom Corporation
|Descriptor-based load balancing
|3 Dec 2001
|6 Feb 2007
|Sony Corporation
|Communication interface method and device utilizing direct memory access data transfer
|14 Mar 2007
|28 Oct 2008
|International Business Machines Corporation
|Non-fenced list DMA command mechanism
|30 Aug 2006
|12 Oct 2010
|International Business Machines Corporation
|Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment
|10 Dec 2008
|25 Jan 2011
|International Business Machines Corporation
|Apparatus, computer program product, and system for completing a plurality of chained list DMA commands that include a fenced list DMA command element
|3 Dec 2001
|16 Jan 2003
|Koichi Sugiyama
|Data transfer method, data transfer device, communication interface method, and communication interface device
|28 Mar 2003
|2 Oct 2003
|Fujitsu Limited
|Data transfer apparatus and method
|31 Jul 2002
|5 Feb 2004
|Dimambro Francesco R.
|Load balancing packet transmission among multiple transmit rings
|14 Oct 2003
|14 Apr 2005
|Broadcom Corporation
|Descriptor-based load balancing
|6 Dec 2002
|2 Feb 2006
|Andrea Bragagnini
|Method for direct memory access, related architecture and computer program product
|30 Aug 2006
|18 Jan 2007
|Day Michael N
|Method to Provide Atomic Update Primitives in an Asymmetric Heterogeneous Multiprocessor Environment
|14 Mar 2007
|26 Jul 2007
|King Matthew E
|Non-fenced list dma command mechanism
|10 Dec 2008
|9 Apr 2009
|Matthew Edward King
|DMA Completion Mechanism
|U.S. Classification
|710/22, 711/147, 710/24, 711/129, 709/213
|International Classification
|Cooperative Classification
|European Classification
|22 Feb 2000
Owner name: STMICROELECTRONICS, INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KASPER, CHRISTIAN D.;REEL/FRAME:010575/0062
Effective date: 20000211
|20 Jul 2007
|Fee payment
Year of fee payment: 4
|28 Jul 2011
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|28 Jul 2015
|Fee payment
Year of fee payment: 12


text:
When I was a teenager and
I saw one of those plastic lids
they place on top of paper cups
in fastfood restaurants and the like
with raised buttons you can press
marked COLA, DIET and ICED TEA,
I always would imagine that
someday a thousand years from now
a scientist who represents
some future civilization,
while excavating the remains
of our decaying cityscape,
would uncover this flimsy disk
(which will outlast the cup and me)
and studying its hieroglyphs
he would declare that this forebear
had once enjoyed a DIET drink.
Monday, December 17, 2007
Monday Musing: Plastic Lids
When I was a teenager and
2 comments:
- nola32 said...
when i was a teenager i used to press all of the little buttons so that it was impossible to discern what i was drinking. i love to confuse future generations.
- December 17, 2007 at 2:32 PM
- Meeg said...
My brother would do that too. I would tell him he was messing up the archaeological record... well, not in so many words.
- December 17, 2007 at 2:34 PM

subset: commoncrawl


text:
+ Beautifully crafted characters and universes
+ Addictive game play
+ Multiple characters and power-ups for survival
+ Awesome sound effects
Nice game something different.....
DEFINITELY SOMETHING NEW AND UNIQUE!! Great job guys!! Amazing graphics and concept.. Lvl design is good too but I feel needs to be bit more forgiving cause somehow the excitement level drops at the initial gameplay this might not work for user retention. I want to give 5 stars but for that u guys need to do some serious game testing (faced a few collider issues)and add a bit more user experience and I bet u'll see the difference. This game definitely has the potential.. U guys need to figure somethings out.
Awesome game! Beautiful graphics, smooth gameplay and the design is absolutely new, nothing I've ever played!!
Nice game. Some thing different and interesting.
I have just installed this game and it seems to very nice and unique...good luck..
Love the mechanics and gameplay!! Had fun!!
Nice game
Nice game
Well the game controls it took some time to get use to it..
Very addictive to play. Awesome sound and graphics....my fav. at the moment...
It's Damm cool


text:
The things they say
"It's a lock. I don't think (Ben Affleck) can be stopped. It's a great movie, he did a great job directing it, and there's a lot of good will for him. I think people like him. Really, why shouldn't he win?" Ben Affleck's brother Casey is convinced the actor/director's thriller Argo will win the Best Picture Oscar at the upcoming Academy Awards.


text:
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text:
I've been wanting to make this 30-second mayo for months. I've had my share of mayo batches turn into soup rather than the thick, rich, creamy, marvelously textured mayo you see in the pictures below. If the weather is too humid (rare here in Phoenix but it does happen!), if…Read More
If you've been keeping up with my blog (I know it can be difficult with so many blogs to follow and so many emails coming into your in box daily and all of the other things you want to fit into a day), you might have seen my recent, but…Read More
The Ancestral Table: Traditional Recipes for a Paleo Lifestyle by acclaimed home chef and paleo blogger Russ Crandall is a glorious celebration of history and heritage of traditional and gourmet cuisines from around the world. The recipes (all gluten-free), easily accessible to both novice and experienced cooks and chefs and…Read More
Maybe you've heard about the benefits of Bone Broth (aka Bone-Building Broth), Ghee made from the fat skimmed from the milk of pasture-raised cows, and Compound Butter, but do you have the time to make them? If not, there's an easy solution if you live in the Phoenix metro area!…Read More
I'd heard about but have never tried okra until about 12 years ago. They way I cooked it, it came out slimy. I was not impressed. Flash forward 5 years, when I tried it again and had the same result. Flash back to a year ago, when a friend told…Read More
Of all of the recipes I tried fromPaleo Happy Hour, The lightly floured (well, sort of floured but not the usual kind) and baked Onion Rings are my favorite. They were a little fussy to make but oh so worth it for the mix of sweet, salty, savory, crunchy goodness….Read More
Since vegetables make up the largest volume of food that I eat, I'm always looking for great ways to season, sauce, and dress them up in different ways. Sure, I have plenty of my own recipes and I like to see try recipes that other people have created. When I…Read More
My friend, Heather, and I had high hopes as we set out to review a new restaurant: Pizza Fusion. They call themselves the "greenest restaurant in America". They use tables made from reclaimed wood sources, counter tops made from recycled glass bottles, paint without VOCs (volatile organic chemicals). More than…Read More
Looking for an easy recipe to bring to a holiday potluck, party, or gift exchange or something you can make for the people on your gift list? I've got just the recipe, actually many recipes, for you. I'll post one below and additional ideas as well. You can savor the…Read More


text:
Internships and projects
International experience, which is essential these days and highly valued by recruiters, plays a dominant role at Iteem, as evidenced by the 8- to 9-month internship in an international company (in a non-French speaking country) that Iteem students are required to undertake at the beginning of their fourth year of studies (from June to end-February).
The goals of this internship are mainly:
- To participate in executing a company project and to be a project participant like any other. There are really no specific requirements regarding the type of mission. It just needs to allow the student to achieve the educational objectives of their studies. Depending on the student, the missions may focus on:
- Business development: Setting-up a new subsidiary, launching a new product
- Logistics: Implementing warehouse processes and concepts, improving delivery processes
- Production: Implementing production monitoring indicators, quality processes
- Information technology: Developing software, implementing E-commerce or E-marketing sites.
- To discover a new company and country culture: the host countries cannot be French-speaking. Once again, the destinations vary depending on the students: South Africa, Austria, Australia, Bangladesh, Burundi, China, Chile, Egypt, the United Arab Emirates, India, Indonesia, Italy, Malaysia, Mexico, Norway, the Czech Republic, Romania, Russia, Sweden, the USA…
The purpose of the fourth-year, 8- to 9-month company internship abroad, which is an overwhelming success with the students and the companies, is to learn how to work in a different culture as well as to gain an enriching professional experience that is highly valued by companies.
This special part of the Iteem programme constitutes a force that drives student to acquire independence and maturity.


text:
Our website uses cookies for technical, analytical and marketing purposes. Here is more information. If you agree to this, just keep browsing.
La Estancia Busuanga Resort offers an airport shuttle during limited hours for PHP 6000.00 per vehicle roundtrip. Guests can splash around at the outdoor pool or grab a bite to eat at the restaurant. Other highlights include a terrace and a garden.


text:
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3 Month
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text:
Moaza was born with beta thalassaemia, a blood disorder that is inherited and can be fatal if not treated. Chemotherapy, which is harmful to the ovaries, was needed before she received bone marrow donated by her brother.
Mom wants to birth dead daughter's baby
A 60-year old woman is fighting in the Court of Appeal, to be granted the right to birth her own grandchild, using her dead daughter's frozen eggs, harvested and stored at a fertility clinic in West London.
Dolce And Gabbana Responds To Elton John's Boycott
Italian designers Domenico Dolce and Stefano Gabbana have responded to the #BoycottDolceGabbana campaign trending on Twitter, after the pair made a remark that gay adoption was unnatural, and IVF children were 'synthetic'. Elton John's boycott of Dolce & Gabbana draws celeb support–read their responses! http://t.co/PioeeJpEV7 — E! Online (@eonline) March 16, 2015 Singer Sir Elton…


text:
The 2008 National Underclassmen Combine season started off with a bang this past weekend at Apache Junction High School, in the Phoenix, Arizona area. Leading the way during the first event of the season was an outstanding performance by sophomore Justin Rodriguez of Marcos de Niza High School, who was named the Overall MVP.
Rodriguez (6 feet 1, 170 pounds) was fantastic during individual drills and unstoppable during the one-on-ones. He was equally impressive during the combine events, as he had a 31.5-inch vertical, 9'7" broad jump, 4.51 shuttle, 4.56 40, and 13 reps on 155 pounds. Another receiver who excelled in Phoenix was sophomore Deche' Milburn of Buena High School, who took home the WR MVP. The 5-foot-11, 167-pound Milburn showed a great combination of route-running ability and hands, to dominate a majority of the defensive backs in attendance. During the combine events, he finished with a 26-inch vertical, 8'6" broad, 4.43 shuttle, 4.69 40, and 10 reps on 155 pounds.
The RB MVP Patrick Browne from Tolleson Union High School. The 5-foot-7 ½, 181-pound sophomore showed great feet, athleticism and hands during the one-on-ones, plus during the combine events he had a 4.57 40, 4.50 shuttle, 29.5-inch vertical, 8'6 ½" broad, and an impressive 28 reps on 155 pounds. The top combine performance by a freshman also came at the running back position, as Buena High School RB Xavier Cooper took home the Freshman Combine King award. The 5-foot-6 ½,145-pound Cooper had a 30.5-inch vertical, 10' broad, 4.70 shuttle, 4.52 40, and 12 reps on 135 pounds.
Article Continues Below
The top overall freshman in Phoenix was Carlton Williams of Westview High School, who took home the Freshman MVP. The 5-foot-8, 165-pound Williams was unstoppable during one-on-ones, and had a 4.52 shuttle, 4.75 40, and 8'8" broad. One of the most memorable performances in Phoenix was turned in by freshman Derek Hubbard of La Joya High School. Hubbard ran a blazing 4.36 40, which not only won him the Fastest Man Award, but also made him the fastest freshman of all time at the National Underclassmen Combine. The 5-foot-5, 139-pound Hubbard also had a 29-inch vertical, 9'5" broad, and 4.62 shuttle.
The remaining awards in Phoenix all went to sophomores. Coming from host Apache Junction High School was DL MVP Cy Maughmar. The 6-foot-1, 256-pound lineman had a good combination of speed and power, plus he showcased some powerful rush techniques. With 25 reps on 185 pounds, Maughmar also took home the Strongest Man Award at the event. Along with his power numbers, he also had a 24-inch vertical, 7'8" broad, 5.01 shuttle, and 5.22 40.
The QB MVP went to Kevin Spain of Horizon High School, who at 6-foot-0 ½ and 180 pounds, showed pinpoint accuracy, great drops, and a quick release. The sophomore also had a 25-inch vertical, 8'11" broad, 4.91 shuttle, 4.91 40, and 10 reps on 155 pounds during the combine events.
Sophomore Ben Cannon (6-foot-0 ½ and 258 pounds) of Tuscon High School was the winner of the OL MVP. Cannon showed great technique and drive during the one-on-one portion of the event. He also had a 7'1" broad, 5.22 shuttle, 5.53 40, and 14 reps on 185 pounds. The LB MVP went to Austin Garday of Centennial High School, who at 5 feet 11 ½ and 198 pounds, did not give up any pass completions during one-on-ones and is a physically dominating player. He also showed that during the combine events by getting 23 reps on 155 pounds, plus an 8'2" broad, 4.54 shuttle and 4.71 40.
The last positional award of the event went to sophomore Yusef Muhammad of Chandler High School, who won the DB MVP. The 5-foot-8 ½, 145-pound Muhammad showcased his athleticism throughout the event, plus he possessed great footwork and skills in coverage which helped him break up several passes during one-on-ones. During the combine events he had a 26-inch vertical, 8'7" broad and 4.74 40.
The sophomore Combine King was LB Raymon Abreu of Marcos de Niza High School. Along with getting an incredible 37-inch vertical, 9'2" broad, 4.38 shuttle, 4.48 40, and 11 reps on 155 pounds, the 5-foot-10 ½, 164-pound Abreu was also impressive during one-on-ones.
And finally, the Leadership Award was won by sophomore QB Dain McFarland of Mountain Ridge High School. Aside from having very impressive passing skills, he also showed tremendous command over his receivers during the positional drills and one-on-ones. The 5-foot-10 ½, 166-pound McFarland also ran a 4.32 shuttle and 4.71 40.
Up next for the National Underclassmen Combine are stops in Miami/Boca Raton, Birmingham, and Las Vegas during the weekend of February 16-17.


text:
AURORA, Ill. (Jan. 24, 2008) — The three-successive Toyota AMA Arenacross Series split weekends to begin the 2008 portion of the season gave way this weekend to one, two-night race at Louisville's (Ken.) Broadbent Arena as Round 10 of the 2007-'08 Toyota AMA Arenacross Series gets set to tee it up for what will be the hottest motorsports ticket in the region this weekend.
As those close to the Toyota AMA Arenacross Series pointed out last week, the championship race hasn't been this close and this exciting — with a total of three racers vying for the lead — in quite some time.
However, with the good comes the bad and it is that the Toyota AMA Arenacross Series will have to do without its defending 2006-'07 champion — Bad Boy/TUF/Honda's Danny Smith — for a yet-to-be determined amount of time. Last weekend at Dayton's Nutter Center, Smith broke his collarbone and it looks like he will not be able to defend his title.
Coming out of the whoop section, Smith lost the rear end of his bike during practice last Saturday, high-sided, lost the bike — then landed back on top of it.
"The bars stabbed me right in the collarbone and it broke, I worked so hard to get ready for this season, to defend the title — it's really disappointing. This is the first bone I've broke in eight years. But it could have been worse. I'll be there watching it go down from here on in.said Smith.
Reportedly, his doctor said: "Six weeks minimum – with or without surgery.
Smith said that one of the reasons for his rough luck this year was the way he had to adjust to the new 250F rule. Though he agrees with the concept, he was one of a few riders — including Robbie Reynard (Reynard Modifications/Suzuki) — that's had a tough time adjusting to the what he called the "all out racing on the 250F versus the 450F, which Smith said was "more my style.
"I knew it was going to be harder for me coming into the season, he said. "I had some good races, and some not-so-good races. But the bottom line was I struggled and never could quite get it going.
Smith's team owner, TUF Racing's Dave Antolak, backed Smith 100-percent throughout the year. "Danny's riding real well. He's bummed about his results, but we're not bummed about him. You need some luck in racing and this has just not been his year. Antolak said that last week and it rang true again in Dayton. Smith was some 70 points off the podium pace (219-149) behind Brock Sellards (Monster/Babbitt's/Kawasaki) after the Dayton round and his return, if possible, would be more for pride than anything else.
We put Smith's feet to the fire and asked him what his take was on the Chad Johnson/Kelly Smith/Brock Sellards title chase. "I definitely see it coming down to the wire — at least as close as it was last year, he said. "Chad won't run away with it. Maybe he could if there was one guy, but not two. He'll (Chad) have to work harder because Brock's been beating him out of the gate pretty consistently. And we all know how important starts are in arenacross. But Chad's been fast for sure.
"The guy that eventually wins will get the advantage with the starts and he's got to have it right upstairs.
Last year at Broadbent Arena, Carolina Xpress/Suzuki's Jim Neese won the Toyota AMA Arenacross Series' opening night main event while Ohio's Brock Sellards (Monster/Babbitt's/Kawasaki) took top honors in the Saturday night main event.
Said Sellards: "We had a great crowd in Louisville last year and this year should be no different.I'm looking forward to racing in front of a packed house both nights at Broadbent Arena.
"We all get back together in Louisville, added Toyota AMA Arenacross Series announcer Tim Cotter. "The split series didn't hurt us at all. We had the highest-ranked rider win in New Mexico (Team Faith/Yamaha's Kevin Johnson) and the hottest racer in the Toyota AMA Arenacross Series win in Dayton — Brock Sellards.
Live Nation's Robert Hansen checked in from Albuquerque with supercrosssonline.com's Jim Holley and Jason Weigandt during the live broadcast of the Anaheim 2 Monster Energy® Supercross race and gave fans an update on the action. He also had this to say about the upcoming Louisville Toyota AMA Arenacross Series round: "The Johnsons (Kevin and FiberWise/Yamaha's Keith) were on fire last week in Albuquerque and Keith was not happy having his little brother whip on him in front of the home crowd. This weekend both of them will have their hands full with all the regulars at Louisville. When the Toyota AMA Arenacross Series doesn't split, the two-night rounds always produce some surprises. The (Louisville) track is long and narrow with unstable dirt, so look for a shake up in the points after this weekend.
The Broadbent Arena floor Hansen speaks about is 39,000 square feet, or 137 feet wide and 310 feet long. The seating capacity at Broadbent is around 6,600 people and capacity crowds are expected. According to many on the Toyota AMA Arenacross Series, they've wicked it up with the opening ceremonies — with lots of pyrotechnics, show lights and rider entrances — much like the opening to a Monster Energy® Supercross races.
Cotter also said to keep an eye on the feud building between Reynard and Kelly Smith. The two got into it on Saturday night in Dayton and Reynard ended up grabbing Smith by the throat. "A lot of drama that's not going to be extinguished anytime soon, said Cotter. "I even got roosted in the skirmish!
2007-'08 AMA Arenacross Class Point Standings
1. Chad Johnson, Hon, 232
2. Kelly Smith, Kaw, 222
3. Brock Sellards, Kaw, 219
4. Teddy Maier, Hon, 195
5. Kevin Johnson, Yam, 188
6. Keith Johnson, Yam, 185
7. Danny Smith, Hon, 149
8. Jim Neese, Suz, 144
9. Tommy Hofmaster, Yam, 141
10. Nathan Skaggs, Hon, 138
Tickets for the Jan. 25-27 Toyota AMA Arenacross Series at Louisville's Broadbent Arena are available through www.arenacross.com, at the Broadbent Arena Box Office, all Ticketmaster outlets, online at www.ticketmaster.com or charge by phone at (502) 367-5001. Fees and handling may apply. Show time is Friday at Saturday, 7:30 p.m., Sunday (amateurs) at noon. Doors open Friday and Saturday at 6:30 p.m., Sunday at 11 a.m. Friday and Saturday advance tickets are $20 to $25 for adults, $5 for kids ages 2-12. Sunday's tickets are $20 for adults, $5 for kids. All tickets $2 more day of show.
Live Nation is the future of the music business. With the most live concerts, music venues and festivals in the world and the most comprehensive concert search engine on the web, Live Nation is revolutionizing the music industry: onstage and online. Headquartered in Los Angeles, California, Live Nation is listed on the New York Stock Exchange, trading under the symbol "LYV." Additional information about the company can be found at www.livenation.com under the "About Us section.


text:
Charles Stanley Quotes About FathersQuotes about: Fathers
Our heavenly Father understands our disappointment, suffering, pain, fear, and doubt. He is always there to encourage our hearts and help us understand that He's sufficient for all of our needs. When I accepted this as an absolute truth in my life, I found that my worrying stopped.
Think about the comfortable feeling you have as you open your front door. That's but a hint of what we'll feel some day on arriving at the place our Father has lovingly and personally prepared for us in heaven. We will finally - and permanently - be 'at home' in a way that defies description.
The Bible tells us that God will meet all our needs. He feeds the birds of the air and clothes the grass with the splendor of lilies. How much more, then, will He care for us, who are made in His image? Our only concern is to obey the heavenly Father and leave the consequences to Him.
Charles Stanley
- Born: September 25, 1932
- Occupation: Pastor
- Cite this Page: Citation


text:
Hi there, I just put an SD card in my new One (M8) (AT&T Stock ROM) and formatted it, but the card seems to be read only. Is there any easy way to be able to write to it directly on the phone?
|external sd card, read only
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High Quality Pit Bull Harnesses
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So You Want a Pit Bull?
Thinking about getting an American Pit Bull Terrier? Read this first.
Training articles and tips to a well trained Pit Bull
Training articles and tips to building a strong bond and having a well trained companion
Having a healthy Pit Bull is having a happy Pit Bull.
Health related articles, tips, and information for a healthier pet.
Ten Facts about Pit Bulls
Did you know a Pit Bull drug dog has the largest recorded drug find in Texas history?
Therapy Dogs - Pit Bulls As Therapy Dogs
Pit Bulls make excellent therapy dogs. One example is Hershey. A therapy dog who happens to be a Pit Bull living in Canada. Read Hershey's story here.
Drug and Bomb Detection Dogs - Pit Bulls As Detection Dogs that Sniff out Bombs and Drugs
Pit Bulls make excellent detection dogs due to their drive. This is the story of Neville. A dog that was doomed by Canadian breed specific legislation but beat the odds. Read Nevilles story today.
Pit Bull rescue resources and organizations
Rescue is an excellent option for finding the right dog for you and your family.
Support Pit Bull Rescues
Rescues and the people who operate them do great work for our breed. Learn how to show your support by reading this page.
Wonderful pictures of Pit Bulls and their owners
Our photo gallery is by far one of the most enjoyed sections of Pit bull lovers.
Tough toys for your Pit Bull
These dogs can destroy even the most "tough" of the toys. We have found some that stand the test of time.
American Pit Bull Terrier books.
It's not easy sifting through the junk online. Find books.
The Top Ten Reasons Why You Can't Trust Vicious Pit Bulls
Ten reasons why you should fear the Pit Bull
Blue Pitbull - Pitbull Puppies and other Destructive Forces
Yet another blue pitbull or pitbull puppy for sale. If you're interested in buying an American Pit Bull Terrer, read this page.
Fighting Pit Bull - Dog Fighting and the American Pit Bull Terrier
In this article you'll learn a bit about the history of Pit Bulls and dog fighting.
Dog Names
Finding the perfect name for your Pit Bull
Pitbull Attacks: Deadly Pit Bull Attacks and Why They Happen
Pitbull attacks are on the rise in the United States. Following is an examination of why these attacks happen and some ideas on preventing them.
Dog Boarding - Pit Bull Boarding Tips
Choosing the right boarding facility can be tough. Follow the tips in this article to decrease your boarding headache.
Pit Bulls in Denver
Pit Bulls in Denver are being seized and killed because of breed specific legislation. Read more here.
Stop the Banning of Pit Bulls
Download petitions to fight breed specific legislation at this page.
Pit Bull Puppies - The Curse of Cute
Read about Pit Bull puppies and the impact they have on over population.
Two Pit Bulls = Bad Idea
Before you go out and get two Pit Bull puppies or add another Pit Bull to your life read this article.
Pit Bull Lovers Site Map
Easily find anything on the site by visiting the Pit Bull Lovers site map page.


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Katraj Snake Park in Pune is a famous conservation park boasting a vast collection of snakes, reptiles, birds and turtles. It later became part of the Rajiv Gandhi Udyan in 1999. There are over 160 species of snakes here, of various shapes and sizes. The prize collection is a 6 years old, nine feet long King Cobra..
The Katraj Snake Park of Pune became functional in 1986, by the efforts of Mr. Neelam Kumar Khaire, aided by the Pune Municipal Corporation. Mr Khaire is not only the Director of the park but also a snake lover himself. He has introduced novel techniques of communication such as providing information about snakes for the blind through braille.
Information about snakes is exhibited in a library within the park. A zoo has just been added, making it a popular tourist destination, particularly for children. This snake park is well-known for its pro-wildlife activities. It has organized many snake festivals and snake awareness programs to clarify doubts and destroy fears about this species. During Nagpanchami, the Katraj Snake Park at Pune arranges programs to discourage ill-treatment towards snakes.
Major Attractions
Among the chief attractions of the park, rare species of Brown Palm Civet, nine feet long King Kobra brought from Sunderbans, some rare species of birds and turtles are a few.
The lush green garden beside the snake park is yet another attraction and a soothing sight to your eyes.
Slightly outside the city proper, Katraj Snake Park is located along the Pune Satara Highway near the Bharati Vidyapeeth University. The Katraj Snake Park is 8 kilometers from Pune, close to the Katraj Bus Depot.
Katraj Snake Park is a popular wildlife zone and tourist spot in Pune.
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Item Description:Pediped Isabella (Chocolate Brown) Excellent used condition. Size 0-6 months. These are adorable shoes! T are some minor scuffing on the toes as you can see in one of the photos. But can definitely be fixed with a little shoe polish. I will include the box if you want it. Please read the terms before bidding. I only accept PAYPAL!! I only ship to confirmed addresses. Please email me before bidding if you have less than 5 feedbacks. If you have any questions, please email me before bidding. Payment is due 5 days from the auction ending. I think that is very reasonable. I am flexible only if you email me to let me know your circumstances!
I am a stay-at-home mom of two children. I have a three-year-old son and a one-year-old baby girl! I am just starting to sell my children's clothes, so please check back often to see my other auctions. More to come!!
I wash both of my children's clothes in Dreft and I always wash according to the tags! We are a smoke free home. I have a Cocker Spaniel in our home, but he does not lay on the clothes or anything. Ha ha!
I do not accept returns unless t is a major problem with my listing. I try my best to represent my clothing well, because I understand the buyer's perspective. I definitely buy more clothes than I sell.... read more


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Kathy Brodie, "Observation, Assessment and Planning in The Early Years: Bringing it all together"
2013 | ISBN-10: 0335246702 | 184 pages | PDF | 11 MB
Children develop and learn best when their environment is tailored to their individual needs, supported through careful observation, informed assessment and dynamic planning - a cycle which is the bedrock of good early years practice.
Although the EYFS recommends that observation, assessment and planning should be linked in a constant, cyclical process, in practice this can be a significant challenge. This book presents an integrated framework which puts the cycle into practical terms, bringing it all together to ensure a seamless process and to support you in this vital part of your work.
The focus is on the critical links within the cycle and combines theory with proven good practice, including:
Making and recording observations effectively and efficiently
How observations should inform next steps, assessment and planning
Bringing all the information together into a cyclical process
Exploring potential challenges
Using reflective practice to refine and improve your techniques
Rich in practical examples and case studies that illustrate how the cyclical framework works in practice, this is an excellent resource for early years practitioners and students looking to improve their observation, assessment and planning techniques.
Download link:
Buy Premium To Support Me & Download with MaX SPeeD!


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I tend to agree with the OP on most points that he makes.
-Graphics/Textures- I am astounded at the beauty that Rockstar managed to muster out of current generation consoles, the game at many points has left me in awe of how beautiful and realistic it is.
The water is something that I always find myself marveling at every time I play, only to be rivaled by the cities night lights from the air.
-World Design- I really feel as though some areas are amazing while some seem sloppy and not very thought out. The Beach is a great area with a perfect transition of 3 different environments, the transition from city to beach to ocean is very well done and spaced perfectly.
The city has some really interesting areas but far to many areas that are just flat out boring and lack the ambiance of the rest of the area.
The countryside I feel lacks that special something that gives me the urge to return to, I always feel like I just want to bypass it completely by flying to my destination as opposed to driving through it.
The only real strong point I feel is the fact that they gave us some huge mountainous areas that make for some great fun with a vehicle.
-Missions- I am split on, while i enjoyed most I feel as though they lacked that epic sense that we have gotten from some of the former missions of past GTA titles.
I cannot recall any real memorable moment that I thought "wow, that was amazing".
They just seemed rather bland and I feel as though they were overly easy to accomplish, I only recall actually having to reattempt a mission once or twice in my whole campaign.
-Driving- This is another spot that I feel kind of split on, although i have had some epic close calls and amazing high speed driving sessions, I feel that they lack that sense of accomplishment due to the fact that handling and driving in general is very easy.
So to sum up my feelings, I think the game is far to massive to be evaluated as a whole, there are some really strong points and some rather weak ones.


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2014 Topps Valor Derek Carr Rookie Shield Honor 2 Color Patch Auto RC #/75
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Up for auction is a 2014 Topps Valor Derek Carr Rookie Shield of Honor Autograph Patch Strength Parallel #72/75. This card contains an authentic autograph of Derek Carr, also contains an authentic piece of memorabilia of Derek Carr, it's a 2 color patch. All my cards are in NrMt to Mint condition, unless otherwise stated. Please check out my other auctions.
Winner agrees to pay $2.35 for shipping and handling. I accept PAYPAL as payment method. US bidders ONLY please, unless you got my permission. I am usually able to ship the next day (excluding Sunday) after I receive payment, by USPS first class mail. Thanks again and have fun!


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I asked my Mum where she would like to go, or what she would like to do, and she decided on afternoon tea at Chewton Glen, a 5-star luxury country house hotel just on the edge of the New Forest in Hampshire, and a 7-minute drive from Highcliffe Castle in Dorset (which, history geek alert, became the residence for Harry Selfridge, the owner of Selfridges. Who else is loving Mr Selfridge on ITV by the way?!). Chewton Glen is a renowned boutique hotel and the only privately owned 5-star in the UK. Over the years we've had many milestone family events at this hotel so it holds very special memories.
My Mum is very special to me for two reasons. We love doing all the usual mother, daughter things, especially shopping together when we have been known to buy the same things! But the second thing that makes my Mum so special is how supportive she is of everything I do. Not only that, but we truly are a dream team because skills and personality wise we are complete opposites so we work in perfect harmony. My Mum does so much to help me run Beauxoxo. In fact, if it wasn't for her support there would be no Beauxoxo quite frankly so I owe her the world for this. She's my bestest friend and biggest support and I'm so thankful to have her in my life.
And so last Sunday we arrived at the impressive gates of Chewton Glen and drove towards the beautiful gothic mansion building set on 130 acres of countryside and natural beauty. After a little browse of the lovely gift shop, selling an array of local produce from Dorset and Hampshire (and gorgeous teddy bears in little Chewton Glen spa robes!) we were shown into the conservatory overlooking their idyllic gardens. My Mum ordered Chewton's Glen own blend of tea whilst I picked Jasmin as I do so adore it.
The afternoon tea selection arrived on a cake tray that included sandwiches such as smoked salmon and brie and pear, home made scones with cream and jam and a varied and artistic array of cake for the perfect finale. To my sheer delight whilst I had to pick a dairy free tea it was just as wonderful as my Mum's selection and there's nothing I really missed out on at all apart from a few alterations to the cake plate that included a scrumptious berry cupcake and almond cake amongst other delicate treats. After managing to eat everything we left feeling very full and content after our glorious afternoon teas that we both enjoyed immensely. In fact, my Mum said it had been one of the best Mother's Day treats ever!
I couldn't recommend afternoon tea at Chewton Glen highly enough and for £29.50 per person it's very reasonable indeed, and you are also able to take home a free sample of tea so that was a wonderful surprise. As the days get lighter you'll no doubt want to stay longer and explore the beautiful surroundings and maybe even wander down to the beach which is just a 1-mile walk from the hotel. The spa is also the ultimate pamper day treat and it's just so wonderful to see how much this hotel has expanded over time with so many huge celebrities favouring this wonderful spot on the South Coast. It certainly makes me feel very fortunate and lucky to have this so near me and I'll definitely do more posts if you would like me to.
A huge thank you once more to Ocean Loans for this lovely treat for my Mum and I that we so thoroughly enjoyed.
Have any of you been to Chewton Glen?


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Return to Sender
I wonder how many of these were gifts that were returned because they simply weren't iPods, and Johnny only wants an iPod because that's what all his friends have. As Michael Gartenberg said to me:
"Kleenex is a generic brand for all tissues. You go to Walgreens and any box of tissues is 'Kleenex.' 'Tivo' is a generic term for DVR, any DVR is a 'Tivo,'" Gartenberg said. "'iPod' is not generic for an MP3 player. Woe unto the consumer who bought something else as a gift thinking they were buying an iPod. It has not become a generic product; it's a very specific product, from a very specific company, with white headphones, and heaven forbid the consumer erred and got that wrong."


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Starting at $424.00
Modern dining chair available in a variety of upholstery options. Available in Black, White, Cream, Brown, Grey, Light Grey or Red leatherette. Available in Brown, Bone,Black, White, Cream or Grey Italian PPM. Available in Dark Grey or Red Oslo wool. Available in Black leather. Available in Amber, Dark Grey, Silver, Rustic Orange or Deep Maroon Camira wool. Base: Chrome plated or Black powder paint steel tubes. Also available in solid Stainless Steel option. Suitable for commercial use.
19"w x 20"d x 34"h
Seat height: 17.5"
Leatherette: 424.00
Oslo Wool/Italian PPM: 468.00
Camira Wool: 557.00
Leather: 647.00
Add 84.00 for solid Stainless Steel base option for each chair.
Type: Dining Chairs


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Stevie bracelet
Stevie bracelet
from 157.00
Five different glittering, crystal-set chains unite to form this gorgeous bracelet. A sliding bar clasp disappears into itself to create an illusion of neverending circlets of sparkle.
- Bracelet is almost 6.75" long including clasp and about 1" across at widest point.
- Genuine Swarovski crystals.
- Packaged in my signature heirloom box.
- Completely handmade in my Denver, Colorado studio.
- Want to try this on in person or customize your color or design? CLICK HERE to find a boutique near you!
- Ships in 5-10 business days. Please CONTACT my team to inquire about expedited processing.
Add To Cart


text: As Millions of Pakistani works in Saudi Arabia in different companies and fields and they sent Billions of dollars each year in Pakistan. Now after the Arab war the conditions of these workers are alarming in Saudi Arabia and other Arab countries. Isis and other civil wars in Yemen, Libya, Syria, Egypt and other countries now companies in Saudi Arabia are on high risk. They are transferring assets from KSA to other countries. New visa policies and prices has been risen in Saudi Arabia and thousands of workers have been sent back to Pakistan or they have transferred to other companies by paying high prices for new permits. Work permits for free labors are restricted already in Saudi Arabia.


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Comments or questions are welcome.Please note: If you have a product question, need further warranty information, requesting a manual or need a product order update or service questions please direct your questions directly to the product manufacturer or vendor. This information would be on your product bill or shipping form. Each merchant has a contact or customer service page on their site. By contacting the manufacturer directly, you will receive the most accurate and quickest response possible. Thank you!
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Libyan security forces freed Thursday a Brazilian reporter detained since March 2 but held on to an award-winning Iraqi journalist working for a British newspaper, their employers said.
Andrei Netto, 34, was at the ambassador's residence waiting to leave Libya for France after being held for eight days in Sabratha, a town 70 kilometers (45 miles) west of Tripoli, the Brazilian daily Estado de Sao Paulo said.
The newspaper said Netto -- a Paris-based correspondent who entered Libya via Tunisia on February 19 and whose detention was made public earlier Thursday -- was "in good health."
Brazil's GloboNews television network said Netto was hit by a gun butt and hooded by four men when he tried to obtain authorization from Libyan officials to stay in the country.
He was held in a cell in a military base and his repeated requests to contact the Brazilian ambassador were refused.
Brazilian President Dilma Rousseff had ordered her government take "urgent measures" to have Netto released after the newspaper confirmed his captivity.
The Estado de Sao Paulo had no information, however, about the fate of the reporter for Britain's daily The Guardian, Ghaith Abdul-Ahad.
He was held in the same cell as Netto for several days, "but the Brazilian reporter does not know where he is right now," the newspaper said.
Both reporters were detained after covering fighting in and near Zawiyah, a town close to Tripoli which Libyan security forces tried to cut off from foreign media. The forces loyal to Libyan leader Moamer Kadhafi retook the town Wednesday.
The Guardian said Thursday on its website that Libya's foreign ministry had finally confirmed to it that Abdul-Ahad was in custody.
The newspaper had been urgently seeking information about his whereabouts for days after it lost indirect contact with him last Sunday.
Abdul-Ahad has worked for The Guardian since 2004, reporting from Somalia, Sudan, Iraq and Afghanistan, the daily said.
He has won the British Press Awards foreign reporter of the year prize, and was shortlisted again this year.
A well-informed source in Tripoli told AFP that Abdul-Ahad had been arrested because he "entered the country illegally."
The source did not provide details on when the newsman was detained, where he was being held or what his condition was.
On Wednesday, the BBC reported that three of its journalists -- a Briton, a Palestinian and a Turk -- had been detained at a checkpoint close to Zawiyah.
They said they were subjected to mock executions by laughing Libyan security officers, and the Palestinian and Turk were repeatedly beaten. All three were released from military barracks in Tripoli after 21 hours and have left the country.
The UN High Commissioner for Human Rights, Navi Pillay, said the treatment given to the BBC team by Kadhafi's men "could amount to torture" under international law.


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In this training course, you learn how to effectively work with stakeholders in multidimensional capacities, develop stakeholder lists, conduct stakeholder analysis, define goals and objectives based on the information stakeholders provide, and ensure the information provided by stakeholders is evaluated against the defined business need and solution scope.
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for each piece, thing, or person; for each one; each:
We ate an orange apiece. The cakes cost a dollar apiece.
Contemporary Examples
In 2008, 324 bundlers raised at least $100,000 apiece for Obama, according to the Center for Responsive Politics.
The Race for 2012's Billions Peter H. Stone March 16, 2011
She has been married twice, for four years apiece, to a diplomat in Ghana and a very handsome American.
Rushka Bergman, Stylist to Michael Jackson, on Remaking Bebe Rebecca Dana September 11, 2012
Only 150 ramen burgers were made available to the public at a price of $8 apiece.
Ramen Burger's Inventor Talks About the Food Craze Eclipsing the Cronut Marlow Stern August 8, 2013
Fetish.xxx and Shemales.xxx went for $300,000 and $200,000 apiece.
How ".XXX," Porn's Domain Name, Made Hundreds of Millions Alex Klein November 12, 2012
Imagine that you've got 10 business class passengers paying $100 apiece, and 100 tourist class passengers paying $5 apiece.
No Matter What the Supreme Court Decides, Textbooks Will Continue to Be Expensive Megan McArdle October 29, 2012
Historical Examples
The chairman allowed them five minutes apiece, and they thought time dear at a dollar a minute.
The Strength of Gideon and Other Stories Paul Laurence Dunbar
There's no sense to it, any way,—sixteen sheep stood him in two dollars apiece.
Tip Lewis and His Lamp Pansy
I've spent already over forty thousand dollars without returns, and my lamps are costing almost two dollars apiece.
Famous Days in the Century of Invention Gertrude L. Stone
I'll tell you what, I'll give you fifty cents apiece for the lot!
Meadow Grass Alice Brown
Beautiful cigar girls sold fragrant Havanas, and bit off the ends at five cents apiece, extra.
Village Life in America 1852-1872 Caroline Cowles Richards
(postpositive) for, to, or from each one: they were given two apples apiece
1550s, a contraction of a pece (mid-15c.), originally of coins, objects for sale, etc. (see a (2) + piece (n.)).
Tagged: a
Read Also:
- Apiezon
adjective trademark designating any of a number of hydrocarbon oils, greases, or waxes, characterized by a low vapour pressure and used in vacuum equipment
- Arracacha
a perennial herb, Arracacia xanthorrhiza, of the parsley family, found in the Andes, having large, fleshy, edible roots. the root of this plant, eaten like potatoes. Historical Examples arracacha, ar-a-kach′, n. an umbelliferous plant with esculent roots, native to the northern parts of South America. Chambers's Twentieth Century Dictionary (part 1 of 4: A-D) Various […]
- Aping
any of a group of anthropoid primates characterized by long arms, a broad chest, and the absence of a tail, comprising the family Pongidae (great ape) which includes the chimpanzee, gorilla, and orangutan, and the family Hylobatidae (lesser ape) which includes the gibbon and siamang. (loosely) any primate except humans. an imitator; mimic. Informal. a […]
- Apiology
the scientific study of bees, especially honeybees.


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Hotels in Lucknow, India
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Lucknow overviewYou can learn about the local heritage of Lucknow at landmarks like Residency and Shah Najaf Imambara. There's plenty more to see, including local sights like K.D. Singh Babu Stadium and Bara Imambara. Whatever your interests are, Lucknow has something for you.
Where to stay in LucknowWhether you're planning to stay for a night or for the week, the area around Lucknow has accommodations to fit every need. Search for hotels in Lucknow with Hotels.com by checking our online map. Our maps display the areas and neighborhoods around all Lucknow hotels so you can see how close you are from landmarks and attractions, and then refine your search within the larger area. The best Lucknow hotel deals are here with our lowest price guarantee.
How to get to LucknowFly in to Lucknow (LKO-Amausi Intl.), 7.8 mi (12.6 km) from downtown Lucknow. Kanpur (KNU-Chakeri) is the next closest major airport, 45.5 mi (73.2 km) away.
What to see around LucknowMemorable for its landmarks including:
- • Residency
- • Shah Najaf Imambara
- • Bara Imambara
- • Rumi Darwaza
- • Hussainabad Clocktower
- • Botanical Gardens
- • Ambedkar Memorial Park
- • K.D. Singh Babu Stadium
- • Hussainabad Imambara
- • Lucknow Zoo
- • State Museums
When to visit LucknowIf you're starting to plan your trip, you might be wondering when's the best time to visit. Here are the seasonal norms to help you decide when to go:
Seasonal temperature averages
- • January-March: 95°F day, 44°F night
- • April-June: 105°F day, 64°F night
- • July-September: 97°F day, 71°F night
- • October-December: 91°F day, 45°F night
- • January-March: 1.54 inches
- • April-June: 4.84 inches
- • July-September: 31.06 inches
- • October-December: 1.85 inches