text:
|Publication number
|Publication type
|Application number
|Publication date
|Aug 25, 1987
|Filing date
|Aug 14, 1985
|Priority date
|Aug 14, 1985
|Fee status
|Publication number
|Rangarajan Srinivasagopalan, Louis V. Farias
|Original Assignee
|Racal Data Communications Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (16), Non-Patent Citations (4), Referenced by (32), Classifications (6), Legal Events (11)
|External Links: USPTO, USPTO Assignment, Espacenet
θ.sub.e (NT)=αjsin (ω.sub.j NT+Ψ.sub.j)+Δω.sub.c NT+n(NT),
1. Field of the Invention
This invention relates generally to the field of phase jitter cancellation in high speed data modems and more particularly to an arrangement for reduction of phase jitter having a sinusoidal component.
2. Background of the Invention
As the speed of operation of data modems continues to increase, the problem of dealing with phase jitter in the transmitted data signal becomes increasingly bothersome. The effect of phase jitter is a rotation of the transmitted symbol without changing the magnitude of the symbol. This can cause the received symbol to differ from the transmitted symbol causing transmission errors. The receiver's immunity to jitter decreases as the number of symbols in the constellation increases. Although the symbol constellations used in such high speed modems have evolved to relatively optimal designs, phase jitter can still create errors which a high speed data modem must correct. It is therefore important to provide a mechanism for canceling as much of the phase jitter in a transmitted signal as possible.
Some types of phase jitter are non-sinusoidal and may be traceable to various randomly occurring electrical signals which may be familiar to those skilled in the art. Another type of phase jitter results when the transmitted data is corrupted by a sinusoidally varying source. This results in sinusoidal phase jitter which is the type of jitter the present invention addresses. The most frequent cause for sinusoidally varying phase jitter is related to ripple in the power supplies used by the telephone company in it's carrier communications equipment. Other sources of phase jitter also produce a slowly varying or approximately sinusoidal component of phase jitter which can be effectively canceled by utilizing the present invention. In the U.S. these sinusoidal components are generally integral multiples of 60 hertz. This is also true in Canada. In some parts of Europe, such as Great Britain, the fundamental frequency of the power line is 50 hertz and in such instances the sinusoidal component of phase jitter is frequently an integral multiple of 50 hertz. According to published data sinusoidal components may exists in transmitted data signals at frequencies between approximately 20 hertz and approximately 300 hertz.
In attempting to correct for such sinusoidally varying phase jitter, numerous problems are encountered. For example, it is possible to lock onto such sinusoidally varying components of phase jitter and produce a signal which cancels the phase jitter. But, in so doing the signal which is being locked to effectively disappears or becomes so reduced in amplitude as to become very difficult to maintain lock on. Additionally, in order to effectively compensate for such phase jitter a relatively wide range of frequencies must be locked upon. This becomes a problem in and of itself but is complicated by the fact that it is desirable to use a very narrow noise bandwidth phase locked loop so that a high degree of noise immunity is maintained. Therefore, use of a simple wideband phase-locked loop or Costas loop may accomplish significant phase jitter reduction, but at the expense of signal to noise ratio. It is also desirable in such a phase jitter canceling system to provide a mechanism for detecting when the phase jitter is small enough that the compensation is not needed. In this instance, the phase jitter correction circuitry can be disabled further enhancing the modem's noise performance.
These and other problems have been effectively addressed in the present invention and such features have been provided in order to enhance the operation of the phase jitter canceling circuitry so that data errors due to sinusoidally varying phase jitter are rare.
It is an object of the present invention to provide an improved method and apparatus for effectively canceling sinusoidal phase jitter.
It is another object of the present invention to provide phase jitter cancellation which effectively cancels sinusoidal phase jitter occurring over a wide band of frequencies without seriously degrading the noise threshold of the phase lock loop.
It is another object of the present invention to provide a phase jitter cancellation network which does not significantly degrade the noise performance of the modem's receiver.
It is another object of the present invention to provide a narrow-band phase jitter cancellation network with improved noise performance.
It is another object of the present invention to provide a phase jitter cancellation network utilizing adaptive loop parameters for enhanced acquisition and tracking of sinusoidal phase jitter with improved noise performance.
It is a further object of the present invention to provide a method and apparatus for canceling sinusoidal phase jitter in a manner which is largely independent of the amplitude of such phase jitter.
It is a further object of the present invention to provide a method for synthesizing the sinusoidal phase jitter component (used in the canceller) in a manner which is independent of the amplitude of such phase jitter.
It is a further object of the present invention to provide a method for estimating the amplitude of the jitter which is essentially independent of the method of estimating the phase and frequency of the jitter during startup and when the loop is locked.
These and other objects of the invention will become apparent to those skilled in the art upon consideration of the following description of the invention.
In one embodiment of the present invention a high speed data modem includes a circuit for compensating for sinusoidal phase jitter. The modem includes a receiver for receiver a data signal including a sinusoidal jitter Φj (t). A demodulator demodulates the data signal and an error calculator calculates an error signal having the form:
Φ.sub.j =α.sub.j sin(ω.sub.j NT+Ψ.sub.j).
A first compting circuit computes an estimate of ωj and an estimate of Ψj designated ωj and Ψj respectively, and produces a first output signal sin(ωj NT+Ψj). A second computing circuit computes an estimate of αj designated αj. A multiplier multiplies αj by the first output signal to produce an estimated jitter signal Φj =αj sin(ωj NT+Ψj). An adding circuit produces a correction signal and the correction signal is applied to the demodulator to provide cancellations of the jitter component.
The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself however, both as to organization and method of operation, together with further objects and advantages thereof, may be best understood by reference to the following description taken in conjunction with the accompanying drawing.
FIG. 1 is an overall block diagram of the modem phase jitter cancellation network according the present invention.
FIG. 2 is a more detailed diagram of the circuitry for tracking frequency translation by computing ωc.
FIG. 3 shows a more detailed diagram of the circuitry used for tracking phase jitter components by computing ωj and Ψj.
FIG. 4 shows a more detailed diagram of the circuitry used to compute the estimate αj of the magnitude αj of the phase jitter.
FIG. 5 shows a detailed diagram of the error calculator.
FIG. 6 shows a diagram illustrating the process of dynamically altering the loop constraints of the present invention.
Before describing the inventive portion of the circuitry, the conventional operation of the modem receiver 10 of FIG. 1 will be briefly described. A receiver line signal ##EQU1## containing the phase jitter component Φj (t) is received from the remote modem transmitter (not shown) preferably at a rate of 14.4 KBPS. In this relation, nG (t) represents Gaussian noise. The line signal is received by an automatic gain control circuitry (AGC) and A/D convertor 12, such as shown in U.S. Pat. No. 4,231,097 which is incorporated by reference as though disclosed fully herein. The regulated digitized received signal is then passed to the Hilbert transform and bandpass filters 14 which produces an output comprising a filtered complex signal having in phase and quadrature phase signal components. The filtered complex signal is received by a passband equalizer 16, which corrects for intersymbol interference.
The equalized complex signal is fed to a demodulator 18 which multiplies the equalized passband signal by the term ε-jθ.sbsp.c with θc reflecting the recovered carrier angle and compensates to some degree for frequency offset and phase jitter. The sine and the cosine signals necessary for demodulating the complex passband signals can be derived from a sine/cosine look-up table 20. The equalized and demodulated signal represents a 2-dimensional, complex valued symbol, with the in-phase signal component being designated as X' and the quadrature signal component being designated as Y'. These two demodulated signals, X' and Y' are supplied to a decision or detection (slicer) circuit 22. The received complex signal X'+jY' defines the received symbol which the detector uses to determine the most probable transmitted symbol defined as X+jY. It is this symbol which comprises the received data. At an error calculating means 24, the inputs and outputs to the detector 22 are subtracted to create the error signals eX =(X-X') and eY =(Y-Y').
Error signals ex and ey are normally employed to continuously adapt equalizer 16 by circuitry so as to remove some of the effects of linear distortion due to the transmission medium between the transmitter and receiver. The decision signals X, Y are then passed to the user through other apparatus, e.g. descramblers, parallel to serial convertors, demultipliers, etc., which are not necessary to the discussion of the invention.
Not shown in the diagram are such normal facets of such a digital receiver, normally forming part of a modem for the recovery of data timing scrambling etc., which again do not form part of this invention. Also, the present description assumes that digital data and timing clock pulses are available so that digital data can be clocked through our apparatus as it is through the normal apparatus of the receiver.
Error calculator 24 produces an error signal θe at node 25 which generally has the form of Equation 1 where n(NT) is a noise component of phase jitter which is not sinusoidal. This error signal θe (or a signal proportional to θe) is applied to a computing block 26 which computes the value of an estimate of the radial carrier frequency ωc designated ωc and produces an output at its output terminal 28 of the form ωc NT. The error signal θe is also supplied to a quantizer within error calculaor 24 (see FIG. 5) which is basically a limiter with a dead zone surrounding the origin. This quantizer serves to produce a constant output signal level at node 35 regardless of the level of the input error signal. Of course if the signal level falls within the bounds of the dead zone, as when only noise is present of when jitter is very small, no quantization will occur and it will appear that the error is completely corrected (i.e. no error correction required). Otherwise, a constant input signal level is provided to computing blocks 32 and 34 at node 35. Computing block 32 produces an output at its output terminal 36 which is an estimate of αj (the magnitude component of the sinusoidal phase jitter) which is designated αj. (For purposes of this document characters with a hat, such as αj are used to represent estimates.)
θ.sub.e (NT)=Φ.sub.j (NT)+Δω.sub.c NT+n(NT) Equation 1
T=1 baud interval;
Δωc is the change in carrier frequency;
N is the Nth time instant;
Φj (NT)=αj sin(ωj NT+Ψj);
Similarly, computing block 34 produces an address signal at node 37 which addresses sine/cosine lock-up table 48 to obtain a signal at its output 38 which includes estimates of ωj and Ψj which are designated ωj and Ψj respectively. The signal output appearing at node 36 is an estimate of the magnitude of the phase jitter αj (NT). The signal at the output node 38 takes the form of sin(ωj NT+Ψj). These signals at nodes 36 and 38 are multiplied together by a multiplier 40 to produce a signal which is an estimate of the error signal Φj and is designated Φj. The error signal estimate therefore takes the form of equation 2 which appears at the output 42 of multiplier 40.
Φ.sub.j (NT)=α.sub.j (NT) sin (ω.sub.j NT+Ψ.sub.j). Equation 2
The outputs of computing block 28 and multiplier 40 are added together in an adding network 44. The output of adding network 44 appears at node 46 as the demodulating carrier angle and has the form of equation 3. The demodulating carrier angle θc (t) at t=NT has two components. The first component ωc NT is an estimate of the phase of carrier frequency and the second term is the estimate of the phase jitter which will be used to cancel the sinusoidal phase jitter. ##EQU2##
This estimate θ(NT) is applied to sine/cosine look-up table 20 which provides outputs which are the sine and cosine of θ(NT) and are used in demodulating the received waveform. In fact, the sine, cosine look-up table 20 may be thought of us a portion of demodulator 18. A second sine cosine look-up table 48 is shown coupled to computing blocks 32 and 34 for convenience of illustration. It will be recognized by those skilled in the art, however, that sine/cosine look-up table 48 may actually be the same table as sine/cosine look-up table 20. One skilled in the art will also recognize that the preferred implementation of the present invention utilizes microcomputer technology so that all of the functional blocks of the present compensation network may be largely implemented by use of digital computer specially programmed for such functions. However, the present invention should not be limited to such embodiments as it is also possible to provide direct hardware implementation of the present invention utilizing integrated circuit technology and the like. Preferably the present invention is implemented largely by utilizing a high speed 16 bit microcomputer with associated ROM firmware and RAM storage. The look-up tables are implemented in ROM and the entire signal processing arrangement is firmware controlled with the phase-locked loops being digital PLL's implemented in firmware.
The overall system includes three loops; one loop for estimating carrier frequency, a second loop for estimating the jitter amplitude and a third loop for estimating frequency and phase of the phase jitter. The main loop serves as a carrier frequency ωc tracking loop and traces a path 18-22-24-26-40-44-20. A second loop serves to lock onto and track the jitter amplitude ωj and traces a path 18-22-24-32-40-44-20. A third loop (the jitter loop) traces the path 18-22-24-34-48-40-42-44-20 and serves to lock onto and track and jitter frequency ωj and jitter phase Ψj. Of course all three loops operate in a manner wherein each loop is somewhat dependent on the other two loops for complete system operation. However, the main loop functions essentially independent of the other two loops with its effects added in at adder 44. Each of the loops are computationally independent except in that output of 48 serves as an input to 32 and all of the jitter computations interact at multiplier 40 to form a composite signal to be used in correcting for the phase jitter.
In the preferred embodiment, the main loop is a very narrow noise bandwidth loop (during steady state) which is locked onto the carrier frequency. It is capable of tracking and providing a small degree of correction for jitter below about 20 hertz. The capture range of the jitter loop starts out at approximately 300 hertz during receipt of a training sequence. During the course of the training sequence, the capture range of the loop is gradually reduced to about 20 hertz so that during steady state conditions, the noise bandwidth is very narrow. This enhances the noise performance of the modem, while allowing for acquisition of sinusoidal jitter from about 10 hertz to about 300 hertz. It has been determined that sinusoidal phase jitter does not normally change very rapidly in a given situation although it may vary from channel to channel, or site to site, etc. For this reason, it is possible to narrow the loop as described and still maintain good tracking of the jitter. In the event a rapid change in jitter does occur, an increase in errors may result which will cause another training sequence to be sent per the normal operation of such high speed modems. In this event, the jitter loop is widened in capture range in order to once again acquire lock with the new jitter signal as described previously. The details of this acquisition enhancement process will be described later.
Turning now to FIG. 2, a more detailed diagram of computing block 26 is shown. The error signal θe (NT) from node 25 of error calculator 24 is applied to multipliers 50 and 52 which multiply this signal by constants K1 and K2 respectively. More detail will be provided later about the constants used in this computing block as well as computing blocks 32 and 34. The product of θe (NT) and K1 at the output of block 50 is provided to an integrator 54 shown in broken lines. Integrator 54 includes a summing device 56 which adds the incoming signals from multiplier 50 to the time delayed output of delay 58 which provides a one baud delay to signals provided at its input. The output of integrator 54 is taken at the junction of summing device 56 and delay 58 at node 60 which also forms the input of a multiplier 62. Multiplier 62 multiplies the signal at node 60 by a constant K3 to produce an output at node 64. The output of multiplier 52 is provided to a node 66 which forms an input to a summing device 68. Node 64 also forms an input to summing devices 68 as does input 69 which supplies a constant K4 to summing device 68. Summing device 68 also operates as an integrator in conjunction with delay 70 which is also one baud in duration. The output of summing device 68 is provided to delay 70 which in turn feeds back its output to another input 72 of summing device 68. The junction of summing device 68 and delay 70 forms the output 28 of computing block 26. Computing block 26 serves to create the carrier frequency estimate ωc.
The operation of computing block 26 may be best understood by considering the following explanation. The error signal θe (NT) has two components; one is the error due to the difference between the transmitter carrier phase and the receiver's estimated carrier phase. The second component is the residual phase jitter. FIG. 2 represents a digital phase locked loop (DPLL) which computes an estimate θc (NT) of the carrier phase angle. The product of θe (NT) and K1 at the output of multiplier 50 is provided to an integrator 54.
The integrator 54 represented by the summer 68 and the delay unit 70 forms a portion of the voltage controlled oscillator (VCO) of the DPLL. The output of the VCO is converted to sin(θc) and cos(θc) using look-up tables. The constant K4 is proportional to the carrier frequency of the modem. In the 14.4 KBPS high-speed modem of the preferred embodiment the carrier frequency is 1700 hertz. The variables in FIG. 2 can be represented by two coupled first order difference equations shown in Equations 4 and 5.
FRC(NT)=FRC((N-1)T)+K.sub.1 K.sub.d1 θ.sub.e ((N-1)T) Equation 4
θ.sub.c (NT)=θ.sub.c [(N-1)T]+[K.sub.3 FRC(NT)]+K.sub.d1 K.sub.2 θ.sub.e [(N-1)T]K.sub.VCO1 Equation 5
Where Kd1 is the phase detector gain θe is the total phase error, θc is the estimate of carrier phase and KVCO1 is the gain of the VCO. Although θe has carrier phase error and phase jitter the loop represented by FIG. 2 only corrects for carrier phase error and does not correct the phase jitter.
Turning now to FIG. 3 computing block 34 is described in more detail. Computing block 34 serves primarily to compute and track the frequency and phase of the phase jitter component. Node 35 which is the output of the previously mentioned quantizer also forms the input to block 34 and is coupled to a multipler 76 whose output 78 is coupled to a second multiplier 80 and also to a third multiplier 81. Multipliers 80 and 81 multiply the signal at node 78 by constants K5 and K6 respectively. The output of node 80 is coupled to an input of an integrator 82 which is formed by a summing device 84 together with a delay 86 coupled together in a similar manner to integrator 54. The output of integrator 82 is taken at node 88 which also forms the input of a multiplier 90. Multiplier 90 multiplies the signal at node 88 by a constant K7 to form its output at node 92. The output at node 92 is provided to a summing device 94.
Summing device 94 also works in conjunction with delay 96 to produce an integrating operation. In doing so, summing device 94 output at node 98 is provided as an input to delay 96. A scaling constant K8 may be added in at summing device 94 in order to provide adjustment of the natural frequency of the system. In the preferred embodiment, this scaling constant is set to 0. The output of delay 96 is in turn fed back to summing device 94. The output signal at node 98 enters sine/cosine look-up table 48 to produce the sine of the input at output node 36 and the cosine output which are supplied to a limiter 100. The output of limiter 100 is delayed by delay 102 before being provided as the second input to multiplier 76.
The circuit embodiment of FIG. 3 is described by the operation of a second order DPLL. The first integrator 82 corresponds to the integrator of the loop filter. The second integrator 95 corresponds to the VCO. The multiplier 76 is the phase detector (PD). The one baud delay introduced by delay element 102 is to match the one baud delay in the loop from 46 to 24 in FIG. 1. The two coupled first order equations which describe the operation of FIG. 3 are:
FRG(N)=FRJ(N-1)+K.sub.5 K.sub.d2 sign[θ.sub.e ]sign(cos[Φ.sub.j (N-1)]) Equation 6
Φ.sub.j (N)=Φ.sub.j (N-1)+K.sub.VCO2K K.sub.d2 sign[θ.sub.e ]sign[cos[Φ.sub.j (N-1)]]+K.sub.VCO2 K.sub.7 FRJ(N) Equation 7
FRJ=jitter frequency, and
KVCO2 =the gain of this VCO
Turning now to FIG. 4, the phase jitter magnitude tracking computing block 32 is described in more detail. The sine output of sine/cosine look-up table 48 at node 38 is provided as a first input at node 38, and the quantized error signal at node 35 is provided as a second input to a multiplier 110 to produce an output at its output node 112. This output at node 112 is multiplied by a constant K9 at multiplier 114. The output 116 of multiplier 114 is connected to the other input of an integrator 118 made up of adder 120 and delay unit 122. The output 126 of integrator 118 is connected to a switch 124 and to node 36 under steady state conditions.
Normally under steady state conditions, switch 124 is controlled by a decision block 134 coupled to a baud counter 138 that connects the output 36 to node 31 after a fixed number of bauds from the beginning of the training sequence. The switching of 124 to position 218 (0 volts) is controlled by decision block 134 which checks the frequency of the jitter being tracked and the magnitude of the jitter being tracked. If any one of the parameters falls below a predetermined threshold the jitter correction circuit will be disabled and the switch 124 will be connected to position 128 as follows:
Baud counter 138 is, of course, responsive to the system clock. Decision block 134 is also coupled to computing block 26 at node 88 to receive jitter frequency information. If the jitter frequency is less than an appropriate threshold (about 10 HZ in the preferred embodiment) the switch 124 is set to 0 volts by decision block 134. Similarly, if decision block 134 determines from node 130 that the jitter magnitude is less than an appropriate threshold (about 2 to 21/2 degrees in the preferred embodiment) switch 124 is set to 0 volts by decision 134. In this manner, the correction circuit can be disabled in the presence of low jitter. This decision making operation is made under the control of baud counter 138 as follows.
If the value of the frequency estimate and amplitude estimate are below the threshold values at about 25 seconds after steady state (as determined by baud counter 138) then the integrator output 126 in FIG. 4 is grounded by switch 124 thereby setting the output of the estimator to zero. If on the other hand the frequency estimate is above the threshold but the amplitude estimate is within the the dead zone of the limiter then the limiter output will be zero thus disabling the loop. If there is indication of jitter present at the sampling instant (i.e. at 25 seconds) but later if the jitter falls into the dead zone of the limiter then the zero output of the limiter will effectively disable the loop.
Turning now to FIG. 5, a more detailed block diagram of error calculator 24 is shown. As previously discussed, error calculator 24 accepts inputs X, Y, X' and Y' from both sides of detector 22. A phase error estimate is computed in block 150 preferably using the equation shown in the block to produce a signal at node 25 which is equivalent θe (NT). This signal at node 25 is further processed by a quantizer 152 which operates as previously described in that it is a quantizer having a dead zone which serves to ignore signals below a predetermined threshold while limiting signals above the noise threshold and producing an output at node 35. The signal at node 35 is therefore quantized (limited) and virtually independent of amplitude of the error signal at node 25. The signal at node 25 is also processed independently by a multiplier 154 which provides a gain factor of K10 to the signal at node 25. Signals X, Y, X' and Y' are also processed by an amplitude error estimator 156 which operates according to the calculations shown in box 156 to produce an estimate of the amplitude error which is scaled by a multiplier 158 operating in conjunction with constant K11. The outputs of multiplier 154 and 158 are processed by an absolute value circuit 160 to produce a signal of the form of equation 8.
output of 160=|[θ.sub.e (NT)]-[(K.sub.11)(amplitude error)]|. Equation 8
This signal is multiplied by K12 at multiplier 162 and then fed to an accumulator 164 to produce the signal at node 31.
Computing block 32 is used to compute the estimate of αj. In theory, block 32 computes an integral approximating the integral of the product of the error signal and the estimated error signal as shown in equation 9.
α.sub.j =∫[α.sub.j sin(ω.sub.j t+Ψ.sub.j)+n(t)][sin(ω.sub.j Nt+Ψ.sub.j)]dt. Equation 9
Exact computation of equation 9, however, produces a signal which ultimately diminshes to a point wherein an update cannot be made at every baud because of pulsation of the jitter. This problem is alleviated by utilizing the quantized signal at node 35. By quantizing the signal computing blocks 32 and 34 are provided with a constant signal level regardless of the level of the error signal θj and depends only on the sign of αj.
Computing block 32 computes the estimate of αj by taking the discrete time integral of the product of the sign of the error signal and the sign of the estimated error signal as shown in equation 10.
α.sub.j (NT)=α.sub.j (NT-T)+sign[Φ.sub.j (NT)]sin(ω.sub.j NT+Ψ.sub.j) Equation 10
During steady state computing, block 32 uses the quantized signal at node 31 (i.e. only uses the sign of αj). Computing block 34 also uses the quantized signal at 31 thus making the estimation of phase and frequency independent of the level of the error signal θe.
It should also be noted that computing block 32 is extremely easy to implement resulting in substantial hardware savings due to the small numbers of calculations. Equations 4 and 5 describe the time domain behavior of the coupled first order difference equations. These equations can to a first order be approximated by linear equations 11 and 12.
FRJ(N)=FRJ(N-1)+K.sub.5 K.sub.ph (Φ.sub.j (N-1)-Φ.sub.j (N-1)) Equation 11
Φ.sub.j (N)=Φ.sub.j (N-1)+K.sub.VCO K.sub.6 K.sub.ph (Φ.sub.j (N-1)-Φ.sub.j (N-1))+K.sub.VC02 K.sub.7 FRJ(N) Equation 12
In arriving at these equations we assume that the carrier phase error is zero. Here Kph is the gain of the equivalent linear phase detector. The phase detector gain Kph can be calculated by the formula of equation 13.
K.sub.ph =(Fundamental Frequency Output)/(Input Phase Angle to Phase Detector) Equation 13
From the constants K5, Kph, KVCO, K6 and K7 it is possible to calculate the constants ζ (loop damping factor) and the natural frequency ωn of the corresponding continuous time loop using well known techniques such as those described in Lindsay and Chie A. Survey of Digital Phase-locked Loops PROC of IEEE Vo. 69 no. 4, April 1981, pp. 4410-431. If T is the sampling period then ##EQU3## where α and β are poles on the unit circle in the sampled data system and ε is the base of natural logarithms.
α=1/2(2-K.sub.Vco K.sub.6 K.sub.ph -K.sub.VCO K.sub.7 K.sub.5 K.sub.ph)
α.sup.2 +β.sup.2 =1-K.sub.Vco K.sub.6 K.sub.PH
where we have assumed ζ<1 (See Lindsay and Chie). A similar set of relations can be obtained for ζ>1. (It must be pointed out that for linerarization to hold it is assumed that the loop is locked and that the error is small). It can be shown from these relations that the larger the value of the phase detector gain ph' the wider the capture range is for the PLL.
However, in Equations 11 and 12, the relation Kph (Φj (N-1)-Φj (N-1)) takes on the discrete values (e.g., +1, -1, 0), then depending on the values of KVco, K6 Kph there is a lower bound on the phase angle advanced per baud. This phase angle advanced per baud decreases as the input frequency decreases. Hence, keeping a large value of Kph limits the lower frequency which can be captured by the DPLL. Thus we have a tradeoff. On approach is to use a Costas loop with automatic frequency argumentation as proposed in C. R. Cahn "Improving Frequency Acquisition of a Costas Loop" IEE Transactions on Communications December 1977 pp. 1453-1459. This however will degrade the noise threshold.
It is a feature of the present invention to start with a wide capture range to capture the frequency and phase of the signal and then to gradually reduce the noise bandwidth of the PLL. Accordingly the training period is divided into several time segments (6 in the preferred embodiment) each of which utilizes a particular capture range, natural frequency and damping factor.
This feature is best understood by noting FIG. 6 in conjunction with Table 1. During the initial time segment from the start up of the training sequence to time T3 no action is taken allowing timing, carrier and equalizer to converge.
During the next six segments the phase lock loop (PLL) captures the jitter and the amplitude estimating loop is trained. During the six segments the value of ωn (natural frequency of the loop) is decreased and ζ (loop damping factor) is increased thereby decreasing the noise bandwidth (capture range) of the loop and at the same time making the loop slower to react to fast changes. This prevents the loop from losing lock in the process of switching the constants. A typical set of ζ and ωn are shown in Table 1. Data can be accepted after the seventh argument since by that time both the amplitude loop and the PLL would have been completely trained.
The sets of values of ωn and β have been selected to approximately optimize operation of the system for typical operation in the present sinusoidal phase jitter. It will be clear to those skilled in the art however that further improvement may be possible by further optimizing the values of table one which are not intended to be limiting.
TABLE 1______________________________________T1 T2 T3 T4 T5 T6 T7 T8 T9______________________________________ζ0 0 0.707 0.944 1.26 1.67 2.25 3 1.123ω.sub.n0 0 430 250 100 50 25 2.5 8.885______________________________________
In accordance with the preferred operation of the invention, at time T1 of FIG. 6 the training sequence for the equalizer of the receiving modem is transmitted by the transmitting modem. The inverval T3-T4 is chosen long enough to capture frequencies from 10 HZ to 300 HZ. In the preferred embodiment all the intervals except the last T8-T9 are made the same and are set equal to 384 bauds and the last interval is set equal to one half of the other intervals. This combination has been chosen mainly for ease of implementation. It can be seen from Table 1 that the product ζωn, which is proportional to the capture range, is decreased with increasing time. In the steady state condition the value of ζ is chosen so that the frequency update of the loop is maintained. The training sequence ends at time T8, after which reception of data begins.
At time T9 the final set of constants are implemented to produce the narrowest capture range of the loop. These set of constants are utilized during steady state reception of data from the transmitting modem. By gradually reducing the bandwidth of the tracking loops of the present invention, significant improvement or noise performance as been attained with the present invention.
The values shown in table one have been selected to approximately optimize operation of the system for typical operation in the presence of sinusoidal phase jitter. It will be clear to those skilled in the art, however, that further improvement may be possible by further optimizing the values shown in table one and the values of table are not intended to be limiting. The selection of values of the constants discussed earlier may be selected by those skilled in the art by known techniques using the values of Table 1.
By using the present invention to cancel sinusoidal phase jitter, the frequency and phase estimates of jitter may be made essentially independent of the amplitude of the jitter. Those skilled in the art will recognize the advantages of such computational independence in light of the previous discussion such as the ability to capture a wide range of amplitudes with ease. In addition, since the amplitude of the jitter is estimated in the first stage by taking the absolute values of the difference between the absolute magnitude of the jitter error and the scaled estimate of the noise amplitude, the system is less prone to error resulting from noise (i.e. the system's noise performance is enhanced).
The present system exhibits the further advantage of updating the jitter estimate at every baud during steady state conditions. This is accomplished by one bit quantization and allows continuous jitter update almost without regard for jitter amplitude. This results from discrete integration of the quantity obtained by multiplying the sign of the (jitter) error by sin (ωj NT+Ψj). This also prevents pulsations of jitter at the receiver.
Of course those skilled in the art will know that even the best of jitter cancellers will result in some degree of degradation in noise performance of a modem. The present invention, however, contends with this by allowing the cancellation to be disabled under circumstances wherein the error rate will not benefit from its operation. Of course, the present invention minimizes such degradations by the scheme disclosed herein of dynamically altering the characteristics of the loop.
Thus it is apparent that in accordance with the present invention an apparatus that fully satisfies the objectives, aims and advantages is set forth above. While the invention has been described in conjunction with a specific embodiment, it is evident that many alternatives, modifications and variations will become apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended that the present invention embrace all such alternatives, modifications and variations as fall within the spirit and broad scope of the appended claims.
|Cited Patent
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|Feb 23, 1972
|Mar 26, 1974
|Honeywell Inf Systems
|Phase jitter compensator
|Oct 21, 1975
|May 31, 1977
|Lang Gordon R
|Apparatus and method for reducing effects of amplitude and phase jitter
|Jul 31, 1975
|Oct 4, 1977
|Milgo Electronic Corporation
|Phase-jump detector and corrector method and apparatus for phase-modulated communication systems that also provides a signal quality indication
|Nov 15, 1976
|Aug 8, 1978
|International Business Machines Corporation
|Self-adaptive digital filter for noise and phase jitter reduction
|Nov 8, 1977
|Mar 6, 1979
|Fujitsu Limited
|Digital phase lock loop circuit and method
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|Jul 15, 1980
|Racal-Milgo, Inc.
|Hybrid automatic gain control circuit
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|Motorola, Inc.
|Apparatus and method for attenuating interfering signals
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|Societe Anonyme Dite: Compagnie Industrielle Des Telecommunications Cit-Alcatel
|Method and apparatus for detecting the training sequence for a self-adapting equalizer
|Jun 11, 1981
|Jul 3, 1984
|Hycom Incorporated
|Adaptive phase lock loop
|Nov 3, 1982
|Oct 2, 1984
|General Electric Company
|Receiver for phase-shift modulated carrier signals
|May 19, 1982
|Nov 20, 1984
|Westinghouse Electric Corp.
|Phase-locked loop having improved locking capabilities
|Feb 25, 1983
|Mar 12, 1985
|Johnson Service Company
|Noise-neutralizing digital interface circuit
|Aug 2, 1983
|Apr 30, 1985
|Ese Limited
|Means and method for reduction of phase jitter
|Jun 30, 1983
|Jul 16, 1985
|Ncr Corporation
|Circuit for reducing errors in a data receiver
|Aug 12, 1982
|Jul 30, 1985
|Paradyne Corporation
|Phase tracking loop for digital modem
|Mar 16, 1984
|Aug 12, 1986
|Trw Inc.
|Method and apparatus for detecting an equalizer training period in a receiving-end modem
|"Improving Frequency Acquisition of a Costas Loop", vol. COM-25, No. 12, Dec. 1977.
|Cahn "Improving Frequency Acquisition of a Costas Loop", IEEE Transaction on Communication, vol. COM-25, No. 12, Dec. 1977, pp. 1453-1459.
|Cahn Improving Frequency Acquisition of a Costas Loop , IEEE Transaction on Communication, vol. COM 25, No. 12, Dec. 1977, pp. 1453 1459.
|Improving Frequency Acquisition of a Costas Loop , vol. COM 25, No. 12, Dec. 1977.
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|Oct 12, 1988
|Nov 14, 1989
|International Mobile Machines Corporation
|AM equalizer circuit for digital systems
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|Jan 23, 1990
|Tektronix, Inc.
|Method and apparatus for measuring jitter in a periodic signal
|Feb 19, 1988
|Aug 28, 1990
|Silicon Systems, Inc.
|Phase jitter tracker
|Aug 17, 1989
|May 26, 1992
|The United States Of America As Represented By The United States Department Of Energy
|Digital quadrature phase detection
|Jul 27, 1989
|Jul 7, 1992
|Nec Corporation
|Apparatus for cancelling carrier phase jitters
|Sep 21, 1990
|Jul 21, 1992
|Proteon, Inc.
|Token ring equalizer
|Aug 12, 1991
|Sep 28, 1993
|Motorola, Inc.
|Circuit and method for phase error correction in a digital receiver
|Oct 11, 1991
|May 24, 1994
|Nec Corporation
|Apparatus and method of canceling periodic carrier phase jitter
|May 1, 1992
|May 24, 1994
|Grumman Aerospace Corporation
|Arrangement for correction of synchronous demodulator quadrature phase errors
|Oct 4, 1994
|Jul 18, 1995
|Motorola, Inc.
|Apparatus and method for equalizing for amplitude jitter
|May 22, 1995
|Jul 1, 1997
|Interdigital Technology Corporation
|Direct digital frequency synthesizer for use in a subscriber unit of a wireless digital communication system
|Jan 11, 1996
|Dec 2, 1997
|Interdigital Technology Corporation
|Subscriber unit for wireless digital subscriber communication system
|Sep 26, 1995
|Feb 17, 1998
|Fujitsu Limited
|Phase jitter extraction circuit and phase jitter cancellation circuit
|Feb 15, 1996
|May 12, 1998
|Ericsson Inc.
|Multichannel receiver using analysis by synthesis
|Jun 24, 1997
|Jan 12, 1999
|Interdigital Technology Corporation
|Subscriber unit for wireless digital subscriber communication system
|Feb 10, 1997
|Jul 27, 1999
|Thomson Multimedia Sa
|Device for correcting phase noise in a digital receiver
|Jan 11, 1999
|Jun 20, 2000
|Interdigital Technology Corporation
|Digital synthesizer
|Mar 31, 1998
|Feb 20, 2001
|Lucent Technologies Inc.
|Carrier recovery system
|Jun 13, 2000
|Sep 10, 2002
|Interdigital Technology Corporation
|Digital synthesizer
|Aug 20, 2002
|Jul 1, 2003
|Interdigital Technology Corporation
|Subscriber unit producing a modulated digital frequency
|Sep 29, 1999
|Feb 3, 2004
|Advantest Corporation
|Apparatus for and method of measuring a jitter
|Apr 11, 2003
|Apr 20, 2004
|David Norton Critchlow
|FIR chip for use in a wireless subscriber unit
|Dec 7, 2000
|Feb 21, 2006
|Agere Systems Inc.
|Adaptive interference cancellation for ADSL
|Dec 25, 2006
|Dec 16, 2008
|Advantest Corporation
|Signal generation circuit, jitter injection circuit, semiconductor chip and test apparatus
|Jul 22, 2008
|Jun 14, 2011
|International Business Machines Corporation
|Data-dependent jitter pre-emphasis for high-speed serial link transmitters
|Dec 7, 2000
|Jun 13, 2002
|Fischer Jonathan Herman
|Adaptive interference cancellation for ADSL
|Apr 5, 2004
|Sep 30, 2004
|Interdigital Technology Corporation
|System for processing digitized communication signals provided over plural RF channels
|Jan 31, 2006
|Aug 2, 2007
|Ibm Corporation
|Data-dependent jitter pre-emphasis for high-speed serial link transmitters
|Dec 25, 2006
|Jun 26, 2008
|Advantest Corporation
|Signal generation circuit, jitter injection circuit, semiconductor chip and test apparatus
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|International Business Machines Corporation
|Data-dependent jitter pre-emphasis for high-speed serial link transmitters
|Sep 10, 1991
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|Proteon, Inc.
|Token ring equalizer
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|Universal Data System Inc.
|Modem including an equalizer for amplitude jitter
|U.S. Classification
|375/346, 329/319, 375/376
|International Classification
|Cooperative Classification
|European Classification
|Aug 14, 1985
Owner name: RACAL DATA COMMUNICATIONS INC., 8600 N.W. 41ST STR
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text: On (24/09/06 16:34), Nacho Barrientos Arias wrote: > Dear mentors, > > I am looking for a sponsor for the new version 0.50-1 of my package > "libapp-info-perl". > Hi, I cannot sponsor the package but I have reviewed it. It looks very good in general. I do have a couple of minor points. * Is there a better text you can use than It was downloaded from the Comprehensive Perl Archive Network (CPAN). Visit <http://www.perl.com/CPAN/> to find a CPAN site near you. and a more precise location? * Your ifndef PERL PERL = $(shell which perl) endif also works as PERL ?= $(shell which perl) Have you considered maintaining the package within the debian-perl group? They are very quick at uploading from what I have seen. If you are not then I would suggest to the DDs on this list that this package is ripe for sponsoring. Nacho has done a very good job, even if he has managed to break linda, the poor girl. James -- James Westby -- GPG Key ID: B577FE13 -- http://jameswestby.net/ seccure key - (3+)k7|M*edCX/.A:n*N!>|&7U.L#9E)Tu)T0>AM - secp256r1/nistp256

subset: commoncrawl


text:
Template >> Resume - The Contract 95543 by SMX90 @ CreativeMarket
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text:
Tip From the Archives
Unusually Fast
You are playing the same course as usual but you are wondering why the greens are becoming faster and faster throughout the year.
Check to make sure that you still have a smooth pace and tempo. However, a likely culprit could be a change in the seasons. The temperature and humidity will change the way the grass bends and how high the blades will sit, therefore changing how the ball will roll.
The ball will roll slower when it is hot and humid because the ball has to move through the grass. The ball rolls faster when it is cold outside because the grass requires less water. When the grass requires less water, it makes the grass stiff and therefore faster since the ball can roll on top on the blades instead of having to move through it as it would on a warmer day.
Are we talking about day-to-day humidity and temperature changes? If so, that is interesting.
It is mostly about the temperature changes throughout the seasons. With fall rapidly approaching, it is a common concern. However, you will notice that the grass plays like this if the temperature/humidity fluctuates from day to day.
Yeah, that's the ticekt, sir or ma'am
Something to Add?
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text:
Home / Recognition / Spotlights / Associate Spotlights
Terrie Walker Inducted into Millionaire's Circle
Terrie Walker first joined Viridian Energy on Sep. 17, 2009, a date that she says she remembers as if it were her birthday. She was introduced to the business by her niece, Jenna Marzullo-Stockwell, who was not only the first Viridian Associate, but also the first woman to be inducted into the Millionaire's Circle. The Viridian business has evolved into a family affair for Terrie, as she's had 14 family members involved as Viridian Associates, including her father who is now 91 and still recruiting customers and Associates.
Terrie hails from Winsted, Conn. where she attended Northwestern Connecticut Community College. She and her husband, Peter, are the proud parents of Tyler, Adam and Cory and the grandparents of three. Before launching her Viridian business, Terrie built a career as an accomplished business manager and was the recipient of the Junior Achievement First Place National Accounting Award.
She's had a decorated career with Viridian, having been a GenV Award Winner, Integrity Award Winner, served as a member of the Associate Leadership Council for three years and been a Top 10 Income Earner for the past five years. If you ask Terrie, however, the greatest reward has been her personal growth and helping the environment.
"The monetary gain is just a measurement of how much we've supported our mission," says Terrie. "The more money we make, the more we lower carbon emissions."
According to Terrie, Viridian may be a network marketing company on paper, but at its heart it's about relationships and personal development. Being able to give back and help others has allowed her to grow personally and professionally.
"There's a saying, 'Rising tides lifts all ships,'" she says. "This job is about helping others. Our success is based on the success of others. Once you realize that you see how significant this company is."
Her success has earned her many incentive trips, including Turks and Caicos, Bermuda and Aruba. The greatest trips, according to Terrie, were the sustainability initiatives. She's been on five 7 Continents in 7 Years (7C7Y) trips, which deliver a sustainability project to a different continent each year. To date, Terrie's visited Brazil, Africa, Indonesia, Fiji and Nicaragua with Viridian. The experiences were life changing.
"These trips elevated my gratitude for what we have," she says. "I always thought a shower was a necessity, but it's not: It's a luxury."
Despite how far she's come, Terrie remains driven, committed and continues to look toward the future. She is determined to share the Viridian opportunity with others and make strides toward creating a more sustainable future.
"After all," she says. "We only have one earth."


text:
|Publication number
|Publication type
|Application number
|Publication date
|Apr 20, 2010
|Filing date
|Sep 27, 2006
|Priority date
|Sep 27, 2005
|Fee status
|Also published as
|Publication number
|Raphael Yahalom, Roee Alon, Assaf Levy, Omri Kessel
|Original Assignee
|Netapp, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (69), Non-Patent Citations (10), Referenced by (19), Classifications (16), Legal Events (7)
|External Links: USPTO, USPTO Assignment, Espacenet
This application claims the benefit of U.S. Provisional Patent Application No. 60/720,977, filed Sep. 27, 2005, the entire content of which is incorporated herein by reference.
The invention is directed to methods and systems for determining and validating accessibility and currency, i.e., the actual status, of data replicated in a networked environment.
Data replication is a technique commonly used for achieving high data availability. When multiple replicas of a data set are created and stored at different locations, a replica of the data will more likely be available to a client application even when some components fail or some data sets are corrupted.
In computing systems many techniques exist for copying data and for managing multiple replicas. Replication techniques can be classified to two main categories: synchronous and asynchronous replication. Synchronous replication processes enforce continuous full synchronization between the source data set and the replicas. This involves strong transactional guarantees and ensures that any update to a source data set is consistently and immediately reflected in all the synchronous replicas. However, achieving synchronous replication can in some environments be prohibitively expensive in terms of the overhead it imposes on computing resources, and in some cases not be possible at all (for example due to temporary failure of some component in the environment).
Asynchronous replication, on the other hand, requires a much less stringent time-consistency between replicas by creating copies only periodically. Thus a replica may represent some past state of the data source rather than the current state of the data source. Depending on how far back in the past that reference point is, such discrepancy may still be acceptable for some client applications under some exceptional circumstances (e.g., when recovering from a catastrophic failure). Asynchronous replication imposes a much lower overhead on the computing resources and is commonly used in many environments, such as maintaining geographically remote copies of application data for Disaster-Recovery (DR) purposes.
However, ensuring continuous conformance of the data sets and their replicas with the applications requirements is a difficult challenge for a number of reasons: different applications may have different minimal currency requirements for replicated-data (that is, there are typically differences in their cost/currency trade-off considerations); there may be multiple data-copiers in a typical environment that may be executing concurrently; copy activities may be based on replicas (which may themselves not be fully current) rather than on the original data set, thus creating chains of dependencies; individual copy activities may fail entirely, and a replica at a remote site may be inaccessible to a host due for example to a network or component configuration problem.
Consequently an application may not have a replica of sufficient currency accessible to it at a remote site, if required. Currently, such a deficiency may not be detected until an application actually requires that replica. Present replication technologies focus on the actual correctness of individual copy mechanism, but not on continuous end-to-end validation of the currency and accessibility of multiple replicas of data.
It would therefore be desirable to provide systems and processes for continuously validating replicated data sets in networks as being in conformance with defined application requirements for currency and accessibility, and for identifying and notifying a user of any discrepancies so that corrective actions can be taken before any undesirable consequences.
The invention is directed to systems and processes for continuously validating replicated data sets in networks as being in conformance with a replicated-data policy.
According to one aspect of the invention, a process for validating replicated data residing on network devices in a network includes the steps of defining a replicated-data policy for replicating data in the network, monitoring access paths between network devices or between applications running on the network devices, monitoring data replication activities in the network, and comparing currency and accessibility of a replica with the requirements in the replicated-data policy to identify discrepancies with the replicated-data policy.
According to another aspect of the invention, a replication validation manager for validating replicated data residing on network devices in a network includes a policy engine that stores replicated-data policy for replicating data in the network and a validation engine that monitors access paths between network devices or between applications running on the network devices. The validation engine further monitors data replication activities in the network and compares currency and accessibility of a replica with the requirements in the replicated-data policy to identify discrepancies with the replicated-data policy. The replication validation manager also includes a notification engine that provides a violation notification if a replica cannot be validated.
Embodiments of the invention may include one or more of the following features. The replicated-data policy may specify an access path between a host or application and a replica, and/or a number of replicas in a network, locations of the replicas, one or more access paths between the replicas, and/or a maximum age of a corresponding replica at each location. The data replication activities may include monitoring at least one of synch, split, copy start, copy complete, source data volume, target data volume, and a time of the replication.
Each replica may be associated with a tag which may include at least one of a source data set name, the copy status, and a time stamp. The tag of a replica may be updated in response to a copier event.
Access path attributes may include redundancy and/or number of intermediate components and/or performance and/or security and/or interoperability, sharability, or capacity.
Discrepancies may be identified from a currency violation and/or missing access path and/or unauthorized access path, and/or path attribute violation.
In another embodiment, replication reports may be generated which may include properties of applications, replicas and replication events, and their impact on replicas; replication violations and time to correct them; replication resource utilization over time, or a combination thereof.
The following figures depict certain illustrative embodiments of the invention in which like reference numerals refer to like elements. These depicted embodiments are to be understood as illustrative of the invention and not as limiting in any way.
In the context of the invention, the following terminology will be used for classifying components of replicated data environments:
Host Components are platforms on which application software programs can execute to achieve some useful purpose. At any point in time each host can have one or more applications executing on it. Each application can be executing on one or more host components. In addition each host may contain control programs which control the access to host resources and to external components.
Storage Components are platforms on which data can be stored and retrieved. Each storage device contains a memory sub-component containing multiple addresses in each of which one or more bits can be stored. Data is read from and written to storage devices in units which are referred to as volumes. A volume may contain any amount of data represented by any number of bits. Volumes are stored on storage devices, each starting with a particular start address on a particular storage component. In addition, each storage component may also contain a controller sub-component which controls access to the data in the memory sub-component.
Network components are platforms via which data can be transferred and routed from any source component to any target component. Each network component can control the flow of data depending on the source, destination and status circumstances.
Each of the aforementioned components have a unique identifier (name) associated with it. Moreover, each of the components has one or more ports which enable input and output data to flow to and from that component. Each component can furthermore have a local state which represents a current "Control Configuration" of that component defining certain information flow characteristics such as which data flow can be enabled based on the source and the target components.
Different components can be connected to each other by "Communication Links" via which data can flow from one component to another. Such communication links can connect components located in very close proximity at single site, or at remote geographical locations. Example communication channels can include a cable a point-to-point connection, a local area network, a wide area network and others.
An Access Path exists between two end points (components, data sets, etc) if there is communication links connectivity, and if each intermediate component as well as the end point themselves are configured to enable data flow between these end points.
Environment Configuration Events that can occur in an environment can be classified to different classes including among others: components configuration changes, components addition and deletion, components failed and recovered, data send and receive, data volumes reads and writes, and others.
Applications running on hosts can generate new "Data Volumes" and submit them for storage on storage devices, as well as update or read existing data volumes stored on storage devices.
A Data Copier is a program which at certain points in time reads a volume from a storage device and writes an identical copy of that volume to another location (address) on the same storage device or a different storage device. A copier can execute on any component (host component, storage component, or network component). An initial source volume updated by an application is referred to a source volume, and any volume which was generated by a copier is referred to as a replica volume.
A Replicated-Data Validation Manager 101 is connected to the networks, as indicated by arrows 172, 174, 176, 178, and performs the process described below in order to validate the currency and accessibility of all data replicas in accordance with a specified application data-replication policy.
At step 204, a replicated-data application policy is defined. For each data volume the policy defines: application access path (and attributes) to that volume, access path between replicas of that volume, and attributes, access paths from replicas to other hosts, required minimal currency (or maximally tolerable age) requirements of replicas at different locations (also referred to as Recovery Point Objectives (RPO))
At step 206, information is obtained about events in the environment that affect the currency of replicas or their accessibility. For example, information may be received indicating that a copy action was successfully completed from replica 130 to replica 132 (
At step 208, an analysis is performed to derive from the event information about the status of currency and accessibility of the volumes and replicas.
At step 210, the conclusions of the analysis performed at step 208 are compared with the currency and accessibility requirements that are specified in the policy and if violations are detected, at step 212, notifications are provided regarding these violations. Such violations can be associated with the status or level of currency, for example all replicas of source volume 128 located at a remote location are at the moment less current than the minimum currency specified in the currency and accessibility requirements. Such violations can also be associated with accessibility, for example, if no remote replicas of source volume 128 are currently accessible by remote host-components as required.
In general, an applications replicated-data policy can specify for each volume in the environment: (1) which hosts and application should have an access path to that volume; (2) how many replicas should it have, where should they reside, and what should be the access path between these replicas; (3) what should be the maximum age of the replica at each location (what is the RPO); and (4) should any remote hosts have an access path to any of the replicas.
Thus the policy can represent many types of application requirements including, for example, the following exemplary requirements:
The next step in the replicated-data validation process (represented by step 206 in
Data copier replication events information include for example:
A conventional asynchronous copy of one volume to another volume may also be represented by a Synch event followed by a simultaneous Copy-Completed and Split events. Any volume generated or updated by a Synch event of a copier is referred to as a Replica Volume.
At point in time 401, a synch copy event occurs between volume 1 and 2, at point in time 402 the copy is completed, and at point in time 403 a split event occurs. If a copy is initiated between volume 2 and 3 at point in time 404 and the copy is completed and a split is performed at point in time 405. In order to determine the currency of volume 3 after point 405 the history of previous copy events need to be considered. Note also that between the time a copy is started (for example, point in time 401) to the point in time it is successfully completed (for example, point in time 402), the state of the target replica is inconsistent.
Environment configuration events may also affect access paths. Event information collected include:
The next step in the replication validation process (represented by step 208 in
The currency conclusions are derived from the replication event information in the following way. An association is maintained between each replica volume and a Replica Header Tag, which may include among others the following attributes:
The Replica Header Tag of a replica is updated in response to different copier events, as described above. These Tag updates can, for example, adhere to the following principles:
Accessibility conclusions are derived from the environment configuration events information by determining all the access paths in the environments. That is, deriving all the volumes and replicas at all storage devices that each initiating component can obtain data from or provide data to. The analysis is performed repeatedly after each event using the following underlying principles:
An access path exists between an initiator component and a target component if there exists a communication connectivity (at least one communication link and possible additional intermediate components interconnected with communication link) between the initiator component and the target, and the access control configuration on each component in the sequence (starting with the host and ending with the storage device) is set to enable data flow between the sources in the prefix of the sequence to the destinations in the postfix of that sequence.
Furthermore, the current step in the process derives for each identified access paths various end-to-end attributes of that access-path as determined by cumulative analysis of all the state information and events information associated with components in that access path. These derived access path attributes represent various service dimensions such as level of redundancy in the path, level of access performance within the path, number of intermediate components between host and target volume, storage capacity, among others.
This analysis may also establish in a similar way the existence of appropriate access paths between data copiers and data volumes (source and target volumes).
An extended type of an access path is a Disaster-Recovery Access-Path (DR-Path) which represents an access relationship between host-components and a sequence of a number of replica volumes (local and remote).
Such a notion of a DR-Path is a useful way to specify and enforce both the host to volume required access attributes as well as the volume to replica and replica to replica required access attributes.
Such DR-Paths can be formally defined in a number of ways, for example, as follows:
Let νl . . . νn be data sets. Each data set νi is of a certain type tk that belongs to a set of types {tl, . . . , tm}.
A path segment exists between νi and νi+l if there is physical connectivity between νi and νi+l and also logical connectivity between them. νi and νi+l have logical connectivity if the physical path/s between them complies with certain set of rules that are a function of νi and νi+l's types.
A path exists from νk . . . νl if for every k≦i<l there exists a path segment from νi to νi+l.
Another exemplary definition:
Let νl . . . νn be computing nodes. Each node νi is of a certain type tk that belongs to a set of types {tl, . . . , tm}.
A Stored-Data Access-Path νk . . . νl exists if there is physical connectivity from νk to νl, and if the logical state of each node νi k≦i<l in the sequence is set to enable data flow along that sequence to or from a longer-term storage type node (in response to an initiation action by one of the other nodes in the sequence).
Another exemplary definition:
Let Hi denote hosts, Let Dj denote Storage Area network (SAN) devices (switches, routers, HBAs, etc.—local area or wide area networks), and let Vk denote stored data sets (volumes on storage devices)
A DR path is a sequence Ha-Vm- . . . -Vn[-Hb], such that:
Multiple types of DR-Paths can be predefined, each representing a particular permutation of replica types, and potentially a remote host associated with a specific sequence at the other end.
For example, EMC Corporation, Hopkington, Mass. (USA) supplies infrastructure storage components. EMC's technology refers to specific names for replica types (e.g. BCVs, R1s, and R2s representing local and remote synchronous and asynchronous replicas respectively) and imposes certain constraints on the replica type copy sequence relationship.
In the context of EMC infrastructures, the following are examples of possible predefined DR-Paths types which can be used and enforced:
Each represents an access-path relationship between a host and a volume, between a volume and replica, possibly between a replica and a replica, and between a replica and a host.
The next step in the replicated-data validation process (represented by step 210 in
These requirements and others can be established with the replication analysis and access-path analysis mechanisms outlined above as follows:
Any discrepancy between the derived conclusions and the policy requirements is considered a violation. Thus a replicated data violation can represent a case in which a volume is not accessible to a host or to another replica in a manner consistent with its DR-Path specification in the policy, that one of the attributes of the existing access path or DR-path is different than the one specified in the policy, or that the most current replica of that volume beyond a specified distance is older than the Recovery Point Objectives (RPO) specified by the policy.
The next step of the replication-validation process process (represented by step 212 in
The violation and the context information are listed and stored, and appropriate notification messages may be generated and sent to appropriate parties based on filtering rules that are applied to the violation information. The correction of a violation is also automatically detected by the mechanisms described, and the stored repositories are updated and appropriate notification messages can be sent.
The current process also stores received event information (from components and from data copiers) in a history structure in a database, and associates with each event the derived access path conclusion results. That history database represents the complete evolution of the access paths status in the environment is available for further analysis and summary reporting.
Another possible embodiment of the invention enables planning and simulation of future changes, events, and failures to determine their expected impact on the replication requirements, and prevent problems before they occur.
The events that can be specified are possible future component change actions, possible data copiers action, or possible component failure or site failure.
The analysis performed is analogous to the one described above using the current state of the environment components and replicas, and considering the simulated event input as if this is the event information that was collected from the environment (represented by step 204 of
The context information of each such future violation is generated and provided in the same way provided for regular violations (see above). Once validated, the innovation can actually track the execution of any corresponding change events, track implementation progress, and reports upon successful completion (or notify of any resulting violations).
Yet another embodiment of the invention enables summary reporting of the information accumulated and processed during the replication validation process. The information collected and analyzed by the current innovation enables the generation of a wide variety of useful data replication validation summary reports and trending reports.
The types of reports that can be generated include for example the following, among many others:
While the invention has been disclosed in connection with the preferred embodiments shown and described in detail, various modifications and improvements thereon will become readily apparent to those skilled in the art. Various aspects of access path, their validation and management, are described, for example, in commonly assigned U.S. patent applications Ser. No. 10/693,632, filed 23 Oct. 2003; and Ser. Nos. 11/112,942 and 11/112,624, both filed 22 Apr. 2005, the contents of which is incorporated herein by reference in their entirety. Accordingly, the spirit and scope of the present invention is to be limited only by the following claims.
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|Jan 18, 2007
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Recently I posted a lace hot pink playsuit from LOVE* that I wore with a leather jacket, black boots and a black fedora to show you one way to wear lace making it look a bit harder. Here I am wearing the exact same playsuit but in a light dusky pink and showing how to wear it to make it look a bit more girly for a weekend BBQ or even a summer wedding or party. (details at the bottom)
Playsuit* – inlovewithfashion / Jacket – Zara / Shoes – Matalan / Necklace, Rings and Sunglasses* – Claire's Accessories /


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Monday Location
Our Monday Class is Held at Eastwood Christian Church on the 2nd Floor of the Fellowship Hall (next to playground).
1601 Eastland Ave
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Sunday Classes are Held at DancEast Located in East Nashville.
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Joosse Interieurs
Langstraat 2
4341 EE Arnemuiden
Accente, Bielefelder Werkstätten, 3 B
pillows, bedside tables, chaises longues, lighting, arm chairs, chairs, coffee tables, sofas, dining chairs, dining tables, beds, side tables, footstools
The listings above were submitted to Liever, either by the brands or by the stores themselves. Although we strive for accuracy and completeness, unintentional errors and omissions may occur.
Accente new
3 B new


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Up & Down Wall Street: A Financial System on the Brink, a documentary presented by The Paulson Institute and the University of Chicago Institute of Politics. Read more Up & Down Wall Street: A Financial System on the Brink
Up & Down Wall Street: A Financial System on the Brink, a documentary presented by The Paulson Institute and the University of Chicago Institute of Politics. Read more Up & Down Wall Street: A Financial System on the Brink
This documentary, The Biggest Con Job in World History Wall Street, is a real eye opener. The fat cats of Wall Street don't give a s*$%! about people, they just care about that stuff on paper that was created basically out of thin air. Right from the creation of the Federal Reserve in 1913, the fat cats and banking elites have plagued human society, and need to be dealt with! Read more The Biggest Con Job in World History Wall Street
This documentary film explains how money is created and how central banks work.
When money drives almost all activity on the planet, it's essential that we understand it. Yet simple questions often get overlooked, questions like; where does money come from? Who creates it? Who decides how it gets used? And what does this mean for the millions of ordinary people who suffer when the monetary, and financial system, breaks down? Read more How Money Is Created
The Crash of 1929, was originally produced in the mid-1990s. This documentary film remains the most authoritative account of the Crash of 1929, and includes rare testimony from the people who worked on Wall Street at the time. Read more The Crash of 1929
Quants The Alchemists of Wall Street, a documentary film of a story about greed, fear and randomness from the insides of Wall Street.
Quants are the math wizards and computer programmers in the engine room of our global financial system who designed the financial products that almost crashed Wall st. The credit crunch has shown how the global financial system has become increasingly dependent on mathematical models trying to quantify human (economic) behaviour. Now the quants are at the heart of yet another technological revolution in finance: trading at the speed of light.
Money and Speed: Inside the Black Box is a thriller based on actual events that takes you to the heart of our automated world. Based on interviews with those directly involved and data visualizations up to the millisecond, it reconstructs the flash crash of May 6th 2010: the fastest and deepest U.S. stock market plunge ever.
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The Wall Street Code, a documentary film presenting a genius algorithm builder who dared to stand up against Wall Street. Haim Bodek, aka The Algo Arms Dealer. Could mankind lose control of this increasingly complex system?


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Facts of Life Book 22 – Profanity
Today, it isn't unusual to hear profanity. We watch actors using it in movies and on television, we listen to it on CD's, and we see it in the form of graffiti on walls. For many people, this widespread acceptance means it's okay to use swear words in daily conversation. Nothing could be further from the truth. The use of dirty words is a turn-off to a majority of the population, even when there is laughter in a packed movie or in front of a television screen.
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