text:
|Publication number
|Publication type
|Application number
|Publication date
|Mar 20, 2012
|Filing date
|Aug 29, 2008
|Priority date
|Aug 29, 2008
|Fee status
|Also published as
|Publication number
|Anthony Correale, Jr., Benjamin J. Bowers, Matthew W. Baker, Irfan Rashid, Paul M. Steinmetz
|Original Assignee
|International Business Machines Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (42), Non-Patent Citations (10), Referenced by (7), Classifications (7), Legal Events (3)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention generally relates to the field of integrated circuits. More particularly, the present invention relates to making design-for-manufacturing alterations to cells of 1×N building blocks via a closed-loop 1×N compiler. The integrated circuits of today commonly have hundreds of millions of transistors on a single chip, with many critical circuit features having measurements in the deep sub-micron range. As manufacturers implement more and more circuit elements in smaller and smaller silicon substrate surface areas, engineers and designers develop hardware and software tools to automate much of the integrated circuit design and manufacturing process.
The classical design methodology for designing and manufacturing integrated circuits employs an open-loop design process whereby the activities of logic capture and physical realization are separate and lack coherency. For example, a team of designers generally start with a conceptual design, develop associated logic, perform synthesis of the logic design to develop an associated physical design, and analyze the physical design for timing performance. During these phases, designers may make adjustments to the one or more circuit devices, such as changing parameters of drive strength or making power optimizations. If the register transfer level (RTL) design is not frozen, the designers may develop or change the logic, perform the synthesis to create another physical design, and analyze the new design. Until designs of the integrated circuits reach a "logic-freeze" stage, at which point synthesis stops, design improvements from physical optimizations are often lost for the iterations through the design flow. Such optimizations are often necessary for meeting design goals related to operating frequencies and power consumption.
To add to the complexity of the design process, some design implementations define specific logic functions for which there are one-for-one physical realizations. The physical realizations are often fixed entities, both logically and from the standpoint of electrical realization. For these specific design implementations, a circuit designer and/or physical designer generally need to know details of the specific design at a very early stage in the design process. Additionally, the designer must have the ability to craft the specific design. As the design progresses, the designer routinely needs to optimize the design to reduce power consumption, increase performance, and reduce the amount of the required area. Current methods of maintaining physical optimizations before a design reaches the stage of logic freeze include manual instantiation of gates and manual changes to the synthesis flow to produce predictable and repeatable results. Designers spend considerable time optimizing the circuits because the optimizations require manual intervention and constant updating for individual iterations through the design flow.
Current state-of-the-art design-for-manufacturing (DFM) enhancement tools generally make changes to standard-cell based designs by enhancing elements of the individual cells, enhancing higher-level wiring using such techniques as wire spreading and via-redundancy, and enhancing overall mask data to perform optical proximity or sub-wavelength effect correction. These techniques are generally shape-based alterations.
Following are detailed descriptions of embodiments depicted in the accompanying drawings. The descriptions are in such detail as to clearly communicate various aspects of the embodiments. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments. On the contrary, the intention is to cover all modifications, equivalents, and alternatives of the various embodiments as defined by the appended claims. The detailed descriptions below are designed to make such embodiments obvious to a person of ordinary skill in the art.
Some embodiments comprise using a 1×N compiler to detect a relationship between two adjacent cells of a 1×N building block. Based on the relationship, the embodiments select a DFM alteration and apply the alteration to a physical design representation of the 1×N building block. The embodiments may apply various types of DFM alterations depending on the relationship, such as adding polysilicon, adding metal to create a redundant connection, merging diffusion areas to increase capacitance on supply nodes, enhancing implant coverage over a gate, merging a small metal feature into a large metal feature to mitigate a minimum metal area problem, merging shapes to improve pattern density, and adding polysilicon shapes to improve polysilicon pattern uniformity.
Further embodiments comprise an apparatus having a cell examiner to examine two adjacent cells of a 1×N building block and determine a relationship of the two cells. The apparatus also comprises a DFM selector to select a DFM alteration based on the relationship. Additionally, the apparatus includes a DFM applicator to apply the selected DFM alteration to one of the cells.
Even further embodiments comprise a computer program product comprising a computer readable medium having a computer readable program, wherein the computer readable program causes the computer to detect a relationship between a first cell and a second cell, wherein the first cell and the second cell are adjacent cells of a 1×N building block. The computer readable program further causes the computer to select a DFM alteration for one of the cells based on the relationship. Additionally, the computer readable program further causes the computer to apply the DFM alteration to a physical design representation of the 1×N building block.
Aspects of the various embodiments will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which like references may indicate similar elements:
The following is a detailed description of novel embodiments depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the subject matter. However, the amount of detail offered is not intended to limit anticipated variations of the described embodiments. To the contrary, the claims and detailed description are to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present teachings as defined by the appended claims. The detailed descriptions below are designed to make such embodiments understandable to a person having ordinary skill in the art.
Many of the embodiments contained herein describe using 1×N building blocks to design an integrated circuit. A circuit layout or circuit design may comprise a hierarchical collection of circuit elements or cells. A building block, or macro, may generally refer to the concept that a circuit may comprise a plurality of different circuit elements or cells, wherein the cells may be divided into categories. These categories may be basic cells, level cells, and building blocks. Basic cells, which may alternatively be referred to as leaf cells, may comprise an aggregation of circuit elements, such as a collection of logic gates, and may be thought of as residing at the bottom of the design hierarchy. Basic cells may be nested together, along with other circuit elements, to form level cells at different mid-levels within the design hierarchy. The level cells, which are frequently referred to as composition cells, may be further nested together to form building blocks, alternatively referred to as macros, which may also be referred to as root cells or prime cells. Building blocks may be thought of as residing at the top of the design hierarchy. Building blocks may also be referred to as blocks or modules.
1×N building blocks may contain a homogeneous collection of cells, also commonly referred to as bits, or contain an inhomogeneous collection of cells. For example, one 1×N building block may contain four AND gates while another 1×N building block may contain two AND gates, three NAND gates, and two OR gates, as well as auxiliary bits or cells. Additionally, while some bits of 1×N building blocks may be relatively simple, such as comprising a latch, some bits may also comprise a more complex collection of elements, such as comprising multiplexers.
The use of a cell at a specific level in the design hierarchy may be referred to as a cell instance, or instantiation. A circuit with only one hierarchical level is said to be flat. During a design sequence a VLSI design system may need to flatten a circuit design, converting the hierarchical levels into a single level, so that certain design tools may work with the design. For instance, a circuit simulation tool or a circuit optimization tool may only be able to simulate or optimize a circuit design that has a flattened netlist. A VLSI design system may flatten, or fully instantiate, a circuit design by recursively replacing all cell instances with basic circuit elements like resistors and capacitors.
Additionally, many of the embodiments use the term "optimized" and or "tuned". As one skilled in the art of integrated circuit design will appreciate, such terms as "tuned", "optimal", and "optimized" as used in the design process may refer to a portion of an integrated circuit that has been altered to comply with some design constraint. For example, a simulation tool may determine drive strength for a specific gate in the circuit, selecting a parameter for the drive strength that makes a tradeoff between two or more competing interests, such as speed versus power consumption. Consequently, such terms should not be interpreted as choosing "optimal" or "best" settings, since such settings or parameters may often be subjective in nature. Such terms should therefore be considered in the context of integrated circuit design, consistent with the manner in which the terms are used by those possessing ordinary skill in the art.
Persons having ordinary skill in the art often use various titles for persons performing different tasks of creating an integrated circuit design. For example, some refer to a design engineer as a person that performs such tasks as receiving specifications, creating behavioral and logical circuit designs, running simulations, and evaluating prototypes that are fabricated. Similarly, some refer to a test engineer as a person that develops a test plan for a circuit design based on the specification and actually performs simulations of the design and/or physical tests of a fabricated prototype. Some may refer to a computer aided design (CAD) engineer as a person that uses CAD tools, such as schematic capture, simulation, synthesis, layout, and power estimation tools to evaluate and modify the circuit design. Due to the difference in use of titles, which may vary greatly, this specification uses the terms circuit designer, logic designer, or simply designer to refer to a person that may perform any of the described tasks for creating the circuit design. In other words, the terms circuit designer, logic designer, designer may be substituted interchangeably in the specification, and should not be interpreted as referring to a person that may only perform specific tasks. To the contrary, the terms circuit designer, logic designer, designer may refer to persons that can perform any of the tasks described herein, such as the tasks of behavioral design, logical design, physical design, and timing analysis/design.
Turning now to the drawings,
1×N compiler 160 and VLSI design application 145 may provide a closed-loop environment that employs high-level 1×N constructs for tuning performance and power consumption. VLSI design application 145 may capture logic using both high-level RTL and references to 1×N building blocks. 1×N compiler 160 and VLSI design application 145 may represent the 1×N building blocks via a high-level language and transform the 1×N building blocks into custom realizations using, e.g., building blocks available in a standard or custom cell library.
The custom realizations for the 1×N building blocks may include numerous DFM alterations made via 1×N compiler 160. For example, the DFM alterations may include such enhancements as adding polysilicon or metal wires that create a multi-layer connection redundancy, wire and/or via redundancy on metal and/or via layers, merging diffusion areas to increase capacitance on supply nodes, enhancing implant coverage over gates, diffusion, or field polysilicon areas, merging small metal features into a larger metal feature to mitigate minimum-metal-area problems, merging shapes to improve pattern density, and adding polysilicon shapes to improve polysilicon pattern uniformity and gate length control. The DFM alterations made by alternative embodiments may also include other types of alterations other than the ones just listed. For example, one embodiment may merge N-well-to-substrate contact areas to create larger voltage islands. Merging N-well-to-substrate contact areas may reduce resistance to a bulk node of a transistor and increase resistance to latch-up.
Compared with standard cell-based designs, an embodiment employing a 1×N design flow may have additional opportunities for DFM alterations. One advantage of a closed-loop 1×N methodology may stem from the 1×N compilation performed via 1×N compiler 160. The 1×N compilation may provide information related to the logical structure, placement, and physical structure of the components inside 1×N building blocks 155. Using the information, 1×N compiler 160 may make both yield and electrical behavior enhancements to cells of 1×N building blocks 155. 1×N compiler 160 may make the DFM alterations by determining which portions of the cell-to-cell interface edges may be modified based on such considerations as relative placement of the cells, cell-to-cell connectivity, cell-types, and shapes inside the layouts of the cells.
In various embodiments, a system may have a processor, such as processor 105, for executing program instructions of applications, such as VLSI design application 145. While executing program instructions of VLSI design application 145, computing system 100 may display images of the circuit design, or information pertaining to simulation or performance tuning, on a monitor or other computer display, such as display 110. For example, VLSI design application 145 may generate pictorial schematic elements, as well as wires connecting the various schematic elements, for a schematic in a window 115 on display 110.
Using input device 120 a circuit designer may interact with VLSI design application 145. In one or more embodiments, input device 120 may comprise a keyboard and/or a mouse, allowing the circuit designer to perform such actions as viewing different circuit sections or performing numerous circuit design activities such as performing a timing analysis, increasing the drive strength of a gate, or defining which circuit elements should not be modified during various design cycle iterations. In some embodiments input device 120 may comprise a tablet and stylus, such as a pressure-sensitive surface or a capacitance pad that recognizes hand-written characters and stylus movement. In even further embodiments input device 120 may comprise an audible input device, such as a microphone used for speech recognition. For example, in one embodiment input device 115 may allow a circuit designer to automate one or more tasks during the design flow, such as by recognizing when the circuit designer speaks the phrase "calculate Vt-hybridization values for selected 1×N building blocks".
Display 110 and input device 120 may also allow the circuit designer to interact with VLSI design application 145 when creating, viewing, and manually modifying various 1×N building blocks 155. For example, 1×N block builder 150 may allow a circuit designer to retrieve a 1×N building block from a cell library 130, stored on a storage device 125. Storage device 125 may comprise a local solid state drive or a network hard drive, as examples, which stores standard cells and various instantiations created by a circuit designer. Upon retrieving a 1×N logic block, 1×N block builder 150 may allow a circuit designer to edit the 1×N building block by displaying configuration information for the 1×N building block in window 115. After editing the 1×N building block, VLSI design application 145 may save the edited version back to cell library 130.
In the embodiment depicted in
The product of the design concept 210 may be a flowchart, a flow graph, or pseudocode. The designer may specify the overall functionality and input-to-output mappings without developing architectural or hardware details for the circuit design. Based on the design concept 210 the circuit designer may develop a behavioral description of the circuit during logic phase 220, such as by using a high-level language to define how the circuit should work at a high level of abstraction. More specifically, the circuit designer may write a hardware description of the IC using a hardware description language (HDL), such as Verilog or VHDL (very-high speed integrated circuit HDL). As is known to those skilled in the art, the high-level code or behavioral representation may be referred to as RTL netlists. At the RTL level, the behavioral description may consist of program-like constructs, such as, variables, operators, conditionals, loops, procedures and functions.
The circuit designer may then simulate the design, or different portions of the design, by using one or more behavioral tools to verify the design works as intended. For example, the circuit designer may apply input combinations and/or sequences of data to different modules to verify that the modules respond as intended. After the hardware description of the design has been through several iterations, and exhibits some degree of operability and stability, the circuit designer may convert the HDL code to a logical representation via a synthesis phase 230. During synthesis phase 230, a VLSI design application may convert the HDL definition of the circuit, transforming the textual descriptions of the behavioral representation to logic gates. In other words, the synthesis phase 230 may transform the VHDL code into a netlist describing the hardware, which may comprise circuit elements and the wires connecting them.
The logical representation may comprise gate-level logic, such as AND, OR, NOT, NAND, and NOR gates, to name just a few. The gate-level logic may be arranged to implement the desired functionality described in the high-level HDL code. The tools that perform the conversion from the high-level description to the gate-level logic are generally called synthesis tools. For example, a set of synthesis programs from Synopsys® may perform the conversion from the high-level code to the logic-level code. As is known to those skilled in the art, the logical representation, or logic-level code, may be referred to as gate-level netlists. The logical representation may comprise a netlist of high-level macrocell components, such as adders, pipelined multipliers, arithmetic logic units, multiplexers, and register-files. Each macrocell, or building block, may have a corresponding netlist of primitive cells as well as a corresponding custom layout. This gate-level netlist of primitive cells and the layout may be generated using a silicon compiler tool, like 1×N compiler 160.
Once the high-level code is converted to gate-level code, the designer may perform additional testing via simulation and formal verification in order to verify that the gate-level netlists accurately represent the RTL netlists. In other words, one or more synthesis tools and/or behavioral tools may help the designer determine whether the logical design accurately represents what the behavioral design describes. If the logic-level code is successfully verified, a circuit designer may use one or more physical design tools to convert the logic level code into a detailed layout of structural components or elements of the circuit in physical design phase 240. The detailed layout of structural components may generally be referred to as a physical design representation. The physical design representation may comprise different forms and formats from embodiment to embodiment, as well as in the same embodiment. For example, persons having ordinary skill in the art may refer to different forms of the physical design representations using such terms as the physical realization, the hierarchical physical design (PD) netlist, the flattened netlist, the physical view, the physical placement data, the electrical realization, or simply netlist.
In various embodiments, a 1×N compiler may be configured to create one or more DFM alterations on a bit-by-bit, or cell-by-cell, basis. For example, the 1×N compiler may add polysilicon, diffusion, and implant straps for redundancy in the physical design representations. Additionally, the 1×N compiler may make the DFM alterations without altering the schematic. Contrasted with current technology DFM approaches, which generally use shape-based manipulation, the 1×N compiler may be configured to make the DFM alterations using connectivity, cell-type, and relative cell placement information to enable both yield and electrical behavior enhancements to the design.
Two common forms of the physical design representations are the hierarchical PD netlist and the flattened netlist. As noted, the hierarchical PD netlist and the flattened netlist may represent the physical design produced during the physical design stage 240. Based on the physical design representation, the circuit designer may use one or more timing analysis tools during a timing phase 250 to evaluate the timing performance of the design. Assuming the timing performance is acceptable, the circuit designer may release the flattened netlist or the hierarchical netlist to a semiconductor fabrication facility to produce the IC.
The circuit designer may have to repeat one or more of the design activities numerous times before reaching the final physical design. For example, once the designer creates the gate-level logic in logic phase 220 and simulates the design via one or more simulation tools, the designer must often make changes to the HDL definition and create a modified version of the gate-level logic. Simulating the modified logic may uncover more design deficiencies that the circuit designer must correct. In other words, the circuit designer may have to pass through logic phase 220 numerous times.
Aside from logic changes, the circuit designer may also need to alter the design to correct problems encountered after synthesis phase 230, physical design phase 240, and timing phase 250. For example, the circuit designer may progress through the design process to the point where the design works perfectly under simulation, but finds that a routing tool cannot create a functional wiring arrangement for the design, due to rule restrictions or area constraints. Alternatively, one or more optimization tools may generate changes to the design. One such example may be incremental performance improvements, such as reduced delays, produced by iteratively feeding the results of a place and route (P&R) tool back into a synthesis tool.
During an open-loop design sequence, the circuit designer may need to exert caution to prevent having the accumulated design improvements altered or negated, due to disjointed activities of capturing logic in logic phase 220 and developing the physical design in physical design phase 240. Until the design reaches the logic-freeze stage, which halts subsequent synthesis in synthesis phase 230, physical optimizations such as tweaks made for drive strengths and power optimization may be lost during subsequent synthesis iterations. Using a closed-loop methodology offered by 1×N compilation 260, an application like VLSI design application 145 may maintain these physical optimizations without depending on disjointed tools and databases.
1×N compilation 260 may allow a VLSI design system to employ a closed-loop design process whereby physical implementation details, such as alterations due to drive strength and power optimization, may be fed back into each step of the design process. The VLSI design system may feed the design alterations back to the different design phases by using 1×N building blocks and inserting data generated by compiling the 1×N building blocks back into the design flow.
A VLSI design system may use a 1×N compiler during 1×N compilation 260 to create, modify, and maintain 1×N macros through the design process. As will be illustrated in the subsequent discussion of the various embodiments, the 1×N compiler may directly update the configuration file or files of a circuit design in a closed-loop manner. Additionally, the 1×N compiler may support direct wiring, have built-in DFM features, and have hierarchical wiring avoidance. DFM improvements made during physical design phase 240 may be retained during 1×N compilation 260 for recompilations of the design for logic phase 220, synthesis phase 230, physical design phase 240, timing phase 250.
With a general understanding of some of the steps that may be involved in the closed-loop 1×N methodology, we return now to
Depending on the embodiment, computing system 100 may run a variety of different operating systems. For example, in one embodiment computing system 100 may use AIX®. In another embodiment, computing system may use Microsoft® Windows®, Linux®, or Mac OS®, as examples. Other alternative embodiments may have no operating system at all. For example, computing system 100 may comprise a state machine or microcontroller executing firmware instructions, such that no operating system is necessary.
One or more design files 135 may be stored on a storage medium of storage device 125 and accessed by computing system 100. For example, storage device 125 may comprise one or more of a variety of different mass storage devices used to store VLSI design files 135 and macro and/or cell library 130. For example storage device 125 may comprise a serial hard disk drive or a small computer system interface (SCSI) redundant array of inexpensive disks (RAID). Alternatively, storage device 125 may also comprise an optical storage device, such as a rewritable compact disc (CD) or a digital versatile disc (DVD) drive, having storage mediums of a CD and DVD, respectively. In other embodiments, storage device 125 may comprise a flash memory device, such as a universal serial bus (USB) drive. Storage device 125 may also store other files and information, such as the operating system for computer system 100.
While not shown in
In one or more alternative embodiments, computing system 100 may also work with one or more other networked computing devices to perform one or more of the different design activities. For example, in one embodiment computing system 100 may edit and compile 1×N building blocks and generate a schematic view for the IC design. However, during the synthesis, physical design, or timing analysis stages, VLSI design application 145 may transfer netlist 185 for the design to the networked computer(s). Such an arrangement may be desired, for example, where the design task requires extensive computational power that may otherwise overload computing system 100. As the above example illustrates, various embodiments of a system may comprise an almost limitless number of wired and wireless communication devices, allowing computing devices of a system to communicate with each other to share and/or process VLSI design files, wherein the computers may be located close to or remote from each other.
As described earlier, 1×N compiler 160 and VLSI design application 145 may work with 1×N building blocks 155. 1×N building blocks 155 may comprise the means by which physical implementation details of circuit elements in 1×N building blocks 155 are stored. A building block of 1×N building blocks 155 may provide a layer of abstraction between the logical behavior of the block and the physical realization of the corresponding logic elements. In numerous embodiments, 1×N building blocks 155 may comprise one or more user-configurable text files. In alternative embodiments, the building blocks may be represented in an alternative file format. For example, the building blocks may be stored in a proprietary binary file that is encoded and decoded as a circuit designer views/edits the 1×N building blocks.
1×N compiler 160 may perform a variety of tasks in VLSI design application 145. 1×N compiler 160 may comprise a software module or other type of module that, at a high level of abstraction, converts data from the building blocks of 1×N building blocks 155 into behavioral, physical, and logical representations, or definitions. 1×N compiler 160 may convert 1×N building blocks 155 into specifically formatted implementations as required by the different design phases. For example, conversions of 1×N building blocks 155 may be represented by 1×N compilation 260 in
1×N block builder 310 may comprise a graphical user interface (GUI) routine that allows the circuit designer to create one or more building blocks and implement a desired logical function. For example, 1×N block builder 150 may allow the circuit designer to create a bank of NAND logic gates in a relatively easy and efficient manner without having to be familiar with the actual scripting language required by 1×N compiler 160.
In various embodiments, 1×N block builder 310 may comprise the initial entry point to the 1×N compilation stage, which may correspond to 1×N compilation 260 shown in
While 1×N block builder 310 may generate a default set of implementation details, the designer may be able to choose between specific implementation types and make specific customizations for 1×N building block 315, such as specific drive strengths, Vt-hybridizations, and/or voltage island references. Once the designer has chosen a desired 1×N building block 315 to build, 1×N block builder 310 may generate a logical RTL instantiation for 1×N building block 315, as well as the physically crafted realization of 1×N building block 315. One embodiment of a window for block builder 310 is depicted in
Compiling 1×N building blocks like 1×N building block 600 with a 1×N compiler may enable a VLSI design application to perform numerous transformations, or modifications, to elements and/or cells in the building blocks during the design process. The VLSI design application or a designer may invoke timing optimizations and/or power optimizations, either directly through synthesis refinement or manually via an engineering change (EC) mode. The designer or VLSI design application may change predefined 1×N building blocks. For example, the designer may transform such parameters as polarity, drive strength, and hybrid-Vt for 1×N building blocks, thereby creating custom 1×N building blocks. Even further, the 1×N compiler may be able to examine or analyze the 1×N building block cell types, cell placement, and connectivity between the cells to make one or more DFM alterations.
Using a 1×N compiler within a 1×N building block methodology to design a VLSI circuit may create a framework that allows 1×N building blocks to be utilized in different ways. For example, in some embodiments, 1×N building blocks may be configured for use with industry-standard formats. In other embodiments, the 1×N compiler may allow the 1×N building blocks to use alternative, special, or proprietary features. As will be illustrated, the 1×N compiler may have the ability to "reform" or reassemble hierarchy from a previously flattened hierarchical design, allowing optimization tools that work on flat data to nonetheless enable use of 1×N building blocks.
1×N building blocks 600 and 660 are exemplary building blocks, none of which may be required in any specific embodiment. 1×N building blocks 600 and 660 may be the results of individual optimizations through each design phase in order to meet power, area, and timing goals for one particular latch bank and the associated timing paths for the latch bank. Various integrated circuit parameters may vary with factors such as temperature, voltage and frequency. One circuit parameter that a circuit designer may adjust is the drive strength of one or more circuit devices, such as an output driver stage. For example, the circuit designer may match the output drive strength of a signal to the circuit being driven. Another parameter that a circuit designer may adjust is Vt-hybridization. Vt-hybridization refers to an optimization technique for static power reduction while optimizing performance within a given drive strength. Worth emphasizing, in many embodiments the polarity of individual bits of a 1×N building block may also be modified by optimization routines. Additionally, the polarity of individual bits may be manually modified.
Returning back to
In some embodiments, uniquifier 320 may also be configured to selectively ignore or uniquify specific sets of 1×N building blocks 315. Selective uniquification of building blocks may be advantageous in situations where parent-child relationships do not need to be defined during the logic entry stage, which may correspond to logic phase 220. The parent-child relationships may be defined on-the-fly as the relationships are required for a design stage. Depending on the embodiment, uniquifier 320 may be configured to read netlist 330 in a mixture of different formats. For an example referring to
During the various iterations of a design, 1×N compiler 340 may generate compilation data for a number of different views 350. The different views of views 350, which may correspond to output view data 180 depicted in
1×N compiler 340 may generate compilation data for behavioral RTL as well as gate-level RTL. Additionally, 1×N compiler 160 may generate compilation data for physical views, helper scripts, and potentially numerous other views depending on the embodiment. For example, VLSI design application 145 may use 1×N compiler 160 to generate Verilog HDL behavioral RTL and corresponding Cadence™ physical views. Additionally, in numerous embodiments, 1×N compiler 160 may be configured based on the tool suite of the user, such as tools 190. In other words, an embodiment may control which languages and view types are generated. An alternative embodiment may generate VHDL behavioral RTL and corresponding Synopsys® physical views.
Iterative Logic Cycle
To illustrate in more detail the iterative logic, synthesis, physical design, and timing cycles for 1×N building blocks, we turn now to
The iterative logic cycle depicted in
1×N compiler 406 may insert checks, or verification text, in the 1×N behavioral RTL model for the parameterized features. When the design is simulated via an RTL simulation tool, the verification text may ensure that the intent of the designer, which is described in the RTL, matches the gate-level implementation defined by the 1×N behavioral model. One should note that the behavioral model for a 1×N building block may not need to be gate-specific. As a behavioral model, the model may describe the logical function using higher-level constructs. The higher-level constructs may be defined by the RTL language used. For example, the higher-level constructs for System Verilog may be different than the higher-level constructs for VHDL.
1×N compiler 406 may verify that the behavioral model, which may be represented by behavioral view 408, and the gate-level implementation are equivalent. For example, in one embodiment 1×N compiler 406 may verify that the behavioral model and the gate-level implementation are equivalent by using one or more verification tools. The verification tools may be, e.g., industry standard verification tools available in IC design systems available from Cadence™, Synopsys®, Mentor Graphics®, Magma®, or other design systems. Verifying the equivalency of the behavioral model and the gate-level implementation may help protect the designer from inadvertent changes during the logic design, as well as protect the designer from gate-level changes that might alter a function of a 1×N building block.
The behavioral model construct generated by 1×N compiler 406 may allow the circuit designer to reuse 1×N building block 404 and related logical function(s) in the design without having to worry about the gate-level tweaks that may be necessary for proper placement or timing of the specific 1×N building block. Consequently, using the generated behavioral model may also help protect the intellectual property described in the gate-level netlist because the gate-level details are not directly disclosed by the RTL listing. In other words, a hardened or physically-realized design that uses this 1×N building block methodology may be converted to a softened, or RTL-level, design and transferred to another party with less risk of exposing physical details, which may be sensitive or proprietary in nature. Generating an RTL-level design from a physically-realized design may not necessarily be limited to 1×N building blocks. 1×N compiler 406 may generate an RTL-level design from other types of hierarchical RTL elements. In other words, the 1×N methodology described herein may provide an automated closed-loop approach that may used to create RTL-level or behavioral-level design for numerous other RTL elements.
Iterative Synthesis Cycle
To illustrate in more detail the iterative synthesis cycle, we move to
The RTL no-touch feature may comprise a software routine of a VLSI design application. For example, RTL no-touch software may comprise a set of instructions that guides a synthesis engine, such as synthesis tool 448, preventing the engine from synthesizing a set of RTL statements. Preventing the synthesis engine from synthesizing a set of RTL statements may be helpful when the RTL for a specific section of a design has already been optimized. For example, the RTL for two sections of a design may have been optimized by some tool or by human intervention. The designer may want the two sections to remain unaltered in subsequent iterations of the synthesis engine. One may contrast the RTL no-touch feature with conventional approaches, where the synthesis engine of the conventional approaches would integrate the gate-level entities within the RTL, alter the generic nature of the RTL, and make the design technology dependent.
Various embodiments may provide an RTL no-touch feature by allowing specific sets of RTL constructs to be designated as having been previously implemented and optimized as gate-level netlists. For example, a circuit design may have twenty-five different 1×N building blocks. A circuit designer may have synthesized the circuit and tuned a portion of the circuit having ten 1×N building blocks. The circuit designer may want to add some additional circuit functions, or otherwise modify the circuit design at the behavioral level, using Verilog HDL. The circuit designer may designate the ten 1×N building blocks that have been tuned as no-touch blocks. As a consequence, any subsequent automated optimizations performed on the circuit design may tune or alter the other fifteen 1×N building blocks and the newly added circuit functions but make no more tuning or optimization changes to the ten previously tuned building blocks.
Various embodiments may implement the RTL no-touch feature by maintaining the gate-level netlists for the no-touch building blocks (element 444) separate from the behavioral level design. The embodiments may maintain separate gate-level netlists and behavioral lists to the building blocks as long as both the gate-level netlists and behavioral lists are proven and maintained to be logically equivalent, such as by using industry-available tools. The RTL no-touch feature may not be limited to 1×N building blocks. Many embodiments may implement the RTL no-touch feature for both 1×N building blocks and other types of hierarchical cells and circuit elements in a circuit design. Using the RTL no-touch feature for other types of circuit elements may allow a designer to tune one or more parts of a circuit design, which may contain both 1×N building blocks and non-1×N elements, and prevent such tuning parameters from being erased or overwritten during subsequent tuning or optimization for other portions of the circuit design. Referring to
In at least one embodiment, the RTL no-touch feature may eliminate the need for disrupting the RTL-only design environment with gate-level implementation details. The 1×N compiler may be configured to avoid generating RTL-level code for the no-touch building blocks. Preventing the generation of the RTL-level code may enable the embodiment to help protect proprietary design techniques, as well as maintain a technology-independent netlist.
Each netlist in the RTL no-touch gate-level netlist database (element 444) may have a one-to-one correspondence to a corresponding element in the behavioral RTL (element 430). The RTL no-touch gate-level netlist database (element 444) may be constructed by selective output extraction of synthesis tool 448, manual intervention (element 442), or another type of automated means. The RTL no-touch file (element 446) may designate which behavioral RTL constructs (element 430) should be replaced by the gate-level netlist counterparts. Further, the RTL no-touch file (element 446) may also specify that synthesis tool 448 should avoid further manipulation of the replaced gate-level netlist counterparts. Avoiding further manipulation of the replaced gate-level netlist counterparts may be beneficial, because the synthesis tool 448 may optimize the other gate-level constructs for better overall design performance without disturbing the previously optimized netlists. Synthesis tool 448 may then generate or create the composite design netlist (element 426), which may include the RTL no-touch gate-level constructs.
By employing a 1×N design methodology, an IC design application like VLSI design application 145 may maintain the results of optimizations of 1×N building blocks, including changes related to DFM alterations, through a process of back-annotation. With back-annotation, a circuit designer may also perform automated optimizations of the design. In many embodiments, the circuit designer may perform the automated optimizations normally, such as the designer would in a traditional design flow. Performing the automated optimizations in a traditional manner may allow a system employing 1×N building blocks to decouple the 1×N building blocks from the tool-suite of the system. Referring back to
A premise of back-annotation may be the detection and description of optimizations via 1×N building blocks. An embodiment may perform an optimization on a design and make changes to the netlist based on the optimization results. The back-annotation feature may allow the embodiment to detect the netlist changes and then describe or create updates to the 1×N building blocks corresponding to the netlist changes.
Back-annotator 424 may read two netlists. In
Since the optimizations made to the elements in the netlists are decoupled from the 1×N building blocks, back annotation for 1×N building blocks may allow an embodiment to support numerous optimization techniques, such as optimization techniques for timing, power, or area. Additionally, an embodiment may have the capability to disable one or more optimization tools or optimization features via synthesis tool 448 or back annotator 424. The quality of the starting netlist or "seed" may determine the output quality and amount of time required for automated optimization routines. Consequently, the use of iterative cycles of synthesis and back annotation may improve runtimes and result in better-optimized designs.
Back-annotator 424 may be extendable and programmed to selectively accept or ignore a specified set of changes to a specific list of 1×N building blocks. An embodiment may program back-annotator 424 to selectively accept or ignore the specified set of changes through a list of directives, which may be similar to the use of directives by existing synthesis tools. For example, if an embodiment needs a specific 1×N bit-ordering to meet a routing requirement, the embodiment may disable placement updates by fixing cell locations in the netlist or by providing back-annotator 424 with a list of 1×N building blocks for which the placement updates should be ignored. Further, depending on the embodiment, the user may be able to select the method used for optimization-exclusion. If the tool suite in an embodiment supports optimization-exclusion, the embodiment may allow a user to configure the optimization-exclusion via synthesis tool 448. However, in another embodiment that does not support optimization-exclusion, or if the optimization-exclusion is difficult or cumbersome to use, the embodiment may allow the user to configure the optimization-exclusions via back-annotator 424.
In many embodiments, synthesis tool 448 may be hierarchy-aware. In other words, synthesis tool 448 may be configured to recognize and work with hierarchical cell elements. For embodiments that have a hierarchy-aware synthesis tool 448, 1×N building block 422 may be represented as hierarchical elements, e.g., traditional hierarchical elements. Synthesis tool 448 may manipulate the hierarchical elements to produce an optimized design. For embodiments that have hierarchy-aware synthesis tool 448, the embodiments may need to perform the timing improvements or timing optimizations using the individual gates within the hierarchical elements so that timing rules such as New Delay Rules (NDRs) are not required for each individual 1×N building block 422. Otherwise, an embodiment may need to update 1×N compiler 428 to generate NDRs for each 1×N building block 422.
In many embodiments, optimizations made to 1×N building blocks may be captured via back-annotation by back-annotator 424. Placement changes allowed on a hierarchical 1×N building block 422 may be used in the physical design phase for floorplanning updates. Because the results of synthesis and automated optimization routines may largely depend on the initial quality of the netlist, or starting seed, maintaining optimizations for 1×N building blocks through back-annotation may result in a better quality synthesis result through successive iterations.
As illustrated above for embodiments that do not have hierarchy-aware tools, the embodiments may flatten the 1×N building blocks before performing the optimizations. For example, many embodiments may generate numerous DFM alterations via structures defined by a flat netlist. Embodiments that flatten the 1×N building blocks before performing the optimizations may detect and capture changes to the 1×N building blocks via back-annotation. However, flattening the design may eliminate the hierarchy established to maintain 1×N building blocks as individually tunable elements in the separate design phases. To address the eliminated hierarchy, various embodiments may recreate the hierarchy through a reassembly process.
Reassembler 432 may comprise a software module or other type of module for 1×N compilation 420 that uses netlist attributes created by 1×N compiler 428 to recreate the hierarchical design. Reassembler 432 may also comprise, e.g., reassembler 335 depicted in flowchart 300, or reassembler 175 of VLSI design application 145 shown in
Reassembler 432 may detect changes to 1×N building blocks, such as 1×N building block 422, via back-annotation. However, because the netlist may have been flattened, the changes may not be directly applied back to the hierarchical RTL and physical design netlists. Reassembler 432 may discern the hierarchical boundaries of the flattened netlist. Plus, reassembler 432 may be configured to apply the updates for the 1×N building block 422 back to the respective hierarchical physical design netlist or RTL netlist without manual intervention.
For example, reassembler 432 may use attributes created by 1×N compiler 428, which are present in the flattened netlist, to recreate the hierarchical design. The flow process for recreating the hierarchical design via attributes of the netlist is illustrated in
Iterative Physical Design Cycle
The physical design phase may comprise the part of the design process that captures or generates the physical attributes of the circuit design. For example, a VLSI design application may capture the physical attributes related to floor planning, cell and 1×N building block placement, routing between the cells/blocks, noise reduction, power bussing, and design rule checking, as just a few examples. Embodiments that employ only classical design methodologies generally lose many of the changes made during the physical design phase due to the iterations through the logic and/or synthesis design phases.
An embodiment employing a 1×N design methodology may automatically maintain changes made to the 1×N building blocks during the physical design phase via the mechanisms of back-annotation and reassembly.
One flow of an iterative physical design stage may comprise reading different 1×N building blocks from a netlist of physical design 468. Depending on the type of netlist (element 452), an embodiment may reassemble the netlist via reassembler 462 and/or perform back-annotation via back-annotator 454 for the individual 1×N building blocks, such as 1×N building block 456. Embodiments may employ 1×N compiler 458 to compile the reassembled and back-annotated 1×N building blocks to generate physical design view 460.
An embodiment employing a 1×N design methodology may leverage the hierarchical nature of a physical design to make many physical design tasks more efficient through the use of scripting. For example, if an integrator wants to change the relative spacing of the leaf cells in 1×N building block 456, the embodiment employing the 1×N design methodology may not require the integrator to move each individual cell manually. Instead, the embodiment may allow the integrator to update 1×N building block 456 to reflect the desired spacing. The embodiment may then allow the integrator to recompile the design via 1×N compiler 458 and re-read the relative spacing changes into the design. The hierarchical 1×N building block 456 may be rewired on-the-fly, such as when the integrator is working on the design in physical design phase 240, so that the spacing changes are ready to use once the design is re-read. Subsequently, the integrator may resolve any potential overlaps between the 1×N building block and other random-logic cells and re-route the hierarchical connections.
An embodiment may make physical design tasks more efficient through the use of scripting for numerous types of transformations. For example, various embodiments may use scripting for relative placement of cells within 1×N building blocks, relative spacing of leaf cells, bit ordering, changes of cell types used in 1×N building blocks, and DFM/redundancy-for-test improved manufacturability implementations.
Embodiments employing dynamic updates to 1×N building blocks, such as 1×N building block 456, may not need to rely on pre-compiled sub-blocks that can be tiled together. Instead, 1×N compiler 458 may interpret the underlying physical structure of each cell and rewire 1×N building block 456 according to the cell placements described in 1×N building block 456. Interpreting the underlying physical structure and rewiring 1×N building block 456 may reduce turn-around-time for design optimizations and provide the designer or integrator with more physical detail information through each design phase.
Iterative Timing Cycle
Due to the nature of classical timing analysis tools, designers typically perform the timing design phase using flattened designs. Based on the results of the timing analyses, a designer may manually update the design to meet timing goals. Alternatively, the timing tool may also apply updates to the design. In other words, the timing tools may use various methods to communicate the recommended changes or updates and have the updates physically implemented in the design. Embodiments employing a 1×N design methodology may update 1×N building blocks in at least two ways. A first method may comprise updating 1×N building blocks through reassembly and back-annotation, whereby the embodiment recognizes design changes and feeds the changes or alterations back to other stages in the methodology. A second method may comprise incorporating the changes via on-the-fly editing and recompilation of 1×N building blocks. This secondary method may allow for more accurate timing information in a rapid fashion via scripting from a 1×N compiler.
In a classical design flow, the timing team may make changes to the abstract or higher-level design, communicate the changes to the physical design team, and wait until the physical design team has incorporated the changes into the physical design. This interaction between the timing team and physical design team may be relatively slow in that the updates may need to be placed and routed before the updates can be analyzed in a timing analysis. Implementing the updates via placement and routing may require days. Once the physical design is ready to be analyzed for timing performance, the timing tool may take hours or days to produce the timing data for the designer depending on the complexity of the design.
Changing 1×N building block 476 may not provide completely accurate timing results in some instances, because changes to 1×N building block 476 may affect other circuit elements, such as random logic gates. However, incorporating changes from a timing analysis using a 1×N design methodology may provide a greater degree of accuracy than a designer not using capabilities provided by a 1×N design methodology. Consequently, the designer may use the 1×N design methodology to reduce the time needed to update the physical design and meet timing goals, resulting in a quicker turnaround time for the design.
Script 480 generated from recompilation may not be limited to use in the timing design phase, nor to a specific set of transformations. Rather, 1×N compiler 478 may be configured to work with various tool sets for other phases of the design methodology and other desired transformations. For example, 1×N compiler 478 may be configured to work with placement and routing tools, DFM tools, design-rule checking tools, simulation tools, timing analysis tools, and other tools used in the logic, synthesis, physical design, and timing phases. Embodiments employing a 1×N building block methodology may provide the necessary design information for the various transformations through reassembly, back-annotation, and uniquification. Some embodiments may employ scripts for adding new 1×N building blocks to a design. Some embodiments may employ scripts for changing internal cell placement, internal rewiring, rewiring pins of a 1×N building block, and/or changing the functions for 1×N building blocks. Even further embodiments may employ scripts to delete specific 1×N building blocks from a design or remove internal cells of designated 1×N building blocks. As one skilled in the art will appreciate, scripts for 1×N building blocks may be used in a variety of different ways for a variety of different purposes. The example uses just cited are only a few of the possible uses.
1×N compiler 700 may use information related to the logical structure, placement, and physical structure of the components inside 1×N building block 748 to select and apply one or more DFM alterations. Using the information, 1×N compiler 700 may make both yield and electrical behavior enhancements to cells of 1×N building blocks of physical design representation 746. 1×N compiler 700 may make the DFM alterations by determining which portions of cell-to-cell interface edges for 1×N building blocks of physical design representation 746 may be modified, based on such considerations as relative placement of the cells, cell-to-cell connectivity, cell-types, and shapes inside the layouts of the cells.
1×N compiler 700 may apply DFM alterations to 1×N building blocks of physical design representation 746 by using a cell examiner 705, a DFM selector 710, and a DFM applicator 715. Cell examiner 705 may examine two adjacent cells of 1×N building block 748 to determine which portions of cell-to-cell interface edges may be modified based on one or more relationships between the cells. For example, cell examiner 705 may examine cell 667 and cell 668, which are adjacent cells of 1×N building block 660 in
As mentioned, cell examiner 705 may examine both cell 667 and cell 668 to determine one or more relationships between the cells. For example, cell examiner 705 may determine the relative placement of the cells, such as the location of cells 667 and 668 in relation to the other cells of 1×N building block 660. As depicted in
Cell examiner 705 may also examine two adjacent cells to determine a cell-to-cell connectivity or an associative connection relationship. For example, cell examiner 705 may determine that the two cells share a common clock signal. Even further, cell examiner 705 may examine shapes within each of the cells, such as shapes that may be presented in cell layout views, for opportunities of DFM alterations. Based on the determined relationship(s), DFM selector 710 may select one or more DFM alterations that DFM applicator 710 may apply to the cells of 1×N building blocks in physical design representation 746.
DFM alterations selected and applied via 1×N compiler 700 may differ from conventional approaches which have used shape-based manipulation. 1×N compiler 700 may make DFM alterations based on connectivity, cell-type, and relative cell placement information. DFM selector 710 may select from a variety of different types of DFM alterations. For example, some of the different types of DFM alterations that DFM selector 710 may select to apply are: adding polysilicon or metal wires that create a multi-layer connection redundancy, adding wire/via redundancy on metal/via layers, merging diffusion areas to increase capacitance on supply nodes, merging N-well/substrate contact areas to create larger islands, enhancing implant coverage over gates, diffusion or field poly areas, merging small metal features into a larger metal feature to mitigate minimum-metal-area problems, merging shapes to improve pattern density, and adding polysilicon shapes to improve polysilicon pattern uniformity and gate length control.
To illustrate a process that 1×N compiler 700 may perform when selecting and making DFM alterations to cells of 1×N building blocks, we may examine
In generating the physical placement of the cells (element 761), 1×N compilation 760 may define the cell connectivity and cell placements. As part of 1×N compilation 760, cell examiner 705 of 1×N compiler 700 may iterate through each cell instance (element 762) in 1×N building block 748 to determine which cells inside 1×N building block 748 are adjacent to which cells. For example, cell examiner 705 may first determine that cells 667 and 668 are adjacent. Cell examiner 705 may then determine that cell 668 is adjacent to cells 667 and 669. Cell examiner 705 may then determine that cell 669 is adjacent to cells 668 and 670, and so on.
If cell examiner 705 determines that an edge of a cell has another cell adjacent to it (element 768), cell examiner 705 may perform a lookup of the cell-types of the two cells, via a lookup table 752 to determine whether the cells are suitably alike, such as being the same or substantially similar (element 770). If cell examiner 705 determines the cells are substantially similar, cell examiner 705 may add the substantial similarity relationship to a property list 754 for the cell. If the two cells are substantially similar, then cell examiner 705 may check the edges of the cells to determine whether there is an associative connection between the two cells in the direction of the shared edge (element 772). If cell examiner 705 determines that an associative connection exists between the two cells by matching an established criterion in lookup table 752, such as both cells sharing a common input signal, then cell examiner 705 may add the associative connection relationship to property list 754 for the cell (element 774).
After cell examiner 705 evaluates all instances (element 762) and instance edges (element 764), and accumulates relationships (element 778) for each cell in property list 754, cell examiner 705 may annotate shared edge/connectivity property list 754 onto 1×N building block 748, in physical design representation 746. A downstream layout tool 780 may open physical design representation 746 and enable a module, such as DFM applicator 715, to read property list 754. DFM applicator 715 may read property list 754, which may comprise an annotated shared-edge/connectivity property list (SECPL), and take one of a variety of different actions for each cell that is annotated by the SECPL (element 781). For example, DFM applicator 715 may select an overlay cell, or overlay cells, from overlay/layout cells 750 to be placed on top of each cell being altered of 1×N building block 748. DFM applicator 715 may also select a programmable overlay cell from overlay/layout cells 750 to be placed on top of each cell and then program the overlay cell. Further, DFM applicator 715 may replace the original cell with a parameterized layout cell from overlay/layout cells 750 and then program the new cell.
The different representation forms generated by 1×N compiler 700 may be used in the respective design phases, such as the design phases illustrated in
Regenerating the behavioral RTL view may comprise either recreating 1×N building blocks via a block builder for sweeping changes, or manually editing 1×N building blocks for minor changes. Worth emphasizing, each iteration through a design cycle, be it a primary or secondary loop, may involve going through a 1×N compilation phase, such as 1×N compilation 260, even if no 1×N building blocks have been altered. For example, such recompilation may allow 1×N compilation phase 260 to check for DFM alterations of 1×N building block cells and update the various representations accordingly. If no DFM alterations to cells are found, no updates may be required.
1×N compiler 700 may convert the information of 1×N building blocks in one representation form to another representation form. 1×N compiler 700 may convert the information of 1×N building block 748 of physical design representation 746 to a 1×N building block in behavioral representation 742 and/or a 1×N building block in logical representation 744. The information of 1×N building blocks in the various representations may comprise, e.g., 1×N building block elements, arrangement of the elements, connectivity information, hierarchical global wiring avoidance information, parameters, and DFM improvement information.
The different representation forms of circuit design 740 may vary from embodiment to embodiment, as well as within an embodiment. Behavioral representation 742 may comprise a high-level description of circuit design 740. For example, behavioral representation 742 may comprise one or more types of HDL code, behavioral RTL descriptions, user-configurable text files, C-language code, RTL netlists, or other high-level elements that describe various circuit devices, including one or more 1×N building blocks, cells, and/or hierarchical cells/macros.
Logical representation 744 may comprise a gate-level description of circuit design 740. For example, logical representation 744 may describe an alternative form of circuit design 740, having such components and/or elements as AND gates, OR gates, NAND gates, and NOR gates, one or more 1×N building blocks, and a mixture of other high-level macrocell components, such as adders, arithmetic logic units, multiplexers, and register-files.
Physical design representation 746 may comprise a low-level description of circuit design 740. For example, physical design representation 746 may describe an alternative form of circuit design 740, having such components and/or elements as nodes, wires, resistors, capacitors, inductors, contacts, poly, diffusion, many of which may have associated placement and dimensional data. Depending on the embodiment, physical design representation 746 may also comprise hierarchical information, such as hierarchical information of cells and 1×N building blocks. In other words, physical design representation 746 may comprise a PD netlist and/or a flattened netlist. Worth emphasizing, 1×N building blocks of physical design representation 746 may comprise collections of circuit elements associated with 1×N building blocks behavioral representation 742 and logical representation 744, wherein the circuit elements of physical design representation 746 may be represented in a flattened netlist or partially flattened netlist.
During the design process, the circuit designer may use one or more tools of tool suite 720. For example, tool suite 720 may comprise a variety of synthesis and performance optimization tools, such as tools 190 in
The integrated circuit designer may have to repeatedly and iteratively use one or more of the tools of tool suite 720 before developing a final physical design representation 746 that may be fabricated. For example, the designer may use one or more logic design tools 722 that work in conjunction with 1×N compiler 700 to create 1×N building blocks in behavioral representation 742. Logic design tools 722 may comprise, e.g., cell editors, 1×N building block editors, RTL editors, and other high-level circuit design applications.
The designer may use one or more synthesis tools 724 to create logical representation 744 from behavioral representation 742. One or more of synthesis tools 724 may work in conjunction with 1×N compiler 700 when creating 1×N building blocks for logical representation 744. The designer may then analyze and/or optimize the design via one or more logic design tools 722. For example, the designer may simulate the operation of groups of elements, cells, and 1×N building blocks of logical representation 744, such as applying various sequences of bit patterns to verify that logical representation 744 behaves in a similar or equivalent fashion as behavioral representation 742 behaves. Additionally the designer may use one or more timing analysis tools 730 with logical design tools 722. For example, the designer may verify that signals propagate through sections of the circuit in required time intervals and that drive strengths are sufficient for implemented fan-outs.
The circuit designer may use physical design tools 726, which may work in conjunction with 1×N compiler 700, to generate physical representation 746, which includes 1×N building blocks, from logical representation 744. Similar to the other iterative closed loops encountered when generating behavioral representation 742 and logical representation 744, the designer may need to make numerous changes to elements of physical design representation 746 due to results of physical design tools 726 and timing analysis tools 730. For example, the designer may discover that a routing tool cannot create a functional wiring arrangement for the design, due to rule restrictions, area constraints, and other problems encountered by physical design tools 726. Alternatively, one or more optimization tools may generate changes to circuit design 740, such as by relocating elements, selecting different pins of different cells and/or 1×N building blocks, increasing gate drive strengths, rearranging cells of 1×N building blocks, making numerous DFM alterations, and making other types of alterations to other elements of physical design representation 746. Consequently, the designer may use 1×N compiler 700 to generate updated representations of the altered 1×N building blocks for behavioral representation 742, the altered 1×N building blocks for logical representation 744, and the altered 1×N building blocks of physical design representation 746.
One or more elements of 1×N compiler 700 may be in the form of hardware, software, or a combination of both hardware and software. For example, in one embodiment, one or more of the modules of 1×N compiler 700 may comprise software instructions of an application stored in a tangible medium, executed in memory by a processor of a computer. In other words, one embodiment of 1×N compiler 700 may comprise portions of stored code for an application, which may design integrated circuits using a closed-loop 1×N methodology, such as VLSI design application 145 shown in
In alternative embodiments, one or more of the modules of 1×N compiler 700 may comprise hardware-only modules. For example, in one embodiment 1×N compiler 700 may comprise a state machine that compiles different versions of netlists to generate the different forms of 1×N building blocks. A state machine 1×N compiler 700 may be desirable when, e.g., the designer needs to create the various representations in a rapid fashion, since a state machine compiler may be able to generate the representations considerably faster than a software-based compiler.
In some embodiments, cell examiner 705, DFM selector 710, and DFM applicator 715 may all reside in a single device, such as in memory 140 of computing system 100 shown in
The arrangement of 1×N compiler 700 may vary in different embodiments. Some embodiments may have different elements than those modules depicted in
In other embodiments, 1×N compiler 700 may include varying numbers of DFM selector 710, DFM applicator 715, and cell examiner 705. For example, one embodiment may have three DFM applicators, one adapted to use overlay cells, one adapted to use programmable overlay cells, and one adapted to use parameterized layout cells.
One may note further that the BP implant is butted at the cell boundaries (element 806) with a hole or notch surrounding the diffusion.
As illustrated by
Design process 910 may include using a variety of inputs; for example, inputs from library elements 930 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 (which may include test patterns and other testing information). Design process 910 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process 910 without deviating from the scope and spirit of the various embodiments.
The design structure is not limited to any specific design flow. Design process 910 preferably translates an embodiment of the invention as shown in
As illustrated in
The process may further involve DFM applicator 715 selecting an overlay cell, or overlay cells, from overlay/layout cells 750 to be placed on top of cells 668 and 669 to alter the physical implementation of the cells during fabrication (element 1030). In other situations, with other types of relationships, DFM applicator 715 may alternatively select programmable overlay cells from overlay/layout cells 750 to be placed on top of cells 668 and 669 and then program the overlay cells. In other situations, with other types of relationships, DFM applicator 715 may replace the cells 668 and 669 with parameterized layout cells from overlay/layout cells 750 and then program the new cells.
The process of flowchart 1000 may also include adding the relationship to a property list of a cell of the 1×N building block (element 1040). For example, DFM applicator 715 may add the common N-well relationship to property list 754. The process may continue by iteratively detecting relationships of adjacent cells and selecting additional DFM alterations based on the additionally detected relationships (element 1050) and adding the new relationships to property list 754. Referring back to
Having altered various elements of 1×N building block cells for DFM improvements, as well as potentially having other modified elements of the circuit, the circuit designer may use a 1×N compiler to generate or create behavioral, logical, and physical design representations that reflect the modified/altered circuit elements. Additionally, some DFM alterations may require back-annotation and reassembly of hierarchical elements, including hierarchical 1×N building blocks, in order to generate the behavioral, logical, and/or physical design representations. Flowchart 1000 of
Another embodiment is implemented as a program product for implementing systems and methods described with reference to
Furthermore, embodiments may take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purpose of describing the various embodiments, a computer-usable or computer readable medium may be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W), and DVD.
A data processing system suitable for storing and/or executing program code may include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code is retrieved from bulk storage during execution. Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers.
Those skilled in the art, having the benefit of this disclosure, will realize that the present disclosure contemplates making design-for-manufacturing changes to cells of 1×N building blocks via a closed-loop 1×N compiler. The form of the embodiments shown and described in the detailed description and the drawings should be taken merely as examples. The following claims are intended to be interpreted broadly to embrace all variations of the example embodiments disclosed.
Although the present disclosure and some of its advantages have been described in detail for some embodiments, one skilled in the art should understand that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Although specific embodiments may achieve multiple objectives, not every embodiment falling within the scope of the attached claims will achieve every objective. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from this disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
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|Approach for routing an integrated circuit
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|Method and system for deterministic control of an emulation
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|Intent-driven functional verification of digital designs
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|International Classification
|Cooperative Classification
|European Classification
|Sep 2, 2008
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION,NEW YO
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text:
Farewell Mr. Kringle Trailer (2010)
04 December 2010 Romance 88 mins
A skeptical journalist is assigned to chronicle the 50th anniversary of Kris Kringle, a Santa Claus in the town of Mistletoe. As her involvement in the town grows, she begins to open up to the enchantment of Christmas and some other wonders of the season.
Watch the official Farewell Mr. Kringle 2010 trailer in HD below or find more Farewell Mr. Kringle videos on Vidimovie.

subset: commoncrawl


text:
ILADS Lyme Disease Conference Streaming Video
Expand Messages
- Join us on Friday October 28th and Saturday October 29th to view streaming video of the The Twelfth Annual ILADS Lyme Disease Conference which is designed to foster collaboration and dialogue between Lyme disease researchers and those who care and advocate for Lyme disease patients in a variety of settings.
The conference will provide updates in clinical knowledge, treatment techniques and innovations in care. To view the entire conference program, click here.
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text:
I am the official cookie maker for all of his school celebrations and I always make my iced sugar cookies for every one. This year they got heart shaped sugar cookies, iced and decorated with piped x's and o's. If you would like a tutorial for how to ice sugar cookies like a pro check out this post.
For the teachers, I had bigger plans but as happens time fell short, so we decorated these cute tin mailboxes from the Target dollar spot with scrapbook paper and stickers. Then we filled them with some yummy Ghirardelli chocolates and Toblerone. I had wanted to make homemade goodies to put inside, but somehow I don't think they will mind.


text:
Some deregulation in proposals to amend Seveso Directive
Proposals to amend the 1996 EU Directive on major accident hazards were published by the European Commission in December.1 As expected, they cover mines and explosives sites, and make detailed changes to the rules covering petroleum installations and chemicals sites - with some of these likely to drop out of the Seveso regime. A response to the recent disaster in Toulouse has been put off for the time being.
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text:
Lucky Bums Moon Camp Chair
Lucky Bums Moon Camp Chair
from 39.99
Your little one can rest comfortably and easily wherever your adventures take you with the help of the Lucky Bums Youth Moon Camp Chair. This sturdy, portable papasan-style folding chair features a rugged, coated steel frame; a padded polyester seat; and embroidered Lucky Bums logo detail -- available in three vibrant colors. Perfect for use during camping trips, picnics, parades, parties, games and sporting events, backyard barbecues, and any other extended outdoor activity!
Available Colors: Green, Blue, Pink
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- The moon chair boasts a double-layer 600D Oxford with seat padding on a 13 mm coated steel frame delivering a sturdy, safe, and durable option for kids
- Easily packable in its carrying bag, this chair is ready to go camping or to go to the next sporting event
- Comfortable and safe


text:
Why does this have to be so hard and stressfull
View Single Post
April 20th, 2012, 05:59 AM
Waiting for our Miracle.
Join Date: Jul 2010
Location: Clarence, Pa
Posts: 5,106
Thank you ladies. Last night after I got home I had two ice cream sanswiches and drank abottle of cold water. He started to kick non stop. I agree with Lisa. I don't think Cody likes to be told what to do. I have been telling people this is the Cody show and he is the star. I am going to talk to my doctor on Tuesday and ask him if Cody continues to fail NSt scans if they will take him early. One thing we did fine out yesterday. Cody isn't breech any more. He is head down. I have another ultrasound on Tuesday.
Thank you Katie for my cute siggy.
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text:
Microsoft adding some of its new Windows Azure services to Windows Server 2012, to this end, the company back in July at the Worldwide Partner Conference--delivered a Community Technology Preview (CTP) test build of these Azure services for Windows Server. Today, Microsoft released the beta of those services.
These services are aimed at service providers and hosting partners. At some point Microsoft might expand the target audience to other customers, but for now, that's the core audience, Chris Van Wesep, Sr. Product Manager said.
"These technologies are not something incremental that needs to be purchased by hosters. This is simply part of the broad solution you tap into when you deploy Windows Server 2012 and System Center 2012," Van Wesep adds.
The versions of these services, which include virtual machine hosting and Web-site hosting for Windows Server along with the System Center 2012 Service Pack 1, is planned for early 2013 release.
Below is a short list of many of the top enhancements coming with this feature complete release:
"Service Management Portal & API
- Distributed install
- of the Service Management Portal and API (datacenter readiness)
- of the Web Sites controller separate from the Service Management Portal and API
- Users are now able to sign up for multiple plans
Web Sites
- HTTPS/SSL support - tenants are now able to upload custom certificates and use them for programmatic access
- Distributed installation with High Availability and Live Upgrade
- Generic FastCGI and custom stack support
Virtual Machines
- Custom create from VM Template with a rich wizard experience
- Create VM from VHD using hardware profile
- Tenants are now VMM Tenant Admins and utilize the new VMM On-behalf Of features," the official informs.
Also, Windows Azure Service Bus is now part of the new Windows Azure portal. In addition to existing features that enable you to manage Service Bus entities, "we are introducing new portal features with the October 2012 release of the Service Bus," the Azure team posted.
The new features include:
- Usage visualization of Service Bus queues topics and subscriptions,
- Entity status updates, and,
- Dashboards for monitoring queues and topics.
Microsoft notes that going forward, they'll be enriching "story for better management, monitoring and diagnostics of Service Bus entities by adding more features include: ""a namespace dashboard for aggregated views, a dashboard for subscriptions on every topic, additional metrics, the ability to update entity properties, and more."
Also, "the current Silverlight-based Portal will continue to work side-by-side with the new portal," the team said. "It is now in maintenance mode, so we won't be adding any new features. However, any changes you make to your Service Bus entities will be reflected in both places," the team adds.


text:
Upotte!! Episode 1 English Subbed
You are watching Upotte!! Episode 1 English Subbed from the Upotte!! Anime Show. Watch or Download Upotte!! Episode 1 MP4 English Sub and other episodes of Upotte!! Streamed for Free.
"Grip and Hold!"
Stream Upotte!! Episode 1
Episode Summary: A Japanese man travels to Seishou Academy to begin his new job as a modern lit teacher. He soon learns that all the students are this school are anthropomorphic assault rifles trained to perfect their weaponry, and he soon finds himself hospitalized after getting on the wrong side of FN-FNC rifle, Funco.


text:
Seniorsunited-vic.info was registered on Go Daddy on 05 April 2016. The site just started on social networks. It has
The site is hosted in Australia. The webmasters of the website can be contacted at . The domain for the website was purchased through Go Daddy on 05 April 2016 (1 year ago) and will expire in 7 months 21 days.
Domain Name: SENIORSUNITED-VIC.INFO Domain ID: D503300000007644747-LRMS WHOIS Server: Referral URL: Updated Date: 2016-04-05T08:36:07Z Creation Date: 2016-04-05T06:42:30Z Registry Expiry Date: 2017-04-05T06:42:30Z Sponsoring Registrar: GoDaddy.com, LLC Sponsoring Registrar IANA ID: 146 Domain Status: clientDeleteProhibited Status: clientRenewProhibited Status: clientTransferProhibited Status: clientUpdateProhibited Status: serverTransferProhibited ID: CR236606706 Registrant Name: Registrant Organization: Registrant Street: PO Box 5129 Registrant City: Frankston South Registrant State/Province: Victoria Registrant Postal Code: 3199 Registrant Country: AU Registrant Phone: +61.70078371 Registrant Phone Ext: Registrant Fax: Registrant Fax Ext: Registrant Email: Admin ID: CR236606709 Admin Name: Admin Organization: Admin Street: PO Box 5129 Admin City: Frankston South Admin State/Province: Victoria Admin Postal Code: 3199 Admin Country: AU Admin Phone: +61.70078371 Admin Phone Ext: Admin Fax: Admin Fax Ext: Admin Email: Tech ID: CR236606707 Tech Name: Tech Organization: Tech Street: PO Box 5129 Tech City: Frankston South Tech State/Province: Victoria Tech Postal Code: 3199 Tech Country: AU Tech Phone: +61.70078371 Tech Phone Ext: Tech Fax: Tech Fax Ext: Tech Email: Billing ID: CR236606711 Billing Name: Billing Organization: Billing Street: PO Box 5129 Billing City: Frankston South Billing State/Province: Victoria Billing Postal Code: 3199 Billing Country: AU Billing Phone: +61.70078371 Billing Phone Ext: Billing Fax: Billing Fax Ext: Billing Email: Name Server: BNS1.VENTRAIP.NET.AU Name Server: BNS2.VENTRAIP.NET.AU DNSSEC: unsigned "For more information on Whois status codes, please visit Access to AFILIAS WHOIS information is provided to assist persons in determining the contents of a domain name registration record in the Afilias registry database. The data in this record is provided by Afilias Limited for informational purposes only, and Afilias does not guarantee its accuracy. This service is intended only for query-based access. You agree that you will use this data only for lawful purposes and that, under no circumstances will you use this data to(a) allow, enable, or otherwise support the transmission by e-mail, telephone, or facsimile of mass unsolicited, commercial advertising or solicitations to entities other than the data recipient's own existing customers; or (b) enable high volume, automated, electronic processes that send queries or data to the systems of Registry Operator, a Registrar, or Afilias except as reasonably necessary to register domain names or modify existing registrations. All rights reserved. Afilias reserves the right to modify these terms at any time. By submitting this query, you agree to abide by this policy.
|Tue, 12 Jul 2016 01:20:51 GMT
|text/html; charset=utf-8


text:
London, May 28 (ANI): The scandal surrounding Silvio Berlusconi's friendship with an 18-year-old aspiring model has started a new guessing game in Italy over its authenticity. His wife, however, is not happy with the news and has, infact, announced intentions of divorcing him in a newspaper.
But, Berlusconi is not alone. His kids are standing by him.
The Italian Prime minister's failure to explain his friendship with Noemi Letizia has hit his normally sky-high approval ratings, according to private polls.
As he prepared to mount a television campaign to boost his flagging popularity, Berlusconi was stung by an opposition leader who questioned his family values, reports The Times.
Dario Franceschini, the leader of the Democratic Party, said: "To the Italians, I want to ask a question: would you want your children brought up by this man?"
Marina Berlusconi, the Prime Minister's oldest child and an executive in his media empire, retorted: "I would be thrilled for Franceschini's children if they had a father like mine."
Barbara, Eleonora and Luigi - the children from Berlusconi's second marriage - also stood by their father.
"We were brought up in a sensible family environment rich in values," they said.
Meanwhile, Letizia had earlier claimed that Berlusconi would launch her into a career in politics.
Letizia, who affectionately calls Berlusconi "Papi", came under media glare after Veronica Lario, the Italian leader's wife, announced their divorce with the words, "I cannot be with a man who spends time with under-age women".
The buzz started that Belusconi had attended the teenager's 18th birthday party, presenting her with a gold and diamond necklace.
However, in an earlier interview, Letizia denied having an "inappropriate relationship" with Berlusconi. (ANI)