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a. These Booking Terms and Conditions apply to the booking of the Jump Inc Experience (the 'Activities") and any ancillary products at the location set out in Jump Inc's booking confirmation.
b. These Booking Terms and Conditions contain important information concerning participation by you and members of your party and, accordingly, you acknowledge and agree that you shall ensure that all members of your party are aware of and accept these Booking Terms and Conditions.
c. No variation to these Booking Terms and Conditions shall be binding unless agreed in writing by Jump Inc.
d. Any typographical clerical or other error or omission in any booking confirmation or other documentation issued by Jump Inc (including any electronic documentation) shall be subject to correction without any liability on the part of Jump Inc. Jump Inc reserves the right to make changes to the Activities whether to conform with any applicable safety or other statutory requirements or otherwise.
a. No booking shall be deemed to have been accepted unless accepted in writing by Jump Inc (which shall include Jump Inc's email confirmation of booking).
b. These Booking Terms and Conditions incorporate Jump Inc Privacy Policy and Disclaimer.
c. You must advise Jump Inc as soon as possible of any mistake in Jump Inc booking confirmation. Jump Inc shall use its reasonable endeavours to ensure that you and your party's participation commences at the time booked and it shall be the responsibility of each participant to ensure that they arrive in sufficient time. Late arrivals may not be permitted to undertake the Activities and no refunds or compensation will be payable in such circumstances.
a. The Activities comprise a challenging trampoline activities and participation is not without risk as a fall could be fatal. All participants will receive a safety brief.
b. Jump Inc reserves the right to refuse admittance to the Activities or to remove a participant from the Activities should it deem it necessary to do so. This includes a participant who does not comply with the safety rules and advice and the safety system or who is deemed to be under the influence of alcohol or drugs.
c. After the safety briefing participants will not be directly supervised by an instructor.
d. All participants must be reasonably fit and healthy and must weigh less than 18 stones/130kg.
If you have any concerns we advise that you visit a site at a time prior to your booking and speak to a member of the Jump Inc staff. Anyone who does not meet these requirements will not be allowed to undertake the Activities. It is your responsibility to ensure that all members of your party meet these requirements.
All participants aged 5 and under* must be accompanied by a participating person aged 14 or above. Prices are on a per person basis and are not depending on age.
*Please note, due to the nature of the equipment at Jump Inc Sheffield (Meadowhall), we are unable to take bookings for children 5 and under.
e. All participants are required to wear Jump Inc Grip Socks for grip and hygiene.
f. The Activities are physically demanding and require a degree of agility, strength and stamina. Participants are advised to jump within their ability – only the individual knows or understands their own limits and competencies. If you are unsure of whether you can complete a manoeuvre, you should not attempt it If participants have medical concerns they are advised to consult their doctor in advance. Participants will be required to certify that they do not suffer from any medical condition which would make it more likely that they would be involved in any incident which could result in injury to themselves or others. Due to the physical nature of the Activities Jump Inc recommends that pregnant women should not take part. Pregnant women who still wish to undertake the activities will be required to sign a disclaimer confirming that they are aware that there are risks to them and to their unborn child and that participation in the Activities is at their own risk.
g. Participants need to be able to see similar distances to those required to drive a car in order to be able to complete the activity and to supervise any under 18's in their care. Consequently, short or long sighted participants must ensure that they wear contact lenses or prescribed glasses.
h. All participants are required to act responsibly and courteously at all times and to respect other participants. Jump Inc shall be entitled to prevent any person from undertaking or completing the Activities in the event it deems the behaviour of any participant unsuitable.
i. Participants must be dressed appropriately (see clause 4) and Jump Inc reserves the right to refuse admittance to the Activities to any participant who is not appropriately dressed.
j. No refunds or compensation will be payable by Jump Inc in the event that any participant is not permitted to, or decides not to, undertake or complete the Activities for the reasons set out in this clause.
k. All participants age 11 and under must be accompanied in our parks by an adult for the duration of their visit. The adult does not have to take part in activities but must be present in the building, unless the participant is aged 5 or under, in which case the adult must be a paying participant and supervise the age 5 or under on the park. (Please note, there is an age restriction at our Sheffield park. All participants must be age 6 or over.)
a. It shall be the responsibility of all participants to ensure that they are dressed appropriately and Jump Inc advises participants to wear clothing appropriate for the activity and which they do not mind getting damaged. In particular the following restrictions shall apply:
i. Participants must wear Jump Inc Grip Socks for grip and hygiene
ii. Long hair must be tied back
iii. No belts, jewellery or other sharp items of clothing that may cause damage to yourself, the equipment or other participants.
b. Jump Inc will not be responsible for any damage to or loss of clothing or other personal items of persons resulting from participation in the Activities.
a. You shall be entitled to cancel your booking subject to Jump Inc receiving your request for cancellation at least 48 hours before the booked start time. Any requests for cancellation must be made by telephoning the booking line: 0330 0882267. You shall be entitled to a full refund in the event of cancellation under this clause.
b. Jump Inc shall be entitled to cancel your booking at any time. In the event that Jump Inc decides to cancel your booking it shall use its reasonable endeavours to notify you as soon as possible. You shall be entitled to a full refund in the event of cancellation under this clause but no other compensation shall be payable.
c. In the event that it proves necessary to close the Activities for reasons beyond the control of Jump Inc and in circumstances where your party has commenced participation in the Activities, you shall not be entitled to any refund (in part or in whole). In such circumstances Jump Inc may, but shall not be obliged to, offer alternative dates or times at reduced rates.
a. Subject to any terms agreed in writing between Jump Inc and you, our charges shall be calculated at our current rates and payment in full shall be due at the time of booking. The charges include the cost of purchasing the Activities. Payment may be made by debit or credit card either on line or by contacting the booking line: 0330 0882267.
a. Payments made by debit or credit card will be refunded to the same card or, if the card has subsequently expired, by cheque. Payments made by Gift Voucher will be refunded by the issuing of a replacement Gift Voucher to the same value.
b. Where multiple forms of payment are used, Jump Inc reserves the right to refund any monies due on a refund or amendment by credit or cheque.
c. Any amendments to a party booking must be made 7 days prior to the date of the booking.
a. Except as otherwise provided in these Booking Terms and Conditions Jump Inc shall not be responsible for the loss, or damage, of or to any property or to any person arising from the booking of or participation in the Activities.
b. Parking facilities are available at the site, and any vehicles are left at the owners' risk and subject to any conditions and the payment of any fees as may be required by the provider of such facilities at the site location.
c. Except as otherwise provided in these Booking Terms and Conditions any liability of Jump Inc shall be limited to the refund of any charges paid to Jump Inc.
d. Nothing contained in these Booking Terms and Conditions is intended to nor shall limit the liability of Jump Inc in respect of death or personal injury caused by the negligence of Jump Inc or of its employees, agents or contractors.
a. If any of these terms are determined to be illegal invalid or otherwise unenforceable it shall be severed and deleted from these terms and the remaining terms shall survive, remain in full force and continue to be binding and enforceable.
b. Nothing above shall confer on any third party any benefit or the right to enforce any of these Booking Terms and Conditions.
c. These Booking Terms and Conditions shall be governed by and interpreted in accordance with the laws of England and Wales and Jump Inc and you submit to the exclusive jurisdiction of the courts of England and Wales.
In consideration of being permitted by Futures Leisure Limited to participate in its activities and to use its equipment and facilities, now and in the future, I hereby agree to release, indemnify and forever discharge Futures Leisure Limited, its agents, owners, members, shareholders, Directors, partners, employees, volunteers, manufacturers, participants, lessors, affiliates, its subsidiaries, related and affiliated entities, successors and assigns (the "RELEASED PARTIES"), on behalf of myself, my spouse, my children, my parents, my heirs, assigns, personal representative and estate as follows:-
1. I acknowledge that my participation in Futures Leisure Limited trampoline games and use of Futures Leisure Limited facilities entails known and unknown risks that could result in physical or emotional injury, paralysis, death, or damage to myself, to property or to third parties. I understand that such risks simply cannot be eliminated without jeopardising the essential qualities of the activity. The risks include, among other things and without limitation:-
Trampoline(s) expose its participants to the risk of cuts and bruises. Other more serious risks exist as well. Participants often fall off equipment, sprain or break wrists and ankles, and can suffer more serious injuries as well. Travelling to and from trampoline locations raises the possibility of any manner of transportation accidents. Double bouncing or more than one person per trampoline can create a rebound effect, causing serious injury. Flipping, running and bouncing off the walls are dangerous and can cause serious injury and must be done at the participants' own risk.
2. I expressly agree to accept and assume all of the risks existing in this activity. My participation in this activity is purely voluntary, and I elect to participate in spite of the risks. I warrant that I will only carry out moves and tricks that are within my ability level and throughout which I will be able to maintain control.
3. I acknowledge that I have been provided with the necessary safety instructions by Futures Leisure Limited in relation to the activities and will comply with these at all times while on the premises.
4. I understand that the activities provided by Futures Leisure Limited require a reasonable level of fitness and ability. I warrant that I do not have (or had) any medical condition including pregnancy that makes it dangerous for me to partake in such activities.
5. I agree as an adult participant, or the Parent/Legal Guardian of a minor participant (anyone currently under the legal age of 18) in consideration of being permitted to participate at Futures Leisure Limited, grant Futures Leisure Limited, the permission to photograph and/or record me or my children)/ward(s) in connection with Futures Leisure Limited to use the photograph and/or recording solely for advertising and promotional purposes. I waive any right to inspect or approve the use of the Photograph and/or Recording, and acknowledge and agree that the rights granted to this release are without compensation of any kind.
6. If the participant is a minor (A person under the legal age of 18), I agree that this Release of Liability and Assumption of Risk Agreement ("RELEASE") is made on behalf of that minor participant and that all of the releases, waivers and promises herein are binding on that minor participant. I represent that I have full authority as Parent or Legal Guardian of the minor participant to bind the minor participant to this Agreement.
7. Epilepsy Warning: Please be aware that there is a risk of flashing lights during each session. A few people may experience epileptic seizures when viewing flashing lights or patterns. Please consult your physician before jumping a Futures Leisure Limited if you have an epileptic condition or experience any unusual symptoms while playing games.
I acknowledge that if anyone is hurt or property damaged during my participation in this activity, I may be found by a Court of Law to have waived my or the minor participant's right to maintain a lawsuit against Futures Leisure Limited or any RELEASED PARTIES on the basis of any claim from which I have released them herein. I have had sufficient opportunity read this entire document. I have read and understood it, and I agree to be bound by its terms.
9. PROMOTIONAL CODE T&Cs (VIP500)
1.This offer code entitles the user to one free open jump session between Friday 11th August 2016 and Sunday 21st August 2016.
2.This offer code can be used multiple times for bookings made between Friday 11th August 2016 and Sunday 21st August 2016.
3.This offer code only entities the user to a free open jump session and excludes all other Jump sessions, including (but not limited to); JumpFit, Jump Parties, Urban Jump, Corporate Bookings and Jump Toddler. Jump-Inc reserve the right to withdraw this offer at any time.
4.Only applicable to Open Jump sessions at Jump-Inc Leeds.
10. LOCKDOWN T&Cs
Please see our separate Lockdown T&Cs for more information.


text:
|Publication number
|Publication type
|Application number
|Publication date
|Oct 13, 1992
|Filing date
|Sep 29, 1989
|Priority date
|Sep 29, 1989
|Fee status
|Publication number
|Robert C. Weppler
|Original Assignee
|Allen-Bradley Company, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (5), Non-Patent Citations (2), Referenced by (15), Classifications (4), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
1. Field of the Invention
This invention relates generally to industrial controllers and specifically to circuitry for connecting remote I/O units, by means of a serial communications link, to the industrial controller.
2. Background Art
Industrial controllers such as those described in U.S. Pat. Nos. 3,810,118, 3,942,158, 4,165,534 and 4,442,504 are typically connected to industrial equipment such as assembly lines or machine tools to operate such processes or equipment in accordance with a stored program. In industrial controllers, such as those disclosed in the above cited patents, the stored program includes instructions which, when executed, examine the condition of selected inputs to the controller from sensing devices on the controlled equipment and energize or de-energize selected outputs from the controller to operate devices on the controlled equipment.
Typically, inputs to the controller may be discrete binary signals such as those from switches which may detect limits of process variables such as motion, temperature, time, or other quantities, or the inputs may be analog measures of the process variables themselves, which are generally then converted to digital binary form for processing. Likewise, the outputs of the controller may be either binary outputs as implemented by mechanical or solid-state relays, or analog outputs produced by means of a digital to analog converter.
The inputs and outputs processed by the controller are received by the controller through I/O modules. A number of I/O modules may be placed with the controller in a rack containing a backplane which electrically interconnects the I/O modules with the controller. Alternatively, the I/O modules may be remotely located and connected to the controller by means of a serial communications "link". An I/O scanner incorporated into the controller allows the controller to send and receive data on this link.
Remote I/O modules may be grouped together within a remote rack and connected to the serial link by means of an adapter. The adapter provides an interface between the serial data on the link and the backplane of the rack and thus provides a shared means for each I/O module to receive and transmit data on the link.
Multiple adapters may be connected to the link each with a separate address to distinguish its own messages from those sent to other adapters. A remote rack may hold 16, 12, 8, or 4 I/O modules and therefore the address of an adapter includes a rack address and a starting quarter to permit multiple racks with less than 16 I/O modules to share one rack address.
For physical locations where only one I/O module is required, a "node adapter" may be connected to the serial link in place of a remote rack and adapter. The node adapter operates in a manner analogous to an adapter on a rack, however, rather than communicating with a plurality of I/O modules distributed on a backplane, the node adapter communicates with only a single I/O module or "node circuitry". In lieu of a backplane, data is typically transferred between the serial link and the node circuitry by means of a random access memory ("RAM") associated with the node adapter. The RAM is read from and written to by a microprocessor associated with the node circuitry.
It is important that the interface between the node adapter and the node circuitry be simple because the burden of the complexity and cost of the interface circuitry is not shared among multiple I/O modules. Maintaining the simplicity of the interface between the node adapter and the node circuitry, however, is complicated by the fact that there is a wide variety of microprocessors that may be used in the node circuitry and each microprocessor may vary in its interface conventions.
For example, there are two common random access memory ("RAM") interface conventions used by most microprocessors. The first of these, termed the "dual strobe convention", makes use of a "read strobe" signal and a "write strobe" signal. The presence of the read strobe and not the write strobe indicates that a read cycle is being requested with the timing of the read cycle indicated by the leading edge of the read strobe signal. Conversely, the presence of the write strobe and not read strobe indicates that a write cycle is requested with the timing indicated by the leading edge of the write strobe signal. This dual strobe RAM interface convention is found, for example, in the Z-80 series of microprocessors manufactured by Zilog of Cupertino, Calif.
The second RAM interface convention is termed the "single strobe protocol". The single strobe protocol makes use of a single undifferentiated "strobe" line and a separate "read/write" line. At the leading edge of the strobe signal a read or write cycle will be started depending on the state of the read/write line. This protocol is found in the 68000 series of microprocessors manufactured by Motorola.
Microprocessors may also differ as to their ability to handle interrupts. Hardware interrupts are a useful interface technique that may increase processing efficiencies in situations when it is necessary that certain conditions be continuously monitored. For example, the serial communications link must be continuously monitored by the node adapter for messages addressed to that node. Those messages must then be passed along to the node microprocessor.
Without the ability to handle interrupts, the microprocessor must continuously poll the node adapter to see if a message has been received. With the ability to handle interrupts, the microprocessor may attend to other tasks and when a message is received by the node adapter, the node adapter interrupts the microprocessor. On receipt of the interrupt, the microprocessor will suspend its current program and start a new program to accept the received message. There may be several different types of interrupts, each associated with a different condition. In order to determine which program to execute on receipt of an interrupt, the node microprocessor typically will receive an interrupt vector from the node adapter which indicates the correct interrupt program to be executed.
The node adapter must be able to rapidly process serial data received from the link. In order to improve the speed with which data may be processed, it is generally known to divide the various communications functions among different processing units. For example, a serial I/O unit may handle the basic serial communications protocols, passing the received data to a more sophisticated controller which handles the higher level communications protocols. Often, processing of the higher level protocols by the controller requires information extracted from the data during the processing of the lower level protocols by the serial I/O unit, for example, indications of certain control characters normally stripped away by the serial I/O unit. Nevertheless, communication of this occasional status information between the serial I/O unit and the controller uses valuable data cycle transfers and hence may reduce the overall operating speed of the node adapter.
The present invention is a node adapter circuit providing a flexible interface between a remote I/O link and a variety of node microprocessors.
The read/write interface circuit for the node adapter has three logic level inputs: a read line, a write line, and a chip select line. A logic decoding network produces a read output to the node adapter if the read line is active, the write line is inactive and the chip select line is active; and produces a write output to the node adapter if the write line is active and the chip select line is active.
It is one object of the invention to produce an interface circuit to allow a node microprocessor to read and write data to the node adapter regardless of whether the node microprocessor uses a dual strobe or single strobe RAM interface convention. In the dual strobe system, the chip select line is grounded and the read strobe and write strobe signals of the microprocessor are connected to the read and write lines respectively. With the single strobe system, the read line is grounded and the strobe and read/write lines are connected to the chip select and write lines respectively.
The node adapter interrupt handling circuitry is comprised of a vector passing system having an interrupt acknowledge input, a read input, and a read address input. When an interrupt is to be generated, an interrupt pending flag is set indicating that an interrupt is pending. A trigger address read input is active if the node microprocessor is reading a predetermined trigger address. A logic decoder circuit resets the interrupt pending flag in response to either the interrupt acknowledge input or the trigger address read input.
Accordingly, it is another object of the invention to produce an interrupt circuit that may be used with microprocessors which do not have interrupt capability. In such systems the interrupt line is periodically checked. If an interrupt is noted, the microprocessor reads the predetermined trigger address, resetting the interrupt pending flag. On the other hand, if the microprocessor has interrupt capabilities, the interrupt pending flag is reset directly by the interrupt acknowledge signal.
The node adapter includes a controller and a serial I/O unit. The serial I/O unit may communicate status information to the controller by means of the controller's instruction flags. An instruction flag is set by data from the output of a multiplexer. A first input to the multiplexer indicates the result of an arithmetic or logical operation performed by the controller that would conventionally be used to set the flag. A second input to the multiplexer indicates status information from the serial interface. This second input sets the flag when an instruction decoder indicates that the controller is processing a "get received data" command, as is used to transfer data from the serial I/O to the controller.
It is thus another object of the invention to provide a simple means for the controller to have access to the serial I/O status bits without the need for a separate data transfer cycle over the internal data bus. The get received data instruction would not normally affect the status of the flags and hence the flags may be used to communicate state data. The controller may "read" the flags by performing a test instruction.
Other objects and advantages besides those discussed above shall be apparent to those experienced in the art from the description of a preferred embodiment of the invention which follows. In the description, reference is made to the accompanying drawings, which form a part hereof, and which illustrate one example of the invention. Such example, however, is not exhaustive of the various alternative forms of the invention, and therefore reference is made to the claims which follow the description for determining the scope of the invention.
FIG. 1 is a front elevation view of an industrial controller showing the serial communications link and the node adapter of the present invention;
FIG. 2 is a block diagram of node adaptor of the present invention showing its connection to a dual strobe node microprocessor with interrupt capabilities;
FIG. 3 is a schematic diagram of the read/write interface circuitry of the node adapter circuit of FIG. 2;
FIG. 4 is a schematic diagram of the interrupt handling circuitry of the node adapter circuit of FIG. 2;
FIG. 5 is a schematic diagram of the flag multiplexer circuitry of the node adapter circuit of FIG. 2.
Referring to FIG. 1, an industrial controller which may incorporate the present invention consists of a main controller rack 10. A power supply 12 is attached to the leftmost wall of the rack 10 and provides power for the units contained in the rack and now to be described. The first unit is the controller processor 14 which executes a control program and supervises the input and output states of its various I/O modules 16. The controller processor 14 is inserted in the leftmost slot of the rack 10 and connects to a backplane 17 to communicate with the I/O modules 16 also connected to the backplane 17. The power supply 12 distributes power to the controller processor 14 and the I/O modules 16 along the backplane 17.
Up to 16 I/O modules 16 may be placed in rack 10. Additional I/O modules may be connected to the controller processor via a remote serial I/O link 18 which allows the controller processor 14 to communicate with one or more remote I/O racks 22 or nodes 26.
A remote I/O rack 22 is comprised of an adapter 20 and a number of I/O modules 16 contained in the rack 22. The adapter 20 provides an interface between the link 18 and the I/O modules 16 in its rack 22 by monitoring the link 18 and looking for data "frames" containing its address. For a description of the circuitry and operation of the adapter modules reference is made to Schultz et al. U.S. Pat. No. 4,413,319, entitled: "Programmable Controller for Executing Block Transfer with Remote I/O Interface Racks" and issued Nov. 1, 1983.
As mentioned, the remote serial link 18 may also connect to one or more nodes 26 via node adapters 24. The node adapter 24 functions analogously to the adapter 20 for the remote I/O racks 22, that is, the node adapter 24 provides an interface between the remote I/O serial link 18 and its node circuitry 28 by monitoring the remote I/O serial link 18 and looking for data "frames" containing its address. The primary functional difference between the remote I/O racks 22 and the I/O nodes 26 is that the nodes 26 perform only a single I/O function.
The protocol for the transmission of serial data on the remote serial link 18 is modelled after the IBM synchronous data link control ("SDLC") protocol familiar to those skilled in the art. The data is transmitted in frames comprised of several serial bytes; each frame being distinguished by the presence of leading and trailing flags.
Industrial controllers of the type shown in FIG. 1 are described in more detail in U.S. Pat. No. 4,250,563, entitled: "Expandable Programmable Controller", and issued Feb. 10, 1981, and U.S. Pat. No. 4,293,924, entitled: "Programmable Controller with High Density Intelligent I/O Interface" and issued Oct. 6, 1981.
Referring to FIG. 2, a node 26 is comprised of a node adapter chip 24, communicating with a separate node microprocessor 40 which handles the actual node I/O functions. The node adapter chip 24 is, in turn, comprised of a controller 32, a microprocessor interface 36, a serial I/O unit 38, a 480 byte RAM 34, and a 2 kilobyte read only memory ("ROM") 30.
The controller 32 performs the arithmetic and logical operations necessary to handle the higher level protocols for interfacing the node with the link 18 such as checking the frame addresses of received data and verifying, but not calculating, the error detection code on the received frame data. The controller 32 executes instructions read from ROM 30 and controls the microprocessor interface 36 and serial I/O unit 38.
The serial I/O unit 38 handles lower level link protocols such as decoding the serial frame data from the link 18 into parallel words and detecting certain control characters such as flags, as described above, which indicate the start and end of a data frame and the abort character which indicates that the current frame is faulty and should be disregarded. The controller 32 communicates with the serial I/O unit 38 by means of an internal 8-bit data bus 45 and the received data bus 43. In addition, the serial I/O unit 38 provides the controller 32 with a flag signal 46 indicating that a flag was received and a normal byte signal 48 indicating that a normal byte has been received. The receipt of an abort signal may be deduced from the absence of a normal byte signal 48 and flag signal 46. The controller reads the normal byte signal 48 and the flag signal 46 by means of its instruction flags as will be described below. The serial I/O unit 38 also provides other status information to the controller 32, such as an indication that the link is available for transmission of data. These status lines 49 differ from the flag and normal byte status lines 46 and 48 in that they need not be examined by the controller 32 after the receipt of every byte of data by the serial I/O unit 38.
The microprocessor interface 36 performs two functions. It mediates between the controller 32 and the node microprocessor 40 in requests for access to the RAM 34, and it provides an interface between the node microprocessor 40 and the controller 32. Specifically, the microprocessor interface 36 provides an interface to the node adapter 24 for RAM read/write control signals 54-60 from the node microprocessor 40 and interrupt control lines 66 and 68 to and from the node microprocessor interface 40 via the 8-bit data but 45 and the internal address bus 41. A separate RAM data bus 39 provides a path from the microprocessor interface 36 to the controller 32 for RAM 34 data. The RAM 34 may be read and written to by both the controller 32 and the node microprocessor 40 and hence provides a channel of communication between the controller 32 and the node microprocessor 40.
As mentioned, the microprocessor interface 36 receives two sets of control signals from the node microprocessor 40: the RAM control signals 54-60 and the interrupt control signals 66 and 68.
The RAM control signals are received via four lines: a chip enable line 54, a chip select line 56, a write line 58, and a read line 60. The first of these lines, the chip enable 54 is produced by an external address decoder 53 connected to the high order bits of the RAM address 62, and the address strobe 51, from the node microprocessor 40. The chip enable signal 54 allows the microprocessor 40 to access RAM at addresses outside those of the node adapter 24 as is understood in the art.
The purpose of the remaining RAM control signals 56-60 is to allow the node microprocessor 40 to specify whether a RAM read or write cycle is to be executed and to provide a timing signal for the transfer of data. The exact function of these lines will depend on the whether the microprocessor being used follows the single strobe or dual strobe convention as has been previously discussed. The microprocessor 40 shown in FIG. 7 is of the dual strobe convention.
The RAM control signals 56-60 are connected to the outputs of different classes of microprocessors according to their read/write convention as follows:
______________________________________Node Adapter Input Dual Strobe Output Single Strobe Output______________________________________Chip Select Line 56 Ground StrobeRead Line 60 Read Strobe GroundWrite Line 58 Write Strobe Read/Write______________________________________
Referring to FIG. 3, the inputs to the read and write lines 60 and 58 of the node adapter 24 are combined by AND gate 71 and the resulting signal is combined with the input to the chip select line 56 by NOR gate 73. A "delay" circuit formed of buffer 75 and NAND gate 77 is triggered by the rising edge of the input of NOR gate 73 to produce an inverted read/write strobe signal 74, with approximately a 3 ns. delay, at the output of NAND gate 77. This read/write strobe signal 74 controls the timing of the read or write cycle within the node adapter 24.
The read/write strobe signal 74 is inverted by inverter 70 and combined with the input to the write line 58 by AND gate 72 to form an external read signal 76 whose use will be described below. The unmodified signal on the write line 58 becomes a read/write select signal 58' that indicates to the node adapter 24 whether a read or a write is to be performed. The delay circuit formed by gate 75 and 77 ensures that the read/write select signal 58' has reached its final value prior to the occurrence of the read/write strobe signal 74.
It is assumed that the RAM control signals are inverted, that is, a logical low (zero volts) indicates the "true" state and the logical high (+5 volts) indicates a "false" state. Read and write strobes are therefore negative going pulses. Hereinafter, the term "active" will be used to refer to a signal in the true state and inactive will be used to refer to a signal in the false state regardless of its logical state or voltage.
Referring still to FIG. 3, for connection to a single strobe system, the read line 60 is grounded or set to logical low. Hence a negative going pulse on the chip select line 56 will cause a rising edge on the output of NOR gate 73 because the grounded read line 60 ensures that the output of AND gate 71 is always low. The positive going pulse from the output of NOR gate 73 is delayed by gates 75 and 77 and becomes the negative going read/write strobe signal 74. The read/write select signal 58' simply mirrors the state of the read/write input to the write line 58. The negative going read/write strobe signal 74 is inverted and when combined with the input to the write line 58 creates the external read signal 76 which is low if the request is a write and high if the request is a read.
The connection of a dual strobe system to the RAM control signals requires that the chip select line 56 be grounded. Now a negative going pulse on the read line 60 or the write line 58 will cause a rising edge on the output of NOR gate 73 because the grounded chip select line ensures that the second input of the NOR gate 73 is always low. Again, the positive going pulse from the output of NOR gate 73 is delayed by gates 75 and 77 and becomes the negative going read/write strobe signal 74. The read/write select signal 58' takes the state of the write strobe input on the write line 58. The delay formed by gates 75 and 77 ensures that the read/write strobe 74 has had sufficient time to reach its final state prior to being interpreted by the node circuitry. As before, the negative going read/write strobe signal 74 is inverted and when combined with the input to the write line 58 creates the external read signal 76, to be described below in connection with the interrupt handling circuitry.
Accordingly, this circuit allows the connection of either a single or dual strobe system to the node adapter 24.
Referring generally to FIGS. 1 and 2, the processing efficiency of the node 26 is increased by delegating the task of monitoring the remote I/O link 18 to the node adapter 24 thus freeing the external microprocessor 40 to attend to other node associated tasks. The ability to delegate the monitoring of the remote I/O link 18 to the node adapter 24 requires that the node adapter 24 be able to advise the microprocessor 40 when link 18 activity requires the attention of the microprocessor 40. Upon an interrupt, the microprocessor 40 will respond by suspending its current program and starting a new program to respond to the link activity indicated by the interrupt. This new program is chosen from several possible interrupt activated programs by means of an interrupt vector or address passed to the microprocessor 40 by the node adapter 24. The interrupt procedure makes use of the interrupt control lines: interrupt line 66 and interrupt acknowledge line 68 as shown in FIG. 2 and to be described below.
The node adapter 24 may interrupt the microprocessor 40 under several circumstances including: the receipt of a valid frame of data addressed to the node 26, a remote I/O link failure indicated by no activity on the link 18 for a predetermined length of time, or the beginning of the transfer of a sequence of data that may require additional preparation time by the microprocessor 40.
As mentioned, however, not all microprocessors are capable of handling an interrupt. Therefore, the node adapter 24 allows for two methods of responding to interrupts: conventional interrupt handling and a special "polling" method of responding to interrupts. Referring to FIG. 2, in conventional interrupt handling, the node adapter 24 generates an interrupt signal which is communicated to the microprocessor 40 by means of interrupt line 66. The microprocessor 40 responds to the interrupt by returning an acknowledgment signal on the interrupt acknowledgement line 68 and reading an interrupt vector from the data lines 64 of the node adapter 24. This action resets the interrupt line 66.
If the external microprocessor 40 cannot handle interrupts, it may use the "polling" procedure by periodically polling or reading the interrupt line 66 as part of the program it is executing. When an interrupt is detected, the microprocessor 40 reads the interrupt vector out of a "trigger" address in the node adapter 42. This action of reading the trigger address causes the signal on line 66 to be reset as in a normal interrupt procedure and presents the interrupt vector on the data lines as in a conventional RAM 34 read cycle.
Referring to FIG. 4, the node adapter circuitry for integrating these two types of interrupt responses is shown. In a conventional interrupt, an interrupt pending line 80 goes high indicating that an interrupt has been generated by the node adapter 24. This interrupt pending line connects to the "D" input of a D-type flip-flop 100. Upon the occurrence of an interrupt acknowledgement signal on line 68, an IEI signal on line 84, and an external read signal on line 76, combined by AND gate 104 the interrupt pending signal is latched by flip-flop 100.
The IEI signal 84 is used to permit other interrupting devices to be connected to the external microprocessor 40 without interference. If another such device is processing an interrupt, the IEI signal 84 is pulled low by that device to inhibit the interrupt processing of the node adapter 24. The external read signal 76 is derived from the RAM control signals 56-60 described above and indicates that the RAM 34 is being read by the microprocessor 40.
The output of flip-flop 100 is combined with the output of AND gate 104, by AND gate 112, and connected to one input of NOR gate 116 to produce an enable interrupt vector signal 118 which causes the interrupt vector to be presented to the microprocessor 40 via data lines 64. The output of AND gate 104 is also connected to one input of OR gate 108 to create the calculate interrupt vector signal 120 which causes the calculation of the interrupt vector in response to the type of interrupt required and resets the interrupt pending signal on line 80 and the interrupt signal 66 to microprocessor 40.
In a polling procedure, address bit zero on line 88 and trigger address read on line 90 are combined by AND gate 106. Address bit zero 88 is the least significant bit of the address lines 62 (as shown in FIG. 2). The trigger address read signal 90 is produced by an internal address decoder (not shown) and indicates that the microprocessor 40 has attempted a read of the trigger location, as previously described for the polling response. More specifically, the address decoder detects two consecutive trigger addresses. Either address may be read by the microprocessor 40 depending on the state of address bit zero 88. If address bit zero 88 is high when the trigger address is read, then the output of AND gate 106 is high. This output is connected to the remaining input of OR gate 108 to create the calculate interrupt vector signal 120 which calculates the interrupt vector depending on the type of interrupt required and resets the interrupt pending signal on line 80 and the interrupt signal 66. If address bit zero 88 is low, the calculate interrupt vector signal 120 is not created and the interrupt vector in RAM 34 is not updated.
In either case, when the interrupt address read line 90 goes high, the "D" input of D type flip-flop 102 is pulled high. The next clock signal 92 from the node adapter's internal clock sets the output of this flip-flop 102. The output of flip-flop 102 is combined with the trigger address read signal 90 by AND gate 114 and connected to the remaining input of NOR gage 116 to produce an enable interrupt vector signal 118 which causes the interrupt vector to be presented to the microprocessor 40 via data lines 64 in response to the microprocessor's reading of the trigger address.
Accordingly, in the polling mode of operation, the interrupt vector may be "read" from one of two predetermined trigger addresses. The higher address, indicated by address bit zero being high, outputs the latest interrupt vector on the data lines 64. The lower address, indicated by address bit zero being low, outputs the previous interrupt vector and does not update the addresses in RAM 34. This lower address is useful primarily as a troubleshooting aid. Reading the higher address resets the interrupt line 66 without the use of the interrupt acknowledge line 68 thereby simplifying the interface with the microprocessor 40.
As described above, the serial I/O unit 38 communicates with the controller 32 via an 8-bit data bus 45 and a received data bus 43. The 8-bit data bus 45 may be used to transmit a single word of data from the controller 32 to the serial I/O unit 38 and hence to the remote I/O link 18. Conversely, the received data bus 43 may be used to transmit a single word of data received by the serial I/O unit 38, from the remote I/O link, to the controller 32.
The serial I/O unit 38 periodically also receives other important status information, distinct from the link data, that may be required by the controller 32. For example, in the SDLC serial link protocol, used in the preferred embodiment, an "abort" or "flag" character may be transmitted encoded within the data on the serial link 18. When received by the serial I/O unit 38, these control characters are decoded and status flags within the serial I/O unit 38 are set. This decoding is a low level link protocol and therefore invisible to the controller 32. Nevertheless, the controller 32 may require the information contained in these status flags. For example, the abort flag indicates that the entire frame of data should be disregarded. The controller 32 must have access to the abort status flag so as to prevent aborted data from being transmitted to the external microprocessor 40. The controller 32 also requires access to the "flag" flag which indicates the start and end of a data frame and is used by the controller 32 to determine when to verify error correction codes as well as for other purposes.
One means of communicating the state of the status flags in the serial I/O unit 38 to the controller 32 would be to use the received data bus 43. The approach, however, would require a full data transfer cycle for the status flags after each transfer of link data, effectively halving the speed of the controller received data bus 43.
The approach adopted in the present invention is to transfer the status flags from the serial I/O unit 38 to the controller 32 via the instruction flags associated with the controller's arithmetic/logic unit ("ALU") (not shown) during the execution of the controller's "get received data" ("GRD") instruction that reads data from the serial I/O unit 38. The GRD instruction would not normally modify the ALU's flags hence the flags are free to be used to communicate other information to the controller 32. This use of the ALU flags therefore allows additional bits to be communicated between the serial I/O unit 38 and the controller 36 without use of the received data bus 43.
The controller 32 uses three status flags: "carry", "minus" and "zero". These flags indicate the result of various logical and arithmetic operations performed by the controller's ALU as is well understood in the art. For example, the carry flag is typically set if the result of an arithmetic operation by the ALU is such as to produce an overflow or underflow. Also, the carry flag is typically used to hold the overflow bits that occur during shift left or shift right logical operations.
Referring to FIG. 5, the ALU's carry flag 160 is indicated by the state of the output of D type flip flop 156. An instruction decoder (not shown), as is generally understood in the art, produces a select signal 130 if the instruction presented to the ALU is an arithmetic instruction. The select signal is connected to the select input of a dual input multiplexer 154. If the select signal is active, multiplexer 154 connects the input of flip-flop 156 to the arithmetic carry signal 132 from the ALU. If the instruction to the ALU is not an arithmetic instruction, as indicated by select signal 130, then multiplexer 154 connects the input of flip-flop 156 to the output of multiplexer 152.
The instruction decoder also produces a shift left signal 134 and a GRD (get received data) signal 142 which are combined by OR gate 149 to produce a select signal for multiplexer 152. If there is no shift left 134 or GRD 142 instruction, the input of flip flop 156 is connected to the bit zero line 138 of the ALU's accumulator, via the combined action of multiplexer 154 and 152, to be loaded with the overflow bit resulting from a shift right instruction as is generally appreciated by those skilled in the art.
Alternatively, if there is a shift left or GRD instruction, indicated by lines 134 and 142 respectively, the input of flip-flop 156 is connected to the output of multiplexer 150.
If there is no GRD instruction 142 and hence implicitly only a shift left 134, the input of flip-flop 156 is connected to the bit seven line 144 of the ALU's accumulator, via the combined action of multiplexers 154, 152, and 150 to be loaded with the overflow resulting from a shift left instruction as is generally appreciated by those skilled in the art. Conversely, if there is a GRD instruction 142, hence implicitly no shift left instruction 134, the input of flip-flop 156 is connected to the flag line 146 from the serial I/O unit 38, via the combined action of multiplexers 154, 152, and 150 allowing the status information from the serial I/O unit 38 to be communicated to the controller 32.
In an analogous manner, the ALU's zero flag is used to indicate both zero flags from the ALU's arithmetic and logical operations and the "normal byte" status flag on line 48 (shown in FIG. 2) from the serial I/O unit 38 when the GRD instruction is invoked.
The above description has been that of a preferred embodiment of the present invention. It will occur to those who practice the art that many modifications may be made without departing from the spirit and scope of the invention. In order to apprise the public of the various embodiments that may fall within the scope of the invention, the following claims are made.
|Cited Patent
|Filing date
|Publication date
|Sep 6, 1979
|Sep 1, 1981
|Honeywell Information Systems Inc.
|Real time adapter unit for use in a data processing system
|May 21, 1984
|Feb 3, 1987
|Rca Corporation
|Universal interface circuit for microprocessor peripherals
|May 16, 1988
|Nov 21, 1989
|Allen-Bradley Company, Inc.
|Programmable controller with I/O expansion module located in one of I/O module positions for communication with outside I/O modules
|Aug 26, 1985
|Feb 6, 1990
|American Telephone And Telegraph Company, At&T Bell Laboratories
|Test interface circuit which generates different interface control signals for different target computers responding to control signals from host computer
|Mar 14, 1988
|Oct 30, 1990
|Advanced Micro Devices, Inc.
|Universal microprocessor interface circuit
|Motorola Product Preview of MC68HC53 Asynchronous Communication Interface Adapter (ACIA) pp. 3.520 3.523, 1983.
|Motorola Product Preview of MC68HC53 Asynchronous Communication Interface Adapter (ACIA) pp. 3.520-3.523, 1983.
|Citing Patent
|Filing date
|Publication date
|Aug 26, 1992
|Feb 15, 1994
|Lsi Logic Corporation
|Computer system module assembly
|Dec 11, 1992
|May 9, 1995
|International Business Machines Corporation
|System and method for dynamically varying between interrupt and polling to service requests of computer peripherals
|May 16, 1994
|Jul 11, 1995
|Smits; Gerard D.
|Computer system module
|Sep 23, 1992
|Oct 31, 1995
|International Business Machines Corporation
|Method and system for enhancing the efficiency of communication between multiple direct access storage devices and a storage system controller
|May 24, 1994
|Feb 27, 1996
|Zilog, Inc.
|Technique for automatically adapting a peripheral integrated circuit for operation with a variety of microprocessor control signal protocols
|Aug 30, 1991
|Jun 17, 1997
|Ncr Corporation
|Work station architecture with selectable CPU
|Jul 31, 1995
|Nov 25, 1997
|Sgs-Thomson Microelectronics S.A.
|Method and apparatus for operating a microcomputer in an emulation mode to access an external peripheral
|Nov 20, 1995
|Mar 10, 1998
|Advanced Micro Devices
|Interrupt coprocessor configured to process interrupts in a computer system
|Nov 24, 1998
|Jun 27, 2000
|Cypress Semiconductor Corp.
|Interruptible state machine
|Mar 8, 1994
|Feb 6, 2001
|Texas Instruments Incorporated
|Data transfer controller employing differing memory interface protocols dependent upon external input at predetermined time
|Jan 6, 1999
|Jul 17, 2001
|Compaq Computer Corp.
|System and method for serial interrupt scanning
|Oct 20, 1998
|Apr 2, 2002
|Siemens Audiologische Technik Gmbh
|Method and digital hearing device for detecting and processing non-synchronous processes in a digital hearing device
|Dec 12, 2003
|Sep 11, 2007
|Samsung Electronics Co., Ltd.
|Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion
|Dec 12, 2003
|Jan 6, 2005
|Seong-Jin Jang
|Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion
|Mar 25, 1996
|Oct 17, 1996
|Siemens Aktiengesellschaft
|Connection for coupling binary control and warning signals to a data processing unit
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Sep 29, 1989
Owner name: ALLEN-BRADLEY COMPANY, INC., MILWAUKEE, WI A WI CO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:WEPPLER, ROBERT C.;REEL/FRAME:005147/0695
Effective date: 19890927
|Oct 12, 1993
|Certificate of correction
|Apr 12, 1996
|Fee payment
Year of fee payment: 4
|Apr 12, 2000
|Fee payment
Year of fee payment: 8
|Apr 13, 2004
|Fee payment
Year of fee payment: 12

subset: commoncrawl


text:
Travel Fizz,study abroad consultants in Chandigarh is a dedicated to provide study abroad students from short-listing right Foreign Universities to make University applications, liaising with Universities on admission decisions, finalizing admissions, visa guidance & more for abroad study. Travel Fizz helps students to make their dream of study abroad come true with the team of experts.We provide study abroad opportunities in Australia,New Zealand, Canada, USA and UK.\n
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text:
- 54 years old
- Date of birth: Aug 19, 1954
- Date of passing: Apr 12, 2009
- Place of passing:
Memphis, Tennessee, United States
|Let the memory of Deborah "Debby" be with us forever
"I would like to send my deepest condolences to the family and friends of Deborah. Though I didn't know her personally, I can tell from the obituary that she was greatly loved and will be sorely missed. Death is never an easy thing to cope with, and the feelings of pain, grief, and helplessness can at times seem unbearable. I would like to share a comforting thought that helped me when I dealt the sting of death in my family. John 5:28, 29 tells us that soon "all those in the memorial tombs will hear his voice and come out." And at Revelation 21:4 God promises that he "will wipe out every tear from their eyes, and death will be no more, neither will mourning nor outcry nor pain be anymore. The former things have passed away." Yes, take comfort in knowing that not only does God eagerly yearn to bring our dead loved ones back to life, He promises to get rid of death and pain forever! If you would like to read more comforting thoughts from the scriptures please visit www.jw.org. May the fond memories you share continue to bring a measure comfort during these trying times."
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Everyone knew that Jose Aldo was going to be far from pleased with the UFC's decision to tap Conor McGregor for a lightweight title shot. But, as it looks right now, not only is the Brazilian star angry, he's saying he's done fighting.
Yes, the promotion has booked McGregor to fight lightweight champ Eddie Alvarez on November 12th, at UFC 205. The booking comes after Dana White said several times that McGregor would need to rematch Aldo next, or vacate the 145 title. McGregor, however, has not been stripped of the featherweight crown.
Since the UFC buzzed the MMA world that Alvarez – McGregor is a go, Aldo has spoken with Brazilian outlet, Combate. According to a follow up report from MMA Junkie.com, here is some of what the interim champ had to say:
"I understand (McGregor) is a big draw, but there's a limit in which this is no longer a sport and it's a circus," Aldo said. "I don't want any type of fight with the UFC. The only thing I want is to move on with my life and that they move on with theirs.."
"I don't want to fight anymore. What if they offer me millions? They can keep them, I don't want it. Pardon the expression, but I'm not a whore, to sell myself. I'm a man. My dad made me this way. So that's all I want."
Wow. Now, you may be one of the folks who isn't interested in seeing McGregor – Aldo II. But, considering McGregor will now fight three times, without defending the featherweight belt, it's not surprising to see that Aldo and others are upset by the move.
Here's hoping Aldo doesn't in fact hang up the gloves. It would be an absolute shame if one of the greatest fighters who ever lived is done competing at the age of 30.


text:
All | Editorial | General Tech | Graphics Cards | Networking | Motherboards | Cases and Cooling | Processors | Chipsets | Memory | Displays | Systems | Storage | Mobile | Shows and Expos
Introduction and Technical Specifications
Courtesy of EVGA
Sometimes, good things do come in small packages. The latest board on our test bench from EVGA proves that fact, the EVGA Z77 Stinger. The Z77 Stinger is a micro-ITX form factor board based on the Intel Z77 chipset, but don't let its size fool you. This board is packed with features and delivers the performance that we've come to expect out of its full-size brethren. At a mere $199.99 base price, the EVGA Z77 Stinger would be at home in any enthusiast's full tower case or HTPC build.
Courtesy of EVGA
Even with its small stature, the EVGA Z77 Stinger promises to pack some power. It features support for the following: SATA 2, SATA 3, eSATA, USB 2.0 and USB 3.0 type devices; two different network types featuring an Intel GigE NIC and an Atheros Bluetooth adapter; PCI-Express x16 3.0 and m-PCIe ports; and HDMI 1.4 and DisplayPort 1.1a style video ports. With the addition of an m-PCIe adapter, the board can support onboard Wi-Fi as well.
Continue reading our review of the EVGA Z77 Stinger mini-ITX Motherboard!!
Introduction and Specs
Courtesy of ECS
As part of their Black Extreme line of motherboards, the ECS Z77H2-AX pairs the promise of performance and a mile-long feature list with looks that could kill. We decided to put this board through the paces, throwing our normal suite of benchmark and functionality tests to see how well it lived up to its reputation. The ECS Z77H2-AX seems to be well priced at its $309.99 base price with all the higher-end features and bling built into the board.
Courtesy of ECS
From the initial unboxing of the board, I was dumbstruck. ECS literally gold-plated every heat-producing surface on this board, giving it a very unique look and feel. The board itself has no shortage of features with SATA 2, SATA 3, mSATA, and eSATA ports, support for 3 different networking types, and enough USB 2.0 and 3.0 ports for anyone.
Continue reading our review of the ECS Z77H2-AX Golden Motherboard!!
Intro and Tech Specs
Courtesy of ASUS
Today we will be evaluating the ASUS P8Z77 WS motherboard on the test bench, evaluating its performance and functionality in various ways to ensure that the board works up to the standards we've come to expect from ASUS. At $339 a base price, this Intel Z77 chipset based board is part of the ASUS Workstation series, designed to meet the needs of the harsh corporate and server environments requiring optimal component functioning over a 24/7 timeframe.
Courtesy of ASUS
The P8Z77 WS is a feature-rich solution with dual Intel-based GigE NICs, an ASUS customized UEFI BIOS, and multi-GPU PCI 3.0 support offered innately through the Intel Z77 chipset as well as the integrated LicidLogix Virtu MVP chipset.
Courtesy of ASUS
Continue reading our review of the ASUS P8Z77 WS Workstation Motherboard!!
Today we are taking a look at MSI's flagship Z77 motherboard, the Z77A-GD80. Beyond being the GD80 SKU, which for several generations now has been given MSI's premiere options, this GD80 in particular is an innovative board. This is due to the Z77A-GD80 being the first Windows motherboard that was certified for Intel's Thunderbolt technology.
As many of you may know, Thunderbolt has 10 Gbps of bandwidth, as well as integrates Mini DisplayPort for video. With all of this bandwidth, Thunderbolt is an exciting standard, which we will focus on in depth later in this review.
Continue reading our review of the MSI Z77A-GD80 Thunderbolt Motherboard!
Introduction and Technical Specifications
Courtesy of ASUS
It's been a couple months since we've had a chance to evaluate a Z77-based motherboard, so we are taking this opportunity to throw ASUS's P8Z77-V Deluxe on our test bench to put it through our comprehensive real-world and synthetic benchmarks. This $279 board has been available for several months and supports the LGA 1155 platform that includes Sandy Bridge and Ivy Bridge processors.
Courtesy of ASUS
There are many features to drool over about the ASUS P8Z77-V Deluxe, but my favorite ones include the board's unique power management features, Wi-Fi functionality with remote access, and customized UEFI BIOS. This board also includes other enhancements that focus on support for faster USB 3.0 and PCIe 3.0 integration as well as extra SATA 6GB/s ports that provide double the bandwidth of current bus systems.
Continue reading more about our review of the ASUS P8Z77-V Deluxe!
Introduction and Technical Specifications
Courtesy of Gigabyte
PC gaming is alive and well and hardware vendors are working to create unique features in their product lines to entice this niche audience. Gigabyte has always had a soft spot for gamers who want the best components for their LAN rigs so they can own their friends in any game genre they choose to play. Gigabyte has broadened their product line to include performance gaming mice, keyboards, and PC cases. They also have a line of "G1-Killer" motherboards that Gigabyte claims is designed with 3D gaming in mind. One of their latest boards in the G1-Killer series is the G1.Sniper M3, and just happen to have a sample that we are reviewing today.
Courtesy of Gigabyte
The G1.Sniper M3 was designed into a micro ATX form factor that sports Intel's latest Z77 Express chipset and supports the third generation of Intel's LGA 1155 "Ivy Bridge" processors. It is challenging to pack enough performance features and overclocking options onto a micro ATX footprint, but Gigabyte's G1.Sniper M3 has broken the code in this department. This $180 board includes a digital power phase design with auto voltage compensation, dual UEFI BIOS, and an onboard Creative Sound Core3D quad-core audio processor for rich, high-definition audio.
Continue reading our review of the Gigabyte G1.Sniper M3 LGA 1155 Micro ATX Motherboard!!
An overview of Thunderbolt Technology
The promise of Thunderbolt connectivity has been around for a couple of years now. Today, Thunderbolt is finally finding its way to the PC platform in the form of motherboards from ASUS and MSI. First unveiled as "Light Peak" at the Intel Developer Forum in 2009, the technology started out as a way to connect multiple devices to a system over a fiber optic cable (hence the 'light' in the name), though the final products have changed the implementation slightly.
The first prototype implementations actually used a USB-style connection and interface. It further required fiber optic cables. When it was renamed to Thunderbolt and then released in conjunction with a new lineup of Apple MacBook laptops, not only did the physical interface move to a mini-DisplayPort connection but the cable was made to use copper rather than fiber. Without diving too far into the reasons and benefits of either direction, the fact is that the copper cables allow for modest power transfer and are much cheaper than fiber optic variants would be.
Thunderbolt's base technology remains the same, however. It is a transfer standard that allows for 10 Gbps of bandwidth for each channel (bi-directional) and concurrently supports both data and display connections. The actual interface for the data path is based on PCI Express and connected devices actually appear to Windows as if they are internally connected to the system which can offer some interesting benefits – and headaches – for hardware developers. The display connection uses the DisplayPort standard and can be used along with the data connection without affecting bandwidth levels or performance.
For current Intel processor implementations, the Thunderbolt connection is supported by a separate controller chip on the motherboard (or a riser card) – and some routing is required for correct usage. The Thunderbolt controller does not actually include a graphics controller, so it must be fed an output from another graphics processor, obviously in this case directly from the Ivy Bridge / Sandy Bridge processors. In theory, these could be from other controllers, but with the ubiquitous nature of integrated processor graphics on IVB and SNB processors, this is going to be the implementation going forward according to motherboard and system designers.
Continue reading our review of Thunderbolt on Windows and the ASUS P8Z77-V Premium!!
Introduction and Features
Courtesy of ASUS
ASUS continues to optimize their hardware for the overclocking and PC gaming crowds, but they are also catering to a niche audience looking for ultra stable and durable PC components. ASUS's Sabertooth X79 motherboard is their one of their latest products to bear the TUF series label and sport customized hardware and thermal components as well as a desert camo color scheme to complete the military look. This $329 motherboard comes with a five-year warranty, digital power management system, rugged chokes, solid capacitors, and MOSFETs that have been certified through third party, military-grade testing.
Courtesy of ASUS
The Sabertooth X79 also comes with a host of other features to improve SSD caching and give users quad GPU support for CrossfireX and SLI graphics card configurations. This board also includes a unique UEFI BIOS and natively supports 2TB hard drives with 64-bit operating systems. The USB BIOS "Flashback" feature also helps new users update their motherboard BIOS without entering the BIOS. ASUS states that users can use any USB storage device with the latest BIOS, push the BIOS button located on the back I/O panel for three seconds, and the board will automatically update the BIOS using standby power. Very cool!
Courtesy of ASUS
The back I/O panel on the Sabertooth X79 is no slouch either as it gives users a healthy amount of USB 2.0, USB 3.0, and eSATA 6GB/s ports for greater performance and expandability options. They also added a small fan over the back I/O panel as part of their "TUF Thermal Armor" feature that will help cool and exhaust heat from ther motherboard out the back of the chassis. Let's move on to the rest of the Saberbooth X79's features where we will get our first out-of-the-box look at this motherboard.
Continue reading our review of the ASUS Sabertooth X79 LGA2011 Motherboard!!
Introduction and Features
Courtesy of Gigabyte
We are still making our way through an avalanche of X79 motherboards on our test bench that leverages the power of Sandy Bridge-E CPUs, but we didn't want to wait any longer on powering up Gigabyte's GA-X79-UD5 extended ATX motherboard. Gigabyte has really stepped up their game by offering optimized LGA 2011 for no-nonsense PC builders, hardware enthusiasts, serious overclockers, and even FPS/RPG PC gamers. Our review of the X79-UD5 is going to evaluate every aspect of the board's ability to handle automatic and manual overclocking, DX10/DX11 gaming, and other synthetic and real-world benchmarks.
Courtesy of Gigabyte
The Gigabyte X79-UD5 motherboard takes full advantage of the new features available with the LGA 2011 platform and X79 Express chipset like the abiliy to use up to 64GBs of quad-channel memory via eight DIMMs and support for dual and triple AMD CrossfireX or NVIDIA SLI graphics card configurations for multi-monitor, high-definition gaming. These features should make ultra enthusiasts grin from ear to ear because they will probably be the ones who tandem this board with an Intel Core i7-3960X processor and dual NVIDIA GTX 680s graphics cards that were just released earlier this week. The $299 price tag on this board also places it right in the middle of the pack of LGA 2011 motherboards available on Newegg and other vendors.
Continue reading our review of the Gigabyte GA-X79-UD5 motherboard!
Introduction and Features
Courtesy of MSI
My first Sandy Bridge-E motherboard review of 2012 showcases the talents of Intel's latest i7-3820 3.6GHz quad-core processor and MSI's X79A-GD65 (8D) ATX motherboard. The enhancements included in the LGA 2011 platform combined with MSI's unique optimizations to the board's overclocking, gaming, and power management capabilities should make for an exciting testing experience.
Courtesy of MSI
MSI currently has six motherboards that support the LGA 2011 socket and the X79A-GD65 (8D) is considered one of their higher-end offerings at $289.99. This board targets users who want to take advantage of three PCI-E x16 slots for AMD CrossfireX or NVIDIA SLI configurations. It also gives users the ability to use up to two SATA 6GB/s and four SATA 3GB/s devices courtesy of the X79 chipset. MSI also used a second ASMedia controller to add two more SATA 6GB/s ports to the board. All of these SATA3 ports support Intel's Rapid Storage Technology, but the SATA3 devices managed by the X79 chipset can only handle RAID 0 and 1 versus the ASMedia chip that handles RAID 0, 1, 5, and 10.
Continue reading our review of the MSI X79A-GD65 (8D) Motherboard!!
7-series based motherboards from ASUS
This is going to be an interesting couple of months as the industry balances the move from Sandy Bridge to the 3rd Generation of Intel Core processor and the 7-series chipsets. We have documented the rumored delays of the Ivy Bridge CPUs but it looks like Intel is moving ahead with the Z77/H77 chipset launch as planned. This means that from now until whenever those new CPUs actually launch we will see quite a few new motherboards announced from the typical vendors claiming "future platform compatibility."
Recently we spent some time with our friends at ASUS to learn about its plans for the Z77 launch and I must say I came away quite impressed with the technology and features being integrated. Today I am allowed to share with you some photos and basic information about the features being offered on the ASUS Z77 lineup, though without much hands-on time we are limited in what we can say.
There are going to be options ranging from the high-end Maximus V Formula to the budget priced P8Z77-V to the ultra-niche with the mini-ITX P8Z77-I Deluxe. Enjoy!
Continue reading our preview of the upcoming ASUS Z77 motherboards!!
Layout and Features
From the Forums is a new segment here on PC Perspective where we dive through the best content on the PC Perspective Forums and bring it to the main stage here on pcper.com. Even though this content isn't direct from our editors it brings value to the reader and so we wanted to push into the spotlight! Our forums are some of the best online if you are looking for community fun and gaming or have a particularly annoying issue you are trying to work out on your latest build. Be sure you stop by to see what our members are up to today!!
Windwithme has been a member of the PC Perspective Forums since mid-2009 and has continually contributed with in-depth reviews of hardware including motherboard, graphics cards SSDs and more. Though English is not his native language, and because of that some of his text will seem odd to US readers, the content is great and we are glad to have Windwithme as part of our community! Enjoy! You can find the original thread for this content right here.
If you have any feedback on this new feature, please drop us a line in the commments below!
Ever since Intel officially launch Sandy Bridge-E new platform in 2011 November,
several motherboard companies successively roll out new motherboard based on X79 chipset to support Intel next generation high-end platform.
Due to the continuous effort of self-own brand management made by FOXCONN, Quantum Force series still dominant high-end motherboard.
FOXCONN X79 Quantumian-1 still provides various choices for the market though the quantities of Quantum Force series are not as various as they are in the past time. Soon after the release of Intel X79 chipset, FOXCONN promptly roll out corresponding X79 motherboard. Quantum Force was naming in a special way which the Intel code won't be shown on the models.
This time, Quantumian-1 which belongs to the series of Quantum Force still follows the high-end style both in material and design.
The patterns shown on exterior packing of high-end product are always different which exhibits the great efforts on art design.
The full picture of FOXCONN Quantumian-1
Quantum Force is common to use black and red to create contrast visual sense.
Currently, there are more and more motherboard brands adopt these two colors to match.
It is known that the market segment of Quantumian-1 x79 is positioned as high-end product line.
Besides, the corresponding specification, design and featured over clocking function have also been highly highlighted.
- Product manual
- easy guide
- nVIDIA SLI 3Way bridge
- IO shield
- SATA connectors and cables both in red and yellow
- DC power cable SATA
Continue reading the rest of this forum review of the Foxconn Quantumian-1 X79 Motherboard!!
Introduction and Specifications
AMD's Fusion technology has worked out well for the company in 2011 and many vendors have reaped the benefits by including this platform in their mini ITX motherboards and netbook offerings. Gigabyte found room in their product line to feature this chipset in its GA-E350N-USB3. We received one of these boards for review to see how it stacks up against other E-350 mini ITX boards available today.
The GA-E350N-USB3 can be purchased for around $89.99 (after mail-in rebate from Newegg) and includes an AMD dual-core E-350 1.6GHz processor with an integrated Radeon HD 6310 GPU and support for USB 3.0, SATA3, and a PCI-E x16 slot for add-on video cards or other PCI-E devices. AMD developed the Brazos platform to directly compete with Intel's Atom and NVIDIA's ION technologies for the top slot this year's netbooks, notebooks, and some entry-level desktop solutions.
Introduction and Features
Our test bench has seen a flood of Z68-based enthusiast motherboards this fall and ASRock added their flagship Z68 Extreme 7 Gen 3 board to the top of the pile for testing. The Extreme 7 Gen 3 pulls out all the stops for extreme enthusiasts and ultra overclockers by arming this board with next-gen PCI-E 3.0 support and an NVIDIA NF200 chip to allow users to run dual graphics cards at PCI-E x16/x16 mode and three graphics cards at x16/x8/x8 respectively.
This $275 board brings with it a lot of features that users have been begging for like a graphical Unified Extensible Firmware Interface (UEFI), Intel's Smart Response techology, dual gigabit LAN capabilities, and support for six USB 3.0 and six SATA 3 devices. They also didn't skimp on the power components by adding premium gold caps that are made in Japan and considered by many to be luxury capacitors.
Read our entire review of the ASRock Z68 Extreme 7 Gen 3 motherboard!
900 Series: Bulldozer Ready
The rumor on the street is that Asus makes a few motherboards. They may or may not be the world's leading motherboard manufacturer. Asus may also have a pretty good reputation for quality and innovation in their products. It is tongue in cheek hour at PC Perspective. All joking aside, Asus anymore is the gold standard for quality manufacturing and design in motherboards.
Some months ago AMD released their AM3+ capable chipsets, though the release was not nearly as exciting as we had hoped. The AMD 900 series of chipsets are essentially the same silicon as those that power the non-integrated AMD 800 series. There are three SKUs that are currently available for the 900 series that Asus makes motherboards around.
Introduction and Features
Courtesy of MSI
Micro-Star International, better known as MSI, has been busy little bees in 2011 to fend off fierce competition from ASUS, Gigabyte and other motherboard vendors. This year's launch of the Z68 chipset from Intel combined the capabilities and features from the H67 and P67 chipsets, and MSI capitalized on this when they joined forces with LucidLogix to include their Virtu technology in their latest Z68A-GD80 motherboard. Lucid's Virtu tech provides users with switchable graphics, which allows users to enjoy both graphics power of integrated GPU and discrete GPU.
Courtesy of MSI
MSI also used the Z68A-GD80 as their first motherboard to support PCI Express 3.0, which boosts 32GB/s of transfer bandwidth and makes this mobo a bit more future proof for users looking for their next hardware upgrade. MSI also upgraded their BIOS system to ClickBIOS II, which provides a consistent user interface both in the UEFI BIOS and in Windows. Users can control their system settings directly from Windows and the GUI also supports touchscreen controls.
Continue reading our review of the MSI Z68A-GD80 G3 motherboard!!
The Basics
If you have been visiting PC Perspective at all over the last week there is no doubt you have seen a lot of discussion about the currently running Battlefield 3 beta. We posted an article looking at performance of several different GPUs in the game and then followed it up with a look at older cards like the GeForce 9800 GT. We did a live stream of some PC Perspective staff playing BF3 with readers and fans, showed off and tested the locked Caspian Border map and even looked at multi-GPU scaling performance. It was a lot of testing and a lot of time, but now that we have completed it, we are ready to summarize our findings in a piece that many have been clamoring for - a Battlefield 3 system build guide.
The purpose of this article is simple: gather our many hours or testing and research and present the results in a way that simply says "here is the hardware we recommend." It is a the exact same philosophy that makes our PC Perspective Hardware Leaderboard so successful as it gives the reader all the information they need, all in one place.
Continue reading our guide for building a system for Battlefield 3!!
Introduction and Specifications
Courtesy of ECS
ECS developed the HDC-I motherboard to take advantage of AMD's new Brazos platform that's based on the Hudson M1 chipset and their latest E-350 dual-core processor and integrated DDR3 800/1066 memory controller. The dual-core E-350 APU, which combines the CPU and GPU, brings a host of features to mini ITX enthusiasts like USB 3.0 compability, SATA 6Gb/s support, bluetooth and Radeon HD 6310 graphics and UVD 3 to play 3D Blu-ray and HD-1080P movies.
Courtesy of ECS
Another huge advantage of going with a mini ITX motherboard for your next home theater PC is the balance of computing power and power consumption that the AMD Brazos platform adds to the ECS HDC-I. The HDC-I is an energy-efficient motherboard that has integrated computing power and graphics firepower for users looking for an "all-in-one" solution for their next small form factor build.
Continue reading our review of the ECS HDC-I Fusion Mini ITX Motherboard!!
Introduction and Features
Courtesy of MSI
In 2011, MSI has based their enthusiast-level Sandy Bridge motherboards on two main features: novice and advanced overclocking and stable and reliable hardware components. We had the opportunity in March to evaluate the sub-$200 P67A-GD65, which flexed its muscles in several benchmarks including PC gaming and general PC tasks and applications.
Courtesy of MSI
The P67A-GD80 adds a few more ultra-enthusiast features and an additional PCIe x16 slot, which pushes the price of this high-end motherboard to around $229 (before mail-in rebate at Newegg). This board sports Intel's P67 chipset that supports their latest LGA 1155 Sandy Bridge processors. It also has three PCIe x16 slots that are compatible with CrossfireX and SLI graphics card configurations to make this board a fantastic solution for triple-monitor, high-resolution gaming.
AMD Unleashes the 990FX: Paving the way for Bulldozer
Word of the AMD 990FX chipset first came around the end of last year. Speculation was brisk as to what new features it would bring, and when exactly it would help to usher in the age of Bulldozer to the world. Most thought that it would be a shrink of the then current 890FX, and the new SB950 southbridge would have improvements to the SATA 6G controller, as well as a native USB 3.0 implementation. Today we finally get to see the reality of the situation. It is not groundbreaking, nor is it altogether exciting, but it is certainly interesting.
The 990FX and SB950 chips are identical to the previous 890FX and SB850. They are the same silicon. For those hoping for new technology will be disappointed. But all is not lost! AMD did increase the HyperTransport specification from 3.0 to 3.1, which allows the HT bus to run at 6.4 GTPS as compared to the older 5.2 GTPS. This is in place to allow the upcoming Bulldozer chips to run the northbridge portion of the chip up to 3.2 GHz, and to give the CPU more bandwidth between the different busses on the board (eg. SATA, USB 3.0, and PCI-E connections).
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Look what I found today? My parental units are legends!!! #AspenMagazine #1980 Story has it that my parents had the first x-country ski school at the bottom of Aspen Mountain (where Starbucks is now) and they commuted to work from their TeePee nearby...


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Analysts left red faced as Reit rally misses Mexico
Analysts from Credit Suisse to Itau BBA who rode a wave of optimism over Mexico's real-estate investment trusts are now facing the sector's first potential annual decline.
A pending increase in US interest rates, sluggish domestic economic growth and an oil-price rout are stripping real-estate trusts of their lustre, forcing analysts to pare their target prices for the investments once designated as top picks.
"Investors are cautious about participating in the sector because of a nervousness over rates," Marco Medina, a Mexico City-based analyst at Ve Por Mas, said in a telephone interview. In addition, "many REITs raised capital and haven't used it. The square footage could get more expensive, bringing down returns on acquisitions."
Known as Fibras in Mexico, REITs package real-estate portfolios for sale on the stock market and pay out dividends based on rents they collect.
At current levels, shares for Fibra Uno Administracion, the largest REIT on the index, deliver a so-called dividend yield of 5.63pc, compared with 6.14pc for Mexican bonds due December 2024.
REITs were popular last year as Mexico's economy looked set to rebound and an opening of oil fields to private drilling heralded a boom for commercial property.
An index of nine REITs has fallen 6.6pc in the past 12 months, after gaining 162pc since the first Mexican REIT hit the market in 2011. The FRMEX Index hasn't had a full-year drop since then. Fibra Uno fell 19pc this year compared with a drop of 0.9pc in the IPC Index.
Medina is one of 16 analysts who recommend buying Fibra Uno, although he says he may suspend coverage of the stock until the Federal Reserve raises rates.
Another eight analysts have a hold recommendation on the shares and only one rates it a sell. That's still a lower rating than a year ago, when Fibra Uno had 16 buys, four holds and one sell.
Target prices have also dropped to 46.76 pesos from 52.97 pesos over the same period.
Real-estate securities like Fibhios, Fibra Shop and Fibra Sendero that have filed for public offerings since at least 2014 have yet to go to market, impeded by sentiment that's vulnerable to a Fed rate hike. Since the investments are considered like fixed income because of their large dividend yields, they are now less attractive when compared with rising government bond yields in Mexico, according to Signum Research.
"With the higher returns of long-term public debt, they aren't able to maintain competitive dividends," said Signum analyst Armando Rodriguez, who recommends holding Fibra Uno and Monday lowered his rating to hold from buy for another REIT -- Fibra Hotelera. "Institutional investors prefer the bonds to Fibras."
Itau, whose top Mexico property pick is Fibra Uno, may lower its target price as the stock takes a beating from concerns about the Fed's decision and an overcrowded REIT market. However, it may not change its outperform rating, according to Enrico Trotta, the bank's Latin American real estate sector head.
"The market was quite heated and now it's quite normal to see a stabilization or decrease in growth levels," Trotta said in a telephone interview from Sao Paulo.
Nevertheless, "Mexico is still in a pretty favorable position. Of course the reforms are taking a bit longer to happen, but on a relative basis when we look in the Latam space it's still doing well."
Itau's leading Mexico analyst in the sector, Ariel Amar, was not available to talk for this story.
Credit Suisse, which reiterated Fibra Uno as its top real estate pick in February, declined to comment for this article.
One Fibra at least is holding up well. PLA Administradora Industrial, the only one on the index posting positive returns this year as of last week, develops industrial real estate in Mexico, which is a more successful area than office space and shopping malls because rent is collected in strengthening dollars, according to Corp. Actinver SAB. The announcement of several new automotive plants in Mexico over the past year is also helping industrial property REITs, according to Actinver analyst Pablo Duarte.
Rodriguez of Signum doesn't see the REIT sector rebounding in the short term.
"I think analysts tried to change the mentality of investors," Rodriguez said. REITs "are going to take their time to come around." (Bloomberg)
Indo Business


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Saturday, September 08, 2007
Bad News Never Had Good Timing... Part 2.
I try not to think about the shootings because all it does is get me mad... with no way to release that anger towards the source... aka meaningless anger. So anytime that i got reminded of what happened, i just pushed it right out to avoid those feelings. No use getting upset for nothing. But after my 2 days off this week being spent at Tech, going to see the free concert put on by DMB for the students, you couldn't avoid thinking about it. Well... i couldn't at least. And i have a few things to add about the situation that i don't think too many people think about. Maybe no-one has thought of them. But there are a few points, none of which are related to another, so i'll just separate them by "-" marks in bullet form.
-Walking to the concert Jessy and I grabbed a Collegiate Times that we walked by, and one of the headlines on the front page was something to the effect of "Parents of Victims Call for Firings and Resignations." Now i understand that the families of all the victims must be living in a nightmare, but in my head... this is really only 1 person's fault... trying to throw the blame to someone who you can actually punish is just wrong. This whole situation is unthinkable. No-one can predict the future. Throwing the blame on people might make the victim's families have a little bit of closure, but at what cost? And it's not the same kind of closure as having the fuckhead here to punish. It would be like blaming the shower for getting your pillow wet, when you were the genius who went and laid down without drying your hair. Following the same example... you see water drops from your bed, through the hall, into the bathroom, and finally into the shower... and after finding out that water comes from the shower head, firing your shower for getting your hair wet, when there is clearly someone else to blame. (Note: i realize that the culprit of this little mystery story is in fact "you" but you get what i'm going for here)
-Virginia Tech failed to stop this kid from going on a rampage. But how many kids have they stopped from doing the same thing? Probably hundreds. Probably thousands. Probably Ten-thousands. Who knows... and who cares. Even if they have stopped 1 person from lashing out at society, they are successful. There are plenty of messed up people out there, and VT has surely helped a lot of them with their counseling center. All the public cares about is that Tech "screwed up" and missed all his signs. But they didn't. They tried to get him help. "You can lead a horse to water, but you can't make him drink." I commend Virginia Tech for help the thousands of kids who need help dealing with their problems... in fact, i commend ANYONE who helps ANYONE ELSE through a tough time. Whether it's just a phone call to check on someone you haven't talked to in a while, or helping an old lady across the street(sorry it's cliche, but you get my point).
-(Continuing on with the previous bullet, but in a different direction): Counselors help kids in many ways, but you really can't tell how many violent acts they have prevented. The only statistics that people ever see are the outcome of someone slipping through the cracks. You can't tell who would've been a rapist, murderer, or a thief... but after something happens, all the signs point to something bad happening... If you could tell who is going to be a rapist, murderer, or a thief... then this world wouldn't need counselors and therapists, etc. But the main point here is that the numbers only reflect all those that slipped through. I like to think that the majority of people that have the potential to do something bad that get help, are actually stopped with the right help. But as i said, we will never know.
-After thinking about all this on my 4 hour car ride home, i can't help but think about how much my life would've been different if this had happened 2 years ago. Even though i feel a huge connection with Tech, and still consider myself a Hokie for life... i have experienced this situation at an arm's distance... with my only connection with Tech right now being Jessy... she's really the only person down there that i even know anymore... But what if that was 2 years ago? How would i convince Mom to let me go back? Would i even want to go back? Would i know someone in one of those rooms? But i wasn't there. Which i'm thankful for.
So that's it. I know this not going away, at least for the time being... but i think i'm done for now. But yeah, it's not over with, and i don't think i'll ever be able to help those who were really affected...
But i will still try.
5 comments:
- Neva said...
YOu are a very deep thinker and I happen to agree with you....very well put....so here is an award for you.....
The 'Power of Schmooze Award' is The Award for bloggers who "effortlessly weave their way in and out of the blogosphere, leaving friendly trails and smiles, happily making new friends along the way. They don't limit their visits to only the rich and successful, but spend some time to say hello to new blogs as well. They are the ones who engage others in meaningful conversations, refusing to let it end at a mere hello - all the while fostering a sense of closeness and friendship".
If you would like to add it to your template you can go to my blog and get the picture...or not.
- Jessy said...
Truly, the biggest bone I have to pick is with the state government. He was committed, and instead of following up with him to ensure that he sought court-ordered treatment, they basically dumped him off on Cook Counseling Center, which didn't even have a staff psychaitrist at the time.
Secondly, he never showed any outward signs or implicit threats towards others- except for in his writings. His emotional troubles made it so he never spoke to anyone, never truly confided in anyone, he never had a single friend. How do warning signs present themselves in someone who cannot use words for expression?
Really... I mean REALLY... are we supposed to be mind readers?
Be happy that you're not in Blacksburg. Every edition of the CT has had a news item about something related to what happened, which makes it hard to forget about it, even for a day.
- Tom said...
I think if you look deep enough at this type of stuff, you'll see that basically everything that happens AFTER a major tragedy in relation to placing blame is politically motivated. In the end, you'll find the people making the most noise (or encouraging the people to make noise) are the ones that stand to gain something from kicking out those people currently in power. Greed for power hides itself in everything.
- MotherOf3Guys said...
Wow, what deep thoughts... I'm proud of the thoughts you've given this matter. It does seem to strike very close to home and, just like the pentagon disaster on 9-11, it seems pretty darned close to home. I think because we live in this area and because we have some connection to Tech, it makes it a lot harder to forget. (That what if it was 2 years earlier..scares the &*$% out of me!) I can't even imagine what those famlies feel and how they are coping, but the one fact is that nothing can now change those facts. I'm doubly impressed with the other sons comments on power and greed... We raised some pretty terrific guys and I'm proud of all three of them!
- Jerry said...
Unfortunately, there is only one person to blame for the tragedy. However, the overall system that was in place to protect us from this sort of tragedy failed due to loopholes in state gun laws. The federal laws enacted to prevent people deemed mentally sick from obtaining firearms were enforced due to information not being shared.
Or perhaps some of the blame lies in a sick society or a society with lots of sick people.
Gun crime is extremely rare in Britain, and handguns are completely illegal. The ban is so strictly enforced that Britain's Olympic pistol shooting team is barred from practicing in its own country. Britain's 46 homicides involving firearms was the lowest total since the late 1980s. New York City, with 8 million people compared to 53 million in England and Wales, recorded at least 579 homicides last year. MSNBC Reports.
That's 1 in 13,817 persons in NYC and 1 in 1,152,174 persons in Britain.