text:
|Publication number
|Publication type
|Application number
|Publication date
|Jul 30, 2002
|Filing date
|May 25, 1999
|Priority date
|May 25, 1999
|Fee status
|Publication number
|Dhiraj Mallick, Jacob Thomas, Rajesh Khanna, Anil L. Pandya, Satish Kumar Raj
|Original Assignee
|Advanced Micro Devices, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (9), Referenced by (74), Classifications (7), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
1. Field of the Invention
This invention relates to tools for designing digital circuits and analyzing digital circuit designs, and particularly to reducing transistor channel length in digital circuit designs.
2. Description of the Related Art
One of the goals in designing synchronous integrated circuits, and particularly very large scale integrated (VLSI) circuits, including application specific integrated circuits (ASICs), general purpose processors, embedded processors, and digital signal processors (DSPs), is high speed operation. To that end, a variety of computer aided design (CAD) tools are used to design, analyze, and simulate integrated circuits. In the process of designing integrated circuits, often referred to as electronic design automation (EDA), a particular integrated circuit (or section thereof) is typically described by a netlist. The netlist is a list of circuit components or cells and interconnections between the circuit components. The various cell input terminals and output terminals through which cells are connected to each other are often referred to as pins or nodes. Determining how fast a given circuit can operate depends in large part on the timing of signals arriving at, and being transmitted from various cells in the circuit. At least two main approaches are used in EDA for timing verification and analysis during the circuit design process, dynamic timing and static timing.
Traditionally, dynamic timing analysis has been used to verify the functionality and timing of an entire design or blocks within a design. Dynamic timing analysis uses vectors provided by the designer and performs logic simulation with timing values to verify the timing behavior of the circuit. Dynamic timing analysis is difficult to use because the designer must provide the input signal patterns and analyze the output wave forms to verify that the circuit functions correctly at the intended speed. Dynamic verification has the advantage that the timing behavior of any design can be analyzed and dynamic verification offers a high degree of accuracy by correctly modeling the Boolean interaction between signals.
However, designers have to create separate timing and functional vectors for dynamic timing analysis, and thus the quality of the dynamic timing analysis is limited by the input stimuli provided by the designer. Additionally, it can be difficult to create timing vectors that will exercise each path in the design exhaustively. For example, if the designer does not correctly specify the input condition that triggers the worst-case delay path in the circuit, the dynamic timing analysis may result in an optimistic value for the circuit speed. Finally, dynamic timing analysis requires extensive computer resources because a large number of input signal patterns must be simulated to offer a high degree of confidence in the results. The vector generation problem is magnified as the size and complexity of designs increase. The advent of larger designs and enormous vector sets make dynamic simulation a serious bottleneck in design flows.
To combat many of these problems, static timing verification is increasingly being used. Static timing analysis is an exhaustive method of analyzing, debugging and validating the timing performance of a design. This is achieved by breaking down the design into sets of paths. A static timing analyzer assesses circuit timing performance by relying upon timing attributes, as specified in a library of timing models, for individual circuit components in the netlist. The library of timing models includes timing information for each circuit component in the netlist. The timing information includes such information as the input pin capacitance, input-to-output delay, and output drive strengths. Combining this library along with a design netlist, a static timing analyzer generates critical path timing information statically without knowledge of the design's logical functionality. The delay of each path in the design is calculated and checked against timing assertions for any possible violation that would effect performance or limit operating frequency. Different types of checks that can be performed by a static-timing analysis tool include setup time (the length of time that a data input pin must be stable before an active clock transition), hold time (the length of time that a data input pin must be stable after an active clock transition), recovery (the length of time that an asynchronous control input pin must be stable before a clock active-edge transition), removal (the length of time that an asynchronous control input pin must be stable after a clock-active edge transition) and clock pulse width. Static timing analysis is exhaustive in that every path in the design is checked for timing violations. This is a benefit over dynamic simulators, which would require a large number of vectors in order to provide the same level of timing coverage. Since static timing analysis is not based on functional vectors, it is typically fast and can accommodate large designs. Static timing analysis does suffer from at least one drawback, false paths. Because the analysis typically considers all possible paths, some paths which will logically never be used can be included in the analysis unnecessarily.
Static timing verification can identify those cells and paths that are critical to the operation, but that is only part of the process. Design changes must be made to reduce or eliminate timing violations. One solution to improve timing along a critical path is to replace one or more of the field effect transistors (FETs) along the path (e.g., transistors in a cell along the path) with a similar transistor having a shorter channel length between the source and drain regions, thereby reducing the channel transit time (i.e., the average time required for an electron to traverse a FETs channel from source to drain), as is well know by those having ordinary skill in the art of circuit design. Because the transit time is reduced, propagation times associated with the transistor are improved, and paths that previously had timing violations can be brought within timing requirements.
Unfortunately, replacing a given transistor with a similar transistor having a shorter channel length does have at least one drawback. Leakage currents associated with a transistor tend to increase with decreasing channel length. For example, one common component to transistor leakage currents, a subthreshold channel current, is known to be inversely proportional to channel length. Increased leakage currents are a concern of integrated circuit designers because the integrated circuit usually has a defined power budget, e.g., approximately 8 W for a processor designed for portable computers, and any increase power drain associated with leakage currents must fall within the power budget.
Accordingly, it is desirable to have integrated circuit design tools and techniques for selective sizing down the channel lengths of transistors in timing critical paths in the integrated circuit, while staying within a power budget.
It has been discovered that tools and techniques used in conjunction with integrated circuit path timing information can selectively reduce the channel length of transistors in cells associated with the most critical paths in an integrated circuit, while keeping the overall integrated circuit design within a specified power budget. Moreover, by targeting pins of cells (and thus their associated transistors) that are used by multiple paths, and/or that offer the greatest potential speed improvement, timing violations along critical paths can be reduced or eliminated with a relatively few number of replacements. Paths within a certain timing violation range are selected for analysis. The pins within those paths are ranked by pin criticality, which can depend on, for example, the number of times a particular pin occurs in any path, the timing enhancement associated with replacing a cell having that pin, and the impact of replacing a cell having that pin would have on the power budget. Transistors within cells (or entire cells) associated with pins are replaced based on the pin criticality until timing improvements are sufficient to remove a path from the range of paths being examined. Successive paths, and ranges of paths are analyzed until the power budget is exceeded, or no more improvements can be made.
Accordingly, one aspect of the present invention provides a method for selectively decreasing a channel length of a transistor to be used in a semiconductor device. A timing database is provided. The timing database includes a plurality of circuit paths, at least two circuit paths each representing a path through a plurality of pins in a circuit design. Each of at least two of the plurality pins in each of the at least two circuit paths is associated with one of an input and an output of a respective cell in the circuit design. Each respective cell has at least one transistor, and each of the at least two circuit paths has an associated timing violation providing information about violation of at least one timing assertion. A subset of circuit paths is selected from the timing database. The subset includes at least one of the at least two circuit paths. The timing violation of each circuit path in the subset is within a range of timing violations. A pin criticality for each pin in each path within the subset is determined. At least one cell associated with a pin in the subset of circuit paths is replaced with a cell having a transistor with a reduced channel length. Replacement depends on the pin criticality of the pin associated with the at least one cell.
In another aspect of the invention, an apparatus includes a processor, a memory coupled to the processor, and a circuit design program at least partially storable in the memory and executable on the processor. The program includes a path selection routine for selecting a plurality of paths in a circuit design, at least one path including a plurality of pins, and having an associated timing violation providing information about violation of at least one timing assertion. The program also includes a pin criticality routine for determining a pin criticality for at least one pin in the at least one path, and a cell replacement routine for selectively replacing at least one cell associated with the at least one pin in the at least one path with a cell having a reduced channel length transistor. Replacement depends on the pin criticality of the at least one pin in the at least one path.
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
FIG. 1 is a block diagram of a computer system for implementing the tools and techniques of the present invention.
FIG. 2 is a flow chart illustrating an integrated circuit cell swap procedure.
FIG. 3 is a flow chart illustrating a portion of an integrated circuit design flow, including the integrated circuit cell swap procedure shown in FIG. 2.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to one having ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to unnecessarily obscure the present invention.
Because of the complexity of designing integrated circuits, many of the design steps are performed on a computer system. FIG. 1 illustrates a block diagram of a computer system 100 for implementing the design tools discussed below. Computer system 100 includes a processor 110 and a memory 120 coupled together by communications bus 105. Processor 110 can be a single processor or a number of individual processors working together. Memory 120 is typically random access memory (RAM), or some other dynamic storage device, and is capable of storing instructions to be executed by the processor, e.g., cell replacement software 130, and information used by the instructions, such as timing database 140. Memory 120 is also used for storing temporary variables or other intermediate information during the execution of instructions by the processor 110.
Cell replacement software 130 is one example of a software design tool, and in the present example, it is illustrative of a cell replacement method implemented in software. Those having ordinary skill in the art will ready recognize that the techniques and methods discussed below can be implemented in software using a variety of computer languages, including, for example, traditional computer languages such as assembly language, Pascal, and C; object oriented languages such as C++ and Java; and scripting languages such as Perl. Timing database 140 is one example of information that can be used by software such as cell replacement software 130 as part of the integrated circuit design process. Additionally, software 130 can be provided to the computer system via a variety of computer readable media including magnetic storage media (e.g., hard disk 158, a floppy disk, etc.), optical storage media (e.g., CD-ROM 160), and communications media conveying signals encoding the instructions (e.g., via a network coupled to network interface 154).
Computer system 100 also includes devices such as keyboard 150, mouse 152, network interface 154, graphics & display 156, hard disk 158, and CD-ROM 160, all of which are coupled to processor 110 by communications bus 107. It will be apparent to those having ordinary skill in the art that computer system 100 can also include numerous elements not shown in the figure, such as additional storage devices, communications devices, input devices, and output devices, as illustrated by the ellipsis shown.
Timing database 140 includes information produced by a static timing analyzer based on a netlist of the circuit design provided to the static timing analyzer. Examples of commercially available static timing analysis tools include PrimeTime by Synopsys, Inc., QuickPath by Mentor Graphics Corporation, and Afirma Pearl by Cadence Design System, Inc. These or other static analyzing tools provide pathbased, or in some cases node or arc based timing information about the integrated circuit design. Typically, timing information produced by these tools, and included in timing database 140, is in the form of a list of paths through the integrated circuit. Each path is defined by the nodes or pins associated with circuit elements or cells that are traversed by the path. Each pin is usually either an input to or an output from a cell, and thus each pin can have a timing delay contribution associated with it. The timing delay contribution for a given pin typically represents any timing delay associated with the portion of the circuit path between the preceding pin and the current pin. The cumulative propagation delay of the path is recorded for each path, and usually provided in units of picoseconds (ps). The timing constraints or assertions of the various cells along the path form a timing budget within which the circuit should perform. Additionally, the overall frequency of operation of the integrated circuit can contribute to the timing budget. Those paths having propagation delays that exceed the available budget are said to have a timing violation, usually indicated by the amount of time the budget is exceeded. Paths that exceed the budget typically have negative violation numbers, while paths that are within the budget are described with positive violation numbers. Note that the propagation delay of a path is often referred to as its timing violation, or violation number, regardless of whether it actually violates a timing constraint.
FIG. 2 is a flow chart illustrating an integrated circuit cell swap procedure utilizing information from timing database 140. As indicated by cell replacement software 130, some or all of the procedure illustrated in FIG. 1 is usually performed by software. Additionally, the examples described below will focus on static timing analysis that provides information about setup time and hold time violations, but those having ordinary skill in the art will readily recognize that the tools and techniques described can be applied to static timing analysis data based on a variety of timing assertions.
Although there are many design, fabrication, and operation factors that will effect the performance of a cell, and thus effect the results of static timing analysis of that cell, the cell swapping tools and techniques of the present invention focus on a particular aspect of cell design, constituent transistor channel length. Thus, because the cell swapping tools and techniques do not directly consider parameters such as operating voltage, operating temperature, and fabrication process, the effect of these parameters on the timing characteristics of the cells, and thus the effect on the cell swapping choices made, are integrated into the development of the timing database.
For example, since the setup time is the minimum length of time that a data input pin must be stable before the active clock edge transition, it is preferable to have setup time static timing analysis based on operating and fabricating conditions that are likely to lead to generally longer switching times, i.e., slower cells, since the longer switch times increase the likelihood that signals may not get,to a memory cell on time. Such analysis provides the designer with worst case (or at least worst usable case) setup time information. Thus, in order to prepare the proper database, static timing analysis is conducted in the "typical corner" where, for example, the operating voltage is relatively low, the operating temperature is relatively high, and the fabrication process is a typical process. Note that the set of parameters is typically referred to as a "corner" because it is defined by three coordinates in a parameter space: voltage, temperature, and process. With worst case setup time provided in the timing database, the cell swapping tools and techniques can proceed to improve setup times by selectively increasing transistor switching speeds.
Similarly, worst case (or at least worst usable case) hold time information should be included in the timing database. Since hold time is the minimum length of time that a data input pin should be stable after the active clock transition, hold time information should be based on static timing analysis in a fast corner, that is with an operating voltage, operating temperature, and fabrication process chosen to produce the fastest (or at least fastest usable) switch times. Thus, fast corner static timing information provides the hold time slack for a pin or cell, that is the amount of time a given cell could be speed up without causing a path through the cell to have a hold time violation. As is seen in FIG. 3 (and described below) combining static timing analysis for the different corners is part of the design flow within which the cell swapping procedure is implemented.
With the requisite timing data provided by timing database 140, integrated circuit cell replacement procedure 200 begins at 210 with the selection of a subset of paths. Since a given circuit design may have numerous paths, a subset is chosen in order to efficiently target the paths with the worst timing violations. Based on a specified tolerance, e.g., 30 ps, a subset of paths is selected from timing database 140, each having a timing violation within the range indicated by the tolerance. For example, if the worst timing violation is −199 ps, and the specified tolerance is 30 ps, than the specified range is −199 ps to −170 ps, and the subset includes paths whose timing violations fall within this range. Note that depending on the number of paths in timing database 140, the complexity of the integrated circuit design, and the desired efficiency of operation, a smaller or larger tolerance can be specified. In fact, a tolerance large enough to include all violating paths (e.g., 200 ps for the example above) could be specified.
The paths in the subset are optionally sorted by timing violation as indicated in 220. Note that sorting is optional because, for example, the paths may already be provided in a sorted form from timing database 140 (thereby obviating the need for additional sorting) or the timing violation range that defines the subset may be so small that sorting is unnecessary. Nevertheless, it is desirable to have the paths sorted by timing violation so that the cell replacement procedure can operate on those paths having the worst timing violations first. Additionally, those having ordinary skill in the art will readily recognize that a variety of the steps illustrated in FIG. 2 can optionally be performed, or can be replaced by one or more equivalent steps.
Next, 230 indicates that an incidence count is determined for each of the pins in each of the paths in the subset. Since any given pin can occur in more than one path, e.g., an output pin on a cell having multiple inputs, replacement priority can be given to those pins whose replacement will benefit the most paths in the subset. Thus, each pin in the paths is given an incidence count, indicating the number of paths in which the pin is used. Note that the paths checked during the incidence count are typically confined to the paths that are in the subset, but incidence counting could include all paths in the integrated circuit design, or a smaller or larger subset of paths as desired.
The incidence count for a pin is one way to rank a pin's criticality in a particular path. Other factors contributing to a pin's criticality, and thereby the desirability of replacing its associated cell, include the potential speed increase of swapping cells (which may vary from pin to pin), the available hold time slack for the pin, power consumption of the cell associated with the pin, and a variety of other factors. In a typical example, the product of a pin's incidence count and the associated improvement are used to determine the pin criticality. Whatever method used, the pins in the paths are sorted by pin criticality in 240 so that within each path, the most critical pins are first to be examined and their associated cells possibly replaced.
As indicated by 250, cell replacement begins with the most critical pin, as determined by the pin criticality, in the path with the worst timing violation. Although the goal is to selectively replace at least one transistor associated with the pin, replacement is typically performed on the entire cell. For example, if the most critical pin in the path with the worst timing violation is one of the input pins of a two-input NAND gate, the entire gate would be replaced with a similar version of the gate, but using transistors in which the channel length has been reduced so as to provide a speed increase. Those having ordinary skill in the art will recognize that number of constituent transistors, including all of the constituent transistors, of a cell can be replaced. Additionally, other timing comparisons may be performed before or in conjunction with a cell replacement, such as, for example, determining the effect of replacement on the hold time slack of the path under consideration. If a replacement is made, the timing violation of the path is updated to reflect the improvement. Additionally, the timing violation of all other paths including the transistor or cell is typically updated to reflect the improvement. As noted above, the timing values will depend on the corner in which the static timing analysis is performed. So, for example, the path timing violation can be updated subsequent to a cell replacement by decreasing the magnitude of the violation number based on the timing difference between the regular cell and the shorter channel length cell as analyzed in the aforementioned typical corner. This would provide a conservative estimate of the improvement. Note also that this type of improvement information can be the same improvement information used to determine pin criticality. The hold time slack available can also be revised based on fast corner timing information. A count of the cells/transistors that have been replaced is maintained for comparison with the power budget.
That comparison is performed in 260. If the increased power consumption associated with replacing the cell is greater than the power budget, the process ends. The replaced cell can be returned to its normal version (not shown) so as to bring the circuit design back within its power budget. If the budget has not been exceeded, the timing violation of the path containing the pin for which a cell was replaced is examined in 270. If the updated timing violation causes the path to no longer fall within the specified range of the subset, no additional swapping needs to be performed, and the path can be removed from the subset, or simply ignored for the remainder of path analysis for the subset. Additionally, one or more additional paths may be removed from the subset if those paths were effected by the replacement to the extent that their respective updated timing violations cause the paths to no longer fall within the specified range of the subset. Note that the subset updating described herein can take place at 250, at 270, or at a variety of other points in the process. Whether there are any paths remaining in the subset is determined in 290. If there are still paths within the subset, a next path is chosen in 295, typically the path with the next worse timing violation, and the procedure returns to 250. If there are no more paths to be analyzed in the subset, a new timing violation range is selected, e.g., the next lowest range based on the specified tolerance, and the procedure returns to 210. If there are no more paths to examine, and/or the specified range is a range that should not be analyzed, e.g., positive timing violation numbers, the procedure can end (not shown).
When it is determined in 270 that the cell replacement has not improved the path sufficiently to render its timing violation outside the specified range of the subset, operation proceeds to 280 where it is determined whether there are additional pins to be examined in the path. If there are, a next pin is chosen in 285, typically the next most critical pin, and the procedure returns to 250. When there are no pins remaining in the path, 290 determines whether there are additional paths in the subset to be examined, and operation proceeds as described above. Note that the procedure can end if the a path cannot be improved beyond the subset (not shown) or it may continue as shown with the hope that other paths in the subset can have their timing violations reduced.
FIG. 3 is a flow chart illustrating a portion of an integrated circuit design flow 300, including the integrated circuit cell swap procedure shown in FIG. 2. FIG. 3 illustrates one of the many possible ways in which cell replacement procedure 200 can be integrated into an integrated circuit design flow, as will be readily recognizable to those having ordinary skill in the art. This portion of the flow begins at 310 with the production of a static timing database for the aforementioned typical corner, although timing analysis can be performed for some corner other than the typical corner if desired. The timing database produced is the basis for the timing database that will ultimately be used to perform cell swap 200. The timing database can then be optionally filtered at 320 according to limitations or design constraints imposed by the designer. Note that between steps that are typically performed by different pieces of software, e.g., 310 and 320, there can be intermediate steps that, for example, convert the format of the output from one tool to a format usable by the next tool. Such intermediate steps have been left out of FIG. 3 for clarity, but will be readily apparent to those having ordinary skill in the art.
322 represents a design constraint that the integrated circuit designer chooses to impose on some or all of the circuit design. Typically, the constraint is limited to certain portions of the circuit design, thus making application desirable through a filter process, instead of through the netlist provided to the static timing analyzer for 310. In general, the filtering process is a way by which circuit designers can have the flexibility to control various aspects of the design. For example, if a designer knows that certain paths will absolutely have to be changed, absolutely cannot be changed, or are false paths, the filtering process can accommodate those constraints. The filter can also be used to remove certain paths having certain timing violations from the timing database, thereby making the timing database smaller and allowing swapping procedure 200 to be performed more quickly.
One example of a use for the filtering step is special handling for buses in a circuit design. Since communications busses typically include multiple wires that transmit signals (e.g., the individual bits of a multi-bit bus) simultaneously, designers often want the timing characteristics of the paths along each of the lines of the bus to be uniform. Thus, a change to a cell on one bus line, can prompt similar changes on the other bus lines so the overall bus performance is more uniform, even though the other lines might not otherwise need the cell change. One way to accomplish this is to use the filtering option to adjust the timing violation of the paths associated with the additional bus lines to match that of the path having a legitimate timing violation. Thus, by "tricking" the cell swap procedure into replacing cells on these other paths, when normally their timing violations would not prompt replacement, the bus timing characteristics can be kept more uniform. Other examples of design conditions that can be addressed through the filter process include: clock low latch paths, half-cycle paths, and known silicon critical paths.
Thus, once a special design constraint is determined, an appropriate new netlist is generated at 324. Static timing information is determined for paths effected by the constraint in 326, and filter information is generated based on the new timing analysis in 328. Note that in some instances, filter information can be specified directly, thereby avoiding 324 and 326. The filter information is used in 320 to adjust the information in the timing database as appropriate. Since the filtering process is optional, 320 can be avoided, but in either case (i.e., filtering or not) the typical corner timing information can be passed on to 332. Fast corner timing information is generated in 332-336. Whether based on the filtered typical corner database, and unfiltered typical corner database, or even a separate input (not shown), a control file is developed and supplied to static timing analysis 334. As mentioned above, the fast corner timing database provides hold time slack information. The database is optionally filtered in 336, in a manner similar to that outlined in 322-328, and then combined with the typical corner database in 330. That combination yields timing database 140 shown in FIG. 2, which is used by cell replacement procedure 200 as previously described. Cell database 350 includes information about each type of cell in at least two different versions (one where transistors have normal channel lengths, and one where transistors have shortened channel lengths), and can also have cell information for a variety of corners, e.g., typical and fast corners. The results of the swapping procedure are used to produce a new netlist 340 which can then be used for additional timing verification (e.g., another iteration of process 300) or other circuit analysis and verification. Additionally, netlist 340 can serve as the final netlist for circuit layout and fabrication 370.
Those having ordinary skill in the art will readily recognize a number of variations in implementation and parameter dependence. For example, the cell swapping procedure can be implemented with more than one alternative channel length. The design flow could begin with all of the cells being a short channel length version, and then proceed to replace the short channel length versions with normal versions where tolerable. Replacement can be based on cells (which include logic gates, a flip-flops, latches, etc.) or may be performed an a larger scale with macros. The design flow can be applied to an entire integrated circuit design, or one or more blocks within that design. Each specified range of paths examined can be based on the same tolerance, or successively different tolerances. Other tools can be utilized at various stages in design flow 300. Some or all of the procedures described herein can be implemented in software and executed on a computer system.
The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope and spirit of the invention as set forth in the following claims.
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|Process monitoring circuit and method
|Sep 13, 2005
|Oct 21, 2014
|Infineon Technologies Ag
|Method and device for checking a circuit for adherence to set-up and hold times
|Nov 27, 2012
|Oct 28, 2014
|United Microelectronics Corporation
|Memory and operation method thereof
|Apr 3, 2013
|Dec 23, 2014
|United Microelectronics Corporation
|Method and device for pulse width estimation
|Nov 7, 2013
|Feb 3, 2015
|United Microelectronics Corp.
|Method and circuit for optimizing bit line power consumption
|Dec 7, 2012
|Feb 10, 2015
|United Microelectronics Corp.
|Memory device and method for driving memory array thereof
|Aug 3, 2012
|Mar 3, 2015
|United Microelectronics Corporation
|Voltage regulating circuit configured to have output voltage thereof modulated digitally
|Jul 23, 2012
|Apr 14, 2015
|United Microelectronics Corporation
|Temperature sensor using delay circuit
|Sep 20, 2011
|May 12, 2015
|United Microelectronics Corporation
|Circuit structure of test-key and test method thereof
|Dec 7, 2012
|May 12, 2015
|United Microelectronics Corp.
|Memory device and driving method thereof
|Jul 4, 2013
|Aug 11, 2015
|United Microelectronics Corporation
|Memory cell array operated with multiple operation voltage
|Dec 20, 2013
|Sep 1, 2015
|International Business Machines Corporation
|Stacked multiple-input delay gates
|Jan 13, 2014
|Sep 22, 2015
|United Microelectronics Corp.
|VCO restart up circuit and method thereof
|Mar 12, 2003
|Sep 18, 2003
|Sequence Design, Inc.
|Method and apparatus for interconnect-driven optimization of integrated circuit design
|Apr 11, 2003
|Oct 16, 2003
|Hahn Mark Steven
|Method and system for logic-level circuit modeling
|Aug 28, 2002
|Mar 4, 2004
|Richard Schultz
|Static timing analysis and performance diagnostic display tool
|Dec 4, 2002
|Jun 10, 2004
|Heather Bowers
|Method and apparatus for analyzing post-layout timing violations
|Apr 4, 2003
|Oct 7, 2004
|Bradfield Travis Alister
|System and method for achieving timing closure in fixed placed designs after implementing logic changes
|Jul 7, 2003
|Jan 13, 2005
|Paul Barnes
|Cell replacement algorithm
|Aug 22, 2003
|Feb 24, 2005
|International Business Machines Corporation
|Method for determining and using leakage current sensitivities to optimize the design of an integrated circuit
|Jan 3, 2005
|May 26, 2005
|Lsi Logic Corporation
|Static timing and risk analysis tool
|Jul 28, 2005
|Dec 1, 2005
|Heathers Bowers
|Method and apparatus for analyzing post-layout timing violations
|Aug 27, 2004
|Mar 2, 2006
|Barney C A
|System and method for repairing timing violations
|Sep 23, 2004
|Mar 23, 2006
|Xiaonan Zhang
|Standard cell library having globally scalable transistor channel length
|Nov 8, 2004
|May 11, 2006
|Lsi Logic Corporation
|Method of associating timing violations with critical structures in an integrated circuit design
|Mar 16, 2005
|Jun 1, 2006
|Fujitsu Limited
|Method for correcting timing error when designing semiconductor integrated circuit
|Sep 13, 2005
|Jun 1, 2006
|Infineon Technologies Ag
|Method and device for checking a circuit for adherence to set-up and hold times
|Aug 31, 2006
|Aug 30, 2007
|Fujitsu Limited
|Critical path estimating program, estimating apparatus, estimating method, and integrated circuit designing program
|Sep 20, 2006
|Sep 27, 2007
|Fujitsu Limited
|Method and apparatus for repeat execution of delay analysis in circuit design
|Sep 18, 2006
|Mar 20, 2008
|Harris Edward B
|Method and apparatus for designing a logic circuit using one or more circuit elements having a substantially continuous range of values
|Mar 24, 2008
|Sep 24, 2009
|International Business Machines Corporation
|Method and system for achieving power optimization in a hierarchical netlist
|Aug 14, 2008
|Feb 18, 2010
|International Business Machines Corporation
|Method of Minimizing Early-mode Violations Causing Minimum Impact to a Chip Design
|Apr 30, 2009
|Aug 26, 2010
|Mcmurchie Larry E
|Timing-optimal placement, pin assignment, and routing for integrated circuits
|May 3, 2010
|Jan 13, 2011
|Taiwan Semiconductor Manufacturing Company, Ltd.
|Fixing Full-Chip Violations Using Flip-Flops
|Dec 22, 2010
|Jun 28, 2012
|Advanced Micro Devices, Inc.
|Method and apparatus for addressing and improving holds in logic networks
|Dec 20, 2013
|Jun 25, 2015
|International Business Machines Corporation
|Stacked multiple-input delay gates
|May 31, 2007
|Dec 5, 2007
|SGS-THOMSON MICROELECTRONICS S.r.l.
|Method for designing semiconductor circuit devices to reduce static power consumption
|May 31, 2007
|Jun 2, 2010
|STMicroelectronics Srl
|Method for designing semiconductor circuit devices to reduce static power consumption
|U.S. Classification
|716/113, 716/122
|International Classification
|Cooperative Classification
|European Classification
|Jul 27, 1999
Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MALLICK DHIRAJ;THOMAS JACOB;KHANNA RAJESH;AND OTHERS;REEL/FRAME:010119/0071;SIGNING DATES FROM 19990715 TO 19990719
|Dec 28, 2005
|Fee payment
Year of fee payment: 4
|Aug 18, 2009
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS
Free format text: AFFIRMATION OF PATENT ASSIGNMENT;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:023119/0083
Effective date: 20090630
|Dec 22, 2009
|Fee payment
Year of fee payment: 8
|Jan 2, 2014
|Fee payment
Year of fee payment: 12


text:
|Half Baths
|Property type
|Minimum Stay
|7 nights
The lodge has been furnished to exceptionally high standards and is well equipped, including calor gas central heating and wooden flooring throughout. Three bedrooms, attractive double with TV, twin bedded with TV point, and L-shaped single bedded with additional pull-out bed converting to compact double. Spacious, high quality bathroom/wc with shower attachment. Very spacious and attractively furnished living/dining room with black leather suite, TV, DVD, CD, iPod docking station and Wi-Fi connection. Dining area with seating for six. Fully fitted kitchen area with elec cooker, gas hob, microwave and slimline dishwasher. Utility room/wc with washing machine and tumble dryer. Magnificent lake and countryside views can be enjoyed from the property, and French doors lead onto veranda with table and chairs. It also has a private lawned area to side and parking for 2/3 cars.
Classification: Ground floor: (Kitchen(cooker(ceramic), oven, microwave, dishwasher, washbasin), Living/diningroom(TV, DVD player, CD player), bedroom(double bed, TV), bedroom(2x single bed, TV), bedroom(single bed, single fold-away bed), bathroom(bathtub or shower, washbasin, toilet), pantry(dryer, washing machine))
conservatory/veranda, garden doors, garden furniture, parking, high chair
These costs are charged on site. They are not included in the rental price.:
Deposit; No
Final Cleaning; Included
Pets; Max. 1; £ 30/Stay
Bed linen; Included
Bath towels; Included
Kitchen linen; Included
Electricity; Included
Gas/Oil; Included
Wifi; Free
Tourist tax; No
Es hat uns allen (Eltern und 3 erw. Kinder sehr gut gefallen, sehr ruhig Umgebung, an den beiden kleinen Seen reichhaltige Vogelwelt, gute Ausflugsmöglichkeiten.
Die Ausstattung ist sehr gut

subset: commoncrawl


text:
April's Skies
, I am also including two other photographs taken on the 26th April at sunrise, just because they were stunning, I think End of skies! 🙂 Advertisements
, I am also including two other photographs taken on the 26th April at sunrise, just because they were stunning, I think End of skies! 🙂 Advertisements
Back again, with 32 sky pictures, I'll insert these at the end! I was taken to Wonderwool Wales, yesterday, by dd1, and had an amazing time. We oohed and ahhed, […]
It's been ages since I last posted, very sorry about that folks, the moving and sorting out of the new place is taking a little longer than planned. Once we […]
Hello again, sorry there has been a gap, but packing up and moving can sort of take over!! The skies for the start of February… The weather has been […]
Well the thing about moving is, getting organised! I have started to tidy away things, rule is ;- If it hasn't surfaced in two years and we really don't use […]
Weaving photos first, I finished the cloth by washing it with a squirt of Fairy liquid, the drape was lovely and the colour remained reasonably fast. Then came the […]
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text:
Results 1 to 3 of 3
Thread: DB2 date conversion
01-10-14, 07:19 #1Registered User
- Join Date
- Dec 2013
- Posts
- 11
Unanswered: DB2 date conversion
//Hi All Please find the code and please give me reply as soon as possible. i am inserting the Date format in string format i.e.'1/20/2014 12:00:00 AM'. but i am getting error
CREATE or Replace FUNCTION TestPmcDate (timestamp_in VARCHAR(30))
Contains SQL
Begin Atomic
if timestamp_in ='MM-DD-YYYY HH24:MIS AM' Then
VALUES( SUBSTR(timestamp_in, 1, 2),
SUBSTR(timestamp_in, 4, 2),
SUBSTR(timestamp_in, 7, 4),
SUBSTR(timestamp_in, 12, 2),
SUBSTR(timestamp_in, 15, 2),
SUBSTR(timestamp_in, 18, 2),
SUBSTR(timestamp_in, 21, 2));
End if;
Return timestamp_in;
------------------------------ Commands Entered ------------------------------
select TestPmcDate('1/20/2014 12:00:00 AM')from sysibm.sysDummy1@
select TestPmcDate('1/20/2014 12:00:00 AM')from sysibm.sysDummy1
SQL0180N The syntax of the string representation of a datetime value is
incorrect. SQLSTATE=22007
01-10-14, 08:18 #2Registered User
Provided Answers: 11
- Join Date
- Apr 2006
- Location
- Belgium
- Posts
- 2,540
..and please give me reply as soon as possible..
if you would take the time to read some docs or check/analyze the message..
this is not the wikipedia of DB2...
nice of you to indicate the "please"
in the infocenter, there are chapters talking about this, PLEASE take to time to read
Date and time formats by territory code - IBM DB2 9.7 for Linux, UNIX, and WindowsBest Regards, Guy Przytula
Database Software Consultant
Good DBAs are not formed in a week or a month. They are created little by little, day by day. Protracted and patient effort is needed to develop good DBAs.
Spoon feeding : To treat (another) in a way that discourages independent thought or action, as by overindulgence.
DB2 UDB LUW Certified V7-V8-V9-V9.7-V10.1-V10.5-V11 Fundamentals- DB Admin - Advanced DBA -Dprop..
Information Server Datastage Certified
01-10-14, 09:40 #3Registered User
- Join Date
- Feb 2008
- Location
- Japan
- Posts
- 3,483
I felt that responding to dharmendra87(op of this and some other thread) might be useless.
(1) I couldn't see any effort of him(her) to make codes to conform with DB2 syntax.
(2) I couldn't see no effort to look for built-in functions and/or expressions in DB2.
Because, I thought that the fuctionality of TestPmcDate might be realized by TIMESTAMP_FORMAT built-in function.
(3) (S)he might not have programming skills(regardless of programming languages including SQL)
Because, there were some incompleted/cofused codes in the function body of TestPmcDate which might be not seen in codes of skilled programmers.


text:
[kyaht, kee-aht] /kyɑt, kiˈɑt/
a paper money, cupronickel coin, and monetary unit of Burma (Myanmar), equal to 100 pyas.
the standard monetary unit of Myanmar, divided into 100 pyas
Tagged: k
Read Also:
- Kyathos
[kahy-uh-thos, -thuh s] /ˈkaɪ əˌθɒs, -θəs/ noun, plural kyathoi [kahy-uh-thoi] /ˈkaɪ əˌθɔɪ/ (Show IPA). Greek and Roman Antiquity. 1. a deep bowl set on a foot, often having a high voluted or serpentine handle rising from the brim and terminating immediately above the juncture of the body and the stem: used for ladling wine into […]
- Kybo
/ˈkaɪˌbəʊ/ noun 1. (Austral, slang) a temporary lavatory constructed for use when camping
- Kybosh
/ˈkaɪˌbɒʃ/ noun 1. a variant spelling of kibosh
- Kyd
[kid] /kɪd/ noun 1. Thomas, 1558–94, English dramatist. /kɪd/ noun 1. Thomas. 1558–94, English dramatist, noted for his revenge play The Spanish Tragedy (1586) Cayman Islands-dollar


text:
Toronto Review: The Coen Brother's Burn After Reading
by Alex Billington
September 6, 2008
Comedy from chaos - that's what Burn After Reading is all about. Essentially this film is a chaotic ensemble drama about six intersecting characters - but remarkably it's hilarious. I don't know how the Coen Brothers did it, but all of the eclectic characters they gathered together in Burn After Reading all really shined through in the finished product. The only problem was the felt it a bit skimpy, like there could have been so much more. At only 96 minutes in length, the film plays fairly well throughout most of it, but ends abruptly and often mixes darker elements and comedy, not always successfully. However, it's still a smart comedy with a hilarious ensemble cast that most people will end up enjoying thoroughly.
CIA agent Osborne Cox (John Malkovich) decides to leave his job after he's cited for "drinking problems," and starts writing memoirs in order to pass the time and eventually make some money. Unfortunately his wife Katie (Tilda Swinton) is having an affair with Harry (George Clooney), a womanizing, gun-toting chauvinist. When Chad (Brad Pitt) and co-worker Linda (Frances McDormand) accidentally find a disk containing files and documents for Cox's memoir in the gym, they attempt to blackmail him. And all hell breaks loose when Harry starts spending time with Linda all because she's desperate for attention. When the lives of all of them eventually start to clash together, chaos and comedy ensue.
While I definitely enjoyed Burn After Reading, for some reason that I can't exactly figure out, I didn't love it like I was expecting. Its problems may lie in the rather abrupt ending (that comes well before you want it to) and murky mix of comedy and suspense. When characters start getting shot and you're trying to laugh all at the same time, it gets a bit confusing. Burn is definitely not a mess of a film, but it's not a comedy classic either. Honestly, only the Coen Brothers could actually write such dry humor and wrap it around the story of an ex-CIA agent on the edge of insanity. Malkovich definitely earns my respect for easily being one of the funniest characters I've seen all year, while Pitt comes in a close second. As much as I loved watching all of eclectic characters go crazy, I just wish I could've been able to spend more time with each.
Toronto Rating: 8 out of 10
Follow Alex's main profile on :


text:
Graeme Blair is Ph.D. Candidate, Department of Politics, Princeton University, 130 Corwin Hall, Princeton, NJ 08544 (email@example.com, http://www.princeton.edu/~gblair). C. Christine Fair is Assistant Professor, Center for Peace and Security Studies, Georgetown University, Edward A. Walsh School of Foreign Service, 3600 N. Street, NW, Washington, DC 20007 (firstname.lastname@example.com, http://www.christinefair.net). Neil Malhotra is Associate Professor, Graduate School of Business, Stanford University, 655 Knight Way, Stanford, CA 94305 (email@example.com, http://www.stanford.edu/~neilm). Jacob N. Shapiro is Assistant Professor of Politics and International Affairs and Co-Director of the Empirical Studies of Conflict Project, Department of Politics and Woodrow Wilson School of Public and International Affairs, Princeton University, Robertson Hall, Princeton, NJ 08544 (firstname.lastname@example.com, http://www.princeton.edu/~jns). We thank our partners at Socio-Economic Development Consultants (SEDCO) for their diligent work administering a complex survey in challenging circumstances. The editor, our six anonymous reviewers, Scott Ashworth, Rashad Bokhari, Ethan Bueno de Mesquita, Ali Cheema, James Fearon, Amaney Jamal, Asim Khwaja, Roger Myerson, Farooq Naseer, and Mosharraf Zaidi provided outstanding feedback. Seminar participants at UC Berkeley, CISAC, Georgetown, the Harris School, Harvard, Penn, Princeton, Stanford, and the University of Ottawa honed the article with a number of insightful comments. Josh Borkowski, Zach Romanow, and Peter Schram provided excellent research assistance at different points. Basharat Saeed led the coding team that developed the violence data. This material is based upon work supported by the International Growth Center (IGC), the Air Force Office of Scientific Research (AFOSR) under Award No. FA9550-09-1-0314, and the Department of Homeland Security (DHS) under awards 2007-ST-061-000001 and 2010-ST-061-RE0001 through the National Center for Risk and Economic Analysis of Terrorism Events. Any opinions, findings, and conclusions or recommendations expressed in this publication are those of the authors and do not necessarily reflect those of any institution. Replication materials can be found at http://hdl.handle.net/1902.1/17042, and the Supporting Information is posted on the AJPS Web site.
Poverty and Support for Militant Politics: Evidence from Pakistan
Version of Record online: 16 JUL 2012
DOI: 10.1111/j.1540-5907.2012.00604.x
©2012, Midwest Political Science Association
American Journal of Political Science
Volume 57, Issue 1, pages 30–48, January 2013
Additional Information
How to Cite
Blair, G., Christine Fair, C., Malhotra, N. and Shapiro, J. N. (2013), Poverty and Support for Militant Politics: Evidence from Pakistan. American Journal of Political Science, 57: 30–48. doi: 10.1111/j.1540-5907.2012.00604.x
Publication History
- Issue online: 2 JAN 2013
- Version of Record online: 16 JUL 2012
- Abstract
- Article
- References
- Supporting Information
- Cited By
Online Appendix A: Question Wordings
Online Appendix B: Randomization Protocol
Online Appendix C: Overview of Militancy in Pakistan
Online Appendix D: Covariate Definitions
Description of Online Appendix Figures and Tables
• Figure 1. Beliefs about Groups' Objectives and Activities
• Figure 2. Distribution of Support for Policies in the Control Group
• Table 1. Sample Demographics and Randomization Checks
• Table 2. Reliability of Responses by Literacy and Poverty
• Table 3. Non-Response by Literacy and Poverty
• Table 4. Individual-Level Income and Support for Militant Groups (Varying Definition of Poverty)
• Table 5. Individual-Level Income and Support for Militant Groups (Dropping Individual Policies)
• Table 6. Individual-Level Income and Support for Militant Groups (Controlling for District Wealth)
• Table 7. District-Level Income and Support for Militant Groups (Varying Model Selection)
• Table 8. Sociotropic Economic Perceptions and Support for Militant Groups
• Table 9. Individual-Level Income and Support for Militant Groups (Controlling for Sociotropic Perceptions)
• Table 10. Individual-Level Income, Urban Residence, and Support for Militant Groups (Varying Definition of Poverty)
• Table 11. Individual-Level Income, Exposure to Violence, and Support for Militant Groups
• Table 12. Individual-Level Income, Exposure to Violence, and Support for Militant Groups (Varying Model Selection)
|Supporting info item
Please note: Wiley Blackwell is not responsible for the content or functionality of any supporting information supplied by the authors. Any queries (other than missing content) should be directed to the corresponding author for the article.


text:
by Matthew M. Lowe
Executive Vice President
This is an excerpt from an article published in the March 2016 issue of Medical Design Briefs.
Design control issues represent a key challenge for many medical device firms. This is the reason why in 1996, the U.S. Food and Drug Administration (FDA) added design control principles to 21 CFR Part 820 and required rigorous documentation to demonstrate design control.
The revision required manufacturers of some Class I and all Class II and Class III devices to follow the conditions and parameters provided under Subpart C, Section 30 of 21 CFR Part 820, also known as the Quality System Regulation (1). The mandate added a whole new level of complexity to the already rigorous and challenging device development process. In addition to designing and testing devices, development engineers must also ensure that all necessary documentation pertaining to design control is in place. This amounts to hundreds if not thousands of documents for every single product launch.
Documentation Burden
Under 21 CFR Part 820.30, there are nine elements of design control, each one requiring strict documentation. Let's take a look at these elements and what the documentation burden of each means (2).
Design and Development Planning or DDP: "Each manufacturer shall establish and maintain plans that describe or reference the design and development activities and define responsibility for implementation…The plans shall be reviewed, updated, and approved as design and development evolves."
Tip #1: This requirement indicates that design control is intended to be a prospective activity in the development process. You must incorporate a planning period into your development process upfront to ensure timely product launch and minimize your risk of product failure. A key part of DDP is assignment of tasks to responsible parties. Make sure your DDP process allows timely communication among those parties.
Design Input: "Each manufacturer shall establish and maintain procedures to ensure that the design requirements relating to a device are appropriate and address the intended use of the device...The design input requirements shall be documented and shall be reviewed and approved by a designated individual."
Tip #2: Many manufacturers mistakenly assume that user requirements gathered by their marketing teams are sufficient as design input requirements. It is a good starting point for developing design input, but it's not enough because most of the time, that information is qualitative, and therefore, insufficient.
You need quantitative design input that can be easily measured. Good sources of design input include prior generation customer complaints, medical device reporting (MDR), corrective action and preventive action (CAPA), sales feedback, marketing surveys, user conferences, and competitor products.
This article is related to the Q&A: ISO 14971: Risk Management for Medical Device Companies. To get the full details, please download your free copy.
This article is related to the Q&A: ISO 14971: Risk Management for Medical Device Companies. To get the full details, please download your free copy.
Design Output: "Each manufacturer shall establish and maintain procedures for defining and documenting design output in terms that allow an adequate evaluation of conformance to design input requirements…Design output shall be documented, reviewed, and approved before release…."
Tip #3: The design output refers to the completed device at the end of the development cycle, but it's not limited to the finished device. Your design output should include all documentation during the development process verifying that the design input requirements were met—plus any item that serves as a basis for the finished device specifications.
Design Review: "Each manufacturer shall establish and maintain procedures to ensure that formal documented reviews of the design results are planned and conducted at appropriate stages of the device's design development…The results of a design review…shall be documented in the design history file (the DHF)."
Tip #4: Design reviews, which are crucial to the efficacy of the design control, should be planned for upfront in the DDP because changes late in the design cycle are more costly than those made early on. You can avoid expensive non-optimal redesigns close to the launch date by conducting design reviews—and identifying changes—sooner than later.
Design Verification: "Each manufacturer shall establish and maintain procedures for
verifying the device design…The results of the design verification, including identification of the design, method(s), the date, and the individual(s) performing the verification, shall be documented in the DHF."
Tip #5: Compare your design output with your design input to determine if design requirements were met. There are many forms of design verification. Risk analysis is part of design verification and will commonly take the form of Failure Modes and Effects Analysis (Design FMEA). The ultimate goal of this step is to verify that the design output meets the engineering specifications that were derived from the user needs.
Design Validation: "Each manufacturer shall establish and maintain procedures for validating the device design…The results of the design validation, including identification of the design, method(s), the date, and the individual(s) performing the validation, shall be documented in the DHF."
Tip #6: Take note that design verification precedes design validation and is not a substitute for the latter. QSR requires validation testing to be conducted on actual production units or their equivalents. When using equivalents, you must provide documentation that clearly demonstrates the equality. Don't manufacture test units under special conditions that don't mimic actual production. This step is intended to validate that the engineering specifications were translated properly from the user needs and thus the design output does indeed meet the user need defined in the design-input phase.
Design Transfer: "Each manufacturer shall establish and maintain procedures to ensure that the device design is correctly translated into production specifications."
Tip #7: At minimum, the design transfer process must assess the completeness and correctness of the production specifications. Furthermore, the specifications must be reviewed and approved and placed under the formal change control process. Most of all, you must make sure that the product is manufactured only to the latest approved revision of the device master record.
Design Changes: "Each manufacturer shall establish and maintain procedures for the identification, documentation, validation or where appropriate verification, review, and approval of design changes before their implementation."
Tip #8: After you have finalized and approved the design input requirements, any changes are subject to formal change control process. Once you have verified and validated the design output specifications, any changes will also require change control. This entails documentation and evaluation of every design change, although it doesn't mean every single change requires the same level of scrutiny.
Design History File: "Each manufacturer shall establish and maintain a DHF for each type of device. The DHF shall contain or reference the records necessary to demonstrate that the design was developed in accordance with the approved design plan and the requirements of this part."
Tip #9: The DHF is intended to serve as the repository of documentation generated by the design control process, with each of the elements discussed above contributing documents to the DHF. Make sure you assemble your DHF properly because it will be referenced throughout the life of the product. The DHF is crucial when a question arises about the design's integrity long after a product has been launched. A manufacturer could pay a high price for an inadequate DHF if such a question leads to a recall of several years' worth of product.
Leverage 9 Elements
Design control is meant to help you develop and manufacture safe and effective products that readily comply with regulations. If you leverage the nine elements discussed above, they will help you focus on building your core competency, instead of just fulfilling regulatory requirements.
Matthew M. Lowe is a mechanical engineer with over a dozen years of medical device experience in product development, product management, and regulatory compliance. Prior to joining MasterControl in 2006, he worked in product development and product management at Ortho Development Corp. and Bard Access Systems. He has successfully launched more than a dozen medical devices and has four patents issued. His regulatory compliance experience includes writing a 510(k) that was cleared by the FDA and managing a multisite, multiyear post-market clinical study for orthopedic devices.
(1) From FDA website, 21 CFR 820.30 https://www.accessdata.fda.gov/scripts/cdrh/cfdocs/cfCFR/CFRSearch.cfm?fr=820.30
(2) These elements are defined in 21 CFR 820. 30 (a) through (j). From FDA website,
Watch Related Videos:BioMimetic Therapeutics
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text:
Santa Clarita, CA, 91381
Joined on November, 2009
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EducationPhD degree in science from UCLA
ExperiencePlease feel free to send me an email to firstname.lastname@example.com. Or call 949-777-5630.Thanks.
Excellent high school and college math/physics tutor is available in Santa Clarita. I received PhD degree in science from UCLA with GPA 3.85/4.00. I can provide high school Pre-Algebra, Algebra, Geometry, Trigonometry, Pre-Calculus, AP Calculus, AP Physics and SAT, ACT, CBEST, CSET tutoring. And also I can teach college level Calculus, Linear Algebra, Multi Variable, Differential Equations, GRE Math, GMAT math and college level Physics. I can help you with your homework or projects and explain the solutions.
I am a California registered Professional Engineer. I passed the Fundamentals of Engineering (FE/EIT) exam, and PE exam. I can provide tutoring on FE/EIT and PE exam.
I am bilingual in Mandarin Chinese and English. I can provide Mandarin / Chinese tutoring for all level students. I am a friendly and patient person with extensive teaching experience for all level students. One-to-one private lessons or group instruction are both available whether in your home or my home. The instruction schedule is flexible.
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text:
A few weeks ago the Chronicle mentioned the proprietor of Cafe Claude had opened a new restaurant on Claude Lane. So Tuesday night I checked out Gitane. The restaurant looks great. It's got a dark supper club kind of atmosphere. On a Tuesday afternoon the restaurant filled up and the bar was hopping by the time we left.....What recession?
Nice wine list. When they bring water they put a carafe on the table -0 which as a heavy water drinker I love. We had a bottle of the Palacios Petalos Bierzo which was lovely. I started with the gazpacho which was more of a puree than the typical chopped soup. It was garnished with a drizzle of basil oil, croutons and cucumber. It was light, fresh, flavorful..exactly what I was looking for. I followed that with the chicken Tajine served with a side of couscous. The presentation is great - in a ceramic tajine. If you take a look at their website you can see the dish on the front page. It was delicious, wonderfully moist and nicely seasoned. For dessert I had the Bavarois au Fruit Rouge. This was a very light fresh layered dessert of fruit mousse, rasperries and what seemed like a cake layer - but was per the menu joconde biscuit.
Service was smooth. The waiter seemed familiar with the menu, the bus boy was attentive and the manager stopped by to see how our meal was.
It's a very nice addtion to downtown dining and I will be back - soon!
Gitane Restaurant & Bar
6 Claude Lane, San Francisco, CA 94108


text:
PIAA playoffs
The high school baseball and softball seasons are over for local schools, and Friday the PIAA championships are scheduled in State College.
Two Schuylkill County teams made it to the state baseball quarterfinals.
Tamaqua lost a defensive struggle to Jersey shore in the AAA playoffs by a 1-0 score, while Schuylkill Haven lost to Juniata Valley in the Class A event.
In softball, Minersville will be competing Friday for the state title against Halifax in a 2 p.m. game. It's the second time in four years they've made it to states, winning the championship in 2011.
A fourth District 11 team, Bethlehem Catholic, also plays for a state softball championship in the AAA division. Parkland was in the softball semifinals, too. They also are part of District 11.
Five teams from the same district advancing to the quarterfinals in PIAA baseball and softball competition is impressive.
Our area has always had some great players in the two sports, with numerous baseball players advancing to major colleges and even several going onto the pros.
Many high school baseball players will participate in summer leagues before returning to high school or going onto college. Some already play for Legion teams.
It's always great to see local high school students do well, whether it be athletics or academics.
Many people don't realize the amount of work involved for sports teams and the sacrifices the whole family makes. The practice and playing schedules are juggled with academic demands and social duties. There's sacrifices to the families.
That's one of the reasons we at the Times News give so much publicity to local sports teams. We know about the efforts the local kids give, no matter what their record.
That's why we're at the forefront of applauding them with big headlines especially when they do very well in tournaments and playoffs.
For these teams, how many players started with the Little League program? How many learned the basics of the sports when they were 8 or 9 years old and diligently continued playing the game through their high school years?
Sports teams are more than just playing a game. They're about learning commitment, teamwork, having pride, and camaraderie.
That's why it is always sad when school boards cut budgets and target athletic programs. Such cuts do hurt the kids.
We'll be watching with eager anticipation how Minersville and Bethlehem Catholic softball teams do in the state finals of the PIAA playoffs Friday.
Both teams have played many local schools this season, so we've seen them play numerous times and feel a bond with them.
The mere fact that they're in District XI, our local PIAA sporting region, means they're representing us.
Keep your fingers crossed for them.
By RON GOWER


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God, is Arod frustrating
I watched the replay of Wednesday night's Cincy game. Arod is lucky these games don't mean anything. Through just 3 innings, he: 1. bobbled a bunt into a hit (admittedly a tough play), 2. ran through Larry Bowa's stop sign to get nailed at home (which would have become a run later if he had paid attention), 3. made a poor throw to 1b (E-5) allowing the hitter to reach (forcing Pettitte to throw 9 extra pitches that inning), 4. with 2 runners on and 2 outs, took strike 3 called right down the pipe. It's only March, it's only March...
- Mo's split-change-slurve was less dynamic than expected when I first heard it reported. I'd still love to see him use it in the regular season. It would be very useful for those 10+ pitch at-bats where the hitter clearly has Mo's timing but keeps fouling off pitches - and at the very least, it can serve as a 'show-me' pitch.
- Melky made two nice plays in centerfield and another where he looked lost. He got a bad jump on a ball hit to right-center and dove several feet short of it. He should only improve though, as I was impressed with his overall D.
- Even though Minky doesn't have one hit yet, his eye and glove still work well. He's worked a couple walks and a HBP. He also made a fine stab tonight on a short-hop toss from Cano on a GDP.
- Josh Phelps is a great fastball hitter. Unless Andy Philips tears the cover off the ball, Phelps has got to be the righty first-baseman. (So far) he's hit his way onto the team.
- I know Brett Gardner is fast, but damn is he fast! Mark Bellhorn (yep, him) hit a shot to left-center that looked like an easy double. Not only did Gardner run it down, but nearly overran it. He looks big and strong enough to have some power, so if he can add just a little, he would be a fantastic OF defensive replacement/pinch-runner extraordinaire (basically Bubba Crosby times 10).
- Luis Vizcaino looked great against his first 2 hitters, then gave up a solo shot to Cincy prospect Joey Votto. In Vizcaino's defense, it was a tough pitch to hit: an inside fastball that Votto seemed to pop-up. He must be strong and there must have been wind, because it somehow carried over the RF wall.


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Taylor Swift Did NOT Have "Mini-Meltdown" When She Saw Jake Gyllenhaal At Golden Globes Party, Despite Report
Taylor Swift did not have a "mini-meltdown" when she saw Jake Gyllenhaal at a Golden Globes after-party, despite a webloid's new claim. Gossip Cop looked into the report and not only is it entirely untrue, but the two exes were extremely cordial when they bumped into each other at the Chateau Marmont, where hosts Tina Fey and Amy Poehler threw a post-awards show bash.
According to HollywoodLife, Swift "panicked" when she spotted her ex-boyfriend a few feet away at the party. The site says Swift tried her best to "avoid" Gyllenhaal, who was dancing with a number of different women, including Rita Ora and Malin Akerman, but at a certain point, the singer "freaked out" and told her friends, "We have to go."
The webloid's account is all very dramatic and wrong. In fact, multiple sources confirm to Gossip Cop that Swift pretty much arrived at the party as Gyllenhaal was making his way out of the bash. And as opposed to HollywoodLies, er, HollywoodLife's account of Swift having a meltdown and being "freaked out," we're told they two talked for a little bit and even hugged. "They looked genuinely happy to see each other, smiling and everything," one eyewitness to Gossip Cop.
Of course, HollywoodLife has a rich history of making up stories about Swift. The webloid falsely alleged that she got breast implants, manufactured a fictitious feud with her friend Selena Gomez, and recently embarrassed itself more (if possible) by claiming that she and Harry Styles were again "secretly dating for months." Sadly, no one at HollywoodLife seems to get "freaked out" by how inaccurate the site is with its reporting on Taylor Swift.


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Our Executive Chef has based his creations on the rich Spanish and Mediterranean cuisine with its latest influences, focused on the highest quality of its products and the freshness of all ingredients. Carefully selected meat and fish accompanied by a wine cellar reflecting the best Spanish regions.
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Goapele "Play" from the forthcoming "BREAK OF DAWN" in stores Oct. 24th, 2011. "Play" available now at iTunes: http://bit.ly/playitunes
Produced by Electric Thunderbolt - Dan Electric and Teddy Thunderbolt
Directed by John Mazyck & Dahveed
http://www.facebook.com/decon http://www.deconrecords.com
After a six-year hiatus on a journey through motherhood and life outside of music, Goapele has returned with the sensual single, "Play". The song features production from Oakland based duo, Teddy Thunderbolt & Dan Electric, and was written by Goapele herself. Currently available through Skyblaze Recordings/Decon via iTunes and Amazon, the single incorporates elements of funky, down-tempo electronic vibes layered with Goapele's smooth and seductive vocals. The video, which was directed by John Mazyck and Dahveed of Detail Shoppe, was shot in a graphic black and white. It showcases Goapele in a glamorous, high fashion themed setting that gives both an evocative and sensual visual to the pillow talk vibe of the song.
"Play" is just a taste of the musical feast Goapele will be offering this fall when her new album, Break of Dawn, to be released October 24th. Collaborating with an array of creative folks including Kerry "Krucial" Brothers, Bobby Ozuna, Malay, Dan Electric and Bedrock, fans will bare witness to a more free-spirited Goapele. "One of my goals for [Break of Dawn] was to be more uninhabited," Goapele says. "I came into this business as a young woman who wanted to lay a foundation of musical integrity and now I'm more willing to share my sensuality as well. I realize that it's possible to be both complex and provocative."


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I'm converting anchors to images, fading them into the page in order,
then removing the anchor (and parent li) from the page.
I'd like to load in the first 10 items from the list, then loads in
additional groups of 10 by clicking a load-more button. Not really sure
what the best way to do this is. I appreciate your help.
is below, everything works app
How do I tell Nokogiri not to convert a document to a different
encoding, in my case not to convert &paund; to to anything
I have a file containing:
<meta http-equiv="Content-Type" content="text/html;
charset=iso-8859-1" />£
I have read a novel about hacking. In the book i read that the hacker
convert the file into high frequency sound wave, from the beep of POST
sound. And he record it with mobile phone, then on his computer he
reconverted the sound file into the Original file. I want to know how to do
that? By help of which software?
I'm on Mountain Lion and installed ImageMagick using Homebrew
(minimagick is also in my Gemfile but I don't think that's relevant).
SimpleCaptcha uses it in a Rails app to create CAPTCHAs.
However, the image isn't created cause of this error:
Error while running convert: convert: unable to read font
`/usr/local/share/ghostscript/fonts/n019003l.pfb' @ error/annotate.c
I am getting some open/closed times as integers since midnight. For
"1140" = 19:00 (or 7 pm if you will) or;"570" =
9:30 (or 9.30 am)
I can easily get the time in European format,
just by doing doing a simple calculation and formatting:
[NSString stringWithFormat:@"%d:00", (T / 60)]
However, this doesn't work for half h
I have data sets in which a hyphen is used in place of the number zero,
as in the example data set my.data below. I can replace the
hyphens with zeroes, but then have trouble converting the affected columns
to numeric. My actual data sets are very large with many columns and I do
not know which columns will contain hyphens. The data sets are also too
large and complex for me to
PHP converts a large number to floating point which I need in "long"
format to pass to a soap xml api.
This gives the result:
Whereas, what I need is:
in order to pass to the api
I am using windows .I want to deploy my django app on Heroku .I got
errors doing that and came to know that it supports postgresql database but
i used SQLITE3. So, how can i convert to Postgresql ? Is changing Engine,
databasename, username, pwd in settings.py enough or any more cahnges ?
Also, after making changes, is my code still valid, or do i need to change
everything, like queries and oth
some set of functions in my class library accepts string[] as parameter
i want to convert my System.Collections.Specialized.StringCollection to
string array. is it possible with some one liner or i have to create array
with loop?
I need to convert text in UTF-8 into text encoded in ISO-8859-1 such
that any character that are not part of ISO-8859-1 set would turn into
character references. (ex β)
Example: I
want to turn text like
hello é β 水
hello é β 水
I am doing all this in PHP. I trie


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The only thing worse than being blind is having sight and no vision. ― Helen Keller
Darkness cannot drive out darkness; only light can do that. Hate cannot drive out hate; only love can do that. Dr. Martin Luther King, Jr.
In the future, everyone will be famous for 15 minutes. Andy Warhol
If you reveal your secrets to the wind, you should not blame the wind for revealing them to the trees. Khalil Gibran
#FFFavorites @unityofamerica @TimeHasComeFilm @cornellyounge @GNRTG4gifts @Martyk2 @sydesjokes @LiveDhirawit @AliceJackson09 @Gr8estGift


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Parade of Flesh presents . . .
Black Tusk, Inter Arma
Baring Teeth, Tyrannosorceress
Club Dada
2720 Elm St.
Dallas, TX, 75226
This event is all ages
Black Tusk is an American sludge metal band from Savannah, Georgia. The band was formed in 2005, when its members were all living on the same street. With the dissolution of Andrew Fidler (guitar, vocals) and Jonathan Athon (bass, vocals) crust punk band and James May (drums, vocals) street punk band, Andrew and Athon went down the street to James' house and asked him if he wanted to play with them. During the next few days they jammed continuously, and within a few months they had recorded the EP When Kingdoms Fall, which was released on Wrecked Signal. Two years later the band self-released their first full-length studio album, The Fallen Kingdom, followed by another a year later with Passage Through Purgatory, released through the local label Hyperrealist Records. In 2009, Black Tusk released a series of split albums with bands such as ASG, The Holy Mountain, and Fight Amp, before signing to relapse records in November. The band released its debut for Relapse, Taste The Sin, in May 2010. They released their third album, Set the Dial, in October 2011 through Relapse Records.
Black Tusk is mostly associated with Baroness and Kylesa, for their shared hometown of Savannah, as well as for their sludge metal sound. The band is linked to Baroness' guitarist and vocalist John Dyer Baizley, who is also a painter and creates all of Black Tusk's artwork. Black Tusk's members describe their music as "swamp metal," a term that has been described by Allmusic as "the murkiest, dirtiest sludge to come out of Savannah since Kylesa".
Formed in 2006, Inter Arma is one of the most talked about heavy bands to come out of Richmond, VA . The group (consisting of T.J. Childers - Drums, Steven Russell - Guitars, Trey Dalton - Guitars, Mike Paparo - Vocals, Joe Kerkes - Bass) formed in 2006 and released their crushing debut full-length Sundown via Forcefield Records in 2010 to much critical acclaim. Combining a punk rock ethos with an esoteric blend of psychedelia, black metal, and doom/sludge, the quintet quickly developed a name for themselves in the underground through relentless touring and mesmerizing live performances. After Sundown's release, Inter Arma began a rigorous DIY touring schedule, playing shows with bands like Cough, Krallice, Mutant Supremacy, Castevet, Royal Thunder, Ken Mode, The Body, Hull, Batillus, Black Breath and many more.
$11.00 - $14.00
Upcoming Events
Club Dada
Fri, November 17
Graham Wilkinson
Fri, November 17
Femme Friday: Ursa Minor
Sat, November 18
No Noodles Involved: Xes, Cardiac the Ghost
Fri, November 24
Alice Merton
Sun, November 26
Curtis Mayz 'TripleDiziac' Album Release


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Here is where sellers can list any catch-all policies about their booth. If any of this information is essential to the buying process, the seller will also mention that within their item description -- so don't sweat it if you don't make a habit of looking at the details for every booth!
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Relax, look around browse abit!
Pictures of the actual item you will be receiving. If you have ANY questions, just contact me and I will be happy to help you!
Have a Great Day.
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We can combine shipping. .. Convo me …
We do not ship outside the USA.
Return policyRefunds available: See booth/item description for details
We gladly accept returns within 3 days of purchase.
Miscellaneous details
Don't forget to leave us a feedback..
Seller coupons & discounts
Shipping discount: Items after first shipped at flat $1.00 Shipping weights of all items added together for savings.


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- Citizens Bank Park Seating Map
- StubHub
- For all your Phillies ticket needs, visit phillies.com/tickets on your computer.
Ticketing Information
Your Tickets are in the MLB.com Ballpark App
- View your tickets and enter Citizens Bank Park with the free MLB.com Ballpark app. Simply log in with your MLB.com account to see your tickets and forward tickets to friends.
Learn more at the Digital Ticketing FAQ
Ticket Alerts
- Text "Phillies" to 49887 for Phillies Alerts.
- Msg and Data Rates May Apply.
- Text STOP to 49887 to cancel
- Text HELP to 49887 for assistance
- Expect 1-2 messages per week


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Government health advisors recommend that all children should be vaccinated against flu from the age of five to stop them spreading the illness among their families.
Under new plans, put forward by a panel of independent advisors which advises the government, school children over the age of five would be vaccinated each year with a nasal spray that avoids the use of needles.
Currently, the seasonal flu jab is recommended for people on the NHS that are 65 years old or over, are pregnant, have a serious medical condition, are living in a long-stay care facility, are the main carer for an elderly or disabled person, or are a frontline health or social care worker.
This means that only children with serious long-term illnesses are given the flu jab, despite receiving 12 vaccines against eight other diseases by the time they start school.
A study published last year found that immunising healthy children would prevent eight in ten flu infections and free up 79,000 GP appointments a year.
The new vaccine, made by AstraZeneca, was licensed in December and contains three strains of flu. It is given in two doses four weeks apart, and can cause side effects like headaches, loss of appetite, fever and muscle pain.
Experts say that vaccinating children would be more cost effective and prevent spreading the illness in adults. Dr George Kassianos, spokesman on immunisation for the Royal College of GPs, said: "It will be beneficial to children and will benefit other patients as well."
"If we can reduce the infection rate among children we can reduce the morbidity and death rate in the community generally, and especially among the elderly."
The panel is in the final stages of evaluating research before formally recommending the expansion of the programme. The committee said it would produce recommendations, which are binding on the Department of Health, at its next meeting.
If you are worried about the health of your child, look for a health insurance policy that covers all members of the family.
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The hastily arranged West Indies tour of India where Sachin Tendulkar is expected to play his 200th Test before home fans will begin on October 31.
The Board of Control for Cricket in India announced on Thursday that the four-week tour, which will comprise of two Tests and three One-day Internationals apart from a three-day warm-up game, will begin on October 31 and conclude on November 27.
dates and venues of the matches will be announced shortly," BCCI secretary Sanjay Patel said in a release.
It is widely believed that the tour has been arranged to give Tendulkar an opportunity to play the historic 200th Test in front of his home fans. As per the rotational policy, Motera Stadium in Ahmedabad is in line to host the 200th game but Tendulkar's home city Mumbai and Eden Gardens Kolkata are also vying to host the landmark occasion.


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A fully-involved house fire has been reported in Jackson County, WV.
Dispatchers say it happened just before 9 a.m. on Dec. 14 on the 10400 block of Spencer Road in Ripley.
A family occupied the home, but no one was inside the house at the time.
A neighbor came over to tell them that their home was on fire.
Investigators believe that the fire may have been electrical.
The fire dept. had problem with access to water because they couldn't locate a hydrate and a creek near the home was too low.
The house have been declared a total loss.
Keep checking wowktv.com for updates.
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When many of us hear the word "style," we immediately—and correctly—think of the physical characteristics and mannerisms that uniquely define a person. Whether we're talking about Audrey Hepburn's style of fashion, Jack Benny's style of comedy, or Ernest Hemingway's style of writing, what we're really doing is calling to the fore the specific elements of individuality expressed by each of these 20th century cultural icons.
In this issue of PS Magazine, we celebrate the dignifying and empowering value of everyone's personal style, and not a moment too soon, in my opinion! Living in a world today where we have digital profiles of ourselves on Facebook, Twitter, LinkedIn, Instagram, etc., existing in far greater number than our old-fashion, single "in-person" self, it's more important than ever that we embrace what makes us unique, that which reveals to our offline world a bit of who we really are on the inside.
The following pages are full of articles that celebrate this message of personal expression through our outward-facing, physical style. Some of us will bask in the creativity and glamour of the women presented in Ari Seth Cohen's Advanced Style, while others will chuckle and remember the last time they donned a festive Hawaiian shirt and ordered a drink with one of those little umbrellas in it. And going beyond clothes and hairstyles, we had some fun attending a feline fashion show in New York City that will likely redefine your vision of what a "cat walk" in the
Big Apple might look like!
Wherever you are and in whatever form of attire you choose today, in the spirit of celebrating you, may this issue of PS Magazine encourage you to proudly display your style! Sincerely, John Polatz Publisher and CEO


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Azzaro Boarding - Opinios Reviews
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- Date Added: 13/01/2015The green freshness Azzaro Borading exudes feels so natural and fresh i haven't found anything similar to this aroma. It brings a pleasant calming sensation that is fresh masculine and has a character of its own, natural and distinct.by Louis
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Browsing Archive September, 2014
If You Find Prostate Cancer Early…1
Prostate Cancer Awareness Should Be Every Month for Black Men.READ MORE +
National Latino AIDS Awareness Day0
The last day of Hispanic Heritage Month, October 15th, has been designated as National Latino AIDS Awareness Day (NLAAD). HIV continues to affect the health of Hispanic/Latino ...READ MORE +
Persistence, Faith, and Action1
Dr. C.M. Lee is a man of faith, action, and persistence.READ MORE +
15M With Social Phobia0
If you have anxiety negatively affecting your life, seek help today.READ MORE +
H.I.S. BET is Good News for Black Men0
BET wants to support Black men with new initiative, H.I.S. BETREAD MORE +
Carrot Fit App0
Make getting fit suck less with CARROT's 7 Minutes in Hell workout.READ MORE +
High Cost of Hep C Tx0
Is the new Hep C drug worth $84,000?READ MORE +
Essence of a Black Man0
Created in the image of God?READ MORE +