text:
|Publication number
|Publication type
|Publication date
|Oct 17, 1972
|Filing date
|Dec 30, 1970
|Priority date
|Dec 30, 1970
|Also published as
|Publication number
|Capowski Robert S, Horsman Larry R, Unterberger Robert M
|Original Assignee
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (8), Referenced by (44), Classifications (8)
|External Links: USPTO, USPTO Assignment, Espacenet
United States Patent Capowski et al.
[ 51 Oct. 17, 1972 INPUT/OUTPUT SYSTEM WITH 3,530,438 9/1970 Mellen et al ..340/l72.5
DEDICATED CHANNEL BUFFERING Primary Examiner-Gareth D. Shaw [72] Invemors' #2 gg fz gz xzgg l Assistant Examiner-Sydney R. Chirlin Poug'hkeepsie both'of N Y 2:2 Attorney-Hanifin and Jancin and Owen L. Lamb R. Horsman, Louisville, Colo. [57] ABSTRACT [73] Asslgnee: g f f YMachmes A storage control unit (SCU) for a data processing orporatmn system which buffers data fetch and data store [22] Filed; Dec, 30, 1970 requests from input/output channels for access to lowspeed high-capacity interleaved logical storage units. [2H Appl' Multiple dedicated buffers are provided for each channel in the storage control unit (SCU) to insure [52 U.S.Cl. ..340/172.s that all Channels have an individual receptacle w [5|] Int. Cl ..G06f 9/18 transfer data to which cannot be made unavailabIe 58 Field of Search ..340/172.5 due transfers by other Channels PFiOYllY rewlulion of requests from channels controls the use of the in [56] References cued bus from the channel to the SCU independently of subsequent priority resolution for use of the main UNITED STATES PATENTS storage. Once a channel transfers its storage address and data into its assigned SCU buffer, that buffer, r p based on the storage address contained within it, en- 3274554 9 l 66 Herman et 40 ters storage priority for the particular logical storage I 5 a unit desired. In this manner, the single queue of chan- 7 I19 6 Ha man et "340M725 nel requests is rearranged into four independent a g i request queues based on logical storage addresses. 0 en e a. 3,483.522 12/1969 Figueroa et al ..340/l72.5 9 Claims, 11 Drawing Figures 20 STORAGE ADVANCE ll DATA *-+r1-+ [-47 LUGlCAL LOGICAL LOGICAL LDGICAL LOGICAL gum I STORAGE STORAGE STORAGE STORAGE I 0 AVAllABlE I l 2 3 I 4o- 203m 5T0RAg[ 7 1:%::T' 2'2: III: I
SEL I v P 1 I STORAGE PRIORITY CPU I**I LOGICAL OUEUE ILOGICAL QUEUE I LOGlGAL cum I LOGICAL OUEUE I I tSILOiRAGE 0 TILSTOIHIGE l iSilgllhlili 2 STORAGE 5 I W ra BIJF REO FOR If I I I I I REG FOR OUT I MAL W I T CHANNEL CHANNEL CHANNEL 1* CHANNEL CHANNEL lgg lfififil I s m olli il olil il olii il DllTil olil ilr I 24 26 I 28 I 50 54 CHANNEL I F cm CH BUF I cu AUDRESSl DATA W I I I PRIOR, 4s m BUSSES I L iI CH 4 m 40 IT I L I CH um I I/O I/u BUS out L W RESP CHANNELl CHANNEL 2 I ll I 12 ADV ADV CHAN l CHAN 2 murmur 1 1 m2 3.699.530
REQ nxCONTENDS FOR 206 205 IN-BUS PRIORITY 207 WAIT FDR ADR VALID LTH A TO BE SET FOR CURRENT IN-BUS SEQUENCE SET RESP TGR nx ISET m-Bus ausv um [RAISE RESP n T0 cum] [SET cnoup RESP LTH n 242 246 RESET REO svuc TGR n SIMPLEX CABLE 244 JJ cm n PULSES RESET CH-BUF m-ausses a ADR REO LTH n VALID S'GNAL 241 MULTIPLEX CABLE DELAY DELAY BETWEEN sou a CHNL 2 i v &
[ SET ADR VALID svuc FF] [sir mans RESP Mm] PATENTEU 3,699,530
SHEET UBUF 11 FIG. 6 B Q? SET ADR vnuo L H A DECODE cum ADR BUS ans SET cum 3%,: 'g gfi SET new 27,28 a SET lN-BUS mm mm "HUF ADR vnuo RESP TGR SET CH- SET DROP BUFF ausv ADR vnuo RESPONSE n 226/ LTH nx LTH B \225 T0 CHNL ADR VALID LTH B &
NOT TGR A RESET REMB RESP LTHS RESET GRP RESP LTH n ANY RESP TGR 0" YES RESET IN BUS BUSY LTH PATENTEIJUBT 1 1 I972 SHEET [19 HF 11 LOG sm REQUESTED IS NON-BUSY HIGHER PRIOR BUFF REO nonausv LOG src 255 FREEZE N0 F E &
GATE crm ADR, SET sm BLOCK CPU SEL MK, a as PRIOR LTH n X 24o & g G STG lN-BUFF n x T0 STG REO BY BUF M RESET BUFF nx 55; L08 L06 sm m. REO TRG 24 BUSY m;
STORAGE SET sm CYCLE PRIOR TRG n x \242 244 CYCLE COMPLETE GATE CH 0m RESET LOG m- BUFF E x are m BUSY m are m m;
PATENTEDnm 11 I972 FIGQGD SHEET lOOF 11 SS BIT TON (CPU OP) DECODE SOURCE SINK FOR OH- BUF ID DELAY CH-BUF nx SDO ADV TO SAMPLE SDBO SET CH- BUF nx COB REO TRG SAMPLE CKS FRON SOURCE SINK BUS INHIBIT SET ALL COB REO LTI'IS ON SET OH-BUF GROUP n COB REO LTH OUT BUS PRIORITY SET CH-BUF GRP n OUT BUS PRIOR TRG RAISE ADVANCE n TO CHANNEL SET OUT BUS PRIOR LTH PATENTED 17 I97? 3. 699 .530 sREET 110T 1 1 T .L CH-BUF cRRR OUT-BUF READREO I LRRTE CH.-BUF no RRTR To cR] IRATE CH-BUF TH om To CH 1 [RATE CH-BUF noCHECKS TocR] TETTE CH-BUFM CHECKS To 011] REsET CH-BUF RX 008 REo TRG zvo RESET CH-BUF REsET INHIBIT sET GROUP l'l CH-BUF ALL cos REO 008 RH) LTH BUSY LTH LATCHES NM 274 T REsET CH-BUF THIS IS A STORE 0P GRP h ouT /Rus PRIOR TRG UCE ON THIS OF 276 PARITY CHECK INHIBIT PTY COB CK 0F T0 CHAN T0 CH INPUT/OUTPUT SYSTEM WITH DEDICATED CHANNEL BUFFERING BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a data processing system and more particularly to apparatus for controlling data flow between the input/output and the storage of the system.
2. Description of the Prior Art ln large scale data processing systems, smoothing of data requests between input/output channels of the system and the main storage of the system is accomplished by buffering. For example, in large systems, a data exchange is provided comprising a plurality of registers which form a queue of requesting signals. An input/output priority control transfers requests to one of the registers in the queue, and an output priority control selectively processes the stored request. This system has the advantage that it no longer is the availability of a storage cycle that determines whether or not a given device is serviced, but rather the availability of a queue position. This type of data exchange is necessary when many channels are in contention for the use of the very slow memory. However, this technique is very expensive and when a relatively faster memory is utilized, the highly sophisticated bufi'ering and priority techniques are not necessary.
As an alternative, a storage control unit (SCU) is provided between channels and memory. In existing systems, the SCU accepts a channel request to access a storage unit only when the inbound bus and an SCU channel buffer are both available. Accepted requests are then allowed to access the desired logical storage unit on a first inlfrrst out basis or according to some other fixed priority scheme. However, an accepted request may still not be able to access the required logical storage if the logical storage is busy or if the unit is not busy but a request in another buffer has a higher priority and its required logical storage unit is busy. Thus, requests from a channel to a logical storage which is not busy can be held up because a request from a higher priority channel to a difl'erent logical storage has not been processed.
Should all buffers filled up by requests be unable to access their required logical storages due to the two cases above, no other channel request may be accepted by the SCU. This needlessly delays channel access to non-busy storage units and ties up the SCU buffers longer than is necessary, to the detriment of the lower priority channels. Increasing the number of shared SCU channel buffers benefits only the high priority channels because more buffering is available to them, however, this does not ease the contention problem faced by lower priority channels.
SUMMARY OF THE INVENTION The primary object of this invention is to provide a simplified and improved buffering system for buffering requests from input/output channels to main memory.
Another object of this invention is to provide an improved priority control which resolves in parallel a large number of requests by many contenders for a large number of facilities.
A further object of this invention is to provide a sequence monitor which controls the loading and unloading of a plurality of buffers such that the loading is done as the buffers become available, and the unloading is done on a first in/t'irst out basis.
Briefly, the above objects are accomplished in accordance with the invention by providing multiple dedicated buffers for each channel in the storage control unit (SCU) to insure that all channels have an individual receptacle to transfer data to which cannot be made unavailable due to transfers by other channels. Priority resolution of requests from channels controls the use of the in bus from the channel to the SCU independently of subsequent priority resolution for use of the main storage. Once a channel transfers its storage address and data into its assigned SCU buffer, that buffer, based on the storage address contained within it, enters storage priority for the particular logical storage unit desired. in this manner, the single queue of channel requests is rearranged into four independent request queues based on logical storage addresses. This results in the ability to concurrently cycle all logical storages in behalf of channel requests.
A further aspect of the invention involves the use of a sequence monitor to control the loading of individual buffers as they become available, and the unloading in the same sequence as the loading, i.e., on a first in/first out basis.
A still further aspect of the invention involves the use of a priority circuit which resolves multiple requests to multiple logical storages in accordance with a fixed priority taking into consideration the availability of each storage and contention to that storage only for purposes of priority determination.
The dedicated buffering system has the advantage that it eliminates unnecessary interference of lower priority channel requests by higher priority channels concurrently requesting at high speed data rates. This allows the lower priority channels to sustain higher [/0 rates than would otherwise be possible.
Multiple dedicated buffers per channel allow concurrent storage cycles to be taken in behalf of individual channels which have the capability to overlap their requests. if only one buffer were dedicated to such a channel, only until after one request was completed and the buffer made available could the next request be handled. The multiple buffers per channel effectively enables doubling the [/0 rates sustainable at each priority position.
The invention has the further advantage that a channel request can be accepted by the storage control unit provided only that the inbound bus is not busy and no other request of higher priority is pending. This allows the channel to unload its internal buffers faster and enables it to maintain higher data rates without severe data overrun exposures.
Storage control unit service priority assigned to the channel is more efficient since accepted requests accessing the same n0n-busy storage unit are processed not on a first in/first out basis but according to channel positions.
Furthermore, storage units can be accessed as soon as they become available and units required by accepted channel requests can be cycled concurrently to compensate for their longer access time. This is particularly advantageous to channels which can overlap storage requests since the logical units required by the overlapped request may be cycled concurrently.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiments of the invention as illustrated in the accompanying drawings.
FIG. I is a block diagram of a computer system in which the invention is embodied;
FIG. 2 is a block diagram of the dedicated buffers of the invention;
FIG. 3 is a block diagram of the in and out buffer controls;
FIG. 4 is a logic diagram of a sequence monitor for controlling the sequence of loading and unloading the channel buffers of FIG. 2;
FIGS. 5A and 5B are a composite diagram of a priority circuit for use with the present invention; and
FIGS. 6A 6E comprise a flow chart of control for the invention described in the foregoing figures.
GENERAL DESCRIPTION Referring to FIG. I, the data processing system in which the invention is embodied is comprised of a storage control unit II) which is connected to channels I] and 12 over shared channel busses, channel address and data in bus 14 and channel data bus out 16; a central processing unit 18 and a main interleaved storage 20. The storage control unit is comprised of a channel in bus priority circuit 22 for granting access by one of the channels ll, 12 to the in bus 14; a plurality of data in channel buffers 24, 26, 28, 30; a storage priority circuit 32 for organizing storage requests into logical queues for each of the logical storages 0 3 of the main memory a channel data out buffer 34 for buffering data to the channels 11, I2; and a channel out has priority 36 for granting access to the common channel data bus out 16.
The [/0 channels [1, l2 communicate with the storage control unit via the shared channel busses l4 and I6. In addition to the main shared busses for information flow, there is provided channel-SCU control lines as an interface between the channels and the storage control unit. The interface includes the channel request lines 40, 42; channel response lines 44, 46; and the advance channel lines 48, 50. It should be understood that other control lines are necessary in such a system and a more complete description of typical controls can be found in the Boland, et al., U.S. Pat. application Ser. No. 776,859 Memory System filed Nov. 14, I968.
To gain access to storage 20, one of the channels 1 I, I2 raises a channel request line 40. The channel in bus priority circuit 22 responds to the request line and grants the highest priority channel access to the common channel address and data in bus 14 while shutting out all lower priority channels. The channel granted priority is immediately responded to by the channel in bus priority circuit 22 raising the appropriate channel response line 45, 46. The channel granted priority then places the desired memory address and data (if a transfer to memory) on the bus 14. The address and data and other control information are placed in a dedicated buffer for the channel granted priority. The dedicated buffers are not shown in FIG. I as they are actually physically organized. Instead, the buffers 24, 26, 28, 30 are shown rearranged into logical buffer queues for the storage. This rearrangement is done log ically in the manner by which the storage priority circuits 32 grant priority to a channel buffer request for logical storage 42. Briefly, logical storage requests are granted on the basis of priority among only those channels which are competing for the same logical storage. The request is granted when the logical storage becomes available and the logical storage available line 44 is utilized for this purpose by the priority circuit 32.
Once a channel request has gained access to a logical storage, the data is transferred from the logical buffer (for example, 24) to the logical storage (for example, logical storage 0).
When data transfer is from storage to the channel, the data stored in the logical storage requested is transferred to a channel buffer 34 which buffers the output data. The sequence of requests received at the dedicated buffers is maintained in correct order by a unique sequence monitor circuit (not shown in FIG. I) which unloads channel buffer data out 34 in the same sequence that the requests from a particular channel were received. The output from the channel buffer 34 is controlled by the channel out bus priority 36.
Two buffers 0 and I, referred to as a buffer group, are allocated to each channel. The buffer is split into a data in portion and a data out portion. The data in portion stores data to be stored in memory and address information along with control information. The data out portion stores data read from memory and corresponding controls. Thus, each channel is allocated one buffer group, consisting of two sections in'the channel in buf fers and two corresponding sections in the channel out buffers. Having multiple sections allows the storage control unit to accept multiple requests from each individual channel.
A sequence control circuit is provided to control the four dedicated buffer sections for each channel, i.e., the two bufier sections per channel for inbound and the two buffer sections per channel for outbound data. The monitor directs the in gating of requests into dedicated buffer sections as they become available but prevents channels from overrunning the assigned buffers when both sections are full. The sequence monitor insures that a channel receives storage information corresponding to requests in the same sequence that the channel initiated the requests.
DETAILED DESCRIPTION Channel Buffers (FIG. 2)
Each channel is assigned a buffer group. Each buffer group is divided into two sections, section 0 and section I. For example, in FIG. 2, channel I is assigned buffer group 1 comprising sections 0 and 1 in both the data in portion 50 and the data out portion 52. The channel data bus in 54 is 9 bytes wide (8 bits per byte) and includes 8 parity bits. The common channel address bus in 56 feeds the address buffer portion 58, the marks portion 60, and the keys portion 62. The definitions of the channel lines are more fully described in U. S. Patv No. 3,488,633 Automatic Channel Apparatus L. E. King et al., filed Apr. 6, 1964 and issued Jan. 6, I970, and assigned to the assignee of the present invention.
A source sink (S/S) section 64 is provided which is described subsequently. Briefly, this register is used for channel buffer identification of the data requests to and from logical storage.
The data out portion of the buffers 52 is also 9 bytes wide and provides for buffering data out to the channel data bus out 16. Also, a buffer section 68 is provided for buffering the checks from the storage for subsequent transfer to the channel. The data in register 70 feeds the storage data bus in (SDBI), and the address register 72 feeds the storage address bus (SAB). These busses feed the main storage 76 which is an interleaved storage comprising four logical storages 3. Data from logical storages is placed on a common storage data bus out (SDBO) which feeds the channel buffer 52. Buffer 52 stores the requested output data in one of the dedicated buffer sections for subsequent transfer to the channel data bus out 16.
Channel In Bus Priority Channel in bus priority is granted to one of the channels by means of channel in bus priority and control circuit 80 of FIG. 3 (this circuit includes priority circuit 22 shown in FIG. 1). In the embodiment shown, only two channels are considered and channel 1 has a higher priority than channel 2. For example, the channel request 40 enters the priority circuit 80. Since no other higher priority channel requests the data bus, priority is granted on the channel 1 response line 46. The request is placed in group 1, section 0 buffers of FIG. 2. The next request from channel 1 is placed in group 1, section 1. Subsequent requests from the same channel are placed in whichever section becomes non-busy first.
Storage Priority (FIGS. A, SB)
The common channel address bus enters a decoder 86 (FIG. 3) which decodes bits 27 and 28. These bit positions indicate which logical storage 0 3 is to be selected by the address stored in register 58 (FIG. 2) in the buffer section corresponding to the request. One of the outputs (Log Stor 0 3) of the decoder 86 is energized indicating one of the logical storages.
The channel in bus priority circuit 80 provides one output corresponding to the channel buffer and the section of that buffer loaded by the pending request, for example, channel in buffer loaded 1 0 line 88.
The output 90 of the decoder 86 is brought into the storage priority circuit 89 shown in detail in FIGS. 5A, 58. Assuming that channel in buffer loaded 1 0 line 88 is energized, a latch in register 92 (FIG. 5A) is turned on indicating the logical storage requested by this channel. Assume that logical storage 0 was decoded by the channel on the channel address bus. This causes the output 94 of register 92 to be energized. When the logical storage 0 becomes available, an output 96 (Log Store 0 Avail) is energized from logical storage controls 76 (FIG. 2). Therefore, when logical storage 0 is available, output 96 is energized which causes the AND circuit 98 in FIG. 5A to generate an output 100. The output 100 energizes OR circuit 102, the output 103 of which is request granted 1 0, meaning that the channel 1 request stored in section 0 can now access logical storage.
The output 100 also energizes OR circuit 104 (FIG. 58) to cause logical storage 0 selected output 106 to be energized.
Referring to FIG. 2, the logical storage 0 selected output 106 selects the logical storage within the logical storage block 76.
Channel In Buffer Selection As described above, an output 103 from the storage priority circuit 89 results when the logical storage becomes available for this highest priority request. The storage request granted 1 0 line 103 enters channel in buffer selection logic 9]. In addition, the channel in buffer loaded line 88 enters this logic. Thus, when the request is granted for section 0, and if section 0 is loaded, then the channel in buffer selection logic 91 energizes an appropriate output 93 which selects the section 0 of buffer group 1 (FIG. 2). As different buffer sections are selected by the priority circuits, the logic 91 moves the pointer 93 to gate the information into the appropriate sections shown in FIG. 2. The data on the SDBI is stored in the address pointed to by the address on the SAB.
In summary, one of the channel requests is granted priority by the channel in bus priority circuit and enters into the storage priority circuit 89. The request for logical storage is granted by this circuit taking into consideration whether or not the logical storage is available. Once the request is granted, the channel in buffer selection circuit 91 responds by energizing an appropriate output 93 to select the appropriate in buffer section for transfer to the storage.
Channel Out Buffer Control If the channel request is for a data transfer from storage to the channel, then the data from the logical storage 76 (FIG. 2) is stored in the appropriate section of the buffer group in the data out portion of the channel buffer 52. The data requested from the logical store is placed on the storage data bus out ($080) along with the source sink data. The source sink data enters the channel out buffer ID and check control logic 95 (FIG. 3). The source sink data identifies the information and this results in an output from the logic 95 out buffer valid 1 0 which indicates that output data has been stored in section 0 of buffer group I which corresponds to the request received from channel 1. The use of source sink data to control fetch and store requests is well known in the data processing art. See, for example, U. S. Pat. No. 3,462,744, Execution Unit With A Common Operand And Resulting Bussing System, Tomasulo et al., filed Sept. 28, 1966 and issued Aug. 19,1969.
Sequence Monitor (FIG. 4)
The channel in buffers 50, 58, 60, 62 and 64 of FIG. 2 are independent of the channel out buffers 52. In order to achieve maximum control efficiency, the sampling of a channel's request information into the in buffers and the out-gating of the contents of the channel out buffer to the channel are both a function of a sequence monitor shown in FIG. 4.
The sequence monitor is comprised of a section 0 busy latch 302 and a section 1 busy latch 304 and a retain sequence latch 306 for each channel buffer group. Thus, in the embodiment shown, FIG. 4 is duplicated for channel 2. Once a channel's request receives priority for use of the channel in bus, the channel in buffer loaded 1 0 line 88 is energized. This causes an output from AND circuit 308 to turn on the section 0 busy trigger 302. A section busy latch remains active until the storage is cycled for that request and the channel is so notified by energization of the advance channel line (FIG. 3). The three triggers 302, 304 and 306 are used to control the sequence in which the buffer sections of FIG. 2 are loaded and unloaded.
A detailed description of the state of the sequence monitor under possible section busy conditions is given below. For each case, the parameters for loading the channel in buffers are the same as those used for unloading the channel out buffers.
Loading of Channel in Buffers Case I Section and Section 1 are Non-Busy The sequence monitor directs the channel request to be loaded into section 0 and activates section 0's busy latch 302. Section 1s busy latch 304 remains off.
Case II Section 0 Busy, Section 1 Non-Busy The monitor recognizes sections 1's availability. The request is loaded into section 1 and section ls busy latch 304 is activated. Section 0 and section 1 busy latches are now active.
Case lll Section 0 and Section 1 Busy The sequence monitor inhibits this channel request from contending for Chan in Bus priority.
Case lV Section 0 Non-Busy, Section 1 Busy The monitor directs the channel request into section 0, however, section 0's busy latch is not activated because AND 310 is de-energized. Instead, the retain sequence trigger 306 is activated (AND 312 is energized). Section ls busy latch 304 is not affected.
Case V Retain Sequence Trigger On, Section 1 Busy The sequence monitor exercises the same inhibiting function as in Case lll. After section ls sequence is completed and the section 1 busy latch reset via AND 302, section 0s busy latch is activated via AND 311 causing the retain sequence trigger to be reset.
The storage address contained in each section of the Channel in Buffer is decoded to determine the logical storage the request seeks to access. Each channel buffer vies for storage priority independently. The time required to ingate storage data, for the channels request, into the Channel Out Buffer section, is dependent upon other channel interference, CPU interference and the interleaving of the storages. Therefore, the controls for loading the Chan Out Buffer are inde pendent of the controls for loading of the Chan in Buffer.
A Channel Out Buffer section 0 or 1 is considered valid during the elapsed time from the ingating of information from storage, into the section, to when the outgating of data, to the channel, from that buffer section occurs.
Unloading ofChannel Out Buffer Sections Case 1 Section 0 and Section 1 are Non-Busy This parameter is not applicable to the outbound sequence.
Case II Section 0 Busy, Section 1 Non-Busy Upon the validation of section 0 (Out Buf valid 1 0 line 314), the sequence monitor allows section 0 to contend for priority for use of the Channel Out Bus. After priority is granted to section 0, and the data is gated to the channel, Ch But" Adv to Ch granted 1 0 line 316 is energized and section 0s latch is reset.
Case "I Section 0 and Section 1 Busy The sequence monitor is pointing to section 0. Once section 0 is validated, it immediately contends for priority for the Channel Out Bus. Section 1 may be validated before or after section 0. However, the sequence monitor inhibits section 1 from contending for Chan Out Bus priority until section 0 has completed its transmission to the channel and section 0s busy latch is reset. After section 1 completes its transmission, its busy latch is also reset.
Case IV Retain Sequence Trigger On, Section 1 Busy The sequence in which section 0 and section 1 may be validated is random. However, the sequence monitor will buffer section 0 from the Chan Out Bus priority until section 1 has completed its transfer to the channel and section 1's busy latch is reset. After resetting section 1's busy latch, section 0's busy latch is activated, causing the retain sequence trigger to be reset. The sequence monitor now allows section 0's validated request to vie for priority for the Chan Out Bus. Upon completion of priority and the transfer to the channel, section 0s busy latch is reset.
DETAILED DESCRlPTlON OF CONTROLS Referring now to FIGS. 6A 6E, the controls for the storage control unit (SCU) of FIGS. 1 6 are described by means of a flow chart. The nomenclature is as follows. The chart refers to any channel n. Channel n is assigned to buffer groups n; 1 refers to a buffer group section 0 or 1. A trigger or latch designated nx refers to buffer group n, section I designating the channel buffer section. If a particular trigger or latch is common to a buffer group, it is designated n.
At block 200 the channel n issues a request. This request is sent to the SCU and since it is asynchronous with the SCU clocks, at block 201 the request is set into a sync trigger, a trigger that has been allocated for this request. (The control logic per se is not shown, however, this can be supplied by one having ordinary skill in the art.) This request then is set into a channel buffer request latch 203. Decision logic 204 determines if this request is for section 1 of the n channel buffer group. If the decision is yes, the logic proceeds to block 205. The decision in block 205 is whether or not both sections of the buffer 1-0 and 1-1 are busy. If they are both busy, the logic cannot proceed. However, if one or the other of the buffer sections is not busy, request It contends for in bus priority at block 207.
Referring again to block 204, if the decision was that request n is not for section 1 of the buffer group, the logic proceeds to decision block 206. Decision block 206 decides that, if this request is for section 1, is section 1 busy. If yes, section 1 is busy, then the logic waits until section 1 becomes not busy. If no, section 1 is not busy, the logic proceeds to decision block 207 which then allows this request to vie for priority on the in bus. Once the logic has initiated a request for the in bus, determine via block 208 if this particular request has highest priority of all the outstanding requests. if it does not, then this request remains in contention for priority until it is the highest priority contender. If this request is the highest priority contender, then proceed to block 209. In decision block 209, if in bus busy latch is on, the in bus is being presently used by some other channel. if yes, the in bus is busy with some other channel, wait until the in bus is no longer busy. Determine if the in bus is no longer busy by the fact that in block 210,
address valid latch A is on. When this latch is turned on, the request that has been serviced over the in bus is through with the in bus. Proceed to decision block 211.
On block 211, set a response trigger mt. This response is sent to channel it to indicate to the channel that it now has been allocated priority for the channel in bus and it may now put its data and address the in bus. From block 211, proceed to 212 where in the SCU a bus busy latch is set. This latch inhibits any other channel from getting use of the bus until this operation is completed. In block 213, a group response latch x is set. This group response latch is used to reset the channel request sync trigger which was set in decision 20]. The channel buffer request latch is turned off in block 215. This request latch was turned on in decision 203. In effect, the logic has prevented this one request which was received from the channel from re-entering the priority network. In block 216, response to channel n is raised. At block 217, the channel responds to the response line and pulses the in busses and the address valid signal. The address and data are then gated onto the in bus. In block 218 the address valid line from the channel turns on address valid sync flip-flop for synchronizing with the SCU clock system.
Simultaneously, in block 219, remember response flip-flop is turned on. The function of this flip-flop is to remember to which channel the response 216 was sent. Referring now to FIG. 6B, in block 220, the address valid flip-flop which was set in block 218 is used to synchronize the SCU by setting address valid latch A. Address valid latch A turns on at a predictable time with respect to the SCU clocks whereas in block 218, the flip-flop can turn on any time in the SCU clock cycle.
Proceeding from block 220, several internal housekeeping tasks are taken care of. In block 221, channel address bus bits 27 and 28 are decoded in order to determine which logical storage is selected. This decoder is shown in the FIG. 3 logic diagram. In block 222, sample the data, the address, the keys and the marks that are on the in bus and ingate this data into the appropriate channel buffer section. In block 223, a check is made to see if any of the data on the in bus has a parity error. If parity checks are detected, that information is loaded into the in buffer. At the same time, the source/sink field is set up. The information generated for the source/sink field is the channel identification (ID). The same buffer section into which data is loaded has that [D loaded into the ID buffer. When this request is serviced by storage, the request is identified via the source/sink bits.
In block 224, set address valid trigger A which feeds an address valid latch B at block 215 and also set channel buffer busy latch 226 in the sequence monitor (FIG. 4). The address valid latch B is just a pipeline chaining used in the controls in order to maintain the correct timing sequence.
Proceed to decision block 227: is address valid latch B on and trigger A off? This is an internal timing control which, if yes, causes the logic to reset the remember response latch block 228. The remember response latch was turned on in blocks 219 (FIG. 6A). At the same time that the functions that are shown in blocks 221, 222, 223, 224 are executed, the controls in block 229 reset the response trigger. This de-energizes the response line 230 to the channel. Then reset the group response latch block 231. After resetting this latch, at decision block 232, determine if another response trigger has been turned on. If none of the response triggers are turned on, then reset the in bus busy latch block 233 and allow any channel that may want activity on the bus to get access to the bus. If any response trigger is on, do not reset the in bus busy latch. This condition exists when some other request is waiting to get response and as soon as channel n dropped response, the other channel turns response right back on again. Therefore, there is no need to turn off the in bus busy latch because the in bus is immediately busy again.
Referring again to block 221, FIG. 6B, address bits 27 and 28 are decoded to determine which logical storage is selected by the channel request. Proceed to the decision block 234: is the requested logical storage busy? If it is busy, wait until it becomes non-busy. However, if it is not busy, proceed to decision block 235. This is the storage priority 89, FIG. 3. Is there any other channel buffer request that is in contention for this logical storage that has a higher priority than our request. If there is a request of higher priority, the logic loops back to block 234. However, if there is no other request or if the requests outstanding are of a lower priority than request n, then proceed to block 236 (freeze). Freeze is a function which is generated during the time when storage is sending data to the SCU. A high speed buffer may be used with the present invention. This has not been shown in the present embodiment. When a high speed buffer is present, there is a common bus which is shared between the channels and the main storage data out register. if the channel is sending data to the high speed buffer, that data is on this common bus. Only one channel can gate data on this bus, otherwise there would be an ORing effect of the two sets of data. Since a storage cycle cannot be stopped once it has begun, storage data goes on the bus and the channel is inhibited by the freeze from out gating its data onto the bus until the storage has completed its utilization of the bus. Once the freeze line has been turned off, then proceed to the logical storage handlers.
In block 237, gate the channel address, the marks, and the source/sink from the in buffer to the storage data bus in (SDBI). At the same time, in block 238, inhibit the CPU from selecting that particular logical storage. The CPU has separate priority circuits (not shown in FIGS. 1 5) for storage different from the ones of the channel. Since the channel has higher priority, once the channel has selected a logical storage, a line is sent over to the CPU priority circuits inhibiting the CPU from selecting that particular logical storage unit. Then set a logical storage busy trigger for the selected storage m. This storage busy trigger is set in block 239. The function of this storage busy trigger is to inhibit another channel or the CPU from selecting this logical storage unit.
During the same interval of time that the logic is executing blocks 237 and 238, the logic is executing block 240. In block 240 the logic sets the storage priority latch for the particular buffer section. This latch is used to reset the request for logical storage that was initially turned on in block 221. This resetting function is done in block 241.
Next, in block 242, set a storage priority trigger. This storage priority trigger is used to select the buffer section 1: corresponding to the request and to out gate the data and send the data for this operation to storage. This is done in block 243. In block 237, which was previously discussed, the address, the marks, and the source/sink were sent to storage. At that time the controls did not send the data. There is a difference in timing from the time the data is sent and the time the other control information is sent.
At this time, the logic is in the storage cycle shown in block 244. After completing the storage cycle, the storage busy trigger is reset at block 245. Resetting this trigger allows either another channel or the CPU to access this particular logical storage unit m. This trigger was set in block 239.
Referring to FIG. 6B, the outbound sequence of the channel buffer control area is described. Block 246 examines the source/sink ID bits and the storage data out (SDD) advance received from the storage unit. Then determine if this particular storage operation is for the channel or for the CPU at block 247. If source/sink bit 7 is on, this indicates that the advance just received is for a CPU operation and it is disregarded. If source/sink bit 7 is on, this indicates that the advance just received is for a CPU operation and it is disregarded. If source/sink bit 7 is off, then at block 248 decode the source/sinkbit in order to determine for which channel buffer section this request is intended. Since the advance received from storage arrives in the SCU two cycles before the data, the advance is delayed via a trigger latch combination block 249 for two cycles. This delayed advance is used to sample the data that arrives into the SCU. At the same time that the advance is being delayed, block 250 examines the source/sink bits which were received from storage to see if there are any checks that have been detected during this operation.
In block 251, set a channel out buffer COB request trigger for this particular request. Each buffer section has dedicated to it a channel out buffer request trigger. Proceed to block 252 which determines where the out buffer pointer (FIG. 2) is pointing to. The out bus pointer is a function of the sequence monitor and in effect, determines if the request for channel n is the first one that was received at the SCU. The first-in first-out (FIFO) sequence monitor is shown in FIG. 4 of the data flow. If the sequence monitor indicates that this request is the first one received in the SCU, then proceed to block 256. In order to inhibit the overrunning of the outbound sequence, logic described subsequently (block 273, FIG. 6E) inhibits the setting of the out bus request latches. [f block 256 is yes, this request is not allowed to continue, but waits until the out bus is no longer busy. Once the out bus is no longer busy, proceed to function block 257. Set channel buffer group request latch. This is the request that vies for priority for the out bus. Block 258 shows the out bus priority. If channel buffer group n does not have highest priority, it must wait and will honor that group which has the highest priority. If it does have the highest priority, which would be determined in decision block 259, then set channel buffer group out bus priority trigger block 260. The priority trigger, when on, indicates that this group n has received priority for the out bus.
Once the out bus priority trigger is on, then raise advance to channel n (block 261). This notifies the channel to expect data on the channel out bus. At the same time that the advance is raised, turn on the out bus priority latch 262. This out bus priority latch is used in the internal controls.
Referring to FIG. 6E, proceed to block 263 which turns on channel out buffer read request. In block 266, determine if the data is to be gated from the channel out buffer section 1 or from section 0. We do this by looking at the out bus pointer. If out bus 0 pointer is on, then proceed to block 264 which gates the channel buffer section 0 data to the channel. In block 265, gate any checks that have been associated with this request to the channel. These checks are stored in the out buffer for section 0. If decision block 266 indicates pointing to section 1, then out gate the data from section 1 of channel it shown in block 267. The checks associated with this request which are located in section 1 of the out buffer are also sent to the channel (block 268).
At this point all data and checks have been sent to the channel. Proceed to block 269 which initiates the channel out buffer reset chain. This chain consists of a series of triggers and latches used to reset the different requests and control lines that have been turned on earlier in the sequence. The first trigger turned off is the channel out bus request trigger (block 270). The turning on of the channel out buffer request trigger was shown on functional block 251 (FIG. 60).
Three functions are reset during the same time interval, those are blocks 27], 272 and 273. In block 271 reset the channel buffer group n request latch. This was the request latch which was used to vie for priority in the priority circuits and was turned on in functional block 257 (FIG. 6D). In block 272 reset channel buffer busy latch. The busy latch was set in functional block 226 (FIG. 6B). These busy latches again refer to the sequence monitor as shown in FIG. 4 of the data flow. In block 273 inhibit the setting of any channel out buffer request. In effect, this prevents another request from interfering with the sequence monitor. This inhibit function is the function that affected decision block 256 described previously (FIG. 6D). After completing functions 27], 272 and 273, then reset the out bus priority trigger block 274. This is the trigger that was turned on once priority had been granted to the out bus. This priority trigger was turned on in functional block 260 (FIG. 6D).
Previously in describing the outbound sequence, blocks 264, 265, 267 and 268, it was indicated that the data is sent to the channel during one interval time and the checks are sent at a later interval mf time. The reason for this is shown in decision blocks 275-278. Decision block 275 indicates a channel fetch (no) or store (yes) operation. If the channel is storing into main storage, then the data being sent to the channel is not used by the channel and there is no reason to check that data to see if there is any bad parity on the out bus to the channel. However, if the channel is fetching from main storage, then the data that is being sent to the channel is the data that the channel plans to use. The refore, activate the checking circuits. The fact that the data are being checked indicates that the checks have to be sent at some later time and that is the reason for the delay shown in 264-268. If in decision block 275 the decision is yes it is a store operation; proceed to block 278 which inhibits parity check for channel out bus to channel. However, if in decision block 275 the decision is no, this is a fetch operation. The logic block 276 determines if during this fetch operation an uncorrectable error was detected in storage. lf storage detected an error in the data, that same error occurs in the channel buffer and that error is not sent to the channels. Therefore, the channels are not informed that an error was detected in the channel buffers when, in fact, the error was from the storage unit. If an uncorrectable error (UCE) is detected from storage, the data that is sent to the channel is not checked. If no uncorrectable error, decision block 276 then proceeds to 277 which checks to see if good parity exists on the bus for the data being sent to the channel. The checking of the data is the last function that is executed for this request n. This completes one operation through the channel buffer area.
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
What is claimed is:
1. An input/output control system for controlling access to an interleaved memory divided into logical memory areas, comprising:
a plurality of channels, each assigned a rank in a priority ranking order;
a plurality of buffers at least one buffer for each channel, including means for storing requests comprising data and addresses of memory locations at which said data are to be stored;
priority determining means responsive to addresses stored in said buffers for granting requests to an available one of said logical memory in the priority order said request holds in the ranking order with respect to requests by other channels in said order for the same memory.
2. The combination according to claim 1 including priority means for granting priority to one of said channels at a time to access a common bus for transmitting said data and addresses to said buffers.
3. The combination according to claim 1 wherein said buffers comprise a predetermined number of buffers specifically dedicated to each channel; and including sequence monitor means for controlling the sequence of loading said predetermined number of said buffers specifically dedicated to a channel such that said buffers are loaded as they become available to said channel.
4. The combination according to claim 3 above wherein said plurality of buffers includes input buffers and output buffers and said sequence monitor includes means for maintaining a sequence of unloading said output buffers to said channel which sequence is the same sequence that said input buffers are loaded with said requests from said channel.
5. An input/output control system for controlling access to a memory having a plurality of independently accessible memory modules, comprising:
means for selecting the module to which a given access requestis made means for indlcatmg ii sald selected module IS busy to said access request;
a plurality of data channels having the capability of requesting access to said memory, said channels arranged in a priority order;
a plurality of buffers, a predetermined number of said buffers specifically dedicated to each channel;
a common bus interconnecting said channels and said buffers; and
means responsive to manifestations corresponding to requests from said channels stored in said buffers, said manifestations corresponding to requests to access the same non-busy memory module, for granting access according to channel priority as among only those channels having requests pending for the same non-busy memory module.
6. The combination according to claim 5 including priority means for granting priority to one of said chan' nels at a time to access a common bus for transmitting said manifestations to said buffers.
7. The combination according to claim 5 including sequence monitor means for controlling the sequence of loading said predetermined number of said buffers specifically dedicated to a channel such that said buf fers are loaded as they become available to said channel.
8. The combination according to claim 7 above wherein said plurality of buffers includes input buffers and output buffers and said sequence monitor includes means for maintaining a sequence of unloading said output buffers to said channel which sequence is the same sequence that said input buffers are loaded with said manifestations corresponding to requests from said channel.
9. For use in a system in which a plurality of users contend for a plurality of utilization devices, a priority circuit for resolving a plurality of said requests to use said utilization devices, in parallel comprising:
means for individually indicating the availability of said utilization devices;
means for registering manifestations of requests from each of said contenders, each of said registering means including means for indicating the utilization device desired; and
means responsive to said means for indicating the utilization device desired and to said availability signal for granting access to said device when said device becomes available and for not granting said request if manifestation of a request from a contender having a higher priority and for the same utilization device is registered in said registering means.
|Cited Patent
|Filing date
|Publication date
|Feb 16, 1961
|Aug 10, 1965
|Burroughs Corp
|Data processing system
|Aug 18, 1958
|Oct 5, 1965
|Sylvania Electric Prod
|Data processing system
|Feb 15, 1961
|Sep 20, 1966
|Burroughs Corp
|Computer system
|Nov 30, 1962
|Sep 20, 1966
|Burroughs Corp
|Data processor input/output control system
|Sep 12, 1966
|Jun 10, 1969
|Control system for interleave memory
|Jul 22, 1966
|Dec 2, 1969
|Gen Electric
|Data processing system including means for awarding priority to requests for communication
|May 26, 1966
|Dec 9, 1969
|Gen Electric
|Priority apparatus in a computer system
|Dec 13, 1965
|Sep 22, 1970
|Sperry Rand Corp
|Task control
|Citing Patent
|Filing date
|Publication date
|Feb 5, 1973
|Aug 6, 1974
|Honeywell Inf Systems
|Universal interface system using a controller to adapt to any connecting peripheral device
|Apr 4, 1973
|Aug 20, 1974
|Gte Automatic Electric Lab Inc
|Sense line processor with priority interrupt arrangement for data processing systems
|Oct 30, 1972
|Dec 31, 1974
|Amdahl Corp
|Data processing system and method therefor
|May 7, 1973
|Dec 2, 1975
|Burroughs Corp
|Memory cycle initiation in response to the presence of the memory address
|Nov 19, 1973
|Feb 3, 1976
|Amdahl Corporation
|Data processing system having a common channel unit with circulating fields
|Dec 20, 1974
|Jan 4, 1977
|Honeywell Information Systems Italia
|Data processing system having a plurality of input/output channels and physical resources dedicated to distinct and interruptible service levels
|Jun 5, 1974
|Jun 7, 1977
|Bell Telephone Laboratories, Incorporated
|Digital computer arrangement for high speed memory access
|Nov 24, 1976
|Aug 2, 1977
|Francois Gernelle
|Channel for exchanging information between a computer and rapid peripheral units
|Apr 25, 1975
|Nov 1, 1977
|Data General Corporation
|Memory access technique
|Sep 20, 1976
|Jan 24, 1978
|Sperry Rand Corporation
|Parallel requestor priority determination and requestor address matching in a cache memory system
|Dec 2, 1974
|Apr 11, 1978
|Compagnie Honeywell Bull
|Process management structures and hardware/firmware control
|Mar 28, 1977
|Sep 19, 1978
|International Business Machines Corporation
|Channel bus controller
|Feb 17, 1977
|Nov 21, 1978
|Xerox Corporation
|Interrupt request controller for data processing system
|Jul 25, 1977
|Dec 26, 1978
|International Business Machines Corporation
|Channel data buffer apparatus for a digital data processing system
|Jul 8, 1977
|Dec 4, 1979
|International Business Machines Corporation
|Task handling apparatus for a computer system
|Feb 21, 1978
|Jun 17, 1980
|Telefonaktiebolaget L M Ericsson
|Apparatus for giving priority to certain data signals
|Sep 11, 1980
|Oct 12, 1982
|Honeywell Information Systems Inc.
|Cache memory command buffer circuit
|Nov 14, 1980
|Jul 12, 1983
|Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme)
|Method and device for the counting and management of asynchronous events emitted by peripheral devices in a data processing system
|Mar 6, 1981
|Oct 18, 1983
|International Business Machines Corporation
|Synchronizing buffered peripheral subsystems to host operations
|Mar 23, 1981
|Oct 18, 1983
|Honeywell Information Systems Inc.
|Memory delay start apparatus for a queued memory controller
|Sep 27, 1982
|Feb 18, 1986
|International Business Machines Corporation
|Peripheral storage system having multiple data transfer rates
|Apr 2, 1984
|Mar 24, 1987
|Sperry Corporation
|Multiple output port memory storage module
|May 23, 1986
|Jul 21, 1987
|Tektronix, Inc.
|Asynchronous multiple buffered communications interface having an independent microprocessor for controlling host/peripheral exchanges
|Apr 21, 1987
|Jun 27, 1989
|501 Hitachi, Ltd.
|Storage control method and apparatus
|Jan 12, 1990
|Aug 6, 1991
|Digital Equipment Corporation
|Adjustable buffer for data communications in a data processing system
|Nov 12, 1993
|Nov 7, 1995
|International Business Machines Corporation
|Establishing and restoring paths in a data processing I/O system
|Aug 8, 1995
|Apr 23, 1996
|National Semiconductor Corporation
|Method and apparatus for receive frame sorting in a media access control/host system interface unit
|Oct 26, 1992
|Dec 10, 1996
|At&T Global Information Solutions Company
|Method and device for processing multiple, asynchronous interrupt signals
|Oct 12, 1995
|Apr 8, 1997
|National Semiconductor Corporation
|Automatic preemption recovery and frame repeat option in a media access control/host system interface unit
|Mar 16, 1995
|Dec 23, 1997
|Hitachi, Ltd.
|Interleave memory controller with a common access queue
|May 19, 1997
|Jan 11, 2000
|Motorola, Inc.
|Data communication system for controlling prioritization and transfer of data and method therefor
|Oct 20, 1997
|Feb 22, 2000
|Canon Kabushiki Kaisha
|Output method and apparatus
|May 28, 1998
|Oct 31, 2000
|Emc Corporation
|Input/output request allocation by establishing master command queue among plurality of command queues to receive and store commands, determine logical volume, and forwarding command to determined logical volume
|Mar 13, 2009
|Dec 20, 2011
|Kabushiki Kaisha Toshiba
|Portable electronic device
|Mar 13, 2009
|Jun 24, 2010
|Kabushiki Kaisha Toshiba
|Portable electronic device
|Aug 30, 1983
|Mar 1, 1984
|Sharp Kk
|Datensteuereinrichtung in lokalen verbindungsnetzen
|Dec 17, 1981
|Jul 7, 1982
|Fujitsu Limited
|Information processor with initial programme loading
|Dec 17, 1981
|Apr 4, 1984
|Fujitsu Limited
|Information processor with initial programme loading
|Jan 17, 1984
|Sep 19, 1984
|International Business Machines Corporation
|Priority system for channel subsystem
|Jan 17, 1984
|Apr 20, 1988
|International Business Machines Corporation
|Priority system for channel subsystem
|Dec 7, 1990
|Jun 19, 1991
|International Business Machines Corporation
|Apparatus for conditioning priority arbitration in buffered direct memory addressing
|Dec 7, 1990
|Feb 19, 1992
|International Business Machines Corporation
|Apparatus for conditioning priority arbitration in buffered direct memory addressing
|Sep 17, 1982
|Mar 31, 1983
|Racal Data Communications Inc
|Microprocessor with memory having interleaved address inputs and interleaved instruction and data outputs
|Apr 13, 1994
|Oct 27, 1994
|Accom, Inc.
|Adaptive asynchronous media server request mechanism
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification


text:
Caveboy Escape
By AppXplore Sdn Bhd
This app is only available on the App Store for iOS devices.
New - Help Caveboy escapes the new haunted Arctic zone!!
Caveboy Escape offers innovative puzzle gameplay, utilizing subtle match-3 and connecting tile gameplay that feels fresh and will tickle puzzle gamers' brains. It takes a keen eye and quick thinking to navigate Caveboy to the exit – Finding the right path will be a challenge as the size of the labyrinth continues to grow. Time is also of the essence as Caveboy must reach the exit or the maze will collapse.
Caveboy Escape Features:
- Maze escape puzzle gameplay: new innovation of match-3 and sliding tile puzzles… it's a whole new type of puzzling fun
- Solve extremely tricky pathway puzzles under the pressure of time
- Casual Challenge: pastel graphics and a mellow soundtrack, with a time limit that will challenge you without being too harsh
- Be a Star Collector: collect all stars in all stages and beat your friend's timing
- High Score and Achievements
- Free to play universal app for iPad, iPhone
- Game Center Support
What's New in Version 1.7.0
- The quantity of the elixir from the store has been increased!
- Support for iOS 11
- Bug fixes
- Free
- Category: Games
- Updated: Sep 22, 2017
- Version: 1.7.0
- Size: 38.4 MB
- Language: English
- Seller: AppXplore Sdn Bhd
- © 2014 Appxplore
Compatibility: Requires iOS 7.0 or later. Compatible with iPhone, iPad, and iPod touch.
Top In-App Purchases
- A few Elixirs$0.99
- Unlock All$3.99
- Unlock Survival Mode$1.99
- Many Elixirs$9.99
- Several Elixirs$4.99
- Unlock Ruin 3$1.99
- Unlock Ruin 2$1.99
- Unlock Forest 1$1.99
- Hundreds of Elixirs$19.99
- Unlock Forest 2$1.99

subset: commoncrawl


text:
A Little Night Music Trailer (2002)
"Život dvojice najboljih prijateljla mijenja se onog trenutka kada se jave na mobitel mrtvaca..." 01 January 2002 Comedy 95 mins
Spasoje and Cole are cute and silly boys who constantly find themselves in risky situations. They work in a morgue. One night they heard mobile phone that rings in your pocket just dead guy. Of course, they can not resist, and answer the call. On the other side man voice ordered them to go to a specific address and get some money. Cole and Spasoje don't reject easy profit...
Watch the official A Little Night Music 2002 trailer in HD below or find more A Little Night Music videos on Vidimovie.


text:
A few weeks ago I started having baby blues like crazy. I told my husband who told me I was crazy for considering another child. But, I had a feeling our family wasn't complete. Then, I thought about it. My kids are 11 and 7. No way did I want another baby with those ages, so we discussed a puppy. And that's exactly what we did. Meet Bella, our chocolate/yellow lab mix.
She is such a good girl. She just turned 10 weeks old, already sits, likes to suck on my finger like a binky and is house training very well with minimal pee accidents.
I'm her mom, she's my baby and I want what is best for her. I did some research on human foods that are safe for pets and knew I would start making her dog treats. I want was is best for her with minimal ingredients and healthy. So I did exactly what I did with my children, trialed foods. For the last 14 days I trialed sweet potatoes, pumpkin, oats and flax and she had no issues. So we made healthy homemade dog treats this morning.
To say she loves this is an understatement. When they cooled I gave her one. She sniffed and ate it in seconds. Then she was attacking the storage container I placed them in.
Of course I tasted a bite. Pretty bland but keep in mind she is a puppy so I will be trialing all foods before making new biscuits.
These are perfect for puppies and dogs loaded with vitamin A, high in fiber and no fat. Crunchy on the outside, soft(ish) on the inside!
Update: So the day after being in a sealed container, these turned completely soft, cookie like. Bella is teething like crazy and loves the soft texture.
- 2 1/2 cups oat flour * see note on how to make oat flour
- 1/2 cup pure pumpkin
- 1/2 cup cooked mashed sweet potatoes
- 1 tablespoon ground flaxseed
- Preheat oven to 350
- Place all ingredients in a bowl.
- With your hands, mix the mixture until ball forms.
- With a rolling pin, roll out to about 1/2 inch thick.
- With a [url href="http://www.amazon.com/gp/product/B0027CU0GS/ref=as_li_ss_tl?ie=UTF8&camp=1789&creative=390957&creativeASIN=B0027CU0GS&linkCode=as2&tag=thekiddiescornerdeals-20″ target="_blank"]dog bone shaped cookie cutter,[/url] cut out. I used the smallest in this [url href="http://www.amazon.com/gp/product/B0027CU0GS/ref=as_li_ss_tl?ie=UTF8&camp=1789&creative=390957&creativeASIN=B0027CU0GS&linkCode=as2&tag=thekiddiescornerdeals-20″ target="_blank"]set[/url]
- Lightly spray a baking sheet
- Bake 20 minutes, cool on wire rack and store in container..


text:
Fulton Bank
Fulton Bank, Womelsdorf Branch
2400 Conrad Weiser Parkway
Womelsdorf, PA 19567
Berks County
Phone: Phone number not supplied
Sponsored Links
Details of Fulton Bank, Womelsdorf Branch, a branch is located at Womelsdorf, Pennsylvania 19567.
|Sunday - Closed
|Branch Hours:
|Monday to Thursday - 9:00 A.M. - 5:00 P.M.
Friday - 9:00 A.M. - 6:00 P.M.
Saturday - 9:00 A.M. - 12:00 P.M.
Sunday - Closed
The bank hours are subject to change. Please let us know the opening hours.
|Office Name:
|Womelsdorf Branch
|This is branch of Fulton Bank
|Identification for Branch:
|# 216009
|Branch Deposit:
|$ 41,104 (in thousands of dollars)
|Established Date:
|Tue, 17 Nov 1970
|Run Date:
|Fri, 15 Aug 2008
|Branch County:
|Full Service Brick and Mortar Office
|Institution Name:
|Fulton Bank
|Institution FDIC Certificate:
|# 7551
|Institution Class:
|Commercial bank, national charter and Fed member, supervised by the Office of the Comptroller of the Currency
Map & Driving Directions
You can also find Fulton Bank locations on usbank101.com with main office and bank branches list.
Bank Nearby:
- Fulton Bank Womelsdorf Branch (0 mi)
- Manufacturers And Traders Trust Company Womelsdorf Branch (1.62 mi)
- Jonestown Bank And Trust Company Newmanstown Branch (2.66 mi)
- National Penn Bank Robesonia Branch (4.13 mi)
- PNC Bank Stone Ridge Branch (4.45 mi)
- Wells Fargo Bank Robesonia Branch (4.59 mi)
- Sovereign Bank Robesonia Branch (4.92 mi)


text:
Guns N' Roses fan forum.
#guns, roses, appetite, discussion, rose, music, bumblefoot, buckethead, slash, richard, forus, tommy, stinson, duff, izzy, stradlin
Welcome to Airsoft forum UK for all enthusiast young or old, sales, wanted and swaps, BB guns and BB pistols, loadouts and other tactical accessories come and chat.
airsoft, #guns, pistols, tactical, accessories, rifle, bb`s, sales


text:
Featured property
Featured property
Featured property
£485,000 Fixed Price
The Stables, Totleywells Steadings, West Lothian
A new build house with 4 bedrooms and 2 bathrooms and en-suite. the spacious living/kitchen area has french patio doors leading to a private courtyard garden. the property also has…
£220,000 Fixed Price
The Granary, Totleywells Steadings, West Lothian
This refurbished property has 3 bedrooms and 1 bathroom. it has a bright kitchen and separate living room and ample storage in the hallway. the property has its own private garden…
£167,750 Offers in Excess of
3 Church View, Winchburgh, Broxburn, EH52 6SZ
Immaculately-presented, three bedroom, modern mid-terrace house with private gardens, and an allocated parking space, located in a quiet and factored residential development in winchburgh,…
£155,000 Offers Over
3 Bedrooms End Of Terrace House for sale
Church View, Winchburgh, West Lothian, EH52 6SZ
Fantastic three-bed terraced family home - early viewing recommended
£150,000 Offers Over
3 Bedrooms Terraced House for sale
A modern and well presented terraced villa located in the heart of winchburgh's new and expanding community, offering a great starter home for the young professional or family…
£89,995 Offers Over
Kirkhill Terrace, Broxburn, West Lothian, EH52 6JG
A competitively priced & deceptively spacious two bedroom lower cottage flat close to all amenities.
£88,000 Offers Over
Crossgreen Drive, Uphall, Broxburn, EH52
* upper villa apartment* freshly decorated in neutral tones* spacious lounge* fitted kitchen with appliances* 2 double bedrooms* bathroom with shower above the bath* rear enclosed…
£74,995 Offers Over
Cardross Avenue, Broxburn, West Lothian, EH52 6JE
A competitively priced two bedroom upper cottage flat in popular location.
Marketed by:
McEwan Fraser Legal Solicitors & Estate Agents, Edinburgh
Claremont House
130 East Claremont Street
Tel: See phone number 0131 524 9797
Website: Go to Agent Website


text:
Giyad.org ranks
#4,176,678 in the world and generates
510 Page views for daily.
FreeWebsiteReport estimates Giyad.org for a valuation of
$1,117 USD for it's visitor traffic that has the potential for CPC and Display-based advertising.
This traffic data suggests the Advertisers with a Traffic Acquisition Cost (TAC) of
$1.53 for daily and
$45.90 for monthly to spend on advertisements with Giyad.org. Giyad.org's page load time for
90th percentile measures at 2 sec. Giyad.org receives most of it's
organic referrals traffic from 9 websites around the world. Giyad.org servers are located in the Turkey.
|Time Average
|Site Rank
|View Rank
|Views Per-User
3 Month
Gümüşhane İktisadi Yardımlaşma ve Dayanışma Derneği
Google Safe Browsing - Safe website. Clean from Viruses, Malicious Worms, Adwares, Trojans, Spywares and Suspicious Phishing Attacks.


text:
So Yahoo! news describes Robyn Lawley as a, "model with normal body," and then goes on to describe said body:
The thing is, when you look at Robyn Lawley, who is 6'2" and wears a size 12, you hardly see a plus sized woman. Lawley has a banging body. Not "a great plus size body" or "a great skinny body," she just has a great body! And while plus size should not be taken as an insult, it's just ridiculous to call this woman "plus size." Even though Lawley has built a career as a plus size model, she has expressed that she dislikes the term, "In the beginning, I didn't mind getting called (plus size), but I am not a plus-size person," she said in a press release earlier this year, "I don't think anyone should be called plus size."
The only problem with this line of reasoning is that while the average American might be a size 12 (actually 14), the average American woman is 5'4", not 6'2". Plus, given the sheer variety of women's sizing options (see this for considerably more info), the whole notion of size 12 being average is simply useless. The truth that everyone can see is that Robyn Lawley is not some fatass size 12 with "real curves," but rather a relatively slender girl with pretty much ideal proportions. She is larger, to be sure, but this is mostly a function of height and having a skeletal frame solid enough to support it.
Using a model like Robyn Hawley to make fat women feel good about themselves is nothing but disingenuous mythologizing. Most size 12 women look nothing like Ms. Hawley, and certainly need no further encouragement to maintain their probably corpulent size. If anything, Ms. Hawley's looks should serve as an inspiration to women everywhere to lose weight and make the most of what they've got. And, frankly, it's utterly ridiculous to even suggest that just because a tall woman looks good as a size 12 means that all women will look good as size 12s.


text:
Don't be so shocked to see veteran actor Jerry Mofokeng back in action when you tune in to watch tonight's episode of e.tv's popular soapie Scandal.
The new episode will undoubtedly come as a surprise to fans who were witnesses to Jerry's character being killed.
Read Also: Actress Lusanda Mbane Joins e.tv's Scandal!
Apparently, Jerry's villainous character Neo Mokethi has managed to survive in prison and is coming back to unleash more mayhem.
e.tv publicist Michael Pocock in a statement confirmed the news. The veteran actor who has been filming with the cast is set to reprise his crime lord character tonight.
"We can confirm that Jerry Mofokeng has returned to the cast of Scandal! He will play the role of Neo Mokhethi. He will make his return to TV screens tonight in a surprise appearance," he said.
"He has been filming with us for a while now. The cast and crew have loved having him back and he has also enjoyed his return. He has been wanting to come back for some time now and we are excited to have him back on the show."
Read Also: E! Cameras Stop Rolling On The Kardashians' Reality TV Show
Meanwhile, other cast members are excited about the return of Jerry on the show. One of the cast members Kgomotso Christopher said that it is an "honor" to be working with this "gentle giant of theater." She went on to recount her encounter with the gentle giant of theatre.
"When I was 17, I was walking from high school to the taxi rank and I bumped into a theater giant across from the Joburg Theatre. I stopped him, opened my homework diary and asked him to autograph it. He wrote "Reach for the Stars"…his name was Ntate Jerry Mofokeng," she wrote in her Instagram note dedicated to Jerry.


text:
United States counts the cost of storms
The devastating tornadoes and storms that killed more than 356 people in the southern US this week will complicate efforts by southern states and municipalities to stabilise their finances, but federal assistance should blunt the disaster's economic impact.
The deadly tornadoes hit Alabama hardest, killing 228 people there, and while the cost of damage is yet to be estimated, they struck as the state struggled to balance its $19bn (€12.8bn) budget in the face of falling revenues.
Mississippi, Georgia, Louisiana, Arkansas and Tennessee suffered a less severe toll but those states are also making cuts and spending less to close budget gaps.
The Deep South as a whole has suffered some heavy blows in recent years, such as the Gulf of Mexico oil spill last year and Hurricane Katrina in 2005.
In Alabama, in the short term, income loss, business loss, property damage and loss of sales tax revenue resulting from the destructive tornadoes will hurt that state's revenue, analysts said.
"It's going to be a very significant negative for at least two or three quarters, if not more, for the whole state," said Jennings Marshall, economics professor at Samford University in Birmingham, Alabama.
"Since the economy's already been struggling, if you just take three to four percentage points from the state, that's a big impact."
US President Barack Obama promised strong federal aid when he visited Alabama to see for himself the havoc wrought by the violent storms.
Many of the damaged businesses were insured so when payments kick in it will spark a mini boom that will help state finances, not least by providing employment, analysts said.
In the disaster's wake, Alabama was focused on rescue and recovery, said Governor Robert Bentley, and he welcomed Mr Obama's promise of assistance.
"While I am asking for federal money, the federal government could benefit from our fiscal example," Mr Bentley said, in a reference to the state's efforts to cut costs.
Mr Bentley announced deep cuts in March to education and other spending programmes and the state may lay off 1,000 employees. While its unemployment fell to 9.2 per cent in March, it is still above the national average.
The Deep South's experience of recovery from past disasters provides clues as to what could happen next.
In 2005, Hurricane Katrina flooded New Orleans and caused tens of billions of dollars of damage to Gulf Coast economies. The region is still recovering economically.
Analysts said one determinant of financial impact was the extent to which the damaged area was locked into the state's overall economy.
"Value is more than price or cost. No matter how much you restore everything, there is value in the things that have been lost," said Sam Addy of the University of Alabama.
Sunday Independent


text:
- Please select a date to see the proper prices!
- Meal can be requested on the spot
Best offer
89 € / person / night, no meal
Description of the Accommodation
Rooms, services Appart'Hotel Odalys Les jardins d Elisa Beausoleil is offering 66 comfortable rooms to guests looking for accommodation in Beausoleil. Parking possibility is available nearby for guests arriving by car. You may secure your valuables in the safe. The hotel is offering wireless Internet connection (WiFi) without charging extra fees, so you may go online anytime with your laptop during your stay. An exact and detailed list of equipment in the rooms and of the services provided by Appart'Hotel Odalys Les jardins d Elisa Beausoleil you will find on the information sheet below, including any applicable additional fees.
Payment Depending on the selected date, room and price, you may need to provide credit card guarantee or advance bank card payment to finalize your reservation.
Arrival, opening hours The earliest time to check in to your room is 14:30, the latest time to check out of your room is 11:30. The personnel is at your service in French and English languages.
Appart'Hotel Odalys Les jardins d Elisa Beausoleil rooms Rooms
- Please select a date to see the proper prices!
Accommodation services
Parking (13 €/night)
Free WiFi in shared places
Pet friendly (10 €/night), Elevator, Safe deposit box
Hairdryer, Washing machine


text:
08/04/04 04-91
Joyce has been charged with seven counts of armed robbery, eight counts of burglary, one count of atte
Joyce targeted small businesses occupied by a lone female proprietor. Joyce would brandish a knife and order the women to give him the money, and then force them to the floor behind the cash register while he made his escape.
The robberies occurred at these locations:
Inspector Dan Gardner of the Robbery Detail will be available for interviews in Room 454 of the Hall of Justice until this evening.
850 Bryant Street, Room 549, San Francisco, CA. 94103


text:
- 0 joburi active
- Intre 51 si 100 angajati
- http://www.softelligence.ro/
Softelligence is a leading international provider of business software services that combines powerful technological know-how with genuine customer orientation. Apart from software development and integrating solutions based on SAP, Oracle, Microsoft and SalesForce, Softelligence harnesses its broad expertise also by developing Softelligence EBS platform, a powerful combination of collaborative crm software, lastest web & mobile technologies and business process automation, certified by more than 1.000.000 end-users across all business verticals. Operating both in CEE as well as in UK, Sweden, Austria and Germany, Softelligence is ranked by Deloitte among Top 50 fastest growing technology companies in Europe and EMEA.


text:
Complaint Review: Hydra White
- Hydra White
United States of America
- Phone: (866) 913-2654
- Web: www.hydrawhite.com
- Category: Liars
Hydra White DEMAND LETTER TO ENFORCE THE CONTRACT AND CANCEL "MEMBERSHIP" Internet
The contract for the MEMBERSHIP is a valid and enforceable contract; consideration and performance requirements have been met and you are not authorized to charge anything more to my credit card or checking account. I have cancelled the account (which conversation was recorded and your customer service representative, Jose #0504, was advised of same) after which your service agent advised me that I was sent a one month supply and that I must return the unused portion at my expense. You did not represent this and I would never agree to that if you did. I DID NOT AGREE TO ORDERING A ONE MONTH SUPPLY - I agreed to a trial MEMBERSHIP. Whatever you sent under the membership that was cancelled within the same say after payment was collected and your site said "the order has been shipped" is mine to keep with no further charge.
I NEEDEN'T ADVISE YOU BUT YOU ARE HEREBY ON NOTICE THAT PURSUANT TO THE LAWS OF FLORIDA - ANY UNAUTHORIZED SHIPMENT THAT IS SENT CAN BE KEPT BY THE RECIPIENT WITHOUT CHARGE OR NOTICE. Even if such law was not in effect, simple contract conditions have been met and the parties' recovery is limited to the four corners of the contract!
If you do not confirm that the MEMBERSHIP has been cancelled, that the amount shipped is mine to keep at no further charge, and no further charges will be made to account, immediately, I will be forced to contact the FRAUD DIVISION OF THE U.S. ATTORNEYS OFFICE; THE STATE ATTORNEY'S OFFICE, AND THE BETTER BUSINESS BUREAU. This is fraud, misrepresentation and theft if you fail to perform and comply with the above. You have not committed any criminal act thus far that I will report you for although I very well could report you for fraud at this time. Furthermore, I will be sure to post anywhere I can that your company is a farce.
cc: email@example.com;
Does your business have a bad reputation?Corporate Advocacy Program™Fix it the right way.
Set the record straight:Arbitration Program
This report was posted on Ripoff Report on 01/02/2013 03:14 PM and is a permanent record located here: http://www.ripoffreport.com/reports/hydra-white/internet/hydra-white-demand-letter-to-enforce-the-contract-and-cancel-membership-internet-990146. The posting time indicated is Arizona local time. Arizona does not observe daylight savings so the post time may be Mountain or Pacific depending on the time of year. Ripoff Report has an exclusive license to this report. It may not be copied without the written permission of Ripoff Report. READ: Foreign websites steal our content
If you would like to see more Rip-off Reports on this company/individual, search here:
ZipBooks Accounting Software
Advertisers above have met our
strict standards for business conduct.


text:
1st Chaparral
We Race a C6R
Victorious 70
69 Racer
67 Racer
66 Racer
65 Racer
63 Racer
Dirtball #238
Wedgie #8797
International Orders:
Here is a method you can use to order through the net store itself. Use my
address in the net store as ship to & use your address in the net store as
billing. That way you can fool the net store on the destination since it get
confused with international. We are smart enough to figure out that we are not
going to ship it to ourselves. You must also be smart enough to figure out that
the domestic shipping will not apply. Don't forget your phone number for export
documents. Note: the software will add state tax automatically. But since we
ship your order that is not actually charged when your c/card is billed, but
the software is not smart enough to figure that out. DO NOT use DocRebuild as your user name. DO NOT use DocRebuild as billing name.
Important: include your email address. And note the year, convertible,
coupe, t-top, engine size 265, 283, 327, 350, 396, 427, 454. And options like
Air Conditioning, Automatic, PS, PB, PW, etc.
address DocRebuild 25 Wells St. Bridgeport, CT 06604 Regretfully the Warehouse is only open by appointment after 38 years.
Note: there is a $4.00 fee added to some
international shipments because all of the export documents must be filled out
by hand; the USPS required immediate payment & we must delivery to the Post
Office, whereas common carriers bill us weekly or monthly & pick up at our
>>>>>> International Orders I DO NOT QUOTE INTERNATIONAL SHIPPING RATES <<<<<<
It is, whatever the carrier charges! Note shipping 1 lb. to Canada with insurance is approximately $25-35; shipping 1 lb. to Europe with insurance is approximately $30-40; shipping
1 lb. to Oz with insurance is approximately $35-45. We DO NOT ship
without insurance - because uninsured ones are "lost" or stolen by
1963-1974 Corvette Fuel Tank Overflow Hose Support Spring Replaces GM 3829398 made in USA
A quality heat treat compression spring with the authentic wire size, OD, number of coils & Black oiled finish. Made right in Connecticut. This spring assures
that the lower end of the hose does not get kinked when it is strapped
close to the rear bumper inner support bar.
DocRebuild was the first to offer this oddball long fuel hose spring. Take a good look at the other repro before you get a dud that collapses upon insertion. 1963 1964
1965 1966 1967 1968 1969 1970 1971 1972 1973 1974


text:
BlakLez has been rather mum about his album and he has always promised us that its coming. Well its coming alright as he tweeted about the type of album we should expect.
My album is going to give so many people hope. I'm not worried about selling gold, it's a minimum expectation. It'll be done.— Blaklez (@Blaklez) August 2, 2015
From this tweet I can imagine that Blaklez is chasing another accolade. Now it makes sense why he mentioned these Wale references cause you see Folarin always goes left when hip hop goes right. Are we going to hear an album from Lez that's turnt down?
I get the sense that some of you have yet to listen to Ambition.— Blaklez (@Blaklez) August 1, 2015
I think we were being warned here on the type of album that is coming our way.
Meek Mill's verse on Ambition was fire????????????... So much so that he smacked both Folarin and Rozzay. That's the Meek I rock with— Blaklez (@Blaklez) August 1, 2015
I'm going to say something crazy. Wale's Ambition LP is slightly better than the Album About Nothing. I love both. You're welcome to @ me— Blaklez (@Blaklez) August 1, 2015
Why on earth is Wale slept on? The world's lost its mind I tell ya— Blaklez (@Blaklez) August 1, 2015
The whole.Ambition album by Wale is all types of hot. Dude knows how to put a project together— Blaklez (@Blaklez) August 1, 2015
However you choose to decipher these tweets its safe to say that BlakLez is got a dope album coming out. We cannot wait to hear it and you should be looking forward to it to.


text: I'm running into a strange problem. Sitting in my living room with both WiFi and 3G, I sometimes discover I can't connect to Gmail, the internet, etc, and then later I can. As far as I can tell, everything is active. I can connect with my computer using WiFi, so the server is up and running, and my wife's iPod can connect using WiFi. Am I doing something wrong, is there a problem with my Android phone, or is just something that happens with Android? Right now, for example, I am trying to send an email using Gmail and it's sitting in the outbox. I can send and receive on the computer fine. It's frustrating.


text: Human Rights Observatory Foreign Diplomats Join Forces to Plant Trees in Washington Diplomats from 12 countries gathered to plant trees in Washington recently at the International Cultural Center, where 21 foreign missions are located. It's part of the U.S. State Department's Greening Diplomacy Initiative. Austrian Ambassador Hans Peter Manz, whose career as a diplomat has moved him from country to country every five years, called the tree plantings an opportunity to experience the American culture of neighbors working together. "If we can put some more trees...Read complete article© Voice of America - Friday, November 6, 2015


text:
The epic and controversial story of a major breakthrough in cell biology that led to the conquest of rubella and other devastating diseases.
Until the late 1960s, tens of thousands of American children suffered crippling birth defects if their mothers had been exposed to rubella, popularly known as German measles, while pregnant; there was no vaccine and little understanding of how the disease devastated fetuses. In June 1962, a young biologist in Philadelphia, using tissue extracted from an aborted fetus from Sweden, produced safe, clean cells that allowed the creation of vaccines against rubella and other common childhood diseases. Two years later, in the midst of a devastating German measles epidemic, his colleague developed the vaccine that would one day wipe out homegrown rubella. The rubella vaccine and others made with those fetal cells have protected more than 150 million people in the United States, the vast majority of them preschoolers. The new cells and the method of making them also led to vaccines that have protected billions of people around the world from polio, rabies, chicken pox, measles, hepatitis A, shingles and adenovirus.
Meredith Wadman's masterful account recovers not only the science of this urgent race, but also the political roadblocks that nearly stopped the scientists. She describes the terrible dilemmas of pregnant women exposed to German measles and recounts testing on infants, prisoners, orphans, and the intellectually disabled, which was common in the era. These events take place at the dawn of the battle over using human fetal tissue in research, during the arrival of big commerce in campus labs, and as huge changes take place in the laws and practices governing who "owns" research cells and the profits made from biological inventions. It is also the story of yet one more unrecognized woman whose cells have been used to save countless lives.
With another frightening virus imperiling pregnant women on the rise today, no medical story could have more human drama, impact, or urgency today than The Vaccine Race.
©2017 Meredith Wadman (P)2017 Penguin Audio
"This is a story about the war against disease - a war without end - and the development of enormously important vaccines, but in telling that story, in showing how science works, Meredith Wadman reveals much more. I loved this book." (John M. Barry, New York Times best-selling author of The Great Influenza)
"Great information "
Wonderful read and very insightful. Provides rarely known details about the way science works and also helps everyone understand the necessity of some choices.
"Fantastic book and excellent reader"
The performance was excellent. It wasn't flat but also didn't distract from the book. Just the right amount of emotion. The reader's voice is pleasant and enjoyable to listen to.
I don't typically read books that have a big science component because, although I believe in the importance of science, I have little background in it and my lazy brain usually has a hard time paying attention and following what's being discussed. I'm glad I made an exception with this fantastic book, however. To begin with, even though the book does cover a lot of scientific ground, the writer explains everything so clearly and simply that I actually understood all of it and maybe even retained some of it. Besides that, this is a book not only about science but also about politics, ethics, history, economics, and most interestingly (at least to me) the complexities of human nature and how it can get the best of even tho most brilliant among us. Wadman weaves all the skeins together with a masterful blend of storytelling skill, knowledge, compassion, and here and there a welcome touch of humor. Whether she's writing about a top scientist or a child afflicted by rubella, you feel that each person in the book is real and multi-dimensional. I came away from the book with a chilling new awareness of how much politics can affect the way medical advances are translated (or not) into actual therapies and a sense of how limited we all are by our circumstances and our selves.
Report Inappropriate Content
If you find this review inappropriate and think it should be removed from our site, let us know. This report will be reviewed by Audible and we will take appropriate action.


text:
My Artist Story
2014 Gallery
2015 Gallery
2016 Gallery
2017 Gallery
Art Shop
100 Faces
What People Are Saying
Stephanie Gagos
soulful vibrant healing art
My Artist Story
2014 Gallery
2015 Gallery
2016 Gallery
2017 Gallery
Art Shop
100 Faces
What People Are Saying
I love to assist in empowering women as well as helping women who were wounded as children heal and awaken to their lives. My courses take each woman on a journey of awakening. My work prompts women to own their truth and and heal from the remnants of what may still be holding them back. I work both with women who were wounded as children and women who want to step into a more empowered life.
Reclaiming the Lost Child Through the Power of YES
Healing the Mother Wound
Inner Child Healing Workshop
Facing Your Fears Workshop
Painting to Heal: A Basic Art Healing Course
Anger Mini Workshop
All classes are non-refundable.
Sign up for updates on healing art journey classes here
I am a Healing Guide, Writer, Artist and Facilitator of Healing Circles for Women.
My healing art journeys are invitations to journey with yourself and others into a greater knowing and understanding of who you are beyond your wounding.
The truth is we are all wounded in some way.
We have all been shut down and told stories we have come to believe about ourselves.
These stories often get in the way of what we want and who we want to be.
I believe we can create a new story. I believe it because I have created a new story for my self and continue to do the "work" necessary to evolve, expand and live and love more fully despite a horrific childhood.
I believe in the power of loving community as it has been the way I have healed most deeply.
I also believe in taking our healing in our own hands, in self reflection and awareness, questioning, journal writing, art, movement, breath and stillness.
I work primarily with women on a healing path and women who have done some healing work and would like some community and guidance in the process of truth seeking, healing and empowerment
Some but not all of my courses are geared toward women who were wounded in childhood such as the Inner Child Healing Workshop, Healing the Mother Wound, Healing the Father Wound (coming soon)
As a survivor of childhood sexual and physical abuse, this is my "heart work".
I also love to work with women who want to say yes in their lives, offer their gifts and shine their bright light in the world. The Yes courses are truly empowerment courses meant to awaken us to our aliveness and light our fire so that we can make our passions come to life.
All of my courses are invitations to go deep with yourself for a period of time, to journey with yourself and others.
Trusting the process, confidentiality, presence, readiness and commitment are vital to the process.
Please read the description of the course carefully and see if it is something that resonates with you and something you are ready for.
Ask yourself:
Do you have the time and energy to devote to it?
Can you show up and be a support to others during the course (this is for live courses)
I am available during the courses and after, (there is an ongoing private FB group for alumni) if you need support, but you will need some in person support as well especially for courses dealing with childhood wounds.
Your emotional safety comes first and is of paramount importance to me. If you are unsure, please email me at firstname.lastname@example.com and we can discuss whether it is the right fit and a good time for you.
About Me:
I have a BA in English Literature and a MS in Elementary Education. I taught for 10 years in a middle school in the Bronx. Teaching I think has always been a part of me. I remember one of my favorite toys being a little school house and I was always gathering my dolls for a lesson.
After 10 years of teaching, I decided I truly needed to focus on my healing. It was like the past just kept catching up with me and I could no longer ignore the story within me. My childhood was so broken and painful, it was literally eating me away inside.
In 2005, I had the opportunity to stay home and write my memoir.
I have never looked back.
I came out about my abuse and told parts of my story on a website I created called, My Voice of Truth. 364 pages later I just knew this was going to be a big part of my work in the world but I needed to let go of certain things that were not allowing me to live fully.
I let go of my marriage and another not so healthy relationship. I went on my own for the first time in all of my life and started to get really clear about what I was here to do.
In 2009, I received my life coaching certification from ICA and have been coaching and facilitating women's groups in person and online ever since.
But my deepest personal transformation came from
my time at
Shalom Mountain
It is where I learned to truly hold space for others in the way that I do. I completed both the six month Process Training there as well as the four month Leadership training.
This is where I learned to be in loving community, to be seen and heard in my pain, to be a witness for others. I learned that my healing was mine and I was responsible for my own process. I learned more than I can ever write here, but the Mountain has been a huge influence on the healing work I do with women.
In 2010 I discovered art. Art was the missing piece of the healing process for me, a piece I never even knew was missing. Art is part of all of my courses in some way, even if it just optional, because it is such a powerful healing tool. I truly want everyone who works with me to have to experience the healing power of creative expression.
Since 2010, I have worked with hundreds of women in my courses and coaching programs doing deep soul work.
I feel very honored and blessed to do the work that I do.