text:
|Publication number
|Publication type
|Application number
|Publication date
|Feb 21, 1995
|Filing date
|Jun 12, 1991
|Priority date
|Jun 12, 1991
|Fee status
|Publication number
|Wilm E. Donath, Wing K. Luk, Donald T. Tang
|Original Assignee
|International Business Machines Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (6), Non-Patent Citations (20), Referenced by (39), Classifications (8), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
1. Technical Field
The present invention relates to the design and manufacture of integrated circuits, and more particularly to a method and apparatus for power minimization in a logic network.
2. Background Art
Power consumption and signal delay are crucial to the design of high-performance very-large scale integrated (VLSI) circuits. In this patent application, the terms "VLSI circuits," "VLSI chips, " "logic networks," and "integrated circuits" are used interchangeably. The size and complexity of integrated circuits are increasing every day, and it is becoming increasingly important to minimize power consumption while simultaneously meeting timing constraints. VLSI chips may contain hundreds of thousands of transistors. The timing delay and power consumption associated with the VLSI chip is directly proportional to the complexity of the VLSI chip.
Each VLSI chip is made up of one or more interconnected circuit elements. These interconnected circuit elements form various logic combinations that perform specified logic functions. Each logic combinations may be identified as a logic block of some predetermined definition. Each circuit element within the logic block has both a power and delay values assigned to it. Logic blocks are provided by the manufacturer with the capability of being able to select an appropriate power level to achieve a predetermined system timing parameter.
In general, every circuit and/or network has distinctive conditions that can not be exceeded relative to power and delay. For example, the power can be continually increased until the intrinsic delay of the circuits is reached or the total power limit for the network is exceeded. If the timing requirement is violated, circuit/timing delay can be reduced by powering up the VLSI circuits until the required arrival time (RAT) is met or until the above conditions are reached, at which time the RAT cannot be met by increasing the power. Consequently, the timing requirement may be achieved in general at the expense of power. However, it is neither necessary nor desirable to set the power level of the individual circuits to their highest power level. Therefore, the problem is one of minimizing the total power for a given combination of logic blocks consistent with the overall timing constraints of the logic network.
Analytical power/timing techniques have been described for optimizing logic circuit designs, such as described in a paper entitled "Analytical Power/Timing Optimization Technique for Digital System", presented at the Fourteenth Design Automation Conference on Jun. 20-22, 1977, by A. E. Ruehli, P. K. Wolff, Sr., and G. Goertzel of the IBM Thomas J. Watson Research Center. This paper describes a method for logic gate delay assignment which achieves power minimization of digital logic while satisfying system timing. However, the method requires simplistic assumptions of the power/delay model in order to perform the analysis. These simplifications seriously reduces the accuracy of both the power minimization and the satisfaction of the delay constraints and the convergence stability of the underlying algorithm, making the approach inappropriate for large scale, high performance circuit design.
Other prior approaches primarily handled the problem of power minimization on a logic block to logic block basis. Very few prior approaches, if any, have handled the problem on a global basis.
Thus, there is a need to minimize the power level in VLSI circuits, while still maintaining the overall system timing requirements. The present invention achieves this result through application of the method and apparatus described herein.
The present invention provides a new and improved method and apparatus for minimizing the total power of a logic network subject to timing constraints. The method of the present invention is applicable for use in connection with logic blocks wherein the combination of logic blocks make up a logic network. The logic blocks consist of either a circuit element (for example, transistor or a logic gate) or a set of circuit elements. Signals are propagated from sources of the network to sinks of the network, and the signals should arrive at their respective sinks within a specified required arrival time (RAT). The problem of power minimization with timing constraints is to assign power to each logic block in the network, such that the RAT requirement is met and the total power consumed by the network is minimized.
The present invention operates by: (1) determining if the required arrival time can be met; (2) assigning delay to each delay-segment so that the arrival time requirement at the sinks is met and every edge-segment is at the largest possible delay; (3) powering down the network such that the overall network delay is increased by DELTA and the total first order power decrease is maximized; (4) powering up the network such that the overall network delay is decreased by DELTA and the total first order power increase is minimized; (5) checking to see if the total power remains the same, and if so reducing DELTA accordingly; and repeating the above steps (3)-(5) until DELTA equals zero.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.
The present invention will be described with reference to the accompanying drawings, wherein:
FIG. 1 shows an environment for the present invention;
FIG. 2a shows in schematic form a first logic network;
FIG. 2b shows a directed delay-graph;
FIG. 3a shows a flow chart of a power minimization method of the present invention;
FIG. 3b shows a flow chart of a RAT check;
FIG. 3c shows a flow chart of initialization;
FIG. 4a shows a flow chart of a power down method of the present invention;
FIG. 4b shows a flow chart of a power up method of the present invention;
FIG. 5 shows a Power-Delay characteristic graph;
FIG. 6 shows in schematic form a second logic network.
FIG. 7a shows a flow chart of a power up method;
FIG. 7b shows a flow chart of a power down method; and
FIG. 8 shows a flow chart of the Delay-Power trade off procedure of the present invention.
I. Environment of the Present Invention
FIG. 1 illustrates an environment in which a preferred embodiment of the present invention operates. The preferred embodiment of the present invention includes an application program 102. The application program 102 represents power minimization software of the present invention.
The preferred embodiment of the present invention operates on a computer platform 104. The computer platform 104 includes certain hardware units 112 including one or more central processing unit (CPU) 116, a random access memory (RAM) 114, and an input/output interface 118. The computer platform 104 includes an operating system 108, and may include microinstruction code 110. A computer aided design automation system 103 and chip fabrication system 105. Various peripheral components may be connected to the computer platform 104, such as a terminal 126, a data storage device 130, and a printing device 134.
In a preferred embodiment of the present invention, the computer platform 104 is any International Business Machines (IBM) 3090 mainframe RS6000 workstation or the PS/2 personal system based on the Intel 80386 or 80486 microprocessor. The operating system is the IBM AIX operating system. The application program 102 is written in C programming language.
II. Description of the Underlying Technology and Theory Utilized by the Present Invention
Generally, a logic network includes a set of logic blocks. The logic blocks are made up of one or more circuit elements. Each logic block has a set of inputs and outputs. Typical logic blocks are transistors, AND-gates, OR-gates, inverters, multiplexers, registers, drivers, data-path and/or random logic macros. The logic blocks are interconnected from output to inputs to form the logic network.
The present invention is described with reference to FIG. 2a, which illustrates a representative logic network 200 having logic blocks labeled A 202a, B 202b,. . ., G 202g. Ai1 204a, Bi1 204b, Ci1 204c, Ci2 205c,...,Gi1 204g, Gi2 205g are inputs and Ao1 206a, Bo1 206b,..., Go1 206g are outputs of the logic blocks 202.
A delay-segment is an element whose power and delay can be adjusted. It can be either a circuit element or a set of circuit elements. External to the logic blocks 202, signals propagate from the outputs 206 to inputs 204 and 205 through external delay-segments, for example (Ao1 206a, Bi1 204b) and (Ao1 206a, Ci1 204c). In each logic block 202, signals also propagate internally through internal delay-segments. An internal delay-segment 216 (for example) in a logic block 202d goes from an input 205d to an output 206d that has logical dependency on the input 205d.
The internal and external delay-segments form a directed, acylic graph or delay graph. FIG. 2b shows an example of the delay graph 275 for the network shown in FIG. 2a. It should be pointed out that, without loss of generality, the delay graph is simplified (FIG. 2b) by excluding the delay-segments related to the REGISTER element 220. For purposes of explaining the directed graph 275 it is helpful to define source and sink nodes. The nodes 280 of the graph are inputs 204 and 205 or outputs 206 of the logic blocks 202, and the edges 290 through 299 are delay-segments (external or internal). The source nodes start from the primary inputs (for example the inputs 204a and 205c) of the logic network and register outputs, and the sink nodes end at the primary outputs of the logic network and register inputs (for example the outputs 206f and 206g). The directed graph 275 is also called a delay graph 275 of the logic network 200.
At each node 280 of the delay graph 275, an arrival time is assigned or allocated by a chip designer. The arrival time measures the time required for signals to travel from the left-most outputs to the right most inputs. Each edge 290 of the delay graph 275 is assigned a delay, which is the time to propagate a signal through the corresponding delay-segment.
For external connections of the logic blocks 202, to the first order, the delay of a delay-segment depends on the length, capacitance, and resistance of the connection, and the input capacitance of the successor circuits. To the second order, the delay depends on the power of a driving circuit and affects the transition time of the signals to the successor circuits, and hence the delay of the successor circuits. For internal delay-segment in a logic block 202, to the first order, the delay is governed by the gate delay, device size and power consumption of the underlying circuits of the logic block 202. To the second order, the delay depends on the loading at the output and the signal transition time at the input of the delay-segment, the delay also affects the delay of the output connections. To account for the second order effect, the delay of a delay-segment is computed in conjunction with the delay of the predecessor and successor delay-segments. If the capacitance and resistance of inter-block connections are given, the delay of a logic block depends on both the predecessor and the successor blocks, and thus only the delay-segment internal to the logic block must be considered.
To the first order, the delay-segments are treated independently with each other in terms of delay. The delay and power of a logic block or an internal delay-segment are modelled by a convex, monotonic decreasing function. The delay of the logic network 200 decreases as more power is applied to the underlying circuits/devices of the logic blocks 202, or the area of the underlying circuits/devices of the logic blocks 202 is increased. Power and area of the circuits may be considered proportional to each other. If the circuit devices are scaled in only one direction, then power and length (or width) may be considered proportional to each other. So minimizing power of a network 200 is directly related to area minimization, hence improving density, wiring and performance of the overall system. In addition, there is also a minimum intrinsic delay in each circuit device which is independent of the power.
The following equation may be used to represent the area-power-delay characteristic, where A, A' and B are constants.
power=A/(delay-B) (1)
area=A'/(delay-B) (2)
These equations are a useful representation of the power-delay relationship. Any convex function of power and delay, discrete tables of power and delay with interpolation and other similar forms can also be used to determine the power-delay relationship. Based on the trade-off of power-delay, a procedure according to the present invention to minimize the total power of a logic network subject to timing constraints is described below.
Generally, a delay graph 275 may be represented by the relationship GD =(VD,ED), where VD is the set of nodes and ED is the set of edges. For each directed edge in the delay graph 275, the arrival time (at) at a successor node (nsucc) should be at least the sum of the arrival time at a predecessor node (npred) plus the delay of the delay-segment represented by the edge=(npred, nsucc). Equation 3 represents this relationship:
at (nsucc)≦at (npred)+delay (npred, nsucc), (npred, nsucc)ε E.sub.D (3)
The boundary condition for the delay graph 275 is set up as follows: For each source (register outputs, for example 212, or logic network inputs, for example 204aand 205c), the arrival time is equal to a source arrival time (SAT) of the network 200. The required arrival time (RAT) is a constraint on the logic network 200. Each logic block 202 in the logic network 200 is allocated a specific delay in order to satisfy the constraint (RAT).
at(n)=SAT(n), n ε SOURCE(G.sub.D) (4)
For each sink (register inputs, for example 208, or logic network outputs, for example 206f and 206g) the arrival time should be at most equal to the required arrival time (RAT) of the logic network 200.
at(n)≦RAT(n), n εSINK(G.sub.D) (5)
The above |ED |+|SOURCE|+|SINK| equations specify the timing requirements of the logic network 200.
The power optimization objective is given by Equation 6:
minΣ.sub.e power(e)=Σ.sub.e power(delay(e)),eεE.sub.D(6)
This is an optimization problem with a non-linear objective function and linear constraints.
III. Description of the Method of the Present Invention
FIG. 3a shows an overall logic flowchart 300 which describes, in general terms, the operation of a power minimization procedure of the present invention. This procedure 300 is embodied in the application program 102 and the computer aided design automation system 103. In general, the procedure 300 shown in FIG. 3a accepts data representing the current delay of the logic network 200 and the current power level of the logic network 200. The delay and power can be considered to be independent and dependent resources, respectively. The circuit elements in the logic network 200 consumes the independent resources and the dependent resource in an amount which is a nonlinear function of the amount of the independent resource consumed by the circuit elements. The procedure 300 then generates more efficient power delay operating points for the logic blocks in the logic network 200 in which the overall power of the network 200 is minimized, while still satisfying the established timing constraints.
In FIG. 3a, the procedure 300 begins with a start command 302, followed by two separate and distinct initialization steps 304 and 306. The first step 304 is the required arrival time (RAT) check.
FIG. 3b is a detailed flowchart 325 representing the operation of block 304 of FIG. 3a. The flowchart 325 outlines the operation of the RAT check 304. The RAT check 304 establishes whether the designer specified RAT can be satisfied.
In step 332, the designer of the network provides an ideal and/or preferred RAT or constraint for the logic network 200 as a whole, as well as for the individual sinks.
In step 334, every edge-segment is set to the smallest possible delay.
In step 338, a timing analysis is performed to determine whether this ideal or preferred RAT can be met.
In step 340, if the given RAT cannot be met, then in step 342 the RAT has to be modified in order to satisfy the timing requirement. The RAT check 325 is applied to the entire circuit as a whole, and only after it is determined in step 340 that the given RAT cannot be met is there, in step 342, a change to individual sinks in the logic network 200. Specifically, in step 342, the RAT is increased for the sinks that fail to meet their given unique RAT. The RAT is increased, for example, by an amount that is equal to the difference between the actual arrival time after administering the above check and the required arrival time. Any standard timing analysis procedure known to one skilled in the art of integrated chip design could be used with the present invention.
FIG. 3c is a detailed flowchart 350 representing the second initialization step shown in block 306. Step 360 entails allocating the independent resource among the resource consuming elements of the logic network 200, or in other words, assigning a delay to each delay-segment. Each delay-segment is assigned, for example, a delay so that the arrival time requirement at the sinks is met, for example at(n)≦RAT(n), n εSINK and Σe delay(e) is maximized. Initially, however, this amounts to setting every edge-segment to the largest possible delay possible, while still satisfying the RAT. If the delay for the delay-segments is unknown in step 360, then: at(nsucc)≧at(npred)+delay(e) , e=(npred, nsucc)εED ; at(n)=SAT(n) , nεSOURCE(GD); at(n)≦RAT(n), nεSINK(GD); and max Σe delay(e). If, however, the initial delay is given for each delay-segment, then change delay of some of the edges to just satisfy the RAT. Thus: at(nsucc)≧at(npred)+delay(e)+Δdelay(e), e=(npred, nsucc)εED ; at(n)=SAT(n), ΔnεSOURCE(GD); at(n)≦RAT(n), nεSINK(GD); and max Σe Δdelay(e).
In step 370, the value of DELTA is set. DELTA can be set at any value, but for illustration DELTA might be set at: DELTA=1/2 maxiεSOURCE, JεSINK (RAT(j)-SAT(i)).
From block 306, the procedure 300 proceeds to a further block 308, in which a procedure 450 of powering down the overall network is performed. The powering down procedure 308 is such that the overall network delay is increased by DELTA and the total first order power decrease Σe (dP/dD)D=d0(e) Δdelay(e), e.εED is maximized. (dP/dD)D=d0 (e) is the derivative at D=dO for delay-segment e on its power-delay characteristic, and Δdelay(e) is the delay increase from D=d0 for e. The power down procedure 450 is detailed below in conjunction with FIG. 4b. Procedure 308 can also viewed as perturbing the constraint (RAT) by an specified amount, for example DELTA. Thus, perturbing the amount of the independent resource in at least one of the resource consuming elements, such that the dependent resource is changed (improved) by a value Pdown =ΣeεEp Pe (d(e))-Pe (do (e))]≦0 where Ep is a set of perturbed resource consuming elements with delay increased, and d(e)≧do (e) .
The procedure 300 flows from block 308 to block 310, in which a procedure 400 for powering up the network is performed. The objective of the power up procedure 310 is the exact antithesis of the power down procedure 308. Accordingly, the overall network delay is decreased by DELTA, while the total first order power increase Σe (dP/dD)D=d0(e) Δdelay(e), e εED is minimized. (dP/dD)D=d0(e) is the derivative at D equal to dO for delay-segment e on its power-delay characteristic, and Δdelay(e) is the delay decrease from D equal to dO for e. The power up procedure 310 is detailed below in conjunction with FIG. 4a. Procedure 310 can also viewed as perturbing the constraint (RAT) by a specific amount. Similar to the power down procedure this amount could be, for example, equal to DELTA. Thus, perturbing the amount of the independent resource in at least one of the resource consuming elements, such that the dependent resource is changed (worsened) by a value Pup =Σe εEp [Pe (d(e))-Pe (do (e))]≧O when Ep is a set of perturbed resource consuming elements with delay decreased and d(e)≦do (e).
Part of the power down 308 and power up 310 procedures described above is defining an object variable equal to the dependent resource consumed by the logic network 200. In other words, the total power of the logic network, before the power down 308 and power up 310 procedure is administered, is saved. The power down procedure's 308 goal is to essentially improve the value of the object variable by an amount Pdown ; while the power up procedure's 310 goal is to worsen the value of the object variable by an amount Pup less than |Pdown |.
Thus, as seen in block 312, the total power of the logic network is measured. If the total power remains the same, DELTA is reduced. An example of such a reduction might be to reduce DELTA to DELTA/2. However, if the total power is not the same then the procedure 300 does not reduce DELTA, but traverses 313 to block 316.
The procedure flows to block 316, where it is determined whether DELTA has reached zero. In an alternative embodiment, the procedure determines whether DELTA has reached or is below some lower limit. If DELTA equals 0 then the procedure flows to 318; however, if DELTA does not equal 0 the procedure flows back 322 to block 308, and the procedure continues as described above. It will become apparent from the examples described in Section VII herein, that DELTA will always reach zero, and thus the procedure 300 will always end.
The procedure 300 iteratively traverses blocks 308 and 310, reducing the power while meeting the overall timing requirement.
Finally, the procedure flows to block 318. Once the procedure 300 has determined what the optimum power and delay values are for the logic network, each delay-segment of the network is assigned a power and delay value such that the total power is minimized and overall timing requirement is met. This step is an essential part of the chip manufacturing process. Once step 318 is finished the procedure 300 stops 320.
The order of blocks 308 and 310 is interchangeable. Consequently, the procedure works equally well regardless of which procedure - the power down 308 or power up 310 is executed first. FIG. 3a has the power down 308 sequence first only for illustrative purposes.
IV. The Power-Delay Trade-off
Given the logic network 200 of circuit connections as shown in FIG. 2a, the arrival time at each sink of the network can be reduced by increasing the power of a subset of circuits. The power up 310 and power down 308 procedure provide, respectively, a method to increase/decrease the power of a subset of circuits in the network 200 in a way to reduce/increase the arrival time at each of the network outputs by a specific amount. By considering the delay-power characteristic of the circuits the arrival time can be reduced in the direction of smallest total power increase. A typical scenario is: given a chip design that exceeds a target cycle time requirement, the procedure 310 can be applied to speed up a subset of the circuits in a way to meet the overall target cycle time.
A. Underlying theory for the Power Up Procedure
Generally, given a chip design where the timing of the network is off at each sink in SINK(GD) by an amount denoted by DELTA(n), nεSINK(GD), the designer/manufacturer may select a subset of the logic blocks or delay-segments and power them up to reduce the delay of the blocks, and subsequently reduce the network delay by the amount given by DELTA(SINK), hence meeting the timing requirement.
Let Δat be the decrease in arrival time, Δdelay be the decrease in delay in the delay-segments; the set of timing specifications that is required to reduce the network delay by at least DELTA(SINK) is given by:
Δat(nsucc)≦Δat(npred)+Δdelay(npred,nsucc), (npred, nsucc)εE.sub.D (7)
Δat(n)=0, n ε SOURCE(G.sub.D) (8)
Δat(n)≧DELTA (n) , nεSINK(G.sub.D) (9)
It should be pointed out that Δdelay equals zero for external connections in this formulation.
The subset of the delay-segments selected for powering up (or reducing delay) is the set that minimizes the total first order power increase. As shown in FIG. 5, the first order power increase ΔP of a delay-segment is the derivative dP/dD at the delay operating point D equal to dO in the power-delay characteristic times the decrease in delay ΔD, as shown in Equation 10.
ΔP=(dP/dD).sub.D=d0 ΔD (10)
The objective of powering up the network to meet the timing requirement is:
minΣ(dP/dD).sub.D=d0(e) Δdelay(e), e εE.sub.D(11)
The solution of Equation 11 gives the increase in power (or decrease in delay) for each delay-segment. The optimization problem can be solved using standard linear programming techniques, such as the simplex algorithm or the interior point techniques or heuristic to take advantage of the special matrix and network structure of this problem.
The present invention, however, contemplates the use of any form of presently known or future developed optimization technique used in combination with the disclosed invention.
B. The Power Up Procedure
FIG. 4a is a detailed flowchart 400 illustrating the operation of block 310 of FIG. 3a which outlines the operation of the procedure for powering up the network. In FIG. 4a, data arrives at block 406, in which the power, delay, and dP/dD are all calculated. These values are all calculated at the delay operating point D equal to d0 for each edge in the delay graph GD.
Next, the procedure flows to block 408, in which a timing constraint is set up for each edge in GD. The timing constraint is represented by Equation (7). Block 410 sets up the boundary conditions, Equations (8) and (9) above, for the arrival time for each SOURCE node and the required arrival time for each SINK node. Finally, Block 412 determines what the increase in power ΔP and/or decrease in ΔD for each delay-segment in order to reduce the network delay by DELTA(SINK) such that the total first order power increase in minimized.
The above description of the power up sequence is an illustration of how the procedure 400 would be implemented if done in accord with the minimization of power procedure 300. However, it is possible to use the power up procedure independently of the minimization of power procedure 300. The power up procedure is shown is FIG. 7a. The procedure 700 is exactly the same as procedure 400, however Blocks 702 704, 706, 715 and 716 are added.
The procedure begins with a start command 702. Block 704 represents the step of performing a timing analysis on the network. The logic proceeds from block 704 to block 706, in which the amount of arrival time being exceeded at each individual sink is calculated. This value is represented by DELTA(SINK). From this point on, the procedure 700 is exactly the same as that described in connection with FIG. 4a. At block 715, the new values of power and delay are assigned to each edge-segment of the network.
C. Underlying Theory for the Power Down procedure
In the case of slowing down the network by DELTA(SINK) in order to lower the power, the above procedure 400 is applied with a slight modification. Let Δat be the increase in arrival time, Δdelay be the increase in delay in the delay-segments; the set of timing specifications that is required to slow down the network delay by at most DELTA(SINK) is given by:
Δat(nsucc)≧Δat(npred)+Δdelay (npred, nsucc);(12)
Δat(n)=0, n ε SOURCE(G.sub.D) (13)
Δat(n)≦DELTA(n), n ε SINK(G.sub.D) (14)
The subset of the delay-segments selected for powering down (or increasing delay) is the set that maximizes the total first order power decrease. The first order power decrease ΔP of a delay-segment, as shown in FIG. 5, is the derivative dP/dD at the delay operating point D=d0 in the power-delay characteristic times the increase in delay ΔD, as shown in Equation 15.
ΔP=(dP/dD).sub.D=d0 ΔD (15)
The objective of powering down the network to meet the timing requirement is:
maxΣ.sub.e (dP/dD).sub.D=d0 (e) Δdelay(e), eεE.sub.D(16)
Hence, for each delay-segment the total first order power is maximized.
As stated above for the power up procedure, the optimization problem can be solved using standard linear programming techniques, such as the simplex algorithm, the interior point techniques, or heuristic. The solution gives the decrease in power (or increase in delay) for each delay-segment.
D. The Power Down Procedure
FIG. 4b is a detailed flowchart 350 illustrating the operation of block 308 of FIG. 3a, which outlines the operation of the procedure for powering down the network.
The procedure for powering down the network is exactly the same as for powering up the network, described above in FIG. 4a and accompanying text, except for Blocks 458, 460, and 462. Block 458 sets up the timing constraint: Δat(nsucc)≧Δat(npred)+Δdelay(npred,nsucc) for each edge in the delay graph GD. Block 460 sets up the boundary conditions based on equations (13) and (14). Block 462 determines what the decrease in power ΔP and/or increase in delay ΔD is for each delay-segment in order to increase the network delay by DELTA(SINK) such that the total first order power decrease in maximized.
Analogous to the independent power up procedure 700, the power down procedure can be used independently from the minimization of power procedure 300. The independent power down procedure is shown in FIG. 7b. Once again, the only difference between the power down procedure 450 and the independent power down procedure 750 is blocks 752, 754, 756, 765 and 766. These blocks are exactly the same as that described above for the independent power up procedure 700.
V. Power optimization and Cut-Sets
The subsets used in the power up and power down procedures, respectively, are typically different subsets. This characteristic is what allows the above described procedure 300 to ultimately decrease and minimize the power used on the overall logic network. The subsets used in the power up 308 and power down 310 procedures described above are ascertained as set forth below. The present invention contemplates the use of any form of presently known or future developed technique for determining the subsets used in combination with the disclosed invention.
Generally, from the inputs to the outputs of a logic network there are a plurality of different paths. Each path contains a collection of different circuits elements. Among all the different paths, the largest path delay determines the total delay of the logic network. The path delay for each unique path is the sum of the delay in each delay-segment present in that path.
A cut-set is a set of circuits that cuts every path once. The power-optimization procedure uses two types of cut-sets: (1) an L set and (2) an M set. The L and M sets are a more general means of performing the power minimization procedure described above. The L set is the set of circuits or set of delay-segments that are powered up and the M set is the set of circuits that are powered down. The L set cuts each path in the logic network at least once, while the M set cuts each path in the logic network at most once.
For illustration purposes consider the power down procedure 450. Powering down is equivalent to allowing the delay to increase. Since one of the objectives of the present invention is to meet the given RAT, the network can not afford to increase every critical path more than once. Delay will inherently increase when powering down the network. Hence, there is no need to increase delay in every particular circuit more than once. On the other hand, when you power up you do not mind if some paths have to be reduced in terms of delay more than once. Lc is a L-cut set that minimizes Σe (∂P/∂D)(e)ΔDe =πL ≧0; Mc is a M-cut set that maximizes Σe (∂P/∂D)(e)ΔDe =πM ≧0; and ΔP=πL+ πM.
The basic concept is that during the power up and power down procedures described above there is a trade-off of one set of subsets for another, such that the delay remains the same while the total power is minimized.
A linear programming technique is implemented to ascertain the L and M sets. The above procedure works well when the logic network is relatively small. However, when the network becomes larger (for example, approximately 10,000 delay segments), compute times increase. Therefore, heuristic or other developed algorithms are the preferred method of isolating the subsets for larger networks.
VI. Delay-Power Trade-off of an Entire Logic Network
Finally, there can be one last step as shown in FIG. 8. At times there might exist a network that can benefit dramatically by an increase/decrease in the RAT at a savings/increase in power. The step 810 includes increasing/decreasing the RAT and repeating the minimization procedure 300 shown in FIG. 3 for this new RAT. This brings the present invention full circle by checking to see if an increase/decrease in delay will produce a significant savings/minimal increase in power for the entire logic network. This has the effect of trading off delay for power, as opposed to the above procedure 300 that basically trades off power for delay.
As a result, one can obtain a faster network (smaller RAT) with the smallest increase in power, or a slower network (larger RAT) with a largest decrease in power.
VII. Two Illustrations of the Present Invention
Table 1 shows the results of performing the above described iterations of power up and power down on the logic network shown in FIG. 6. These iterations produce successively smaller power levels. The first column (Delta arrTime) shows that the initial value of DELTA is set at 190. Increasing the delay is analogous to power down and decreasing the delay is analogous to power up. Consequently, a plus (+) sign in front of the DELTA value signifies the power down operation and a minus (-) sign signifies the power up operation.
TABLE 1______________________________________Delta totalarrTime a1 . . . a8 b1 . . . b4 c1 . . . c2 power RAT______________________________________ 100 100 100 155704 380+190 290 100 100 95384 570-190 100 100 100 155704 380+95 195 100 100 110056 475-95 100 100 100 155704 380+47 147 100 100 125028 427-47 147 100 53 149496 380+23 147 100 76 133288 403-23 124 100 76 145064 380+11 135 100 76 138896 391-11 135 100 65 144956 380 +5 135 95 75 141974 385 -5 135 95 70 144538 380 +2 133 95 72 143424 382 -2 133 97 72 144498 380 +1 133 97 71 143952 381 -1 133 96 71 144484 380 (-7.77%)______________________________________
Columns 2,3, and 4 (a,b, and c) shows the delay in each individual logic block 602a through 602g. Column 5 (power) shows the total power in the network. The total power goes up and down depending upon whether the procedure is in the power up or power down mode. The delay in each external inter-logic block connection is 20.
Column 6 (RAT) shows the required arrival time at each iteration step. In this example the overall RAT is set to 380. During the power down mode, the overall network delay is increased by DELTA. A typical starting DELTA is the RAT divided in half. Consequently, as shown in the first power down sequence of TABLE 1, DELTA is set at 190 and the overall network delay is increased to 570 (380+190), and the total first order power decrease is maximized. It should be noted, however, that any value that is less then the given RAT could be used for the starting DELTA. The total first order power drops from 155704 to 95384.
The procedure continues by decreasing the overall network delay by DELTA (190) during the first power up sequence, resulting in the minimization of any increase in the total first order power. This procedure is continued until DELTA is equal to zero, at which time the total power is minimized and the overall timing requirement is met. In this case the total power has been decreased by 7.77% and the RAT of 380 was met.
It should also be noted that the procedure shown in FIG. 3 calls for determining if the power level remains the same 312. In the example shown in TABLE 1, it appears that the power level never remained the same within a given DELTA. However, the iteration where the power remained the same was removed from the table for the sake of brevity (thus, the power up and power down iteration with DELTA equal to �190 was repeated and the power remained the same).
The example shown in TABLE 1 indicates the results after completing the procedure at one particular starting point (delay=(100, 100, 100)). The decrease in power was 7.77%. The final delay, as shown in TABLE 1, is (133, 96, 71).
The percentage decrease in power that might be realized is dependent upon the starting point. However, the final power level will be relatively consistent regardless of the starting point. It is possible to start with a very poor design which might initially result in the total power being very high. For example, if the starting point was initially set at delay=(278, 11, 11), for each logic block (a,b,c) in FIG. 6., respectively. The total power improvement would be from 6029998 to 144480, a savings of 4073%. However, the final total power remains almost the same or to within a negligible round-off error. The exact optimal solution for the simple network in FIG. 6 can be shown, by mathematical computation, to be (132.3, 96.5, 71.2). For more complex circuits, however, the optimum solution can not be calculate by hand, and thus the need for the present invention.
TABLE 2 demonstrates the use of subsets (cut-sets) through an example of performing both the power up and power down sequence once. The logic blocks represented in TABLE 2 refer to those shown in FIG. 2a and delay graph shown in FIG. 2b.
The upper portion of Table 2 shows the power down sequence with the M-set of delay-segments marked with an X. Only this set of delay-segments is powered down, and thus the delay in each individual delay-segments in the set is increased.
DELTA is set to 10. The table shows the delay D before the power down sequence, as well as the delay D' after the power down sequence. As the table indicates the power was lowered from 366081 to 330282, while the M-set of delay-segments each increased in delay by 10.
The bottom portion of Table 2 shows the power up sequence with the L-set of delay-segments marked with an X. Once again, only this group of delay-segments are powered up. It should be noted, that this set is different from the M-set used in the power down procedure. However, in general, the L-set and M-set may have common elements. Table 2 indicates that the power was increased from 330282 to 348060, while the selected delay-segments each decreased their respective delay by 10.
TABLE 2__________________________________________________________________________ArrTime: Ai1, Bi2 = 0, RAT: Fo1, Go1 = 300, WireDelay = 20, power =10.sup.6 /(delay-10) a b c1 c2 d1 d2 e1 e2 f g1 g2 power__________________________________________________________________________Powering Down (DELTA = +10)delay 40 50 50 110 30 30 80 30 30 30 130 366081dP/dD 1111 625 625 100 2500 2500 204 2500 2500 2500 69M-cut x x x xDelay D; 40 50 50 110 40 40 90 30 30 30 140 330282Powering Up (DELTA = -10)delay D 40 50 50 110 40 40 90 30 30 30 140 330282dP/dD 1111 625 625 100 1111 1111 156 2500 2500 2500 59L-cut x x xdelay D' 40 40 40 100 40 40 90 30 30 30 140 348060__________________________________________________________________________
This one sequence of power up and power down demonstrates how the total power is reduced (366081 to 348060) while the timing delay of the entire network remains the same as when the above procedure started.
The above sequence would be performed a plurality of times. The iterations would continue until there was no further reduction in power, at which time DELTA would be decreased and the above procedure would start all over again.
TABLE 3______________________________________iteration delDelay delPower total Power______________________________________0 3660811 150 -790950 2634751 -150 15150 3660812 75 -395475 2765392 -75 21975 3660813 37 -195101 2942633 -37 27417 3660814 18 -94914 3147024 -18 21798 3668975 18 -127656 3147025 -18 21798 3668976 9 -63828 3299776 -9 12321 3459077 9 -45540 3143667 -9 14094 3322928 9 -24408 3150358 -9 12276 3322929 4 -10848 3231449 -4 7720 33229210 2 -5424 32732910 -2 4456 33208211 2 -5372 32703211 -2 4524 33197912 2 -5408 32703212 -2 4524 33197913 1 -2704 32939613 -1 2376 33194714 1 -2526 32939614 -1 2376 331846______________________________________
TABLE 4__________________________________________________________________________Power lmprovement: (-10.3%)Delaya b c1 c2 d1 d2 e1 e2 f g1 g2 power__________________________________________________________________________initial40 50 50 110 30 30 80 30 30 30 130 366081optimized31 39 40 91 40 39 91 31 39 39 149 331846__________________________________________________________________________Power Improvement: Random starting point (-1721%)Delaya b c1 c2 d1 d2 e1 e2 f g1 g2 power__________________________________________________________________________initial11 11 136 167 136 11 167 11 11 11 73 6044613optimized31 39 40 91 40 39 91 31 39 39 149 331846__________________________________________________________________________Power Improvement: Another starting point (-131%)Delaya b c1 c2 d1 d2 e1 e2 f g1 g2 power__________________________________________________________________________initial50 50 50 120 15 15 50 15 50 50 120 768310optimized31 39 40 91 40 39 91 31 39 39 149 331846__________________________________________________________________________
Table 3 shows another illustration of a complete run through the power minimization procedure 300 of the present invention on the logic network shown in FIG. 2a and delay graph in FIG. 2b . Column 1 indicates which iteration is being performed. Column 2 indicates the DELTA being used during that particular iteration. Column 3 shows that difference in power that particular iteration produced. Finally, Column 4 indicates the total power .for the logic network 200. As shown, the iterations 1 through 14 produce successively smaller power levels. As discussed earlier, sometimes the same DELTA is used more then once. For example, iterations 6, 7 and 8 all use DELTA equal to 9. Increasing the delay is analogous to powering down and decreasing the delay is analogous to powering up. The total decreasing power of the logic network can be seen in the last column.
TABLE 4 shows the results of the procedure with three separate and distinct starting points. Consequently, there are three different values for the power improvement in terms of percentage depending on which starting point was used (for example, for a randomly selected starting point, the improvement obtained is 1721%). However, the procedure 300 resulted in the final power of the logic network being the same regardless of the starting point.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
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|U.S. Classification
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|International Classification
|Cooperative Classification
|European Classification
|Jun 12, 1991
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:DONATH, WILM E.;LUK, WING K.;TANG, DONALD T.;REEL/FRAME:005747/0888;SIGNING DATES FROM 19910513 TO 19910524
|Jun 19, 1998
|Fee payment
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|Sep 10, 2002
|Maintenance fee reminder mailed
|Feb 21, 2003
|Lapse for failure to pay maintenance fees
|Apr 22, 2003
|Expired due to failure to pay maintenance fee
Effective date: 20030221


text: Seller: easyboo (414) 100%, Location: WEST YORKS, Ships to: Worldwide, Item: 381154801693 STUNNING Antique Stained Glass Window MACKINTOSH ROSE This beautiful old window has outlived the original frame . It has been rehoused in a new pine frame The colours IN THE ROSE ARE SIMPLY DIVINE BEAUTIFUL MACKINTOSH ROSES ARE BECOMING VERY DIFFICULT TO FIND - THIS IS A REAL BEAUTY It was removed from a house in LONDON during refurbishment. The glass has no chips or scratches. The leading is in excellent condition. The frame measures 21 1/4 "W x 17 1/2 "h The glass measures 18 1/2 x 14 3/4" Shipping and packing for ALL WORLDWIDE LOCATIONS IS FREE INC INSURANCE I accept most credit cards via Paypal I welcome And Respond To All Ebay Best Offers Condition: In the very best condition, Type: Stained Glass Windows, Primary Material: Glass, Age: 1900-1940, Original/Reproduction: Original

subset: commoncrawl


text:
Dear colleagues and friends,
Registration for the 30th congress of the French Society of Aesthetic and Plastic Surgery is now open. As a reminder, the event will take place on June 1, 2 & 3 in Marseilles at the exquisite Palais du Pharo.
As announced, this year's event will be held under the auspices of openness: openness to new techniques that are increasingly sophisticated and performing in our line of activity, and openness to other fellow countries in particular European and Mediterranean ones.
Marseilles was the European Capital of Culture in 2013. Not only will it be the European Capital of Sport in 2017 but definitely too the Capital of Aesthetics.
Our Faculty members have carefully set up a top class agenda for this unprecedented event that undoubtedly will keep you riveted to your seat!
15 sessions organised as round tables will foster talks and interaction for us to find inspiration and both practical and innovative solutions. For a greater comfort, all sessions will be held in one single plenary room.
Thursday, June 1st will be dedicated to the ISAPS meeting (International Society of Aesthetic Plastic Surgery). Contributions will be given in English and simultaneous translation services will be provided. A breast surgery session will give us the opportunity to compare different surgical procedures between male and female surgeons.
Friday, June 2nd will host a legal session: a fake complication case will be presented complete with legal and insurance expert contributions.
The "Breast" session on Saturday, June 3rd will bring up the issue of the inframammary fold: should we preserve its loadbearing capacity or not?
A parallel conference over a day and a half will be dedicated to our assistants: close to our patients, their role is crucial. Technical and regulatory aspects are major concerns to us but we must not forget the personal development of our staff, a key point in team performance and patient's relationship management.
As always, our Congress will credit attendees with DPC (the French continuing medical education) with compensation for free-lance surgeons.
The main topics of the 30th SOFCEP congress:
The combination of surgery and cosmetic medicine is increasingly ambitious and accurate. The association of radio frequencies, ultrasound, cryolipolysis, etc. offers highly interesting options without replacing surgical options.
Whether for the face or the body, the always increasing refinement of procedures offers outcomes enhancing a soft and natural aspect with long lasting effects and a much less traumatic postoperative course.
This is the objective of the French Aesthetic Touch, a surgery aiming at a natural, reliable and long-lasting outcome, now acknowledged as an international reference.
A long past history! And a promising future with stem cells and regenerative medicine to prevent or slow-down ageing with our own cells.
Entertainment has also carefully been organised: sports, music, good food and more will be on offer throughout the event between working sessions.
As part of our social programme, a private visit of MuCEM i.e. the Museum of European and Mediterranean Civilizations is also on the agenda.
The Chairman's gala dinner will take place on Friday June 2 at the 'Cercle des Officiers', a stone's throw from the Palais du Pharo.
The event will close on Saturday evening to give you the unique opportunity of staying over through Whit Monday and visit Marseilles and its surroundings whether alone or in company.
Looking forward to welcoming you very soon,
With kind regards,
Dr Richard Abs
SOFCEP President
More than a congress, SOFCEP is a learned society in an open environment.
The French Society of Plastic and Aesthetic Surgeons (SOFCEP) is a learned society created 30 years ago whose members are exclusively French plastic surgeons with a diploma in Plastic, Reconstructive and Aesthetic surgery, with a practice in aesthetic surgery as main activity. With a membership of 300 SOFCEP is a group of practitioners strongly represented within the International Society of Aesthetic and Plastic Surgeons (ISAPS) ranking fourth after USA, Brazil and Mexico.


text:
|Super Mario Bros.: Ate' Bit Adventures
| None is default!
| * Action Adventure
|Age Rating(s)
|* TV-PG (Mild coarse language, blood pictures)
|Opening Theme
|"Hotel Mario 8-Bit"
|Country of Origin
| * Canada
|Original Language
| Official Languages
Constructed Languages
|40 Minutes
The 8-Bit version uses NES-style graphics and sound effects, but it also makes use of low quality radio voice acting to complement the NES theme, much like Konami's Blade of Steel, S.C.A.T. and High Speed.
The Name is a pun on the term, "8-bit" albeit being Mario's traditional start and perhaps based on the fact he likes Spaghetti.
The LEGO version uses the same idea as the Modern CGI except built entirely of Lego blocks and Legofied versions of Nintendo, SuperMarioLogan and DiC characters alike
- Note: You can't/shouldn't decide which one of those five versions of the TV Show is default.
The Mushroom Kingdom is having a funtime yet again, but Bowser keeps attempting like usual, but this time fatigued from kidnapping several Princesses including Peach, he had hired an innocent Human Chef named Pee Pee and force him to make Food Rations for his Koopa Troops.
Jackie Chu goes to the Mushroom Kingdom from the Dragon Federation and teaches his martial-arts and math to various citizens, creating units of Kung Fu Toads, the mere opposite of Ninji units from Wart's Nazi-esque Subcon Faction. Prince Hugo returns with more huge stuff happening, with his military and police faction growing stronger with over-sized primitive tech armor, cutlasses, spears, and firearms.
Toad is now braver and able to use an Axe, like seen used on the decoys of Bowser, he also knows how to rap like Black Yoshi. Stanley the Bugman meets the Mario Bros. as they all had the same gorilla problem and to expand their crew inorder to outclass Bowser and his more desperate son and friends, Joseph and Cody. Oogtar and his primitve human tribes, return with the Clan of Yoshis aiding them with meat, hired employees and higher technology/equipment.
The Wario Bros. have also formed a mob of criminals with Black Yoshi being the wildcard contributor, they are all hunted down by Officer Goodman and the Block City Police Department.
Nintendo Characters
- Mario/Maria
- Dr. Mario
- Luigi
- Mr. L
- Toad (now raps and uses an Axe)
- Toadette
- Stanley the Bugman
- Princess Peach
- Princess Daisy
- Rosalina
- Wario
- Waluigi
- Random Yoshi
- Red Yoshi
- Yellow Yoshi
- Blue Yoshi
- Pink Yoshi
- Light Blue Yoshi
- Brown Yoshi
- White Yoshi
- Orange Yoshi
- Magenta Yoshi
- Green Yoshi (leader of the yoshis)
- Bowser
- Dark Bowser
- Dry Bowser
- Bowser Jr.
- Toadsworth
- Koopalings
- Larry Koopa
- Morton Koopa Jr.
- Wendy O. Koopa
- Iggy Koopa
- Roy Koopa
- Lemmy Koopa
- Ludwig Von Koopa
- Plessie
- Mouser
- Birdo
- Robirdo
- Wart
- Dry Wart
- King Boo
- Kamek
SuperMarioLogan/Thirtyacrean Characters
- Jackie Chu
- Kung Pow
- Officer Goodman
- Cody the Magiwarlockoopa
- Ken
- Joseph Tuman (Turtle-Human hybrid)
- Craig the Devil
- Chef Pee Pee
- Black Yoshi (with gun and golden necklace)
- Loan Dolphin
- Mine! Bird
DiC Characters
- Prince Hugo
- King Mackarel
- Holly Mackarel
- Oogtar
- Pronto (Western toad with revolvers)
- Scooter
- Stool Pigeon
- Cheepy
- Hooded Robin
- Salvador Drainado
Special Characters
- Purple Yoshi (a Samurai yoshi)
- Teal Yoshi (Knight Yoshi wearing Yoshi armor)
- Dry Harold (Mario's Maternal Grandfather)
- Walgina (Waluigi's Girlfriend and Richalvarez' character)
- Mushroom Kingdom
- Toadsville Fire Department
- Mushroom City Royal Police
- Mushrapier Toads
- Fire Flower Corps
- Koopa Kingdom
- Subcon Regime
- Sniffet Corps
- Liberty of America
- Liberty Marine Corps
- Block City Police Department
- Brooklyn
- Brooklyn Plumber's Academy
- Giant Land
- Giant Royal Guards
- Yoshi's Island
- Dome City Tribes
- Mertropolis
- Mertropolis Royal Marines
- Waki-Waki
- Super Mushroom
- 1-Up Mushroom
- Fire Flower
- Poison Mushroom
- Ice Flower
- Starman
- Mushrapier
- Yoshi Egg
- Yoshi Armor (Steel, Gold, Cobalt)
- Dragon Coin
- Wearable Shell
- Wearable Spiked Shell
- 3-Up Moon
- Boomerang Flower (Steel, Gold, Cobalt)
- Dragon Suit
- Ninja Belt
- Crescent Wrench Suit (Steel, Gold, Cobalt)
- Hammer Suit (Steel, Gold, Cobalt)
- Laser Bros. Gun
- Golden Mushroom
- Diamond Mushroom
- Concrete Flower
- Tornado Flower
- Mushketoom
- Purple Coin
- Coin
- Frog Suit
- Salamander Suit
- Snake Suit
- Axe Suit (Steel, Gold, Cobalt)


text:
Cole carries Pirates past NationalsJul 24, 2013 - 4:44 AM Washington, DC (Sports Network) - Standing on first base in the second inning, Gerrit Cole used his right hand to fist bump his first base coach and exchanged a few words behind his black batting glove if only to break up long, emotionless stares with the dirt surrounding the bag.
Cole saved his best work, and excitement, for the mound, where he shut down the Washington Nationals and led the Pirates to a 5-1 win in the second of a four-game series.
The 22-year-old rookie gave up one run on two hits in seven innings to snap a three-start losing streak. Cole (5-3) struck out four and walked one in addition to two hits and an RBI at the plate.
Pedro Alvarez slammed his 25th home run for the Pirates, who have won three in a row and remain 1 1/2 games behind NL Central-leading St. Louis.
"We don't live and die by it, we go out there to win every game," Cole said of the standings. "I think we're really good about it, but we watch the scoreboard to see if we can pick up a game here or there."
Taylor Jordan (0-3) took the loss after giving up five runs -- four earned -- on nine hits and a walk over 7 2/3 innings.
"I really wanted to win today because we needed it," Jordan said. "I'd love to celebrate one time."
Wilson Ramos' home run was the only run for Washington, which has lost five in a row.
The Pirates put up three runs to take the lead in the second. Alvarez and Russell Martin singled before Garrett Jones worked a walk to load the bases with no outs. Neil Walker grounded into a fielder's choice to score the game's first run.
Jordy Mercer followed with a hard chopper that Ryan Zimmerman picked at third base. Zimmerman threw to second to start a double play, but second baseman Anthony Rendon dropped the throw, allowing Martin to score and failing to record an out.
Cole showed bunt, but pulled back and grounded a base hit into left field to score Walker and cap the three-run rally.
Ramos lifted his fifth home run to center field in the third inning, just out of the reach of a leaping Andrew McCutchen.
Cole made the lead stand, however. When Mercer made a diving stop that led to the second out of the seventh inning, Cole didn't hide his excitement. With a glove slap and a smile peering through his thick brown beard, Cole's reaction punctuated his outing.
Alvarez gave the Pirates' bullpen some extra run support when he lined a solo home run to left field in the eighth. Martin followed with a single, stole second and scored on Gaby Sanchez's pinch-hit double to push the score to 5-1.
Bryan Morris tossed a scoreless eighth before Mark Melancon took over in the ninth. Melancon, who is taking over the closer role with All-Star closer Jason Grilli on the disabled list with a strained right forearm, tossed a perfect ninth.
Game Notes
Prior to the game, the Pirates activated Walker from the 15-day disabled list and recalled pitcher Vic Black. The club also placed Grilli on the 15-day disabled list and designated infielder Brandon Inge for assignment ... Pittsburgh has won 10 of its last 14 on the road ... The Nationals are 6-8 against rookie starting pitchers this season ... Washington is 2-10 in its last 12 games.
Jul 23 9:48 PM
- Pinch-Hitter Gaby Sanchez double to right center scored Russell Martin with two out. Runner on second and Neil Walker due up.
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Andrew Coombs blasts Newport Gwent Dragons for cancelling medical insurance
Former Wales lock Andrew Coombs has branded Newport Gwent Dragons a "total embarrassment" in a dispute over the termination of an insurance policy.
Coombs suffered a serious knee injury in April 2015 and was forced to retire 14 months later.
Now the 32-year-old insists he feels "disgusted and devastated" at the cancellation of his medical insurance, claiming he has now been left with thousands of pounds in unpaid bills.
Dragons chief executive Stuart Davies insisted in a statement, however, that Coombs received "financial support over and above our contractual obligations".
In a statement posted on Twitter, Coombs said: "Absolutely disgusted and devastated to discover that the Newport Gwent Dragons have cancelled my private medical insurance policy.
"The policy was providing me with ongoing crucial medical treatment from the career-ending injury I sustained whilst playing for the region.
"This was done without the option of personally financing the policy following assurances from the region that this option would be available.
"I'm now left facing thousands of pounds of medical bills to receive essential care not available on the NHS in an attempt to improve my severely impaired knee."
Allied to the statement, Coombs also tweeted: "Player welfare and duty of care to players @dragonsrugby is a total embarrassment. 10 years of loyal service to RP (Rodney Parade), this is how they treat me."
Coombs won 10 caps for Wales between 2013 and 2015, enjoying stints with Pontypool and Newport, while representing the Dragons 80 times in seven years.
The Dragons issued a lengthy statement from CEO Davies on Wednesday afternoon in response to Coombs' claims.
"We were disappointed that Andrew Coombs feels aggrieved that he no longer has the benefit of medical insurance after the termination of his employment," said Davies.
"The private medical insurance policy to which Andrew refers was our group medical insurance policy taken out to cover the costs of medical treatment for players while they are employed at the region.
"Like most employers' medical insurance schemes, cover ordinarily ceases on termination of employment. In fact, Andrew remained covered at our expense for some months after his retirement.
"Andrew's cover under the policy came to an end as we moved towards self-funding the cost of treatment for players in our employment, due to the escalating costs of insurance.
"Consequently, we no longer have medical treatment insurance in place since the money spent on the policy would probably outweigh the cumulative costs of treatment. However, our players still receive the same high level of medical care, but this will be funded directly by the region going forward.
"No assurances were given to Andrew about a transfer of his medical insurance either prior to or after his retirement.
"However, I would point out that significant financial support over and above our contractual obligations was extended to Andrew before he left our employment, in deference to his standing within and long service at the region.
"Like all professional rugby organisations, we also fund the cost of premiums to provide financial support for players who suffer a career ending injury, to ensure our players are looked after financially in the immediate aftermath of retirement in such circumstances.
"In addition, we extended to Andrew at the time he retired, the offer of full and ongoing access to our medical staff and facilities in respect of his continued rehabilitation. This offer remains in place and we will continue to offer whatever support can reasonably be provided.
"We feel that we have acted both professionally and reasonably in our dealings with Andrew, in terms of providing him with every opportunity to return to the team before he retired, and in relation to our ongoing offer of support after his retirement."


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Credit Advice
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It should update when the CC company next updates your credit report.
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You cannot change it, give it a month or two to update. If it doesn't update after that time, contact the credit card company and kindly ask them to update it. Under NO circumstances should you attempt disputing the account over this as it may get the account deleted and that would hurt your credit.
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Anacostia Riverkeeper Submits Comments to PEPCO Remedial Investigation Report
Anacostia Riverkeeper would like to thank the Pepco Benning Road Community Advisory Group (CAG) as well all of the individuals who devoted many long hours to reviewing and assessing the Remedial Investigation Report in order to submit comments and address data gaps.
We have submitted these comments on behalf of the residents of the District of Columbia who are impacted by the issue of legacy pollution emanating from the Pepco Benning Road facility adjacent to the Anacostia River.
Below are comments submitted by Anacostia Riverkeeper including those developed in conjunction with the CAG.
· Significant data gaps identified throughout this report should have been identified and addressed sooner given how much time has been taken. DOEE and PEPCO have made many promises to the public of continuous evaluation and oversight, but we have only seen excuses and delays throughout this process, which are reflected by the outcomes of the Draft RI Report. We ask that PEPCO and DOEE be more forthcoming about their expectations for the completion of the RI/FS and that improvements and adjustments be made in order to stand by their commitments to the communities.
· The additional sampling that will be conducted should not automatically delay work needed for the treatability and feasibility studies. If these activities are carried out in sequence rather than parallel, it will take a lot more time to complete the RI/FS. The table below shows the significance of the delays thus far (delays in red). Whatever work can be done in parallel, should be done in parallel.
Originally Proposed RI/FS Timeline (From Consent Decree and RI/FS Work Plan)
Actual RI/FS Timeline
Approval of RI/FS Work Plan by DDOE
No estimate or deadline provided
December 28, 2012
Obtain Permits (NPS, USACE, DCRA/DDOE)
Within 30 days of RI/FS Work Plan approval
Final permit approved Sept 10, 2013 (Approval took more than 250 days)
Begin RI Field Work
Within 30 days of RI/FS Work Plan approval
January 25, 2013
Complete RI Field Work
Within 120 days of field work start date
December 31, 2014
PEPCO's Submission of Draft RI Report
Within 120 days after completion of RI field work
April 30, 2015
PEPCO's Submission of Draft FS Report
Within 180 days after completion of RI filed work or 120 days after approval of treatability study report, if required
Incomplete - Treatability Study (TS) is required and expected to take 6-9 months from approval of a TS work plan and issuance of permits. TS currently on hold, no date identified.
Completion of the RI/FS
Within 18-24 months of consent decree filing
DDOE Issuance of Record of Decision Regarding Cleanup Actions
Promptly after approval of RI/FS reports
DOEE estimates 2 years after RI/FS completion (from May 2015 status report to the court)
· Statements in the report such as the one below (see pages ES-2, 4-30, 4-36, 4-37) are not well understood. These assertions ignore the fact that PEPCO operated a combustion-based power plant for almost 100 years and operates a fleet of vehicles at its Benning Road property. The import or relevance of any asserted differences in the two classifications on PAHs mentioned should be explained and not left open-ended. Since more investigation and forensic analysis is being planned to better define PAH sources, what will be the determining factors to better understand contamination sources?
"This preliminary forensic analysis suggests that PAHs in site soils and stream sediments may be predominantly from combustion related sources (pyrogenic) rather than fuels (petrogenic), although as noted, this conclusion is based on a limited list of PAHs and a limited site-specific background dataset." (page 4-36)
· Given the long and relatively complex operational history at the property, has consideration been given to using a Tentatively Identified Compound (TIC) analysis in the follow-up work that has been proposed in the RI, to identify any additional compounds of potential interest? Limiting the number of COPIs too early in the process can result in a sampling and characterization program that is too restrictive (and reduced reporting) that can result in missed potential COCs.
· The report goes to some lengths to compare PCBs found on the landside with those found in the waterside, including forensic analyses to determine to what extent the landside PCBs likely contributed to the waterside PCBs. This preliminary forensic assessment exhibits some shortcomings that should be addressed in the next phase of work - including: the PCB comparison does not appear to consider the weathering of PCBs and the effect this has on the analysis; the PCB comparison appears to neglect the role of sediments that were removed from overflows/storm drains on PCB transport and contamination; the initial conclusion of the RI that the site is not a substantial contributor appears to contradict previous findings by EPA.
· Some of the sample results were ascribed to the collection of turbid samples. Further evaluation of these "outlier" results should be provided in the next phase of work since at least some of the COCs (e.g., PCBs) are known to be transported as or facilitated by colloids.
· We agree with statements in the report indicating that more exposure pathways need to be addressed (pages ES-4 and 7-8). In addition to the current/future construction worker, future industrial worker, and future recreational user scenarios, nearby residents (particularly those who dig on their properties) and in-stream workers (ie Groundwork Anacostia DC employees who regularly work in nearby wetlands and tributaries in the water and sediment) should be evaluated since their properties were likely contaminated when the power plant was in operation. Further, we recommend that anglers are examined according to subsistence fishing practices, not only recreational fishing. If risks to any of these groups will not be evaluated going forward, please explain why not.
· With regard to the potential exposure scenarios that are listed as being under consideration in the revised BHHRA: these appear to all be relatively short duration exposure scenarios, that would tend to lead to higher cleanup levels than longer-duration exposure scenarios. Given this, detailed attention must be paid to the assumptions that are incorporated into these scenarios.
· This report continues to state that there have been five historical releases of PCBs on the PEPCO Benning Rd property. For consistency and accuracy this number needs to be changed to "six" throughout the report (RI Report pages 1-3 and 1-6; Appendix Z page 2-1). There were six historical releases of PCBs. EPA has documented six and the July 2012 RI Work Plan was revised to reflect this and other changes and officially re-released in February 2013.
· Will all contaminants that exceed screening levels and that are determined to be a risk to human and or ecological health on the PEPCO Benning road property be remediated regardless of the source?
· If contaminants exceeding screening levels are ruled out as having migrated from the PEPCO Benning Rd property (i.e. contaminants are not from PEPCO's operations); how will the source(s) be further evaluated by DOEE to ensure remediation and how will DOEE and PEPCO work to ensure no further delay in remedial actions on PEPCO property? For instance, if a contaminant deemed to originate off-site is found in the immediate vicinity of a contaminant deemed to originate on-site, how will DOEE and PEPCO ensure that remedial action is taken as soon as possible for the on-site origin contaminant regardless of the off-site origin contaminant found in the same area of the site?
· We understand that further investigation is warranted on the waterside, but in the meantime will potential remediation options for the landside start to be evaluated much like what has been done to clean up PCB contamination surrounding the cooling tower basins? We suggest this be done as not to delay further.
· Bird species observations seem incomplete in this report because it missed the migratory species that use the river at other times of the year than November and December (page 3-10.) While winter can be a good time for sighting resident birds, there should have been observations throughout the year, especially given the nearly 2 year duration of field studies.
· It would have been helpful if the large tables for this report (e.g., Tables 4-1, 4-3, 4-5; Appendix R) were made available in Excel spreadsheets because it was difficult to navigate such large datasets in PDF form.
· Could the rationale for the screening levels used for this investigation be explained? For example, the use of mean values seems to gloss over potential problems with contamination hotspots (see pages 4-26 and 4-27, giving mean values for PCBs in sediments that are an order of magnitude lower than the peak values in particular samples). If any of the values used here differ from those proposed in the original Remedial Investigation Work Plan (July 2012), please also explain the rationale for changing those values. In addition, if a mean value is to be used, regulatory guidance in many settings proposes the use of an upper confidence limit (UCL) for the mean that accommodates the variability in the sample data and resulting uncertainty in the estimate of the true mean.
· What are the implications of contaminant groups (such as PCBs, PAHs, heavy metals, etc.) found together at sampling locations? For example, what does it tell us about the condition or need for remediation when PCBs and PAHs are found exceeding screening levels at the same location?
· With regard to the contaminant groups (see above): has or will consideration be given to the role that co-disposal / co-contamination can have on facilitated transport of some contaminants – for example, the transport of PCBs has been documented as facilitated at some sites by co-disposal with solvents.
· How are potential interactions and cumulative or additive effects going to be handled in the human and ecological risk assessments, given that contaminants overlap at different sample locations and given that many exposure pathways do not expose people or wildlife to just this dose of a single contaminant at a time?
· The transport and fate of chemicals of concern between media, across the site, and across the study area needs to be further explained. It is not clear that all modes of chemical transport have been identified; implications of extreme weather events and the potential for colloidal transport, for example, need to be better understood and explicated, and health impacts need to be revisited to account for resultant changes in assumptions.
· What will be done to further evaluate and address any sampling that resulted in false positives or negatives identified in the report? (pages 4-16, 4-17, 4-20)
· Background sample locations are too close to the contaminant plumes near the PEPCO Benning site. Given that the Anacostia River is a small tidal river subject to dispersal of suspended sediment and its associated toxics upstream and downstream from the source with the tides as well as upstream during storm surge events, and given the length of time during which the PEPCO Benning site contributed contaminants to the river, it is unreasonable to assume this report's background sites actually exclude contamination from this site. We recommend that the background sites used in the Anacostia River Sediment RI be used for this report as well. Given that DOEE is already using the data from the Potomac sites as background for the Anacostia River, including the stretch covered in this PEPCO specific RI, we see no reason why switching to the Anacostia River Sediment RI background sites should present significant difficulty. (See definition of "background" given on page 4-2)
o What are the "revised background conditions" for PCBs referenced on page 4-28 that will be assessed in conjunction with the additional field investigation?
· With regard again to background data: there is a concern that using data from within the Anacostia River which is known to be contaminated to define "site-specific background" conditions is only potentially of use in determining whether the Benning Road facility contributed significantly to an otherwise already impacted waterway. If the intent of the RI/FS process is to lead to actions that help to return the watershed to maximum beneficial uses then this impacted "site-specific background" condition should be supplemented by consideration of an "unimpacted" background condition – which in the case of anthropogenics such as PCBs, would be zero. Otherwise, in the limit, if every source equally contributed to contamination, and the "impacted background" is uniformly equal and elevated throughout the waterway, the inference would be that no-one has rendered an impact "above background" such that nothing need be done: the fact contamination is ubiquitous doesn't remove the obligation of contributors to minimize long-term impacts.
· The discussion of the PCB forensic analysis from page 4-37 through 4-47 seems to ignore the possibility that tidal flows could have distributed PCBs from the Benning Road site throughout the tidal portions of the Anacostia River, both upstream and downstream.
· There has been and continues to be an assumption that contamination has not migrated from the PEPCO Benning Rd property to nearby residential areas. What is it about the fence-line that protects or protected (when the plant was in operation) these communities from contaminants?
o We strongly recommend that the sampling be expanded to include neighborhoods immediately adjacent to the site since there is reason to expect that smokestack contaminants migrated to these neighborhoods at a minimum. Citing that this is not a requirement of the consent decree is not an acceptable response; PEPCO and DOEE should and have claimed to be committed to the residents of the District and therefore should go above and beyond minimum consent decree requirements if truly committed to community and environmental health.
o Where contaminants are found near the fence, the extent of the contamination needs to be investigated further and PEPCO needs to continue to follow the contamination regardless of where it is until the full extent of contamination is determined and acceptable levels are detected. For example, screening levels for total PCBs were exceeded at SUS18 (Figure 4-2, Table 4-1) which is near the border of a community area.
o The direction of the PCE plume (pages 4-50 and 4-51) suggests that migration of contaminants can occur in directions that are not westward as is the assumption for the modeling. This assumption of westward migration of contaminants towards the river may be erroneous based on the PCE contaminants found on the site which is north and west of the historical dry cleaner site (suspected source of pollution) and should be reexamined. This becomes especially important since most of the historically reported PCB spills occurred on the eastern section of the site near Kenilworth Parkside. If migration can occur in directions such as east then you would expect that PCB and other contaminants might be found in Kenilworth Parkside as that is closer to the spill sites than the river.
· Conclusions from the PEPCO Benning RI risk assessments seem to be inconsistent with what has been concluded for the Phase 1 Anacostia River Sediment RI risk assessments. These need to be addressed:
o Baseline Ecological Risk Assessment - PEPCO found "little to no potential for ecological risks to the wildlife community from ingestion of prey items containing PCBs" (PEPCO Benning RI at 6-3), but the Anacostia River Sediment RI found possible PCB risks to green heron and kingfishers in Reach 456 (which includes the PEPCO Benning study area) when NOAEL TRVs were used (Anacostia River RI at 139 and Table 10.14).
o Human Health Risk Assessment - PEPCO concluded that fish consumption presents a risk only for non-cancer effects (PEPCO Benning RI at 6-2), but the Anacostia River Sediment RI found total PCBs were a contaminant of concern for both fish ingestion cancer risks and fish ingestion non-cancer hazards for all reaches of the river (Anacostia River RI at 149).
· It is unacceptable that little effort has been made to post signs near the PEPCO Benning property warning people not to fish or consume fish caught in the area. We strongly urge DOEE to ensure that sufficient signage is posted up and down the entire river, especially locations frequented by people.
· The report states that "To some extent, the existing operational and institutional controls that are in place at the Site provide effective exposure prevention measures, and direct contact exposure pathways may be currently incomplete or insignificant." While this might be to some extent true for the time-being, incidental land-use controls for operational or occupied facilities do not constitute legally-binding institutional controls or covenants that are protective of human health and the environment. We are pleased therefore to see that the revised BHHRA will reflect some more realistic potential exposure scenarios.
· The general tone of this RI report seems much more like an opinion piece than a scientific report. PEPCO seems more interested in placing the responsibility on other potential sources rather than uncovering the facts and presenting date in an unbiased manner. For instance, PCE should not be described as a dry-cleaning agent unless it is also described as a solvent potentially used on-site. Either no assumptions should be encouraged, or all the potential scenarios should be explicated together.
· There is a substantial amount of work that PEPCO and DOEE are going to be engaged in to better understand contaminants found in order to finalize the Remedial Investigation report. We recommend that an additional comment period for RI Work Plan Addendum #3 or at the very least the report on findings following this additional work (second/revised draft RI report) be offered to the public. We realize that this may add more time to the schedule, but with so much new work and information to come it is important to give the public time to review and comment.
· The report states that "…this CSM will be updated in a separate stand-alone CSM Technical Memorandum." The public should have the opportunity to review and comment on this separate CSM Tech Memo. We note that this newly-proposed document was not previously listed as being provided to the public for review and comment: will it be made available for such a review, and if not, please explain the rational since the CSM is a critical component of the RI/FS process.
· We recommend that PEPCO reassess the way it presents figures and tables for public consideration in this report. At the very least, references to them should be hyperlinked so members of the community accessing the report electronically can have the referenced information immediately to hand. Requiring members of the community to flip between appendices and the main report as they review it in their leisure time puts an extra burden on them as they voluntarily educate themselves about the potential threats to their health and that of their community. PEPCO and DOEE, in their commitment to the community, should do everything in their power to make this report as accessible as possible to those residents who take it upon themselves to read and understand it. The best option would be to include pertinent figures in-line with the pertinent discussions. Many figures in the report combine contaminant name, level, and location in maps that cover much of the most relevant information from the tables. Where a table is still needed, a trimmed version in-line would greatly aid the accessibility of the document.


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Why predictions are pointless
There is very little evidence that we can make accurate decisions, and plenty that we can't. So why do we do it?
Wading through pages of legalese from my pension fund recently, I struggled to get any idea of likely income in my dotage. It all depends on assumptions about investment returns over the next 20 years, interest rates when I retire, and how long an actuary (who probably hasn't even done his or her maths A level yet) will think I am likely to live after I don pipe and slippers. The only honest answer to any of these questions is 'I don't know' – which all the legal waffle was trying desperately to conceal.
There is very little hard evidence that we can make accurate predictions, and plenty that we can't. Yale psychologist Philip Tetlock's epic 20-year study asked 284 experts in forecasting political and economic trends to make 28,000 such calls. He found that they were slightly less accurate than random guesswork.
Daniel Kahneman analysed data on 25 investment advisors over eight years and found no evidence they could predict anything at all.
Denial is a common human response to uncomfortable truths like this, and tends to make us take refuge in forecasting of baroque complexity and minimal validity. Like the Goldman Sachs model which assessed certain adverse events as having a '25 sigma' probability (meaning they might happen once in the life of the universe), only for several of them to happen in a week.
On a more mundane level, an obsession with prediction makes us prevaricate – will we need 22 or 23 people in year three? Are those recruitment costs realistic? – when we should simply be getting on with things now.
Life would be more fun, faster-moving and more profitable if we could stop worrying about predicting the future. Successful entrepreneurs know this – they tend to be very sceptical about their own or anyone else's claims to be able to say what's going to happen next. Managers need to grasp the nettle of unpredictability too.


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Welcome to The Nintendo Forum Site!
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Prove your worth with quick desire. Ice and Earth. Electric. . . Fire. . .
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A roleplay set in the world of Game of Thrones/A Song of Ice and Fire.
Cheltenham based aircooled VW club and forum in association with www. roastietoastie. com FOR CHAT AND MORE FORUMS PLEASE SIGN IN :)
dubbin, kriminals, volkswagen, roastietoastie, #fire, juggling


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