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Kuala Lumpur - A Nigerian student has died during a drug raid in Malaysia and four others were arrested, police said on Thursday, adding that west Africans seem to be replacing Iranians in the illicit trade.Police seized several kilogrammes of heroin and methamphetamine worth a total of 600 000 ringgit ($200 000) in a raid on a flat in Kuala Lumpur on Tuesday, said Othman Harun, deputy director of the Federal Narcotics Department.They also arrested four Nigerians in their 20s, while a fifth man tried to run away and when caught collapsed with breathing difficulties and died.Othman said police were still awaiting a report on the cause of death but believe the Nigerian could have swallowed heroin capsules to smuggle them abroad.The grade-four heroin that was seized from the apartment is not commonly used in Malaysia but destined for such countries as Australia, Othman said.Othman said police had arrested 19 Nigerians from January to April, mainly in Kuala Lumpur and at the international airport."This number is considered very high," he told AFP. "In the last few weeks, there is an increase in Western Africans, especially Nigerians, bringing in methamphetamine."Three more Nigerians have been arrested in separate cases since Friday at the Kuala Lumpur International Airport when methamphetamine was found hidden in their bags.Previously others had allegedly hidden drugs in cassavas and sweet potatoes, Othman said.All suspects held in custody face hanging if convicted of drug trafficking, which carries a mandatory death penalty in Malaysia.Othman said police believed the Nigerians were filling a vacuum left after the arrest of several Iranian alleged drug syndicate masterminds."When there is a vacuum, West Africans step in on this activity," he said.He said that police had arrested 44 Iranians for drug trafficking in the first four months of the year, and several more in May.
Ah... Nigerians... Born corrupted & spreading their vile ways across the globe. Well, for once at leas they managed to ply their deeds outside of South Africa, their preffered nesting ground.
@DABOSS247365, we are all aware that our South African brothers are very brave folks. Probably, it took them over a century to dismantled the obnoxious apathied regime. Where the South Africans failed, Nigerians succeeded greatly in those areas. It is all about envy. A nation of rapists should kept mute when Nigerians are talking
I say we send these root eating idiots back to they land......
We should start the clean up in all major cities........
have u ever travel to other countries? u look like idiots
shut up big fool what do you know apart from eating drinking,how many countries have you been do you know what it takes to be in a foreign land?good for nothing fools
All drug crimes carry mandatory death penalty in Malaysia, so being shot during arrest is just early sentencing...
I agree... it save time and paperwork (and money)
people must leave Nigerians alone
You Nigerians are the scum of the earth.
@ Edozie / chi chi - Then Nigerians should take their business elsewhere; stop selling drugs in South Africa. Then there will be reason to leave you alone. Funny 'a nation of rapists'. When you sell hard drugs to children, then the Nigerians look more like a nation of rapists. If you corrupt the innocent, it makes little difference if you do it for profit or pleasure.
I can see the bias in everyone's comment. Look at what the statistics in the report above says;
"Othman said police had arrested '19' Nigerians from January to April, mainly in Kuala Lumpur and at the international airport.
- He said that police had arrested '44' Iranians for drug trafficking in the first four months of the year, and several more in May.
Drug Trafficking is a global issue and we must together fight it.
We need to make more intellectual comments to move our societies ahead.
as far as am concerned,every country has its own share of crminality,malaysians abroad also engage in crinnal activities even worse than africans,interally it is even worse but the local media will not broadcast it on the english channel...If malaysia feel only africans ae crminals and their society is full of "holy" people then they should not have had a police force in the first place...they should stop tis persecution and handle individual cases as they arise...Fred,KL


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found it x
I found the pink mm...but couldn't find the skittle.
me too! pretty!
Found it !
Walgum, I c d pink M & M (thanks).

subset: commoncrawl


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April 11, 2010
April 10, 2010
April 8, 2010
March 3, 2010
Nick has yet to fill out a bio.
Will Arsenal's Defence Define Their Season?
made a general cricket slideshow: (humor)
Hope u can take a look.
I've finally gotten round to writing a football article! It's about players with huge potential who never quite achieved what they should have.
I think it will prove an interesting read. Let me know what you think.
Please spread the word!!!
Hello bro..i published the second part of the funniest soccer quotes ever.,..so pls have a look and give your opinion..
Hi Nick! The final 19th Hole at the Masters is up:
Thanks for all of your hard work on this one! Maybe they liked us enough to ask us to do something with the U. S. Open.
Well, thanks for being honest at least! haha! I understand my style isn't to everyone's taste and I respect your opinion and the fact that you could tell me straight. Cheers for the feedback!
Hey Nick,
I've written an article about Liverpool with religious connections as it is Easter Sunday. Now, I'm not the most religious guy on this earth, as you may have guessed, so I'm not sure how it has come out! I would appreciate your thoughts and views on it as I'm not convinced it came out as well as I had planned!
Definitely want to do a final 19th Hole after the tournament - that will be killer!
Thanks for the feedback on the tennis piece. You are the 2nd person to mention that using the 'alter ego' angle was a bit of a put-off. I will get with the two writers and see if they want to revise it. I was using the metaphor to accentuate the difference in how the 2 of them think, even when they agree. I am toying with putting the names Federer and Agassi in quotes in the title.
Hi Nick! The 19th Hole has been revised and looks good:
I also SOMEHOW managed to complete a collaboration with 2 of B/R's best in the tennis community. Take a peek and let me know what you think!
Hi Nick! Our collaboration is up. Take a look and let me know what you think!


text:
Visit California
The state's official web site for California travel planning.
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Lodi Wine & Visitor Center
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by Serge Berger | December 9, 2013 11:21 am
Chinese internet stocks have been and continue to offer juicy opportunities for active traders and those looking to follow trends. Given their recent bullish price action, most of those stocks now require a closer look again as actionable trades are waiting in the wings.
Front and center in the Chinese internet stock space is Baidu (BIDU[1]), the Beijing-based internet giant. It's easy to see why trades like BIDU are popular if we consider its respect for various technical indicators, plenty of volatility, news flow and an average daily trading volume of more than 2.6 million shares. Although the stock had a rough start to 2013, sliding more than 15 percent in the first four months of the year, it came back with a vengeance in the second half, particularly with its steep incline in July.
On the long-term chart, the BIDU stock rally has brought the stock back towards its all-time highs, which were first seen in August 2011. With momentum indicators such as the slow stochastics coiling up to spring higher and the stock having consolidated just below the August 2011 lows for the past several weeks, Baidu looks to have plenty of room to move higher in the medium term.
On the daily chart, BIDU stock has support from its 50-day simple moving average (yellow), and a series of bullish engulfing and hammer candles over the past two months. All of this is pushing BIDU right up at the upper end of the recent trading range, which stands a good chance of breaking to new all-time highs soon.
And BIDU stock is hardly alone. Just look at the performance of other Chinese internet stocks…
Sohu.com (SOHU[2]) just pushed past a multi-month resistance point last week. SOHU stock continues to look better, particularly if it can overcome its 50-day moving average (yellow line), currently near $72.10.
And thirdly, internet television company Youku Tudou Inc (YOKU[3]), which is currently consolidating/coiling-up below a multi-month resistance line, has given the bulls plenty of bullish price action lately. YOKU stock's strength is confirmed by bullish candlestick patterns that should allow for a push to new highs soon.
BIDU stock, SOHU stock, and YOKU stock all look good for higher highs in coming weeks. However, this doesn't mean you should completely drop risk management in favor or risk chasing. As always, traders must respect the possibility of bearish reversals.
Like what you see? Sign up for our daily Beat the Bell[4] e-letter and get investment advice delivered to your inbox every morning!
Learn more about the strategies Serge Berger uses to create profits in the market every day. Download his trading plan in the Essence of Swing Trading e-book by clicking here[5]. As of this writing, he did not hold a position in any of the aforementioned securities.
Source URL: https://investorplace.com/2013/12/bidu-chinese-internet-stocks/
Short URL: http://invstplc.com/1nwtZvh
Copyright ©2017 InvestorPlace Media, LLC. All rights reserved. 700 Indian Springs Drive, Lancaster, PA 17601.


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Well, i've been playing this game for quite some time now, and i'm really enjoying it. But o well the hacker in me always comes snooping around. So here are some facts (some better proven then others)
- Uses blowfish ECB for send/recv
- Uses WSARecvFrom & WSASendTo
- The key for that game session is given to the game client thought command line by the launcher process
- The key is base64 encoded
- Still not sure what they do with the (packetLenght-headerSize) % 8, i'm thinking of some custom simpel xoring, but no idea yet for that part.
I'm currently trying to derive what the different headers for the recv packets means, its quit a hassle but i think i'm starting to see the pattern. You have 2 different types, a multi packet header (32 bytes) and a solo packet header (14 bytes)
Well while i'm making this, i'm upping my IntPe9 packet editor, and its getting awesome. Currently it works through:
- Boost IPC (message que)
- Qt GUI client
- Skeleton hooking system for a per target app
Well i keep you informed about progress on these 2 projects.
Tags: base64, blowfish, decryption, encryption, League of Legends, LoL, packet, packet encryption


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S39 - Timbavati Road
Discuss the different camps and roads of the Kruger National Park
Re: S39 - Timbavati Road
PHVDM wrote:I am wondering whether to take the S39 via S127 (Ntomeni) or the H1-4, from Satara to Olifants. The H1-4 has never been good to me, always had poor sightings.
The S90 is also an option, but they say it's also a very poor road for sightings. Any suggestions for the best route?
It's always difficult to suggest a route to take....things could change so rapidly!
However, I planned to take the S90 (a road that I really love) when we travelled from Satara up to Balule; but turned around after about 2 km; the combination of the extremely dry conditions (similar to the S39 which we took on the way back a week later) and quite bad corrugations changed my mind!
We actually saw quite a lot along the H1-4, including 4 of the big 5 (no lions, saw those earlier just north of Tshokwane). I am not a big fan of the tar roads, but in this case the water holes along the H1-4 presently makes this probably the best bet right now.
Latest lifers: House Crow, Grey-backed Cisticola, Ludwig's Bustard, Tractrac Chat, African Reed Warbler, Black-bellied Starling, Plain-backed Pipit, Common Buttonquail, Cutthroat Finch, Freckled Nightjar
Re: S39 - Timbavati Road
Thank you Albert. I think the H1-4 will be best road to take!
Shingwedzi 1-5/10
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Some good news for those who either do not, or prefer to not speak English while using Google Voice Search on a mobile device. Well, more specifically, on an Android device. It seems Google has recently added support for an additional 13 languages. The new support comes for;
Basque, Bulgarian, Catalan, European Portuguese, Finnish, Galician, Hungarian, Icelandic, Norwegian, Romanian, Serbian, Slovak, Swedish
This brings the total of supported Voice Search languages up to 42 (with accents in 46 countries). That bit aside though, those with a device running Android 2.2 or later will see the microphone icon on the Google Search widget — from here you simply have to tap the icon and begin speaking. You can also install the Voice Search app which can be found in Google Play. Finally, there is one limitation (though we suspect that this will not bother all that many users) — you can only speak in one language per search.
Via [Official Google Blog]


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Geet Asher
Mom - Poem by Geet Asher
Mom oh mom without you i am no one.
Whenever i needed u,
you were always there for me,
mom oh mom without you i am no one.
You had bore the pain for me,
when i was in your big belly.
You raised me with full of heart,
as i was your only one,
mom oh mom without you i am no one.
You have always helped me,
in making me right,
whenever i was wrong.
Without you i would be going to a path,
which i would have never known,
mom oh mom i will make u proud my mom.
You always bring a smile on me,
whenever im sad and lonely.
I could have never asked for a mom,
as great as u my only mom.
mom oh mom im so glad to have you as my mom.
Comments about Mom by Geet Asher
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Geet Asher's Other Poems
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Maya Angelou
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Stopping By Woods On A Snowy Evening
Robert Frost
I Do Not Love You Except Because I Love You
Pablo Neruda


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Large federation of labor unions is strongly Democratic.
A Project of The Annenberg Public Policy Center
Who are the people and groups behind the TV ads in the 2014 federal elections? Below is a list of organizations that have been active or are expected to be active in raising and spending money to influence voters in 2014. Click on the links to read profiles of each organization. The groups were selected based on the amounts they have spent, or say they plan to spend, or the media attention they have attracted. It is not a comprehensive list, and additional groups will be added as the campaign season unfolds.
Many of these groups may legally raise and spend unlimited amounts of money. They are known as super PACs and must register with the Federal Election Commission. Others may legally raise unlimited donations and avoid disclosing their donors. Those groups do not file with the FEC, but register rather with the IRS under Section 501(c).
This is our third year providing a guide to groups seeking to influence federal elections. Our 2010 Players Guide and 2012 Players Guide are still available, although they have not been updated since those elections ended.
Large federation of labor unions is strongly Democratic.
A super PAC and a nonprofit sister organization launched by former Obama White House staffers as a Democratic counter to American Crossroads/Crossroads GPS.
Democratic-leaning labor union representing 2.1 million health care, government and property management workers.
A liberal super PAC that conducts opposition research to aid Democratic candidates and organizations.
A 501(c)(4) founded by a former Republican senator and a longtime GOP fundraiser. It focuses on keeping the House in Republican control.
Affiliated liberal groups founded by a Democratic political strategist and heavily funded by labor unions.
A liberal super PAC founded by San Francisco billionaire and climate-change activist Tom Steyer that focuses on environmental issues.
A super PAC that has opposed House incumbents from both parties in primary elections.
An environmental group launched in 1969 that targets a "Dirty Dozen" list of politicians for defeat.
A labor union that represents more than 1.6 million public sector employees and retirees.
Q: Did President Donald Trump shut down a service dog training program for veterans?
A: No. Walter Reed National Military Medical Center ended its contract with the program and told us that the president was not a factor.


text:
A bill being viewed by some as discriminatory and by others as a protection of religious freedom will go before Gov. Jan Brewer on Friday.
Senate Bill 1062, which allows private business owners to deny service to gays and lesbians based on religious freedom, passed the Republican-controlled state Senate last week before also receiving approval by the state House of Representatives in a 33-27 vote on Thursday.
Brewer, who is still in the process of weighing the mixed input she has received from critics and supporters, spoke to CNN on Friday, but gave no distinct indication as to her leaning.
"I think anybody that owns a business can choose who they work with or who they don't work with," Brewer said. "But I don't know that it needs to be statutory. In my life and in my businesses, if I don't want to do business or if I don't want to deal with a particular company or person or whatever, I'm not interested. That's America. That's freedom."
The bill has gained national attention since its inception, receiving support primarily from conservatives and criticism from both sides of the political aisle.
That pattern is similar at the local level, where legislators from five Arizona districts unanimously voted no on the bill, one district saw mixed votes, and two districts unanimously supported it.
Sen. Al Melvin, R-District 11, announced his support of the bill on Saturday.
"The Religious Freedom Restoration Act (RFRA), also known as SB1062, protects the rights of every Arizonan to work and live according to their faith," Melvin wrote in a release. "It prohibits punishing someone because of faith. It is common sense, it is a good law, it was carefully crafted, it was supported by more than 90 percent of the Republicans in the legislature, and I strongly urge the governor to sign the bill."
A candidate for governor, Melvin also announced his displeasure with fellow Republican candidates that did not support the bill.
"I was disappointed how fast my fellow Republican candidates for governor caved to the media and liberal pressure," wrote Melvin. "Each of them offered excuses, but none of them were willing to stand up and publicly fight to protect the religious liberties of Arizonan citizens and businesses."
But local business organizations such as the Tucson Metro Chamber, the Greater Oro Valley Chamber of Commerce, and the Marana Chamber of Commerce have taken the opposite stance, each publicly announcing their disapproval of the bill.
The Tucson Metro Chamber sent a letter to Brewer asking her to veto the bill.
"We are writing to you on behalf of the 1,450 member businesses of the Tucson Metro Chamber and their 110,000 employees to ask that you veto SB1062. While the authors of SB1062 may have had good intentions, it is our opinion that, if enacted, SB1062 will have immediate and long term negative economic impact," the letter stated.
Sen. Steve Farley, D-Tucson said it makes sense that the bill, sponsored by Steve Yarbrough of Chandler, is unfavorable to such business organizations.
"I think this bill makes a statement … that we don't welcome people here," Farley said. "This bill gets in the way. This bill sends the wrong message around the country and around the world."
U.S. Sen. John McCain, R-Ariz., recently tweeted, "I hope Governor Brewer will veto#SB1062."
The bill was introduced after a New Mexico case in which a gay coupled successfully sued a wedding photographer for denying service.
Here's how Arizona lawmakers voted on the bill:
District 2
Sen. Andrea Dalessandro, no
Rep. Rosanna Gabaldón, no
Rep. Demion Clinco, no
District 3
Sen. Olivia Cajero Bedford, no
Rep. Sally Ann Gonzales, no
Rep. Macario Saldate, no
District 4
Sen. Lynne Pancrazi, no
Rep. Juan Carlos Escamilla, no
Rep. Lisa Otondo, no
District 8
Sen. Barbara McGuire, no
Rep. Frank Pratt, yes
Rep. T.J. Shope, yes
District 9
Sen. Steve Farley, no
Rep. Ethan Orr, no
Rep. Victoria Steele, no
District 10
Sen. Dave Bradley, no
Rep. Stefanie Mach, no
Rep. Bruce Wheeler, no
District 11
Sen. Al Melvin, yes
Rep. Adam Kwasman, yes
Rep. Steve Smith, yes
District 14
Sen. Gail Griffin, yes
Rep. David Gowan, yes
Rep. David Stevens, yes


text:
Roxanne Johnson
Touching a human spirit beyond the diagnosed disease, causing a heartfelt smile in a failing heart, are the results of an act of service that reaches far beyond the logical reason of time. Nursing touches the essence of charity, compassion and care. It is layered with strength, and selflessness. These ringing concrete undertones provide layers of an advocates heart straddled with protective courage of those who are preciously fragile and unable to find their voice.
A bustling ward, with beeps of monitors and a radiant baby warmer, an unusual place for normal person. An eight-pound baby lies asleep with cords extending to different machines. A kind, gentle lady checking the tubes, she gracefully glides over the machines and sweeps her hands across a few buttons. She turns and smiles and explains that everything will be okay. Thirteen days passed and she explains with cautious excitement, he is all yours, he is good and you are ready and so is he to go home!
That was eight years ago when my newborn suffered a critical medical condition. As a new mother, helpless and alone, I was forced to trust someone else to take care of my boy. It was scary and terrifying. My nurse, my son's nurse was the star in my day, and all emotions rested on her words and her actions. She was my voice when no question could come to mind about foreign procedures that I only heard of until the moment in time. The ability to care for a mother and child is an enormous responsibility, which she did. Leaving that hospital, I was convinced I wanted to be just like her. I wanted to be taking care of sick babies and their families. I wanted to encourage a scared first time mother to be strong and help find her voice. I wanted to be a baby nurse.
The Robert Wood Johnson Scholarship has given me the opportunity to make this dream come through. Leaving behind everything that I knew as normal, I began my journey in nursing. Getting this scholarship gave me the opportunity to pay my tuition and support my family on a part-time wage in order to fully dedicate my time to the nursing program. This, I strongly believe, has resulted in my success thus far in completing my classes.


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As the days continue to get longer, The Raptor Center at the University of Minnesota anticipates the upcoming raptor baby season.
Typically it begins with great horned owls which lay their eggs as early as the end of January and incubate them during the harshest Minnesota winter weather. Eggs start hatching at the end of February, and by mid-March the downy juveniles can often be detected in the nest.
Great horned owls do not build their own nests. Most often, they use the old stick nests of hawks and crows, although sometimes they lay eggs on structures such as platforms, unused machinery, and decks of abandoned buildings.
The old nests are usually worn from previous use, winter weather, or even exploration by raccoons and other predators, and do not have the integrity to support owl babies as they grow. Thus, a relatively large number of great horned owlets come out of the nest before they can fly.
In the majority of these instances, they land uninjured and the female will raise them on the ground, feeding and fiercely protecting them from potential predators (including humans) during hours of darkness.
What can you do?
If you find a juvenile great horned owl on the ground or perched on an unusual structure, DO NOT REMOVE IT. Please contact The Raptor Center (phone 612-624-4745 or email firstname.lastname@example.com) for guidance. Humans cannot raise raptor babies as effectively as can their own parents.
The majority of the time the adults are close by, raising their youngsters in a fashion typical of the species, even if we don't immediately see them.
The rearing behaviors of raptors do differ by species, so as the baby season continues and youngsters from other owl and hawk species appear, please DO NOT REMOVE THEM from near their family. Please contact The Raptor Center to determine if intervention is really necessary. We all want to do the right thing by our feathered friends. The Raptor Center can help with advice on each instance to make sure that these raptor families stay healthy and together.
Note: This post first appeared on The Raptor Center's blog.


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My trusty old laptop is getting a bit long in the tooth and I'm toying with switching to a desktop.
I fancied something with plenty of processing grunt for video editing, plenty of storage space for, well stuff, and I don't really need a lap top as I've an iPad that I tend to use for general web browsing.
Choice seems to be really limited compared to when I last brought one.
Anyone got any recommendations?


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Chipotle Mexican Grill
Go ahead and make my Cinco de Mayo.
And Chipotle Mexican Grill did just that by introducing soft corn tacos. Previously, only hard (i.e. fried) corn or soft flour tortillas were being used to make tacos — so very un-Mexican. This glaring deficit was the sole complaint I had about the high quality chain where carefully sourced ingredients (local and organic when possible) are routinely used.
So, there I was, about to order lunch at the Chipotle in Deer Park, when I beheld a sign proclaiming the advent of the soft corn taco. All I could think was: yay!
Since tacos come three to an order, I got one filled with spicy dark meat chicken, another with barbacoa (spicy shredded beef braised with chipotle) and the third with carnitas (highly seasoned seared and braised pork). It doesn't take that much to make me happy; just near-perfection. And that's where Chipotle seems to be heading in the fast food sphere.
There are Chipotle Mexican Grill locations in Hicksville, Farmingdale, Deer Park, Huntington Station, Uniondale and Carle Place.


text:
This product is no longer available.
You can try these similar gifts instead.
Galway Crystal Bride and Groom Toasting Glasses
Made in Ireland, these glasses are the perfect way to toast to a long and happy marriage. They'll be the final touch that makes their ceremony and their celebration perfect. Give them to a lovely bride and groom.


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Cuttlebug Anna Griffin Embossing Folder & Border A2 - Blossom Dance
Ideal for scrapbooking and card making. Can be used in most die cutting systems
eB1 390
Discovery Miles 1 390
This item is in stock in our CPT warehouse and can be shipped from there.You can also collect it yourself from our warehouse during the week or over weekends.
This item is in stock in our JHB warehouse and can be shipped from there. No collection facilities available, sorry!
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- Warranty
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- Dimensions (mm)
- 210x120x5
- Title
- Cuttlebug Anna Griffin Embossing Folder & Border A2 - Blossom Dance
- Country
- South Africa
- Brand
- Cuttlebug
- Barcode
- 093573039850
Hannelise, South Africa. 18 February 2014
The coolest, The cutest, The most steadfast little embossing and die cutting machine EVER! Just love it!
Valerie, South Africa. 20 February 2014
a very very very lovely product
Priya, South Africa. 26 March 2014
This was an excellent purchase. Waiting to get more die cuts and embossing stencils to see its true potential.
Mariam, South Africa. 26 March 2014
Fun product
Nevillene, South Africa. 9 May 2014
love it
Natalie, South Africa. 8 July 2014
I was really impressed when I received the product much quicker than expected.
The Cuttlebug is nicely packaged and a sturdy little device. It comes with the 2 A-plates and B-plates, as described, I was surprised to find 1 Cuttlebug embossing folder in the box. A pleasant experience overall. Thanks.
Tracey, South Africa. 20 August 2014
Got mine, and loving it, just wish there was a little more info available as to what you need to get, etc. Sure once have some more folders and dies it will give me hours of fun.
Takealot good prices and excellent service.
Lizette, South Africa. 30 November 2014
Great Product... Very quick shipping.. Thank you...
Lisa, South Africa. 15 January 2015
Love, love, LOVE my new Cuttlebug!
Casper, South Africa. 28 January 2015
After using a friend's Cuttlebug and seeing the vast range of embossing and die cutters she had and I was blessed to receive some samples to use for my cardmaking and scrapbooking, I was hoooooooooked. I was given a Cuttlebug for Christmas and wait with baited breath to be able build up my collection of embossing and die cutters. An awesome little machine that is so easy to operate and compact to store.
Estelle, South Africa. 26 November 2015
Absolutely LOVE my Cuttlebug!!!! Super easy to use and extremely awesome <3


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is back-ordered. We will ship it separately in 10 to 15 days.
You will love to cuddle with this soft and adorable CK Manatee. Each highly detailed CK Manatee comes with lifelike facial and authentic features. With its ultra-plush stuffing, the CK Manatee is so cute and huggable. Measures approximately 12".
Wild Republic successfully provides a wide range of interactive and innovative toys that spark the imagination and make learning fun. Wild Republic has been delighting and educating children with an expansive collection of nature-related toys and gifts since 1979'
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text:
|Publication number
|Publication type
|Application number
|Publication date
|27 Jul 2004
|Filing date
|8 Jun 2001
|Priority date
|25 Feb 2000
|Fee status
|Also published as
|Publication number
|Robert Osann, Jr., Shafy Eltoukhy, Shridhar Mukund, Lyle Smith
|Original Assignee
|Lightspeed Semiconductor Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (41), Non-Patent Citations (8), Referenced by (20), Classifications (8), Legal Events (8)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a continuation-in-part of application Ser. No. 09/512,783, filed Feb. 25, 2000, now U.S. Pat. No. 6,694,491, and claims priority to Provisional Application No. 60/231,059, filed Sep. 8, 2000, both incorporated by reference herein.
This invention generally relates to Application Specific Integrated Circuits (ASICs), and particularly to Programmable Logic Arrays (PLAs) incorporated into non-reprogrammable ASIC devices.
Application Specific Integrated Circuits (ASICs) have become widespread in the semiconductor industry. ASICs are generally integrated circuits that are customizable to implement a circuit specified by a design engineer or other user (a "user-defined" or "user-specified" circuit).
ASICs can be divided into two groups: (1) those that are "multi-time configurable" or "reconfigurable" (i.e., they can be programmed with data and reprogrammed) and (2) those that are only "one-time configurable" or "non-reconfigurable." Multi-time configurable devices include Programmable Logic Devices (PLDs) and FPGAs. One-time configurable devices include some gate arrays and module-based arrays (MBAs). A general discussion of each technology will be useful.
Multi-time Configurable Devices
Generally, most PLDs are based on a PLA structure where a function is expressed in product terms and sum terms to be implemented. Each product term is generated by a gate that can be programmed to form the AND of any subset of the inputs and their complements. Subsets of the product terms can be summed in a set of programmable OR gates.
PLAs are constructed in the form of arrays, with the input lines being orthogonal to the product lines, as shown in the generalized circuit diagram of FIG. 1. FIG. 1 shows one type of PLA known as a PAL. In FIG. 1, PAL 100 includes inputs 106, A, B, and C, where each input and its complement is input into programmable AND array 102 on lines 104. Product term lines 110 are formed orthogonal to lines 104. When the intersection between the input term and a product term line is programmed, then "AND terms" or "product terms" 108 are formed. The product terms 108 are then fed into OR gates 112, forming "sum terms" 114.
Product-terms are often implemented with a wired-OR mechanism, where multiple programmable transistors 116 are connected to the product-term line 110 and a pull-up 118 is used, as shown in the generalized circuit diagram of FIG. 2. Although the pull-up 118 is shown as a resistor in FIG. 2, frequently a passive pull-up is implemented with a biased P-channel transistor instead.
A second type of PLA structure (sometimes referred to as a "Full PLA") is shown in FIG. 3, having both a programmable AND array 102 and a programmable OR array 111. In other words, both product terms and sum terms can be programmed using the device of FIG. 3. Relative to the device of FIG. 1, the device of FIG. 3 sacrifices some speed, but has greater programming flexibility and is better for implementing state machines. As well, unlike the FIG. 1 device, in the FIG. 3 device, product terms can be shared among all OR terms. Thus, the device of FIG. 3 can implement any set of combinational logic limited only by the number of inputs, outputs, and product terms.
Flexibility of PLA structures, including those of FIGS. 1 and 3, can be further enhanced by adding flip-flops to one or more of the outputs to create general-purpose sequential circuits, often referred to as "sequencers." A generalized block diagram of such a device is shown in FIG. 4. In FIG. 4, the sum terms 114 output from the OR array 111 can feed directly to output pins 506 or to inputs of a flip-flop 508. The flip-flop outputs can be fed back either to the AND array 102 or directly to output pins 506. Product terms 108 can also be fed back into the AND array, often through an inverter 510 to create "expander" terms (such feedback often creates what is known as a NAND-NAND array or a NOR-NOR array). Not all sequencers have all of these options available. Nonetheless, such options are ideal for state machines.
Each of the conventional PLA structures described in FIGS. 1-4 is usually a discrete device and is programmable and reprogrammable by the user either using a specialized programming device or in-system as is understood in the art. As should be understood in the art from FIGS. 1-4, there are numerous types of PLAs available and those described are exemplary only.
One-time Configurable Devices
The second category of ASIC mentioned is a one-time configurable ASIC, frequently gate arrays, MBAs, or standard cells. Typically, these one-time configurable devices are configured (or customized) by "mask-programming"—i.e., these devices are customized once using various mask and etch steps to form interconnections dictated by a user-defined circuit. Once configured, these mask-programmed devices are not reconfigurable.
An example MBA is shown in the generalized block diagram of FIG. 5, and is composed of an array 702 of function blocks 704. Each function block 704 in an MBA usually includes a predefined circuit that is often identical in all function blocks. To customize the device, mask-programming techniques are used to interconnect the function blocks in a manner that creates a user-defined circuit. In other words, to configure the device, mask and etch techniques are used to form the conductors that interconnect the blocks 704 and/or interconnect active devices within the blocks 704.
Gate arrays are known in the art and are similar in many respects to MBAs, except they are frequently composed of a "sea of gates"—prefabricated transistors that are (for the most part) unconnected to one another. These gate arrays are also configured using mask and etch techniques to interconnect the active devices and thereby form a user-defined circuit.
More specifically, as shown in FIG. 6, each MBA (or standard cell or gate array) is formed from many layers that usually include an active layer 810 (where active devices such as transistors are formed) and several metal layers (M1-M4) 820, 830, 840, and 850 separated by insulation layers 815, 825, 835, 845. Frequently, an MBA device will be prefabricated up through a particular metal layer, say M2. Then customizing will be done in metal layers above, say M3 and M4. Although four metal layers are shown, MBAs can contain more or fewer metal layers, and four is used as exemplary only. As well, customization can be done using any number of metal layers.
Another type of mask-programmed device is a "standard cell." A standard cell is similar to an MBA, but instead of predefined function blocks, it includes custom cells that are optimized for performing a respective designated function. In other words, compared to MBA function blocks, the custom cells of a standard cell device have adjusted transistor size and placement and have eliminated extraneous devices. Thus, standard cells are customized in all the layers shown in FIG. 6, including active layers 810. Both MBAs and standard cells, however, often use libraries to store available potential logic functions that can be implemented by function blocks (in the case of MBAs) or a custom cell (in the case of standard cells) for easier configuration. Gate arrays can also utilize similar libraries.
Once the customizing metal layers have been designed and implemented, the mask-programmed device (e.g., MBA or standard cell) is said to have been configured—but it cannot be reconfigured. As a result, designers of mask-programmed ASICs typically implement high-speed logic functions, including state machines and control logic, with conventional non-reconfigurable ASIC gates. Still, in many instances, when a mask-programmed device is configured, many parts of the implemented circuit are not fully verified. Moreover, during the development process, changes often need to occur in certain parts of the circuit, such as the control logic. Therefore, frequently portions of the circuit that are to be reconfigurable or may need to be changed are typically separately implemented in a separate PLD device. Thus, it is desirable to maintain some level of reconfigurability in at least part of the circuit, thereby minimizing the use of multiple ICs.
In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment, receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.
The ability to reconfigure a portion of a one-time configurable device is especially useful where time-to-market and flexibility are particularly important. Such reconfigurability is also useful for high-risk circuits and state machine control. For instance, if a designer using a mask-programmed device is unsure of part of his/her design, the designer may want the ability to reconfigure a portion of that design without having to resort to multiple chips. In particular, because most circuit changes in a user-defined circuit occur in the control logic, a PLA structure incorporated into a mask-programmed device in accordance with the invention is particularly useful for implementing a circuit's control logic.
The present invention is described with respect to particular exemplary embodiments thereof and reference is accordingly made to the drawings in which:
FIG. 1 is a generalized circuit diagram of a PAL;
FIG. 2 is a circuit diagram illustrating a more specific circuit diagram of a portion of a PLA;
FIG. 3 is a generalized circuit diagram of a full PLA;
FIG. 4 is a generalized block diagram illustrating flip-flops used to enhance PLA functionality;
FIG. 5 is a generalized block diagram of an MBA;
FIG. 6 is a generalized cut away view showing the layers of an ASIC;
FIG. 7 is a generalized block diagram of a PLA in accordance with the invention;
FIG. 8 is a generalized block diagram of a one-time configurable ASIC incorporating PLAs in accordance with the invention;
FIG. 9 is a generalized flow diagram illustrating the creation of a one-time configurable ASIC with a multi-time configurable portion in accordance with the invention;
FIG. 10 is a generalized flow diagram illustrating the generation of a programming pattern to use in the programming of a multi-time programmable structure incorporated in a one-time configurable device in accordance with the invention.
FIG. 11 is a function block diagram in an MBA used in one embodiment of the invention;
FIG. 12 is a function block diagram in an MBA used in another embodiment of the invention;
FIGS. 13 and 13a show a function block diagram illustrating a configuration of the function block of either FIG. 11 or 12 used in an embodiment of the invention;
FIGS. 14 and 14a show a function block diagram illustrating a second configuration of the function block of either FIG. 11 or 12 used in an embodiment of the invention;
FIG. 15 is a function block diagram of a portion of an MBA used in one embodiment of the invention that is useful for loading a programming pattern into a PLA in accordance with the invention;
FIG. 16 shows the configuration of FIG. 12 and further illustrates use of a default pattern in accordance with an embodiment of the invention; and
FIG. 17 shows the embodiment of FIG. 12 and further illustrates an embodiment that uses both a default pattern and external loading.
In accordance with the invention, a multi-time configurable structure such as a reconfigurable PLA structure is incorporated into a one-time configurable ASIC. In accordance with the invention, the following generalized steps can be performed to obtain reconfigurability. First, the designer (user) defines the planned functionality for the ASIC as a whole, including the functionality that the designer believes will be required for the particular reconfigurable logic block, such as a state machine. The designer designates that portion of the functionality that is to be reconfigurable, and software next takes the specified description of the designated functionality to model a PLA structure suitable for implementation of that reconfigurable logic. The designer and/or software then adds a selected number of AND terms, OR terms, nonregistered outputs, registered outputs, state-bits, etc., to allow for expansion or modification of the functionality in the event of later reprogramming. This modeled PLA structure (with added capacity) is then incorporated into the rest of the ASIC design.
Hence, as shown in the generalized PLA structure 900 of FIG. 7, the number of inputs I, the number of product terms P, the number of sum terms S, the number of non-registered outputs X, the number of registered outputs Y, the number of state bits Z (registered output with feedback), and any other characteristics of the PLA are specified by the designer and/or software. Further, not only can a PLA structure 900 in accordance with the invention be implemented in a mask-programmed device in virtually any size with any features, but as shown in FIG. 8, there can be multiple PLAs 900 in one particular ASIC device, where each has a different size (indicated by dashed lines) and/or features.
Creating a PLA Within an ASIC
The particular steps used to form a reprogrammable structure with a non-reprogrammable device in accordance with an embodiment of the invention are shown with respect to FIG. 9. As shown in FIG. 9, a user-defined circuit to be implemented by the ASIC device is functionally defined in HDL or other functionally similar language, 1102. The portions of that user-defined circuit that are to be reconfigurable are marked or designated by the user in some fashion, and then the marked portions are automatically converted 1104 to produce a PLA format file 1106 that can accommodate the specified reconfigurable functionality. In other words, a PLA sized for the functionality as specified by the user is first modeled. As a result of step 1104, a PLA Format File 1106 is generated that includes the number of product terms, sum terms, inputs, outputs, etc., as defined by the user's specified functionality.
Next, in some embodiments of the invention, additional capacity 1108 is added to the PLA format file 1106 (to accommodate changes and/or modifications in functionality later) in step 1110 to generate a structural netlist 1112 for the PLA. The amount of additional capacity 1108 can be determined by the circuit designer or it can be added automatically by software (e.g., by automatically making the PLA 10% larger than required to accommodate the user's functionality).
In still other embodiments a PLA in accordance with an embodiment of the invention could even be designed to perform two or more diverse tasks. In other words, a single PLA could be built, but it may be used in circuitry that could be applied to two (or more) distinct applications. In such a case, the functionality for the PLA for each task will be different and the PLA will be later programmed based on one set of functionality or the other. Thus, in accordance with an embodiment of the invention, the initial size of the PLA will be generated according to the larger set of functionality and then additional capacity can be added (if desired). In another embodiment of the invention, the size of the PLA will be generated to accommodate the union of the set of designs being merged, essentially creating an array that accommodates a superset of the functionality.
In one embodiment of the invention, structural netlist generation 1110 creates netlist 1112 in terms of an ASIC library. Nonetheless, it is to be understood that in a preferred embodiment of the invention, although an ASIC cell library is utilized, the entire PLA is a custom PLA—i.e., the ASIC cell library does not include a primitive logic function for a PLA having a designated number of inputs, outputs, p-terms, etc., although other embodiments may utilize such a primitive logic function in a library. The structural netlist 1112 models the PLA that is actually to be constructed.
After the netlist 1112 has been generated, PLA physical layout and timing extraction is performed 1114. As a result, a PLA placement 1116 is generated, defining a physical relationship among the functions that form the PLA. Such a placement can be used in many embodiments of the invention to optimize PLA performance.
In the meantime, a structural netlist 1118 for the rest of the ASIC has been synthesized 1120 from the HDL file 1102. The PLA placement 1116 is combined with a structural netlist for the complete ASIC (minus the PLA) 1118 to perform the physical layout and timing extraction 1122 for the entire ASIC device. Once the layout for the entire device has been performed, the ASIC can be fabricated (e.g., completely fabricated or selected layers mask-programmed) 1124, resulting in custom ASIC 1126 that includes a custom and reprogrammable PLA.
Simulation of the ASIC can be performed at various stages during the ASIC creation process of FIG. 9. For instance, once the structural netlist for the PLA 1112 and the netlist for the rest of the ASIC 1118 are generated, then functional simulations can be run 1128. Then once PLA physical layout and timing extraction is performed 1114, PLA timing data 1130 is generated and can be used for more accurate simulations with the pre-layout timing data 1132 for the rest of the ASIC. In many embodiments as well, the PLA can be simulated alone, without combination with the data for the rest of the ASIC. Finally, after physical layout and timing extraction 1122 for the entire ASIC is formed, post-layout timing data 1134 for the entire device is generated and further (even more accurate) simulations can be run. As should be understood, there are many options for providing timing data and other information for simulations and those described are exemplary only.
Many of the steps shown in FIG. 9 can be performed by either the ASIC supplier or the ASIC purchaser/user. For instance, in one embodiment, the user performs step 1104 and provides a PLA format file 1106 to the ASIC supplier who then performs steps 1110, 1114, 1122, and 1124. The user would receive timing data back from the supplier to perform simulations 1128. In other embodiments, the user further performs steps 1110, 1112, and 1122, while the supplier only performs 1124. In still other embodiments, the user will perform a subset of these steps (e.g., 1110 or 1110 and 1114) while the supplier performs the remainder. Hence, as should be understood, the steps performed by the user and those by the supplier will vary from embodiment to embodiment.
As should be further understood from the flow of FIG. 9, the PLA is generated and integrated into the rest of the ASIC automatically. There is no need for manual generation or placement of a custom PLA into the target ASIC technology. Moreover, many embodiments of the invention will not need special tools to create such a PLA but can use the standard tools that it would use for formation of the rest of the ASIC—for instance, the same place and route tools would be utilized. Thus, as used herein, the term "automatic" refers to lack of time-consuming manual generation, placement, or routing. The term "automatic" is not, however, meant to exclude all user or operator interaction from the process. For instance, even if the user/operator is prompted for a response between the steps illustrated in FIG. 9, the process is still considered automatic.
Generating a Programming Pattern
FIG. 10 illustrates steps taken in order to reprogram a PLA incorporated into a one-time configurable ASIC in accordance with the invention. First, the HDL description of the new PLA functionality 1102′ will be converted 1104 to create a PLA format file 1106′, similar to that done in FIG. 9. Next, the structural netlist 1112 for the PLA and the PLA placement 1116 files (both of which were previously generated during the construction of the device (FIG. 9)) are used to map the new PLA format file 1106′ in step 1140. As a result, a revised programming file 1142 is generated that contains the programming pattern that is to be loaded into the already built ASIC 1126. (The actual loading of the program data will be discussed below.)
Physical Structure
The structure for a PLA device in accordance with the invention will vary with the ASIC technology utilized. For instance, in one embodiment using a standard cell where all the layers are customized, the structure of a PLA device in accordance with the invention can be designed to look much like conventional PLAs as described with respect to FIG. 2—e.g., product terms implemented with a wired-OR mechanism by connecting multiple transistors to a product term line. Likewise, with many gate arrays where transistors in function blocks are not interconnected (or are minimally connected) in each function block, a FIG. 2-like structure may be implemented.
This wired-OR approach, however, typically requires a PLA structure with a regular array, i.e., one that has wired-OR lines that have the same length and loading, because it usually uses sense amps coupled to that line to amplify signals. If the wired-OR lines are not all the same length with the same loading, then the sense amps would necessarily also have to be different, creating more complicated design issues.
Therefore, in other embodiments, the structures will be different. In MBA devices, for example, circuits in each function block are pre-defined (i.e., designed and/or formed prior to receiving the user-defined circuit) and often do not contain leftover or otherwise available transistors to implement conventional PLA configurations. The existing functionality and/or devices must be adapted.
An example of a function block 1200 in an MBA used in one embodiment of the invention is functionally shown in FIG. 11. Function block 1200 generally includes three multiplexers 1260, 1280, and 1296 and two bit-storage units 1270 and 1288. First multiplexer 1260 has a first input for receiving a signal DS on line 1262 and a second input, which is coupled to the output of bit-storage unit 1288 via line 1294. DS serves as a signal input into function block 1200. Multiplexer 1260 has two internal paths to its output on line 1264. The first, or upper, path couples the input on line 1294 to multiplexer output on line 1264 when switch 1263 is closed. Switch 1263 is controlled by signal F on line 1268. The second, or lower, path couples the DS signal on line 1262 to the output on line 1264 when switch 1261 is closed. Switch 1261 is controlled by signal M on line 1266. Multiplexer 1260, and others like it, are herein referred to as "dual-control multiplexers."
Bit-storage unit 1270 receives as an input the output from dual-control multiplexer 1260 on line 1264. In one embodiment of the invention, bit-storage unit 1270 is a pair of cross-coupled inverters 1272 and 1274 as shown in FIG. 11. Inverter 1274 is generally designed to be weaker than inverter 1290 in order to allow any changing bit outputs from multiplexer 1260 to be placed in bit-storage unit 1270 by overdriving inverter 1274. In addition, inverter 1274 is enabled and disabled by signal M on line 1266. Thus, bit-storage unit 1270 can be configured to appear as a simple inverter in certain configurations of function block 1200.
Dual-control multiplexer 1280 receives as a first input the output of bit-storage unit 1270 on line 1276. The other input to multiplexer 1280 is coupled to signal DA on line 1278, an input into function block 1200. Similar to multiplexer 1260, multiplexer 1280 has two signal paths, each controlled by a respective switch 1281 or 1283. Signal S on line 1282 controls switch 1281 while signal L on line 1284 controls switch 1283.
Bit-storage unit 1288 receives as an input the output of dual-control multiplexer 1280 on line 1286. Like bit-storage unit 1270, bit-storage unit 1288 is, in one embodiment, composed of a pair of cross-coupled inverters 1290 and 1292, where inverter 1292 is weaker than inverter 1272, and where inverter 1292 is selectively enabled by signal L on line 1284.
Multiplexer 1296 receives as a first input the output of bit-storage unit 1288 on line 1294. The second input to multiplexer 1296 is received from the output 1276 of bit-storage unit 1270. Multiplexer 1296 further has a select input SX, which multiplexer 1296 receives on line 1297 and which selects one of the multiplexer's inputs to be output onto line 1298.
Line 1298 is coupled to inverter 1301, which serves as a buffering mechanism and which outputs signal Q on line 1302.
In addition, function block 1200 also includes select and enable logic, which selects the various switches in multiplexers 1260 and 1280 as well as enables inverters 1274 and 1292 in bit-storage units 1270 and 1288, respectively. The select and enable logic in one embodiment includes NOR gate 1304, NAND gate 1310, NAND gate 1316, and inverters 1322 and 1324.
NOR gate 1304 has a first input MC on line 1306, an input into function block 1200, and a second input received from the output of NAND gate 1310 via line 1268. NOR gate 1304 outputs signal M on line 1266, which controls switch 1261 and enables inverter 1274.
Inputs to NAND gate 1310 are EN on line 1312 and AS on line 1314, both inputs to function block 1200. The output 1268 from NAND gate 1310 is the signal F which controls switch 1263 in multiplexer 1260.
NAND gate 1316 receives as inputs signal SC on line 1318 and signal S2 on line 1320, both inputs to function block 1200. The output of NAND gate 1316 is coupled to inverter 1324, which outputs signal S on line 1282 to control switch 1281 in multiplexer 1280.
Inverter 1322 also receives signal S2 on line 1320 and outputs signal L on line 1284 to control switch 1283 of multiplexer 1280 as well as inverter 1292 in bit-storage unit 1288.
While select and enable logic for function block 1200 is shown in FIG. 11 as NOR, NAND, and inverting gates, a person of ordinary skill in the art will recognize that a number of other gate combinations are possible. Further, select and enable logic is not shown fully connected in FIG. 11 to aid in the clarity of the figures. However, the connections should be clear to those of skill in the art by the signal names and/or line reference numbers provided.
In some embodiments of the invention, function block 1200 forms only a portion of a larger function block. A more detailed explanation of these function blocks and MBAs can be found in Function Block Architecture for Gate Array, Ser. No. 08/821,475, filed on Mar. 21, 1997, and Test Circuitry for ASICs, Ser. No. 08/985,790, filed on Dec. 5, 1997, both incorporated by reference herein.
A second embodiment of the invention utilizes a function block such as that shown in FIG. 12. The function block 1300 of FIG. 12 is similar to that of FIG. 11 with the following modifications. Two additional dual-control multiplexers 1332 and 1334 are added. The output of dual-control multiplexer 1260 is coupled to the first input of dual-control multiplexer 1332 while the second input of dual-control multiplexer 1332 is coupled to input TD on line 1336. The output of dual-control multiplexer 1332 is coupled to bit-storage unit 1270. Dual-control multiplexer 1334 has its first input coupled to the output of dual-control multiplexer 1280 and its second input coupled to the output of bit-storage unit 1270. The output of dual-control multiplexer 1334 is coupled to bit-storage unit 1288.
In addition in FIG. 12, select and enable logic additionally includes NOR gate 1344 and inverter 1342. NOR gate 1344 receives a CC signal on one input and a CR signal on a second input. CC and CR are also sometimes referred to herein as a column mode select signal and a row mode select signal, respectively. The output of NOR gate 1344 carries signal {overscore (C)} while the output of inverter 1342 carries signal C. Signals C and {overscore (C)} act as "program" indication signals as will be later discussed. {overscore (C)} is coupled to switch 1346 in multiplexer 1332 and switch 1350 in multiplexer 1334. Two additional signals are provided: TCLKLO and TCLKHI. TCLKLO is coupled to switch 1348 in multiplexer 1332 and TCLKHI is coupled to switch 1352 in multiplexer 1334. TQ is output from bit-storage unit 1288.
The function blocks 1200 and 1300 described with respect to FIGS. 11 and 12 can be configured to incorporate a variety of both combinational and sequential functionality simply by changing the signals coupled to the inputs. For instance, inputs can be coupled to a logical 1 (e.g., a "high" value, VCC, etc.), a logical 0 (e.g., a "low" value, gnd, etc.), an output from another function block 1200/1300, or an input into the integrated circuit itself.
In particular, a function block 1200/1300 can be configured to function as a latch or a flip-flop. For instance, to implement a flip-flop, the data input (D-input) of the flip-flop is applied to input DS 1262. The output Q 1302 from the function block is also the output (Q) of the flip-flop. A clock signal (CLK) is applied to inputs MC 1306 and SC 1318. An enable signal is applied to input EN 1312. A clear signal or a preset signal is applied to inputs AS 1314 and S2 1320. DA 1278 is connected to a logical low for a clear signal or to a logical high for a preset signal. SX 1297 is tied to a logical low. In this manner, a data bit input at DS will pass serially through bit storage unit 1270 and bit storage unit 1288, and the implementation acts as a master-slave configuration. Thus, when input data is input on line DS and switch 1261 closes (driven by CLK) then the input data will be stored in units 1270 and 1288. When switch 1261 opens, bit storage units 1270 and 1288 remain undisturbed and hold the last bit stored. A latch can be implemented in a similar manner, but only one bit storage unit needs to be utilized.
Referring now to FIGS. 13 and 13a, function blocks (such as 1200 or 1300) configured as two latches or as two flip-flops can be used to form a PLA core cell 1402. For discussion purposes only, these devices in the core cells will simply be referred to herein as latches, although it is to be understood that they could be flip-flops in various embodiments. The core cell 1402 includes latch 1404 and latch 1406. Each latch 1404, 1406 is coupled to mux 1408. The select line 1410 to mux 1408 is an input to the AND array. The mux output 1412 is input into multi-input AND gate 1414, whose output forms a product term. AND gate 1414 may be formed using a tree of AND gates as will be understood in the art. It is to be understood that, in addition to the latches, all of the logic shown in FIG. 13 can be implemented with function blocks, such as 1200 or 1300.
Each latch 1404, 1406 is programmed to store a value that dictates how the core cell 1402 will behave upon receiving an input signal on line 1410 into the PLA. Programming is done in accordance with Table 1:
Thus, when latch 1404 stores a logical 1 and latch 1406 stores a logical 0, the signal input on line 1410 will be output on line 1412. When latch 1404 stores a logical 0 and latch 1406 stores a logical 1, the signal input on line 1410 will be inverted on line 1412. When both latches 1404 and 1406 store a logical 1, it indicates a "don't care" condition—no matter what is input on line 1410, the product-term will not be affected. But if latches 1404 and 1406 both store a logical 0, the entire p-term will be disabled (a 0 input into an AND gate always results in a 0 output).
An alternative embodiment of a PLA core cell 1402 is shown in FIGS. 14 and 14a. In FIG. 14a, a single latch or flip-flop 1504 is coupled to an NAND gate 1506, where both the latch 1504 and 2-input NAND gate 1506 can be formed using function blocks, such as 1200 or 1300. The second input 1508 (or 1508′) to the 2-input NAND gate is formed from the input signal 1510 or its complement. When latch 1504 stores a logical 1, the output of NAND gate 1506 carries the inversion of the signal input on line 1508 (1508′). When the latch 1504 stores a logical 0, the input is a "don't care"—it will not effect the p-term.
A comparison of FIGS. 13 and 14 illustrates that in FIG. 14, while only one storage device 1504 is required two physical input lines 1508, 1508′ (one positive and one negative) must be run through the array while in FIG. 13 two storage devices are utilized, 1404 and 1406, but only one physical input line 1410 need be run through the array. Although both embodiments are useful, FIG. 13 has the advantage in deep-submicron semiconductor technology that the total wire-length has been cut in half. Although the fanout-dependent loading in FIG. 13 will be double that of FIG. 14, it is not fanout loading but absolute wire length that is the predominant factor in determining delays in today's semiconductor devices.
Nonetheless, both the embodiments illustrated in FIGS. 13 and 14 are advantageous over wired-OR structures. First, the structures of FIGS. 13 and 14 do not require a regular array structure. In fact, during implementation, portions of a particular array may be spread throughout a particular ASIC. Still, even if all portions of the PLA were located in proximity to one another, these portions can be scrambled—in other words, in its physical implementation, the array need not be regular and the structure may not match its conventional counterparts.
Further, wired-OR structures are notorious for static power consumption since anytime the product-term line is pulled low, current flows. But since the structures of FIGS. 13 and 14 use gates, static power consumption can be minimized.
A PLA using a structure such as those shown in FIGS. 13 and 14 is further advantageous. In addition to using a regular array structure, in all past attempts to include a PLA structure into a standard cell, a custom layout was required that had to be performed manually—a time-consuming, expensive, and burdensome task. But, in accordance with the invention, a PLA structure can be generated automatically for an MBA, a standard cell, or a gate array. Although each PLA is custom to each ASIC in terms of size, number of inputs, outputs, etc., a library can be used to implement each core cell. For instance, a library can store as a core cell the implementations shown in FIGS. 13, 14, or both. In this manner, a standard cell, a gate array, or an MBA that includes a PLA structure can be designed and implemented rapidly and cheaply (using the steps of FIG. 9).
Because of their ease of use and rapid production time, an MBA may be used by circuit designers in designing prototypes. Once a design has been finalized, however, a user may wish to optimize the circuit implemented by an MBA. Such optimization may take place using a "standard cell" or a "partial standard cell." As used herein, the term "standard cell" generally refers to ASICs having a higher degree of customizability than an MBA, even if such ASIC is not completely customizable, usually having a substantial number of masks that are customized for an individual design. For instance, compared to the MBA, transistor size and placement within the function blocks may be altered and/or unused transistors may be eliminated. Routing may also be optimized for the particular application. Thus, in some embodiments of the invention a circuit first implemented in an MBA may be converted to one implemented in a standard cell. Still in many embodiments, the PLA in a standard cell retains user programmability and uses a programming structure similar to that of the MBA (e.g., FIGS. 13a or 14 a).
Programming (Loading the Programming Pattern)
In order to program and/or reprogram a PLA embedded in a one-time configurable ASIC in accordance with the present invention, several alternatives exist. In one embodiment, a JTAG (or similar) controller can be used as will be understood in the art to shift a programming pattern through a test scan path.
A second embodiment uses an array structure with function blocks such as those of FIG. 12 where the function blocks 1300 used to form the PLA are configured as flip-flops that are "daisy-chained" together and can be programmed using external pins. An example is shown in FIG. 15. Specifically, in an array 1710 of function blocks 1300 where the function blocks are configured to behave as flip-flops, the flip-flops in each column 1720 i of array 1710 are "daisy-chained" together. For example, in Column 1 1720 1 the TQ output of flip-flop 1701 10 is coupled to the TD input of flip-flop 1701 11. The daisy-chain continues to the bottom of the column 1720 1. Likewise, the flip-flops of Column 0 1720 0 would be similarly daisy-chained.
Referring back to FIG. 12 in operation when {overscore (C)} is a logical low signal C is a logical high), the function block is in a "program" mode of operation. When in a program mode of operation ({overscore (C)} is a logical low), TCLK, distributed through the signals TCLKLO and TCLKHI, permits the shift of data from the data input on line TD through bit-storage units 1270 and 1288 and out through TQ. In one embodiment of the invention TCLKLO and TCLKHI are inverse signals to one another, being derived from the same clock TCLK (i.e., when TCLKLO is high, TCLKHI is low and vice versa), and both TCLKLO and TCLKHI only distribute TCLK when the array is in a program mode of operation, otherwise leaving switches 1348 and 1352 open. (In one embodiment of the invention, these signals may also be used in testing of the MBA as described in the application entitled "Test Circuitry for ASICs" mentioned previously).
Now referring again to FIG. 15, FIG. 15 illustrates several of the function blocks 1300 ij configured as flip-flops with the TQ/TD lines daisy-chained. Note that NOR gate 1344 and inverter 1342 are shown in FIG. 14 simply as OR gate 1344′ having one input coupled to CR and one input coupled to CC.
To load the flip-flops and thus program the PLA, all rows and columns are first selected to be in a program mode by applying logical high values to all of the CR lines 1716 j and/or all of the CC lines 1712 i. PLA program values are placed in a shift register 1702, where the output of each stage 1704 i of the shift register 1702 is coupled to the TD input of the first flip-flop 1701 i0 in each column, in one embodiment of the invention. Applying TCLK 1734, PLA program values are applied one at a time, from shift register stages 1704 i to the respective daisy-chains where they are simultaneously shifted through each column 1720 i via the daisy-chains. When all values have been shifted to the appropriate flip-flops, CC and CR are de-asserted.
In many embodiments of the invention, it will be desirable to have the ability to load a default programming pattern into the "programming memory" (e.g., latches or flip-flops) of the PLA. Such a default pattern would be written into the programming memory by a signal that is, for instance, related to the system power-on-reset or similar signal, setting all programming memory elements to a predetermined value.
For instance, shown in FIG. 16 is an embodiment of the invention that utilizes the core cell of FIG. 13. The D inputs on the latches are tied to VDD (logical 1) or VSS (logical 0) to set them to the desired initial condition. These default values would be built into the PLA during the construction of the ASIC (FIG. 9). This default programming pattern would be loaded using a signal like a power-on-reset pulse (!POR) 1802.
In another embodiment, such as implementing a PLA in a standard cell, or even loading the PLA dynamically during the operation, the loading mechanism will be able to choose between a default pattern (if one is used) and a new pattern used for reprogramming. In such a case, the circuit of FIG. 17 can be utilized. As shown, the inputs to latches 1404 and 1406 are coupled to respective muxs 1902 and 1904. One input of each mux 1902, 1904 is connected to a default value, such as VDD or VSS. The second input is coupled to an external data line 1906, 1908, which can come from I/O pads, from RAM, or from another source. The select line 1910 of the muxs selects between whether the default values or other external values will be loaded. A load pulse is provided through OR gate 1912, which receives power-on-reset as one input and a write pulse as a second input.
The embodiment shown in FIG. 17 can be useful not only for dynamic loading of a program pattern during operation but also for loading programming values into only a portion of the PLA instead of the entire array.
It should be understood that the particular embodiments described above are only illustrative of the principles of the present invention, and various modifications could be made by those skilled in the art without departing from the scope and spirit of the invention. Thus, the scope of the present invention is limited only by the claims that follow.
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|U.S. Classification
|International Classification
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|8 Jun 2001
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The University System of Georgia has put the brakes on a controversial revision of its core curriculum framework, a set of courses that students are required to take before getting a college degree.
Critics had complained the revision could leave students without the broad education teachers say should be part of a college education, and could even lead to job cuts.
An announcement from Susan Herbst, USG chief academic officer and executive vice chancellor, said she and Chancellor Erroll Davis decided to stop the curriculum revision process until later this year.
Davis had appointed a group last year to overhaul the system's core course requirements. The revisions would help Georgia college graduates better compete in a global economy, he said.
"The attempt to revise our core is clearly controversial," Herbst wrote in a letter that went out to all faculty in the state's 35 public colleges and universities Monday. "Given the nature of much of the dialogue, and in order to be responsive to the concerns many of you have expressed about process and involvement, I believe that it is appropriate to take some time out to ponder our options and consider all opinions in a systematic fashion."
The planning break comes after more than 400 professors from across the state signed a petition opposing the proposed curriculum revision.
Critics said the changed curriculum might produce students who would graduate with less knowledge of American history and culture, with little understanding of globalization. Anticipated changes also could make it harder for students to transfer between schools in the system, according to the petition.
George Rainbolt, who helped start the petition opposing the curriculum revision, hailed the decision to step back.
"I think it's a wise decision," said Rainbolt, chairman of Georgia State University's philosophy department.
Rainbolt said pressure from a diverse array of professors and administrators probably is what convinced University System of Georgia administrators to stop the curriculum revision.
Objections came from small and large colleges, from professors in sciences as well as professors in humanities, he said.
William Vencill, a University of Georgia professor who was a member of the committee Davis appointed to begin the curriculum revision, agreed that taking a break is a good decision.
"There was more than enough confusion to go around. It's a wise decision," Vencill said.
But Vencill hopes the university system's decision won't confuse people on the UGA campus, where Vencill and others recently finished work on UGA's own core curriculum revision.
Called the "general education curriculum" instead of a core curriculum, the UGA changes are scheduled to go into effect this fall.
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Written on: 20/07/2012 by whybewhy (9 reviews written)
Slimming World does work if you stick at it. I've lost about 1 1/2 stone over the past 9 months or so and therefore I guess I have to recommend it.
I think it sometimes frustrates my BF that I'm always pulling the book out to check certain foods and that I have to effectively decide what I'm going to eat at the start of the day (or at least not eat certain food types - which does cut down spontaneity), but he loves the results and so do I ;)