text:
|Numéro de publication
|Type de publication
|Numéro de demande
|Numéro PCT
|Date de publication
|26 mars 2002
|Date de dépôt
|28 mai 1997
|Date de priorité
|30 mai 1996
|État de paiement des frais
|Autre référence de publication
|Numéro de publication
|Antonio Esposito, Rosario Esposito
|Cessionnaire d'origine
|Biprocessor S.R.L.
|Exporter la citation
|BiBTeX, EndNote, RefMan
|Citations de brevets (4), Référencé par (42), Classifications (12), Événements juridiques (6)
|Liens externes: USPTO, Cession USPTO, Espacenet
This invention relates to a general purpose electronic numeric parallel computer with multiple processors. MIMD (Multiple Instruction stream Multiple Data stream) in the Flynn's classification model, latency reduction oriented, and relates also to its composing processors.
Replication or regularly interconnected and co-operating processing elements or nodes can improve performances, reliability and costs of computers.
MIMD with multiple processors, also called MULTI, consists of a collection of processors that, through an interconnection structure, either share a global memory or only communicate without memory sharing. The formers are also called multiprocessors, the latter multicomputers.
Beyond advantages, current MULTI still have inconveniences and disadvantages.
To communicate among parallel processes, multiprocessors adopt the same processor-memory communication mechanism, which results flexible and suitable for whatever computation, but the shared memory becomes a "bottleneck" as the number of approaching processors increases.
The complexity and the costs of multi-ported memory can be bounded only at the expense of increased memory latency, or reducing memory traffic by using local cache memories, which add further complexity and costs to manage their coherency protocols.
Within multicomputers each processor has a private memory that allows less latency and more scalability, but existing communication mechanisms do nor allow efficient communication among parallel processes. The communication of a message requires an input/output operation. Even associating a message to a high priority interrupt, its average latency remains greater than the one of the access to the shared memory.
The used interconnection structures determine the topology, the node or connection degree, and several performance characteristics of MULTI. Any direct connection among nodes also requires a node interface. Since the node decree increases with the growing of the number nodes, the interconnection costs rapidly prevail on the machine costs. According to current technologies, the node degree must be held necessarily low, even if this increases the probability of congestion and conflicts, makes the communication latency inconstant, and performances result dependent on the space-time distribution of the traffic and on the application itself. In order to have flexible and accessible networks at acceptable costs, optimal topologies are used as well as switching and message combining elements, buffers, routing and flow control techniques, all of which make the current interconnection structures hard to manufacture, and still too expensive and inefficient by the performance point of view.
The degree of parallelism matches the number of processors, but the total computing power also depends upon the power of the single processors. Actual realisations have constraints by which these two power factors are not independent. The parallel processes communicate on globally shared resources with limited capacity and this generates congestions and/or access conflicts which degrade the expected performances either with the growing of the processor number and with the growing of the single processor power.
Within MULTI the difficulty to synchronise the parallel processes strongly reduces the number of applications that can take advantage of a parallel execution. Problems do not reside in distributing a common iso-frequential timing signal to all processors, as it is ordinarily done within SIMD too, but mainly in the impossibility to predict the exact execution time of a process. Each processor has its own autonomous sequence control, and as time passes, parallel processes become timely unrelated one another, in a way that they are not controllable by the programmer.
Synchronisation is achieved indirectly through communication. Current methods are based on message passing in the multicomputers and on access control to memory shared variables within multiprocessors. These operations, performed mostly at software level with many instructions of the ordinary repertoire and few specialised instructions (test & set, fetch & add, etc.), still result too slow, penalising, the communication time. Moreover they generate messages that increase the traffic congestion. Therefore most of MULTI built so far are unsuitable for synchronising a large number of small processes, and for strongly reducing the execution time (latency) of a single task.
Within MULTI it also exists the load balancing problem that aims to optimise use of resources by uniformly distributing the load among processors. Migration, or movement of allocation to resources after the initial decision, has been taken into account as a solution to the dynamic load balancing problem, though it has been noticed its validity also for reducing the network load, making the communication partners closer. With multicomputers the process migration is more burdened because it also requires to copy memory, therefore the migration of simpler entities is used. Convenience of run-time migration is doubtful because the transferring overload is hardly balanced by performance increments, therefore process migration from processor to processor is seldom used in highly parallel computers.
MULTI usually employ normal microprocessors available on the market and also used in SISD machine. Otherwise, they employ dedicated processors with special mechanisms for fast interrupt handling, fast context switching, with several register banks or windows, or they integrate communication/routing message interfaces and units. However the used processors are equipped with full and autonomous fetch/execution capability, and configured as memory bus masters, that once activated continuously fetch and execute instructions, but normally do not allow accessing to their own internal registers from outside, except for debug purposes. Computing nodes in multicomputers are usually multiprocessors with an application processor and one or more communication and switching routine processors, to overlap communication time with processing time, even if that increases the parallelism cost.
Aim of the invention is to find an optimal combination of processor replication and inter-connection, as well as modalities of process execution and co-operation, and to devise the appropriate structural and functional processor modifications, in a way to achieve a parallel processor or MULTI, without said inconveniences, having an optimised and very performing interconnection structure to allow an efficient communication and synchronisation among parallel processes, to reduce easily single task execution and completion time (latency). The posed technical problem is big and hard one because of the high number of possible choices at both the physical and the logical level, concerning several aspects of parallelism, investigated for long time but difficult to understand and to resolve.
The proposed solution, as per claim 1, consists in the direct pairing between processors of separate memory buses, in way that two tightly coupled processors can reciprocally synchronise themselves and share the internal register files, for allowing an easy communication and synchronisation between the two adjacent parallel processes of the pair, and in adopting the process migration among redundantly replicated processors on the same memory bus, to allow each process to communicate/synchronise itself with several adjacent parallel processes.
The pairing is accomplished through mutual extension of internal buses from one processor to the functional units of the other one. So the single processor also becomes a pair communication unit, normally connected to memory and peripherals, but mainly connected to another processor. More processors are connected on the same memory bus, for accessing equally rather than concurrently to the same instructions and data in the shared memory. Each memory bus is managed as a single master bus, wherein processors co-operate to the execution of a single sequential migrating process. Beyond the memory bus, processors also share a process migration structure that allows to transfer process control and "context" contained within state registers, from one processor to another one of the bus. Thus the run-time process migration among processors is achieved easily preserving identity and continuity of each process.
Processors are modified to eliminate concurrent access conflicts to the shared memory. They are formed to be, on the memory bus, either master-active like a traditional processor, either slave-inactive like a peripheral which does not perform processing activity, but that allows accessing and loading of its internal registers by the outside. A slave processor remains inactive for an indefinite period of time, awaiting to receive control and to resume processing activity starting upon received context. Processors of the same bus are individually paired with a processor belonging to a separate memory bus so as to form pairs between distinct memory buses.
The outcome processor architecture offers new instructions in two categories:
migration or intra-bus communication instructions, for handling the (sequential) interaction among processors on the same memory bus and allowing the run-time process migration;
pair communication or inter-bus communication instructions, for handling the (parallel) interaction within the pair, and allowing communication and synchronisation among parallel processes.
The parallelism comes out of the plurality of processes which simultaneously run on as many memory buses, and migrate on their own bus among paired processors to communicate/interact and synchronise themselves.
A multicomputer/multiprocessor formed in accordance with the invention has many advantages.
Congestions and access conflicts to global shared resources, which become "bottlenecks" as parallelism increases, are substantially eliminated.
Parallel processes communicate through high performance local dedicated buses, which do not require interface controllers and input/output operations. The communication among processors is based on local registers sharing, normally and efficiently achieved by hardware, and easily controlled by special pair communication and process migration instructions.
The dual access to the processor registers by both of the units of a pair allows a variable time interaction among parallel adjacent processes, and also to program the synchronisation points. Processors have direct access to the sequence control of the adjacent processors, and this allows the programmer to control mutual proceedings and time relations among all adjacent processes in parallel. Communication time between adjacent processes is mainly influenced by the process migration operation that requires a definite constant time. Therefore, also owing to the lack of conflicts/congestions, communication latency among adjacent processes is constant and can be on average lower than that in a multiprocessor. Additional devices to mask communication latency or to overlap communication and computation times, are no longer needed. Synchronisation is possible without global traffic generation and even without explicit communication. It is possible to program synchronising barriers and to achieve, within the short execution time of some new specialised instructions, the explicit synchronisation of many small processes with dimensions of few instructions, preserving also the asynchronous and efficient process execution and the other implicit synchronisation modalities. Thanks to these capabilities they can efficiently execute parallel and even synchronous algorithms. The interconnection structure, composed by inexpensive, low latency, wide bandwidth buses of ordinary make, results optimised in complexity, costs and performances. It does not force topology and machine connection degree, on the contrary it allows to obtain different topologies with a high connection degree, without the need of switching or buffering components. Within regular machines, the connection degree is given by the number of processors per bus, that is only limited by physical parameters which constrain the bus and processor dimensions, but bus bandwidth no more constitutes the main obstacle to the numeric growth of processors attachable to it.
The degree of parallelism matches the number of memory buses, and it can be freely increased, with a proportional increase of the total power, independently of the single processor power. The reducible dimensions of the pairing connections and the opportunities offered by the microelectronic (VLSI) technology allow to design and build a single logical biprocessor unit, whose integration leads to further advantages in terms of modularity, resource sharing and different part numbers.
In summary, the invention maintains about all of the advantages, but fixes most of the disadvantages, of current MULTI in both categories, with low, medium and high degree of parallelism.
The achieved process migration constitutes a "context/process switching" wherein more processors share the single process that controls the switching. There is no formatted data packet, and no maximum time interval exists within which a processor will surely lose or receive control.
No computer has ever adopted a processor relay executing for a single sequential process. The expensive functional inefficiency given by the redundancy of inactive processors is only justifiable by the rake-off gained with parallelism. On each memory bus the situation is only structurally similar to that of shared bus multiprocessors, but functionally very different. Besides the pair connections, in the invention the processors are neither standard nor all simultaneously active-masters, and they do not compete for resources and do not engage conflicts in a casual and asynchronous way. Migrations take place tidily under software control.
Further characteristics of the invention will result by the following description, accompanied with the attached drawings, relative to no restrictive examples of topologies and realisations, depicted in the following list of figures, wherein any drawn connection line represents one or more buses, and the shown direction is the prevailing one, but it does not exclude bidirectionality or the existence of connections with opposite direction.
FIG. 1 shows a partial block scheme of a computer made according to the invention, in a regular "matrix" topology, reporting memory modules M, memory buses C-BUS, processors SPU, pair interconnection structures P-P, migration structures A-S, and biprocessors DPU.
FIG. 2 shows the smallest possible configuration of multicomputer according to the invention, capable to execute in parallel only two processes that cannot migrate.
FIG. 3 shows a regular "linear chain" topology, connectable at the ends as a ring, in which are also reported dual port memories or communication memories (2-fifo) DPM, connectable like biprocessors between bus C-BUS pairs.
FIGS. 4, 5, 6 show other processing nets R-P with regular topology, of multicomputers fulfilled according to the invention, wherein it has been left out the distinction of the structures A-S and P-P and the representation of the others processing units (M,IU,DPM), which are supposed to be connected, on each bus C-BUS, according to the already described criterion and depicted by FIGS. 1, 2 and 3.
FIG. 7 shows the main external connections, shared A-S, C-BUS, and private P-P, of a processor SPU pair forming a biprocessor DPU.
FIG. 8 shows the simplified block diagram of the main functional units of both the two processors SPU of a pair, fulfilled and connected in accordance with the invention.
FIG. 9 shows a block scheme of the migration structure A-S of a single bus C-BUS, comprising processor selection means P-SEL, a migration bus MIG-B, and interconnection structure interfaces S and A distributed in the pair processors SPU.
FIG. 10 shows the existence of address decoders ADEC within the selection means P-SEL of the biprocessors DPU on one same bus C-BUS.
FIG. 11 shows with greater detail the internal connections of the interfaces A and S of the migration structure A-S, and presence of arbitrating means A-R between the access control ports MC, SC to processor register file REG-F.
FIG. 12 shows a possible circuit switching means M-X interposed on some internal pair buses, in accordance with the invention.
FIG. 13 shows said switching means M-X, composed of circuit switching elements IXI of 2×2 type, arranged according to the invention, and details of data connections between registers REG-F and execution units EX-U comprising arithmetic and logic unit ALU.
FIG. 14 shows the connection asset among the functional units of the two SPU processors in pair, when said switching means M-X are "cross switched".
FIG. 15 shows a scheme of the command and synchronisation circuit XAND of the switching blocks IXI composing said switching means M-X.
FIG. 16 shows the biprocessor DPU containing only one timing circuitry TGEN-U for both processors SPU of the pair.
The main memory M is distributed among the buses C-BUS, each one with its separate address space, giving rise to multiple private address spaces. On the single bus C-BUS, the memory M, optionally modular and hierarchical (caching) L1/2, is shared by the attached processors SPU and locally accessible in a single shared address space.
The whole interconnection structure is partitioned into several different structures: local shared structures, A-S and C-BUS, allowing process migration; private structure P-P allowing communication and synchronisation of parallel processes. Each processor SPU is connected only to one memory bus C-BUS, to one migration structure A-S, and to one pair interconnection P-P.
Input/output controllers IU can be connected to each bus C-BUS and/or directly to each memory module M, in the usual ways.
In each memory bus C-BUS only one migrant process takes place at once, and only one processor SPU per bus C-BUS is active-master at any instant, while all others are inactive-slave, awaiting to take part in the processing activity. This one-master-many-slaves situation is initially forced by reset. To recognise the different initial condition, the processor SPU reset receiving unit RST has one more input signal M/S strapped to a different logic value for the master unit compared to slave ones. An active-master processor SPU behaves on its bus C-BUS like a traditional central unit (CPU), processing, with complete control of connected resources, instructions and data contained in the local memory M of the bus C-BUS. All the modalities already contemplated in a CPU, among which in particular the hold disconnected state reached by the active unit following and during a Direct Memory Access (DMA), belong to the active-master operating mode. Within an inactive-slave processor SPU the instruction fetch-execution activity is suspended but ready to restart. Its registers are accessible from the external bus C-BUS. An inactive-slave processor can receive from the active-master one the context data, and, upon request, resume processing activity starting on received context. The inactive-slave operating mode includes all those modalities already contemplated in a peripheral or in a coprocessor when they do not access the memory. No processor SPU autonomously exits the inactive-slave state unless it is explicitly required to do so by the master processor through the migration structure A-S or by reset. The program running on a bus decides to which processor of the same bus to transfer its process by executing process migration instructions that control the block transferring of the state registers content from the active processor into the corresponding registers of the destination inactive-slave one, and also synchronise control transferring between the sender and the receiver. Migration wakes up the receiving processor as master and sends to sleep the sender as inactive-slave.
Under program control, the processors sharing the same memory bus transfer among themselves the context and control of the running process, and in turn become active-master of the bus C-BUS, in such a way to continue the migrant process without jumps or losses of instructions.
Two processors SPU of a pair DPU are almost independent form each other, and when the one is inactive-slave, the other one can continue processing. Two parallel processes are "adjacent" if they can directly interact within a pair through a pair interconnection P-P. To interact, any two adjacent processes must migrate on their bus C-BUS to the processor SPU which puts them in communication. When both reside in the same pair DPU, they can communicate and synchronise themselves by using said pair communication instructions.
The network of all processors SPU interconnected by memory buses C-BUS, by migration A-S and pair interconnection P-P structures, forms a single processing organ R-P, or parallel processor, able to process simultaneously an independent instruction and data stream on each memory bus C-BUS, and capable to synchronise the parallel processes by executing dedicated instructions opportunely programmed within the processes themselves.
The invention can be carried out in several processor realisation modes, general purpose CISC or modern RISC for executing sequential programs. To illustrate the characteristics of the invented pair processor SPU, in the following we will consider a simple but not restrictive processor representation scheme, comprising usual functional units, normally interconnected and operating among which at least:
a bus unit BU, for interfacing the processor to the memory bus C-BUS and to the other external structures, and for assuring physical compatibility and signal driving on the bus, receiving from the internal executive units EX-U, under the control unit DECO-U control, data and addresses of the memory locations to access, and able to control the external bus cycles and data transferring to/from the outside and the internal registers, and able to transfer to the decode and control unit DECO-U the criterions concerning interrupts, exception conditions, arbitration etc., and the instructions coming from the memory;
a set of executive units EX-U, all connected and controlled by the decode and control unit DECO-U, and connected to said bus unit BU by data buses DATA-MB and someone also by address buses ADDR, for executing as usual, at least the arithmetic and logic operations, the memory data loading and storing operations, the address generation and branch operations or also the floating point ones, etc., and sending the computed addresses and data to the resisters REG-F or to the bus unit BU, and the conditions/exceptions to the control unit DECO-U;
a bank of general and special purpose registers REG-F, for containing the processor state or context, with a set of data ports MD normally connected by data multi bus DATA-MB to said executive units EX-U and to the bus unit BU, and controlled by at least one control port MC connected with a control bus REGS-B to the control unit DECO-U;
a decode and control unit DECO-U, asking/receiving, via an input instruction bus IST-B a single sequential instruction stream, and decoding and controlling the instruction executions and sending the immediate data to the executive units B-U, and controlling the data flow to/from the registers bank REG-F and also coordinating the other functional units.
The processor SPU can also comprise registers which do not belong to the state, optional buffers, data and instructions caches, and optional prefetch and branch prediction units, memory management units (MMU,TLB), interconnected and operating in the usual ways. The registers bank REG-F usually has two output and one input data ports, but it can also have a greater or lower number of data ports. The bank Program Counter register can be directly connected even to the prefetch unit. The bus unit BU comprises at least the bus transferring control unit BC and the external bus C-BUS drivers. Usually it also includes other units as bus C-BUS arbitrating units, interrupts reception/control unit, external/internal cache control units, etc.
According to the invention, the bus unit BU is designed to be either master or slave of the memory bus C-BUS. It includes means for interfacing the migration structure A-S to the processor internal registers REG-F and control unit. It is connected internally by a selection/control bus LDR-B to the near resister bank REG-F for context registers REG-F loading from the outside, and it is connected to the control unit DECO-U by a further control transferring bus R/R-B for signalling the release/resume of processing activity. The bus unit BU sets itself to master or slave according to the active or inactive state of its control unit DECO-U. In slave mode, beyond the external access/loading of internal registers REG-F, upon receiving of a control migration criterion from the migration structure A-S, it allows to wake up the decode and control unit through the control transferring bus R/R-B.
The control unit DECO-U suspends any host processor activity and sets the connected bus unit BU in slave mode, upon receiving the special slave reset signal RESET-P by the receiving reset unit RST. In the inactive-slave state the decode unit DECO-U does not process instructions, but allows access to the register by the outside bus C-BUS and by the pair unit. The inactive control unit DECO-U can restart only if it receives the wake up criterion by the control transferring bus R/R-B, or the special master reset signal RESET-A by the reset receiving unit RST. In the first case it assumes the registers REG-F current content as the transferred process context, and resumes processing starting on such state. In the second case, it initialises the registers REG-F and the other processor functional units and resumes processing on a defined state.
To allow synchronisation of instruction pairing, the decode and control unit DECO-U of each pair processor SPU is directly and reciprocally connected to the other decode/control pair unit by several control/synchronism signals SINC-B. To synchronise the two parallel processes, the decode/control unit DECO-U, is also connected with a further selection/control bus XREG-B to the registers bank REG-F of the pair unit, in a way that it can access them concurrently with that, and it can control the transferring to/from its own executive units EX-U and its own registers REG-F. To co-operate for process migration, the decode and control unit DECO-U is also conceived to remain inactive without processing instructions, signalling its state through at least one signal IDLE to the functional units of any other processor, and holding them in a suspended state.
To allow independent access by both pair units, the register bank REG-F is a dual access one, having a further and dual data SD and control SC ports sets, connected with the pair processor, former to the executive EX-U and bus BU units and latter to the control unit DECO-U. Arbitrating means A-R are located between the dual control ports, MC and SC, of each register bank, for resolving concurrent access conflicts to the same register.
The processing activity inside the active-master processor SPU takes place normally.
The instructions fetched from the program memory M of the external bus C-BUS flow inside the processor through the interface unit BU and optional caches and buffers until they arrive via an instruction bus IST-B to the decode unit DECO-U input. Thanks to said exchanged synchronism signals SINC-B their execution can be synchronised in unison with the instruction stream in the pair unit. The external data stream flows in across the bus unit BU and via the data multi bus DATA-MB to/from the executive units EX-U and the registers banks REG-F of both pair processors. The executive units EX-U can dialogue via said data multi bus DATA-MB with both registers banks REG-F. The control unit DECO-U controls only the executive units EX-U located within the same host processor SPU, and manages as executing process context the resisters REG-F connected with the own resister control bus REGS-B.
Upon execution of pair communication instructions it accesses to the pair unit resisters REG-F by the pair register control bus XREG-B, and controls their transferring via data bus DATA-MB to/from its own executive EX-U and/or bus BU units.
Upon execution of migration instructions, the decode/control unit DECO-U sets up the addressing to select on the external bus C-BUS the processor SPU identified by the instruction operand, and either control the block transferring of the own context register bank REG-F to the destination processor, or it issues on the control transferring bus R/R-B a control release criterion to start a control migration cycle, at the end of which it turns itself inactive slave.
The most seemly way to transfer a process still consists in using the shared bus C-BUS and in connecting to it processors selection means P-SEL, built in the usual way to allow a normal CPU to select memory components or peripherals. The selection means P-SEL, shared with the bus C-BUS, reduce the communication by diffusion to a point-co-point dialogue between the active unit and the selected one only. Driving the address and the control buses of the out shared bus C-BUS, master processor can select any one else, including itself.
A process context, or the set of state variables that allows process suspension, transferring and resuming with continuity, is entirely contained within state registers REG-F of the processor that executes it. This context can be transmitted on the shared C-BUS data bus DATA-B. The selected inactive slave processor receives such context directly in its state registers REG-F, or in other interface BU register file transferable to state registers REG-F at the wake-up time.
The bus unit BU includes a registers selection/control unit S, connected to the external bus C-BUS drivers,/receivers and also, via a selection/control bus LDR-B, to the register bank REG-F. When the bus unit BU is in the inactive-slave mode, said selection unit S detects the input selection signal SELT coming from said external means P-SEL, and connects the bus C-BUS receivers to input also the external address ADRS-B and control CNTL-B buses, and controls the registers REG-F selection and loading by the data buses.
To allow block transferring of the state register file and speed-up the process context migration, the processor accessible registers are consecutively allocated in a unique address space segment. Moreover single instructions are conceived for transferring the whole context. On the shared bus C-BUS each processor SPU takes a different memory address space segment (memory mapped) or, by the right presetting of the migration instructions of the SPU processor and signals of the control bus CNTL-B, within an address space reserved for peripherals (I/O mapped) or for processors (Processor mapped) only.
The control migration can be associated to a particular context variable, for example one bit of the Status Register SR. To achieve greater flexibility and availability it is preferable to transmit separately the control migration message on a special structure. To this aim, the migration structure A-S comprises communication means devoted to the explicit control transferring. Such means can be implemented in several ways, but a suitable one for modularity is that they be of decentralised type, composed of a plurality of identical control communication cells A, singularly distributed within each bus processor SPU interface BU, and connected by the input signal SELT to the aforesaid selection means P-SEL and via control transferring bus R/R-B to the host control unit DECO-U,, and all interconnected by a shared devoted migration bus MIG-B for exchanging among themselves, under the bus migrant process control, criterions or messages concerning control migration, and each able to communicate with its control unit DECO-U during the control releasing/acquiring phases.
It is also preferable to build said migration bus MIG-B with bidirectional level signals, comprising at least:
one signal to send/receive the control migration criterion;
one opposite signal to receive/send the grant/acknowledge criterion as reply to such control migration criterion,
one optional signal to assert or recognise the possession of the shared bus and resources, constantly asserted by the active-master;
by which said communication cells A interact one another with the usual hardware handshake request-acknowledge protocol.
Upon execution of one control migration instruction SIDE.<dest>, the decode/control unit DECO-U sets the addressing to select on the external bus C-BUS the processor SPU identified by the instruction operand <dest>, and it issues on the control transferring bus R/R-B a release criterion to its cell A, that in turn sends on the migration bus MIG-B the migration criterion, then the decode unit DECO-U controls the defined release cycle, at the end of which it arranges with a signal IDLE the bus unit BU in the slave mode and the cell A in receiving, and releases the shared bus C-BUS control to the newly selected processor, suspending indefinitely its own process activity awaiting to be waked up.
On the opposite, the cell A of the selected unit connects itself in receiving, and on the arrival of the control migration criterion from the migration bus MIG-B, sends through a control transferring bus R/R-B the wake-up criterion. The waked-up control unit DECO-U restores the internal state according to the current content of the context register REG-F, eventually adjusts the Program Counter register and, upon the external bus C-BUS releasing, arranges the interface unit BU in master mode and the cell A in transmitting, and takes up again the process
The register bank REG-F includes at least one special register for dynamically containing the current executing instruction address. Such register can be the Program Counter, provided that it is not incremented at fetch time, but at the end of the instruction of which it holds the address. Its content is transferred to the other requesting pair unit wherein it is compared for the wanted address to identify the corresponding instruction and to recognise the synchronism condition. "Process explicit synchronisation" instructions are conceived which, within the operands, refer to said special or Program Counter register of the pair unit, and specify exactly one instruction instance of the adjacent process, through the (relocatable) memory M address taken on the instance.
Upon execution of one such instruction, the control unit DECO-U accesses with said pair selection/control bus XREG-B to said modified Program Counter register in the pair unit, and controls the register content transferring via data bus DATA-MB in one its own executive unit, wherein it does a comparison check between the captured address and the address specified within the instruction operand itself. If equality is satisfied the instruction terminates, otherwise the program counter register of the executing unit is updated (not incremented) so that the same instruction is soon executed again on next cycle, or it stalls. This instruction finishes to repeat itself or to stall, only when its execution occurs in parallel with the given address instruction in the pair unit. The wasted time (busy waiting) for repeating executions represents the syrchronisation cost, which can be optimised (with task switching) by the Operating System.
The invention allows also "process implicit synchronisation" instructions that work in a similar way, but they specify within the operand a generic wait condition on the value of one of the pair unit registers. Again, the execution of one such instruction is repeated indefinitely until the selected register does not satisfy the required condition. Process synchronisation instructions can be used either unilaterally by only one of the parallel adjacent processes, or bilaterally by both, and reciprocally refer to one another with the one's address in the other one's operand, to form a synchronising barrier. They can also cause stalls and deadlocks.
Inside a processors pair DPU, the two instruction streams are independent, but they can also be paired in unison as well as proceed with different synchronism asset. In isochronous mode the two paired processors proceed tuned in. In the asynchronous mode the one is disconnected with synchronisms SINC-B coming from the other one, like when the partner unit is inactive.
It is possible to modify the synchronism relationship in a pair using special instructions. Upon execution of a "pair synchronism setting" instruction SINC <modo>, the control unit DECO-U sets itself and the processor in the "mode" required by the instruction operand, respect to the exchanged synchronism signals SINC-B, and eventually records the operand value in the assigned field of the status register SR.
All new instructions are combined with the usual operand addressing modes. Several instruction versions are possible by subdivision or aggregation of instructions in the same category. For instance, it is possible to combine the Program Counter and/or the Status Register SR transferring with a control migration instruction rather then a context migration instruction, or to have a single instruction implementing a control and context migration atomic action.
The use of selection means P-SEL presumes a logic scheme of processor addressing, achievable in several ways. The simplest scheme consists in assigning to each processor SPU, unequivocally among those attached on the same bus C-BUS, a Processor Identification Number or NIP, usable also as operand in the migration instructions. Since to address the process migration correspond to route the communication among parallel processes, to avoid indirect address handling at any computing level, it is necessary to identify the most suitable logic scheme of processor addressing. So in the invention the memory buses C-BUS also are logically and unequivocally numbered with a Bus Identification Number or NIB. The assignment is accomplished in a way that each processor has a NIP corresponding to the NIB of its pair processor bus, and no processor has a NIP corresponding to its own bus NIB. With this scheme, by addressing a processor, a migrant process directly address itself to the corresponding adjacent process bus. On the several buses C-BUS the addressing schemes are similar but never equal. Relationship among NIP and NIB characterises the scheme on each bus as well as the configuration and/or the content of the address decode units ADEC of said selection means P-SEL.
The processor pairing allows also internal optimisations by sharing functional units within the pair. For example the biprocessor DPU may include only one internal time generation unit TGEN-U for both processors of the pair.
The decode and control unit DECO-U is also connected reciprocally to the pair control unit, at least through one signal IDLE, to communicate the operating state active-master or inactive-slave with respect to its own migrant process, which is eventually reported in a field of the Status Register SR, so that the one can know the activity state of the other one. In considering the biprocessor DPU as a communication unit between a bus pair C-BUS, one soon sees the advantage to integrate within it a dualport or communication memory DPM (or 2-FIFO), and also a pair of interrupt communication units. The interrupt structures relevant to each bus C-BUS can be interconnected in pairs with local private structures, following the processors pairing scheme. An interrupt communication unit, working and accessible as any generic interrupting device, is normally connected to the interrupt structure of the one bus C-BUS, but characteristically connected with point-to-point buses to a corresponding identical unit belonging to the interrupt structure of the bus C-BUS of the other one, so as to transfer interrupt messages between the paired bus C-BUS. One such interrupt communication unit can be integrated within the pair processor SPU, by connecting it internally with a complete data-address-control bus to the respective bus unit BU, or to the memory management unit (MMU) if any, and making it accessible by the external C-BUS.
According to the invention, the bus C-BUS private memories M, even with physically disjoint address spaces, can also be shared by all parallel adjacent processes in no concurrent way. To this purpose it is enough that the two processors SPU of a pair exchange reciprocally the fetched instruction stream and the accompanying context. To this aim some buses of both processors of the pair can be made dynamic by introducing circuit switching means M-X for reconfiguring the pairing asset. Upon synchronised execution of dedicated switching instructions XEX on both pair units, such means M-X may switch in a way that instantaneously each unit could receive instructions fetched by the other one and could see as own context the pair unit register bank REG-F. There are several ways to insert switching elements within the pair structure P-P, if one includes also the data multi bus DATA-MB, but it is better to switch the lower number of buses. In accordance with the invention, switching elements M-X are interposed only on the bus pairs REGS-B. XREG-B connecting each decode and control unit DECO-U to both register banks REG-F, and on the two buses IST-B allowing the instruction flow input to the decode units DECO-U. The switching elements need only two switching states or functions: "straight", wherein the switching means NIL-X are transparent and do not modify bus connections seen so far; and "cross", wherein the first input part and the second output part of each said bus pairs results inversely connected to one another within the pair. In order to control their switching, each control unit DECO-U is directly connected to said switching means M-X with at least one output signal X-S and one input signal C. Control mechanism is the same for both switching states.
Upon execution of a switching instruction XEX <b>, the decode and control unit DECO-U commands through the output signal X-S the switching state required by the Boolean operand <b>, then checks the operand with the input signal C that carries back the means M-X switching state. If they coincide (i.e. switching done), the instruction ends, after eventual exchange of some register: otherwise it stalls or the Program Counter register is adjusted (decreased or not increased) in such a way that the instruction will be executed again on next cycle. The processor SPU stalls in busy-waiting state by executing again indefinitely the switching instruction XEX until the switching of said means M-X occur when the pair unit also requires the same switching state.
At switching time it takes place also the two processes synchronisation. During the "cross" switching state, instructions fetched from one bus C-BUS directly act on variables located in the private memory M of the other one adjacent bus, so that data streams of the two running processes result switched on the memory M buses C-BUS of corresponding instruction streams. Within this asset the two involved processes cannot migrate and any execution of migration instructions causes an exception handling. Since switching involves twin bus pairs, it is natural to use switching blocks IXI made up of the usual 2×2 type elements, having two inputs and two outputs controlled by an input control port CP, and capable to assume, between inputs and outputs, one of said switching states (straight or cross) in accordance with the logic value put on the control port CP. At least three switching blocks IXI are needed, one for each said bus pair, having all control ports CP interconnected, in way to be able to switch simultaneously as reaction to one single control signal C. A switching enable unit XAND with at least two inputs connected respectively to the two command signals X-S coming from both control units DECO-U, enables the switching with at least one output control signal C, connected to the control ports CP of all switching blocks IXI and to the control units themselves, upon concurrent receiving on both inputs of agree switching requests. Eventual processor SPU status register SR, besides the usual information concerning its processor state, can contain further fields concerning the migration activity, the own and pair processor synchronism mode, the switching means M-X mode, etc.
The invention allows industrial scale production of the same economic microelectronic (VLSI) component that integrates both processors SPU of a pair DPU and their interconnections P-P, eventually including also said switching means M-X, a dual port or communication memory DPM and a pair of interrupt communication units, in a single biprocessor unit, usable on its turn for manufacturing parallel and compatible computers in a large range of configurations, powers and costs, addressed toward different market segments, from personal to supercomputers.
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|Classification aux États-Unis
|Classification internationale
|Classification coopérative
|Classification européenne
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Owner name: BIPROCESSOR S.R.L., ITALY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ESPOSITO, ANTONIO;ESPOSITO, ROSARIO;REEL/FRAME:012283/0817
Effective date: 20011016
|12 oct. 2005
|Maintenance fee reminder mailed
|21 oct. 2005
|Surcharge for late payment
|21 oct. 2005
|Fee payment
Year of fee payment: 4
|21 aoűt 2009
|Fee payment
Year of fee payment: 8
|19 sept. 2013
|Fee payment
Year of fee payment: 12


text:
ForexLive European Morning Wrap – Key Levels Targeted but Holding so far…
EURUSD tests 1.3320-25 support again as EURJPY falls to test key 124.50
GBPUSD finds a mix of buyers to challenge offers above 1.5500 but fails to breach again
German ZEW economic sentiment sharply high at + 48.2 in Feb versus 31.5 in Jan
Eurozone Contruction Ouput falls 1.7% mm 4.8% yy
What started out as a quiet session turned lively again very quickly just as I posted " its all gone quiet " in time honoured ForexLive tradition.
EURJPY fell rapidly through support at 125.00 as Middle East names targetted the stops just below and succeeded, driving the pair lower to 124.75 before a small bounce.
EURUSD of course came down rapidly with it and tested yesterday's lows around 1.3325, but the subsequent rally was weak and EURJPY got closer to the magnet that is 124.50, hitting lows of 124.55 before bouncing again
In the meantime GBPUSD saw a test of the reported offers above 1.5500 again after concerted buying from a combination of Middle East names ( again ) and a UK clearer buying for UK insurance company repatriating funds from the US.
Throw in a brief cocktail of much better than expected German ZEW sentiment, worse EZ construction output, and an array of sell orders, and we spent the next couple of hours of up and down in ever tightening ranges as EURJPY rebounded to 125.26 and EURUSD to 1.3374 before running out of steam and heading back lower along with GBPUSD, where we've sat for almost 2 hours now.
Let's see what the US make of it all upon their return to the fray.
The preceding article is from one of our external contributors. It does not represent the opinion of Benzinga and has not been edited.
Posted-In: News Forex Global Economics Markets Trading Ideas

subset: commoncrawl


text:
IDEAL Industries has taken a major step forward in making power quality analysis easier, safer and more accurate with the introduction of its Model 806 Power Analyzer. This rugged, hand-held test instrument performs all the measurements needed by large-scale commercial and industrial enterprises to create an effective energy management program.
Sought-after features of the new tester include: single- and three-phase measurements with auto-configuration to the electrical system specified; True-RMS readings for error-free testing; data logging with 1MB of internal memory and optional FIFO memory to allow continuous recording; a 4th current channel for neutral current measurements; auto-detect clamps for easier setup; a backlit 160 x 160 pixel LCD; and an RS-232 interface for fast data downloading to IDEAL PowerVision analysis software.
For more information, visit www.idealindustries.com.


text:
Results 1 to 5 of 71
Threaded View
March 12th, 2013 12:11 AM #21
It has been four years since you returned from your study abroad program in (Spain). You have since graduated from (USC) with a degree in (History). After graduation, you got a job in (Law) in a big city.
What city do you move to?
5. Atlanta
You have dated several guys since you returned from (Spain), but you haven't forgotten about (Jose). Therefore, you are very excited when your employer, (NAME OF EMPLOYER), decides to send a group of employees to (Spain) for a conference. You are even more excited when your boss tells you that you get to go.
As you pack your suitcases and get ready to leave on your trip, you tell yourself that you're excited to be going back to (COUNTRY) and being able to practice (Spanish), not because you're hoping to see (Jose) again. After all, what are the odds that you'll run into him again?
You and a co-worker get seats next to each other on the flight to (Spain). Although your co-worker is friendly, you can't help comparing her to your roommate from your study abroad program, (Charlotte).
What is your co-worker's name? Amelia
Your plane lands in (Spain) and you can't help but feel a little smug when you're the only one in your group who speaks enough (Spanish) to communicate with locals. You help your group find the hotel, where you discover that you and (Amelia) are roommates.
The next morning you wake up early. By the time the rest of your group, including (COWORKER), wakes up, you are ready to go. Your driver pulls up in the car, and the whole group piles in. Your conference is being held in a large government building, and your group is told that several government officials from (Spain) will be in attendance.
You and (COWORKER) find seats next to each other in the auditorium where the opening meeting is being held. You see several well-dressed people in front of the stage, talking urgently and shuffling papers, and you assume that these are the government officials.
The leader of the conference begins the meeting by thanking everyone for showing up, and then announces that the Crown Prince of (Spain) will be making a speech about Human trafficking ). A younger man stands up and walks to the center of the stage. You pretend to be coughing to stifle your gasp, but (Amelia) still looks at you funny. The Crown Prince is (Jose)!
You barely hear a word he says during his speech because you are so shocked. Sure, you had hoped to see him again on your trip, but not quite like this.
Eventually the meeting is over and the conference leader says that everyone will split up and attend smaller discussions. You and (Amelia) decide to go to different discussions, and split up. You are walking down the hall toward one of the rooms when you hear your name.
You turn around, and (PRINCE Jose) is behind you. You don't really know what to say to a Crown Prince, but before you can embarrass yourself he starts talking. He tells you that he saw you in the audience and wanted to talk to you. You are wary, but he tells you that he is the same guy that you met four years ago. He asks you go out for dinner with him that night, and you agree.
To be continued…Raquel-23 year old who loves names, books, and languages
Ladies: Clara Josephine, Amelia Juliet, Louisa Genevieve, Rose Caroline, Charlotte Rosamund, Eleanora Winter, Marina Adelaide, Emmeline Margot, Alice Primrose,Annabel Frances, Catherine Isabella, Vivienne Lucille
Gentlemen: Frederick Arthur Louis, Nicholas Hugo, Henry Oliver, William Grey, Matthew Isaiah, Thomas Alaric, George Everett, Edmund Tobias, Asher Benjamin, and James Raphael


text:
RAB Special Situations, the fund which bet on Northern Rock after it ran into trouble last year, said that while it had suffered from a dramatic fall in equity prices, its focus on commodities and the Asia puts it in a good position.
The fund, part of hedge fund RAB Capital and personally run by its chief executive Philip Richards, said that while investors had fled from equities, its strategy would pay off in the longer term because of the burgeoning demand for commodities from Asia.
"In the real world our companies are generally further advanced along the development curve than a few months ago, but have been marked down heavily in the market for no fundamental reason.
"The demand for natural resources remains strong throughout Asia and the developing world, and this relates very largely to the building of infrastructure which is not that sensitive to a US slowdown," the funds said today.
It said it would own "some of everything that China needs to buy" over the next 20 years.
RAB made the comments alongside the fund's 2007 results. It has fielded much criticism over its high risk punt on Northern Rock which failed to pay off when the stricken bank was nationalised.
The value of assets under management remained roughly flat in 2007 at 157.13p a share, but the fund said that by the end of last month net assets had fallen by 13pc to 136.67p a share.
RAB has historically made its money from betting on oil and gas companies but has diversified in recent years. The most striking example is RAB's investment in A1 Grand Prix, the Asian motor racing series and alternative to Formula 1.


text: > Wouldn't you also need to delete ~/.dingrc? Jerome, you are quite right. I had relied on the list file and didn't realize that it omitted configuration files. Once I got the clue, sure enough, the file was there, and the script problem was obvious and easily fixed. Thanks. Haines


text:
To Battlescar!
|Darnassian Glaive Thrower destroyed (5)
|Alliance Soldier in Battlescar Valley slain (20)
DescriptionI will allow this old fool time to plead his case. He has assured me that he will bring back proof that the night elves do not harbor a weapon of mass destruction. We shall see.
While we await this proof, you will assist our army in the valley. We have prepared a large number of siege tanks for this purpose. Our demolishers are poised for attack.
Take the elevator down to the base of the outpost and take control of a Krom'gar demolisher. Use it to lay waste to our enemies in Battlescar Valley.
You possess quite a talent for destruction, <name>. Whatever Alliance remain after your rampage across Battlescar Valley will be dealt with by the bomb.
You will be able to choose one of these rewards:
|Grebo's Crossbow
|Wand of Destructive Talent
|Shield of Battlescar Valley
|Rampaging Staff
GainsUpon completion of this quest you will gain:
- 6,650 experience
- 350 reputation with Orgrimmar
To Battlescar!
Please keep the following in mind when posting a comment:
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Simply type the URL of the video in the form below.
The Wowhead Client is a little application we use to keep our database up to date, and to provide you with some nifty extra functionality on the website!
It serves 2 main purposes:
- It maintains a WoW addon called the Wowhead Looter, which collects data as you play the game!
- It uploads the collected data to Wowhead in order to keep the database up-to-date!
You can also use it to keep track of your completed quests, recipes, mounts, companion pets, and titles!
So, what are you waiting for? Download the client and get started.


text:
Please remember to follow the manual of style and code of conduct at all times.
Check BNN and Bulbanews for up-to-date Pokémon news and discuss it on the forums or in the Bulbagarden Discord server.
User talk:Sparen/Archive 1
I noticed you have been editing the
User: namespace a lot recently. You may not be aware of this, but Bulbapedia has a Userspace policy that asks users to try and minimize the number of userspace edits they make in a short period of time. Heavy editing of these personal pages can put undue stress on the server, so please leave your page alone for now and go help out in the mainspace. Bulbapedia is an encyclopedia, after all, so please help us to complete it! If you edit the mainspace more often, you will be allowed to edit your userpage more often too. Thanks! --♫Green♫ギャラドス♫Talk♫ 02:50, 13 December 2009 (UTC)
Page Categorization
Whenever you create a new encyclopedic page, please make sure to categorize it. It's official policy, all pages in encyclopedic namespaces must be categorized, with the one and only exception of the Main Page.
Furthermore, you might want to reference similar already-existing articles as reference when creating new articles of those types. This may help in increasing the quality of articles you create from the start, instead of having them tagged for a cleanup effort which may take some time to get completed. If you can learn the ins and outs of working on quality articles, you'll become a pro in no time. Trust me, even the best of them have rocky starts, just ask our editor-in-chief. --Shiningpikablu252 05:41, 13 December 2009 (UTC)
Hold on!
If you did not read your last warning, then please read it now. You have edited the
User: namespace too much. In the past, no one was allowed to edit their userpages because some users were over-editing their own userpages. Your personal editing privileges can be taken away, so please do not edit your page any more for now. Thank you. --- Kogoro | Talk to me - 06:43, 13 December 2009 (UTC)
Don't reply to old comments like what you did at talk:Boulder Quarry. The user might have found the answer by now. Turtwig A (talk | contribs) 22:50, 3 February 2010 (UTC)
Talk Page Comments
Removing talk page comments, including the initial welcome template, is prohibited per Bulbapedia's talk page policy. Please do not remove any comments in the future. If you wish to clean old comments away, you should archive your talk page instead. Thank you! --▫▫ティナ♫★ 20:05, 20 May 2010 (UTC)
Woah, hold up!
You've been told before, don't create encylopedia articles with one sentence. The ones you made today are set to be deleted. Takharii ~ Talk! 01:28, 26 June 2010 (UTC)
Axe and Edward
You have Axe confused with Dress and Edward confused with Axe. The Pokémon used by each of the Tea Party members are:
- Dress: Ditto
- Magic: Giant Crobat
- Axe: Regigigas
- Edward (leader): Mewtwo
Please don't make new articles without checking that their contents are true. Shiny Noctowl 22:59, 26 June 2010 (UTC)
Preview Button
Hi, I've noticed you've been editing the same article numerous times in a very short span of time. Please, use the preview button next time, before saving, so you only have to make one edit. —♥ Jello 21:16, 6 July 2010 (UTC)


text: I have an 86 Silverado that just cuts off on me. When I try to start it back up it just turns over and over. I can come back later and it usually starts right up. I have replaced the distributor cap, coil, rotor button, and module(under the rotor button). The plugs have about 1500 miles on them. What gives???? I'm on the verge of putting this thing in the river.


text:
MC: Pres: Book 4 (MC Series)
Today's Free Kindle eBook: MC: Pres: Book 4 (MC Series)
Ben James was groomed to become an Officer in the MC. Prospecting early he was sent to college by the MC President that was looking to form a new type of leadership in their Club. When the President was killed in drug wars and the Brothers started taking each other out to get a bigger cut of the drug money, Ben steps into the President role fighting to keep his Brothers alive and get out of the flesh and drug trades. Pulling his best friend Knight into the VP slot he has his security specialist keeping the Club moving in the right direction. As he moves out of the quick money and into legitimate businesses his Club grows. The new Officers; fight for right, respect their women and value their kids. Working to make money legitimately makes for happy members. All but Ben's old lady, without the constant threats and excitement of wars she leaves Ben and they're adopted son Jessie. Ben sees his Officers finding strong women that build and solidify their purpose and his dream of a clean Brotherhood working and living peacefully within their drug free neighborhoods and community. Raising their kids to take care of each other and treat their women with respect, Ben is so close to his dream but he has no one to share it with. Kate runs the Women's Center within the MC's backyard. The MC supplies the buildings for her offices, shelters for abused women and security to keep them all safe. Ben admires Kate's strength, ability and compassion running the Center and adopting kids from the shelters that would have gone into the system. Danny, Kate's husband, is Ben's Building Supervisor and number two High Security enforcer when he's needed. He's proven himself and earned respect from his Brothers and Ben. When his old lady leaves he moves a few houses away from Kate and her family. His son spends so much time with the LaPonte family Ben is invited regularly to dinners and family activities. He finds himself drawn to them and starts to wonder if he'll ever find a woman like Kate to share his life with.
Just follow this link to get the freebie:


text:
The food you eat in summer should be light and easily digestible.
Yesterday, we suggested how you could include lots of liquid coolers in your diet.
Today, we bring you some simple recipes and diet mantras to help you beat the heat.
Try cold soup
Swap heavy dinners for cold soup and sandwiches or have a sandwich, salad and fruit juice. Here is a recipe for Cold Cucumber Soup.Serves 6 ~Ingredients1 kg fresh cucumbers500 gm curd150 ml milk 1 tbsp butter 1 tbsp capsicum, chopped
Chop up one cucumber finely and the others into big pieces.
Add three cups of water to the big cucumber pieces and cook till soft.
Blend in a mixie after cooling.
Add curd, milk and salt to taste to the cucumber puree. Mix well.
Heat one tablespoon of butter and fry the finely chopped cucumber along with one tablespoon of finely chopped capsicum for a few minutes.
Add to the soup. Mix well and chill. Serve cold.
Chutney with amla
This is yet another cooling food, which is a healthy substitute for butter. Chutney, when prepared with amla, is an antidote for fatigue. You could substitute amla for lime or tamarind.
~ Ingredients1 bunch coriander leaves 3 medium-size onions3-4 flakes garlic Juice of � lime/ juice of 1 marble-sized ball of tamarind/ 1 amla, grated 2 green chillies
Clean and wash the coriander leaves (kothmir) well.
Grind into a paste with three medium sized onions, three to four flakes garlic, lime juice/ tamarind juice/ grated amla, green chillies and salt to taste.
Tarla Dalal's curd rice
Renowned cookery expert Tarla Dalal had, in one of her recipe books, this unusual recipe for curd rice. This recipe is rich in protein, calcium and Vitamin A. Curd rice, incidentally, is a perfect summer meal.Serves 2~ Ingredients
2 katoris rice1 katori curd1 small cucumber1/2 carrot, grated1 tbsp coriander, chopped1/2 tsp cumin seeds A pinch asafoetida2 tsp urad dalSalt to taste ~Method
Put the cooked and cooled rice in a large bowl.
Add thick fresh curd, finely chopped cucumber, grated carrots, finely chopped coriander leaves and salt to taste. Mix well. In another pan, heat oil and season some cumin seeds.
When they crackle, add urad dal (split black gram) and asafoetida (hing).
Saut� for a minute and pour over the rice and mix well. Serve immediately.
Eats for kids
Instead of giving children commercially available ice candies that are nothing but frozen sugar syrup laden with additives and flavours, try these Vitamin C-rich recipes.
Ice lollyUse any juicy fruits you already have in your larder to whip up ice lollies. ~Ingredients
Oranges/ sweet limes/ mango/ pineapple/ watermelon/ muskmelonA little sugar (optional)~Method
Chop the fruit into small pieces.
Add a little sugar if needed and mix well.
Spoon the fruit pieces into kulfi moulds and freeze them in their own juices.
Unmould and serve.
Ice cream
Banana and curd makes this a healthy ice cream that children will love. Serves 4
2 cups curd1 bananaHoney to taste1/2 teaspoon vanilla essence/ Pinch of elaichi powder~MethodCombine the curd, banana, honey and half teaspoon of vanilla essence/ pinch of elaichi powder in a mixer till smooth.
Pour into kulfi moulds or ice lolly moulds and freeze.
Diet mantras
~ Avoid spicy, oily dishes and fried foods. Excessive amounts of chilli, pepper and garam masala are irritating to the digestive system. Instead, season foods with small amounts of jeera, fresh coriander and mint (pudina) as these are milder and also act as digestives. ~ Your diet should include plenty of fresh juicy seasonal fruits such as oranges, sweet limes, strawberries, grapes, guavas, watermelons, jamuns, banana, papaya, etc.
Sprouts, salads, raita, curd rice, solkadi rice (kokum curry rice is a Konkani speciality), sandwiches, etc, along with the fruits, provide all the nutrients needed by the body -- particularly Vitamin C and the B-complex vitamins that help build resistance against the colds and fever that are very common during this season. ~ Mangoes and jackfruit, available in plenty during the summer, are rich sources of b-carotene, which is converted into Vitamin A and stored by the body in the liver.
This is sufficient to meet the body's Vitamin A requirements for at least six months. However they are heat-inducing and high in calories, so they should be eaten in moderation (two big or three small mangoes per day). Excessive consumption can lead to a weight gain, skin eruptions and diarrhoea. Diabetics should be particularly cautious and not eat too many mangoes as it can cause the blood sugar levels to skyrocket.
Too much of jackfruit can lead to indigestion. ~ Curd is a great summer food as it is cooling, contains proteins in the predigested form and is richer in B-complex vitamins as compared to milk. It also contains bio-available calcium, phosphorus and magnesium and a variety of probiotics or friendly bacteria that have many beneficial effects on health. ~ During summer, avoid porridges of nachni (ragi) as it increases the body's heat level. Keep this in mind when weaning babies and cooking for small children.
Share your favourite summer recipes with us. The best recipes will be featured on rediff.com
Rohini Cardoso e Diniz is a consultant dietician with Naomi's Fitness Centre and manages a private practice in Goa.


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I found the Kool-aid statement a tad strange, based simply without having access to the main stream "kool aid" you miss out on a lot of the set up and configurations that make the SHP one of the oldest and most sucessful airframes in their fleet. However, if it is going to be flown in more of an aerobatic / IMAC fashion, this may not even matter. I just thought it was an interesting statement.
From the landing and its appearence to "hunt" I have seen in the videos it "seems" like it could use some additional nose weight, but it could just be a side affect of the winds, or being too touchy around the middle. Question for you, fully assembled without fuel, will it hold its own tail up while leaning on the front cowl?
Are the rates and expo set up as the manual indicates? If you are not going to fly the plane as it is designed to be flown, you throws and configuration could stand to have a bit of changes. Flat Spins... That chassis will do them all day long once you learn the sweet spot. Often the big control surface can act as a break and cause drag when not needed.
A full 3 control surface snap on that plane with stop the plane like brakes, and cause it to fall like a rock. Its a good practice to not pin all 3 controls full at once, make sure at least one is not fully tossed.
I do think once you get it dialed in, it will become your best friend.
I have always found the easiest way to enter a flatspin Is to enter it from a hammer head. Always left stick for upright and right for inverted. Right after the hammer head I like to pull hard elev and on some planes add a little oppsite aileron. On my 41 inch 3DHS Edge I have to bump the throttle to get the nose up. On the twist going WOT really flattens her out.
michael, welcome!
I've owned both the Twist 40 and the Sabre 47, also the Aerowotks In the 40 size.
Nice plane Wayne. Enjoy!!
If Extreme flight would get stock in, I would not have the 3DHS plane so maybe some of the popularity of the 3DHS planes is lack of options.
Yes, the throws will stall the plane. My TT60 was the same way. I could pop a snap roll and stop it and reverse direction in the length of the plane. I will have to work with this one more but I can normally get one to spin even if the throws are really high. Like I said, I was more interested in the smoke system that peaking the plane.
As for the Kool-Aid comment. I did read a lot of posts on the Slick and SHP. That is where I learned a lot of people have had broken gear on the SHP.
There is also a lot of puffing, in my opinion, and lack of objectivity (or lack of experience) with some of the owners when considering possible problems and alternative air frames.
It is just the feeling I get Ron when looking the responses.
I am pretty happy with the CG right now. I have not tried to stand it on its nose lately. It would hit the wheel pants when they were on. I liked the landing characteristics, slow flight, and inverted this weekend. It only required minor corrections in knife edge and it was pretty easy to move it around in knife edge. Now that I have had some success with it, I will move to tweaking the setup.
It really does not feel tail heavy and I don't want to get it where it feels like I am picking up the nose all the time.
The elevator throw was the only think I could not get to the rates in the book. I may look at that more later as well. I think it has plenty for the moment.
I did not call it a dog or anything. I just am still reserving judgement.
As for flat spin entries, I have seen a lot of variance in planes. Some if it pilot dependent also, in my opinion. I think the right way is the way you and the plane can agree. I know one plane that seems to flat spin best to the right and I usually spin left (upright). I had to have the guy show me several times.
One of the lessons on real flight, as I remember, suggests you fly level, reduce throttle and hold altitude until it stalls, and then spin it in which ever way the wings drop. I know one person the makes an up line, flips over to a down line and then hits the spin sticks. Maybe there is a mental picture that works for some and not for others. I stall it, force a left roll, then hit left rudder and up elevator, and add tight aileron as needed to level the wings. I add power, if the plane will take it, to speed up the spin. I had one plane that always flew out of it if it got much throttle. The Model Tech Magic loved to spin. It was easy to enter and you could go full power.
We will see in the next few weeks how it does and how I like it. I had my YAK really flying easy. I did not have to work for much of anything. I will take a while to get comfortable with this one.
Last edited by waynemia; Feb 04, 2013 at 10:48 PM.
Make sense Wayne, but remember the Threads are a double edge sword that often can be miss leading. You have to sometimes authenticate your "Kool Aid" and makes sure the source has the actual knowledge of the product.
I find the discussions around the landing gear on the threads amusing. These planes are designed to be oober light wing loading and a the gear is a part of that design function. I have gone to several events and seen some of the roughest grass feilds around with 20-30 of the 3DHS planes flying all weekend and seldom see a lg pop <outside of a crash>.
Don't be afraid to shift that CG a bit forward of the recommended range, I know several of the more proficent pilots that prefer not to fly a "neutral" set up.There are dozens of people that insist that the only way a plane will hover or spin is for it to be tail heavy. These type of planes have enough throws to make a forward CG set up do every stunt very well, and they fly better over all. Not to mention they land better, which is better on the LG.
Even though it's 25 this morning, they're calling for 50. With 10 mph winds. Now our field is going to be soft and we have no drive way.
On the other hand I do have twist field, but I have to mow it.
O no thats unheard of here in febuary, but you guys have seen my field.
The last time twist flew there, she was a bush plane.
I would nick name her the bush master but that name has already been taken.
Guys I was over at flying giants trying to post this video and it wouldn't link.
So even though many of you seen snowdog filming trixie an the green machine, here it is again http://www.youtube.com/watch?feature...&v=4neuVcCXHPg
Yeah she did a nice job showing kerwin50 what he suppose do with that MX Ok kerwin Your up
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I can't believe we've already come to the end - for now - of the Bess Crawford series! Today we discuss the 4th book in Charles Todd's bestselling series, but our read along is not over yet. After today's discussion here, we still have our live online radio podcast with the Charles Todd writing team this Thursday night, during which we will talk about the entire Bess Crawford series!
I think An Unmarked Grave might have been my favorite Bess mystery so far - it certainly kept me guessing until the end and I loved how much action there was. Bess was on the move the entire time.
World War I nurse and amateur sleuth Bess Crawford matches wits with a devious killer in this exciting and suspenseful adventure from New York Times bestselling author Charles Todd
In the spring of 1918, the Spanish flu epidemic spreads, killing millions of soldiers and civilians across the globe. Overwhelmed by the constant flow of wounded soldiers coming from the French front, battlefield nurse Bess Crawford must now contend with hundreds of influenza patients as well.
However, war and disease are not the only killers to strike. Bess discovers, concealed among the dead waiting for burial, the body of an officer who has been murdered. Though she is devoted to all her patients, this soldier's death touches her deeply. Not only did the man serve in her father's former regiment, he was also a family friend.
Before she can report the terrible news, Bess falls ill, the latest victim of the flu. By the time she recovers, the murdered officer has been buried, and the only other person who saw the body has hanged himself. Or did he?
Working her father's connections in the military, Bess begins to piece together what little evidence she can find to unmask the elusive killer and see justice served. But she must be as vigilant as she is tenacious. With a determined killer on her heels, each move Bess makes could be her last.
1) In each of the previous books in the series, we saw Simon Brandon take on a increasingly bigger role in investigating crimes with Bess and in this book, the Colonel and Bess' mother are also actively involved in her search for the killer. What did you make of this?
2) Both Bess and Simon fall ill in this novel - Bess from the Spanish Flu epidemic ravaging both France and England and Simon from his wounds. What did you think of each of them in their more vulnerable states and why do you think the authors chose that for them?
3) There were several suspects put forth throughout the course of the novel. How did you feel when the killer, and his motives for killing, was finally revealed?
4) What did you think of Bess' decision to help Hugh Morton in his desertion?
5) I loved the scene of Bess working alongside the doctor to save Sargeant Mitchell, with her father looking on. As far as we know this is the first time he's seen his daughter in action as a nurse and what she can do. What did you think of that scene?
6) What new word did you learn from this mystery? For me it was "sappers" - which refers to either a military specialist in field fortification work or a military demolitions specialist.
More than anything, this novel drove home for me, even more than the previous three, the toll that the war is taking, as it drags on - on soldiers, nurses and the people of England and France. There was a haunting sense of the loss and devastation and the hopelessness that the end is not in sight. I found this audio recording of Roses of Picardy - the song that Bess hears a soldier playing on a mouth organ when she is working in Ypres: "I thought how homesick he must be, letting the instrument put into words what he couldn't, that the war had last far too long and there was still no end in sight. He had lost heart, and I couldn't fault him for that."
I look forward to seeing your answers to the above questions, and then, our Book Time with Bess Read Along isn't quite over yet! Please join us on Thursday night, June 28th at 7pm ET, as we welcome the writing team of Charles Todd to Book Club Girl on Air to answer all our questions about the entire Bess Crawford series - as well as anything else you'd like to ask them about their Inspector Ian Rutledge series and researching and writing the war in general. Set your reminder for the show here!


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Written on: 10/07/2013
I have only ever ordered cards from Moonpig, and they have always been excellent. The choice is very extensive, the personalisation is great, and to my knowledge they have always turned up on time. I also love the reminder feature, which has saved me from forgetting my friends' and families' birthdays and special events - as a rather absent-minded person, I find this an absolute godsend.
I hardly ever buy cards from a shop anymore, as I much prefer the personal touch you get with a Moonpig card. Absolutely delighted with the service, and have nothing negative to say.


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Jake McVey sings Friday at Sondheim
Iowa native and country music star Jake McVey brings his show, with special guests Lady Lowe and Quay Thomas, at 7 p.m. Friday to the Fairfield Arts & Convention Center's Stephen Sondheim Center for the Performing Arts.
McVey has opened for country stars, such as Merle Haggard, Kenny Chesney, Lady Antebellum, Miranda Lambert, Blake Shelton, Martina McBride, Jason Aldean, Sugarland, Dierks Bentley and many others.
McVey's first national radio release, "Carry On," quickly became a benchmark for his career. It was a No. 1 Video on CMT and voted Top 10 of 2012 Most Inspirational Videos by Great American Country.
McVey followed up with his second release, "Redlined And Wasted," which again quickly climbed the charts, and he decided to head back into the studio and create a body of new songs in late 2011: "Best Days Of Our Lives," released in early 2012 — "Used To Be," "Just Drive" and "Slow Dancing."
"I love to entertain — that's my drug," McVey said. "I love people. I'm one of the fortunate ones that I get to perform for a living. There's nothing else I'd rather do. The whole process, from the concept of a song to performing it in front of thousands. That's my passion."
This summer, McVey will be on the road opening and touring with Pistol Annies, Josh Turner, Craig Morgan, Easton Corbin, Toby Keith, Love and Theft and Aaron Tippin to name a few.
Friday evening, Lady Lowe and Quay Thomas also will be performing.
The trio, Lady Lowe, originated in early 2009 in North Liberty. They are an acoustic adult contemporary band playing covers of artists like Sugarland, Carrie Underwood, Sara Evans, Lisa Loeb and Jason Mraz. Jennifer Lowe has lead vocals and plays the keyboard.
Quay Thomas is a young blues artist from a small Iowa town. His debut album released in January, "Please Stay," has 11 original works ranging from alternative to bluesrock, and he keeps the blues rooted in his wide variety of styles in music.
General admission tickets in advance are $14. Tickets at the door are $15.
For information about the show, visit the website www.fairfieldacc.com or call the ticket office at 472-2787.


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Interview attire: 'Conservatism is key'
GRAND FORKS, N.D. -- Job interviews can stir a lot of nerves and anticipation of new possibilities, which can put clothing at the back of one's mind. But employers around the Grand Forks area agree that the first impression is everything, and one's clothing choices have a lot to do with it.
"Everything is about that first impression," said Mickie Nakonechny, owner of True Colors. "You don't want to overdo and you don't want to under-do it."
Pat Hanson, director of human resources and payroll services at the University of North Dakota, agreed.
"I think it's important when you make that first initial impression that it tells us who you are," she said. "If your clothes are really wrinkled, if they are not appropriate for the environment you'll be working in, it says a lot about whether you'd fit into that position."
Dress for the position
When choosing an outfit for an interview, they said the first thing to consider is the type of position one's applying for.
"In general, I recommend that you dress up a notch from the position," said Ilene Odegard, director of career services at UND.
Hanson said UND doesn't have a dress code, but she expects applicants to come dressed appropriately, and appropriate attire may vary with the type of position.
"If they're coming in and interviewing for a faculty position, the dress might be different than if they're coming in for a custodial position," she said.
For professional interviews such as a teaching, office or bank job, Nakonechny said black pants, a blouse and cardigan or blazer would be appropriate. She said men should wear an ironed button down shirt with a crisp collar and tie.
Other employers suggest more formal business attire.
"For women and men, a suit is an investment," Odegard said. "In a way, you can't not afford it."
But that formal business attire isn't required for every interview.
For custodial and blue-collar jobs, Hanson said, "It might not be the two-piece suit and tie that you'd wear if you were interviewing for a faculty position or a professional position."
She said khakis and a dress shirt or polo shirt would be more appropriate for those jobs.
Similarly, Nakonechny said structured leggings or jeans and a nice tunic are acceptable for most retail interviews.
Dress for the environment
Kathy Kenyon, employment recruiter at Altru Health Systems, and Kristi Stoltman, nurse recruiter at Altru, said it's also important to dress for the environment.
"We are a smoke free facility, so we really discourage or frown upon people who come in smelling like cigarette smoke, just because we are smoke free, and we can't have employees like that around our patients," Stoltman said.
Kenyon added, "If it's specifically health care that you're interviewing with, you want to keep fragrance free… you always want to be aware of your surroundings."
They suggested doing some research on a company and the specific department to determine whether or not there is a dress code.
Be conservative
"I think what we'd recommend is to dress very conservative and be overdressed rather than underdressed," Hanson said. "Conservatism is key."
That conservatism includes the cut, design and length of pieces, as well as the colors and patterns.
"You always want to air on the side of caution," Nakonechny said. "The time for individuality is when you get the job."
She suggested neutral tones such as black, white and even navy.
Kenyon agreed. "It comes across more professional when you stick to those neutral colors because it's more of a traditional feel when you stick to those blacks and browns," she said.
Nakonechny added: "I would stay away from the larger patterns and bolder colors. The whole idea is to make a good impression and you want the interviewer to be listening to what you're saying not looking at your clothes."
At the same time, Nakonechny said for a retail position she appreciates a little individuality in an interview.
"If you're applying for a job in retail, where your appearance helps sell clothes, then your individuality can show through more, and you can wear more unique pieces," she said. "For me, individuality in a person's style is important."
It's more than the clothes
Even at a more professional interview, Nakonechny said interviewees can show a little personality with their jewelry and accessories, as long as it isn't too distracting.
"You want to show your personality, I get that, but if the interviewer walks out the room you want him to remember you, not your Mickey Mouse tie," Odegard said.
Along with the professional attire and accessories, Nakonechny said men should be clean shaven, women should have their hair done nice and nails should always be well-groomed.
"Chipped nail polish looks unprofessional," she said.
She also suggested covering up tattoos and taking out any body piercings.
Kenyon said she sees a lot of people come in with flip-flops, which takes away from the candidate's professionalism.
"One time I had an applicant who had sunglasses on their head," Stoltman said. "They were dressed professionally, but the manager noticed that right away."
All of those little things contribute to one's overall appearance and professionalism and can help determine whether someone receives a job offer.
"We look at their responses, their communication skills, their skill sets, but we definitely look at what they're wearing and how they present themselves," Stoltman said. "And I think what they wear can really help."
Interviewing do's and don'ts
- Research the company, department and position before the interview.
- Prepare questions about the position.
- Practice interview questions with a friend.
- Have good posture.
- Be confident and positive.
- Dress professional.
- Be genuine and authentic.
- Keep jewelry and makeup to a minimum.
- Leave the purse in the car; instead bring a pad folio for notes.
- Don't wear loud colors and busy patterns.
- Don't fidget.
- Don't wear flip-flops.
- Don't chew gum.
- Don't bring your children.
- Don't bring your cellphone.


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PATRICK HOSTS the "Patrick Madrid Show," airing M-F from 6:00 to 9:00 am Pacific. The program is produced and distributed nationally by Immaculate Heart Radio.
Each edition of the "Patrick Madrid Show" is podcast and also archived for later listening.
To call the show, dial 888-914-9149 (between 6:00 am and 9:00 am Pacific). Show-related comments and questions can be sent directly to Patrick via Twitter: @patrickmadrid.
Prior to launching the "Patrick Madrid show," from 2012-2015, Patrick hosted the "Right Here, Right Now" show on Immaculate Heart Radio, carried across a network of approximately 300 AM & FM affiliate stations, as well as on Sirius Satellite Radio, and globally via shortwave. From 2007-2012, he hosted the Thursday edition of the popular "Open Line" radio program.
Patrick is also a frequent guest and occasional guest-host on the "Catholic Answers Live" radio show.


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WMV Video Converter
DVDFab Video Converter can be used as a great WMV video converter that converts any video to WMV video for display on specific devices. This simple tutorial on how to do the conversion will give you a general idea about how professional DVDFab is.
Step 1: Start up DVDFab 9, choose Converter option and load in the video source
Start up DVDFab 9 and choose Converter option. On this Video Converter interface, just drag and drop the video source you want to convert into it.
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Open Profile box to navigate to Format then to wmv on the left panel. And choose a profile for the output WMV.
Step 3: Edit video parameters and video effect
Click Advanced Settings button to go to set video parameters and audio parameters.
You can also click Edit button on the main interface to open Video Effect window to resize the source aspect ratio and frame resolution of the video, or you can crop the image for display.
Step 4: Start conversion
Hit Start button on the main interface to start conversion. During the process, you can monitor all detailed progress info and preview the progress with real time images.
OK. Done. More info about DVDFab Video Converter can be found at: https://www.dvdfab.cn/video-converter.htm


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It's difficult to believe it's been almost 20 years since the Reverend Horton Heat released his first album — and he hasn't changed a bit. Of course, the whole point of psychobilly is an unabashed dedication to purity of sonic identity. (That, and getting just fucked up enough to let your inner redneck show off its less-than-desirable personality traits.)
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Though the right reverend is headlining this show, the rest of the bands on the bill are no less religious in their approach. Nashville Pussy has been playing the same demented and sleazy Skynyrd-meets-Motorhead rock for more than a decade. And what of Hank III? Isn't he supposed to be the crazy, diverse one? Well, not exactly. The grandson of Hank Williams lends his Christian name to psychobilly twang and country two-step, but he typically doesn't play them in the same set. What about when he wants to do something else altogether, say a punk/metal set? Well, he simply joins another band or calls his own band Assjack. So yeah, the first song might be a surprise, but after that, you know what's coming. For the most part, all of the bands here deliver shit-kicking sets. After all, each of them has staked out a unique slice of the hellbilly pie for himself (in Hank III's case, he has taken a few slices). And what they do, they do loudly and powerfully. Which, really, is exactly what bands of this caliber should be doing anyway.