text:
|Publication number
|Publication type
|Application number
|Publication date
|Jan 2, 1996
|Filing date
|Jul 20, 1994
|Priority date
|Jul 20, 1994
|Fee status
|Also published as
|Publication number
|James S. Blomgren, David E. Richter
|Original Assignee
|Exponential Technology, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (21), Non-Patent Citations (6), Referenced by (138), Classifications (35), Legal Events (15)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is related to copending application for a "Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode", filed Jan. 11, 1994, U.S. Ser. No. 08/179,926, hereby incorporated by reference. This related application has a common inventor and is assigned to the same assignee as the present application.
This invention relates to computing hardware, and more particularly to the architecture of registers in a processor capable of executing from two instruction sets.
Processors, or central processing units (CPU's) that are capable of executing instructions from two separate instruction sets are highly desired at the present time. For example, a desirable processor would execute user applications for the x86 instruction set and the PowerPC™ instruction set. It would be able to execute the tremendous software base of x86 programs that run under the DOS™ and WINDOWS™ operating systems from Microsoil of Redmond, Wash., and it could run future applications for PowerPC™ processors developed by IBM, Apple, and Motorola.
Such a processor is described in the related to the copending application for a "Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode", filed Jan. 11, 1994, U.S. Ser. No. 08/179,926. That dual-instruction-set CPU has a pipeline which is capable of executing instructions from either a complex instruction set computer (CISC) instruction set, such as the x86 instruction set, or from a reduced instruction set computer (RISC) instruction set, such as the PowerPC™ instruction set.
Two instruction decode units are provided so that instructions from either instruction set may be decoded. Two instruction decoders are required when the instruction sets are separate because the instruction sets each have an independent encoding of operations to opcodes. For example, both instruction sets have an ADD operation or instruction. However, the binary opcode number which encodes the ADD operation is different for the two instruction sets. In fact, the size and location of the opcode field in the instruction word is also different for the two instruction sets. In the x86 CISC instruction set, the opcode 03 hex is the ADD r,v operation or instruction for a long operand. This same opcode, 03 hex, corresponds to a completely different instruction in the PowerPC™ RISC instruction set. In CISC the 03 hex opcode is an addition operation, while in RISC the 03 hex opcode is TWI--trap word immediate, a control transfer instruction. Thus two separate decode blocks are necessary for the two separate instruction sets.
Programs may run in either or both instruction sets. Data and other information may be shared between RISC programs and CISC programs. One way to share data and other information is to store the data in a register within the CPU before switching to the alternate instruction set, and making all registers readable by either instruction set. Unfortunately, this requires that the instruction sets be extended to provide instructions to read the additional registers. The shared data could also be saved to a stack in memory, but this decreases performance due to the time required to transfer the data to memory and to adjust the stack pointers.
Two sets of registers could be provided; one set for the use of CISC programs and a second set for the use of RISC programs. This is an expensive approach since the registers reside on the CPU die, which has a limited space available for registers. The additional registers would require increasing the size of the CPU die, or deleting another function such as floating point processing.
What is desired is a way to share some of the registers between a CISC and a RISC architecture on a dual-instruction-set CPU. It is further desired to have shared registers for data and system information. The shared registers should not be extra registers in addition to the registers already defined by the CISC or RISC architectures, but should be registers already existing in the architectures. The shared registers must not cause conflicts between use in the two instruction sets or other undesirable effects.
Certain CPU registers defined by a RISC and a CISC architecture are shared. CISC and RISC programs may alter and read these shared registers, allowing data and system information to be exchanged between programs running in the two instruction sets.
A shared register system for a dual-instruction-set processor has a shared register for storing information to be transferred between a first program comprised of instructions from a first instruction set and a second program comprised of instructions from a second instruction set. The first instruction set has a first encoding of operations to opcodes, while the second instruction set has a second encoding of operations to opcodes. The first encoding of operations to opcodes is substantially independent from the second encoding of operations to opcodes.
A first means is for accessing the shared register from the first instruction set. The first means writes information into the shared register responsive to a first subset of instructions from the first instruction set. A second means is for accessing the shared register from the second instruction set. The second means reads information from the shared register responsive to a second subset of instructions from the second instruction set and.
The invention allows information to be transferred from the first program to the second program using the shared register. In other aspects of the invention, the shared register may be any one of the general-purpose registers accessible to both instruction sets, while the source and destination fields in the instruction words specify which general-purpose register to access. In still further aspects of the invention, the shared register is the flags register which stores flags or condition codes that are implicitly written by arithmetic-logic-unit (ALU) operations. Although the shared flags register contains a first flags field for flags from the first instruction set and a second flags field for the flags from the second instruction set, either instruction set can access the flags in the shared register regardless of which instruction set the flags are from.
FIG. 1 is a diagram of a RISC register set.
FIG. 2 is a diagram of a CISC register set.
FIG. 3 is a diagram of a CISC condition flag register and a RISC condition register.
FIG. 4 shows shared registers in a dual-instruction-set CPU.
The present invention relates to an improvement in processor architecture. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
This application is related to the copending application for a "Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode", filed Jan. 11, 1994, U.S. Ser. No. 08/179,926, hereby incorporated by reference.
A dual-architecture central processing unit (CPU) is capable of operating in three modes--RISC mode, CISC mode, and emulation mode. A first instruction decoder decodes instructions when the processor is in RISC mode, while a second instruction decoder decodes instructions while the processor is in CISC mode. Two instruction decoders are needed since the RISC and CISC instruction sets have an independent encoding of instructions or operations to binary opcodes.
The third mode of operation, emulation mode, also uses the first instruction decoder for RISC instructions, but emulation mode executes a superset of the RISC instruction set. Using emulation mode, individual CISC instructions may be emulated with RISC instructions. Thus, not all CISC instructions need to be directly supported in the CPU's hardware. Unsupported CISC instructions cause a jump to an emulation mode routine to emulate the unsupported CISC instruction. Upon completion of the emulation mode routine, control is returned to the CISC program with the next CISC instruction.
Emulation of CISC instructions with RISC instructions creates a need for the RISC instructions to have access to CISC registers. For example, a CISC branch instruction may be emulated by an emulation routine of RISC instructions. The CISC branch instruction may be a conditional branch that only branches if a certain bit in a condition code register is set, perhaps by a previous CISC instruction. Since the CISC condition code register is part of the CISC architecture, but not the RISC architecture, the condition code register would not be visible to the RISC instructions in the emulation routine. However, the RISC emulation routine must have access to this CISC condition code register to determine if the branch should be taken.
FIG. 1 is a diagram of a register set for a RISC architecture such as the PowerPC™. Registers that are visible to a user program are shown as user register space 10. Supervisory programs such as operating systems are able to see all of the registers in the user register space 10 and the registers in the supervisor's register space 12. The user registers include general-purpose registers 14 which are used by programs for temporary storage of operands and results, and for address formation. Floating point registers 16 are provided for storing floating point numbers that a numeric processor operates on. Condition register 20 contains condition codes set by various instructions and is useful for setting and checking conditions for conditional branch instructions. Integer exception register 18 contains bits that are set when an exception is caused by execution of an instruction. It contains information on overflows and carries that occurred in an arithmetic-logic-unit (ALU) when the instruction causing the exception was executed. Link register 22 contains the branch target address when a special branch to link register instruction is executed. Count register 24 holds a value for a loop count which can be decremented, providing a simple way of programming loops.
A supervisory program such as an operating system has access to additional registers in the supervisor's register space 12. Supervisor general-purpose registers 26 are for general use by the supervisory program. Segment registers 28 and block-address translation registers 32 are for address translation functions. Machine state register 36 defines the state of the processor, including reset, and CISC/RISC/emulation mode. Machine state register 36 contains a privlege-level bit, the PR bit, to indicate if a the processor is running in user or supervisor mode when RISC mode is active. An additional bit, the xE bit, is included in machine state register 36 to indicate CISC and emulation modes. The xE bit and the PR bit are encoded as shown in Table 1.
TABLE 1______________________________________Machine StatusxE bit PR bit Processor Mode______________________________________0 0 RISC Supervisor0 1 RISC User1 0 x86 Emulation1 1 x86 CISC______________________________________
Machine status save restore 0 register 30 saves the effective address of the instruction following the instruction causing an exception or a system call instruction. Machine status save restore 1 register 34 saves part of machine state register 36 and other information on the cause of an exception when an exception occurs. In particular, machine status save restore 1 register 34 receives the PR bit and xE bit from the machine state register 36. Machine status save restore 1 register 34 thus saves the mode the processor was in at the time of an exception or other event, and is used to restore the processor to that mode when exception processing is complete. A return from interrupt (rfi) instruction at the completion of the exception processing will restore the xE and PR bits to the machine status register 36 from machine status save restore 1 register 34. Together, machine status save restore registers 30, 34 save the state of the processor when an exception occurs, allowing the system to return to the user program once the exception handler routine is completed. Hardware-specific registers 38 contain miscellaneous implementation-specific information such as extended features.
FIG. 2 is a diagram of a register set for a CISC architecture such as the x86 used in microprocessors by Intel corporation of Santa Clara, Calif., Advanced Micro Devices of Sunnyvale, Calif., and Cyrix Corporation of Richardson, Tex. Registers that are visible to a user program are shown as user register space 11. Supervisory or system-level programs such as operating systems are able to see all of the registers in the user register space 11 and the registers in the system-level register space 13. The user registers include general-purpose registers 15 which are used by programs for temporary storage of operands and results, and for address formation. Segment registers 17 are provided for address translation. Floating point registers (not shown) may be included in some embodiments to store data in a floating-point format. Flags register 21 contains flags or condition codes set by various instructions and is used for setting and checking conditions for conditional branch instructions. Instruction pointer 19 contains the address of the instruction currently being executed.
A system-level program such as an operating system has access to additional registers in the system-level register space 13. System address registers 26 are for use by system-level programs for address generation. System segment registers 29 are for segment address translation functions. Control registers 31, 35, 39 define the state of the processor, including protected or real modes, exception handling, cache enabling, and contain the base address of page tables. Breakpoints and control, performance monitoring, real-time clocks and other control may also be included in control registers 31, 35, 39. Floating point instruction pointer register 38 contains the address of the instruction last executed by the floating point unit. It must be saved because a floating point exception may be signaled after other instructions pass through the integer pipeline. It allows an exception handler routine to find the exact address causing a floating point exception.
Condition codes are employed by both RISC and CISC instruction sets. Instructions that use the arithmetic-logic-unit (ALU) may produce a result having a zero or negative value. These instructions cause a flag or condition code in register 21 or 20 to be set when the result is zero or negative. Iterative loops may be programmed using such flags. For example, a simple loop may execute a series of instructions and decrement a loop variable each time the series of instructions in the loop is executed. The loop variable is initially set to the number of times to execute the loop. At the end of the loop, an ALU instruction subtracts one from the loop variable. When the loop variable becomes zero, the zero flag will be set. A conditional branch instruction will check the zero flag and exit the loop when zero is reached.
Many other flags may be defined. For example, the x86 CISC EFLAGS register defines the flags of Table 2 that are set or cleared by ALU instructions depending on the result of the instruction.
TABLE 2______________________________________CF Carry Flag Set if carry-out or borrowPF Parity Flag Set if low 8 bits have even parityAF Auxiliary (2nd) Carry Bit 3 carry-out, used for BCDZF Zero Flag Set if all bits are zeroSF Sign Flag Set if highest-order bit is oneDF Direction Flag Incr. or Decr. string variableOF Overflow Flag Signed overflow to highest bit______________________________________
Other bits in the x86 EFLAGS register are not flag bits set by operations but are control bits that define how the processor will operate. Table 3 shows these control bits.
TABLE 3______________________________________TF Trap Flag Trap after next instructionIF Interrupt enabled Flag Enables external interruptsIOPL Input/Output Privilege Max. Privilege for I/O instr. level (2 bits)NT Nested Task Flag Nested task being executedRF Resume Flag Resume after breakpointVM Virtual Mode Virtual 8086 mode executingAC Memory Alignment Check Mis-aligned data will fault______________________________________
The dual-instruction set processor directly executes only the simpler CISC instructions. Many of these simpler CISC instructions set or clear the flag bits in Table 2. However, the control bits in Table 3 are set or cleared by complex or infrequently used CISC instructions such as privileged instructions. These instructions are therefore emulated. Only the simple CISC instructions will modify the flag bits in the CISC EFLAGS register. Emulated instructions will modify the control bits in the CISC EFLAGS register.
FIG. 3 shows the CISC flags register 21 and the RISC Condition register 20. In the PowerPC™ RISC architecture, flags or condition codes are kept in the condition register (CR) 20. Condition register 20 is a 32-bit register divided into eight 4-bit fields, CR0 to CR7. Most RISC integer instructions generate the four bits in CR0, but do not modify any bits in fields CR1 to CR7. Table 4 shows the meanings of the four bits in CR0.
TABLE 4______________________________________RISC CR0 fieldCR0 bit Name Description______________________________________0 Negative Result is negative1 Positive Result is positive and not zero2 Zero Result is Zero3 Overflow Overflow has occurred______________________________________
Floating point operations do not modify the bits in the CR0 field, but they do modify the four bits in the CR1 field. Table 5 shows the definitions of the four bits in CR1 set by floating point operations.
TABLE 5______________________________________RISC CR1 fieldCR1 bit Name Description______________________________________0 FP exception Floating point exception has occurred1 FP enabled exception A floating point enabled excep- tion has occurred2 FP invalid exception An invalid floating point exception has occurred3 FP Overflow Floating Point Overflow has occurred______________________________________
A RISC compare instruction can set bits in any of the 4-bit fields CR0-CR7. Table 6 shows the definitions for the four bits in any field CRn set by the RISC compare instruction.
TABLE 6______________________________________RISC CRn field set by Compare InstructionCRn bit Name Description______________________________________0 Less Than register A is less than register B or immediate value from instruction word1 Greater Than register A is greater than register B or immediate value from instruction word2 Equal To register A is equal to register B or immediate value from instruction word3 Overflow Copy of the Overflow bit in XER register______________________________________
The compare instruction specifies which field to write its result to. Likewise, the RISC branch instructions can specify, as a condition for branching, any bit in any of the fields CR0 to CR7. Thus the programmer may write condition codes to the other six fields in the CR register 20. The programmer may later use these other fields with the branch instruction using any of the bits in any of the fields CR0 to CR7. RISC move instructions may also load bits into any of the fields CR0 to CR7 of the CR register 20. The RISC move instruction may move bits from another register, or from one 4-bit CR field to another field within CR register 20. A mask may be specified in the move instruction word to indicate which bits to move and which bits to not modify. A wealth of RISC logical instructions are provided that specify as inputs one or two bits in any of the 4-bit fields. A Boolean logical function is performed on the specified input bits, and the resulting output bit is written to any bit in any of the 4-bit fields in CR register 20. Thus RISC provides a variety of instructions to update, modify, and perform logical functions on parts of the CR register 20.
Although fields CR2 to CR7 may be updated in a variety of ways by RISC instructions, the inventors have recognized that fields CR2 to CR7 may be infrequently updated while fields CR0 and CR1 are typically updated frequently. A programmer has to explicitly decide to update fields CR2 to CR7, while fields CR0 and CR1 are implicitly updated by many RISC instructions.
The inventors have also recognized that most CISC instructions update bits 0 to 11 in the CISC EFLAGS register, while few CISC instructions update bits 12 to 31 in the CISC EFLAGS register. FIG. 3 compares the CISC flags register 21 and the RISC Condition register (CR) 20. FIG. 3 shows that simple CISC integer instructions update flags in bit-positions 0 to 11 of CISC EFLAGS register 31, while RISC integer instructions update bits in the 4-bit CR0 field. RISC floating point instructions update field CR1, while few RISC instructions update fields CR2 to CR7. If a RISC programmer can avoid using fields CR5 to CR7 in RISC CR register 20, which correspond to bit-positions 11 to 0 in the CISC EFLAGS register 21, then the CISC EFLAGS register 21 can be folded into or combined with the RISC CR register 20. Since the RISC programs that will share data with CISC programs are typically RISC emulation routines, the RISC programmer will be aware of these limitations and avoid using fields CR5 to CR7. Standard RISC user programs that do not avoid using fields CR5 to CR7 will not be able to take advantage of the data sharing features of the invention, but will still be able to take advantage of the cost savings of the invention beacuse fewer registers are needed on the microprocessor. However, x86 CISC emulation routines written in RISC code will greatly benefit by both sharing data using the shared registers and by cost savings.
Complex CISC instructions modify the control bits of Table 3, which are in bit-positions 12 to 21 of EFLAGS register 21. These complex CISC instructions may be emulated with RISC instructions in the emulation mode of the dual-instruction-set processor. These control bits may be stored in memory rather than in EFLAGS register 21, freeing up these bits for use by CR2 to CR4. If CISC instructions need to read any of these control bits, then they may be stored in bit positions 12 to 21 of the EFLAGS register 21, but still updated by emulation.
The CISC EFLAGS register 21 and the RISC CR register 20 are combined into a single 32-bit register in the dual-instruction-set processor. When a complex CISC instruction that updates a control bit in the EFLAGS register 21 is emulated, the RISC instructions in the emulation routine merely have to update the corresponding bit in one of the fields CR2 to CR4 in the RISC CR register 20, because the RISC CR register 20 and the CISC EFLAGS register 21 are the same shared register. For example, a complex CISC instruction writes a one to the Virtual 8086 mode bit (VM) at bit-position 17 in the EFLAGS register 21. This complex CISC instruction is not supported by the instruction decoder and signals an unsupported opcode exception, which causes emulation mode to be entered from CISC mode. An emulation routine of RISC instructions is executed to emulate the complex CISC instruction. This emulation routine contains a RISC Boolean instruction which will set bit 2 in CR3, corresponding to bit-position 17, the VM bit, in the EFLAGS register 21. The RISC Boolean instruction setting this bit may be a CR-register Boolean XOR instruction (creqv) that exclusive-OR's bit 2 to itself, with field CR3 as its sources and destination. Once the emulation routine is completed, CISC mode is again entered and execution of the CISC program resumes at the following CISC instruction. Because CISC EFLAGS register 21 and RISC CR register 20 are implemented as the same hardware register on the CPU die, updating the RISC register also updates the register seen by CISC programs.
The emulation routine of RISC instructions, or other native RISC programs, may freely update bits in fields CR0 and CR1, because these bits correspond to reserved bits in CISC EFLAGS register 21. At the conclusion of the emulation routine, before CISC mode is entered, these bits in CR0 and CR1 are cleared so that they will all be read as zero when CISC mode instructions read CISC EFLAGS register 21.
Folding CISC EFLAGS register 21 and RISC CR register 20 together brings additional benefits besides cost reduction by having fewer registers on the CPU die. RISC programs can examine the flag bits in CISC EFLAGS register 21 to determine the results generated by the CISC program using the existing RISC instructions. No special instructions are needed to examine this information from the other instruction set. The RISC program may examine the zero flag to determine if the CISC program had a zero result, which might indicate the end of an iterative loop. The CISC zero flag (ZF) at bit position 6 may be examined by a RISC instruction simply by reading bit 2 of field CR6. Likewise, any of the other flag bits may be examined by a RISC program by reading the corresponding bit in the RISC CR register 20. Particularly with emulation routines, having this information is critical. Because the RISC instruction set has so many instructions which can access RISC CR register 20 directly, the emulation routine may be efficiently programmed without many move or load/store instructions to make available the CISC EFLAGS register 21. Thus the emulation routine will have a much higher performance than if the CISC EFLAGS register 21 had to be stored on a stack in memory and retrieved for the emulation routine to examine. Even moving a separate CISC EFLAGS register 21 from one CPU register into the RISC CR register 20 for use by RISC branch instructions would require extra RISC instructions, decreasing performance relative to the invention.
The emulation routine can perform branches directly off the CISC flag bits. A RISC instruction in the emulation routine can branch off the VM bit in the CISC EFLAGS register by merely specifying the corresponding bit in the RISC CR register. The CR register is the most visible and accessible state register in the PowerPC™ RISC architecture. The EFLAGS register in the x86 CISC architecture is likewise the most interesting CISC register because of the many state flags stored in it. Using the RISC CR register as a window into the CISC architecture provides a versatile and powerful tool.
The RISC and CISC condition code and flags registers are effectively merged together into a single flags register that is accessible by instructions from both instruction sets. The merged register is special because it is not just explicitly accessible as a register, but the merged register is also accessible implicitly. Instructions that implicitly update the flags register, whether RISC or CISC instructions, will update the same merged register. Because the two instruction sets tend to use separate portions of the merged register, each instruction set can use its portion of the merged register, without interfering with the other instruction set. Yet programs running in one instruction set can still observe the flags set by programs in the other instruction set. Thus information about the results generated by one instruction set may be made available to programs in the other instruction set.
Information about the operating state of the x86 CISC program is also available by reading the merged flags register since control bits are stored in bit-positions 11 to 21. These control bits, shown in Table 3, include virtual 8086 mode, interrupt enabling and privilege levels, an indication of task nesting, debug trapping, and data alignment checking. Again, a RISC program merely has to read the proper bit in the merged register, which appears as the standard RISC CR register to the RISC program. Often the register does not even have to be explicitly read by the RISC program, but only implicitly read. A RISC conditional branch instruction can be set to branch on the bit in CR 5 corresponding to the CISC interrupt enable control bit (IF). A RISC program could branch to a routine to check and disable interrupts if the IF bit is set, but continue without disabling interrupts if the bit is zero, knowing that interrupts are not possible. Thus the CISC interrupt enable bit is used to direct program flow in the RISC program merely by branching on the CISC bit. No register transfers, loads, or even explicit reads were necessary. The invention provides a very clean, simple, and efficient way to pass information between programs running in two different instruction sets.
Other registers are also be folded together or combined. The RISC count register (CTR) is a 32-bit register that contains a loop count that can be decremented when a branch instruction is executed. It can be explicitly accessed by some RISC move instructions, and can be implicitly accessed by certain RISC branch instruction which cause the CTR register to be read and decremented.
One of the CISC segment registers (17 of FIG. 2) holds the base address of the code segment. This code segment register is needed to generate addresses for fetching instructions when in CISC mode. The base address in the code segment register is also needed to calculate the targets of a branch instruction. Thus the code segment register is accessed frequently.
The RISC CTR register and the CISC code segment registers may be combined together in the dual-instruction-set processor. The combined register holds the CISC code segment base address during CISC mode. The code segment base address is left in the combined CTR/CS register when RISC mode is entered. If a RISC iterative-branch instruction is encountered that uses the count register, then the code segment base address can be saved to memory before the RISC iterative-branch instruction begins execution. The code segment base address is restored by the emulation routine to the combined CTR/CS register before CISC mode is re-entered.
Since the CTR register is infrequently used, the code segment can remain in the combined CTR/CS register most of the time, even during RISC mode. RISC emulation routines may be programmed that do not use the CTR register, thus increasing performance of the emulation routine. Since both the CISC code segment register and the RISC count register are needed by the branching unit, merging these into the same register provides a single shared register to supply both CISC and RISC address information to the branching unit.
The RISC machine status save restore 0 register (SRR0) 30 of FIG. 1 saves the effective address of the instruction following the instruction causing an exception, or the effective address of the instruction following a system call instruction. When the exception handler routine completes and a return-from-interrupt (rfi) instruction is executed, the address that was stored in SRR0 is reloaded into the instruction pointer so that program execution can continue with the next instruction. Thus the SRR0 register provides a place for the address of a RISC instruction that occurs after a RISC instruction causing an exception.
In the dual-instruction-set processor, when a CISC program causes an exception, a RISC emulation routine is called and executed. Thus the normal CISC exception handling hardware is not needed and no counterpart to the SRR0 register is necessary. The CISC CR2 register would normally hold the address of an instruction causing a page fault in a CISC-only processor. This CR2 register is not needed in the dual-instruction-set processor since page faults, like other exceptions, are all handled by RISC emulation code. Other CISC exceptions would cause the instruction pointer (IP) to be pushed on the stack in memory by the exception handler. Pushing the IP to the stack is not performed in micro-code, as in prior-art x86 processors, but by the emulation routine for the dual-instruction-set processor. Any time emulation mode is entered from CISC mode, regardless of the cause, the address of the CISC instruction being executed is stored into the RISC SRR0 register. When the emulation routine completes, the processor switches back to CISC mode, the address stored in register SRR0 is re-loaded into the instruction pointer, and the next instruction in the CISC program is fetched and executed.
If emulation mode is entered to handle an exception, then SRR0 should point to the CISC instruction causing the exception, so that CISC instruction can be re-started once the exception handling is complete. If emulation mode was entered to emulate a complex CISC instruction, then SRR0 should hold the address of the instruction following the CISC instruction. When the emulation routine determines the size of the CISC instruction, the size is added to the address stored in the SRR0 register to get the address of the next CISC instruction. This addition must occur because CISC instructions can vary in size, CISC instructions being 1-15 bytes in size. Thus SRR0 will cause the CISC program to continue at the instruction following the CISC instruction being emulated, unless an exception occurs.
The RISC SRR0 register, which normally holds the address of an instruction causing an exception, is also used to hold the address of a CISC instruction following a CISC instruction that caused emulation mode to be entered because the CISC instruction was not supported in hardware but had to be emulated. These are two parallel uses, but for two different instruction sets. The additional hardware to support both of these functions is minimal because these functions are closely related.
The RISC link register (LR) provides a branch target address for a RISC branch conditional to link instruction. It is a 32-bit register. While most RISC branch instructions do not use the link register, some do.
The CISC architecture requires that the address of a floating point instruction be saved. Since floating point operations may take several clock cycles to complete, several simple integer .instructions could have completed execution by the time an exception is signaled that was caused by the floating point instruction. Storing the address of the floating point instruction allows the exception handling routine to backtrack the code and sort out the integer instructions executed. This address of the floating point instruction is stored in the FP IP register in the CISC architecture. In the dual-instruction-set processor this address is instead stored in the RISC link register.
Storing the CISC floating point instruction's address in the RISC link register may cause a problem if a RISC program contains a RISC instruction that uses the link register. If that happens, the CISC floating point instruction's address must be saved to a stack in memory or to another general-purpose register. It is believed that this will be an infrequent occurrence and therefore the cost savings of combining the registers justifies sharing these two registers. Most of the time the RISC link register will not be used, so no conflict will occur.
Since the link register is used to store the address of the RISC target, a path for an instruction address is already provided to this register. Thus the floating point instruction's address may also use this instruction path to the shared LR register.
There are 32 general-purpose registers (GPR's) for RISC which may be explicitly read or written by RISC instructions. The x86 CISC architecture provides only 8 general-purpose registers which can be read or written by a user program. CISC also provides 6 segment registers which contain segment base addresses that are used to calculate the linear address of code, data operands, and a stack. These segment registers can only be used for segmentation, a part of address generation, and have restrictions on reading and writing them with CISC instructions. Only x86 privleged or segment-load instructions can read or write the segment registers. All of these instructions are emulated by the dual-instruction-set processor. Thus CISC-mode instructions cannot directly read or write these segment registers.
These 32 RISC general-purpose registers may be merged with the 8 CISC general-purpose registers and the 6 CISC segment registers. Table 7 shows how these registers are used for RISC, CISC, and emulation mode.
TABLE 7______________________________________Shared GPR'sRISC Mode CISC Mode Emulation Mode______________________________________GPR0 EAX GPR EAX GPRGPR1 ECX GPR ECX GPRGPR2 EDX GPR EDX GPRGPR3 EBX GPR EBX GPRGPR4 ESP GPR ESP GPRGPR5 EBP GPR EBP GPRGPR6 ESI GPR ESI GPRGPR7 EDI GPR EDI GPRGPR8 ES Seg Base ES Seg BaseGPR9 CS Seg Base CS Seg BaseGPR10 SS Seg Base SS Seg BaseGPR11 DS Seg Base DS Seg BaseGPR12 FS Seg Base FS Seg BaseGPR13 GS Seg Base GS Seg BaseGPR14 N/A Emulation Base AddressGPR15 N/A 0 Base AddressGPR16 N/A GPR16GPR17 N/A GPR17GPR18 N/A GPR18GPR19 N/A GPR19GPR20 N/A GPR20GPR21 N/A GPR21GPR22 N/A GPR22GPR23 N/A GPR23GPR24 N/A GPR24GPR25 N/A GPR25GPR26 N/A GPR26GPR27 N/A GPR27GPR28 N/A GPR28GPR29 N/A GPR29GPR30 N/A Emulation Assist AddressGPR31 N/A Emulation Assist Data______________________________________
Table 7 shows that in RISC mode, the 32 general-purpose registers are accessible as true general-purpose registers. Any of the 32 registers may be read or written by RISC programs. In CISC mode, there are only 8 general-purpose registers, EAX through EDI, which share the same physical registers with the RISC GPRs 0 to 7. A CISC program may load one of its GPR's, such as EAX, with a data value, then switch to RISC mode, allowing the RISC program to read that value the CISC program placed in EAX merely by reading the RISC GPR 0. Since the RISC architecture defines GPR 0 as a regular GPR, many instructions can access this register without an explicit load from memory or register-to-register transfer. For example, a RISC add instruction could specify the value in GPR 0 that was loaded by the CISC program merely by identifying GPR 0 in one of the source fields in the RISC ADD instruction word. The result of the ADD may be written back to GPR 0 or any other GPR. Thus no explicit transfer is needed to access the CISC data by the RISC program.
The 6 CISC segment base address registers, ES Base to GS Base, may be implicitly read by the CISC program when generating an address. A RISC program may read or write these registers merely by specifing the corresponding GPR. If the CISC program required emulation code to load segment register FS Base with a base address, then the RISC emulation program would merely have to identify GPR 12 in a RISC instruction to read or write this base address.
CISC programs, however, cannot freely access any RISC GPR except GPR 0 to 7. CISC programs may access GPR 8 to 13 in a restricted way, since these registers correspond to the CISC segment registers ES Base to GS Base. The CISC program may use a special segment override in the CISC instruction word to access one of these segment base registers when calculating an address. The CISC architecture imposes limitations on accessing these segment registers, making them useful for transferring address information between the RISC and CISC programs, but not useful for transferring data. The CISC program can only implicitly access these segment registers for address generation.
CISC mode programs have no access to RISC GPR 14 to 31, since there is no corresponding CISC register. However, emulation mode can access all 31 RISC registers, including the first 8 registers, which are the CISC GPR's, and the 6 CISC segment base registers. However, emulation mode can freely access the CISC segment base registers. Emulation mode executes RISC instructions, so the mechanism to transfer data and address information between CISC and emulation modes is similar to transfers between CISC and RISC modes as described above. The RISC instructions in emulation mode can implicitly access a CISC register by identifying the corresponding RISC GPR as a source in the RISC instruction word.
Emulation mode differs slightly from RISC mode. Normal RISC address checking and page fault handling is performed for accesses to most registers. However, when any of the 6 CISC segment registers, or GPR 14 or 15, are used to generate an address, the CPU uses x86-type address checking and x86 page fault handling, rather than the normal RISC address checking and page faulting routines.
GPR 14 and 15 are used in emulation mode as special emulation-mode segment base address registers. When emulation code generates an address using GPR 15 as one of the operands, no segment validity checking is performed at all, neither RISC nor x86 segment validity checking. Using GPR 15 allows for emulation code to generate an address without any segment checking. Using GPR 14 causes the CPU to use one of the 6 CISC segment registers to form the address, and for checking segment validity. When emulation mode is entered, a 3-bit register is loaded with a pointer to one of the 6 CISC segment base registers. The pointer value loaded is the segment used by the CISC instruction being emulated. This is normally the data segment register DS, or code segment register CS, but a segment over-ride prefix appended onto the CISC instruction could indicate that one of the other segment base registers be used. Thus using GPR 14 allows the emulation code to generate an address using whichever CISC segment register would have been used by the CISC instruction. This is a very powerful feature for emulation, saving dozens of instructions in the emulation routine to examine and decode the CISC instruction word to determine which segment register should be used.
Both registers GPR 14 and 15 are preferably loaded with the value zero so that they do not modify the address being generated. Thus using these registers in emulation mode alters the address checking being used. Emulation mode, although using RISC instructions, can have CISC address checking for certain addresses generated with the CISC segment base registers and the two emulation base registers GPR 14 and 15. Some of the RISC GPR's may be used by emulation mode for particular purposes. For example, GPR's 14, 15, 30, and 31 may be used by emulation routines for address generation within emulation mode, and for various assist functions.
If RISC mode and emulation mode are to be both used at the same time on a system, then the RISC program should not overwrite the four special emulation mode registers, or the CPU hardware needs to provide two sets of registers for GPR 14, 15, 30, and 31, one set exclusively for RISC mode, with a second set exclusively for emulation mode. RISC-mode programs must also not overwrite GPR's 0-13, which are used for CISC mode architectural registers. Because general RISC user programs will write these registers, and may not have a need for transferring data to a CISC program, a process or task switch from a CISC user program to a general RISC user program would be handled as a normal task switch, with all registers being saved to a stack before the switch so that the values in the GPR's will not be overwritten and lost.
The code segment base address is available in two separate registers: GPR 9 holds the CISC code segment base (CS Base) while the RISC count CTR register also holds this same code segment base. This is beneficial for modern pipelined and superscalar processors because the CTR/CS register can provide the branching unit with the code segment base address, while the GPR array also can provide the code segment base address to the execution unit. Thus the code segment base address may be provided from two separate registers to two separate units within the processor. Since these units are often separated, having the separate registers can save the delay in transferring the code segment from the GPR's to the branching unit. As the code segment base address is frequently used in address calculations, having it in two separate locations is useful, effectively doubling the available bandwidth for supplying this base address.
Merging the GPR's together with the CISC GPR and segment registers provides a very efficient and clean way of transferring address and data between CISC and RISC programs and emulation programs. Normal architectural features are used to access and transfer data. Data can be accessed explicitly by specifying the corresponding GPR as the source in the instruction word.
FIG. 4 is a diagram of the shared registers in the dual-instruction set processor. The CISC EFLAGS register and the RISC CR register are combined into a single 32-bit CR/EFLAGS register 40 that can be accessed by CISC user programs and RISC user programs and emulation code. The CISC code segment base address register and the RISC count CTR register are merged to a single CS/CTR register 42, also accessible by CISC user programs and RISC user programs and emulation code. The RISC system save/restore (SRR0) register, which normally holds the address to return to after an interrupt has been processed, also holds the return address when emulation code was called. Thus SRR0 can hold a RISC address or a CISC address. The RISC or CISC user can indirectly load SRR0 register 44 by causing emulation code to be entered, but cannot directly access SRR0 register 44. However, RISC supervisor code and emulation code has full access to SRR0 register 44.
The RISC link register, which is used to hold a branch address, is combined with a CISC register that holds the instruction address of the last floating point instruction. This merged FP-IP/LR register 46 is also indirectly accessible by CISC programs because they cannot directly read or write it, but can only load it by executing a floating point instruction. RISC and emulation programs can freely access this merged FP-IP/LR register 46. The 32 general-purpose registers from RISC are merged with the 8 GPR's and 6 segment base registers from the CISC architecture into merged GPR's 48. Four of the RISC GPR's are used by emulation code for special uses, although emulation code can access all RISC and CISC registers.
This improvement relates to a central processing unit (CPU) for a dual-instruction set architecture. While the detailed description describes the invention in the context of the PowerPC™ reduced instruction set computer (RISC) and the x86 complex instruction set computer (CISC), it is contemplated that the invention applies to other instruction sets besides PowerPC™ and x86, and to more than two instruction sets, and to architectures besides RISC and CISC, without departing from the spirit of the invention. The exact number of bits in each register may likewise be varied by persons skilled in the art without departing from the spirit of the invention, although architecture compatibility may be lost.
The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
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|Unified single-core and multi-mode processor and its program execution method
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|Boundary address registers for selection of ISA mode
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|Flexible digital rights management with secure snippets
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|Securing microprocessors against information leakage and physical tampering
|Sep 25, 2007
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|Apparatus for executing programs for a first computer architechture on a computer of a second architechture
|Mar 12, 2007
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|Method of sharing registers in a processor and processor
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|Circuits and methods for efficient data transfer in a virus co-processing system
|Sep 12, 2008
|Mar 26, 2009
|Siemens Energy & Automation, Inc.
|Systems, Devices, and/or Methods for Managing Programmable Logic Controller Processing
|Jan 22, 2009
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|Bluerisc Inc., A Massachusetts Corporation
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|Delayed deallocation of an arithmetic flags register
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Dec 5, 1994
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text:
Great Arch (5.5*) Climber's Log
[ Sign the Climber's Log ]
|Bob Sihler
|Great Arch
Date Climbed: Jun 23, 2015
|Climbed this a few days ago with my son, cool and sobering to see where the split flake was pried off and sent down the mountain. Thanks to those who reported it and to those who removed it; it was easy to imagine what might have happened to a belayer at P1.
Not much to add that hasn't already been said, but I want to mention that I found the second pitch the hardest and the most run-out, and it was the area around the removed block that seemed the most so. Maybe that pitch used to be easier to protect, maybe not. And maybe I just completely missed good placements.
Still, a fun route. And the walk back down is not long as some claim. It took my 44-year-old butt and my 10-year-old son less than 30 minutes to walk back to the car.
|Posted Jun 28, 2015 11:50 pm
|Climbed Many times!
|Climbed this one maybe a dozen times. Was a great "intro to friction" route!
|Posted Apr 12, 2013 9:04 pm
Date Climbed: Jan 3, 2009
|super fun route, great winter climbing
|Posted Jul 7, 2009 4:29 pm
|Back killer
Date Climbed: Feb 17, 2008
|Climbed it with the fiance and WoundedKnee. Great pro, a nice alternative to the usual friction climbs at Stone.
|Posted Mar 15, 2009 5:27 pm
Date Climbed: Feb 17, 2008
|Very fun climb. Some local climbers were surprised at how crowded it was for a winter weekend.
|Posted Feb 18, 2008 10:48 am
Date Climbed: Apr 1, 2000
|this climb is awesome. takes great pro and is easy, secure climbing. bolted belays. great fun.
|Posted Dec 21, 2007 11:10 am
Date Climbed: Sep 6, 2007
|Absolute classic. Even if you hate friction climbing you absolutely have to climb it if you are a carolina climber.
|Posted Dec 11, 2007 9:15 am
|Great climb!
|Excellent climb. Great rock.
|Posted Mar 12, 2006 6:08 pm

subset: commoncrawl


text: quote:Originally posted by minilopsTexianjoe, Did you try Hullabaloo Diner? My husband and I saw the episode of "Diners, Drive-Ins, and Dives" that featured the diner and couldn't believe it was here in College Station, Tx (Wellborn) where we live. The next week we went to try it out. We both ordered the Philly Cheesesteak, but a minute later the waitress came back and said there was only one cheesesteak left!! My husband graciously let me have it and he ordered a hamburger. He said the hamburger was okay, not as good as the hamburgers at Koppe Bridge on Wellborn Rd. in College Station. Since I have never had a "real" Philly cheesesteak, I have nothing to compare this one with, but that said, I thought it was pretty good. I have heard that the breakfasts are supposed to be quite good, so we will give it another try.If you are in College Station, I would definitely recommend you try Koppe Bridge!Minilops (Allison)


text:
Big Night for DePauw Men Including All-America Relay
March 22, 2013
Shenandoah, Texas - On the third of four days of competition, the DePauw men turned in some more solid performances including an all-America finish in the 800-yard freestyle relay.
After finishing 13th in the prelims of the 200 butterfly, sophomore Casey Hooker broke his own school record set just hours earlier by placing 10th in 1:49.06.
Senior Matt Kukurugya joined Hooker in earning honorable mention all-America after turning in a ninth-place finish in the 100 breaststroke in 56.09 which broke his own school mark.
Hooker, Robby Spichiger, Alex Grissom and Matt Haeske finished the night by placing seventh in the 800 free relay and earning all-America honors in a school-record time of 6:40.36. Hooker's leadoff of the relay (1:38.99) also broke the Tigers' 200 free mark.
The Tigers have totaled 77 points and are in 13th place as a team headed into the final day of competition. Saturday's prelims begin at 10 a.m. CDT at the Conroe Natatorium.
For more information on the DePauw men's swimming and diving program, follow DePauw on Twitter (@DePauwAthletics / @DPUMensSwimming) or like them on Facebook (www.facebook.com/DePauwAthletics).Back


text:
Deep snow in early summer
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Ankogel a little farther on the track of Hochalmspitze. You can reach the top of Ankogel from Osnabrücker Hütte. This track take a compass to the top from North. 14.06.2006.
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text:
Last night, New Orleans Regional Transit Authority (RTA) officials and engineers revealed the first glimpse of the anticipated streetcar connecting the Central Business District to the French Quarter and Marigny. According to current plans, the new streetcar won't run on the neutral ground but on a shared lane — which becomes streetcar-only during "peak" traffic. The transit corridor's overhaul also will include a bike lane, though only heading from the Marigny into the CBD.
"We've tried to incorporate as many of your questions and concerns as possible over the last three years," said Justin Augustine, RTA general manager and vice president of Veolia TransDev.
According to the project's timeline, final construction documents are due by the end of June, with the construction bid finalized and awarded by early 2014, and construction wrapped by 2015. (Sixty percent of the design is complete.) The $75 million bond-financed project will run track from Canal Street to Elysian Fields Avenue, with six stops — at Conti, St. Ann and Ursulines streets, Esplanade Avenue, Pauger Street, and Elysian Fields. There, a double crossover (which will resemble an "X" at the intersection) will remove the travel lane closest to the neutral ground between Frenchmen Street and Elysian Fields for a "full-time dedicated" streetcar lane, according to project manager Bill Norquist. Also, "the travel lanes will be pushed to the outside to the cost of a parking lane for that block," he said.
Each shelter stop will have lights, ADA accessibility, ticket machines, bike parking and seating. "We also wanted to be respectful of the historic vernacular of the neighborhoods we're going through," Norquist said. "We want neighborhoods to take ownership of these stops."
When the public meeting was announced earlier this month, the announcement did not include instruction for public transit-riding attendees. Instead it offered validated parking. The RTA will schedule its next meeting in May, but some attendees were frustrated that last week's meeting, held inside the Hyatt French Quarter off Bourbon Street, made it difficult for residents near the planned streetcar line to attend. "This location is nice but inaccessible to primary stakeholders," Jacques Morial said. "Essentially for many people have to pay to park to come here if they can't take the RTA. You're imposing a tax on them."
"Equity is critically important to the RTA," Augustine replied. "We understand our role. We serve everybody and everybody's neighborhoods throughout this entire community. … We have gone in other neighborhoods throughout the city to discuss this project. This is not the only meeting. We will continue to go to other locations. … As we move closer to the neighborhoods, we will be in those respective locations. I promise that."
RTA board chairwoman Barbara Major interjected, saying, "If we really are to rebuild our city differently than it was before, we've got to not give such vague responses. … I'm demanding we have some more meetings in other neighborhoods."
The RTA also revealed its compromise with the city — a compromise that seemingly doesn't satisfy either party. The streetcar will not run on the neutral ground (Norquist said it already is too congested with fiber optics, gas lines, AT&T lines, and an "existing underground drainage canal that dates back to the 1800s"), but will instead occupy a shared lane, except during peak traffic hours.
Meeting attendees asked, then, if Rampart Street becomes just one lane in each direction during peak traffic hours, why not 24 hours a day?
Even Norquist admitted that a traffic study looking at 16 impacted intersections found only three diminished traffic times, each less than three seconds.
"It was clear from the traffic study that the least impact the traffic flowing through the area would be is through the use of a shared guideway," he said. "The decision was made by the city. … I don't want to say compromise, (but) how we could come to a solution that addressed as many concerns as we can. Nobody came out a complete victor. I'm sure if I asked now if Justin would like to see a shared guideway the whole way, he'd be shaking his head very quickly."
Augustine shook his head "yes." Gulf Restoration Network communications director Dan Favre later asked if there still is an opportunity in the planning process for a dedicated lane. That's up to the city, Augustine said.
Early pre-Katrina planning for a downtown streetcar lane, the Desire line, proposed building a line from Rampart and Canal as far as Poland Avenue. An RTA recommendation from 2002 considered building an underpass at Press Street to avoid Norfolk Southern Railway, which owns the railroad at Press. "The underpass would be in the neutral ground and allow streetcars to pass underneath the railroad line," the project fact sheet reads.
Early plans for the current incarnation of the Rampart line included sending the cars as far as Press — but not to Poland. The RTA's current funding limits its reach, unless any federal Department of Transportation TIGER grants become available. Augustine said the RTA would seek them.
Augustine said he'll be in Washington D.C. this week to negotiate with Norfolk Southern. "It's going to come down to a protracted legal battle," he said. "The best and strongest voice will win, I guess."
Residents also are bracing for the same kind of brief-yet-messy construction overhaul seen recently on Loyola Avenue. Augustine said "that's just the way it is."
"If you look at the national audience, they're asking, 'Wow, how'd you get this thing done so fast?'" he said.
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text:
We have our own experiences with being on the transplant list in 2011, but right now, in light of Donor Awareness Week, I want to introduce you to Alexa!
|Alexa (age 4) has Citrullinemia and is waiting for a liver transplant.
Ammonia toxicity kills brain cells, and can result in catastrophic neurological damage. It can also result in death, but we aren't talking about that right now!
For Alexa, getting a new liver would mean no longer having to worry about normal childhood illnesses and viruses such as colds, flu, chicken pox, etc causing permanent damage to her brain. She has had a number of hospitalizations needing specialized medicines to bring down the ammonia levels when she contracts what would normally be mild illnesses for children.
|Alexa is a Toronto Maple Leafs fan!
Alexa is from Toronto (see her Maple Leafs jersey!) I met her mom Shanna for dinner one night in the fall when I was visiting Toronto. We talked the night away about transplant issues, urea cycle disorders, and low protein diets among other things!
In Ontario, you can sign up to be a donor by registering with Be A Donor.ca. Use my link here to register to support Alexa and in memory of our son Kyle.
To learn more about Alexa and her family, you can go to their blog:


text:
Written on: 07/10/2012 by tonyparky (0 reviews written)
This website was great, they list all the storage sites for caravan and motor-homes in the UK which saved me loads of time. Not only that but I filled in their quotation form and they sent me details of caravan and motor-home storage sites that are local to where I live.
Never come across a site like this very easy too use - thanks guys you saved me a load of hassle trying to find a storage site for my caravan.
And the service is totally free!
As rated by our community of reviewers
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Written by Samanth1
" Fantastic caravan " Read More
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text:
Meet Emilia Clarke — or as you might know her Game of Thrones' "Mother of Dragons" Daenerys Targaryen.
The 26-year-old actress has taken a break from raising an army on HBO's hit medieval-fantasy series to play Holly Golightly in the Broadway production of Truman Capote's Breakfast at Tiffany's.
Here TV host Josh Rosenzweig sat down with Ms. Clarke to discuss what her small screen and stage roles have in common — turns out that Daenerys and Holly aren't so different: they're both callow young women who dream of being much greater than they are amid a world that preys on innocence.
But Clarke also dishes on how stage differs from her screen work and what it's like playing a role famously brought to life by iconic actress Audrey Hepburn.
Watch Rosenzweig's interview with Clarke below:


text: An aptly-named affair, Shaw and then new star Kenny Garrett work out over five standards and one example of a silk purse fashioned from a sow's ear, "The Woody Woodpecker Song." And if you're going to cut this type of an album then this is the way to go, Shaw's burnished tones and Kenny Barron's exquisite comping a match made in heaven. All that now remains is for 32 Jazz to put out SETTING STANDARDS (which they promise is forthcoming) and Shaw's entire Muse catalog will be available for future generations to enjoy. A more befitting testimony no one could ask for!


text:
The great Mt. Pleasant debate
To the editor:
A few years ago, on a totally unrelated issue, the American people were told by a leader in the U.S. House of Representatives that, "We have to pass the bill so that you can find out what's in it." Maybe not the exact words, but it's close enough to get the point across.
In a letter to the editor, in the Mt. Pleasant News of Friday, May 16, 2014, Mr. Dave Helman makes this comment, in regards to reaction to the controversial measures being proposed by the MPCSD School Board and district administration, "A bond referendum is not even on the table. This bunch wants to kill any such initiative before it is even proposed by the school board."
The issue, call it a referendum or whatever you'd like, was on the table and proposed by the school board and district administration when information was first published in the Mt. Pleasant News. Like any other issue to be voted on, debate from both sides should be allowed and in fact, encouraged. Can it not be seen that the purpose for which information is published is so that debate can take place? The school board and district administration published the proposed changes with the hope of gaining the support of the community. Perhaps even getting it "passed" before it comes to a vote. Should not those in the community who oppose, not all the changes but at least some, also have the right to voice, publically, our opinions? Or, are we to vote these measures in and then discuss the details?
There are parts of the proposed changes that I support — air-conditioning the elementary schools is one. But there are much greater needs in our district for which the rest of the proposed $30 million spending plan could be used — getting our schools off of the "Schools in need of assistance" list, is just one.
I want the children of our community to be comfortable, at minimum physically, in our elementary classrooms, but I cannot and will not vote to approve $30 million in spending (read – property and other tax hikes) of which most will be on some seriously misplaced priorities.
I would encourage all parties to listen carefully to all sides of the debate. And please, all sides, let the debate continue!
Mike Scudder
Mt. Pleasant taxpayer


text:
Gafni Beats Out Litzman, Will Head Finance C'tee
Knesset Member Moshe Gafni will be the next chairman of the Knesset Finance Committee, the United Torah Judaism faction in parliament decided yesterday. The race had been between Gafni and the committee's former leader, Yaakov Litzman. The Finance Committee itself has to confirm the appointment next week.
Gafni won the support of two UTJ members besides himself, MKs Meir Porush and Uri Maklev. Litzman won the support of MK Eliezer Moses. In conversations prior to the vote, Litzman had indicated he thought Porush would support him, but Porush was nursing a beef over the fact Litzman hadn't thrown his support behind his bid for the Jerusalem mayoralty five months ago.
After the vote, Litzman stalked out of the party meeting and announced that he refused to serve as deputy health minister, the second executive position offered to UTJ, after the faction chose him for that post. It is expected that Moses will assume the position of deputy health minister.
The Finance Committee is one of the most important - and prestigious - of the Knesset panels. It is responsible for overseeing the budget, for one thing. Tax reforms also fall under its purview, as do laws pertaining to the banks and insurance sector.
The status of the committee chairman is equivalent to that of a minister. UTJ demands the position because its members are unwilling to fill ministerial seats - and because as committee leader, their man is positioned to persuade the treasury to provide more financing to yeshivas.
Gafni, 57, is married, with three children, and lives in Bnei Brak. He represents the Degel Hatorah faction of UTJ. He previously served as deputy minister of religious affairs and as the chairman of the Knesset Interior and Environment Committee. In 2002 Gafni won the Israel Union for Environmental Defense award for being the "greenest " MK, in recognition of environmental legislation he sponsored.
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text:
i picked this tea at NYC Coffee and Tea Festival yesterday. i did my little homework before i came and I was going to pick this tea. I have several Golden Monkey (Teavivre, H&S) and I wanted to compare.
Dry leaves: greenish with lots of gold silver and hairy. Teavivres are black and gold.
As usual gongfu treatment
1 heaping TBS 150ml gaiwan 195F( I did the same parameters as for Teavivre's GM, but the company suggests 212F) Maybe I'll try it next time
rinse 5/10/15/20/30/45/1
This tea is great. Rich and malty. Not as much chocolaty as Teavivre's. No sweet potatoes detected. But has grape notes and some slight sourness which is delightful. Some bread notes in later steeps.
To conclude, this tea is amazing. its quite different from Teavivre. And its a good thing. i wouldn't be happy to have identical teas in my overflowing cupboard. i picked only 1oz (surprisingly they had such small amount, other vendors were pushing a lot of tea on you). When I run out of it i will definitely pick some more.
Flavors: Baked Bread, Chocolate, Grapes, Malt


text:
Hamilton: Title fight more intense this year
20 August 2014 – Lewis Hamilton has said the title this season with Nico Rosberg is more intense than when he won it in 2008.
Hamilton took the crown that year in the final race at the final corner, when he passed Timo Glock, leaving him one point up on Felipe Massa.
However, he believes that season was relatively easy in one sense, as he wasn't battling with his team-mate in identical machinery.
"The battle does feel a lot more intense this year," Hamilton stated at a Puma Forever Faster PR event recently.
"When I was racing against [Kimi] Räikkönen and Massa [back in 2008], they were in a different team and their cars had different strengths and weaknesses to my car and, in my team, it was just me that was really competing with them.
"Now I'm racing against a guy who has the same car as me – we both have access to exactly the same data and feedback so it is really hard to try and be ahead.
"It's a little bit like playing poker - you have a set of cards and the other guy is not supposed to know what you got, but Nico and I can see each other's cards so then it's more difficult to beat each other."
"You have to find ways to create small margins," added the Englishman. "And so what you do is bring your skills, things that you've learned, things you can put into the mix.
"And you always have to move forward - you can't just be good and that will be enough, you have to keep pushing the boundaries, because every time you take a step forward the other guy makes an equal step so you have to keep doing it."


text:
WILMINGTON, NC (WHQR-FM) — You've heard it in 1D, now see it LIVE … in glorious 2D.
In this special staging of 'Wait Wait…Don't Tell Me,'host Peter Sagal and official judge and scorekeeper Carl Kasell will be joined by special guest Steve Martin and panelists Paula Poundstone, Mo Rocca,and Tom Bodett in front of a live audience.
Mayfaire Stadium 16 Cinema — Thursday, May 2 Live Simulcast at 8pm
Tuesday, May 7 Encore presentation at 7:30pm
WHQR will host special Meetups before the two showings at Towne Tap and Grill next door!
Join WHQR and other Wait Wait fans for delicious complimentary appetizers at 6:30pm on May 2 and 6pm on May 7. The event is complimentary – all you need to do is RSVP.


text:
What We Need in an AG
Mazuz's term as attorney general has given the impression that the attorney general's main focus was criminal law. But that's not the case.
Prime Minister Benjamin Netanyahu's decision to choose the next attorney general from the four candidates with the most support in the selection committee is justified. It's unfortunate, but Netanyahu is right in saying he sees no reason to appoint a new committee or consider new candidates who have not been discussed in depth by the committee or introduced to the public, as the current candidates have.
When the prime minister has to choose among the four people, clearly he'll pick the best person for the job. Menachem Mazuz's term as attorney general has seen serious indictments against senior government officials, which gave the impression that the attorney general's main focus was criminal law.
But that's not the case. Most of the attorney general's work is in constitutional, administrative and economic law, so in selecting a successor to Mazuz, the cabinet must choose the candidate who has proved the most knowledgeable in these fields.
Two years ago, when the selection committee for state prosecutor was considering candidates, this column said Yehuda Weinstein was the appropriate choice because of his professional standing over many years as a criminal defense attorney. But now a different post is in question, even if it holds ultimate responsibility for the State Prosecutor's Office.
Criminal law is in the hands of State Prosecutor Moshe Lador, who is a top expert on criminal matters and a public servant with integrity who has proved his independence by criticizing Justice Minister Yaakov Neeman's plan to split the functions of the attorney general. Appointing another criminal expert attorney general, while Lador continues at his post as state prosecutor, would create redundancy without a solid basis of knowledge and experience in public law: constitutional, administrative and economic.
Weinstein is among the four candidates chosen by the current selection committee. But it seems an expert should be chosen in the other areas of the attorney general's brief and that sole expertise in criminal law is not what is needed now.
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