text:
|Publication number
|Publication type
|Application number
|Publication date
|Aug 18, 1992
|Filing date
|Mar 22, 1991
|Priority date
|Mar 22, 1991
|Fee status
|Also published as
|Publication number
|Dirk J. Bartelink
|Original Assignee
|Hewlett-Packard Company
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (2), Referenced by (62), Classifications (25), Legal Events (4)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention relates to metal-oxide semiconductor devices and, more particularly, to vertical MOS devices and their fabrication. A major objective of the present invention is the fabrication of vertical CMOS components.
The rapidly expanding microelectronics industry continues to develop new technologies and process refinements, yielding extremely dense circuitry upon single semiconductor chips. The number of components that may be included on a single silicon integrated circuit nearly doubles every year. Advances in microelectronics have had a major impact on the size and cost of computer hardware. The increasing capacity of semiconductor memory devices has provided cheap, efficient means of accessing and storing large amounts of information. Further, the means to integrate a central processing unit on a single chip has allowed the incorporation of powerful computing systems in automobiles, appliances, and in home and office computers.
Several technologies exist for producing microelectronic circuits in semiconductor materials. Scientists first explored bipolar technology, using the operational principles of the original transistor, to create small-and medium-scale integrated circuit devices, each having upwards of 200 separate logical gates on a single silicon substrate. Metal Oxide Semiconductor technology (or MOS), while conceptually simpler than bipolar technology, did not emerge until later, because of material problems associated with making high-quality gate oxides.
The MOS fabrication procedure starts with a thin silicon wafer, from which each IC chip will be cut. The wafer is cut from a pure silicon crystal doped with impurities to be either a p-type or n-type material. P-type semiconductors possess an excess number of "holes", or positively-charged carriers. N-type semiconductors possess an excess number of electrons, or negatively-charged carriers.
Typically, the MOS transistor is laid out across the surface of the silicon wafer, which for this example will be of p-type silicon. Two n-type regions are formed in an upper silicon layer by diffusing impurities at specific areas on the silicon surface. These regions are usually referred to as the "source" and "drain" terminals of the device and are separated by a "channel" region, composed of the original p-type silicon material. A third terminal of the device, termed the "gate", comprises a layer of polycrystalline silicon (polysilicon) deposited on top of a thin (typically 100-200 Å thick) insulating layer of silicon dioxide. The gate is positioned directly over the channel region of the MOS transistor, and is normally heavily diffused with impurities so that it behaves as a good conductor.
The gate acts as one plate of a capacitor, while the relatively low-conductivity silicon channel acts as the other plate. A sufficiently positive potential applied to the gate electrode induces a negative charge in the silicon semiconductor and acts to repel the majority carrier (the holes) from the channel region's surface. As the potential applied to the gate increases, so too does the concentration of minority carrier electrons at the interface between the oxide and the silicon substrate and eventually this minority concentration becomes comparable with the density of majority carrier holes to produce what is termed an inversion layer. Since the inversion charge at the oxide-semiconductor interface provides a conductive channel between the source and drain, a potential difference applied between these two electrodes causes a current to flow between them. The device is then said to be in the ON state and the gate voltage required to allow conduction to occur is known as the threshold voltage. Prior to inversion, the channel is not formed, hence no current can flow, and the device is said to be OFF. The gate of a MOS transistor therefore acts as a switch, between the source and drain, which is open or closed depending on the voltage applied to the gate.
The MOS transistor is the central element in many integrated circuit applications, allowing electronics designers to cascade logical on/off devices by replicating and connecting together an array of MOS transistors across a silicon chip. An extremely important factor in the advancement of integrated circuit technology has been the scaling down of device dimensions. Until recently, the manufacturing penalty which has been required to achieve scaling reductions has been low and has been considerably outweighed by the resulting improvements in circuit performance. Stated algebraically, if all dimensions of a device are scaled by a given factor k, the scaling provides a k2 increase in devices on a given sized chip. The commonly-used constant field approach to scaling assumes that as the dimension scales so do all voltages (both supply and threshold voltages) within the circuit by the same ratio, so that the current in the chip will also be reduced by k and the power dissipated in each device by k2. Therefore the overall power consumption of a chip of given size remains unaltered. A further benefit of scaling is that individual gates operate k times faster. Therefore, the functional throughput of the chip (defined as the number of gates multiplied by the clock rate of the device divided by its power consumption) should scale as k3. Since functional throughput increases so dramatically while holding power requirements constant, there are enormous benefits gained from scaling MOS integrated circuits to ever smaller sizes.
Recently, however, production and material limitations have begun to hamper continual reduction of MOS circuit size. Several considerable production limitations involve the ability to fabricate structures reproducibly across a whole wafer as one shrinks each surface feature. Integrated circuits are laid out onto silicon wafers by photolithographic processes, whereby a succession of different photographic plates bearing the locations and sizes of individual features (for example, the source regions across a chip) are optically projected onto a wafer coated with photoresist. The photoresist hardens during subsequent processing in those places where it is exposed. These hardened areas form a mask for subsequent etching or impurity implantation steps. However, as the dimensions of IC devices approach the wavelengths used by the optical projectors, diffraction effects begin to blur fine circuit patterns, degrading manufacturing control. Hence the ability to define and resolve patterns of this size using conventional optical lithographic techniques ultimately becomes diffraction limited, such that continuously shorter wavelengths are needed.
Further, imaging individual patterns is itself not sufficient for the fabrication of a large scale integration (or LSI) chip; patterns must also be aligned (or registered) in the correct place relative to previous ones. For this reason the minimum linewidth that can be used for LSI chips is not the smallest that can be imaged onto a silicon wafer, but the smallest that can be controlled within critical tolerances. Typically, the mask for a single chip begins with a reticle plate containing an enlarged (perhaps by 5 times) image of the patterns appropriate to one layer on one chip. The image is then photoreduced and repeatedly stepped over a two-dimensional array to produce a final mask. A series of these masks are used to lay out each successive process step in the production of the completed integrated circuit. Registration can be improved by using single-chip masks and reduction-projection printers, which step the individual chip pattern over the entire wafer. These projection systems offer advantages (over prior full wafer printers) of higher resolution, better chip-by-chip alignment and less sensitivity to dust on the mask. However, they are more expensive, take longer to expose a wafer, and, ultimately, also suffer from alignment and resolution problems as the complexity in the number of masks (and integrated devices) increases and the size of individual device elements grows smaller. As circuit features shrink in size, the alignment, or registration, of successive patterns becomes increasingly difficult.
Self-alignment in semiconductor processing has been attempted to solve registration problems and limit the number of masks required. In a self-aligning process, certain features or spacers are created in the semiconductor wafer using conventional masks. Spacers may be created by forming a conformal deposit of an oxide or nitride, and then using an anisotropic etch to remove the deposit from horizontal areas but leave thin deposited spacers along vertical walls (for instance, the walls of a patterned photoresist mask). These spacers then function as a secondary mask in further processing steps. By using the spacer portions of the layout to mask other wafer areas, circuit features can be aligned to one another by a natural and accurate process. The number of masks required is also reduced. While widely used in MOS processing, self-alignment techniques are often limited to only suitable device designs, however, they still provide attractive methods for scale reductions.
In addition to problems inherent in the photolithographic methods of producing very large scale integrated (or VLSI) circuits, several fundamental material and device structure problems also limit the scale reductions of current MOS-technology ICs. As the channel length, the distance between the MOS transistor's source and drain regions, decreases, the depletion regions formed at the source-to-substrate and the drain-to-substrate p-n junctions begin to overlap. When this occurs, control of the device by the gate electrode is lost. The width of these depletion regions can be decreased by either reducing the circuit supply voltage or by increasing the substrate doping concentration. However, increasing the doping concentration also increases the electric field required at the gate to turn the MOS transistor on, and this field must be maintained below the breakdown field of the oxide layer separating the gate from the channel region. In addition, parasitic capacitance goes up, slowing circuit operation. Hot electron degradation has been perhaps the major limitation on scale-reductions in VLSI circuits. In order to avoid the onset of avalanche in MOS transistors, the electric field in the channel region must be maintained within certain limits. As channel length shrinks, channel voltage must therefore also decrease, leading to reduced current flow and slower circuit operation. However, in addition to these problems, the threshold operation voltage VT proves to be a fundamental limit to scaling of MOS transistor devices, preventing further decreases in voltage.
Another major problem in scaling MOS transistors results from the relationship of the channel region's depth to its length. As these two dimensions become comparable, current not only flows directly through the channel from source to drain, but also (at high enough electric fields) through the substrate, having deleterious effects on MOS operation. At small geometries and high terminal biases, some of the parasitic current can flow from the source to the drain, outside of the MOS channel. Under what is termed parasitic bipolar action, the source-to-substrate junction can then become forward biased, causing electrons to be injected into the substrate. Although much of the current will be collected by the drain, some will diffuse several hundred microns away and interfere with the operation of other parts of the circuit. Another deleterious effect of excess injected electrons is that of latch-up. Latch-up occurs where neighboring transistor areas form a parasitic NPNP diode. The NPNP diode can suddenly turn on by virtue of the parasitic current once current flow between the two transistor regions is made to cross a critical threshold, interrupting normal circuit operation, and even permanently damaging the circuitry.
To attempt to eliminate the spurious parasitic currents in MOS microelectronic circuits, attention has been placed on so-called silicon-on-insulator (or SOI) technologies. The motivating idea behind these new approaches is that of eliminating the portion of the silicon substrate which extends below the actual MOS transistor. Current in an SOI transistor would have nowhere else to flow but through the channel region itself. SOI technology isolates one circuit component from another by allowing the construction of each component in its own "island" of silicon. The various SOI techniques promise design and process simplicity, high circuit density and immunity from the effects of parasitic transistor activity. In addition, SOI technology promises to lessen the effects of hot electron degradation when scaling circuit devices to smaller dimensions.
One potential SOI technique employs a substrate of sapphire and is termed silicon-on-sapphire. The process involves depositing an epitaxial layer of silicon onto a single crystal sapphire surface such that single crystal growth of the silicon layer (necessary for transistor fabrication) is promoted. Epitaxial deposition refers to any process for growing single-crystal layers upon another substrate. While some success has been made with this technology, several significant problems exist. Namely, large thermal mismatches may exist between the sapphire substrate and the silicon layer, and the process yields a silicon layer with residual defects and lacking a unique orientation. Moreover, the cost of the sapphire outweights its advantages for most commercial applications.
Other SOI approaches have also been investigated. In one of these approaches, very large doses of oxygen or nitrogen are implanted at high energy to form a buried silicon oxide or nitride layer under the bulk silicon wafer surface. Promising results have been achieved using this approach, but optimization of the ion implantation process must be accomplished to reduce the implantation time and cost to an economic level. In another approach, a polycrystalline silicon layer is deposited onto an oxidized silicon wafer and then melted to recrystallize into a single-crystal device-usable form. A third approach attaches a silicon wafer, before the integrated circuits have been fabricated, to a new substrate and etches away part of the wafer, to insulate each eventual circuit from parasitic effects.
While all of the SOI approaches attempted so far show promise in solving some of the existing material problems such as parasitic current paths, none have as yet provided cost-effective, commercially viable techniques for reproducibly fabricating large scale integrated circuits. Bi-polar activity in SOI transistors can lead to a "kink" effect, whereby excess charge carriers can distort transistor characteristics and require complicated design changes. To eliminate the kink effect, SOI transistors often require an extra terminal to bleed parasitic charge away, which makes for bulkier circuitry. Ultrathin SOI transistors can encourage parasitic bipolar transistor snap-back action that degrades circuit operation; this effect can be reduced by very low voltage CMOS circuit design. None of these SOI techniques directly addresses the fabrication problems related to photolithography and registration of short channel transistors.
Another novel MOS approach creates a Surrounding Gate Transistor (or SGT). An SGT surrounds a vertical cylindrical channel with a gate layer. A drain electrode is placed on the top portion of the vertical channel and a source electrode surrounds the channel's base. By building a MOS device upwards, horizontal chip space may be saved while also limiting parasitic current flow. In addition, SGT technology may provide similar advantages as SOI methods for minimizing hot electron degradation effects. However, the SGT techniques may have difficulty controlling critical channel length dimensions, since these depend on etch-depth tolerances, and the techniques still require all the complex processing steps of conventional CMOS devices.
What is needed is an improved method and system for fabricating MOS integrated circuits which allows for increased miniaturization of individual circuit elements. More specifically, the method should resolve both the process problems of photolithographic circuit resolution and pattern registration and the material problems associated with the close proximity of conventional MOS devices, such as latch-up and parasitic current flows. In addition, the method should provide a simple and cost-effective technology for reliably producing VLSI integrated circuit chips.
In accordance with the present invention, a vertical MOS device comprises a vertical gate post rising and electrically insulated from a substrate, a channel layer connecting to the gate post, and a pair of source/drain layers occupying the upper and lower surfaces of the channel layer. To achieve the novel structure of the present invention, and improved MOS manufacturing process combines a deposition of variously doped silicon layers and etching through the silicon layers, using deposited spacers as masks, to form vertical MOS circuit components. The inventive method requires relatively few photolithographic masks, lessening registration and linewidth resolution requirements, and enabling smaller and more dense circuitry to be fabricated using current lithographic apparatus. Further, critical circuit parameters such as channel length may be determined by precise epitaxial deposition instead of lithographic dimensions, allowing for tighter transistor tolerances.
A first step in the method of the present invention involves fabricating a substrate with a series of uniformly layered vertical semiconductor depositions on its upper surface. In one embodiment, these depositions may be made with molecular beam or CVD epitaxy for improved layer control. A simple inverter formed of two vertical transistors will be used as a sample circuit to explain the general inventive principles. Starting with a thick p+ substrate, a p+ -n-p+ series of layers are deposited epitaxially (to form an eventual PMOS transistor), then a set of separation (or barrier) layers of n and p+ material, and then an n+ -p-n+ series of layers (to form an NMOS transistor). A "+" in the superscript of the layer doping indicates a heavier (or enhanced) doping, usually near saturation, and therefore greater than that of an un-superscripted layer (e.g. a p+ layer has a greater concentration of hole carriers than does a p layer).
In a second step of the method, a series of oxide and nitride spacers are deposited on the surface of the substrate, leaving exposed areas which will form the sites of posts around which annular vertically-spaced transistors will be constructed. To form the spacers, first a relatively thick layer of oxide is deposited upon the upper surface of the deposited substrate (the n+ layer). Photoresist is applied and exposed using a photolithographic mask, allowing regularly spaced square, rectangular or circular areas of the oxide layer to be etched away. A thin nitride spacer is formed by a conventional spacer fabrication process along the inner wall of each of these holes in the first oxide layer, and then another thin oxide spacer is deposited next to the nitride spacer, leaving a smaller square, rectangular or circular area of the upper n+ layer exposed at each post site.
In a third step, a central post that serves both to support the vertical transistors and also to apply gate voltages to each is constructed within the area left exposed in the second step. To create the central post, a hole is etched within the exposed area down to and partly into the first p+ substrate layer. Then, a thick layer of oxide is deposited into the bottom of the etched well, and a thin layer of oxide is formed along the walls. The thin oxide layer will provide the gate oxide separation layer for the two vertical transistors. The hole is then filled with a conductive material such as polycrystalline silicon up to the oxide spacer and is topped off by a nitride layer which connects to the nitride spacer, essentially burying the oxide spacer.
In a fourth step, the first, upper vertical transistor is constructed out of the top three epitaxial layers. As a preliminary step, the exposed oxide layer which had formed the initial mask for constructing the gate posts is removed. Next, using the nitride spacer left exposed as a mask, a trench is etched vertically through the uppermost n+ layer, the next p layer and into the next n+ layer. Thermal oxidation then forms a thin protective oxide coating on the exposed face of the upper NMOS vertical transistor. A second nitride spacer is deposited next to the first nitride spacer and down across the back face of the NMOS transistor, and an anisotropic vertical etch removes the bottom oxide layer to allow for further vertical etching.
In a fifth step, the barrier layer separating the two transistors is removed. Using the second nitride spacer as a mask, a deeper trench is etched through the lower n+ layer of the upper vertical transistor, through the p+ barrier layer and into the n barrier layer. A third nitride spacer layer is deposited next to the second spacer, and the bottom layer of nitride is removed. A wet, dopant-sensitive etch removes the entire n barrier layer everywhere. A thin oxide layer is thermally grown along the exposed portions between the two transistors and the volume between them is then filled with a thicker oxide, the face of which is covered by a fourth nitride spacer.
In a sixth step, the second transistor is fabricated. A silicon anisotropic etch, using the fourth nitride layer as a mask, cuts a trench through the p+, n and into the bottommost p+ layer to form the lower PMOS transistor. An oxide layer is then formed on the face of the exposed silicon layers of the lower transistor.
In a seventh step, the substrate and its array of vertical transistors surrounding isolated posts is cleaned up through several etchings, and metal connections are attached. First, all nitride layers and spacers are removed. Then a vertical anisotropic etch removes any oxide layers on the horizontal silicon surfaces, allowing electrical and mechanical connection between a metal deposition, such as a selective tungsten deposition, and the exposed shelves of each transistor (including the top surface of the polycrystalline gate post). The volume between each inverter "island" (comprising a gate post surrounded by two vertical annular transistors) can be filled with a dielectric material. This dielectric material is then etched to form steps. Various interconnections between transistors can be laid along these steps in order to construct complex digital circuitry.
The present invention provides a novel and efficient approach for fabricating very large scale integrated circuits. Using only one lithographic mask, the process allows extremely tight spacing of individual circuit elements without sacrificing circuit performance. The placement and size of the central gate post, the principal feature of the lithographic mask, determines the spacing and size of each transistor across the wafer. Having only one processing mask (other masks may be employed later for constructing the metal wire interconnects) reduces considerably the registration problems inherent in multiple-mask approaches, while also reducing the device area consumed by source, drain and gate areas. The present invention provides a fabrication technique well-suited for single wafer processes currently being implemented, often in cluster tool fabrication systems.
In addition, the unique vertical arrangement of the individual transistors allows the nitride and oxide spacers to function as process masks, accurately and uniformly configuring each transistor's channel depth, while precise epitaxial deposition of the channel layer determines channel length. Further, the vertical construction of each transistor provides the operational characteristics of silicon-on-insulator technology, since each channel annular region has a "bottom" portion (in the described configuration, actually the sides of the channel region) connected only to the dielectric fill material, minimizing possible parasitic current paths. By having the NMOS and PMOS transistors occupying the same wafer area, circuit density can be greatly increased.
The width of the channel region in the present invention runs all the way around the transistor annulus. Thus, the channel width for transistors constructed according to the present invention can be at least four times as wide as the channel width of prior MOS transistors, for the same relative transistor width. The increased channel width provides improved transistor characteristics and operating stability and the annular shape eliminates channel edge effects. These and other features and advantages of the present invention are apparent from the description below with reference to the following drawings.
FIGS. 1A through 1S shown cut-away views representing stages in the fabrication of a vertical CMOS device in accordance with the present invention.
FIG. 2 shows a cut-away view of a vertical CMOS inverter device and its associated metallic traces and via in accordance with the present invention.
FIGS. 3A and 3B illustrate an upper view and an electrical schematic diagram, respectively, of an electrical inverter incorporating vertical CMOS devices in accordance with the invention.
In accordance with the present invention, a method for fabricating vertical CMOS electrical components is illustrated in FIGS. 1A through 1S. FIG. 1A presents the starting point for the present invention and reveals a silicon wafer 10 in cross-section containing a series of alternately doped silicon layers. The first p+ layer 12 is a relatively thick silicon wafer and forms the structural substrate for the circuit components to be constructed. The wafer's thickness depends upon the structural characteristics required and upon the diameter of the wafer used. Next, a series of silicon layers are epitaxially deposited on top of the substrate p+ layer 12. First, a thin p+ layer 14 (˜0.03 μms),a somewhat thicker n layer 16 (˜0.1 μms)and another thin p+ layer 18 (˜3.03 μms) are deposited. The p+ -n-p+ layer series, subject to further fabrication steps, will form the first vertical transistor above substrate 12. The n middle layer 16 functions as the first transistor's channel layer, while the first and second p+ layers 14, 18 may function as source or drain layers, depending upon eventual circuit connections. For this reason, they will be termed source/drain layers for the remainder of the description.
Next, a thicker n layer 20 (˜0.3 μms) is deposited followed by another thin p+ layer 22. These two layers separate the two vertical transistors from one another and are useful for several of the subsequent processing steps. Finally, the second vertical transistor region is formed by epitaxially depositing an n+ source/drain layer 24, a p channel layer 26 and another n+ source/drain layer 28, the layers approximately duplicating the layer thicknesses chosen for the first transistor. In the present embodiment, the substrate layer 12 and the first source/drain layer 14 are both of p+ semiconductor material, but this is not necessary and various other combinations are also possible. In addition, the substrate serves as a power supply connection VDD to the circuitry.
A thick oxide layer 30 (approximately 0.5 to 1.0 μms), deposited over the top n+ layer 28, is masked and etched to form an aperture 32 approximately 1.0 μms wide, extending down to upper n+ layer 28, as shown in FIG. 1B. Nitride is deposited along the inner wall of aperture 32 to form a first nitride spacer 34, approximately 500 Å wide. Oxide is deposited next to the first nitride spacer 34, to form an oxide spacer 36, also approximately 500 Å wide. All spacers used in the preferred embodiment are formed in the same way. First, a conformal (or isotropic) deposition of the particular material leaves a constant thickness of material, for example nitride, everywhere, especially down the face of a stair-step. In the present instance, the stair-step would comprise the inner wall of aperture 32. Second, an anisotropic vertical etch removes all material along exposed horizontal portions of the wafer, leaving most of the spacer intact along the wall of the stair-step.
Using the collection of oxide layer 30, nitride spacer 34 and oxide spacer 36 as a mask, a hole 38 is cut through aperture 32, through all of the epitaxially-deposited layers 14 through 28 and into the substrate layer 12, as illustrated in FIG. 1C. Any anisotropic silicon etching process may be employed to cut hole 38. Using electron cyclotron resonance deposition (ECR), or other similar anisotropic deposition techniques, the bottom portion of the hole is filled with an oxide deposit 40 to a depth of about 0.15 μms, depending on the depth of the etch, so that its top edge aligns closely with the top of layer 12, as seen in FIG. 1D. An isotropic clean-up etch removes any oxide left on the side-walls of hole 38. Then, using a furnace or rapid thermal process (RTP), a thin layer of high-quality gate oxide 42 is grown along the walls of hole 38. As familiar to the art, the oxide deposit may be accomplished by raising the substrate to a carefully controlled temperature of approximately 800� C. in an oxygen environment. RTP can raise substrate temperature while avoiding substantial interdiffusion of the epitaxial layers.
Hole 38 is next filled with polysilicon doped with enough impurities to function as a highly-conductive gate post 44. A chemical vapor deposition (CVD) process may be used to fill hole 38 with the polysilicon. The polysilicon of gate post 44 is etched back so that its upper edge 45 locates near the center of oxide spacer 36, but above the upper n+ layer 28. The remaining depression in hole 38 is filled with a nitride layer 46 by depositing a layer of nitride across the wafer, and then etching the nitride back (with a resist etch-back process) so that it just fills the depression left in hole 38.
The original oxide layer 30 is removed from the top of wafer 10 using an oxide-selective etch (such as applying hydrofluoric acid) leaving the faces of the first nitride spacer 34 exposed, as revealed in FIG. 1F. Next, a vertical silicon etching process etches a trench 48 into the epitaxial layers, using the first nitride spacer 34 and nitride layer 46 as a mask. End-point detection, which is sensitive to dopant concentration of the current etch layer, allows the vertical etching process to end on a particular layer. In the first trech etching, the process ends on or in n+ layer 24, as shown in FIG. 1G. The exposed faces of n+ layer 28, p layer 26 and n+ layer 24 are then coated with a thin protective oxide layer 50 using a rapid thermal oxidation process.
A second nitride spacer 52 is applied to the exposed side of first nitride spacer 34, and down the vertical faces of the first transistors layers 28, 26 and 24. The remainder of the exposed oxide layer 50 is then removed, as shown in FIG. 1H, re-exposing n+ layer 24. Using the second nitride spacer 52 as a mask, a second trench 54 is etched through the n+ layer 24, p+ buffer layer 22 and into the n buffer layer 20, as illustrated in FIG. 1I. A third nitride spacer 56 is deposited along the side of second nitride spacer 52 and the exposed vertical faces of layers 24, 22 and 20, and any remaining nitride left on the exposed horizontal areas of n layer 20 is removed as shown in FIG. 1J. A dopant-selective wet etch then removes the entire n layer 20 up to oxide layer 42 surrounding polysilicon gate post 44. The resulting structure is shown in FIG. 1K. Thermal oxidation applies a thin oxide layer 58 on all exposed silicon and a second oxide deposition 60 fills in the cavity left between the first and second transistor layers (i.e. between layers 22 and 18). Oxide depositions 58 and 60 are then etched back anisotropically, using third nitride spacer 56 as a mask, allowing the next p+ layer 18 to be exposed, as shown in FIG. 1L.
Next, a fourth nitride spacer 62, deposited against the third nitride spacer 56, extends downwards against oxide deposition 60 to p+ source/drain layer 18, as shown in FIG. 1M. Using fourth nitride spacer 62 as a mask, an anisotropic etch excavates a third trench 64 extending through the p+ source/drain layer 18, through n channel layer 16 and into p+ source/drain layer 14, as shown in FIG. 1N. Again, thermal oxidation deposits a thin oxide layer 68 over the exposed vertical faces of the second transistor layers 14, 16 and 18 and over the exposed horizontal face of layer 14 as illustrated in FIG. 1P.
Removing, through appropriate etches, all nitride spacers 34, 52, 56, and 62 and nitride layer 46 leaves the structure as seen in FIG. 1Q. An anisotropic etch removes oxide layer 50a (the suffix "a" denotes the horizontal components of this conformal oxide layer 50) on the horizontal silicon surface of layer 24, shown in FIG. 1R. Finally, a metal connection 70 of tungsten is grown on the exposed horizontal ledges of all silicon areas (silicon layers 18, 24, and 28 and the upper surface 45 of polysilicon gate post 44). The original oxide spacer 36 prevents the connection 70a on gate post 44 from connecting with electrical connection 70b on upper source/drain layer 28 of the upper vertical transistor. The resulting arrangement is revealed in FIG. 1S.
The fabrication of the vertical CMOS inverter is now essentially complete. As shown in FIG. 1S, vertical polysilicon gate post 44 rises from the silicon substrate 12 surrounded by two transistors T1 and T2. The individual layers of each vertical transistor surround the vertical gate post 44 and mirror its geometry. For instance, if the gate post 44 were round, the transistors and their layers would have a round annular geometry; if the gate post were square, the transistor layers would have a square annular geometry (annular in this context describes an enclosed region having a smaller central portion removed of the same boundary shape). Transistor T1 comprises p+ source/drain layer 14, n channel layer 16 and p+ source/drain layer 18, and their associated connections 70a, 70d and substrate layer 12. Transistor T2 comprises n+ source/drain layer 24, p channel layer 26 and n+ source/drain layer 28, and their associated connections 70a, 70b and 70c.
The channel length, the distance between the two source/drain layers of an individual transistor, is determined in the preferred embodiment by the epitaxial layer thickness, not the placement and resolution of a photolithographic mask. Epitaxial deposition allows for much tighter control over this thickness and therefore over transistor operational characteristics. In addition, by orienting the transistor vertically, in contrast to conventional horizontal technology, and removing any silicon material from the underside of the channel (that portion below the source/channel/drain regions of a conventional MOS transistor and opposite the gate) any path for spurious parasitic current to flow is removed as with SOI transistors. Hence, the present novel approach furnishes greater control over transistor operation. The gaps left in the substrate from the trench-etching operations may be filled with a dielectric material, thereby covering the underside of the channel region with an insulator and yielding true silicon-on-insulator transistors.
To create a usable integrated circuit, one needs to connect the two transistors to each other, to other transistors and circuit elements on the chip, and/or to connections with the outside world. To accomplish this, a series of steps selectively fill the open areas between the gate post/transistor "islands" and other deposited vias (electrical posts that penetrate multiple layers in the substrate) with a dielectric material, and etch the dielectric fill to particular levels to lay down metal interconnections. To illustrate the procedures, FIG. 2 shows one-half of the previously-constructed vertical gate post 44 and transistors T1 and T2.
The first step in the connection procedure consists of filling the substrate up to above top layer 28 with a dielectric material 76 such as an oxide. A first interconnect mask is used to pattern via 72, which is etched partway to layer 14 leaving oxide insulation layer 68a. Via 72 is then filled with a tungsten plug using a blanket deposition of tungsten which then is etched back. A second interconnect mask is employed to expose a portion of the dielectric material around gate post 44 (and transistors T1 and T2) and via 72. The outline of the masked area can be seen as area W1 in the plan view of the inverter shown in FIG. 3A. In FIG. 3A, the inverter island comprises a square vertical gate post 44 surrounded by the stacked, square annular transistors T1 and T2 as previously described. The upper surface of gate post 44 has the metallic connection 70a attached, as shown in FIG. 2. After the area W1 is exposed by the mask, the dielectric is etched down to the level of source/drain layer 18 of transistor T1, forming a shelf 78 running from connection 70d on source/drain layer 18 to via 72. Before removal of the second interconnect mask, a silicon implantation into the shelf 78 creates a nucleation layer for selective tungsten deposition.
The second interconnect mask is removed and a third interconnect mask is applied, this time exposing area W2 in FIG. 3A. The dielectric layer 76 is etched in area W2 down to the level of source/drain layer 24 of transistor T2, exposing a shelf 80 of dielectric running from connection 70c to via 72. Once these shelves 78 and 80 are exposed and implanted with silicon, a second metal deposition forms connections W1 and W2 from the inner source/drain layers 18 and 24 of transistor T1 and T2 to via 72, effectively connecting these closest layers of the two transistors together. After these connections have been made, the trenches left in the dielectric layer 76 may be refilled to provide a solid substrate.
A final masking step constructs a top-level connection W3, from the top source/drain layer 28 of transistor T2 to another via 82, which connects the transistors to ground as shown in FIGS. 3A/B. Top-level metallic trace can then be fabricated to connect the output via 72, the input connection 70a for gate post 44, and the ground via 82 to appropriate other portions of the integrated circuit. The resulting schematic for the inverter may be seen in FIG. 3B, where appropriate physical portions of the circuit are also noted. In the present embodiment, substrate 12 provides the VDD voltage for circuit operation, through its direct connection with first transistor layer 14. As can be seen in FIG. 3A, if the physical area of the gate post 44 determines the fundamental feature size of the integrated chip, the entire inverter requires only two features by six features for fabrication, significantly reducing the horizontal room required per inverter.
Although the present description focused on an inverter element comprising two transistors and associated vias, the present invention may be adapted to a wide variety of circuit designs. Each different circuit embodiment depends only upon how the individual connections W are formed between each transistor layer. For example, one transistor of the vertical pair may remain unconnected, using only one of the vertical transistors from each gate post. Or, the transistors between gates may be connected in much more complicated ways to achieve circuit design goals as understood by those skilled in the art of integrated circuitry. Further, it is not necessary to fabricate two stacked transistors on top of one another. If only one vertical transistor is required, layers 20 through 28 need not be deposited and the process may be followed by depositing the oxide layer 30 onto the now upper source/drain layer 18, and proceeding with the remainder of the process steps. Or, three or more transistors may be fabricated as necessary for circuitry designs. Also, the vertical transistors need not completely encircle the central gate post, but can be further patterned. Thereby, several individual transistors at the same level can be formed, each transistor only partially surrounding the gate post. And, as described, the substrate need not provide VDD for circuit operation, and the vertical transistors need not directly contact the substrate. These and other variations upon and modifications to the described embodiments are provided for by the present invention, the scope of which is limited only by the following claims.
|Cited Patent
|Filing date
|Publication date
|Jun 8, 1984
|Nov 11, 1986
|Eaton Corporation
|Lateral bidirectional power FET with notched multi-channel stacking and with dual gate reference terminal means
|Aug 24, 1988
|Aug 21, 1990
|Harris Corporation
|Trench gate VCMOS
|Citing Patent
|Filing date
|Publication date
|Jun 17, 1992
|Feb 1, 1994
|International Business Machines Corporation
|Vertical gate transistor with low temperature epitaxial channel
|Jun 22, 1992
|May 3, 1994
|Motorola, Inc.
|Self-aligned thin film transistor
|Nov 22, 1991
|May 10, 1994
|Kabushiki Kaisha Toshiba
|Semiconductor vertical MOSFET inverter circuit
|Feb 23, 1994
|Dec 20, 1994
|Motorola, Inc.
|Method of forming a self-aligned thin film transistor
|Mar 5, 1996
|Nov 18, 1997
|International Business Machines Corporation
|Vertical double-gate field effect transistor
|Sep 28, 1995
|Jan 6, 1998
|Motorola Inc.
|Method for forming trench transistor structure
|Jul 18, 1997
|Jul 7, 1998
|Hewlett-Packard Company
|Vertical CMOS digital multi-valued restoring logic device
|Apr 16, 1997
|Jul 14, 1998
|International Business Machines Corporation
|Vertical double-gate field effect transistor
|Sep 28, 1995
|Mar 9, 1999
|Motorola Inc.
|Trench random access memory cell and method of formation
|Jul 18, 1997
|Mar 23, 1999
|Motorola, Inc.
|Trench transistor structure comprising at least two vertical transistors
|Jul 18, 1997
|Mar 14, 2000
|Motorola, Inc.
|Method for growing an epitaxial layer of material using a high temperature initial growth phase and a low temperature bulk growth phase
|Feb 29, 2000
|Sep 25, 2001
|Micron Technology, Inc.
|Circuits and methods using vertical complementary transistors
|Feb 24, 1998
|Oct 16, 2001
|Micron Technology, Inc.
|Circuits and methods for a static random access memory using vertical transistors
|Aug 24, 1998
|Feb 26, 2002
|Micron Technology, Inc.
|Memory cell having a vertical transistor with buried source/drain and dual gates
|Feb 4, 2000
|Apr 30, 2002
|Micron Technology, Inc.
|Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
|Jun 5, 2000
|May 21, 2002
|Fairchild Semiconductor Corporation
|Method of manufacturing a trench MOSFET using selective growth epitaxy
|Jun 16, 2000
|Jun 4, 2002
|Micron Technology, Inc.
|Memory cell having a vertical transistor with buried source/drain and dual gates
|Jul 27, 2001
|Jul 9, 2002
|Micron Technology, Inc.
|Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
|Jul 27, 2001
|Aug 6, 2002
|Micron Technology, Inc.
|Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
|Jul 27, 2001
|Aug 13, 2002
|Micron Technology, Inc.
|Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
|Aug 8, 2001
|Sep 10, 2002
|Micron Technology, Inc.
|Circuits and methods for a static random access memory using vertical transistors
|Feb 22, 2000
|Oct 15, 2002
|Micron Technology, Inc.
|Method of fabricating a semiconductor-on-insulator memory cell with buried word and body lines
|May 16, 2000
|Nov 5, 2002
|Micron Tecnology, Inc.
|4 F2 folded bit line dram cell structure having buried bit and word lines
|Aug 8, 2001
|Nov 5, 2002
|Micron Technology, Inc.
|Circuits and methods for a static random access memory using vertical transistors
|Mar 8, 2000
|Nov 26, 2002
|Micron Technology, Inc.
|Field programmable logic arrays with vertical transistors
|Jan 8, 2001
|Nov 26, 2002
|Micron Technology, Inc.
|Programmable logic array with vertical transistors
|Aug 30, 2000
|Dec 24, 2002
|Micron Technology, Inc.
|Memory address decode array with vertical transistors
|Jan 8, 2001
|Feb 4, 2003
|Micron Technology, Inc.
|Programmable logic array with vertical transistors
|Dec 20, 2000
|Mar 25, 2003
|Micron Technology, Inc.
|Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
|Aug 27, 2001
|Apr 29, 2003
|Micron Technology, Inc.
|Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits
|Feb 6, 2002
|Jun 10, 2003
|Fairchild Semiconductor Corporation
|Trench MOSFET formed using selective epitaxial growth
|Sep 26, 2000
|Jul 22, 2003
|Micron Technology, Inc.
|Programmable memory address decode array with vertical transistors
|Aug 27, 2001
|Jan 6, 2004
|Micron Technology, Inc.
|Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits
|Sep 21, 2001
|Feb 3, 2004
|Agere Systems Inc.
|Multiple operating voltage vertical replacement-gate (VRG) transistor
|Mar 17, 2000
|Feb 10, 2004
|Micron Technology, Inc.
|4 F2 folded bit line DRAM cell structure having buried bit and word lines
|Nov 26, 2002
|Jun 8, 2004
|Micron Technology, Inc.
|Memory address decode array with vertical transistors
|Feb 4, 2003
|Jun 8, 2004
|International Business Machines Corporation
|Vertical gate conductor with buried contact layer for increased contact landing area
|Apr 17, 2000
|Jul 20, 2004
|Micron Technology, Inc.
|Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
|Dec 26, 2001
|Aug 10, 2004
|Agere Systems Inc.
|CMOS vertical replacement gate (VRG) transistors
|Feb 11, 2003
|Sep 28, 2004
|Micron Technology, Inc.
|Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
|Aug 28, 2002
|Nov 2, 2004
|Micron Technology, Inc.
|Field programmable logic arrays with vertical transistors
|Jun 4, 2002
|Nov 16, 2004
|Micron Technology, Inc.
|Memory cell having a vertical transistor with buried source/drain and dual gates
|Dec 16, 2003
|May 23, 2006
|Micron Technology, Inc.
|Vertical gain cell and array for a dynamic random access memory and method for forming the same
|Oct 14, 2003
|Jun 6, 2006
|Agere Systems Inc.
|Multiple operating voltage vertical replacement-gate (VRG) transistor
|Jun 29, 2004
|Jun 6, 2006
|Micron Technology, Inc
|Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
|Aug 30, 2005
|May 29, 2007
|Micron Technology, Inc.
|Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
|Jul 11, 2006
|Aug 5, 2008
|Micron Technology, Inc.
|Device, system, and method for a trench capacitor having micro-roughened semiconductor surfaces
|Jul 19, 2005
|Aug 25, 2009
|Samsung Electronics Co., Ltd.
|Semiconductor device having a channel pattern and method of manufacturing the same
|Jan 16, 2008
|Apr 19, 2011
|Cadence Design Systems, Inc.
|Spacer double patterning for lithography operations
|Oct 5, 2005
|May 29, 2012
|X-Fab Semiconductor Foundries Ag
|Method for the construction of vertical power transistors with differing powers by combination of pre-defined part pieces
|Sep 23, 2010
|Oct 2, 2012
|Cadence Design Systems, Inc.
|Spacer double patterning for lithography operations
|May 18, 2012
|Jul 29, 2014
|X-Fab Semiconductor Foundries Ag
|Method for the construction of vertical power transistors with differing powers by combination of pre-defined part pieces
|Jun 12, 2015
|May 16, 2017
|Eastman Kodak Company
|Bottom-gate and top-gate VTFTs on common structure
|Dec 26, 2001
|Jun 26, 2003
|Sailesh Chittipeddi
|CMOS vertical replacement gate (VRG) transistors
|Feb 11, 2003
|Jul 31, 2003
|Micron Technology, Inc.
|Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
|Dec 16, 2003
|Jul 8, 2004
|Micron Technology, Inc.
|Vertical gain cell and array for a dynamic random access memory and method for forming the same
|Oct 14, 2003
|Mar 3, 2005
|Layman Paul Arthur
|Multiple operating voltage vertical replacement-gate (VRG) transistor
|Jul 19, 2005
|Jan 26, 2006
|Jae-Man Yoon
|Semiconductor device having a channel pattern and method of manufacturing the same
|Oct 5, 2005
|Oct 2, 2008
|X-Fab Semiconductor Foundries Ag
|Method for the Construction of Vertical Power Transistors with Differing Powers by Combination of Pre-Defined Part Pieces
|Jul 20, 2005
|Jul 2, 2009
|Avraham Frenkel
|Ballistic Protective Radome
|Sep 23, 2010
|Jan 20, 2011
|Christophe Pierrat
|Spacer double patterning for lithography operations
|Jan 16, 2008
|Jan 27, 2011
|Christophe Pierrat
|Spacer double patterning for lithography operations
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Oct 28, 1991
Owner name: HEWLETT-PACKARD COMPANY A CA CORPORATION, CALIF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:BARTELINK, DIRK J.;REEL/FRAME:005886/0925
Effective date: 19910315
|Mar 26, 1996
|Maintenance fee reminder mailed
|Aug 18, 1996
|Lapse for failure to pay maintenance fees
|Oct 29, 1996
|Expired due to failure to pay maintenance fee
Effective date: 19960821


text:
By using this site, you agree to the IDC Privacy Policy
15 Jun 2017
NEW DELHI, June 15th, 2017 - According to the latest IDC Worldwide Quarterly Wearable Tracker, CY Q1 2017 saw total shipments of 612K units of wearables in India, which includes smart wearables, that can run third-party apps, and basic wearables which cannot run third-party apps.
In terms of product category, basic wearables accounted for almost 90 percent of total wearable shipments in Q1 2017. Celso Gomes , Associate Market Analyst, Client Devices, IDC India says "In addition to the low entry price of basic wearables, consumers are now getting better value from these devices as the category now offers advanced features. Features such as heart rate, sleep monitor and among others are soon becoming the must-have features in basic wearables, even in entry level (<US$50) segments."
Less than US$50 segment continues to dominate the category accounting for 78.6 percent of total wearable shipments in CY Q1 2017. This entry level segment is led by GoQii followed by Xiaomi. "New entrants like Titan, with aggressive marketing, have entered Indian wearable market in March further increasing the competition in this highly cluttered entry-level segment," adds Gomes.
The offline share of wearables shipments stood at 36.2 percent in Q1 2017 up from 24.3 percent over the same period last year. The offline share has improved over the last couple of quarters and is expected to grow even further. Key new entrants like Fossil, Titan, etctera have entered the Indian wearable market primarily through retail stores. In addition, certain online vendors like Xiaomi and GoQii are also exploring offline channels to expand their customer base and enhance their presence.
Vendor Highlights:
GOQii maintains its leadership in the Indian wearable market with 20.8 percent share. GOQii shipments increased 21.0 percent sequentially in CY Q1 2017 driven by fresh demand for its newly launched GoQii HR and promotional upgrade offer. It is gradually migrating from online only to hybrid channel to increase its offline presence.
Xiaomi slipped to the second position with 10.1 percent vendor share as shipments declined 30.6 percent in Q1 2017 over the previous quarter. Increasing competition and limited supply of Mi Band 2 in Q1 2017 led to the decline of Xiaomi's share in Indian wearables market.
Fitbit maintained its third place in CY Q1 2017 even though shipments declined 42.7 percent sequentially. Newly launched Alta HR helped offsetting volume of earlier Alta shipments. New lineup of product launches in the coming quarter to prepare for the festive season are expected to revive the vendor's shipments.
IDC India Forecast:
Wearable market is expected to grow at a double-digit in CY Q2 2017. To further intensify competition, few new vendors primarily China-based are expected to make inroads into Indian wearable market especially in sub US$50 segments. "Currently, primary use-case of wearables are focused on the specific niche market like fitness and health. Hence, to sustain volume and existence in long run, wearables should evolve to appeal to a wider consumer segment resulting in either to be a mainstream device or an essential product of a broader ecosystem." says Navkendar Singh, Senior Research Manager, IDC India. Singh adds "Like IoT vendors, the wearables market should differentiate themselves either in terms of service offered with the product or its product features to enhance the scope of the market"
For more information on the India wearables market, please contact Navkendar Singh email@example.com or Celso Gomes email@example.com. For press inquiries, please contact Shreya Jain at firstname.lastname@example.com.
About IDC Trackers
IDC Tracker products provide accurate and timely market size, vendor share, and forecasts for hundreds of technology markets from more than 100 countries around the globe. Using proprietary tools and research processes, IDC's Trackers are updated on a semi-annual, quarterly, and monthly basis. Tracker results are delivered to clients in user-friendly excel deliverables and on-line query tools. The IDC Tracker Charts app allows users to view data charts from the most recent IDC Tracker products on their iPhone and iPad.
About IDC
International Data Corporation (IDC) is the premier global provider of market intelligence, advisory services, and events for the information technology, telecommunications, and consumer technology markets. With more than 1,100 analysts worldwide, IDC offers global, regional, and local expertise on technology and industry opportunities and trends in over 110 countries. IDC's analysis and insight helps IT professionals, business executives, and the investment community to make fact-based technology decisions and to achieve their key business objectives. Founded in 1964, IDC is a subsidiary of IDG, the world's leading technology media, research, and Events Company. To learn more about IDC, please visit www.idc.com. Follow IDC on Twitter at @IDC.
All product and company names may be trademarks or registered trademarks of their respective holders.
Xiaomi Inc., Fitbit, Inc., GoQii Inc.

subset: commoncrawl


text:
Contact: Erica Loftus, President/CEO
Phone: 724.775.3944
Email: firstname.lastname@example.com
BEAVER, PA, October 1, 2013 – The Beaver County Chamber of Commerce announces today the launch of their new logo and tagline. The objective of the logo image was to develop a fresh, modern design supportive of the organization's new strategic plan, adopted in January 2012. We also wanted to develop a tagline that concisely communicated our renewed dedication to growth and opportunity. Following a three-month review and revision process, we believe that our new logo and tagline design will sustain us for the next decade.
The logo is built around geographic images of Beaver County, representing our singular focus on the communities we call home. The four iconic map images converge to represent Opportunity, Partnership, Growth, and Progress. Stylistically, the key graphic "icon" provides an unmistakable connection to Beaver County. Together, the four map-like elements also converge to reference a large "B."
The Chamber's new tagline, "Business@Work. Partners in Progress." succinctly communicates the Chamber's principal mission and one of the intrinsic, unyielding attributes of Beaver County residents. Our legacy is that of hard-working individuals and business investment, forged together through collaboration and partnership. With a renewed focus, the Chamber will honor that legacy in the years ahead.
About the Beaver County Chamber of Commerce:
The Beaver County Chamber of Commerce is comprised of 530 member companies and is focused on supporting the growth and improvement of our local economy. Our mission is to prepare, develop and promote the community for economic growth. Our vision is to strengthen local businesses so that Beaver County will be the premiere place to live and work in the region and beyond. For more information about the Beaver County Chamber of Commerce, please visit our website at www.bcchamber.com or visit our Facebook page at The Beaver County Chamber of Commerce. You can also find us on LinkedIn if you search Beaver County Chamber of Commerce or onTwitter by searching @TheBCCC.


text:
Article 450 in the National Electrical Code (NEC) covers requirements for transformers. The scope of Article 450, located in 450.1, states that it covers the installation of all transformers, but there are eight exceptions. Some of the transformers not covered include current transformers; transformers that are an integral part of an X-ray, high-frequency or electrostatic-coating apparatus; transformers used with Class 2 and Class 3 circuits that comply with Article 725; transformers for sign and outline lighting that comply with Article 600; and transformers for electric-discharge lighting that complies with Article 410. In accordance with 450.3, overcurrent protection of transformers shall comply with 450.3(A), (B) or (C).
Table 450.3(B) shows the maximum rating or setting of overcurrent protection for transformers 1,000 volts (V) and less. The table shows ratings or settings as percentages of transformer-rated current, and it displays percentages in two rows. Use the top row when overcurrent protection will only be installed on the primary side of the transformer. In accordance with the top row, secondary protection is not required so long as the primary protection does not exceed the percentages (and notes) shown in Table 450.3(B). For example, a 75-kilovolt-ampere (kVA), three-phase transformer will be installed. The transformer's primary-side voltage will be 480V. Secondary protection for this transformer will not be installed. What is the maximum size (rating) fuse that can be installed on the primary side of this transformer so that secondary overcurrent protection will not be required?
The transformer-rated current on the primary side will be 90 amperes (A) (75,000 ÷ 480 ÷ 1.732 = 90.2 = 90). The primary protection percentage for a transformer having a current draw of 90A or more is 125 percent. After multiplying by the primary protection percentage, the current is 113A (90 × 125 percent = 112.5 = 113).
While the title of this table states that these are the maximum ratings, there is a note beside the primary protection percentage. Below Table 450.3(B), Note 1 states that, where 125 percent of the current does not correspond to a standard rating of a fuse or nonadjustable circuit breaker, a higher rating that does not exceed the next higher standard rating shall be permitted. Standard ampere ratings for fuses and fixed-trip circuit breakers are in 240.6. The next standard rating above 113 is 125. Therefore, the maximum size fuse that can be installed on the primary side of this transformer is 125A (see Figure 1).
Use the bottom row of Table 450.3(B) when overcurrent protection will be installed on the primary side and the secondary side of the transformer. For example, a 112.5-kVA, three-phase transformer will be installed. The transformer's primary-side voltage will be 480V, and the secondary-side voltage will be 208Y/120V. This transformer will have primary and secondary overcurrent protection. What is the maximum size (rating) fuse that can be installed on the primary and secondary side of this transformer?
The transformer-rated current on the primary side will be 135A (112,500 ÷ 480 ÷ 1.732 = 135.3 = 135). After multiplying by the primary protection percentage, the current is 338A (135 × 250 percent = 337.5 = 338). When multiplying by any percentage other than 125, the product is the maximum rating. If the rating is not standard for a fuse or circuit breaker, it is not permissible to round up to the next standard rating. For this transformer, the primary overcurrent device rating shall not exceed 338A. In accordance with 240.6(A), the next standard rating lower than 338 is 300. While the fuse rating for the primary side of this transformer can be less than 300A, the maximum size fuse that can be installed is 300A. The transformer-rated current on the secondary side will be 312A (112,500 ÷ 208 ÷ 1.732 = 312.3 = 312). After multiplying by the secondary protection percentage, the current is 390A (312 × 125 percent = 390). Because there is text to the right of 125 percent that states to see Note 1, it is permissible to round up to the next standard-size fuse. The maximum size fuse that can be installed on the secondary side of this transformer is 400A (see Figure 2).
Sometimes there is confusion when sizing transformer conductors and overcurrent protection, and it is usually because of Tables 450.3(A) and (B). As previously mentioned, transformer overcurrent protection shall comply with 450.3(A), (B) or (C). In accordance with these tables, secondary overcurrent protection may not be required. In the first example, secondary protection was not required because the primary was protected at 125 percent of the transformer rated current. It certainly seems wrong to install a transformer with no overcurrent protection on the secondary side. When looking at the requirements in Article 450, it is important to realize it contains requirements for transformers and for the installation of transformers. Article 450 does not contain requirements for transformer conductors. While secondary overcurrent protection may not be required for the transformer itself, overcurrent protection may be required for the conductors. Requirements for overcurrent protection of conductors are in 240.4. There is even an informational note under 450.3 that refers to 240.4, 240.21, 240.100 and 240.101 for overcurrent protection of conductors. In accordance with the first sentence in 240.4(F) and the last paragraph in 240.21(C)(1), single-phase (other than 2-wire) and multiphase (other than delta-delta, 3-wire) transformer secondary conductors are not considered to be protected by the primary overcurrent protective device. Because of these two sections, secondary overcurrent protection (for the conductors) is not required if the transformer is a single-phase transformer having a 2-wire (single-voltage) secondary or a three-phase, delta-delta connected transformer having a 3-wire (single-voltage) secondary. Although secondary overcurrent protection is not required for these two transformer types, the installation of the conductors and primary overcurrent protection shall comply with 240.21(C)(1) (see Figure 3).
While a disconnecting means is usually installed within sight of the transformer, it is not a requirement. Section 450.14 was added to the Code in the 2011 edition. Transformers, other than Class 2 or Class 3, shall have a disconnecting means located either in sight of the transformer or in a remote location. This section continues by stating, where located in a remote location, the disconnecting means shall be lockable in accordance with 110.25, and its location shall be field-marked on the transformer. The term "in sight" is not just a general term; Article 100 defines it. Where the Code specifies that one piece of equipment shall be "in sight from," "within sight from," or "within sight of," and so forth, another piece of equipment, the specified equipment is to be visible and not more than 15 meters (50 feet) from the other.
Before the 2014 NEC, this section stated that the disconnect simply had to be lockable. Now this section states that the disconnect shall be lockable in accordance with 110.25, which is a new section in the 2014 edition. Where a disconnecting means is required to be lockable open elsewhere in the NEC, it shall be capable of being locked in the open position. The provisions for locking shall remain in place with or without the lock installed (110.25) (see Figure 4).
Next month's column continues the discussion of sizing conductors.


text:
Owls fail in Riordan move
Skysports.com understands Sheffield Wednesday have failed in a move for Celtic's Derek Riordan.
By Peter O'Rourke
Last Updated: 06/08/07 10:23pm
Skysports.com understands Sheffield Wednesday have failed in a move for Celtic's Derek Riordan.
It is understood the Owls made an enquiry for Riordan as they look to bolster their squad ahead of the new season.
However, Wednesday were put off by Celtic's £1million valuation of the versatile attacker.
Riordan's future at Celtic has been the subject of intense speculation with the player frustrated with his lack of first-team opportunities.
The 24-year-old has admitted he may have to consider his options if he does establish himself in Gordon Strachan's side this season.
Celtic have a wealth of attacking options at Parkhead and Riordan found himself playing a bit-part role for most of last term.
Wednesday boss Brian Laws was keen to offer Riordan an escape route out of Glasgow, but they unable to meet Celtic's price-tag for the player.
It now seems Riordan will stay at Celtic unless any interested party is willing to meet the Scottish's side £1million valuation of the former Hibernian star.


text:
Multi-Vitamin, 30 Tablets - WonderSlim
- Description
WonderSlim Multi-Vitamin Weight Loss Supplements
30 Tablets/Bottle
Taking one WonderSlim Multi-Vitamin a day provides superior protection to help you avoid nutritional deficiencies that could ruin your weight loss plans. Designed by nutritional experts, this easy to take vitamin and mineral supplement provides the proper balance of many essential nutrients shown to be vital for effective and sustainable weight loss.
Key Features of WonderSlim Multi-Vitamin:
- Scientifically balanced blend of nutrients essential for weight loss
- Only need to take one tablet a day
- Easy swallow tablets
- Guaranteed potency and efficiency
OUR GUARANTEE: We're so certain you'll be pleased with the quality of these products, we gladly offer our 150% Money Back Guarantee on all purchases.
* These statements have not been evaluated by the FDA. This product is not intended to diagnose, treat, cure, or prevent disease.
- Directions
For adults take 1 tablet daily with water.
- Nutrition
Serving Size: 1 Tablet
Servings Per Container 30
Amount per tablet %DV Amount per tablet %DV Vitamin A 5,000 I.U 100% Copper 2mg 100% Vitamin D3 400 I.U. 100% Vanadium 10mcg * Vitamin E 30 I.U. 100% Iodine 150mcg 100% Vitamin K 25mcg 31% Calcium 162mcg 16% Vitamin C 90mg 150% Phosphorus 125mg 12% Niacin 20mg 100% Magnesium 100mg 25% Vitamin B1 2.25mg 150% Biotin 45mcg 15% Vitamin B2 2.60mg 153% Manganese 5mg 250% Vitamin B6 3mg 150% Potassium 30mg 1% Vitamin B12 9mcg 150% Chromium 25mcg 20% Pantothenic Acid 10mg 100% Molybdenum 25mcg 33% Folic Acid 400mcg 100% Selenium 25mcg 35% Iron 27mg 150% Nickel 5mcg * Zinc 15mg 100% Tin 10mcg 12%
* % Daily Value not established
by Chandra on 8/7/2014
Great product and reasonable!
Great price
by JazzyC on 8/5/2013
Easy to take. I like taking just 1 a day.
feelin good
by Leslie on 5/3/2013
I was on another program and lost weight and broke my bank in the process. I cross referenced the products and found these vitamins at a more affordable cost. I can continue my journey to weight loss with out going broke.
great 1 day vitamin
by Pam on 4/25/2013
Replaced a much more expensive product from health place- seems to work and easy for me to swallow
by Amber on 3/6/2013
The reason why I love this multi-vitamin so much is because it does not have the pill coating that usually makes me sick to my stomach. I've always hated taking vitamins for that reason. Now I know I am getting all my essential vitamins while on this diet.
* Results not typical. Weight loss will vary for each person based on their individual weight, metabolism, age, activity level and commitment to their plan.


text:
Assassin's Creed
Review by audiotype
Reviewed: 11/19/07
Simply wonderful and amazing
Imagine yourself being an assassin, being able to climb buildings, jump around here and there, killing people using stealth ability, engage in combat against enemies and all awesome stuff, well people, you're gonna get this kind of feeling when you're playing Assassin's Creed. Yes it is without no doubt one of the best games I've ever play in my 360.
I'm not going to review the storyline as it will be spoilers, but the story takes place during the Third Crusade, and the year was 1191. And more stories will be revealed as you play the game.
The gameplay itself mainly focuses on defeating all of your main targets, which requires you to assassinate each and every one of them, and maybe you're gonna think like, "well this is damn easy...I only need to assassinate all of them and get all the achievements easily LOLZZZZ..." YOU'RE WRONG!!! Firstly you're gonna have to gather informations around the city, by eavesdropping, pickpocketing some major informations and all that, and yes, at first you're gonna think like "LOLZ this is so boring I can't do all this stuff LOLZZZ..." and guess what, it's not boring, it's very and I mean VERY fun, this is what a true assassins gotta do before they actually assassinate their target, man this game is sooo realistic, believe me. And this game also focuses heavily on interaction, the you act will affect all of the people surrounding you, and to my surprise is that they really act according to our own actions, so realistic.
The graphics is so awesome, every city, characters, pedestrian and objects are designed so well, that at first glimpse you're gonna say like "ZOMGGG!!! THIS IS NOT A GAME, ITS A MOVIE!!!" Yes it was actually a movie (no no I was just kidding lol...) for me the graphic was top notch.
Let's talk about sound, yeah it's kinda awesome, when you were engaged in a combat against guards for example, you can hear blades crashing here and there, the pedestrians were so awesome, sometimes if we bumped accidentally right in front of them, sometimes they get mad, and for example if we climb a building, the crowds will gather around and commenting our actions...simply awesome.
For me the game does not make you bored so easily even after you complete the main objectives, there are many free missions around each cities you visited, and tons of other activities for you to play.
At last, my final recommendation will be that this game is so awesome you don't want to miss it, buy it if you really can't wait to play this awesome game, or you can rent it first to try and see whether you like it or not.
Rating: 4.5 - Outstanding
Product Release: Assassin's Creed (US, 11/13/07)
Got Your Own Opinion?
Submit a review and let your voice be heard.


text:
PC Magazine finds salesforce.com's latest release "should cause IT administrators to rethink
what to expect from an on-demand platform"
"Editor's Choice" distinction recognizes salesforce.com's industry leadership and customer success delivered thru the Software-as-a-Service and Platform-as-a-Service model
Salesforce.com is the world's largest provider of customer relationship management (CRM) software. For more information about salesforce.com (NYSE: CRM), visit: www.salesforce.com.
Any unreleased services or features referenced in this or other press releases or public statements are not currently available and may not be delivered on time or at all. Customers who purchase salesforce.com applications should make their purchase decisions based upon features that are currently available. Salesforce.com has headquarters in San Francisco, with offices in Europe and Asia, and trades on the New York Stock Exchange under the ticker symbol "CRM." For more information please visit http://salesforce.com, or call 1-800-NO-SOFTWARE.


text:
You're seeing this message because you're using an older version of Internet Explorer that is unsupported on our website. Please use these links to upgrade to a modern web browser that fully supports our website and protects your computer from security risks.
This page of the arboretum site contains an incomplete list of non-woody plants, vines, and shrubs you may encounter along the trails of the arboretum.
Skunk Cabbage
Common Barberry
Daisy Fleabane
Red Trillium
Spring Beauty


text:
The administrator at Portsmouth has served notice that the club will be shut down on 10 August unless all senior players still on the books at the 2008 FA Cup winners accept compromise deals on their wages or agree to transfers away from Fratton Park before that date.
Trevor Birch has revealed he will have "no option" but to liquidate the club by that deadline, four days before a Capital One Cup tie against Plymouth and eight before Pompey are due to start their League One campaign at home to Bournemouth, if agreement is not reached with the seven remaining senior players at the club. Both interested purchasers – the former owner, Balram Chainrai and the Portsmouth Supporters' Trust – have apparently stipulated that their attempts to complete a takeover are dependent upon settlements being reached with those high earners.
"The facts are straightforward: under the terms of the offer for the club, in order to complete the CVA proposal, the players have to leave and conclude compromise settlements," said Birch, a partner at PKF and the joint administrator of Pompey. "This condition has been imposed by the Pompey Supporters' Trust as well as by [Chainrai's company] Portpin. Both interested parties have made it clear that they won't take on the club unless there is movement from the players.
"We will continue to do all we can to facilitate these deals but the club's future hinges on the willingness of certain players and their agents to sign up to compromise agreements that are affordable both in terms of the amount and timing of repayments. Unless we make significant progress on this front by 10 August, then we are likely to have no option other than to close the club."
Birch has implemented a £5,000-a-week salary cap at the stricken club in an attempt to prolong the club's existence in the short term – as the players would be classed as "football creditors", the excess money owed would be paid at a later date if liquidation is avoided – but long-term progress would require such as Tal Ben Haim, who earns £36,000 a week, and Nwankwo Kanu accepting a compromise on the remainder of their lucrative deals.
Kanu, who is in Nigeria, has lodged a claim for £3m in back pay with Pompey and Ben Haim claimed this week that he is due a similar amount in salary arrears, bonuses and the remainder of his contract. Birch has stressed that any new owner would inherit considerable liabilities and would need to guarantee around £10m to football creditors before the Football League, which is closely monitoring the situation, will be satisfied, meaning an agreement on a compromise amount with those players is key.
David Norris, Greg Halford, Dave Kitson, Erik Huseklepp and Liam Lawrence are all in talks aimed at reaching an agreement or smoothing their transfers away. Luke Varney has joined Leeds for around £200,000, money that was paid directly to Derby County to cover the player's original transfer to the south coast club.
"We are making good progress with three or four players," added Birch. "But, despite many conversations and offers over the past few weeks, some players and agents still don't understand what's at stake here. If the club is liquidated, players will not be protected by the Football Creditor provisions. They will become ordinary unsecured creditors in a situation where there is unlikely to be any dividend."
Pompey were deducted 10 points when they returned to administration last term and were duly relegated to League One, where they will begin with a further 10-point penalty.


text:
Greek voters, fed up with five years of recession coupled with two years of harsh austerity measures, dealt a huge blow to the major political parties in parliamentary elections on Sunday. Many Greeks chose parties promising to roll back or amend the austerity deals that Greece has struck with Europe and the International Monetary Fund.
For the past three decades, a center-right and a center-left party have essentially handed power back and forth in Greece. In fact, it was a coalition of those two parties that worked together recently to ensure the country met its austerity targets to secure promises of more EU bailout money.
But it seems Greek voters have had enough of "austerity," and the parties — both far left and far right — that promised "no more of it" got the vote.
The result is a tumultuous new political landscape.
"This is a totally new reality. All hell has broken loose. Even the winners have been shocked by the election," said Stephanos Kassimatis, a columnist for the Kathimerini newspaper.
"It's a contradiction. Seventy percent of the people in this country want to stay in the European Union. At the same time, the same percentage do not want to bear the consequences of that choice."
In other words, the Greeks want to be in the eurozone, but they don't want to pay the bill, and the far-left and far-right candidates capitalized on this – especially the left-wing coalition called Syriza, which finished second with more than 16 percent of the vote.
Syriza's leader, Alexis Tsipras, said the message was clear. "The European people cannot compromise with the barbaric bailouts, they cannot legitimize an undignified future," Tsipras said on Monday.
He added that German Chancellor Angela Merkel "needs to understand that the policy of austerity has suffered a huge defeat."
Tzipras vowed that his party will do "whatever is necessary" to "have a government that will condemn the bailout agreement and cancel austerity measures."
Merkel voiced her own opinion on that line of thinking.
"The voting result is not uncomplicated," said Merkel. She emphasized that what's important is that the economic and fiscal measures that Greece has already agreed to be continued.
"There is no alternative," she said, adding that, "Now is the time for Greece to figure out how to form a coalition government."
But that's not going to be easy, given that the pro-austerity parties are now so unpopular, and the anti-austerity parties run the gamut from communist to far-right nationalist.
Some are skeptical that anyone will be able to form a coalition, at least a stable one that can actually govern or pay off debts. And as time slips away, the markets will mete out their own punishment, according to Pippa Malmgren, a former senior economic adviser to President George W. Bush.
"Time is money," Malmgren said. "The more time the politicians take to deal with this problem, or make the payments, the more costly it will be. Because the markets will make it more expensive, and interest rates will go up."
Under Greece's current bailout plan, the country is supposed to find about $12 billion more in cuts by next month – in order to qualify for more bailout money.
The clock is definitely ticking.
On Monday, New Democracy – the party that garnered the most votes in Sunday's elections – made an initial stab at trying to form a coalition. That evening, its leader said he had given up after less than a day.


text:
Have you heard about Julep? If not, your missing out. You get $40 worth of nail care and sometimes beauty items for only $20 a month. You can skip a month if you wish, as not every month will have something you want. It is great because with the holidays coming, you can gift subscriptions, or buy a box and give it to someone you know. The colors right now match the upcoming holidays, so Novembers box has beautiful fall and Thanksgiving colors.
You can get your first box for only a penny! Shipping is always free. Go to the Julep website, and click Become a Maven. It will ask you questions and try to determine your style (of course, if you don't like what your given, you can chose another). When you get to the final page, and are ready to order your box, it will tell you that it is $19.99, but don't worry, we got a code for that! Add the box to the cart and create an account. It will take you back to cart. Enter one of the codes below, and enter your state in the shipping area and the total comes down to $0.01.
You can also earn Jules. You earn Jules a variety of ways. These Jules will get you free boxes or free add-ons. Referring people, adding more to your box, on your birthday, on your anniversary of becoming a Maven, etc. There are more on their FAQ page (once you sign up).
So go here and take your style quiz. Enter one of the following codes to get your first box for only a penny:
JULEPVIP, PENNY, COLOR2012. This is good for first time/new customers only!
Here are my previous posts on Julep and some boxes I have received:


text:
Trot like a turkey and learn about honey badgers
Things to do over Thanksgiving weekend
Scott Ellis 7 a.m., Nov. 22
It's nine, ten at night. You can hear the clanging of work behind closed doors. In University Heights, the really cute small-shop cluster of eateries on Park Boulevard, where it ends at Adams.
Curiosity gets the better of me. I knock on a door. It opens and ta-dah! Four people look up from their work and say "Hi!"
Kate, Jinda, Sam, Paul.
Now I see the sign above. "Bahn Thai." I see we're at 4646 Park Boulevard.
"It means 'Thai House.' We're opening this weekend," says Sam. "Phone number's 619-299-6363."
"Soft opening, if we're ready," says Paul.
"It'll be traditional Thai and not expensive," says Kate. "Like $4.99 to $8.99."
"And no MSG, and dishes for lactose intolerant people, and plenty of vegetarian," says Jinda.
"This is the sixth restaurant I have opened," says Sam. "Most in the Midwest. So the food should be good from the start."
Sam punches the air outside
I leave them to get back to their hammering and painting.


text:
Scuderia Car Parts have over 14 years of hands-on experience with Audi's, so we know what it takes to maintain these beautiful and efficient machines. Your Audi Original Equipment parts should come from a trusted supplier that is committed to providing you with the optimal driving experience, so look no further.
Here at Scuderia Car Parts, we will only provide you with genuine Audi parts, sourced directly from the factory and we will deliver them directly to your door, wherever you are in the world. Buy online or contact us directly to make an enquiry.


text:
Dragon Shield Sunglasses - Matte Stealth / Copper PolarizedProduct ID# 2068167
We'll beat any lower price by 10%
Introducing the Dragon Shield Sunglasses. Two time ASP World Champion Mick Fanning's signature sunglass and Dragon's most technically advanced release yet. High contrast lenses, protective coatings, polarization... Mick wanted it all and Dragon delivered. Featuring Dragon's Performance Polar lens system with Mick's wish list of colors, coatings, and treatments, the Shield is the only sunglass you will ever need. These sunglasses feature an 8 base curve, a 5 barrel stainless steel hinge, and rubber nose pads. And all Dragon frames are armed with their exclusive Variable Configuration Geometry (VCG) technology - a design process that gives you crystal-clear, no-distortion vision at any point of view through the lens curve.
As for the lenses, Dragon's low-molecular weight Carbon based lenses are not only optically true, they block just about anything you can throw at them, including 100% of all harmful UV and Blue Light. Mick has his sunglasses coated with a hydrophobic coating, and yours will be too.
Customers Who Bought This Item Also Bought
Product Details
Prices and Availability
The chart provides price, UPC, and availability data.
In Stock - ships immediately
Out of Stock - we may get more but it is not currently on order with the manufacturer.
Backordered - we have the product on order with the manufacturer and expect to ship the product by the date indicated
Sold Out - we are sold out and will not receive any more.
You can still order a backordered item. It will simply ship when we receive the item from the manufacturer. Or you can choose to be notified when we get more in stock by selecting the Notify Me link in the Notify column. That way we will email you when we receive more and have fulfilled all backorders.
|Sold Out


text:
Cramer: House Passes Critical Funding for Fallen Soldiers' Families
Washington, D.C. – Today Congressman Kevin Cramer voted in the U.S. House of Representatives to pass a critical funding bill for fallen soldiers' families during the fiscal impasse. The Department of Defense suspended its payment of survivors benefits to the families of deceased military service members despite being given authority to pay its bills under the Pay Our Military Act. The legislation reiterates the intent of Congress for these benefits to be paid immediately, and was passed unanimously.
"The House deliberately gave the Department of Defense broad authority to pay its bills including this fundamental benefit to the loved ones of a fallen soldier. It is unconscionable our Commander in Chief would hesitate even for a moment to order these benefits paid," said Cramer.
The bill explicitly provides for the payment of the death gratuity to a soldier's family and reimbursement for funeral expenses, burial expenses, and travel expenses relating to the memorial service. Prior to the current fiscal impasse, Congress passed and the President signed the Pay Our Military Act with the clearly stated purpose of funding all military pay and allowances during a government shutdown.
The House also approved legislation today allowing the Federal Aviation Administration (FAA) to remain fully staffed during the fiscal impasse.
Twelve bipartisan critical funding bills have been passed by the House since September 30. So far none have been taken up for consideration by the U.S. Senate, and most have received veto threats from President Obama.


text:
SINGAPORE, Feb. 16 (UPI) -- Singapore's Prime Minister Lee Hsien Loong says the latest developments in North Korea are a matter of concern for ASEAN, ChannelNewsAsia reported Tuesday.
North Korea recently announced that it has manufactured nuclear weapons for self-defense and is suspending participation in disarmament talks.
"This is a long-standing problem. It's a latest twist in a complicated story. It's a problem which will have to be tackled by the parties of the six-party talks. I'm sure the Americans, the Chinese, the Russians, the Japanese, the Koreans -- they are busily caucusing to decide what is the best way to deal with this very prickly problem, which worries all of them," Lee said.


text:
Customer service was one of the biggest problems that McDonald's Corporation (NYSE:MCD) faced in 2003. New CEO Jim Skinner combated this problem by slowing new-store openings and focusing on the basics – customer service and restaurant cleanliness. If McDonald's has to go back to the basics again, it doesn't bode well for shares.
At this point, the turnaround in McDonald's should be complete and the focus needs to be on new-store openings and expanding the menu. A return to basics is what the shorts want, as the company will be less-focused on growth.
McDonald's is still having a hard time luring younger customers with its new menu items. For freshness and a healthier option, most younger customers would rather go to Subway and get a sandwich made to order. McDonald's is still looked at as a sinful treat when one gets a gluttonous craving.
Even McDonald's says that they worry most about Subway rather than other hamburger chains, such as The Wendy's Company (NASDAQ:WEN) and Jack in the Box Inc. (NASDAQ:JACK). To compete with Subway, McDonald's just launched the McWrap as a healthier option with the hopes of luring young people into its fast-food chains instead of going to Subway.
Management has previously expected weakness in China to lead a 25% fall in same-store sales for the first quarter of 2013; however, the company reported same-store sales down only 20%, part of which has driven the stock up over 5% after earnings. Yet, earnings were still down over 26% year-over-year for the first quarter, and management affirmed its downbeat 2013 guidance.
Where McDonald's had notable billionaires as its top hedge fund owners, Yum! has niche-concentrated hedge fund Joho Capital as its top hedge fund owner by shares. Joho had nearly 10% of its public equity portfolio invested in the fast food company at the end of 2012.
The article Are the Golden Arches Still Golden? originally appeared on Fool.com and is written by Marshall Hargrave.
Copyright © 1995 – 2013 The Motley Fool, LLC. All rights reserved. The Motley Fool has a disclosure policy.


text:
All quotes by Stanley Milgram
(8 quotes found)
"It may be that we are puppets-puppets controlled by the strings of society. But at least we are puppets with perception, with awareness. And perhaps our awareness is the first step to our liberation."
"The disappearance of a sense of responsibility is the most far-reaching consequence of submission to authority."
"With numbing regularity, good people were seen to knuckle under the demands of authority and perform actions that were callous and severe,"
"[T]he viewer is instructed by the narrator about exactly what to look for; his comments reinforce the notion that what we are about to see will be funny. Studio laughter accompanies each episode as a way of continually defining the actions as funny, prompting the home viewer to experience the scene as amusing, rather than feeling sympathy or compassion for the victim's plight, or searching to understand it."
"The soldier does not wish to appear a coward, disloyal, or un-American. The situation has been so defined that he can see himself as patriotic, courageous, and manly only through compliance."
"The state produced in the laboratory may be likened to a light doze, compared to the profound slumber induced by the preponent authority system of a national government."
"The key to the behavior of subjects lies not in pent-up anger or aggression, but in the nature of their relationship to authority. They have given themselves to the authority; they see themselves as instruments for the execution of his wishes; once so defined, they are unable to break free."


text:
Your August Financial To-Dos
We're thrilled to present this smart LearnVest story here on Savvy!
Every month, we figure out the top to-dos to get your financial life in order, so you don't have to. No need to divert time from all those fabulous summer parties we know you've got planned—complete these to-dos in your spare moments and you'll be free to enjoy the last of these hot summer days. (Until, you know, the "dog days are over.")
Here's the plan:
Make Your Doctor Appointments. Deadline: Monday, August 1
Summer is usually a bit slower in the office, so it's a great time to head in for your annual exam and make appointments for the doctors you should be seeing regularly. If your health insurance includes free check-ups, use that as extra incentive to schedule an appointment. (If you're looking for doctor recommendations, check out our favorite doctor review sites.)
Reassess Your Budget. Deadline: Monday, August 8
Make sure that your summer travel plans haven't bombed your budget for the month. Visit LearnVest's My Money Center to link up your accounts to track exactly how much you're spending in different categories of your life. (Tip from one member: Customize a folder just for your "bad habit," so you can track it even more carefully!) Use this information to make sure you're sticking to your current budget or to create a new budget if your lifestyle has changed.
Think About The Brand Of "You." Deadline: Wednesday, August 17
If you had to pick one thing for people to remember about you, what would it be? Knowing how to present yourself and communicate effectively can improve your job prospects. This includes knowing when to use social media to promote yourself … and when professionalism is paramount. Even a Facebook post as benign as, "Long day at work. So glad to go home tonight!" can send the wrong message. As you refocus on work in the fall, keep this in mind. (We got publicists to give us tips on how to be our own publicists, here.)
Read on for other money things to do this month.
Spend Time With Your Portfolio. Deadline: Monday, August 22
Whether you're a seasoned pro or just starting out, take LearnVest's new series of Investing Courses to make sure your investments are perfectly positioned to help you achieve your goals. These courses work for investors at all levels: From creating a beginner's portfolio to maximizing your investments for tax purposes, there's something for everyone.
Get On A Food Plan. Deadline: Monday, August 29
In general, September is when work ramps up again and people become more serious. Save yourself the hassle of yet another thing to do by thinking about your meals in advance. That way, you can do your grocery shopping all at once and cook enough to portion out extra meals during the week. (Of course, if you really want to make your food last, you can always freeze it according to our guide.)
To find out what items you should buy this month, read on.


text:
California Hospital Association Launches Statewide Quality Institute
The regional associations — Hospital Council of Northern & Central California, Hospital Association of Southern California and Hospital Association of San Diego and Imperial Counties — and CHA created the Hospital Quality Institute to support and align patient safety and quality improvement activities in hospitals throughout the state. As such, HQI will include all of the associations' existing patient safety and quality improvement activities.
The institute will be governed by CHA, the regional associations and hospital representatives, and will be led by CEO Julianne Morath, RN, MS, current chief quality and patient safety officer of Vanderbilt University Medical Center in Nashville, Tenn.
More Articles on Patient Safety:Nearly 400 California Hospitals Join CMS' Partnership for Patients
Patient Safety Tool: Preventing Falls in Hospitals Toolkit From AHRQ
10 Most Common Root Causes of Sentinel Events
© Copyright ASC COMMUNICATIONS 2017. Interested in LINKING to or REPRINTING this content? View our policies by clicking here.
To receive the latest hospital and health system business and legal news and analysis from Becker's Hospital Review, sign-up for the free Becker's Hospital Review E-weekly by clicking here.


text:
To all CiTs
Expand Messages
- Hello everyone,
Could all CiTs (or those who want to be CiTs) please contact me off-line? I would like to know where each of you are in regards to your status/training time. I haven't received a lot (or any) reports on CiTs in quite some time. If you could let me know how long you've been a CiT and what events you've worked at (if any). Please pass this on to any CiTs you know who may not be on this list.
Thank you.
In service,
Your message has been successfully submitted and would be delivered to recipients shortly.


text:
If you manage to launch a SEO Manchester campaign for your business effectively, you stand a very good chance to generate a significant amount of revenue. What you must remember is that SEO is not a one-time job; it is an ongoing initiative. After generating a steady flow of traffic from SEO Manchester, you should constantly maintain the campaign. If not, it is very easy to lose your ranking within a very short period, depending on the amount of competition you have.
01. Have someone to be online for you
You should have an expertise person to be online for you all the time. The assistance of such person is vital for a business; he should continue to post contents, maintain blog, reply to inquiries and maintain a good relationship with the potential customers. Such approach will help you to gain solid, organic traffic.
02. Make your website mobile-friendly
No matter how valuable the products or services you offer, your website becomes a failure if it is not compatible with mobile devices. Today, most of the people use mobile devices to access internet; a mobile-incompatible website will be rejected by your target audience regardless of the strength of your SEO Manchester campaign.
03. Build effective backlinks
One of the best SEO Manchester strategies to drive organic traffic towards your website is building backlinks. These backlinks are capable of driving organic traffic from relevant popular sites. Eventually, you will experience better conversion rate.
04. Update contents
Don't forget to update your content regularly and meaningfully. Useful, relevant and original content will be loved by search engines. If you don't have enough time to create contents, it is always better to hire an experienced professional.
Besides, it is always better to have your website examined by a professional on regular basis to rectify potential errors at the earliest.