text:
|Publication number
|Publication type
|Application number
|Publication date
|Oct 26, 2010
|Filing date
|Oct 7, 2005
|Priority date
|Dec 27, 1996
|Fee status
|Also published as
|Publication number
|Martin Vorbach, Robert Münch
|Original Assignee
|Martin Vorbach, Muench Robert
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (582), Non-Patent Citations (269), Referenced by (12), Classifications (26), Legal Events (3)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a continuation of U.S. patent application Ser. No. 10/265,846, filed Oct. 7, 2002, now U.S. Pat. No. 7,028,107 which is a continuation of U.S. patent application Ser. No. 09/613,217, filed Jul. 10, 2000, now U.S. Pat. No. 6,477,643, which is a continuation of U.S. patent application Ser. No. 08/947,002 filed on Oct. 8, 1997, now U.S. Pat. No. 6,088,795, expressly incorporated herein by reference in the entirety.
The present invention is directed to a process for automatic dynamic reloading of data flow processors.
Programmable units presently used (DFPs, FPGAs—Field Programmable Gate Arrays) can be programmed in two different ways:
Configuration data is loaded into programmable units through a hardware interface. This process is slow and usually requires hundreds of milliseconds due to the limited band width accessing the external memory where the configuration data is stored, after which the programmable unit is available for the desired/programmed function as described in the configuration file.
A configuration is obtained by entering a special bit pattern of any desired length into the configurable elements of the unit. Configurable elements can be any type of RAM cells, multiplexers, interconnecting elements or ALUs. A configuration string is stored in such an element, so that the element preserves its configuration determined by the configuration string during the period of operation.
The existing methods and options present a series of problems, such as:
The present invention makes it possible to reconfigure a programmable unit considerably more rapidly. The present invention allows different configurations of a programmable unit to be used in a flexible manner during operation without affecting or stopping the operability of the programmable unit. Unit configuration changes are performed simultaneously, so they are rapidly available without need for additional configuration data to be occasionally transmitted. The method can be used with all types of configurable elements of a configurable unit and with all types of configuration data, regardless of the purpose for which they are provided within the unit.
The present invention makes it possible to overcome the static limitations of conventional units and to improve the utilization of existing configurable elements. By introducing a buffer storage device, a plurality of different functions can be performed on the same data.
In a programmable unit, there is a plurality of ring memories, i.e., memories with a dedicated address control, which, upon reaching the end of the memory, continues at the starting point, thus forming a ring. These ring memories have read-write access to configuration registers, i.e., the circuits that receive the configuration data, of the elements to be configured. Such a ring memory has a certain number of records, which are loaded with configuration data by a PLU as described in German Patent Application No. 44 16 881 A1. The architecture of the records is selected so that their data format corresponds to the configurable element(s) connected to the ring memory and allows a valid configuration to be set.
Furthermore, there is a read position pointer, which selects one of the ring memory records as the current read record. The read position pointer can be moved to any desired position/record within the ring memory using a controller. Furthermore there is a write position pointer, which selects one of the ring memory records as the current write record. The write position pointer can be moved to any desired position/record within the ring memory using a controller.
At run time, to perform reconfiguration, a configuration string can be transmitted into the element to be configured without the data requiring management by a central logic or transmission. By using a plurality of ring memories, several configurable elements can be configured simultaneously.
Since a ring memory with its complete controller can switch configurable cells between several configuration modes, it is referred to as a switching table.
There is a plurality of ring memories in a programmable unit or connected externally to said unit. The one or more ring memories have one or more controllers controlling the one or more ring memories. These controllers are part of the PLU named in German Patent Application No. DE 44 16 881 A1. The ring memories contain configuration strings for the configurable elements of one or a plurality of configurable units; the configurable elements can also be expressly used for interconnecting function groups and they can be crossbar circuits or multiplexers for interconnecting bus architectures, which are conventional.
Ring memories and ring memory controllers can be either directly hardware-implemented or first obtained by configuring one or more configurable cells of a configurable unit (e.g., FPGA).
Conventional ring memories can be used as ring memories, in particular ring memories and/or controllers with the following properties:
The switching table controller is implemented using a regular state machine. In addition to simple controllers required by a conventional ring memory, controllers with the following properties are best suited for performing or possibly expanding the control of the switching tables of a programmable unit (in particular also of FPGAs and DPGAs (Dynamically Programmable Gate Arrays, a new subgroup of FPGAs)) according to the present invention:
In particular the following commands or a subset of those commands can be used as command strings for the appropriate control of a switching table requiring command string control. The command strings concerning position pointers can be used on the read position pointer(s) or on the write position pointer(s). Possible command strings include:
The indication of the direction of jump can end either in a forward movement or in a backward movement of the position pointer with the use of a positive or negative number.
The ring memory record architecture has the following format:
The first bit identifies a record as a command or a data string. The controller of the switching table thus decides whether the bit string in the data portion of the record should be treated as a command or as configuration data.
The second bit identifies whether the controller should proceed immediately even without the occurrence of another event, should proceed with the next record, or wait for the next event. If an oversampling process is used and the RUN bit is set, the subsequent records will be processed with the help of this oversampling cycle. This continues until a record without a RUN bit set has been reached or the number or records that can be processed at the oversampling cycle rate within one system cycle has been reached.
If an oversampling process is used, the normal system cycle and the RUN bit set cause commutation to take place. Events occurring during the execution of a command sequence marked with the RUN bit are analyzed and the trigger signal is stored in a flip-flop. The controller then analyzes this flip-flop again when a record without a RUN bit set is reached.
The rest of a record contains, depending on the type (data or command), all the necessary information, so that the controller can fully perform its function.
The size of the ring memory can be implemented according to the application; this is true in particular for programmable units, where the ring memory is obtained by configuring one or more configurable cells.
A ring memory is connected to an element to be configured (or a group of elements to be configured), so that a selected configuration string (in the ring memory) is entered in the configuration register of the element to be configured or group of elements to be configured.
Thus a valid and operational configuration of the element or group to be configured is obtained.
Each ring memory has one controller or a plurality of controllers, which control the positioning of the read position pointer and/or the write position pointer.
Using the feedback channels described in German Patent Application DE 44 16 881 A1, the controller can respond to events of other elements of the unit or to external events that are transmitted into the unit (e.g., interrupt, I0 protocols, etc.) and, in response to these internal or external events, moves the read position pointer and/or the write position pointer to another record.
The following events are conceivable, for example:
If a unit has several ring memories, the controller of each ring memory can respond to different events.
After each time the pointer is moved to a new record, the configuration string in this record is transferred to the configurable element(s) connected to the ring memory.
This transfer takes place so that the operation of the unit parts that are not affected by the reconfiguration remains unchanged.
The ring memory(ies) may be located either in a unit or connected to the unit from the outside via an external interface.
Each unit may have a plurality of independent ring memories, which can be concentrated in a region of the unit, but can also be distributed in a reasonable manner on the surface of the unit.
The configuration data is loaded by a PLU, such as described in German Patent Application No. DE 44 16 881 A1, or by other internal cells of the unit into the memory of the switching table. The configuration data can also be simultaneously transferred by the PLU or other internal cells of the unit to several different switching tables in order to allow the switching tables to load simultaneously.
The configuration data can also be in the main memory of a data processing system and be transferred by known methods, such as DMA or other processor-controlled data transfer, instead of the PLU.
After the PLU has loaded the ring memory of the switching table, the controller of the switching table is set to a start status, which establishes a valid configuration of the complete unit or parts of the unit. The control of the switching table starts now with repositioning of the read position pointer and/or the write position pointer as a response to events taking place.
In order to cause new data to be loaded into the switching table or a number of switching tables, the controller can return a signal to the PLU, as described in German Patent Application No. DE 44 16 881 A1, or other parts of the unit that are responsible for loading new data into the ring memory of the switching table. Such a feedback can be triggered by the analysis of a special command, a counter status, or from the outside (the State-Back UNIT described in Patent Application PACT02).
The PLU or other internal cells of the unit analyze this signal, respond to the signal by executing a program possibly in a modified form, and transfer new or different configuration data to the ring memory(ies). Only the data of each ring memory that is involved in a data transfer as determined by the signal analysis, rather than the configuration data of a complete unit, must be transferred.
Buffer: A memory can be connected to individual configurable elements or groups thereof (hereinafter referred to as functional elements). Several known procedures can be used to configure this memory; FIFOs are well-known, in particular. The data generated by the functional elements are stored in the memory until a data packet with the same operation to be performed is processed or until the memory is full. Thereafter the configuration elements are reconfigured through switching tables, i.e., the functions of the elements are changed. FullFlag showing that the memory is full can be used as a trigger signal for the switching tables. In order to freely determine the amount of data, the position of the FullFlag is configurable, i.e., the memory can also be configured through the switching table. The data in the memory is sent to the input of the configuration elements, and a new operation is performed on the data; the data is the operand for the new computation. The data can be processed from the memory only, or additional data can be requested from the outside (outside the unit or other functional elements) for this purpose. As the data is processed, it (the result of the operation) can be forwarded to the next configuration elements or written into the memory again. In order to provide both read and write access to the memory, the memory can have two memory arrays, which are processed alternately, or separate read and write position pointers can exist in the same memory.
One particular configuration option is the connection of a plurality of memories as described above, which allows several results to be stored in separate memories; then, at a given time, several memory regions are sent to the input of a functional element and processed in order to execute a given function.
Architecture of a ring memory record: One possible structure of the records in a switching table ring memory, used in a data processing system as described in German Patent Application No. DE 44 16 881 A1 is described below. The following tables show the command architecture using the individual bits of a command string.
Bit Number
Identifies a record as a data
or command string
Identifies Run or Stop mode
Thus, if a record is a data record, bit number 0 has the value 0, so the bits from position two have the following meanings:
Bit Number
Cell number
Provides the cell numbers within a
group using the same switching table
Configuration data
Provides the function that the cell
(e.g., an EALU) should execute
If the record is a command, bit number 0 has the value 1, and the bits from position two have the following meanings:
Provides the number of the command that is
executed by the switching table controller
Shows whether the command is to be applied
position pointer
to the read position pointer or the write
position pointer. If the command does not
change either position pointer, the bit status is
Depending on the command, the data needed
for the command are stored starting with bit 8.
In the following table, bits 2-6 and 8-n are shown for each of the commands listed. The overall bit length of a data string depends on the unit where the switching table is used. The bit length must be chosen so as to code all data needed for the commands in the bits starting from position 8.
Bit 2-6
Description of bit 8-n
00 00 0
Number indicating how often an event is to be
waited for
00 00 1
Number with plus or minus sign showing how
many records are to be skipped forward
(backward if negative)
00 01 0
See SKIP1
00 01 1
1st record position, 2nd record position
00 10 0
Number of the record on which the position
pointer is to be set
00 10 1
Number indicating how often an event is to be
waited for, followed by the number of the
record on which the position pointer is to be
00 11 0
No function!
00 11 1
Number of the record on which the position
pointer is to be positioned
01 00 0
Bit pattern entered into the multiplexer to
select the events
01 00 1
A trigger signal is generated for the PLU
Reconfiguring ALUs: One or more switching tables can be used for controlling an ALU.
The present invention can be used, for example, to improve on Patent PACT02, where the switching table is connected to the M/F PLUREG registers or the M/F PLUREG registers are fully replaced by a switching table.
In addition to the configuration of the ring memory by the PLU, the ring memory can also be set as follows: Configurable element 0903 is wired so that it generates, alone or as the last element of a group of elements, records for ring memory 0906. It generates a trigger pulse, which advances the write position pointer in the ring memory. In this mode, multiplexer 0904 switches the data from 0903 through to the ring memory, while with a configuration by the PLU the data are switched through by the PLU. It would, of course, be conceivable that additional permanently implemented functional units might serve as sources of the configuration signals.
Glossary ALU Arithmetic Logic Unit. Basic unit for data processing. The unit can perform arithmetic operations such as addition, subtraction, and occasionally also multiplication, division, expansions of series, etc. The unit can be configured as an integer unit of a floating-point unit. The unit can also perform logic operations such as AND, OR, as well as comparisons. data string A data string is a series of bits, of any length. This series of bits represents a processing unit for a system. Both commands for processors or similar components and data can be coded in a data string. DFP Data flow processor according to German Patent No. DE 44 16 881. DPGA Dynamically Configurable FPGAs. Related art. D Flip-Flop Memory element, which stores a signal at the rising edge of a cycle. EALU Expanded Arithmetic Logic Unit, ALU which has been expanded to perform special functions needed or convenient for the operation of a data processing device according to German Patent Application No. DE 441 16 881 A1. These are, in particular, counters. Elements Generic concept for all enclosed units used as a part in an electronic unit. Thus, the following are defined as elements: configurable cells of all types clusters RAM blocks logics arithmetic units registers multiplexers I/O pins of a chip Event An event can be analyzed by a hardware element in any manner suitable for the application and trigger an action as a response to this analysis. Thus, for example, the following are defined as events: clock pulse of a CPU internal or external interrupt signal trigger signal from other elements within the unit comparison of a data stream and/or a command stream with a value input/output events run, overrun, reset of a counter analysis of a comparison flag Status bit in a register showing a status. FPGA Programmable logic unit. Related art. gate Group of transistors that performs a basic logic function. Basic functions include NAND, NOR. Transmission gates. configurable A configurable element represents a component of a logic unit, which can element be set for a special function using a configuration string. Configurable elements are therefore all types of RAM cells, multiplexers, arithmetic logic units, registers, and all types of internal and external interconnecting units, etc. configure Setting the function and interconnections of a logic unit, an FPGA cell or a PAE (see reconfigure). configuration Any set of configuration strings. data configuration The configuration memory contains one or more configuration strings. memory configuration A configuration string consists of a series of bits, of any length. This bit string series represents a valid setting for the element to be configured, so that an operable unit is obtained. PLU Unit for configuring and reconfiguring the PAE. Constituted by a microcontroller designed specifically for this purpose. latch Memory element that usually relays a signal transparently during the H level and stores it during the L level. Latches where the level function is reversed are used in some PAEs. Here an inverter is normally connected before the cycle of a normal latch. read position Address of the current record for read access within a FIFO or a ring pointer memory. logic cells Cells used in DFPs, FPGAs, and DPGAs, performing simple logic and arithmetic functions, depending on their configuration. oversampling A clock runs with a frequency that is a multiple of the base clock, synchronously with the same. The faster clock is usually generated by a PLL. PLL Phase Locked Loop. Unit for generating a multiple of a clock frequency on the basis of a base clock. PLU Units for configuring and reconfiguring the PAE. Constituted by a microcontroller specifically designed for this purpose. ring memory Memory with its own read/write position pointer, which-upon reaching the end of the memory-is positioned at the beginning of the memory. An endless ring-shaped memory is thus obtained. RS flip-flop Reset/Set flip-flop. Memory element that can be switched by two signals. write position Address of the current record for write access within a FIFO or ring pointer memory. State-Back Unit that controls the feedback of status signals to the PLU, comprising a unit multiplexer and an open-collector bus driver element. switching A switching table is a ring memory, which is addressed by a controller. table The records of a switching table may contain any configuration strings. The controller can execute commands. The switching table responds to trigger signals and reconfigures configurable elements using a record in a ring memory. gate Switch that forwards or blocks a signal. Simple comparison: relay. reconfigure New configuration of any number of PAEs, while any remaining number of PAEs continue their functions (see configure). processing A processing cycle describes the time required by a unit to go from a cycle specific and/or valid state into the next specific and/or valid state. state machine Logic that can assume different states. The transition between the states depends on different input parameters. These machines are used for controlling complex functions and correspond to the related art.
Naming conventions
negated signal
register visible to PLU
internal register
shift register
Function conventions
AND function &
OR function#
NOT function!
GATE functionG
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|U.S. Classification
|710/8, 711/147, 712/10, 712/23, 711/153, 710/10, 711/152, 712/16, 710/1, 716/128
|International Classification
|Cooperative Classification
|European Classification
|Feb 2, 2010
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