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Crime & prejudice
Concerns other than crime ... Doria Chafic, centre, with her
daughters, Kawthar, 14, and Fadila, 16, in their Bankstown home.
Photo: Kate Geraghty
THE signposts pointing north on Canterbury Road read like a catalogue of Sydney's darkest fears and imaginings. Heading west, you pass them one by one: Campsie, Belmore, Lakemba, Punchbowl - names synonymous with "Middle Eastern crime", and even terrorism.
"It is a war zone, south-west Sydney," says the State Opposition Leader, Peter Debnam. "People are living with regular gunfire. You do have gangs who are operating in some suburbs, who to some extent control suburbs."
The Liberal member for Vaucluse paints a bleak picture of an area that's traditionally served as a stepping-off point for postwar migrants to Australia: Greeks and Italians, Vietnamese and Lebanese, and now Pacific Islanders and willowy, dark-skinned refugees from the Horn of Africa.
It's remarkable how little the physical landscape along Canterbury Road has changed since the 1960s. The odd gleaming palace of commerce or recreation aside, it's the same arthritic thoroughfare under a big sky framed by timber power poles that it was in decades past, when John Howard went to school and Steve Waugh played backyard cricket in the area, and the Bulldogs were the Berries.
Equally remarkable is the chasm separating the reality in this generally peaceable, law-abiding melting pot and the "war zone" claims of Debnam and a noisy chorus of former police whistleblowers, politicians and media commentators who feel compelled to call the pot black. Crime and prejudice are like two hotted-up cars, racing along Canterbury Road towards next year's state election. It wasn't always so. Bankstown Sports Club, a suburban folly nestling amid an artificial rainforest and Corinthian columns in imitation stone, is the place where Paul Keating delivered his "sweetest victory of all" speech on the night of the 1993 federal election.
"It will be a long time before an Opposition party tries to divide this country again," Keating told his euphoric audience. "It was Australian values on the line, and the Liberal Party wanted to change Australia from the country it's become, a co-operative, decent, nice place to live where people have regard for each other."
One in three Sydneysiders was born overseas, the vast majority from non-English-speaking backgrounds, and two in three Sydneysiders have at least one foreign-born parent. Yet, in the aftermath of the riots in Cronulla in December, the terms "ethnic thugs" and "grubs" have dominated the discourse about crime in Sydney. The words ethnic and Australian are becoming mutually exclusive.
In January, the Premier, Morris Iemma, the son of migrants and the state Labor MP for Lakemba, announced the formation of a new Middle Eastern organised crime squad, a permanent body of 50 police, mainly detectives assisted by analysts, interpreters and, for an initial three-month period, 50 uniformed officers.
What looked like another sop to the post-September 11 politics of fear is, say senior NSW police, a necessary weapon to break up criminal gangs rooted in ethnicity in south-west Sydney.
"These people [have] a common heritage, but I'm not suggesting that their activities are cultural ... they come from one particular area of Sydney because that's where people of this characteristic tend to live, but not exclusively so. This is not cultural, this is not religious, this is not racist," assistant commissioner Graeme Morgan says, identifying Australian-born offspring of Lebanese migrants as the main source of the problem.
Morgan says organised crime in and related to the Middle Eastern community is "serious, and in comparative terms, prevalent" and that recent sporadic outbreaks "have given rise to concern [that] it may be on the rise again". But his office declined a request to provide data backing his assertions.
This paucity of hard data is a feature of the debate on ethnicity and crime. Neither the Australian Institute of Criminology nor the NSW Bureau of Crime Statistics and Research collects such information. Reasons range from the failure of police to provide adequate figures, to the fear held by many researchers that ethnic-based statistics would raise more questions than they answer, and would be wide open to misrepresentation.
Department of Corrective Services records show that Lebanese-born migrants are over-represented in the state's prisons. They make up 1.4 per cent of the prison population but only 0.8 per cent of the general population of the state, according to the 2001 census. Migrants born in Vietnam, Fiji and New Zealand are even more likely to end up in prison. Migrants born in Greece and Italy are less likely to end up in prison than their Australian-born peers.
But again, these figures say little because the department records only the birthplace, not the ethnic background of prisoners.
IN GREENACRE, the old fibro bungalows are making way for two-storey brick veneer palaces, often with three or four cars in the driveway. Early in the morning, veiled mothers drive their children to school in four-wheel-drives. But daylight reveals a burnt-out car near Gosling Park, the scene of an horrendous incident in August 2000 when up to 14 males led by Bilal Skaf raped a 16-year-old girl.
Says one Greenacre resident, Pat Ebsary, who moved here three years ago from Cabramatta: "There's a lot of crime and I think the crime is from people not working." But she's never been affected by crime.
They're not yet donning flak jackets at the Bankstown Youth Development Service. Tim Carroll, who's worked with the service for 15 years and whose office overlooks Bankstown Plaza, has witnessed only one incident of criminal behaviour - a failed mugging - in all those years. "I would argue that this area is a really, really good example of multiculturalism going right. People say g'day to their neighbours," Carroll says.
Bureau of Crime Statistics figures show you are more likely to be murdered in western Sydney than in Canterbury-Bankstown; more likely to be burgled in the eastern suburbs; more likely to be assaulted in Gosford-Wyong. The figures for some offences, such as robbery with a firearm and motor vehicle theft, are above the state average, but the picture is mixed. The "war zone" hysteria has no basis in fact.
"We're certainly at record low levels of crime now, and that includes in this particular area [south-west Sydney]," says Graeme Morgan. "We're not at war. This is not anything like Los Angeles, or anywhere else that has the incidence of drive-by shootings and lawlessness that some would like to paint us as being synonymous with ... there are no no-go areas in Sydney."
But security is in the eye of the beholder. "It may be that there is this belief in Australia and in many other countries that immigrants are more prone to crime than non-immigrants, even though most statistics show otherwise," says Dr James Jupp, director of the Centre for Immigration and Multicultural Studies at the Australian National University.
Nomise, a 28-eight-year-old Palestinian Christian and hip-hop artist, says that, like generations of young Australians, Middle Eastern youth in the south-west love their hotted-up cars. But these days, the Yagoona resident says, they get pulled over by police with frustrating frequency. To them, booze buses are RATs, random Arab testing units.
Violent crime is not confined to any one group of Australians, Nomise says. He remembers being chased and bashed up at school by white Australians. "They ask 'why do people stick together?' It's because you want to feel safe ... it really does affect you, what happens to you at an early age ... it took me a while before I was able to trust Anglo-Australians.
"I believe the society is turning these Middle Eastern men into really negative people," he says. "They feel that if you treat me badly, I'm going to behave badly ... It's getting hard for them to get jobs." To get work, he says, some have taken to using fake names on their applications.
Since the September 11 terrorist attacks in the US and the notorious gang rapes in Sydney's south-west in 2000, young men from Middle Eastern backgrounds can't win. If they try to act like some of their Anglo peers - taking lots of alcohol and drugs and behaving badly - they are labelled as dysfunctional ethnics who can't adjust to "Australian values".
If they are religious and follow their faith - like Mohammed Michael Ahmed, who plans to remain a virgin until he marries - they risk being labelled extremist.
Ahmed, 21, is one Lebanese Muslim negotiating the divide between Islam and Western culture. He dresses like an Australian Idol contestant in trendy hoodies and distressed jeans. He writes and acts. But he also plans to remain a virgin until he marries, and regularly preaches from the Koran at Al Sadiq College in Yagoona.
Ahmed feels that the divide between traditionally minded parents and their Australian-born children can also lead to problems. "Most Middle Eastern parents don't know about their kids' lives," he says. "They don't know if they have a girlfriend, they don't know if they smoke. Maybe if a parent is a bit more open-minded, their kids can open up to them."
Having a father who gives and takes has helped him bridge the divide between cultures and helped him stay out of trouble.
WHILE there is no evidence of a causal relationship between ethnicity and crime, the link between poverty and crime is well-established. A recent study by Monash University academics found that 47 per cent of all Lebanese Muslim men in Australia aged 25 to 64 were unemployed or not in the labour force, compared with 28 per cent of Lebanese Christians and 21 per cent of all men in that age group.
Carroll says the tightening of welfare payments in recent years has lowered the incomes of many families in Sydney's south-west, creating a situation in which property crime is more likely.
The gleaming palace that is police headquarters at Parramatta resembles a five-star hotel. It's a fitting monument to the cargo cult of law and order that has caught on in NSW over the past 20 years. But not all is well in the police.
At Cronulla, the mob shouted "Cops are tops" and the police let them continue drinking, with predictable consequences. When Muslims took revenge, trashing beachside suburbs, police bore the brunt of Opposition and media criticism.
Under pressure from politicians, the media and the public to get tough on crime, senior officers are talking up a new round of "in your face" policing, while fending off controversy over a four-days-on/six-days-off rostering system that looks like a vacation planner.
Dr Michael Kennedy, a former policeman who is now a lecturer at the University of Western Sydney, believes the community's "moral panic" about crime and zero-tolerance approaches are counterproductive.
"Operation Viking [a blitz on crime hot spots] promoted the myth that if you are tough on petty crime the more serious issues will all be catered for, and it was a failure," he says. "The price [of such approaches] is the loss of information to the police, networks of community resources, and discretion in dealing with less than serious crime."
In the United States, zero tolerance was credited with achieving a big drop in spiralling crime rates in New York City in the 1990s. But other US cities achieved similar results with "community policing", based on deep engagement with local communities.
Ethnic profiling has been abandoned by New York's Police Commissioner, Raymond Kelly, who recently told The New Yorker: "It's the wrong thing to do and it's also ineffective."
The regional police commander for south-west Sydney, Superintendent Dave Owens, admits that pursuing both strategies - "in your face" and community policing - is a delicate balancing act. But he's trying.
Police under his command will continue to engage with local government and community groups and persist with efforts to win the confidence of the locals, but he warns local youth, Middle Eastern and others, that "if you step over this line, the boot's still there to give you a swift kick up the backside".
But "in your face" policing carries risks for police on the beat, too. The NSW Ombudsman recently warned about an "alarming" increase in complaints against police - from 1443 in 2001-02, to 6000 in 2004-05.
While acknowledging her area has a problem with gang-related crime, the Mayor of Bankstown, Helen Westwood, worries that another law-and-order auction will siphon funds needed to tackle problems associated with high unemployment.
For the state's top crime expert, Don Weatherburn, the risk of fighting yesterday's bogys is that we may not see emerging trends in crime. "It causes everybody involved a great deal of grief when people for commercial, personal or political reasons seek to inflame the situation," he says. "During the height of the crisis over Lebanese gang rapes, no one was paying any attention to the figures on multiple sexual assaults in Aboriginal communities which were readily available."
Weatherburn, the director of the NSW Bureau of Crime Statistics and Research, says it's time the public focused on less sensational, but equally important crime issues such as alcohol-related assaults and offensive behaviour, problems that may worsen if the state's liquor licensing laws are further liberalised as proposed.
"These issues come up again and again when you survey the public about their concerns. They just want to go about their business free from the fear of harassment and assault."
Did you know you could pay less than $1 a day for a subscription to the Herald? Subscribe today.


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Yeah, that's right — Louie's called in a couple of friends for his new single. Pusha Ton and Juicy J will be joining Louie on "Drugs", the second official single from his Epic/Lawless Inc. debut. The record was produced by Yung Berg and should see release sometime in the near future.
I don't know about y'all, but I can't wait to hear this one.
Show Comments (1)
That's gonna be crazy!!!!! I'm proud of this dude!!!

subset: commoncrawl


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My X and I have a friendly agreement to communicate/help if old debts rear their ugly head which they have from time to time. I filed bankruptcy in 2009 and included everything I could think of but still some things crop up.
Earlier this year one company filed suit against my X. He never responded and basically never dealt with it except to let me know and ask me what it was. I told him. Well back last summer they garnished his paycheck for some portion of a default judgement they got.
A few days ago, I got a series of irate texts b/c he has quit his job and same company had garnished his check again
1. He identified the amount owed as the actual amount of his gross pay for the final check.
2. Then somehow interpretted the max amount that they could withhold for garnishment as the amount being garnished. (despite a note from his payroll group with the specific amount being withheld)
3. Flipped out on me b/c it must be my fault that he owed some HUGE amount.
4. Freaked out b/c he had just quit his job and this happened. (not my fault you suddenly decided to quit a job you've had for 13 years)
5. He hates to deal with this stuff and why can't I just do it.(nevermind that I have 2 jobs)
6. the total amount owing is $130 not the $8K he orginially flipped out over.
7. He kept apologizing for getting mad and then would wind himself up again.
I was proud of myself.
1. I calmly said if it was mine I would reimburse him
2. properly read the legal docs and in 2 minutes figured it out.
3. calmly informed him that I understand he's frustrated but venting needs to be saved for OW. Its no longer my role to listen to him when he's upset.
4. Quit responding when the situation was addressed.
Yep...D was clearly for the best.
TG got cranky with me over something small. I can see what made him cranky but it wasn't really anything big. He thought about it and apologized a short while later b/c he considered it from my perspective and understood. THAT is the difference between my X and my SO....emotional maturity.
Many of us crucify ourselves between two thieves - regret for the past and fear of the future. -foulton oursler
They do make things interesting, don't they?
AJ's MOM
"Truth has no special time of its own. Its hour is now - always." - Albert Schweitzer
Me: BW - Him: 200+ # tumor removed 7/09
One AMAZING DS - 34
3. calmly informed him that I understand he's frustrated but venting needs to be saved for OW. Its no longer my role to listen to him when he's upset.
Amen. Amen to all of it.
THAT is the difference between my X and my SO....emotional maturity.
I'm proud of you hexed!


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Spectrum Health Named One Of The Top Hospitals In The Country
The annual report on health care providers in the United States has been released by U.S. News & World Report. Spectrum Health fared very well in several categories.
The reports ranks Spectrum Health as the 40th best hospital for Diabetes and Endocrinology treatment in the nation. Spectrum was also ranked "high performing" in the following specialties: cancer, cardiology and heart surgery, ear, nose and throat, gastroenterology, geriatrics, gynecology, nephrology, orthopedics, pulmonology, and urology.
See the details on Spectrum Health's rankings here.


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We welcome you as a patient...
Our purpose is to provide our patients with quality dental service in a friendly and caring atmosphere. We will strive to treat each person who enters our office with kindness and understanding and will make each day as enjoyable as possible for both our patients and ourselves.
We will expend every effort to elevate each patient's dental awareness to provide them with the means of maintaining their own oral health in an optimum condition.
Every individual in this office, whether patient or staff, will be treated with equal dignity and will be encouraged to reach their maximum potential.
For Patients Without Insurance
We now offer a Dental Health Maintenance Club which offers reduced fees on most of our offered services. Call our office for details
We make great smiles happen.
Emergency Care Available
Call 573-334-8798


text:
Driving on Ice - Part 1
Ice driving is a thrilling winter sport that can be done in some of the world's most stylish sports cars. From handling a Porsche in Sweden to steering an Aston Martin in St Moritz, we've picked some of the slickest cars to drive on some of the iciest terrains, which are sure to give you the ultimate adrenaline rush....
In the north of Sweden in Arjeplog, close to the Arctic Circle, Mercedes offers drivers the chance to get behind the wheel of one of their luxurious cars on a five-day training course. Those who are lucky enough to get a slot - the course is limited to a maximum of twelve participants - will be given basic training, theory lessons and advanced training, which includes one-to-one coaching. Vehicles are provided for each driver, who will be given the chance to perfect their technique on the dynamic surface.
Prices start from £4,400 and include theoretical and practical driving and training and accommodation. For more information see www.mercedes-amg.com/driving-academy


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SEO & SEMWe don't promise to get you on page 1 of Google, but we will help you become more relevant to make your site more findable to new clients, users or visitors.
Email MarketingEmail Marketing is a great way to keep in touch with your existing community. Email is also the best way to take non-converts and share new products, services and events to meet their interests in you.
Social MediaSocial Media Marketing is more than just putting up a profile and posting now and then. Social is about building a community of advocates, followers and leads.
Mobile MarketingMobiel Marketing is a way to hit a moving target in the world of Digital Marketing. You can use tools like SMS, Location or QR Codes to turn that lead or prospect into a user, visitor or client.
Usability & UXWebsite Optimization includes: Usability, User Experience (UX), Conversion Rate Optimization (CRO) and Testing. We will look at your website flow and create a plan to get your site converting better than ever before.
What makes Deadshot Digital different? Transparency for one, we aren't going to talk to you about billable hours or have restrictions on how long we will work on your projects. We are great time managers and with years of digital marketing experience under out belts we are pretty good at judging how long a project will take.
If you want something in this world you have to ask for it. So plain and simple, we want your business. We are going work as hard for you as we do for ourselves, if there is something we can't do, we will solve that problem or recommend one of our partners to help. Check out our services so we can help.
1Internet MarketingAt Deadshot Digital we walk the link of art and science with our Internet Marketing strategy and execution. There is no one-size fits all digital solution, so we look at your business and tailor our plan, recommendations and solutions to you!
2Email MarketingEmail Marketing is one of the most underutilized tools in the digital and Internet marketing tool kit. We use email to capitalize on your the efforts of your other channels like social media and your website.
3Individual AttentionWe might be small, but we make up for it in attention to our clients. We are always happy to meet at your business, hop on the phone or Hangout on Google+ to talk about how things are going. We might be an outside consultant, but at the end of the day we value our partners and only succeed with they do.
4Services & Portfolio
Services showcase
Our services revolve around keeping your marketing channels working together. You can't just just one channel and expect people to find you, like you can have the greatest Facebook page in the history of Facebook, but with our a strong Website it will go largely unnoticed. Think of it this way, you wouldn't go buy a Ferrari and then just leave it parked in the garage? A social presence without a branded website is just that, sure your stuff looks nice and might get a few 'Likes', but at the end of the day you still have to take the bus to the grocery.
5We Love What We Do (period)Whether we are digging into web analytics, writing copy for your latest email, or interacting with your Internet community; at the end of the day we love this stuff. We live and breathe the Interent 22/7 (we need a couple hour of sleep to recharge), but when we aren't online we are thinking about what's happening online and how we can make it better.
Do you still need more reasons to work with us?


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The Best of College Football (sans smuggling Bourbon in your pants)
NCAA Football 11
Depending in part on how and where you spent your formative years, you should understand the following statement: nothing in the sporting world compares to the excitement of college football. Of course, you're entitled to disagree or to blow your vuvuzela in protest, but you'd be just plain wrong. That's why today we salute EA Sports and the yearly release of their collegiate gridiron simulator; that's right, NCAA Football 11 is in stores today, a precursor to the upcoming college season.
We've been devotees of this franchise for years, and, unlike other annually-appearing games, NCAA Football rarely missteps; instead, each year's game builds on previous successes and adds solid features to its already refined gameplay. This time out, each team's playbook has been optimized to mirror their real-life play style (you'll get the chance to perfect the spread, the triple option, the wishbone, and more), and realistic stadium features, coaching tendencies, and school traditions feature more prominently than ever. The big addition to gameplay comes in the form of locomotion running mechanics which rely on dual stick control to affect a 1-to-1 movement animation on your controlled player. Translation: it's up to you to control the severity of your ball carrier's juke or lean, as well as to independently manipulate both his upper and lower body. NCAA 11 looks better than every, sounds better than ever, and has the deepest set of online play and league options you'll find anywhere. If this can't get you through to week 1 this fall, nothing will.
Buy Now: PS3 ($60) | Xbox 360 ($60)


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Shoulda got Ted to cowrite this article.
Then I could have read things like 'those fucking Sun boxes" and "that fucking HP cluster business".
paris, because she likes to fuck.
The annual x64 server customer survey, put together by Gabriel Consulting Group, is out this week, and the top four server makers in this subset of the server space - Hewlett-Packard, Dell, IBM, and Sun Microsystems - have been given their report cards concerning how well they put together machines, deliver performance and …
Then I could have read things like 'those fucking Sun boxes" and "that fucking HP cluster business".
paris, because she likes to fuck.
we benchmarked HP DL160 against a Dell Pe1950 and the whilst the CPU performance wasn't huge, the raid controller on the Dell beat the HP resoundingly; I haven't played with DL3xx since the G3 and G4 series. Therefore I think that TheReg's summary is misleading as it's very unclear what systems were actually tested at all.
With both sides being different shades of green?
Ouch, my brain hurts
First off, I'm biased my current employer has lots of Proliants. Second, I like the G5 DL series a lot. But HP's website has to be the most sluggish, poorly designed POS. Using it is a painful waste of time, particularly since they removed the configurator.
Who the survey surveyed? A CIO and most directors couldn't comment with any accuracy of what the iron is or how well it actually does. On another note. HP and IBM target these Einsteins of IT hard. Why? Purse strings. Sun does a bit and DELL? When was the last time anyone seen a Dell rep cold call? This report is very interesting for anyone who reads between the lines. HP and IBM FUD machines power of influence. I love the crap i hear from our HP rep how Sun is dead and Dell is crap. If you keep saying it people will start to believing it to be true.
Dell's RAID controllers are very good. AMI makes them, or did.
How did you read two pages and miss the entire subject? This is a review of a market survey. The graph shows customer perception of performance. The article says exactly where the numbers came from: 187 customers, 43% of which were SMBs (see the third paragraph for more detail).
Where did they get these figures from? IBM have the worst x86 support of any organization I have ever used. This month I have had a P1 call which took more than 14 days to resolve and I have a server with a fault which they still haven't fixed after six months.
Why are the bars in the graphs in reverse chronological order? It makes all the trends look in the opposite direction and is very misleading.
Let's see
1. IBM performance leader? Falling off my chair laughing....
For example, when were they last #1 in vmark performance for VMware environments? Dell obviously leads here in just about every category and has done for a long while now.
Dell largely leads in the measurements that most matter to customers: price-performance per watt, performance per watt.
2. Green leader? Dell again. Dell's leadership in price-performance per watt
3. Scientific survey? 187 customers is not a particularly scientific sample.
4. Customers speak with their dollars. Dell is growing servers market share faster than overall market. Are HP, IBM, Sun ?
5. Technology leader? Dell again. Compare Dell blades to IBM Blades and you'll see technology that actually saves customers money and reduces their ongoing management costs.
6. Sun's not even worth mentioning here - they have a microscopic X86 market share and fall under the other category with Supermicro and white box manufacturers.
7. Roadmaps? Remind me again how many times IBM has forced customers to update power supplies in their blades to accomodate new server formats. Bad planning, in comparison to HP, Dell who pre-designed blades to accomodate multiple generations of Intel and AMD chipsets.
CONCLUSION: article sucks.


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Do you ever wonder what we know about the world around us?
The somewhat recent phenomenon known as "BioBlitzes" is rapidly rewriting what we know about the natural world that resides in national parks. In some cases, what we didn't know can appear astounding.
Perhaps the leader of the "BioBlitz" pack is Great Smoky Mountains National Park, where at last count the number of previously-unknown-to-the-world species discovered since an all-taxa biodiversity inventory got under way in 1998 had surpassed 900, while those not previously known to call the park home has soared beyond 7,100!
The "BioBlitzes" that are moving through other units of the National Park System are not as long-ranging, and so perhaps not as thorough. But they're impressive just the same.
During a 24-hour period from Oct. 21-22, for example, a biodiversity inventory swept through Saguaro National Park and, when all was said and done, more than 850 species were added to the roster of known species in the park. That number could continue to grow as organizers sort through data sheets and analyze samples that were collected.
Among the newcomers were 190 invertebrate species and 205 fungi species. Adding to the wealth of the 24-hour survey was an Electronic Field Trip organized by the National Park Foundation. Via it more than 90,000 students from around the country were able to take in two live broadcasts originating in Saguaro.
You can check out the nearly hour-long broadcast at this site, and even sort through previous Electronic Field Trip broadcasts made from other parks.
The BioBlitzes are made possible with the help of the National Geographic Society and, in many cases, local organizations. The Saguaro blitz was aided by Friends of Saguaro National Park and the Arizona-Sonora Desert Museum.
In 2010, Biscayne National Park near Miami, Florida, was the first ever marine bioblitz. Volunteers at the 2009 Indiana Dunes National Lakeshore BioBlitz turned up more than 1,200 species (download a PDF list here) compared with more than 1,700 in the Santa Monica Mountains National Recreation Area in 2008 and more than 650 in Washington, D.C.'s Rock Creek Park in 2007.


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NORTH CAROLINA – Rex W. Gallegos, who began his Boy Scout journey in Fallbrook Troop 731 in October of 2010, recently completed his Eagle Scout project in North Carolina.
Gallegos led a group of 25 youth and 10 adults over a total of 117 hours to promote and collect items in the Harrington Grove area to assemble 245 rack packs for distribution to service men and women through the USO of North Carolina. The donation amount totaled $5,040 worth of goods.
The USO invited Gallegos to help on one distribution day during a recent deployment and he was able to see first-hand how this affected the troops and how thankful they were to have the basic essentials for their journeys.
According to Gallegos, his effort would not have been possible without the help and support of 4-H of North Raleigh, BSA Troop 352, and Fallbrook BSA Troop 731, in addition to many others.
"I will always remember what a community can accomplish together and be grateful for that," said Gallegos.


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LAKE FOREST, Ill. — Hefty announced on Tuesday a new trash bag with advanced odor-control, the company stated.
Hefty Ultimate with Arm & Hammer provides a trio of advanced technology to give the consumer everything needed in one bag. The Arm & Hammer patented odor-neutralizing technology helps eliminate kitchen odors. Hefty Ultimate bags come in scent-free, lavender and clean burst scents.
Hefty Ultimate bags are designed to reduce messes with a unique formulation of textured plastic providing more tear- and puncture-resistance than any other Hefty tall kitchen bag, as well as a silver patented elastic gripping drawstring that expands and retracts around the lid of the trash can preventing the bag from slipping down into the canister.
Hefty Ultimate Arm & Hammer tall kitchen bags are available now to ship to major retailers and will be on store shelves this Fall.
Get connected and follow us on LinkedIn for the most in-depth coverage of drug store news. Join the conversation.


text:
Foot rest for M2 - S3 Complete control system including sealed ball bearings and CNC milled pegs. These will move the peg position back 40mm and up 45mm. The changed gear linkage with it's double rod system provides exact gearchanges with less effort. No frame modifications necessary.
Please Note: Owners of Pre-2001 models will also require H-D OEM T0225.01A1 (Splined gear change and rod).
please specify color when ordering
Buell PartsBuell onderdelenpièces buellأجزاء بويلBuell teileビューエルパーツPartes buellBuell части
Twin Motorcycles Buell Support forever


text:
A poll asks a SRS of 1,000 tee
A poll asks a SRS of 1,000 teens whether they have a TV in their room. 64% of the sample said they have a TV in their room. Unknown to the pollster, the actual percent of teens who have a TV in their room is 66%.If we continue to take samples of teens from the same population, we will get a different sample proportion each time, due to sampling variability. What is the mean of that distribution of p-hats?
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|Número de publicación
|Tipo de publicación
|Número de solicitud
|Fecha de publicación
|30 Abr 1985
|Fecha de presentación
|26 Abr 1982
|Fecha de prioridad
|26 Abr 1982
|También publicado como
|Número de publicación
|Palmer W. Agnew, Joseph P. Buonomo, Steven R. Houghtalen, Anne S. Kellerman, Raymond E. Losinger, James W. Valashinas
|Cesionario original
|International Business Machines Corporation
|Exportar cita
|BiBTeX, EndNote, RefMan
|Citas de patentes (3), Otras citas (2), Citada por (93), Clasificaciones (23), Eventos legales (5)
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet
1. Field of the Invention
This invention is concerned with methods for partitioning the large instruction sets of mainframe computing systems in order that such partitioned sets can be run by a plurality of microprocessors. More particularly, this invention relates to methodology for partitioning mainframe instruction sets to obtain the most effective cost/performance emulation of the mainframe instruction set through microprocessor implementation thereof.
2. Description of the Prior Art
One noteworthy characteristic of this era of integrated circuits is that higher performance computers use lower levels of integration. This is the result of individual optimizations across the performance spectrum. Since the price of a state-of-the-art silicon chip is, on balance, independent of the level of integration, the price per gate is lower for microcomputers that for super computers. One result of this situation has been the complete reversal of Grosch's Law which stated that payment of twice as much for a computer would provide four times as much processing power. This meant that one would achieve the best cost/performance from the largest computer that could be justified when its resources were shared among many unrelated users. As amended by the most recent technological advances and designs, the reversal of Grosch's Law now implies that the best cost/performance will be obtained from the smallest computer that will perform an application in an acceptable time.
Large scale integration or LSI has played a major role in the cost/performance improvements of all computing systems, particularly in reducing storage costs. However, LSI has been much more effective in reducing the costs of low performance processors having simple architectures than of high performance processors having complex architectures. This property of LSI favors implementing high performance computers using large numbers of low performance processors and storage chips. However, this implementation is difficult to apply to existing complex architectures intended for uni-processors that process a single stream of instructions. This limitation is best understood by considering the basic nature and effect of LSI on digital designs.
Recent improvements in the cost/performance of digital computer systems have been driven by the availability of increasingly denser LSI chips. Denser LSI memory chips, with reduced costs per bit stored, have direct and obvious applicability to digital systems over the entire application range from hand held calculators to super computers. Denser LSI logic chips, however, apply most naturally to digital systems near the low end of the performance and complexity spectrum.
LSI, as previously noted, applies naturally to very small digital systems. The logic portion of a hand calculator, microwave oven, or wrist watch, including the necessary memory and I/O device interfaces, can be implemented on a single LSI microcomputer chip. A small personal computer can be readily realized by using a single microprocessor chip, to implement the entire instruction set of the computer, together with other LSI chips which implement the interfaces between the microprocessor and the memory, keyboard, display tube, disks, printers, and communication lines. This is an example of partitioning a digital system's function for implementation by several LSI chips. This functional partitioning method is simple, well known, and straightforward because the instruction processing function can be accomplished entirely by a single chip.
Methods of applying LSI technology to the implementation of still more powerful digital systems, in which the state of the LSI art does not permit implementing the entire instruction processing function on a single LSI chip, are far less obvious. A first approach would be simply to wait until technology advances far enough to contain a desired architecture, of a given complexity, on a single chip. Unfortunately, this approach has its pitfalls. For example, the architecture of each generation's state-of-the-art microprocessor was determined by the then current capability of the technology, which explains why today's leading microprocessors lack floating-point instructions. The most significant disadvantage of this method is that it precludes implementing a pre-defined architecture that does not happen to fit within one chip in the current technology. This has led to the major software problems inherent in having each generation of microprocessors implement an essentially new architecture.
Another method of employing LSI in the larger, more complex processing systems is to partition the instruction execution function so that the data flow is on one chip and the microcode that controls the data flow is on one or more other chips. This method is the obvious application of LSI technology, separately, to the data flow and to the control store. Unfortunately, this method relinquishes the main advantage of LSI implementation, namely, that of having the control store and the data flow that it controls, both on the same chip. In most processors, the critical path runs from control store, to data flow, to arithmetic result, to address of the next control store word. Its length, in nanoseconds, determines the microcycle time and hence the instruction processing rate of the processor. For a given power dissipation, a critical path that remains wholly on one LSI chip results in a shorter cycle time than that of a critical path that must traverse several inches of conductor and a number of chip-to-card pin connections.
This off-chip microcode partitioning method also requires what LSI technology is least adept at providing, namely, large numbers of pins. The data flow chip needs at least a dozen pins to tell the control store what microword to give it next. Even worse, the data flow chip needs from 16 to 100 pins to receive that control word. A processor using this method is often limited to roughly 16-bit control words, and hence a vertical microprogram that can control only one operation at a time, whereas a far higher performance processor could be designed if a 100-bit control word were available. If available, such 100-bit control words would permit a horizontal microprogram that can control several operations in each micro-cycle and thus perform a given function in fewer cycles. It should be noted that the off-chip microcode partitioning method has been particularly successful when applied to bit-slice processors, in which the data flow is not reduced to a single chip, but rather is a collection of chips, each of which implements a particular group of bits thoughout the data flow. Bit-slice processors usually employ bipolar technologies whose densities are limited by the number of gates available, or the ability to cool them, rather than by the number of pins on the chips. The off-chip microcode partitioning method applies to FET implementations only in more unusual cases where many pins are available and the chip density happens to exactly match the number of gates needed to implement the data flow of a desired processor. The Toshiba T88000 16-bit microprocessor happens to meet these conditions. Such an implementation can be best viewed as a bit-slice design in which the implementable slice width has widened to encompass the entire desired dataflow.
Each major microprocessor manufacturer has faced the need to implement an architecture more complex that can be put onto a single LSI chip. Some needed to implement pre-existing architectures in order to achieve software compatibility with installed machines. Others sought to enhance the functions of existing successful one-chip microprocessors by adding further instructions.
For example, Digital Equipment Corporation needed a low-end implementation of their PDP-11 minicomputer architecture. They chose the off-chip microcode partitioning method. The result was the LSI 11 four-chip set manufactured first by Western Digital Corporation and then by Digital Equipment Corporation itself.
Intel Corporation needed to add hardware computational power, particularly floating-point instructions, to its 8086 microprocessor systems. For this purpose, they developed a "co-processor", the 8087. A processing system containing both an 8086 chip and an 8087 chip operates as follows. The chips fetch each instruction simultaneously. If the instruction is one that the 8086 can execute, it executes the instruction and both chips fetch the next instruction. If the instruction is one that the 8087 executes, the 8087 starts to execute it. In the usual case where a main store address is required, the 8086 computes the address and puts it on the bus shared with the 8087. The 8087 uses that address to complete execution of the instruction and then signals the 8086 that it is ready for both of them to fetch the next instruction. Thus, each chip looks at each instruction and executes its assigned subset, but only the 8086 computes addresses.
Zilog Corporation similarly needed to add floating-point instructions to its Z8000 microprocessor and developed an Extended Processing Unit or EPU. A system containing a Z8000 and one or more EPUs works as follows. The Z8000 fetches an instruction. If the Z8000 can execute the instruction, it does so. Otherwise, the Z8000 issues a request for service by an EPU and supplies an identifier (ID) that it determines by examining the instruction. One EPU recognizes that ID as its own and begins executing. The EPU can use special wires to the Z8000 to instruct the Z8000 to move necessary data back and forth between the EPU and the main store. The Z8000 proceeds to fetch and execute more instructions while the EPU is working, and only stops to wait for the EPU if it requests service by the same EPU while that EPU is still busy. Thus, it is the responsibility of the Z8000 to start the EPU and respond to commands from the EPU. A great deal of execution overlap is possible in such a system.
National Semiconductor Corporation had a similar requirement to add floating-point instructions to its NS-16000 microprocessor systems. It called the NS-16000 a "master" and called the computational processor a "slave". In a system containing a master and a slave, the master fetches instructions and executes them if it can. When the master fetches an instruction it cannot execute, it selects a slave to begin execution. The master sends the instruction and any needed data to the slave, waits for the slave to signal completion, receives the result, and proceeds to fetch the next instruction. Thus, the master never overlaps its execution with the slave's execution and is responsible for knowing what the slave is doing and what it needs.
Data General Corporation needed an LSI implementation of its Eclipse minicomputer architecture. The resulting MicroEclipse family employs a one-chip processor that contains the data flow as well as the horizontal (35-bit) and vertical (18-bit) microcode for executing the most performance-critical instructions in the architecture. This processor can call for vertical microwords from an off-chip control store, as necessary, to execute the rest of the instructions in the architecture by making use of the on-chip horizontal microwords. This is a variant of the other approaches described above with some of the advantages of both the off-chip control-store method and the instruction-set partitioning of a main frame instruction set method.
Designs that partitioned off I/O functions for implementation on dedicated microprocessors were common and none of the advanced microprocessor partitioning methods previously discussed had yet appeared when the present invention was conceived. Partitioning of functions within a central processing unit for implementation on separate processors had been employed in super computers. Their goal was separate execution units for fixed-point, floating-point, and perhaps decimal instructions, that could overlap execution to achieve maximum throughput.
Accordingly, it is a principal object of the present invention to provide methods for implementing large system instruction sets in a manner that minimizes the critical path.
It is also a principal object of the present invention to provide a method of implementing large and/or complex instruction sets in a manner that retains the critical path on one LSI chip.
It is another object of the present invention to provide methodology for implementing large and/or complex instruction sets in an efficient manner that takes maximum advantage of LSI technology without the need of providing a very large number of different custom chips.
These and other objects of the present invention in using LSI to implement an architecture that is too large or complex to implement on one chip are realized by partitioning the instruction set of the architecture itself into subsets that are each microprocessor implemented. This method of utilizing select architectural subsets preserves the main advantage of a one-chip implementation, namely, keeping each critical path on a single chip. For each subset of the instructions, for which execution time is important to system performance, the corresponding microprocessor chip contains the data flow path and all elements, including registers, necessary for the execution of that subset as well as the microcode that controls execution. The application of this method requires partitioning that makes each identified important subset fit on one microprocessor in the current state of technology, a way to quickly pass control back and forth between all of the microprocessors, a suitable way to pass data back and forth between all of the microprocessors, and a technology in which it is economically feasible to have several copies of a complex data flow and control store mechanism.
The invention will be described further, by way of preferred examples thereof, with reference to the accompanying drawings wherein:
FIG. 1 schematically illustrates a partitioned mainframe instruction set in accordance with the present invention, said partitioned set having two overlapping subsets;
FIG. 2 schematically reveals the critical path of a computing system, in particular, the critical path as it is comprehended by the present invention;
FIG. 3 schematically depicts another partitioned mainframe instruction set in accordance with the present invention, said partitioned instruction set having four subsets, three of which are implemented by on-chip microcode and the other of which is implemented by higher level instructions stored in memory chips;
FIG. 4 schematically shows another partitioned mainframe instruction set in accordance with the present invention, said partitioned instruction set having two subsets, only one of which is implemented by on-chip microcode and the other of which is implemented by higher level instructions stored in memory chips;
FIG. 5 schematically depicts a further partitioned mainframe instruction set, partitioned in accordance with the present invention, said partitioned instruction set having only one on-chip implemented subset;
FIG. 6 schematically illustrates another partitioned mainframe instruction set, with said partitioning being implemented in accordance with the present invention by placing predetermined vertical microcode elsewhere than on the implementing microprocessor chip;
FIG. 7 schematically shows yet another partitioned mainframe instruction set, with said partitioning being implemented in accordance with the present invention by placing predetermined horizontal microcode elsewhere than on the implementing microprocessor chip; and
FIG. 8 schematically depicts still another partitioned mainframe instruction set, with said partitioning being implemented in accordance with the present invention by placing one subset and a collection of primitives on the implementing microprocessor chip.
Mainframe architecture can be microprocessor implemented in many ways with any one or more specific goals or criteria in mind. The goal of the present invention is to optimize cost/performance, not performance, at the low end of the mainframe spectrum. To achieve that end, it was decided to use a microprocessor that was general purpose in design, that was significantly microcoded thereby allowing architectural tuning and that had an appropriate number of 32-bit general purpose registers. Motorola's 16 bit processor, the 68000, was an excellent choice that fit this description rather well. This MPU implementation approach was selected due to projections that HMOS and comparable FET technologies would require a wait of several years before they would permit implementation of mainframe architecture on a single chip.
As used herein, the terms "mainframe architecture" or "mainframe instruction set" identify or refer to the architecture or instruction set of general purpose digital computers of the type that have a rich and varied instruction set, typically several hundred in number, a relatively wide word size, typically four bytes, and a complete methodology for handling exception conditions. The IBM 4331, manufactured by International Business Machines Corporation, is considered to be a such a mainframe computer at the low end of the spectrum. Further, as used herein, "System/370" is a term that identifies a range of computers, also manufactured by International Business Machines Corporation, the details of which are well known and publicly documented, that also fall within the scope of the foregoing definition of a mainframe. In addition, as used herein, the term "critical path" defines a path that runs from the control store, to data flow, to arithmetic result, to address of the next control store word. Its length, in nanoseconds, determines the microcycle time and hence the instruction processing rate of the processor. For a given power dissipation, a critical path that remains wholly on one LSI chip results in a shorter cycle time than that of a critical path that must traverse several inches of conductor and a number of chip-to-card pin connections.
The following descriptions of several approaches to solving the problems of single chip mainframe implementation are limited to the instruction processing portion of a computer. Each approach provides a local bus within the instruction processing portion on which one or more microprocessor chips can communicate with each other and with a local store. Each approach assumes that the local bus can be connected to a global bus to allow the instruction processing portion to communicate with I/O devices and main memory. At other times, the local bus is disconnected from the global bus so that separate communications can occur over the two buses.
The first approach to partitioning a mainframe architecture employs two specially microcoded microprocessors A1 and B1 that implement overlapping subsets of the architecture, as schematically depicted in FIG. 1. Each of the microprocessors is provided with on-chip microcode that replaces the standard microprograms that are usually found in a 68000. This overlapping emulation is achieved in the following manner. The mainframe architecture is partitioned into three sets named P1, Q1 and R1, with most of the high-frequency use instructions being in set P1.
As employed in this description, the terms "most frequently used instructions" or "high-frequency use instructions" or any other term having similar connotation refers to those instructions in the entire set that are used the most when a typical group of user programs is run on a mainframe and the resulting instruction mix is surveyed. It has been found that at least 70%, and usually 75%, of such frequently used instructions can be grouped in the key or prime subset, subset P1 in this approach, and will account for approximately 95% or more of use of the computing system.
The special microcode referred to above is written for the combination of sets P1 and Q1 to reside in processor A1 and microcode is written for the combination of sets P1 and R1 to reside in processor B1, as shown in FIG. 1. At any one time, only one of the processors is "active", and the other processor is "passive". Only the active processor fetches and executes instructions and controls the bus. There is no contention between the processors.
This approach functions in the following manner. Assume that the last several instructions have all been either in set P1 or in set Q1. Thus, processor A1 is active and processor B1 is passive. Note that the internal values of processor A1 (I-counter, general purpose registers, condition code, etc.) are up-to-date, and the internal values of processor B1 are not. If the next instruction is in set R1, processor A1 fetches this instruction and performs the following operations:
1. it places all of its internal values, that processor B1 might need in order to execute any instructions in sets P1 or R1, into a mailbox in a local store;
2. it taps processor B1 on the shoulder, telling it to become the active processor, that is, to read new internal values from the mailbox and to then execute instructions as long as instructions remain in set R1 or set P1; and
3. it becomes the passive processor until, sometime later, it feels a shoulder tap from processor B1 telling it to read internal values and execute an instruction in set Q1 and then continue executing all instructions up to the next instruction in set R1.
The sets P1, Q1, and R1 are selected based on the following criteria. First, all of the high-usage instructions are placed in set P1, which is common to both processors, thereby greatly reducing the frequency of swapping the active and passive processors. This is desirable because, between swaps, instructions are executed as fast as if they were all implemented in the microcode of a single processor. Second, the frequency of processor swaps is reduced still further if sets Q1 and R1 are selected in such a way that instructions in these two sets seldom interleave with each other. One particularly suitable instruction set partition scheme is to have set P1 contain only fixed-point, branch, and load instructions, have set Q1 contain only floating-point instructions, and have set R1 contain only decimal and privileged instructions. This selection satisfies both criteria. First, the fixed-point, branch, and load/store instructions represent about 75% of the execution time in a typical mainframe instruction mix. Second, although there is frequent interleaving of floating-point, branch, and load instructions with either fixed-point instructions or decimal instructions, there is much less frequent interleaving of floating-point instructions with decimal instructions. Therefore, there is relatively little performance lost to swapping active and passive processors if this selection of P1, Q1, and R1 is made. In fact, a need for both floating-point and decimal instructions in the same application is sufficiently rare that special-purpose systems containing only one of microprocessor A1 or microprocessor B1 could be attractive.
If a selection is made in which instructions in sets Q1 and R1 frequently interleave, but have rather independent internal value modification characteristics, then an additional manipulation could be used to shorten the processor swap overhead time. This would be to have the passive processor actually executing instructions in set P1 along with the active processor, listening to the bus, and updating its internal values, but not controlling the bus or affecting any external values. In addition, the passive processor would decode those instructions not implemented in its own microcode just enough to see whether each such instruction would affect its internal values other than the I-counter and Condition Code (CC). If so, the passive processor would set a bit indicating that it must read internal values from the mailbox when it again becomes the active processor. If it becomes the active processor when this bit is still reset, then the passive processor would read in only the I-counter and CC values when it thereafter accessed the mailbox. This strategy often reduces the time required to swap the active and passive processors, although it does not reduce the frequency of swapping.
It should be noted that the foregoing partitioning method keeps the critical path of either microprocessor chip to an absolute minimum, since there is no deviation from the path shown in FIG. 2. As used herein, the "critical path" in all of described approaches defines a path, as shown in FIG. 2 by way of example, that runs from the control store, to data flow (the dashed box), to arithmetic result, to address of the next control store word. The length of the critical path, in nanoseconds, determines the microcycle time and, hence, the instruction processing rate of the processor.
The second approach to partitioning, employs four microprocessors as shown in FIG. 3. Three of these, a primary processor A2 and two secondary processors, B2 and C2, are Motorola Corporation 68000s with special on-chip microprograms that replace the 68000's standard microprograms. The first of these specially microcoded processors A2 is utilized to implement I-cycles (instruction fetch and decode and effective-address calculation) for all instructions, and E-cycles (instruction execution) for the fixed-point, load, and branch instructions. The register space of this processor is used for the general purpose registers (GPRs). It should be noted that its on-chip microcode implements all functions that make heavy use of the GPRs, so the critical path remains on and is contained within one chip. The second of the special microprocessors B2 is employed to implement E-Cycles for floating-point instructions. Half of the register space in this microprocessor is used for the floating-point registers (FPRs) and the other half is used for work space. Again, the microcode is on the same chip as the registers and, of course, the data flow that it controls. An alternative design employs a different microprocessor chip that can execute floating-point instructions faster because its data flow is wide enough to process most common floating-point variables in parallel. The third of the specially coded microprocessors C2 is used to handle the E-Cycles for decimal instructions. All of the register space in this microprocessor is available for work space, since decimal instructions have storage-to-storage format.
The fourth microprocessor D2 is off-the-shelf, that is, it contains the standard Motorola microcode that implements the instruction set of the 68000. The part of the System/370 architecture not implemented by microcode, namely, privileged instructions, exception or error conditions, address translation misses, and interrupt handling, are simulated by sequences of 68000 instructions that are stored in a separate local store, rather than on a microprocessor chip. This is appropriate because these instructions and functions are used infrequently so maximum speed is not required, are error-prone so early models should have them in easily changed PROMs, and are voluminous so they can be written more economically in the relatively high-level 68000 machine language rather than in the very low-level 68000 horizontal microcode language.
A system containing these four microprocessors operates as follows. The first or primary microprocessor A2 fetches an instruction. If it can execute the instruction, it does so. If not, the primary hands off control to one of the other or secondary microprocessors, B2 or C2. This involves, first, passing necessary data such as the operation code and effective address in predefined local store locations and, second, setting a new value into the four-state circuit (Quatch) whose state determines which microprocessor has control of the local bus that connects all four microprocessors and their local store, in parallel, to the rest of the system. The selected secondary runs, with full control of the local bus and full access to the main store and I/O system, until it has completed execution of the instruction it was given. Then, it sets the original value back into the Quatch, handing control back to the primary. At this point, the primary looks at a return code in local store and proceeds to fetch the next instruction, or passes control to the off-the-shelf secondary microprocessor for instruction error handling. Note that this mechanism for passing control allows a secondary microprocessor responsible for floating-point or decimal instructions to call on the off-the-shelf secondary to complete an instruction that detected an error. Thus, the error handling function, which is voluminous and not critical to performance, need not occupy valuable control store space on the floating-point secondary chip.
The desirability of this approach's partitioning of the System/370 architecture can be seen by noting that the primary processor runs more than 75% of the time when executing typical job mixes, and has to hand only one instruction in twenty over to a secondary processor.
The third approach to partitioning is similar to the second, but only employs a single specially microcoded microprocessor A3 and a standard coded microprocessor B3. This approach combines the excellent cost/performance of on-chip microcode for the most critical functions with the flexibility, extendibility, and low development cost of off-chip microprocessor code for less critical functions. It uses the structure shown in FIG. 4 and works as follows. Processor A3, called the primary processor, contains the general purpose registers (GPRs) and the microcode for all functions that make heavy use of GPRs. It performs I-cycles for all instructions. It also performs E-cycles for the most frequently used instructions, that is, for almost all instructions except floating-point, decimal, and privileged instructions. In a typical instruction mix, the instructions that the primary processor executes constitute about 95% of the instructions by frequency of occurrence and about 5% of the instructions by execution time. Because the primary processor also performs I-cycles for all instructions, it actually runs more than 50% of the time.
The primary processor A3 is also responsible for detecting instructions for which it does not contain the execution microcode. It hands over control to the secondary processor B3 to complete such instructions. Most of the decimal, floating-point, and privileged instructions do a relatively large amount of data processing or are used very infrequently in typical instruction mixes. Therefore, the time to pass control from the primary processor to the secondary processor, and back, is relatively small. The secondary processor carries out the necessary processing under control of code contained in the local store. The same local store contains other registers, such as the floating point registers, and the mailboxes in which the processors leave instruction codes, operand addresses, condition codes, and other necessary data as they pass control back and forth. Control of the two processors is simple because only one of them is ever running at any one time. There is no overlap and no bus contention. Either processor can pass control to the other by inverting the state of the two-state latch that determines which of them is granted use of the bus.
It is important to note that a state-of-the-art microprocessor, the Motorola 68000, has been used to successfully implement a reasonably high-level machine language. This is the language in which most of the mainframe architecture is coded when using this approach to partitioning. Development of this code is rapid and inexpensive, in comparison to writing in a low-level microcode language. Moreover, the code resides in local store where it is easy to change, in comparison to microcode residing on a microprocessor chip. The corresponding disadvantage is that code implementing instructions tend to run longer than microcode implementing the same instructions. Therefore, there is a performance imbalance between the high-usage instructions, which are implemented in microcode, and the low-usage instructions, which are implemented in code.
The fourth approach relies heavily on software to implement parts of the architecture that cannot be placed on a single microprocessor chip, as is illustrated in FIG. 5. In using this approach, one first defines a suitable subset P4 of the mainframe architecture, implements this subset as the "machine" architecture of the microprocessor chip, and then writes a first layer of software to raise the level of the subset to the level of full mainframe architecture. The subset P4 must include sufficient instructions and functions to enable the first layer of software to simulate the rest of the mainframe architecture, including preservation of system integrity.
In some applications, no such first software layer is necessary. It might be possible to run some System/360 software, that which does not use new functions introduced in System/370, directly on the machine interface of the microprocessor chip. The selected subset might suffice for many OEM type applications, such as intelligent terminals, intelligent printers, and test-equipment control. Applications in turnkey "applications machines" could be written for the subset with customers or users never knowing that the subset was there. In other applications, missing instructions can be replaced by subroutine calls at compile time. In the remaining applications, the operating system, as shown in FIG. 4, can have a first layer that handles "invalid operation" program interruptions by simulating the missing instructions instead of passing these interruptions up to the next-higher layer.
This solution of the problem of insufficient control store space has the advantages of minimal hardware development cost, risk, and time, as well as excellent product cost/performance for applications that employ only the selected subset. However, it has the disadvantages of a large mix imbalance in any sort of software simulation of missing instructions, and an increased maximum interrupt latency time.
The three remaining approaches employ two levels of microcode. The fifth approach, shown in FIG. 6, has the advantages of using two levels of microcode with different widths. Current microprocessors achieve excellent cost/performance by allowing a single chip to contain both the control store and the data flow that it controls. Their cost/performance is further improved if the control store is wide, or "horizontal", rather than narrow or "vertical". A wide control store eliminates most decoding, so it reduces both complexity and propagation delay. In addition, a wide control store can control several simultaneous operations, so it improves performance. However, a wide control store usually needs to contain more bits than a narrow one in order to implement a given function. As used herein, the terms "narrow" or "vertical" storage or microcode are employed to signify that a use of a word length on the order of 16 bits, while the terms "wide" or "horizontal" signify a word length on the order of 100 bits. In between these two, although not used herein, is a midrange word length of approximately 32 bits.
One common solution to the problem of a large wide control store, has been described with reference to the Motorola 68000 microprocessor. This solution is based on noting that the information in a wide control store is highly redundant; i.e., many control words have bits that are identical. The solution is to have both a wide horizontal store and a narrow vertical store. The horizontal store contains the few, non-redundant control bit patterns required by the data flow. The vertical store contains the many bit patterns that are necessary for sequencing through many machine instructions. Such an approach is said to reduce the total control store size by about a factor of two in the Motorola 68000 microprocessor.
Even with this approach, current microprocessors have insufficient on-chip control store to implement all of the microcode that is necessary to implement an architecture as complex as that found in a mainframe. Yet, there is a major cost/performance advantage in having all of the horizontal microcode on the same chip as the data flow, to avoid the many pins or bus cycles required to bring a wide control word onto the chip, and there is a cost/performance advantage in having the most frequently used vertical microwords on the same chip as the data flow to avoid any accesses to the off-chip bus in most microcycles. This leaves only the infrequently used vertical microwords to be stored off the microprocessor chip, in a microprocessor-based implementation of a large system or mainframe architecture.
Such an implementation leaves two detailed design problems to be solved. These problems are accommodated in the following manner. First, branch from on-chip to off-chip vertical microcode by setting a latch attached to a microprocessor output pin, by restricting on-chip vertical micro read-only memory (ROM), for example to 512 words, and branching to a word whose address exceeds 511, or by branching to the highest valid on-chip vertical microword address after setting the off-chip vertical microword branch address onto the data bus. Second, allow conditional branches to depend on status bits by bringing up to 16 raw status bits off the chip, by way of the data bus or dedicated pins, just before the data bus or other dedicated pins are used to bring the next vertical microword on chip or by using the branch control fields of the horizontal microwords to select just the desired status information and bring off of the chip just the low two bits of the address of the next off-chip microword.
Note that most horizontal microwords will probably be used by both on-chip and off-chip vetical microwords. However, some specially written horizontal microwords will have to be put onto the chip just for the use of the off-chip vertical microcode. That is, the microprocessor, as seen by the off-chip vertical control store, should interpret a thoroughly general and flexible vertical microcode language. This provides the ability to implement a complex mainframe architecture. The on-chip vertical microcode provides very high performance for the most-frequently-used portions of that architecture.
Other advantages of this method of partitioning microcode are that it allows microcoding for high speed, since coding for smallest size is not necessary, it allows off-chip vertical microcode, written for a first product, to be put in the on-chip vertical microstore in subsequent products whose microprocessors have larger Read Only Memory (ROM), and it encourages a microprogramming methodology of first selecting a set of useful horizontal microwords, and then stringing them together with vertical microwords, which increases microprogrammer productivity.
The sixth approach, shown in FIG. 7, employs two sets of microwords that have the same width. One set is on the microprocessor chip and executes very rapidly. The other set is in an external store and can be very large. In a typical instruction mix, fixed-point, branch, and load instructions account for 95% of the instructions by frequency of occurrence, and for 60% to 75% of the instructions by execution time. Thus, these instructions are suitable candidates for this partitioning scheme to have on-chip. The remaining microwords, kept in an off-chip control store, are brought onto the chip one by one for execution. This could be done in several cycles using existing address and/or data pins for microword bits; or it could be done using dedicated pins. The off-chip control store must be wide enough for both the microword bits required by the data flow and the microword-selection bits required by the sequencer. The off-chip microword sequencer must have access to on-chip status information, in order to perform conditional microprogram branches and in order to pass control back and forth between on-chip and off-chip functions and instructions.
This method of partitioning the microcode necessary for implementing a complex mainframe architecture has the advantage of permitting an architecture of unlimited complexity to be implemented by use of a sufficiently large off-chip control store. Further, difficult parts of the architecture can be placed off-chip, where they can be corrected without altering the microprocessor chip itself. In addition, off-chip microcode written for a product so implemented may be placed on chip, with minimal modifications, if a subsequent product uses a microprocessor chip with larger on-chip control store. With care, patches to the on-chip microcode can be implemented in the off-chip microcode if errors are found. Since off-chip instructions are executed in the same engine as on-chip instructions, they have full access to registers, condition code, and other facilities of the machine yielding other advantages. A final advantage accrues from the fact that all accesses to main storage and channels are made by the same microprocessor.
The arrangement for partitioning microcode between on-chip and off-chip control stores allows the most frequently used instructions to benefit from the cost/performance of microprocessors due to the short critical path produced by on-chip microcode, and runs the remaining instructions and functions with the cost/performance characteristics of bit slices with the longer critical path produced by off-chip microcode.
The last approach, shown in FIG. 8, could produce a very economical processor at the expense of a difficult and prolonged development process. The most difficult aspect of this approach is defining suitable "primitive" operations. In principle, a microprocessor that contains on-chip microcode for a mainframe system's fixed-point, branch, and load/store instructions can be programmed to emulate the remainder of that system's architecture, as described under "Subset with Emulation" above. In practice, that design produces relatively poor performance for the instructions and functions that are emulated by off-chip code, rather than microcoded on the microprocessor chip. Microcoding some "primitives", instead of some instructions that could occupy the same on-chip control store space, can produce significantly higher performance on a complete instruction mix. A primitive is not itself a system instruction, but rather it executes a simple function that is useful in the emulation of more complicated instructions or functions. An emulation program can achieve higher performance if it has primitives available as well as the basic instructions. Examples of primitives are "load registers with contents of instruction fields", "set condition code according to arithmetic result" and " compute effective address."
This method of implementing a large system architecture on a microprocessor is itself implemented by subdividing the microprocessor's operation code space into the following three sets:
A. codes of high-usage instructions, each of which is implemented by a sequence of on-chip microcode;
B. codes assigned to primitives which are useful for emulating instructions, each of which is implemented by a sequence of on-chip microcode; and
C. codes of the remaining low-usage instructions, each of which is implemented by a sequence of high-usage instructions (A) and primitives (B).
In operation, an instruction stream is being fetched from store. As long as these instructions' codes are found to be in set A, execution is controlled by on-chip microcode. Any codes in set B are illegal, in this mode. When an instruction's code is found to be in set C, direct execution of on-chip microcode is terminated after completion of that instruction's I-cycles, which can include effective address generation. The instruction code selects a starting address in a private program store, and the microprocessor fetches its next "instruction" from this address. That "instruction" code will be in set A or B, so it initiates a sequence of on-chip microcode. This sequence ends by fetching another "instruction" which initiates another sequence of on-chip microcode, and so on, until the instruction whose code was in set C has been completely emulated. Then the next instruction is fetched from store, not from the private program store. That instruction, too, is either executed directly by a sequence of on-chip microcode, or simulated by "instructions" in the private program store, which are in turn executed by sequences of on-chip microcode.
It should be noted that the emulation mode used to program a low-usage instruction, whose code is in set C, has the following special characteristics. In this mode, "instructions" are fetched from the private program store, not from main store. The instruction counter is not incremented and codes in both sets A and B are legal while emulating an instruction in set C. In addition, interrupts must be held pending until all of the "instructions" that emulated one instruction in set C are completed. Any instructions in set A, that are used along with primitives in set B to simulate an instruction in set C, must be prevented from changing the condition code or taking their ordinary exceptions.
Some advantages of this method of partitioning the architecture between on-chip microcode and off-chip emulation code are as follows. An instruction in set C can be simulated with relatively few bus cycles. An "instruction" brought in from the private instruction store by one or two bus cycles, initiates a sequence of many microwords which do not require bus cycles. Constant data needed by difficult instructions or by interrupts such as Translate and Test's implied register, or interrupts' many implied storage addresses, can be brought in easily as immediate fields of "instructions" fetched from the private program store. Such constants may be difficult to introduce by way of on-chip microcode. An architecture of unlimited complexity can be emulated by a sufficiently large private program store, if the codes in sets A and B supply functions or sufficient generality. The private program store can be relatively small, because it stores relatively powerful "instructions" each of which is interpreted by many microwords. This is especially true if powerful branch and subroutine call "Instructions" are used to save space.
The transfer of control from on-chip microcode to an off-chip emulation program need not be limited to the time when an I-cycle completes. On-chip microcode should be allowed to call for simulation of the rest of an instruction whenever it detects an unusual condition, so it does not require high performance, that is difficult to handle and would otherwise consume many valuable on-chip microwords. For example, the on-chip microcode for Move Characters should be able to call an off-chip program if it detects operand overlap.
The foregoing description has been specifically directed to a methodology by means of which state-of the-art microprocessors can be utilized to emulate mainframe architectures. A comparison summary of the various approaches is presented in Table I. This table should prove useful in comparing each approach with respect to different measures of goodness. Although the present invention has been described in the context of preferred embodiments thereof, it will be readily apparent to those skilled in the appertaining art, that modifications and variations can be made therein without departing from its spirit and scope. Accordingly, it is not intended that the present invention be limited to the specifics of the foregoing description of the preferred embodiments. Instead, the present invention should be considered as being limited solely by the appended claims, which alone are intended to define its scope.
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Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION; ARMON
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text: #7130: scale2x scaling of 64x64 BeOS icons in Tracker ------------------------------------+---------------------------- Reporter: jscipione | Owner: stippi Type: enhancement | Status: in-progress Priority: normal | Milestone: R1 Component: Applications/Tracker | Version: R1/Development Resolution: | Keywords: Blocked By: | Blocking: Has a Patch: 1 | Platform: All ------------------------------------+---------------------------- Comment (by jscipione): I tried my hardest and I cannot find the screen shots of BeOS icons using the HQX algorithm but let me assure you that if I had found them they would not be very impressive. Transparency didn't work and the icons were cartoonist because of the anti-aliasing. Scale2x was the right choice. The patch has been applied, can we close this ticket? -- Ticket URL: <http://dev.haiku-os.org/ticket/7130#comment:11> Haiku <http://dev.haiku-os.org> Haiku - the operating system.