text:
|Publication number
|Publication type
|Application number
|Publication date
|Sep 5, 1995
|Filing date
|Nov 12, 1992
|Priority date
|Nov 12, 1992
|Fee status
|Also published as
|Publication number
|Paul Chang, Joseph W. Coates, Edward H. C. Ku, Simin H. Sanaye
|Original Assignee
|International Business Machines Corp.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (6), Non-Patent Citations (2), Referenced by (117), Classifications (7), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
The patent application Ser. No. 07/658,945, filed Feb. 21, 1991, entitled "Source Routing Transparent Bridge," U.S. Pat. No. 5,280,480, and commonly assigned describes a MAC bridge for handling either source routing information or transparent bridge information.
1. Field of the Invention
The present invention relates to communications network in general and in particular to devices for interconnecting local area networks (LAN).
2. Prior Art
The proliferation of LANs creates a need for devices which interconnect the LANs so that a data terminal equipment (DTE) on one LAN can communicate with DTEs on other LANs. The conventional LAN includes a transmission medium interconnecting a plurality of DTEs. For maximum efficiency, each LAN has a maximum number of DTEs which it can support. If the DTEs exceed the maximum number, the efficiency of the LAN goes down. Depending on the use and/or configuration of the LAN, there may be instances when the number of active DTEs on a LAN are maintained below the maximum number in order to maintain a certain level of performance.
To address the limitation requirements, it is known in the prior art to provide independent or separate LANs and interconnect them by interconnecting devices. The interconnecting devices are referred to by a variety of different names including bridges, gateway, router, etc. The interconnected LANs form a unified or combined network in which DTEs on one LAN may communicate with DTEs on other LANs via the interconnecting devices.
To a certain extent, LANs are somewhat like people, in that they come in a variety of different characteristics. The variety of different characteristics adversely affects the ease with which LANs are interconnected. The interconnecting devices have to compensate for the differing characteristics in individual LANs and provide a mechanism over which dissimilar LANs can communicate.
To better understand the difficulties which have to be surmounted in order to provide an efficient interconnecting device, some of the different LAN characteristics will now be described. Included in the different characteristics which have to be addressed in order to provide an effective interconnecting device are the type of transmission media and the types of DTEs forming the LAN. The transmission media may be copper wire, fiber optics, etc. Also, the DTEs may include work stations, PCs, file servers, etc. The LANs can be implemented using different topologies, operating at different speeds, with different formats and different protocols. The topologies usually define the LAN type whereas the format and protocols define the requirements under which a DTE gains access to the network. The speed of the LAN defines the rate at which data is transmitted on the network. For example, some of the typical LAN types include star or ring networks, busses, etc. Likewise, some of the typical LAN protocols include IEEE 802.3 CSMA/CD, IEEE 802.4 Token-Passing Bus, IEEE 802.5 Token Ring, ANSI X3T9.5 Fiber Distribution Data Interface (FDDI), etc. . Finally, typical network speeds are in the range of from 4M bits/sec to well over 100M bits/sec.
Another variable affecting the interconnectivity of LANs is the interconnecting architecture (hereinafter called bridging architecture) which is used to allow passing of a frame from one LAN to another LAN. The bridging architecture is usually used by the interconnecting device. The prior art provides two types of bridging architecture which can be used to interconnect LANs. The two architectures are "Source Routing" and "Transparent Bridging". Both prior art architectures and related protocols are fully described in the literature to be identified hereafter. Therefore, only a short description of each of the two architectures will be given here in order to identify the environment in which applicants' invention is used.
In the "Source Routing" architecture and related protocols, the specific route which a frame must traverse between one end station called the "Source" and another end station called the "Destination" is carried in the frame. Prior to issuing the frame with routing information, the "source station" issues an "explorer frame" which is propagated throughout the network to the destination station. As the explorer frame traverses the network, the bridge enters routing information such as bridge identification number, LAN number, etc. On arriving on the destination LAN, the explorer frame is copied by the destination station and is rerouted via the specific route to the origination station which stores the route information and uses it to send subsequent messages to the destination station. A more detailed description of the source routing architecture and protocol is set forth in various IEEE 802.1 and IEEE 802.5 draft standards for MAC bridges and Token Ring LANs and in an article entitled, "Table-Free Bridging" by Daniel Pitt and Jacalyn L. Winkler, (IEEE Journal on Selected Areas in Communication, Vol. SAC-5, No. 9, December, 1987, pp. 1454-1462).
In the transparent bridging architecture and related protocols, the routing information is not carried in the frame. Instead, the source and destination addresses in each frame and address tables in the interconnecting bridge are used to forward the frame from one LAN to another. In particular, the addresses of stations which are connected to respective bridged LANs are recorded and maintained in separate tables which are generated in the interconnecting bridge. When a source station on a first LAN wishes to communicate with a destination station located on another LAN, the destination address of the destination station is included in the frame. The interconnection bridge, on receiving the frame, compares the destination address with address entries in the address table which is associated with the first LAN. If a match is not made and the bridge is in a "forwarding state", the frame is forwarded to the other LAN. A more detailed description of the transparent bridge architecture and related protocols are set forth in International Standard ISO 10038 (IEEE Draft Standard P802.1d/D9).
For a variety of reasons, most if not all LAN users have a plurality of different LANs which have to be interconnected to and from the unified network. Due to the above described differences, the LANs may be viewed as non-homogeneous or heterogeneous networks. The challenge which the system integrator faces, in interconnecting these LANs, is to provide an interconnecting device which is able to satisfy the unique characteristics of the heterogeneous LANs and, at the same time, provide optimum services.
It is well-known in the prior art to use an interconnecting device such as bridges or the like to interconnect discrete LANs. The prior art interconnecting devices are described in the following U.S. Pat. Nos. 4,597,078, 4,627,052, 4,707,827, 4,737,953, 4,933,938 and 4,996,524. Generally, the prior art interconnecting devices are store and forward devices. The devices are provided with look-up tables in which the addresses for DTEs are stored. Depending on the philosophy of the design, the address in an incoming frame is compared with the contents of the look-up table and is either discarded or forwarded to another LAN. Even though there may be variations in the design of a particular patent, the broad store and forward approach is the underpinning for the prior art designs.
Even though the prior art interconnecting devices work well for their intended purposes, they do not possess the versatility to connect LANs with a wide variety of different characteristics. For example, the prior art interconnecting devices interconnect LANs which use the same type of transmission medium. Thus, a LAN using a wire transmission medium would be connected to another LAN which also uses wire transmission media.
Another area of deficiency in the prior art bridging devices is that DTEs using the source routing (SR) bridging architecture and those using the transparent bridging (TB) architecture are not connected in an efficient manner. As is exemplified by the cited patents, the interconnecting devices connect DTEs using the TB architecture or, as is exemplified in the above article by Daniel Pitt and Jacalyn L. Winklet, the interconnecting devices connect DTEs using SR architecture.
Still another area of deficiency in the prior art interconnecting devices is that there is no translation function so that LANs with different protocols can be connected and communicate. Instead, only LANs using the same protocols can be connected. Thus, a LAN using the token ring protocol can only be connected to other LANs using the same protocol or one using ethernet may only be connected to others using the same protocol and so forth.
Finally, the prior art interconnecting devices provide limited connectivity. Usually, only two LANs are connected via the same interconnecting device.
We believe that the above deficiencies place unnecessary restrictions which adversely affect the interconnectability of LANs.
It is a main object of the present invention to provide an interconnecting device which is more efficient than has heretofore been possible.
It is another object of the present invention to provide improved interconnecting devices which link heterogeneous LANs.
It is still another object of the present invention to provide an interconnecting device which links DTEs using both source routing (SR) and transparent bridging (TB) architectures.
The above and other objects are achieved by providing a heterogeneous multiport bridge which performs frame filtering, copying, forwarding and header conversion in a relatively short time interval.
In particular, the multiport bridge includes at least one LAN controller interconnected by a medium access device to a LAN. The LAN controller, in turn, is connected through a Bridge Port Frame Handler to a first high speed bus, called system control/address/data bus. Other units including a packet memory and a microprocessor are also interconnected to the bus.
The LAN controller and medium access device are responsible for receiving and transmitting information frames from and onto the LAN. The bridge port frame handler, among other things, does the frame filtering, copying and forwarding decisions for every frame it receives. If required, the bridge port frame handler also modifies the frame and relays it to the proper bridge port for retransmission. The packet memory temporarily stores frames which await additional services (such as retransmission or additional services from the microprocessor). The microprocessor performs bridge management functions and handles frames requested by the bridge port handler.
A second high speed bus,called a transparent bridge (TB) bus interconnects the bridge port frame handler, the microprocessor and a transparent bridge control and management (TBCM) unit. At least one isolator (ISO) device interconnects the at least one bridge port frame handler to the TB bus. The TBCM unit assists the bridge port frame handler to quickly identify the port to which transparent bridge frames are to be routed. As a result, bridging functions such as frame filtering, copying, forwarding, header conversion and other decision making are done faster than has heretofore been possible.
More particularly, the TBCM unit is coupled to a content addressable memory (CAM) and an SRAM. The workstation addresses are stored in the CAM. The routing parameters and signature information (such as, origination port ID, frame format, etc.) and bridge management status tags are stored in the SRAM. The microprocessor is responsible for enabling and disabling the TBCM, updating and maintaining the data bank (CAM and SRAM) table contents
The bridge port handler forwards, on the TB bus, to the TBCM destination addresses (DA), source addresses (SA) and optional frame format tag of received frames, The TBCM processes received information and returns to the bridge port handler results (such as target port ID, target port frame format, etc.), on the TB bus.
The foregoing features and advantages of the invention will be more fully described in the accompanying drawings.
FIG. 1 shows a block diagram of the interconnecting device according to the teachings of the present invention.
FIG. 2 shows a detailed block diagram of the transparent bridge control/management (TBCM) unit.
FIG. 3A shows a graphical representation of the contents address memory (CAM).
FIG. 3B shows a graphical representation of the SRAM 1 which stores signature information on the bridge port frame handler (BPFH).
FIG. 4 shows a graphical representation of the SRAM 2 which store "new" source addresses (SA) and other information to be entered in the CAM and/or SRAM 1.
FIG. 5 shows a partial general frame format.
FIG. 6 is a graphical representation of data format on the transparent bridge (TB) bus.
FIG. 7 shows a block diagram of the bridge port frame handler.
FIG. 8 is an event chart showing and explaining a typical transparent bridging (TB)/destination address (DA) match process.
FIG. 9 is an event chart showing and explaining a typical TB/source address (SA) match process.
FIG. 1 shows a functional system diagram of a device which interconnects local area networks such as LAN 1, LAN 2 . . . LAN n. The LANs may be homogeneous formed from a plurality of similar networks taken from any of the network types such as token ring, ethernet, token bus, fiber distribution data interface (FDDI), etc. The interconnecting device can be used to interconnect heterogeneous or a mixture of different LANs. In this regard, one or more of the LANs could be of one type while other LANs are other types. In addition, the interconnecting device can interconnect LANs which utilize different protocols. Each of the LANs are connected through LA Controller/Front End Module 1', 2'. . . n'. The LAN controller/front end modules are connected through transmit media 8 to Bridge Port Frame Handlers 1", 2". . . n". The bridge port frame handlers 1", 2". . . n" are connected through transmission media 9 to a high speed System Control/Address/Data Bus 10. Packet memory means 12 is connected through transmission media 14 to Bus 10. Likewise, Bus Arbiter 16 is connected through transmission media 18 to High Speed Bus 10. As is evident from the structure, LAN 1 is connected through LAN Controller/Front End Module 1', transmission media 8, Bridge Port Frame Handler 1" and transmission media 9 to high speed bus 10. Similarly, LAN 2 is coupled through like components to high speed bus 10 and so forth.
Still referring to FIG. 1, a microcontroller 20 is coupled through microprocessor glue logic 21 to High Speed bus 10. The microcontroller 20 includes a microprocessor and interconnected RAM/ROM. The function of the microcontroller is to manage the interconnecting devices Transparent Bridge Bus 22 is coupled through independent isolation (ISO) circuit means 24, 24'. . . 24n to respective ones of the bridge port frame handlers. Transparent Bridge Control/Management unit (TBCM) 26 is connected through appropriate transmission media 26' to Transparent Bridge Bus 22. The TBCM 26 is coupled through appropriate transmission media to SRAM 2, SRAM 1 and contents address memory (CAM). As will be described in greater detail hereinafter, the function of TBCM 26 and its attached SRAM 2, SRAM 1 and CAM is to identify Bridge Port Frame Handler to which a Transparent BridgeFrame (to be described hereinafter) is to be forwarded. The identified Bridge Port Frame Handler in turn routes the frame to the destination station on the LAN which it supports.
Before discussing the details of each of the above identified functional units, it is worthwhile giving a short summary of the type of frames that are usually transmitted through a bridging device. Broadly speaking, the frames are classified as a Source Routing Frame and a Transparent Bridge Frame. In a Source Routing Frame, the path that the frame travels in going from an origination station to a destination station, each of which are located on different LANs, are set forth in the frame. In a Transparent Bridge Frame, there is no routing information in the frame. Therefore, the interconnecting device has to determine the route along which the frame must travel from the origination station to the destination station. A more detailed description of the source routing and transparent bridging frames is set forth in the above-identified Pitt et al article.
Turning now to FIG. 5, a partial representation of a general frame format used to transport data within the interconnected network is shown. The frame format includes a header section A and information section B. Among the information which is carried in the header section is the routing information which is used to shuttle Source Routing Frames through the network. The information section, in turn, carries among other things, the data which one station wants to forward to another station. Other fields such as CRC, end delimiter, ect., follow the informational section also known as information field. It should be noted that detailed fields in each of the frame formats depend on the type of local area network. For example, a token ring LAN has a different frame format from an ethernet LAN, a FDDI LAN and so forth.
Notwithstanding the differences, the header section includes a destination address (DA) field and a source address (SA) field. It also includes a control source routing (SR) bit "R" which can be set by the originating station as a "1" or a "0". Usually when set as a 1, the frame is a Source Routing Frame. As described above, a Source Routing Frame carries a RI (routing information) field in which the route that the frame follows through the network is provided in the RI field. When the SR bit is set to a "0", this indicates a Transparent Bridge Frame and the route port of the frame has to be generated in the interconnecting device. The key to the interconnecting device of the present invention is the speed with which it allows a station on one of the attached LANs to communicate with other stations on other LANs. This requires efficient frame filtering, copying, forwarding and header conversion.
Referring again to FIG. 1, each LAN Controller/Front End Module and its attached Bridge Port Frame Handler can be viewed as a port (entry point) into the interconnecting device. With this characterization, the interconnecting device of the present invention can be construed as a multiport interconnecting device. The LAN Controller/Front End Module receives and transmits data frames from and onto the medium constituting the LAN to which it is connected. Each Bridge Port Frame Handler performs the frame filtering, copying and forwarding decision for every frame received, modifies the frame, if necessary, and relays the frame to the proper bridge port for retransmission. The-packet memory 12 stores the frames which await for the next services (retransmission or additional services from microcontroller 20). As stated previously, the microcontroller provides interconnecting or bridge management functions as well as handling frames requested by the Bridge Port Handler units. Having described the overall structure of the interconnecting device, the detailed description of selected functional units will now be described.
FIG. 2 shows a block diagram for the transparent bridge control/management (TBCM) unit and its attached SRAM 2, SRAM 1 and CAM. The TBCM 26, SRAM 2, SRAM 1 and CAM cooperate with the Bridge Port Frame Handlers to provide the bridging device with high speed (rapid) frame filtering, copying, forwarding and header conversion decision making. The TBCM includes DA/SA Data Buffer 28, CAM/SRAM 1 Process Engine (CSPE) Means 30, Contents Address Memory (CAM) means 32, transparent bridge (TB) bus arbiter 34, Aging Facility/Empty Entry Locator Means 36, Microprocessor Interface means 38 and Update Data Buffer 40. One set of outputs from TBCM 26 is fed over conductors 42, 44 and 46 to register (REG) 48 and MUX 50. The output from REG 48 forms an address bus into SRAM 1. Similarly, the output from MUX 50 form control signals and are transmitted over conductor labeled CNTL into SRAM 1. The output from SRAM 1 is fed over a data bus into register (REG) 52. The output from register 52 is fed over data bus 54 to TB data bus 22". It should be noted that transparent bridge (TB) bridge bus 22 includes TB control bus 22" and TB data bus 22'.
Another set of outputs from TBCM 26 is fed over conductor 56 to SRAM 2 Process Unit (SPU) 58 and over conductor 60 to SRAM 2 Process Unit 58. The output from SRAM 2 Process Unit 58 is fed over Address Control lines to SRAM 2. The internal interconnections between the functional units are made by appropriate transmission media as shown in the figure. For brevity, a detailed description of each of the interconnecting lines is omitted. The TBCM 26 is coupled to microcontroller 20 by microprocessor interface means 38 and bus 62. Isolator circuit 64 provides isolation function between microcontroller 20 and the TBCM 26. The ISO 64 is a conventional off-the-shelf isolator circuit module which can be set in a high state to isolate the TBCM 26, by signals from the microprocessor. Having described the functional units of TBCM 26, the function which each unit performs will now be described.
Still referring to FIG. 2, the DA/SA Data Buffer 28 is used to temporarily store the DA and the SA during each DA/SA address matching process (to be described hereinafter). If the incoming source address (SA) is "new" (i.e., no CAM matches) the incoming SA data, at the end of the SA process, stored in the DA/SA buffer is transferred to SRAM 2.
The TB bus arbiter 34 arbitrates the TB bus request from the attached Bridge Port Frame Handler (BPFH) ports. The ports can be arranged with different priority status and will be serviced by the TB bus arbiter 34 according to their status and the order in which the request is made over TB control bus 22". A First-In First-Out (FIFO) buffer is used in the TB bus arbiter 34 to track the non-priority ports request sequences. The TB bus arbiter 34 communicates over transmission media 63 with the CAM/SAM 1 Process Engine Means 30. The TB bus arbiter 34 also issues the TB grant to the appropriate BPFH port, requesting use of the TB bus.
The CSPE 30, CAM means 32, SRAM 1, registers 48 and 52 and MUX 50 form a central data bank means which stores source addresses of LAN stations and signature information. The signature information includes bridge port IDs, control information, etc. Source addresses for stations on respective LANs are stored in the CAM means 32. Likewise, the SRAM 1 holds the routing parameters or signature information, such as target BPFH port, QID, accepted frame format, etc. for stations on the LANS. The CAM/SRAM processing engine 30 is an execution unit which carries out the DA/SA matching process against data bank entries in the CAM. For each DA match, the engine reads matched entry location in CAM and uses the same CAM address to access the SRAM 1 to read out the signature information which is associated with the DA address. For example, if a matched address was found at CAM location 283, the same location address 283 would be used to access SRAM 1. The information found in SRAM 1 at location 283 would be the matching signature information for the DA address extracted from location 283 in the CAM means. Once the signature information is extracted from the SRAM 1, it is fed into register 52, over bus 54 to bus 22 and to the Bridge Port Frame Handler port which requests the information.
For any SA match, the CSPE 30 reads the match location in CAM and reads the paired SRAM 1 data, sets the time stamp bit (to be described subsequently) and writes back into the same SRAM 1 location. For match SA, the serviced BPFH ID must match the port ID in the SRAM 1. Otherwise, the matched entry will be removed from the data bank immediately and the processed SA will be treated as a no match SA. If no SA match occurs, the CSPE 30 tells SRAM 2 Process Unit 58 to move the SA data in the DA/SA buffer and its BPFH port ID into SRAM 2 "new SA" FIFO buffer for the microprocessor to process at a later time. The CAM/SRAM 1 Process Engine 30 in addition to performing the matching function and extracting signature information which is forwarded to the requesting bridge port, is also responsible for executing the data bank entry update and removal processes.
Turning to FIG. 3B for the moment, a graphical representation of the CAM and SRAM 1 structures are shown. The CAM is a self-contained off-the-shelf module which accepts an address, simultaneously compares it against a plurality of addresses and outputs a signal indicating the location in the CAM where a matched address resides. Suitable off-the-shelf CAMs include AM99C10A marketed by Advanced Micro Devices.
In FIG. 3B, the column labelled LOCATION indicates CAM addresses and SRAM 1 addresses. Therefore, the CAM can be addressed from location or address 1 through 8192. The CAM is used for storing stations' addresses and is six bytes wide. This means a station with six bytes of address can be stored in each CAM location. Of course, different size adresses can be used without departing from the scope or teachings of the present invention.
The SRAM 1 is 27 bits wide and has addressable location like the CAM. The relationship between the CAM and SRAM 1 is such that the address and signature information relating to that address are stored in like locations of the CAM and SRAM 1. For example, the signature information that is stored in location 256 of SRAM 1 is for the address which is stored in location 256 of the CAM. By using a common address for storing a station address and its related signature information, a single location address can be used to access the CAM and SRAM 1. The SRAM 1 bits includes a parity field, Table Management (TABLE MGMT) field including Port-ID, Next QID field, R reserved bits, remote QID field, and CCF field. The parity field stores a parity bit for each byte of data in the SRAM 1. The table management field stores management information relative to information stored in the table. The next QID or target QID stores information representative of the target or direct device.
The Port-ID field stored information representative of which port the source address is from. The R bits are reserved bits for future use. The remote QID stores information representative of in-direct target QID. The CCF field stores frame conversion information. The following Table 1 identifies and describes the SRAM1 bits. As is evident from the Table 1 and FIG. 3B, SRAM1 is twenty-seven bits wide, including twenty-four data bits and three parity bits.
TABLE 1______________________________________BIT # DESCRIPTIONS______________________________________24: Frame format test enable (TE) 0 = disable frame format test 1 = enable frame format test23: Protected entry22: Entry in use21: Time-Stamp tag20: FRAME FORMAT (VALID ONLY ON ETHERNET; 0 = ETHERNET, 1 = IEEE802.3)19-17: PORT ID16-11: QID1 (Forwarding port QID)10, 9: Reserved8-5: QID2 (Remote port QID)4-2: Frame conversion control field (CCF) 4 3 20 0 0 No frame conversion0 0 1 Convert to FDDI format0 1 0 Convert to Token-Ring format0 1 1 Reserved1 0 0 Convert to Ethernet format1 0 1 Convert to IEEE 802.3 format1 1 0 Reserved1 1 1 Generic Format1: Reserved______________________________________
With reference to Table 1, the first column, labeled Bit #, identifies respective bits within SRAM1 (FIG. 3B) and the column labeled Descriptions indicates the function which the bits provide. In particular, bit 23 is the "Protected entry" bit which indicates the table element is a permanent or static address element and that "Aging" should not apply to this element. As used in this specification, Aging is a technique which is used to delete an entry from the SRAM 1 and CAM (jointly called a look-up table). Unless entries are entered and periodically deleted from the look-up table, an oversized table would be required to store signature information for each station on the network. However, by using the aging function of the present invention, a relatively smaller size SRAM 1 is sufficient to store information about the active stations on the network. The "entry in use" bit 22 is a flag bit which reminds the microprocessor which one of the address table elements is in operation. The bit is set and reset by the microprocessor. The "time stamp tag" bit is a flag bit which is important to the address table element birth/aging process. Whenever a SA/AMmatch is detected, this flag bit (in the same address as the address here the match occurs in the CAM) is set to "1" by the TBCM to indicate hat the station is still "active". The microprocessor scans this bit of each entry periodically and decides when to delete the "age" address table element. In the alternative, if "auto aging enable" (to be described subsequently) is set, the microprocessor issues the auto aging command to TBCM which deletes the aged elements from the address table. As stated before, this deletion provides space for entering information about "New" LAN stations which are entering the network.
Still referring to Table 1, bits (19-17) identify the port which sends the source address (SA). Likewise, bits (4-2) are the frame conversion control bits. The setting of the frame conversion control bits indicates if the frame format is to be changed. For example, if the bits are all zeros, there is no frame conversion. Similarly, if the bits are 001' the frame is converted to FDDI format. The conversion is done by the Bridge Port Frame Handler which is communicating with the TBCM (FIG. 1). The functions of other bits in the table have already been described or are evident from the Table 1. This being the case, further description of the Table 1 is not warranted.
Still referring to FIG. 2, the Aging Facility and Empty Entry Locator Means 36 perform the aging function which deletes old entries from the CAM and SRAM 1 and locates empty location within the CAM and SRAM 1. Preferably the Aging Facility and Empty Entry Locator means are implemented in hardware. The aging facility hardware which could be a state machine scans the SRAM 1 Time Stamp (TS) bit, Entry in use (U) bit and Protected Entry (P) bit depending on their settings takes appropriate action. The below Table 2shows the bits which are scanned and the appropriate action taken according to the setting of the bits.
TABLE 2______________________________________P U TS ACTIONS______________________________________1 x x No action, go to next item.0 0 x No action, go to next item.0 1 0 Ask CAM/SRAM1 process engine to empty CAM entry, Zero out SRAM1 entry, Advance Aging entry deleted counter.0 1 1 Reset TS bit to "0", Advance Entry remained counter.x -- Don't care______________________________________
The aging facility begins the auto aging process when the microprocessor (FIG. 1) issues a start auto aging command. The aging facility begins at the beginning (i.e., the first entry in the CAM SRAM 1) and works it way to the last entry. After the last entry is processed, the aging facility sets auto aging completed flag and interrupts the microprocessor indicating that the auto aging process is now completed.
As soon as the aging command is detected, the Empty Entry Locator, also a hardware state machine, resets the empty entry found flag. It synchronizes with the aging facility state machines and starts from the first table location. When it detects the first available empty entry location, it freezes its pointer and sets the empty entry found flag. When the empty entry found flag bit is reset, the Empty Entry Locator continues to scan table entries until it either finds another empty entry location and sets the empty entry found flag or reaches the last table entry and sets the table resource exhausted flag to inform the microprocessor of the finding. Therefore, the Empty Entry Locator locates the empty entry location for table update.
The SRAM 2 Process Unit (SPU) 58 works with the CSPE 30 (FIG. 2) to store the "New" SAs and their correlated Bridge Port Frame Handler (BPFH) port ID and its frame format into the SRAM 2. The microprocessor, at its convenience, transfers the information from SRAM 2 into the Update Data Buffer 40 (FIG. 2) from whence it is transferred into the CAM means and SR 1. As is used in this specification, new SA refers to a source address which does not find a match in the CAM means. As stated previously, if there are no SA matches in the CAM, the address with its signature information is stored in SRAM 2 and is subsequently processed by the microprocessor. The SRAM 2 Process Unit (SPU) 58 also handles the event counts, the update statistical counters which are kept in the SRAM 2.
Turning to FIG. 4 for the moment, a graphical representation of SRAM 2 is shown. The SRAM 2 is a static random access memory, and in this embodiment, has 8,192 addresses shown on the left hand side of FIG. 4. As is evident from the first row in FIG. 4, the SRAM 2 is eighteen bits wide. The SRAM 2 includes an address section whose data includes a parity (P field) a port ID field (bits 16, 15 and 14), a frame format field (bits 13, 12, 11) and a reserve field (bit 10 through 1). As is evident from the right hand side, the SRAM 2 includes a plurality of counters, each one being listed to the right of the SRAM 2 buffer. It should be noted that the showing in FIG. 4 is only exemplary of the information stored in the SRAM 2 buffer and should not be used as a limitation on the scope of this invention.
Returning again to FIG. 2, the microprocessor interface unit means 38 provides communication between the microprocessor (FIG. 1) and the TBCM. To this end, the microprocessor interface means includes the microprocessor address decodes, the command, the status registers, the setup registers, etc. Details of the status registers, etc., are not shown because it is believed that such structures are well known in the prior art and is not necessary to understand or carry out the teachings of the present invention.
Still referring to FIG. 2, the Update Data buffer means 40 is a tri-section buffer having a CAM data section, an address section and a SRAM 1 data section. Its function is to store information for updating the CAM and SRAM 1. To this end, when the microprocessor wants to update and/or delete information in the CAM/SRAM 1, it first place the CAM data into the CAM data section of the Update Data Buffer, the CAM/SRAM 1 address location into the address section and the SRAM 1 and data in the SRAM 1 data register section. The microprocessor then issues the appropriate command (such as update CAM/SRAM 1 or delete CAM/SRAM 1). The CSPE 30 updates or deletes the table entry and inform the microprocessor when the process are completed.
Referring again to FIG. 1, the Bridge Port Frame Handlers are connected through individual isolation (ISO) circuitry to the transparent bridge bus 22. As stated previously, the transparent bridge bus 22 shuttles header information (SA/DA) and signature information between the TBCM and respective bridge frame handlers. The structure of the transparent bridge (TB) bus 22 is as follows:
A) 16-bit data bus which is common to all Bridge Port Frame Handlers (BPFH).
B) One request line per BPFH. The bus request line is raised when abridge Port Frame Handler wishes to use the bus. With reference to FIG. 2, permission to use the bus is granted by TB bus arbiter 34. The request line remains active until the BPFH services are completed.
C) One token bridge bus grant line per BPFH. The TBCM activates the grant line to the selected Bridge Port Frame Handler that is given permission to use the bus. The signal on the token bus grant line is used to activate the ISO circuits coupled to the Bridge Port Frame Handlers which are not granted permission to use the bus. The signal bus grant line remains active until the TBCM completes its TB service to the BPFH.
D) A DA/SA data flag tag which indicates whether the transmitted address is a data address (DA) or source address (SA) data.
E) Frame format flag tag which indicates the frame format of a SA packet.
F) Transparent bridge (TB) DA/SA data valid issued to the bridge port handler to indicate DA/SA data valid.
G) A TB result data valid for TBCM to indicate the validity of data transmitted to the Bridge Port Frame Handler.
FIG. 6 is a graphical representation of typical data format on the transparent bridge (TB) bus. The data format includes two bytes (high and low) and two parity bits. Table 3 below shows the structure of data (step A) from bridge port handler to the TBCM and the structure of data (step B) from the TBCM to the BPH when a match occurs. As was stated previously, the addresses (source address or destination address) is six bytes wide. As is evident from Table 3, bytes 0, 2 and 4 are the low bytes, while bytes 1, 3 and 5 are the high bytes. For each transmission, a high and a low byte are transmitted. Therefore, in the first transmission from BPH to the TBCM, bytes 0 and 1 are transmitted. 0n the second transmission, bytes 2 and 3 are transmitted and so forth. As is shown in FIG. 6, the TB Bus is two bytes wide. Therefore, three transmissions are required to transmit a DA or SA.
In step B, the TBCM writes destination match result to the BPH. The first column represents the bit numbers and the second column gives the description. The table is self-explanatory and a detailed description of each line will not be given. Suffice it to say that bits 3, 2 and 1 represent frame conversion control field. The action which the target bridge port must follow depends on the setting of the bits. For example, if all three bits are logical 0s, then no frame conversion is necessary. If bit 1 is a logical 1, bits 2 and 3 are 0s, then the target bridge port converts the frame to FDDI format before it is transmitted and so forth. It should be noted that if no DA match occurs, QID 1 is the default value.
TABLE 3______________________________________Step A - BPH sends DA/SA data to TBCM: HI-BYTE LO-BYTE______________________________________DA/SA Byte 1 Byte 0DA/SA Byte 3 Byte 2DA/SA Byte 5 Byte 4______________________________________Step B - TBCM writes DA match result to BPFH:BIT # DESCRIPTIONS______________________________________15-10: QID 1 (Forwarding port frame data QID)9: 0 = DA match found; 1 = no DA match found8: Reserved7-4: QID 2 (Remote port frame data QID)3-1: Frame conversion control field (CCF) 3 2 10 0 0 No frame conversion0 0 1 Convert to FDDI format0 1 0 Convert to Token-Ring format0 1 1 Reserved1 0 0 Convert to Ethernet format1 0 1 Convert to IEEE 802.3 format1 1 0 Reserved1 1 1 Generic format0: Reserved______________________________________
FIG. 7 shows a block diagram of the Bridge Port Frame Handler (BPFH) which interfaces respective LANs to the interconnecting device of the present invention. One BPFH device is required to attach each LAN to the interconnecting device. Therefore, if the interconnecting device, also known as a bridge, interconnects one LAN, one device is required. Two devices are required for two LANs, and so forth. The BPFH devices are identical. Therefore, only one will be described hereinafter with it being understood that the other devices are identical. Turning to FIG. 1 for the moment, each BPFH device is coupled to the LAN which it serves by aLAN Controller Front End Module. The LAN Controller Front End Module is LAN specific which means that the module only performs only MAC protocols specific to the LAN. For example, if the LAN Controller Front End Module attaches a token ring LAN, it performs that token ring protocol (also called IEEE 802.5). The IBM token ring network PC adapters (IBM Technical Reference #6165876) performs the token ring protocol. Other types of networks, such as token bus (IEEE 802.4), ethernet, CSMA/CD (IEEE 802.3), FDDI (ANSI X3T9.5, etc.) would be coupled by an appropriate adapter to the BPFH. Details of the various types of adapters are well known in the prior art and further discussion is not warranted.
Referring again to FIGS. 7 and 2, the BPFH has LANC bus 8 which interconnects it to the LAN Controller/Front End Module a TB/SR bus and ISO (isolation circuitry) which interconnects it to the TB bus 22 and interconnection to the system bus 10. The BPFH includes bridged frame Process Unit 66, receive frame buffer 68, transmit frame buffer 70, system bus interface unit 72 and hardware device driver 74. The system bus interface unit 72 interconnects the BPFH to the system bus. To this end, the system bus interface unit 72 transfers data, commands and interrupts. It performs hand shaking function with other devices on the system bus. It also tracks by the count of data transfer across the system bus. It manages data storage pointers, performs enqueue and dequeuing functions, etc.
The hardware device driver 74 interconnects the BPFH to its respective LAN Controller Front End Module (adapter). To this end, it initializes LANC, gets status counter values, receives frame data from LANC, handles receive frame protocols (interrupts, receive frame status, required frame receiver responds to LAN, etc.). The hardware device driver also transmits frame data to LANC, handles transmit frame protocols (interrupts, transmit frame status, required from transmit response to LANC, retransmit and transmit error, etc.). It also deposits receive frame data from the appropriate LAN into the Receive frame buffer 68, moves transmit frame data from the Transmit frame buffer 70 and forwards to LANC. The hardware device driver74 also interfaces with bridged frame Process Unit 66 to assist in the frame filtering/forwarding decision process. Finally, it interfaces with system bus interface unit 72 and assists in required microprocessor services.
The receive frame buffer 68 is an elastic buffer which receives data frames for subsequent transmission. Similarly, the transmit frame buffer 70 is an elastic buffer which temporarily stores frame for transmission. The receive frame buffer 68 and the transmit frame buffer 70 function to absorb system bus latency.
The bridged frame Process Unit 66 performs a frame routing function on received frames. To this end, it extracts frame control data, frame destination address data, frame source address, routing information field data, process them for frame filtering/forwarding and frame conversion (if required).
Among the various benefits which the multi-port MAC bridge of the present invention provides is high speed frame routing between LANs. The LAN type may be homogeneous (i.e., token ring to token ring or FDDI to FDDI or ethernet to ethernet, etc.) and/or heterogeneous (i.e., token ring to ethernet, etc.). In addition, the LAN media type may be the same or different (for example, optical fiber, copper twisted shielded pair, copper unshielded twisted pair, etc.). The message protocol can be source routing and/or transparent bridging. The bridge provides efficient frame filtering, copying, forwarding, and header conversion. The named functions are provided in a relatively short time.
In operation, the frames arriving at the Bridge Port Frame Handler are separated into Source Routing Frames and Transparent Bridge Frames. This is done by the Bridged frame process Unit 66 (FIG. 7) examining the R bit in the header section of the frame (FIG. 5). In the preferred embodiment of this invention, if the R bit is set to a 1, the frame is characterized as a Source Routing Frame. Source routing frames are those in which the routing information is provided in the RI field of the header. The receiving Bridge Port Frame Handler examines the routing information in the RI field and determines if the frame is to be forwarded. If it is to be forwarded, the frame is sent to the packet memory and the bus arbiter is notified of the immediate target to which the frame should be routed for processing and/or forwarding. It should be noted that the immediate target would be the microprocessor or another Bridge Port Frame Handler. Access to the system bus is granted by bus arbiter 16.
If the setting of the R bit is a 0, the frame is characterized as a Transparent Bridge Frame and the Destination Address (DA) followed by the Source Address (SA) is transmitted over the transparent bridge (TB) bus 22 (FIG. 1) to the transparent bridge control management (TBCM) unit 26. On arriving at the TBCM 26, the DA address is compared with the contents in the CAM (FIG. 2). If a match is found in the CAM, the signature information in SRAM 1 which relates to the matched address, is extracted and forwarded on the TB bus to the Bridge Port Frame Handler (BPFH) having control of the bus. The BPFH then forwards the received information and header to the BPFH serving the LAN on which the destination station is located. If the SA and DA is on the same LAN, the BPFH invoked the Frame Filtering Function to process (i.e., discard) the frame.
FIG. 8 is an event chart setting forth details of a typical Transparent Bridging Destination Address (TBDA) matching process. Briefly stated, the DA address which the BPFH sends to the TBCB is compared with the contents in the CAM. If a match occurs, signature information stored in like address in the RAM is extracted and returned to the BPFH. The signature information is used to reroute the related frame. Viewing the chart (FIG. 8) from left to right (columns) and top to bottom (rows), the first column labeled A indicates cycle time. The following columns indicate the various activities being performed between previously named and described components. For example, the second column lists in the first row "BPH-TB bus activities" which mean activities ensuing between the Bridge Port Frame Handler unit and the transparent bus. Similarly, TBCM activities refers to functions performed by the transparent bridge control management unit 26 (FIG. 1) to provide the matching process of the present invention. The other headings are self-explanatory and further description will not be given. The symbol "RP" in this chart represents Routing Parameters. Also, blank under a specific component indicates time slots in which there is no activity of the named component or unit. For example, there is no activity between TBCM and SRAM1 (col. 5) between the first and seventh cycle. Therefore, during this time interval, SRAM1 segments may be used to carry out the aging process previously described.
Still referring to FIG. 8, during the first cycle, col. 1, row 1, bridge port handler unit issues a request to the TB bus arbiter 34 (FIG. 2) for use of the transparent bus. The TB request stays active until the TBCM responds and completes its service to the requestor. Arbitration to use the bus occurs and is indicated at col. 3, row 1 as TB arbitration. The bus is granted during cycle 2 and is identified on the chart at row 2, col. 3 as TB grant. The TB grant stays active throughout the TBCM service. The other activities occurring between the various components are self-explanatory in this chart and further description will not be given.
If no match is found for the DA address in the CAM, then TBCM writes a no-match result which is forwarded to the BPFH unit. The no-match result is prepared by setting appropriate bits in the previously described Table III. In particular, a predetermined default value for the QID1 is set in bits 15-10 (Table III). Bit 9 is set to a logical "1" signifying no DA match found. All other bits in the table are set to logical "0".
Next, the SA is forwarded from the Bridge Port Frame Handler to the TBCM 26. The TBCM compares the SA with the contents of the CAM. If a match occurs, the CSPE time stamps the matched entry (set SRAM1 bit 21=1). If no match occurs, the SPU 58 (FIG. 2) works with CSPE to store the new source addresses (SAs) and their correlated BPFH port ID and its frame format into the SRAM2 for subsequent entry into the CAM/SRAM1.
FIG. 9 is an event chart listing the source address match process. The physical outline or format is substantially the same as FIG. 8. Essentially, the first column A' represents cycle time. The following columns indicate activities or functions done by the units named in the first row.
The source address is used for maintaining the different tables (i.e., SRAM1, SRAM2, etc.) used in this invention.
Still referring to FIG. 9, the first two cycles (Column A) relates to the request and grant of the transparent bus (TB). As previously described, the bridge port frame handler (BPFH) requests the bus which is granted by the TB bus arbiter 34 (FIG. 2). The BPFH uses three cycles (3, 4 and 5) to send the source address (SA), frame format and tags to the TBCM. The received information is stored in the TBCM. The SA is compared with the contents of the CAM (cycle 6). If a match occurs, the location or address of the match is read out (cycle 7) and is used to access or read SRAM1 (cycle 8). In particular, the TABLE MGMT field of SRAM1 (FIG. 3B) is of interest. The stored port ID is compared with the incoming port ID and the TS bit is set if the port IDs match (cycle 9). In addition, the SA, port ID, etc., are stored (cycle 8 through 12). It should be noted that while the TBCM is performing internal processing of SA matching, etc., another BPFH could raise a request (cycle 6) for use of the TB bus. The blank spaces in the table of FIG. 9 indicate that TB grant data transfers, etc., could be done simultaneously with the internal processing. The simultaneous operation further reduces the time required to route information through the multiport bridge. Finally, it should be noted that conventional timing diagrams instead of the event charts, FIGS. 8 and 9, could be used to explain BPFH, TB Bus, TBCM, SRAM1, SRAM2, CAM, etc., activities.
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
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|U.S. Classification
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|International Classification
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|European Classification
|Nov 12, 1992
Owner name: INTERNATIONAL BUSINESS MACHINES CORP., NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:CHANG, P.;KU, E. H.;SANAYE, S. H.;AND OTHERS;REEL/FRAME:006390/0217;SIGNING DATES FROM 19921028 TO 19921106
|Dec 2, 1998
|Fee payment
Year of fee payment: 4
|Mar 26, 2003
|Maintenance fee reminder mailed
|Sep 5, 2003
|Lapse for failure to pay maintenance fees
|Nov 4, 2003
|Expired due to failure to pay maintenance fee
Effective date: 20030905


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text:
Welcome to Limbic Studio!
Named for the deep, primitive structures of the brain, the studio, like the limbic system, is the anatomic seat of the emotions. Not only is making art emotionally engaging, but the product should engage you, the viewer, in all your senses.
The goal of these images is to kindle your limbic memory – for you to feel the mood, the summer warmth, the crisp autumn air, to hear the wind in the leaves, and especially to smell the New England marshes or summer fields. Olfaction (smell) is the oldest, most primitive sense; it takes us back, reliably and instantaneously, to another place and time.
Even the portraits, mostly commissioned pieces or family, pets and friends, should spark a connection; the personality, stage of life, contemplation, or certainly humor, should provoke a sense of reminiscence, recognition, or humorous curiosity.
I hope you enjoy the site - but even more, I hope you find the work evocative. ~ BJ Beck


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Simone Rocha: Fashion shows are like giving birth to really skinny ladies
Simone Rocha compares showing off her new pieces to "giving birth".
The Irish designer recently unveiled her Fall/Winter 14 collection as part of London Fashion Week.
When awaiting the reviews from critics Simone admits she finds it hard to cope with their comments.
"I'm not a weepy person normally, but, yeah, I cry... who came up with that idea?" she laughed to fashion.telegraph.co.uk when discussing how the international press critiques her pieces.
"It's like you've given birth. You've just given birth to 37 outfits, on 37 really skinny ladies and you're, like... [pretends to sob] But everyone's there waiting, asking, 'So ?' And I want to say, 'If you didn't get it, that's cool. Go away and digest it. That's fine with me!'"
Simone's latest range heavily featured plaid, gold and animal-print material with decadent ruffles.
There were also more fun pieces, such as a scarlet dress with a structured skirt.
She often uses the phrase "a little bit lady" to describe her designs and puts this down to her tomboy style when younger.
"I was a city kid. Lots of sportswear. There was a real-ness to it," she explained. "The look would be so different if people wore... Like, we wear a lot of trainers with the clothes. But if someone wore a stiletto we'd say, 'Oh no... you look completely different. You're goin' somewhere else.'"
Simone finds her approach to designing differs when creating alongside her mother. Her usual upfront persona is adjusted to suit her mom more.
"I'm very precise and headstrong. It's very funny working with my mum because we're completely different... She's, um, really nice!" Simone mused.
"I'm very yes or no. I know what I like and I don't like. That's how I work on my collection. I can be quite cut-throat with myself. I'll say, 'I know it's a good skirt but it's out. It's out!'"
Online Editors


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Price Supports And Exchange Rate Adjustments; Implications For Japanese Wheat And Beef Markets, 1960-83
An agricultural protection policy is very common among industrial countries. However, there are actual pro and con arguments for it because someone must bear its cost. Even in Japan, consumers themselves do not necessarily object to increasing the importation of agricultural products. It may not be easy for today's advanced industrial countries to determine the criteria for opening their agricultural markets completely since to implement this kind of policy adjustment, many difficult political considerations must be taken into account. The number of agricultural items restricted for import in Japan was reserved at 22, in 1983. This number was the greatest among the advanced industrial countries. According to the investigation by Yujiro Hayami, the price support rate of Japanese agricultural products, which shows how much higher the Japanese prices are in comparison with the rest of the world, was inferred at 45% in 1980. This number is regarded as almost twice the EC's and is similar to the level in Switzerland where agriculture is strongly protected in order to preserve the "Alps Agriculture". As general impression, people may think that agricultural protection policy in Japan must be adopted because the pressure of agricultural organizations on the government is so strong. Before World War II, the small textile or miscellaneous good industry which used labor intensive technology and cheaper labor was Japan's main industry for earning foreign exchange. For these small industries, the increase in food prices which would have forced a wage increase was a matter of life or death. Through the desperate resistance of these commercial and industrial concerns, even the political pressure of the agricultural organizations could not force the government to adopt agricultural protection policies. However, after World War Ii, especially during the High Economic Growth Period (from the 1950's), the Japanese industrial structure was transformed from a labor intensive form into a capital and knowledge intensive form. Further, owing to an increase in income of its wage-earning class, the rate of food costs against the household account was reduced and the degree of closer repercussion which had brought forth previous wage increases was also gradually reduced. In such a situation, Financial Circles and consumers began to lose their ability to resist the expansion of agricultural protectionism and the increase in prices of agricultural products as a matter of life or death. Through these political and economic processes, the level of Japanese agricultural protectionism was greatly raised during its high economic growth period. By inference, using the Agricultural Price Support Rate, at the beginning of the high economic growth period (1955) the rate was 15% and was lower then the EC's 23%. However, 10 years later, Japan's support rate exceeded that of the EC and reached that of Switzerland's. The ultimate purpose of this paper is to assess the welfare effects of price supports in Japan. However, there exists an external factor on agricultural trade, which is the effect of foreign exchange rates. Hence, another purpose is to infer Japan's benefits from the change of foreign exchange systems. The time period for these analyses is confined mainly to 1960 through 1983, and the agricultural products to be examined are limited to two - wheat and beef. Efforts will be made to answer the questions: 1) How much has Japan benefitted from the foreign exchange adjustments through the shifting of the system from a fixed to a floating exchange rate? and 2) How much have the producers benefitted and how much of the cost of the internal program have the consumers borne over this period?
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|Date of creation:
|Contact details of provider:
| Postal: Justin S. Morrill Hall of Agriculture, 446 West Circle Dr., Rm 202, East Lansing, MI 48824-1039
Phone: (517) 355-4563
Fax: (517) 432-1800
Web page: http://www.aec.msu.edu/agecon/
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Bad for Euroland, Worse for Germany-The ECB's Record
This paper assesses the contribution of the European Central Bank (ECB) to Germany's ongoing economic crisis, a vicious circle of decline in which the country has become stuck since the early 1990s. It is argued that the ECB continues the Bundesbank tradition of asymmetric policymaking: the bank is quick to hike, but slow to ease. It thereby acts as a brake on growth. This approach has worked for the Bundesbank in the past because other banks behaved differently. Exporting the Bundesbank "success story" to Euroland has undermined its working, however; given its sheer size, Euroland simply cannot freeload on external stimuli forever. While Euroland cannot do without proper demand management, the Maastricht regime and especially the ECB are firmly geared against it. The ECB's monetary policies have been biased against growth and have thus proved bad for Euroland as a whole. Meanwhile, the German disease of protracted domestic demand weakness has spread across much of Euroland. Yet, by pursuing its peculiar traditions of wage restraint and procyclical public thrift, the ECB's policies have had even worse results for Germany. Fragility and divergence undermine the euro's long-term survival.
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|34 pages
|Date of creation:
|17 Nov 2005
|Type of Document - pdf; pages: 34
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| Web page: http://econwpa.repec.org
References listed on IDEAS
Please report citation or reference errors to , or , if you are the registered author of the cited work, log in to your RePEc Author Service profile, click on "citations" and make appropriate adjustments.:
- Kromphardt, Jürgen, 2003. "Lohnpolitik bei möglicher Deflation," Wirtschaftsdienst – Zeitschrift für Wirtschaftspolitik (1949 - 2007), ZBW – German National Library of Economics / Leibniz Information Centre for Economics, vol. 83(8), pages 501-508.
- Hans-Werner Sinn, 2005. "Basar-Ökonomie Deutschland - Exportweltmeister oder Schusslicht?," ifo Schnelldienst, ifo Institute - Leibniz Institute for Economic Research at the University of Munich, vol. 58(06), pages 03-42, March.
- Kenen,Peter B., 1995. "Economic and Monetary Union in Europe," Cambridge Books, Cambridge University Press, number 9780521558839, March.
- Jorg Bibow, 2002. "The Markets versus the ECB, and the EURO's Plunge," Eastern Economic Journal, Eastern Economic Association, vol. 28(1), pages 45-57, Winter.
- George A. Akerlof & Andrew K. Rose & Janet L. Yellen & Helga Hessenius, 1991. "East Germany in from the Cold: The Economic Aftermath of Currency Union," Brookings Papers on Economic Activity, Economic Studies Program, The Brookings Institution, vol. 22(1), pages 1-106.
- Joerg Bibow, 2004. "Fiscal Consolidation Contrasting Strategies & Lessons from International Experience," Macroeconomics 0402014, EconWPA.
- Eckhard Hein & Achim Truger, 2005.
"What ever happened to Germany? Is the decline of the former european key currency country caused by structural sclerosis or by macroeconomic mismanagement?,"
International Review of Applied Economics,
Taylor & Francis Journals, vol. 19(1), pages 3-28.
- Eckhard Hein & Achim Truger, 2005. "What ever happened to Germany? Is the decline of the former European key currency country caused by structural sclerosis or by macroeconomic mismanagement?," Macroeconomics 0501007, EconWPA.
- Jorg Bibow, 2004. "Assessing the ECB's Performance since the Global Slowdown A Structural Policy Bias Coming Home to Roost?," Macroeconomics 0407026, EconWPA.
- Jorg Bibow, 2004. "Investigating the Intellectual Origins of Euroland's Macroeconomic Policy Regime: Central Banking Institutions and Traditions in West Germany After the War," Economics Working Paper Archive wp_406, Levy Economics Institute.
- Jorg Bibow, 2005. "Germany in crisis: the unification challenge, macroeconomic policy shocks and traditions, and EMU," International Review of Applied Economics, Taylor & Francis Journals, vol. 19(1), pages 29-50.
- von Hagen, Jurgen, 1993. "Monetary union, money demand, and money supply : A review of the German monetary union," European Economic Review, Elsevier, vol. 37(4), pages 803-827, May.
- von Hagen, Jürgen, 1992. "Monetary Union, Money Demand and Money Supply: A Review of the German Monetary Union," CEPR Discussion Papers 719, C.E.P.R. Discussion Papers.
- Jorg Bibow, 2004. "Assessing the ECB's Performance since the Global Slowdown: A Structural Policy Bias Coming Home to Roost?," Economics Working Paper Archive wp_409, Levy Economics Institute.
- C. Randall Henning, 1994. "Currencies and Politics in the United States, Germany, and Japan," Peterson Institute Press: All Books, Peterson Institute for International Economics, number 15, November.
- Adam S. Posen, 2003. "Is Germany Turning Japanese?," Working Paper Series WP03-2, Peterson Institute for International Economics. Full references (including those not matched with items on IDEAS)
This item is not listed on Wikipedia, on a reading list or among the top items on IDEAS.
When requesting a correction, please mention this item's handle: RePEc:wpa:wuwpma:0511018. See general information about how to correct material in RePEc.
For technical questions regarding this item, or to correct its authors, title, abstract, bibliographic or download information, contact: (EconWPA)
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text:
Mobile Wardrobe Cabinet - 48"W x 24"D x 67"H
Price $863.95Weight: 510.00 pounds
Add item to your cart for a shipping quote.Usually Ships within 4 - 6 Weeks
Stevens' Mobile Wardrobe Cabinet provides plenty of storage space for jackets, supplies, personal belongings and more. This durable particleboard cabinet features four adjustable side shelves on the right, a fixed accessories shelf and a coat rod. Casters make it easy to move the coat cabinet wherever you need it most. The doors are available with locks for an extra charge. Choose from several great colors for the laminate finish. Stevens' Mobile Wardrobe Cabinet is made in the USA and is GREENGUARD certified. No assembly required.
Key Features
- Particleboard cabinet with laminate finish
- Comes with four adjustable shelves, fixed accessories shelf and a coat rod
- Close the two doors to block contents from view
- Available with a lock for an additional charge
- Casters make it easy to move
- Made in the USA
- Material: Particleboard
- Finish: Laminate
- Shelves: 4 adjustable shelves, fixed accessories shelf and coat rod
- Doors: 2
- Assembly: Ship fully assembled
- Other Info: GREENGUARD certified; made in the USA
- Width: 48"
- Depth: 24"
- Height: 67"


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Women who have shared Linamen's hilarious life journeys in Just Hand Over the Chocolate and No One Will Get Hurt and Sometimes I Wake Up Grumpy... and Sometimes I Let Him Sleep know her writing to be funny, forthright and unforgettable. Linamen continues in her usual comedic style with this offering of 14 ways to combat the insufferable circumstances of life by embracing a sort of "insanity" as a solution in and of itself. Linamen's life is comparable to a leisurely read of the Sunday comics, and she tells all. Guaranteed to produce more than a chuckle, her suggestions for coping with life include stealing furnishings from one room to redecorate another, purchasing matching panties and bras to help enhance "boditude," and selecting a horror film to help a stressed-out spouse relax. Granted, these ideas are presented with tongue planted firmly in cheek, and even Linamen admits her blunders as she speeds along life's highway. She also balances the laughter with serious entreaties to seek for God amidst every circumstance. The author's deep faith, and her conviction that the Bible is the source for all help and direction, comes across plainly, as do her nudgings for women to seek Christ first and foremost. Closing out each chapter is a compact list of practical (read: serious) problem-solving ideas that do work outside of Linamen's funny-farm world. This text is sure to gratify the expectations of the author's faithful readers with a generous dose of the comedic retreat from the stresses of life. (Sept.)
Release date: 08/01/2002


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September 2, 2011,
By Allison Zisko
Sheer will and determination have earned tabletop newcomer Darbie Angell a high-profile spot at retail, a situation many big-time brands would covet.
Forced bedrest during a pregnancy made her reconsider her life's work. She had studied interior design as an undergraduate but did not want to open an interior design company. She liked "niche" items better, she said, and so started out designing a coffee press that she shopped around to small boutiques. Most of those stores were more interested in tabletop, however, and so she shifted her focus to dinnerware design.
Designing dinnerware appealed to her. Weddings are one of the few businesses that keep people buying, she reasoned, and that boded well for tabletop sales. She began to educate herself on the industry in a hurry, using Google as her guide. She funded her efforts by getting into the diamond trade; she bought diamonds in Israel and sold them in China.
Within five months she had found a factory in China (she has since moved her operations to Bangladesh) and started drawing. Lacking proper computer design tools, she created patterns in PowerPoint and used its line tools to indicate to the factory when she wanted to move something. Among her first patterns were Monaco, which has a very wide band of painted 24-karat gold, and Athena, a gold scroll design on white. The dinnerware is made of either bone or porcelain, and the metallic embellishments and use of rich color (as in the turquoise-hued Lauderdale) convey a sense of luxury, though a five-piece place setting retails for between $49.99 and $79.99. The goal, Angell said, is to give consumers something they can be proud of "without breaking the bank."
She named the company Cru Dinnerware because cru means "great strength," had a design student create a logo that included the umlat over the "u", and designed silk-lined, black-box packaging for "maximum impact."
Then came the hard part: selling the line to retailers.
"We had no contacts in this industry," Angell said. "We have great friends now, but in the beginning we were on our own."
Setting her sights on Macy's, Angell found the name of one of its home buyers online and made a cold call. Repeatedly rejected, she kept changing the last four digits of the telephone number until she eventually connected with Diane Narwid, Macy's buyer of fine china, Christmas china and ornaments. Macy's minority business office has transferred her to Narwid.
"We're from Texas," Angell said, referring to her two assistants and her brother, Aaron Wilson, who serves as chief operating officer, "and not a part of this industry at all. I didn't know how to present myself, but I think we were perceived well because we're different and we are who we are."
Norwid agreed to meet Angell during the fall tabletop market in New York, where Angell was showing products at the Carlton Hotel. Narwid walked her through the new-vendor process and gave her a primer on the tabletop industry. She explained Macy's routing guide, logistics and its style-out and assortment process, as well as gave her advice on industry standards, like what makes up a standard five-piece place setting, how bridal impacts the business, and what accessories are most important.
Bed Bath & Beyond picked up part of the line first, in 2009, initially offering the dinnerware online and then in various doors. Macy's followed suit in the spring of 2010. Three patterns are available on macys.com and in the retailer's top 10 A doors.
"Our selections were based primarily on design and trying to fill in a niche or void that we didn't have covered on our floor," Narwid said. "We review each pattern individually, not by vendor. We take into account the design, brand and price point. We think Darbie is a great personality, and in a very static industry thought the designs were good enough to throw into the mix and see what happened."
So far, there has been a fairly strong initial bridal read, according to Narwid, "especially in that this is an arena that is so dominated by powerhouse name brands. Our stores for the most part have been excited to have a fresh new brand and the press reaction has certainly been great, so time will tell."
The negotiating process with Macy's was worth it, according to Wilson. "Macy's is a perfect fit for our product," he said. "It strikes a sophisticated palate, but on an affordable scale."
Dillard's, meanwhile, carries some of Cru's recently introduced recycled glassware, a category another upscale department store is also considering, according to Angell. Cru is also considering branching into stemware, through a partnership with another vendor, and is considering additional categories, "possibly textiles."
Cru is developing several new dinnerware patterns for next month's tabletop market, including Madison's April in New York, a pattern inspired by a 14-year-old girl Angell met who wanted to be part of the tabletop industry, but who died from cancer before she had the chance. Angell is in the process of arranging a partnership in which the sale of Madison's April in New York which will help fund pediatric cancer research.
Angell is thri lled about her success with her new venture, but displayed some of the confidence that undoubtedly helped her achieve that success. "Anything can be done if you have passion and drive," she said.
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40+ Beers / 9 Breweries
Scion Restaurant and Crios Modern Mexican invite you to join us for "A Night of Extraordinary Ales."Scion and Crios will host 9 out-of-market breweries featuring over 40 beers in both draft and bottle. Participating breweries include Falling Sky, Foothills, Fullsteam, Funkwerks, Gigantic, Haymarket, Oakshire, Odell, and Two Brothers. Each of these excellent brands will bring a collection of rare offerings almost never available in DC. Representatives from each brewery will be in attendance to drink and talk about beer. Do not miss this opportunity to try some truly extraordinary ales.
Tickets or reservations are not required for this event. All beers will be available at 5:00 pm. Featured beers will be specially priced for the event. Additional information, including the full beer list will be made available at a later date.
Participating Breweries
Falling Sky - Eugene, OR
Foothills - Winston-Salem, NC
Fullsteam - Durham, NC
Funkwerks - Fort Collins, CO
Gigantic - Portland, OR
Haymarket - Chicago, IL
Oakshire - Eugene, OR
Odell - Fort Collins, CO
Two Brothers - Warrenville, IL
Draft List
Falling Sky Pan Galactic Gargle Blaster IPA
Falling Sky Sky Nectar Braggot
Falling Sky Spelt Rebel Dinkelbier
Falling Sky Wind Up Bird Best Bitter
Foothills Jade IPA
Foothills Seeing Double IPA
Foothills Sexual Chocolate
Fullsteam Hogwash Hickory Smoked Porter
Fullsteam Bourbon Barrel Aged Working Man's Lunch
Fullsteam Southern Lager
Funkwerks Bastogne
Funkwerks Saison
Funkwerks Tropic King Saison
Gigantic IPA
Gigantic Kiss the Goat!
Gigantic Ume Umai
Haymarket Indignari Imperial Stout
Haymarket Indignant Bourbon Barrel Aged Imperial Stout
Haymarket Degan Imperial IPA
Haymarket Lucy's Tripel
Oakshire Watershed IPA
Oakshire O'Dark:30 Cascadian Dark Ale
Oakshire Hellshire III Bourbon Barrel Aged Stout
Odell 90 Shilling
Odell IPA
Odell Lugene Chocolate Milk Stout
Two Brothers Cane and Ebel Rye Beer
Two Brothers Ebel Weiss
Two Brothers Northwind Imperial Stout
Bottle List
Bottle List
Foothills People's Porter
Fullsteam First Frost Persimmon Ale
Funkwerks Dark Prophet
Gigantic City Never Sleeps Black Saison
Gigantic Black Friday Cascadian Dark Ale
Gigantic End of Reason Quad
Gigantic Geezers Need Excitement Chocolate IPA
Gigantic The Royale Belgian Pale
Gigantic Time Traveler Porter
Oakshire Amber
Oakshire Overcast Espresso Stout
Oakshire Big Black Jack Chocolate Pumpkin Porter
Oakshire "6" Brandy Barrel Aged Barleywine
Oakshire Framboise Pinot Noir Barrel Aged Raspberry Beer
Odell Myrcenary Double IPA
Two Brothers Domaine DuPage Biere de Garde


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The teenager who persuaded the California Assembly to approve a No Cussing resolution earlier this month has a message for Vice President Joe Biden: Watch your mouth.
South Pasadena High School student McKay Hatch held a news conference Friday in front of his city's post office where he asked the vice president to apologize for letting a profanity slip during a bill-signing ceremony earlier this week.
Hatch, 17, said he also plans to mail Biden one of his No Cussing Club's penalty jars and an official club T-shirt.
Hatch founded the No Cussing Club at his junior high school in 2007. Since then he says it has grown to include chapters in all 50 states and 20 countries.


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When you purchase a MartinLogan product, you join an exclusive community of people who own and love the very best audio. We want you to be part of that family and join in the conversation with other MartinLogan enthusiasts.
Join our community today to keep track of your registered products, submit your own personal product reviews, and create a profile page to show off your MartinLogan system!
Ethos Customer Review
by Jim D., 5 years ago
I have had my Ethos for about a month now, and for once in my life I am speechless. As they begin to "Break In", I can actually detect specific sounds (vocals, instruments, breathing, etc.) that I swear were never present before. Please trust me when I say, and what I've heard time and time again, but they do make you believe that the band is playing live for you in your very own living room. Yes people, they are that good! To the men here who may need spousal approval to spend the significant amount of cash required for these, I strongly recommend that you take her to your nearest ML dealer and just let her see them; worked for me.
Jim D.
Edmonton, Alberta
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Ronan and Jessica O'Gara settle case over alleged unpaid €41k bill for new kitchen
RUGBY legend Ronan O'Gara and his wife Jessica today settled a case brought against them by a Cork-based luxury furniture company over an unpaid bill for a kitchen and appliances.
House of Coolmore Limited of Raheens, Carrigaline, Co. Cork brought the O'Garas before Cork Circuit Court on Washington St claiming that the couple failed to keep their end of a promotional agreement.
In its Civil Bill, House of Coolmore Limited had claimed that in June 2006 it had entered into an agreement with the O'Garas wherein it would supply and install a kitchen with appliances and other furniture.
The plaintiffs claimed that the terms of the agreement were that that the O'Garas would pay for some of the cost of the €76,166 worth of work, with the balance being discharged by the couple providing photographs of them in the supplied kitchen to House of Coolmore Limited for promotional purposes.
House of Coolmore Limited said that the kitchen was supplied by September 2006 and that they received €35,238 towards the cost of the work.
The plaintiff claimed that in July 2008 it paid a photographer to take promotional photographs of the O'Garas in the supplied kitchen, but that in October 2008 the couple refused to approve the promotional photographs for publication.
House of Coolmore Limited claimed that the O'Garas failed to approve the photographs or to pay the sums due.
Today the court heard that the matter could be struck out with no order by consent of both parties.
Neither the O'Garas, or representatives from House of Coolmore commented on the settlement as they left the court.
Online Editors


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Samsung AT&T CaptivateFiled under News by Adam on June 29, 2010 at 4:58 PM
Update: Want to know more about the Galaxy S phones? Check out our official Samsung Galaxy S Phone Guide.
Samsung's released an AT&T Captivate promotional video to highlight the features of the Captivate. The Captivate is the fraternal twin of the Samsung Galaxy S. While they share most of the same specifications, its packaged in a different box. The Captivate mimics the Galaxy S' plasticky-but-sleek style with its full plastic back. The AT&T Captivate will be upgradeable to Android 2.2 Froyo in the near future. But, it does in fact feature Android 2.1 out of the box.
Like the other Galaxy S phones, the Captivate will feature Samsung's exclusive Media Hub which will allow users to watch movies, television, and other premium content all in high-definition tailored to the Captivate's brilliant Super AMOLED screen.
The phone, like all other AT&T Android phones, will not allow for unsigned apps or app sideloading. AT&T has spoken out about the lock down saying,
"Android Market, managed by Google, is open to all developers. There is no approval process for applications, they are all accepted by default and Google has stated that they place apps in the Android Market within 24 hours of their submission. AT&T selected Android Market as the exclusive source for applications because it forces developers to be accountable for the apps they submit. If the Android community has issues with an app, the app can be flagged and removed. This minimizes the risk of malicious apps harming customers and provides more protection to the customer's private data stored on the phone."
But, with root on the Galaxy S, we should see these AT&T limitations axed by developers in no time. With the specifications we've seen on these Galaxy S phones, we think this one's a real iPhone 4 competitor. Check out our iPhone 4 vs. Galaxy S battle.
- 4″ Super AMOLED display
- 1 GHz Hummingbird Processor (1 GHz Cortex A8 by Samsung)
- 3D Graphics Engine onboard
- Android 2.1 Eclair
- 5 megapixel camera w/ auto-focus
- 720p video recording at 30 fps
- DLNA connectivity
- 16 GB Memory
- Samsung "Smart Life" custom UI
- Gyroscope w/accelerometer (six-axis motion control)
- No front-facing camera