text:
From 1 July 2011, private persons in Norway who buy electronic services from abroad must pay VAT. It is the foreign supplier of electronic services who must calculate and collect the VAT in these cases.
The Norwegian tax authorities have established a simplified system for registration and reporting.
The new rules and the simplified registration system are very similar to the rules that have been in force in the EU's member states since 2003. Several suppliers now included in the Norwegian system will therefore already be familiar with its content.
Information about VAT on electronic services follows below.
Electronic services sold by Norwegian suppliers to Norwegian consumers have been liable to VAT since 2001, but not sales to Norwegian consumers by foreign suppliers. From 1 July 2011, VAT must be charged when private individuals living in Norway purchase electronic services from foreign suppliers.
The Norwegian system is based on the rules that have applied in the EU since 2003 and guidelines from the OECD. The rules state that the jurisdiction where the service is consumed has the right to levy general consumption taxes – including VAT.>
As an alternative to normal registration in the Norwegian VAT system, foreign suppliers can use a simplified registration and reporting system when selling services to private individuals.
Sales to businesses and public enterprises (B2B) shall still be dealt with pursuant to the normal reverse charge rules.
The supplier can use the simplified system if it delivers electronic services or electronic communication services from abroad to Norwegian private individuals (B2C).
The supplier can also use the system if it also delivers electronic services to businesses and public enterprises (B2B).
The supplier cannot use the system if it is established in Norway or chooses to set up business in Norway. In such cases, the supplier has an obligation to register in the Norwegian VAT register, for example when the supplier has other turnover that triggers a duty to pay VAT.
If a supplier of electronic services delivers the services through the use of an intermediary, the intermediary shall be deemed to be the supplier. This means it is necessary to explain the distinction between the supplier and the intermediary:
The difference will be based on an overall assessment of whether 'the delivery takes place through the use of an intermediary'. It is not decisive whether underlying agreements between the parties classify the relationship as involving a subcontractor, intermediary, agent or commissioner etc. The definition of electronic services is mainly based on the delivery of the services. Who is contractually responsible for the content of the service is not necessarily decisive when assessing who must be registered. When deciding who the supplier is pursuant to the Value Added Tax Act, the most important factor is who is responsible for the actual delivery, i.e. who is responsible for transferring the files to the end user or gives the end user access to the digital content. Who collects payment from the recipient must also be taken into consideration. This provision means that those who sell electronic services through an intermediary cannot themselves be registered pursuant to section 2-1 third paragraph.
Electronic services are defined in the Norwegian Value Added Tax Act section 1-3 first paragraph letter j. The definition is based on the EU VAT Directive (2206/112/EU) and the EU VAT Regulation (Council Implementing Regulation NO 282/2011 of 15 March 2011). They can be used as guidelines when deciding what is included in the term electronic services.
Examples include the downloading of software, music, films, digital books and other electronic publications.
A foreign supplier of electronic communication services to Norwegian private individuals can also use the simplified system. This goes further than the current system in the EU. By electronic communication services is meant broadband telephony and internet access, among other things. Broadcasting services are also included, regardless of whether the broadcasting takes place via traditional radio or TV networks, the internet or other networks.
If the content of the service would be exempt from the duty to pay VAT in connection with domestic sales in Norway, VAT will not be charged in connection with the sale of such services from a foreign supplier to Norwegian private customers. For example, this means that VAT shall not be charged on the sale of services in the form of lotteries and games of chance delivered via the internet (online poker etc.) to Norwegian customers.
No. Suppliers included in the simplified system must use the system for reimbursement of VAT.
See here for more information.
Registration, reporting and payment take place by following the instructions at www.voesnorway.com.
The supplier is assigned an identification number and password.
The duty to register arises when the total value of deliveries to recipients in Norway exceeds NOK 50,000 during a period of 12 months. Suppliers who otherwise meet the requirements can nonetheless be registered in the simplified registration system before this amount limit is exceeded.
A supplier who falls below the amount limit of NOK 50,000 and who has not been deleted (see below), must nonetheless register in the system for two calendar years and calculate and pay VAT and submit VAT returns during this period.
The simplified system enters into force on 1 July 2011. Registration can take place from 20 June 2011. However, a confirmation e-mail will not be sent until 30 June 2011.
VAT must be declared and paid by the same deadlines as apply to the EU system, i.e. quarterly, with a deadline for the submission of returns and payment 20 days after the end of the period:
In the simplified registration system, the supplier must submit a VAT return stating its identification number, the calculation basis and the calculated VAT translated into Norwegian kroner. The amounts must be rounded off to the nearest whole krone.
Bank details for making payments
Payee:Skatte- og avgiftsregnskap P.O.Box 384891 Grimstad Norway
DNB Bank ASA SWIFT/BIC: DNBANOKKIBAN: NO5876940518888
IMPORTANT: It is essential that you use your 7 character scheme identification number (issued at registration) as the payment reference.
In the simplified registration system, the supplier must keep a list of transactions that concern the sale of electronic services to Norwegian private individuals. The list of transactions must be sufficiently detailed for it to be compared with the VAT return and thereby function as a means of control.
According to the Regulation to the VAT Act Section 15-10-1, the transaction record shall at least contain the following information
a) documentation reference
b) delivery date
c) name and residential address of customer
d) currency
e) fee, inclusive of value added tax, where the amount is given in Norwegian kroner, and
f) value added tax.
The list of transactions must be stored for 5 years and, at the Norwegian tax authorities' request, it must be made available electronically within three weeks.
As regards compliance with the regulations, suppliers in the simplified registration system will be subject to most of the Value Added Tax Act's general administrative provisions. Among other things, this means that the suppliers will have a general duty to disclose information that has a bearing on VAT control and that the VAT authorities can obtain information about the suppliers from third parties. It also means that the VAT authorities can stipulate VAT by discretionary judgement and otherwise impose sanctions such as additional tax or penal sanctions if a supplier provides incorrect or incomplete information or fails to submit a VAT return.
A supplier will be deleted from the simplified registration system when the enterprise ceases trading or when the conditions for using the simplified registration system are no longer met. A supplier will also be deleted if it repeatedly fails to fulfil its obligations pursuant to the Value Added Tax Act.
Deleted suppliers who still engage in activities that are liable for VAT are obliged to register in the Norwegian VAT register through a representative.


text:
I Guess Dennis Rodman is a Reason to Download a Card-Based Basketball Game
The last time I saw basketball bad boy Dennis Rodman in a way that registered with me at all was on stage at a Counting Crows / Live concert in the early 2000s. Now he's helped Hothead Games make Big Win Basketball. I'm still only mildly impressed.

subset: commoncrawl


text:
|Publication number
|Publication type
|Publication date
|Nov 12, 1974
|Filing date
|Nov 1, 1971
|Priority date
|Nov 1, 1971
|Publication number
|Jen D, Lotan A
|Original Assignee
|Bunker Ramo
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (11), Referenced by (29), Classifications (5), Legal Events (1)
|External Links: USPTO, USPTO Assignment, Espacenet
United States Patent Lotan et al.
[ 1 Nov. 12, I974 l l METHOD AND APPARATUS FOR INTERFACING WITH A CENTRAL PROCESSING UNIT [75] Inventors: Amram Zvi Lotan, Holon, Israel;
Dixson 'Ieh-Chao Jen. Monore Conn.
[73} Assignee: Bunker Ramo Corporation, Oak
Brook, lll.
Filed: Nov. 1, 1971 211 Appl No: 194,677
[52l U.S. Cl. I. 340/1725 [Sl Int. Cl. H G03f 3/04 [58] Field of Search 340N715 I56] References Cited UNITED STATES PATENTS Primary EvrumineF-Gareth D. Shaw Assistant Examiner-Melvin B Chapnick Atrorne \',/lger1r.0r FirmF. M. Arbuckle; R. J Kransdorf [57] ABSTRACT An interface unit for controlling the transfer of infon mation between a plurality of data bearing lines at least some of which are fed by input/output devices, and a central processing unit. Since information may be received at at least two different priority levels. the unit includes a means for detecting the priority level of received information. When the unit receives infor mation, it stores the information in an addressable buffer memory in an area allocated to the particular priority level and informs the CPU that information at the priority level is available. The address at which the information is stored is determined from an input address memory which storcs the address at which the next item of information at each priority level is to he 331L055 WWW MU/I725 placed. The CPU then interrogates the unit causing 3 5.394 WW6? Cottrcllilr 340M725 v 3396-572 8H9 Culvert 340/1725 mlormation to be transterred trom the buftei memory 3.399384 8/1968 Crockett at al 340/1725 m the .QPU Comml of "P i 3 149 722 6/1969 Tucker H 340N715 ory which contains the address in the buffer tor each 1453mm 7 19 g rr cl MW 340/1735 priority level of the next item to be transferred to the 3,456,244 7/1969 Seichter et all, 340M725 CPU. An output buffer memory is also provided in the 534.339 0 Rosc alt 340/1725 unit. When the CPU indicates that it has data to trans- 5 3fl Ill97| Bhrnhllrdl 340/1715 mit. data is loaded into this memory in a position cor SW t l responding to the intended device a character at a U m time. Each time the unit is ready for another character from the CPU, the CPU is informed of this fact.
I9 Claims, 13 Drawing Figures 2 Sir/6H spa-0 Y/VC/MO/VOILS L //v PROCESSOR WrffiFfiCf CIRCUIT 22 21 25 Mffl/l/M 525m gflg pc s 7' HSY/VCf/fifl/(OOS LINE hvrffiitflc gal/RC5 e c/flcu/r [Z 26 56' l0 J5 /005 was L T 3 M/TERFHCE 0 CPU 36 c/Acu/ r j 1 /o 05 we; Afi 52 0V/C IIVTERF/YCE C/RC U/ 7' PATENT 33v 1 2 I974 sum 07 nr 10 NEW Q 0 :Qu kWWWW Why wmi
ma l PATENTE HEY I 2|974 SHEEI RE C 5/ V5 I Y/VOV/M/VOUS Ml RECf/V' IOL M005 WITH 60!? 3=0 152' (qswcflnawaus UN! 6055 zow YES COMB; SE?
(comm: cons WITH Ac;
40190 ,qci Mm COMB mmmavr cou/vr 11v Map am 94!) M n sr M50 :5?
NO YES 7 rcsr can I2=l? if! 00] (00M INTO COD $HIFTIVW 8/7 INTO C)? TEsr cap/m =0 TEJTLINF $774M. LOW? YES SHIFT 0 INTO C)?! SET CHDRZ 70 L000 Cflfifl INTO (HP 7 YES Raono (RDR IN 70 CHDM REED OUT [DIM H7 ADDRESS F01? PRIOR! T Y 0F 10C 800175 55 L090 mm; Inc INTO IDBM m HDDRESS IND/607E!) av [DIM SET 1P4. M/CfiL-ME/VT [DIM RESEI' (0M 9/2 =0 L080 HLL 1'5 INTO CHDR 555 FIG. 4B
METHOD AND APPARATUS FOR INTERFACING WITH A CENTRAL PROCESSING UNIT This invention relates to a method and apparatus for controlling the transfer of information between a plurality of data-bearing lines and a central processing unit and more particularly to a unit for effecting such transfers where the data being transmitted may have various priority levels.
The central processing unit (CPU) of most data processing systems is capable of performing only a single function at a time. Thus, when the CPU is receiving information from a piece of peripheral equipment or over a transmission line from another CPU, or when the CPU is generating information for one of these devices, the performance of other operations by the CPU must be interrupted. The duration of the interrupt must be long enough to permit the CPU to receive or transmit the required data. However, the speed of the CPU is generally many times greater than that of the lines and devices feeding into it. Thus, some sort of an input/output interfacing device is required in order to minimize the amount ofCPU time required to service the various data transmission operations.
In order to minimize the cost of an l/O interfacing device, the amount of hardware per device or line contained in the interface should be minimized. However, the interface must still be capable of operating with a great variety of I/O devices having variable speeds, priority requirements, clocking schemes, and other interface requirements. The interface should thus be versatile enough to handle various [/0 equipment which it is known that the CPU will interface with as well as to handle possible additional devices which it may be called upon to handle in the future without requiring substantial hardware changes in the interface itself. To some extent, this versatility may be achieved by permitting much of the interface operation to be controlled programmatically from the CPU. However, the actual CPU time required for servicing the interface should be minimized.
It is therefore a primary object of this invention to provide an improved input/output interface unit for a CPU.
A more specific object of this invention is to provide an I/O interface unit which permits great versatility in the nature of equipment which may be serviced thereby with little if any hardware changes being required in the interface hardware to accommodate a new type of I/O device.
Another object of this invention is to provide an interface unit of the type indicated above which requires a minimum amount of CPU time.
A further object of this invention is to provide an interface unit of the type indicated above which is capable of handling priority assignment allocations for the various devices serviced thereby.
In accordance with these objects, this invention provides an interface unit for controlling the transfer of information between a plurality of data-bearing lines, at least some of which are fed by input/output devices, to a central processing unit. The received information has at least two different priority levels. The unit includes a means for detecting the priority level of each item of information applied to the system and a means responsive to the detecting means for informing the CPU of the availability of information at the detected priority level. An addressable memory is also provided, the memory having an area allocated to each priority level. The unit also has an input means for indicating the ad dress in the memory at which the next item of information at each of the priority levels is to be stored and an output means for indicating the address in the memory at which is stored the next item of information at each priority level to be transferred to the CPU. Each ap plied item ofinformation is stored in the memory under control of the priority detecting means and the input address indicating means. Each item of information is transferred from the memory means to the CPU under control of the CPU informing means and the output address indicating means. The input address indicating means and the output address indicating means are each incremented for the appropriate priority levels when they are utilized and the unit includes a means operative after an information transfer to the CPU for comparing the addresses indicated by the input and output indicating means. The informing means for the detected priority level is reset when the comparator ad dresses are equal.
An output buffer memory is also provided in said unit. When the CPU indicates that it has data to transmit, data is loaded into this memory in a position corresponding to the intended device a character at a time. Each time the interface is ready for another character from the CPU, the CPU is informed of this fact thus freeing the CPU from continuously having to monitor the transmit operation.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention as illustrated in the accompany ing drawings.
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic block diagram of a computer system in which the invention is utilized.
FIGS. 2A 2C, when combined as shown in FIG. 2, form a schematic block diagram of a preferred embodiment of the invention.
FIG. 3 is a chart illustrating the contents of the con trol memory shown in FIG. 28.
FIGS. 4A 48, when combined, form a flow diagram of the operation of the system shown in FIGS. 2A 2C when receiving synchronous data.
FIG. 5 is a flow diagram of the operation of the system shown in FIGS. 2A 2C when receiving asynchronous data.
FIGS. 6A 6B, when combined, form a flow diagram of the operation of the system shown in FIGS. 2A 2C when transmitting data.
FIG. 7 is a schematic block diagram of a portion of the circuit shown in FIG. 2C for an aiternative embodiment of the invention.
GENERAL SYSTEM DESCRIPTION Referring to FIG. 1, it is seen that a central processing unit (CPU) 10 is connected to an input-output control unit (IOU) 12 through lines I4. As will be seen later, data, addresses, or commands may pass over the lines 14. Since the quantity and type of devices interfacing CPU I0 through IOU I2 will vary with each ap plication, the configuration shown in FIG. I merely illustrates the various types of inputs. Thus, another processor 16 which may itself have an IOU and modems or other interface circuits is connected through a high speed synchronous line 18, a suitable interface circuit which may again be a modem or other special circuitry to be described briefly later, and a line 22 to one input or port of IOU 12. Since information may pass from processor 16 to CPU 10 or from CPU 10 to processor 16, lines 18 and 22 are both bidirectional lines. A broadcast source 24 may send data through a medium speed asynchronous line 26, a suitable interface circuit 28, and a line 30 to another port of IOU l2. Broadcast source 24 may, for example, be a newswire or, in stock market applications, a ticker source. Since broadcast source 24 does not receive information from CPU 10, unidirectional lines may be utilized for the lines 26 and 30. The interface circuit 28 may be a standard modem, A portion of the interface circuitry utilized with a bidirectional asynchronous line will be described later. A third port of IOU 12 may be connected through bidirectional lines 32 to an interface circuit 34 which is in turn fed by a plurality of I/O devices 36 over bidirectional lines 38. The devices 36 would normally be low speed devices such as keyboards, the scanning of which may be multiplexed without the loss of information. A higher speed l/O device 40 is connected through a line 42, an interface circuit 44, and line 46 to a separate port of I/O device 12. Lines 42 and 46 are bidirectional and line 42 may be either synchronous or asynchronous depending on its speed and other considerations.
GENERAL DESCRIPTION OF PREFERRED EMBODIMENT OF THE INVENTION Referring now to FIGS. 2A 2C, a block diagram of IOU 12 is provided along with certain elements of CPU 10 and interface circuits such as 20, 28 and 34. Briefly, a character of information to be received by CPU 10 is applied to the system a bit at a time. Input-output scan control (IOSC) circuit 50 (FIG. 2A) selects the line being monitored by the IOU at any given time. An input address counter (IAC) 52 (FIG. 2B) controls the line selected by IOSC S0. Counter 52 is normally being incremented at a rate many times greater than the rate at which the fastest device being monitored applies bits to the IOU. Thus, each received bit is scanned many times. For each address indicated by IAC 52, there is a memory position in character assembly disassembly memory (CADM) 54. Each time IAC 52 changes address, the memory position in CADM corresponding to the new address is read out into character assembly disassembly register (CADR) 56 (FIG. 2A) (conditions under which this read out does not occur will be mentioned later). If the line being monitored has a bit to be applied to the IOU, this bit is shifted into CADR 56. Before IAC 52 is again incremented, the new word now stored in CADR, or the original word if there is no change, is read back into the appropriate memory position in CADM 54.
The above sequence of operations is repeated with a new hit being shifted into CADR each time it appears on the monitored line until an indication is received that a full character has been loaded into CADM for a particular line. At a subsequent time, when the contents of CADM are read out into CADR, the assembled character is passed through lines 58 and OR gate 60 to be stored in input data buffer memory (IDBM) 62 (FIG. 2C). The address in IDBM 62 at which a given input is stored is obtained from IDBM pointer in memory (IDIM) 64. IDBM 62 is divided into separate areas, one for each input priority level of the system. IDIM 64 indicates the address in IDBM 62 at which the next input character for each priority level is to be stored. Each address indicated by IAC 52 has a priority level which is detected by priority level detector (PLD) 66 (FIG. 2B). The detected level is utilized to read out the input address from IDIM 64. The character from CADR 56 is stored in memory 62 at the read out address. The device address in IAC 52 is also stored with the character in memory 62.
In addition to causing the read out of IDIM 64, the priority level indication detected by PLD 66 also causes interrupt flops control (IFC) 68 to set the inter rupt flip-flop (IFi) 70 for the detected priority level. The contents of flip-flops 70 are sent to interrupt register 71 of the CPU through OR gate 73. The next time that the CPU 10 tests interrupt register 71, it will find that one or more of the flip-flops 70 is set. In response to this detection, the CPU generates an internal interrupt and applies an input-output command (IOCJ through register 72 to the IOU. This command is decoded in [QC decoder 74 and causes pointer out decoder (POD) 76 to generate a read out command from both IDIM 64 and IDBM pointer out memory (IDOM) 78. IDOM 78 contains the address in IDBM 62 for each priority level at which the next character to be read out into the CPU from that priority level is stored. The reading out of IDOM thus causes the oldest character in IDBM for the given priority level to be read out into the B (data) register 80 of CPU 10. The address stored with the character is read into the D (address) register 82 of the CPU.
The address read out from IDOM is then incre merited and compared against the address read out from IDIM. If these two addresses are the same, then all characters for the given priority level have been read out from IDBM and the interrupt flip-flop 70 for the priority level is reset. If these addresses do not compare, then the next time the CPU tests interrupt, it will still find the interrupt flop set and the next character for the given priority level will be read out into the B and D registers of the CPU in the manner indicated above.
When the CPU has a character to transmit through one of the lines, it will set the IOU to transmit mode for the given line in a manner to be described later, will store the character to be transmitted in the B register 80 and will store the address to which the character is to be transmitted in the D register 82. The IOU has an output data buffer memory (ODBM) 84 (FIG 2B) which has a character position corresponding to each of the lines addressed by IAC 52. When the position for the address indicated in D register 82 is empty, the IOU will load a message into the appropriate priority position of the IDBM, in a manner to be described later, informing the CPU that the ODBM is available to receive the character in the B memory. The CPU then issues a command to the IOU causing the character to be stored in the ODBM at the address indicated by the D mem ory. The character in the ODBM is then transferred to the CADR (FIG. 2A), a bit of the device shifted out to the interface for the addressed device, and the contents of CADR shifted back into CADM 54 at the appropriate address position. Each subsequent time that the contents of the CADM are read out into CADR, the IOU tests to see if the interface is ready to receive an other bit. When the interface is ready to receive another bit, another bit of the character is shifted out to the interface and the altered contents of CADR reloaded into CADM. In the mean time, the CPU is loading a new character into ODBM 84. When the entire character in CADM has been shifted out, the character now in ODBM 84 is shifted into CADR 56 in the manner previously indicated and the shifting of this character onto the line through the interface begun. This sequence of operation is repeated until an end of message indication is received from the CPU.
It should be noted that while the IOU is transmitting data to one line, it may be receiving data from another line and except for certain instances where the running of IAC 52 (FIG. 2B) is temporarily halted to permit some operation to be performed, the operations with respect to one device in no way interferes with the op erations with respect to another device. The IAC is temporarily halted by a signal on line 238 from OR gate 236 when a) the CPU wants control of the IOU as when an IOC is being generated; b) the CPU is loading the ODBM; and c) the CPU is receiving a character from the IDBM. The hold on the IAC is normally in response to an IOC from the CPU on line 88. It should also be noted that the CPU handles interrupts in accordance with their priority level and that information for the appropriate priority level is provided to the CPU without requiring time-consuming searching or processing operations either in the CPU or IOU.
DETAILED DESCRIPTION In addition to the elements described in the previous section, the IOU also contains a control memory (COM) 90 (FIG. 2B). COM 90 contains a separate [2 bit word for each line addressed by the IAC. FIG. 3 is a table indicating the significance of each bit of a word in the COM. Each time [AC 52 contains the address for a particular line, the control word stored in memory 90 for that line is read out into control memory register (COMR) 92. The contents of this register are detected by COM detectors (COMD) 94 and the output from the detectors 94 are applied through lines 96 to IOU control logic (IOCL) 98. From the control memory word applied to it, and other inputs to be described later, the IOCL determines what, if any functions, are to be performed by the IOU during each time interval that the IAC is addressing a particular line and generates signals to control the various data transfers within the IOU, to alter the control word stored in COMR, or to perform various other functions to be described shortly. In order to simplify the drawings, no attempt will be made to show the details of the IOCL logic. Instead, the functions of this logic will be described in detail, it being understood that the logic for implementing these functions in hardware or software might be easily generated from the following functional description and flow diagrams by one normally skilled in the art. Similarly, gates have not been shown in the various lines inter-connecting the elements, it being understood that IOCL-controlled gates would appear in most of these lines to control the data transfers.
Of the control word bits shown in FIG. 3, bits 3 and 7 are of particular interest at this time. Bit 3 indicates whether the IOU is in transmit or receive mode for the particular line, the IOU being in transmit mode if this bit is set and in received mode if this bit is reset. Bit 7 indicates whether the IOU is in active or passive mode for the particular line during a transmit operation, the IOU being in active mode if this bit is a zero and a pas sive mode if this bit is a one. The state of both ofthese bits is controlled by the CPU. To alter the state of one of these bits, the CPU stores the appropriate i/O command in register 72 and the address for the command in D register 82. Decoder 74 decodes the command and applies a signal through an appropriate line I00 and OR gate 102 to alter the appropriate bit in COMR 92. The contents of COMR 92 are then read back into the address position of COM to cause the desired alteration of bit condition.
From the above and the description to follow it can be seen that, for each line, the IOU may be operating in one of four different modes. In the receive passive or idle mode, the IOU is monitoring the line to determine if data is present, It is thus looking for sync characters or for a transition in the state of the line indicating that data is present. In the receive active mode which the device switches to in a manner to be described later when received data is detected, the IOU knows that there is data present and receives everything that comes in on the line. The received data is presented to the CPU.
In the transmit passive mode all data in the CADR and ODBM will be transmitted to the output channel but the IOU will not issue a request for a new character from the CPU when these memories are empty, In the transmit active mode the I/O channel will issue a request for a new character from the CPU every time the ODBM is empty.
RECEIVE MODE As indicated previously, IOU I2 is capable of trans mitting or receiving information on a synchronous line or channel such as line 18, or an asynchronous line or channel such as line 26 and a plurality of I/O devices may be multiplexed to a single channel such as 3238. As will be seen in the following, the operation of the IOU differs slightly in the transferring of data for the various channels.
RECEIVING DATA FROM A SYNCHRONOUS CHANNEL FIGS. 4A 48 form a functional flow diagram of the manner in which the system operates to receive data from a synchronous channel. Referring now to FIG, 4A, it is seen that for the particular channel. the IOU is in the receive idle mode with all bits of the COM word for the channel, including COM 3, set to zero (step 101). Assume initially, that step 103 indicates the channel being served as containing only a single device. The channel might thus, for example, be the high speed line 18 connected to processor 16. Under these conditions, data is being received at interface 20 with each new bit being loaded into position IOBI of the interface buffer 105 (FIG. 2A) At each synchronous clock of interface 20 a bit stored in IOBI is shifted into position IOB2 of the buffer and flip-flop COMB l of the interface is set (step 104). The condition of COMB l is monitored through IOSC S0 and line 107 by IOCL 98. Each time that [AC 52 is pointing to the particular channel, and it is detected that COMB] for the channel is set, IOCL generates a command causing the bit in 10132 to be transferred through IOSC 50 and shifted into the left most position of CADR 56 (this position being hereinafter referred to as CADR-I When IOB2 is empty, COMB-l is reset on the next synchronous interface clock. The operations shown in block 106 of FIG. 4 are in this manner effected. As indicated previously, the contents of CADR are shifted into the appropriate memory position of CADM at the end of each clock time of IAC 52.
The shifting of bits into CADR 56 is a continuous operation which is repeated each time a new bit is loaded into 1081. A sync code decoder in CADR detectors (CRD) 108 is continuously monitoring the contents of CADR to determine if a sync code is stored therein (step 110). So long as no sync code is detected, the bits continuously shift through CADR 56. When a sync code is detected in CADR 56, CRD 108 applies a signal through line 112 to lOCL 98 to cause the control word stored in register 92 to be altered by setting bit number five (COM to one. lOCL 98 also applies signals through lines 114 to set bits 2-11 of CADR to one and to reset bit 1 of CADR to zero (step 116). The loading of CADR in this way permits the detection of a new character in CADR to be easily effected. Since a new character is shifted into CADR a bit at a time, bit 11 of CADR will remain set to one until a full ten-bit character has been shifted into CADR at which time a zero will be shifted into this position. A full character in the CADR may thus be detected by monitoring bit 11 of CADR for zero. At the end of the lAC clock, the contents of CADR and COMR are loaded into appropriate memory positions of CADM and COM respectively to preserve the settings of these registers until the IAC again indicates the address of a particular channel.
As indicated by step 118 of FIG. 4, bit 11 of CADR is continuously tested in CRD 108 for a zero bit in the bit 11 position. From previous discussions, will be remembered that the detection of this condition means that a new full character is in CADR. This character is then tested to determine if it contains the sync code (step 120). Since sync is established only if two or more successive sync characters are received, if the second character is not a sync character, bit 5 of COM is reset (step 122) and the system returns to step 110 testing for the sync code. If the second character is a sync code, then sync is established. This condition is stored in the system by setting COM 6 to its one state and resetting COM 5 to its zero state. This effectively converts the system from the receive idle to the receive active or receive mode. As may be seen from step 124, lOCL also resets CADR-l to zero and CADR 2-11 to one at this time. The reason for this is to permit the de tection of the next full character in CADR in the manner previously described.
Since steps 104 and 106 are continuously being performed new characters are continuously being shifted into CADR from the selected channel. Each time that the channel address appears in IAC, CADR 11 is tested for zero. When the CADR 11 equals zero condition is detected, CRD also checks to determine if the character is not a snyc character (step 126) (FIG. 48). If the character is not a sync character, then the system branches to step 128 to start loading the character into the system. The first step in this operation is to generate an output on line 130 from PLD 66 indicating the priority level of the channel having the address contained in IAC 52. The signal on line 130 is utilized to address lDlM 64 causing the address in lDBM at which the new character is to be stored to be read out and temporarily stored in pointer-data-in buffer PDIB 132. The contents of buffer 132 are incremented in circuit 134 and restored in the appropriate priority position of memory 64. The address in buffer 132 is also applied through OR gate 136 and line 138 to the address input of lDBM 62 causing the character in CADR 56 which is applied through OR gate and line 140 to be stored in lDBM 62. The lAC address on line 129, indicating the channel for the received character is stored with the character in memory 62. The reason for storing the address with the character is that several channels may have the same priority level and no means is provided in lDBM for distinguishing between these channels.
The priority level on line 130 is also applied to interrupt flop control (IFC) 68 to cause the interrupt flip flop for the indicated priority level to be set. The operations required by step 142 are thus completed. The system then tests to be sure COM 6 is still equal to one (step 143). lf it is, CADR 2-11 are set to one and CADR 1 is set to zero (step 144) thus setting the register for the detection of the next complete character therein. The system then returns to step 126 to cause a new received character to be recognized and loaded into an appropriate position of lDBM.
CPU 10 periodically tests interrupt (step 146). When, during a test interrupt. it is found that one of the lFi flip flops 70 is set, the CPU generates an inputoutput command (IOC) which is decoded in lOC decoder 74 causing a signal to be applied through line 148 to POD 76. POD 76, in response to a signal on line 148, generates an output on a line corresponding to the highest priority flip flop 70 which is set, this signal causing the position in IDIM and IDOM for the indicated priority level to be read out. The address from lDOM is applied directly through OR gate 136 to cause the contents of the address position in lDBM to be read out with the data portion of the contents of this address being stored in B register and the address portion of this word being stored in D register 82 (step 149). The address read out of IDIM is temporarily stored in buffer 132 and is thus ineffective at this time. The output from IDOM is also incremented in circuit 150. The incrcmented address is restored in IDOM and is also applied as one input to compare circuit 152, the other input to this circuit being the output from lDlM (step 154). if necessary, the output from IDIM may be delayed slightly before being applied to compare circuit 152 to compensate for any delay in incrementing circuit 150. If the compared values are not equal, lFi 70 remains set and any additional stored character for this priority level is read out the next time the computer tests interrupt. If the compared values are equal, there are no fur ther characters waiting to be read out at the given priority level, and a signal is applied through line 156 to lFC 68 to cause the flip flop 70 for the particular prion ity level to be reset (step 158). It should be noted that if the incrementing of IDIM or lDOM at any time causes the address pointer to move to an address outside the area assigned to the particular priority level in lDBM 62, this is detected by initial and final address control (IFAC) circuit 159. When this occurs, circuit 159 resets the address indication to the first address in lDBM for the priority level.
The loading of new characters from the synchronous channel into CADR, the transferring of these characters into lDBM, and the final transfer of these characters into the CPU continues in the manner indicated above until, during step 126, when a full character is detected in CADR, the end oftext (ETX) code is found by detectors 108 in this register (step 160). When this occurs, IOCL causes COM 6 for the select channel to be reset, returning the IOU to the receive idle mode for the given channel (step 162). The ETX character is however treated the same as any other character and is processed through steps 128, 142, 146, I49, I54 and 158.
RECEIVE ON MULTIPLE DEVICE SYNCHRONOUS INPUT CHANNEL For the embodiment of the invention shown in FIGS. 2A 2C it is assumed that eight keyboards are tied together to make up an input channel. The portion of interface 34 shown in FIG. 2A appears for each of the eight keyboards. It should be noted that unlike the channel described above on which information is received on a bit by bit basis, the information from the depression of a key on a keyboard is received in parallel.
When scanning the multiple device channel, keyboard scan counter (KBSC) 166 replaces the three least significant bits of IAC 52. Referring now to FIG. 4A, it is seen that a character is loaded into interface 34 by storing its characters in bits 2-Il (assuming bit character) of character buffer register (CRBF) 168 (step 170). The loading of the character into CRBF is under control of a strobe signal synchronized with the addressing of the keyboard by KBSC 166. When a character is loaded into CRBF, data present (DP) flip flop 172 is set, bit (N 2) (bit 12 for the example chosen) in CRBF is set, and bit one in CRBF is reset (step 173). The setting of bit 12 is for the detection of an end of character at CRBF while the resetting of bit one is used to detect that a full character is in CADR (i.e. bit ll equals zero). The character in CRBF 168 is then shifted out a bit at a time into CADR 56 during successive accesses to the channel (step 174). When it is detected that the complete character in CRBF has been read out (CRBF all zeros), DP flop 172 is reset (step 176). At the same time, a full character is detected in CADR, (bit 11 is detected as being equal to zero). When this occurs, the circuit branches to step 128 and proceeds with the succeeding steps to store the character in IDBM and to transfer the character into the CPU. However, since there is no testing for sync when operating with multiple devices, COM 6 is not utilized and steps 143, 160 and 162 are not required.
RECEIVED DATA FROM AN ASYNCHRONOUS CHANNEL The reception of data from an asynchronous channel differs from the reception of data on a synchronous channel in that clocking for the receive operation must be supplied by the IOU. FIG. 5 is a functional flow diagram of the operations performed in receiving data from an asynchronous line. Referring to FIG. 5 it is seen that, as with the synchronous channel, the IOU is initially in the receive idle mode for the channel with all bits of its control word, including bit 3 reset to zero. When the communications line goes low, indicating that data is present (step 182), and [AC 52 gets to the address of the channel, the value of the asynchronous clock (AC) 184 associated with the channel is loaded into COM 8 and COM 9 is set to one (step 186). There is an asynchronous clock for each different speed channel serviced by the IOU with the frequency of the asynchronous clock being four times higher than the asyn chronous frequency of the channel. There are thus eight transitions in the asynchronous clock for each hit time of the channel. When the line goes low, this may be caused by the space bit at the beginning of a character, or it may be caused by a noise signal. The first step in the operation is to determine if the change is in fact the beginning of a character.
To accomplish this, it is assumed that if the space pulse lasts for at least halfa clock time then it is a true space pulse. The circuit thus counts five asynchronous clock transitions and tests to determine if the line is still low. To do this, each time IAC addresses the channel. the value in COM 8 is compared with the setting of the appropriate AC clock 184 (step 188). When these compared values are not equal, this means that an ACi clock transition has occurred. When this happens. the new value of ACi is loaded into COM 8 by IOCL 98 and the count in midpoint detector counter (MBD). which is formed by bits 9ll of COM for the given channel, is incremented (step 190). After each incrementing the count in MBD is tested. When this test finds that MBD is equal 5 (step 192) and at the same time it is found that COM 12 is not equal one (step 194) the circuit tests to determine if the input channel is still low (step 195). If the line is not still low this means that the initial input was not a true space pulse and that a character is not in fact being applied to the line. Under these conditions MBD is reset to zero (step 196) and the system returns to step 182 looking for a space bit.
If the line is found to be low during step 195 this means that a character is now being applied to the line. This is indicated by setting COM 12 to l for the given channel. For reasons which have been indicated previously, CADR l is set to zero at this time and CADR 2-1] are set to one (step 198). The contents of (ADR are then loaded into CADM.
The circuit then returns to step 188 incrementing the count in the MBD counter each time a transition of the asynchronous clock is detected. MBD counts to seven and then resets to one. Thus, the next time that the count in MBD is equal to five, the midpoint of the first data bit of the input should be on the channel. Thus, when during step 194, COM I2 is tested and found equal to one, the system branches to step 200. From FIG. 5, it is seen that this involves the reading out of CADM into CADR and the shifting of the new hit from IOBZ 202 of the asynchronous channel interface 28 into CADR 56. After the loading of the new bit into CADR, CADR ll (assuming 10-bit characters) is tested for Zero (step 204). If this test indicates that the bit is not zero, the contents of CADR arc reloaded into CADM (step 206) and the system returns to step 188 to find the midpoint of the next received bit and load it into the system.
When the last bit of a character has been loaded into CADR, the test of step 204 yields a positive result causing the system to branch to step 208. During step 208 the input address in IDIM for the priority level indicated by PLD is accessed and during step 210 this address is utilized in a manner previously indicated to load the received character in CADR and the channel address in IAC 52 into IDBM 62. Also during step 210. the appropriate interrupt flip flop 70 is set and the ad dress for the given priority level in IDIM incremented both in manners previously described. The circuit is then prepared for the receipt of a new character by restoring it to the receive idle mode. This is accomplished by resetting COM 9-12 to zero. In order to prevent a spurious character from being loaded into lDBM all ones are set into CADR (step 212).
The character stored in IDBM is read out into the CPU in a manner identical to that previously described in connection with the reception of synchronous data. This involves the performance of step 146, 149, 154 and 158 shown in FIG. 4. The operations involved in performing these steps will not be repeated at this point.
TRANSMIT The transmit operation is substantially identical for both synchronous and asynchronous lines and these operations will thus both be treated in the same section. The system is shifted into transmit mode by an lOC issued by the CPU. This lOC is decoded in decoder 74 and applied to lOCL 78 to cause COM 4 at the address indicated by D register 82 to be set equal to one (step 220). If the system is to be operating in transmit passive rather than transmit active mode, COM 7 is also set equal to one at this time.
The next time that the channel address appears in lAC 52, the marked COM 4 bit is detected (step 222). The RTS flip flop 224 or 226 in the channel interface is set (step 228). Since there is generally a delay of about twenty microseconds, from the time that the RTS flip flop is set until the time that data can actually be transmitted, a timer may be provided in the IOU which delays further operations for approximately this time duration. At the end of this time duration, when [AC again indicates the address of the particular channel, COM 3 is set by the IOCL indicating that the [OU is in transmit mode for the given channel (step 230).
The circuit then tests to see if COM 2 is reset (step 232). From P10. 3 it is seen that COM 2 being set indicates that ODBM 84 does not contain data to be transmitted and is thus in condition to receive a character from the CPU. Under these conditions, the lOCL generates a signal on line 234 which is applied through OR gate 236 and line 238 to cause the running of the lAC to be temporarily halted (step 240). The [DIM is then read out under control of the PLD in the manner previously indicated (step 242), and a request-for-character signal is generated by the lOCL and applied through line 244 OR gate 60 and line 140 to be stored in IDBM 62 (step 246). As before, the lAC address is stored with this signal in the lDBM. The priority flip flop 70 corresponding to the indicated channel is set and the address in lDlM incremented both in the manner previously indicated (step 250) and the hold on the IAC release (step 252).
When the CPU tests interrupts (step 254) and finds that the device in question has a message to send (it should be noted that several other interrupts may have been processed in the interim) it causes the contents of IDBM at the address determined by lDOM to be read out into the B and D registers, 80 and 82 respectively, in a manner previously described (step 256). Likewise, the [DOM is incremented, compared against the lDlM, (step 258) and the lFi reset if they are equal (step 260) all in the manner previously described.
The effect of the above described sequence of operations is to inform the CPU that the ODBM is available to receive a character to be transmitted to the channel which the CPU has indicated it wishes to transmit to. Performing the operation in this manner eliminates the necessity of the CPU continuously monitoring the state of the ODBM.
When the CPU receives the message, it loads the character to be transmitted into B register and the channel address for the character into D register 82. The CPU then issues an I/O command on line 73 which is decoded by decoder 74 to cause the character stored in B register 80 to be loaded into ODBM 84 at the address given by the D register. During the loading of ODBM (step 262) the issued [0C is effective to cause a hold signal to the IAC to appear on line 238. This hold is released when the loading of the ODBM is completed.
When the ODBM is loaded, COM 2 for the selected device is set and COM 4 reset (step 264). These operations would normally be performed in response to an lOC from the CPU but may also be performed under control of IOCL 98. These operations indicate to the system that the ODBM has a character to be transmitted.
The next step in the operation is to determine if CADR for the given device also contains a character to be transmitted. If CADR does not contain a character to be transmitted, then the character in ODBM is transferred to CADR for transmission. The above operations are accomplished by testing COM 1 to determine if it is reset (step 266). If this bit is reset, then, the next time IAC addresses the given channel, the contents of ODBM 84 rather than the contents of CADM 54 are read out into CADR 56 (step 268).
At this point the operation varies depending on whether it is a synchronous or an asynchronous channel to which transmission is being sent. Assume initially that transmission is to a synchronous channel. Under this condition the system branches from step 270 to step 272. During this step bit 11 of CADR is set to one. As will be seen later, this is utilized to detect that the entire character has been transmitted. In addition, COM 1 for the given channel is set, indicating that CADM now contains a character to be transmitted and COM 2 is reset indicating that the ODBM does not contain data to be transmitted. Finally COM 4 is set (step 274). At this point in the operation, if the unit is operating in the transmit active mode for the channel (step 276), the unit returns to step 232 to start the loading of a new character to be transmitted into ODBM 84. If bit 7 is marked, indicating that the unit is in the transmit passive mode, this request for a new character is not generated.
At the same time that this request for a new character is being made, and regardless of whether the system is in the transmit active or the transmit passive mode, the unit branches to step 278 during which CONB l in the interface is tested to determine if it is equal to zero. If CONB 1 equals zero, then 1082 is empty and the inter face is available to receive a character. if CONB 1 equals 1, there is a bit in the buffer and a new bit may therefore not be transferred into it. Under these conditions, as may be seen from FIG. 6B, the loading steps to now be described are bypassed and the contents of CADR loaded into CADM (step 286).
If CONB l is equal to zero, the unit branches to step 280 during which CADR is shifted left once, loading its left-most bit (CADR 1) into IOB2. During step 282,
CONBl is set equal to 1 indicating that there is now a bit in its buffer. At some later time, this may be several lAC clock cycles later, the contents of [0132 are shifted into lOBl from which they are applied to the channel and CONBl is set to zero (step 284).
In the mean time, the character in CADR is loaded into CADM at the addressed memory position (step 286) and bit COM 1 is set to indicate that CADM now contains data to be transmitted (step 288).
The next time that lAC 52 addresses the channel, the word to be transmitted or portion thereof, now stored in CADM is reloaded into CADR (step 290) and the unit returns to step 278 to determine if the interface is ready to receive another bit. Steps 278-290 are cyclically repeated as many times as are necessary in order to read out the character to be transmitted to the interface. lt is noted that after each performance of step 282, bits 2-ll of CADR are tested to determine if they are all zero (step 292). Since CADR 11 was marked during step 272, bits CADR 2-ll cannot be equal to zero until the entire character has been shifted out of CADR. Thus, step 292 yields a positive result only when the character to be transmitted has been completely transferred to interface 20 and CADM is ready to receive a new character. Under these conditions, the IOCL resets COM 1 and loads all ones into CADR to prevent a spurious end-of-character indication from being generated (step 294). It should be noted that while steps 286 and 290 continue to be performed each time IAC addresses the channel, the performance of step 288 is suppressed.
With COM I reset, the system returns to step 266, assuming that the system is in the active mode, to read out the character which is now in ODBM into CADR and to cause this character to be transferred from CADR and CADM into interface 20.
Transmission of characters in the manner indicated above continues until, after the loading of a character into the [DC the CPU makes an end-of-transmission determination (step 296). When this happens, the CPU issues an lOC which is decoded by decoder 74 to cause COM 3 to be reset (step 298) causing the system to return to the receive mode.
If, during step 270, it is determined that the channel to which transmission is being made is an asynchronous rather than a synchronous channel, the unit branches to step 300. During step 300 COM 1 is set to one, COM 2 is reset to zero, the lOB2 buffer 202 in interface 28 is reset to zero, COM 12 is set to l, and the count is started in midpoint detector (MPD) counter. This later step is accomplished by setting the value of asynchronous clock 184 into bit 8 and by setting bit 9 equals l. Each time that the value of bit 8 and the asynchronous clock are not equal, bit 8 is set to the value of the asynchronous clock and the count in MBD (COM 9-COM II) is incremented.
At the same time that step 300 is being performed, the system tests (step 276) to determine if it is in the transmit active mode and, if the system is in the transmit active mode for the given channel, returns to step 232 to load a new character into ODBM in the manner previously indicated.
The count in MBD is incremented in the manner indicated above and the value of the count monitored. When this count equals zero (step 302), CADR is shifted left with CADR 1 being loaded into [B2 (step 304). The system then returns to step 302 incrementing the MBD and testing its value for zero. This sequence of operations is repeated until all bits of the character in CADM are loaded into I082 and the stop bit is loaded into 1082 as well. When the stop bit is in 1082 and MBD equals zero (step 306), MED is set equal to four (step 308). One half clock cycle later when MBD is again equal to zero (step 310), COM 2 and COM 12 are both reset to zero (step 312). The unit then branches either to step 266 to cause a new character from ODBM to be loaded into CADR for transmission to the channel or to step 296 to end the transmission.
ALTERNATIVE EMBODIMENT in the embodiment of the invention shown in FIGS. 2A-2C, the priority assignments for the various channels is fixed and may be altered only by rewiring the IOU. FIG. 7 shows an alternative embodiment of the invention in which the CPU has the capacity to assign or change the priority levels for the various channels thus permitting greater flexibility in the operation of the system. This is accomplished by connecting the out put lines from each of the flip flops to POD 76 through a weight scale control circuit (WSC) 320. This circuit is effective to change the weight assigned to each of the flops 70 in accordance with the word stored in priority control register (PCR) 322. PCR 322 is loaded by an [DC from the CPU. Thus, if 64 different priority sequences were possible, PCR 322 would be an eight bit register. The code contained in the PCR is decoded in WSC 320 and utilized to gate the lFi output which is to be passed to POD 76.
Another possible way in which some flexibility may be provided over channel priority assignments is to provide one or more unused priority levels. In the event that the CPU needs an immediate response from an l/O device or other channel element, this level is assigned to the channel and given the highest priority. Where immediate responses are desired, this method has the advantage that all outstanding interrupts for channels of the same priority do not have to be served before the desired access can be granted.
It is apparent that means equivalent to those described above might be utilized for performing some of the functions such as endof-character detection and the like and that some of the functions indicated as being performed by hardware may be performed by software and visa versa. Thus, while the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be under stood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the in vention.
What is claimed is:
l. A unit for controlling the transfer of information between a plurality of data bearing lines, which lines are scanned in a predetermined sequence, and a central processing unit (CPU), said information having at least two different priority levels, said unit comprising:
means for indicating the data bearing line being scanned at any given time;
means for detecting the priority level of each item of information applied to said unit;
means responsive to said detecting means for informing the CPU of the availability of information at the detected priority level;
an addressable memory, said memory having an area allocated to each of said priority levels;
input means for indicating the address in said memory at which the next item of information at each of said priority levels is to be stored;
means responsive to said detecting and input indicating means for storing each applied item of information in said memory;
output means for indicating the address in said memory at which is stored the next item of information at each of said priority levels to be transferred to said CPU; and
means responsive at least in part to said informing means and said output means for transferring an item of information from said memory to said CPU.
2. A unit of the type described in claim 1 wherein said informing means includes at least one element for each priority level;
wherein the priority represented by each element of said informing means may be varied; and
including means for indicating the priority level represented by each element of said informing means; and
means responsive to the last mentioned indicating means for controlling the address in the output means utilized for each transfer of information from said memory to said CPU.
3. A unit of the type described in claim 2 including means for permitting said controlling means to be controlled from the CPU.
4. A unit of the type described in claim 1 wherein said means for storing information in said memory stores information in said memory a character at a time; and
including means for assembling bits received on said data bearing lines into characters.
5. A unit of the type described in claim 4 wherein said character assembling means includes a memory having a storage position for each of said lines, a register in which each received bit is stored, and a means operative each time said indicating means indicates a given line for transferring a partially assembled character from the position for the line in said memory to said register and for restoring the contents of said register to the position in said memory when said indicating means is ready to pass on to the next line.
6. A unit of the type described in claim 5 including means for detecting when a full character has been assembled in said register; and
wherein said means for storing information in said memory includes means operative in response to said full-character detecting means for transferring the contents of said register into said memory.
7. A unit of the type described in claim 6 wherein at least one of said data bearing lines is a synchronous line; and
including means for detecting a sync code in said register; and
means responsive to said sync code detecting means for activating said full character detection means.
8. A unit of the type described in claim 4 wherein at least one of said lines is an asynchronous line; and
including means for generating a clock which is related to the clock rate of said asynchronous line;
means operative when a pre-determined change oc curs in the condition of said asynchronous line for determining if a character is present on the line; and
means responsive to said determining means for initiating the operation of said means for assembling bits into characters.
9. A unit of the type described in claim 5 including output buffer memory means having at least one posi tion for each of said lines;
means responsive to an instruction from said central processing unit for loading a character to be transmitted on a given line into a position corresponding to the line in said output buffer memory means; and
wherein said means for assembling bits into characters includes character disassembly means for transmitting said character on said given line a bit at a time.
10. A unit of the type described in claim 9 wherein said character disassembly means includes a memory having a character position for each of said lines, a register, means for transferring a character to be transmitted from said output buffer memory means to the corresponding position in said disassembly means memory, means operative each time said line indicating means indicates the line for transferring the character from the disassembly means memory to the disassem bly means register, and means operative when the character is in said disassembly means register and said line is available to receive a bit for transferring a bit from the disassembly means register to said line.
11. A unit of the type described in claim 1 including an interface device for at least one of said lines, said interface device having a means for assembling a charac ter; and
means operative when a character has been assembled in said interface device for transferring the character to said unit.
12. A unit of the type described in claim 11 wherein there may be a plurality of lines serviced by said interface device; and
wherein said data bearing line indicating means includes means for indicating the particular one of said plurality oflines serviced by said interface device.
13. A unit of the type described in claim 1 wherein said information storing means includes means for storing an indication of the data bearing line being scanned with said information.
14. A unit of the type described in claim 4 including memory-means for storing a control word for each of said lines;
register means for storing the control word for a line each time the line is scanned; and
means responsive to the control word stored in said register means for controlling the character assem bly and other operations of said unit.
15. A unit of the type described in claim l4 including means for altering the control word in said register means in response to controlling means or said CPU said unit.
16. An interface unit for a CPU, said unit comprising:
means for scanning a plurality of lines; means for indicating the line being scanned at any given time;
second means responsive to said priority level indicating means for indicating to the CPU that the unit has a character at the indicated priority level, the CPU being adapted to generate a request for a character; and
means responsive to a request for a character from the CPU for transferring to the CPU a character from the highest priority area of said memory having a character to transmit.
17. A unit of the type described in claim 16 including means operative when a character is transferred to said CPU for determining if there are any additional charac ters to be transmitted from said highest priority area of memory; and
means responsive to a determination that there are no further characters to be transmitted in said highest priority area for resetting the priority level indicating means for the priority level from which characters were transmitted. 18. A unit of the type described in claim 16 wherein said memory is an addressable memory;
and wherein said means for storing the character in said memory includes means for indicating the address in said memory, for each of said priority levels, at which the next character is to be stored. 19. A unit of the type described in claim 16 wherein said memory is an addressable memory;
and wherein said means for transferring a character to the CPU includes means for indicating, for each priority level, the address from which the next character is to be transferred.
|Cited Patent
|Filing date
|Publication date
|Jun 1, 1964
|Jul 11, 1967
|Sperry Rand Corp
|Data communication system with matrix selection of line terminals
|Oct 20, 1965
|Jul 30, 1968
|Gen Electric
|Priority selector
|Dec 29, 1965
|Aug 6, 1968
|Polling system
|Sep 10, 1965
|Aug 27, 1968
|Variable priority access system
|May 2, 1966
|Jun 10, 1969
|Honeywell Inc
|Electronic multiprocessing apparatus including common queueing technique
|Aug 18, 1966
|Jul 1, 1969
|Program suspension system
|Mar 1, 1967
|Jul 15, 1969
|Gen Dynamics Corp
|Data terminal with priority allocation for input-output devices
|Aug 24, 1967
|Oct 13, 1970
|Burroughs Corp
|Service request priority resolver and encoder
|Jun 3, 1969
|Jan 5, 1971
|Gen Electric
|Selector for the dynamic assignment of priority on a periodic basis
|Apr 22, 1969
|Aug 10, 1971
|Comcet Inc
|Priority tabling and processing of interrupts
|Apr 29, 1970
|May 23, 1972
|Honeywell Inf Systems
|Data processing system with program interrupt priority apparatus utilizing working store for multiplexing interrupt requests
|Citing Patent
|Filing date
|Publication date
|Aug 29, 1974
|Jul 20, 1976
|Honeywell Information Systems, Inc.
|High speed peripheral system interface
|Mar 26, 1975
|Dec 28, 1976
|Honeywell Information Systems, Inc.
|Steering code generating apparatus for use in an input/output processing system
|Oct 28, 1975
|Nov 29, 1977
|Compagnie Internationale Pour L'informatique Cii-Honeywell Bull
|Data input and output controller
|Apr 7, 1975
|Mar 14, 1978
|Compagnie Honeywell Bull
|Apparatus for synchronizing tasks on peripheral devices
|Aug 17, 1976
|Apr 29, 1980
|Cincinnati Milacron Inc.
|Asynchronous bidirectional direct serial interface linking a programmable machine function controller and a numerical control
|Dec 8, 1978
|Jan 27, 1981
|Motorola, Inc.
|Re-linked portable data terminal controller system
|Apr 18, 1980
|Aug 17, 1982
|Cselt-Centro Studi E Laboratori Telecomunicazioni S.P.A.
|Message-interchange circuitry for microprocessors linked by synchronous communication network
|Nov 9, 1978
|Jan 18, 1983
|Compagnie Honeywell Bull
|Apparatus and method for providing synchronization between processes and events occurring at different times in a data processing system
|Dec 4, 1978
|Jul 19, 1983
|Compagnie Honeywell Bull
|Apparatus and method for transferring information units between processes in a multiprocessing system
|Sep 29, 1980
|Sep 20, 1983
|Honeywell Information Systems Inc.
|Communication multiplexer having an apparatus for establishing a single line priority
|Mar 6, 1981
|Oct 18, 1983
|International Business Machines Corporation
|Synchronizing buffered peripheral subsystems to host operations
|Sep 15, 1982
|Oct 25, 1983
|Braddock Iii Walter D
|Automated stock exchange
|Feb 24, 1982
|Dec 3, 1985
|Caprio A Ronald
|Interchangeable interface circuitry arrangements for use with a data processing system
|Sep 19, 1983
|Sep 30, 1986
|International Business Machines Corporation
|Memory controller with synchronous or asynchronous interface
|Oct 14, 1982
|Dec 13, 1988
|Italtel-Societa Italiana Telecomunicazioni S.P.A.
|Control unit of input-output interface circuits in an electronic processor
|Nov 3, 1983
|Feb 20, 1990
|World Energy Exchange Corporation
|Automated futures trading exchange
|Sep 27, 2003
|Aug 1, 2006
|Klug John R
|Method and apparatus for identifying, managing, and controlling communications
|Oct 30, 2002
|Jul 6, 2010
|Nasdaq Liffe Markets, Llc
|Liquidity engine for futures trading exchange
|Oct 30, 2002
|May 6, 2004
|Nasdaq Liffe Markets, Llc
|Liquidity Engine for futures trading exchange
|Nov 22, 2002
|May 27, 2004
|E-Comm Connect, Llc
|Method and system for insuring users of electronic trading systems or exchanges and traditional established commodity exchanges against weather-related risks and hazards
|Sep 27, 2003
|Sep 9, 2004
|Klug John R.
|Method and apparatus for identifying, managing, and controlling communications
|Sep 27, 2003
|Jan 6, 2005
|Klug John R.
|Method and apparatus for identifying, managing, and controlling communications
|Jun 19, 2006
|Oct 5, 2006
|Klug John R
|Method and apparatus for identifying, managing, and controlling communications
|Jun 9, 2009
|Oct 1, 2009
|Klug John R
|Method and Apparatus for Identifying, Managing, and Controlling Communications
|Sep 10, 1984
|Apr 3, 1985
|International Business Machines Corporation
|Interface circuit and method for connecting a memory controller with a synchronous or an asynchronous bus system
|Sep 10, 1984
|Mar 2, 1988
|International Business Machines Corporation
|Interface circuit and method for connecting a memory controller with a synchronous or an asynchronous bus system
|Jun 26, 1987
|Jan 7, 1988
|Bull HN Information Systems Inc.
|Multiprocessor interrupt level change synchronization apparatus
|Jun 26, 1987
|Jul 20, 1988
|Honeywell Bull Inc.
|Multiprocessor level change synchronization apparatus
|Dec 1, 1982
|Jun 23, 1983
|Western Electric Co
|Interface processor unit
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Jun 15, 1983
Owner name: ALLIED CORPORATION COLUMBIA ROAD AND PARK AVENUE,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:BUNKER RAMO CORPORATION A CORP. OF DE;REEL/FRAME:004149/0365
Effective date: 19820922


text:
|You are in: Europe
Friday, 8 October, 1999, 14:17 GMT 15:17 UK
French trains: Safer but costly
By Nick Wood in Paris
In France, rail experts, the state owned railway, and the press are all asking the same question: Could a disaster on the scale of Paddington ever take place here?
The answer is a resounding no.
Fourteen years ago, France suffered a series of rail crashes that prompted it to take drastic measures. As a result it now has one of the safest railway networks in Europe.
The reaction of the government was prompt. Within a year, a new automatic signalling system was being tested.
Speed control
Called KVB, or "speed control by beacon", it brings a train to a dead halt if it passes a red signal, or if it thought to be travelling too fast.
In the UK, systems exist to warn drivers they have passed a red light. But it is possible - as the Clapham, and Southall disasters have shown - for the trains to ignore these warnings and carry on their journey.
With KVB, a series of beacons laid between the tracks relay messages to an onboard computer. An alarm sounds in the driver's cabin prompting them to slow the train down.
If they fail to do so, the train is brought automatically to a halt.
The impact of the system on drivers has been very noticeable.
Passing red signals
By contrast in Britain, some 643 trains passed red signals last year.
KVB covers three-quarters of the French rail network at the cost so far of £500m. The programme is expected to be complete by 2005.
Britain hopes to have introduced its own Train Protection and Warning System by then.
At just £150m, it is very much KVB's poorer cousin. It does not control overall speed and cannot when a train is travelling faster than 70mph.
Since the introduction of the new system, signal-related accidents have fallen drastically.
Only one fatal crash has occurred this decade, in an area where the new warning programme had yet to be introduced.
Not surprised
While shocked, rail experts in France have not that been taken back by Paddington.
"When I heard about Paddington I was not surprised," says Jean Paul Masse.
"The way railways work in Britain is completely different in France, where the state is far more ready to invest."
But it has cost a lot to make the SNCF one of the most advanced railways in the world.
It has seen debts of 200bn francs (£20bn) and an annual deficit of 15bn francs (£1.5bn).
Japan and Germany's equally impressive rail networks have even greater financial problems.
"You have a choice", according to Mr Masse.
"You can chose a railway with a high debt, but a very good railway - safe and very modern. The other choice is to have an unsafe railway, but with no debt behind it."
State investment has not eliminated all of France's safety problems though.
Two years ago, 13 people were killed when a lorry ran in front of an oncoming passenger train in the Dordogne.
It should also be noted that some 40% of French trains are still pulled by diesel engines. It was the explosion of diesel fuel that added to such a high death toll at Paddington.
Top Europe stories now:
Links to more Europe stories are at the foot of the page.
|E-mail this story to a friend
Links to more Europe stories
To BBC Sport>> | To BBC Weather>> | To BBC World Service>>
© MMIII | News Sources | Privacy


text:
Just as I predicted, the iZombie TP Gosh! Exclusive Bookplate Edition has arrived. I'm like some sort of Criswell but accurate and with access to future shipping lists, which if we're being honest is less fun but whatever. If you've already ordered a copy (that's the one signed by Chris Roberson, Mike Allred and Laura Allred that you can only get here at Gosh!) you'll be hearing from me very shortly.
Mike Allred also turns up in this week's Yo Gabba Gabba! Comic Book Time HC along with Evan Dorkin (Beasts of Burden), Sarah Dyer (Batman Beyond), J. Torres (Teen Titans Go!), J. Bone (Batman: The Brave and the Bold) and Jamie S. Rich. I have still failed to see a single episode of this TV show, but maybe you have and maybe you'll probably like this too.
From Fantagraphics you can get the latest instalment in their acclaimed comics anthology Mome, now in its sixth (!) year. There's stuff from Sara Edward-Corbett, Steven Weissman (Chewing Gum in Church), Sergio Ponchione (Grotesque), Nate Neal, Dash Shaw (Bottomless Bellybutton), Jon Adams (responsible for this sort of thing), Tom Kaczynski, T. Edward Bak, Derek Van Gieson, Kurt Wolfgang, Lilli Carré (The Lagoon), Nicolas Mahler (Van Helsing's Night Off) and Josh Simmons, whose biography goes "Simmons draws comics about happy bunnies, cirkus folks, and violent sex. He is a nice young man." Preview as per.
Fantagraphics are still enthusiastically plowing on with their plan to collect every Krazy Kat Sunday page ever, which is about as ambitious a plan as they come. A Kind, Benevolent and Amiable Brick is the penultimate volume of the series, collecting over 150 pieces published between 1919 and 1921. As usual, they're housed in a handsome package designed by the esteemed Mr Chris Ware so they'll match the others on your shelf, or near enough, providing he isn't pulling a wacky Acme Novelty Library design on us. PDF preview at Fantagraphics.
Since I've already mentioned a classic strip I could theoretically segue seamlessly into another one if I could come up with a linking sentence. Having failed that, here we go: I've been all over Popeye the last few days ever since I saw this picture of E.C. Segar near the front of the latest collection. I mean, just look at this guy's hair:
In the LA Times you can get a glimmer of an alternative reality in which the pipe-smoking sailor man never existed. Imagine that.
Brand new stuff this week includes the likes of Downsized, billed as a Big Chill for the new millennium. Indie creator Matt Howarth normally tells fairly oddball tales but was inspired by a real life event to do this book in which a 50th wedding anniversary gives old friends a reason to reunite and take stock of their lives. He's inteviewed over at Comicbook Resources and Adhouse Books have a PDF preview. Incidentally, as it's from AdHouse you should grab a copy now if you fancy it. They're notorious for letting stuff fall out of print.
From Oni Press (home of Scott Pilgrim) comes Possessions Volume 2: Ghost Table, giving you the next chunk of story about Gurgazon the Unclean, a demon who looks like a five-year-old girl and is trapped in a house for captured spirits. The previous volume was coloured a queasy Exorcist-green, which Fawkes was keen to keep in further books, but judging from this preview it looks like someone's had a quiet word, or he's decided against it.
Tony Lee and Sam Hart give you Excalibur: The Legend of King Arthur, the next in their Heroes & Heroines series after Outlaw: The Legend of Robin Hood which went a treat with the American Library Association and turned up on several Best Of 2010 lists. It's for ages ten and up, so if you're trying to teach someone about Arthurian legend and Disney's The Sword in the Stone just ain't cutting it, this might be more help. No preview on this one so you'll just have to wait and see.
Neil Gaiman, who also counts librarians among his many fans, sees his children's book Blueberry Girl released in softcover this week. I wrote about it on the Gosh! Blog back when it debuted in hardcover.
A couple of movie-themed books deserve a mention: The imminent release of the Cowboys & Aliens film starring Harrison Ford means that the 2006 graphic novel about an alien invasion in the Wild West is getting a re-release in hardcover. Then there's Your Highness TP, which is the prequel to the upcoming film of the same name but with an added exclamation point, written by Danny McBride (him off Eastbound & Down) and Jeff Fradley (The Foot Fist Way) and illustrated by the amazing Sean Phillips (Incognito). Dark Horse have a preview.
Phillips' frequent collaborator Ed Brubaker (Criminal) launches the good ship Fear Itself with his prologue one-shot The Book of the Skull, illustrated by Scot Eaton. It stars Steve Rogers and Namor, and sets the scene for Matt Fraction's seven-issue miniseries, set to land next month. It's the next big event in the Marvel Universe and will no doubt spill over into regular titles Civil War-style, so there'll be a checklist kicking about somewhere soon. Preview over at Comicbook Resources. Incidentally, we've still not received the Marvel Previews we were supposed to get a couple of weeks ago but you can see a full online list of them over at CbR in the meantime.
Steve Rogers and Namor also pop up in Uncanny X-Men Annual #3, written by James Asmus (X-Men: Manifest Destiny) and illustrated by Nick Bradshaw (X-Men: Second Coming). It's the first part of Asmus' Escape From the Negative Zone! story, which continues in Namor: The First Mutant Annual #1 and Steve Rogers: Super-Soldier Annual #1 next month. Preview at Newsarama.
Somewhere next to that in the X-books you'll find Deadpool: Pulp HC which is the whole four-issue series in one book. Written by Adam Glass and Mike Benson, you'll probably want it mostly for the art by Gosh! Favourite Laurence Campbell. I linked to a bunch of interviews and a preview when first issue landed in September last year.
Marvel's flooding the shelves with jumping-on points of late with their Point One line but you can include this issue too: Avengers: Children's Crusade: Young Avengers One-Shot by regular Young Avengers writer Allan Heinberg. It's is a stand-alone tale that introduces you to an all-new team of Avengers, illustrated by the legendary Alan Davis (Captain Britain). While trying to find an interview with Heinberg about the book I found this recent one instead, in which he talks about LGBT characters in comics and telly and is far more interesting.
Much like last week's return of CrossGen's Sigil, Mark Waid is writing a "soft reboot" of his old series Ruse about Simon Archard, master Victorian detective. "This Ruse series is geared towards new readers–but certainly, you can read these as "continuing adventures" if you're so inclined. All you have to do is know that here, Partington is firmly set in England, not on some alien world called Arcadia." It's a four-parter illustrated by Mirco Pierfederici (Tron: Original Movie Adaptation), previewed here and talked about here.
Non-Marvel titles include DC Comics Presents Batman: Irresistible, reprinting a three-part tale from 2003's Batman: Legends of the Dark Knight. Written by Tom Peyer (most recently of Tek Janson, the Stephen Colbert comic), with art by Tony Harris (Ex Machina) and Wade Von Grawbadger (Starman), it's about a guy called Frank Sharp, ugliest dude around, who by some Derren Brown magic manages to convince people to do whatever he wants them to simply by shaking their hands. As with all of the DC Comics Presents titles it has never been collected before so chances are you've never seen it.
Also from DC is a new/reboot ongoing series written by its original creator John Rozum and illustrated by Frazer Irving (Batman & Robin): Xombi. In a short, explanatory essay over at DC's The Source, Rozum writes, "If you're thinking rotting corpses shambling around looking for living bodies to dine on then you'd be wrong, though it's possible those sorts of zombies will show up at some point." He gives you a run down on the history of the title and the characters so it's worth a read.
That's it, book-wise, but if you're still after more stuff and you're up North why not head over to the Leeds Alternative Comic Fair on Saturday? The last one was such a success they're doing it all over again. Everything you need to know is at their blog.
-- Hayley
Tuesday, March 15, 2011
The Gosh! Authority 15/03/11
Just as I predicted, the iZombie TP Gosh! Exclusive Bookplate Edition has arrived. I'm like some sort of Criswell but accurate and with access to future shipping lists, which if we're being honest is less fun but whatever. If you've already ordered a copy (that's the one signed by Chris Roberson, Mike Allred and Laura Allred that you can only get here at Gosh!) you'll be hearing from me very shortly.


text:
89-Year-Old Auschwitz Guard Arrested
Johann Breyer, 89, is now the oldest person ever accused of ties to the Nazi regime by the U.S. after being arrested Tuesday at his Philadelphia home. Breyer is accused of being an SS guard at the age of 17 at Auschwitz and Buchenwald, where hundreds of thousands of Jews were slaughtered. Breyer emigrated to the U.S. in 1952, but Germany is asking that he be extradited to face 158 counts of aiding and abetting Nazis. Breyer claims his service was "involuntary." He was first charged in 1992, but was allowed to stay in the U.S. under claims he was a U.S. citizen, as his mother was born in the U.S.


text:
Sale of Astros could be approved next week
Sale of Astros could be approved next week
"I definitely think it can get done by then," he said.
McLane announced in May that he had reached a deal to sell the team to Crane's group. The vote to approve the sale was on the agenda at the owners' meetings earlier this month, but Major League Baseball released a statement two weeks ago saying that it had postponed the vote and needed more time to complete its homework on the $680 million transaction.
Astros officials say that they haven't been informed that Crane's bid is in trouble. And McLane maintained on Tuesday that Major League Baseball's dealings with the Dodgers -- who are in bankruptcy -- and last week's hurricane that affected the East Coast have pushed the vote on the Astros sale further to the back burner.
"It's just gotten more complicated at the Commissioner's Office," he said. "Hopefully they're going to get back on it this week."
McLane said that the complaints filed against one of Crane's companies by the Equal Employment Opportunity Commission in 1997 aren't an issue, and he didn't hesitate when asked if there was any reason to believe that the deal wouldn't be approved by the other owners.
"I think it will sail right through," he said.


text:
A MAN who slept through a house fire had to be lifted to safety after a pan set alight at his Chorley home.
Fire crews were called to the Guernsey Avenue flat in Buckshaw Village at around 5.40am on Sunday after neighbours raised the alarm.
Bamber Bridge fire station watch manager Steve Boyne said: "The man had put a pan on the hob and fell asleep.
"The pan developed into a small fire which produced a huge amount of smoke in his flat. Neighbours were alerted to the fire by the smoke detectors, but the 30-year-old male slept through it.
"Firefighters forced entry into his flat and rescued him from the smoke-logged flat by grabbing him and carrying him out.
"He was still asleep and unaware of the fire until he was taken outside into the fresh air. He was attended to by the ambulance service but declined hospital treatment.
"The smoke detectors did their job and alerted people."


text:
Just to say hello to all the Members of Wiihacks!
Ive paid myself a Wii has a chrismas gift and i came to see what king of possibility it can give me, and also what can i bring to the community.
Im brand new to all of this ( wii modding and all...) , but im here to learn!
have a nice holiday y'all!
Rays now in Québec


text:
Food Inspection Authority
Roughly 18,000 Viennese businesses have to follow the Food Law provisions. The staff of the Municipal Department 59 - Food Inspection and Market Authority inspect the businesses and take approximately 11,000 samples per year for bacteriological and chemical tests.
Inspected businesses range from
- strawberry stands to supermarkets and whole sale traders,
- from hot dog stands to restaurants and hospital kitchens,
- from smallest manufacturers to industrial companies.
During unannounced inspections the following standards are monitored in order to protect consumers and serious entrepreneurs:
- shape and conditions of the business building, focussing on hygiene, including pest monitoring
- delivery, storage and processing of food
- visual inspection of food, including correct labelling
- hygiene and competence of staff
- self-control measures (including HACCP)
Particular attention is paid to organic food and drinking water in businesses. But the inspectors also check cosmetics and toys.
To ensure the quality of the controls, there are regular trainings for the inspectors. As the inspections follow EU wide rules, specialised EU agencies regularly monitor inspection standards. The Food Inspection Authority of the Vienna Market Authority is a member of the European Working Community for Food Inspection and Consumer Protection (EWFC).Contact for this page:
Market Service and Food Safety (Municipal Department 59)
Contact form


text:
Product DescriptionTug on the Campagnolo Sportswear T.G. System Lycra Overshoes before your next race. The Lycra fabric hugs your shoes and creates a smooth profile for air to flow over, which makes you more aerodynamic, and hopefully faster. Reflective logos make you more visible in headlights, and flat seams help your feet keep a low profile.
No Reviews Found.


text:
More Videos...
VW Bora VR6 Turbogockel - Sound & Accelerations & Onboard
VW Bora VR6 turbogockel - Sound, Accelerations, Onboard Facebook : https://www.facebook.com/pages/40-Perform/1527762747444429?ref=hl Lamborghini | Ferrari | Bugatti | McLaren | Porsche | Maserati | Corvette .......and more Mercedes | BMW | Audi | Opel | VW .........and more Chrysler | Dodge | Ford | Cadillac ........and more Honda | Toyota | Nissan | Mitsubishi..........and more what do i love.... hmm Aventador M3 M4 M5 M6 C63 AMG RS P1 GTR Supra SOUND Exhaust G-Power NOVITEC LaFerrari Acceleration Burnout flames V8 V10 V12 and more SOUND SOUND SOUND :) ..... this list will never end :)
Wheelandtorque.com presents Aaron Ok's 2003 Volkswagen Jetta Wolfsburg 1.8T
With all the exposure Aaron Ok was getting for his bagged and fitted VW Jetta Wolfsburg 1.8T, it was only a matter of time before Wheelandtorque.com had the opportunity to make a killer video of the car. Mr. Ok has been one of my toughest clients thus far, but all the criticism was constructive and much appreciated. Artist: Kinetics & One Love Song: Highline Exterior: OEM Jetta GLI Front Lip OEM Jetta GLI Rear Valence w/ Dual Tip Cutout OEM Jetta Euro Front Rubstrip Emphase E46 M3 Sideskirts Speedtech Boser Hood Extension Retrofit Porsche 996 TT Bi-Xenon HID Headlights OEM Jetta GLI Smoked Taillights 4 Bar Badgeless Grille Black Rear VW Emblem 35% Llumar Llumastar Tint Interior: Black Microsuede Headliner w/ Lime Green Inserts Black w/ Lime Green Stitching Armrest and Shift Boot VDO Boost Gauge Newsouth Steering Column Gauge Pod Blitzsafe Aux Input OEM European Light Switch OEM Jetta Monster Mats OEM Jetta GLI Pedals OEM Jetta GLI Deadpedal OEM Votex Aluminum Shift Knob Shortened Shifter Rod Megan Racing C-Pillar Tie Bar Engine, Trans & Exhaust: Revo Technik Stage 1 Software Custom 2.5" Unresonated Catback Exhaust w/Magnaflow Muffler ECS Stage 1 Clutch and Lightweight Steel Flywheel Eurosport Cool Flo Short Ram Intake Forge 007 Diverter Valve Lime Green Valve Cover Suspension, Wheel & Tire: Universal Air Front Airbags over B&G Coilovers Firestone Rear Airbags Twin VIAIR 400 Compressors Easystreet Autopilot Management w/ 5 gallon tank, 8 3/8th" SMC valves, 1/4" lines 18x8.5 (Front) & 18x10 (Rear) CCW K57 wheels w/ Mirror Polished 2.5" and 3.5" Lips 215/40/18 Falken Ziex 512 Tires (Front) 225/40/18 Falken Ziex 512 Tires (Rear) Cut out front sway bar Passenger side frame rail notched Subframe corners modified for control arm clearance
Volkswagen "Mk4" Jetta VR6 - One Take
The Fourth-Generation Volkswagen Jetta was the first total overhaul of the Jetta's basic design in nearly 20 years, and it was immensely popular when new, and now with the Waterfest crowd. Most were sold with 1.8L four-cylinder engines, but what about the VR6 version? Could it be a bargain on the used market? Check out the Jetta on WheelWell! https://www.wheelwell.com/profile/54e5119e48216e6b5c08389d/vehicles/54e511b 848216e6b5c08389e/specs/
Matte Black Plasti Dipped Volkswagen Jetta


text:
I would like to hire a Copy Typer
Presupuesto $30-250 USD
Adjudicado a:
I am a professional writer cum editor in the Government of Kenya. I am ready to do Copy typing for you in a professional way. Waiting to hear from you
5 los freelancers están ofertando un promedio de $124 para este trabajo.
Hi..I think this will be a good opportunity for me.I need to know your project details then I can easily move on to your project. I have the experience in this field. I can give you 24hrs service so that I can deliver Más


text:
Remembering Sean Taylor
Tuesday, November 27, 2007; 12:37 PM
Thousands of readers have offered tributes to Redskins safety Sean Taylor, expressing sympathy for his family and appreciation for his achievements. Below are excerpts of some of those comments. To share your thoughts, use the Comments form below.
As NFL football fans we send our sympathy to Mr. Taylors family and the Washington Redskins organization. RIP #21, You were a worthy opponent.
N.Y. Giants fans section 121
- franklakat
Sean Taylor was my favorite Redskin since Art Monk. I thought of him as a queit, misunderstood, ludicrously talented star in the secondary whom opposing offenses feared. It turns out he was also a father, a son, a brother and guy with a big heart.
- squid1
To Washington Residents and Redskins fans...
Having experienced the tragedy of losing our young star cornerback, Darrent Williams to a similar senseless act, I think everyone here in Denver understands how you are feeling this morning....Even if you have never met the man, it is entirely reasonable to feel a sense of personal loss and emptiness. I know, I've been there....
Jeff Thompson, Denver, CO
God Bless Taylor's family and the Redskins organization.
A Sad Dallas Cowboys Fan
- browine
21 was the face of the Skins for me. He played with reckless abandon on the field and appeared to be developing into a family man off it. I always admired that he never used the media as an outlet to showboat or draw attention to himself. Rather, he let his remarkable play speak for him....Hail.
- mile.high
Sean, you were my favorite current Redskin for so many reasons - your toughness, athleticism, love of the game, and the fear you instilled in the opposition....Rest in peace and God bless you and those you've left behind.
- johnwp
I'm sad today and for some reason feel as though I've lost a friend of mine. Maybe that's because I've been bleeding burgundy and gold for too long. Today the colors aren't quite as bright, the helmets aren't as shiny, and the roar of the stadium has turned into a whimper. We will miss you Sean, we will miss you.
- robertsimpson1
I loved this dude like he was my little Brother. He renewed my excitement about football. I always said if I played football I would have changed positions to SS just to play with him. This was my favorite football player EVER. I will miss him. I don't even know if I'll watch another game this season... or ever.
- SilkySlim19
This really puts a perspective on what is really important in life. Just to think, a couple days ago, everyone was upset we blew it against the Bucs. I would take years and years of futility on the field, blowing leads, not making playoffs to have Sean back....
- ayagci33
I'm literally at a loss for words... Such a sad and senseless tragedy. Suddenly, football seems just so unimportant. This young man was just beginning to realize his potential... Not only on the field, but in life. The entire Redskins family has been robbed of a treasure and now must grieve and heal together, from Dan Snyder and the coaching staff, to the players and everyone else who's ever held a place in their heart for the Burgundy & Gold.
- jfmayer
I absolutely loved the way #21 played the game and the passion he brought everytime he stepped on to the field. He may have been critized at times as being undisciplined - but his drive to be the best safety in the NFL came through with every bone crushing hit he delivered. Such a tragic loss. God bless Sean and his family. You will truely be missed. R.I.P.
- WeMissUSeanTaylor
Sean Taylor gave his life this morning defending his family. His sacrifice moved me to tears. He became what this world so cynically demands of our "mere" sports figures -- a true hero....
- HaikuMan
I've been crying all morning. I will miss Sean Taylor. A great player and human being.
A young professional football player a boy maturing into a man, ,a new father, a son to a mother and father....Sean Taylor brought it everytime he stepped on the football field his ACTIONS ON THE FIELD speak for themselves....
- TheBeatDontStop
I think I could feel a little more distant from this if I didn't have to explain it all to my son, who is 4 years old. But, because Sean Taylor was his favorite football player, I have had to explain to him about the shooting and how senseless violence impacts others. And now, I will have to explain his death as well, which is something I'm not looking forward to doing. He has been to almost every home game with me over the past 2 years, and it will be very strange that he won't be dragging me down to the lowest rows of section 112 to watch ST warm up any longer....
- JustMe


text:
Earlier this week, we told you that Jackie Robinson's brother Mack finished just .4 seconds behind Jesse Owens in the 1936 Olympics' 200-meter dash. Eventually, Owens, who won four gold medals that year, would give the one of those medals to famed tap-dancer and actor Bill "Bojangles" Robinson, whose family is now putting it up for auction.
Bidding for Owens' medal will begin at SCP Auctions on November 20 and close December 7.
[H/TSports Collectors Daily