text:
|Publication number
|Publication type
|Application number
|Publication date
|Oct 4, 2005
|Filing date
|Feb 25, 2003
|Priority date
|Mar 22, 2002
|Fee status
|Also published as
|Publication number
|Jade M. Kizer, Benedict C. Lau, Craig E. Hampel
|Original Assignee
|Rambus Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (53), Non-Patent Citations (5), Referenced by (28), Classifications (16), Legal Events (4)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a continuation-in-part of U.S. patent application Ser. No. 10/104,230, filed Mar. 22, 2002, and claims the benefit of U.S. Provisional Application No. 60/408,063, filed Sep. 3, 2002, U.S. Provisional Application No. 60/408,108 filed Sep. 3, 2002, and U.S. Provisional Application No. 60/436,756 filed Dec. 27, 2002. U.S. patent application Ser. No. 10/104,230 is hereby incorporated by reference in its entirety, and each of U.S. Provisional Application Nos. 60/408,063, 60/408,108 and 60/436,756 is hereby incorporated by reference in its entirety.
The present invention relates generally to high speed signaling within and between integrated circuit devices, and more particularly to clock generation in high-speed signaling devices and systems.
Delay locked loop (DLL) circuits are often used in high-speed signaling systems to generate clock signals having precisely controlled phase offsets relative to a reference clock.
The mix loop 123 includes a mixer 141, level converter 143, clock tree circuit 145 and phase detector 147 which cooperate to generate a mix control signal, MCTL. The mixer receives the phase vectors 122 from the reference loop 121 and interpolates between a selected pair of the phase vectors to generate a mix clock signal 142. The mix clock signal 142 is converted from a DPSS signaling level to a CMOS signaling level by converter 143, and is then passed through the clock tree circuit 145 (typically a series of amplifiers that enable fan out of multiple instances of the clock signal) to generate a feedback clock signal, FCLK. The phase detector 147 compares the feedback clock signal with the reference clock signal and generates the mix control signal according to which clock signal leads the other. For example, if the reference clock signal leads the feedback clock signal, the phase detector 147 signals the mixer 141 (i.e., by appropriate state of the mix control signal) to shift interpolation toward the leading one of the selected phase vectors (and away from the trailing phase vector), thereby advancing the phase of the feedback clock. Conversely, if the reference clock signal lags the feedback clock signal, the phase detector 147 signals the mixer to shift interpolation toward the trailing one of the selected phase vectors. If the reference clock still leads or lags the feedback clock signal after interpolation has been shifted completely to one of the selected phase vectors, a different pair of phase vectors (i.e., bounding an adjacent range of phase angles) is selected by the mixer 141.
The sampling clock generator 125 includes a mixer 149, converter 151 and clock tree circuit 153 that essentially mirror the operation of the mixer, converter and clock tree circuit within the mix loop 123 to generate a sampling clock signal, SCLK. The mixer 149 receives the mix control signal, MCTL, generated within the mix loop 123 and therefore, when an offset control signal, OCTL, indicates zero offset, performs the same interpolation operation on the same pair of selected vectors as the mixer 141. As the mix control signal is incremented and decremented, the mixer 149 tracks the operation of the mixer 141 such that the sampling clock signal tracks the feedback clock signal (i.e., the sampling clock signal and feedback clock signal have the same phase). The offset control value, OCTL, is a value that is added to a count maintained within the mixer 149 to provide a controlled, adjustable offset between the sampling clock and reference clock, thereby allowing correction of skew between the reference clock and a desired sampling instant.
Because of the high impedance load driven by the DACs 173 (i.e., the gate terminals of biasing transistors 165 1 and 165 2), several cycles of the reference clock signal are typically needed for the DAC to settle and, therefore, for the mix control signal to become valid. This is a significant disadvantage of the mixer 141, as a relatively long time is typically required to perform a phase locking operation in which numerous successive phase steps are needed to reach phase lock. Also, the ability to rapidly switch between phase offsets is limited by the DAC settling time.
The presence of the DPSS-to-CMOS converter 143 at the mixer output (see
The asymmetric swing of the DPSS signal relative to CMOS signal swing tends to complicate the return conversion from DPSS to CMOS signaling levels.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
In the following description, for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the present invention. In some instances, the interconnection between circuit elements or circuit blocks may be shown as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be single signal conductor lines, and each of the single conductor signal lines may alternatively be multi-conductor signal lines. A signal is said to be "asserted" when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be "deasserted" to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to "output" a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be "activated" when a signal is asserted on the signal line, and "deactivated" when the signal is deasserted. Additionally, the prefix symbol "/" attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., '{overscore (<signal name >)}') is also used to indicate an active low signal. Active low signals may be changed to active high signals and vice-versa as is generally known in the art.
Dual Rail Regulated Delay Locked Loop
In embodiments of the present invention, both the upper and lower supply voltages to a chain of inverters are adjusted by a voltage regulation circuit to produce a desired input-to-output delay through the inverter chain. Signals generated by individual inverters within the inverter chain are output as reference phase vectors to a mixing circuit and have signaling levels referred to herein as dual regulated small swing (DRSS) signaling levels. Because both supply voltages to the inverter chain are adjusted toward or away from a midpoint between system supply voltages (e.g., toward or away from VDD/2), the signal swing of each DRSS-level phase vector is substantially symmetric with respect to the signal swing of CMOS signals, thereby avoiding the duty cycle distortion problems that plague prior art converters upon re-conversion from small-swing to CMOS signaling levels.
In one embodiment, a mixing circuit within a DLL is formed by inverters that are sized to achieve a binary weighted delay in proportion to the delay introduced by an inverter within the inverter chain. By this arrangement, a pair of phase vectors may be mixed by inputting the phase vectors into respective sets of the binary weighted inverters and selectively enabling the binary weighted inverters to achieve a desired phase contribution from each of the phase vectors. Thus, unlike the prior art mixer described above, no DAC-generated bias voltage is needed, and the multi-clock cycle DAC settling time is avoided. As a result, substantially faster phase locking may be achieved and the time required to switch between arbitrary phase offsets may be reduced.
Overview of a DLL Circuit According to an Embodiment of the Invention
The phase detector 257 receives the feedback and reference clock signals (FCLK and CLK) and generates a mix control signal 260 (MCTL) that indicates whether the reference clock signal leads or lags the feedback clock signal. Mix logic within the DRSS mixer 253 1 responds to the mix control signal 260 by advancing or retarding the phase of the mix clock signal 254 1 and, therefore, advancing or retarding the phase of the feedback clock signal 256. In one embodiment the phase detector 257 is a zero phase detector (ZPD) in which the feedback clock signal 256 is used to sample the reference clock signal and thereby generate the mix control signal 260 according to whether the reference clock signal has changed state before or after the sampling instant (i.e., before or after an edge of feedback clock signal 256). Alternatively, the reference clock signal may be used to sample the feedback clock signal 256. Also, other types of phase detectors may be used in alternative embodiments.
The DRSS mixer 253 2 receives both the mix control signal 260 and an offset control value 262 (OCTL). The offset control value 262 is used to provide an adjustable offset between the sampling clock signal 258 and the reference clock signal. Mix logic within the DRSS mixer 253 2 responds to the state of the mix control signal 260 by advancing or retarding the phase of the mix clock signal 254 2 and, therefore, the sampling clock signal 258. Thus, if the offset control value specifies a zero phase offset, the sampling clock signal 258 and feedback clock signal 256 will remain substantially phase aligned with one another and with the reference clock signal.
In one embodiment, the offset control value 262 is maintained in a configuration circuit within the integrated circuit device that includes the DLL circuit 250. The configuration circuit may be a volatile or non-volatile memory, or a fusible or otherwise one-time programmable circuit. Also, instead of on-chip configuration, the offset control value 262 may be maintained or generated by a device that is external to the integrated circuit that contains the DLL circuit 250. Whether maintained on or off chip, the offset control value 262 may be initialized at system startup (e.g., as part of a calibration procedure that determines a desired offset between the sampling clock signal and reference clock signal) and/or updated in periodic calibration operations or in response to predetermined events (e.g., detection of threshold error rate or threshold phase difference between center of data eye and edge of sampling clock signal 258). Also, because the DRSS mixer 253 2 is able to adjust the phase of the sampling clock signal 258 relatively quickly in response to changes in the mix control signal 260 and/or offset control value 262, the offset control value 262 may be adjusted between successive reception and/or transmission operations to achieve a phase-jumping mode of operation. Phase jumping is discussed below in greater detail.
Dual Regulated Small Swing Signal Conversion
Still referring to
Dual Regulated Small Swing Reference Loop
The dual rail regulation circuit 361 adjusts the regulated voltages, REG+ and REG−, to achieve a desired delay through each of the delay lines. More specifically, the dual rail regulation circuit 361 adjusts the upper and lower regulated voltages, REG+ and REG−, in response to a phase difference between a selected pair of clock signals output by the delay lines 363 and 365 (and, optionally converted to CMOS signaling levels) such that the propagation delay through a subset of the delay elements within each delay line 363 and 365 is equal to half the period (i.e., 180 degrees) of the reference clock signal. In the example of
In the embodiment of
The dual regulation circuit 361 includes a phase detector 371, common-mode-feedback charge pump 373 and linear regulator 375. The phase detector 371 is coupled to receive the nominally 360 degree phase vector from a converter E (a most delayed phase vector) and to receive the 0 degree phase vector, V0, from converter A (a least delayed phase vector). The phase detector 371 compares the 0 and 360 degree phase vectors and generates a voltage control signal 372 according to which of the vectors leads the other. More specifically, the phase detector 371 asserts (e.g., to a logic high state) an up signal (UP) to reduce the delay through the delay lines 373 and 375 if the 360 degree phase vector lags the zero degree phase vector, and asserts a down signal (DN) to increase the delay if the 360 degree phase vector leads the zero degree phase vector. In one embodiment the phase detector 371 is a zero phase detector (ZPD) in which the 0 degree phase vector is used to sample the 360 degree phase vector and thereby generate the voltage control signal 372 according to whether the 360 degree phase vector has changed state before or after the sampling instant (i.e., before or after an edge of the 0 degree phase vector). Alternatively, the 360 degree phase vector may be used to sample the 0 degree phase vector. Also, other types of phase detectors may be used in alternative embodiments.
The up and down signal components of the voltage control signal 372 are received by the common-mode-feedback charge pump 373 and used to adjust the levels of reference voltages, REF+ and REF−. The reference voltages, REF+ and REF−, are output to the linear regulator 375 where they are used to generate the regulated voltages, REG+ and REG−. Overall, the negative feedback operation of the reference loop 360 drives the regulated voltages, REG+ and REG−, to the levels necessary to achieve phase alignment between the 360 degree and 0 degree phase vectors input to the phase detector 371. As discussed below, the common-mode-feedback charge pump 373 includes a negative-feedback bias control circuit that maintains the common mode between the REF+ and REF− voltages, and therefore the common mode between the REG+ and REG− voltages, substantially at the common mode of the system supply voltages, VDD and GND. That is, the regulated voltages, REG+ and REG−, generated by the dual rail regulation circuit 361 are maintained substantially centered about the CMOS common mode. In an alternative embodiment, the set of DRSS to CMOS converters 367 maybe omitted, and the 0 degree phase vector output by inverter A of delay line 363 and the 360 degree phase vector output by inverter E of delay line 365 may be input directly to the phase detector 371.
Still referring to
Referring again to
Note that, in a delay line formed by a chain of delay elements 390, the desired delay between input and output transitions of any single delay element in the chain depends, in part, on the number of delay elements interposed between the 0 and 180 degree outputs. If four such delay elements are used (as in the delay lines 363 and 365 of FIG. 13), an input-to-output delay (i.e., of each delay element 390) equal to the 45 degree interval is needed to create phase alignment between the 0 degree phase vector and the 360 degree phase vector. If, for example, eight such delay elements are used instead of four, a delay of 180/8=22.5 degrees is needed to create the same phase alignment. Although 45 degree intervals are described as the desired separation between phase vectors in the remainder of the description, different degrees of phase vector separation may be used in alternative embodiments.
Referring again to
Dual Regulated Small Swing Mixer
The mix vector select circuit 419 receives the octant select signal 432 and includes select logic 451 and multiplexers M1, M2, M3 and M4 to select a pair of octant-bounding phase vectors and their complements from the set of eight phase vectors output from the reference loop (i.e., V0-V3 and /V0-/V3). That is, the mix vector select circuit 419 selects, according to the octant select signal 432, a pair of phase vectors (and their complements) that are offset from one another by a 45 degree interval and that therefore bound an octant within the 360 degree phase plot of a reference clock signal. The selected pairs of phase vectors are referred to herein as mix vectors, MV0 and MV1, and complement mix vectors, /MV0 and /MV1, as they are mixed by the DRSS mix amplifiers 423 to produce mix clock signals, MCLK and /MCLK.
Note that, in a system in which more or fewer than eight phase vectors are input to the mix vector select circuit 419, the number of bits maintained within counter 431 (and offset count register 435, if used) for selection of a vector pair may be greater or less than three. In general, if N phase vectors are input to the mix vector select circuit 419, log2N bits are needed to select a pair of mix vectors and complement mix vectors.
Still referring to
The CMOS-to-DRSS converters 421 1 and 421 2 are provided to convert the signal levels of the selected mix vectors (i.e., MV0, MV1, /MV0 and /MV1) from CMOS to DRSS signal levels before the mix vectors are input to the DRSS mix amplifiers 423. As discussed above, in an embodiment in which the DRSS reference loop outputs DRSS-level phase vectors, the converters 421 1 and 421 2 may be omitted.
Referring again to the mix logic 417, the ramp polarity selector 437 includes an inverter 439 and a pair of multiplexers 441 and 443 to generate an N-bit interpolation word, IW, and N-bit complement interpolation word, /IW, in response to the interpolation value 442. The purpose of the ramp polarity selector 437 is to ramp the interpolation word (i.e., in response to increases in the count value) in an increasing direction for certain selected pairs of mix vectors and to ramp the interpolation word in a decreasing direction for other selected pairs of mix vectors. This operation is described in further detail below. Note that a stage of flip-flops or other synchronizing circuits may be provided to synchronize the outputs of the mix logic so that the interpolation word, IW, complement interpolation word, /IW, and octant select signal 432 all change state synchronously in response to changes in the count value (i.e., maintained within counter 431) or offset count value.
The DRSS mix amplifier block 423 includes four mix amplifiers A, B, C and D, that each receive a respective one of the mix vectors, MV0, MV1, /MV0 and /MV1, and that each receive the interpolation word, IW, and complement interpolation word, /IW. More specifically, mix amplifiers A and B receive the uncomplemented mix vectors, MV0 and MV1, respectively, while mix amplifiers C and D receive complement mix vectors, /MV0 and /MV1. Also, mix amplifiers A and C receive the interpolation word and complement interpolation word at inverting and noninverting control inputs, respectively, while mix amplifiers B and D receive the interpolation word at a noninverting control input and the complement interpolation word at an inverting control input. By this arrangement, constituent amplifier circuits within mix amplifiers A and C are enabled while the corresponding constituent amplifier circuits within mix amplifiers B and D are disabled, and vice-versa. The outputs of mix amplifiers A and B are coupled together to supply a DRSS-level mix clock signal (MCLKDRSS) to converter 425, and the outputs of mix amplifiers C and D are similarly coupled together to supply a DRSS-level complement mix clock signal (/MCLKDRSS) to converter 425. Thus, mix amplifiers A and B each output a respective mix vector onto a first output line 424, and mix amplifiers C and D each output a respective complement mix vector onto a second output line 426. Converter 425 converts the DRSS-level mix clock signal and complement clock signal to CMOS-level mix clock signals, MCLKC and /MCLKC.
The interpolation word, IW, and complement interpolation word, /IW, generated by the mix logic are used to control the relative drive strengths of the mix amplifiers A, B, C and D such that the resultant mix clock signals have phase offsets that fall within the range of phase angles bounded by the input mix vectors. As the interpolation word, IW, is incremented (and the complement interpolation word, /IW, correspondingly decremented), the phase angle of the mix clock signal is progressively stepped away from the leading mix vector and toward the trailing mix vector (i.e., mix clock signal is incrementally delayed). Conversely, as the interpolation word is decremented (and the complement interpolation word correspondingly incremented), the phase angle of the mix clock signal is progressively stepped away from the trailing mix vector and toward the leading mix vector (i.e., the mix clock signal is incrementally advanced). For example, in the case of a six bit interpolation word that is used to control the mixing of vectors V0 (selected to be mix vector MV0) and V1(selected to be mix vector MV1), the interpolation word might initially be 0 such that the complement interpolation word is at a maximum value, thereby causing vector V0 to be driven onto the MCLKDRSS output line by mix amplifier A at maximum drive strength and mix amplifier B to be disabled (i.e., a zero drive strength used to drive vector V1 onto the MCLKDRSS output line). As the interpolation word, IW, is incremented (and the complement interpolation word, /IW, decremented), the drive strength of mix amplifier A is decreased and the drive strength of mix amplifier B is increased to adjust the phase of the resultant mix clock signal, MCLKDRSS, away from vector V0 and toward vector V1. Eventually, when the interpolation word reaches a maximum value, the complement interpolation word applied to mix amplifier A will be 0 and a full drive strength (i.e., due to the maximum value interpolation word, IW) will be enabled within mix amplifier B. As a result, vector V1 will be output as the mix clock signal, MCLKDRSS with zero contribution from vector V0. If the count value within the mix logic is incremented further, the interpolation value will roll from a maximum value to a minimum value and the octant select value will be incremented to select a different pair of mix vectors. In the case of an increment beyond the V0/V1-bounded octant, vector V2 will be selected by multiplexer M1 instead of vector V0 such that mixing will now take place between vectors V2 and V1. The least significant bit of the octant select signal is applied to the multiplexers 441 and 443 within the ramp polarity selector 437 to cause the interpolation word, IW, to be decremented from a maximum value to a minimum value and the complement interpolation word, /IW, to be incremented from a minimum value to a maximum value.
Each of the tri-state inverters within the mix amplifier 471 is enabled by respective bit of the interpolation word, IW, and complement interpolation word, /IW. For example, if bit 0 of the interpolation word (i.e., IW0) is high and its complement (/IW0) is low, the x1 inverter will be enabled to drive the input mix vector, MV, onto the output signal line 472. Note that the interpolation word and complement interpolation word connections shown in
The tri-state inverters within the DRSS mix amplifier 471 are powered by the regulated supply voltages, REG+ and REG−, generated by the dual rail regulation circuit within the DRSS reference loop. Consequently, by sizing the tri-state inverters such that the full scale drive strength of the mix amplifier 471 is equal (or substantially equal) to the drive strength of a delay element within the DRSS reference loop (i.e., one of the delay elements A-E within delay lines 363 and 365 of FIG. 13), the full-scale slew rate of the mix amplifier 471 may be aligned with the slew rate of the reference loop delay element. For example, by establishing the drive strength of the x32 inverter (e.g., by transistor width selection) to be half the drive strength of a 45 degree delay element within the DRSS reference loop, then the full scale drive strength of the mix amplifier 471 will be substantially equal to the drive strength of the 45 degree delay element (i.e., x32+x16+x8+x4+x2+x1=x63≅2 times x32), and the full scale mix amplifier output will cross the regulated common mode voltage at the 45 degree interval. Thus, as shown in
Phase Jumping
Because the DRSS mixer described in reference to
Embodiments of the present invention may also be used to achieve a rapid succession of different phase alignments of a sampling clock signal, with each different phase alignment corresponding to a respective transmission source within a signaling system. For example, in a master/slave system in which slave transmissions to a master device occur deterministically in response to master device commands or requests (i.e., when the master device issues a command or request, the master device may anticipate a responsive transmission from the slave a predetermined time later), the master device may select a previously determined sampling clock offset according to which slave device is scheduled to transmit at a given time. Such operation is referred to herein as source-based phase jumping and may be implemented within a master device, for example, by storing a respective offset control value (OCTL) for each slave device in a signaling system and selecting (e.g., from a lookup table or other memory) different ones of the stored offset controlled values according to the identities of the slave devices scheduled to transmit. More generally, source-based phase jumping may be used in any device that has or receives forehand information of transmission sources. Such forehand information may result from system determinism (i.e., predetermined response times to system events such as commands, requests, interrupts, timing signals, etc.) or from other communications including, without limitation, communications via out-of-band signaling channels (e.g., handshaking signals).
Both destination and source-based phase jumping may be implemented within the same integrated circuit device (e.g., one or more master devices within a master/slave system) and a shared memory structure used to store offset control values for the various transmission destinations and sources. Offset control values may be determined, for example, by transmission of predetermined test patterns between system devices to learn the leading and lagging phase boundaries beyond which transmission errors are detected. Methods and apparatuses for performing such timing calibration operations are disclosed, along with other locked-loop applications in which embodiments of the present invention may be used, in U.S. patent application Ser. No. 09/421,073, filed Oct. 19, 1999 (entitled "Bus System Optimization"), and U.S. Pat. No. 6,321,282, each of which is hereby incorporated by reference in its entirety.
Embodiments of the present invention may also be applied to achieve destination and/or source-based phase jumping in signaling systems in which integrated circuit devices (or components within an integrated circuit device) are clocked by different clock signals having nominally the same frequency, but arbitrary phase relationships. In such a system, the phase offsets between various transmit and sampling clock signals used to time signal transmission and reception may be systematically determined and used to generate offset control values. The offset control values may then be dynamically retrieved (e.g., from a lookup table or other memory) to time data reception and/or transmission operations in one or more of the integrated circuits according to the source or destination of the data transmission. In one such system, for example, a memory controller mounted to a motherboard (or other substrate) is coupled to multiple memory modules (i.e., daughterboards or other substrates having one or more integrated circuit memory devices mounted thereon) via a common signaling path, the memory modules being clocked by respective clock signals having nominally the same frequency, but arbitrary phase relationships. The memory controller may receive any or all of the clock signals provided to the memory modules, and/or a separate clock signal. In one embodiment, the memory controller includes a DLL circuit or PLL circuit according to the present invention to achieve rapid, source and/or destination-based phase jumping.
The phase jumping capability of the DRSS mixer of
Avoiding Transient Phase Errors Due to Mix Amplifier Switching
Referring to
In one embodiment of the invention the most significant bits of the interpolation value 442 of
Charge Pump with Common Mode Feedback
Referring again to
Current I1 may similarly be expressed as a function of differential amplifier gains, bias currents and differential inputs as follows:
Thus, currents I1 and I2 are each dependent on the difference between the CMOS common mode voltage, VDD/2, and the regulated common mode voltage, REFCM. Also, referring to
Linear Regulator
The differential amplifier 603 includes a first current source 631 which sources current 2I to the source terminals of differentially coupled transistors 635 and 637, and a second current source 633 which sinks current I via transistor 635. By this arrangement, half the current generated by current source 631 (i.e., current I) flows through transistor 637, thereby causing the regulated voltage, REG−, developed at the gate terminal of transistor 637 to follow the REF− input signal. The current sinking transistor 607 is coupled in a follower configuration with the differential amplifier 603 (i.e., gate terminal of transistor 607 coupled to the drain terminal of the transistor 635, and source terminal of transistor 607 coupled to the gate terminal of the diode-configured transistor 637), drawing current IX from the load 609 and current I from the first current source via transistor 637. Thus, the voltage at the drain of transistor 635 is developed as necessary to bias transistor 607 to sink current I+IX, thereby maintaining current I through transistor 637 and, therefore, maintaining equality (or substantially so) between the regulated output voltage, REG−, and the reference signal, REF−, regardless of the current IX drawn from the load 609. Capacitor CL is coupled in parallel with the load 609 to dampen transient voltage changes as discussed above.
Reflecting on the operation of the linear regulator of
It should be noted that the DRSS locked loop architecture described in reference to
System Application of Locked Loop Circuit
The system 700 includes a pair of integrated circuits (ICs) 701 and 703 coupled to one another via a transmit signal path 702 and a receive signal path 704. In the embodiment, shown, the signal paths 702 and 704 are unidirectional high-speed serial links for conducting serialized transmissions from one IC to the other. In alternative embodiments, either or both of the links may be bi-directional (i.e., with appropriate circuitry provided to select which of the ICs is enabled to transmit on the link at a given time), and multiples of such signal paths may be provided to enable transmission of parallel groups of bits (e.g., each group of bits forming a data or control word (e.g., command, address, etc.) or portion of a data or control packet). Also, the transmit signal path 702, receive signal path 704, and/or shared transmit-receive signal path may be a multi-drop bus that is coupled to additional ICs. The ICs 701 and 703 may be peers (e.g., each IC is capable of independently initiating a signal transmission to the other), or master and slave. Also, the relative status of the ICs 701 and 703 may change from time-to-time such that one IC is a master at a first time, then a slave at another time, and/or a peer at another time. IC 701 is shown in simplified block diagram form and includes a transmit circuit 711, receive circuit 713, locked loop circuit 709, and application logic 715. As shown, the locked loop circuit 709 is coupled to receive complementary reference clock signals, CLK and /CLK, from an off-chip reference clock generator 705, and outputs a phase-locked clock signal 706 to the transmit circuit 711 and the receive circuit 713. In an alternative embodiment, the reference clock signals, CLK and /CLK, may be generated within IC 701 or IC 703. A configuration circuit 717 (e.g., register, one-time programmable circuit, non-volatile memory, etc.) may be included within the application logic 715 to store one or more offset control values that are used to establish a phase offset between clock signal 706 and reference clock signal, CLK. Note that clock signal 706 may include a complementary pair of clock signals as described above. Also, while the locked loop 709 is depicted as providing a clock signal to both the transmit circuit 711 (i.e., a transmit clock signal) and to the receive circuit 713 (i.e., a sampling clock signal), separate locked loop circuits may be provided to generate separate transmit and sampling clock signals. Alternatively, multiple clock generation circuits may be provided within the locked loop circuit 709 to generate separate transmit and sampling clock signals. For example, in an embodiment in which locked loop 709 is a DLL circuit implemented as shown in
Time-Multiplexed TX/RX Clock Line
The signaling device 745 includes a tracking loop 747, offset clock generator 749, transceiver 781 and application logic 771. The signaling device additionally includes a DRSS-reference loop (not shown) implemented according to the embodiments described above to supply a set of phase vectors 758 and dual regulated supply voltages to the phase jumping mixers 751 within the tracking loop 747 and the offset clock generator 749. The tracking loop 747 includes a phase counter 757, phase jumping mixer 751, clock tree 753 and phase detector 759. The phase jumping mixers 751 within the tracking loop 747 and offset clock generator 749 are implemented in substantially the same manner as the DRSS mixer 415 described in reference to
The offset clock generator 749 includes a pair of storage circuits 761 and 765, summing circuit 750, select circuit 769, phase jumping mixer 751 and clock tree 753. The storage circuits 761 and 765 are used to store a transmit phase offset value and a receive phase offset value, respectively, which are output to the summing circuit 750. In the embodiment of
The application logic 771 includes circuitry specific to the general function of the integrated circuit device (e.g., memory controller, memory device, processor, application-specific integrated circuit (ASIC), programmable logic device (PLD), or any other type of integrated circuit device. In one embodiment, the transmit circuit 773 is a pull-down type transmit circuit that pulls signal path 778 down from a precharged level (e.g., pulled up to a supply voltage) to transmit a symbol other than a zero-valued symbol, and that transmits a zero-valued symbol by allowing the signal path 778 to remain at the precharged level. Thus, the application logic 771 may effectively disable transmitter 773 from affecting the state of the signal path 778 during a data reception interval by outputting a value onto the transmit data line 774 that corresponds to a zero-valued symbol. In an alternative embodiment in which the transmitter 773 is a push-pull output driver (or any other type of output driver that affects the state of the signal path 778 regardless of the value of the symbol being transmitted), the application logic may output a disable signal to the transmitter 773 to disable the transmitter from affecting the state of the signal path 778 during a data reception interval. Also, while the transmit phase offset value and the receive phase offset value are depicted as being stored in dedicated storage circuits 761 and 765, a shared storage circuit (e.g., a multi-entry memory array) may alternatively be used.
Reflecting on the operation of the device of
Phase Searching
To save power during periods of non-communication in a high-speed signaling system, delay locked loop and phase locked loop circuits are often disabled from tracking a reference clock signal (the reference clock signal itself being shut off in some systems). Before communication is restored in such systems, the locked loop circuits are re-enabled in a wake-up operation. In many systems, the time required to complete the wake-up operation is the dominant factor in how quickly communication may be restored, and is directly related to the time required for the locked loop circuit to regain phase lock with the reference clock signal.
Reflecting on
When a locked loop circuit which includes the tracking loop 823 is enabled (e.g., in a wake-up operation), the value in the phase counter 827 may be stale, random or otherwise may not reflect the phase difference between the reference clock signal 760 and the feedback clock signal 752. Accordingly, the phase of the feedback clock signal 752 may have any phase offset relative to the reference clock signal 760 and the phase search operation of
Referring to
Searching for Leading and Trailing Edges of a Data Eye
After phase lock is achieved within the tracking loop of a locked loop circuit, another phase search may be performed in the offset clock generator (i.e., element 749 of
While the task of determining pass-fail phase boundaries may be achieved by incrementing a phase offset value (e.g., the offset control value 262 of
As shown in
At 903, the search vector offset is loaded into the offset register to produce an initial search vector (i.e., clock signal generated by the DRSS mixer 253 2 of
Returning to 907, in the case of a pass-vector, if a trailing edge of the data eye has not been found (i.e., any preceding executions of the pattern transfer test have not yielded a pass-vector determination followed by a trail-vector determination), then the pass-vector represents a possible bounding vector for a trailing edge of the data eye. Accordingly, at 919, Boolean value TESEARCH is set to true to indicate detection of a pass-vector, and the search vector offset is recorded in EYE TEPASS, a value that represents the phase angle of the bounding pass-vector for a trailing edge of the data eye. At 921, Boolean value LESEARCH is inspected to determine whether a fail-vector was located in a prior execution of the pattern transfer test 905. If so, then the pass-vector detected in the present iteration constitutes an outer bound of a leading edge of the data eye. Accordingly, at 923, Boolean value LEFOUND is set to TRUE to indicate that fail- and pass-vectors that bound the leading edge of the data eye have been found, and the search vector offset that yielded the present pass-vector is recorded in EYE LEPASS. Also, Boolean value LESEARCH is set to FALSE to prevent further update to the EYE LEPASS value.
After fail-vector processing in blocks 909-915 or pass-vector processing in blocks 917-923, the jump angle is summed with the search vector offset at 925 to produce a search vector offset that corresponds to the next search vector. At 927, the search vector offset is compared with a maximum value to determine whether all the search vectors have been evaluated. If so, the coarse linear search is completed and a binary edge search is executed at 931. The binary edge search is described in further detail below in reference to FIG. 40. In one embodiment, even if all the search vectors have not been evaluated, the coarse linear search may still be concluded if the leading and trailing edges of the data eye have been found (i.e., LEFOUND and TEFOUND are determined to be true in 929). Otherwise, the coarse linear search is repeated, starting at 903, for the updated search vector offset.
The following table illustrates the result of a coarse linear search according to
TABLE 1 Test SVO Result LESRCH LEFOUND LEFAIL LEPASS TESRCH TEFOUND TEPASS TEFAIL 0� Fail True False 0� 0� False False 0� 0� 72� Fail True False 72� 0� False False 0� 0� 144� Fail True False 144� 0� False False 0� 0� 216� Pass True True 144� 216� True False 216� 0� 288� Fail True True 144� 216� True True 216� 288�
Thus, at the conclusion of the coarse linear search, a leading edge of the data eye has been determined to be bounded by phase offsets of 144� and 216�, and a trailing edge of the data eye has been determined to be bounded by phase offsets of 216� and 288�. Note that the search vector offset is a digital value, but is listed in degrees in the table above for purposes of illustration.
Still referring to
Upon conclusion of the bounded binary search at 951 (and optionally the linear search at 953), the bounded binary search may be repeated to determine the phase offset of the trailing edge of the data eye; the bounding variables B1 and B2 being assigned trailing edge bounding offsets (EYE TEPASS and EYE TEFAIL values, respectively), instead of the leading edge bounding offsets shown in 935; and the operations in 947 and 945 being swapped to account for the opposite direction of the transition between pass- and fail-vectors.
As discussed above, fine linear searches may be used to determine the precise phase offsets of leading and trailing edges of a data eye instead of bounded binary searches. In one embodiment, a coarse linear search is performed as described in reference to
where C is the number of phase search operations performed in the coarse linear search; F1 is the number of phase search operations performed in a fine linear search (i.e., stepwise increment of phase control value, rather than a discontinuous jump) for the phase offset of the leading edge of the data eye, and F2 is the number of phase search operations performed in a fine linear search for the trailing edge of the data eye. Letting M represent the total number of selectable phase offsets within the complete searchable range, then F1 and F2 may be expressed as follows:
For example, if an 9-bit phase control value is used to control the phase offset of the mix clock signal generated by a phase jumping mixer, and twenty coarse phase search operations are performed to locate the bounding phases of the leading and trailing edges of the data eye, then M=29=512, and F1=F2=(512−20)/20=25 (i.e., after rounding up from 24.6 to an integer value). Thus, 25 stepwise phase search operations are performed between bounding coarse phase offsets to locate the leading edge of the data eye and another 25 stepwise phase comparison operations are performed between bounding coarse phase offsets to locate the trailing edge of the data eye, yielding a total of N=20+25+25=70 phase search operations to precisely locate the phase offsets of the leading and trailing edges of the data eye.
Substituting the right-hand side of expression (2) for the F1 and F2 terms in expression (1), the following expression for N is obtained:
In locked loop circuits for which M is a predetermined value and therefore fixed (M may alternatively be a programmable or adjustable value), it can be seen that N is a nonlinear function of C. Based on this insight, expression (3) may be rewritten as a differential expression and solved for a relative minima (the second derivative of expression (3) is positive for C>0, so that the zero-valued first derivative is a relative minima) as follows:
N=C+2MC −1−2 {rewriting expression (3) to simplify the differential} (4)
dN/dC=1−2MC −2 (5)
0=1−2MC −2 {setting the differential to zero to solve for the relative minima} (6)
Thus, for a locked loop circuit having M selectable phase offsets within a searchable range, the number of coarse linear search operations, C, which yields the lowest total number (N) of coarse and fine linear search operations used to determine the phase offsets of the trailing and leading edges of a data eye is given by the square root of 2M. In the example above in which M=512, expression (7) indicates a minimum N when C=32. Inserting C=32 into expression (2) yields F1=F2=15. Similar analyses may be performed for systems in which a coarse linear search is followed by a bounded binary search, and for systems in which phase comparison operations are performed more than once per phase offset (e.g., performing the phase comparison operation multiple times to filter erroneous lead-lag determinations).
For some values of M (256, for example), the expression (7) yields a non-integer value for C which, when rounded up or down to the nearest integer, may lead to a value of N that is not a minimum. In such cases, neighboring values of C (i.e. C+1, C+2, . . . , C−1, C−2, . . . ) can be checked to determine if the resulting number of searches (i.e. values of N) are lower than with the calculated value of C. Alternatively, the calculated, rounded value of C can be used since the corresponding value of N will be close to the absolute minimum, if not the absolute minimum.
Timing Maintenance; Compensation for Drift
In one embodiment of the present invention, the fast phase-jumping ability of the locked loop circuit 251 of
Referring to
When a timing maintenance operation is to be performed, the sample select signal 970 is transitioned to a leading-edge-test state, and selects register 965 to source a leading edge phase offset value to adder 971. Consequently, the phase control value 968 is transitioned from the sampling clock phase control value to a leading-edge phase control value. The phase jumping mixer 751 responds to the transition of the phase control value 968 by rapidly transitioning the phase of the output clock signal to the leading edge sampling instant shown at 955 of
After a pass/fail result is recorded for the leading-edge data transfer test, the sample select signal 970 is transitioned to a trailing-edge-test state, and selects register 969 to source a trailing edge phase offset value to adder 971. The adder 971 responds to the new phase offset value by transitioning the phase control value 968 from the leading-edge phase control value to a trailing-edge phase control value, and the phase jumping mixer 751 responds in turn by rapidly transitioning the phase of the output clock signal to the trailing edge sampling instant shown at 959 of
Still referring to
Per-Device Phase Offset; Source- and Destination-Based Phase Jumping
In one embodiment of the present invention, the fast phase jumping ability of the locked loop circuit 251 of
Still referring to
Still referring to
Locked Loop Circuit with Clock Hold Function
The offset clock generator 1109 includes an offset selector 1121, adder 1131, phase jumping mixer 1123, clock hold circuit 1125, and clock tree circuit 1127. The offset selector 1121 selects between offset values 1114 and 1116 (OFST1 and OFST2, respectively) according to an offset select signal 1102 (OFF_SEL). The selected offset value 1118 is summed with the phase count value 1112 in adder 1131 to produce a phase control value 1120. In an alternative embodiment more than two offset values may be input to the offset selector 1121, and the offset values or a subset thereof may be maintained within the locked loop circuit 1101 rather than being provided by external logic. Also, the phase count value 1112 may alternatively be summed with each of the offset values in separate adder circuits, with the summed values being input to the offset selector 1121 (see summing circuit 750 of
The phase jumping mixer 1123 generates a mix clock signal 1122 (MCLK) by interpolating between a selected pair of the phase vectors 1110 in accordance with the phase control value 1120. The mix clock signal 1122 is provided to the clock hold circuit 1125 which, in response, outputs a hold clock signal 1124 (HCLK) to the clock tree circuit 1127. The hold clock signal 1124 propagates through the clock tree circuit 1127 to produce multiple instances of an offset clock signal, at least one of which is the clock signal 1130 provided to the synchronous logic circuit 1103. The synchronous logic circuit includes one or more logic circuits which respond to transitions in the clock signal 1130 (e.g., flip-flops and/or other edge-triggered logic circuits). Note that the clock tree circuit 1127 may be omitted in embodiments in which the fan out of the hold clock signal 1124 is limited. Also, a delay circuit which exhibits substantially the same propagation delay as the clock hold circuit 1125 may be included within the tracking loop 1105 such that, in the case of a zero-valued offset 1118, clock signal 1130 is substantially phase aligned to with the feedback clock signal 1108.
Clock signals exhibiting occasional runt pulses may be tolerated in some systems, (e.g., where the clock signal is used solely to clock input/output circuits), but tend to produce undesirable meta-stable states and/or race conditions in synchronous logic circuits due to the inability to guarantee signal setup and hold times and due to the uncertain transition time of state variables (e.g., flip-flop outputs). In the locked loop circuit 1101 of
Still referring to
The hold signal generator 1177 includes ahold control circuit 1183, delay element 1187 (D1), exclusive-OR gate 1185, delay element 1189 (D2) and multiplexer 1191. In one embodiment, the hold control circuit 1183 is a finite state machine that outputs a hold signal 1190 as a state variable, and that transitions between states according to the respective states of a jump signal 1202, and a clock-XOR signal 1186. The jump signal 1202 is asserted by the synchronizing logic 1181 in response to a transition in the offset select signal 1102, and therefore indicates that a phase jump in the mix clock signal 1122 is being initiated. The clock-XOR signal 1186 is high whenever the hold clock signal 1124 and a delayed instance 1188 of the mix clock signal 1122 (i.e., delayed by delay element 1187), have different states. In one embodiment, the delay element 1187 is formed by an inverter chain that matches an inverter chain in a non-latching input-to-output path within the latch 1175. Consequently, when the qualified hold signal 1194 is deasserted, the delayed mix clock signal 1188 is phase aligned with the hold clock signal 1124, and the clock-XOR signal 1186 is low. By contrast, when the qualified hold signal 1194 is asserted, the clock-XOR signal goes high when the delayed mix clock signal 1188 transitions to a state different from the latched state of the hold-clock signal. That is, the clock-XOR signal goes high at the start of the first high- or low-level pulse following assertion of the qualified hold signal 1194.
As briefly discussed above, if the qualified hold signal 1194 is asserted coincidentally with a transition of the hold clock signal 1124 (or transition of the mix clock signal 1122 or an intermediary clock signal generated within the latch 1175), a metastable hold clock signal 1124 may be output by latch 1175 (i.e., the voltage level of hold clock signal 1124 may fall within an invalid range between two valid output voltage levels). In addition to the potential for producing undesired results in the synchronous logic circuit 1103 of
Referring to
It should be noted that the exemplary phase jumping applications described above, though described in terms of locked loop circuits that include phase jumping mixers according to the DRSS mixer embodiments described herein, may alternatively be implemented by locked loop circuits that include other types of mixing circuits. In general, any circuit of producing a relatively rapid phase transition in an output clock signal may be used in the above-described applications in place of the DRSS mixer embodiments described herein.
The section headings provided in this detailed description are for convenience of reference only, and in no way define, limit, construe or describe the scope or extent of such sections. Also, while the invention has been described with reference to specific exemplary embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, although specific circuits have been described and depicted as including metal oxide semiconductor (MOS) transistors, such circuits may alternatively be implemented using bipolar technology or any other technology in which a signal-controlled resistance may be achieved. Also, while CMOS and DRSS signaling levels have been described, any signaling levels having a substantially equal common mode voltage may alternatively be used. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
|Cited Patent
|Filing date
|Publication date
|Apr 15, 1992
|Apr 27, 1993
|Telesystems Slw Inc.
|Wireless local area network
|Feb 15, 1994
|Sep 10, 1996
|Rambus, Inc.
|Voltage controlled phase shifter with unlimited range
|Aug 21, 1995
|Mar 25, 1997
|Rambus, Inc.
|Delay-locked loop
|Jun 7, 1995
|Jun 3, 1997
|David Sarnoff Research Center, Inc.
|Dual chrominance signal processor for combined TV/VCR systems
|Oct 13, 1995
|Nov 4, 1997
|Credence Systems Corporation
|Compensated delay locked loop timing vernier
|Sep 14, 1995
|Mar 24, 1998
|Mitsubishi Denki Kabushiki Kaisha
|Voltage control type delay circuit and internal clock generation circuit using the same
|Aug 12, 1996
|Apr 21, 1998
|International Business Machines Corporation
|Compensation of chip to chip clock skew
|Feb 11, 1997
|Dec 22, 1998
|Micron Technology, Inc.
|Low-skew differential signal converter
|Oct 17, 1996
|Mar 9, 1999
|Samsung Electronics Co., Ltd.
|Signal de-skewing using programmable dual delay-locked loop
|Sep 26, 1996
|Mar 16, 1999
|Nec Corporation
|Clock signal generating device having a redundant configuration
|Aug 8, 1995
|Mar 30, 1999
|Siemens Aktiengesellschaft
|Generating circuit including selection between plural phase regulators
|Oct 10, 1996
|Apr 6, 1999
|Hewlett-Packard Company
|Memory system and device
|Feb 11, 1997
|Jul 6, 1999
|Micron Technology, Inc.
|Synchronous clock generator including delay-locked loop
|Feb 11, 1997
|Aug 17, 1999
|Micron Technology, Inc.
|Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
|Aug 29, 1997
|Aug 17, 1999
|Micorn Technology, Inc.
|Synchronous clock generator including a false lock detector
|Jul 31, 1997
|Aug 31, 1999
|Rambus Incorporated
|Circuitry for the delay adjustment of a clock signal
|Mar 5, 1997
|Aug 31, 1999
|Micron Technology, Inc.
|Delay-locked loop with binary-coupled capacitor
|Jul 9, 1998
|Oct 5, 1999
|Mitsubishi Denki Kabushiki Kaisha
|Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing
|Aug 20, 1997
|Jan 4, 2000
|Micron Technology, Inc.
|Synchronous clock generator including a compound delay-locked loop
|May 28, 1998
|Jan 18, 2000
|Micron Technology, Inc.
|Clock vernier adjustment
|Feb 10, 1999
|Feb 15, 2000
|Micron Technology, Inc.
|Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
|Mar 24, 1999
|Feb 15, 2000
|Micron Technology, Inc.
|Low skew differential receiver with disable feature
|Sep 9, 1998
|Feb 22, 2000
|Micron Technology, Inc.
|Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
|Apr 17, 1998
|Feb 22, 2000
|Micron Technology, Inc.
|Method and apparatus for generating multi-phase clock signals, and circuitry, memory devices, and computer systems using same
|Dec 8, 1998
|Feb 29, 2000
|Fujitsu Limited
|Semiconductor integrated circuit
|Sep 22, 1998
|Mar 28, 2000
|Intel Corporation
|Signal synchronization and frequency synthesis system configurable as PLL or DLL
|Feb 2, 1998
|Apr 4, 2000
|Rambus Inc.
|System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers
|Feb 19, 1999
|Jul 4, 2000
|Rambus Inc.
|Method of operating a memory device having a variable data output length and an identification register
|Sep 18, 1997
|Aug 8, 2000
|Micron Technology, Inc.
|Method and apparatus for adjusting the timing of signals over fine and coarse ranges
|Oct 30, 1998
|Aug 8, 2000
|Micron Technology, Inc.
|Apparatus for aligning clock and data signals received from a RAM
|Dec 23, 1997
|Aug 15, 2000
|Lucent Technologies Inc.
|Phase aligner system and method
|Oct 30, 1998
|Aug 22, 2000
|Micron Technology, Inc.
|Method for aligning clock and data signals received from a RAM
|Feb 6, 1997
|Sep 26, 2000
|Rambus, Inc.
|Delay-locked loop circuitry for clock delay adjustment
|Oct 10, 1997
|Oct 17, 2000
|Rambus Inc
|Variable delay element
|Jul 12, 1999
|Mar 6, 2001
|Nortel Networks Limited
|Voltage controlled oscillator power supply and temperature compensation circuit
|Sep 27, 1999
|Jul 3, 2001
|Conexant Systems, Inc.
|Phase lock loop used as up converter and for reducing phase noise of an output signal
|Jan 18, 2000
|Oct 16, 2001
|Samsung Electronics Co., Ltd.
|Delay locked looped circuits and methods of operation thereof
|Oct 19, 1999
|Nov 20, 2001
|Rambus Inc.
|Apparatus and method for topography dependent signaling
|Jan 5, 2001
|Apr 16, 2002
|Xilinx, Inc.
|Direct-measured DLL circuit and method
|Jul 13, 2001
|Aug 20, 2002
|Hitachi, Ltd.
|Clock generation circuit, control method of clock generation circuit, clock reproducing circuit, semiconductor memory device, and dynamic random access memory
|Aug 18, 2000
|Oct 22, 2002
|Rambus, Inc
|Apparatus and method for generating multiple clock signals from a single loop circuit
|Mar 1, 1999
|Oct 22, 2002
|Micron Technology, Inc.
|Method and apparatus for generating a phase dependent control signal
|Aug 3, 2001
|Nov 19, 2002
|Nec Corporation
|Digital phase control using first and second delay lines
|Sep 17, 2001
|Jan 7, 2003
|Rambus, Inc.
|Dual loop phase lock loops using dual voltage supply regulators
|Dec 29, 1999
|Jun 17, 2003
|Intel Corporation
|Generating a clock signal
|Feb 25, 2003
|Jul 6, 2004
|Rambus Inc.
|System with phase jumping locked loop circuit
|Oct 1, 2002
|Aug 31, 2004
|Nec Electronics Corporation
|Digital phase control using first and second delay lines
|Feb 23, 2001
|Dec 20, 2001
|Simon Thomas D.
|Symbol-based signaling device for an elctromagnetically-coupled bus system
|Oct 23, 2001
|Jul 4, 2002
|Samsung Electronics Co., Ltd.
|Delay locked loop for improving high frequency characteristics and yield
|Mar 27, 2002
|Oct 3, 2002
|Hiroshi Sonobe
|Semiconductor device
|Title not available
|Oct 12, 2000
|Apr 26, 2001
|Rambus Inc.
|Bus system optimization
|Jul 30, 2001
|Feb 7, 2002
|Rambus Inc.
|Apparatus and method for operating a master-slave system with a clock signal and a separate phase signal
|Bang-Sup Song and David C. Soo, "NRZ Timing Recovery Technique for Band-Limited Channels," IEEE Journal of Solid-State Circuits, vol. 32, No. 4, Apr. 1997, pp. 514-520.
|Description "Stefanos Sidiropoulos et al., ""Circuit Design for a 2.2GB/s Memory Interface, ""2001 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 70-71."
|Gu-Yeon Wei et al., "A Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation," IEEE Journal of Solid-State Circuits, vol. 35, No. 11, Nov. 2000, pp. 1600-1609.
|John G. Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.
|John Poulton, "Signaling in High-Performance Memory Systems," ISSCC, 1999, pp. 1-59.
|Citing Patent
|Filing date
|Publication date
|Apr 28, 2004
|Jun 6, 2006
|Cypress Semiconductor, Corp.
|Circuit and method to eliminate startup and shutoff runt pulses from crystal oscillators
|Jun 14, 2005
|Feb 19, 2008
|Micron Technology, Inc.
|DLL measure initialization circuit for high frequency operation
|Jun 16, 2006
|Jan 13, 2009
|Xilinx, Inc.
|Structures and methods for heterogeneous low power programmable logic device
|Dec 9, 2005
|Jan 19, 2010
|Rambus Inc.
|Transmitter with skew reduction
|Jul 16, 2007
|Feb 9, 2010
|Micrel, Inc.
|System and method for phase-locked loop (PLL) for high-speed memory interface (HSMI)
|Feb 28, 2007
|May 25, 2010
|Micron Technology, Inc.
|Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal
|Oct 9, 2008
|May 24, 2011
|Intersil Americas Inc.
|Waveform current monitor using RDSon of low-side bridge FET
|Jun 7, 2007
|Jan 10, 2012
|Qualcomm, Incorporated
|Circuit and method for dynamically selecting circuit elements
|Apr 23, 2010
|Dec 11, 2012
|Micron Technology, Inc.
|Phase-generation circuitry with duty-cycle correction and method for generating a multiphase signal
|Jan 3, 2013
|Feb 4, 2014
|Avnera Corporation
|Multiple output dynamic element matching algorithm with mismatch noise shaping for digital to analog converters
|Mar 11, 2013
|Dec 23, 2014
|Micron Technology, Inc.
|Apparatuses, methods, and circuits including a delay circuit
|Jun 18, 2013
|Feb 3, 2015
|Micron Technology, Inc.
|Apparatuses and methods for duty cycle adjustment
|Jul 8, 2013
|Nov 22, 2016
|Micron Technology, Inc.
|Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals
|Jan 21, 2015
|Jan 10, 2017
|Micron Technology, Inc.
|Apparatuses and methods for duty cycle adjustment
|Sep 3, 2014
|Jan 10, 2017
|Microsoft Technology Licensing, Llc
|Multi-phase clock generation
|Dec 19, 2014
|Feb 28, 2017
|Micron Technology, Inc.
|Apparatuses, methods, and circuits including a delay circuit
|Jun 14, 2005
|Dec 14, 2006
|Micron Technology, Inc.
|DLL measure initialization circuit for high frequency operation
|Dec 9, 2005
|Jun 14, 2007
|Elad Alon
|Four-wire signaling system
|Dec 9, 2005
|Jun 14, 2007
|Elad Alon
|Transmitter with skew reduction
|Dec 27, 2006
|Jul 3, 2008
|National Taiwan University
|Network on chip device and on-chip data transmission device
|Feb 28, 2007
|Aug 28, 2008
|Micron Technology, Inc
|Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal
|Jun 7, 2007
|Nov 6, 2008
|Qualcomm, Incorporated
|Circuit and method for dynamically selecting circuit elements
|Jul 16, 2007
|Jan 22, 2009
|Micrel, Inc.
|System and method for phase-locked loop (pll) for high-speed memory interface (hsmi)
|Oct 9, 2008
|Aug 20, 2009
|Intersil Americas Inc.
|Waveform current monitor using rdson of low-side bridge fet
|Apr 23, 2010
|Aug 12, 2010
|Feng Lin
|Phase-generation circuitry with duty-cycle correction and method for generating a multiphase signal
|Dec 19, 2014
|Apr 16, 2015
|Micron Technology, Inc.
|Apparatuses, methods, and circuits including a delay circuit
|Sep 3, 2014
|Mar 3, 2016
|Microsoft Corporation
|Multi-phase clock generation
|Apr 21, 2015
|Jun 16, 2016
|Micron Technology, Inc.
|Tracking and correction of timing signals
|U.S. Classification
|327/147, 327/158
|International Classification
|Cooperative Classification
|European Classification
|Feb 25, 2003
Owner name: RAMBUS INC., CALIFORNIA
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subset: commoncrawl


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The Kyoto protocol passed in 1997 and took force in 2005. 184 countries committed to it; the United States didn't ratify it.
The United Nations set up a system. Certified Emission Reduction credits were created. They are similar to a stock certificate, which can be bought and sold. Currently they sell for about $17. A refrigerant manufacturer in India reduces carbon emissions. A CER is created for each ton of carbon emissions it reduces. The same type of thing happens in China and other countries. A project is called a Clean Development Mechanism.
An electrical company in Scotland has purchased CER's. I don't know how many they purchased, but the cost will end up on their customer's bills.
The UN estimates that as many as 2.9 Billion CERs will be created by 2012.
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- Rose Angelique Alma Bb
Via Milanese 3 – Sesto San Giovanni – Milano
To get here by car
With the navigation system must be set as the destination address:
- "via Milanese 3, Sesto San Giovanni, Milano" corner"
- "via Caduti sul lavoro 1, Sesto San Giovanni, Milano"
Or calculate your route with Google Maps
To reach us by subway M5
It 'function in the new underground line M5 (line Lille), 300 meters from' Hotel BIGNAMI stop (ticket € 1.50 in).
Visit the ATM (Azienda Trasporti Milano) to calculate the route by public transport in Milan.
To get here by car from the airport
From the Airport: Milano Linate
From the Airport: Milano Malpensa
For further information: +39 02 241.121


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CMO Search, LLC is an executive search firm serving North American companies with sales of $10-250 million who are struggling with the question of "How do we bring world-class "direct-to-consumer" digital marketing DNA into our firm in a resource-friendly, brand-accretive, reality-based way?"
Ultimately, CMO Search's new job site, cmojobs.com, will serve as a one-stop-shop for high quality full-time job opportunities specific to VP/up consumer marketing Top Guns who are looking to take their careers to the next level.
This site is brand new. Some of our previous searches include …
- NEW – President, Specialty Autoparts Retailer (Mountain Timezone)
- CLOSED: ForeSee Results seeks CMO
- CLOSED: GENCO Marketplace seeks CEO (Pittsburgh, PA)
- CLOSED: US Electrical Services seeks a VP of Ecommerce (Middletown, CT 06457)
- CLOSED: NASB seeks a VP of Ecommerce (Kansas City, MO)
- CLOSED: CityPASS seeks a VP of Ecommerce (Victor, ID)
- CLOSED: Wolverine Worldwide seeks a VP Global Ecommerce (Grand Rapids, MI)


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Dr. Timothy D. Poppell is a native of Tallahassee, Florida, where he attended Florida State University, graduating with honors. His dental education was completed at University of Florida. While there he was inducted into OKU, a national dental honor society for academic achievement and leadership in dentistry.
He completed his orthodontic residency at the University of Florida in 1989 and established his practice in the DeBary area. Dr. Poppell is Board Certified, the highest and most difficult designation an orthodontist can receive. This status is achieved by only 25% of all orthodontists. He has also obtained Diplomate status from the American Board of Orthodontics.
He is trained in all aspects of orthodontic treatment and stays current through continuing education and affiliations with professional organizations and study clubs. He continues to be knowledgeable of the latest technological advances in orthodontics, affording him the ability to treat the most difficult cases.
Dr. Poppell is married to Maggie, who is also a dentist, and has a daughter, Kelly. When not straightening teeth, he enjoys playing golf and all outdoor activities.
Dr. Poppell's practice philosophy is to treat each and every patient with the best orthodontic treatment and personal service possible.


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It is important for you to choose right furniture that has long durability. By consider this thing; you do not spend much money to buy furniture again if it gets broken. Make sure that your kids are really like the furniture, because kids are usually easy to changing their tastes. When you are buying furniture for kids, it is not only about the function and design but also the safety for your kids. Make sure that all furniture you buy does not have sharp corners. Sharp corners are very danger to get injured when your kids falling down. Rounded shape corner is the best solution for kids furniture.
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I'm supposed to be reading a script and answering work emails, but I ended up picking up this old clip-art book I bought several years ago called Illustrations of Senior Citizens. E. Clams and I once made a giant stencil from one of the illustrations and used it to tag walls and streets in Boise, but I haven't done much with it since then. So I started a tumblr called Elder Thoughts (http://elderthoughts.tumblr.com), because that's the kind of thing people do when they want to do a stupid project .0001% of people might find interesting/funny/weird/offensive, and they wanna show it off.
It's funny pictures with writing. I will update it regularly, because there are a million more pictures. There are other interesting things I can say about how these illustrations are depicting the elderly as disembodied Cialis commercials, but I'll save that for another time.
Here's Elder Thoughts.


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|HOUSTON COUGARS (13-2 • 3-0 American)
at CINCINNATI BEARCATS (12-5 • 2-2 American)
|6 p.m. (CST) • Wednesday, Jan. 13, 2016
|Fifth Third Arena (13,176) • Cincinnati
|ESPNU • WatchESPN
Alex Faust, PxP
Brooke Weisbrod, analyst
|KPRC 950 AM • Listen Live
Matt Thomas, PxP
Pregame show starts at 5:45 p.m. (CST)
|Live Stats
|Series History
|Cincinnati leads 26-1
• Cincinnati won last 12
• Second straight season teams will play;
• Cincinnati won last 63-53
Feb. 21, 2015 (Hofheinz Pavilion)
Cincinnati leads 13-0 in Cincinnati
• Cincinnati won last 67-54
Jan. 21, 2015 (Cincinnati)
|Game Notes
|• Houston Notes
• Cincinnati Notes
• The American Notes
|Social Media
CINCINNATI –After a week-long break in its schedule, the University of Houston Men's Basketball program returns to action at 6 p.m. (CST) Wednesday, when it faces American Athletic Conference rival Cincinnati inside Fifth Third Arena.
Winners of their first three games to open American play, the Cougars have not played since taking a 63-45 win against Tulane on Jan. 5 inside Hofheinz Pavilion.
However, the Cougars are no stranger to the road this season. Houston opened American Athletic Conference play with wins at USF on Dec. 30 and at Temple on Jan. 2. It was the first time since 1946-47 that the Cougars opened conference play with a 2-0 record after back-to-back road games.
Houston leads the league with 81.5 points per game and has scored at least 75 points in 10 of 15 games this season. The Cougars are on pace to post the program's highest scoring average since the 1982-83 squad averaged 82.4 points per contest.
Sophomore guard Rob Gray, Jr., leads the Cougars and the American Athletic Conference with 18.6 points per game – two points higher than his closest competitor – and is one of four Cougars to average double-digit points. The Forest City, N.C., native is the only Cougar to reach double digits in every game in which he has played this season.
Senior forward Devonta Pollard stands second among the Cougars with 14.1 points per game and leads the Cougars with a 52.8 field goal percentage. Junior guard and Yates High product Damyean Dotson is third with 12.1 points per game but leads the team with 7.2 rebounds per game and four double-doubles in 2015-16.
Competing in his first season with the Cougars, junior point guard Ronnie Johnson stands fourth with 11.9 points per game and trails only freshman point guard Galen Robinson (3.7) for the team lead in assists with 3.2 per game.
Despite the impressive offensive numbers, the Cougars have been equally effective on the defensive side of the ball. Houston is allowing 66.7 points per game, which is the program's second-lowest mark since 2005-06.
The 45 points allowed against Tulane in the Cougars' most recent win was the fewest allowed in a conference game since a 63-43 win against Saint Louis on Feb. 2, 2005, and was the fewest overall since an 88-42 win over Grambling State in the 2011-12 season opener.
Fans can hear Wednesday's Men's Basketball game live on KPRC 950 AM with Matt Thomas calling the action and Hall of Famer Elvin Hayes providing analysis. The pregame show begins at 5:45 p.m. (CST), Wednesday.
Fans can hear the radio broadcast online by visiting UHCougars.com and following the appropriate links to Houston All-Access or by clicking here. A Houston All-Access subscription is required to listen to the game online.
The game will be shown on ESPNU with Alex Faust calling the play-by-play action and Brooke Weisbrod providing analysis. Fans can watch the game online by visiting WatchESPN or by clicking here.
Fans can follow live stats by visiting UHCougars.com and clicking the GameTracker link or by clicking here.
Cincinnati enters Wednesday's game with an 12-5 overall mark and 2-2 record in American Athletic Conference play. The Bearcats are tied for ninth in the league with Tulsa and have won two of their last three games.
In its last game, Cincinnati claimed a 54-51 win at USF on Sunday in Tampa, Fla. After battling to a 26-26 tie at halftime, Bearcats outscored USF by three in the final 20 minutes to earn the win.
Against the Bulls, junior guard Troy Caupain led Cincinnati with 14 points and four 3-pointers. Senior forwards Octavius Ellis and Shaq Thomas posted 10 points apiece with sophomore forward Gary Clark grabbing a game-high 11 rebounds.
This season, senior guard Farad Cobb leads Cincinnati with 12.1 points per game. Caupain ranks second on the team with 11.2 points per game and paces the team with 4.6 assists per game. Clark ranks third with 9.5 points per game but leads the Bearcats with 8.6 assists per contest.
Head Coach Mick Cronin is in his 10th year at Cincinnati and his 13th as a collegiate head coach. He has compiled a 197-123 record during his Cincinnati career after building a 69-24 record at Murray State (2003-06).
Cronin is 4-0 during his career against Houston.
Following Wednesday's game, the Cougars return to the friendly confines of Hofheinz Pavilion to play host to UConn at 1 p.m., Sunday, in a game presented by Maintenance Supply Headquarters
From there, Houston quickly hits the road again for a showdown at No. 10 SMU at 8 p.m., Tuesday, inside Moody Coliseum in Dallas.
Fans have a variety of ticket options to accommodate any budget. Season tickets, group tickets, single-game tickets and 3-Point Packs are on sale now. To purchase tickets or for complete information, fans can visit uhcougars.com/tickets and follow the appropriate links or click here.
Fans also can call 713-GO-COOGS (462-6647) or visit the Athletics Ticket Office from 10 a.m., to 5:30 p.m., Monday through Friday. To purchase tickets in person, fans can visit the Athletics Ticket Office located on the northeast corner of TDECU Stadium, just outside of Gate 1 off Cullen Boulevard. Parking is available in the TDECU Stadium parking garage with the first 30 minutes free of charge.
Current University of Houston students are admitted free to ALL Houston Men's Basketball game when presenting a valid ID at the doors.
Single-game tickets for Houston Men's Basketball's 2015-16 season begin at only $5 per game. Fans can purchase General Admission single-game tickets for only $5, while Reserved 2 seating is available for only $10 per game. Fans may buy Reserved 1 single-game tickets for $15 per ticket.
Fans can purchase single-game tickets by clicking here.
Fans can purchase tickets to any three remaining home games in the 3-Point Pack. Reserved 1 seating for the 3-Point Pack can be purchased for $40 with Reserved seating available for only $30.
Fans can purchase the 3-Point Pack by clicking here.
Tickets for groups of 10-24 or more can be purchased for as low as $12 per ticket in Reserved 2 for 18 regular-season home games inside Hofheinz Pavilion. Groups of more than 25 people can buy Reserved 2 tickets for only $10 per ticket
Groups of 10-24 can buy tickets for only $10 per ticket in Reserved 2 with prices plummeting to only $6 per ticket for groups of 25 or more.
Administrators can find more information about group tickets seating and pricing by clicking here.
Fans can receive the latest news and notes by following @UHCougarMBK on Twitter. Fans also can discuss the latest Houston Men's Basketball news and notes on the team's Facebook page by clicking LIKE at HoustonCougarMensHoops.


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South Florida's Top Culinary Event Celebrates its Tenth Year on Atlantic Avenue in Delray Beach!
One of the hallmarks of South Florida's high season is its most celebrated culinary event: Savor the Avenue. Savor the Avenue was launched ten years ago by Delray & Boca Magazines with Delray Beach's Downtown Development Authority. Guests can experience an epic al fresco dinner table seating hundreds of people who dine on a scrumptious multicourse dinner in the middle of Downtown Delray Beach. The elegant dining table now stretches for five blocks down the middle of picturesque Atlantic Avenue. It seats more than 1,100 people, and there are typically 15-18 participating restaurants. There is a friendly competition among restaurants to outdo one another when it comes to table decor - and prizes are awarded for the top three winners of this effort.
The event also benefits a local charity; this year a portion of all tickets sold will benefit the Delray Beach Public Library.
Reservations are required and must be made directly through the participating Delray Beach restaurants starting February 1st.
This year, in addition to the judging panel, there will also be a People's Choice Award granted to the restaurant with the best table décor. Be sure to vote for your favorite Savor the Avenue tablescape by uploading a picture of it to Facebook or Instagram, using #SavorPeoplesChoice and checking in to or tagging the restaurant name.
2018 Participating Restaurants*:
Racks Fish House & Oyster Bar & Farmhouse Kitchen
Schedule of Events
Greet, Toast & Dine:
5:30–6:15 p.m.: After checking in, enjoy a complimentary drink during the welcome reception provided by each participating restaurant. Locate your seats at Florida's longest dining table, and prepare to enjoy a beautiful night.
6 p.m.: Seating begins.
6:15 p.m.: Welcome comments, grand toast provided by Steve Weagle, Chief Meteorologist, WPTV
6:30–9 p.m.: Four-course dinner to be served with custom adult-beverage pairings.
7:30 p.m.: Table Decor Contest winner announced.
Attire: Downtown Delray Beach evening casual
Parking: Public parking lots and garage parking are available, as well as some valet locations. Atlantic Avenue will be closed during the event. Side streets will remain open for vehicle access. Visit DowntownDelrayBeach.com/parking for more parking information
2018 Savor the Avenue Charity Partner: to be announced
Presented by: Delray Beach Magazine, Boca Raton Magazine, Delray Beach Downtown Development Authority
Thank you to our 2017 sponsors: JM Lexus, 111 First Delray, Douglas Elliman Real Estate, Worthing Place, Atlas Party Rental, Delray Garden Center, and GRIMES Events & Party Tents
Congratulations to our 2017 Savor Table Decor Contest Winners:
1st Place Winner & People's Choice Winner - Salt7
2nd Place Winner - 50 Ocean
3rd Place Winner - Max's Harvest


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Saint-Luc University Hospital
1200 Brussels
Nearly 15,000 patients each year, men and women whatever the type of cancer from which they suffer, benefit from the support offered by the Mimi Ullens Foundation.
The beauticians of the Mimi Ullens Foundation provide care and offer advice designed to alleviate the ill-effects of treatment:
Everything is done to provide the patient with a direct feeling of physical well-being, some repose, and to relieve tension thanks to relaxation and massage techniques.
The Mimi Ullens Foundation offers specific support or longer-term help in order to ward off or treat the psychological repercussions of the disease. The aim is help them and those close to them to cope when the going gets hard. It must be remembered that in addition to sadness, worry and denial, there are very few people who don't also suffer from feelings of anxiety, blame, impotence or depression.
The Mimi Ullens Foundation also offers a range of hats and scarves to offset the loss of hair. Learning how to tie a scarf or a turban or choose a wig that goes with one's face – the Foundation's professional staff enable each patient to choose, in total privacy the solution that suits him or her best.
The Mimi Ullens Foundation creates Wellness Centres that are located within the oncology departments of its partner hospitals. It entirely renovates the premises in order to create an atmosphere of calm and warmth that is utterly different to that of a hospital. Spaces are entirely redecorated so that patients can feel they're at home, the aim being to help them refocus on their physical and mental well-being. The Foundation works with professionals who are specifically trained in caring for cancer patients. It operates in Belgium, France and Switzerland.
Hadi Waelkens
Gwenn Michielsen
Camille Reichling
Christine Delhorbe Marques
Alicia Duvernay
Oriane Augier
Nele Berckmans
Caroline Delvaux
Adriana Rios
Heidi Sebrechts
Alexandra Meert
Gwanaëlle Paye


text: To get from Marina di Ardea-Tor San Lorenzo a Siderno Superiore by train you can catch one of the 19 trains that everyday travel between Campo di Carne and Siderno, the closest station to the city. For your trip from Campo di Carne to Siderno by train you can choose to leave from one of Campo di Carne main stations: Campo di Carne, Roma Termini The trip by train from Campo di Carne to Siderno last on average 05:38 travelling with high-speed trains (Frecciarossa or Italotreno) If travelling with Trenitalia, you need to know the Campo di Carne to Siderno train schedule: the first train leaves at 06:20, while the last ride is at 22:50. A Campo di Carne to Siderno train cost about 39.90 €. But how long is the train ride from Campo di Carne to Siderno? Your journey takes about 8 hours on average. Trenitalia offers 3 direct trains between these two cities. If you need to travel this week, prices range from 44.90 € to 63.50€. Booking your train ticket a few weeks in advance though, you can find low cost trains from Campo di Carne to Siderno with fares starting from 29.90€, saving 40% on average.


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Thursday, February 19, 2009
The Drama of our Laptop
On our way to Red Knight Gardens in Davao City, where we rented two apartments for the whole family, Isabelle was sleeping in the taxi. It was 11 at night. As soon as the taxi stopped at the gate of our apartment, I said, "Honey, would you help Joy (my adopted sister) carry Izzy to our room? Be careful, so you won't wake her up." And he did. We were so worn-out from all of our activities that day and from Grace's Wedding Reception that Paul couldn't wait to hit the bed. I was still up talking to my siblings. After sleeping for 30 minutes, Paul got up and announced that he left the bag with my laptop in the taxi. We were shocked! We did all our best to recall the name of the taxi but we couldn't. It was very important that we recover that laptop because it's got our personal information that could be used by others on our behalf. Clif thought of the guard house in the entrance of the subdivision where Red Knight Gardens is located. Dan didn't waste time, he drove to the guard house and the security guard on duty gave him the name of the taxi and it's number. Later, he also gave the name of the taxi driver. The next hour was spent on making calls to the office of the taxi company, 911 and the police headquarters. The taxi company refused to give the contact info's of the said taxi driver for reasons he won't disclose. We were so desperate to get our laptop back before the one who got it open it and uses our credit card info's. We called our bank and requested to put our credit card on hold. Dan and Nemrod drove far to personally talk to the person on duty in the taxi company office that night but didn't get any more info's about the driver. When they got home, we were so hopeless! The impossibility to get our computer back just got more real. A month before our trip to the Philippines, Dan was telling me how people in the Philippines have become so desperate to survive in a very depressed economy that thieves and robbers were everywhere. He warned us to make extra effort to protect our moneys, credit cards, passports and other important belongings on our trip. In fact, a thief broke into my parents' house a few months ago. With that in mind, I was just very hopeless that our laptop would be recovered. We had the name of the taxi and the driver but to try to trace him could take weeks. That's just how system in the Philippines work. Our final effort was to gather in the living room and prayed. Every one, except the kids who were soundly sleeping, was praying. After lots of prayers and Paul promising to give all the cash he had that night to the driver if he came back with our lappy in the morning, we all slept like a baby. Around 5 am, my mom heard a hard knock on our gate. She got up and opened the gate and lo and behold, she saw a taxi driver with a bag in his hand. He came back with our laptop! Mama woke us all up to announce the great news! We got our lappy back! The driver said that he was driving home very far from where we were and found out about the bag. He said he couldn't sleep that night at home and that he felt really convicted to look for us and return the bag, so he drove back to us very early in the morning. Every one was full of joy! Paul gave him all the cash he had and the driver felt very appreciated for his integrity. What a story of God's faithfulness to answer our prayers! That's just the God we serve and love! And oh, when we left for Tandag, we left the power cord of that laptop somewhere in Davao. We couldn't trace where we left it and thought it was lost. We bought a new power cord for it. But when we went back to Red Knight Gardens, they said they had our power cord and gave it to us. We called them before to ask if they had it but they said, "no". It's crazy... but yes, that's the drama of our laptop! We cleaned that lappy and gave it to Dan.
Posted by Dines at 9:16 AM
Labels: Family, Philippine Trip 2009
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Wedding makeup is much less easy the way it looks which include. This is actually among the most difficult, not to mention demanding makeup, a makeup artist actually encounter. Learn how to create a perfect and beautiful bridal makeup with these helpful makeup tips.
If get to buy equipment for beauty salons submitting to directories thing will need do is make a shopping describe. If you are opening a new salon, make a wish list inventory from the items you'll need to open your facial salon. List them in order of most to least necessary. This particular you will help make sure to target on the must have items and also can opt for the items reduce on your list if you find an outstanding deal or maybe if you have extra money left on. If you are redesigning your salon or upgrading, create a subscriber base based on the oldest, most from date equipment to the lowest amount. Even if individuals need it, keep an authority list which can address it each and every time you look for.
As soon as the hair is dry, an unusually hot ceramic flat-iron is treated to straighten each tiny section of hair. Subsections should be about 1/8 of an inch. Method could have a lot of your time.
You ought send your invites well ahead from the wedding period. Since music is a great element of one's function, might hire an active band or DJ because of wedding party theme. Participate in the perfect song that suits your ceremony and atmosphere. As for your wedding makeup, do remember to book a hair and facial salon. Make bookings in advance for trial runs so that you have an insurance policy about the way you look on D-day. Make without doubt you don't panic and gaze after calmness.
If additionally you want something unique and innovative, ought to the Philadelphia hair stylists for those wedding. Choosing them in order to a fun process and you must feel better about yourself.
What are these duck down? Before anyone thought of putting them in their hair, fishermen used these feathers develop flies for fly doing some fishing. However, these days the only water these feathers are seeing are when their "owners" jump into Lake Minnetonka on a hot summer day!
Some days curly tresses are a dream, with soft, bouncy well-defined curls. On other days curly hair can seem like a nightmare with fly aways, frizzies and troubles. By using styling products made especially for curly hair and having a few hair do helpers like wide headbands and two sided clips on hand, naturally head of hair can nearly look effortlessly elegant regardless of whether you curly haired girls (and their Moms) know the truth.


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Lamar Institute of Technology football play by play
Think about what career is best suited for you, and where you want to study. Request more information now.
Think about what career is best suited for you, and where you want to study. Request more information now.
Think about what career is best suited for you, and where you want to study. Request more information now.
Info concerning Lamar Institute of Technology football play by play, and registering for elective lectures and seminars. Not all recruiting is done like NCAA Division I teams. College coaches at different division levels have different recruiting practices. Finally, check with your major department for assistance with prerequisites, tuition payment deadlines, and Lamar Institute of Technology Football information. Please use the form above to request admissions info for Lamar Institute of Technology.
You don't have to quarterback the university football team to a state championship to earn an athletic scholarship. Most major sports that field a team in intercollegiate competition have sports scholarships available. From women's gymnastics to men's track and field, coaches are seeking players to build a team around. Further, that leadership role often is accompanied by a full-scholarship.
The best time to begin searching for scholarships is before your senior year, in order to meet deadlines. Schools confirm that it is important to file financial aid forms such as the CSS Profile early in the school year. There are many sports scholarships that focus on less tangible qualities, such as the ability to lead a team, motivate others, and learn new skills rapidly. Take stock of your athletic abilities as you mature through high school. Students must meet specific eligibility requirements each year to participate in Minot State University baseball jerseys. Beyond consideration for Lamar Institute of Technology football play by play, you may think about Peninsula College AP credit for complementary electives to your primary course of study.
Assistant Fitness Manager
You will be responsible for overseeing a group of personal trainers at the club level and ensuring that our members expectations are exceeded.
1 day ago Texas Athletic Coaches (2017-2018)
Great Hearts Academies
Basketball and Soccer. Basketball, Track and Field, Tennis. ATHLETIC COACHES - Great Hearts Academies in Texas (2017-2018).
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4 hours ago Personal Training Sales Director
Youfit Health Clubs
Here at YouFit we structure our compensation to reward our employees for their dedication to revenue growth, team development, client retention as well as..
6 days ago Women's Soccer Head Coach - Part-time
Kern Community College District
This assignment will also require coaching at games/tournaments that are scheduled in the evening and/or Saturdays.
4 days ago