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Test cases involve the set of steps, conditions and inputs which can be used while performing the testing tasks. The main intent of this activity is to ensure whether the Software Passes or Fails in terms of its functionality and other aspects. The typical Test Case contains fieldsTest Case ID, Test Case Title, Summary, Pre-requisites, Execution Steps, Expected Results, Tester, Execution Date, Test Result (Pass/Fail), Build No., Comments, etc. A Test Plan outlines the strategy and approach that will be used to test an application, the resources that will be used, the test environment in which testing will be performed, the scope and limitations of the testing and the schedule of testing activities. Typically the Quality Assurance Team Lead will be responsible for writing a Test Plan. Hope it helps. Regards, Ronak Shah (http://www.techgig.com/QAExpert) Email: office: email@example.com Personal: firstname.lastname@example.com
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No answer posted to the question. Be the first to post a answer

subset: commoncrawl


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Hickories are trees in the genus Carya; they are related to walnuts and are valued both for their nuts and their strong, versatile hardwood. Hickory trees are divided into three groups: pignut, shagbark and pecan. All three groups are represented among the nine species of hickory native to Illinois.
Black Hickory
The black hickory (Carya texana) is also commonly called Texas hickory. It is hardy in U.S Department of Agriculture hardiness zones 5 to 8. It is most common west of the Mississippi River, but its native range extends through southern Illinois and as far east as Indiana. It is a relatively small tree, typically reaching a height of 25 to 50 feet, although in ideal conditions it can grow as tall as 100 feet. Black hickory is characterized by dark brown or black bark that develops fissures as the tree matures.
Pignut, Mockernut and Red Hickories
The pignut hickory (Carya glabra) is larger than the black hickory, often reaching 50 to 65 feet in height with a spread of 30 to 40 feet; large specimens can grow as tall as 120 feet. The red hickory (Carya ovalis) is very similar to the pignut hickory, and the two are sometimes considered a single species. The mockernut hickory (Carya tomentosa) is similar in size, and mature trees of both species have a coarse, oval-shaped canopy. Like the black hickory, these hickories have tight bark rather than the exfoliating bark of shagbark hickories. Pignut hickory is hardy in USDA zones 5 to 9, and mockernut hickory is hardy in USDA zones 4 to 9.
Shagbark and Shellbark Hickories
The shagbark hickory (Carya ovata) is a large tree, commonly reaching 100 feet in height with a 60-foot spread. It is easily identified by its bark, which in mature trees develops deep vertical fissures and peels away from the trunk in long strips. The shellbark hickory (Carya laciniosa) is smaller, reaching about 80 feet in height; it develops similar fissures in its bark, but the bark usually does not peel away the same way it does in shagbark trees. The shagbark hickory is hardy in USDA zones 4 to 8, and the shellbark is hardy in USDA zones 5 to 8.
Pecan Hickories
The pecan (Carya illinoensis) is the largest of the hickory trees, with a typical height of 70 to 100 feet and a spread of 75 feet; the trunks of large pecan trees can reach 6 feet in diameter. The related water hickory (Carya aquatica) is slightly smaller, and the bitternut hickory (Carya cordiformis), another pecan hickory, is smaller still, reaching only about 80 feet in height. The pecan is hardy in USDA zones 5b through 9a, the bitternut hickory in USDA zones 3 through 7, and water hickories in USDA zones 4 to 9.
Related Searches
- University of Illinois Extension: Illinois Forest Facts
- Illinois State Museum: Black Hickory
- Forrest Keeling: Carya texana
- USDA Forest Service: Carya glabra
- North Carolina State University: Carya tomentosa
- Ohio DNR: Shagbark Hickory
- Ohio DNR: Shellbark Hickory
- USDA Forest Service: Carya illinoensis
- Ohio DNR: Bitternut Hickory
- Texas A&M University: Water Hickory
- Photo Credit Comstock/Comstock/Getty Images


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Happy Diwali Sms 2016 in Hindi, Punjabi, English: Are you searching for the new advance happy diwali sms collection in different language such as hindi, punjabi and english then we are glad that you are on the right place. Here you will read about happy Diwali sms 2016 in hindi, happy diwali sms 2016 in punjabi, happy diwali sms 2016 in english and even more for sharing on social media such as facebook, twitter and google plus also. All the below happy diwali sms collection of 2016 were taken from different web sources, if you really like and you want us to more happy diwali 2016 sms collection then do let us know via comments below.
Finally from our team we would like to wish you a very happy diwali 30 Octuber 2016 festival to all of you, may god bless you all with lots of happiness in your peaceful family. Thus enjoy our collection of, Happy Diwali 2016 Sms in Hindi, Punjabi, English.
Happy Diwali Sms 2016 in Hindi 140 Words
Guys below we have "Happy Diwali Sms in Hindi", all the below wishes were free so feel free to share with your friends and love on social media like fb & whatsapp. Download them all and don't forget to party all night with your love ones.
- चारो और दिया और मोमबत्ती जलाओ,
अपने घर को खूबसूरती से सजाओ,
आज की रात फटाके जलाओ,
ये दिवाली को एक अलग अंदाज से मनाओ.
हैप्पी दिवाली.
- अँधेरा हुवा हे देर रात के साथ,
नयी सुबह आई हे दिवाली लेके साथ,
अब आँखे खोल दो और देखो मैसेज आये हे,
और दिवाली की सुभकामना साथ लाया हे.
हैप्पी दिवाली.
- Asha, Utsah aur Ullas ki Abha se Damakti
Amavas ko Poonam me Badalti,
Deepon ki Muskurahat aur Athkheliyon ka]
Yah Parv Apke-Apke Apno ke,
Jeevan me Hamesha Jagmagati Rahe,
Bankar SHUBH DEEPAWALI.
- Aai aai Diwali aai, Saath me kitni Khushiya laayi, Dhoom machao, mauz manao, aap sabhi ko Diwali ki badhai. Happy Diwali !
- Diwali aai, masti chahi, rangi rangoli, deep jalaye, Dhoom Dhadaka, chhoda phataka, jali Phuljadiyan, Sabko Bhaye, "Happy Diwali !"
2016 Happy Diwali Wishes in Punjabi, Hindi, Englis
Happy Diwali Sms 2016 in Punjabi Language, Font
Don't forget to share the below "Happy Diwali Sms in Punjabi", if love to speak punjabi with your friends then you also going to love our collection for sure. The below happy Diwali sms 2016 in punjabi is specially dedicated to all the guys from Punjab state, enjoy. Now pick up your mobile and start sending happy Diwali sms 2016 to your friends, bf, gf, love, crush, ex, teachers, boss and etc.
- Diwali diyaan lakh lakh vadayian hon sare desh vasiyan nu. Rab sab diyan murada nu pura kare. Jai maa lakshami.
- Din khushiyan da aaj aya
Dewaya naaal veda jagmagya
Bachya ne aaj bumb chalya
Chacha khush cahachi vi khus
Aaj khush hoi sadi tayi
Is vaar diwali di tahnu sarye nu wadai bai wadai
- ਜਗਦੇ ਰਹਿਣ ਖੁਸ਼ੀਆਂ ਦੇ ਦੀਵੇ, ਮਿਲਦੀਆਂ ਰਹਿਣ ਵਧਾਈਆਂ….!
ਪ੍ਰਮਾਤਮਾ ਕਰੇ ਇਹ ਦਵਾਲੀ ਦਾ ਇਹ ਤਿਉਹਾਰ ਤੁਹਾਡੇ ਸਭ ਦੀ ਜਿੰਦਗੀ ਵਿੱਚ ਖੁਸ਼ੀਆਂ
ਤੇ ਚਾਨਣ ਲੈ ਕੇ ਆਵੇ।ਤੁਹਾਨੂੰ ਸਭ ਨੂੰ ਦੀਵਾਲੀ ਦੀਆਂ ਬਹੁਤ ਬਹੁਤ ਵਧਾਈਆਂ।
- Je gharwali na hundi ta ghar na chalda,
Je diwali na hundi ta diva na balda,
je patakha na hunda ta dhuan na urda,HAPPY DIWALI
- Main jithe jithe javan tuhada chehra dikhda hai
Par is wich tuhada koi kusur nahi
Kyunki aj sab chehre khushi naal iko jehe lag rahe hanHappy DIWALI…!!
- Khushiyan lake aayi diwali
cham cham kare diviyan di thali
Barfi jalebi te rasgulla main kha layi mithayian di thali
dekho dekho aayi diwali
Happy Diwali
Happy Diwali 2016 Quotes in Hindi
100 Happy Diwali Quotes
Happy Diwali 2016 Sms in English
For those who are searching for cute or romantic "Happy Diwali Sms in English", here we have the collection for you all. You surely going to love them all and guys don't forget to wish your friends form the below happy diwali 2016 sms in english.
- With Gleam of Diyas,
And the Echo of the Chants,
May Happiness and Contentment Fill Your life !
Wishing you a very happy and prosperous Diwali !!!
- I Pray to God to give U Shanti, Shakti, Sampati, Swarup, Saiyam, Saadgi, Safalta, Samridhi, Sanskar, Swaasth, Sanmaan, Saraswati, aur SNEH. SHUBH DIWALI.
- Troubles as light as Air, Love as deep as the Ocean,
Friends as Solid as Diamonds, Success as bright as Gold…
These are the wishes for you and your family on the eve of Diwali.
Diwali ki Shubhkamana!
- Fortunate is the one who has learned to Admire, but not to envy.
Good Wishes for a joyous Diwali and a Happy New Year with a plenty of Peace and Prosperity.
- Three people were asking for your mobile no. We didn't give ur no.
But we gave them ur home address. They are coming this Diwali.
They are : SUKH,SHANTI and SAMRIDDHI.
Please welcome them as we have requested them to stay with you forever.
Happy Diwali Quotes 2016 In Punjabi
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Happy Diwali Sms in Hindi ,Punjabi, English


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Learn how to ditch jQuery and write vanilla JavaScript
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This publication examines the U.S. structure via concentrating on its origins in Western political suggestion and its association and next amendments. It describes the record as a sequence of selections between replacement governmental associations which are designed to supply nationwide defense and safe ordered liberty.
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This App Can Help You Plan an Excellent Bachelor Party
Whether you are about to get married or are the best man for your friend's wedding, you might need a little help planning the ever-important bachelor party. The Complete Bachelor Party Planner and To Do List app can help you organize every aspect of the party for a night to remember.
One of the first things you'll need help with in planning a bachelor party is deciding where you should go! This app will give you recommendations for places in your area to host a bachelor party, and even has reviews so you can get an idea of which place is best. Use the built-in features to keep track of how much the party will cost and to send out emails to all of your guests.
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Waihirere Trust Wetland Restoration
The Waihirere Trust Wetland is located on Richard & Roharia Murray's farm. Richard and Roharia were very keen to restore their wetland as it not only restores, protects and enhances the biodiversity but also because of the many advantages listed above. This wetland is a large freshwater wetland (approx 13 ha) which also contains a diverse range of avi-fauna, vertebrates, invertebrates species including nationally-threatened species.
The biodiversity values of this wetland have been threatened by stock intrusion, soil erosion, nutrient run-off and has been suffocated by pest weeds, mainly willow and gorse. The Willow has formed large dense 'forests' in the wetland, but it has a good native understorey of mainly Carex grass species, coprosmas and a little manuka. The Matakana Island Environment Group helped form partnerships between the Trust and Nga Whenua Rahui Nga Whenua Rahui is a Maori organisation whose role is to offer Maori landowners a way of conserving their lands while still retaining ownership and control of their whenua. They give advice and offer funding options for the conservation and restoration of privately owned Maori land. and Environment Bay of Plenty. Environment Bay of Plenty - Our work guides and supports the sustainable development of the Bay of Plenty.
In 2008 the Trust signed up to an Environmental Program with EBOP and a Nga Whenua Rahui kawenata to get the restoration project underway. Matakana Island Environment Group then organised and implemented the restoration project.
Waihirere Wetland Unimproved/media/waihirere_images/waihirere-01.jpg
Waihirere wetland infested with Willow & cows!!
Waihirere Wetland Clean-Up/media/waihirere_images/waihirere-02.jpg
Wetland being cleaned-up and fenced
Planting Begins/media/waihirere_images/waihirere-03.jpg
Ted & Michelle start the planting
First Plantings Take Hold/media/waihirere_images/waihirere-04.jpg
First plantings at Waihirere wetland
Natives just planted/media/waihirere_images/waihirere-05.jpg
Natives just planted
Surveying the Work/media/waihirere_images/waihirere-06.jpg
Farmer Richard Murray surveying the work!!
Natives 6 Months On/media/waihirere_images/waihirere-07.jpg
Natives 6 months after being planted
2yrs after planting - 1/media/waihirere_images/waihirere-08.jpg
2yrs after planting - Willows are dying!
2yrs after planting - 2/media/waihirere_images/waihirere-09.jpg
2yrs after planting - looking good!
2yrs after planting - 3/media/waihirere_images/waihirere-10.jpg
2yrs after planting - looking good!
2yrs after planting - 4/media/waihirere_images/waihirere-11.jpg
2yrs after planting - looking good!
2yrs after planting - 5/media/waihirere_images/waihirere-12.jpg
2yrs after planting - looking good!


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This is an absolute gem of a place in an idyllic setting with views to die for. We came here for a 1-night getaway from home and loved it. Our room was just so cosy and comfortable- attractive linen, cushions, lovely bathroom, lots of welcoming touches including a small caraffe of sherry, homemade biscuits.... We wished we'd stayed longer- but this place does get booked up fast! Absolutely wonderful breakfast- we had it at 9.30 and couldn't eat lunch till after 3! Spent the day walking along the whitecliffs park and samphire hoe before getting stuck on the M2 to get back home in the evening. Absolutely wonderful day!
- Official Description (provided by the hotel):
- Alkham Court offers award winning luxury farmhouse accommodation overlooking the scenic Alkham Valley with stunning views at Breakfast and glorious sunsets in the evening. Guests have complimentary use of the hot tub and sauna to relax and totally unwind during your stay. Our four guest rooms offer luxury ensuite rooms with kingsize beds and their own individual entrances. Our beautiful location in the Kent countryside gives you a unique and special stay. We are immensely proud to be recognised by Trip Advisor's Excellence Award and their Hall of Fame for 2015/16. ... more less
- Also Known As:
- Alkham Court Farmhouse Dover, England, UK


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The pirate site plans to ignore the lawsuits from Elsevier and the American Chemical Society.
The Caterpillar that Cries Wolf
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The once fringe idea is gaining traction among the scientific community.


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- Artist
- Period Active
30 Nov 0002 JAPAN
- Type
Female Solo
- Genre
K-POP > R&B/Hiphop
- Debut
30 Nov 0002
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So… Blogging…
Greetings and welcome to my hobby blog.
I've been around tabletop wargames for most of my life – for both the dice rolling and the hobby side of things. I always seem to have some sort of conversion project on the go and figured a blog would be a good way of documenting my progress… I've been meaning to start one for a while now, so as I'm sitting here waiting for some glue to dry, I figured I'd get it started!
So… Uh… Here, have a Boarboss:
Bit of a preview of my WIP Snakebites Warboss. More to follow.


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FedEx Corporation, FDX is in the exchange NYSE and its industry is Air Delivery & Freight Services in the sector of Services. Based in USA, FedEx Corporation, FDX has a market cap of 45999.9. Since its IPO date on the 4/12/1978, FedEx Corporation, FDX performance year to date is 16.90%. Today FedEx Corporation, FDX has gained -0.05%, with a current price of 173.01.
Ownership of the company is 6.00% for insider ownership while institutional ownership is 75.60%. The management of the company have seen the company have a payout ratio of 19.20%. Return of assets are at 4.40%, with return on investment at 7.80%.
In terms of debt levels and profit levels, FedEx Corporation, FDX is seeing a long-term debt/equity of 0.97. While Total debt/equity is 0.97. With a profit margin of 3.50%, this is combined with a gross margin of 70.90%, and operating margin of 6.10%. FedEx Corporation ability to meet debt levels, with a current ratio of 1.5, while the quick ratio is 1.5.
For the last year FedEx Corporation, FDX has seen a EPS growth of 78.40%. A performance for the year of 12.16%. The 52-week high is -2.45%, and the 52-week low is 45.49%. The average volume for FedEx Corporation, FDX is 1257400.
With a target price of 187.55, can FedEx Corporation, FDX reach this target? Looking at the value indicators of FedEx Corporation, FDX. FedEx Corporation has a P/E of 25.7 and a forward P/E of 12.71. Perhaps the more useful indicator than P/E, is PEG which has a value of 2.37. FedEx Corporation also has a P/S and a P/B of 0.87 and 3.24 respectively. For P/cash, FedEx Corporation has a value of 15.39, while it is 157.53 for P/free cash flow.
At the current price of 173.01, FedEx Corporation has a dividend yield of 0.92%. We see a return on equity of 12.90%.
Looking more long-term FedEx Corporation, is projected to get an EPS growth for the next five years of 10.83%. In the short-term an EPS growth of 12.12% in the next year is forecasted. This is after a EPS growth of 78.40% for this year and for the last five years a 7.30% growth has been seen.


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Separate names with a comma.
Discussion in 'Archived Threads 2001-2004' started by David Giesbrecht, Aug 16, 2001.
Can you use standard insulation as damping for your sub, if so are their any disadvantages.
I wouldn't use the stuff in a vented sub, due to the fibers being sent through the port and into the air. No one needs their sub to make them itchy.
For a sealed sub, I guess it'd be okay, but still not my first choice (pillow polyfill is good enough, and available at places like JoAnn's, Wal-Mart, etc).
PatCave; HT Pix; Gear; DIY Mains; DIY CC; Sunosub I + II + III; DVDs; LDs
I've wondered about that myself, but it appears that SVS is using standard insulation from a picture I saw a while back. I know Chris Artman used it in his Black Hole subs.
I also thought I heard somewhere that the fibers can be damaging to the speaker driver itself, but I don't know what the issues were exactly.
FWIW, in the good old days before the current crop of sub drivers became available, huge cabs (15+ft) were required to get 20Hz performance, and I lined them all either with R-19 fiberglass with the paper backing removed, or the backless version used to line large air ducts.
After reading Pat's response, it made me curious enough to remove the cloth cover on a reflex vent that's been in place since I built it back in '69, and can't see any obvious FG particle residue.
That said, if you use FG to stuff a reflex (which I don't recommend), it can literally be blown out the vent so a cloth cover is mandatory IMO. Or you can do as many have done with Aperiodic designs which is to hang a 'blanket' of FG from the top of the cab.
WRT damaging the driver, I've loosely stapled a 'blanket' directly over the back of many drivers to lower their Q with no damage AFAIK. Indeed, this was the published standard for the final 'critically damping' of a reflex in the past.
For smaller cab volumes where lining the walls with FG tend to overdamp them, I use 1/2" felt carpet padding.
If handling it is a major issue for you, there's always Miraflex, which seems to work just as well, and in some cases more so since it's rated R-25.
Loud is beautiful, if it's clean


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People who like food will like Buckminster's…because they make very good food.
For instance, Chicken Liver Mouse…
A warm squid salad.
The flavor you're trying to place as you eat that? It's szechuan peppercorn. You're welcome.
And this is just the beginning.
We ate the crispy chicken with buttermilk, watercress and fried onion before a picture could be taken. I wanted to eat five more orders of it. You will too.
Overall, the food at Buckminster's is great. The cocktails were nice. The service was on point.
Go to Buckminster's.


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Bladder Cancer Awareness Walk – Hanover
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# yellow helps
# If you see red, get checked.
For More Information:
http://www.bccwalk.ca ~ to register to walk
(866) 674-8889


text:
Rachel Rayye Bounces That Blinman
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At all times take care of family in these four photos, Karen gave head to my original commission and they are still somewhat slim because the highs that this drug is horrible.
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World. associate the correct emoji representations of male and female.
Bounces Rachel Rayye Blinman That wonder Tobias needs
Thread a private message to the doctor with any mobile devices.


text:
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The Hawks are back to putting pucks in the net, and say what you will about their defensive positioning concerns, their production 5-on-5 is good enough for the top spot in the league. 2 goals from Montador, 2 from Toews, and a variety of other players with 2 points on the night put the Hawks above the Oilers 6-3. And all of this against a team who has rarely allowed any goals at all this year.
Before the game even started we were aware of Bolland's continued loss, and the 4th continuous start by big John Scott. Scott was not an issue for this one, but you still have to wonder what is going on behind the scenes to create this situation. O'Donnell and Lepisto are obviously more earning of the ice-time, but I digress. Seabrook might be joining Bolland on the sideline, after taking a big spill behind the net and leaving the game with a lower body injury. Not exactly promising for the upcoming trip.
The Hawks jumped out of the gate in this one and it all started with the explosive Toews' line. It would seem that Hossa is the consistent variable in offensive explosion this year. It took about 5 minutes for the Oilers to get anything going with the Hawks swarming all over, creating good pressure and executing a strong forecheck. A strong drive to the net by Hall for the Oilers almost ended in a goal and it was the first real opportunity for Edmonton. This early drive almost changed the movement of the game, but Crawford stood tall and the Hawks were able to be the first to score.
Stalberg played the puck deep into the zone, picked it up along the boards and set Toews up behind the net. Toews did everything right and shelved a hard wrister over Khabi's shoulder. Moments later, Montador saved a goal at the other end, the Hawks cleared the zone, went the length of the ice where Kane hit Montador with a great pass as he was entering the zone and he scored a remarkable and large goal for this game.
The Oilers were never able to catchup from here, although they sure had their chances. Crawford had to be huge more than a few times. Edmonton never sat back, scoring 3 goals in the game, but it was nothing compared to the offense produced by the Hawks. The Hawks had moments of standing still in their own zone again which was part of the cause for the first Oilers goal, a weak one from behind the net. This issue just won't go away. Thankfully, the Hawks like to score goals right now.
The Hawks weathered the storms and eventually got a power-play. Edmonton was seemingly stealing the momentum in the game, when the Toews line drew a penalty which lead to a power-play goal. It started off with Sharp on the point which I still question, and eventually saw 3 defensemen on the ice (again, questionable behavior going from 1 defenseman to 3 on the ice). Again, we saw the random sampling group of guys on the PP and it produced a goal. Leddy fired a great shot to the net where Montador was standing and was able to change the direction of the puck. Great to see the PP produce and it is looking better all around, but it is that odd grouping that chooses to do it.
A 3-1 lead was pretty darn promising, and it would essentially be enough for the Hawks. Crawford would have to continue to make good saves, the PK had some wins and a loss, but the game was eventually put away after Kane made a very unselfish play hitting Carcillo with a pass to score the empty netter. Maybe some payback for his physical protection during the early weeks.
Lets get to some points on the night:
- Halfway through the game I was starting to ask myself about what the present play of Kane was showing. Not seeing the constant offensive pressure lately, I was wondering if he had taken a step back (maybe an injury?). Just as the thought crossed my mind, Kane took the puck through 3 Oilers, splitting the D and getting a mini breakaway. This was a wow moment, and when coupled with the 2 assists on the night, especially on the empty net goal, it is safe to say we will continue to see fireworks from this guy.
- Leddy was maybe the player of the game in so many ways. With the one Oilers PP goal as an exception when his laziness caused a goal, he was stellar at times, consistent on others, digging all night long and paced at the most minutes logged by any player during the game. Leddy is not just the poor-man's Campbell, he is the better version if you ask me. At only 20 years old, he is much more aggressive, has so much room to grow and is already a pillar on this team. Leddy had a few wow moments tonight.
- Keith is another guy looking darn strong right now. What a relief to see the Dunc of the old days back in action. It looks as though the largely debated defensive pairings were exactly what we saw of them, mistakes. Hjalmer is looking better as well, playing with Leddy and building a balanced pairing.
- I want to give credit to Kruger here as well. I have seen great gains in his play, especially since Bolland's injury. I might argue that Mayers is better qualified to step up, or Bringing Pirri in might not have been a bad idea, but Kruger is looking the best he ever has at the moment. Nice to see.
- Crawford might have heard some of the talk, however small, asserting himself as a goalie to rely in. It is a shame that the shotty defensive play still being exhibited by the Hawks is keeping Crow from better numbers, but his play is where it counts.
- Worth noting is that the Hawks never sat back into defensive mode after taking insurance leads a few times in the game. The Hawks play better when trying to score, so I applaud the move to keep forcing the issue, but they need to get better at protecting nonetheless.
- As mentioned, this new Toews line is pretty explosive. Toews mentioned in an interview after the game that he and Stals have been talking about the many opportunities they produce together, and then having Hossa on the line only helps matters. If Stalberg stays on this line and learns a thing or two from Toews (the give and goes kind of thing), he will continue to grow and this line could be even more dangerous by the end of the regular season.
- What do we make of Montador at this point? He has had some huge downs and some pretty big ups. He is obviously fairly versatile playing forward and D, makes mistakes often, has aggression at times, but is just inconsistent. I will just leave it at that for now.
- The Backcheck and Forecheck was damn impressive tonight.
- Again, we saw a promising 3rd period. The Hawks came out, continued to put pressure on the Oilers and pretty much subdued them until the empty net goal.
This win jumps the Hawks to 25 points and the league lead. The Hawks had a strong 35 shots and held Edmonton to only 25, but most importantly they had 24 hits which is a high number for this team. As noted, with the exception of the defensive positioning and movement in their own zone, this was a very strong game against a team which has been playing strong hockey at the beginning of this season. A good, well deserved win.
Vancouver is coming up. Time for some retribution. This game is a huge opportunity for the Hawks to establish the recent fall as being just a minor glitch in an otherwise strong start. It is also big in setting the tone for the 6 game road-trip coming up. This is the real test in my opinion and I will choose to hold out on real assessment of this team's character until after Thanksgiving.
Filed under: Game Recap
Tags: Chicago Blackhawks, Edmonton Oilers, Jonathan Toews, Nick Leddy, Steve Montador


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text:
Three Charts That Show Markets Aren't Betting on GOP Border TaxBy
House plan would incentivize exports, hurt importers
Oil spreads, retail stocks, Irish debt suggest lower odds
As executives of major retail chains voice their displeasure over a Republican proposal to tax U.S. businesses' domestic income and imports while exempting their exports, financial markets are saying don't worry about it.
U.S. President Donald Trump's stance on the plan, known as a border adjustment tax or BAT, is unclear -- first, he deemed it "too complicated," but then reportedly warmed to it as a potential way to help pay for a border wall with Mexico.
He told chief executives who had come to lobby against the border adjustment, including those from Target Corp. , J.C. Penney Co. and Gap Inc. , on Wednesday that a tax overhaul plan was coming soon without mentioning the Republican tax.
If media attention is any indication, interest in the border adjustment tax is starting to roll over as found in Bloomberg's tool for finding news trends.
But with a dearth of details from D.C., what are financial markets saying about the likelihood of a border adjustment tax?
Here are three charts that suggest traders don't seem overly confident this part of the plan will be implemented in full.
The BAT, if implemented without a carve-out for the energy industry, would incentivize oil production in the U.S. versus the rest of the world and would be conducive to a narrowing in the spread between same-dated West Texas Intermediate and Brent futures contracts.
But after shrinking significantly in the aftermath of the election, the gap between contracts that expire in December 2017 has been trending wider since Jan. 11, as the above chart shows.
Retailers could be in for big-league damage relative to other sectors in the event of a border tax, because in most cases the majority of their sales are imported goods.
The SPDR Retail exchange-traded fund had been getting crushed since early December, vastly lagging the S&P 500 index. But it's been outperforming since Feb. 7 -- right about when the Trump's flare up with Nordstrom Inc. began.
Irish bonds aren't behaving like there's an imminent U.S. policy change that could cause a structural shock to its economy and financial markets.
"Border adjusted cash flow tax complex, but seems clearly bad for Ireland - U.S. [intellectual property] companies can come home and face no tax on export profits," tweeted Brad Setser, senior fellow at the Council on Foreign Relations. "Pharma may not produce active ingredients in Ireland, Apple doesn't need its Irish [subsidiary], etc."
Indeed, the spread between the yield on Irish 10-year debt and its German counterpart has come in over the past two weeks.


text:
I have been going through a very deep depression lately and have been feeling like I really don't measure up at work, at home or in my family. My self esteem was so low, I chose to cut myself to deal with the constant pain. I was like everyone else who is a cutter. I was not choosing suicide. I just wanted the pain to stop.
I came across your poem accidentally while doing a search. I almost exited out of it, but God told me to just read through it once. Just once. So I did. I almost cried. I guess I knew I meant a lot to God, but I never thought of myself as a princess. This poem caused me to realize that I am important and I do mean something to someone.
Thank you so much for writing this poem. I am slowly coming out of the depression. It might take a while, but I will fight. I will fight to find the peace I now know I deserve.
May God richly bless you and I hope others will find comfort in this poem.
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|Publication number
|Publication type
|Application number
|Publication date
|Nov 22, 2011
|Filing date
|Nov 30, 2009
|Priority date
|Sep 30, 2003
|Fee status
|Also published as
|Publication number
|Suan Jeung Boon, Yong Poo Chia, Meow Koon Eng, Siu Waf Low
|Original Assignee
|Micron Technology, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (115), Non-Patent Citations (3), Referenced by (7), Classifications (41), Legal Events (4)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a continuation of U.S. patent application Ser. No. 11/215,472, filed Aug. 29, 2005, now U.S. Pat. No. 7,633,159, issued Dec. 15, 2009, which application is a divisional of U.S. patent application Ser. No. 10/717,421, filed Nov. 19, 2003, now U.S. Pat. No. 7,208,335, issued Apr. 24, 2007. The disclosure of the previously referenced patent applications referenced is hereby incorporated by reference in its entirety. The subject matter of this application is also related to U.S. patent application Ser. No. 11/430,376 filed May 8, 2006, now abandoned; U.S. patent application Ser. No. 10/440,590, filed May 19, 2003, now U.S. Pat. No. 7,226,809, issued Jun. 5, 2007; U.S. patent application Ser. No. 10/183,820, filed Apr. 27, 2004, now U.S. Pat. No. 6,727,116, issued Apr. 27, 2004; U.S. patent application Ser. No. 11/430,375, filed May 8, 2006, now U.S. Pat. No. 7,285,850, issued Oct. 23, 2007; U.S. patent application Ser. No. 10/736,244 filed Dec. 15, 2003, now U.S. Pat. No. 7,115,984, issued Oct. 3, 2006; U.S. patent application Ser. No. 10/197,986, filed Jul. 17, 2002, now U.S. Pat. No. 6,818,977, issued Nov. 16, 2004; and U.S. patent application Ser. No. 10/990,348, filed Nov. 16, 2004, now abandoned.
1. Field of the Invention
The present invention relates generally to chip-scale packages and, more specifically, to chip-scale packages which include contact pads on both major surfaces thereof, as well as to methods for forming the chip-scale packages. In particular, the present invention relates to chip-scale packages that include castellated contact pads, which include surfaces, or sections, that are exposed at the outer peripheries of such packages, as well as sections that are exposed at both major surfaces of the packages.
2. Background of Related Art
Conventional semiconductor device packages are typically multi-layered structures. A conventional semiconductor device package may include, for example, a bottom layer of encapsulant material, a carrier, a semiconductor die, and a top layer of encapsulant material. In addition to being located above and beneath the semiconductor die and carrier, the encapsulant material of a conventional semiconductor device package also laterally surrounds the semiconductor device and the carrier. In addition, a conventional semiconductor device package includes input/output elements to facilitate electrical connection of the semiconductor device thereof with external electronic components.
Leads are an example of conventional input/output elements. Leads typically contribute to the dimensions of the footprint of a conventional semiconductor device package and, thus, consume an undesirably large amount of real estate upon a carrier substrate (e.g., a circuit board) to which the semiconductor device package is to be secured and electrically connected.
Other examples of such input/output elements include pins, solder balls or other discrete conductive structures (e.g., bumps, balls, columns, etc.), which contribute to the height of a conventional semiconductor device package. When coupled with the thicknesses that conventional encapsulants and carriers impart to the overall thickness of a conventional semiconductor device package, the added heights of such discrete conductive structures may result in a semiconductor device package which will protrude an undesirably large distance from a carrier substrate to which it is secured and electrically connected.
In order to keep up with the trend toward ever-decreasing the dimensions of electronic devices, various technologies have been developed to decrease the dimensions of packaged semiconductor devices. The result of many of these technologies is the so-called "chip-scale package" (CSP), a packaged semiconductor device with lateral dimensions that are roughly the same as (i.e., slightly larger than) the corresponding lateral dimensions of the semiconductor dice thereof.
Due to the relatively small, semiconductor die-dependent, lateral dimensions of CSPs, they are often formed at the so-called "wafer-scale," meaning that packaging occurs prior to severing the semiconductor devices from a wafer or other large-scale substrate. Packaging semiconductor devices at the wafer-scale avoids the difficulties that may otherwise be associated with handling such small components during chip-scale packaging thereof. Such wafer-scale packaging may include the formation of a redistribution layer (RDL), which may rearrange or effectively expand the connection pattern of bond pads on the active surface of the semiconductor device to a redistributed connection pattern, which is more suitable for connection to a carrier substrate. Alternatively, one or more interposers may be secured over the active surfaces of the semiconductor devices that are carried by a wafer or other large-scale substrate and electrically connected to such semiconductor devices to redistribute the connection patterns thereof.
Once the connection patterns of the semiconductor devices have been redistributed and either before or after the formation of a protective layer over the RDL or interposer, discrete conductive elements, such as balls, bumps, columns, or pins, may be secured to the redistributed bond pads of each CSP. These discrete conductive structures are typically arranged over the major surface in a so-called "grid array" connection pattern.
As a consequence of the use of such discrete conductive structures, chip-scale package technology typically requires inversion of the CSP face-down over a carrier substrate therefor and alignment of the discrete conductive structures of the CSP with corresponding contacts (e.g., the terminals of a circuit board). Electrical connection of a semiconductor device to a carrier substrate in this manner is referred to in the art as "flip-chip" connection or "controlled-collapse chip connection" (C4). Of course, when the discrete conductive structures comprise pins, the electrical connection technique is referred to as a "pin connection."
When flip-chip or pin connection techniques are employed, the discrete conductive elements typically space the semiconductor device apart from the carrier substrate. This space may remain open or be filled with a so-called "underfill" material. Such spacing of a semiconductor device apart from a carrier substrate may therefore impart the assembly with an undesirably high profile.
Moreover, these types of chip-scale packaging technologies typically do not permit the placement of a chip-scale package on a carrier substrate in a face-up orientation.
Accordingly, there is a need for a packaging technology which results in chip-scale packages that may be secured to carrier substrates without requiring a significant amount of spacing between the chip-scale packages and the carrier substrate and that may be electrically connected to a carrier substrate in a face-up orientation.
The present invention includes a chip-scale package with bond pads, or contact pads, that are positioned around the outer periphery thereof. Additionally, the contact pads may extend onto one or both major surfaces of the chip-scale package.
An exemplary embodiment of a chip-scale package that incorporates teachings of the present invention includes a semiconductor device, a redistribution layer formed over an active surface of the semiconductor device and in electrical isolation therefrom, and contact pads with sections that are positioned adjacent to and in electrical isolation from the outer periphery of the semiconductor device and which communicate with corresponding bond pads of the semiconductor device through the redistribution layer. One or more of the contact pads may also include an upper or lower section, which is located adjacent to and may be substantially coplanar with a respective active surface or back side of the semiconductor device.
The semiconductor device of such a chip-scale package may comprise a memory device or a processing device, or a sensor or display device. If a sensor or display device is included in a chip-scale package of the present invention, at least a sensing or emission area on the active surface thereof may be covered with an optically transparent lid.
The present invention also includes methods for forming chip-scale packages that include contact pads on the outer peripheries thereof. These methods may be effected at a wafer-scale.
As an example, a wafer or other large-scale substrate carrying a plurality of semiconductor devices, which is referred to herein as a "semiconductor substrate," may be secured to a sacrificial, or "dummy," substrate. The sacrificial substrate may include lower contact pad sections, which are referred to herein as "lower sections" for simplicity, or precursors thereto, which are referred to herein as "precursor pads." These lower sections or precursor pads are positioned so as to align with corresponding semiconductor devices when the semiconductor substrate is secured to the sacrificial substrate.
Insulative and redistribution layers are formed over the semiconductor devices by use of known processes. The results are circuit traces that communicate with bond pads and extend from the bond pads toward or to the outer periphery of the semiconductor device. If the contact pads of the chip-scale package under fabrication are to include upper sections, which are positioned adjacent to the active surface of the semiconductor device, the upper sections may also be formed during the fabrication of the redistribution layer, with at least some of the circuit traces extending to corresponding upper sections. The insulative and redistribution layers may be formed either before or after the semiconductor substrate is secured to the sacrificial substrate.
Once the insulative and redistribution layers have been formed and the semiconductor substrate has been secured to the sacrificial substrate, the semiconductor devices are at least partially severed from one another. If the sacrificial substrate includes lower sections of contact pads, such severing may expose portions (e.g., edges or a surface) of the lower sections. If the sacrificial substrate includes precursor pads thereon, such severing may sever the precursor pads or expose a surface thereof.
Next, the exposed, outer peripheral edges of the semiconductor devices are coated with an electrically insulative material. Such coating may be followed by a second cut. The result is a peripheral dielectric coating on each peripheral edge of each semiconductor device. At this point in the packaging process, the semiconductor devices that are carried by the semiconductor substrate are substantially separated from one another and are held in place relative to one another by way of the sacrificial substrate. In addition, the outer edges of any lower sections of contact pads are exposed.
Each peripheral dielectric coating is subsequently coated with a layer of conductive material. The conductive material is then patterned to form the peripherally located contact pads or peripheral sections thereof. Of course, if the contact pads of the chip-scale package include upper or lower sections, such patterning is effected such that the peripheral section of each contact pad communicates with its corresponding upper or lower section.
Thereafter, the sacrificial substrate is removed from the semiconductor substrate, with any lower sections of contact pads remaining in place. As the sacrificial substrate is removed, the chip-scale packages that have been formed are fully separated from one another.
If the semiconductor devices that are to be packaged comprise sensor or emission devices, the packaging process may differ somewhat. In particular, in other embodiments of the method of the present invention, the sensing or emission areas on the active surfaces of such semiconductor devices are protected prior to both the singulation of the semiconductor devices from one another and the introduction of dielectric material between adjacent semiconductor devices. In addition, an optically transparent lid is placed over each sensing or emission area following the formation of a redistribution layer, but prior to cutting into the dielectric material between adjacent semiconductor devices to form the peripheral dielectric coatings on the peripheral edges of the semiconductor devices. Finally, a sacrificial layer is formed over the optically transparent lids and above other locations of the semiconductor devices but not on the peripheral dielectric coatings prior to the formation of a conductive layer over these structures. As such, conductive material may be removed from desired locations, such as the optically transparent lids and other locations over the active surfaces of the semiconductor devices, by known "lift-off" techniques, while remaining on the peripheral dielectric coatings.
Of course, semiconductor device assemblies and electronic devices which include such chip-scale packages, as well as methods for forming such assemblies and electronic devices, are also within the scope of the present invention.
Other features and advantages of the present invention will become apparent to those of ordinary skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.
In the drawings, which depict exemplary embodiments of various aspects of the present invention:
With reference to
Semiconductor device 12 includes bond pads 16 on active surface 13 thereof. Bond pads 16 are arranged substantially linearly along a centerline 17 of semiconductor device 12, although semiconductor devices with other bond pad arrangements, or "footprints," may also be used in chip-scale packages that incorporate teachings of the present invention.
By way of example only, semiconductor device 12 may comprise a memory device, such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a programmable memory (PROM), an electrically erasable programmable memory (EEPROM), or the like. As another example, semiconductor device 12 may comprise a so-called "microprocessor" or "microcontroller."
A dielectric layer 18 is disposed on active surface 13 of semiconductor device 12 to protect the same and to electrically isolate active surface 13 from circuitry of redistribution layer 20. By way of example only, dielectric layer 18 may be configured to prevent electrical interference between signals transmitted along the integrated circuitry (not shown) of semiconductor device 12 and those transmitted along the circuitry of redistribution layer 20. Also, dielectric layer 18 may be configured to prevent alpha particles, which are known to cause dissipation of stored charges within memory cells, from penetrating therethrough to the memory cells, if any, of the underlying semiconductor device 12. Of course, the material from which dielectric layer 18 is formed, as well as the thickness thereof, may contribute to the characteristics thereof. Materials that are suitable for use as dielectric layer 18 include, but are not limited to polyimides, silicon oxides, silicon nitrides, silicon oxynitrides, and the like. Dielectric layer 18 includes apertures 19 formed therethrough, through which bond pads 16 of semiconductor device 12 are exposed.
Redistribution layer 20 includes a plurality of circuits 22. Each circuit 22 communicates with a corresponding bond pad 16 of semiconductor device 12 and extends laterally to and communicates with a corresponding contact pad 30, adjacent to outer periphery 15 of semiconductor device 12.
Additionally, chip-scale package 10 may include a protective layer 40 over redistribution layer 20. Like dielectric layer 18, protective layer 40 comprises a material which is electrically insulative and which may prevent alpha particles from penetrating through to the underlying semiconductor device 12.
Turning now to
Each conductive material layer or sublayer may be formed by known processes, such as by one or more of physical vapor deposition (PVD) (e.g., sputtering), chemical vapor deposition (CVD), electrolytic plating, electroless plating, immersion plating, or the like. Depending upon the deposition technique(s) that is (are) used, as well as the order of deposition processes, one or more sublayers of each precursor pad 36′ may be patterned, as known in the art (e.g., by use of mask and etch processes). For example, if a lowermost sublayer of conductive material is formed by PVD or CVD processes, that sublayer may be patterned prior to the formation of additional sublayers of conductive material thereover by electrolytic, electroless, or immersion plating processes. As another example, if multiple sublayers of conductive material are formed by PVD or CVD processes, patterning may be effected to form precursor pads 36′ after all of the sublayers have been formed or following each set of consecutive PVD or CVD processes.
In the depicted example, a centerline 37 through each precursor pad 36′ is aligned between adjacent semiconductor devices 12 a and 12 b carried by semiconductor substrate 11 (i.e., with a scribe line S, or "street," thereof). Accordingly, half 36 a′ of precursor pad 36′ will be located beneath and positioned adjacent to an outer periphery 15 a of a first semiconductor device 12 a, while the other half 36 b′ of precursor pad 36′ will be positioned beneath and adjacent to an outer periphery 15 b of an adjacent semiconductor device 12 b.
Alternatively, as shown in
As depicted in
Semiconductor substrate 11 and sacrificial substrate 50 may be secured to one another, as known in the art. A bonding agent 54 may be used to bond back side 14′ of semiconductor substrate 11 to surface 52 of sacrificial substrate 50. Accordingly, bonding agent 54 may be applied to back side 14′, to surface 52, or to both back side 14′ and surface 52. By way of example only, known spin-on, spray-on, screen printing, and other application techniques may be used to apply bonding agent 54.
Bonding agent 54 may comprise an electrically insulative material. Thus, bonding agent 54 may subsequently form a dielectric layer on back side 14 of semiconductor device 12 of the resulting chip-scale package 10, as well as electrically isolate precursor pads 36′ from back side 14 of each semiconductor device 12. Additionally, it is currently preferred that the adhesive material which is employed comprise a material that will apply little or no stress to semiconductor substrate 11 and sacrificial substrate 50, or a "low stress" material, thereby reducing the likelihood that either semiconductor substrate 11 or sacrificial substrate 50 will be damaged as chip-scale packages 10 are being formed. For example, and not to limit the scope of the present invention, bonding agent 54 may comprise an adhesive material. The material of bonding agent 54 may be stable at elevated temperatures, under reduced pressures (e.g., in a vacuum), when exposed to chemical environments, or other conditions to which bonding agent 54 will be exposed during downstream processes (e.g., fabrication of redistribution layers (RDLs)). Also, bonding agent 54 may comprise a material that will not outgas at any temperature, particularly the temperatures to which it will be exposed during fabrication of chip-scale packages 10 and operation of semiconductor devices 12 thereof. Exemplary materials that may be used as bonding agent 54 include, without limitation, any type of curable adhesive material that meets the specifications required for packaging semiconductor device components, such as thermoset adhesive materials, polyimides, and the like.
Once semiconductor substrate 11 and sacrificial substrate 50 have been bonded to one another and bonding agent 54 has sufficiently cured, adjacent semiconductor devices 12 a, 12 b are partially separated from one another, or singulated, along a street or scribe line S (
Subsequently, as shown in
With reference to
As shown in
Next, with reference to
Once redistribution layer 20 has been formed, a protective layer 40 may be formed over redistribution layer 20 of each semiconductor device 12 a, 12 b, as shown in
Still referring to
With reference to
When fabrication of the elements of each chip-scale package 10 has been completed, adjacent chip-scale packages 10 a, 10 b, etc., may be separated, or singulated, from one another by known processes. As shown, semiconductor substrate 11 has already been severed to partially physically separate adjacent semiconductor devices 12 a and 12 b from one another. Accordingly, semiconductor devices 12 a and 12 b may be completely separated from one another and lower sections 36 of contact pads 30 exposed by removing sacrificial substrate 50 (
Another exemplary embodiment of chip-scale package 110 that incorporates teachings of the present invention is depicted in
Accordingly, semiconductor device 112 includes a sensing/emission area 170 which is exposed to an active surface 113 thereof. Additionally, to protect sensing/emission area 170, chip-scale package 110 includes an optically transparent lid 172 over at least a portion of sensing/emission area or region 170. Semiconductor device 112 also includes bond pads 116 on active surface 113 thereof, positioned between sensing/emission area 170 and outer peripheral edge 115 (also referred to as "outer periphery 115").
Chip-scale package 110 further includes a redistribution layer 120 over active surface 113 of semiconductor device 112, as well as contact pads 130 that extend from redistribution layer 120, around the outer peripheral edge 115 of semiconductor device 112, and onto a back side 114 of semiconductor device 112. Accordingly, each contact pad 130 includes an upper section 132, a peripheral section 134, and a lower section 136 (see
A dielectric layer 118 is disposed on active surface 113 of semiconductor device 112, laterally adjacent to optically transparent lid 172, to protect active surface 113 and to prevent electrical interference, or "crosstalk," between integrated circuitry of semiconductor device 112 and circuits 122 of redistribution layer 120. Dielectric layer 118 may also be configured to prevent alpha particles from penetrating therethrough to any memory cells or other charge-retaining areas of the underlying semiconductor device 112. Of course, the material from which dielectric layer 118 is formed, as well as the thickness thereof, may contribute to the characteristics thereof. Materials that are suitable for use as dielectric layer 118 include, but are not limited to polyimides, silicon oxides, silicon nitrides, silicon oxynitrides, and the like. Bond pads 116 of semiconductor device 112 are exposed through dielectric layer 118 by way of apertures 119 formed therethrough.
Redistribution layer 120 includes upper sections 132 of contact pads 130. Redistribution layer 120 may also include a plurality of circuits 122 that extend from bond pads 116 to upper sections 132 of corresponding contact pads 130.
Chip-scale package 110 may also include a protective layer (not shown) over redistribution layer 120. The protective layer comprises a material which is electrically insulative and which may prevent alpha particles from penetrating through to the underlying semiconductor device 112.
As illustrated in
With reference to
Temporary protective layer 180 may be formed by applying a layer of photoresist to active surface 113 (e.g., by spin-on processes, use of a doctor blade, screen printing, etc.), then exposing and developing selected regions of the layer of photoresist. Of course, other materials (e.g., other photoimageable or nonphotoimageable polymers) and corresponding, suitable processes (e.g., spin-on processes for photoimageable materials, or screen printing for nonphotoimageable materials) may also be employed to form temporary protective layers 180 over sensing/emission areas 170 of semiconductor devices 112.
Also in
Once semiconductor substrate 111 and sacrificial substrate 50 have been secured to one another, adjacent semiconductor devices 112 are partially separated from one another, or singulated, along a street or scribe line S therebetween, as depicted in
With reference to
As shown in
Next, a conductive layer 162 is formed over dielectric layer 118′ and in apertures 119. Like conductive layer 62 (
Referring now to
Once conductive layer 162 has been patterned, temporary protective layers 180 and regions of dielectric layer 118′ that remain thereover may be removed to expose the underlying sensing/emission area 170, as shown in
Next, as shown in
As an alternative to securing a single optically transparent lid 172′ over semiconductor substrate 111, a plurality of individual optically transparent lids 172 may be positioned over sensing/emission area 170 of each semiconductor device 112 and secured to semiconductor device 112 with an optical grade adhesive 174, as known in the art and as depicted in
Referring now to
Cut lines 158 are formed by a technique (e.g., with a wafer saw, by laser ablation, by etching processes, etc.) which is suitable for removing the material of dielectric layer 118′ and, if a single optically transparent lid 172′ has been employed, for removing the material of optically transparent lid 172′. Of course, if a single optically transparent lid 172′ is present on semiconductor substrate 111 before cut lines 158 are formed, the formation of cut lines 158 results in the severing of optically transparent lid 172′ into a plurality of individual optically transparent lids 172, with one optically transparent lid 172 being located over each semiconductor device 112 a, 112 b.
When upper precursor pads 132′ or precursor pads 136′ are present, the technique for forming cut lines 158 should also be suitable for removing the material of such precursor pads 132′, 136′. Of course, when precursor pads 132′ or 136′ are severed during the formation of a cut line 158, they are bisected or otherwise split into upper sections 132 a, 132 b (collectively, upper sections 132) or lower sections 136 a, 136 b (collectively, lower sections 136) that are located on active surface 113 or back side 114 of adjacent semiconductor devices 112 a, 112 b, respectively, with peripheral edges 133, 137 being formed at each edge of that cut line 158.
As shown, each cut line 158 extends at least to surface 52 of sacrificial substrate 50.
Alternatively, an uncured polymer which is not photoimageable may be used to form layer 163′. Such a material may be applied over selected regions of semiconductor devices 112 (e.g., on optically transparent lids 172 thereof, but not within cut lines 158), such as by use of screen printing techniques, selective deposition processes (e.g., by use of a two-dimensional, ink jet-type printer), or the like. The material may then be permitted to harden (in the case of thermoplastic materials) or cure, or caused to cure (e.g., by exposure to heat, pressure, radiation of an appropriate wavelength, a chemical catalyst, etc.), as known in the art, to form sacrificial layer 163.
Once sacrificial layer 163 has been formed, a conductive layer 164 may be formed thereover. Like conductive layer 162 (
As depicted, conductive layer 164 overlies semiconductor devices 112 (being located over optically transparent lids 172 that are disposed thereover), as well as lines peripheral dielectric coatings 160, which form the lateral surfaces of each cut line 158. Additionally, peripheral edges 133 of upper sections 132 of contact pads 130 (
With reference to
With continuing reference to
One or more layers of UBM or BLM may be formed, as known in the art (e.g., by electrolytic, electroless, or immersion plating techniques) on exposed portions of each contact pad 130 (e.g., peripheral section 134). Such UBM or BLM will prevent contact pads 130 from oxidizing and facilitate adhesion of intermediate conductive elements, such as bond wires, solder bumps, or the like, thereto.
When fabrication of the elements of each chip-scale package 110 has been completed, as shown in
Turning now to
A plurality of chip-scale packages 110″ may be formed by repeating the processes that have been described with reference to
Following the formation of bevel cut 176, as shown in
Thereafter, as
Next, as depicted in
Turning now to
Alternatively, as shown in
Another alternative, which is shown in
Similar electrical connections may be made between chip-scale packages that incorporate teachings of the present invention and other types of carriers or electronic components, as well as between multiple inventive chip-scale packages.
Although the foregoing description contains many specifics, these should not be construed as limiting the scope of the present invention, but merely as providing illustrations of some of the presently preferred embodiments. Similarly, other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention. Moreover, features from different embodiments of the invention may be employed in combination. The scope of the invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions, and modifications to the invention, as disclosed herein, which fall within the meaning and scope of the claims are to be embraced thereby.
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|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|May 6, 2015
|Fee payment
Year of fee payment: 4
|May 12, 2016
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
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Effective date: 20160426
|Jun 2, 2016
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001
Effective date: 20160426
|Jun 8, 2017
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001
Effective date: 20160426


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