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Being Pope comes with a few nice perks: Popemobile, a sweet ring, and a personal choir.
Some Interesting Facts About the Choir:
- While the choir's official name is The Sistine Chapel Choir, everyone knows them as The Pope's Choir, because they sing at all important Papal celebrations.
- They are the oldest choir in the world dating back to the 7th Century!
- They weren't always as good as they are now. In fact, they used to be called the "Sistine Screamers."
- The choir is currently made up fo 30 boys and 22 men.
- Most of the music they perform was written by Palestrina who wrote it specifically for this choir and the Sistine Chapel, in which they most frequently perform.
- The choir puts in three hours of practice every day.
- Conductor Massimo Palombella was born on Christmas.
- Over 700 boys audition every year, only about a dozen at most make it.
- Boys in the choir are awarded a 5-year scholarship to a special school in Rome.
- The choir's 2015 album – Cantante Domino (featured in the playlist below) was the first recording ever allowed in the Sistine Chapel.
- Boys must leave the choir when they reach puberty and their voice breaks, though they may return later as adults.
- There are no records of boy singers in the choir between 1441 and 1903 – high parts were sung either by men who used their falsetto or by those who were castrated (consequently, their voices never broke).
- Due to his objections to human castration, Pope Pius X released a letter in 1903 stating only "whole men" could be in the choir or clergy.
The Pope's Choir is pretty great. We put two of their newest albums in the playlist below. We've found their music perfect for concentrating and getting work done as well as relaxing.
60 Minutes produced a piece about The Pope's Choir, and it was so well received by producers and viewers, that it became the only story 60 minutes has ever run two weeks in a row. Click here to watch.
The Pope's Choir | 60 Minutes
Sistine Chapel Choir | Wikipedia
Photo: UK in Holy See via Flickr


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Author: clwilson2006
Characters/Pairing: Lorne/Parrish (Pre-Slash/One sided musings!)
Rating: NC-17
Word Count: 220ish
Beta by: None, Sorry.
Warnings/Notes: Written for stargateland Anywhere but Here Challenge. Someone's internal thoughts in a tedious/terrible situation. I admit I was at a loss with this one until calcitrix posted this art. So thanks calcitrix for the inspiration!
Disclaimer: Not mine, never have been, never will be.
Summary: Lorne is bored. When Lorne is bored, his mind wanders.
Anywhere But Here at my Journal
Title: Things I Need to Stop Doing.
Author: clwilson2006
Characters/Pairing: Lorne/Parrish
Rating: NC-17
Word Count: 330ish
Beta by: camshaft22, thank you darling!
Warnings/Notes: So I wrote Anywhere But Here this afternoon for a stargateland challenge. somehowunbroken poked the muse and I got this. An extension/continuation of Anywhere but Here and submitted for Day One at mmom.
Disclaimer: Not mine, never have been, never will be.
Summary: Lorne really needs to stop thinking about David Parrish.
Things I Need to Stop Doing at my journal.

subset: commoncrawl


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Football receiving votes in first regular season poll
Sep 16th, 2013 @ 4:25 pm | Author: Mark Potts, Sports Information Director
The Valley City State football team is just outside the Top 25 in the first regular season NAIA Top 25 Coaches' Poll released on Monday.
VCSU is rated No. 26 after receiving 17 poll points. The Vikings are 2-1 to start the season, with wins over Dakota State and Jamestown College, and a loss to No. 1 Morningside College. VCSU was also receiving votes in the preseason poll.
Morningside remains No. 1 in the first regular season poll after posting a 2-0 record. Saint Francis (Ind.) is No. 2, followed by Cumberlands (Ky.), Carroll (Mont.) and Saint Xavier (Ill.) to round out the Top 5.
Valley City State is in action again Saturday, Sept. 21, when they host Trinity Bible College at 6 p.m.


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July 9, 2014 - Products
Phillips Industries has expanded their rubber air hose product line. Now available are both pre-fabricated and bulk rubber air hoses in blue and red to denote emergency and service lines.
Phillips' recently introduced 3-IN-1 and 4-IN-1 combination assemblies will also now incorporate the new color coded air hoses in place of the previous black air hoses in the groupings.
The blue and red prefabricated air hoses are outfitted on the tractor end with swivel fittings for easy installation, spring guard for strain release, and large color-coded handle grips for easy coupling and uncoupling. All Phillips air hoses provide excellent abrasion resistance, resist cracking, kinking and weathering and are SAE J1402 compliant, the company claims.
Go directly to this company's home page
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On the Spot: The Mack Trucks Anthem Launch [Video]
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Eberspaecher to Exhibit Aftertreatment Systems at NACV


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Davis-Monthan AFB, AZ - New Parent Support Program
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Davis-Monthan Family Advocacy is located at 5427 E Madera Street, Tucson, AZ 85707. Davis-Monthan Family Advocacy can be reached by their main phone number at (520) 228-2104. The listed DSN line is 312-228-2104. You may also request contact by clicking here.
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Protected Research Time
A minimum of 60% protected time must be guaranteed by each MTPCI scholar's department. Surgeons may only be allowed 50% protected research time.
Some small tuition assistance grants covering part of one or two classes may be available for the required, graduate-level coursework. The application cycle for these grants typically opens in fall.
Participation in the Clinical Research Training Center (CRTC) MTPCI may count toward the requirements of the NIH Loan Repayment Program (LRP).
Clinical Research Training Center (CRTC)
MTPCI scholars have access to the Clinical Research Training Center. The CRTC provides computer labs, break-out rooms, a classroom, poster printing, and administrative office suites.


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Music Examples:
Cantatas BWV 1-224
| Other Vocal BWV 225-524, 1081-1127
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Cantata BWV 145
Mvt. / Music Example
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Complete Cantata [m3u]
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Complete Cantata [ram]
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Mvt. 3: Duet [S, A] | Mvt. 5: Aria [B]
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Will G. Stoner
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The Associated Press
Judge could open priest abuse docs
ALBUQUERQUE — A New Mexico judge is reviewing three binders filled with years-old documents on three former Catholic priests accused of sexually abusing children to decide what records should and shouldn't be released to the public.
Judge Alan Malott said Friday there is good cause to open sealed records, but that he will review them "with an eye toward what is appropriate for public disclosure."
Submitted to the Optic
Las Vegas is home to many unique and historic buildings, including Our Lady of Sorrows Catholic Church, whose present site dates back to 1852. But it's what's inside the church that has gained national attention: the church's historic 1885 Kilgen mechanical tracker pipe organ.
Trump to phase out DACA
President Donald Trump will phase out a program that has protected hundreds of thousands of young immigrants brought into the country illegally as children. He will call for Congress to find a legislative solution to protect the immigrants, who are often called "Dreamers."
By Norman Merchant and Will Weissert
The Associated Press
HOUSTON — The U.S. government carefully designed a path of least resistance to building a border wall in Texas, picking a wildlife refuge and other places it already owns or controls to quickly begin construction. All it needed was Congress to approve the money.
Then came Harvey.
SANTA FE — Today through Nov. 7, , The Prudential Spirit of Community Awards is looking for New Mexico's top youth volunteers of the year.
Students in grades 5-12 are invited to apply for 2018 Prudential Spirit of Community Awards if they have made meaningful contributions to their communities through volunteer service within the past 12 months.
The application is available at http://spirit.prudential.com and www.nassp.org/spirit.
Isolated showers and thunderstorms after noon. Mostly sunny, with a high near 79. South wind 10 to 15 mph. Chance of precipitation is 20 percent.
6:37 a.m. to 7:20 p.m.
A 20 percent chance of showers and thunderstorms. Partly sunny, with a high near 80. South wind around 10 mph becoming west in the afternoon.
6:38 a.m. to 7:19 p.m.
New Mexico Highlands University is seeking comments from the public about the university in preparation for its periodic evaluation by its regional accrediting agency.
The university will host a visit Nov. 6 to Nov. 8, with a team representing the Higher Learning Commission. Highlands University has been accredited by the HLC since 1926. The team will review the institution's ongoing ability to meet the HLC's criteria for accreditation.
Preserving Las Vegas history is the shared job of public and private organizations, including the nonprofit MainStreet de Las Vegas.
By Jason W. Brooks
Las Vegas Optic Editor
A San José man, who is identified in court documents as a Pecos Schools custodian, is in the San Miguel County Detention Center on more than 30 sex-abuse charges, including criminal sexual penetration of a minor.
Louis Ivan Vigil, 45, of San José, was booked into jail Friday on eight counts of criminal sexual penetration of a minor younger than 13. He also faces 14 counts of second-degree criminal sexual contact of a minor and 11 counts of contributing to the delinquency of a minor.
Copyright © 2017
The Las Vegas Optic is your source for local news, sports, events, and information in San Miguel County and Las Vegas, NM, and the surrounding area.


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- E: email@example.com
- South Farm Lane, Langton Green, Tunbridge Wells, Kent TN3 9JN
Crestala Trellis Fencing panels are very versatile and have many uses around the garden including, screening, as part of a fence, framing for climbing plants, enclosing features such as pergolas or eyesores like dustbin areas. For those who would like a little more screening, we have Diamond Privacy Trellis panels.
All CrestalaTrellis is made using treated batten 19mm x 38mm.
Other non-standard Trellis sizes, different batten spacings, diamond pattern Trellis or any special orders can be produced in our workshop to meet your requirements.
Width: 3m
0.30m £24.67£17.40
0.45m £------£20.32
0.60m £35.62£23.25
0.75m £------£28.16
0.90m £46.55£31.49
1.05m £------£35.10
1.20m £57.18£38.95
1.50m £68.11£45.60
1.80m £79.06£52.06
0.30m £23.34£16.43
0.45m £------£19.19
0.60m £33.41£21.95
0.75m £------£26.27
0.90m £43.16£29.44
1.05m £------£32.76
1.20m £52.92£36.17
1.50m £62.99£39.72
1.80m £73.06£48.38
0.30m £22.22£15.56
0.45m £------£18.12
0.60m £31.21£20.68
0.75m £------£24.36
0.90m £39.78£27.53
1.05m £------£30.70
1.20m £48.67£32.95
1.50m £57.86£38.71
1.80m £67.07£44.28
Width: 2.1m
0.30m £20.71£14.80
0.45m £------£16.99
0.60m £28.93£19.18
0.75m £------£22.60
0.90m £37.98£25.76
1.05m £------£28.49
1.20m £44.98£30.74
1.50m £52.88£36.06
1.80m £60.80£40.61
Width: 3m
0.30m £34.30
0.60m £44.75
0.90m £59.23
1.20m £75.48
1.50m £84.12
1.80m £95.28
0.30m £32.46
0.60m £42.24
0.90m £54.54
1.20m £66.14
1.50m £76.97
1.80m £87.02
0.30m £30.72
0.60m £39.55
0.90m £50.29
1.20m £60.74
1.50m £70.50
1.80m £79.56
Width: 2.1m
0.30m £28.32
0.60m £37.03
0.90m £46.24
1.20m £55.54
1.50m £64.03
1.80m £72.22
To discuss your requirements, check stock availability or to find out more about our local delivery service to Tunbridge Wells, Tonbridge, East Grinstead & Crowborough please contact us
For a quotation, please call us on 01892 864646 or email firstname.lastname@example.com
Trade and quantity discounts may be available.
and are subject to change without prior notice
We are members of the West Kent Chamber of Commerce and Industry and the Association of Fencing Industries.
Regd. Office: Crestala Fencing & Construction Co. Ltd, South Farm, Langton Green, Tunbridge Wells, Kent. TN3 9JN.
Registered in England No 869419
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Atlanta Online Retailer EdgewoodAve.com Relocates Headquarters to Historic M. Rich Building
June 13,2014
June 12, 2014 (Atlanta, GA) - After growing out of their original offices on Edgewood Avenue in Old Fourth Ward, Atlanta-based e-commerce startup EdgewoodAve.com has moved their headquarters to the M. Rich Building in south downtown. The move is symbolic as this cutting-edge, 21st century e-commerce company now resides in the turn of the 20th century building that revolutionized traditional retail.
"Having our headquarters in the converted department store that helped pioneer the shopping experience over 100 years ago is exciting and very motivating," says EdgewoodAve.com CEO Rick Lockett. "Our website borrows many of the cues from the offline shopping experience, which was greatly shaped in this very location."
EdgewoodAve.com has worked a real world street metaphor into its site design and functionality, taking the best of the offline shopping experience and merging it with the convenience of online shopping. The layout of the website encourages the community to shop by brand, not product, the same way one would shop at a traditional brick and mortar store. This exposes consumers to a brand's whole story and purpose, allowing them to have a greater understanding and appreciation for what they are about to buy.
Over the past few years, the M. Rich Building has attracted creative, tech, and entertainment-focused tenants such as Creative Loafing, C4 Atlanta, Carl Anthony Payne Entertainment, and now EdgewoodAve.com. "At M. Rich, we are looking to build a community that thrives on collaborative creativity and passion for Atlanta's growth. We are excited that EdgewoodAve.com has joined the building, and we look forward to seeing their work for Atlanta grow in the future," says Dora Din-Durant, Leasing and Communications Director for The Creation Group.
About EdgewoodAve.com: Launched in 2014, EdgewoodAve.com is an online social shopping community that creates a place for design-conscious individuals to shop and interact with brands, designers, and one another while they discover and discuss new products. The company was founded on, and inspired by the resurgence of Atlanta's Edgewood Avenue. The revitalization and social energy that run along this historic avenue are the same elements that EdgewoodAve.com is looking to bring to the online shopping experience. For more info download the EdgewoodAve.com press kit here.


text:
- Currae
- Doctors
Dr. Anil Magdum
Laproscopic Surgeon, Gynaecologist and Obstetrician
Laproscopic Surgeon, Gynaecologist and Obstetrician
- Cochin Obstetrics and Gynecology Society, Cochin
- Thane Association of Gynecologists, Thane, Mumbai (life member)
- Mumbai Obstetrics and Gynecology Society (applied)
- American Association of Gynecologic Laparoscopists (AAGL) (membership no. 42260)
- Association of Gynecologic Oncologists of India (AGOI) (life member)
- An experienced laparoscopic surgeon, gynaecologist and obstetrician with 17 years of experience.
- Performed more than 6500 laparoscopic proceudres (operative and diagnostic) which include more than 1600 total laparoscopic hysterectomies.
- Skilled in performing tlh, myomectomies,laparoscopic abdominal encirclage, laparoscopic conservative sling surgery for prolapse uterus, laparoscopic interna iliac, artery ligation, laparoscopic radical hysterectomy and pelvic lymphadenectomy,laparoscopic reversal of tubal sterilization surgeries, diagnostic and operative hysteroscopic procedures.
- Trained more than 500 gynaecologists and surgeons for hands on laparoscopy and hysteroscopy courses.
- Experience as teaching faculty for undergraduate and postgraduate students at various medical colleges.
Awards and Recognitions
- Part of team of gynecologists at the teal to heal together them , India's largest cervical cancer awareness campaign- a Guinness world records tm, record achievement on December 23, 2012 for largest number of pap smears (751). Done within 8 hours.
- Was part of the team in managing acute post partum inversion of uterus with laparoscopy (2nd only case in world literature- unpublished data).
- Was part of team who performed 1st successful documented procedure of amino patch for preterm pre-labor rupture of membranes at 18 weeks of gestation in Kerala state, India.
Papers And Publications
Presented papers and posters at various National and International conferences.
- Co author: primary squamous cell cancer in ovary
- Presenting author: complications with myoma screw when used as sole uterine manipulator in total laparoscopic hysterectomy.
- Presenting author: combined use of vasopressin and uterine artery ligation during myomectomy for large uteri in resource poor set up.
Last two papers were presented at Barcelona, Spain in annual conference of American association of gynaecologic laparoscopists , June 2014.
Last two papers were published as abstract in journal of minimally invasive gynaecology, an official journal of American Association of Gynaecological Laparoscopists.
Conference And Courses
Invited faculty for laparoscopy live surgery workshops at various National and International conferences.
Experience #HassleFreeHealthCare


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This property has been removed by the agent. It may be sold or temporarily removed from the market
4 bedroom town house for saleMill Court, Oxenhope, Keighley, West Yorkshire, BD22
Property Description
Key features
- Spacious end town-house
- Four bedrooms
- Two reception rooms
- Well-presented family accommodation
- UPVC double glazing and gas fired heating
- Close to local amenities and popular primary school
- Parking to the front and garden to the rear
- Viewing essential
Full description
A well-presented and spacious four bedroom family home pleasantly situated on a cul-de-sac in the centre of this ever popular village. With gas fired heating and UPVC double glazing the property has off road parking to the front for two vehicles and a garden to the rear. Realistically priced, an early viewing is essential.
This four bedroom end town house offers spacious accommodation over two floors and is located in one of the area's most desirable villages. With UPVC double glazing, gas fired heating, block paved driveway and rear garden, in brief the accommodation comprises: Ground floor: Entrance vestibule leading to dining area, kitchen, good sized living room to the rear with double doors leading to the garden, wc. First floor: Spacious landing with three double bedrooms and a single, four piece bathroom suite. The property will undoubtedly appeal to families and an internal inspection is sure to impress.
The property is situated in the centre of the village of Oxenhope, convenient for local amenities, which include a popular first school, mini supermarket, park, various pubs and sports clubs, all surrounded by delightful countryside. Keighley town centre is approximately 5 miles distant, which has larger shopping facilities and links by both road and rail to the major towns and cities of West Yorkshire.
From our North Street office into the high Street and turn left into South Street, continue through the lights into Halifax Road, up the hill to the roundabout at Cross Roads and turn right into Haworth Road. Continue down Haworth Road and turn left into Hebden Road. Continue for 2 miles to the mini roundabout then turn left into Station Road. Continue straight forward passing the mini supermarket and then turn left into Waterside. Head around the corner and turn left in to Mill Court. The property will be found on the left hand side, identified by our for sale board.
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Disclaimer - Property reference KEI160526. The information displayed about this property comprises a property advertisement. Rightmove.co.uk makes no warranty as to the accuracy or completeness of the advertisement or any linked or associated information, and Rightmove has no control over the content. This property advertisement does not constitute property particulars. The information is provided and maintained by Dacre Son & Hartley, Keighley. Please contact the selling agent or developer directly to obtain any information which may be available under the terms of The Energy Performance of Buildings (Certificates and Inspections) (England and Wales) Regulations 2007 or the Home Report if in relation to a residential property in Scotland.
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|Publication number
|Publication type
|Application number
|Publication date
|Jun 29, 1999
|Filing date
|Jan 5, 1998
|Priority date
|Jan 5, 1998
|Fee status
|Also published as
|Publication number
|Andrew J. Wardrop
|Original Assignee
|General Dynamics Information Systems, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (2), Non-Patent Citations (2), Referenced by (38), Classifications (16), Legal Events (6)
|External Links: USPTO, USPTO Assignment, Espacenet
This invention relates, in general, to memory configurations for computing systems, and in particular to memory systems utilizing error correction techniques for fault tolerant operations.
Encoding techniques are used in digital systems to provide for detection and correction of errors occurring during data processing. Such encoding techniques include, for example, the use of gray codes, Huffman encoding, or block codes. Block codes subdivide an input or source data stream into discrete blocks, and perform a particular encoding procedure on the input data. A fixed number of check digits or bits is added to the input data during message encoding which forms a transmittable codeword. These check bits are added to the input data so that errors occurring during transmission can be detected and possibly corrected. Upon receiving the transmitted codeword, a syndrome is calculated using a parity check matrix and the received codeword. The syndrome indicates which digit, if any, in the received codeword is in error and may be corrected.
One such block encoding procedure involves the use of Hamming codes. Hamming codes are binary codes which use predefined parity check matrices to provide single bit error correction capability. Hamming codes are generally not used to provide multiple bit error correction.
With respect to computer memory structures in modern computer systems, the use of Hamming codes to implement memory systems having single bit error correcting, double bit error detecting capabilities is nearly universal in the computer industry. For example, a 32 bit computer word can be used with a 7 bit Hamming codeword to correct all single bit errors of the 32 bit word, and detect all double bit errors of the 32 bit word. However, these memory systems have only single bit error correction capabilities.
Single bit, non-recurrent errors, also known as "soft errors", may be caused by relatively rare radiation effects, such as cosmic rays or trace radioactive elements in the material surrounding the memory device. Computing systems which operate in severe environments, such as outer space, can be subjected to random upset of memory bits, as well as total failures of individual memory devices. Without the shielding provided by the Earth's atmosphere, such upsets can be very common in outer space, potentially thousands per day in a 64 Mbit dynamic memory chip.
If more than two bits are in error in a codeword, a Hamming code may falsely indicate that 0 or 1 bits were in error, or may correctly indicate that there were multiple bits in error. However, an odd number of bits in error will generally cause a single bit (correctable) error indication or a multiple bit (uncorrectable) error indication. For example, if 5 bits were actually in error, a conventional error correction system based on Hamming codes may erroneously indicate that there was only 1 bit in error. Further, it is possible for an even number of bits in actual error, a conventional error correction system based on Hamming codes could falsely indicate that there is no error. Even if the Hamming code properly indicates the number of bits in error, the Hamming code can only be used to correct single bit errors.
What is needed is a fault tolerant memory system having reliable multiple bit error detection and multiple bit error correction capabilities for use in a computer system operable in severe environments.
The present invention provides a fault tolerant memory system for storing data in computing systems operable in severe environments.
In one embodiment of the invention, a memory system providing triple bit error detection and correction, as well as quadruple bit error detection, is disclosed. The system comprises a pair of decoders, a comparator, and control logic. Data is stored in memory as two Hamming encoded copies of the same data. A first decoder decodes the first copy of the data, the first decoder detecting single bit errors present in the first copy and correcting the single bit errors by providing a corrected first copy of the data. The first decoder also detects double bit errors in the first copy.
A second decoder decodes the second copy of the data, the second decoder detecting single bit errors present in the second copy and correcting the single bit errors by providing a corrected second copy of the data. The second decoder also detects double bit errors in second copy.
The comparator compares the first corrected copy to the second corrected copy and generates an output signal indicating that the first corrected copy matches the second corrected copy. The control logic, responsive to the first and second decoders and the output signal of the comparator, selects between the first corrected copy or the second corrected copy as the data to be provided to a computing system. In this manner, if the total number of errors present the first copy and the second copy is three, the present invention can still provide valid data to the computing system.
In another embodiment of the invention, a memory sparing system is provided so that a failure in one memory device can be circumvented without permanently disabling the memory system. The memory system comprises an error correction code generator, a pair of selectors, and a plurality of memory devices. The error correction code generator is provided to generate error correction codes to be encoded with the data. The plurality of data storage devices is provided comprising at least one data storage device for storing the error correction codes, at least one storage device for storing data from each data line, and at least one additional spare storage device. A first selector couples the data lines and the error correction code generator to a selectable subset of said plurality of data storage devices so that data and the error correction codes are stored in the selectable subset of said plurality of data storage devices. A second selector, coupled to the plurality of data storage devices, selects the subset of the plurality of data storage devices so that the data and the error correction codes stored in the selectable subset can be read therefrom. In this manner, a failure in one memory device can be circumvented by selecting the subset of remaining memory devices for data storage.
A computer system incorporating the features of the present invention is also disclosed.
The foregoing and other features, utilities and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention as illustrated in the accompanying drawings.
FIG. 1 illustrates a memory system having dual error correction modes in accordance with the present invention.
FIG. 2 illustrates an organization of a physical memory using the operable error correction modes of the memory system of FIG. 1 in accordance with the present invention.
FIG. 3 illustrates a memory column sparing system in accordance with one embodiment of the present invention.
FIG. 4 illustrates a multiple memory window set having two memory address spaces within the logical address space of a processor to provide for operable error correction modes and memory column sparing in accordance with one embodiment of the present invention.
FIG. 5 illustrates in block diagram form a computer system in accordance with the present invention.
The present invention provides a fault tolerant memory system for use in high performance computer systems that are operable in severe environments such as outer space. The memory system includes an error correction system that has two modes: a single error correction, double error detection (SECDED) mode; and a triple error correction, quad error detection (TECQED) mode. Additionally, spare memory resources can be provided to both enhance the long term reliability of the memory system and provide access to the error correction codes for the purposes of dynamic system testing. Finally, a memory address aliasing or windowing is provided that allows simultaneous access to the installed memory using two different combinations of error correcting mode and spare resource control settings.
These three components form a memory system that is very tolerant of the random upsets of memory bits in severe environments such as space; can tolerate total failures of the individual memory devices that make up the memory system; and is adjustable to provide the optimum mixture of fault tolerance, memory capacity, and memory speed of access for a particular application.
The data stored in the memory system uses Hamming codes so that when the data is read from the memory, any erroneous data can be detected, and corrected if appropriate. It is assumed that each piece of data is stored in the memory system with the check digits required by the particular Hamming code used. The particular Hamming code used is a matter of choice dependent on the performance and operating requirements of the computing system. As will be explained below, the invention can also be extended to any error detecting and correcting code.
FIG. 1 illustrates a memory system 100 in accordance with the present invention. The memory system includes a first and second decoder module 102, 104, a comparator 106, control logic 108, and a selector 110. In accordance with the present invention, the same data is redundantly stored in the memory system as two Hamming encoded codewords 112, 114 (i.e., 2 copies of the data are stored). As will be explained below, by comparing the bit error status associated with each stored codeword as it is read from memory and decoded, more bit errors or each piece of data can be detected and corrected than if only one copy of the data was stored in memory.
The first decoder module 102 and second decoder module 104 are provided in parallel, each module implementing single error correction/double error detection based on Hamming code error detection and correction techniques. Each decoder module processes a separate copy of the exact same Hamming encoded data, shown as copy A (112) and copy B (114). It is understood, however, that each copy A or B of the same Hamming encoded data word may in fact differ if one of the copies was corrupted in memory.
Each decoder decodes the its respective copy of the encoded data and provides a status signal to the control logic indicating if no error was detected, a single bit error was detected and corrected, or double bit error was detected. If a single bit error was detected and corrected by the decoder, the decoder provides the corrected data word. If no error was detected, the decoder provides as the output the uncorrected copy of the data.
The comparator 106 compares the corrected data provided by the output of each encoder, and generates a status signal 107 to the control logic 108 if both decoder outputs are identical. The control logic 108 is responsive to the status signals generated by each decoder and the comparator, as will be explained below. The control logic 108 is coupled to a selector 110 for selecting between the copy A output of decoder 102 or the copy B output of decoder 104. This selected output 116 is provided to the computing system as the data word read from memory. The control logic also indicates if an uncorrectable error 118 is detected meaning that neither the copy A output nor the copy B output contains valid data.
The two copies of the memory words are independently processed by decoders. The data words will be corrected if either are determined to have single bit errors, and then will be compared. The single and double bit error status, as well as whether the two words agree, will be processed in the control logic, which implements the logic rules discussed herein.
While each decoder can detect and correct single bit errors, or detect double bit errors, the control logic 108 of the present invention can detect and correct triple bit errors or detect quad bit errors in a single data codeword. Table 1 shows the logic rules used by the control logic 108 to implement a triple bit error correction, quad bit error detecting memory.
TABLE 1______________________________________Triple Error Correcting Rules B Word Indicated ErrorsA WordIndicated Errors 0 1 2______________________________________0 Use if match Use A Use A1 Use B Use corrected if Use corrected A they match2 Use B Use corrected B Flag Error______________________________________
Table 2 shows the results of applying the rules stated in Table 1 and described herein, and the appropriate indicated errors, for all combinations of actual errors of up to 4 bit errors in a data codeword. All combinations of three or fewer bit errors are processed such that the correct data is obtained. All combinations of 4 bit errors are either corrected or an "uncorrectable" error is indicated. Five or more errors are not supported by the mechanism shown in FIG. 1.
TABLE 2__________________________________________________________________________Triple Error Correction ResultsWord A Word BActual Indicated Actual Indicated Total Rules ApplicationErrors Errors Errors Errors Errors Result Action__________________________________________________________________________0 None 0 None 0 Use A or B, since Correct they are identical1 Corr. 0 None 1 Use B Correct0 None 1 Corr. 1 Use A Correct1 Corr. 1 Corr. 2 Use corrected A or Correct corrected B, since they are identical2 Uncorr. 0 None 2 Use B Correct0 None 2 Uncorr. 2 Use A Correct1 Corr. 2 Uncorr. 3 Use corrected A Correct2 Uncorr. 1 Corr. 3 Use corrected B Correct0 None 3 Corr. 3 Use A Correct0 None 3 Uncorr. 3 Use A Correct3 Corr. 0 None 3 Use B Correct3 Uncorr. 0 None 3 Use B Correct0 None 4 None 4 A and B do not Error agree, so indicate detected an error0 None 4 Uncorr. 4 Use A Correct1 Corr. 3 Corr. 4 A and B do not Error agree, so indicate detected an error1 Corr. 3 Uncorr. 4 Use A Correct2 Uncorr. 2 Uncorr. 4 Indicate error Error detected3 Corr. 1 Corr. 4 A and B do not Error agree, so indicate detected an error3 Uncorr. 1 Corr. 4 Use B Correct__________________________________________________________________________
The following logic can be used by the control logic 108 in connection with the rules shown in Table 1:
a. If 0 errors are detected in both words, use the common value if both words agree. If both words disagree, flag an uncorrectable error.
b. If one word indicates 0 errors, and the other indicates 1 error, then use the value with 0 errors indicated.
c. If 1 error is indicated in both words, correct each word, and use the common value if they agree. If they disagree, flag an uncorrectable error.
d. If either copy indicated a double error detected (i.e., uncorrectable error), then use the other copy of the data if it has 0 or 1 bit errors indicated. Use the corrected value if there was 1 bit in error.
e. If both copies detect a double bit error (i.e., uncorrectable error), then flag an uncorrectable error.
While the system shown in FIG. 1 uses two decoders in parallel, the principle is the same if a single decoder were used with two data words in sequence. The implementation using parallel decoders has the advantage of higher performance, since two memory words are accessed simultaneously.
Optionally, the memory system of FIG. 1 can selectively operate between two modes of operation. In the first mode, the memory system operates in single bit error correction/double bit error detection mode where the decoders operate to provide two data words per cycle using Hamming single bit error correction/double bit error detection decoding. The control logic 108 is essentially bypassed in this mode of operation, and thereby would have the benefit of faster processing time. This mode is referred to herein as SECDED mode.
In the second mode of operation, the memory system operates in triple bit error correction/quad bit error detection mode where the output of the decoders provides error information to the control logic 108 as described above. The control logic then processes the error information and provides appropriate data to the computing system. This mode of operation has the benefit of a greater number of errors detected and corrected than the first mode of operation. This mode is referred to herein as TECQED mode.
Hence, two data words can be read simultaneously from the memory system if the memory system is operating in single bit error correction/double bit error detection mode (SECDED); and one data word can be read from the memory system if the memory system is operating in triple bit error correction/quad bit error detection mode (TECQED).
An optional third mode of operation is also possible, with two variations. Half the memory bits are assigned to each of the two decoders, and both decoders are used in the TECQED and SECDED modes. It is also possible to use just one decoder. Since half the memory bits are assigned to each decoder, only half the memory can be accessed in this manner. Nevertheless, this can be advantageously used in cases where half the memory is unusable, either due to device failures, or if a minimum system was constructed that did not install the full memory complement, or if the memory devices were present but not powered.
The two variations of the single decoder mode are to use the decoder that would be servicing even addressed words in the dual decoder SECDED mode, or to use the other decoder, that would service odd addressed words in the dual decoder SECDED mode. FIG. 2 shows how data is assigned in the four data modes. Each row of every diagram represents the two words of memory that can be read and written simultaneously, one for each decoder. There are as many rows as there are double words of memory installed, but only two rows are shown. Each column represents the memory words assigned to the same decoder.
In the TECQED mode 204, the same data is written to both columns 201 and 202, so the two data words have the same address (words 0 and 1 shown). In the SECDED mode 203, the two words are different. The example shown has placed words with even addresses, such as the 0 and 2 shown, in column 201, and words with odd addresses, such as the 1 and 3 shown, in column 202.
In the single decoder odd mode 205, only the memory column 202 is used for all words, as shown for words 0 and 1. Similarly, in the single decoder even mode 206, only the memory column 202 is used for all words, as shown for words 0 and 1.
While the invention has been described herein using Hamming codes, the invention can be extended to any error detecting and correcting code. The number of bits that can be corrected using the two word method described is generally equal to the sum of the number of bits in error that can be corrected and the number of bits in error that can be corrected in a single word. For a Hamming code that can correct one error and detect two in a single word, the number of bits that can be corrected using the described invention is 1 correction plus 2 detection, or a total of 3.
To achieve this level or correction for all possible locations of errors, it is further required that the error detecting and correcting code not misinterpret error counts within a single word up to the double word correction limit as a fault free condition. For the Hamming case, this means that triple errors in a single word must result in an indication that 1 or more errors was detected.
As shown in FIG. 3 and Table 3 (below), another feature of the present invention is an additional column or DRAM memory chips provided as spare memory in the event of an individual DRAM device failure. If a DRAM device fails, this spare memory can be used to replace the failed device, enhancing long term reliability. This mechanism can even circumvent shorts on data lines.
In accordance with a particular embodiment of the present invention, a set of software controllable multiplexers 302, 304 is provided between the plurality of memory chips 306, as shown in FIG. 3. These multiplexers control the selection of memory sparing modes of the memory system of the present invention. FIG. 3 shows four data bytes D0, D1, D2, and D3 (in one example, 8 bits/byte) for storage into the set of memory chips or devices M0, M1, M2, M3, M4, and M5. An error correction code (ECC) generator 308 is provided for encoding each four data byte stream with an error correction code prior to storage in the memory.
The multiplexers choose which 5 of the 6 accessible memory devices M0-M5 will be used for storing and retrieving data and the associated error correction code. A first multiplexer 302 is provided to select which memory chips M0-M5 are to be used for storing data. A second multiplexer 304 is provided to select from which memory chips the data should be read from. Both multiplexers can be configured by a software controllable register to ensure coordination between the write and read of data. As data is selectively read from M0-M5 through the second multiplexer, the data is then passed to the error detection and correction section 100 of the memory system, shown in FIG. 1 and described above, for decoding.
The set of memory chips and the data/ECC lines are arranged so that if one of the memory chips M0-M5 fails, the sparing mode can be dynamically altered so that the failed memory chip is bypassed and the remaining chips are used to provide memory to the computing system. Based on the configuration shown in FIG. 3, data is always written into every memory device, but the data read from the spare column is not used.
For writes of data to the memory system, the 4 data bytes of data D0, D1, D2, and D3 (32 bits) are presented to the ECC generation circuit 308, which produces an additional byte of ECC code. Based on the structure shown in FIG. 3, the data byte D0 is always written to the memory device M0, and the data byte D3 is always written to the memory device M5. Which data or ECC bytes are written into memory bytes M1-M4 is dependent on the input multiplexer 302 settings, which are controlled by a software accessible configuration register.
All 6 bytes of memory data are read, but the 5 bytes to be used for further processing are selected by the second multiplexer 304. As discussed above, the second multiplexer 304 is controlled by the same configuration register used for the write operation, assuring that writes and reads use the same sparing mode. The 5 selected bytes (D0-D4 plus the ECC byte) are further processed by the decoding section 100, described above with reference to FIG. 1, to detect and possibly correct bit errors that may have been introduced in the memory writing, storage, and reading processes.
Table 3 shows the possible configurations of the various memory sparing modes for data writes and reads. For the entries in Table 3 labeled "unused", the value in parentheses is the data written when the memory is written.
TABLE 3______________________________________Memory Sparing ModesPhysical Memory Column ContentsMode M5 M4 M3 M2 M1 M0______________________________________0 D3 D2 ECC D1 D0 Unused (D0)1 D3 D2 ECC D1 Unused D0 (D1)2 D3 D2 ECC Unused D1 D0 (ECC)3 D3 D2 Unused ECC D1 D0 (D2)4 D3 Unused D2 ECC D1 D0 (D3)5 Unused D3 D2 ECC D1 D0 (D3)______________________________________
Referring to Table 3, if, for example, memory device M3 fails, then sparing mode 3 can be dynamically selected so that M3 is not used for data storage and retrieval.
In a memory system that uses error correction codes, the present invention also provides for writing erroneous data or error checking codes into memory to allow the error detection and correction mechanism to be tested dynamically or on the fly. The correct generation of ECC bits can be directly checked dynamically by writing data in sparing mode 2. Data can then be read in sparing mode 0 or 1 to provide access to the ECC bits for verification. Further, to generate error indications, an ECC code can be placed in the D2 byte and the data word written using sparing mode 3. If the data is then read in sparing mode 2, the D2 data will be used as the ECC code, generating a fault indication if the ECC code is not correct.
In order to flexibly use the SECDED/TECQED modes and the memory sparing modes, multiple memory windows are also provided by one embodiment of the present invention. In one example, within the 2 32 bit address space of a modern RISC processor, two or more address regions are set up. A typical size for these regions might be 2 30, allowing up to four such regions to be available, although in practice only two might be used, with the rest of the address space used for input/output or other control functions. While these address regions access the same physical memory, they can have different settings based on the data mode and the sparing mode, thereby allowing the software of the computing system to flexibly manage the pool of physical memory.
FIG. 4 shows two memory address spaces 402, 404 within the logical address space of a processor that access the same physical memory with possible different settings for memory column sparing and error detection and correction mode. Since error correction codes of the SECDED and TECQED modes use differing amounts of raw memory words to form computer data words (TECQED mode uses two memory words for each data word), the same physical memory word will have a different address in the two correction modes, as shown previously in FIG. 2. Table 4 shows the addressing for the two modes SECDED and TECQED. The memory address windows or aliases allow simultaneous access to the installed memory using two different combinations of error correcting mode and spare resource control settings.
TABLE 4______________________________________Addressing Relationships Among Data ModesData Mode Address of Nth Even Word Address of Nth Odd Word______________________________________Interleaved Base + 2 * N Base + 2 * N + 1TECQED Base + NEven Word Base + N n/aOdd Word n/a Base + N______________________________________ Base = 0 � 0000-- 0000 for Memory Access Window 0 and 0 .times 2000-- 0000 for Memory Access Window 1, for example.
For example, all the software program code could be accessed and stored using TECQED memory mode for greater security and reliability, and all data could be accessed through a second memory address region using SECDED mode to achieve a larger memory capacity and speed of access. Memory would be allocated to be used in the SECDED or TECQED mode when the software was compiled and logical addresses assigned to all program and data items.
With the memory system of the present invention, data can be moved freely between memory sparing modes by reading from one address space and writing to another. This enhances the ability of the computing system to work around failed memory segments, and to reconfigure memory while retaining as much access as possible to its previous contents.
Reading from one address space and writing to another address space will re-encode data error correction codes for future access through the second address space. However, reading data from one correction mode (i.e., SECDED) other than the one in which the data was written (i.e., TECQED) will generally result in garbled data. Table 3 can be used to understand what is happening to the data.
FIG. 5 illustrates a typical general purpose computer system 500 which can incorporate a memory system 507 in accordance with the present invention. Computer system 500 in accordance with the present invention comprises a system data bus 501 for communicating information, processor 502 coupled with bus 501 through a host bridge device 503 for processing data and executing instructions, and memory system 507 for storing information and instructions for processor 502. The memory system disclosed above can be used to enhance the reliability of memory system 507, and can be integrated on-chip with processor 502 or with external memory.
In a typical embodiment, processor 502, host bridge device 503, and some or all of cache memory 505 may be integrated in a single integrated circuit, although the specific components and integration density are a matter of design choice selected to meet the needs of a particular application.
User I/O devices 506 are coupled to bus 501 and are operative to communicate information in appropriately structured form to and from the other parts of computer 500. User I/O devices may include a keyboard, mouse, card reader, magnetic or paper tape, magnetic disk, optical disk, or other available input devices, including another computer. Mass storage device 517 is coupled to bus 501, and may be implemented using one or more magnetic hard disks, magnetic tapes, CDROMs, large banks of random access memory, or the like. Mass storage 517 may include computer programs and data stored therein.
In a typical computer system 500, processor 502, host bridge device 503, main memory system 507, and mass storage device 517, are coupled to bus 501 formed on a printed circuit board and integrated into a single housing. However, the particular components chosen to be integrated into a single housing is based upon market and design choices. Accordingly, it is expressly understood that fewer or more devices may be incorporated within a housing.
Display device 509 is used to display messages, data, a graphical or command line user interface, or other communications with the user. Display device 509 may be implemented, for example, by a cathode ray tube (CRT) monitor, liquid crystal display (LCD) or any available equivalent.
When used in conjunction with computing system 500, the memory system of present invention can improve the performance and reliability of the computing system as described above.
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various other changes in the form and details may be made without departing from the spirit and scope of the invention, as defined by the following claims.
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|U.S. Classification
|International Classification
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|Jan 5, 1998
Owner name: GENERAL DYNAMICS INFORMATION SYSTEMS, INC., MINNES
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WARDROP, ANDREW J.;REEL/FRAME:008928/0774
Effective date: 19971222
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|Nov 28, 2006
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|Jan 31, 2011
|Maintenance fee reminder mailed
|Mar 17, 2011
|Fee payment
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|Mar 17, 2011
|Surcharge for late payment
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